1994_MXCOM_Mixed_Signal_ICs 1994 MXCOM Mixed Signal ICs

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MX·~M,IN~.
MiXed Signa/Integrated Circuit
Product Handbook

©1994

INTRODUCTION
This handbook presents technical specifications and application notes
for MX-COM's MiXed signal integrated circuits.
MX-COM specializes in the development of high-performance, MiXed
signal Application Specific Standard IC's for communication tasks
such as:
-

wireless modems
sub-audio tone signaling
speech security
and voice storageiretrieval.

MX-COM offers quick turn-around design methodologies supported by
specialized manufacturing facilities, comprehensive test, quality assurance, and prototype assembly backed by more than 10 years of
telecommunication product design experience.
Call us at (910) 744-5050 or Toll-Free in the Continental U.S., Alaska
and Canada at (800) 638-5577. Or Fax us at (910) 744-5054 for price,
availability and applications assistance.

Page 2

MX-COM, INC.

CONTENTS
INTRODUCTION .................................................................................................................... p. 6

TECHNICAL SPECIFICATIONS ......................................................................................... p. 11

1. WIRELESS MODEMS ......................................................................................

p. 13

2. SUB-AUDIO TONE SIGNALING/DETECTION ...............................................

p. 153

3. SEQUENTIAL TONE ENCODERS/DECODERS .............................................

p.221

4. VOICE PROCESSORS .....................................................................................

p.265

5. VOICE SECURITY ............................................................................................

p.343

6. CVSD CODECS ................................................................................................

p.373

7. DIGITAL CONTROL AMPLIFIERS ................................................................ ..

p.447

8. TELEPHONY ....................................................................................................

p.467

9. SIGNAL PROCESSING ....................................................................................

p.501

10. APPENDIX ......................................................................................................

p.517

MX-COM, INC.

Page 3

PRODUCT GUIDE

Device

Description

"Page

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1. WIRELESS MODEMS ............................................. ~p,13

.....
..... .....
.....

.....
.....

.....
.....

.....
.....

MX919/929 High-Speed 4-Level FSK Modem/ARDIS ........ NEW .. •• p. 103

.....
.....

.....
.....

CDPD/AMPS-WBD Full-Duplex Modem ......... NEW .. •• p.140

.....

.....

.....
.....

.....

.....
.....
.....
.....
.....

.....
.....

MX429/529 1200 bps MSK Modem with Parallel BUS Control ....... .. p:15
MX439

1200 bps MSK Modem with Serial Control .................. ..

p."2~

MX469

1200/2400 bps MSK Modem with Serial Control ......... np.35

MX589

40k bps GMSK Modem with Serial Control ................. " p. 43

MX809

1200 bps MSK Modem with C-BUS Control ................ c' p. 57

MX909

High-Speed and MOBITEX GMSK Modem ..... NEW .. .• p. 70

MX939

.....

2. SUB-AUDIO TONE SIGNALING/DETECTION ...... · p. 153
MX315A

CTCSS Encoder .................................................... .. p. 155

MX165B

CTCSS Encoder/Decoder with Audio Filter .......... .. p. 160

MX165C

CTCSS Encoder/Decoder with Audio Filter -NEW •; p. 169

MX365A

CTCSS Encoder/Decoder with Audio Filter .......... .. p. 178

MX275

Pvt SQU ELCWM CTCSS Encoder/Decoder ......... .. p. 187

MX375

Pvt SQUELCWM CTCSS Encoder/Decoder ......... .. p . 195

MX805A

Sub-Audio Signaling Processor ............................ .. p.204

.....

.....

3. SEQUENTIAL TONE ENCODERS/DECODERS ... · p. 221
MX013

HSC Tone Decoder ..................................................... .. p. 229

.....

.....

MX203

Selective Call Codec .................................................... .. p. "234

MX503

Sequential Tone Encoder ............................................ .. p. 242

.....
.....

MX803A

Audio Signaling Processor ........................................... .. p. 249

.....
.....
.....

.....

4. VOICE PROCESSORS ........................................... • p. 265
MX316

NMT Audio Filter Array ................................................ .. p. 267

.....

MX336

Audio/Subaudio Filter Array ......................................... .. p. 272

..... .....

MX346

Cellular Audio Processing Array .................................. .. p. 278

MX366

Quad Filter Array (NAMPS/ETACS) ............................ .. p.285

MX386

Quad Filter Array (NAMPSITACS/AMPS/ACSB) ........ .. p . 291

.....
.....
.....

MX806A

Audio Processor .......................................................... .. p. 295

MX816

NMT Audio Processor ................................................. .. p. 307

MX826

AMPS/NAMPS Audio Processor ................................. .. p. 319

MX836

R2000 Audio Processor ............................................... .. p. 331

Page 4

.....
.....
.....
.....

MX-COM, INC.

PRODUCT GUIDE

Device

Description

Page

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V'

V'

V'

5. VOICE SECURITY ................................................... • p. 343
MX014

Voice Band Inverter ..................................................... ... p. 345

V'

MX214/224 VSB Inverter ................................................................... p. 351

V'

V'

MX118

Full-Duplex Scrambler for Cordless Telephones ............ ... p.360

V'

V'

MX128

Full-Duplex Scrambler for Cordless Telephones. NEW .. p.366

V'

V'

6. CVSD CODECS ....................................................... • p. 373
MX109

Full Duplex CVSD Codec with Serial Control ... NEW .. p.377

V'

V'

V'

V'

MX609

Full Duplex CVSD Codec with Companding ............... .. p.384

V'

V'

V'

V'

MX619/629 Delta Modulation Codec ............................................... ... p.391

V'

V'

V'

V'

MX709

Voice Storage and Retrieval (VSR) Codec wI SRAM ... p.403

V'

MX802

VSR Codec with Filters and DRAM Control .............. ... p. 420

V'

V'

V'

MX812

VSR Codec with DRAM Control ................................ ... p.434

V'

V'

V'

V'

7. DIGITAL CONTROL AMPLIFIERS ........................ · p. 447
MX009

Octal Digital Control Amplifier ..................................... ... p. 449

V'

V'

MX019

Quad Digital Control Amplifier .................................... .. p. 455

V'

V'

MX029

Dual Digital Control Amplifier .......................... NEW .. .. p.460

V'

V'

8. TELEPHONy ........................................................... • p.467
MX613

Global Call Progress Detector ........................ NEW .. .. p.469

MX623

Line-Powered Call Progress Detector ............ NEW .. .. p.477

V'

MX631

Low-Power SPM Detector .............................. NEW .. .. p.483

V'

MX641

Dual SPM Detector ......................................... NEW .. .. p.490

V'

V'

9. SIGNAL PROCESSING .......................................... • p. 501
MX102

Autocorrelator .............................................................. .. p.603

V'

MX105

Tone Detector .............................................................. .. p.509

V'

10. APPENDIX ............................................................... p. 517
STANDARDS & REFERENCES ........................................................ p. 519
APPLICATIONS ................................................................................. p. 523
DEFINITIONS ..................................................................................... p. 585
PACKAGING & HANDLING ............................................................... p. 591
PRODUCT REPLACEMENT GUIDE ................................................. p. 617
LIST OF XTALS COMPATIBLE WITH MX-COM IC'S ....................... p. 619
INDEX ................................................................................................. p. 621
MX-COM, INC.

PageS

COMPANY PROFILE
MX·COM, INC., a member of CML Microsystems Pic. group of Witham, Essex, England, designs, manufactures and sells
radio, telecommunication, and wireless data communications IC's. The company products utilize a mixed analog and digital
CMOS process. The combination of detailed system knowledge and integrated circuit design capability has resulted in highquality products for:
• Two-Way Mobile Radio
• Cellular Radio
• Modems for Radio Data Communications
• Voice SecurityNoice Coding
• Paging
• Cordless Telephones
• Military Communications
Although manufactured in separate facilities in North Carolina and the UK, the monolithic products of MX·COM and
Consumer Microcircuits Ltd. (also a member of CML Microsystems Pic.) share similar form, fit and function. Each thereby
serves as a 2 nd source back-up of the other - unique among niche market IC suppliers.

FACILITIES
MX·COM occupies a 28,000 square foot purpose-builtfacility in Winston-Salem, NC. Product design, packaging and testing
are performed at the Winston-Salem facility. Qualified foundries are used forwaferfabrication. All subcontractors are subject
to stringent MX·COM specifications and oversight -- see "Quality and Reliability."
Customer visits to MX·COM are welcomed and can be arranged by contacting the sales department.
MX·COM has distributors and agents worldwide. See the inside back cover of this catalog for a complete listing.

MX·COM headquarters, Winston-Salem, North Carolina

Page 6

MX-COM, INC.

DEVELOPMENT PROCESS
MX·COM's integrated circuit products focus on baseband
signal processing for wireless telecommunication applications. To offer truly integrated solutions it is necessary to
combine analog and digital technology on a single monolithic
silicon substrate ("mixed signal" technology).
MX·COM's integrated circuit designers follow a clearly defined protocol from the conceptual phase through device
fabrication (see figure at right). State ofthe art CAD tools are
a critical component to all phases of this process. Maximizing the usage of CAD tools minimizes the probability of errors
from human intervention.
The concept phase involves the use of high-level system
simulators for verifying the approach to a particular deSign.
Ultimately, this process yields a top-level block diagram
which must be approved by key departments throughout
MX·COM. The next step is design capture. This consists of
turning the top-level block diagram into a transistor level
representation. The transistor level design is then simulated
using a proprietary analog simulator (similar to SPICE) in
conjunction with an industry standard digital simulator. The
simulation results are carefully analyzed, and any necessary improvements are made. When the results are satisfactory the design is ready for the layout phase.
The first step in the layout phase, and the most critical, is
"floor planning." In MX·COM's mixed-signal devices high
performance analog circuitry is completely isolated from onchip digital sections, ensuring optimum noise performance.
After a suitable floorplan is agreed upon the actual layout
begins. Layout is accomplished using a combination of
computer generated (auto-routing) and full-custom techniques. Once the layout is complete the verification phase
begins.
In the verification phase the layout is first checked for design
rule violations. When all design rule violations are removed
the layout is compared to the schematic and/or HDL (Hardware Description Language) using a "Layout versus Schematic" CAD tool. After this comparison the design is completely re-simulated. Butthis time the inputforthe simulator
is extracted from the layout, including the parasitic effects
due to routing. When the results of the re-simulation compare favorably to the previous simulation the design is ready
for fabrication.
IC design at MX·COM is a highly structured, metiCUlous
process. The end result is a family of products that offer the
highest levels of performance and integration attainable.

MX-COM, INC.

Layout versus Schematic Check

Parasitic Extraction

Re-simulation

Integrated Circuit
Development Protocol
Page 7

QUALITY AND RELIABILITY
MX-COM is committed to the quality that grows customers.
Our policy is to only provide products that conform to
realistic, documented standards that establish fitness for
use and assure continued performance over time.
Producing quality products requires:
- Knowledge - knowing what to do,
- Skills - being able to do it,
- andContinuous Improvement - getting better every day.
Knowledge is obtained through careful market and product
definition which includes the involvement and feedback of
valued and potential customers, and by actively participating
on industry standards committees.
Skills are provided by talented and dedicated employees.
Continuing training is provided to maintain
existing skills, to promote employee awareness and to develop needed new skills and
knowledge. Additionally, MX-COMcontinues to make substantial capital investments
necessary to support design, manufacturing, and quality activities and objectives.

Quality and reliability are an integral part of product definition
objectives and manufacturing practice. For instance,
MX-COM products are implemented using conservative
design rules and fabricated using well-established processes from qualified foundries. The product is then assembled at the MX-COM facility in North Carolina or by
qualified third party assembly operations. The MX-COM
assembly process is qualified to Mil Standard 45208. Conformance to specification for sub-contract assembly and
wafer production is strictly monitored through inspection and
audit procedures. Electrical test, at wafer level and finished
assembly, is performed at the Winston-Salem facility using
proprietary hardware and software. Product traceability is
provided throughout the production cycle.
MX-COM's quality objective is total customer satisfaction.

Continuous Improvement is a necessary
element of any quality effort, and MX-COM
is no exception.ln 1994, MX-COM expects
to complete 150-9000 certification, and
subsequently intends to build on this through
the Malcolm Baldrige process to achieve
quality levels second to none.

IC Assembly is Performed in MX-COM's Clean Room

DATA SHEET IDENTIFIERS
All products in this catalog may be classified in one of the following ways:

Identifier

Product Status

Comments

None

Full Production

Guaranteed limits will not be changed except through formal change
procedures that update specifications upon the next publication issue
-- contact MX-COM,INC for current information.

Preliminary

Pre-Production

The test limits specified are predicated on an incomplete statistical
sampling, possibly taken from only an initial production batch, and are
therefore likely to change.

Advance

Samples Pending

Specificatons are based on unproved design targets of products in
development.

CUSTOMER SUPPORT
Backing up our products is a team of factory and worldwide manufacturing reps (see inside back cover) staffed by sales
and application engineers who can provide a wealth of information, as well as identify additional resources to help
develop customer products. In addition, our technical literature discusses radio and modem technology and applications. Other services include on-site design support or factory analysis of any issues our customer may have.
Page 8

MX-COM, INC.

ORDERING INFORMATION
Please specify the device package type when placing an order. Package type suffix codes are defined below. See
the last section of the catalog for package dimensions.

E"mpl:r51~-------~~c~:;:!~~ualln_Line
Major Revision
Level
(A, B, C, etc.)

P = Plastic Dual In-Line
LH, LH8 = Plastic Leaded Chip Carrier
OW = Small Outline Integrated Circuit
TG = Thin Quad Flat Pack
TS = Thin Shrink Small Outline Package

SECOND SOURCE: A qualified second source for MX·COM integrated circuits is Consumer Microcircuits Limited.
Device numbers on Consumer's and MX·COM's products are the same with the following exceptions:
- Where MX·COM products bear an "MX" prefix, Consumer's products bear an "FX" prefix. For example, a
Consumer's FX365A is the equivalent of an MX·COM MX365A.
- MX·COM's and Consumer's products may not have identical pin-outs or package styles. Call the factory
for more information.
- Some MX·COM and Consumer's package styles have different suffixes:
MX·COM
Consumer's
24-lead Plastic Leaded Chip Carrier
LH
LS
28-lead Plastic Leaded Chip Carrier
LH8
LH
TO PLACE AN ORDER:
In the U.S. and Canada, call or write the MX·COM sales department:
Attn: Sales Dept.
MX·COM, Inc.
4800 Bethania Station Rd.
Winston-Salem, NC 27105
Phone: (910) 744-5050 OR (800) 638-5577 (Toll-Free in the Continental U.S., Alaska and Canada)
Fax (91 0) 744-5054.
The phones are staffed from 8AM to 5PM E.S.T., Monday through Friday.
Terms of payment are net 30 days with approved credit, F.O.B. Winston-Salem, NC.
In the Far East or Europe, please contact the authorized distributors listed on the inside back cover of this catalog.

Final Test is Performed in Clean, Controlled Environment
MX-COM, INC.

Page 9

Page 10

MX-COM, INC.

Technical Specifications

MiXed Signal
Integrated Circuits
The following sections contain specifications on
MX·COM's MiXed Signal IC's.

MX-COM, INC.

Page 11

Page 12

MX-COM, INC.

Technical Specifications

I

Section 1:
Wireless Modems
The following section contains specifications on
MX·COM's Wireless Modem IC's

Device

Description

Page

All

Guide to MX·COM Modems

p. 14

MX429/529

1200 bps MSK Modem with Parallel BUS Control

p. 15

MX439

1200 bps MSK Modem with Serial Control

p. 29

MX469

1200/2400 bps MSK Modem with Serial Control

p. 35

MX589

40k bps GMSK Modem with Serial Control

p. 43

MX809

1200 bps MSK Modem with C-BUS Control

p. 57

MX909

High-Speed and MOBITEX GMSK Modem

p. 70

MX919/929

High-Speed 4-Level FSK Modem/ARDIS

MX939

CDPD/AMPS-WBD Full-Duplex Modem

MX-COM, INC.

NEW
p. 103 NEW
p. 140 NEW

Page 13

;;?

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GUIDE TO MX-COM MODEMS

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'AS..•. ·

i.';;.,. '.:;
'.M:.,.

MX429

1200
MSK

FULL

8-BIT
PARALLEL

YES
1mATYP.

4.032

TRUNKED RADIO
BAND III
MPT 1317/1327

HIGH INTELLIGENCE
ERROR CHECKING IN RX
ERROR CHECK WORD GENERATION
FRAME SYNC/SYNT DETECTION

MX529

1200
MSK

FULL

8-BIT
PARALLEL

YES
1mATYP.

4.032

TRUNKED RADIO
PAA 1382
ETSI/EBSS 1200

HIGH INTELLIGENCE
ERROR CHECKING IN RX
ERROR CHECK WORD GENERATION
FRAME SYNC/SYNT DETECTION
PIN/FUNCTION COMPATIBLE WITH MX429

MX439

1200
MSK

FULL

NO

YES
650ll-A TYP.

4.032

GEN. DATA
TRUNKED RADIO
ZVEI/BOS/R2000
NMT 4501900

ON-CHIP RX & TX BANDPASS FILTERS
ON-CHIP CLOCK RECOVERY
PIN-SELECTABLE XTAUCLOCK FREQ.

1.008

GEN. DATA
TRUNKED RADIO
BAND III
ZVEI/BOS/R2000
NMT 4501900

ON-CHIP RX & TX BANDPASS FILTERS
ON-CHIP CLOCK RECOVERY
PIN-SELECTABLE XTAUCLOCK FREQ.
PIN/FUNCTION COMPATIBLE WITH MX439

RX & TX DATA CLOCK GENERATION
SERIAL RX & TX DATA INTERFACES
SELECTABLE BT (0.3 OR 0.5)
PIN/FUNCTION COMPATIBLE WITH MX489

or
1.008

,s:8

~

YES
6501l-A TYP.

4.032

1200
2400
MSK

FULL

MX589

4kTO
40k
GMSK

FULL
OR
HALF

NO

YES
1mATYP.

4.096
4.9152
2.048
2.4576

CDPD
RAM-MOBITEX
HIGH-SPEED DATA
UNIVERSAL DATA

MX809

1200
MSK

HALF

SERIAL
"C-BUS"

YES
2mATYP.

4.032

UNIVERSAL
TRUNKED RADIO
MODEM

MX909

4.8/9.6/19.2k
OR 4/8/16k

HALF

8-BIT
PARALLEL

YES
1mATYP.

1 to 10

RAM-MOBITEX

MX919

4.8/9.6/19.2k
4-Level FSK

HALF

8-BIT
PARALLEL

YES
1mATYP.

2to 10

UNIVERSAL

MX929

4.8/9.6/19.2k
4-Level FSK

HALF

8-BIT
PARALLEL

YES
1mATYP.

2to 10

RD-LAP

AUTO. HANDLES RD-LAP FRAME STRUCT.
"SOFT" VITERBI RX SIGNAL DECODING &
ERROR CORRECTION

MX939

10/19.2k
GMSK

FULL

8-BIT
PARALLEL

YES
1mATYP.

1.44

CDPD
AMPS-WBD

SAT TONE DETECTION & REGENERATION
SERIAL RX & TX DATA INTERFACES

MX469

~

I

';""<~PS);.,;, i:';'~iri;:; .,~RFACE~' '-'1110~;"': ;'"OVItii)i, ,'_~A~DARDS

NO

or

HIGH INTELLIGENCE
MPT1327 ERROR CHECKING
SELECTABLE CHECKSUM GEN.
AUTO. HANDLES MOBITEX FRAME STRUCT.
HIGH-SPEED DATA TRANSMISSION
AUTO. HANDLES GEN/PURP. FRAME STRUCT.
"SOFT" VITERBI RX SIGNAL DECODING &
ERROR CORRECTION

MX· rnM, IN~.

MX429
MX529

STANDARD PROTOCOL MSK MODEM FOR TRUNKED RADIO
FEATURES

APPLICATIONS

•
•
•
•
•

• Standard Protocol Radio Trunking
Systems
• Mobile Radio SELCALL, ANI, Status,
Data
• MX429: British MPT1327 Signaling
• MX529: French PAA 1382 Signaling

Full-duplex Operation
Generates Preamble I Detects Carrier
Flags Both Control & Traffic Frames
Detects Errors I Outputs Symptom
High Data Throughput for 2-way Radio

DESCRIPTION
The MX429 and MX529 are single-chip, low-power CMOS 1200 baud MSK Modems,
designed primarily for use in trunked radio, telemetry and packet radio applications. The
MX429 has been designed to conform to the MPT1317/1327 UK Band III trunked radio
protocols. The MX529 has been designed for both the PAA 1382 French trunked radio and
the proposed ETSI EBSS 1200 Digital Signaling Specifications.
The devices are full-duplex at 1200 baud and include an 8-bit parallel microprocessor
interface. The on-chip programmable timer may be settor interrupt periods of 8 to 120 bits.
Preamble and an error check word are automatically generated in Transmit mode. Error
checking is performed and the 16-bit SYNC or SYNT words are detected in Receive.
An on-chip xtal/clock generator which requires an external 4.032 MHz xtal or clock
input provides 4.032 and 1.008 MHz outputs. In addition, it performs all modem timings.
The MX429/MX529 requires a single 5 volt powersupply and has powersavecircuitry. They
are available in 24-pin Cerdip, 24-pin PDIP or 24-lead PLCC packages.

I
MX429J/529J (CDIP)
MX429P (PDIP)
24 pins

MX429LHl529LH
24-pinPLCC

RECEIVER INPUT

V DD •

MICROPROCESSOR
INTERFACE

STROBE.

~
~

~

~

: g~:

8·BIT uP BUS

~
~
~

CONTROL
REGISTER
TXPARITY
ENABLE

: gO:

rL---"-,
CLOCKS

TRANSMITTER
OUTPUT

XTALICLOCK
.. XTAL

Figure 1 - Internal Block Diagram

MX-COM, INC.

Page 15

I

MX429/MX529

PIN FUNCTION TABLE

V BIAS: The internal circuitry bias line, held at V 0012. This pin must be decoupled to Vss by capacitor C4' See
Figure 3.
2

2

TRANSMIT OUTPUT: The 1200 baud, 1200/1800Hz MSK TX output. When not enabled by the Control
Register (Do). the output is set to a high impedance state.

3

4

RECEIVER INPUT: The 1200 baud received MSK signal input. The 1200/1800 Hz audio to this pin must
be a.c. coupled via capacitor C 3 . See Figure 3.

5

5

V DO: Positive supply. A single +5V regulated supply is required. It is recommended that this power rail be
decoupled to Vss by capacitor Cs' See Figure 3.

6

6

CARRIER DETECT TIME CONSTANT: The on-chip carrier detect integration function requires a
capacitor, C5, to VsS' together with a resistor, R2, to VDO' that determine the carrier detect response time.

7

7

XTAUCLOCK: The inputto the clock oscillator inverter. A 4.032 MHz Xtal or externally derived clock pulse
input should be connected here. See Figure 3.

8

8

XTAL: The output of the 4.032 MHz clock oscillator.

9
10
11
12
13
14
15
16

9
10
11
12
13
14
15
16

Do:

17
18

17
18

AD:
A,:

Microprocessor Data Interface

0,:
O2 :
0 3 : These eight lines are used by the device to communicate with a
0 4 : microprocessor, and with the AD, A, and A2 inputs
0 5 : determining register selection.

Os:
0 7:
REGISTER SELECTION: These inputs, with the A, input,select the
required register to the data bus as shown in Table 1 (below).

Table 1

Control
Status
RX Data
TXData
Syndrome Low
Syndrome High

0
1
1
0
1
1

1
1
0
0
0
1

1
1
1
1
0
0

19

19

STROBE: This input performs the dual functions of selecting the device for Read or Write and strobing
data in or out. It should be generated by gating high order address bits with a read-write clock. This device
is selected when STROBE = 0 (see Figure 5). NOTE: If data at inputs 00-07 changes during STROBE
an interrupt may occur.

20

20

A,: This input determines which internal registers are connected to the Data Interface pins (00-07) during
STROBE (see Table 1 and Figure 5).

21

21

IRQ: Interrupt Request. This line will go to a logic "0" when an interrupt occurs. This output can be "wire
OR'd" with other active low components (100 kQ pullup to V oo).The conditions that cause the interrupts
are indicated at the Status Register and are as follows:
Timer Expired
TXldle

Page 16

RX Data Ready
RX SYNC Detect

TX Data Ready
RX SYNT detect

MX-COM, INC.

MX429/MX529

PIN FUNCTION TABLE
J,P LH
23

22

Vss: Negative Supply (GND)

24

23

CLOCK+4: A 1.008 MHz (X, +4) clock is available atthis output for external circuit use. Note the source
impedance and source current limits.

4,22

3,24

These pins are not connected. Leave open circuit.

I

Modems in Mobile Data Signaling ... An Introduction
Digital Code Format
The MPT1327 Signaling Standard for Trunked LMR Systems protocol is used by the MX429 for communication
between a trunking system controller (TSC) and users' radio units. The PAA 1382 Signaling standard protocol is used for
the MX529. These data stream formats are summarized in Figure 2.

SYNC or SYNT

Preamble
MX429
For bit sync.
101010.... 10.. -bit
reversals
Minimum 16 bits,
ending in logic "0"

SYNC Word
1100010011010111
HEX: C4D7

SYNT Word
0011101100101000
HEX: 3B28

MX529
SYNC Word
(PAA 1382) 1011010000110011
HEX: B433

SYNT Word
0100101111001100
HEX: 4BCC

~MPT1317

1327)

NOTESSYNQ+SYNT=_
SYNT= SYNC

Address
Code
Word

Optional
Data
Code Words

64 bits

/ '

Address Code Word Structure

(Bit 1 is transmitted first)

Bit No.

1

2 to 8

9 to 48

49 to 64

No. of bits

1

7

40

16

User's Identity

Address
& Data

Check Bits
(Checksum)

Structure Logic "1"

RX and TX at 1200 baud, the minimum overall transmission length is 96 bits.

Figure2 - The Data Stream forMPT 131711327 and PAA1382

MX-COM, INC.

Page 17

MX429/MX529
Modems in Mobile Data Signaling ... An Introduction (Cant.)
Operation
The MX429/S29 can be used in full-duplex mode in conjunction with a host microprocessor. The IlP operates on the
data, while the MX429/S29 handles all other signaling routines and requirements.
In the TX mode, the MX429/S29 will:
(1)

I

In the RX mode, the MX429/S29 will:

Internally generate and transmit a preamble for system
bit synchronization,

(2) Search for and detect the 16-bit SYNC or SYNT word,

(2) Accept from the host and transmit a 16-bit SYNC or
SYNTword,

(3) Output all received data after SYNC/SYNT in byte form,
and

(3) Accept from the host and transmit 6 bytes of data
(Address Code Word) and, upon a software command,

(4) Upon a software command (RX Message Format), use
the received checksum to calculate the presence (if
any) of errors and advise the host with an interrupt and
a 16-bit Syndrome word.

(a) internally calculate and transmit a 2-byte
checksum based on the previous 6 data bytes, or
(b) disable internal checksum generation and
allow continuous data transmission, and
(4) Transmit one "hang bit" and go idle when all loaded data
traffic has been sent (followed by a "TX Idle" interrupt).

(1) Detect and achieve bit synchronization within 16 bits,

Note: In the RX mode, a software command tells the
MX429/S29 to expect either a SYNC/SYNT word every 8
received bytes (6 data + 2 checksum) or a continuous data
stream. Normally the SYNC word is used on the Control
channel and the SYNT word is used on the Traffic data
channel.

Non-MPT Application (Full-Duplex)
The functions described here can be accessed via the commands and indications detailed in the Register Instructions
pages.
Transmit: When enabled, the device transmits a
"101010 ... 010" preamble until data fortransmission is loaded
by the host microprocessor. The MX429/S29 will transmit 6
bytes of the loaded data followed by a 2 byte checksum
based on that data. As long as TX data is being loaded, the
transmitter will transmit in the 6 byte datai2 byte checksum
format.
Automatic checksum generation can be inhibited by
a software command, allowing transmission of continuous
data streams.

Receive: A 16-bit SYNC or SYNT word is required
(see note above) before output of data bytes. The modem
receiver will then output continuous bytes of data. After
every 6 bytes, a 2-byte checksum word will be generated,
which can be ignored or used for error checking.

The Control Register, when selected, directs the modem's operation as described below.

Bit

Description

Function

Bit 0

TX Enable •

Set - Do enables the transmitter for operation. A "0-1" transition causes bit synchronization and the start of 1010......... 10 preamble pattern transmission. At least one byte of
preamble will be transmitted. If data is loaded into the TX Data Buffer before one byte has been
sent, then that data will follow. Otherwise, whole bytes of preamble will continue until data is
loaded.
Clear- The Transmitter Output pin is setto a high impedance and no transmitter interrupts are
produced.

Do

Page 18

Set = logic "1" (High)

Clear = logic "0" (low)

MX-COM, INC.

MX429/MX529

".~~
D,

TX Parity
Enable

Set - 0, indicates to the transmitter that 2-byte checksums are to be generated by
the modem. A "0-1" transition starts checksum generation on the next six bytes loaded from the
TX Data Buffer into the TX Data Register. Checksum generation continues for every six bytes
loaded until this bit is cleared. The transmitter will send the generated checksum (2 bytes) after
the last of each 6 bytes have been sent. If an underrun (no more data loaded) condition occurs
before 6 bytes have been loaded, checksum generation will abort, the transmission will cease
after one "hang" bit has been sent, and Bit 4 in the Status Register (TX Idle) will be set. No
checksum will be transmitted.
Clear - No checksum generation is carried out and the host may supply the checksum bytes.
The output is then "as written."

Bit2

RX Enable"

Set - O2 enables the receiver for operation. No data is produced (i.e. no RX Ready
interrupts) until a SYNC or SYNT word is found in the received bit stream.
Clear - The receiver is disabled and all interrupts caused by the receiver are inhibited.

D3

RXMessage
Format

Set - 0 3 is sampled after a checksum has been received and allows the host to
control the way the receiver handles the following data bits. If set, the receiver will assume that
the next 6 bytes are data and will start error checking accordingly.
Clear - The receiver will stop data transfer to the host after the 2 checksum bytes until another
SYNC or SYNT frame word is received.

Bit 4

Timer LSB

Bit 1

D2
Bit3

D.

BitS

D7

a
a
a
a
a
a
a
a

Timer

Ds

BitS

Timer

Ds

Bit 7

These 4 bits control the timer as follows:

TimerMSB

D7

1
1
1
1
1
1
1
1

Ds

Ds

a
a

a
a

0

1
1

a
1
1
1
1

a
a
a
a
1
1
1
1

a
a
1
1

a
a
1
1

a
a
1
1

D4

a
1

a
1

a
1

a
1

a
1

a
1

a
1

a
1

Reset Counter and disable timer interrupts
Count and interrupt every
8 bits
16 bits
"
"
"
"
"
24 bits
"
32 bits
"
"
"
40 bits
"
"
"
48 bits
"
"
"
56 bits
"
"
"
64 bits
"
"
"
"
72 bits
"
"
"
"
80 bits
"
88 bits
"
"
"
"
"
"
96 bits
104 bits
"
"
"
"
112 bits
"
"
120 bits
"
"
"

If a new timer value is written to these inputs within 1 byte period ofthe lasttimer interrupt,
the next timer period will be correct without first having to reset the timer. Otherwise, the
timer must be reset to zero and then set to the new time.
"Note:

Enabling Times - The time taken to enable one section (receiver or transmitter) when both sections are
initally disabled is 16 bit periods. If one section (receiver or transmitter) is already enabled this time is
reduced to 1/2 bit period.
TX Enable - If using the internal TX Preamble generation circuitry, e.g. with the internal timer setting the
preamble length, the device occasionally produces a TX Data Ready interrupt immediately after a TX
Enable. Software should handle this by either:
1) Detecting that the Timer Interrupt status bit is not set and that it is not appropriate to load data for
TX at that time.
or 2) By not using the timer, i.e. immediately after TX Enable, reading the status register and loading a
byte of preamble. This resets any interrupt. The length of the preamble transmitted is now controlled
by the number of bytes loaded.

MX-COM, INC.

Page 19

I

MX429/MX529

When an interrupt is generated the IRQ output goes Low with the Status Register bits indicating the sources of the
interrupt.
Set =logic "1" (High)

Clear = logic "0" (low)

Bit

Description

Function

Bit 0
Do

RX Data
Ready

Do' when set, causes an interrupt indicating that received data is ready to be read from the
RX Data Buffer. This data must be read within 8 bit periods.
Set - when a byte of data is loaded into the RX Data Buffer, if a frame (SYNC/SYNT) word has
been received.
Bit and Interrupt Cleared - a) by a read of the Status Register followed by a read of the RX
Data Buffer or b) by RX Enable going Low.

Bit 1
D,

RXChecksum
True

0 when set, indicates that the error checking on the previous 6 bytes agreed with
"
the received checksum. This function, which is valid when the RX Data Ready bit (DO) is set
for the second byte of received checksum, does not cause an interrupt.
Set - by a correct comparison between the received and generated checksums.
Cleared - a) by a read of the Status Register followed by a read of the RX Data Buffer, or b)
by RX Enable going Low.

Bit 2

RX Carrier
Detect

O2 is a "real time" indication from the modem receiver's carrier detect dircuit and does not
cause an interrupt. When MSK tones are present at the receiver input, this bit goes High. With
no MSK input, it goes Low. When the RX Enable bit (02 - Control Register) is Low, RX Carrier
Detect will go Low.

D3

TX Data
Ready

0 3 , when set, causes an interrupt to indicate that a byte of data should be written to the TX
Data Buffer within 8 bit periods.
Set - a) when the contents of the TX Data Buffer are transferred to the TX Data Register, or b)
when theTX Enable is set-"No interrupt is generated in this case.
Bit Cleared - a) by a read of the Status Register followed by a write to the TX Data Buffer, or
b) by TX Enable going Low.
Interrupt Cleared - a) by a read of the Status Register, or b) by TX Enable going Low.

Bit4

TXldle

0 4 causes an interrupt when set to indicate that all loaded data and one "hang" bit have been
transmitted.
Set - one bit period after the last byte is transmitted. This last byte could be either "checksum"
or "loaded data" depending on the TX Parity Enable state (Control Register 0 ,),
Bit Cleared - a) by a write to the TX Data Buffer, or b) by TX Enable going Low.
Interrupt Cleared - a) by a read of the Status Register, or b) by TX Enable going Low.

Bit 5
Ds

Timer
Interrupt

OS' when set, causes an interrupt to indicate that the set timer period has expired.
(Control Register D. - 0 7 ),
Set - by the timer.
Bit and Interrupt Cleared - by a read of the Status Register.

Bit6
D6

RXSYNC
Detect *

0 6 , when set, causes an interrupt to indicate that a 16-bit SYNC word (see Figure 2) has
been detected in the received bit stream.
Set - on receipt of the 16th bit of a SYNC word.
Bit Interrupt and Cleared - a) by a read of the Status Register, or b) by RX Enable going Low.

Bit 7
D7

RXSYNT
Detect *

0 7 , when set, causes an interrupt to indicate that a 16-bit SYNT word (see Figure 2) has
been detected in the received bit stream.
Set - on receipt of the 16th bit of a SYNT word.
Bit and Interrupt Cleared - a) by a read olthe Status Register, or b) by RX Enable going Low.

I
D2

Bit 3

D4

*Note

Page 20

SYNC and SYNT Detection is disabled while the checksum checker is running.

MX-COM, INC.

MX429/MX529

These 8 bits are the last byte of data received. Bit 7 is received first. Note the relative positions of the MSB and LSB
presented in this stream: the position may be different from the convention used in other microprocessor peripherals.

L5B

I
These 8 bits loaded into the TX Data Buffer are the next byte of data that will be transmitted (bit 7 first) .Note the relative
positions of the MSB and LSB presented in this stream: the position may be different from the convention used in other
microprocessor peripherals. If the TX Parity Enable bit (Control Register 0,) is set, a 2-byte checksum will be inserted and
transmitted by the modem after every 6 transmitted "message" bytes.

°1
L5B

M5B

The Syndrome Word
This 16-bit word (both Low and High bytes) may be used to correct errors.
Bits S, to S'5 are the 15 bits remaining in the polynomial divider of the checksum checker at the end of 6 bytes of
"received message." For a correct message all 15 bits (S, to S'5) will be zero.
The 2 Syndrome bytes are valid when the RX Data Ready bit (Status Regiser Do) is set for the second byte of the
received checksum and should be read, if required, before 8 byte periods.

51

59

52

510

53

511

54

512

55

513

56

514

57

515

58

Parity Error

0 7 is a "Parity Error Bit" indicating an error between the received parity bit and the parity bit internally generated from
the incoming message. So for a correctly received message all 16 bits of the Syndrome Word (S, to S'5 and Parity Error)
will be zero.
MX-COM, INC.

Page 21

MX429/MX529

,....-------------Inset

Clock
24
23 V

v
Transm~

Output

Receive Input

2

I

3

22

C3

I

C4~,V~ii::'=." ~
XTALJCIock
":"

XTAL

See Inssl 8

0

I

Recommended XTAL
Components

21 I--'I,-"R",--+
20 f+-!A2
:!!O..-_ _
19

MX429J
MX529J

Si'ROiiE

18 j+-!l'Al"--_
AO
171+-'-"'---

Cl~ ~C2

9

--------------Component References

~1

~

Com~~ment

R2

Cl
C2
C3
C4
C5
C6

Microprocessor Data Interface

~~*t 05**~~
06 07 08

Xl

Un~

Value
1M
1M
33p
33p
0.111
LOll

1.01L

LOll
4.032MHz

Tolerances: Resistors ±10%

DO 01 03 D4

C8pacitors ±20%

Figure 3 - Recommended Extemal Components

Carrier Detect Capacitor
The value of the Carrier Detect Capacitor, Cs' determines the carrier detect time constant. A long time constant
(larger value Cs) results in improved noise immunity but increased response time. Cs may be varied to optimize noise
immunity/responsetime.

2

X

10"

Ideal Coherent MSK
Characteristic

10'"

\

MX429
Characteristic

8
6
4

3
2

Signal to

Ratio (dB) [Bit-Rate Bandwidth]
(Linear Scale)

Figure 4 - Bit Error Rate vs Signal to Noise Ratio
Page 22

MX-COM, INC.

MX429/MX529
Timing Information
DATA READ (OUT OF MX429)

~~~~~s

==><.:. ----------------i'".....,,;:>C:

rc:

~

_ _ _ _~'_ _
'

c'_ _ __ _

I~:

Si'RffiiE

~?UT

!

M

:~

tSTR

:-tACS-:

. - tOHR-:

p>-

q

lACS - Chip Select Access Time: 135ns max.
lAS - Address Set-up TIme: Ons min.
tAH
Address Hold Time: Dns min.
t",." - Outpul Hold Time: 15ns min., l05n8 max.
I"", - Strobe TIme (Read): I40ns min.

DATA WRITE (INTO MX429)
ADDRESS

AO,A1,A2.

==><~!

__________________ ;;::::;:

+,~;:>C:

.-.
: tAS :

,

----~-....
:""-:

tsrw

(WRITE)

I AH

:...,.....,....-..;.;-----

~

DATA IN

tAS - Address Set-up Time: Qns min.

,: tAH I

,

:tl»fN

i:><

==>S

AS

81

1)(

OUTPUT

IRQ OUTPUT

Checksum
Data Code
Hang Bn

Preamble
S - SYNC/SYNT
TX Output at bias level
2 - TX Oulput at hi h impedance
3 - If TX Data R~ 18 set he", tt Inhlbilll TX DaIa
Roady Interrupt The TX Idle Interrupt occurs

111-

1 bit later.

Figure 7 - Simplified TX Timing
Page 24

A:l

______~1

Noles
CD H P-

N2

t

DATA
READY

1)(

WRITE TO 1)(
DATA BUFFER
READ STATUS
REGISTER
1)( PARITY
ENABLE
1)(

IDLE

Ii "
~

"I
l!

1)(

I

Parity Enable remain. high. IndlcaHng 1I1at

all foUowing data is to be included in

the checksum

MX-COM, INC.

MX429/MX529
Basic Power-up Software

(

)

Power Up

r
Set up a 1 byte variable - initialize to zero
(AX Msg length)

I
Set up an 8 byte variable
start address (IX Buffer)

Write 04

to Control Regi_

r
- Wait at least 1

b~

-

r
Write zeros

to MX429 Control Register

B~

Write to Control Register
B~ 2 - AX Enable = 1
3 - AX Message Format = 0

Return to Main. Program
Figure 8 - Power-up Flow
MX-COM, INC.

Page2S

MX429/MX529
Basic Software Interrupt Flow

I

No

Yes

Write to Control Register - TX Enable

=0

No

If error correcting is to
be done, Read and Save
Syndrome - High and Low

Yes
No

Retum
from IRQ
Figure 9 - Interrupt Flow
Page 26

MX-COM, INC.

MX429/MX529

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

OPERATING LIMITS

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following conditions
unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(ref V ss OV)
Sink/Source Current
(supply pins)
(other pins)
Total Device Dissipation
@ T AMB 25°C
Derating
Operating Temperature
Storage Temperature

=

=

-0.3 to 7.0 V
-0.3 V to V DD + 0.3 V
Xtal/Clock fo
±30mA
±20mA

=4.032 MHz

Audio Level OdB ref.

I

=300 mVrms

800mWmax.
10mW/oC
-40°C to +85°C
-55°C to + 125°C

Static Values
Supply Voltage

RX Enabled, TX Disabled
RX Disabled, TX Enabled
RX & TX Disabled

5.5

4.5

Supply Current Ranges
RX & TX Enabled

10

V

5.0
5.0
5.0
1

mA
mA
mA
mA

1.5

ms

Dynamic Values
Modem Intemal Delay

Interface Levels
Output Logic "1" Source Current
Output Logic "0" Sink Current
Three State Output Leakage Current

2
3

120
360
4.0

Do - D7 Data InlOut
Logic "1" Level
Logic "0" Le=,v=,e:,-I=-=
A" Ao' A2, STROBE, IRQ
Logic "1" Level
Logic "0" Level

V

3.5
1.5

V

1.0

V
V

4
4.0

Analog Impedances
RX Input
TX Output (Enabled)
TX Output (Disabled)

kO
kQ
MO

100
10
5

On-Chip Xtal Oscillator

R'N
RDUT
Oscillator Gain
Xtal Frequency
Timing (See Fig. 5)
Chip Select Access Time (tAGS)
Address Hold Time (tAH)
Address Set-up Time (tAS)
Data Hold Time (Write) - (t DHW )
Data Set-up Time - (tDS)
Output Hold Time (Read) - (tOHR)
Strobe Time (Read) - (tSTR )
Strobe Time (Write) - (tSTW)

MX-COM, INC.

5

10
5.0

15
15
4.032
135

0
0
85
0
15
140
50

105

MO
kO
dB
MHz
ns
ns
ns
ns
ns
ns
ns
ns

Page 27

I

MX429/MX529
Receiver

Signal Input Levels
Bit Error Rate
@ 12 dB Signal/Noise Ratio
@ 20 dB Signal/Noise Ratio
Synchronization @ 12 dB SIN Ratio
Probability of Bit 16 being correct
Carrier Detect Response Time

6

-9.0

-2.0

+10.5

dB

7

7.0
1.0

8
99.5
13.0

8

%
ms

Transmitter

Output Level
Output Level Variation
Output Distortion
3rd Harmonic Distortion
Logic "1" Frequency
Logic "0" Frequency
Isochronous Distortion
1200-1800 Hz
1800-1200 Hz

8.25
-1.0

9
9

3.0
2.0
1200
1800
25
20

+1.0
5.0
3.0

40
40

dB
dB
%
%
Hz
Hz
Ils
Ils

Notes

1. With each data line loaded as C = 50 pf and R = 10 kQ.
2. VOUT =4.6 V.
3. VOUT = 0.4 V.
4. Sink/Source currents:::; 0.1 rnA.
5. Both Xtal and Xtal + 4 Outputs.
6. With 50 dB SIN ratio.
7. See Figure 3, Bit Error Rate.
8. This response time is measured using a 10101010101 ... 01 pattern input signal at a level of 230 mVrms (-2.3 dB) with
no noise.
9. Dependent upon Xtal tolerance.
10. Powersave is only active when both RX and TX functions are disabled.

Checksum Generation and Checking
Generation - The checksum generator takes the 48 bits from the 6 bytes loaded into the TX Data Buffer and divides them
modulo-2, by the generating polynomial:

X'5 + X14 + X13 + X" + X4 + X2 + 1
It then takes the 15-bit remainder from the polynomial divider, inverts the last bit and appends an EVEN parity bit generated
from the initial 48 bits and the 15 bit remainder (with the last bit inverted).
The 16-bit word is used as the "checksum."
Checking - The checksum generator does two things:

It takes the first 63 bits of a received message, inverts bit 63, and divides them modulo-2, by the generating polynomial:
X'5 + X'4 + X13 + X" + X4 + X2 + 1
The 15 bits remaining in the polynomial divider are checked for all zero.
Second, it generates an EVEN parity bit from the first 63 bits of a received message and compares this bit with the received
parity bit (bit 64). Ifthe 15 bits in the polynomial divider are all zero, and the two parity bits are equal, then the RX Checksum
True bit (SR D,) is set.
Page2B

MX-COM, INC.

MX·~M,IN~.

MX439

MSK MODEM
FEATURES
1200 Baud MSK Modem
Meets Cellular & Trunked Radio Specifications
Full-Duplex 1200 Baud
On-Chip RX and TX Bandpass Filters
Clock Recovery and Carrier Detect
Pin Selectable XtallClock Frequencies

MX439J: 22 pin CDIP
MX439P: 22 pin PDIP

APPLICATIONS
Mobile & Cellular Radio Data Signaling
Personal Radio
Portable Data Terminals
General Purpose Applications

MX439DW
24-pin SOIC

MX439LH
24-pin PLCC

DESCRIPTION
The MX439 is a single-chip CMOS LSI circuit which
operates as a 1200 baud MSK modem. The mark and
space frequencies are 1200Hz and 1S00Hz phase continuous, and the frequency transitions occur at the zero
crossing point. The transmitter and receiver will work
independently, thus providing full-duplex operation at 1200
baud. The baud rate, transmit mark and space frequencies, and the TX and RX synchronization are all derived
from a highly stable Xtal oscillator. The on-chip oscillator
is capable of working at one of two input frequencies:

1.00SMHz or 4.032MHz external Xtal/clock input. Frequency is pin-selectable with the "Clock Rate" logic input.
The device includes circuitry for carrier detect and facility
forthe RX clock recovery. An on-board switched capacitor
900Hz - 2100Hz bandpass filter provides optimum carrier
filtering. The use of switched capacitor analog filters and
digital signal processing results in excellent dynamic performance with few external components; the CMOS process and current-saving techniques offer low standby
supply current for portable battery-powered applications.

CARRIER DETECT
TIME CONSTANT ('t)

~

CARRIER DETECT
______________________
~OUTPUT

r---------------.

AX SYNC

CLOCKED AX DATA

BANDPASS
OUWU~-+------~~

AX INPUT

--+---I

~)h~Ej

MONOSTABLE

I

Wo~Ej: 6Jlf1

~
::

r
-t>: I____________+

~

TXDATA
1)(

GENERATOR

1)(

FILTER

BUFFER

Figure 1 - Internal Block Diagram

MX-COM, INC.

Page 29

I

I

MX439

PIN FUNCTION TABLE
Pin
DW

J,P

Function
LH
XtaVClock: The input to an on-chip inverter for use with either a 1.008MHz or a
4.032MHz Xtal. Alternatively, an external clock may be used. Xtal frequency is
selectable on the "Clock Rate" input pin.

2

2

2

Xtal: Dutput of the on-chip inverter. (See Figure 2.)

3

3

3

TX Sync DIP: MSK signal centered at a DC level of V S1AS

5

5

5

TX Signal DIP: With the transmitter disabled, this pin is set to a high impedance state.
When the transmitter is enabled, this pin outputs the 1200/1800Hz MSK signal centered
at a DC level of VS1AS - 0.7 V. (See Figure 5.)

7

6

7

TX Data liP: Serial logic data to be transmitted is input to this pin and synchronized by
the "TX Sync D/P." (See Figure 5.)

8

7

8

TX Enable: A logic "1" applied to this input will put the transmitter into powersave while
forcing "TX Sync DIP" to a logic "1" and ''IX Signal DIP" to a high impedance state. A
logic "0" will enable the transmitter (See Figure 5). This pin is internally pulled to VDD •

9

8

9

Bandpass DIP: This is the output of the RX 900Hz-2100Hz bandpass filter. The output
impedance of this pin is typically 10kn and may require buffering prior to use.

10

9

10

RX Enable: This is the control of the RX function. The state of other outputs is given
below:

RX Enable
"1"
"0"

RX Function
Enabled
Powersave

Clock Data OIP
Enabled
"0"

-

0.7V. (See Figure 5.)

Carrier Detect RX Sync Out
Enabled
Enabled
"1" or "0"
"0"

When both TX and RX functions are disabled, the bias voltage is switched internally to
Vss and Bias pin output impedance is approximately 12.5kQ. When the Bias pin is
decoupled by a 1.011F capacitor (C2) the MX439 may require up to 25ms to establish
correct operation after enabling the RX function. This period may be decreased by either
reducing the value of C2, lowering the Bias pin impedance externally, or adopting a
different powersaving strategy (such as using C2 and C5 and supplying V00 via a series
switch). This pin is internally pulled to VOO.
11

10

11

Bias: Provides bias internally and should be decoupled externally to V55 by capacitor
(C2 ). (See Fig. 2.)

12

11

12

V•• : Negative supply rail (GND).

13

12

13

Unclocked Data DIP: This pin outputs recovered asynchronous serial data from the
receiver.

14

13

14

Clocked Data DIP: This pin outputs recovered synchronous serial data from the receiver
and is internally latched out by a recovered clock appearing on the "RX Sync DIP" pin.
(See Figure 6.)

15

14

15

Carrier Detect DIP: This pin will output a logic "1" when an MSK signal is being received.

16

15

16

RX Signal lIP: This is the MSK signal input for the receiver. It should be decoupled using
capacitor C3 •

18

17

18

RX Sync DIP: This is a flywheel 1200Hz squarewave output which, upon presentation
of the MSK data signal, is synchronized internally to the incoming data. (See Figure 6.)

Page 30

MX-COM, INC.

MX439
Pin

Function

ow

J,P

LH

21

19

21

Clock Rate: This logic input selects and allows the use of either a 1.00SMHz or 4.032MHz
Xtal/clock input to the on-chip inverter. Logic "1" = 4.032MHz; logic "0" = 1.00SMHz. This
input has an internal pulldown resistor (1.00SMHz).

22

20

22

Carrier Detect Time Constant (1:): This input forms part of the carrier detect integration
function. The value of C4 connected to this pin will affect the carrier detect response time
and hence noise performance. (See Figure 2, Note 3.)

24

22

24

V DO: Positive supply rail. A single 5 volt supply is required.

4,6,17
19,20
23

4,16,
1S,21

4,6,17
19,20,
23

I

No Connection.

Note: Output Loading. Large capacitive loads could cause the output pins of this device to oscillate. If capacitive
loads in excess of 200pF are unavoidable, a resistor of (typically) 100n put in series with the load should minimize
this effect.

C1

r r

3

C7

C6

C2

5

BPF OUT
AX ENABLE

Tolerances:

Value
1M
33p
1.011
0.111
0.111
1.011
1.011
33p
1.00SMHz
or 4.032 MHz
R = ±10%
C = ±20%

8
9

*

MX439J

7

Component References
Component
R1
C1
C2
C3
C4
C5
C6
C7
X1

IC4

4

6

r
r1

C5

2

X IN

F!--

CARRIER DETECT

BIAS

10

13 CLOCKED DATA

Vss

11

12 UNCLOCKED DATA

Notes:
1. Bias may be decoupled to V 88 and V DO using C2 and C6 when input
signals are referenced to the bias pin. For input signals referenced to V88'
decouple Bias to V88 using C2 only.
2. Use C5 when input signals are referenced to V 88 to decouple V DO'
3. The value of C4 determines the carrier detect time constant. A long time
constant results in improved noise immunity but increased response time.
C4 may be varied to trade-off response time for noise immunity.
4. The value of C7 reduces XTAL voltage overshoot. Refer to MX-COM's
Crystal Oscillator Application Note (see Appendix).
5. X1 can be either a 1.00S MHz or 4.032 MHz crystal, depending on the
Clock Rate setting.

Figure 2 - External Component Connections
MX-COM, INC.

Page 31

MX439
DIAGRAMS
1

1

10.'

X

10-2

X

B.E.R.
1

I

1

X

X

10"

"Bit Rate Bandwidth

~e
,

\~

i'-

\ '"

10"

1 x 10"

~

'-....

~
r-

V
/'

_V

/

\~

50

100

150

200

250

aoo

500

700

BOO

Input Signal Level (mVrms)

Figure 3 - Typical Variation of "BER." with Input Signal Level

"Incorporates an attenuator &
5kHz BW noise genemror.

Figure 4 - MX439 Test Set-up
-+II.....- 2pB

MIN.

r~O~MAX.

11----+------+11I
I
TX SYNC OIP

T!

SEE NOTE
TX DATA VP

TX SIGNAL OIP

DC

~~~~~~

~ MIN.

I

SEE

I'brE

2

3~1\~~

~DC
II
II
II
- I 1+-1.2pB II
II
II
II
II
II
II
II
II
II
I
II
I
I

SEE NOTE 4

-----!-----

__ L

_~

~

NOTES:
1. All timings are related to the TX SYNC OUTPUT. 3. 2~ min. + crystal tolerance.
2. O.833ms for 1.008MHz or 4.032MHz XtaL
4. DC = Don't Care. DV = Data Valid.
Figure 5 - Transmitter Timing Diagram
Page 32

MX-COM, INC.

MX439
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

OPERATING LIMITS

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All charactistics are measured using the standard test
circuit (Figure 4) with the following test parameters and is
valid for all tests unless otherwise stated:

Supply Voltage
Input Voltage at any pin
(ref Vss = OV)
Sink/Source Current (Total)
Total Device Dissipation
@ T AMB = 25°C
Derating
Operating Temperature
Storage Temperature

-0.3 to 7.0 V
-0.3 V to V DD + 0.3 V
20mA
800mW max.
10 mW/oC
-40°C to +85°C
-55°C to +125°C

VDD = +5V
TAMB = 25°C
Xtal (X1) Frequency: 1.008MHz
OdB reference = 300 mVrms
Noise (band limited 5kHz gaussian white noise)
SNR ratio measured in bit rate bandwidth (1200Hz)

Ultit
Static Values
Supply Volts
Supply Current:
RX Enabled, TX Disabled
RX Enabled, TX Enabled
RX Disabled, TX Disabled
Logic "1" level
Logic "0" level
Digital Output Impedance
Analog and Digital Input Impedance
TX Output Impedance
On-Chip Crystal Oscillator:
Rin
ROUI
Inverter Gain
Gain Bandwidth Product
Crystal Frequency
Crystal Frequency
Dynamic Values
Receiver:
Signal Input: Dynamic Range (50dB SNR)
Bit Error Rate:
12dB SNR
20dB SNR
ReQeiver Synchronization 12dB SNR:
Probability of Bit 8 being correct
Probability of Bit 16 being correct
Carrier Detect
Sensitivity
Probability of Carrier Detect being high:
12dB SNR after Bit 8
12dB SNR after Bit 16
OdB Noise (No Signal)

MX-COM, INC.

4.5

5.0

5.5

3.6
4.5
650

mA
mA

80%VDD
20%V DD
100
10

1,9
1,10

2,3
3
3

15
20

230

MQ
kQ
dB
MHz
MHz

1.008
4.032

100

itA
V
V
kQ
kQ
kQ

4

10
5
10
3 x 106

V

1000

mVrms

7.0
1.0

10.4
10.8

99
99.5

%
%

6

4
6,7
4,8
4,8
8

125
98
99.5
5

mVrms
%
%
%

Page 33

I

I

MX439

Transmitter Output
TX Output Level
Output Level Variation 1200/1800Hz
Output Distortion
3rd Harmonic Distortion
Logic "1" Carrier Frequency
Logic "0" Carrier Frequency
Isochronous Distortion
1200Hz - 1800Hz
1800Hz - 1200Hz

775

o

3
2

5
5

mVrms
dB
%

±1.00
5
3

0/0

1200
1800

Hz
Hz

25
20

40
40

J.1s
J.1s

Notes:
1. Crystal frequency, type and tolerance depends on system requirements.
2. See Figure 3.
3. SNR (Bit Rate Bandwidth).
4. See Figure 2, Note 3.
5. Depending on crystal tolerance.
6. 10101010101 ... pattern.
7. Measured with 100 mVrms signal (No noise).
8. OdB level for CD probability measurements is 230mVrms.
9. Clock rate pin at logic "0."
10. Clock rate pin at logic "1."

AX
SIGNAL
INPlJ[

~~'v\~A !\ f\ /
I ....

W: Vl/ VV

2

10"

W

g
en
g

(NOTE 1)

d

a:

i

IJNOTE 4~1

w

Iii

(NOTE 2)1
l ___________

~'~~~

LOGIC

o

2 __________ _
(NOTE 3)

NOTES:
1. Internal delay typically 1.5ms.
2. From freely running to Sync in 8 data bits (See spec).
3. Undetermined state: 2J.1S max.
4. Min 800J.1s, Max. 865J.1S.

Figure 6 - Receiver Timing Diagram

Page 34

10"

~

AX SYNC
OUTPUT
(1200Hz) 0

CLOCKED
DATA
OUTPUT

x 10-"

10"
9
8

a5
4
3

o

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

SNR (dB) BIT RATE BANDWIDTH (LINEAR SCALE)

Figure 7 - Receiver BER. vs SNR

MX-COM, INC.

MX·~,IN~.

MX469

Preliminary Information

1200 AND 2400 BPS MSK MODEM
Features
•
•
•
•
•

Selectable Data Rates: 1200 and 2400 bps
Full-Duplex MSK
RX and TX Bandpass Filters
Clock Recovery and Carrier Detect Cababilities
Pin Selected Xtal/Clock Inputs
1.00BMHz or 4.032MHz
• Radio and General Applications
• Data-Over-Radio • PMR/Cellular Signaling
• Portable Data Terminals
• Personal/Cordless Telephone
TX GENERATOR

~
:

'

"I'

,

MX469P/J
22-pin PDIP/CDIP

,I

MX469LH
24-pin PLCC

MX469DW
24-pin SOIC

TX FILTER
TX SIGNAL DIP

TX DATA liP

TX SYNC
CLOCK RATE

DIP

--v"

XTAUCLOCK

V BIAS

f..

n

XTAL

1200/2400 BPS SELECT

v"

BANDPASS O/P

AX ENABLE
AX SIGNAL lIP

•

UNCLOCKED

DATA OJP

CLOCKED
DATA O/P

•

RX SYNC OIP

CARRIER DETECT DIP

•

Figure 1 - Functional Block Diagram

Description
The MX469 is a full-duplex pin-selectable 1200 or
2400 bps Minimum Shift Key (MSK) Modem for FM radio
links. The mark and space frequencies are 1200/1BOO
and 1200/2400Hz respectively. Tone frequencies are
phase continuous; transitions occur at the zero crossing
point.
Use of a common Xtal oscillator with a choice of two
clock frequencies (1.00BMHz or 4.032MHz) provides
data-rate, transmit frequencies and RX/TX
synchronization. The transmitter and receiver operate
entirely independently including individual section
powersave functions.
The MX469 includes on-chip circuitry for Carrier
MX-COM, INC.

Detect and RX Clock Recovery, both of which are made
available at output pins.
RX, TX and Carrier Detect paths each contain a
bandpass filter to make sure you get the best quality
signal in the Modem and TX modulation circuitry.
The MX469 demonstrates a high sensitivity and good
bit-error-rate even under adverse signal conditions.
The carrier detect time constant is set by an external
capacitor, whose value should be arranged as required to
further enhance this product's performance in high-noise
environments.
This low-power device requires few external
components and is available in SOIC (small outline),
CDIP, PDIP and PLCC packages.
Page 35

I

MX469

Pin Function Table
Pin Number
ow

Function

MX469
J/P
LH
XtaliClock: The input to the on-chip inverter, for use with either a 1.00SMHz or a
4.032MHz Xtal or external clock. Clock frequency selection is by the "Clock Rate"
input pin. The selection of this frequency will affect the operational Data Rate of this
device. Refer to 1200/2400 BPS Selection information on the next page. Operation of
any MX·COM IC without a Xtal or clock input may cause device damage. To minimize
damage in the event of aXtall drive failure, it is recommended that a current limiting
device (resistor or fast-reaction fuse) in installed on the power supply (Voo)'

2

2

2

Xtal: Output of the on-chip inverter.

3

3

3

TX Sync OIP: A squarewave, produced on-chip, to synchronize the input of logic data
and transmission of the MSK signal (See Figure 4).

5

5

5

TX Signal O/P: When the transmitter is enabled, this pin outputs the (140-step
pseudo sinewave) MSK signal (See Figure 4). With the transmitter disabled, this
output is set to a high-impedance state.

7

6

7

TX Data liP: Serial logic data to be transmitted is input to this pin.

8

7

8

TX Enable: A logic '0' will enable the transmitter (See Figure 4). A logic '1' at this
input will put the transmitter into powersave while forcing "TX Sync Out" to a logic '1'
and "TX Signal Out" to a high-impedance state. This pin is internally pulled to V 00'

9

8

9

Bandpass O/P: The output of the RX Bandpass Filter. This output impedance is
typically 10kQ and may require buffering prior to use.

10

9

10

RX Enable: The control of the RX function. The control of other outputs is given
below.

RXEhable= RX Function Clock Data O/P
"1 "
=
Enabled
Enabled
"0"
"0"
= Powersave

11

10

11

12

11

12

Page 36

Carrier Dl'rtectRxSyrtcOut
Enabled

Enabled

"0"

"1" or "0"

VB1AS : The output of the on-chip analog bias circuitry. Held internally at Voo/2, this pin
should be decoupled to Vss by a capacitor (C 2 ). See Figure 2 and RX Enable notes.
This bias voltage is maintained under all powersave conditions.

VSS:

Negative supply rail (GND).

MX-COM, INC.

MX469
Pin Number

Function

DW

MX469
J/P

LH

13

12

13

Unclocked Data O/P: The recovered asynchronous serial data output from the
receiver.

14

13

14

Clocked Data OIP: The recovered synchronous serial data output from the receiver.
Data is latched out by the recovered clock, available at the "RX Sync O/P", (See Fig. 5).

15

14

15

Carrier Detect O/P: When an MSK signal is being received this output is a logic '1'.

16

15

16

RX Signal liP: The MSK signal input for the receiver. This input should be coupled via

a capacitor, C3 .
18

17

18

RX Sync O/P: A flywheel squarewave output. This clock will synchronize to incoming
RX MSK data (See Figure 5).

19

16

19

1200/2400 BPS Select: A logic '1' on this pin selects the 1200 bps option. Tone
frequencies are: one cycle of 1200Hz represents a logic '1', one-and-a-half cycles of
1S00Hz represents a logic '0'. A logic '0' on this pin selects the 2400 bps option.
Tone frequencies are: one-half cycle of 1200Hz represents a logic '1', one cycle of
2400Hz represents a logic '0'. This pin has an internal 1MQ pullup resistor.

Operational Data Rate Configurations are illustrated in the table below.
XtallClock Frequency
Clock Rate pin
1200/2400 Select pin
Data Rate (bps)

1.008MHz

4.032MHz

o

0

1

1

1
1200

0
2400

1
1200

0
2400

20

18

20

Internally connected, leave open circuit.

21

19

21

Clock Rate: A logic input to select and allow the use of either a 1.00SMHz or
4.032MHz Xtal/clock. Logic '1' = 4.032MHz, logic '0' = 1.00SMHz. This input has an
internal pulldown resistor (1.00SMHz).

23

20

22

Carrier Detect Time Constant: Part of the carrier detect integration function. The
value of C. connected to this pin will affect the carrier detect response time and hence
noise performance (See Figure 2, Note 3).

24

22

24

Voo: Positive supply. A single 5-volt supply is required.

4,6,
17,
22

4,
21

4,6,
17,
23

MX-COM, INC.

No internal connection, do not use.

Page 37

I

MX469
Application Information
XTAUCLOCK
R,

C;>Voo

1

A

f:'Yv

22

XTAL

TX SYNC O/P

TX SIGNAL O/P
TX DATA liP

I

TX ENABLE
BANDPASS O/P
RX ENABLE

VBIAS

vss

2
3
4
5
6

Voo

21 \-20

CARRIER DETECT
TIME CONSTANT
CLOCK RATE

19

MX469J

7
8
9
10
11

18
17
16
15
14
13
12

I

1---------'

t--

RX SYNC O/P
120012400 BPS SELECT
RX SIGNAL liP
CARRIER

C S I~

DETECT~ O}~

CLOCKED DATA O/P
UNCLOCKED DATA O/P
~

--:Component

Value

Tolerance

R,

1.0M!}
33pF
1.01JF
O.1IJF
O.1IJF
1.01JF
33pF
1.00BMHz

±10%
±5%
±20%
±20%
±10%
±25%
±5%
See
'Clock-Rate'
Pin

C,

C2
C3
C4
Cs
C6
X,

or
4.032MHz

Notes

1. VBIAS may be decoupled to Vss and VDO using C2 and
Cs when input signals are referenced to the VBIAS
pin. For input signals referenced to VsS' decouple
VBIAS to Vss using C2 only.

2. The value of C4 determines the Carrier Detect time
constant. A long time constant results in improved
noise immunity but increased response time. C4
may be varied to trade-off response time for noise
immunity.
3. Ca reduces Xtal voltage overshoot. Refer to
MX·COM Xtal Application Note (see Application
section).

Figure 2 - External Components

r

v

v

?"

MILLI-

MILLI-

AMMETER

AMMETER
CLOCKED
DATA OIP

TX
DATA

I

lIP
PREAMBLE &
PSEUDO-RANDOM
DATA
GENERATOR

TX
SIGNAL
OIP

MX469

-----

i

TRANSMITIER

(~m~~~e~}ts

I
Tx SYNC

BUFFER

I-r+

j. ""'"

OSCILLOSCOPE

(INTERFACE)

CIRCUIT

f----t

S3 TELEPHONE
CHANNEL
SIMULATOR
(with attenuator
&
5kHz BW noise gen)

RX
SIGNAL
VP

I
MX469

c ..

RECEIVER

RX
SYNC

-r-

.
ERROR

DETECTOR

(~m~~e£ts

1

...
TRUE RMS

TRUE RMS

VOLTMETER

VOLTMETER

1

CARRIE~
DETECT
OIP

CARRIER
DETECT
OIP HIGH

DETECTOR

Figure 3 - Suggested MX469 Test Set-Up
Page 38

MX-COM, INC.

MX469
Application Information ..... .
TX
ENABLE

TX
SYNC

TX DATA

DC "" Oonl Care
DV = Data Valid

1200 BPS
TX OUTPUT

2400 BPS
TX OUTPUT

OPEN CIRCUIT

OPEN CIRCUIT

OPEN CIRCUIT

OPEN CIRCUIT

I

Figure 4 - Transmitter Timing

Characteristics

Note

Min.

TX Delay, Signal to Disable Time
Data Set-Up Time
Data Hold Time
TX Delay to OIP Time
TX Data Rate Period
RX Data Rate Period
Undetermined State
Internal RX Delay
t'D
1. Consider the Xtal/Clock tolerance.
2. All TX timings are related to the TX Sync Output.

Typ.

2.0
2.0
2.0

Max.

Unit

800

IJs
IJs
IJs
IJs
IJs
IJs
IJs
ms

1.2
833
865
2.0

800
1.5

RX
SIGNAL liP
2400 BPS

LOGIC '0'

LOGIC'1'

RX
SIGNAL liP
1200 BPS

1:

i----,

RX
SYNC OIP
(1200Hz)

~

tRDR

~

--.i

i.-Undetermined

: :

g~~;~~ :::umummn::::::::u:::::::::u:umm :: uumuuJ
1

State

LOGIC'1'

I

LOGIC '0'

I

Figure 5 - RX Timing Diagram

MX-COM, INC.

Page 39

I

MX469
Application Information ..... .

1

10-1

X

*

1

BIT RATE BANDWIDTH

10-2

X

W

!;;c
a:
a:
0 1 x 10-3
a:
a:
w

I-

iIi

1

X

10-4

1

X

10-5
100

50

250

200

150

300

500

700

800

INPUT SIGNAL LEVEL (mVrms)

Figure 6 - Typical Variation of Bit Error Rate with Input Level

2

X

W

MX469

IDEAL COHERENT MSK

10-2

10-3

~
a:
a:

oa:

a:
w

I-

10

10-4
8

1Q-s--1---,--,--,--..,--..,----,---r---r--..,--,---'-;---;--...,----,--'.......,,.--r--r--

o

2

3

4

5

6

7

8

9

10

11

12

13

14

15

SNR (dB) BIT RATE BANDWIDTH

16

(lin scale)

Figure 7 - RX Bit-Error-Rate vs Signal-to-Noise Ratio

Page 40

MX-COM, INC.

MX469

Specifications
Absolute Maximum Ratings

Operating Limits

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(ref Vss=OV)
Sink/Source Current
(supply pins)
(other pins)
Total Device Dissipation
(@ T AMS=25°C)
Derating
Operating Temperature
Storage Temperature

-0.3 to 7.0V

Voo = 5.0V

-0.3 to (Voo+ 0.3V)

TAMS = 25°C

±30mA
±20mA

Audio Level OdB ref = 300 mVrms
Xtal/Clock = 4.032 MHz

800mW max.
10 mW/oC
-40°C to +85°C
-55°C to +125°C

Signal-to-Noise Ratio measured in the Bit-Rate
Bandwidth (1200 bps BRB = 1200 Hz
2400 bps BRB = 2400 Hz)

Static Values
Supply Voltage
Supply Current RX Enabled, TX Disabled
RX and TX Enabled
RX and TX Disabled
Logic '1' Level
Logic '0' Level
Digital Output Impedance
Analog and Digital Input Impedance
TX Output Impedance
On-Chip Xtal Oscillator

4.5

Dynamic Values
Receiver
Signal Input Dynamic Range SNR = 50dB
Bit Error Rate
SNR = 12dB
SNR = 20dB
Receiver Synchronization SNR =12dB
Probability of Bit 8 Being Correct
Probability of Bit 16 Being Correct
Carrier Detect
Sensitivity
Probabilty of C.D. Being High
(1200 bps) SNR = 12dB
After Bit 8
SNR = 12dB
After Bit 16
OdB Noise
No Signal

MX-COM, INC.

5.5

~A

1.0
4.0
100
10.0

3, 4
4
4
7

100

V
V
kQ
kQ
kQ
MQ
kQ

10.0

2

V
mA
mA

4.0

RIN

ROUT
Inverter d.c. Voltage Gain
Gain Bandwidth Product
Xtal Frequency

5.0
3.6
4.5
650

10.0
10.0

VN

10.0
1.008 or 4.032

MHz
MHz

230
7.0
1.0

1000

10-4
10-8

%
%

99
99.5
5
7,8

mVrms

150

mVrms

5,9
5, 9

98
99.5

%
%

9

5

0/0

Page 41

I

I

MX469

Transmitter Output
TX Output Level
Output Level Variation
1200/1800Hz or 1200/2400Hz
Output Distortion
3rd Harmonic Distortion
Logic '1' Carrier Frequency 1200 bps
2400 bps

Logic '0' Carrier Frequency

1200 bps
2400 bps

Isochronous Distortion
1200Hz - 1800Hz/1200Hz - 2400Hz
1800Hz - 1200Hz/2400Hz - 1200Hz

Notes

Page 42

1.
2.
3.
4.
5.
6.
7.
8.
9

775
0

6
6

3.0
2.0
1200
1200

6
6

1800
2400

25.0
20.0

mVrms
±1.0
5.0
3.0

dB
0/0
0/0
Hz
Hz
Hz
Hz

40.0
40.0

Ils
IlS

With reference to V DO = 5.0 volts.
Xtal frequency (ref. Clock Rate pin), type and tolerance depends upon system requirements.
See Figure 5 (variation of BER with Input Signal Level).
SNR = Signal-to-Noise in the Bit-Rate Bandwidth.
See Figure 2.
Dependent upon Xtal tolerance.
10101010101 ... 01 pattern.
Measured with a 150mVrms input signal (no noise).
Reference (OdB) level for C.D. probability measurements is 230mVrms.

MX-COM, INC.

MX·~M,IN~.

MX589

Preliminary Information

LOW VOLTAGE, HIGH SPEED GMSK MODEM
4 kbps to 40 kbps
FEATURES

APPLICATIONS

•
•
•
•
•

• PORTABLE WIRELESS DATA

MX·COM MX'D SIGNAL CMOS
FULL- OR HALF-DUPLEX OPERATION
DATA RATES FROM 4KBPS TO 40KBPS
SELECTABLE BT: 0.3 OR 0.5
LOW VOLTAGE OPERATION
3 TO 5.5 V

- CELLULAR DIGITAL PACKET DATA (CDPD)
- MOBITEX· MOBILE DATA SYSTEM

• DATA FOR GPS/DIFFERENTIAL GPS
• WIRELESS BAR CODE READERS
• WIRELESS LANS

• LOW POWER USAGE
• LOW PIN COUNT
• MEETS RCR STD-18 (JAPAN)
MX589J
24 pin CDIP

MX589DW
24 pin SOIC

Description
The MXS89 is a single-chip synchronous Modem
The MXS89 features a mixed signal CMOS process
designed for wireless data applications. Employing that offers considerably lower current drain than DSP
Gaussian Minimum Shift Keying (GMSK) baseband
technology. For data rates up to 20kbps, drain is typically
1.SmA at 3V, and for data rates up to 40kbps at SV, it is
modulation, the MXS89 features a wide range of available
data rates: 4,000 to 40,000 bits per second.
typically 4.0mA.
The data rate and choice of BT (0.3 or O.S) are pinThe MXS89 is available in 24-pin SOIC and CDIP
programmable to provide for different system
packages.
requirements.
TX ENABLE
The TX and RX digital data
TX PS
interfaces are bit serial,
synchronized to TX and RX data
DATA RETIME
TX OUT
TX DATA
&
clocks generated by the modem.
XTAUCLOCK
LEVEL SHIFT
Separate TX and RX Powersave
TX CLK
inputs allow full or half-duplex
operation. RX input levels can be
RX DATA
ClkDIVA
set by a suitable a.c. and d.c. level
ClkDIVB
adjusting circuit built with external
BT
components around an on-chip
RX SIN
RX input amplifier.
Acquisition, lock and hold of
RX data signals is made easier
PLLacq
RX ClK
and faster by the use of RX Control
RXDCacq
Inputs to clamp, detect and/or hold
RX PS
v"
input data levels and can be set by
RX SIGNAL IN
the J.lProcessor as required.
The RX SIN output gives an
RX FEEDBACK
indication of the quality of the
received signal.
Figure 1 - Functional Block Diagram
• MOBITEX is a registered trademark of Swedish Telecom.

MX-COM, INC.

Page 43

I

MX589

I

1

Xtal: The output of the on-chip clock oscillator.

2

XtallClock: The input to the on-chip Xtal oscillator. A Xtal, or externally derived clock (fXTAJ
pulse input should be connected here. If an externally generated clock is to be used, it should be
connected to this pin and the "Xtal" pin left unconnected. Note that operation of the MX589
without a suitable Xtal or clock input may cause device damage.

3
4

ClkDivA:
ClkDivB:

5

RX Hold: A logic "0" applied to this input will 'freeze' the Clock Extraction and level
Measurement circuits unless they are in 'acquire' mode.

6

RXDCacq: A logic "1" applied to this input will set the RX level Measurement circuitry to the
'acquire' mode.

7

Pllacq: A logic "1" applied to this input will set the RX Clock Extraction circuitry to 'acquire'
mode (see Table 2).

8

RX PSAVE: A logic "1" applied to this input will powersave all receive circuits except for RX ClK
output (which will continue at the set bit-rate) and cause the RX Data and RX SIN outputs to go to
a logic "0".

9

V BIAS: The internal circuitry bias line, held at V00/2, this pin must be decoupled to V ss by a
capacitor mounted close to the pin.

10

RX FB: The output of the RX Input AmplifierlThe input to the RX Filter.

These two logic level inputs control the internal clock divider and hence the transmit
and receive data rate. See Table 1.

11

RX Signal In: The input to RX input amplifier.

12

Vss: Negative supply rail. Signal ground.

13
14

Doc1:
Doc2:

15

BT: A logic level to select the modem BT (the ratio of the TX Filter's -3dB frequency to the BitRate). A logic "1" sets the modem to a BT of 0.5, a logic "0" to a BT of 0.3.

16

TX Out: The TX signal output from the MX589 GMSK Modem.

17

TX Enable: A logic "1" applied to this input enables the transmit data path through the TX Filter
to the TX Out pin. A logic "0" will put the TX Out pin to VB1AS via a high impedance.

18

TX PSAVE: A logic "1" applied to this input will powersave all transmit circuits except for the TX
Clock.

19

TX Data: The logic level input for the data to be transmitted. This data should be synchronous
with TX ClK.

20

RX Data: A logic level output carrying the received data, synchronous with RX ClK.

21

RX elK: A logic level clock output at the received data bit-rate.

22

TX ClK: A logic level clock output at the transmit-data rate.

23

RX SIN: A logic level output which may be used as an indication of the quality of the received
signal.

24

Voo: Positive supply rail. A single +5 volt power supply is required. levels and voltages within
this modem are dependent upon this supply. This pin should be decoupled to Vss by a capacitor
mounted close to the pin.

Page 44

Connections to the RX level Measurement Circuitry. A capacitor should be
connected from each pin to Vss.

MX-COM, INC.

MX589

,,,
,

~--------------

R

,,
,

1

,
,: _:

---- -- --,,

, ,,,

e

•

,,!
,

_x'

C2

XTAl

2

24
23

2

,
,:
:

3
4
5
6
7
8

1______ - - - ______________ 1

9
10
11
12

MX589

22
21
20
19

RX elK
RX DATA

I

18
17
16
15
14
13

Component

Value

Tolerance

Component

Value

R,
R2
R3

Note 1
1.0MO
Note 2
100kO
Note 1
Note 5

±5%
±10%
±10%
±10%
±10%

C3
C,
C5
C.
C7
C.

Note 5
O.1J.lF
1.0J.lF
22.0pF
Note 4
Note 4
Note 3

R.
C,
C2

X,

Tolerance
±20%
±20%
±20%

Figure 2 - External Components

Notes
1. The RC network formed by R, and C, is required
between the TX Out pin and the input to the
modulator. This network, which can form part of
any d.c. level shifting and gain adjustment circuitry,
forms an important part of the transmit signal
filtering. The ground connection to the capacitor C,
should be positioned to give maximum attenuation
of high-frequency noise into the modulator.
The component values should be chosen so
that the product of the resistance (Ohms) and the
capacitance (Farads) is:
BT of 0.3 = 0.34/bit rate (bits/second)
BT of 0.5 = 0.22/bit rate (bits/second)
with suitable values for common bit rates being:
BOOO bps
4800 bps
9600 bps
19,200 bps
32,000 bps
32,000 bps
38,400 bps
38,400 bps
MX-COM, INC.

BT
BT
BT
BT
BT
BT
BT
BT

= 0.3
= 0.5
= 0.5
= 0.5
= 0.3
= 0.5
= 0.3
= 0.5

R,

C,

91.0kQ
100kQ
47.0kQ
22.0kQ
47.0kQ
47.0kQ
47.0kQ
47.0kQ

470pF
470pF
470pF
470pF
220pF
150pF
180pF
120pF

Note that in all cases the value of R, should not be
less than 20.0 kQ, and that the calculated value of
C, includes calculated parasitic capacitances.
2. R3, R4 and C6 form the gain components for the RX
Input signal. R3 should be chosen as required by
the signal input level.
3. The MX589 can operate correctly with Xtal/Clock
frequencies between 1.0MHz and 6.5MHz (see
Table 1). Operation of this device without a Xtal or
Clock input may cause device damage.
4. C7 and Cs should both be 15.0nF for a data rate of
Bkbps, and inversely proportional to the data rate
for other data rates, e.g. 30.0nF at 4kbps, 3.0nF at
40kbps.
5. The values chosen for C2 and C3, including strays,
should be suitable for the frequency of X1 and the
supply voltage:
5V C2 = C3= 33pF at 1MHz falling to 18pF at 6.5MHz
3V C2 = C3 = 33pF at 1MHz falling to 18pF at 5MHz
The ESR of X1 should be less than 2kQ at 1 MHz
falling to 150Q at the maximum frequency.
Page 45

MX589

Application Information
--. RX Frequency
Discriminator

I

RX
RX
TX
TX

Data
Clock
Data
Clock

MX589
GMSK MODEM

Figure 3 - External Signal Paths

Clock Oscillator and Dividers
The TX and (nominal) RX data rates are determined
by division of the frequency present at the Xtal pin, which
may be generated by the on-chip Xtal oscillator or
derived from an external source. Any Xtal/clock
frequency in the range 1.0 to 5.0 MHz for V DD=3.0V, or
1.0 to 6.5 MHz for V DD=5.0V may be used, depending on
the desired data rate.
Pin 3

Pin 4

Division Ratio

0
0
1
1

0
1
0
1

128
256
512
1024

The division ratio is controlled by the logic level inputs
on ClkDivA/B (pins 3 & 4), and is shown in the table below
- together with an indication of how various 'standard'
data rates may be derived from common iJP Xtal
frequencies.
Xtal/clock Frequency
Data Rate = - - - - - - - ' - - - - " ' - Division Ratio (Clk DivA/B)

XtaliClock Frequency (MHz)
4.9152
2.048

4.096
32kbps
16 kbps
8 kbps
4 kbps

38.4kbps
19.2 kbps
9.6 kbps
4.8 kbps

2.4576

16 kbps
8 kbps
4 kbps

19.2 kbps
9.6 kbps
4.8 kbps

-

-

Table 1 - XtallClock Frequencies and Corresponding Data Rates
Settings: D/Rate 4800 bps, BT 0.5, RX & TX Enabled
4.9152MHz

~

__~~~----~I Xtal/Clock
Xtal

RXD
Serial [ RXC
I/O Port TXD 1------+1
TXC

I/O Port

I------t~

uControlier

RX
RX
TX
TX

Data
Clock
Data
Clock

TX Enable

+5V

Ck DivA
Ck DivB
BT
RX Hold
. RXSN Det
TX PS
RX PS

PLL Acq
RX DC Acq

MX589 MODEM

Figure 4 - Minimum /lController System Connections
Page 46

MX-COM, INC.

MX589

Application Information ..... .
RX Clock Extraction

I

The 'RX Clock Extraction' circuit is based on a zero
crossing tracking loop which uses a multi mode or
multi resolution digital PLL. The lowest timing resolution
option (Acquire mode) allows for fast initial phase
acquisition. At most 8 zero crossings are required for
initial acquisition. The loop can be programmed to
operate in this mode using the RX Hold and the PLLacq
pins (see Table 2).
The highest timing resolution, which is 1/64 bitperiod, is obtained when the PLL is in its track mode. This
mode of operation yields the least amount of phase jitter,
which is desirable to limit the associated BER
performance degradation. The loop can be set up to
operate in this mode as shown in Table 2.
The loop also has a medium resolution (Le. medium
bandwidth) which is activated only when the MX589
controls are such that the PLL is switching from its
acquire to its track mode. In such cases the medium
setting is used automatically for a limited time (30 bits)
after which the loop goes into its track mode. The
medium bandwidth setting offers a compromise between
fast acquisition and low jitter requirements.
The PLL can also be placed in a HOLD mode, where
the RX Clock phase corrections are completely stopped.
This mode of operation can be selected as shown in
Table 2.

RX DC Level Measurement
The MX589 provides three user-programmable
modes of operation for DC level measurement:
1) Fast Peak Detect - the detectors rapidly capture
the positive and negative going signal peaks
(more susceptible to noise).
2) Averaging Peak Detect - gives a slower but
more accurate measurement of the signal peak
amplitudes.
3) Hold - the outputs of the voltage detectors
remain essentially at the last reading.

circuit. This threshold is adapted from bit to bit to
compensate for intersymbol interference caused by the
bandlimiting of the overall transmission path and the
Gaussian premodulation filter.
Extracted data is output from the 'RX Data' pin, and
should be sampled externally on the rising edge of the
'RX CLK.'

RX Data Formats
The receive section of the MX589 works best with
data which has a reasonably 'random' structure --the
data should contain approximately the same number of
'ones' as 'zeroes' with no long sequences (>100 bits) of
consecutive 'ones' or 'zeroes'. Also, long sequences
(> 100 bits) of '10101010 .. .' patterns should be avoided.
For this reason, it is recommended that data is made
random in some manner before transmission, for example
by 'exciusive-ORing' it with the output of a binary pseudorandom pattern generator.
Where data is transmitted in bursts, each burst should
be preceded by a preamble designed to allow the receive
modem to establish timing and level lock as quickly as
possible. This preamble for BT=0.3 should be at least 16
bits long, and should preferably consist of alternating pairs
of '1 's and 'O's Le. '110011001100 .... .'; the eye of pattern
'10101010 ... .' has the most gradual slope and will yield poor
peak levels for the RX circuits. For BT=0.5 the eye pattern
of '10101010 .. .' has reduced intersymbol interference and
may be used as the preamble (DC Acq pin should be held
high during preamble). See Fig. 10.

RX SIN Detection
The 'RX SIN Detector' system classifies the
incoming zero-crossings as GOOD or BAD depending
upon the time when each crossing actually occurs with
respect to its expected time as determined by the Clock
Extraction PLL. This information is then processed to
provide a logic level output at the 'RX SIN' pin. A high
level indicates a series of GOOD crossings; a low level
indicates a BAD crossing.
By averaging this output it is possible to derive a
measure of the Signal-to-Noise-Ratio and hence the BitError-Rate of the received signal (see Fig. 5).

A fourth "Clamp" mode operates for one bit-time
after a LO to HI transition of the , - - - - - : - : - : - : c : - - , - - - - - , - - - - - - - - - - - - - - - - - - - - - - - - ,
RXDCacq input.
100 ~0 H'19 h Time
l
~~---These modes of operation can be 90
BT~
selected, one at a time, by applying the 80
~
appropriate logic levels to the RX Hold 70
BT = 0.3
j..---and RXDCacq inputs (see Table 2).
60
60

40

30
20

-- --- ---~

+---

---

-

----+----

10

a
6

9

10

11

MX-COM, INC.

MX589
Application Information ..... .
RX Signal Path Description
The
1.
2.
3.

function of the RX circuitry is to:
Set the incoming signal to a usable level.
Clean the signal by filtering.
Provide DC level thresholds for clock and data
extraction.
4. Provide clock timing information for data extraction
and external circuits.
5. Provide RX data in a binary form.
6. Assess signal quality and provide Signal-to-Noise
information.

The output of the radio receiver's Frequency
Discriminator should be fed to the MX589's RX Filter by
a suitable gain and DC level adjusting circuit. This circuit
can be built with external components around the on-chip
RX Input Amplifier. The gain should be set so that the
signal level at the RX Feedback pin is nominally 1V peak
to peak (for Voo =5.0V) centered around VB1AS when
receiving a continuous "1111 00001111 0000.:' data pattern.

Positive going signal excursions at RX Feedback pin
will produce a logic "a" at the RX Data Output. Negative
going excursions will produce a logic "1."
The received signal is fed through the lowpass RX
Filter, which has a -3d8 corner frequency of 0.56 times
the data bit-rate, before being applied to the Level
Measure and Clock and Data extraction blocks.
The Level Measuring block consists of two voltage
detectors, one of which measures the amplitude of the
'positive' parts of the received signal. The other
measures the amplitude of the 'negative' portions.
(Positive refers to signal levels higher than V 00/2, and
negative to levels lower than V 00/2.)
External capacitors are used by these detectors, via
the Doc1 &Doc2 pins, to form voltage 'hold' or 'integrator'
circuits. These two levels are then used to establish the
optimum DC level decision-thresholds for the Clock and
Data extraction, depending upon the RX signal
amplitude and any DC offset.

RX Circuit Control Modes
The RX Circuit blocks are controlled by externally applied logic levels to the PLLacq, RX Hold and RXDCacq pins
(see Table 2). Table 2 shows control signals, the functions they control and their modes of operation.

LO
LO
HI
HI
X
HI
LO
HI
HI

LO
LO
LO
LO
LO to HI
HI
HI
LO
HI

LO
HI
LO
HI
X
HI
LO
HI to LO
LO

Hold
Hold
Averaging Peak Detect
Averaging Peak Detect
Clamp
Fast Peak Detect
Fast Peak Detect
Averaging Peak Detect
Fast Peak Detect mode

Hold
Acquire
Track
Acquire
X
Acquire
Hold
Medium Bandwidth
Track

X=Don't Care

PLL Acquire: Sets the PLL bandwidth wide enough to allow a lock to the received signal in less than 8 zero crossings. The
Acquire mode will operate as long as PLLacq is a logic "1".
PLL Medium Bandwidth: The correction applied to the extracted clock is limited to a maximum of ±1/16th bit-period for
every two received zero-crossings. The PLL operates in this mode for a period of about 30 bits immediately following a "1"
to "0" transition of the PLLacq input, provided that the RX Hold input is a logic "1".
PLL Track Mode (Narrow Bandwidth): The correction applied to the extracted clock is limited to a maximum of ±1/64th
bit-period for every two received zero-crossings. The PLL operates in this mode whenever the RX Hold Input is a logic "1"
and PLLacq has been a logic "0" for at least 30 bit periods (after Medium Bandwidth operation for instance).
PLL Hold: The PLL feedback loop is broken, allowing the RX Clock to freewheel during signal fade periods.
RX Level Measurement Clamp: Operates for one bit-time after a "0" to "1" transition of the RXDCacq input. The external
capacitors are rapidly charged towards a voltage mid-way between the received Signal input level and VBIAS' with the charge
time-constant being of the order of 0.5bit-time.
RX Level Measurement Fast Peak Detect: The voltage detectors act as peak-detectors, one capacitor is used to capture
the 'positive'-going signal peaks of the RX Filter output signal and the other capturing the 'negative'-going peaks. The
detectors operate in this mode whenever the RXDCacq input is at a logic "1," except for the initial 1-bit Clamp-mode time.
RX Level Measurement Averaging Peak Detect: Provides a slower but more accurate measurement of the signal peak
amplitudes.
RX Level Measurement Hold: The capacitor charging circuits are disabled so that the outputs of the voltage detectors
remain substantially at the last readings (discharging very slowly [time-constant approx. 2,000 bits] towards VBIAS )'
Table 2 - RX Circuit Controls

MX-COM, INC.

Page 47

I

MX589
Application Information ..... .
RX Circuit Control Sequence
As shown in Figure 6, a data transmission generally
begins with a preamble of, for example,
"1100110011001100," to allow the receive modem to
establish timing- and level- lock as quickly as possible.
During the time that the preamble is expected, the
RXDCacq and PLLacq inputs should be switched from a
logic "0 to 1" so that the Level Measuring and Clock
Extraction modes are operated and sequenced as
shown.
The RX Hold input should normally be held at a logic
"1" while data is being received, but may be driven to a
logic "0" to freeze the Level Measuring and Clock
PREAMBLE

.' ')::1 :"::" r:.~~%~'~{~:::,
-,'."'

Extraction circuits during a fade. If the fade lasts for less
than 200 bit periods, normal operation can be resumed
by returning the RX Hold input to a logic "1" at the end of
the fade. For longer fades, it may be better to reset the
Level Measuring circuits by placing the RXDCacq to a
logic "1" for 10 to 20 bit periods.
RX Hold has no effect on the Level Measuring
circuits while RXDCacq is at a logic "1," and has no effect
on the PLL while PLLacq is at a logic "1."
A logic "0" on RX Hold does not disable the RX Clock
output, and the RX Data Extraction and SIN Detector
circuits will continue to operate.
DATA

0

~

I

RX Signal
Carrier Det.
(RSSI)

---.-/

----...-J

I

/'~
FAST PEAK
CLAMP
DETECT

...

---------------------------~

AVERAGING
PEAK DET.

.

----...-J

I

ACQUIRE

...

30 bits

~

~

MEDIUM BW

-------------~

NARROW BW

RXDC Acquire
Level Measuring
Circuit Mode

PLL Acq.
Clock Extraction
Circuit Mode

- RX Mode Control Diagram

Figure 6

-1

10

'-.....

-2

10

......

~

-3

10

"'

a::
UJ

!D

10

'""'-

BT

-5

10

= 1.0

"-

'" f\.

\

-4

1"'"

"

MX589 BT

"-

'"~

(lheoretical)'o

MX589 BT

= 0,3

-'"

0.5

10-6

6

5

Figure 7

-

7

8

9

10

11

Typical Bit-Error-Rate Performance

MX-COM, INC.

12

13

14

15

16

17

18

19

20

SIN (dB) (Noise Bandwidth = Bit Rate)

Page 49

I

I

MX589

Application Information ......
TX Signal Path Description
The binary data applied to the 'TX Data' input is
retimed within the chip on each rising edge of the 'TX
Clock' and then converted to a 1-volt peak-to-peak binary
signal centered about V BIAS (for V DD= S.OV)
If the 'TX Enable' input is 'high,' then this internal
binary signal will be connected to the input of the lowpass
TX Filter, and the output of the filter connected to the 'TX
Out' pin.
TX Filter Input

TX Out Pin

1 volt p-p Data In
V BIAS

Filtered Data
VBIAS via SOOkn

TX Enable
'1' (high)
"0" (low)

A 'low' input to the 'TX Enable' will connect the input
of the TX Filter to V BIAS' and disconnect the 'TX Out' pin
from the filter, connecting it instead to V BIAS through a high
resistance (nominally SOOkQ).
The TX Filter has a lowpass frequency response,
which is approximately gaussian in shape as shown in
Figure 9, to minimize amplitude and phase distortion of
the binary signal while providing sufficient attenuation of
the high frequency-components which would otherwise
cause interference into adjacent radio channels. The
actual filter bandwidth to be used in any particular
application will be determined by the overall system
requirements. The attenuation-vs-frequency response
of the transmit filtering provided by the MXS89 have been
designed to meet the specifications for most GMSK
modem systems, having a -3dB bandwidth switchable
between 0.3 and O.S times the data bit-rate (BT).

Note that an external RC network is required
between the 'TX Out' pin and the input to the Frequency
Modulator (see Figures 2 and 3). This network, which can
form part of any d.c. level shifting and gain adjustment
Circuitry, forms an important part of the transmit signal
filtering. The ground connection to capacitor C 1 should be
positioned to give maximum attenuation of highfrequency noise into the modulator.
The component values should be chosen so that the
product of the resistance (Q) and the capacitance
(Farads) is:
BT of 0.3 = 0.34/bit rate (bits/second)
BT of O.S = 0.221bit rate (bits/second)
with the following suitable values for common bit rates:
Data Rate

BT

R

C

8000 bps
4800 bps
9600 bps
19,200 bps
32,000 bps
32,000 bps
38,400 bps
38,400 bps

0.3
0.5
0.5
0.5
0.3
0.5
0.3
0.5

91.0kQ
100kQ
47.0kQ
22.0kQ
47.0kQ
47.0kQ
47.0kQ
47.0kQ

470pF
470pF
470pF
470pF
220pF
150pF
180pF
120pF

The signal at 'TX Out' is centered around V BIAS' going
positive for logic "1" (high) level inputs to the 'TX Data'
input and negative for logic "0" (low) inputs.
When the transmit circuits are put into a 'powersave'
mode (by a logic "1" to the 'TX PS' pin) the output voltage
of the TX Filter will go to V SS. When power is
subsequently restored to the TX Filter, its output will take
several bit-times to settle. The 'TX Enable' input can be
used to prevent these abnormal voltages from appearing
at the 'TX Out' pin.

1 BIT PERIOD
.-----..

TX ClK

~
-.J

----.
'----__t

TX DATA SAMPLED BY
THE MX589 AT THESE
INSTANCES

1

r- 1 ,OIlS Min,

TX CLOCK AND RX CLOCK OUTPUTS
(MARK/SPACE) DUTY CYCLE NOMINAllY 50%.

i.-l,ollS Min,

DON'T CARE

D

TX Data

D

RX Data

RX ClK

DATA MUST
BE VALID

I

1

i.-l.OIlS Max,

~

r-1,OIlS Max,

DATA INVALID

DATA VALID

tr------,L
t

EXTERNAL CIRCUITS SHOUUD
SAMPI F RX DATA AT THIS TIMF

Figure 8 - RX and TX Clock Data Timings
Page 50

MX-COM, INC.

MX589
Application Information ..... .

-10
BT - 0.3

= 0.5

BT

-20

1D

I

-30

~

c

~

-40

-50

..
..

-60

-70

0.01

Frequency/Bitrate

0.1

10

Figure 9 - TX Filter Response

BT = 0.3

BT

= 0.5

Figure 10 - Typical Transmit Eye Patterns

o

~

-10

1ST ~

-20 I---

m

~-so 1--- -

.~ -40
!11

Cl

-50

o

0.51

~~
\ \

...-

1\ \ ( -\

-60

-70

-_ ..

o.sl"", ~IST ~

\ .......
1.0

-.

--

._.-.

-....
~~

~

~

Frequency/Bitrate

2.0

Figure 11 - TX Output Spectrum (Random Data)
MX-COM, INC.

Page 51

I

MX589
Application Information ..... .
Radio Channel Requirements
To achieve legal adjacent channel performance at high bit-rates, a radio with an accurate carrier frequency
and an accurate modulation index is required.
For optimum channel utilization, (eg. low BER and high data-rates) attention must be paid to the phase and
frequency response of both the IF and baseband circuitry.

Bitrate, BT and Bandwidth
The maximum data rate that can be transmitted over a
radio channel depends on the following:
- Channel spacing
- Allowable adjacent channel interference
- TX filter bandwidth
- Peak carrier deviation (Modulation Index)
- TX and RX carrier frequency accuracies
- Modulator and Demodulator linearity
- RX IF filter frequency and phase characteristics
- Use of error correction techniques
- Acceptable error-rate

As a guide to MOBITEX operation, a raw data-rate of
8kbps at 12.5kHz channel spacing may be achievable depending on local regulatory requirements- using a
±2kHz maximum deviation, a BT of 0.3, and no more
than 1.5kHz discrepancy between TX & RX carrier
frequencies.
Forward error correction (FEC) could then be used
with interleaving to reduce the effect of burst errors.
Reducing the data-rate to 4,800bps would allow the
BT to be increased to 0.5, improving the error-rate
performance.
For CDPD operation, a raw data-rate of 19.2kbps at
30kHz channel spacing may be utilized with a ±8kHz
maximum deviation, a BT of 0.5, and no more than 3kHz
discrepancy between TX & RX carrier frequencies.
The above values should be used as a guide only.
Regulatory compliance of a design should be verified.

FM Modulator, Demodulator and IF
For optimum performance, the 'eye' pattern of the
received signal (when receiving random data) applied to
the MX589 should be as close as possible to the Transmit
'eye' pattern examples shown in Figure 11.
Of particular importance are general symmetry,
cleanliness of the zero-crossings, and for a BT of 0.3, the
relative amplitude of the inner eye opening.
To achieve this, attention must be paid to Linearity and frequency/phase response of the
TX frequency modulator. Unless the transmit
data is especially encoded to remove low
frequency components, the modulator
frequency response should extend down to a few
hertz. This is because two-point modulation is
necessary for synthesized radios.

Ideally, the RX demodulator should be d.c. coupled to
the MX589 'RX Signal In' pin (with a d.c. bias added to
center the signal at the RX Feedback pin around VDr/2
[V BIAS] ). However a.c. coupling can be used provided
that:
The 3 dB cut-off frequency is 20Hz or below
(Le. a 0.11tF capacitor in series with 100kQ).
The data does not contain long sequences of
consecutive ones or zeroes.
Sufficient time is allowed after a step change at
the discriminator output (resulting from channel
changing or the appearance of an RF carrier) for
the voltage into the MX589 to settle before the
'RXDCacq' line is strobed.

Bandwidth & phase response of the RX IF filters.
Accuracy of the TX and RX carrier frequencies any difference will shift the received signal
towards one of the skirts of the IF filter response.

Page 52

MX-COM, INC.

MX589
Application Information ..... .
-1

10

~

x -_

-- -

~---

::::::::::-,

(-;,- -"'- ...

----------- ~;;-----

-2

10

~~

- - --

-

-- - --

~ (;,...

~-

10-3
II:

TX and RX DC coupled

I.U

ID

~

TX 5Hz, RX 10Hz

10

I
4

5

-,

..... "'-

,~

- - - 0 - - TX 5Hz, RX 100Hz
-5

,,

,

----------- TX 5Hz, RX 30Hz

10

~

.1
6

I

,

~

- - X - - TX 5Hz, RX DC coupled
-4

-- ........'" ~ - --

7

8

9

10

11

12

13

SIN (dB) (noise in 8kHz bandwidth)

Figure 12 - Typical Bit-Error-Rate Performance for TX and RX D.C. Coupling

A.C. Coupling of TX and RX Signals
Practical applications may require AC coupling from
the MX589's TX Output to the frequency modulator and
between the receiver's frequency discriminator and the
MX589's RX Input. This creates two problems:
1) AC coupling of the signal degrades the Sit Error
Rate (SER) performance of the MX589. Figure 12
(above) shows the typical static SER performance of the
MX589 at 8kbps (without FEC) for different levels of AC
coupling.
2) AC coupling at the RX Input will transform a step
in the voltage at the discriminator output to a slowly
decaying pulse which can confuse the MX589's level

measuring circuits. The time for this step to decay to
37% of its original value is "RC":
RC= ______=-__~~~--~~~--~~
2nothe 3dB cut-off frequency of the RC network
and is 8ms (64 bit-times) at 8kbps for a 20Hz network.

For these reasons, the optimum -3dS cut-off
frequencies are approximately 5.0Hz in the TX path and
20.0Hz in the RX path under the following conditions:
Data Rate = 8kbps
Voo= 5.0V

TX ST = 0.3
TAMB = 25°C

STEP INPUT
TO RC CIRCUIT

OUTPUT OF
RC CIRCUIT

:..
Figure 13 - Time Required for Voltage Step Decay to 37%

MX-COM, INC.

Page 53

I

MX589

Application Information ..... .
Two Point Modulation
When designing the MX589 into a radio that uses a
frequency synthesizer, a two-point modulation technique
is recommended. This is both to prevent the radio's PLL
circuitry from counteracting the modulation process, and
to provide a clean flat modulation response down to d.c.
Figure 14 shows a suggested basic configuration to
provide a two-point modulation drive from the MX589 TX
Output using MX·COM's MX019 Digitally Controlled
'Quad' Amplifier Array. The MX019 elements provide
individual set-up, calibration and dynamic control of
modulation levels. Level setting control of the amplifiers/
attenuators of the MX019 is via an 8-bit data word.
With reference to Figure 14, the buffer amplifier is

required to prevent loading of the MX589 external RC
circuit.
Stage B, with R/R2' provides suitable signal and d.c.
levels for the VCO varactor; C t is RF decoupling. The
drive level should be adjusted (digitally) to provide the
desired deviation.
Stage C, with R/R" provides the Reference Oscillator
drive (application dependent). This parameter is set by
adjusting for minimum a.c. signal on the PLL control
voltage with a low-frequency modulating signal (inside
the PLL bandwidth) applied.
Stage D could be used with the components shown
if a negative reference drive is required. Stage A provides
buffering and overall level control.

MX589 TX OUT

C.

Fig.2
External

v,,

RC
V REF

With reference to the MX019 Data Sheet
Stage A = MX019 Channel 4
Stage B = MX019 Channel 1
Stage C = MX019 Channel 2
Stage D = MX019 Channel 3

t+)

To TX
REF Osc (+)

v"
To TX
REF Osc (-)

Note that ALL stages of the MX019 are 'Inverting' stages

Note: this example has not been verified.

Figure 14 - An Example of Two-Point Modulation Drive with Individual Adjustment Using the MX019

'Acquisition' and 'Hold' Modes
The 'RXDCacq' and 'PLLacq' inputs must be pulsed
'High' for about 16 bits at the start of reception to ensure
that the DC measurement and timing extraction circuits
lock-on to the received signal correctly. Once lock has
been achieved, then the above inputs should be taken
'Low' again.
In most applications, there will be a DC step in the
output voltage from the receiver FM discriminator due to
carrier frequency offsets as channels are changed or
when the distant transmitter is turned on.
The MX589 can tolerate DC offsets in the received
signal of at least ±0.5V with respect to VBIAS' (measured
at the RX Feedback pin). However, to ensure that the DC
offset compensation circuit operates correctly and with
minimum delay, the 'Low' to 'High' transition of the
'RXDCacq' and 'PLLacq' inputs should occur after the
mean input voltage to the MX589 has settled to within
about 0.1 V of its final value. (Note that this can place
restrictions on the value of any series signal coupling
capacitor.)

Page 54

As well as using the 'RX Hold' input to freeze the
Level Measuring and Clock Extraction circuits during a
signal 'fade', it may also be used in systems which use
a continuously transmitting control channel to freeze the
RX circuitry during transmission of a data packet, allowing
reception to resume afterwards without losing bit
synchronization. To achieve this, the MX589 'Xtal' clock
needs to be accurate enough that the derived 'RXClock'
output does not drift by more than about 0.1 bit time from
the actual received data-rate during the time that the
'RXHold' input is 'Low'.
The 'RXDCacq' input, however, may need to be
pulsed 'High' to re-establish the level measurements if
the 'RXHold' input is 'Low' for more that a few hundred
bit-times.
The voltages on the Doc1 and Doc2 pins reflect the
average peak positive and negative excursions of the
(filtered) receive signal, and could therefore be used to
derive a measure of the data signal amplitude.
Note however, that these pins are driven from very highimpedance circuits, so that the DC load presented by any
external circuitry should exceed 10Mn to V BIASMX-COM, INC.

MX589

Specifications
Absolute Maximum Ratings

Operating Characteristics

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(ref Vss=OV)
Sink/Source Current
(supply pins)
(other pins)
Total Device Dissipation
(@ TAMs=25°C)
Derating
Operating Temperature
Storage Temperature

MX-COM, INC.

-0.3 to 7.0V

Voo = 5.0V

-0.3 to (Voo+ 0.3V)
±30mA
±20mA
800mW max.
10 mWrC
-40°C to +85°C
-55°C to +125°C

I

Data Rate = 8000 bps
Xtal/Clock fo = 4.096 MHz
Noise bandwidth = bit rate

Page 55

MX589

Transmit Parameters
TX Output Impedance
TX Output Level
TX Data Delay (BT = 0.3)
(BT = 0.5)
TX PS to Output-Stable Time

I

3
4,11

1.0
1.0

0.8

5

2.0
1.5
4.0

5

6

Receive Parameters
RX Amplifier Input Impedance
Output Impedance
Voltage Gain
RX Filter Signal Input Level
RX Time Delay

kil
V pop

1.2
2.5
2.0

bit-periods
bit-periods
bit-periods

1.0
7
8,11

10.0
50.0
1.0

0.7

Mil
kil
dB
V pop

1.3
3.0

9

bit-periods

On-Chip Xtal Oscillator
R

10.0

IN

12
12

ROUT

Voltage Gain

Mil
kil
dB

50.0
25.0

Notes
1. Not including current drawn from the MX589 pins by external circuitry. See Absolute Maximum Ratings.
2. For Y'N in the range V 55 to V DO.
3 For a load of 10kil or greater. TX PS input at logic "0"; TX Enable = "1".
4. Data pattern of "1111000011110000 .."
5. Measured between the rising edge of 'TX Clock' and the center of the corresponding bit at 'TX Out.'
6. Time between the falling edge of 'TX PS' and the 'Tx Out' voltage stabilising to normal output levels.
7. For a load of 10kil or greater. RX PS input at logic "0".
8. For optimium performance, Measured at the 'RX Feedback' pin for a "1111000011110000 ..." pattern.
9. Measured between the center of bit at 'RX Signal In' and corresponding rising edge of the 'RX Clock'.
10. Timing for an external clock input to the Xtal/clock pin.
11. Typical level shown is at Voo=5.0V; actual levels are proportional to applied VDO.
12. Small signal measurement at 1.0kHz with no load on Xtal output.

r--I

Data

-----I

..

---,
I

I

I
1 ______ ,

1)(

Out, BT=0.5

1)(

Out, BT=0.3

I
I ____________ J

I
1 ______ 1

Figure 15 - Typical Signal Waveforms

Page 56

MX-COM, INC.

MX·~M,IN~.

MX809

Preliminary Information

C·BUS
COMPATIBLE

MSK MODEM
DESCRIPTION
The MX809 is an intelligent, half-duplex 1200 baud MSK Modem which operates under
C-BUS control. This modem provides software selectable checksum generation and
error checking in accordance with MPT1327.

I

In TX Mode the MX809 will:
1. a) Accept from the host and transmit 8-bit bytes of data as instructed (preamble, sync,
address and data).
b) Internally calculate and insert a 2 byte checksum based on the preceding 6 bytes of
data, or

MX809J
24-pin CDIP

c) Disable the internal checksum generator and continuously transmit the data supplied.
2. Transmit 1 hang-bit and go to TX Idle when all loaded data bytes have been
transmitted.
In RX Mode the MX809 will:
1. Detect and carry out bit synchronization within 16 bits.
2. a) Search and detect the user-programmed Sync (or its opposite logic sense) Word
and carry out frame synchronization. Data will then be output in 8-bit bytes via the RX
Data Buffer.

MX809LH
24-pin PLCC

TX OUT

RX IN

AX DATA

READY

REPLY
D

1)(

IDLE

READY

INTERRUPT

C-BUS
INTERFACE

SERIAL
COMMAND
DATA

TX DATA

ENABLE

AND
CONTROL
LOGIC

llllll
INTERRUPT
GENERATOR

I

~
~

ADDRESS
SELECT

Figure 1 - MXB09 1200 Baud MSK Modem
MX-COM, INC.

Page 57

I

MX809
DESCRIPTION ...
b) Use the received checksum to calculate the presence of any errors, setting the Status Register accordingly.
3. Make the incoming data directly available via the RX Data Buffer (RX Freeformat), overriding the synchronization
requirements.
RX input timing is achieved by recovering an RX clock from the incoming data stream. Output tones are timed to the
internally generated TX clock. Filter, register clocks, and transmit MSK tone frequencies are derived internally from the
external Xtal or clock pulse input.
A 4.032 MHz Xtal or clock input is required for compliance with the MPT1327 Signalling Specification. Note: All
information contained in this data bulletin is specified using a 4.032 MHz Xtal, 1200 bps baud rate, with Mark and Space
frequencies of 1200 Hz and 1800 Hz. The MX809 has a non-committed amplifier on-chip for general applications in
the DBS 800 serie. The MX809 is a low-power 5V integrated circuit that incorporates Powersave modes to further
reduce power requirements. It is available in 24-pin Cerdip and 24-lead SMT Packages.

PIN FUNCTION CHART

Xtal: This is the output of the on-chip clock oscillator. External components are required at this input
when a Xtal input is used. See Figure 2, Inset.
2

Xtal/Clock: This is the input to the on-chip clock oscillator inverter. A Xtal or externally derived clock
should be connected here. See Figure 2, Inset.

3

Interrupt Request (IRQ): The output of this pin indicates an interrupt condition to the microcontroller
by going to a logic "0." This is a "wire-or able" output that enables the connection of up to 8 peripherals
to 1 interrupt port on the microcontroller. This pin is an open-drain output, and therefore has a low
impedance pulldown to logic "0" when active and a high impedance when inactive. The conditions
that cause interrupts are indicated in the Status Register and are shown below:
TX Idle
RX SYNC Detect

RX Data Ready

TX Data Ready
RX SYNC Detect

Interrupt outputs can be disabled by bit 3 of the Control Register.

4

5

N/C
N/C

6

RX Freeformat: When this input is logic "0" in the RX Mode, it allows received data to be read from
the RX Data Buffer via the Reply Data line without having to achieve byte synchronization (SYNCI
SYNC) first. Data will continue to be available after this input goes to a logic "1" until either a SYNC
or SYNC Prime Bit is set or the modem is set to TX Mode. When held at a logic "1" the modem
operates normally. This pin has an internal 1Mil pullup resistor.
Note: If this input is held at a logic "0" in the TX Mode, the RX Data Ready bit in the Status
Register may occasionally be set, but not cause an interrupt. If this input is a logic "0" when
going into the RX Mode, an RX Data Ready interrupt may be generated immediately (in this
case the first byte of RX data should be ignored).

7

VBIAS: The internal circuitry bias line, this is held at VDrl2. This pin must be decoupled to V88 by
capacitor Cs. See Figure 2.

8

Amp In: The inverting input to the on-chip uncommitted amplifier.

9

Amp Out: The output of the on-chip uncommitted amplifier.

10

RX In: This is the 1200 baud, 1200Hz/1800Hz received MSK signal input. The input signal to this
pin must be a.c. coupled via capacitor C 4 . See Figure 2.

Page 58

MX-COM, INC.

MX809
PIN FUNCTION CHART

11

N/C

12

Vss: Negative Suply (GND).

13

TX Out: This is the 1200 baud, 1200Hz/1800Hz MSK TX output. When not transmitting data the
output impedance of this pin is high. On power-up this output can be any level. A General Reset
command is required to ensure that this output attains VB1AS initially.

14

N/C

15

N/C

16

N/C

17

Reply Data: This is the C-BUS serial data output to the microcontroller. The transmission of Reply
Data bytes is synchronized to the Serial Clock under the control of the Chip Select input. This 3-state
output is held at high impedance when not sending data to the microcontroller. See Timing Diagrams.

18

N/C

19

Chip Select (CS): The C-BUS data loading control function, this inpu@providedbythemicrocontroller.
Data transfer sequences are initiated, completed or aborted by the CS signal. See Timing Diagrams.

20

Command Data: This is the C-BUS serial data input from the microcontroller. Data is loaded to this
device in 8-bit bytes, MSB (bit7) first, and LSB (bit 0) last, synchronized to the Serial Clock. See Timing
Diagrams.

21

Serial Clock: This is the C-BUS serial clock input. This clock, produced by the microcontroller, is
used for transfer timing of commands and data to and from the MSK Modem. See Timing Diagrams.

22

Address Select: This pin enables two MX809s to be used on the same C-BUS, providing full-duplex
operation. When at a logic "1" Address/Command bytes (with the exception of a General Reset) must
have bit 3 set to a logic "1" to address this device. See Tables 1 and 2.

23

Wake: This input can be used to reactivate the MX809 from Powersave. The device will be in
Powersave when both this pin and bit 2 of the Control Register are set to a logic "1." Recovery from
Powersave is achieved by putting either the Wake pin or the Powersave bit in the Control Register
to logic "0." This allows MX809 activation by the microcontroller or an external signal, such as R.S.S.1.
or Carrier Detect.

o
1
o
24

1

o
o

Enabled
Enabled
Enabled

Voo: Positive supply. A single +5V power supply is required. Levels and voltages within the MSK
Modem are dependent upon this supply.

Note: Pins 4, 5, 11, 14, 15, 16 and 18 may be connected to Vss to improve screening.

MX-COM, INC.

Page 59

I

MX809

External Components
Voo

SEE INSET

I

2
3
4
5
RX FREEFORMAT
6
7
8
9
10
---lC4
11
v".
12

car
r

20

MX809J

19
18
17
16
15
14
13

v

,*,06

WI>J 5.0MHz.

5.

External capacitors Cs and C7 form part of the
received signal level measuring circuit; the
values of Cs and C7 should satisfy the
following: C (F) x Data Rate (bps) = 120 x 10·s.

If the on-chip Xtal oscillator is to be used, then
the external components Xl' Cs' C4 , and Rs are
required as shown in Figure 2 (inset).
If an external clock source is to be used these
components are not required; the input should
be connected to the Xtal/clock pin and the Xtal
pin left unconnected.
Table 4 (Clock/Data Rates) provides advice on
the selection of the correct Xtal value.

DlRate(kbls) C/C7(JJF) DlRate(kbps) C/C(IIF)
4
.030
4.8
.022
8.0
.015
9.6
.012
19.2
.0068
16.0
.0068

External Signal Paths
The diagram below shows signal connections to and from the MX909. Inputs and outputs are shown with DC
coupling and level-shifting components; the notes and diagrams on the following page (Figures 5 and 6) describe
how, if acceptable, AC coupling may be used (see notes on the following page).

RX FREQUENCY
DISCRIMINATOR

h

t

r

RX IN

=t>-y CIR~~ITS I I

Do - D7

An - A,

cs

-

-

AD

WR
IRQ

TX
CIRCUITS

I

TX OUT

Do - D7
Ao - A1

cs

AD

WR
IRQ

MODULATOR

i

I

RX FEEDBACK

~CONTROLLER

TX FREQUENCY

I

SIGNAL AND
DC LEVEL
ADJUSTMENT

MX909 GMSK Modem

SIGNAL AND
DC LEVEL
ADJUSTMENT

i

I

1

Figure 3 - External Signal Paths

Figure 4 - Example Transmit EYE Diagram (after the external RC network)
Page 74

MX-COM, INC.

MX909
Installation Information ..... .
AC Coupling
For a practical application, AC coupling from the modem's transmit output to the Frequency Modulator and from
the receiver's Frequency Discriminator to the receive input of the modem may be desired. There are, however,
two problems.
1) AC coupling of the signal degrades the bit-error-rate performance of the modem. Figure 5 illustrates the
typical bit error rates at Bkbps (without FEC) for differing degrees of AC coupling.
~.

x
,'~

----

----

-------~~,

~ .f..-.....
~

"'

~ (....

"""'-......

TX 5Hz, RX DC coupled

"

TX 5Hz, RX 10Hz

1==

~
~ -

4

.......

TX and RX DC coupled

~
r-- -------®-----r--

r-r--r--

----

..... ....

~'

E
1=

I

~~

-

-

TX 5Hz, RX 30Hz

------D--- TX 5Hz, RX 100Hz

5

6

......

,

'",...... ..........

10
11
12
8
9
SIGNAL-TO-NOISE RATIO (dB) (noise in 8kHz bandwidth)

7

"

13

Figure 5 - Examples of BER Performance Degradation Due to Varying Degrees of AC Coupling
2) Any AC coupling at the receive input will transform any step in the voltage at the discriminator output
to a slowly decaying pulse which can confuse the modem's level measuring circuits. As illustrated below,
the time for this voltage step to decay to 37% of its original value is:
1

T = --(2fI x f)

Where f is the 3dB cut-off frequency of the AC coupling network and is B ms (or 64 bit-times at B kbps)
for a 20Hz network.
For these reasons the maximum -3dB cut-off frequencies would seem to be around 5Hz in the TX path
and 20Hz in receive at 8 kbps.

Step Input
to RC Circuit

I

~

Output of
RC Circuit

Figure 6 - Decay Problems of the AC Coupling Network
MX-COM, INC.

Page 75

I

MX909
Installation Information ..... .
Radio Performance
The maximum data rate that can be transmitted over a radio channel using this modem depends on:
•
•

RF channel spacing.
. Allowable adjacent channel interference.

•

Bit rate.

•

Peak carrier deviation (modulation index).

•

TX and RX reference oscillator accuracies.

•

Modulator and demodulator linearity.

•

Receiver IF filter frequency and phase characteristics.

•

Use of error correction techniques.

•

Acceptable error rate.

As a guide, 8 kbps can be achieved - subject to local regulatory requirements - over a system with 12.5kHz
channel spacing if the transmitter frequency deviation is set to ± 2kHz peak for a repetitive' 1100... ' pattern and
the maximum difference between transmitter and receiver 'carrier' frequencies is less than 1500Hz.
The modulation scheme employed by this modem is designed to achieve high data throughput by exploiting
as much as possible of the RF channel bandwidth. This does, however, place constraints on the performance
of the radio.
In particular, attention must be paid to:
•

Linearity, frequency and phase response of the TX Frequency Modulator.

•

The bandwidth and phase response of the receiver's IF filters.

•

Accuracy of the TX and RX reference oscillators, as any difference will shift the receiVed signal towards
the skirts of the IF filter response and cause a DC offset at the discriminator output.

Viewing the received signal eye (at the MX909 RX Feedback pin) gives a good indication of the overall
transmitter/receiver performance.

Modem to IJControlier Interface
The Data Bus Buffers and Address and ReadlWrite Decode blocks form a byte-wide parallel IJControlier
interface. This diagram shows how this function can be memory mapped.

Do
D,
D2
D3
D,
D5
D,
D7
-

WR
RD

••
•••
••
•

~

~

I~O~~

Do
D,
D2
D3
D,
D5
D,
D7

~
~
~
~
~
~

~+5Vo1ts

I!CONTROLLER

iRa

line
pullup resistor

IRQ

WR
RD
I

t!--

•

Ao

~

A,

~

:

ii,

~

~c

Address Bus

MX909
MODEM

IRQ
other IRQ Inputs
to IlControlier

Ao
A,

~-~~~~~i
: i Address ~ cs
~:__ ~~~O_d~__ j

Figure 7 - Typical Modem to JlController Interface
Page 76

MX-COM, INC.

MX909
Installation Information ..... .
Baseband and RF Frequency Requirements
= 1.0 V RMS

OdS

10

50

:s.
-'

UJ

>

UJ

-'

100

150
5.0

10.0

15.0

20.0
FREQUENCY (kHz)

Figure 8 - Typical TX Out Frequency Spectrum for a Random Data Input

RF Channel Occupancy
The diagram below shows the theoretical RF bandwidth requirements when interfacing the MX909 baseband
(TX OUT) signal (Figure 8, above) to a radio transmitter. This plot assumes a perfect frequency modulator.

o

10 -20

Unmodulated Carrier Level

.+ . . . . ._............__ . . . . . . . . . . . . . . _. . . . . . . . . . . . . . . . . . . . . . .

:s.
-'

~

UJ

-' -40

.+ . . . . .-.............
Mobitex Settings
Data Rate = Bkb/s
Deviation =

2.0kHz

-80

Ie -20

Ie -10

Ie

Ie

+10

Ie

+20

FREQUENCY (kHz)

Figure 9 - Theoretical TX RF Frequency Spectrum Resulting from a Random Data Input to the MX909

MX-COM, INC.

Page 77

MX909

Programming Information
Data Formats
Mobitex Frame and Data Structures
The Mobitex format for transmitted data is in the form of a Frame Head immediately followed by a number of
Data Blocks (0 to 32).
The Frame Head consists of 7 bytes ..... .
2 bytes of Bit Sync:
1100 1 10 0 1100 1100
0 1100 11 00 1 100 11
(sent L to R).
2 bytes of Frame Sync:
System specific.

o

- from base, or
- from mobile

2 bytes of Control Data:
- System specific 10 and control information.
1 byte of FEC Code (generated by the MX909):
- 4 bits for each of the control bytes:
- bits 7 - 4 operate on the first control byte.
- bits 3 - 0 operate on the second control
byte.
Each byte in the Frame Head is transmitted bit 7
(MSB) first, bit 0 (LSB) last.

The Data Block consists of ..... .
18 bytes of Data:
2 bytes of CRC are calculated by the MX909
from the 18 Data Bytes.
4 bits of FEC code are calculated for each of the
Data and CRC bytes
The resulting 240 bits are interleaved and scrambled
before transmission; see Figure 22, (Interleaving).
Figure 10 shows how the over-air signal is built up
from Frame Sync and Bit Sync patterns, Control Bytes
and Data Blocks.
The binary data transferred between the modem
and the controlling jJControlier is that shown enclosed
in the heavily outlined rectangles.

Frame Head

Data Block

Msa

LSB

!.!.l 6..! I 4. . .3 I ; . . 1 l~
loaded first -Byte 0
Bit Sync 1

I

Byte 1

Byte 2

loaded first -Byte 0

Frame Sync 1

Byte 3

I----,F~'a:::.m.c:e-:s:.:Y'-nc'-::-2--1
LI_

_:c~o-nt:-'o_:_'-=Byt:.,e---::'--I

Byte 5

Byte 4
Byte 6

-

NOTE

-

The binary data

I tran~:;:~ ':.:~~~

i

LSB

t

-;"3 \~ 1 ~ 3

Byte 4

i=

Control Byte 2

FEe,

"'T

FEc2

-I

2

,

0

::r:
+

:;.: ~ t

Bit Sync 2

I

Byte 3

loaded last -Byte 5

- -

Msa

"::t 6.i!

Oata
(18 bytes)

:t:
-I-

F

T
I

....

the I

+

I :~t~I~~~:~~~I::r i~ I
I ~ d~ed ,::tan~s I

~

.... 1 +1

CRC

(2 bytes)

=-L
INTERLEAVING/DE-INTERLEAVING

SCRAMBLE/DE-SCRAMBLE

OVER-AIR
SIGNAL
BITS

BL~~~S

--------~

1 - - - - ! - - - I - - - ' - - - - - 1 - - - - - - - - - - . . : . - - - - -- - - _.---.-1

'1'6

:

FRAME
'6
HEAD

24

I

DATA BLOCKS
(0 TO 32)

~~

~

FRAME

Figure 10 - MX909 Mobitex System Data Format
Page 78

MX-COM, INC.

MX909
Programming Information ..... .
ModemlJ.lControlier Interaction
In general, data is transmitted over-air in the form of
messages, or 'Frames', consisting of a 'Frame Head'
optionally followed by one or more formatted Data Blocks.
The Frame Head includes a Frame Synchronization
pattern designed to allow the receiving modem to identify
the start of a frame. The following data blocks are
constructed from the 'raw' data using a combination of
CRC (cyclic redundancy checksum) generation, Forward
Error Correction (FEC) coding, Interleaving and
Scrambling.
To reduce the processing load on the host fJController,
the MX909 has been designed to perform as much as
possible of the computationally intensive work involved in
Frame formatting and de-formatting and, when in receive
mode, in searching for and synchronizing onto the Frame
Head.
In normal operation the modem will only require

servicing by the fJController once per received or
transmitted data block. Thus, to transmit a block, the
controlling fJController has only to load the unformatted
(raw) binary data into the modem's data buffer then
instruct the modem to format and transmit that data. The
modem will then calculate and add the CRC bits as
required, encode the result with FEC coding, interleave
then scramble the bits before transmission.
In receive mode, the MX909 modem can be instructed
to assemble a block's worth of received bits, de-scramble
and de-interleave the bits, check and correct (using the
FEC coding) and check the resulting CRC before plaCing
the received binary data into the Data Buffer for the
fJController to read. The MX909 modem can also handle
the transmission and reception of un-formatted data; to
allow for example, the transmission of special Bit and
Frame Synchronization sequences or test patterns.

Register Selection
The MX909 modem appears to the programmer as 4 write-only 8-bit registers shadowed by 3 read-only
registers. Individual registers are selected by the Al and Ao inputs; see Read and Write cycle timing diagrams
(Figure 24).

Table 1 - Register Selection

o
o
1

o
1
o

1

1

Write to Modem

Read from .Modem

Data Buffer
Command Register
Control Register
Mode Register

Data Buffer
Status Flegister
00 Register
not used

Data Buffer
An 18-byte read/write buffer which is used to transfer data (as opposed to Command, Status, Mode,
Data-Quality and Control information) between the modem and the controlling fJController.
The Data Buffer appears to the IJController as a single 8-bit register; the modem ensures that sequential
fJController 'read' or 'write' actions to the buffer are routed to the correct locations within this buffer.
The IJController should only access this buffer when the Status Register BFREE (Buffer Free) bit is at a logic
'1'. The buffer should only be written to while in the TX mode and read from in the RX mode (except when loading
Frame Sync detection bytes in the RX mode). See Figure 24 for data ReadlWrite Timing information.

Command Register
Writing to this register instructs the modem to perform a specific action or actions, depending upon the setting
of the TASK, AQLEV, and AQBC bits (see Figure 11/Table 1).
r-~~~~~~~~~--~~~----~----~~~~~

¢*tn.fn~d'Fieg,ister

Figure 11 - The Command
Register

{1f;
.(;,•.',:,r,: .~:"

.1.

.'

t,\.y. t.r.IJI .(}rI. . .

I

.' Aq~{:~~'i~R$$$,
•. ~r~
~

<,;.; .. '"

When it has no action to perform (but is not powersaved), the modem will be in an idle state, and if it is in the
TX mode the input to the TX (Lowpass) Filter will be connected to V S1AS '
When it has no action to perform in the RX mode the modem will continue to measure the received data quality
and extract bits from the received signal, feeding them into the De-Interleave Buffer, but will otherwise ignore
the received data.

MX-COM, INC.

Page 79

I

MX909
Programming Information ..... .

Acquire Bit Clock: This bit has no effect in the TX mode.
In the RX mode, whenever a byte with the AQBC bit set to logic '1' is written to the Command
Register, it initiates an automatic sequence designed to achieve bit-timing synchronization with
the received signal as quickly as possible. This involves setting the Phase Locked Loop of the
received bit-timing extraction circuits to their widest bandwidth, then gradually reducing the
bandwidth as timing synchronization is achieved, until it reaches the 'normal' value set by the
PLLBW bits of the Control Register.
Setting this bitto logic '0' (or changing itfrom '1' to '0') has no effect. Note that the acquisition
sequence will be re-started every time that a byte written to the Command Register has the
AQBC bit set to logic '1'.
The AQBC bit will normally be set at the same time as an SFS (Search for Frame Sync) or
SFH (Search for Frame Head) task, however it may also be used independently to re-establish
clock synchronization quickly after a long fade. Alternatively, an SFS or SFH task may be
written to the Command Register with the AQBC bit at logic '0' if it is known that clock
synchronization does not need to be re-established.
More details of the Bit Clock Extraction Sequence are given in the Operational Information
section of this Data Sheet
Acquire Receive Signal Levels: This bit has no effect in the TX mode.
In receive mode, whenever a byte with the AQLEV bit set to a logic '1' is written to the Command
Register, it initiates an automatic sequence designed to measure the amplitude and DC offset of
the received signal as rapidly as possible. This sequence involves setting the measurement circuits
to respond quickly at first, then gradually increasing their response time -improving the
measurement accuracy- until the 'normal' value set by the LEVRES bits of the Control Register is
reached. See Figure 12.
Setting this bit to a logic '0' (or changing it from '1' to '0') has no effect; note that the acquisition
sequence will be re-started every time that a byte written to the Command Register has the AQLEV
bit set to a logic '1'.
The AQLEV bit will normally be set at the same time as an SFS (Search for Frame Sync) or SFH
(Search for Frame Head) task is initiated, however it may also be used independently to re-establish
Signal levels quickly after a long fade. Alternatively, a SFS or SFH task may be written to the
Command Register with the AQLEV bit at logic '0' if it is known that there is no need to re-establish
the received signal levels. Refer to the Clock Extraction (Operational Information section) notes.

These bits should each be set to a logic '0'.

Task: Operations such as transmitting a data block are treated by the modem as 'tasks'.
Information on Task functions is given on the following pages. A task is initiated when the
~Controller writes a byte to the Command Register with the Task bits set to anything other than the
'NULL' ('0' '0' '0') code.
The ~Controller should not write a task (other than NULL or RESET) to the Command Register
or write to or read from the Data Buffer if the BFREE (Buffer Free) bit of the Status Register is a
logic '0'.
Different tasks apply in receive and transmit modes.
TX Mode: All tasks other than NULL, RESET and TSO instruct the modem to transmit data from
the Data Buffer, formatting it as required. For these tasks the ~Controller should wait until the
BFREE (Buffer Free) bit of the Status Register is a logic '1 " before writing the data to the Data Buffer,
then it should write the desired task to the Command Register. If more than 1 byte needs to be
written to the Data Buffer, byte number '0' of the block should be written first.
Once the byte containing the desired task has been written to the Command Register, the
modem will: Set the BFREE (Buffer Free) bit of the Status Register to a logic '0', take the data from
the Data Buffer as quickly as it can -transferring it to the Interleave Buffer for eventual transmission;

Page 80

MX-COM, INC.

MX909
Programming Information ..... .
Command Register ......

82
81

80
TASK ......

Task: ...... This operation will start immediately if the modem is 'idle' (Le. not transmitting data from
a previous task), otherwise it will be delayed until there is sufficient room in the Interleave Buffer.
Once all of the data has been transferred from the Data Buffer the modem will set the BFREE and
IRQ bits of the Status Register to a logic '1 " (causing the IRQ output to go low if the IRQEN bit of
the Mode Register has been set to a logic '1 ') to tell the I-lControlier that it may write new data and
the next task to the modem.
In this way the I-lControlier can write a task -and the associated data- to the modem while the
modem is still transmitting the data from the previous task.
RX Mode: The I-lControlier should wait until the BFREE bit of the Status Register is a logic
'1 " then write the desired task to the Command Register. Once the byte containing the desired
task has been written to the Command Register, the modem will:
Set the BFREE bit of the Status Register to a logic '0'.
Wait until enough received bits are in the De-Interleave Buffer.
Decode them as needed, and transfer any resulting data to the Data Buffer.
Then the modem will setthe BFREE and IRQ bits of the Status Registerto logic '1 " (causing
the IRQ output to go low if the IRQEN bit of the Mode Register has been set to a logic '1 ') to
tell the I-lControlier that it may read from the Data Buffer and write the next task to the modem.
If more than 1 byte is contained in the Data Buffer, byte number '0' of the data will be read first.
In this way the IJControlier can read data and write a new task to the modem while the
received bits needed for this new task are being stored in the De-Interleave Buffer. The above
is not true for loading the Frame Sync detection bytes (LFSB); the bytes to be compared with
the incoming data must be loaded prior to the task bits being written. Detailed timings for the
various tasks are given in later sections.

Rx In

= I for Task 1

for Task 2

IRQ Output
(IRQEN = '1')
Status Register IRQ Bit
Status Register BFREE Bit

~
~ Task 1

Task from I1C to Command Register

.j Task 2
_

Data from Data Buffer to mC

Task 1 data

Figure 12 - The Receive Process
Data from I1C to Data Buffer

_

Task 1 data

_

Task 2 data

Task and/or Commands from I1C
to Command Register
Status Register BFREE Bit

'----!!

Status Register IRQ Bit

J

IRQ Output
(IRQEN = '1')

~

Tx Out

Figure 13 - The Transmit Process

MX-COM, INC.

=======:1=f=ro=m==Ta=s=k=1================fro=m=~"=as=k=2=====
Page 81

I

MX909
Programming Information ......
Modem Tasks in Detail
The following describes the setting and format of the Command Register 'task' bits (bits 2, 1 and O). Note
that before a task is programmed the TXlRX bit in the Mode Register must be set to the required level.

o
o
o
o

0
0 NULL
0
1
SFH
Search for Frame Head
1
0
R3H
Read 3 Byte Frame Head
1
1
RDB
Read Data Block
0
0
SFS
Search for Frame-Sync
1
0
1
RSB
Read Single Byte
1
0 LFSB
Load Frame-Sync Bytes
1
1
1
1
1 RESET
Cancel any Current Action
Table 2 Modem Task Allocations

NULL
T7H
Reserved

TDB
TQB
TSB
TSO
RESET

Transmit 7 Byte Frame Head
Transmit Data Block
Transmit 4 Bytes
Transmit Single Byte
Transmit Scrambler Output
Cancel any Current Action

No Effect. This task is provided so that an AQBC or AQLEV (Command Register) command can
be initiated without loading a new task.
Search for Frame Head. Causes the modem to search the received signal for a valid Mobitex
Frame Head. The Frame Head will consist of a 16-bit Frame Sync followed by control data which
has no uncorrectable errors (see Figure 10, Data Format). The search will continue until a valid
Frame Head has been found, or until the RESET task is loaded. The search is carried out by the
modem in 3 stages:
1 Attempt to match the incoming bits against the previously programmed (task LFSB) 16-bit
Frame Sync pattem (allowing up to anyone bit (of 16) in error}.
2 When a match has been found, the modem will read the next 3 received bytes as Frame
Head bytes; these bytes will be checked using the FEC bits. If the FEC indicates
uncorrectable errors (Status Register) the modem will resume the search, looking for a new
Frame Sync pattern.
3 If the received bytes are error free or correctable, BFREE and IRQ bits (Status Register)
are set to a logic '1' and the CRCFEC bit set to a logic '0'; the two corrected (by the modem)
Frame Head Control Data bytes are then placed into the Data Buffer.
The MOBAN bit (Mobile or Base) in the Status Register will be set according to the polarity
of the 3 bits that preceded the Frame Sync pattern.
On detecting that the BFREE bit ofthe Status Register has gone to a logic '1', the )JControlier should
read the 2 Frame Head control data bytes from the Data Buffer and then write the next task to the
modem's Command Register.
Read 3 Byte Frame Head. This task, which would normally follow an SFS task, will cause the
modem to place the next 3 bytes directly into the Data Buffer and, concurrently, check those 3 bytes
as Frame Head Control Data bytes; the modem will set the CRCFEC bit to a logic '1' (high) if errors
are detected. Note: This task will not correct any errors. The BFREE and IRQ bits of the Status
Register will be set to a logic '1' when the task is complete; this is to indicate that the )JControlier
may read the data from the Data Buffer and write the next task to the Command Register. The
CRCFEC bit in the Status Register will be set according to the validity of the received FEC bits.
Read Data Block. Causes the modem to read the next 240 bits (see Data Formats -Mobitex Frame
and Data Structures) as a Mobitex data block. This task will de-scramble and de-interleave the
received bits, FEC correct and CRC check the resulting 18 data bytes placing them in the Data
Buffer. When the task is complete the BFREE and IRQ bits of the Status Register are set to a logic
'1' to indicate that the )JController may read the data from the Data Buffer and write the next task
to the Command Register. The CRCFEC bit in the Status Register will be set according to the
outcome of the CRC check. Note that in the receive mode the checksum circuits are initialized
(ready for operation) on completion of any task other than NULL.

Page 82

MX-COM, INC.

MX909
Programming Information ..... .
Modem Tasks ......
SFS

Search for Frame Sync. Intended for special test and monitoring purposes, this task performs
the first part only of an SFH task. It causes the modem to search the received signal for a 16bit sequence which matches the previously programmed Frame Sync pattern (allowing up to
anyone bit (in 16) in error). When a match is found the modem will set the BFREE and IRQ
bits of the Status Register to a logic '1' and update the MOBAN bit. The jJController may then
write the next task to the Command Register.

RSB

Read Single Byte. This task, which is intended for special tests and channel monitoring perhaps preceded by an SFS task, causes the modem to read the next 8 bits and translate them
directly (without de-interleaving or FEC) to an 8-bit byte which is placed into the Data Buffer
(B7 will represent the earliest bit received). The BFREE and IRQ bits of the Status Register
will then be set to a logic '1' to indicate that the jJController may read the data byte from the Data
Buffer and write the next task to the Command Register.

LFSB

Load Frame Sync Bytes. This task is unlike other RX tasks in that the Data Buffer must be
loaded (with the 2 Frame Sync bytes) before the task is issued and the task must only be issued
'between' received messages; i.e. before the first task for receiving a message and after the
last data is read out of the Data Buffer. It takes 2 bytes from the Data Buffer and loads them
into the MX909's internal Frame Sync pattern store. The MSB of byte 0 represents the first bit
of a received Frame Sync pattem and the LSB of byte 1 is compared to the last bit of a received
Frame Sync pattem that will be looked for when a SFS or SFH task is executing. The LFSB
task itself does not initiate a search for a received Frame Sync pattern.
Once the modem has read the Frame Sync bytes from the Data Buffer, the BFREE and IRQ
bits of the Status Register will be set to a logic '1', indicating that the jJControlier may write the
next task to the modem.

T7H

Transmit 7-Byte Frame Head. Takes 6 bytes of data from the Data Buffer, calculates and
appends 8 bits of FEC from bytes 4 and 5 then transmits the result as a complete Mobitex
Frame Head. Bytes 0 and 1 form the bit -sync pattern, bytes 2 and 3 form the frame-sync pattern
and bytes 4 and 5 are the Frame Head control bytes. Bit 7 of byte 0 of the Data Buffer is sent
first and bit 0 of the FEC byte last.
Once the modem has read the data bytes from the Data Buffer, the BFREE and IRQ bits of
the Status Register will be set to a logic '1', indicating that the jJController may write the next
task and its data to the modem.

TQB

Transmit 4 Bytes. Takes 4 bytes of data from the Data Buffer and transmits them, bit 7 of byte
o first, bit 0 of byte 3 last.
Once the modem has read the data bytes from the Data Buffer, the BFREE and IRQ bits of
the Status Register will be set to a logic '1', indicating that the jJControlier may write the next
task and its data to the modem.

TDB

Transmit Data Block. Takes 18 bytes of data from the Data Buffer, calculates and applies a
16-bit CRC and forms the FEC for the 18 data bytes and the CRC; the resulting 240 bits are
then interleaved and passed through the scrambler, if enabled, before being transmitted as a
Mobitex Data Block. Note that in transmit mode the CRC checksum circuit is initialized on
completion of any task other than NULL.
Once the modem has read the data bytes from the Data Buffer, the BFREE and IRQ bits of
the Status Register will be set to a logic '1', indicating that the jJController may write the next
task data to the modem.

TSO

MX-COM, INC.

Transmit Scrambler Output. Intended for channel set-up, this task enables the scrambler
and transmits its output (which will be 9-bit pseudo-random). When the modem has started this
task the Status Register bits will not be changed and hence an IRQ will not be raised. The
jJControlier may write data and the next task to the modem at any time and the scrambler output
will stop when the new task has produced its first data. See Mode Register SCREN.

Page 83

I

MX909
Programming Information ..... .

Stop any Current Action. This 'task' takes effect immediately, and terminates any current
action (Task, AQBC or AQLEV) the modem may be performing and sets the BFREE bit of the
Status Register to a logic '1', without setting the IRQ bit. RESET should be used when VDD
is applied to set the modem into a known state. Note that due to delays in the TX Lowpass
Filter filter, it will take approximately 2 bit-times for any change to become apparent at the TX
Out pin.
Transmit Single Byte. Takes a byte from the Data Buffer and transmits the 8 bits, bit 7
first. Once the modem has read the data byte from the Data Buffer, the BFREE and IRQ
bits of the Status Register will be set to a logic '1', indicating to the IJControlier that it may
write the next task and its data to the modem.

I

Lowpass Filter Delay
The Task Timing figures detailed in Table 2 are based upon: the signal at the input to the TX lowpass Filter
in the transmit mode, or the signal at the input to the de-interleave circuits in the receive mode. As can be
seen from the diagram in Figure 14, there is an additional delay of approximately 2 (two) bit-times in both TX
and RX modes due to the (TXlRX) Lowpass Filter.

Page 84

MX-COM, INC.

MX909
Programming Information ..... .
Transmit and Receive Task Timing

OJ

Data to Data Buffer
Task to Command Register
IBEMPTY

B~

BFREE Bit

!
!

[gJ

I

[]

12

1

,

'(

t.

t.

i(

)i,.

i:

13

)i

'(

>'

I

!

~I--~--~I--~--~-------

i

, t2 :

!;t2J
t2:
,
t ~;(~ t3
....------.- t3
~ t3
'
1
;(:(-----------?)~:(~--------~)~:(~--------~):
Bits to Tx Lowpass Fmer----{=Jf~ro~m~li~a~sk~1C=r=Jf~ro~m~li~as~kJ2C:::J==f~ro~m~li~a~sk~3C:::J1-Modem Tx Output

Figure 15 - TX Task Timing Diagram
Modem Rx Input
Bits to De-Interleave Circuit----l

for Task 1
t3

;(

I

for Task 2

)~(

BFREE Bit

for Task 3
t3

ITl

Data from Data Buffer
Task to Command Register

I

)i(

t3

: la I, 1

n

I(

I

la

)i

[]J

12

:

):

:(

~

II

la

~
[]

13
):

wI I

W

:

r

Figure 16 - RX Task Timing Diagram
Timing
t1

Notes
Modem in idle state. Time from writing first task to the application of
the first TX bit to the TX Lowpass Filter.

t2
Time from the application of the first bit of the task to the TX Lowpass
Filter until BFREE goes to a logic '1' (high).

Task

Typical (Bit) Time

Any

1

T7H
TQB
TDB
TSB

36
24
20
1

T7H/SFH
TQB
R3H
TDB/RDB
TSB/RSB

56
32
24
240
8

t3

Time to transmit all bits of the task.
or
Time to receive all bits of the task

t4

Maximum time allowed from BFREE going to a logic '1' for the next
task (and data) to be written to the modem.

T7H
TQB
TDB
TSB

18
6
218
6

t6

Maximum time between the first bit of the task entering the
de-interleave circuit and the task being written to the modem.

SFH
R3H
RDB
RSB

14
18
218
6

t7

Time from last bit for task entering the de-interleave circuit to BFREE
going to a logic '1'.

Any

1

Table 3 - Typical RXlTX Task Load Timings
MX-COM, INC.

Page 85

I

MX909
Programming Information ......
Control Register
This 8-bit write-only register controls the modem's bit-rate, response times of the receive clock extraction
and signal level measurement circuits and the internal analog filters.

Figure 17 - The Control
Register

I

Table 4 shows how bit-rates of 4000/8000/16000 or 4800/9600/19200 bits per second may be
obtained from common Xtal/clock frequencies. The values of Cs and C4 should be suitable for
the frequency of the Xtal X j .
For Xj < 5.0MHz, Cs = C. = 33.0pF; for Xj > 5.0MHz, Cs = C. = 18.0pF .
Clock Division Ratio: These bits, together with the HI/LO bit, control a frequency divider
driven from the Xtal/clock signal; this ratio and signal input will determine the nominal bit-rate.
High or Low Xtal Range Selection: see Table 4 below.

'1 '

B5
High

Xtal/Clock Frequency (MHz)
8.192

9.8304

4.096

4.9152

(12.288/3)

B7

'0'

4.096

Low

(12.288/3)

4.9152

2.048

2.4576

(6.14413)

(12.288/5)

2.048

2.4576

(6.144/3)

(12.288/5)

1.024

1.2288

86 Division Ratio:
XtallClock
Data Rate

0

0

256

128

0

1

512

256

1

0

1

1

Data Rate (bits per second)
16000

19200

8000

9600

16000

19200

8000

9600

4000

4800

1024 512

8000

9600

4000

4800

2048 1024

4000

4800

Table 4 - Clock/Data Rates

Note that device operation is not guaranteed or specified above 19.2 kbps or below 4 kbps

Data Rate: Employed in both RX and TX, this bit optimizes the modem's internal signal filtering
circuitry to the relevant bit-rate.
For bit-rates above 10 kbps this bit (84) should be set to a logic '1', for bit-rates at or below
10kbps set to a logic '0'.
Level Measurement Response Time: These bits are only used in the RX mode and have
no effect in the TX mode; they set the 'normal' response time of the RX signal amplitude and
DC offset measuring circuits. This setting will be temporarily overriden by the automatic
sequence of an AQLEV command. See Table 5.
For Mobitex systems, and most general-purpose applications using this modem, these bits
should be set to 'Peak Averaging', except when the IlController detects a receive signal fade,
when 'Hold' should be selected.

Page 86

MX-COM, INC.

MX909
Programming Information ..... .
Control Register......

B3, B2 ......
LEVRES

LEVRES ...... : The 'Lossy Peak Detect' setting is intended for systems where the IJControlier
cannot detect signal fades or the start of a received message; this setting allows the modem
to respond quickly to fresh messages and recover rapidly after a fade without IJControlier
intervention -this however will be at the cost of reduced Bit-Error-Rate vs Signal-to-Noise
performance.
Note that as the measured levels are stored on capacitors C 6 and C7 via pins Doc 1 and Doc
2, these levels will decay gradually towards VBIAS when the 'Hold' setting is used; the discharge
time-constant is approximately 2000 bit-times. Table 4 details bit-setting application.
B3

B2

o
o

0

1
1

0
1

1

Setting
Hold
Peak Averaging
Peak Detect
Lossy Peak Detect

Action
Keep current values of amplitude and offset
Track input signal using bit peak averaging
Track input signal using peak detection
Track input signal using lossy peak detection

Table 5

B1,BO
PLLBW

PLL Bandwidth: For use in the RX mode only (no effect in TX).
In the receive mode these two bits set the 'normal' bandwidth of the RX Clock Extraction phase
locked loop circuit to allow for RX and TX Xtal tolerances. This setting will be temporarily
overridden by the automatic sequence of an AQBC (Command Register Bit 7) command.
B1

a

o
1
1

BO

0
1

0
1
Table 6

PLL Bandwidth (:tppm)
o (Hold)

Note
For use during signal fades

30
250
50,000

The minimum bandwidth consistent with the RX and TX modem bit-rate tolerances should be
chosen; e.g. if the Xtals used with both modems have accuracies of:t1 OOppm, the PLLBW bits
(B1, BO) should be set to '1', '0'.
The very wide bandwidth ('1', '1') is intended for systems where the ,...Controller cannot detect
signal fades or the start of a receive message; it allows the modem to respond rapidly to fresh
messages and recover rapidly after a fade without IJControlier intervention. This action
however is at the expense of reduced Bit-Error-Rate vs Signal-to-Noise performance.
Note that PLL bandwidth figures are intended for 'a reasonably random received signal.'
LEVRES

.and
PLLBW

Opendlonal
Notes

Any new setting written to the Control Register will be implemented immediately regardless
of any acquisition sequence; any acquisition sequence in progress will be cancelled .
e.g. Changing B1 or BO will set the PLL to the new setting and cancel an AQBC sequence
if running. The AQLEV sequence, if running, will continue as normal (and vice versa).
Thus if an acquisition sequence is to be started using different 'normal' settings, then the new
settings must be written before triggering the acquisition sequence.
See the Operational Information section of this Data Bulletin for further details.

MX-COM, INC.

Page 87

I

I

MX909
Programming Information ..... .
Mode Register
This a-bit write-only register controls the basic operating modes of the modem.

Figure 18 - The Mode
Register

{>'... ~e~~I~r-:

"'~~~~_;:
·:'.'n.

. IRQ Output Enable: When set to a logic '1' the Interrupt Request output will be pulled low
(to VSS) whenever the IRQ bit (BIT 7) of the Status Register is set by the modem to a logic '1'.
When set to a logic '0' the Interrupt Request output will not function and will remain in its highimpedance state (see Pin Functions and Figure 7 - ~Controller Interface).
Invert Bits: When set to a logic '1', all data (sense) voltages to and from the modem's RX and
TX paths are inverted.
For example:
B6
Tx/RX Logic '1'
Tx/RX Logic '0'
'0'
High (above VBIAS )
Low (below VBIAS)
'1'
High (above V BIAS )
Low (below V BIAS)

Data will be affected immediately after B6 is set and so this bit should not be changed whilst
the modem is decoding or transmitting data. This bit only operates on data bits, there is no
effect upon functional logic inputs.
TXlRX Mode: When set to a logic '1' places the modem in the Transmit mode; when set to
a logic '0' places the modem in the Receive mode. To allow the lowpass filter to stabilize, when
changing from RX to TX there must be a 2 bit pause before setting a new task. Note that
changing between Transmit and Receive modes will cancel any current task.
Scramble Enable: Setting this bit to a logic '1' enables data scrambling; setting it to a logic
'0' disables scrambling. The scrambler only takes effect during the transmission or reception
of a Mobitex Data Block (see Figure 10 -System Data Format) and during TSO (Transmit
Scrambler Output) task. The scrambler is only operative if enabled by B4, during TSO, RDB
or TDB (see Modem Tasks), it is held in the reset state at all other times. This bit should not
be changed while the modem is decoding or transmitting a Mobitex Data Block.
Powersave: When set to a logic '1' this bit places the modem in its Powersave mode. In this
mode the following circuits only are disabled: Internal Filters, RX Level and Clock Extraction
Circuits and the TX Output Buffer; the TX Out pin is connected to V BIAS through a high-value
resistance. Xtal oscillator circuits and the ~Controller Interface logic continue to operate. When
set to a logic '0' restores power to all of the device circuitry and the modem is in its operational
mode. Note that the internal filters will take about 2 bit-times to settle after this bit is taken from
a logic '1' to '0'. Note that RX-bit and levels will be lost if the Powersave mode is selected.
Data Quality IRQ Enable: For use in the RX mode only (no effect in TX).
In the RX mode, setting this bit to a logiC '1' causes the IRQ bit (of the Status Register) to be
set to a logic '1' whenever a new Data Quality reading is ready; the DQRDY bit of the Status
Register will also be set to a logiC '1' at the same time.

These bits should be set to a logic '0'.
Page 88

MX-COM, INC.

MX909
Programming Information ..... .
Status Register
This register may be read by the IlControlier to determine the current state of the modem.

Status Register
Figure 19 - The Status
Register
IRQ

I

Status Register

B7
IRQ

Interrupt Request: This bit is set to a logic '1' by:
The Status Register BFREE bit going from a logic '0' to '1', unless this transition is
caused by a RESET Task or by a change to the Mode Register's PSAVE or TXlRX bits.
or

The Status Register IBEMPTY bit going from a logic '0' to '1', unless this transition is
caused by a RESET Task or by a change to the Mode Register's PSAVE or TXlRX bits.
or

The Status Register DQRDY bit going from a logic '0' to '1' (if DQEN = '1').
or

The Status Register DIBOVF bit going from a logic '0' to '1'.
This (IRQ) bit is cleared to a logic '0' immediately after a read of the Status Register. If the
IRQEN bit of the Mode Register is a logic '1', the MX909 IRQ output pin will be pulled low (to
Vss ) whenever the Status Register IRQ bit is a logic '1'.

B6
BFREE

B5
IBEMPTY

MX-COM, INC.

Data Buffer Free: BFREE reflects the availability of the Dala Buffer; BFREE is cleared 10 a
logic '0' (Buffer NOT Free) whenever a task other Ihan NULL, RESET or TSO is written to the
Command Regisler.
In Transmit mode, the BFREE bit will be sel to a logic '1' (setting the Stalus Register IRQ bit
to a logic '1) when Ihe modem is ready for the IlControlier 10 write new data to the Data Buffer
and the next lask 10 Ihe Command Register.
In Receive mode, the BFREE bil is sello a logic '1' (setting the Status Register IRQ bit to a
logic '1) when it has compleled a task and any dala associated with thai task has been placed
inlo the Data Buffer. The IlControlier may Ihen read that data and write the next task to the
Command Register.
The BFREE bit is also selto a logic '1' -butwilhoul selling the IRQ bil- by a RESETIask or when
the Mode Register PSAVE or TXlRX bits are changed.
Interleave Buffer Empty: In Transmit mode, IBEMPTY is set 10 a logic '1' (also setting the
IRQ bit) when less than two bits remain in the Interleave Buffer. Any transmit task written to
the modem after IBEMPTY goes to a logic '1' will be 100 late to avoid a gap in the transmit output
signal (see Figure 15 and Table 3, TX Task Timing)
IBEMPTY is also set to a logic '1' by a RESET task and by a change of the Mode Register
PSAVE or TXlRX bits, but in these cases the IRQ bit will not be set.
IBEMPTY is cleared to a logic '0' by writing a task other Ihan NULL, RESET or TSO to the
Command Register.
Note that when the modem is in Ihe transmit mode and the Interleave Buffer is empty, a midlevel (V B1AS) voltage will be fed to the TX Lowpass Filter.
In Receive mode this bit is a logic '0'.
Page 89

MX909
Programming Information ..... .

De-Interleave Buffer Overflow: In Receive mode DIBOVF is set to a logic '1' (also setting
the IRQ bit) when a task is written to the Command Register too late to allow continuous
reception (see Figure 16 and Table 3, RX Task Timing).
DIBVOF is cleared to a logiC '0' by reading the Status Register, by writing a RESET task to the
Command Register or by changing the PSAVE or TXlRX bits of the Mode Register.
In Transmit mode this bit is a logic '0'.

I

CRC or FEC Error: In Receive mode CRCFEC will be updated at the end of a Mobitex Data
Block task, after checking the CRC, and at the end of receiving Frame Head control bytes, after
checking the FEC.
A logic '0' indicates that the CRC was received correctly or that the FEC found no uncorrectable
errors. A logic '1' indicates that errors are present. CRCFEC is cleared to a logic '0' by a RESET
task, or by changing the PSAVE or TXlRX bits of the Mode Register.
In Transmit mode this bit is a logic '0'.
Data Quality Reading Ready: In Receive mode DQRDY is set to a logic '1' whenever a Data
Quality reading has been completed (see Figure 20, data quality graph). DQRDY is cleared
to a logic '0' by a read of the Data Quality Register, or by changing the PSAVE or TXlRX bits
of the Mode Register.
Mobile or Base Bit-Sync Received: In Receive mode the MOBAN bit is updated at the end
of the SFS and SFH tasks. MOBAN is set to a logic '1' whenever the 3 bits immediately
preceding a detected Frame Sync are '0' '1' '1' (received left to right), with up to anyone bit
MOBAN is set to a logic '0' if the bit pattern is '1' '0' '0', again with up to anyone bit in error.
Thus if this bit is set to a logic '1' then the received message is likely to have originated from
a mobile station, and if set to a logiC '0' the call is likely to have originated from a base station.
The Data Formats section of this document describes the different mobile and base sync
structures.
In Transmit mode this bit is a logic '0'.
This bit is always set to a logic '0'.

Page 90

MX-COM, INC.

MX909
Programming Information ..... .
The Data Quality Register
The information presented in this 8-bit register is intended to indicate the quality of the receive signal during a
Mobitex Data Block or 30 single bytes.
In Receive Mode, the modem measures the quality of the received signal by comparing the actual received zerocrossing time against an internally generated time. This value is averaged over 240 bits and at the end of the
measurement the Data Quality Register and the Data Quality Reading Ready (DQRDY) bit in the Status Register are
updated. An interrupt will only occur at this time if the DQEN bit in the Mode Register = logic'1'.
In Transmit Mode all bits are set to a logic '0'.
To provide synchronization with Data Blocks, and thereby ensure that the DQ Register is updated ready to be read
when the RDB task finishes, the measurement process is reset at the end of Tasks SFH, SFS, RDB and R3H.
Figure 20 shows how the value (0 - 240) read from the Data Quality Register varies with received signal-to-noise
ratio.

Cl 240

c
'6

Hl

a:

--

220

2en 200

-- -

.0,
Q)

a:

180

~
(1j

160

::>

a

(1j

140

Oi

0

120
100

---80
60

--40
20

3

4

7

9

10

11

12

Received Signal-to-Noise Ratio (dB)

Figure 20 - Typical Data Quality Reading vs RX Signal-to-Noise Ratio (calculated for noise in a bit-rate
bandwidth)

MX-COM, INC.

Page 91

I

I

MX909

Programming Information ..... .
MX909 Registers
The following diagram is a quick-reference to MX909 register allocations.

Register
Write to Modem
Data Buffer
Command Register
Control Register
Mode Register
Command

I

I

Register

6

I

I
IRQEN

I
IN\I13rr

5

I
lX;RX

I

4

I
SCREN

I

3

I
FSA\IE

I

2

llJ

I

I

HIIlO

DAAA

lEWES

PlLBW

Status

I

[

[)<;)EN

Reserved

set to 0 a

IRQEN
INVBIT
TXIRX
SCREN
PSAVE
DQEN

Register

CKDIV
- Clock Division Ratio
B7 B6 B5 = 1 B5 = 0
o 0
256
128
]
512
256
o 1
Xtal
1024
512
- Bit-Rrue
1
0
1
1
2048
1024
HIILO
High or Low Xtal Range Selection
Data Rate
DARA
LEVRES - Level Measurement Response Time
B3
B2
o 0 Hold
o 1 Peak Averaging
0
Peak Detect
1
1
1
Lossy Peak Detect
PLLBW - PLL Bandwidth
B1
BO
Bandwidth (+1- ppm)
o 0 0 (Hold)
o 1 30
1
0
250
1
1
50,000

RX Mode
NULL
SFH Search For Frame Head
R3H Read 3-byte Frame Head
ROB Read Data Block
SFS Search For Frame Sync
RSB Read Single Byte
LFSB Load Frame Sync Bytes
RESET
TX Mode
NULL
Transmit 7-Byte Frame Head
T7H
Reserved
TOB Transmit Data Block
TOB Transmit 4 Bytes
TSB Transmit Single Byte
TSO Transmit Scrambler Output
RESET

I

I--

Read from Modem
Data Buffer
Status Register
DO Register
not used

CK~V

TASK

- Acquire Bit Clock
- Acquire Receive Signal Levels

Mode

Ao
0
1
0
1

]

Reserved
settoOOO

BO
0
1
0
1
0
1
0
1
BO
0
1
0
1
0
1
0
1

Selection

Control

I

I

AOBC
AOLEV
TASK:
B2 B1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
B2 B1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1

7

-

0
0
1
1

Register

M;:i!A;,Af,:,lEV

I

A,

- IRQ Output Enable
- Invert Bit
- Transmit or Receive Mode
Scramble Enable
Powersave
- Data Quality IRQ Enable

IRQ

IRQ
BFREE
IBEMPTYDIBOVF CRCFECDQRDY
MOBAN -

IBEMPlY

CRCFEC

Interrupt Request
Data Buffer Free
Interleave Buffer Empty
De-Interleave Buffer Overflow
CRC or FEC Error
Data Ouality Reading Ready
Mobile or Base Bit-Sync Received

Figure 21 - Ready-Use Guide to Register Functions

Page 92

MX-COM, INC.

MX909

Operational Information
Cyclic Redundancy Code (CRC)
A 16-bit CRC code is used in the Mobitex Data
Block.
In Transmit Mode the CRC is calculated by the
modem from the 18 data bytes (see Figure 10, Mobitex
System Data Format) using the following generator
polynomial:
g(x) =

X'6 + X'2

+ x5 + 1

Forward Error Correction (FEC)
In Transmit Mode, during T7H and TDB, the modem
generates a 4-bit Forward Error Correction code for each
coded byte.
The FEC is defined by the following H matrix:

DATA BYTE
MSB

[CCITT]

This code detects all (single) error bursts of up to 16
bits in length and about 99.998% of all other error
patterns.
The CRC Register is intialized to all logic '1 's and the
CRC is calculated octet by octet starting with the LSB
of byte O. The CRC calculated is bit-wise inverted and
appended to the data bytes with the MSB transmitted
earliest.
In Receive Mode a 16-bit CRC code is generated
from the 18 data bytes of each Mobitex Data Block as
described above and the bit-wise inverted value is
compared with the received CRC bytes, if a mis-match
is present then an error has been detected.

7

LSB

6

H=

4

5
1

0

0
1

3
1
0

0

2
1 0
0
0

0

0

0
0
1
0

0

FEC
MSB
LSB

3
1
0
0
0

2 1 0
0 0 0
0 0
0 1 0
0 0

Generation of the FEC consists of logically ANDing
the byte to be transmitted with bits 7 to 0 of each row of
the H matrix. Even parity is generated for each of the 4
results and these 4 parity bits, in the positions indicated
by the last 4 columns of the H matrix, form the FEC code.
Receive Mode: In checking the FEC the received 12bit word is logically ANDed with each row of the H matrix
(earliest bit received compared with the first column).
Again even parity is generated for the 4 resulting words
and these parity bits form a 4-bit nibble. If this nibble = 0
then no errors have been detected. Other results 'point'
to the bit in error or indicate that uncorrectable errors
have occured.
This code can correct any single error that has
occured in each 12-bit (8 data + 4 FEC) section of the
message.

Example of FEC Generation
If the byte to be coded is '0 0 1 0 1 1 0 0', then the FEC is derived as follows:
H Matrix Row

1

2

3

4

A

11101100 11010011 10111010 01110101

B

00101100 00101100 00101100 00101100

A 'AND' B

00101100 00000000 00101000 00100100

Even

Parity

1

0

0

0

With reference to the table above, Row A is bit 7 to 0 of one row of the H matrix and Row B is the byte to
be coded. The Even Parity bits refer to the result of 'A' AND 'B'.
Therefore the word formed will be: '0 0 1 0 1 1 0 0 1 0 0 0' -sent left to right.
When the same process is carried out on these 12 bits ( '001 01 1 00 1 000'), using all 12 bits of
each H matrix row, the resulting parity bits will be '0000'.

MX-COM, INC.

Page 93

I

MX909

Operational Information ..... .
Interleaving
The 240 bits of a Mobitex Data Block are interleaved
by the modem before transmission to give protection
against noise bursts and short fades. Interleaving is
not performed on any bits in the Mobitex Frame Head.

Considering the 240 bits to be numbered sequentially
before interleaving as 0 to 239 (0 = bit 7 of byte 0, 11
=bit 0 of the FEC for byte 0, and ....... ,239 =bit 0 of the
FEC for byte 19), then they will be transmitted as
shown in Figure 22.
INPur DATA

~

I

~

~

I

first

- Byte 0

FIRST OUT

0
12
24
36
48
60
72
84
96
108
120
132
144
156
168
180
192
204
216
228

1
13
25
37
49
61
73
85
97
109
121
133
145
157
169
181
193
205
217
229

2
14
26
38
50
62
74
86
98
110
122
134
146
158
170
182
194
206
218
230

~

~

4

3

~

DATA
5

6

0
7

I

BLOCK
RESULnNG FEe
3
2
1 0
9

10

12

13

14

15

16

17

18

19

20

21

22

23

Byte 2

24

25

26

27

28

29

30

31

32

33

34

35

Byte 3

36

37

38

39

40

41

42

43

44

45

46

47

Byte 4

48

49

50

51

52

53

54

55

56

57

58

59

Byte 5

60

61

62

63

64

65

66

67

68

69

70

71

Byte 6

72

73

74

75

76

77

78

79

80

81

82

83

Byte 7

84

85

86

87

88

89

90

91

92

93

94

95

Byte

96

97

98

99 100 101 102 103

Byte

104 105 106 107

108 109 110 111 112 113 114 115

116 117 118 119

Byte 10 120 121 122 123 124 125 126 127

128 129 130 131

1~1.1341~1~1~1~1M

140 141 142 143

Byte 12 144 145 146 147 148 149 150 151

152 153 154 155

Byte 13 156 157 158 159 160 161 162 163

164 165 166 167

14 168 169 170 171 172 173 174 175

176 177 178 179

Byte 15 180 181 182 183 184 185 186 187

188 189 190 191

Byte

16 192 193 194 195 196 197 198 199

200 201 202 203
212 213 214 215

last - Byte

17 204 205 206 207 208 209 210 211

CRC

Byte

18 216 217 218 219 220 221 222 223

224 225 226 227

CRC

Byte

19 228 229 230 231 232 233 234 235

236 237 238 239

3
15
27
39
51

63
75
87

99
III
123
135
147
159
171
183
195
207
219
231

4
16
28
40
52
64
76
88
100
112
124
136
148
160
172
184
196
208
220
232

5
17
29
41
53
65
77
89
101
113
125
137
149
161
173
185
197
209
221
233

6
18
30
42
54
66
78

90
102
114
126
138
150
162
174
186
198
210
222
234

7
19
31
43
55
67
79
91
103
115
127
139
151
163
175
187
199
211
223
235

8
20
32
44

56
68
80
92
104
116
128
140
152
164
176
188
200
212
224
236

9
21
33
45
57
69
81
93
105
117
129
141
153
165
177
189
201
213
225
237

I

11

Byte 1

Byte

loaded

2

0

Byte 11

INTERlEAVED 0U1P\II" TO
LOWPASS FILlER

~

INPIIl DATA
5
4
3
2

6
loaded

~

MOBITEX

10
22
34

46
58
70
82
94
106
118
130
142
154
166
178
190
202
214
226
238

11
23
35
47
59
71
83
95
107
119
131
143
155
167
179
191
203
215
227
239 LAST our

t.
Figure 22 - Interleaving - Input/Output

Scrambling
The Mobitex Data Block may be transmitted or
recieved as scrambled information in accordance with
the setting of the Scramble Enable bit (Mode Register
SCREN).
All formatted bits of a Mobitex Data Block are passed
through a 9-bit scrambler. This scrambler is initialized at
the beginning of the first data block in every frame.
Page 94

The 511-bit sequence is generated with a 9-bit shift
register with the output of the 5th and 9th stages being
Exclusive OR'd and fed back to the input of the 1st
stage. The scrambler is enabled when SCREN = logic
'1' or when the Transmit Scrambler Output (TSO) task
is selected but disabled during all others.

MX-COM, INC.

MX909

Operational Information ..... .
"Receive (Mobitex) Frame" Example
If the MX909 is required to receive a Mobitex Frame, assuming that the device starts from a powersave
state, the following sequences of control and data will have to be issued:

MX909 out of Powersave, Set to RX

Mode
PSAVE='O'
TXlRX ='0'

2 bits after carrier detect, set level acquisition and bit clock extraction

Command
AQLEV='I'
AQBC = 'I'

l

I

~

2 relevant Frame Sync bytes loaded by write to Data Buffer

Load Frame Sync byte task set

Second Frame Sync byte read from Data Buffer by modem
... Interrupt ...

Data Buffer
WRITE 2 Bytes
Command (task)
LFSB

~

IRQ
Status
BFREE ='1'

l

Search for Frame Head task set

Command (task)
SFH

Frame Head detected (no uncorrectable errors)
... Interrupt ...

IRQ
Status
MOBAN ='1'fO'
BFREE = 'I'

Read out 2 Frame Head control bytes from Data Buffer

Data Buffer
READ 2 Bytes

~
~

l

Receive Mobitex Data Block task set

Command (task)
RDB

Data Block received; CRC calculated
... Interrupt ...

IRQ
Status
CRCFEC = '1'fO'
BFREE = 'I'

Read-out 18 Data Block bytes

Data Buffer
READ 18 Bytes

Data Quality Register may be read

OR
Last Data Block received; another Frame Head imminently expected
2 relevant Frame Sync bytes loaded to Data Buffer

OR
Another Data Block expected

~
~

DQ Register
READ

!
!

OR

Data Buffer
WRITE 2 Bytes

~
OR

~

Command (task)
RDB

If the last data block has been decoded and no more information is imminent, the
task bits do not need to be set; the MX909 will automatically select the idle state.

MX-COM, INC.

Page 95

I

MX909

Operational Information ..... .
"Transmit (Mobitex) Frame" Example
If the MX909 is required to send a Mobitex Frame, assuming that the device starts from a powersave state,
the following sequences of control and data will have to be issued:

MX909 out of Powersave, set to TX

Mode

PSAVE = '0'
TXIRX'I'

~

A 2 bit pause is required to allow the lowpass filter to stabilize. During this time the 6
bytes forming the Frame Head may be loaded to the Data Buffer by the ILControlier

Data Buffer
WRITE 6 Bytes

Transmit Frame Head task set

Command (task)
T7H

~

Last (6th byte) of Frame Head read from Data Buffer by modem
- - - Interrupt - - -

IRQ
Status
BFREE='I'

~

Load 18 data bytes into the Data Buffer

Data Buffer
WRITE 18 Bytes

Transmit Data Block task set

Command (task)
TDB

~

Last (18th) byte of the loaded data read from the Data Buffer by modem
- - - Interrupt - - -

Load data and set tasks as required
Another Data Block in this current frame is to be transmitted
Load 18 data bytes into the Data Buffer
Last Data Block has been transmitted... another frame is to be transmitted
Transmit Frame Head
6 bytes forming the Frame Head are loaded to the Data Buffer by the ILController,
followed by a 2-bit pause to allow the Lowpass Filter to stabilize

IRQ
Status
BFREE='I'

,
,

-I-------j--------

,,,

...

:
Data Buffer
: WRITE 18 Bytes

...
Data Buffer
WRITE 6 Bytes

If the last Data Block has been transmitted and another frame is not to be sent, then
a new task need not be written and the ILControlier can wait for the (Status Register)
IBEMPTY interrupt when, after a few bits pause, to allow for the TX Lowpass Filter
delay, it can shut down the RF circuitry if required.

Page 96

MX-COM, INC.

MX909
Operational Information ......
Received Signal Acquisition
Level Measurement and Clock Extraction
To achieve reasonable error rates the MX909
modem needs to make accurate measurements of the
received signal amplitude, DC offset and bit-timing.
Accurate measurements, especially in the presence of
noise, are best made by averaging over a relatively
long time period.

Note that due to the delay through the RX low pass filter,
the AQBC and AQLEV sequences should not be started
until about 2-bit times after the RX carrier has been
detected at the discriminator output.
In a system where the controlling IJControlier is not
able to detect the RX carrier, the AQBC and AQLEV
sequences may be started at any time; possibly when no
carrier is being received. However in this case the clock
and level acquisition operation will take longer as the
circuits will have to recover from the change from a large
amplitude noise signal at the output of the frequency
discriminator to the wanted signal, probably with a DC
offset. In this type of system the time between the turn-on
of the transmitter and the start of the Frame Sync pattern
should be extended -preferably by extending the Bit Sync
sequence to 32 or even 48 bits.
Note thatthe clock extraction circuits work by detecting
the timing of received edges, i.e. a change from '0' to '1'
or '1' to '0'. They will eventually fail if logic '1 's or logic 'O's
are transmitted continuously. Similarly, the level measuring
circuits require '00' and '11' bit pairs to be received at
reasonably frequent intervals.

In most cases the modem will be used to receive
isolated messages from a distant transmitter that is
only turned on for a very short time before the message
starts; also, the received baseband signal from the
radio's frequency discriminator will have a DC offset
due to small differences between the receiver and
transmitter reference oscillators and hence their 'carrier'
frequencies.
To allow for this situation, AQBC and AQLEV
(Acquire Bit Clock and Level) commands cause the
modem to follow an automatic sequence designed to
perform the measurements as quickly as possible.
The complete AQBC and AQLEV sequence is
illustrated in Figure 23; in the described situation the
IJControlier can detect the received carrier and therefore
knows when to issue the AQBC and AQLEV commands.

AQLEV
SEQUENCE

ao

r~EVEL

AVERAGE

PEAK DETECT

:,,-

."
:5

EXTRACTION
tETTING

o

BIT TIMES

LOSSY PEAK DETECT (if set)

N.B. CLAMP will still operate

0 bits

16 bits

BIT SYNC

,,
,
,,
,,

MOBITEX TYPE
RX SIGNAL FROM
DISCRIMINATOR

RESIDUAL

!Hold Average or Peak)

32 bits

FRAME SYNC

i.---.!2-BIT DELAY (min.)

!

SET AQBC AND AQLEV BITS
TO START ACQUISITION SEQUENCES

f

GOOD
50,000

SIGNAL

8,000

Residual

FRAME SYNC DETECT
:
(internal):
~ (25013010)
(SFS/SFH) NOT ENABLED ::.~----------;-..
~~--~~~:---.I<~.:--~

------SO-bltS'--:----

AQBC
SEQUENCE
50,000:

FRAME SYNC DETECT
(SFS/SFH) ENABLED
FRAME SYNC

D8E~

FRAME SYNC:
DETECT

.

8,000
(internal)

Residual
250130/0)

+-----

50,000 (if set)

.

30 bits

.-~---~-~---~------------­

(Don't Care)

GOOD SIGNAL is determined if the last 4 zero-crossings have been detected as clean. i.e. lillie jitter
If Frame Sync is not set, then the '8,000' setting will start
when either: 1 GOOD signal is detected
2 Frame Sync is set and detected -- WHICHEVER OCCURS FIRST
The acquisition sequences AQLEV and AQBC can be set independantly and at any time.
If AQBC is set with Frame Sync Detect (SFS) active then the 50,000 selling will continue until Frame Sync
is received, or the PLLBW bits are changed, or the device is reset .

Figure 23 - Bit-Clock and Level Acquisition Example
MX-COM, INC.

Page 97

I

I

MX909

Operational Information ...•..
Received Signal Acquisition ..... .
Acquire Receive Signal Levels
AQLEV
Command Register
The Acquire Receive Signal Levels (AQLEV)
sequence starts with a measurement of the average
signal voltage over a period of 1 bit-time (CLAMP). If
the LEVRES bits are not set to 'Lossy Peak Detect' ('1'
'1') the sequence continues by measuring the positivegoing and negative-going peaks of the signal.
The attack and decay times used in this 'peak
detect' mode are such that a sufficiently accurate
measurement can be made within 16bitsofa '11001100
.. .' pattern (Le the bit-sync sequence) to allow the bitclock extraction circuits to operate.
Once the bit-clock extraction circuits have detected
the presence of a sufficiently coherent signal, then
-provided that the LEVRES bits of the Control Register
have been set to the 'Peak Averaging' settings or
'Hold' - the level measurement circuits will switch to the
'Peak Averaging' mode, in which they calculate the
average of the peak voltages due to received bits.
If the LEVRES bits are set to 'Hold' the 'Peak
Averaging' measurement will cease after 16 bit times
-and the final values kept- otherwise the circuits will
continue in the operation as previously described.
For normal operation the LEVRES bits would only
be set by the controlling IlControlier to 'Hold' for the
duration of a "fade".

Acquire Bit Clock
AQBC
Command Register
The Acquire Bit Clock (AQBC) sequence follows a
similar pattern; starting with a very fast initial estimate
of the received bit timing, then reducing the bandwidth
of the Phase Locked Loop as a coherent Signal is
detected until the limit reached by the (Control Register)
PLLBW bits is reached.

LEVRES Peak Detect and Peak Averaging Operation
Further information on this subject is currently unavailable in this "Advance Information"
Document

Page 98

MX-COM, INC.

MX909
Operational Information ..... .
Control and Data Load Timing
Control Instructions, Task and Data is loaded to the MX909 in a parallel form as detailed in the relevant
Programming Information sections of this Data Sheet. Timing information for Read and Write operations is given
in Figure 24; timing parameters are provided in the Specification section.
WRITE CYCLE (DATA TO MODEM)

~___________A_D_D_R_ES_S__VA_L_ID______________~'~»<:~

ADDRESS

P.o.

A,

~tACSL

--------~~~
tAHCSL

~

IE

_______

~_SH~i~(~~----~~~S~HI-----~

__________________________

N

tCSAWL

y

tWL

.

~----------~: i

----'-'------

'( tosw ):

i
DATA
Do to D7

: ~tOHW

______-J~~--~A-A[-~--~)x(-------

(1 byte)

READ CYCLE (DATA FROM MODEM)

ADDRESS
Ao. A,

~____________A_D_D_R_Es_s__vA_L_ID____________~i,i~»<:~
~:tACSL

~

_______

~sHh;,

LSHI

~

i ~~____________________________:,--..J/ ~____~'C~_ _ _ _ _~

tWHCSL

[<--->'

"'--

i'( tCSAWL )',
i
:
~ ~,(;-_ _----"tAL'----_-----c;

)'

,

'k:~________________~{ ~
;(

DATA
Do to D7 (1 byte)

--t-

tRAAL

):

C- -------«

RA L

tOHA

~

DATA VALID

tAX

i

::>---

)1

Figure 24 - MX909 - jiProcessor ReadiWrite Timing

MX-COM, INC.

Page 99

I

I

MX909

Specifications
Absolute Maximum Ratings

Operating Limits

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(ref Vss=OV)
Sink/Source Current
(supply pins)
(other pins)
Total Device Dissipation
(@ T AMB=25°C)
Derating
Operating Temperature
Storage Temperature

-0.3 to 7.0V

V DD

=5.0V

-0.3 to (VDD+ 0.3V)
Bit Rate = B kbps

±30mA
±20mA

Xtal/Clock = 4.096 MHz

BOOmW max.
10 mW/oC
-40°C to +B5°C

Noise Bandwidth = Bit Rate

Static Values
Supply Voltage
IDD (powersaved)
IDD (not powersaved)

4.5
1.0
B.O

TX Output
Impedance
Impedanc
Signal L
TX Data Delay :'!;'.:'t;:Power-up to TX Our
TX Low Pass Filter

300
0.9

-.

1.0
500
1.0
4.0
3

5.5
1.5
12.0

V
mA
mA

2.5

kQ
kQ
Vp-p
bits
bits

1.1
6.0
5

RX Input
Impedance (RX In pin)
RX Input Amp Voltage Gain
Input Signal Level
RX Data Delay
Xtal/Clock
XtallClock Frequency
'High' pulse width
'Low' pulse width
Input Impedance
Inverter Gain (lIP = 1mV rms @ 1kHz)
IJControlier Interface
Input logic '1' level
Input Logic '0' level
Input Leakage Current (VIN = OV to V DD)
Input Capacitance
Output Logic '1' Level (IOH = 120IJA
Output Logic '0' Level (IOL = 3601JA)
'Off' State Leakage Current (V = V DD)

Page 100

MQ
V/V
Vp-p
bits

9
9

10, 11
10,11
10, 11
10,11
11
11,12
12

1.0
40.0
40.0
10.0
20.0

MHz
ns
ns
MQ
dB

V DD -1.5
1.5
+5.0

-5.0
10.0
V DD -0.4

0.4
10

V
V
IJA
pF
V
V
IJA

MX-COM, INC.

MX909
Specifications ..... .
Modem ReadJWrite Load Timing

'~tfif~i}:/I·..
t ACSL
tAH
tCSH
tCSHI
tCSAWL
tOHA
tOHW

y··:c

"Address Valid" to "CS Low" time
"Address Hold" time
"CS Hold" time
14
"CS High" time
"CS" to "WR" or "RD" Low time
"Read-Data Hold" time
Write-Data Hold time
Write-Data Set-Up" time
"RD High" to."CS Low" time (write cycle)
"Read Access" time from "CS Low"
13
13
"ReadAc~" timefr.orj; "RD Low"
"RD" Low time
.
"RD High" to "0 0 0 7 3-sta~ time
"WR High" to "CSLQw" time (read cycle)
"WR" Low time

tosw
tAHCSL
t AACL
tAAAL
tAL
tAX

tWHCSL
tWL
Notes:

1.
2.
3.
4.

5.
6.
7.
8.
9.
10.
11.
12.
13.
14.

..

0
0
0
6.0
0
0
0
90.0
0

200
0
200
._,

ns
ns
ns
XtallClock Cycles
ns
ns
ns
ns
ns
175
ns
145
ns
ns
50.0
ns
ns
ns

.'

Not including any current drawn from the rriQdel1'lpi~;6.y.ext.emalcirp:yitry.
Small signal impedance (dynamic measurernent);:.'·
...
Measured after external CR (RjC 6 ) filter, for 1111000011;110000•. bit seqtJence~ lilt V 00 = 5.0V
(output level is proportional to Voo )'
Measured between issuing first task after idle and the center of tMfirst bit at TX Out (see Figure
13, 'The TX Process').
Measured between setting PSAVE = '0' and TX output becoming stable.
See Figure 25, Lowpass filter response.
For optimum performance, measured at the RX Feedback pin, for a '... 11110000.. .' bit sequence.
Measured between center of last bit of an RX single byte or Frame Sync at RX In and an IRQ
interrupt to the IJControlier.
Timing for an external input to the Xtal/Clock pin.
WR, RD, CS, Ao and A, pins.
~ 0 7 pins.
IRQ pin.
With 30pF (Max.) to Vss on Do - 0 7 pins.
Xtal/Clock cycles at the Xtal/clock pin.

MX-COM, INC.

Page 101

I

MX909
Lowpass Filter Response

..... "r-.

0

r-. ....

-10

r--" ~
-20

1'."
-30

I

iii'
:g.

z

«
Cl

" ~i\

-40

" r--r--

r--

-so

r-.r--

........

-60

........
r--r--....

-70

r--r-. r-. ........

-80
0

0.2

0.4

0.6

1

0.8

1.2

1.4

1.8

1.6

2

FREQUENCY/DATA RATE

Figure 25 - Lowpass Filter Response (Including the External RC Filter Components) in the TX Mode

Signal-to-Noise Performance
o

......

~

Block Error Rate with FEC

--

-

"

--

Bit Error Rate No FEC

..............

I"-....
NOTE: A block is deemed to be "In Error' if the CRC fails

4

5

6

7

8

9

10

11

12

SIGNAL-TO-NOISE RATIO (dB)

Figure 26 - Typical Error Rates

Bit and Block Errors
The figure above shows both bit and block error possibilities for a received signal with a specific signal-tonoise performance. Bit Errors are individually detected errors in the raw data stream.
Block Errors are those where a complete block of data (240 bits; see Figure 10, Data Format) is in error, as
indicated by the CRC. Note that signal-to-noise ratios illustrated in this Data Bulletin are calculated for noise in
a bit-rate bandwidth.
Page 102

MX-COM, INC.

MX·~,IN~.
Advance Information

MX919
MX929

HIGH-SPEED FOUR-LEVEL FSK "PACKET DATA" MODEMS
MX919: General Purpose

MX929: RD-LAP* (ARDIS**)

Features
• MX-COM MX'D Signal CMOS
• FM Radio Packet Data Applications
• Wireless Data Systems
• Radio Telemetry
• Mobile Data Links
• Wireless LANs
• Medical Telemetry
• Wireless Bar-Code Readers
• 4-Level FSK - 4.8/9.6/19.2 kbps
• Low Power Requirement
• Custom Frame Capabilities (MX919)

• Automatic Protocol Handling (General
Purpose & RD-LAP)
• Symbol and Frame Sync
• Block Formatting
• Forward Error Correction
• CRC Check and Generation
• Interleaving
• PCMCIA Packaging Available···

MX919J
MX929J
24-pin CDIP

MX919LH
MX929LH
24-pin PLCC

Description
The MX919 and MX929 are half-duplex high-speed,
4-level FSK 'packet data' modems. They work with a
host IJControlier to provide packet data transfer via FM
radio systems.
The MX919 provides a versatile frame structure for
general-purpose applications. The MX929 is designed
specifically for the ARDIS RD-LAP network.
Having a low power requirement of 5.0mA at 5 volts,
the MX919 and MX929 modems provide:
•
Automatic handling of general purpose (MX919)
and RD-LAP (MX929) frame structures, including RX
symbol and frame synchronization, blOCk formatting,
CRC generation and checking, Forward Error Correction
and Interleaving to reduce the processing load on the
host IJControlier.
•
Selectable data rates of 2400/4800/9600
symbols/s (4.8/9.6/19.2 kbps) for high-speed operation.
•
4-Level FSK (2 bits per baud) baseband

modulation enables high-speed, economical data rates
in a narrow RF bandwidth.
On-chip baseband processing and filtering.
Pre-selectable signal acquisition and tracking
permits the rapid acquisition of received signals,
followed by automatic tracking of signal dc level
variations.
Clock recovery PLL bandwidth and RX signal level
measurement circuitry will react automatically when set.
RX and TX data and control between the host
IJControlier and this microcircuit is via an 8-bit
bi-directional parallel interface; input and output signals
to and from the radio system are in analog form suitable
for connection to the radio's discriminator and frequency
modulator.
The MX919 and MX929 modems are available in 24pin CDIP and Surface Mount packages, as well as
packaging for PCMCIA applications···.
"RD-LAP is a trademark of Motorola, Inc.
"ARDIS is a service mark of ARDIS.
"""Contact MX-COM for more information.

MX-COM, INC.

Page 103

I

I

MX919IMX929
MX919 and MX929 Circuit Descriptions
Data Bus Buffers
Eight bi-directional 3-state logic-level buffers between
the modem's internal registers and the contrOlling
IJController's data-bus lines.

RX Input Amp
The amplifier that allows the received signal input to the
modem to be set to the optimum level by suitable selection
of the external components.

RIW, CS and Address Lines

Frame Sync Detect
This circuit, which is only active in the receive mode, is
used to look for the user-specified 24-symbol Frame
Synchronization pattern which is transmitted to mark the
start of every frame.

Control. the transfer of data bytes between the
IJController and the modem's internal registers, according
to the state of the Write and Read Enable (WR and RD)
inputs, the Chip Select (CS) input and the Register Address
inputs (Ao and AJ
The Data Bus Buffers and Address & RIW Decode
blocks provide a byte-wide parallel IJController interface.
Status and Data Quality Registers
8-bit registers which the IJController can read to
determine the status of the modem and the received data
quality.
Command, Mode and Control Registers
The values written by the IJController to these 8-bit
registers control the operation of the modem.
Data Block Buffer
An 12-byte buffer used to hold RX or TX data to or from
the IJController.
CRC Generator/Checker
A circuit which generates (transmit mode) or checks
(receive mode) the Cyclic Redundancy Checksum bits
which may be included in transmitted data blocks so that the
receive modem can detect transmission errors.
FEC Generator/Checker
In transmit mode, this circuit adds Forward Error
Correction bits to the transmitted data, then converts the
resulting binary data to 4-level symbols. In receive mode, it
translates received 4-level symbols to binary data, using the
FEC information to correct a large proportion of
transmission errors. The 4 possible levels of a symbol are
referred to in this Data Sheet as: +3, +1, -1 and -3.
InterleaveiDe-interleave Buffer
Interleaves data symbols within a data block before
transmission and de-interleaves the received data so that
the FEC system is best able to handle short noise bursts or
fades.

Page 104

Root Raised Cosine (RRC) Filter
This filter, which is used in both transmit and receive
modes, is a linear-phase lowpass filter with a 'Root Raised
Cosine' frequency response.
In TX mode, the 4-level symbols are passed through this
filter to eliminate the high frequency components which
would otherwise cause interference into adjacent radio
channels.
In AX mode this filter is used to reject HF noise and to
equalize the received signal to a form suitable for extracting
the 4-level symbols.

RX Symbol/Clock Extraction
These circuits, which operate only in receive mode,
extract a symbol-rate clock from the received signal, and
measure the received signal amplitude and its dc offset.
This information is then used to extract the received 4level symbols and also to provide an input to the received
Data Quality measuring circuit.

Clock Oscillator and Dividers
This circuit derives the transmit symbol-rate (and the
nominal receive symbol-rate) by frequency division of a
reference frequency which may be generated by the onchip Xtal oscillator or fed from an external source.

TX Output Buffer
A unity-gain amplifier used in the transmit mode to buffer
the output of the RRC filter. In receive mode, the input of this
buffer is normally connected to V BIAS unless the AXEYE bit
of the Control Register is set. When the modem is set to the
powersave mode, the buffer is turned off and the TX Output
pin connected to V BIAS via a high value resistance.

MX-COM, INC.

MX919/MX929

IRQ

0::

~~

0«

cco.

... 0::

5~
0-

,.

Do
D,
D2
D,

~
~

D4~
D5~
D6~
D7~

CRC
GENERATOR!
CHECKER

~>

WR
RD
~

> ADDRESS
> AND
RNI
> DECODE
>

Ao

A,

I

~

FRAME
SYNC DETECT

RX Symbols

DOC 1

~I--'--4IIj--~

11

RRC
FILTER

RX SYMBOUCLOCK
EXTRACTOR

XTAL
CLOCK
OSCILLATOR
AND
DIVIDERS

XTAUtCL~O~C~K~---i~~~=-J

I

Figure 1 - MX919IMX929 Functional Block Diagram

MX-COM, INC.

Page 105

I

MX919/MX929
MX919 and MX929 Pin Functions
1

IRQ: A 'wire-ORable' output for connection to the controlling )JController's Interrupt Request
input. This output has a low-impedance pull-down to Vss when active, and is high-impedance
when inactive.

2
3
4
5
6
7
8
9

0 7:
Os:
05:

0 4 : 8 bi-directional 3-state )JController interface data lines.
0 3:
O2 :

0 1:
Do:

10

logic level input used to control the reading of data from the modem into the

11

used to control the writing of data into the modem from

13

CS: An active-low logic level input
Figure 26, Timing).

14
15

Ao: Two logic-level modem register selection inputs.
A1 :

16

Xtal:

17

Xtal/Clock: The input to the on-chip Xtal oscillator. Operation of the MX919/MX929 without a
suitable Xtal or clock input may cause device damage.

18
19

Doc 2:
Doc 1:

20

TX Out: The TX signal output from the modem.

21

VBIAS: The internal circuitry bias line, held at V00/2, this pin must be decoupled to Vss by a
capacitor mounted close to the device pins.

22

RX In: The input to the RX input amplifier.

23

RX Feedback: The output of the RX input amplifier, and the input to the (RX) Lowpass Filter.

24

VOD : The positive supply. Levels and voltages within the modem are dependent upon this supply.
This pin should be decoupled to V ss by a capacitor mounted close to the device pins.

Page 106

The output of the on-chip Xtal oscillator.

Connections to the internal RX signal level measurement circuitry. Capacitors as
shown in Figure 2 should be installed from each of these pins to Vss.

MX-COM, INC.

MX919/MX929
Installation Information

VOl

r7
RQ

w

(J

itII:

w

I~

II:

W

0

~

Do

~

05

~

0_

~

0

~

3

O2

...J
...J

0,

°~

Do
RD

(J

WR

II:

•
•
•
•
•

•

~

~

0_
::t

Vss

CS

•
•

2

23

3

22

4

21
20

5
6
7

MX919J
MX929J

19

C[

RX IN

C2

V S1AS

R_

TX OUT
Doc 1

TX OUT=

I

Doc 2

18

8

17

9

16

10

15

11

14

12

13

XTAUCLOCK

:E7-=-

rols

XTAL

-=::::'"

A,

-=-

Ao

LAO
A,

Figure 2 - Recommended External Components

Component
R,
R2
R3
R4

C,
C2
C3
C4
Cs
Co
C7
C.
X,

Value
Note 1
100kQ
1.0MQ

Rand
Cs should be chosen so that the product of R4
4
(Ohms) and Cs (Farads) is:
0.34
bit rate (bits per sec)
R should be not less than 20kQ; the value used for
Cs4 should take into account parasitic capacitance.

Tolerance
±10%
±10%
±20%

Note 2

O.1IlF
O.1IlF
Note 3
Note 3
Note 2
Note 2

Note 4

±20%
±20%
±20%
±20%
±20%
±20%

Examples
BOOObps
4BOObps
3.

TBD
Note 3

Resistors R, and R2 , with the RX Input Amplifier, set
the signal input level to the modem.
The value of R, should be calculated to give 1.0v pp at the RX Feedback pin for a received +3 +3 -3 3 +3 +3 -3 -3 sequence. The dc level of the received
signal should be adjusted so that the signal at the
modem's RX Feedback pin is centered around V BIAS.

2.

External components R4 and Cs form an RC lowpass
filter between the TX Buffer output and the input to
the radio's frequency modulator; this is an important
part of the TX signal filtering. These components
may form a part of any dc level shifting and gain
adjustment circuitry. The ground connection (Vss) of
C should be positioned to give maximum
attenuation of high frequency noise into the
modulator.

MX-COM, INC.

Cs
430pF
710pF

The values used for C3and C4 are determined by the
frequency of X,.
As a guide:
C3 = C4 = 33pF for X, < 5.0MHz.
C3 = C4 = 18pF for X, > 5.0MHz.
If the on-chip Xtal oscillator is to be used, then the
external components X,, C3, C 4' and R3 are required
as shown in Figure 2 (inset). If an external clock
source is used these components are not required;
the input should be connected to the Xtal/clock pin
and the Xtal pin left unconnected. Table B provides
advice on the selection of the correct Xtal value.

Installation Notes
1.

R4
100kQ
100kQ

4.

External capacitors C 6 and C7 form part of the
received signal level measuring circuit. For
optimum performance the values of these
components should be as shown below.

For
2400 symbols/sec
4800 symbols/sec
9600 symbols/sec

0.021.lF
0.011.lF
0.00471.lF
Page 107

I

MX919/MX929
Installation Information ...
Binary to Symbol Translation
Although the over-air signal, and hence the signals at the modem TX Out and RX In pins, consists of 4-level
symbols, the raw data passing between the modems and the I-IControlier is in binary form. The MX919/929 translates
between binary data and the 4-level symbols in one of two ways, depending on the task being performed:

Direct
The simplest form, which converts between 2 binary
bits and one symbol according to the table below.
Symbol
MSB
LSB
+3
1
1
+1
1
0
-1
0
0
-3
0
1

With Forward Error Correcting (FEC)
This is more complicated, but essentially translates 3
binary bits to two 4-level symbols using an FEC coding
scheme which lets the receiving modem detect and
correct a large proportion of transmission errors. Full
details are given later in this document

This scheme can be expanded so that an 8-bit byte
translates to four symbols:
MSB
Bits

LSB

-=7--,--1-,6=-+--,5=--.!._4-,-+_3~1,--=-2-l--'--d,--I...::.0-11

Symbols~~a~~__-,b~~___c~~__~~

sent first

sent last

MX919IMX929 Modem

Figure 3 - Flow Through the MX919

TX FREQUENCY
SIGNAL AND
DC LEVEL
ADJUSTMENT

RX FEEDBACK

I'CONTROLLER
Do - D7 ~----.a
Ao - A,

cs

MX919/929

AD

WR
IRQ

t----..WR
IRQ

4-Level FSK Modem

Figure 4 - External Signal Paths

Page 108

MX-COM, INC.

MX919/MX929
Installation Information ..... .
AC Coupling
For a practical application, AC coupling from the modem's transmit output to the Frequency Modulator and from the
receiver's Frequency Discriminator to the receive input of the modem may be desired. There are, however, two
problems.
1) AC coupling of the signal degrades the bit-error-rate performance of the modem. Figure 5 illustrates the typical
bit error rates at 4800 symbols/sec (without FEC) for differing degrees of AC coupling;

-

I

,J::;=::.~ ~-

~ Bl-~ '---

-

~

.........

-

""-

Tx & Rx DC coupled

=
=

=

-~-T x

-

-0---

-

- - - - Tx 5Hz, Rx 10Hz

~

5H z, Rx DC

~

~

Tx 5Hz Rx 5Hz
'

5

6

7

8

9

10

11

12

SIGNAL-TO-NOISE RATIO (dB) (noise in 0 - 9600Hz band)
Figure 5 - Examples of BER Performance Degradation Due to Varying Degrees of AC Coupling

2) Any AC coupling at the receive input will transform any step in the voltage at the discriminator output to a slowly
decaying pulse which can confuse the modem's level measuring circuits. As illustrated below, the time for this
voltage step to decay to 37% of its original value is:
RC
(2II x f)

Where f is the 3dB cut-off frequency of the AC coupling network; RC is 32msec -or 153 symbol-times at
4800symbols/sec- for a 20Hz network.
In general, it will be best to DC couple the receive discriminator to the modem, and to ensure that any AC coupling
to the transmitter's frequency modulator has a -3dB cut-off frequency of no higher than 5Hz (for 4800symbols/sec).

Step Input
to RC Circuit

Output of
RC Circuit

Figure 6 - Decay Problems of the RC Network
MX-COM, INC.

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MX919IMX929
Radio Performance
The maximum data rate that can be transmitted over a radio channel using the MX919/929 depends on:
•

RF channel spacing.
Allowable adjacent channel interference.

•

Symbol rate.

•

Peak carrier deviation (modulation index).

•

TX and RX reference oscillator accuracies.
Modulator and demodulator. linearity.
Receiver IF filter frequency and phase characteristics.

•

Use of error correction techniques.
Acceptable error rate.

As a guide, 4800 symbols/sec can be achieved -subject to local regulatory requirements- over a system with
12.5kHz channel spacing if the transmitter frequency deviation is set to ±2.5kHz peak for a repetitive +3 +3 -3 -3
pattern and the maximum difference between transmitter and receiver "carrier" frequencies is less than 2400Hz.
The modulation scheme employed by these modems is designed to achieve high data throughput by exploiting
as much as possible of the RF channel bandwidth. This does, however, place constraints on the performance of
the radio. In particular, attention must be paid to:
Linearity, frequency and phase response of the TX Frequency Modulator. For a 4800 symbol/sec system,
the frequency response should be within ±2dB over a range 3Hz to 5Hz, relative to 2400Hz.
•

The bandwidth and phase response of the receiver's IF filters.

•

Accuracy of the TX and RX reference oscillators, as any difference will shift the received signal towards
the skirts of the IF filter response and cause a DC offset at the discriminator output.

Viewing the received signal eye (using the Mode Register RX Eye function) gives a good indication of the overall
transmitter/receiver performance. See Figure 7 for the appearance of the RX Signal Eye.

RX Mode,
RX EYE bit = '1'
(Mode Register 84)

Figure 7 - RX Eye Signal at the TX Out pin for Pseudo-Random Received Data

Figure 8 - TX Eye Diagram
Page 110

MX-COM, INC.

MX919/MX929
Baseband and RF Frequency Requirements
OdB

= 1.0 V RMS

iii'
~

....J

-20

UJ

>
UJ

....J

-40 .

I
2.0

8.0

10.0
FREQUENCY (kHz)

Figure 9 - 'TX Out" Spectrum Plot

.0dB

..... Unmodulated Carrier Level

iii'
~

u:l

>
UJ

-20

___________________________________ L __________________ _______

.AJ·"...."Lc.·,

....J

-40 ................ .

-60 ...

-80

fe

fc : 10

fc - 20

fc

10

fc + 20
FREQUENCY (kHz)

Figure 10 - Theoretical RF Spectrum Plot

Do
D,
D,
D,
D4
D5
D,
D,

=I"'~'.
4

~

WR

Do
D,
D,
D,
D4
D5
D,
D,
WR

AD

~+ 5 Volts
fRO line

~CONTROLLER

pullup resistor

IRQ

AD
I
~
•

MX919
MX929

The Data Bus Buffers and
Address and Read/Write
Decode blocks form a bytewide parallel ~Controller
interface.
This diagram shows how this
function can be memory
mapped.

iRQ
other IRQ inputs
to I1Controlier

A,

A,
A,

A,

~~~~~~

:

ii,
~C

Address Bus

: i Address ~
~~:~dej

CS

Figure 11 - Typical Modem to JlControJler Interface

MX-COM, INC.

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I

MX919/MX929

Programming Information
Data Formats
Frame and Data Structures
The MX919 Frame and data structures are illustrated
in Figure 12, and the MX929 in Figure 13. The structures
consist of a Frame Preamble (comprising Symbol and
Frame Synchronization patterns) followed by one or
more 'Header', 'Intermediate' or 'Last' blocks. The binary
data transferred between the modem and the controlling
~Controller is that shown in the shaded area near the top
of the diagram.
The 'Header' block is self-contained in that it includes
its own CRC, and would normally carry information such
as the addresses of the called and calling parties, the
number of following blocks in the frame (if any), and
miscellaneous control information.
The 'Intermediate' block(s) contain only data, the
CRC checksum for all of the data in the 'Intermediate'
and 'Last' blocks is contained at the end of the 'Last'
block.

This arrangement, while efficient in terms of data
capacity, may not be optimum for poor signal-to-noise
conditions, since a reception error in anyone of the
'Intermediate' or 'Last' blocks would invalidate the whole
frame. In these conditions, increased throughput may be
obtained by using the 'Header' block format for all blocks
of the frame, so that blocks which are received correctly
can be identified, and need not be retransmitted.
In the TX mode, the modem translates the 96 bits of
the block into 66 4-level symbols as follows:
The 12 bytes are divided into 32 groups of three bits
each (Tri-bits). An extra tri-bit ('0' '0' '0') is added
giving a total of 33 tri-bits.
The 33 tri-bits are then passed to the Trellis Encoder
which provides 66 4-level symbols.
In the RX mode, the modem takes the 66 received
symbols and decodes them into tri-bits.

Possible Data Formats

Typical On-Chip Frame Structure and Process
Header Block
Byte
Byte
Byte
Byte

Intermediate Block(s)

Last Block

II

0
1
2
3

Header Block 'He' contains 'addresses', signal parameters
and its own CRe
Intermediate Block 'IB' contains only data; no CRG.
Last Block 'LB contains data and the CRG for all
Intermediate Blocks and the Last Block.

Byte 4
Byte 5
Byte 6
Byte 7
Byte 8

: : ~o

Data Blocks

!-.;..;.;~~'"""..,

Byte 11

1 Block _.

33 Tri-blts

Data field consists of a train of Intermediate Blocks
followed by one Last Block carrying the CRC for the
whole field.

Tri-bits

Data field consists entirely of Intermediate Blocks; no
CRG is carried in the signal.
66 Symbols

4-level

Symbols --

Note
The Data Block areas shown shaded (left) represent the data loaded
to and from the 4-Level FSK MX919 modem by the IlControlier.
Symbol Sync configuration is predetermined within the modem as at
least 24 symbols of ... +3 +3 -3 -3 ... sequence.
Frame Sync sequence is predetermined within the modem.

FRAME

Symbol Sync: a1 least 24 symbols of .. +3 +3 -3 -3 ... sequence
Frame Sync:

--

1-11+11-1 1+11-11+31-31+31-31-11+11-3\+31+31-11+11-31-31+11+31-11-31+11+31
~

Figure 12 - MX919 System Data Format
Page 112

MX-COM, INC.

MX919/MX929

msb

Station 10

19b

Byte 0
Byte 1

Byte 0
Byte 1

Byte 2
Byte 3

Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte B
Byte 9
Byte 10
Byte 11

Header Block

Intermediate Blocks

Last Block

76543210

76543210

76543210

Data BreS
Address
and
Control

(0-8

Data Bytes

------

(12)

Pad Botes
(0-8

(10 bytes)

I

CRC2
(4 bytes)

CRC1
(2 bytes)

96 Bits

Over-air signal
(symbols)

:(
PACKET (1 TO 44 BLOCKS)

FRAME

:(

PREAMBLE

>:(

FRAME

S: Channel Slatus Symbol:

+3 = Busy

+1 = Unknown

-1 = Unknown

NEXT FRAME
(OPTIONAL)

>

-3 = Idle

Frame Sync:

I -1 I +1 I -1 I +1 I -1 I+3 I -3 I+3 I -3 I -1 I +1 I -3 I +3 I+3 I -1 I +1 I -3 I -3 I +1 I +3 I -1 I -3 I +1 I +3 I
Symbol Sync:

I +31 +3 I -3 I -3 I +31 +3 I -3

1-3

I +3 I +3 I -3 I -3 I +3 I+3 I -3 I -3 I +31

+31 -3

I -3 I -3 I -3 I +31 +3 I

sent first

last

Note
The Data Block areas shown shaded represent the data
loaded to and from the MX929 modem by the l1Controlier.

Figure 13 - MX929 System Data Format

MX-COM, INC.

Page 113

I

MX919/MX929
Programming Information ..... .
Modem/j.lControlier Interaction
In general, data is transmitted over-air in the form of
messages, or 'Frames', consisting of a 'Frame
Preamble' followed by one or more formatted data
blocks. The Frame Preamble includes a Frame
Synchronization pattern designed to allow the receiving
modem to identify the start of a frame. The following data
blocks are constructed from the 'raw' data using a
combination of CRC (cyclic redundancy checksum)
generation, Forward Error Correction coding and
Interleaving. Details of the message format handled by
the MX919 is shown in Figure 12; the format of the
MX929 is in Figure 13.
To reduce the processing load on the associated
!JController, the MX919/929 has been designed to
perform as much as possible of the computationally
intensive work involved in Frame formatting and deformatting and - when in receive mode - in searching for
and synchronizing onto the Frame Preamble. In normal
operation the modem will only require serviCing by the

!JControlier once per received or transmitted block.
Thus, to transmit a block, the controlling !JControlier
has only to load the -unformatted - 'raw' binary data into
the modem's Data Block Buffer then instruct the modem
to format and transmit that data. The modem will then
calculate and add the CRC bits as required, encode the
result as 4-level symbols (with Forward Error Correction
coding) and interleave the symbols before transmission.
In receive mode, the modem can be instructed to
assemble a block's worth of received symbols,
de-interleave the symbols, translate them to binary
-using the FEC coding to correct as many errors as
possible- and check the resulting CRC before plaCing the
received binary data into the Data Block Buffer for the
!JControlier to read.
The MX919/929 can also handle the transmission
and reception of unformatted data -to allow for example
the transmission of Symbol and Frame Synchronization
sequences or special test patterns.

Register Selection

The MX919 modem appears to the programmer as 4 write-only a-bit registers shadowed by 3 read-only registers.
Individual registers are selected by the Al and Ao inputs; see Read and Write cycle timing diagrams (Figure 26).

Table 1 Register Selection

Data Block Buffer
A 12-byte read/write buffer is used to transfer data (as opposed to Command, Status, Mode, Data-Quality and
Control information) between the modem and the controlling !JControlier.

The Data Block Buffer appears to the !JControlier as a single a-bit register; the modem ensures that sequential
!JControlier 'read' or 'write' actions to the buffer are routed to the correct locations within this buffer. When the modem
is in the TX mode, any attempt by the !JControlier to 'read' from this buffer will have no effect. Similarly, any attempt
to 'write' to this buffer will have no effect when the modem is in the RX mode.
Command Register
Writing to this register instructs the modem to perform a specific action or actions, depending upon the setting
of the TASK, AQLEV, and AQSC bits.

Figure 14 - The Command
Register

When it has no action to perform (but is not powersaved), the modem will be in an idle state, and if it is in the
TX mode the input to the TX Filter will be connected to a voltage mid-way between the '+1' and '-1' symbol Voltages.
In the RX mode the modem will continue to measure the received data quality and extract bits from the received
signal, feeding them into the De-Interleave Buffer, but will otherwise ignore the received data.
Page 114

MX-COM, INC.

MX919/MX929
Programming Information ..... .
Command Register

87
AQSC

86
AQLEV

Acquire Symbol Clock: This bit has no effect in the TX mode.
In the RX mode, whenever a byte with the AQSC bit set to logic '1' is written to the Command
Register, it initiates an automatic sequence designed to achieve timing synchronization with the
received signal as quickly as possible. This involves setting the Phase Locked Loop of the received
symbol-timing extraction circuits to its widest bandwidth, then gradually reducing the bandwidth as
timing synchronization is achieved, until it reaches the 'normal' value set by the PLLBW bits of the
Control Register.
Setting this bit to logic '0' (or changing it from '1' to '0') has no effect, however note that the
acquisition sequence will be restarted every time that a byte written to the Command Register has
the AQSC bit set to logic '1'. The AQSC bit will normally be set at the same time as a SFS (Search
for Frame Sync) or SFSH/SFP (Search for Frame Sync + Header for MX919 I Search for Frame
Preamble for MX929) task, however it may also be used independently to re-establish clock
synchronization quickly after a long fade. Alternatively, an SFS or SFSH/SFP task may be written
to the Command Register with the AQSC bit at logic '0' if it is known that clock synchronization does
not need to be re-established. Refer to the Operational Information section for further details.
Acquire Receive Signal Levels: This bit has no effect in the TX mode.
In receive mode, whenever a byte with the AQLEV bit set to a logiC '1' is written to the Command
Register, it initiates an automatic sequence designed to measure the amplitude and DC offset of the
received signal as rapidly as possible. This sequence involves setting the measurement circuits to
respond quickly at first, then gradually increasing their response time -hence improving the measurement
accuracy- until the 'normal' value set by the LEVRES bits of the Control Register is reached.
Setting this bit to a logic '0' (or changing it from '1' to '0') has no effect. Note that the acquisition
sequence will be re-started every time that a byte written to the Command Register has the AQLEV bit
set to a logic '1'.
The AQLEV bit will normally be set at the same time as an SFS (Search for Frame Sync) or SFSHI
SFP (Search for Frame Sync + Header for MX919 I Search for Frame Preamble for MX929) task is
initiated, however it may also be used independently to re-establish signal levels quickly after a long fade.
Alternatively, a SFS or SFSH/SFP task may be written to the Command Register with the AQLEV bit at
logic '0' if it is known that there is no need to re-establish the received signal levels. Refer to the
Operational Information section of this publication for further details.

85

84

These bits should each be set to a logic '0'.

83
82

81

80
TASK

Task: Operations such as transmitting a data block are treated by the modem as 'Tasks'. Information
on Task functions is given on the following pages.
A task is initiated when the IlControlier writes a byte to the Command Register with the Task bits set to
anything other than the 'NULL' ('0' '0' '0') code.
The IlControlier should not write a task (other than NULL or RESET) to the Command Register or write
to or read from the Data Buffer when the BFREE (Buffer Free) bit of the Status Register is a logic '0'.
Different tasks apply in receive and transmit modes.
TX Mode: All tasks other than NULL, RESET instruct the modem to transmit data from the Data Block
Buffer, formatting it as required. For these tasks the IlControlier should wait until the BFREE (Buffer Free)
bit of the Status Register is a logic '1 " before writing the data to the Data Block Buffer, then it should write
the desired task to the Command Register. If more than 1 byte needs to be written to the Data Block Buffer,
byte number '0' of the block should be written first.
Once the byte containing the desired task has been written to the Command Register, the modem
will: Set the BFREE (Buffer Free) bit of the Status Register to a logic '0', take the data from the Data Buffer
as quickly as it can -transferring it to the Interleave Buffer for eventual transmission. (continued ... )

MX-COM, INC.

Page 115

I

MX919/MX929
Programming Information ..... .

Task: ..••.• This operation will start immediately if the modem is 'idle' (Le. not transmitting data from a
previous taSk), otherwise it will be delayed until there is sufficient room in the Interleave Buffer. Once all
of the data has been transferred from the Data Block Buffer the modem will set the BFREE and IRQ bits
ofthe Status Register to a logic '1', (causing the IRQ outputto go low ifthe IRQEN bit ofthe Mode Register
has been set to a logic '1 ') to tell the IJControlier that it may write new data and the next task to the modem.
In this way the IJControlier can write a task -and the associated data- to the modem while the modem
is still transmitting the data from the previous task.
RX Mode: The IJControlier should wait until the BFREE bit of the Status Register is a logic '1', then
write the desired task to the Command Register. Once the byte containing the desired task has been
written to the Command Register, the modem will:
Set the BFREE bit of the Status Register to a logic '0'.
Wait until enough received bits are in the De-Interleave Buffer.
Decode them as needed, and transfer any resulting data to the Data Block Buffer.
Then the modem will set the BFREE and IRQ bits of the Status Register to logic '1', (causing the
IRQ output to go low if the IRQEN bit of the Mode Register has been set to a logic '1 ') to tell the
IJControlier that it may read from the Data Buffer and write the next task to the modem.
In this way the IJControlier can read data and write a new task to the modem while the received
symbols needed for this new task are being stored in the De-Interleave Buffer.

Ax In

IRQ Output
(lRQEN
'1')

=

Status Register IRQ Bit
Status Register BFREE Bit

= I for Task 1
L

for Task 2

L
S

S

~----~I------~~I______

~

~ Task 2

Task 1

Task from IlC to Command Register

_

Data from Data Block Buffer to mC

Task 1 data

Figure 15 - The Receive Process

Data from IlC to Data Block Buffer

_

Task 1 data

_

Task 2 data

Task from IlC to Command Register

'------IrS

Status Register BFREE Bit
Status Register IRQ Bit

~

IRQ Output
'1')
(IRQEN

=

Tx Out

- - - - - - -

....-:~-:::--:---------r-:---:::--:----,

from Task 1 _ _ _ _ _-'--'-_--'-_
from Task 2 _--'
_ _ _ _ _ _ _ ..J....--'--'-"--_

Figure 16 - The Transmit Process
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MX-COM, INC.

MX919IMX929
Programming Information ..... .
Modem Tasks in Detail
The following tables describe the setting and format of the Command Register 'task' bits (bits 2, 1 and 0). Note that
before a task is programmed the TXlRX bit in the Mode Register must be placed in the relevant position.

MX919 General Purpose Modem Tasks
Command
2
1
0
0
0
0
0
1
0
1
1
0
1
0

Bits
0
NULL
0
1
0
1
0
1
0
1

SFSH
RHB
RILB
SFS
R4S
1
1
NULL
1
1
RESET
Table 2 - MX919 Modem

Receive Mode

Transmit Mode

.. .... ..

Search for Frame Sync + Header
Read Header Block
Read Intermediate or Last Block
Search for Frame Sync
Read 4 Symbols
.. .... ..
Cancel any Current Action
Task Details

NULL
T24S
THB
TIB
TLB
T4S
NULL
RESET

.. .... . .

Transmit 24 Symbols
Transmit Header Block
Transmit Intermediate Block
Transmit Last Block
Transmit 4 Symbols
........
Cancel any Current Action

MX929 RDwLAP Modem Tasks
Command Bits
2' 1
0
0
0
0
1
0
0
1
0
0
1
0
1
1
0
0
1
0
1
1
1
0

NULL
SFP
RHB
RILB
SFS
R4S
RSIO
1
1 RESET
1
Table 3 - MX929 Modem

Receive Mode

Transmit Mode

.. .... ..

Search for Frame Preamble
Read Header Block
Read Intermediate or Last Block
Search for Frame Sync
Read 4 Symbols
Read Station 10
Cancel any Current Action
Task Details

MX919 Modem Tasks

NULL
T24S
THB
TIB
TLB
T4S
TSIO
RESET

........

Transmit 24 Symbols
Transmit Header Block
Transmit Intermediate Block
Transmit Last Block
Transmit 4 Symbols
Transmit Station 10
Cancel any Current Action

MX929 Modem Tasks

NULL

No Effect. This task is provided so that an
AQSC or AQLEV (Command Register)
command can be initiated without loading
a new task.

NULL

No Effect. This task is provided so that an
AQSC or AQLEV (Command Register)
command can be initiated without loading
a new task.

SFSH

Search for Frame Sync + Header Block.
Causes the MX919 to search the received
signal for a valid 24-symbol Frame Sync
sequence followed by a Header Block
which has a correct CRC1 checksum.

SFP

Search for Frame Preamble. Causes the

This task continues until a valid Frame
Sync + Header Block has been found.

MX929 to search the received signal for a
valid RO-LAP Frame Preamble, consisting
of a 24-symbol Frame Sync sequence
followed by Station 10 data which has a
correct CRCO checksum.
This task continues until a valid Frame
Preamble has been found.

The search consists of two stages:
1. The MX919 will attempt to match the
incoming symbols against the
General Purpose Modem Frame
Synchronization pattern to within

MX-COM, INC.

The search consists of four stages:
1. The MX929 will attempt to match the
incoming symbols against the ROLAP Frame Synchronization pattern

Page 117

I

MX919/MX929
Programming Information ..... .

I

the tolerance defined by the Frame
Sync Tolerance (FSTOL) bits of the
Control Register.

to within the tolerance defined by the
Frame Sync Tolerance (FSTOL) bits
of the Control Register

2. Once a match has been found, the
MX919 will read the next 66 symbols
as if they were a 'Header' block,
decoding the symbols and checking
the CRC1 checksum. If the CRC1
checksum is incorrect the modem
will resume the search, looking for a
fresh Frame Sync pattern. If the
CRC1 is correct, the 10 decoded
data bytes will be placed into the
Data Block Buffer, the BFREE and
IRQ bits of the Status Register will
be set high to a logic '1' and the CRC
Checksum Error (CRCERR) bit
cleared low to a logic '0'.

2. Once a match has been found, the
MX929 will read the next'S' symbol,
then update the SVAL bits of the
Status Register and set the SRDY bit
to '1'. (The IRQ bit of the Status
Register will also be set to '1' at this
time if the SSIEN bit of the Mode
Register is '1'.)
3. The MX929 will then read the next 22
symbols as Station 10 data. The 22
Station 10 symbols will be decoded
and the CRCO checked. If this is
incorrect the MX929 will resume the
search, looking for a fresh Frame
Sync pattern.

On detecting that the BFREE bit of the
Status Register has gone to a logic '0', the
I1Controlier should read the 10 bytes from
the Data Block Buffer and then write the
next task to the MX919's Command
Register.
RHB

Read Header Block. Causes the MX919
to read the next 66 symbols as a 'Header'
block, decoding them, placing the
resulting 10 data bytes and the 2 received
CRC bytes into the Data Block Buffer, and
setting the BFREE and IRQ bits of the
Status Register high to a logic '1' when the
task is complete to indicate that the
I1Controlier may read the data from the
Data Block Buffer and write the next task
to the modem's Command Register.

The CRCERR bit of the Status Register
will be set to a logic '1' or '0' depending on
the validity of the received CRC1
checksum bytes.

4. If the received CRCO is correct, the
next'S' symbol will be read, the
SVAL bits of the Status Register
updated and the SRDY, BFREE and
IRQ bits set to a logic '1'. The CRC
Checksum Error (CRCERR) bit will
be cleared to a logic '0', and the three
decoded Station 10 bytes placed into
the Data Block Buffer.
On detecting that the BFREE bit of the
Status Register has gone to a logic '1', the
I1Controlier should read the 3 Station 10
bytes from the Data Block Buffer and then
write the next task to the MX929's's
Command Register.
RHB

Read Header Block. Causes the MX929
to read the next 69 symbols as a 'Header'
block. It will strip out the'S' symbols, then
de-interleave and decode the remaining
66 symbols, placing the resulting 10 data
bytes into the Data Block Buffer. It also
sets the BFREE and IRQ bits of the Status
Register to a logic '1' when the task is
complete to indicate that the I1Controlier
may read the data from the Data Block
Buffer and write the next task to the
modem's Command Register.

The CRCERR bit of the Status Register
will be set to a logic '1' or '0' depending on

Page 118

MX-COM, INC.

MX919/MX929
Programming Information ..... .

RILB

MX919 Modem Tasks

MX929 Modem Tasks

Read 'Intermediate' or 'Last' Block.
Causes the modem to read the next 66
symbols as an 'Intermediate' or 'Last'
block (the IlControlier should be able to tell
from the received 'Header' block how
many blocks are in the frame, and hence
when to receive the 'Last' block).

the validity of the received CRC1
checksum bytes.

In each case, the modem will decode the
66 symbols and place the resulting 12
bytes into the Data Block Buffer, setting
the BFREE and IRQ bits of the Status
Register high to a logic '1' when the task is
complete to indicate that the IlControlier
may read the data from the Data Block
Buffer and write the next task to the
modem's Command Register. If an
'Intermediate Block is received then the
IlControlier should read-out all 12 bytes
from the Data Block Buffer and ignore the
CRCERR bit of the Status Register, for a
'Last' block the IlControlier need only read
the first 8 bytes from the Data Block Buffer,
and the CRCERR bit in the Status Register
will reflect the validity of the received
CRC2 checksum. Note that in the RX
mode the CRC2 checksum circuits are
initialized on completion of any task other
than NULL or RILB.

As each of the 3 'S' symbols of a block is
received, the SVAL bits of the Status
Register will be updated and the SRDY bit
set to '1 '. (If the SSIEN bit of the Mode
Register is '1' the Status Register IRQ bit
will also be set to '1 '.)
RILB

Read 'Intermediate' or 'Last' Block.
Causes the modem to read the next 69
symbols as an 'Intermediate' or 'Last'
block (the IlControlier should be able to tell
from the received 'Header' block how
many blocks are in the frame, and hence
when to receive the 'Last' block).
In each case, the MX929 will strip out the
3 'S' symbols, de-interleave and decode
the remaining 66 symbols and place the
resulting 12 bytes into the Data Block
Buffer. The BFREE and IRQ bits of the
Status Register are set to a logic '1' when
the task is complete to indicate that the
IlControlier may read the data from the
Data Block Buffer and write the next task
to the MX929's Command Register.
If an 'Intermediate Block is received then
the IlControlier should read all 12 bytes
from the Data Block Buffer and ignore the
CRCERR bit of the Status Register. For a
'Last' block the IlControlier needs only to
read the first 8 bytes from the Data Block
Buffer, and the CRCERR bit in the Status
Register will reflect the validity of the
received CRC2 checksum. Note that in the
RX mode the CRC2 checksum circuits are
initialized on completion of any task other
than NULL or RILB.
As each of the 3 'S' symbols of a block is
received, the SVAL bits of the Status
Register will be updated and the SRDY bit
set to '1'. (If the SSIEN bit of the Mode
Register is '1' the Status Register IRQ bit
will also be set to '1 '.) Note that when the
third'S' symbol is received the SRDY bit
will be set to '1' at the same time the
BFREE bit is set to '1'.

MX-COM, INC.

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MX919IMX929
Programming Information ..... .

SFS

I

Search for Frame Sync. Causes the
MX919 to search the received signal for a
24-symbol sequence which matches the
Frame Synchronization pattern to within the
tolerance defined by the FSTOL bits of the
Mode Register.

SFS

SFS causes the MX929 to search the
received signal for a 24-symbol sequence
which matches the RD-LAP Frame
Synchronization pattern to within the
tolerance defined by the FSTOL bits of the
Mode Register.

When a match is found the modem will set
the BFREE and IRQ bits of the Status
Register high to a logic '1' to indicate to the
IJControlier that it should write the next task
to the Command Register.

R4S

Read 4 Symbols. This task is intended for
special tests and channel monitoring perhaps preceded by an SFS task. Causes
the modem to read the next 4 symbols and
translate them directly (without deinterleaving or FEC) to an a-bit byte which is
placed into the Data Block Buffer. The
BFREE and IRQ bits of the Status Register
will then be set high to a logic '1' to indicate
that the IlControlier may read the data byte
from the Data Block Buffer and write the next
task to the Command Register.

Search for Frame Sync. This task is
intended for special test and channel
monitoring purposes. It performs the first
two parts of an SFP task.

When a match is found the MX929 will read
the following'S' symbol, then set the
BFREE, IRQ and SRDY bits of the Status
Register to a logic '1' and update the SVAL
bits. The IJControlier may then write the next
task to the Command Register.

R4S

Read 4 Symbols. This task is intended for
special test and channel monitoring
purposes, perhaps preceded by an SFS
task. It causes the MX929 to read the next
4 symbols and translate them directly
(without de-interleaving or FEe) to an a-bit
byte which is placed into the Data Block
Buffer. The BFREE and IRQ bits of the
Status Register will then be set to a logic '1'
to indicate that the IJControlier may read the
data byte from the Data Block Buffer and
write the next task to the Command
Register.

RSID

Read Station 10. This task causes the
MX929 to read and decode the next 23
symbols as Station ID data followed by an'S'
symbol. It is similar to the last two parts of an
SFP task except that it will not re-start if the
received CRCO is incorrect. It normally
follows an SFS operation.
The decoded System, Domain and Base ID
bytes will be placed into the Data Buffer, and
the CRCERR bit of the Status Register will
be set to '1' if the received CRCO is incorrect.
Otherwise it will be cleared to '0'. The SVAL
bits of the Status Register will be updated
and the BFREE, SRDY and IRQ bits will be
set to '1' to indicate that the IJ-C may read the
3 Station ID bytes from the Data Block Buffer
and write the next task to the MX929's
Command Register.

Page 120

MX-COM, INC.

MX919/MX929
Programming Information ......
MX919 Modem Tasks
T24S

Transmit 24 Symbols. This task, which is
intended to facilitate the transmission of
Symbol and Frame Sync patterns as well as
special test sequences, takes 6 bytes of data
from the Data Block Buffer and transmits
them as 24 4-level symbols without any CRC
or FEC.

MX929 Modem Tasks
T24S

Byte '0' of the Data Block Buffer is sent first,
byte '5' last.

Byte '0' of the Data Block Buffer is sent first,
byte '5' last.

Once the modem has has read all the data
bytes from the Data Block Buffer, the
BFREE and IRQ bits of the Status Register
will be set high to a logic '1', indicating to the
IJControlier that it may write the next task and
its data to the modem.

Once the MX929 has has read all the data
bytes from the Data Block Buffer, the
BFREE and IRQ bits of the Status Register
will be set to a logic '1', indicating to the
IJControlier that it may write the next task and
its data to the modem.

Table 4 shows what data has to be written to
the Data Block Buffer to transmitthe modem
Symbol and Frame Sync Sequences.
THB

Transmit Header Block. Takes 10 bytes
of data (Address & Control) from the Data
Block Buffer, calculates and appends the
2-byte CRC1 checksum, translates the
result to 4-level symbols (with FEC),
interleaves the symbols and transmits the
result as a formatted 'Header' Block.

Table 5 shows what data has to be written to
the Data Block Buffer to transmit the modem
Symbol and Frame Sync Sequences.
THB

Once the modem has read the data bytes
from the Data Block Buffer, the BFREE
and IRQ bits of the Status Register will be
set high to a logic '1', indicating to the
IJControlier that it may write the next task
and its data to the modem.
TIB

Transmit Intermediate Block. Takes 12
bytes of data from the Data Block Buffer,
updates the 4-byte CRC2 checksum for
inclusion in the 'Last' block, translates the
12 data bytes to 4-level symbols (with
FEC), interleaves the symbols and
transmits the result as a formatted
'Intermediate' Block. Once the modem
has read the data bytes from the Data
Block Buffer, the BFREE and IRQ bits of
the Status Register will be set high to a
logic '1', indicating to the IJControlier that
it may write the next task and its data to the
modem.

Note that in TX mode the CRC2 checksum
circuits are initialized on completion of any

MX-COM, INC.

Transmit 24 Symbols. This task, which is
intended to facilitate the transmission of
Symbol and Frame Sync patterns as well as
special test sequences, takes 6 bytes of data
from the Data Block Buffer and transmits
them as 24 4-level symbols without any CRC
or FEC, interleaving or adding any'S'
symbols.

Transmit Header Block. Takes 10 bytes of
data (Address & Control) from the Data
Block Buffer, calculates and appends the
2-byte CRC1 checksum, translates the
result to 4-level symbols (with FEC),
interleaves the symbols and transmits the
result as a formatted 'Header' Block,
inserting'S' symbols at 22-symbol
intervals.

Once the modem has read the data bytes
from the Data Block Buffer, the BFREE
and IRQ bits of the Status Register will be
set to a logic '1', indicating to the
IJControlier that it may write the next task
and its data to the modem.
TIB

Transmit Intermediate Block. Takes 12
bytes of data from the Data Block Buffer,
updates the 4-byte CRC2 checksum for
inclusion in the 'Last' block, translates the
12 data bytes to 4-level symbols (with
FEC), interleaves the symbols and
transmits the result as an RD-LAP
formatted 'Intermediate' Block, inserting
'S' symbols at 22-symbol intervals.

Once the MX929 has read the data bytes
from the Data Block Buffer, the BFREE
and IRQ bits of the Status Register will be
set to a logic '1', indicating to the

Page 121

I

MX919/MX929
Programming Information ..... .
MX919 Symbol and Frame Sync Sequences

-3
-3
-3
-3
-3
-3

Byte 0:
Byte 1 :
Byte 2:
Byte 3:
Byte 4 :
Byte 5:

11110101
11110101
11110101
11110101
11110101
11110101

F5
F5
F5
F5
F5
F5

-1 +1 -1 +1
-1 +3 -3 +3
-3 -1 +1 -3
+3 +3 -1 +1
-3 -3 +1 +3
-1 -3 +1 +3

Byte 0 :
Byte 1 :
Byte 2 :
Byte 3 :
Byte 4:
Byte 5 :

00100010
00110111
01001001
11110010
01011011
00011011

22
37
49
F2
5B
1B

+3
+3
+3
+3
+3
+3

I

+3
+3
+3
+3
+3
+3

-3
-3
-3
-3
-3
-3

Table 4 - MX919 Symbol and Frame Sync Sequences (T24S)

MX929 Symbol and Frame Sync Sequences

-3
-3
-3
-3
-3
+3

Byte 0:
Byte 1 :
Byte 2 :
Byte 3 :
Byte 4 :
Byte 5:

11110101
11110101
11110101
11110101
11110101
01011111

F5
F5
F5
F5
F5
5F

-1 +1 -1 +1
-1 +3 -3 +3
-3 -1 +1 -3
+3 +3 -1 +1
-3 -3 +1 +3
-1 -3 +1 +3

Byte 0:
Byte 1 :
Byte 2 :
Byte 3 :
Byte 4:
Byte 5:

00100010
00110111
01001001
11110010
01011011
00011011

22
37
49
F2
5B
1B

+3
+3
+3
+3
+3
-3

+3
+3
+3
+3
+3
-3

-3
-3
-3
-3
-3
+3

Table 5 - MX929 Symbol and Frame Sync Sequences (T24S)

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MX-COM, INC.

MX919/MX929
Programming Information ..... .

TLB

MX919 Modem Tasks

MX929 Modem Tasks

task other than NULL, TIB or TLB.

IJControlier that it may write the next task
and its data to the modem.

Transmit 'Last' Block. Takes 8 bytes of
data from the Data Block Buffer, updates
and appends the 4-byte CRC2 checksum,
translates the resulting 12-bytes to 4-level
symbols with (FEC), interleaves the
symbols and transmits the result as a
formatted 'Last' Block. Once the modem
has read the data bytes from the Data
Block Buffer, the BFREE and IRQ bits of
the Status Register will be set high to a
logic '1', indicating to the IJControlier that
it may write the next task and its data to the
modem.

Note that in TX mode the CRC2 checksum
circuits are initialized on completion of any
task other than NULL, TIB or TLB.

T4S

Transmit 4 Symbols. This task is similar
to T24S but takes only one byte from the
Data Block Buffer, transmitting it as four 4level symbols.

RESET

RESET. Stop any current action. This
'task' takes effect immediately, and
terminates any current action (task, AQSC
or AQLEV) the modem may be performing
and sets the BFREE bit of the Status
Register high to a logic '1', without setting
the IRQ bit. RESET should be used to set
the modem into a known state when V DD is
applied.

TLB

Transmit 'Last' Block. Takes 8 bytes of
data from the Data Block Buffer, updates
and appends the 4-byte CRC2 checksum,
translates the resulting 12-bytes to 4-level
symbols with (FEC), interleaves the
symbols and transmits the result as an RDLAP formatted 'Last' Block, inserting'S'
symbols at 22-symbol intervals.
Once the modem has read the data bytes
from the Data Block Buffer, the BFREE
and IRQ bits of the Status Register will be
set to a logic '1', indicating to the
IJControlier that it may write the next task
and its data to the modem.

T4S

Transmit 4 Symbols. This task is similar
to T24S but takes only one byte from the
Data Block Buffer, transmitting it as four 4level symbols.

TSID

Transmit Station ID. This task takes 3 ID
bytes from the Data Block Buffer,
calculates and appends the 6-bit CRCO
checksum, translates the result to 4-level
symbols (with FEC) and transmits the
resulting 22 symbols preceded and
followed by'S' symbols.

RESET

RESET. Stop any current action. This
'task' takes effect immediately, and
terminates any current action (task, AQSC
or AQLEV) the MX929 may be performing
and sets the BFREE bit of the Status
Register high to a logic '1', without setting
the IRQ bit. RESET should be used to set
the modem into a known state when VDD is
applied.

Note that due to delays in the transmit filter,
it will take several symbol-times for any
change to become apparent at the TXOp
pin.

Note: due to delays in the transmit filter, it
will take several symbol-times for any
change to become apparent at the TXOp
pin.

MX-COM, INC.

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MX919/MX929
Programming Information ..... .
RRC Filter Delay
The Task Timing figures detailed in Tables 6 and 7 are based upon: the signal at the input to the RRC Filter in
the transmit mode, or the signal at the input to the de-interleave circuits in the receive mode. As can be seen
from the diagram in Figure 17, there is an additional delay of approximately 8 (eight) symbol-times in both TX
and RX modes due to the (TXlRX) RRC Filter.

I
Transmit and Receive Task Timing
Data to Data Block Buffer
Task to Command Register

OJ
I

1

IBEMPTY Bit
BFREE Bit

Symbols to RRC Filter

from Task 1

from Task 2

from Task 3

I--

Modem Tx Output

Figure 18 - MX9191929 TX Task Timing Diagram

Modem Rx Input
Symbols to
De-Interleave Circuit

Data from Data Block Buffer
Task to Command Register

BFREE

B~

Figure 19 - MX9191929 RX Task Timing Diagram
Page 124

MX-COM, INC.

MX919/MX929
MX919 Timing
Timing

Notes

t1

Modem in idle state. Time from writing first task to the application of the
first TX symbol to the RRC Filter.

t2

Time from the application of the first symbol of the task to the RRC Filter
until BFREE goes to a logic '1' (high).

Task

Typical
(Symbol) Time

Any

1

T24SfTSID
TH BfTI BfTLB
T4S

5
16
1

T24S
THBfTlBfTLB
RHB/RILB
T4S
SFS
SFSH
R4S

24
66
66
4
<24
<90
4

T24S
THBfTlBfTLB
T4S

18
49
2

SFSH
RHB/RILB
SFS
R4S

21
49
21
3

Any

1

Task

Typical
(Symbol) Time

Any

1

T24SfTSID
THBfTlBfTLB
T4S

5
16
1
24
69
23
69
4
<48
<25

-

t3

Time to transmit all symbols of the task.
or
Time to receive all symbols of the task

t4

Maximum time allowed from BFREE going to a logic '1' for the next task
(and data) to be written to the modem.

t6

Maximum time between the first symbol of the task entering the
de-interleave circuit and the task being written to the modem.

t7

Time from last symbol of task entering the de-interleave circuit to BFREE
going to a logic '1'.

Table 6 - Typical RXlTX Task Load Timings (MX919)

MX929 Timing
Timing Notes
t1

Modem in idle state. Time from writing first task to the application of the
first TX symbol to the RRC Filter.

t2

Time from the application of the first symbol of the task to the RRC Filter
until BFREE goes to a logic '1' (high).

t3

Time to transmit all symbols of the task.
or
Time to receive all symbols of the task

T24SfTSID
THBfTlBfTLB
RSID
RHB/RILB
T4S/R4S
SFP
SFS

t4

Maximum time allowed from BFREE going to a logic '1' for the next task
(and data) to be written to the modem.

T24S
THBfTlBfTLB
TSID
T4S

18
52
18
2

t6

Maximum time between the first symbol of the task entering the
de-interleave circuit and the task being written to the modem.

SFP/SFS
RHB/RILB
RSID
R4S

21
51
15
3

t7

Time from last symbol of task entering the de-interleave circuit to BFREE
going to a logic '1'.

Any

1

Table 7 - Typical RXlTX Task Load Timings (MX929)

MX-COM, INC.

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MX919IMX929
Programming Information ......
Control Register
This 8-bit write-only register controls the modem's symbol-rate, the response times of the receive clock
extraction and signal level measurement circuits and the Frame Sync pattern recognition tolerance.

Figure 20 - The Control Register

I
Table 8 shows how bit-rates of 2400/4800/9600 symbols per second may be obtained from common
Xtallclock frequencies. The values of C3 and C4 should be suitable for the frequency of the Xtal X,.
For X, < 5.0MHz, C3 = C4 = 33.0pF; for X, > 5.0MHz, C3 = C4 = 18.0pF.

Xtal Frequency (MHz)

2.4576

87
0
0
1
1

86
0
1
0
1

Division Ratio
Xtal Freq.
Symbol Rate
512
1024
2048
4096

Table 8 - Clock/Data Rates

4.9152

9.8304

Symbol Rate (symbols/sec.)
4800
2400

9600
4800
2400

9600
4800
1200

Note that device operation is not guaranteed or specified above 9.600symbolsls or below 2.400symbolsls

Frame Sync Tolerance: For use in the RX mode only; these bits have no effect in the RX
mode. These bits define the maximum number of mismatches which will be allowed during a
search for the Frame Sync pattern:

85 84
o 0

o

Mismatches Allowed

0

1
2
104
1
1
6
Note that a single 'mismatch' is defined as the difference between two adjacent symbol levels;
if the symbol '+1' were expected, then the received symbol values of '+3' and '-1' would count
as 1 mismatch, a received symbol value of '-3' would count as 2.
+3
+1

-1
-3
Symbol Levels
Page 126

MX-COM, INC.

MX919/MX929
Programming Information ......
Control Register ......
B3,B2
LEVRES

Level Measurement Response Time: These bits are only used in the RX mode and have no effect
in the TX mode; they set the 'normal' response time of the RX signal amplitude and dc offset
measuring circuits. This setting will be temporarily overriden by the automatic sequencing of an
AQLEV command.
For most general-purpose applications using this modem, these bits should normally be set to 'Peak
Averaging', except when the jJController detects a receive signal fade, when 'Hold' should be
selected. The 'Peak Detect' setting is intended for systems where the jJController cannot detect
signal fades or the start of a received message; this setting allows the modem to respond quickly
to fresh messages and recover rapidly after a fade without jJController intervention -this however
will be at the cost of reduced Bit-Error-Rate vs Signal-to-Noise performance.
The Signal Average setting is a test mode and should not normally be used.
Note that as the measured levels are stored on capacitors C e and C 7 via pins Doc 1 and Doc 2, these
levels will decay gradually towards V BIAS when the 'Hold' setting is used; the discharge time-constant
is approximately 1000 symbol-times.
Table 9 details the bit-setting application.
B3

o
o
1

B2

0
1

0

1
1
Table 9
81,80
PLL8W

Setting
Hold
Peak Averaging
Peak Detect
Signal Average

Action
Keep current values of amplitude and offset
Track input signal using bit peak averaging
Track input signal using peak detection
Measure average signal level

PLL Bandwidth: For use in the RX mode only (no effect in TX).
In the receive mode these two bits set the 'normal' bandwidth of the RX Clock Extraction Phase
Locked Loop circuit. This setting will be temporarily overridden by the automatic sequence of an
AQSC (Command Register Bit 7) command.

B1

o
o
1

BO

0
1

0

1
1
Table 10

PLL Bandwidth (±ppm)
o (Hold)
30
250
50,000

Note
For use during signal fades

The 'Hold' setting is intended for use during signal fades otherwise the minimum bandwidth
consistent with the RX and TX modem symbol-rate tolerances should be chosen, Le. if the Xtals
used with both modems have accuracies of ±100ppm, the PLLBW bits (B1, BO) should be set to
'1', '0',
The very wide bandwidth ('1', '1') is intended for systems where the jJController cannot detect signal
fades or the start of a receive message; it allows the modem to respond rapidly to fresh messages
and recover rapidly after a fade without jJController intervention. This action however is at the
expense of reduced Bit-Error-Rate vs Signal-to-Noise performance.
Note that PLL bandwidth figures are intended for 'a reasonably random received signa/.'

MX-COM, INC.

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I

MX919/MX929
Programming Information ..... .
Mode Register
This 8-bit write-only register controls the basic operating modes of the modem.

Figure 21 - The Mode Register

':a7

•

IFlQEN'.

IRQ Output Enable: When set to a logic '1' the Interrupt Request output will low (logic '0')
whenever the IRQ bit (BIT 7) of the Status Register is set by the modem to a logic '1'.
When set to a logic '0' the Interrupt Request output will not function and will remain in its highimpedance state (see Pin Functions and Figure 11 - jJControlier Interface).
Invert Symbols: Controls the polarity (sense) inversion of transmitted and received symbol voltages.
86
Symbol
Signal at TX Out
Signal at RX Feedback
'0'
'+3'
above V BIAS
below VBIAS
'0'
'-3'
below VBIAS
above VBIAS
'1'
'+3'
below VBIAS
above VBIAS
'1'
'-3'
above V BIAS
below VBIAS
TXlRX Mode: When set to a logic '1' places the modem in the Transmit mode; when set to a logic
'0' places the modem in the Receive mode. Note that changing between Transmit and Receive
modes will cancel any current task.
Show RX Eye: This bit should be set to a logic '0' for normal RX operation and always for TX
operation. Setting this bit to a logic '1' in the receive mode configures the modem into a special test
mode, in which the input to the TX Output Buffer is connected to the RX Symbol/Clock Extraction
circuit at a point which carries the equalized receive signal. This may be monitored with an
oscilloscope (at the TX Out pin before the external RC filter), to assess the quality of the complete
radio channel including the TX and RX modem filters, the TX modulator and the RX IF filters and
FM demodulator. The resulting 'eye' diagram (for reasonably random data) should ideally be as
shown in Figure 7, with 4 'crisp' and equally spaced crossings.
Powersave: When set to a logic '1' places the modem in its Powersave mode. In this mode the
following circuits only are disabled: Internal Filters, RX Symbol and Clock Extraction Circuits and
the TX Output Buffer; the TX Out pin is connected to V BIAS through a high-value resistance.
Xtal oscillator circuits and the jJControlier Interface logic and the RX Input Amplifier continue to
operate. Note that RX clock and levels will be lost if Powersave mode is selected.
Setting to a logic '0' restores power to all of the device circuitry and the modem is in its operational
mode. Note that the internal filters -and hence the TX Out pin in the TX mode- will take about 20
symbol-times to settle after this bit is taken from a logic '1' to '0'.

•. '"i·< •.·· " . '

..... : • '.• ' .

'S' Symbol IRQ Enable (MX929 only): In Receive mode, setting this bit to '1' causes the IRQ
bit of the Status Register to be set to '1' whenever a new'S' symbol has been received. (The SRDY
bit of the Status Register will be set to '1' at the same time, and the SVAL bits updated to reflect
the received'S' symbol.) In Transmit mode, setting this bit to '1' causes the IRQ bit of the Status
Register to be set to '1' whenever an'S' symbol has been transmitted. (The SRDY bit of the Status
Register will be set to '1' at the same time).
On the MX919, this bit should always be set to a logic '0'.
'S' Symbol to be Transmitted (MX929 only): For the MX929, these bits have no effect in RX
mode. In Transmit mode, these bits define the next'S' symbol to be transmitted.
On the MX919, these bits should always be set to a logic '0'.

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MX-COM, INC.

MX919/MX929
Programming Information ..... .
Status Register
This register may be read by the

~Controller

to determine the current state of the modem.

Status Register

Figure 22 - The Status Register
IRQ

IBEMPTY

CRCERR

I

SVAL'
'MX929 ONLY.
Read as 0 0 0 on MX919

Status Register
B7
IRQ

Interrupt Request: This bit is set to a logic '1' by:
The Status Register BFREE bit going from a logic '0' to '1', unless this transition is caused
by a RESET Task or by a change to the Mode Register's PSAVE or TXlRX bits.
or

The Status Register IBEMPTY bit going from a logic '0' to '1', unless this transition is
caused by a RESET Task or by a change to the Mode Register's PSAVE or TXlRX bits.
or

The Status Register DIBOVF bit going from a logic '0' to '1'.
This (IRQ) bit is cleared to a logic '0' immediately after a read of the Status Register.
If the IRQEN bit of the Mode Register is a logic '1', the MX919/929 IRQ output pin will be pulled
low (to Vss) whenever the Status Register IRQ bit is a logic '1'.

B6
BFREE

B5
IBEMPTY

MX-COM, INC.

Data Block Buffer Free: BFREE reflects the availability of the Data Block Buffer; BFREE is
cleared to a logic '0' (Buffer NOT Free) whenever a task other than NULL or RESET is written to
the Command Register.
In Transmit mode, the BFREE bit will be set to a logic '1' (also setting the Status Register IRQ
bit to a logic '1) when the modem is ready for the ~Controller to write new data to the Data Block
Buffer and the next task to the Command Register.
In Receive mode, the BFREE bit is set to a logic '1' (also setting the Status Register IRQ bit to
a logic '1) by the modem when it has completed a task and any data associated with that task has
been placed into the Data Block Buffer. The ~Controller may then read that data and write the next
task to the Command Register.
The BFREE bit is also set to a logic '1' -but without setting the IRQ bit- by a RESET task or when
the Mode Register PSAVE or TXlRX bits are changed.
Interleave Buffer Empty: In Transmit mode, IBEMPTY is set to a logic '1' (also setting the IRQ
bit) when less than two symbols remain in the Interleave Buffer or the Interleave Buffer is empty.
Any transmit task written to the modem after IBEMPTY goes to a logic '1' will be too late to avoid
a gap in the transmit output signal (see Figure 18 and Tables 6 & 7, TX Task Timing)
IBEMPTY is also set to a logic '1' by a RESET task and by a change of the Mode Register PSAVE
or TXlRX bits, but in these cases the IRQ bit will not be set.
IBEMPTY is cleared to a logiC '0' within 1-symbol time after a task other than NULL or RESET is
written to the Command Register.
Note that when the modem is in the transmit mode and the Interleave Buffer is empty, a mid-level
(half-way between '+1' and '-1') will be fed to the RRCFilter.
In Receive mode this bit is a logic '0'.

Page 129

MX919IMX929

Programming Information ..... .

De-Interleave Buffer Overflow: In Receive mode DIBOVF is set to a logic '1' (also setting the
IRQ bit) when an RHB, RILB, RSID or R4S task is written to the Command Register too late to allow
continuous reception (see Figure 19 and Tables 6 & 7, RX Task Timing).
DIBVOF is cleared to a logic '0' by reading the Status Register, by writing a RESET task to the
Command Register or by changing the PSAVE or TXlRX bits of the Mode Register.
In Transmit mode this bit is a logic '0'.

I

CRC Checksum Error: In Receive mode CRCFEC will be updated at the end of an SFSH, RHB,
or RILB task to reflect the result of the receive CRC check.
A logic '0' indicates that the CRC was received correctly. A logic '1 ' indicates that an error is present.
Note that this bit should be ignored when an 'Intermediate' block (which does not have an integral
CRG) is received.
CRCERR is cleared to a logic '0' by a RESET task, or by changing the PSAVE or TXlRX bits of the
Mode Register.
In Transmit mode this bit is a logic '0'.
'5' Symbol Ready (MX929 only): In Receive mode, this bit is set to '1' whenever an'S' symbol
has been received. The IlC may then read the value of the symbol from the SVAL field of the Status
Register.
In Transmit mode, this bit is set to '1' whenever an'S' symbol has been transmitted. The bit is
cleared to '0' by a read of the Status Register, by a RESET task or by changing the PSAVE or
TXRXN bits of the Mode Register.
On the MX919, this bit should always be set to a logic '0'.
Received '5' Symbol Value (MX929 only): In Receive mode, these bits reflect the value of the
latest received'S' symbol. In Transmit mode, these bits will be '0'.
On the MX919, these bits should always be set to a logic '0'.

The Data Quality Register
In Receive Mode, the modem continuously measures the quality of the received signal by comparing the actual
received waveform over the previous 64 symbol times against an internally generated "ideal". The result is placed into
bits 3 to 7 of the Data Quality Register for the !JControlier to read at any time, bits 0 to 2 being always set to '0'. Figure
22 shows how the value (0 to 255) read from the Data Quality Register varies with the received signal-to-noise ratio. In
Transmit Mode all bits are set to a logic '0'.
250

g>

J

200

i
I

150

/

~

;;;

8

100

~
50

o

l--/

5

7

/
9

/

11

~

13

15

Signal-!o·Noise Ratio (dB) [noise in 2 x symbol-rate bandwidth]

Figure 22 - Typical Data Quality Reading vs RX Signal-to-Noise Ratio
Page 130

MX-COM, INC.

MX919/MX929
Programming Information ..... .
MX919 & MX929 Modem Register Selection
The following diagram is a quick-reference to MX919IMX929 register allocations. The MX919/MX929 modem
appears to the programmer as 4 write-only a-bit registers shadowed by 3 read-only registers. Individual registers
are selected by the Aj and Ao inputs.

Register
Write to Modem

Aj

Data Block Buffer
Command Register
Control Register
Mode Register

Command

-

Register

I

I

AOSC AOLEV

o
1
1
1
1

0
1
0
1
0
1
0
1

NULL
SFSH
RHB
RILB
SFS
R4S
NULL
RESET

Reserved

set to 0 0 0

TASK

Levels

Search For Frame Sync + Head
Read Header Block
Read Intermediate or Last Block
Search For Frame Sync
Read 4 Symbols
Cancel any Current Action

82 81 80 TX Mode
o 0 0 NULL
001T24S
o 1 0 THB
o 1 1 TIB
1 0 0 TLB
1 0 1 T4S
1 1 0 NULL
1 1 1 RESET

Transmit
Transmit
Transmit
Transmit
Transmit

-

I

Register

CKDIV

FSTOL

LEVRES

PLLBW

CKDIV
Clock Division Ratio
FSTOL
Frame Sync Tolerance
LEVRES - Level Measurement Response
B3
B2
o 0 Hold
o
1
Peak Averaging
1
0
Peak Detect
1
1
Signal Average
PLLBW - PLL Bandwidth
B1
BO Bandwidth (+/-ppm)
o 0 0 (Hold)
o 1 30
1
0
250
1
1
50,000

lime

24 Symbols
Header Block
Intermediate Block
Last Block
4 Symbols

Cancel any Current Action

SSYM'

IRQEN
INVSYM
TXlRX
RXEYE
PSAVE
*SSIEN
*SSYM

I--

Modem

Data Block Buffer
Status Register
DQ Register
not used

0

82 81 80 RX Mode
0
0
1
1
0
0
1
1

Read from

IIL-_+_---O

AQSC - Acquire Symbol Clack
AQLEV - Acquire Receive Signal
TASK:

o
o
o

Ao
0
1
0
1

Control

171615413121
I

0
0
1
1

Selection

IRQ Output Enable
Invert Symbol
Transmit or Receive Mode
Show RX Eye
Powersave
S Symbol IRQ Enable (MX929 only)
S Symbol to TX (MX929 only)

*Bits 2, 1 and 0 are all set to '0' for MX919

IRa

IRQ
BFREE
IBEMPTY
DIBOVF
CRCERR
*SRDY
·SVAL

IBEMPTY

cReERR

SVAL'

- Interrupt Request
- Data Block Buffer Free
- Interleave Buffer Empty
- De-Interleave Buffer Overflow
- eRC Checksum Error
- S Symbol Ready (MX929 only)
- Received S Symbol Value (MX929 only)

*Bits 2, 1 and 0 are all held to '0' for MX919

Data Block Buffer A 12-byte read/write buffer used to hold and transfer receive or transmit data to or from the
controlling IJControlier.
DQ (Data Quality) Register The information presented in this 8-bit register is intended to indicate the 'quality' of
the received signal.

Figure 23 - Ready-Use Guide to Register Functions

MX-COM, INC.

Page 131

MX919/MX929

Operational Information
MX919/929 "Transmit Frame" Example
The operations needed to transmit a single Frame consisting of Symbol and Frame Sync sequences and one each
Header, Intermediate and Last blocks are shown in Figure 24 (below).

MX919 out of Powersave
SettoTX
Interrupt Enable as required
RXEYE disabled
Invert Symbol as required

I

Ensure Data Block Buffer is FREE

Mode
PSAVE= '0'
TXlRX'1'
IROEN='X'
RXEYE = '0'
INVSYM='X'
Status
BFREE ='1'

Write 6 Symbol Sync bytes to Data Block Buffer

Data Block Buffer
Write 6 Bytes

Transmit 24 Symbols

Command (task)
T24S

Wait Interrupt - Interrupt occurs - Read Status Register

Status
IRO='1'
BFREE = '1'

Write 6 Frame Sync bytes to Data Block Buffer

Data Block Buffer
Write 6 Bytes

Transmit 24 Symbols

Command (task)
T24S

Wait Interrupt - Interrupt occurs - Read Status Register

Status
IRO='1'
BFREE='1'

D!li,.i3lobl<

~

CO

MX939

1

Xtal: The output of the on-chip clock oscillator.

2

Xtal/Clock: The input to the on-chip Xtal oscillator. A Xtal, or externally derived clock (fXTAL)
pulse input should be connected here. If an externally generated clock is to be used, it should be
connected to this pin and the "Xtal" pin left unconnected. Note that operation of the MX939
without a suitable Xtal or clock input may cause device damage.

3-10

I

15

DATA VO 0-7: 8 bi-directional 3-state

~P

interface data lines.

RX FB: The output of the RX Input Amplifier and the input to the RX Filter.

16

RX Signal In: The input to RX input amplifier.

17

VBIAS: The internal circuitry bias line, held at V00/2. This pin must be decoupled to V 55 by a
capacitor mounted close to the pin.

18
19

Doc1: ,::3"G.onnections to the RX level Measurement Circuitry. A capacitor should be
Doc2:., ..~'---' nected from each pin to V ss'

20

ignal ground.
the MX939 GMSK Modem.

21
22
23

AUX Gain In:
AUX Gain Out:

30

CS (Chip Select): This is an active low
or write operation.

31

IRQ: This is a "wire-ORable" output for connection to e
It has a low impedance pull-down to Vss when active, and h

32

WRITE: This active low logic level input is used to control the writing
the controlling ~P.

33

READ: This active low logic level input is used to control the reading of data fro
into the controlling ~P.

34
35

ADDRESS 1: These are logic level register select inputs.
ADDRESS 0:

36

RX Data: A logiC level output carrying the received data, synchronous with RX ClK.

37

RX ClK: A logiC level clock output at the received data bit-rate.

38

TX Data: The logic level input for the data to be transmitted. This data should be synchronous
with TX ClK.

39

TX ClK: A logic level clock output at the transmit-data rate.

of the auxiliary inverting digitally

TX & RX Data, and TX & RX Clk form the serial I/O interface for the CDPD or wide band data
modems with the bit rate frequencies listed below:
Modem Type
CDPD
AMPS WBD
40

RX Data

RXClk

TX Data

TXClk

9.6kHz max.
10kHz max.

19.2kHz
20kHz

9.6kHz max.
5kHz max.

19.2kHz
10kHz

VDD: Positive supply rail. A single +5 volt power supply is required. levels and voltages within
this modem are dependent upon this supply. This pin should be decoupled to V55 by a capacitor
mounted close to the pin.

Note: Pin-out for the 48-pin TQFP is T.B.D.

Page 142

MX-COM, INC.

MX939

----------------------,

voo

MX939J

..

voo

40

TXCLK

39

DATA I/O 0

TXDATA

38

DATA I/O 1

RXCLK

XTAL
2.
3

=

4

-----------------------

5
6

To uP
Data I/O

7
8
9
10
11
12
13
14

Ra

15
Ca

16

XTAUCLOCK

DATA I/O 2

RXDATA

36

DATA I/O 3

ADDRESS 0

35

DATA I/O 4

ADDRESS 1

DATA I/O 5

READ

DATA I/O 6

WRITE

DATA I/O 7

IRQ

NC

CS

NC

NC

NC

NC

NC

NC

RX F8

NC

RX SIGNAL IN

NC

17

Cs

II
=

=

Component

R,
R2
R3

C,
C2

19

cl
I=

Value
1.0MQ
Note 1
100kQ
T.B.D.
T.B.D.

20

DOC 1

AUXGAIN OUT

DOC 2

AUXGAIN IN

33

To uP
Address!
Control

32
31
30
29
28
27
26
25
24
23

AUX Gain Out

22

AUX Gain In

21

TXOUT

vss

Data Lines

34

NC

VBtAS

18

}~~'m

37

TX Signal Out

=
Component

C3
C.
Cs
C.
Cl
X,

Value
33pF
Note 1
1.0JlF
15pF
15pF
1.44MHz

Notes
1. R 2 , R3 , C3 and C4 form the gain components for the RX
Input signal. They should be chosen as required by the
signal input level.

Figure 3 - External Components

MX-COM, INC.

Actual Pin-out T.B.D.

Page 143

I

I

MX939

Application Information for CDPD/Wide Band Data
RX Signal Path Description

will produce a logic "0" at the RX Data Output. Negative
going excursions will produce a logic "1."
The received signal is fed through the lowpass RX
Filter, which has a -3dB corner frequency of 0.56 times
the data bit-rate, before being applied to the Level
Measure· and Clock and Data extraction blocks.
The Level Measuring block consists of two voltage
detectors, one of which measures the amplitude of the
'positive' parts of the received signal. The other
measures the amplitude of the 'negative' portions.
External capacitors are used by these detectors, via the
Doc 112 pins, to form voltage 'hold' or 'integrator' circuits.
Results of the two measurements are then processed to
establish the optimum d.c. level decision-thresholds for
the Clock and Data extraction, depending upon the RX
signal amplitude and any d.c. offset present.

The function of the RX circuitry is to:
1. Set the incoming signal to a usable level.
2. Clean the signal by filtering.
3. Provide d.c. level thresholds for clock and data
extraction.
4. Provide clock timing information for data extraction
and external circuits.
5. Provide RX data in a binary form.
The output of the radio receiver's Frequency
Discriminator should be fed to the MX939's RX Filter via
a suitable gain and d.c. level adjusting circuit. This gain
circuit can be built, with external components, around the
on-chip RX Input Amplifier.
Positive going signal excursions at RX Feedback pin

RX Circuit Control Modes

"1" while data is being received, but may be driven to a
logic "0" to freeze the Level Measuring and Clock
Extraction circuits during a fade. If the fade lasts for less
than 200 bit periods, normal operation can be resumed
by returning the 'RX Hold' input to a logic "1" at the end
of the fade. For longer fades, it may be better to reset the
Level Measuring circuits by placing the 'RXDCacq' to a
logic "1" for 10 to 20 bit periods.
'RX Hold' has no effect on the Level Measuring
circuits while 'RXDCacq' is at a logic "1," and has no
effect on the PLL while 'PLLacq' is at a logic "1."
A logic "0" on 'RX Hold' does not disable the 'RX
Clock' output, and the RX Data Extraction and SIN
Detection circuits will continue to operate.

The operating characteristics of the RX Level
Measurement and Clock Extraction circuits are
controlled, as shown in Table 1, by logic level inputs
applied to the 'PLLacq,' 'RX Hold' and 'RXDCacq.'
As shown in Figure 4, a data transmission generally
begins with a preamble such as "1010101010," to allow
the receiving modem to establish timing- and level-lock
as quickly as possible. During the time that the preamble
is expected, the 'RXDCacq' and 'PLLacq' inputs should
be switched from a logic "0 to 1" so that the Level
Measuring and Clock Extraction modes are operated
and sequenced as shown.
The 'RX Hold' input should normally be held at a logic

DATA
RX Signal
Carrier Det.
(RSSI)

-+....... _____________ ~

.....I--_ _ _---t.......I -_ _-=30=-.::b:.:.:its==--_ _

ACQUIRE

MEDIUM BW

NARROW BW

PLL Acq .
Clock Extraction
Circuit Mode

Figure 4 - RX Mode Control Diagram
Page 144

MX-COM, INC.

MX939

Application Information ..... .
PLLacq

RX Hold

PLL Action

"1"

X

Acquire: Sets the PLL bandwidth wide enough to allow a lock to the received signal in less
than 8 zero crossings. The Acquire mode will operate as long as PLLacq is a logic "1".

to "0"

"1 "

Medium Bandwidth: The correction applied to the extracted clock is limited to a maximum
of ± T.B.D. bit-periods for every two received zero-crossings. The PLL operates in this mode
for a period of about 30 bits immediately following a "1" to "0" transition of the PLLacq input,
provided that the RX Hold input is a logic "1".

"0"

"1 "

Narrow Bandwidth: The correction applied to the extracted clock is limited to a maximum
of ± T.B.D. bit-periods for every two received zero-crossings. The PLL operates in this mode
whenever the RX Hold Input is a logic "1" and PLLacq has been a logic "0" for at least 30
bit periods (after Medium Bandwidth operation, for instance).

"0"

"0"

Hold: The PLL feedback loop is broken, allowing the RX Clock to freewheel during signal
fade periods.

"1"

RX Level Measure Action

RXDCacq RX Hold
"0" to "1"

X

CIGain: Operates for one bit-time after a "0" to "1" transition of the RXDCacq input. The
external capacitors are rapidly charged toward a voltage halfway between the received
signal input level and V BIAS' with the charge time-constant being approximately 0.5bit-time.

"1 "

X

Fast Peak Detect: The voltage detectors act as peak-detectors. One capacitor is used to
capture the 'positive'-going signal peaks of the RX Filter output Signal; the other captures
the 'negative'-going peaks. The detectors operate in this mode whenever the RXDCacq
input is at a logic "1," except for the initial 1-bit CIGain-mode time.

"0"

'''1 "

Averaging Peak Detect: Provides a slower but more accurate measurement of the signal
peak amplitudes.

"0"

"0"

Hold: The capacitor charging circuits are disabled so that the outputs of the voltage
detectors remain substantially at the last readings (discharging very slowly [time-constant
approx. 2,000 bits] towards V BIAS ).

Table 1

- PLL and RX Level Measurement Operational Modes

RX Clock Extraction

RX Data Extraction

Synchronized by a phased locked loop (PLL) circuit
to zero-crossings of the incoming data, the 'RX Clock
Extraction' circuitry controls the 'RX CLK' output. The RX
Clock is also used internally by the Data Extraction
circuitry. The PLL parameters can be varied by the 'RX
Circuit Control' inputs PLLacq and RX Hold to operate in
one of four PLL modes as described in Table 1.

The 'RX Data Extraction' circuit decides whether each
received bit is a "1" or "0" by sampling the output of the RX
Filter in the middle of each bit-period, and comparing the
sampled voltage against a threshold derived from the 'Level
Measuring' circuit. This threshold is varied on a bit-by-bit
basis to compensate for intersymbol interference. The
extracted data is output from the 'RX Data' pin, and should
be sampled externally on the rising edge of the 'RX CLK.'

TX Signal Path Description

distortion of the binary signal while providing sufficient
attenuation of the high frequency-components which
would otherwise cause interference into adjacent radio
channels.
The signal at 'TX Out' is centered around V BIAS' going
positive for logic "1" (high) level inputs to the 'TX Data'
input and negative for logic "0" (low) inputs.

The binary data applied to the 'TX Data' input is
retimed within the chip on each rising edge of the 'TX
Clock' and then converted to a binary signal centered
about V BIAS.
The TX Filter has a lowpass frequency response,
which is designed to minimize amplitude and phase

MX-COM, INC.

Page 145

I

I

MX939
Application Information ..... .
FM Modulator, Demodulator and IF
For optimum performance, the 'eye' pattem of the
received signal (when receiving random data) applied to the
MX939 should be as close as possible to the Transmit 'eye'
pattern example shown in Figure 5. Of particular importance
are general symmetry and cleanliness ofthe zero-crossings.
To achieve this, attention must be paid to:
- Linearity and frequency/phase response of the TX
frequency modulator. Unless the transmit data is
encoded to remove low frequency components, the
modulator frequency response should extend down
to a few Hz. This is because two-point modulation is
necessary for synthesized radios.

[VBIASI

),

however a.c. coupling can be used provided that

- The 3 dB cut-off frequency is 20Hz or below
(i.e. a 0.111F capacitor in series with 100kQ).
- The data does not contain long sequences of
consecutive ones or zeroes.
- Sufficient time is allowed after a step change at the
discriminator output (resulting from channel changing
or the appearance of an RF carrier) for the voltage
into the MX939 to settle before the 'RXDCacq' line is
strobed.

- Bandwidth and phase response of the RX IF filters.
- Accuracy of the TX and RX carrier frequencies -any
difference will shift the received signal towards one of
the skirts of the IF filter response.
Ideally, the RX demodulator should be d.c. coupled to
the MX939 'RX Signal In' pin (with a d.c. bias added to
center the signal at the AX Feedback pin around VDr/2

Data Formats
The receive section of the MX939 works best with data
which has a reasonably 'random' structure --the data
should contain approximately the same number of 'ones' as
'zeroes' with no long sequences of consecutive 'ones' or
'zeroes'. Also, long sequences (>100 bits) of '10101010 .. .'
patterns should be avoided.
For this reason, it is recommended that data is
randomized in some manner before transmission, for

'Acquisition' and 'Hold' Modes
The 'RXDCacq' and 'PLLacq' inputs must be pulsed
'High' for about 16 bits at the start of reception to ensure that
the d.c. measurement and timing extraction circuits lock-on
to the received signal correctly. Once lock has been
achieved, then the above inputs should be taken 'Low'
again.
In most applications, there will be a d.c. step in the
output voltage from the receiver FM discriminator due to
carrier frequency offsets as channels are changed or when
the distant transmitter is tumed on.
The MX939 can tolerate d.c. offsets in the received
signal of at much as ±0.5V with respect to V BIAS' (measured
at the AX Feedback pin). However, to ensure that the d.c.
offset compensation circuit operates correctly and with
minimum delay, the 'Low' to 'High'transition of the 'RXDCacq'
and 'PLLacq' inputs should occur after the mean input
voltage to the MX939 has settled to within about 0.1 V of its
final value. (Note thatthis can place restrictions on the value
of any series signal coupling capacitor.)

Page 146

Figure 5 - Typical Transmit Eye Pattern

example by 'exciusive-ORing' it with the output of a binary
pseudo-random pattern generator.
Where data is transmitted in bursts, each burst should
be preceded by a preamble designed to allow the receive
modem to establish timing and level lock as quickly as
possible. This preamble should be at least 16 bits long, and
should preferably consist of alternating pairs of '1 's and 'O's
i.e. '110011001100 .... .'; the pattem '10101010 ... .' should
not be used.

As well as using the 'RX Hold' input to freeze the Level
Measuring and Clock Extraction circuits during a signal
'fade,' RX Hold may also be used in systems which employ
a continuously transmitting control channel to freeze the
receive circuitry during transmission of a data packet,
allowing reception to resume afterwards without losing bit
synchronization. To achieve this, the MX939 'Xtal' clock
needs to be accurate enough that the derived 'AXClock'
output does not drift by more that about 0.1 bit time from the
actual received data-rate during the time that the 'RXHold'
input is 'Low'.
The 'RXDCacq' input, however, may need to be pulsed
'High' to re-establish the level measurements if the 'AXHold'
input is 'Low' for more that a few hundred bit-times.
The voltages on the Doc1 and Doc2 pins reflect the
average peak positive and negative excursions of the
(filtered) receive signal, and could therefore be used to
derive a measure of the data signal amplitude.
Note however, that these pins are driven from very highimpedance circuits, so that the d.c. load presented by any
external circuitry should exceed 10MQ to V BIAS.

MX-COM, INC.

MX939
Read and Write Registers - Memory Map
Read Only
Status Register
Write Only
GAIN 1 Register
GAIN 2 Register
Control Register

HEX

READ

WRITE

CS

BIT 7

$0

0

1

0

0

$0
$1

1

0

0

1

0

0

$2

1

0

0

-

I BIT 6 I
I 0 I

-

x
x

BIT 5
0

-AUXGAINI
I

x
x

I BIT4
I 0
-

-

x
I
I x
IIRQ Maskl Hold

I BIT 2 I BIT 1 BIT 0
I 0 I COLOR CODE

BIT 3
0

----TXGAIN - - - -

-

-

-

RX GAIN- -

--

PLLacq I DCacq I MODE
x = don't care

Read Only Register
STATUS Register (HEX address $0)
This read only register contains the status of the color code as described below:
COLOR CODE (Bits 0 and 1)
Bits 0 and 1 indicate the SAT tone frequency or "COLOR CODE" of the incoming signal according to the table
below. Whenever the COLOR CODE changes an interrupt may occur, depending on the state of the IRQ mask
(Bit 5) in the control register.
Measured Frequency
of Incoming Signal

Measured SAT
Determination

f ~ f,
f, ~ f < f2
f2 ~ f < f3
f3 ~ f < f4
f4 ~ f
No SAT Received

No valid SAT
SAT = 5970
SAT = 6000
SAT = 6030
No valid SAT
No valid SAT

Where
f,
f2
f3
f4

= 5955 ± 5Hz
= 5985 ± 5Hz
= 6015 ± 5Hz
= 6045 ± 5Hz

COLOR CODE
Bit 1
Bit 0
1
0
0
1
1
1

1
0
1
0
1
1

Table 2 - Color Code Frequencies

Write Only Register
GAIN 1 Register (HEX address $0)
This write only register controls the MX939's gain functions as described below:
AUX GAIN (Bits 7, 6, 5 and 4)
This 4-bit number specifies the gain of the auxiliary amplifier. The desired gain is selected according to Table
3. In the OFF state the amplifier is in a powersave mode, and the output is taken to bias via a 500kQ resistor.
TX GAIN (Bits 3, 2, 1 and 0)
This 4-bit number specifies the TX gain. The desired gain is selected according to Table 4. In the OFF state
the amplifier is in a powersave mode, and the output is taken to bias via a 500kQ resistor.
Bit 7
Bit 6
Bit 5
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
1
1
0
1
1
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
Table 3 - AUX Gain Register
MX-COM, INC.

Bit 4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Gain dB
OFF
-3.0
-2.571
-2.143
-1.714
-1.286
-0.857
-0.428
0
0.428
0.857
1.286
1.714
2.143
2.573
3.0

Bit 3
Bit 2
Bit 1
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
1
0
1
1
0
0
1
1
1
0
0
1
0
0
1
0
1
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
Table 4 - TX Gain Register

Bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Gain dB
OFF
-3.0
-2.571
-2.143
-1.714
-1.286
-0.857
-0.428
0
0.428
0.857
1.286
1.714
2.143
2.573
3.0

Page 147

I

MX939
GAIN 2 Register (HEX address $1)
This write only register controls the MX939's gain functions as described below:
RX GAIN (Bits 3, 2, 1 and 0)
This 4-bit number specifies the RX gain. The desired gain is selected according to Table 5 below.

I

Bit 3

Bit 2

Bit 1

Bit 0

Gain dB

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

OFF
-3.0
-2.571
-2.143
-1.714
-1.286
-0.857
-0.428
0
0.428
0.857
1.286
1.714
2.143
2.573
3.0

Table 5 - RX Gain Reaister

CONTROL Register (HEX address $2)
This register controls the MX939's functions as described below:
MODE (Bits 1 and 0)
This 2-bit number configures the MX939 to function as a CDPD, SAT Tone or Wide Band Data Modem
described in Table 6 below.
Bit 1

Bit 0

CDPD

0
0
Powersaved
1
Enabled
0
Powersaved
0
1
1
Powersaved
1
Table 6 - Mode Control Register

SAT Tone

Wide Band Data

Powersaved
Powersaved
Enabled
Powersaved

Powersaved
Powersaved
Powersaved
Enabled

RXDCAcq (Bit 2)
A logic "1" applied to this bit will set the RX Level Measurement circuitry to the acquire mode. This applies to
both the CDPD and the Wide Band Data Modem functions.
PLLAcq (Bit 3)
A logic "1" applied to this bit will set the RX Clock Extraction circuitry to the acquire mode. This applies to
both the CDPD and the Wide Band Data Modem functions.
Hold (Bit 4)
A logic "0" applied to this bit will "freeze" th? Clock Extraction and Level Measurement circuits unless they are
in the acquire mode. This applies to both the CDPD andJtJe Wide Band Data Modem functions.
IRQ Mask (Bit 5)
When this bit is set to "1" the COLOR CODE interrupt will be gated out to the IRQ pin. When this bit is set to
"0" the COLOR CODE interrupt will be inhibited.

Page 148

MX-COM, INC.

MX939

Timing Information
WRITE CYCLE (DATA TO MX939)

tah:""'-":

ADDRESS-V

AO,A1~
~~:tacsl
CS ---~,

y

'

ADDRESS VALID

0~,

I

___

I

tcsh ~........'

'~-------.'

~,','
: ~/.
~ 'io..___
, -------------'--t' ~..

tcshi

~

.. ; " -

WRITE _ _ _ _---;---L..______'-!.., i"I
',OIl
twl
~, '
, ~:
.. -~~=s~~1~~~__________~
trhcsl:........:

READ

I

,

/:
~I

'OIl tdsw.:

:

:

II.

:

I

~tdhw

_ _----'XVALID DATAX~---

DATA DO-D7

READ CYCLE (DATA FROM MX939)

ADD:a~~~

==><:....-.....:tacsl

CS -----r-~
I

! ><~
I

___

I

,
,',,-------'
i++:
l'

~

twhcsl ........'

,
WRITE~
~'

tah :.....-...:

ADDRESS VALID

tcsh
%
,---'- - - - - - - - - - - - - - - < ' :..

tcshi

.: " -

"

:

: .. tcs~I.,
I

:

I

_____~-__~,''''_~:,~.. ----trl---~~:~'+---+:trx
~
READ
: III

DATA DO-D7

:.

trarl

tracl

Period
tacsl:
tah:
tcsh:
tcshi:
tcsrwl:
tdhr:
tdhw:
tdsw:
trhcsl:
tracl:
trarl:
trl:
trx:
twhcsl:
twl:

.. :

.,

--------«

Note
Address valid to CS low time
Address hold time
CS hold time
CS high time
CS to WRITE or READ low time
Read data hold time
Write data hold time
Write data setup time
READ high to CS low time (write)
Read access time from CS low
Read access time from READ low
READ low time
READ high to 00-07 3-state time
WRITE high to CS low time (read)
WRITE low time

>--

tdhr ,+----+-1 :

DATA VALID

Min.
0
0
0
6
0
0
0
90
0

200
0
200

Typ.

Units
ns
ns
ns
xtal cycles
ns
ms
ns
ns
ns
175
ns
145
ns
ns
50
ns
ns
ns

Max.

Note 1: With 30pF max. to Vss on DO-D7 pins.

Figure 6 - Paralle/l1P Interface Timing
MX-COM, INC.

Page 149

I

I

MX939

Specifications
Absolute Maximum Ratings

Operating Characteristics

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(ref Vss=OV)
Sink/Source Current
(supply pins)
(other pins)
Total Device Dissipation
(@ T AMB=25°C)
Derating
Operating Temperature
Storage Temperature

-0.3 to 7.0V

Voo = 5.0V

-0.3 to (Voo+ 0.3V)

TAMB = 25°C
Xtal/Clock fo = 1.44 MHz

±30mA
±20mA

Noise bandwidth = bit rate

SOOmW max.
10 mW/oC
-40°C to +SsoC
-SsoC to +12SoC

3.0

Supply Voltage (V 00)

Static Values
Supply Current
Powersaved
Enabled

1.0
S

5.S

V

TBD
TBD

mA
mA

TBD
TBD

kQ
kQ

TBD

V p-p
V p-p
V p-p

Transmit
TX Output
1.0
Powersaved
TX Signal Level
CDPD
AMPS WBD
SAT

SOO

Receive Parameters
RX Input Impedance
RX In Amp Voltage Gain
RX Input Signal Level
CDPD
AMPS WBD
SAT
XtallClock Input
High Pulse Width
Low Pulse Width
Input Impedance
Voltage Gain (i/p = 1mVrms @ 1kHz)

Page 150

MQ

TBD

VN
4,5
4,S
4,S

6
6

TBD
TBD
TBD

TBD
TBD
TBD
TBD

1.0
1.7
0.4

TBD
TBD
TBD

V p-p
V p-p
V p-p

ns
ns
MQ
dB

MX-COM, INC.

MX939

~P

Interface
Input Logic "1" Level
Input Logic "0" Level
Input Leakage Current
Input Capacitance
Logic "1 "Output Level at IOH = 120llA
Logic "O"Output Level at IOL = 360llA
"Off' State Leakage Current (V = VDO)
AUX Gain
Input Impedance
Output Impedan~

1.5
TBD

TBD
10.0
V 00-0.4

0.4
TBD

Enabled
Powersave·

RX Gain, TX Gain, AUX Gain
Gain
Gain per Step
Step Error
SAT Characteristics
SAT RX Decode Response
SAT RX Not Decode Level
SAT TX Phase Step Response
SAT TX Phase Jitter
SAT TX SIN
Characteristics
RX Bit Rate
RX Data Delay
RX BER
TX Bit Rate
TX BT
TX Data Delay

500
TBD

7
·8
9

0.35
180

TBD
TBD

TBD
':

V
V
/lA
pF
V
V

flA

kn
kn
kn
kn
%
mVrms
V pop

'

-.'.. ". ;.>
, '.," ..

10
10
10

. TBO

TBD
TBD

dB
dB
dB

T8D<

ms

TBD
TBD
TBD

ms
degrees
%

TBD

kbps
bit periods

.-

16

200
TBD

11
TBD

19.2
13

12

AMPS WIDE BAND DATA (WBD) Characteristics
WBD RX Bit Rate
15
WBD RX Data Delay
13
WBD RX BER
WBD TX Bit Rate
14
WBD TX Data Delay
12

MX-COM, INC.

V oo-1.15

TBD

Bandwidth (-3dB)
Total Harmonic Distortion
Output Noise Level
Onset of Clipping

CDPD
CDPD
CDPD
CDPD
CDPD
CDPD
CDPD

17,18
17,18
17,18
17,18
18
18,19
19

TBD
19.2
0.5
1.5

kbps
TBD

bit periods

TBD

kbps
bit periods

TBD

kbps
bit periods

20
TBD
10
1.5

Page 151

I

I

MX939
Notes
1. Not including current drawn from the MX939 pins by external circuitry.
2. Small signal impedance.
3 Measured with a SV supply and the TX gain amplifier set to OdB.
4. Measured with a SV supply, the RX gain amplifier set to OdB, and OdB gain in the input amplifier.
S. Typical levels equate to carrier deviations of :t8kHz for WBD, ±4.8kHz for CDPD, and ±2kHz for SAT.
The levels are directly proportional to the supply voltage.
6. Timing for an external clock input to the Xtal/clock pin.
7. Gain set to OdB, input level of S49mVrms at 1kHz.
8. With an A.C. short-circuit input, measured in a 30kHz bandwidth.
9. With a S volt supply.
10. With reference to a 1kHz signal.
11. Time to settle to within 10° of final steady state phase.
12. Measured between the rising edge of 'TX Clock' and the center of the corresponding bit at 'TX Out.'
13. Measured between the center of bit at 'RX Signal In' and corresponding rising edge of the 'RX Clock'.
14. Input as NRZ data and converted on chip to Manchester encoded data.
1S. Output as Manchester encoded data at a frequency of twice the NRZ data rate.
16. SIN T.B.D.
17. WRITE, READ, CS, AD and A1 pins.
18. DO-D7 pins.
19. IRQ pin.

Page 152

MX-COM, INC.

Technical Specifications

Section 2:
Sub-Audio Tone
Signaling/Detection

I

The following section contains specifications on MX·COM's
Sub-Audio Tone Signaling/Detection IC's. Included in this
section are digital, CTCSS and Pvt SQUELCHTM devices.
Pvt SQUELCH, MX·COM's "privacy" method, is a combination
of CTCSS and speech inversion.
A thorough explanation of PvtSQUELCH is given in the Applications section of this book (see Appendices).

Device
MX315A
MX165B
MX165C
MX365A
MX275
MX375
MX805A

MX-COM, INC.

Description
CTCSS Encoder
CTCSS Encoder/Decoder with Audio Filter
CTCSS Encoder/Decoder with Audio Filter
CTCSS Encoder/Decoder with Audio Filter
Pvt SQUELCHTM CTCSS Encoder/Decoder
Pvt SQUELCHTM CTCSS Encoder/Decoder
Sub-Audio Signaling Processor

Page
p. 155
p. 160
p. 169
p. 178
p. 187
p. 195
p. 204

NEW

Page 153

I

Page 154

MX-COM, INC.

MX·~M,IN~.

MX315A

CTCSS ENCODER

Features
•
•
•
•
•
•

Field Programmable Tone Encoder
40 CTCSS Frequencies
Crystal-Controlled Frequency Stability
Low Distortion Sinewave Output
Few External Components Required
CMOS Low Power Requirements

I

Applications
•
•
•
•
•
•

Mobile Radio Base Stations & Repeater Stations
Mobile Radios
Hand-Held Radios
Industrial Controls
Intercom Systems
Door-Entry Systems

MX315AJ (CDIP)
MX315AP (PDIP)
14 pins

MX315ADW
(SOIC)
16 pins

Description
The MX315A is a monolithic CMOS tone encoder for
sub-audible tone squelch systems. It provides three more
frequencies than the earlier MX315: 69.3, 97.4 and
206.5 Hz. The tone frequencies are derived from an input
reference frequency. An on-chip inverter is provided to
drive an external crystal circuit.

Tone selection is achieved through six programming
inputs and two control inputs (which allow either a logic "1"
or "0" to enable the device). A low distortion sinewave is
generated at the TX Tone Output when the MX315A is
enabled. The emitter follower output stage can source
1mW directly into a 600n load (OdBm).

XtaVClock

XtaI ...- - - - '
DO-05 L...-----,JI

TX Tone Output

TX Enable

--r--------,L,>-------------'

Figure 1 - Internal Block Diagram

MX-COM, INC.

Page 155

MX315A

Pin Function Chart

I

1

1

2
3
4
5
6

2
3

03
02
01

00-05 are tone select inputs with internal pull-up resistors. The logic combination at
these inputs determines the encoded CTCSS tone. See Table 1.
The input sequence is not latched and may be changed at any time. A logic "1" will
be programmed if the input is open circuit, allowing the use of SPST switches.

4

DO

5
6

04
05

7

7

V ss: Negative Supply Voltage.

8

8

XtallClock In: This is the input to the CMOS inverter. It can be used in conjunction with the Xtal
output to form the active element in a crystal oscillator circuit. Alternatively, a logic level 1MHz
frequency can be injected at this pin. However, the supply voltage should never be applied
without the input clock signal.

9

9

Xtal Output: This is the output of the CMOS inverter. When used as a crystal oscillator, track
lengths and loading of this pin should be minimized.

10

10

Internal Connection: Do not use.

11

N/C

12

N/C

11

13

TX Tone Output: This is the tone output pin. It includes a low impedance emitter follower stage
for sourcing sinusoidal tone. The tone is generated about a DC level of approximately 1/2 Voo.
The pin is high impedance when not encoding.

12

14

TX Enable Input: This logic input has an internal pull-up resistor. A logic "0" at this pin enables
the MX315A.

13

15

TX Enable Input: This logic input has an internal pull-down resistor. A logic "1" at this pin
enables the MX315A.

14

16

Voo: Positive Supply Voltage.

MX315A External Components

(See Figure 2)
Figure 2 illustrates the required external components:
• The 1Mil resistor is used to bias the internal CMOS inverter into its linear mode. A tolerance of ±20% is
acceptable .
• "X1" is a parallel resonant crystal. A reference frequency of 1 MHz ±0.19% is required to maintain a tone
accuracy within 0.5%.

Where two or more circuits are required to use a single oscillator (i.e. repeater applications), the ~al at Xtal can
be used to drive one additional Xtal/Clock input. Any further circuits can be driven from the buffered Xtal output of the
second device.
The program code can be set on the 00-05 inputs by hardwired logic levels or SPST switches to VS8' as illustrated
in Figure 2 (allowing the internal pull-up resistors to program a logic "1 ").
The MX315A provides both a TX Enable input and a TX Enable input. Either input can be used to enable the tone
output, with the unused pin left open circuit (internal resistors establish a valid logic level and prevent damage). Any
configuration of PTT switch or TX signal can therefore be interfaced.

Page 156

MX-COM, INC.

MX315A

r-

TX ENABLE - - - .

',---._ _-----'I

MICROPHONE
VOICE BAND
FILTER

TX TONE
OUTPUT
SUMMING
AMPLIFIER
D.C. GROUND

D.C. GROUND

I

11
TX TONE OUT

FREQUENCY

Figure 2 - External Components and Typical
Application

Figure 3 - Tone Encoding Sequence and
Spectral Response

Application Notes
The MX315A is dedicated to Continuous Tone-controlled Squelch Systems (CTCSS) in radio applications.
However, it can be used wherever encoding of low-frequency tones is required, such as intercoms, door-entry systems
and various industrial applications.
The performance of a CTCSS system can be degraded if speech frequencies in the signaling spectrum are not
removed prior to transmission. This can be accomplished by filtering the microphone signals to attenuate frequencies
below 250 Hz. Figure 2 illustrates the addition of TX Tone Output to the filtered microphone signals prior to modulation.
Figure 3 illustrates the TX Tone Output sequence and a typical spectral analysis.

Interfacing and Electromagnetic Capability
The MX315A requires a clock of 1 MHz, which is internally converted to logic level square waves. Consideration
should therefore be given to possible interference problems with RF or IF circuitry caused by 1 MHz or its harmonics.
A decoupling capacitor can be used to reduce ripple on the power supply. This will reduce the level of
superimposed noise on the supply caused by internal switching transients (particularly at 1 MHz and fa).

MX-COM, INC.

Page 157

MX315A

I

67.0

67.06

+.10

69.3

69.37

+.10

1

71.9

71.84

-.08

0

74.4

74.33

-.10

1

1

0

0

3F
0

0

39
1

iF

0

3E

77.0

76.99

-.02

79.7

79.65

-.06

82.5

82.50

0.0

0

85.4

85.34

-0.7

1

88.5

88.62

+.14

0

91.5

91.38

-.13

1

94.8

94.88

+.08

0

97.4

97.46

+.06

1

100.0

99.87

-.13

0

0

0

103.5

103.39

-.11

0

1

0

0

1C

107.2

107.17

-.03

0

0

0

0

110.9

110.85

-.04

0

OC
18

114.8

114.80

0.6

0

0

0

1

08

118.8

118.60

-.17

0

1

0

0

1A

123.0

123.12

+.10

0

0

0

0

OA

127.3

127.50

+.16

0

131.8

131.67

-.10

0

0

1
0

0

+.14

0

1

+.13

0

0

1

146.2

145.96

-.16

0

1

0

151.4

151.45

+.03

0

0

0

156.7

156.59

-.07

0

1

0

162.2

162.10

-.06

0

0

0

167.9

168.01

+.07

0

1

0

173.8

173.43

-.21

0

0

0

179.9

180.21

+.17

0

1

0

186.2

186.46

+.14

0

0

0

192.8

193.16

+.19

0

203.5

202.88

-.31

0

+.14
+.07

0

218.1

217.96

-.07

0

225.7

225.58

-.05

233.6

233.75

+.07

0

3C

0

1

10

0

3A
00

0

0

19

0

0

09

0

0

0

18

0

0

0

08

1

07

17
0

16

0

06

0

15

0
0

0

05
14

0

0

04

1

0

0

0

0

1

1

03

0

0

0

38

13

0

0

0

12

0

0

0

0

02

0

1

0

0

0

11

0

0

0

0

0

01

241.8

242.54

+.31

0

1

0

0

0

0

250.3

250.06

+.10

0

0

0

0

0

0

4032

0.0

0

0

Test

OE
38

0

136.69

206.78

1E

1
0

141.48

210.84

0
0

0

136.5

206.5

OF
3D

0

141.3

210.7

1
0

10
00
33

(or any
invalid
address)

Table 1 - CTCSS Tone Programming
Page 158

MX-COM, INC.

MX315A

Specifications
Absolute Maximum Ratings

Operating Limits

Exceeding the maximum rating can result in
device damage. Operation of the device outside the
operating limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.

Supply Voltage
Device Dissipation @ 85°C
Operating Temperature
Storage Temperature

VDD = 5V

-0.3V to 7.0 V
100mW
-30°C to +85°C
-55°C to +125°C

TAMS = 25°C
Clock = 1MHz

4.5

Supply Voltage (V DD)
Supply Current (operating)
Input Impedance
Input Impedance

2

Logic Input "1"

5.0

5.5

V

1.5

4.5

mA

500

kQ

10

MQ

3.5

V

Logic Input "0"

1.5

TX Output EMF

3

550

TX Risetime

V

775

mVrms

1

ms

TX Tone Output Load Current

5

TX Distortion

3

2

Variation in Output Level Between Tones

3

0.1

mA

5

%

dB

Notes:

1. Refers to DO, D1, D2, D3, D4, D5, TX Enable and TX Enable inputs.
2. Refers to XtallClock input.
3. Any program tone and RL

MX-COM, INC.

=600, CL = 15pF.

THD measurements are taken in the 0-6 kHz bandwidth.

Page 159

I

MX·~,IN~.

MX165B

CTCSS ENCODER/DECODER
WITH TXlRX AUDIO FILTERS

I

FEATURES

APPLICATIONS

•
•
•
•
•

• Mobile Radio Channel Sharing
• Wireless Intercom
• TlAiEIA-603 - 37 Tone Plus 97.4Hz &
69.3Hz
• Serves 3-Cell Applications

39 CTCSS Tones + Notone
TXlRX Audio Filters
TX Tone Phase Reversals
Serial or Parallel Programming
Low Voltage Supply: 3.0 to 5.5 V

BENEFITS
•
•
•
•

Scanning of any Channel
Improved Sinad
Squelch Tail Elimination
Easy I1P Interface

MX165BLH
24 pin PLCC

MX165BDW
24 pin SOIC

DescriPtion,E2I!lY~~S:cd~s;gn~~~D~i'ji:"x speech, depending
Voice on shared radio channels is multiplexed wllt:! 1if,,1n~~ bn the t:!!,>st:tra!1}~!1l1ftar's pre-emphasis network.
subaudible CTCSS tone as a means of direc;tirgz1j"i1~.;.,:~fonly 6g
ffil.~;~~ir attenuation of speech composages among user groups sharing the ,sar!leF:llt,fiie- nei1ts a~;U:ie
i"CTCSS tones was only a few dB, which
quency. Continuous Tone Contrql)~$~~)dttSystem"
.
°g:kl''''ia'lk-off' (low frequency voice components
(CTCSS) modulates the tran~l!i!:itte'twfttl;,a"?atilcrete .~9~.<: un "elching the receiver audio).
taken from a field of 3!'ld[J\~, ran~ of 67 tOj'~dStandard pl~.,,~)J~lia:nd The MX165B features TXlRX selection and a LOADI
97.4Hz. Groups~t::r~iii~ceiver~;,~gre~tEiid
com- LATCH pin. A Notone program code has been included to
mon interest andilissigned tql'ieii~~ulate the voicel permit scanning channels without CTCSS. A choice of
tone mixture for voice mt~~~iO'15e heard.
serial or parallel tone programming is offered. Operation
oS '.
of the PTL signal during TX reverses the phase of the
The MX165B CTCSS EncoderlDecoder enhances voicel transmitted CTCSS tone by 180°. This is used in some
tone multiplexing with an on-chip filter that attenuates TX radios to eliminate squelch tails.
speech 36dB at 250Hz, while passing signals >300Hz with
only ±1dB of ripple.
The MX165B requires a single 3.75- or 5-volt supply and
a 1 MHz clock or crystal.
0

0

by

Page 160

MX-COM, INC.

o~

~

XTAl../CLOCK

~

XT.lIJ.

p

1)(

VBIAS

AUDIO IN
1)(

AI DIO OUT

AX AUDIO I
AX J UDIO OUT

~
~

TONE IN

fTONE

ONE DETECT

LOAD~

SERIAL
SERIAL
SERIAL
SERIAL

ENABLE/D6
ENABLE/D.
DATA/D.
CLOCK/D.

a-BIT
SERIAL
SHIFT
WITH
JAM
INPUTS

D,
Do

RXJTX

a-BIT
LATCH

PROGRAM
LOGIC

ONE OUT

1)(

ENABLE

PTL
CLOCK

Voo Vss_
VBIAS _
DECODE COMPARATOR REF.
DECODE COMPARATOR IN

~
~

....
....

Ol

AX TONE DECODEE OUT

s::

><
......
Figure 1 - MX165B Internal Block Diagram

0)

UI

OJ

MX165B
PIN FUNCTION TABLE
Pin

Function

MX165A
MX365A
1

VDD : Positive Supply.

2

XtallClock: Input to the on-chip inverter used with a 1 MHz Xtal or external clock source.

3

Xtal: Output of the on-chip inverter (clock output).

4

LoadlLatch: Controls 8 on-Chip latches and is used to latch RXfTX, PTL, and 00-05. This pin is
internally pulled to V DO. A logic "1" applied to this input puts the 8 latches in ''transparent'' mode. A logic
"0" applied to this input puts the 8 latches in the "latched" mode. In parallel mode data is loaded and
latched by a logic 1-0 transition (see Fig. 3). In serial mode data is loaded and latched by a 0-1-0 strobe
pulse on this pin (see Fig. 4).

5

D5/Serial Enable 1: Data input 05 (in parallel mode). A logic "1" applied to this input together with
a logic "0" applied to D4/Seriai Enable 2 will put the device in serial mode (see Fig. 4). This pin is
internally pulled to VDO.

6

D4ISerial Enable 2: Data input 04 (in parallel mode). A logic "0" applied to this input together with
a logic "1" on pin 5 will place the device in serial mode (see Fig. 5). This pin is internally pulled to VOO.

7

D3/Serial Data Input: Data input 03 (in parallel mode). In serial mode this pin becomes the serial data
input for 05-00, RXfTX and PTL (see Fig. 4). 05 is clocked first and PTL last. This pin is internally
pulled to VDO.

8

D2ISerial Clock: Data input 02 (in parallel mode). In serial mode this pin becomes the serial clock
input. Data is clocked on the positive going edge (see Fig. 4). This pin is internally pulled to V DO.

9

01: Data input 01 (in parallel mode). This pin is internally pulled to VDO.

10

DO: Data input DO (in parallel mode). This pin is internally pulled to VOO.

11

Vss: Negative supply.

12

Decode Comparator Ref.: This pin is internally biased to V 0013 or 2V0013 via 1M resistors depending
on the logical state of the RX Tone Decode Out pin. RX Tone Decode Out 1 will bias this input 2VDol
3; a logic "0" will bias this input V 0013. This input provides the decode comparator reference voltage,
and switching of bias voltages provides hysteresis to reduce "chatter" under marginal conditions.

13

RX Tone Decode Out: This is the gated output of the decode comparator. This output is used to gate
the RX Audio path. A logic "0" on this pin indicates a successful decode and that the Decode
Comparator Input pin is more positive than the Decode Comparator Ref. input (see Table 1).

14

Decode Comparator Input: This is the inverting input of the decode comparator. This pin is normally
connected to the integrated output of the RX Tone Detect line.

15

RX Tone Detect: In RX mode this output will go to logic "1" during a successful decode. It must be
externally integrated to control response and deresponse times (see Table 1).

16

TX Tone Out: The CTCSS sinewave output appears on this pin under control of the RXfTX pin. This
pin, when not transmitting a tone, may be biased to V oo -0.7VorO/C (see Table 1). This pin is an emitter
follower output with high impedance load, requiring capacitive coupling or a low impedance «1 kQ) load
to ground.

Page 162

=

MX-COM, INC.

MX165B
PIN FUNCTION TABLE
Pin

Function

17

RXlTX: This input (in parallel mode) selects RX orTX modes (see Fig. 2). In serial mode this function
is serially loaded. This pin is internally pulled to VDO via a 1Mn resistor.

18

PTL: In parallel RX mode this pin operates as a "Push To Listen" function by enabling the RX audio
path, thus overriding the tone squelch function. In parallel TX mode this pin reverses the phase of the
transmitted CTCSS tone (used for squelch tail elimination). In serial mode this function is serially
loaded (see Fig. 2).

19

RX Audio Out: This is the high pass filtered receive audio output pin. This pin outputs audio when
RX Tone Decode = 0, or PTL = 1, or when Notone is programmed (see Table 2). In TX mode this pin
is biased to VoJ2.

20

TX Audio Out: This is the high pass filtered transmit audio output pin. In TX mode this pin outputs
audio present at the TX Audio Input pin. In RX mode this pin is biased to V00/2.

21

Bias: This pin is the output of an internally generated VoJ2 bias level and would normally be externally
decoupled to Vss via capacitor C7.

22

TX Audio In: This is the TX Audio input pin. In TX mode it may be prefiltered, using the TX audio
path, thus helping to aviod talkoff due to intermodulation of speech frequencies with the transmitted
CTCSS tone. This pin is internally biased to VoJ2.

23

RX Audio In: This is the input to the audio high pass filter in RX mode. It is intemally biased to VoJ2.

24

Tone Input: This is the input to the CTCSS tone detector. It is intemally biased to V 00/2.
NOTE: Pins labeled "N/C" (no connect) may have intemal connections. Do Not Use.

TONE IN
RX AUD IN
LOAD/LATCH

5 D5
6 D4
7 D3

TXAUD IN
BIAS

21
20
TX AUD OUT
19
RX AUD OUT
18

8 D2

9
10
11
12

-

D1

TONE OUT

DO

RX DETECT

Vss

DECODE
COMPo IN

COMPo REF

RX DECODE

MX165BJ

Figure 2 - External Component Diagram
MX-COM, INC.

13

~
~

Component Values
R1
1Mn
R2
560kn
R3
820kn
X1
1MHz
C1
0.1!lF
68pF
C2
C3
33pF
C4
0.1!lF
C5
0.1!lF
C6
0.47!lF
C7
0.1!lF
C8
0.1!lF
C9
0.1!lF
C10
0.1!lF
C11
0.1!lF
01
small signal

Tolerances: Resistors: ±10%
Capacitors: ±20%
Xtal:±O.l%

Page 163

I

MX165B

VO CONDITIONS
OUTPUT PIN
CONDITION

INPUT PIN
CONDITION

RESULTIFUNCTION

RXITX

PTL

Decode
Comp.
Input

RX
Tone
Detect

Tone
Decode

Tone
Transmitter
Enabled

TXTone
Phase
Reversed

TXAudio
Path
Enabled

Tone
Decoder
Enabled

RXAudio
Path
Enabled

Notes

Tone

0

0

X

0

1

Yes

No

Yes

No

No (bias)

1a

Tone

0

1

X

0

1

Yes

Yes

Yes

No

No (bias)

1b

DO-D5

-

-

No tone

0

X

X

0

1

No (bias)

X

Yes

No

No (bias)

2

Tone

1

0

0

0

1

No (o/c)

X

No

Yes

No (bias)

3a

Tone

1

1

0

0

1

No (o/c)

X

No

Yes

Yes

3b

Tone

1

X

1

1

0

No (o/c)

X

No

Yes

Yes

4

No tone

1

X

X

X

0

No (o/c)

X

No

Yes

Yes

5

olc = open circuit
X = don't care

Table 1 - Combinations of Input/Output Conditions

Notes:
1a.
1b.
2
3a.
3b.
4.
5.

Normal tone transmit condition.
Tone transmit with phase reversed.
Notone programmed in TX mode, tone transmit O/P set to Vorf2 - O.7V. TX audio path enabled.
Normal decode standby.
Normal decode standby with PTL used to enable audio.
Normal decode of correct CTCSS tone condition, PTL has no effect.
Notone programmed in RX mode, tone transmit O/P (o/c). RX audio path enabled.

FILTER RESPONSE
Gain (dB)
0
-10
-20

crcss Frequencies

Voiceband Frequencies

-30
-40
-50
-60

250.3

-70
100

200

300

400

Frequency (Hz)
Figure 3 - Voiceband Filter Response
Page 164

MX-COM, INC.

MX1658
SERIAL AND PARALLEL MODE TIMING

,

k

DO-~

--------------_____________ .... : ; '-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

RX/TX, PTL

,,
,,, -" ""

r~tt~{LATCH

-----

,.,.

tl

----------t--n----------------------,
,

"

-(Note)

~

:..

tsp

I

Note: For wired, non microprocessor applications LoadlL.rtCh should be connected to V 00.
tl min. = 400ns
tsp min. = 400ns

Figure 4 - Parallel Mode (not to scale)

~~~~CEI

'----"',
) )
!
{O--__
J';~~ ______________________________________________________________________________ \0,
, .

,,
,

'----"':;(------------------------------------------------1--1---------------------------- 10,

~~~~CE2

O----J : ~--r'------------------------------------~

---:

DATA
(Note)

i----

Ii

.'~! . . . :
{'-------r---...,
DATAD.

'

IW

DATA 0,

o-------~--I

•

{

I

155 _____:

:-.-

,~---------r-------------------~----

~ ~~----In,---!D.
:

-------~ f-----------~---------------- \

g~~; {:::::j~::::::::~:::::::::~;;:~~~f:~~~;~~~~;::::~ F::::::::::L::::::::::::=--=:
____ J';t~,~ _________ ~ _________ ~~_~~~_~~:~---~~~!~-~::~~----1 ~ ___________ ~ ________________
LOAD!
LATCH

ti=
le=
Iss=
tw=

11=

r---+n-'
----j~,'---------t-!----------------~!-----------l
!

- - - - .....,

mln400nS

min 400nS
min400nS
min400nS
min400nS
min400nS

!

i

I

•

I
•

:

I

D3

~ Ie

!
n "M
:
'
----', :
. ----..
:

X-_-_-_t

PTL

I

o

:

~"/T"

.~---------'.

:. - - . ,

"

SERtAL
CLOCK

, ..

:~

~tL

I
I

I
I

•
•

I
I

:

----i

•

I

I

I

J :

i
"

i

T

T

I

:

!
LOADDATA

~

:---+I

:

0,
Do

!
I LA.

I

I.

DATA

! , LATCHED
L LATCH DATA

Note 1: Serial bit llhrough bit B= Os. D•. 0 3 • D•. D •. Do. RxiT" and PTL respectively.
Load bit 1 first. bit BiasI.

Figure 5 - Serial Mode (not to scale)
MX-COM, INC.

Page 165

MX1658

Tone
Nominal
Frequency (Hz)
67.0
69.3
71.9
74.4
77.0
79.7
82.5
85.4
88.5
91.5
94.8
97.4
100.0
103.5
107.2
110.9
114.8
118.8
123.0
127.3
131.8
136.5
141.3
146.2
151.4
156.7
162.2
167.9
173.8
179.9
186.2
192.8
203.5
210.7
218.1
225.7
233.6
241.8
250.3
Notone
Serial Input Mode
Test

Programming Inputs

MX165B

67.05
69.32
71.9
74.35
76.96
79.77
82.59
85.38
88.61
91.58
94.76
97.29
99.96
103.43
107.15
110.77
114.64
118.8
122.8
127.08
131.67
136.61
141.32
146.37
151.09
156.88
162.31
168.14
173.48
180.15
186.29
192.86
203.65
210.17
218.58
226.12
234.19
241.08
250.28

4082

Table 2 - CTCSS Tones
Page 166

.6. fo (%)

05

04'

03

02

01

00

1
0

0

1
1
0

Hex

Freq. (Hz)
+0.07
+.03
0
-0.07
-0.05
+0.09
+0.1
-0.2
+0.13
+0.09
-0.04
-0.11
-0.04
-0.07
-0.05
-0.12
-0.14
0
-0.17
-0.17
-0.10
+0.08
+0.02
+0.12
-0.2
+0.11
+0.07
+0.14
-0.19
+0.14
+0.05
+0.03
+0.07
-0.25
+0.22
+0.18
+0.25
-0.30
-0.01
N/A
N/A
N/A

1
0
0

0
0
1
0

0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

3F
39
1F
3E
OF
3D
1E
3C
OE
38

1
0
0
1
0

1
0
1
0
0
1
0
1
0
0
0
1
0
0
1

0
0
0
1
0
0
1
0

1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data
0

1 .
0
0
0
0
0
0
0
0

1
0
0

1
0

10
0

0
0
0

1
0
0
0
0

1
1
0
0
0
0

0
0
0
0
0
0
0
Clock
0

0
0
0

1
0
0
0
0
0
X

0
0

0
0
1
0
0
1
1
0

0

0
0

0
0
1
0
0
0
X

3A
00
1C
OC
18
08
1A
OA
19
09
18
08
17
07
16
06
15
05
14
04
13
03
12
02
11
01
10
00
30
2X
330rany
invalid
address

MX-COM, INC.

MX165B

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

OPERATING LIMITS

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(ref V 88 = OV)
Sink/Source Current
(supply pins)
(other pins)
Maximum Device Dissipation
Operating Temperature
Storage Temperature

T AMB=25°C
Xtal/Clock fo = 1.0 MHz

-0.3 V to Voo + 0.3 V
±30mA
±20mA
100mW
-40°C to +85°C
-55°C to + 125°C

STATIC VALUES
Supply Voltage
Supply Current
TX
RX
Tone Input Impedance
Tone Output Impedance
Audio Input Impedance
Audio Output Impedance
Digital Input Impedance
Input logic"1"
Input logic "0"
Logic "1" output l' source = 0.1 mA
Logic "0" output l' sink - 0.1 mA
DYNAMIC VALUES
Decoder
Decode Input Signal Level
Decode Response Time
Deresponse Time
Decode Selectivity (see Fig. 6)

t

Voo = 3.75V

-0.3 to 7.0 V

1.005*fo.,

Adjacent
Tone

OdS ref. = 100mVrms @ 1kHz
Composite signal: 1kHz test tone at 300 mVrms,
75 mVrms noise (band limited 6kHz gaussian white
noise), 30 mVrms CTCSS tone.

3.0

5.5

V

3.5
3.5

mA
mA
MQ
kQ
MQ
kQ
MQ
V

30%V oo

V

3.75

4

2
2

80%V oo

3

30

3,6,10
3,6,10
3,12

V
V

250
250

180
±0.5

1.005*fo

0.995*fo+1

mVrms
ms
ms
%fo

t

Adjacent
Tone

Figure 6 - Decode Selectivity

MX-COM, INC.

Page 167

I

MX165B

Encoder
Tone Output Level
Tone Frequency Accuracy (f error)
Risetime to 90% nominal O/P:
f o>100Hz
fo<100Hz
Tone Output Load Current
Total Harmonic Distortion
Output Level Variation Between Tones
TX Output Impedance
Audio Filter
Total Harmonic Distortion
Output Noise Level
(input a.c. short circuit, audio switch enabled)
Sinad
Spurious Emissions
Cutoff Frequency
Passband
Bandpass Ripple
Stopband Attenuation <250Hz
Passband Gain 1kHz
Audio Switch
Isolation
Serial/Paraliellnputs (See Figures 3 &4)
Parallel Set-up Time tsp
Load/Latch Pulse Width tl
Serial Clock Pulse Width tc
Serial Set-up Time tss
Serial Clock Frequency

400
-0.3
4,10
4,10

627

55
70

2
11

800
+0.3

-1.0

5
5
+1.0

2.0

5,10
8
9
13
7

2
2
36

33
-2.0

5

3000
2
36
0.5

60

400
400
400
400

ms
ms
mA
%

dB
kQ

0/0

mVrms

40
-48
300

300
5,7

5

mVrms
%f o

dB
dB
Hz
Hz
dB
dB
dB

dB

ns
ns
ns
ns
MHz

NOTES:
1. Refers to RX/TX, PTL, Decode Comparator Input, 00-05.
2. All logic outputs.
3. Composite Signal Test Condition.
4. Any programming tone and RL =10,000, CL =15pF. This includes response to a phase reversal instruction.
5.
1kHz references = OdB.
6. fo> 100Hz (for 100 Hz>fo>67Hz: t = 100/foHz x 250ms)
7. See Figure 3.
8. Measured in a 30kHz bandwidth.
9. Measured with an input level of 100 mV @ 1kHz, in a 30 kHz bandwidth.
10. Per TIA/EIA-603.
11. Ref. to 100 Hz.
12. Complies with TIA/EIA-603, must not decode adjacent fo ±0.5%.
13. Test system resolution is ~ -35dB.
Page 168

MX-COM, INC.

MX·~,IN~.

MX165C

Advance Information

LOW VOLTAGE CTCSS ENCODER/DECODER
WITH TXlRX AUDIO FILTERS
FEATURES

APPLICATIONS

•
•
•
•
•
•

• Mobile Radio Channel Sharing
• Wireless Intercom
• Serves 3-Cell Applications

MX·COM MiXed Signal CMOS
47 CTCSS Tones + Notone
TXlRX Audio Filters
TX Tone Phase Reversals
Serial or Parallel Programming
Meets TIAIEIA-603 Land Mobile Standard"

I

BENEFITS
•
•
•
•

Scanning of any Channel
Improved Sinad
Squelch Tail Elimination
Easy ~P Interface

MX165CLH
24 pin PLCC

MX165CDW
24 pin SOIC

Description

CTCSS. A choice of serial or parallel tone programming
Voice on shared radio channels is multiplexed with a is offered. Operation of the PTL signal during TX reverses
subaudible CTCSS tone as a means of directing mes- the phase of the transmitted CTCSS tone by 180°. This
sages among usergrpups sharing the same RF fre- is used in some radios to eliminate squelch tails.
quency. Continuous ToneControlled Sub-audible Squelch
The MX165C requires a single 3.75-volt supply and a
(CTCSS) mod!Jlates t!1~;~ransiDitte:rWtlh a discrete tone, 1 MHz clock or crystal.
taken from a fieldofag:ID theraogeof67 to 250 Hz, .-------------=--------------,
according to TINEIA-:ap3Sta0dardplus 159.8Hz,
183.5Hz, 189.9Hz, 196.6Hz,1fl9.5Hz, 206.5Hz, .. .!"TO""NE'-"'N.'---_--->I
229.1 Hz, and 254.1 Hz. Groupsofradio rec:eivers.
segregated by common interest and assigo~ ·Wne,
TONE
demodulate the voice/tone mixture for voice mes, ..
DECODE
OUT
sages to be heard.
The MX165C CTCSS Encoder/Decoder enhances voice/tone multiplexing with an on-chip filter
TX TONE OUT
that attenuates TX speech 36dB at frequencies
below 250Hz, while passing signals >300Hz with
PTL
XTA LK
only ±1dB of ripple.
Early CTCSS designs did not filter TX speech,
depending instead on the host transmitter's preemphasis network. At only 6dB/octave, their attenuTX AUDIO OUT
TX AUDIO IN
,
ation of speech components at the higher CTCSS
tones was only a few dB, which resulted in "talk-off' RX AUDIO IN
AX AUDIO our
AUD!ORLTER
(low frequency voice components unsquelching the
receiver audio).
~DE~CO~DE~C~O~MP~AR~fl~O~RR~E~e______-1+
The MX165C features TXlRX selection and a DECODE COMPARATOR IN
LOAD/LATCH pin. A Notone program code has
Figure 1 - Internal Block Diagram
been included to permit scanning channels without
• The following tones are not specified in the TlAiE/A-603 Standard, and do not meet the Standard when used with their adjacent tones: 159.8Hz,
183.5Hz, 189.9Hz, 196.6Hz, 199.5Hz, 206.5Hz, 229. 1Hz, and 254. 1Hz.

MX-COM, INC.

Page 169

MX165C
PIN FUNCTION TABLE

I

1

Voo: Positive Supply.

2

XtalfClock: Input to the on-chip inverter used with a 1 MHz Xtal or external clock source.

3

Xtal: Output of the on-chip inverter (clock output).

4

Load/Latch: Controls 8 on-chip latches and is used to latch RXfTX, PTL, and DO-OS. This pin is
internally pulled to V DO' A logic "1" applied to this input puts the 8 latches in "transparenf' mode. A
logic "0" applied to this input puts the 8 latches in the "latched" mode. In parallel mode data is loaded
and latched by a logic 1-0 transition (see Fig. 3). In serial mode data is loaded and latched by a 01-0 strobe pulse on this pin (see Fig. 4).

5

D5/Serial Enable 1: Data input 05 (in parallel mode). A logic "1" applied to this input together with
a logic "0" applied to 04/Serial Enable 2 will put the device in serial mode (see Fig. 4). This pin is
internally pulled to VDO.

6

D4/Seriai Enable 2: Data input 04 (in parallel mode). A logic "0" applied to this input together with
a logic "1" on pin 5 will place the device in serial mode (see Fig. 5). This pin is internally pulled to V DO'

7

D3ISerial Data Input: Data input 03 (in parallel mode). In serial mode this pin becomes the serial
data input for OS-DO, RXfTXand PTL (see Fig. 4). 05 is clocked first and PTL last. This pin is internally
pulled to V DO.

8

D2ISerial Clock: Data input 02 (in parallel mode). In serial mode this pin becomes the serial clock
input. Data is clocked on the positive going edge (see Fig. 4). This pin is internally pulled to Voo'

9

D1: Data input 01 (in parallel mode). This pin is internally pulled to Voo'

10

DO: Data input DO (in parallel mode). This pin is internally pulled to Voo'

11

Vss: Negative supply.

12

Decode Comparator Ref.: This pin is internally biased to V oJ3 or 2V oJ3 via 1M resistors depending
on the logical state of the RX Tone Decode Out pin. RX Tone Decode Out = 1 will bias this input 2VoJ
3; a logic "0" will bias this input V 00/3. This input provides the decode comparator reference voltage,
and switching of bias voltages provides hysteresis to reduce "chatter" under marginal conditions.

13

RX Tone Decode Out: This is the gated output of the decode comparator. This output is used to
gate the RX Audio path. A logic "0" on this pin indicates a successful decode and that the Decode
Comparator Input pin is more positive than the Decode Comparator Ref. input (see Table 1).

14

Decode Comparator Input: This is the inverting input of the decode comparator. This pin is normally
connected to the integrated output of the RX Tone Detect line.

15

RX Tone Detect: In RX mode this output will go to logic "1" during a successful decode. It must be
externally integrated to control response and deresponse times (see Table 1).

16

TX Tone Out: The CTCSS sinewave output appears on this pin under control of the RXfTX pin. This
pin, when not transmitting a tone, may be biased to Voo-O.7V or O/C (see Table 1).

Page 170

MX-COM, INC.

MX165C
PIN FUNCTION TABLE

17

RXlTX: This input (in parallel mode) selects RX or TX modes (see Fig. 2). In serial mode this function
is serially loaded. This pin is internally pulled to V00 via a 1MQ resistor.

18

PTL: In parallel RX mode this pin operates as a "Push To Listen" function by enabling the RX audio
path, thus overriding the tone squelch function. In parallel TX mode this pin reverses the phase of
the transmitted CTCSS tone (used for squelch tail elimination). In serial mode this function is serially
loaded (see Fig. 2).

19

RX Audio Out: This is the high pass filtered receive audio output pin. This pin outputs audio when
RX Tone Decode = 0, or PTL = 1, or when Notone is programmed (see Table 2). In TX mode this
pin is biased to Voi2.

20

TX Audio Out: This is the high pass filtered transmit audio output pin. In TX mode this pin outputs
audio present at the TX Audio Input pin. In RX mode this pin is biased to Voi2.

21

Bias: This pin is the output of an internally generated Voi2 bias level and would normally be
externally decoupled to Vss via capacitor C7.

22

TX Audio In: This is the TX Audio input pin. In TX mode it may be prefiltered, using the TX audio
path, thus helping to aviod talkoff due to intermodulation of speech frequencies with the transmitted
CTCSS tone. This pin is internally biased to V00/2.

23

RX Audio In: This is the input to the audio high pass filter in RX mode. It is internally biased to Voi2.

24

Tone Input: This is the input to the CTCSS tone detector. It is internally biased to Voi2.

V DD

TONE IN
RX AUD IN
TXAUD IN
BIAS

D5

TX AUD OUT

6 D4

RX AUD OUT

7 D3

8
9
10
11

12

D2
Dl

TONE OUT

DO

RX DETECT

Vss

- - + CaMP. REF

DECODE
CaMP. IN
RX DECODE

MX165CJ

Figure 2 - External Components

MX-COM, INC.

21
20
19
18

13

Component Values
R1
1MQ
R2
560kQ
R3
820kQ
X1
1MHz
C1
0.1J.lF
C2
68pF
C3
33pF
C4
0.1J.lF
C5
0.1J.lF
C6
0.47J.lF
C7
0.1J.lF
C8
0.1J.lF
C9
0.1J.lF
C10
0.1J.lF
C11
0.1J.lF
01
small signal

Tolerances: Resistors: ±10%
Capacitors: ±20%
Xtal: ±O.1%

Page 171

I

MX165C

1/0 CONDITIONS
INPUT PIN
CONDITION

RESULTIFUNCTION

RXITX

PTL

Decode
Compo
Input

RX
Tone
Detect

Tone
Decode

Tone
Transmitter
Enabled

TXTone
Phase
Reversed

TXAudio
Path
Enabled

Tone
Decoder
Enabled

RXAudio
Path
Enabled

Notes

Tone

0

0

X

0

1

Yes

No

Yes

No

No (bias)

1a

Tone

0

X

0

Yes

Yes

No

No (bias)

1b

00-05

1

r-------

I

OUTPUT PIN
CONDITION

--

._----

1
-- ----

--

Yes
--

-

No lone

0

X

X

0

1

No (bias)

X

Yes

No

No (bias)

2

Tone

1

0

0

0

1

No (o/c)

X

No

Yes

No (bias)

3a

Tone

1

1

0

0

1

No (o/c)

X

No

Yes

Yes

3b

---

Tone

1

X

1

1

0

No (o/c)

X

No

Yes

Yes

4

No lone

1

X

X

X

0

No (o/c)

X

No

Yes

Yes

5

olc = open circuit
X = don't care

Table 1 - Combinations of Input/Output Conditions

Notes:
1a.
1b.
2
3a.
3b.
4.
5.

Normal tone transmit condition.
Tone transmit with phase reversed.
Notone programmed in TX mode, tone transmit O/P set to VDrl2. TX audio path enabled.
Normal decode standby.
Normal decode standby with PTL used to enable audio.
Normal decode of correct CTCSS tone condition, PTL has no effect.
Notone programmed in RX mode, tone transmit O/P (ole). RX audio path enabled.

FILTER RESPONSE

Gain (dB)
0
-10
-20

CTCSS Frequencies

Voiceband Frequencies

-30
-40
-50
-60

250.3

-70
100

200

300

400

Frequency (Hz)
Figure 3 - Voiceband Filter Response

Page 172

MX-COM, INC.

MX165C
SERIAL AND PARALLEL MODE TIMING
I

-------------~ ~

DO-Q5

RX[TX, PTL

-- - -- - -- -- - --

--:;

'--------------------------

I

I
I

I
I

I

.........
~I
I
I

-

f~~~{LATCH

-----

I
I
1
.......- I

----------t--n~----

tl

------------------

-(Note)

I

--I"~:

~tsp

I

Note: For wired, non microprocessor applications Load/Latch should be connected to V DD'

II min. = 400ns
tsp min. = 400ns

Figure 4 - Parallel Mode (not to scale)

1.m__

~~~~CEI {O ....J:;~~
I
I
I

D.

.

I

0-----' :

--.J
DATA

)

:;!(_____________

1______

~~~~CE2

(Note)

l
!
....---.---------------------------------_____________________________________
m

________________________________
\ __
\ _____ - - - - - - - - - - - - - - - - - - - - - - -

I-- ti

}
{1-------r-----'
~---J·

DATA

I n

0

:

Iw

I •

0,

I

:

~

OATAD.

:'---lr-----.J

O_______

{

D.

;

I

SERIAL
CLOCK

!

I

I'

:l~'

tss ______:

~

PTL

X_--.-_lDl

~_---~.

I

!1l------In~_!D2

----', :,.----------r-------------------~--- . . . ------------~

I
~-----------~----------------,

g~~: {:::::(i\::::::::t:::::::::~:~:;:~~l:~~~:~~~~;::::~ (:::::::::::f::::::::::::::.::: ~
______,~t~.~ _________ ~ _________ ~~_~~~_~~:~--..~~~~-~::~~----1 ~ ___________~ ________________
:
i
:---t r-r-----+-n-:
!Ui.
------>,'----.. .1.________.;!_______~
!
00

tl

LOAD!
LATCH

----"'"

I

I

I

ti=
te=
155=

Iw=

lJ=

min400nS
min 400nS
min400nS
min400nS

min400nS
min400nS

t
I

:
:

'
I

I

:
:

i

i

T

T

I

I

I
I

I
I

I
I

I

~

I

I

I

I

I

:

:

!

LOAD DATA

~

t---r-

t2

DATA
LATCHED

! 1
L LATCH DATA

Note I . Serial bil I through bilS= 0,. D~. 0 3 • O2 • 0,. Do. RxiTx and PTL respectively.
Load bil I first. bit Slast.

Figure 5 - Serial Mode (not to scale)

MX-COM, INC.

Page 173

MX165C

Tone
TIAJEIA-603
Nominal
Frequency (Hz)

I

67.0
69.3
71.9
74.4
77.0
79.7
82.5
85.4
88.5
91.5
94.8
97.4
100.0
103.5
107.2
110.9
114.8
118.8
123.0
127.3
131.8
136.5
141.3
146.2
151.4
156.7
159.8
162.2
167.9
173.8
179.9
183.5
186.2
189.9
192.8
196.6
199.5
203.5
206.5
210.7
218.1
225.7
229.1
233.6
241.8
250.3
254.1
Notone
Serial Input Mode

·

·
·
··

·
·
·

Programming Inputs

MX165C
Freq. (Hz)
66.98
69.32
71.901
74.431
76.965
79.677
82.483
85.383
88.494
91.456
94.76
97.435
99.96
103.429
107.147
110.954
114.84
118.793
123.028
127.328
131.674
136.612
141.323
146.044
151.441
156.875
159.936
162.311
167.708
173.936
179.654
183.680
186.289
190.069
192.864
196.329
199.312
203.645
206.207
210.848
217.853
225.339
229.279
233.359
241.970
250.282
254.162

Table 2 - CTCSS Tones

Page 174

.i fa (%)
·0.029
0.024
0.001
0.042
·0.046
·0.029
-0.021
-0.020
-0.007
-0.048
-0.042
-0.036
-0.040
-0.069
-0.05
0.049
0.035
-0.006
0.023
0.022
-0.095
0.082
0.016
-0.107
0.027
0.112
0.085
0.069
-0.114
0.078
-0.137
0.098
0.048
0.089
0.033
-0.138
-0.094
0.071
-0.142
0.070
-0.113
-0.160
0.078
-0.103
0.070
-0.007
0.024
N/A
N/A

05
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
1
1
0
1
0
0
0
1
0
0
0
1
1

04

03

1
1
0

1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
1
0
1
1
1
1
0
1
1
0
1
1
0
1
0
1
1
0

1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Data

02

01

1
0
1
1

1
0

1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
0
1
0
0
1
1
0
1
0
0
0
1
0
0
0
0
0
Clock

1
0
1
0
1
1
0
1
0
0
0

1
0
0
0
0
1
1
1
0
1
0
0
0
1
0
1
1
0
0
1

1
0
1
0
0
0
0
0
X

00

Hex

1
0
1
1
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
1
0
0
0
0
X

3F
39
1F
3E
OF
3D
1E
3C
OE
38
10
3A
OD
1C
OC
18
08
1A
OA
19
09
18
08
17
07
16
31
06
15
05
14
32
04
33
13
34
35
03
36
12
02
11
37
01
10
00
38
30
2X

oNot specified in the TIAIEIA-603 tone set, and does not meet the
TIAIEIA-603 specification when used w~h their adjacent tones.

MX-COM, INC.

MX165C

FN
(Hz)

67.000
69.300
71.900
74.400
77.000
79.700
82.500
85.400
88.400
91.500
94.800
97.400
100.000
103.500
107.200
110.900
114.800
118.800
123.000
127.300
131.800
136.500
141.300
146.200
151.400
156.700
159.800
162.200
167.900
173.800
179.900
183.500
186.200
189.900
192.800
196.600
199.500
203.500
206.500
210.700
218.100
225.700
229.100
233.600
241.800
250.300
254.100

Band Separation-

FA -1.23%

(Hz)

(Hz)

NA
1.130
1.371
1.256
1.246
1.312
1.370
1.420
1.461
1.489
1.637
0.963
0.844
1.657
1.812
1.854
1.974
1.958
2.121
2.147
2.119
2.473
2.403
2.242
2.648
2.789
0.486
-0.283
2.635
3.058
2.776
0.622
-0.419
0.601
-0.357
0.151
-0.721
0.644
-0.846
0.723
3.421
3.378
-0.369
0.244
4.227
4.195
-0.515

66.157
68.465
71.017
73.516
76.018
78.697
81.469
84.333
87.288
90.331
93.595
96.237
98.731
102.157
105.829
109.590
113.428
117.332
121.515
125.762
130.055
134.932
139.585
144.248
149.579
154.946
157.970
160.316
165.646
171.797
177.445
181.422
183.999
187.732
190.493
193.915
196.862
201.141
203.671
208.256
215.175
222.569
226.460
230.489
238.995
247.204
251.037

Band Separation+

(Hz)

66.980
69.317
71.901
74.431
76.965
79.677
82.483
85.383
88.374
91.456
94.760
97.435
99.960
103.429
107.147
110.954
114.840
118.793
123.028
127.328
131.674
136.612
141.323
146.044
151.441
156.875
159.936
162.311
167.708
173.936
179.654
183.680
186.289
190.069
192.864
196.329
199.312
203.645
206.207
210.848
217.853
225.339
229.279
233.359
241.970
250.282
254.162

Table 3 - CTCSS Decode Performance for the MX165C

MX-COM, INC.

FA +1.23%

FA
(Hz)

67.804
70.169
72.785
75.346
77.911
80.656
83.497
86.432
89.461
92.580
95.925
98.633
101.189
104.700
108.464
112.318
116.252
120.254
124.540
128.893
133.293
138.292
143.060
147.840
153.303
158.804
161.902
164.307
169.770
176.074
181.863
185.938
188.580
192.406
195.235
198.743
201.763
206.149
208.742
213.441
220.532
228.110
232.098
236.228
244.945
253.359
257.287

Band SeparationBand Separation+

(Hz)

1.150
1.371
1.243
1.269
1.391
1.431
1.476
1.526
1.582
1.746
0.988
0.867
1.793
1.964
1.881
1.908
1.954
2.131
2.123
2.248
2.524
2.302
2.409
2.803
2.614
0.197
-0.513
2.754
3.161
2.926
0.719
-0.669
0.371
-0.570
0.382
-0.240
0.720
-0.682
0.904
3.569
4.040
-0.155
0.334
4.363
4.104
-0.529

I

NA

=DBJi] - 1.005*F [i-1]
=O.995*F [i+1] - DBH[i]
N

N

Page 175

MX165C
SPECIFICATIONS

I

ABSOLUTE MAXIMUM RATINGS

OPERATING LIMITS

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(ref Vss = OV)
Sink/Source Current
(supply pins)
(other pins)
Total Device Dissipation
Derating
Operating Temperature
Storage Temperature

Voo = 5.0V

-0.3 to 7.0 V

Vss = OV

-0.3 V to Voo + 0.3 V

Xtal/Clock fo = 1.0 MHz

±30mA
±20mA
800mW max.
10mW/oC
-40°C to +85°C
-55°C to + 125°C

OdB ref. = 300mVrms

Encoder
Tone Output Level (relative to 775 mVrms)
Tone Frequency Accuracy (f error)
Risetime to 90% nominal O/P:
fo>100Hz
f o<100Hz
Total Harmonic Distortion
Output Level Variation Between Tones

Page 176

@

1kHz

Composite signal: 300 mVrms 1kHz test tone,
75 mVrms noise (band limited 6kHz gaussian white
noise), 30 mVrms CTCSS tone.

STATIC VALUES
Supply Voltage
Supply Current
TX
RX
RX Monitor
Tone Input Impedance
Tone Output Impedance
RX and TX Audio Input Impedance
RX and TX Audio
.ut Impedance
Digital Input I
Input logic"1::·
Input logic<:;;·
Logic "1" outpu
Logic "0" output l'
DYNAMIC VALUES
Decoder
Decode Input Signal Level
Decode Response Time
Deresponse Time
Decode Selectivity
Upper Decode Band Edge
Lower Decode Band Edge

T AMB =25°C

2.75

3.75/5.0

5.5

V
mA
mA
mA
MQ
kQ
MQ
kQ
MQ
V
V
V
V

3.0
3.0
2.0
1
1
1
1
1
70%V oo
30%V oo
80%V oo
20%V oo

250
250
3,11
3,11

Hz
Hz

548
-0.3

-1.0

mVrms
%fo

775

15
45
2

4,10
4,10
11

mVrms
ms
ms

75
120
5
+1.0

150
150

ms
ms
%
dB

MX-COM, INC.

MX165C

Of!

'''''''M'''

Audio Filter
Total Harmonic Distortion
Output Noise Level
(input a.c. short circuit, audio switch enabled)
Sinad
Spurious Emissions
Cutoff Frequency
Passband
Bandpass Ripple
Stopband Attenuation <250Hz
Passband Gain 1kHz
Audio Switch
Isolation
Serial/Parallel Inputs (See Figures 3 &4)
Parallel Set-up Time tsp
Load/Latch Pulse Width tl
Serial Clock Pulse Width te
Serial Set-up Time tss
Serial Clock Frequency

5,10
8
9

2
2
36

5

40

36
0

dB
dB
Hz
Hz
dB
dB
dB

eo

dB

-48
300
5
5

300
-1
33

.:;fr.

400
400
400
400

0/0
mVrms

3000
+1

ns
ns
ns
ns
MHz

NOTES:
1. Refers to RX/TX, PTL, Decode Comparator Input, 00-05.
2. All logic outputs.
3. Composite Signal Test Condition.
4. Any programming tone and RL = 10kn, CL = 15pF. This includes response to a phase reversal instruction.
5. 1kHz references = OdB.
6. fo> 100Hz (for 100 Hz>fo>67Hz: t=100/foHz x 250ms)
7. See Figure 3.
8. Measured in a 30kHz bandwidth referenced to 300 mV.
9. Measured with an input level of 300 mV @ 1kHz, in a 30 kHz bandwidth.
10. Per TIAIEIA-603.
11. Only for the Fj in TIAIEIA-603, where Fj is the program tone.

MX-COM, INC.

Page 177

I

I

MX·~,IN~.

MX365A

CTCSS ENCODERIDECODER
WITH TXlRX AUDIO FILTERS

FEATURES
•
•
•
•
•

39 CTCSS Tones + Notone
TXlRX Audio Filters
TX Tone Phase Reversals
Serial or Parallel Programming
Low Voltage: 4.5 to 5.5 V

MX365AJ (CDIP)
MX365AP (PDIP)
24 pins

BENEFITS
•
•
•
•

Scanning of any Channel
Improved Sinad
Squelch Tail Elimination
Easy I1P Interface

MX365ALH
24 pin PLCC

MX365ADW
24 pin SOIC

APPLICATIONS
• Mobile Radio Channel Sharing
• Wireless Intercom
• TIAlEIA-603 - 37 Tone Plus 97.4Hz &
69.3Hz

Description

""

",

Early CTCSS'designs did not filterTX speech, depending
Voice on shared radio channels is multiplexed with a instead:en thehOsttransmitler'S"pra-emphasis network.
subaudible CTCSS tone as a means of directing mes- . M~:otily~dB/octave, their, ~teffoation of speech composages among user groups sharing the same RF .fre",i\~ntsmthe higl:1~r.Ct?S$,tones was only a few dB, which
quency. Continuous Tone Controlled Squelch System: 'resulted "i!'l"talk~ff" (low frequency voice components
(CTCSS) modulates the transmitter with adlspretl';ltone, un~uelcbing the receiver audio).
taken from a field of 39 in the range" Of 67: to 250 Hz.
according to TIAIEIA-603 Standard:pluS69.3Hz and The MX365A features TXlRX selection and a LOAD/
97.4Hz. Groups of ra9ioteQeivers, segregated by com': ,tATCH pin. A Notone program code has been included to
mon interest and ~gn~tone, demOdulatErthe voice/ permit scanning channels without CTCSS. A choice of
tone mixture for voice messages to be fieard.'
serial or parallel tone programming is offered. Operation
of the PTL signal during TX reverses the phase of the
The MX365A CTCSS Encoder/Decoder enhances voice/ transmitted CTCSS tone by 1800 • This is used in some
tone multiplexing with an on'-t:hip filter that attenuates TX radios to eliminate squelch tails.
speech 36dB at 250Hz, while passing signals >300Hz with
only ±1dB of ripple.
The MX365A requires a single 5-volt supply and a 1MHz
clock or crystal.

Page 178

MX-COM, INC.

~

8

~

XTALJCLOCK

~

V.IAS

XIAL

V.IAS

TX AUDIO IN
TXA DIO OUT
AX AUDIO IN
AXt DIO OUT

~
~

TONE IN

ONE DETECT

LOAD/~

SERIAL ENABLElD5

SERIAL ENABLE/D.

8-BIT
SERIAL
SHIFT
WITH

SERIAL DATNDa
SERIAL CLOCKlD2
D,
Do

a-BIT
LATCH

PROGRAM
LOGIC

ONE OUT

JAM

RXI1X

TX ENABLE

INPUTS

PTL
CLOCK

VooVss_
V.IAS _
DECODE COMPARATOR REF.
DECODE COMPARATOR IN

AX TONE DECODE OUT

~

~

......

(;:l

Figure 1 - MX365A Internal Block Diagram

-

s::

><
w
Q)
U1

»

MX365A
PIN FUNCTION TABLE
Pin

Function

MX165A
MX365A

I

1

V DD : Positive Supply.

2

XtallClock: Input to the on-chip inverter used with a 1 MHz Xtal or external clock source.

3

Xtal: Output of the on-chip inverter (clock output).

4

Load/Latch: Controls 8 on-chip latches and is used to latch RXlTX, PTL, and DO-OS. This pin is
internally pulled to V 00' A logic "1" applied to this input puts the 8 latches in "transparent" mode. A logic
"0" applied to this input puts the 8 latches in the "latched" mode. In parallel mode data is loaded and
latched by a logic 1-0 transition (see Fig. 3). In serial mode data is loaded and latched by a 0-1-0 strobe
pulse on this pin (see Fig. 4).

5

D5/Seriai Enable 1: Data input 05 (in parallel mode). A logic "1" applied to this input together with
a logic "0" applied to 04/Serial Enable 2 will put the device in serial mode (see Fig. 4). This pin is
internally pulled to V 00'

6

D4/Seriai Enable 2: Data input 04 (in parallel mode). A logic "0" applied to this input together with
a logic "1" on pin 5 will place the device in serial mode (see Fig. 5). This pin is internally pulled to V 00'

7

D3/Seriai Data Input: Data input 03 (in parallel mode). In serial mode this pin becomes the serial data
input for OS-DO, RXlTX and PTL (see Fig. 4). 05 is clocked first and PTL last. This pin is internally
pulled to V 00'

8

D2ISerial Clock: Data input 02 (in parallel mode). In serial mode this pin becomes the serial clock
input. Data is clocked on the positive going edge (see Fig. 4). This pin is internally pulled to Voo'

9

01: Data input 01 (in parallel mode). This pin is internally pulled to V 00'

10

DO: Data input DO (in parallel mode). This pin is internally pulled to Voo'

11

Vss: Negative supply.

12

Decode Comparator Ref.: This pin is internally biased to V od3 or 2Vod3 via 1M resistors depending
on the logical state of the RX Tone Decode Out pin. RX Tone Decode Out = 1 will bias this input 2V od
3; a logic "0" will bias this input V od3. This input provides the decode comparator reference voltage,
and switching of bias voltages provides hysteresis to reduce "chatter" under marginal conditions.

13

RX Tone Decode Out: This is the gated output of the decode comparator. This output is used to gate
the RX Audio path. A logic "0" on this pin indicates a successful decode and that the Decode
Comparator Input pin is more positive than the Decode Comparator Ref. input (see Table 1).

14

Decode Comparator Input: This is the inverting input of the decode comparator. This pin is normally
connected to the integrated output of the RX Tone Detect line.

15

RX Tone Detect: In RX mode this output will go to logic "1" during a successful decode. It must be
externally integrated to control response and deresponse times (see Table 1).

16

TX Tone Out: The CTCSS sinewave output appears on this pin under control of the RXlTX pin. This
pin, when nottransmitting a tone, may be biased to V oo -0.7VorO/C (see Table 1). This pin is an emitter
follower output with high impedance load, requiring capacitive coupling or a low impedance «1 kn) load
to ground.

Page 180

MX-COM, INC.

MX365A
PIN FUNCTION TABLE
Pin

Function

17

RXlTX: This input (in parallel mode) selects RX or TX modes (see Fig. 2). In serial mode this function
is serially loaded. This pin is internally pulled to VDD via a 1MQ resistor.

18

PTL: In parallel RX mode this pin operates as a "Push To Listen" function by enabling the RX audio
path, thus overriding the tone squelch function. In parallel TX mode this pin reverses the phase of the
transmitted CTCSS tone (used for squelch tail elimination). In serial mode this function is serially
loaded (see Fig. 2).

19

RX Audio Out: This is the high pass filtered receive audio output pin. This pin outputs audio when
RX Tone Decode = 0, or PTL = 1, or when Notone is programmed (see Table 2). In TX mode this pin
is biased to VDi2.

20

TX Audio Out: This is the high pass filtered transmit audio output pin. In TX mode this pin outputs
audio present at the TX Audio Input pin. In RX mode this pin is biased to VDi2.

21

Bias: This pin is the output of an internally generated VDD/2 bias level and would normally be externally
decoupled to Vss via capacitor C7.

22

TX Audio In: This is the TX Audio input pin. In TX mode it may be prefiltered, using the TX audio
path, thus helping to aviod talkoff due to intermodulation of speech frequencies with the transmitted
CTCSS tone. This pin is internally biased to VDi2.

23

RX Audio In: This is the input to the audio high pass filter in RX mode. It is internally biased to VDi2.

24

Tone Input: This is the input to the CTCSS tone detector. It is internally biased to VDi2.
NOTE: Pins labeled "N/C" (no connect) may have internal connections. Do Not Use.

TONE IN
RX AUD IN
1)(

24
23

AUD IN
BIAS

7

OS
D4

RX AUD OUT

D3

PTL

D2

RX/1X

9 D1
10 DO

RX DETECT

8

11 Vss
12 COMPo

--

17

TONE OUT

REF

DECODE
COMPo IN
RX DECODE

13

MX365AJ

Figure 2 - External Component Diagram

MX-COM, INC.

~
~

AUD OUT

1)(

Component Values
R1
1MQ
R2
560kQ
R3
820kQ
X1
1MHz
C1
0.1~F
C2
68pF
C3
33pF
C4
0.1~F
C5
0.1~F
C6
0.47~F
C7
0.1~F
C8
0.1~F
C9
0.1~F
C10
0.1~F
C11
0.1~F
01
small signal

TDlerances: Resistors: ±10%
Capacitors: ±20%
Xtal:±O.1%

Page 181

I

MX365A
110 CONDITIONS
INPUT PIN
CONDITION

DO-OS

RESULT/FUNCTION

RXITX

PTL

Decode
Compo
Input

RX
Tone
Detect

Tone
Decode

Tone
Transmitter
Enabled

TXTone
Phase
Reversed

TXAudio
Path
Enabled

Tone
Decoder
Enabled

RXAudio
Path
Enabled

Notes

0

0

X

0

1

Yes

No

Yes

No

No (bias)

1a

1

X

0

1

Yes

Yes

Yes

No

No (bias)

1b

Tone
Tone

0
-

I

OUTPUT PIN
CONDITION

-

No lone

0

X

X

0

1

No (bias)

X

Yes

No

No (bias)

2

Tone

1

0

0

0

1

No (ole)

X

No

Yes

No (bias)

3a

Tone

1

1

0

0

1

No (ole)

X

No

Yes

Yes

3b

Tone

1

X

1

1

0

No (ole)

X

No

Yes

Yes

4

No lone

1

X

X

X

0

No (ole)

X

No

Yes

Yes

5

ole = open circuit
X = don't care

Table 1 - Combinations of Input/Output Conditions

Notes:
1a.
1b.
2
3a.
3b.
4.
5.

Normal tone transmit condition.
Tone transmit with phase reversed.
Notone programmed in TX mode, tone transmit O/P set to VDr/2 - O.7V. TX audio path enabled.
Normal decode standby.
Normal decode standby with PTL used to enable audio.
Normal decode of correct CTCSS tone condition, PTL has no effect.
Notone programmed in RX mode, tone transmit O/P (ole). RX audio path enabled.

FILTER RESPONSE

Gain (dB)
0
-10
-20

CTCSS Frequencies

Voiceband Frequencies

-30
-40
-50
-60

250.3

-70
100

200

300

400

Frequency (Hz)
Figure 3 - Voiceband Filter Response
Page 182

MX-COM, INC.

MX365A
SERIAL AND PARALLEL MODE TIMING
I

~~

•

~ ~~~~ ~~~~~~~~ ~>K. .----------------------

PTL

[rS>O~{LATCH

•
•
•
••
•• • •
••
• .,.
•
••

-----

tl

----------t--n-----------------------

-(Note)

:...

•

--I"~:

tsp

I

Nole: For wired, non microprocessor applicalions Load/Lalch should be connected 10 V00II min. = 400ns
Isp min. = 400ns

Figure 4 - Parallel Mode (not to scale)

~~~:E 1{~~~~~::~('--~----------------------------------------- ____ ~ __)_______

m

______ m

_________

D.

1

~~, ,----~k·---------------------------------------------·\-~----------------------------I
0----"" I,

i

,

~

DATA

{

(Note)

1-------r---.. .';!
I

:

SERIAL
CLOCK

o

----...., I

g<:Z

{

DATAD.

r ~_!

i

Ii:
le=
tss=

tw=
11=

12=

'

~_PTL_X~]D3

DATA 0,

---'H"--'C
I'

i--

11~-----IrL------1

::::::..f;::::::::*:::::::::~;;;:j;:~7;;:~~~~~::::~ ~:::::::::J::::=::=::::::

----J';t~.'----------~---------~-~~:-~~:i..--~~~!~-~::~~- ___ -{ ~ ___________ ~________________
i

____ J;,,~____~!________~!______________~I

----""',

mln400nS
min 400ns
min400nS
min400nS
min400ns
min400nS

D.

l

,~---------r-------------------~-----------------\ t-----------~----------------,

i

LOAD!
LATCH

I
I

I

{

1

tw

:-',...~..!!!---..,

l--li

O_______ ~---J'

0,

I

I
•
I

I

I

r----+-n-

I
I
'

i

T

T

~IL

,
I
I

I
I
I

I
I
I

:

:

'

!
I

!
LOADDATA

Do

:~
l

~

I

: :
"

i

0,

----1

I

r UL

i--+- ~

I

DATA

! , LATCHED
L LATCH DATA

Note 1: Serial bil 1 through bit 8=0•• o~. 0 3. O2 .0 •. 0 0 • RxiTxandPTLrespeclively.

Load bll I firsi. bil8last.

Figure 5 - Serial Mode (not to scale)
MX-COM, INC.

Page 183

MX365A

Programming Inputs

Tone
Nominal
Frequency (Hz)

I

67.0
69.3
71.9
74.4
77.0
79.7
82.5
85.4
88.5
91.5
94.8
97.4
100.0
103.5
107.2
110.9
114.8
118.8
123.0
127.3
131.8
136.5
141.3
146.2
151.4
156.7
162.2
167.9
173.8
179.9
186.2
192.8
203.5
210.7
218.1
225.7
233.6
241.8
250.3
Notone
Serial Input Mode
Test

MX365A

6.fo (%)

05

04

03

02

01

1
0

1
0

00

Hex

Freq. (Hz)

67.05
69.32
71.9
74.35
76.96
79.77
82.59
85.38
88.61
91.58
94.76
97.29
99.96
103.43
107.15
110.77
114.64
118.8
122.8
127.08
131.67
136.61
141.32
146.37
151.09
156.88
162.31
168.14
173.48
180.15
186.29
192.86
203.65
210.17
218.58
226.12
234.19
241.08
250.28

+0.07
+.03
0
-0.07
-0.05
+0.09
+0.1
-0.2
+0.13
+0.09
-0.04
-0.11
-0.04
-0.07
-0.05
-0.12
-0.14
0
-0.17
-0.17
-0.10
+0.08
+0.02
+0.12
-0.2
+0.11
+0.07
+0.14
-0.19
+0.14
+0.05
+0.03
+0.07
-0.25
+0.22
+0.18
+0.25
-0.30
-0.01

4082

N/A
N/A
N/A

1
0
0

1
1
0

0
1
0

1
1
0

1
0
1
0
1
0
0

0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0

3F
39
1F
3E
OF
3D
1E
3C
OE
3B

1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data
0

0
0
0
0
0
0
0
0

1
0
0
0

1
0
1
0
0
0

0
1
0
0

0
0
0
0

0
0
1
1
0
0

10

0
0

1
0
0
0
0
0
0
0
0
0
Clock
0

0
0
0
0

1
0
0
0
0
0

X

0
0

0
0
1
1
0
0
0
X

3A
00
1C
OC
1B
OB
1A
OA
19
09
18
08
17
07
16
06
15
05
14
04
13
03
12
02
11
01
10
00
30
2X
330rany
invalid

Table 2 - CTCSS Tones
Page 184

MX-COM, INC.

MX365A

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

OPERATING LIMITS

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(ref Vss = OV)
Sink/Source Current (Total)
Maximum Device Dissipation
Operating Temperature
Storage Temperature

MX365A V DO = 5.0V
TAMS = 25°C
MX365A OdB ref. = 308mVrms @ 1kHz

-0.3 to 7.0 V
-0.3 V to Voo + 0.3 V
20mA
100mW
-40°C to +85°C
-55°C to + 125°C

Composite signal: OdB 1kHz test tone, 75 mVrms
noise (band limited 6kHz gaussian white noise),
30 mVrms CTCSS tone.

~tj~ •...
STATIC VALUES
Supply Voltage
Supply Current
TX
RX
RX Monitor
Tone Input Impedance
Audio Input Impedance
Audio Output Impedance
Digital Input Impedance
Input logic"1"
Input logic "0"
Logic "1" output l' source = 0.1 mA
Logic "0" output l' sink - 0.1 mA
DYNAMIC VALUES
Decoder
Decode Input Signal Level
Decode Response Time
Deresponse Time
Decode Selectivity (see Fig. 6)
Encoder
Tone Output Level (relative to 775mVrms)
Tone Frequency Accuracy (f error)
Risetime to 90% nominal O/P:
fo>100Hz
fo<100Hz
Tone Output Load Current
Total Harmonic Distortion
Output Level Variation Between Tones
TX Output Impedance

MX-COM, INC.

4.5

5.0

5.5

3.5
3.5
2.5

mA
mA
mA
MQ
MQ
kQ
MQ
V

70%V oo
30%V OD

2
2

80%V OD

3
3,6,10
3,6,10
3,12

-20

V
V
V

180
±0.5

-3
-0.3
4,10
4,10

+3
250
250
±3

dB
ms
ms
%fo

+0.3

dB
%fo

0

15
45
2

11

V

-1.0
2.0

75
120
5
5
+1.0

ms
ms
mA
0/0
dB
kQ

Page 185

I

MX365A

Audio Filter
Total Harmonic Distortion
Output Noise Level
(input a.c. short circuit, audio switch enabled)
Sinad
Spurious Emissions
Cutoff Frequency
Bandpass Ripple (300-3000Hz)
Stopband Attenuation <250Hz
Passband Gain 1kHz
Audio Switch
Isolation
Serial/Parallel Inputs (See Figures 3 &4)
Parallel Set-up Time tsp
Load/Latch Pulse Width tl
Serial Clock Pulse Width tc
Serial Set-up Time tss
Serial Clock Frequency

5,10
8

9

2
-54
36

5
-48

40

36
0

dB
dB
Hz
dB
dB
dB

60

dB

-48
300

7

2
5,7

33

5

400
400
400
400

%
dB

ns
ns
ns
ns
MHz

NOTES:
1. Refers to RX/TX, PTL, Decode Comparator Input, 00-05.
2. All logic outputs.
3. Composite Signal Test Condition.
4. Any programming tone and RL =10,000, CL =15pF. This includes response to a phase reversal instruction.
5. 1kHz references = OdB.
6. fo>100Hz (for 100 Hz>fo>67Hz: t = 100/foHz x 250ms)
7. See Figure 3.
8. Measured in a 30kHz bandwidth.
9. The MX365A is measured with an input level of 308mV @ 1kHz, in a 30 kHz bandwidth.
10. Per TIAIEIA-603.
11. Ref. to 100 Hz.
12. Complies with TIAIEIA-603, must not decode adjacent fo ±0.5%.

Page 186

MX-COM, INC.

MX·~M,IN~.

MX275

LOW VOLTAGE Pvt SQUELCHTM CTCSS ENCODER/DECODER

Features
•
•
•
•
•
•

MX·COM MiXed SIGNAL CMOS
PRIVATE/CLEAR CAPABILITY
ON-CHIP TX AUDIO PRE-fDE-EMPHASIS
ALTERNATIVE TO CTCSS "PARTY LINE"
LOW VOLTAGE
EXCEEDS TIAIEIA-603 LAND MOBILE RADIO STANDARD

SIX SIGMA
BASED

Applications
•
•
•
•
•

MOBILE RADIOS
COMMUNITY REPEATERS
TELEPHONEIRADIO INTERCONNECT SYSTEMS
SPORT RADIOS
SERVES 2- and 3-CELL APPLICATIONS

Filter
0uIput

MX275LH
24-lead PLCC

Balanced
Modulator
Input
CLR

TX Audio
Input

AX Audio
Input '--'-'oo-----~~
1--":":::::"'-1

AX Tone Input
3333 Hz

LoadA.atcl1=:.._ _ _ _-.
Serial Enable
SerIal Da1a Input

SeriaJ Clock Input

RXITX

8-Bit
Shift
Register
and

LD5-I.DO
logic

Con1rOl

'ClJ(2

latI:hes

'BIPH

AX PaIh
TX Path
PrIvate

Control

Private Enable
Push-To-Listen

'CARRIER
'ClKt

PTL

~
~

~

Figure 1 - Internal Block Diagram

MX-COM, INC.

Page 187

MX275
Description
The MX27S is a CMOS lSI combination of a CTCSS encoder/decoder and a simple (frequency
inversion) speech scrambler. CTCSS (Continuous Tone-Controlled Squelch System) multiplexes a subaudible tone (1 of 38) with speech. This is performed continuously in 2-Way Radio systems -- as a means
of segregating the traffic of co-channel talk groups. The MX275 integrated circuit carries this process
an extra step called Pvt SQUElCHTM. This uses the detection of the CTCSS tone to enable the clear
recovery of scrambled speech. As talk groups are assigned unique CTCSS tones, their voice traffic is
rendered intelligible only among its own members. The audio monitored by co-channel users with
different talk group tones is unintelligible.
The MX275 Features

1)
2)
3)
4)
S)

Serial control, but with parallel PTT, PTl and PVT/ClR options.
Squelch Tail Elimination facilitated by 1800 reverse burst option.
On-chip speech filters aid FDM (CTCSS+audio) multiplexing.
Pvt SQUElCHTM operation.
Grants to the 2-Way Radio protection under the ECPA.

Why not Busy Channel Lock Out? (sometimes called Privacy lock Out)

While BClO also affords co-channel users privacy, its implementation is at the discretion of the
receiver, not the sender. BClO prevents inadvertant PTT keying and impolite disruptions by co-channel
users who fail to monitor before transmitting. But BClO provides no protection against scanners nor
under the ECPA. BClO assures politeness, Pvt SQUElCHTM privacy.

Application Notes
Pre- and de-emphasis (6dB/octave) filters are included on-chip in the transmit path, so that the use
of this device will produce natural sounding audio (clear or private modes) when installed in modern radio
communication transceivers, with or without existing audio processing circuitry. The recommended
layout is shown in block form below.

From Receiver
Stages

Figure 2 - The MX275's Transmit and Receive Paths
• Electronic Communications Privacy Act of 1986.

Page 188

MX-COM, INC.

MX275

Pin Function Chart

Voo: The positive 2.7V supply pin.
2

XTAUCLOCK: This is the input to the clock oscillator inverter. An external 4 MHz xtal or
clock input should be applied to this pin.

3

XTAL: This is the 4 MHz output of the clock oscillator inverter.

4

LOAD/LATCH: This input controls the eight input latches: RX/TX, Private Enable, and 00OS, as detailed in Table 2(a). Alternative~e RX/TX and Private Enable inputs can be
addressed separately by setting the Load/Latch and Control inputs as shown in Table 2(b).
1 Mil pullup. An external pull-up or active CMOS drive is recommended.

5-7

Programming Inputs: These are the RXlTX tone programming and function inputs which
enable the serial programming mode. With Load/Latch at logic "0" data is loaded in the
following sequence: OS, 04, 03, 02, 01, DO, RXlTX, Private Enable. When these 8 bits have
been clocked in on the rising clock edge, data is latched by strobing the Load/Latch input
"0 - 1 - 0" (See Figure 4).
Pin 5 = Serial Enable
Pin 6 = Serial Data Input
Pin 7 = Serial Clock Input

8

RX TONE DECODE: The gated output of the decode comparator. In RX, a logic "0"
indicates a valid CTCSS tone decode condition, or the presence of NOTONE programming.
A logic "0" enables the RX audio path. In TX this output is held at logic "1."

9

DECODE COMPARATOR: The voltage level at this pin is compared internally with a
switched 1/3 -% V DD reference that provides hysteresis. An input level exceeding the
reference results in a logiC "0" at the RX Tone Decode output. This input should be externally
connected to the RX Tone Detect output via external integration components C1O' R2 , R3 , and
0 1 (see Figure 3).

10

RX TONE DETECT: In RX, this pin outputs a logical "1" when a valid programmed CTCSS
tone is received at the RX TONE INPUT. This input should be externally connected to the
Decode Comparator input via external integration components C 10 , R2 , R3 , and 0 1 (see
Figure 3).

11

V ss: The negative supply pin (ground).

12

TX TONE OUTPUT: The buffered CTCSS sinewave tone output appears on this pin. In TX
mode, the tone frequency is selected by program code (see Table 1); if NOTONE is
programmed, the output is at VB1AS -0.7V. In RX mode, the output goes open circuit. This is
an emitter follower output with an internal 10 kil load.

13

BIAS: This pin is set internally to approximately V DD/2. It must be externally connected to
VS8 using capacitor C7 and resistor R4 • See Figure 3.

14

FILTER OUTPUT: This is the output of the Input Audio Bandpass Filter. It must be A.C.
coupled to the Balanced Modulator Input via capacitor C4 • See Figure 3.

15

BALANCED MODULATOR INPUT: This is the input to the balanced modulator. It must be
A.C. coupled to the Filter Output via capacitor C4 • See Figure 3.

MX-COM,INC.

Page 189

I

MX275

Pin Function Chart

I

16

RX AUDIO OUTPUT: Outputs the received audio from a buffered output stage and is held at
VBIAS when in TX. Capacitive loads exceeding 15pF should be avoided.

17

TX AUDIO OUTPUT: Outputs the transmitted audio in TX. In RX, this pin is held at VBIAS'
Capacitive loads exceeding 15pF should be avoided.

18

RX AUDIO INPUT: The audio input for the RX mode. Input signals should be AC coupled via
external capacitor Cs' See Figure 3.

19

TX AUDIO INPUT: This is the TX Audio voice input. Signals should be AC coupled via external
capacitor C11" See Figure 3.

20

PTL: The "press to listen" function input. In RX mode, a logic "0" enables the RX Audio Output
directly, overriding tone squelch but not intercepting a private conversation; in TX mode, a logic
"0" reverses the phase of the TX Tone Output for "squelch tail" reduction (see Table 2).

21

CONTROL: This input, together with Load/Latch, selects the operational mode of the RXlTX
and Private Enable functions. See Table 2(b).

22

RXlTX: This input selects the RX or TX mode (RX = 1, TX = 0). See Table 2.

23

PRIVATE ENABLE: This input selects either Private or Clear mode (Clear =1, Private =0), and
is loaded as described in Table 2. This input has an internal 1 Mil pullup resistor.

24

RX TONE INPUT: This is the received audio input to the on-chip CTCSS tone decoder. It should
be A.C. coupled via capacitor Cs '
+2.7V

C~ C2
~

+2.7V

MX275LH
RXTONE 24
~ CTess TONE IN (RX)
PRIVEN 1-"2".3...._ _ PRIVACY ENABLE

Xl

Rl

00AD/LATCH

RX/TX 22
PUSH TO TALK
CONTROL 21
MODE SELECTION
PTL 20
PUSH TO LISTEN
TXIN 19
p;;1LTX AUDIO IN
RXIN 18
~RX AUDIO IN
TXOUT 17
I C12 TX AUDIO OUT
RXOUT 16
~ RX AUDIO OUT
BALMOD 1-:1-;5_ _--,
4 _ _-+."::"':-_-,
FILTER 1-:1-::BIAS f-l_3.,..-_-,

COMPONENT VALUES

Rl =lMQ
R2=560kQ
R3=820kQ
R4=560kQ
Xl =4MHz
Tolerances: Resistors: ±5%

Cl = l!lF
C2 = 33pF
C3= 33pF
C4=0.1!lF
C5=0.1!lF
Capacitors: ±10%

Figure 3 - External Component Connections

Page 190

C6=0.1!lF
C7= l!lF
C8 = O.l!lF
C9 = O.l!lF
Cl0=0.1!lF

Cll=O.l!lF
C12=0.lflF
C13 = O.OOlflF
Dl = small signal

XTAL: At cut, fundamental, parallel resonant
20pF load capacitance, tolerance 100 PPM.

MX-COM, INC.

MX275

TIAIEIA-603
Nominal
Frequency
Frequency(Hz)
(Hz)
67.0
71.9
74.4
77.0
79.7
82.5
85.4
88.5
91.5
94.8
97.4
100.0
103.5
107.2
110.9
114.8
118.8
123.0
127.3
131.8
136.5
141.3
146.2
151.4
156.7
162.2
167.9
173.8
179.9
186.2
192.8
203.5
210.7
218.1
225.7
233.6
241.8
250.3
Notone

67.05
71.9
74.35
76.96
79.77
82.59
85.38
88.61
91.58
94.76
97.29
99.96
103.43
107.15
110.77
114.64
118.8
122.8
127.08
131.67
136.61
141.32
146.37
151.09
156.88
162.31
168.14
173.48
180.15
186.29
192.86
203.65
210.17
218.58
226.12
234.19
241.08
250.28

Programming Inputs

A fa (%)
+0.07
0
-0.07
-0.05
+0.09
+0.1
-0.2
+0.13
+0.09
-0.04
-0.11
-0.04
-0.07
-0.05
-0.12
-0.14
0
-0.17
-0.17
-0.10
+0.08
+0.02
+0.12
-0.2
+0.11
+0.07
+0.14
-0.19
+0.14
+0.05
+0.03
+0.07
-0.25
+0.22
+0.18
+0.25
-0.30
-0.01

05

04

03

02

01

DO

HEX

1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1

1
1
1
0
1
1
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0

1
1
1
1
0
1
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0

1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0

3F
1F
3E
OF
3D
1E
3C
OE
38
10
3A
00
1C
OC
18
08
1A
OA
19
09
18
08
17
07
16
06
15
05
14
04
13
03
12
02
11
01
10
00
30

Table 1 - CTCSS Programming Chart

No change while serial data train is loaded
Loaded serial data is latched

Serial Control Input
Serial Control Input
Notes:

RXlTX, Private Enable
Serial Load
Transparent

"0 - 1 - 0" is a strobe pulse as shown in Figures 4 and 5 (Timing).
"X" denotes any logical state.

Table 2 - Load/Latch and Control Functions

MX-COM,INC.

Page 191

I

MX275
Control instructions are input to the MX275 by serial means, using Data Inputs and Load!
Latch as shown below.
1

1

SERIAL

ENAB~

~I-----------------------------------tSMS_1
'--I
1

1 tPWH 1

1
1

1
1
1

:_tOS_1

1_---------.;

~

SERIAL DATA
INPUT
~_______---01

I

1

~

1
1

1
1

'------><= =t><1

1

--t LL

1

LOAD/LATCH

1
-I

1

1

----------------------------------- ~

Figure 4 - Serial Load Timing (see notes 1 and 9 in Specification section)

TONE
TONE
NOTONE
TONE
TONE
TONE
NOTONE
TONE
TONE
NOTONE
TONE
TONE
TONE
NOTONE

1
1

a
1
1
1

a

a
0

a
1
1
1
1

1
1

a
a
a

1
1
1

1
1
1
1

a
a

a
a
a
a
0

1

a

x
1
0

a

x

0
1
1
1
1
1
1
1

X
1

a
a
a
a
a
1
X

a

a
a
a
a
a

X
X

1
X

a

x
1

1
1
1
1
1

a
a
1
1
1
1
1

a
0

YES
YES
BIAS
BIAS
BIAS
BIAS
BIAS
YES
YES
BIAS
BIAS
BIAS
BIAS
BIAS

0°
180°
X
X
X

x
x

0°
180'
X
X
X

x
X

OPEN
OPEN
OPEN
BIAS
BIAS
BIAS
BIAS
OPEN
OPEN
OPEN
BIAS
BIAS
BIAS
BIAS

BIAS
BIAS
BIAS
BIAS
OPEN
OPEN
OPEN
BIAS
BIAS
BIAS
BIAS
OPEN
OPEN
OPEN

INV
INV
CLR
X
CLR
INV
CLR
CLR
CLR
CLR
X
CLR
CLR
CLR

TX, TONE
TX, TONE REV
TX, NOTONE
INCOMPATIBLE
INCOMPATIBLE
COMPATIBLE
RX, NOTONE
TX, TONE
TX, TONE REV
TX, NOTONE
INCOMPATIBLE
INCOMPATIBLE
COMPATIBLE
RX, NOTONE

ALGEBRAIC FUNCTIONS:
RX PATH ON = RX* (PTL + RX TONE DECODER)
CLEAR PATH = NOTONE + PRIVATE ENABLE + (PTL * RX* RX TONE DECODER)
NOTONE (00-05) = 000011
CARRIER FREQUENCY = 3333Hz DURING INVERTED PATH(TX or RX)
NOTES: 1, The Pre- and De-emphasis circuits remain in the transmit path in both Clear and Invert modes.
2, Power remains applied to the CTCSS tone decoder at all times.
3, During Clear operation the carrier frequency is turned off to reduce spurious emissions.

Table 4 - Functions and Outputs

Page 192

MX-COM, INC.

MX275

Specifications
Absolute Maximum Ratings

Operating Limits

Exceeding the maximum rating can result in
device damage. Operation of the device outside
the operating limits is not suggested.

Measured using the standard test circuit
(Fig. 3) and under the following conditions
unless otherwise noted.

Supply Voltage
Input Voltage at any pin
Sink/Source Current
(Supply pins)
(Other pins)
Total Device Dissipation
@ TAMS 25°C
Derating
Operating Temperature
Storage Temperature

Static Values
Supply Voltage
Supply Current

-0.3 to 4.0 V
-0.3V to (Voo + 0.3 V)
±30 mA
±20 mA
800 mW max.
10 mW/oC
-15°C to +60°C
-55°C to + 125°C

Composite input signal =300 mVrms,
1 kHz tone in, 75 mVrms (6 kHz band limited)
gaussian noise, and a 30 mVrms CTCSS tone.

2.2

2.7

TX
RX

Impedances

Speech In
Speech Out
Tone In
Tone Out

I/O Logic

Input "1"
Input "0"
Output "1" (source 0.1 mAl
Output "0" (sink 0.1 mAl

2.7V
25°C
4.0 MHz
250 mVrms

Voo
TAMS
Xtal/Clock fo
Audio level OdS ref

3.2
4.0
3.0

V
10.0
4.6

mA
mA

155
850
540
1800

223
1200
664
2966

kQ
Q
kQ
Q

30%
20%

Serial Clock

Voo
Voo
Voo
Voo
ns

Dynamic Values
CTCSS Encode
Tone Output Level
Tone Accuracy
Distortion
T-T Level D
Risetime to 90%
180°Phase Reversal
CTCSS Decode
Signal Threshold
Must Decode S/E

MX-COM,INC.

2

350
-0.3

400
fo
3.5
13
10
10

460
0.3
5
47
50
50

mVrms
%fo
%
mVrms
ms
ms

30
-0.5

10
±2

0.5

mVrms
%fo

?100Hz
90% ?100Hz

4

Page 193

I

MX275

CTCSS Decode•••
Response Time
> 100 Hz
Deresponse Time >100 Hz
Don't Decode B/E Adjacent Tone

t

1.005*f0-1

Adjacent
Tone

4,5
4

170
150
±1

0.5

0.995*fo

t

1.005*10

0.995*fo+1

250
250

-0.5

ms
ms
%

t

Adjacent
Tone

to

Figure 5 - Do Not Decode Band-edge Adjacent Tone

Speech Filter
TXlRX
Passband
Passband Gain
Ripple
Clear
Distortion
CTCSS Rejection f1n<250Hz
AC/SC Noise

3
3,7
3,7
3
3
6

Scrambling
TXlRX
Inversion Carrier
Carrier Breakthrough
Baseband Breakthrough
Carrier Rejection
f;n>3333Hz
Baseband Reject
f;n>3633Hz

1,3
1,3
3
3

300
-1.5
-3

0

25

6
32
2.5

7.9

3333
-58
-54

3336.3
-46
-42

3329.7

20
45

3000

10

Hz
dB
dB
%
dB
mVrms

Hz
dB
dB
dB
dB

1. Untested parameter - derived by statistical characterization.
2. An emitter follower output.
3. With reference to an input signal of 1 kHz @ OdB.
4. Composite signal.
5. fo > 100 Hz, (for 100Hz> fo > 67Hz: t = [100/fo(Hz)] x 250ms), per ANSIITIAIEIA-603.
6. AC Short-Circuit input, speech path enabled.
7. <6dB per octave roll-off, <500 Hz >2500 Hz per ANSIITIAIEIA-603
8. Capacitive loads not to exceed 15pf.
9. External Pull-Up or active CMOS drive recommended.
10. Includes LOAD/LATCH don't load immunity testing.

Page 194

MX-COM, INC.

MX·~M,IN~.

MX375

Pvt SQUELCHTM CTCSS ENCODER/DECODER

Features
•
•
•
•

PRIVATEICLEAR CAPABILITY
ON-CHIP TX AUDIO PREIDEEMPHASIS
POWERSAVE OPTION
ALTERNATIVE TO STANDARD CTCSS
"PARTY LINE"

MX375P 28-pin PDIP
MX375J 28-pin CDIP
MX375LH
24-lead PLCC

Applications
• MOBILE RADIOS
• COMMUNITY REPEATERS
• TELEPHONEIRADIO INTERCONNECT
SYSTEMS

MX375LH8
28-lead PLCC

Balanced
Modulator
Input
CLR
TX Audio
Input

AX Audio
Input :...+11X1-----~~

;: ;=i>-

,.,

L..-......;...:::=<;...I

AX Tone Input

1

-I

-

Reference

Fillers

,.

DO Input

RXfTX
Control

Private Enable

,.
'"

03 or Serial Oata Input
01 Input

H

Y
,
8·BIt
Shift
Register
and
Latches

,
,
,.

Push·To·Usten

AX Tone Oecoder Output
OAmdA

r.om...",tnr
nAt"'"

Innlli

Olltnld.

3333 HZ-===]"]

A

04 or Serial Enable 2
02 or Serial Clock Input

Hysteresis

~

RX TmA

CTCSS
Tone Oetect

LoadILatch
05 or Serial Enable 1

~3333HZ

Clocks

L05-LOO

Logic
Control

TXTone
Output

'CARRIER

I
I
NoTone Output

~1

V

'~~H
~
AX Path

~TXPaIh
Private

tm

...

VWAS

~

Figure 1 - Internal Block Diagram
MX-COM, INC.

Page 195

I

MX375
DESCRIPTION
The MX375 is a CMOS LSI microcircuit which combines CTCSS Encode/Decode operation with voice band
frequency inversion. Frequency inversion is achieved by modulating the input audio with a 3333 Hz carrier frequency.
Higher voice band frequencies are translated downward, and lower frequencies upward, resulting in a "mirror image"
voice transmission.

Device features:
1)
2)
3)
·4)
5)

I

serial or parallel tone programming capability (serial or parallel offered on MX375J, P & LH8),
the ability to operate under NOTONE conditions,
on-chip Tx and Ax audio filtering,
pin-selectable Private/Clear operation, and
pre/deemphasis filters in the Tx path, for optimal recovered audio quality.

The MX375 is fabricated using CMOS technology. It is offered in 28 pin PDIP, CDIP and PLCC packages. It is
also offered in a 24-pin PLCC package. A low-cost 4 MHz crystal/clock and a single 5V supply are required.

What is Pvt SQUELCH?
Pvt SQUELCH™ combines CTCSS with inverted speech to prevent users from understanding each other's
communications unless the transmissions are accompanied by the group's assigned tone. Its net effect is to eliminate
casual eavesdropping and give mobile radio users a certain degree of privacy at a minimal price. Up to 38 PvtSQUELCH
user groups (one per CTCSS tone) can share a single radio channel. With PvtSQUELCH, competing businesses can
share a radio channel without compromising communications security.

APPLICATION NOTES
Pre- and De-emphasis (6dS/octave) filters are included on-chip in the transmit path, so that the use of this device
will produce natural sounding audio (clear or private modes) when installed in modern radio communication transceivers,
with or without existing audio processing circuitry. The recommended layout is shown in block form below.

From Receiver
Stages

Figure 2 - Transmit and Receive Paths

Page 196

MX-COM, INC.

MX375
PIN FUNCTION CHART
~~~~~>~
. ~~
~==
LH

J,P,LH8
28

Note: The MX375LH package is available in serial mode only.
V DO: The positive 5V supply pin.
XTAUCLOCK (lIP): This is the input to the clock oscillator inverter. An external 4 MHz xtal or
clock input should be applied to this pin.

2
3

2

XTAL (OIP): This is the 4 MHz output of the clock oscillator inverter.

4

3

LOAD/LATCH (liP): This input controls the eight input latches: RXiT5<, Private Enable, and DOD5, as detailed in Table 2(a). Alternatively, the RXlTX and Private Enable inputs can be
addressed separately by setting the LoadlLatch and Control inputs as shown in Table 2(b). 1 MQ
pullup.

5-7

D4-D2 (liP) Programming Inputs (Serial Mode Only): These are the RXlTX tone programming
and function inputs which enable the serial programming mode. With LoadlLatch at logic "0" serial
data is loaded in the following sequence: D5, D4, D3, D2, D1, DO, RXlTX, Private Enable. When
these 8 bits have been clocked in on the rising clock edge, data is latched by strobing the Load!
Latch input "0 - 1 - 0" (See Figure 5).
Pin 5 (D4) = Serial Enable 2
Pin 6 (D3) = Serial Data Input
Pin 7 (D2) Serial Clock Input

=

4-9

D5-DO (liP) Parallel Programming Inputs: These are the RXlTX tone programming and function
inputs which select the CTCSS tone (See Table 1).
For both Serial and Parallel Modes: In RX, a NOTONE program enables RX Audio Output and
forces the RX Tone Decode Output to a logic "0". In TX, a NOTON E program generates a constant
V bias -0.7V condition at the TX Tone Output pin. Each input has a 1 MQ pullup resistor.

8

10

RX TONE DECODE (O/P): The gated output of the decode comparator. In RX, a logic "0"
indicates a valid CTCSS tone decode condition, or the presence of NOTONE programming. A
logic "0" enables the RX audio path. In TX, this output is held at logic "1".

9

11

DECODE COMPARATOR (lIP): The voltage level at this pin is compared internally with a fixed
reference level. A greater input level compared to the reference will result in a logic "0" at the RX
Tone Decode output. This input should be externally connected to the RX Tone Detect output via
external integration components C7 , R2 , R3 , and D, (see Figure 3).

10

12

RX TONE DETECT (O/P): In RX, this pin outputs a logical "1" when a valid programmed CTCSS
tone is received at the RX TONE INPUT. This input should be externally connected to the Decode
Comparator input via external integration components C7 , R2 , R3, and D, (see Figure 3).

N/A

13

NOTONE (O/P): This pin outputs a logic "0" when a notone CTCSS code has been programmed
in RX. It is typically used to enable carrier squelch circuits under notone RX conditions.

11

14

V ss: The negative supply pin (ground).

12

15

TX TONE OUTPUT: The buffered CTCSS sinewave tone output appears on this pin. In TX mode,
the tone frequency is selected by program code (see Table 1); if NOTONE is programmed, the
output is at V bias -0.7V. In RX mode, the output goes open circuit. This is an emitlerfollower output
with an internal 10 kQ load.

13

16

BIAS: This pin is set internally to V oi2. It must be externally decoupled using a capacitor (C a)
to Vss' See Figure 3.

14

17

FILTER OUTPUT: This is the output of the Input Audio Bandpass Filter. It must be A.C. coupled
to the Balanced Modulator Input via capacitor Ca' See Figure 3.

15

18

BALANCED MODULATOR INPUT: This is the input to the balanced modulator. Must be A.C.
coupled to the Filter Output via capacitor Ca' See Figure 3.

MX-COM, INC.

Page 197

I

MX375
PIN FUNCTION CHART

I

16

19

RX AUDIO OUTPUT: Outputs the received audio from a buffered output stage and is held at Vbias
when in TX.

17

20

TX AUDIO OUTPUT: Outputs the transmitted audio in TX. In RX, this pin is held at Vbias '

18

21

RX AUDIO INPUT (lIP): The audio input for the RX mode. Input signals should be AC coupled
via external capacitor C4. See Figure 3.

19

22

TX AUDIO INPUT (lIP): This is the TX Audio voice input. Signals should be AC coupled via
external capacitor C3 . See Figure 3.

20

23

PTL (lIP): The "press to listen" function input. In RX mode, a logic "0" enables the RX Audio
Output directly, overriding tone squelch but not intercepting a private conversation; in TX mode,
a logic "0" reverses the phase of the TX Tone Output for "squelch tail" reduction (see Table 2).

21

24

CONTROL: This input, together with LoadlLatch, selects the operational mode of the RXlTX and
Private Enable functions. See Table 2(b).

22

25

RXlTX (lIP): This input selects the RX or TX mode (RX = 1, TX = 0). This can be loaded in Serial

or Parallel modes as described in Table 2.

=

23

26

PRIVATE ENABLE: This input selects either Private or Clear mode (Clear 1, Private = 0), and
can be loaded by Serial or Parallel modes as described in Table 2. This input has an internal 1
MO pullup resistor.

24

27

RX TONE INPUT: This is the received audio input to the on-Chip CTCSS tone decoder. It should
be A.C. coupled via capacitor Co'

C1

r-----------------------------------~----+5V

MX375J/P/LH8

C2

LOAD/lATCH

t=-_--PRIVACy ENABLE

D5r---~'-~~D5

r _ - - P U S H TO TALK

D4
D3

D4
D3

I-'="-_--PUSH TO LISTEN

D2
D1

D2
D1

DO

r=-_--MODE SELECTION
pL-TX AUDIO IN
t-C2--RX AUDIO IN

~ TX AUDIO OUT

DO
DE~CSS~~ R""'X~DE~C""O""D=E

~RX AUDIO OUT

11 COMP IN
~ 01
R312
'-I/IR2I"-4'---=-f DETECT
NOTONE _----'-'13'-1 NOTONE
C10

14 Vss

COMPONENT VALUES
R1=1MO
R2 = 560kO
R3 = 820kO
X1 4MHz

=

Tolerances: Resistors: ±10%

C1 = 11lF
C2 33pF
C3 = 33pF
C4 = 0.11lF

=

Capacitors: ±20%

Figure 3 - External Component Connections
Page 198

C5
C6
C7
C8
C9

=
=
=
=
=

0.1~F
0.1~F

1.01lF
O.1IlF
0.1~F

C10=0.1IlF
C11 = 0.11lF
C12=O.1IlF
C13 = 0.0011lF
D1 small signal

=

XTAL: At cut, fundamental, parallel resonant
20pF load capacitance, 0.05% tolerance

MX-COM, INC.

MX375

Nominal
Frequency(Hz)

Frequency(Hz)

67.0
71.9
74.4
77.0
79.7
82.5
85.4
88.5
91.5
94.8
97.4
100.0
103.5
107.2
110.9
114.8
118.8
123.0
127.3
131.8
136.5
141.3
146.2
151.4
156.7
162.2
167.9
173.8
179.9
186.2
192.8
203.5
210.7
218.1
225.7
233.6
241.8
250.3

67.05
71.9
74.35
76.96
79.77
82.59
85.38
88.61
91.58
94.76
97.29
99.96
103.43
107.15
110.77
114.64
118.8
122.8
127.08
131.67
136.61
141.32
146.37
151.09
156.88
162.31
168.14
173.48
180.15
186.29
192.86
203.65
210.17
218.58
226.12
234.19
241.08
250.28

Notone
Table 1 - CTCSS

+0.07
0
-0.07
-0.5
+0.09
+0.1
-0.2
+0.13
+0.09
-0.04
-0.11
-0.04
-0.07
-0.05
-0.12
-0.14
0
-0.17
-0.17
-0.10
+0.08
+0.02
+0.12
-0.2
+0.11
+0.07
+0.14
-0.19
+0.14
+0.05
+0.03
+0.07
-0.25
+0.22
+0.18
+0.25
-0.30
-0.01

D5

D4

D3

D2

D1

DO

1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1

1
1
1
0
1
1
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0

1
1
1
1
0
1
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0

1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0

I

Chart

Load Configuration
Parallel
Parallel
Parallel
Serial (data loading)
Serial (data loaded)

Load/Latch

Load Configuration
Parallel
Parallel
Parallel
Serial
Serial

Load/Latch

Notes:

Program Inputs

h,. fo (%)

1
1-0
0
0
0-1 - 0

Result
Transparent, the data acts directly
Latches present data in
No further changes except to allow serial mode selection
No change while serial data train is loaded
Loaded serial data is latched

0
1
X
0-1 - 0
X

RXfTX, Private Enable
Latched
Transparent
Transparent
Serial Load
Transparent

"0 - 1 - 0" is a strobe pulse as shown in Figures 4 and 5 (Timing).
"X" denotes any logical state.

Table 2 - Load/Latch and Control Functions

MX-COM, INC.

Page 199

MX375
TIMING INFORMATION
Control instructions are input by serial (Figure 4) or parallel (Figure 5) means, using Data Inputs and
Load/Latch as shown.

I

D4
I
SERIAL MOD~---------------ENABLE
D5
I
__ tSMS_1

--./'.i

...--1

I

I tPWH I

I

~

:1
:
:-tos_1

I

:tDH

I

-"i

I

:
~/

I

~~~LDMA~

~~_ _ _ _~~ ~~_ __

I

I

I

I

I

--ILL - I
I

LOAD/LATCH

------------------Im,.

Min.

I

~
Max.

Unit

250
250
250
150
50
250
150

Serial Mode Enable Set Up Time (tSMS )
Clock "High" Pulse Width (t pWH )
Clock "Low" Pulse Width (tpWL)
Data Set Up Time (tos)
Data Hold Time (tOH )
Load/Latch Set Up Time (t LL)
Load/Latch Pulse Width (tLLW)

I

ns
ns
ns
ns
ns
ns
ns

Figure 4 - Serial Load Timing

DATA INPLJTS

DO -..Q5

RXfTX

PRIVATE ENABLE

LOAD/LATCH

__-J~~:__________~~,----___-J/A':
:
I
I
I
I

I
I
I
I

~Jt.:
~:+
I
I~I-------

t

I

t

t

LOAD DATA

DATA LATCHED

Min.
Data Valid Time (lyp)
Load Time (t L)
Fall Time (t F)
Data Hold Time (t H)

200
150
50
50

ns
ns
ns
ns

Figure 5 - Parallel Load Timing

Page 200

MX-COM, INC.

MX375
SPECIFICATIONS
Absolute Maximum Ratings

Operating Limits

Exceeding the maximum rating can result in
device damage. Operation of the device outside the
operating limits is not suggested.
Supply Voltage
Input Voltage at any pin
Sink/Source Current
(Supply pins)
(Other pins)
Total Device Dissipation
@ TAMB 25°C

Derating
Operating Temperature
Storage Temperature

All devices were measured under the following
conditions unless otherwise noted:
TAMB = 25°C

-0.3 to 7.0 V
-0.3V to (V DD + 0.3 V)

XtallClock fa = 4.0 MHz

±30 rnA
±20 rnA

VDD = 5.0V
Audio level OdB ref = 300 mVrms.

800 mW max.
10 mW/oC

Composite input signal = OdB, 1 kHz tone in,
-12dB (6kHz band limited) gaussian white noise
with a -20dB CTCSS tone.

-40°C to +85°C
-55°C to +125°C

Static Values
Supply Voltage
Supply Current
TX (Private)
TX (Operating)
RX (Operating)
Analog Input Impedance
Analog Output Impedance
Tone Input Impedance
Input Logic "1"
Input Logic "0"
Output Logic "1" (1=-0.1 rnA)
Output Logic "0" (1=-0.1 rnA)
Dynamic Values
Decoder
Input Signal Level
Response Time
Deresponse Time
Selectivity
Encoder
Tone Output Level (775mV rms ref)
Tone Frequency Accuracy
Tone Harmonic Distortion
Tone Output Load Current
Output Level Variation between Tones
Risetime (to 90% nominal level)
(fo>100 Hz)
(V100 Hz)
RX Clear
Total Harmonic Distortion
Output Noise Level
Passband Gain (300-3033Hz)
Passband Ripple (300-3033Hz)

MX-COM, INC.

4.5

5.0

5.5

V

15.0
12.0
7.0

1.0

rnA
rnA
rnA
MO
kO
MO
V
V
V
V

250
250
±3.0

dB
ms
ms
%f0

+3.0
+0.3
5.0
5.0
1.0

dB
%fo
%
rnA
dB

0.5
0.5
0.5
3.5
1.5
4.0

1,4
1,4,6
1,4,6
4

-20

±0.5
-3.0
-0.3

0
2.0

2
9

-1.0

5
5

15
45

3

2
-43
0

7

3
3

-1

ms
ms

5
+1
3

%
dB
dB
dB

Page 201

I

MX375

Audio Stopband Attenuation
(fin >3333Hz)
(fin >3633Hz)
(fin<250Hz)

RX Invert
Total Harmonic Distortion
Baseband Breakthrough
Carrier Breakthrough
Output Noise Level
Passband Ripple (300-30ooHz)
Audio Stopband Attenuation
(fin >3333Hz)
(fln>3633Hz)
(fin <250Hz)
TX Clear
Total Harmonic Distortion
Output Noise Level
Passband Gain (300-3033Hz)
Passband Ripple (300-3033Hz)
Audio Stopband Attenuation
(fin>3333Hz)
(fin>3633Hz)
(fin <250Hz)
TX Invert
Total Harmonic Distortion
Baseband Breakthrough
Carrier Breakthrough
Output Noise Level
Passband Ripple (300-3033Hz)
Audio Stopband Attenuation
(fln>3333Hz)
(fin >3633Hz)
(fin<250Hz)

8
8

-20
-45
-42

3,8
3

4
-40
-40
-37

7,8
3

-50
-60
-60

3
7
3
3

3
-43
0

8
8

-20
-45
-42

3,8

4
-40
-40
-37

8
8
8

10

%
dB
dB
dB
dB

4

8
8

7,8
3,8

dB
dB
dB

dB
dB
dB

%
dB
dB
dB

5

3

dB
dB
dB

10

0/0

4

dB
dB
dB
dB

-50
-60
-60

dB
dB
dB

NOTES:
1. These values are obtained using the external integrating components given in Figure 3.
2. An emitter follower output
3. With an input signal of 1 kHz @ OdB.
4. Under Composite Signal test conditions.
5. Any programmed tone with RL=600 n, C L=15pF, including any response to a phase
reversal instruction.
6. fo > 100 Hz, (for 100Hz> fo > 67Hz: t = [100/fo(Hz)] x 250ms).
7. Input ac short-circuit, audio path enabled.
8. Due to frequency inversion, these figures reflect the difference from the ideal response.
9. Reference 156.7 Hz (MX175 and MX275).

Page 202

MX-COM, INC.

~
~
~
C"l

00-05
TONE
TONE
NOTONE
TONE
TONE
TONE
NOTONE
TONE
TONE
NOTONE
TONE
TONE
TONE
NOTONE

NOTONE

RX/TX

PRIVATE
ENABLE

PTL

1
1
0
1
1
1
0
1
1
0
1
1
1
0

0
0
0
1
1
1
1
0
0
0
1
1
1
1

0
0
0
0
0
0
0
1
1
1
1
1
1
1

1
0
X
1
0
X
X
1
0
X
1
0
X
X

RXTONE RXTONE
DETECT DECODER
0
0
0
0
0
1
X
0
0
0
0
0
1
X

1
1
1
1
1
0
0
1
1
1
1
1
0
0

TONE
OUTPUT

TONE
PHASE

TX
PATH

AX
PATH

PATH
STATE

TONE

YES
YES
BIAS
BIAS
BIAS
BIAS
BIAS
YES
YES
BIAS
BIAS
BIAS
BIAS
BIAS

00
1800
X
X
X
X
X
CO
1800
X
X
X
X
X

OPEN
OPEN
OPEN
BIAS
BIAS
BIAS
BIAS
OPEN
OPEN
OPEN
BIAS
BIAS
BIAS
BIAS

BIAS
BIAS
BIAS
BIAS
OPEN
OPEN
OPEN
BIAS
BIAS
BIAS
BIAS
OPEN
OPEN
OPEN

INV
INV
CLR
X
CLR
INV
CLR
CLR
CLR
CLR
X
CLR
CLR
CLR

TX, TONE
TX, TONE REV
TX, NOTONE
INCOMPATIBLE
INCOMPATIBLE
COMPATIBLE
AX, NOTONE
TX, TONE
TX, TONE REV
TX, NOTONE
INCOMPATIBLE
INCOMPATIBLE
COMPATIBLE
AX, NOTONE

ALGEBRAIC FUNCTIONS:
AX PATH ON = AX • (PTL + RX TONE DECODER)
CLEAR PATH = NOTONE + PRIVATE ENABLE + (PTL • AX • RX TONE DECODER)
NOTONE (00-05) = 000011
CARRIER FREQUENCY = 3333Hz DURING INVERTED PATH (TX OR AX)
NOTES:
1. The Pre- and De-emphasis circuits remain in the transmit path in both Clear and Invert Modes.
2. Power remains applied to the CTCSS tone decoder at all times.
3. During Clear operation the carrier frequency is turned off to reduce spurious emissions.

Table 4 - Functions and Outputs
~
~

2

s::

-

~

~

MX • ~M, INK:!..

MX805A

Advance Information

SUB-AUDIO SIGNALING PROCESSOR
DESCRIPTION
The MX805A, a member of the DBS800 IC family, is a sub-audio frequency signaling
processor that provides outband audio and digital signaling capability for LMR systems.
The MX805A is designed for the transmission and non-predictive reception of
1) Continuous Tone Controlled Sub-audible Squelch (CTCSS) tones and other nonstandard frequencies, and 2) Non-Return-to-Zero (NRZ) data reception and transmission to provide Digitally Coded Squelch (DCS/DPL1M) and LTR1M signaling.
The MX805A contains the following:
-A non-predictive CTCSS Tone Decoder and DCS sub-audio signal demodulator.
-A CTCSS/NRZ Encoder with TX level adjustment and lowpass filter output stage with
optional NRZ pre-emphasis.
-A selectable sub-audio bandstop filter.
-A Notone (CTCSS RX) period timer.

MX805AJ
24-pin CDIP

Setting of the MX805A functions and modes is by data loaded from the microcontroller
to the controlling registers within the device. Reply Data and Interrupt protocol keep the
microcontroller up to date on the operational status of the circuitry.
CTCSS tone data for transmission is generated in the microcontroller, loaded to the
CTCSS TX Frequency Register, encoded and output as a tone via the TX Sub-Audio
MX805ALH
LPF.
24-pin PLCC
Received non-predicted CTCSS tone frequencies are measured and the resulting
data, in the form of a 2-byte data word, is presented to the microcontroller for matching against a look-up table. Noise
filtering is provided to improve the signal quality prior to measurement.
NRZ coded data streams for transmission, when generated within a microcontroller, are loaded to the NRZ TX Data

AX SUB-AUDIO

I

AX LPF

I~.~

AX SUB·AUDIO
OUT

COMPARATOR

t

I -_ _--!.:N~OTONE

180HZ/260Hz

AMP OUT

COMMAND DATA

AM~
~

REPLY DATA

CHip SELECT
SERIAL CLOCK

I+-_ _ _---!WAKE
ADDRESS SELECT

1)(

SUB·AUDIO
OUT

vss_ _
AUDIO OUT

AUDIO IN
AUDIO SIGNAL PATH

MXB05A Sub-Audio Signaling Processor
DPL is a trademark of Motorola, Inc. LTR is a trademark of EF. Johnson Co.

Page 204

MX-COM, INC.

MX805A
DESCRIPTION ...
Buffer and output, in 8-bit bytes, through the lowpass filter circuitry as sub-audible signals. DCS turn-off tones can be
added to the data signals by switching the MX805A to the CTCSS transmit mode at the appropriate time. NRZ coding
is produced by the microcontroller and translated to sub-audio signals by the MX805A.
Received NRZ data is filtered, detected, and placed into the NRZ RX Data Register, which is then available for
transfer (one byte at a time) to the microcontroller for decoding by software. Clock extraction circuitry is provided onchip. TX and RX baud rates are selectable.
Hardware and software are designed to allow consecutive addressing of two MX805A Sub-Audio Signaling
Processors to achieve multi-mode duplex operation. Powersaving may be controlled by software or an input dedicated
to the purpose.
The MX805A is a low-power 5 volt CMOS IC available in 24-pin Cerdip and 24-lead plastic SMT packages. It is
pin-compatible with the earlier MX805.

PIN FUNCTION CHART

Xtal: The output from the on-chip clock oscillator inverter. External components are required atthis input
when a Xtal input is used. See Figure 2.

2

3

4

XtaVClock: The input to the clock oscillator inverter. A Xtal or externally derived clock should be
connected here.,

Addre$$.(~'Thisjt.ptJt~l:lableS two MX805As to be used on the same C-BUS to provide full-duplex
oper~;;~'(abl~~~;a:fin~~

,>

ReqtHlst(lBij):}~'~U~bf th~;ijjn

Interrupt
indicates an interrupt condition to the microcontroller
,the connection of up to 8 peripherals to 1 interrupt
by going to a logic "0;" Th:is~te-or~ .',.~t all
port on the microcontroller. This Pi.
. , ce pulldown to logic "0" when active, and a high
.' 'ges 1 pullup resistor to VDO. The conditions that
impedance when inactive. The s
cause interrupts are indicated in the Stat
r(Tabl~..4)anda(e. shown below:

""

~~,\<>'

-<,'.'~;,'

RX CTCSS Tone Measurement Completed .'
CTCSS NOTONE Timer Expired
1 NRZ RX Data Byte Received
New NRZ Data Received Before Last Byte Read
NRZ TX Buffer Ready
NRZ Data Transmission Complete
5

Serial Clock: This is the "C-BUS" serial clock input. This clock, produced by the microcontroller, is used
for transfer timing of commands and data to and from the MX805A. See timing diagrams.

6

Command Data: This is the C-BUS serial data input from the microcontroller. Data is loaded to this
device in 8-bit bytes, MSB (bit 7) first and LSB (bit 0) last, synchronized to the Serial Clock. See timing
diagrams.

7

Chip Select (CS): This is the "C-BUS" data loading control function. This input is e!:2vided by the
microcontroller. Data transfer sequences are initiated, completed or aborted by the CS signal. See
timing diagrams.

8

Reply Data: This is the C-BUS serial data output to the microcontroller. The transmission of Reply Data
bytes is synchronized to the Serial Clock under the control of the Chip Select input. This 3-state output
is held at high impedance when not sending data to the microcontroller. See timing diagrams.

9

TX Sub-Audio Out: This is the sub-audio output (pure or NRZ derived). Signals are band limited. The
TX Output Filter has a variable bandwidth (see Table 6). This output is at VB1AS (a) when the NRZ
Encoder is enabled but no data is being transmitted, (b) when the MX805A is placed in the Powersave
All condition.

MX-COM, INC.

Page 205

I

MX805A
PIN FUNCTION CHART
10

Audio In: This is the input to the switched sub-audio bandstop (highpass) filter. It is internally biased,
and should be a.c. coupled by capacitor C7 •

11

Audio Out: This is the output of the audio signal path (filter or bypass). It is controlled by the Control
Register. When disabled, the pin is held at VSIAS'

12

Vss: Negative supply (GND).

13

This is the inverting input to the on-chip RX Input Amp (see Figures 2, 3 and 4).
the non-inverting input to the on-chip RX Input Amp.

14
15

on-chip RX Input Op-Amp. This circuit may be used, with external
8:nti-aliasing filter prior to the RX Lowpass Filter. or for other

16

RX Sub-Audio In: This is the
VSIAS' The signal to this pin

17

RX Sub-Audio Out: This is the output
amplifier or comparator as required.

18

VSIAS: The internal circuitry bias line, held at "Vor/2. This

input. It is internally referenced to
Figure 2.

(see Figure 2).
19

Comparator In (-): This is the inverting input to the on-chip "comparator"
and 4.

20

Comparator In (+): This is the non-inverting input to the on-chip "comparator" amplifier. See Figures
2,3 and 4.

21

Comparator Out: This is the output of the "comparator" amplifier. This node is also connected internally
to the input of the Digital Noise Filter (See Figure 1). When both decoders (CTCSS or NRZ) are
powersaved, this output is at logic "0."

22

Notone Timing: External RC components connected to this pin form the timing mechanism of a Notone
period timer. The external network determines the "charge rate" of the timer to VBIAS' The expiration
of the timer will cause an interrupt. This function is only used in the CTCSS RX mode. See page 9.

23

Wake: This "real time" input can be used to reactivate the MX805A from the "Powersave All" condition
using an externally derived signal. The MX805A will be in a "Powersave All" condition when both this
pin and bit 0 of the Control Register are set to a logic "1." Recovery from "Powersave All" is achieved
by putting either the Wake pin or the "Powersave All" bit at logic "0." This allows MX805A activation by
the microcontroller or an external Signal, such as RSSI or Carrier Detect.

24

Voo: Positive supply. A single +5 volt regulated supply is required.

NOTES:
More information on external components and the DBS 800 system integration of the MX805A are contained in the DBS 800
System Support Document. Guidance on the generation and manipulation of NRZ and RX and TX data is given in the DBS
800 Application support document.

C-BUS is MX-COM's proprietary standard for the transmission of commands and data between a microcontrolier and DBS
800 microcircuits. It may be used with any microcontrolier, and can, if desired, take advantage of the hardware and serial
1/0 functions embodied into many types of microcontroliers. The C-BUS data rate is determined by the microcontrolier.

Page 206

MX-COM, INC.

MX805A
Application Information

.

R7.

SEE INSET

Xi'A[

XTAUCLOCK
ADDRESS SELECT

- ..........

1R()
SERIAL CLOCK
COMMAND DATA

~~

'v

1)( SUB-AUDIO OUT

I C7

23
22
21
20

2
3
4
5
6

rn. 7
REPLY DATA

24~

1

MX805AJ

8
9

AUDIO IN 10
AUDIO OUT 11

t12

4:C5

R6~

WAKE

C6

NOTONE

+

COMPARATOR OUT

R4

COMPARATOR IN (+)

19 COMPARATOR IN~
18 Y.ai&
17 AX SUB-AUDIO OUT C3
AX SUB-AUDIO IN

?

~

i"

l-

16
15 AX AMP OUT
AX AMP IN (+)
14
AX AMP IN (-I..
13

T

1

R2

~

~1fo2

J

J

I

I.J.

AS

INSET

~~r,-MX805AJ

Component
R1
R2
R3
R4
R5
R6
R7
R8

Figure 2 - Recommended External Components
Notes
1.
Xtal/Clock circuitry components shown in INSET are
recommended in accordance with MX-COM's "Standard and
DBS 800 Crystal Oscillators" application note.

2. Resistor R8 is a System Component. Its value is chosen
together with the MX806A Modulation Summing Amplifier to
provide a sub-audio signal level of -11.0dB to the system
modulator.
3. Figures 3 and 4 illustrate alternative input component
configurations.
4. The value of R5 is dependent on the input signal level.
Values given are forthe specified composite signal 0140 mVrms.
R4 adds hysteresis to the comparator and is not always
required.

MX805A
AX LPF

Value
1.0MQ
360kn
10.0kn
150kn
100kn
150kQ
22.0kQ
360kQ

Tolerance: R = ±5%

C1
C2
C3
C4
C5
C6
C7
C8
D1
D2
X1

See Note 5
See Note 5
1.51lF
15.0IlF, 6VTanl. ±20%
1.01lF, 10VTanl. ±20%
1.0IlF, 10VTanl. ±20%
O.1IlF, 25V x 7R ±20%
1.01lF
silicon small signal
silicon small signal
4.00MHz

5. The values used for C, and C2 are determined by the
frequency of X,.
As a guide:
C, = C2 = 33pF for X, < 5.0MHz.
C, = C2 = 18pF for X, > 5.0MHz.
If the on-chip Xtal oscillator is to be used, then the external
components X" C" C2 , and R, are required as shown in Figure
2 (inset). If an external clock source is used these components
are not requ!@Q; the input should be connected to the Xtal/clock
pin and the Xtal pin left unconnected.
6. Resistor R7 is used as the DBS 800 system common pullup
for the C-BUS Interrupt Request (IRQ) line. The optimum value
of this component will depend upon the circuitry connected to
the IRQ line.
7. The level at this point should be approximately 900mV peak
to peak.

MX805A
AX AMP

MX805A
COMPARATOR

%

HYSTERESIS (OPTIONAL)

~

D1

TC3
AX SUB-AUDIO
INPUT
R5

Figure 3 - MXB05A Input Components
MX-COM, INC.

Page 207

MX805A
Application Information
Figure 3 shows an input configuration that is generally for use for CTCSS signal and NRZ data reception.
Input coupling capacitor C3 is required because the
RX Sub-Audio Input is held at V BIAS during all powered
conditions of the MX805A. Diodes 0 1 and O2 can be any
silicon small-signal diode.

The output resistance (open loop) of the on-chip RX
Amp is ",6kU. In the configuration shown in Figure 3, the
(RX Amp) RC time constant is therefore 90ms. If this
period is too long for some systems, ie. those using halfduplex, short data burst, an external amplifier should be
considered in place of the on-chip RX Amp.

MX805A
COMPARATOR

I

100k

D.C. RESTORATION
LEVEl. SHIFT" AND AMPLIFY

Figure 4 - MXB05 Input Components using an External Op-Amp

Using An External Op-Amp
For d.c. coupling the MX805A to the receiver's
discriminator output when using burst mode NRZ communication, it is recommended that an additional, external
Op-Amp is employed as configured in Figure 4. This
configuration will quickly compensate for sudden shifts of
DC input bias.

Operating Modes
NRZ Encoding
The NRZ Encoder is formed by a shift register and the
TX Sub-Audio Lowpass Filter. Data loaded from the
Command Data line is output one 8-bit byte at a time from
the NRZ TX Data Register. The output data level may be
adjusted and filtered. Data may be pre-emphasized via a
C-BUS command. The expected RX baud rate is programmed as the NRZ TX Baud Rate (R NRZTX)' See Table

5.
CTCSS Encoding
The CTCSS Tone Encoder is comprised of a clockdivider programmed by an 11-bit binary number (a) loaded
to the CTCSS TX Frequency Register (see Table 5) via the
C-BUS Command Data line.
The square-wave output of the encoder is fed through
the TX Level Adjust variable gain block to the TX SubAudio lowpass filter, a variable bandwidth circuit controlled
by 4 bits (P) of the CTCSS TX Frequency Register. The
TX Sub-Audio output is a sine-wave. Standard and nonstandard sub-audio tones are available. A CDCS turn-off
tone may also be generated.
Page20B

Components Re, RlO' and Rll should be calculated to
provide an accurate potential of 2.5 Vd.c. (equal to V BIAS )
at pin junction 15/16 when using a discriminator input and
900 mV peak to peak at the output of the external op-amp.
Note that the MX805A LPF has a 6 dB gain. If additional
filtering is required, Ce should be used; it should be
calculated with Re to provide a lowpass cut-off frequency
(feo) of 500 Hz.

NRZ Decoding
Input (NRZ type) sub-audio signals are filtered and the
data clock extracted. Decoded data is serially loaded into
a shift register buffer. This data is output one 8-bit byte at
a time as Reply Data from the NRZ RX Data Register to the
microcontroller. The expected RX baud rate is programmed
as the NRZ RX Baud Rate (RNRZ RX)' See Table 5. Any
codeword recognition can be carried out by software.
CTCSS Decoding
Received CTCSS signals are filtered, and coherence is
increased by the digital noise filter. The quality of the signal
is assessed by measurement of the cycle-to-cycle period
variance and, provided it is sufficiently good, the frequency
is measured over a period of 122.64 milliseconds (4.0 MHz
xtal).
If the average signal quality is consistently too low,
Notone is indicated; if not, the input frequency is precisely
indicated in the CTCSS RX Frequency Register in a binary
form.
Any single sub-audio tone within the specified range
may be selected, enabling a DCS turn-off tone (of 134 Hz)
to be decoded while in the NRZ RX mode.
MX-COM, INC.

MX805A

Controlling Protocol
Control of the MX805A Sub-Audio Signaling Processor's operation is by communication between the microcontroller
and the MX805A internal registers on the C-BUS, using Address/Commands (NCs) and appended instructions or data
(see Figure 9). The use and content of these instructions is detailed in the following paragraphs and tables. The Address
Select Input enables the addressing of 2 separate MX805As on the C-BUS to provide full-duplex signaling.

MX805A Internal Registers
MX805A Internal Registers are detailed as follows:
Control Register (70/78H) -- Write only, control and
configuration of the MX805.
Status Register (71i79H) -- Read only, reporting of
device functions.
CTCSS RX Frequency Register (72i7AH) -- Read only,
a 2-byte binary word indicating the frequency of the
received sub-audio input.

CTCSS TX Frequency/NRZ TX or RX Baud Rate Register (73i7BH) -- Write only, a 2-byte command to set
the relevant parameters.
NRZ RX Data Register (74j7CH) -- Read only, a single
byte of received NRZ data.
NRX TX Data Register (75i7DH) -- Write only, to load a
single byte of NRZ data for transmission.
Gain Set Register (76/7EH) -- Write only, a single byte to
set the gain of the TX Lowpass Filter.

Address/Commands
The first byte of a loaded data sequence is always
recognized by the C-BUS as an Address/Command (NC)
byte. Instruction and data transactions to and from this
device consist of an Address/Command byte followed by
either:
or

(i) further instructions or data
(ii) a Status or data Reply.

General Reset
Write to Control Register
Read Status Register
Read CTCSS RX Freq. Reg.
Write to CTCSS TX Freq./
NRZ Baud Rate Reg.
Read NRZ RX Data Reg.
Write to NRZ TX Data Reg.
Write to Gain Set Reg.

01
70
71
72
73

o0
o1
o1
o1
o1

74
75
76

0 1
0 1
0 1

0
1
1
1
1

Instructions and data are loaded and transferred, via CBUS, in accordance with the timing information in Figures
9 and 10.
Placing the Address Select input at a logic "0" will address
MX805A #1, a logic "1" will address MX805 #2.
Tables 1 and 2 show the list of NC bytes relevant to the
MX805A.

0 0 0
1 0 0
100
100
100

0
0
0
1
1

1
0
1
0
1

+
+
+
+

0 1 0 0
0 1 0 1
0 1 1 0

+
+
+

1 byte instruction to Control Register
1 byte reply from Status Register
2 byte reply of CTCSS RX Data
2 byte instruction for TX Frequency and
NRZ Tx/RX baud rates
1 byte binary data Reply
1 byte binary data Command
1 byte instruction for TX Output

Table 1 - MXB05A #1 C-8US Address/Commands -

General Reset
Write to Control Register
Read Status Register
Read CTCSS RX Freq. Reg.
Write to CTCSS TX Freq./
NRZ Baud Rate Reg.
Read NRZ RX Data Reg.
Write to NRZ TX Data Reg.
Write to Gain Set Reg.

o0
o1
o1
o1

01
78
79
7A
7B

0 0 000 1
1 1 1 000
1 1 100 1
1 1 101 0
01111011

7C
7D
7E

0
0
0

o0
o1
1 0

+
+
+
+
+
+
+

1 byte instruction to Control Register
1 byte reply from Status Register
2 byte reply of CTCSS RX Data
2 byte instruction for TX Frequency and
NRZ Tx/RX baud rates
1 byte binary data Reply
1 byte binary data Command
1 byte instruction for TX Output

Table 2 - MXB05A #2 C-8US Address/Commands MX-COM, INC.

Page 209

MX80SA

Controlling Protocol ...
"Write to Control Register" -- AlC 70 H (78H), followed by 1 byte of Command Data
Table 3 below shows the configurations available to the MX805A. Bits 5, 6 and 7 are used together to Enable and
Powersave circuit sections as required.

CTCSS Decoder
NRZ Decoder
CTCSS Encoder
NRZ Encoder
CTCSS Encoder and Decoder
NRZ Encoder and CTCSS Decoder
NRZ Decoder and CTCSS Decoder
NRZ Decoder

NRZ Decoder and Both Encoders
CTCSS Decoder and Both Encoders
All Decoders
All Decoders
NRZ Encoder and Decoder
No circuits
All Encoders
All Encoders except TX Sub-Audio LPF
and CTCSS Decoder

Enable Audio Output -- Used with Bit 3
Disable Audio Output -- Output to V BIAS
Enable Sub-Audio Bandstop Filter (Audio Signal Path)
Bypass Sub-Audio Bandstop Filter
Enable All MX805A Interrupts
Disable All MX805A Interrupts
Set AX Lowpass Filter Bandwidth to 180Hz -- For low CTCSS tones or NRZ data
Set RX Lowpass Filter Bandwidth to 260Hz
All Encoders and Decoders Powersaved
All Encoders and Decoders Enabled unless individually Powersaved

General Reset
Upon power-up the bits in the MX805A registers will be
random (either "0" or "1"). A General Reset Command 01 H)
will be required to reset all ICs on the C-BUS. It has the
following effect on the MX805A:
Control Register
Status Register
Notone Timer

Glossary of Abbreviations
Below is a list of abbreviations used in this Data Bulletin.
DCS

Continuous Digitally Coded Squelch

CTCSS

Continuous Tone Controlled Sub-Audible
Squelch

Set as OOH
Set as DOH
Discharged

Digital Private Line
Logic Trunked Radio

Warning: The following MX805A register configurations
are not affected by a General Reset Command:
CTCSS RX Frequency
CTCSS TX FrequencylNRZ Baud Rate Register
NRZ RX Data Register
NRZ TX Data Register
Gain Set Register
Note that setting the Control Register in this way will set the
MX805A to the CTCSS decode mode and overwrite a
"Powersave All" instruction. It should also be considered
that a General Reset command will reset ALL DBS 800 ICs
operating on the C-BUS.

Page 210

Non-Return-to Zero
fCO

Riter Cut-off frequency

fCTCSS IN

Sub-Audio RX frequency

fCTCSSOUT

Sub-Audio TX frequency

fTONE

Tone frequency

fXTAL

Xtal/Clock frequency

RNRZRX

NRZ RX baud rate

R NRZTX

NRZ TX baud rate

SINPUT

Audio input signal

MX-COM, INC.

MX805A

Controlling Protocol ...
"Read Status Register" -- AlC 71 H (79H), followed by 1 byte of Reply Data
The Status Register indicates the operational condition of the MX805A. Bits 0 to 5 are set individually to indicate specific
actions within the device. When a Status bit is set to a logic"1 ," an Interrupt Request (IRQ) output is generated. A read
of the Status Register will reset the Interrupt and ascertain the state of this register. Table 4 shows the conditions
indicated by the Status bits.

Received First
Not used

Not used

NRZ data transmission
complete. No new data is loaded.

1. Write to NRZ TX Data Reg., or
2. General Reset, or
3. NRZ Encoder Powersave

NRZ TX Data Buffer ready for
next data byte.

1. Write to NRZ TX Data Reg., or
2. General Reset, or
3. NRZ TX Powersave

New NRZ RX data received before
last byte was read.

1. Read NRZ RX Data Reg., or
2. General Reset, or
3. NRZ Decoder Powersave

1 byte of NRZ RX data received.

1. Read NRZ RX Data Reg., or
2. General Reset, or
3. NRZ Decoder Powersave

Notone Timer period expired.

1. Read Status Register, or
2. General Reset, or
3. CTCSS Decoder Powersave

I

RX Tone Measurement Complete

"Read CTCSS RX Frequency Register" -- AlC 72H (7AH) , followed
Measurement of CTCSS RX Frequency (fCTCSS IN)
The input sub-audio signal (fcTCSS IN) is filtered, doubled
and measured in the Frequency Counter over the "measurement period" (122.64ms) (4.0 MHz Xtal).
The measuring function counts the number of complete
input cycles occurring within the measurement period and
then the number of measuring-clock cycles necessary to
make up the period.

by 2 bytes of Reply Data

When the measurement period of a successful decode is
complete, the RX Tone Measurement bit in the Status
Register and the Interrupt bit are set.
The CTCSS RX Frequency Register will now indicate the
sub-audio signal frequency (fCTCSS IN) in the form of 2 data
bytes (1 and 0) as illustrated in Figure 6.

t--------- Measurement Period -----------+1
Complete
Input
Cycle

Complete
Input
Cycle

Complete
Input
Cycle

Complete
Input
Cycle

FILTERED AND DOUBLED SUB-AUDIO INPUT SIGNAL

Complete
Input
Cycle

Measuring
Clock
Cycles

11111

2 x fcrcss IN

Figure 5 - Measurement of a CTCSS RX Frequency
MX-COM, INC.

Page 211

MX80SA

Controlling Protocol ...
"Read CTCSS RX Frequency Register" ...
The Integer (N) -- Byte 1
A binary number representing twice the number of complete input sub-audio cycle periods counted during the
measurement period of 122.64ms (4.0 MHz Xtal).

Byte 1

(Reply Data)
(MSB) • Transmitted Arst

15 1 14
'0'

The Remainder (R) - Byte 0
A binary number representing the remainder part, R, of 2
x the Sub-Audio Input Frequency. R = number of specified
measuring-clock cycles required to complete the specified
measurement period (See N). The clock cycle frequency
is 4166.6Hz (4.0 MHz Xtal).

13 112 111

Byte 0

1 J J
10

9

8

"OU

Integer (N)

"0·

J

7

5

6

"0·

14 l 3 J2

•

J1

I0

Remainder (R)

CTCSS RX Frequency Register
Figure 6 - Format of the CTCSS RX Frequency Register
CTCSS RX Frequency Register
Figure 6 above shows the format of the CTCSS RX
Frequency Register.
Bits 8 (lSB) to 13 (MSB) are used to represent the
Integer (N). From Byte 1, valid values of N = 16.$ N .$ 61.
ie. values of N less than 16 and greater than 61 are not
within the specified frequency band.

Bits 0 (lSB) to 5 (MSB) are used to represent the
Remainder (R). From Byte 0, valid values of R .$ 31.
This register is not affected by the General Reset command (01 H) and may adopt any random configuration at
Power-Up.

CTCSS RX Frequency Measurement Formulas
To assist in the production of "look-up" tables and limit-values in the microcontrolier, and to provide guidance upon the
determination of Nand R from a measured CTCSS frequency, the following formulas show the derivation of the CTCSS
RX Frequency (fCTCSS IN) from the measured data bytes (N and R).
fCTCSS IN
In the measurement period of 122.64ms there are N cycles at 2 x fCTCSS IN and R clock cycles at 4166.6Hz, for
any input frequency.
So,
N X fXTAL

fCTCSS IN

Hz

[1]

R = INTr511- [

L

1920 x (511-R)

N

INT r1920 x 511 x fCTcss ]

t

fXTAL

N x fXTAL

]

+0.5] [3]

E920 x fCTCSS IN

[2]

J

Calculate N first
Examples (fXTAL

= 4.00MHz):

fCTCSS IN

= 100Hz

N

= 24

R

= 11;

fCTCSS IN

= 250Hz

N

= 61

R

=3

Notone Timing
The input sub-audio signal is monitored by the Frequency Assessment circuitry. Before any Notone action is
enabled, the MX805A must have achieved at least one
successful "Tone Measurement Complete" action.
If there is no signal or the signal is of a consistently

Page 212

poor quality, the Notone Timer will start to charge via the
timing components. When the timing period has expired
(at V 00/2), an Interrupt and a Status bit (Notone Timer
Expired) are generated. This is a one-shot function which
is reset by a "Tone Measurement Complete" interrupt.

MX-COM, INC.

MX805A

Controlling Protocol ...
"Write to CTCSS TX FrequencylNRZ Baud Rate Register" -- AlC 73 H (7B H), followed by 2 bytes of Command Data
The information loaded to this register will set either the:
fCTCSSOlIT
(a) CTCSS TX Tone Frequency
(b) NRZ TX Baud Rate
RNRZTX
(c) NRZ RX Baud Rate
RNRZ RX
The chosen mode for this register (a, b or c) is determined by the MX805A modes enabled by the Control Register,
as shown in the table below.

0
0
1
1
0
0
1
1

0
0
0
0
1
1
1
1

CTCSS Decode
NRZ Decode
CTCSS Encode
NRZ Encode
CTCSS Encode and Decode
NRZ Encode & CTCSS Decode
NRZ & CTCSS Decode
NRZ Decode

0
1
0
1
0
1
0
1

Table 5 - CTCSS

I

NRZ RX Baud Rate
CTCSS TX Frequency
NRZ TX Baud Rate
CTCSS TX Frequency
NRZ TX Baud Rate
NRZ RX Baud Rate
NRZ RX Baud Rate

Baud Rate

Data Format
Data is transmitted to this register as 2 bytes of Command Data in the form illustrated in the diagram below. This register
is not affected by the General Reset Command (01 H) and may adopt any random configuration at power-up.
!Command Data)
MSB) - Loaded First

11.15 114

Byte 1

1 13 1 12

P

.1

Byte 0
9

11

"0

11

1.

'0

8

II

7

5

6

1 4

1 3

a

(Command Data)
(LSB) • Loaded Last

1

2

1

1

10

.11

CTCSS TX Frequency/NRZ Baud Rate Register
Figure 7 - Format of the CTCSS TX Frequency/NRZ Baud Rate Register

Command Words P and Q
The two data words, P and a, loaded to this register are interpreted as:
P = a binary number to set the TX Sub-Audio Lowpass Filter bandwidth (applicable to NRZ and CTCSS modes).
= a binary number to set the frequency or baud rate of the selected function.

a

Command Word P

o
o
o
o
o
o

o

0
0

1

0
0

0

MX-COM, INC.

fC/O =

2
3

o

4

1

o

5
6

o

8

7

1

o

Bits 12 to 15 are used to produce the data word uP" as
shown in the table at left. The cut-off frequency fCio (0.5dB
point) of the TX Sub-Audio Lowpass filter is calculated as:
300Hz
200Hz
150Hz
120Hz
100Hz
85.7Hz
75Hz

fXTAL
32 x 208.33 x P

so P =

fXTAL

32 x 208.33 x feo
Table 6 is given as an example and calculated using a
Xtal/Clock (fxTAL) frequency of 4.00MHz. As illustrated,
only values of Up" of 2 to 8 are usable.
Page 213

MX805A

Controlling Protocol .. .
"Write to CTCSS TX Frequency/NRZ Baud Rate Register" .. .
Command Word "Q"
Bits 0 to 10 (see Figure 7) are used to produce the data word "Q" which sets one of the parameters described below.
As you can see, Command Word "Q" could be used to produce a parameter outside that specified in the "Characteristics"
section of this data bulletin. Care should be taken not to do this. Examples for limits of "Q" in each operational
configuration are included. "Q" = 0 is not valid in the following calculations. Bit 11 is not used and must be set to logic

"0."

(a) CTCSS TX Tone Frequency
fCTCSSOUT =

(fCTCSS

Hz

fXTAL
32x"Q"

so "Q"

our)

Example Limits
fcrcss OUT

67Hz

so "Q"

1866

Hz

fXTAL

250Hz

fcrcssouT

32 x fCTCSS OUT

so "Q"

(b) NRZ TX Baud Rate (R NRZTX)
RNRZTX

=

fXTAL

500

67bits/sec.
so "Q"

1866

_300bits/sec.
so"Q"

(c) NRZ RX Baud Rate (R NRZ RX)
fXTAL
32x11x"Q"
so"Q"

417

"00110100001"

Example Limits

=

bits/sec.
so "Q"

100bits/sec.
114

"00001110010"

fXTAL
300bits/sec.

352 x RNRZRX
80"Q"

Page 214

"11101001010"

fXTAL
32 X RNRZTX

RNRZRX

"00111110100"

Example Limits

bits/sec.

32 x "Q"
so "Q"

"11101001010"

38

"00000100110"

MX-COM, INC.

MX805A

Controlling Protocol...
"Read NRZ RX Data Register" -- AlC 74H (7CH), followed by
Received NRZ data bits are organized into bytes and
made available to the microcontroller via the Reply Data
line. As 8 bits are received into this register an interrupt is
generated to indicate that a complete byte has been
received. This byte must be read before the arrival of the
last (8th) bit of the next incoming byte. If this is not done,
an interrupt to indicate this condition will be generated and
the previous RX data is discarded. (See Table 4.)
Word synchronization is not provided. Byte synchro-

"Write to NRZ TX Data Register" -- AlC 75H (7DH),
A byte for transmission is loaded from the C-BUS
Command Data line with this AlC. The first data bit
received via the C-BUS is transmitted first. This transmitter operation is non-inverting.
The first data byte loaded after the NRZ Encoder is
enabled (Control Register) initiates the transmission sequence and an interrupt will be generated when the NRZ
TX Data Buffer is ready for the next data byte. Subse-

"Write to Gain Set Register" -- AlC 76H (7EH),

7

4
0

5
0

6
0

Transmitted Bit 7 First
These 4 bits must be "0"

Pre-Emphasis Setting
1.72dB Gain Enabled
1.72dB Gain Disabled

3
1

0
2
0
0
0
0
1
1

1

0

0

0
1
0
1
0
1
0
1

0
1
1
0
0
1
1

followed by 1 byte of Command Data
quently, interrupts occur for every 8 bits transmitted.
Transmission is terminated, the TX Sub-Audio Output is placed at VBIAS' and an interrupt is generated if the
next byte is not loaded within 7 bit periods (see Table 4).
This register is not affected by the General Reset
Command (01 H)' and may adopt any random configuration
at Power-Up.

followed by 1 byte of Command Data

MSB

0

1 byte of Reply Data
nization and any codeword recognition will be performed
by the host microcontroller. The RX baud rate is set by
writing to the CTCSS TX Frequency/NRZ Baud Rate
Register (73J7BH). The first bit received is the first bit sent
to the microcontroller.
This register is not affected by the General Reset
Command (01 H)' and may adopt any random configuration
at Power-Up.

TX Level Adjust Gain Setting
-2.58dB
-1.72dB
-0.86dB
OdB
+0.86dB
+1.72dB
+2.58dB
Not Used

Table 7 - Gain Set Register Settings

The Gain Set Register Settings
The settings of this register control the CTCSS and
NRZ signal level that is presented at the TX Sub-Audio
Output.
Bit 3, when enabled, is used to produce a preemphasis effect on the NRZ TX Data by increasing the
gain of the data bit before a level change (see Figure 8), by
1.72dB to make that data pulse level slightly more positive
(or negative). The signal level will be 1.72dB greater than
that set by Bits 0 to 2. If the TX Sub-Audio Output level is
set to +2.58dB, the pre-emphasized level will be +4.3dB.
The pre-emphasis function will remain enabled until
disabled by setting Bit 3 to a 10gic"0." If this function
remains enabled when using the CTCSS Encoder, the
output signal may be adversely affected. Therefore this
function should only be enabled when in the NRZ Encode
mode.
This register is not affected by the General Reset
Command (01 H)' and may adopt any random configuration
at Power-Up.

NRZ TX DATA

BIT PERIODS

I

GAIN SET NRZ TX DATA WITH PRE-EMPHASIS ENABLED

Gain Set
+1.72dB

Gain Set
+1.72d8

Gain Set
+ 1.72d8

Gain Set

l..-_ _ _""L----.2+~1.~72~d~8:J

Figure 8 - Gain Set With Pre-Emphasis
MX-COM, INC.

Page 215

I

MX805A
Timing Information
Figure 9 shows the timing parameters for two-way communication between the

CHIP

~C

and the MX805A on the C-BUS.

~~--------------------------+/

~

,---1.-

tCSOFF-+/

SElECT

------------------~.

~

-+/

~

t=

~-----

I

• 71 61 61 41 31211 I 0 . .~~~:
FIRST DATA BYTE

ADDRESSICOMMAND
BYTE

iii

~~tH~

LAST DATA BYTE

REPLY DATA

........-,71,-6.. .-1-,61r-4"1-3 2"""T1-1....0-'.""'0
.... - - - -'-1

MSB

LSB
lAST REPLY DATA BYTE

ARST REPLY DATA BYTE

Logic level Is not Important

1

Figure 9 - C-8US Timing

tCSE
tCSH
tCSOFF

t NXT
tCK
tCH
tCl

tcos
tCOH
tAOS

t AOH
tHIZ

Chip Select Low to First Serial Clock Rising Edge
Last Serial Clock Rising Edge to Chip Select High
Chip Select High
Command Data Inter-Byte Time
Serial Clock Period
Decoder or Encoder Clock High
Decoder or Encoder Clock Low
Command Data Set-Up Time
Command Data Hold Time
Reply Data Set-Up Time
Reply Data Hold Time
Chip Select High to Reply Data High - Z

2.0

4.0
2.0

4.0
2.0
500
500
250

o

250
50.0
2.0

Notes: 1. Command Data is transmitted to the peripheral MSB (bit 7) first, LSB (bit 0) last. Reply Data is read
from the MX805A MSB (bit 7) first, LSB (bit 0) last.
2. Data is clocked into the MX805A and into the microcontroller on the rising Serial Clock edge.
3. Loaded data instructions are acted upon at the end of each individual, loaded byte.
4. To allow for differing microcontroller serial interface formats, the MX805A will work with either polarity Serial
Clock pulses.

..:-t

-+-.
tCDS-+-:

.

SERIAL CLOCK
(from I1C)

CDH

:+:

=>CJC
. .

COMMAND DATA
(from I1C)

t RDS -+-.
REPLY DATA
(to IIC)

:
I+-

.•

-+-. : - t RDH
•

•

•

.

.

=X~JC

Figure 10 - Timing Relationships for C-8US Information Transfer
Page 216

MX-COM, INC.

MX805A

Specifications
Absolute Maximum Ratings

Operating Limits

Exceeding the maximum rating can result in
device damage. Operation of the device outside the
operating limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.
Voo = 5.0V

Supply Voltage
Input Voltage at any pin
(ref. V88 = OV)
Sink/Source Current
(supply pins)
(other pins)
Total device dissipation
@ TAMB 25°C
Derating
Operating Temperature
Storage Temperature

-0.3 to 7.0 V
TAMB = 25°C
-0.3 to (V DO + 0.3V)
XTAUClock frequency
±30mA
±20mA
800mW max.
10mW/oC
-40°C to +85°C
-55°C to +125°C

= 4.0MHz

Audio level OdB ref. = 308mVrms @ 1kHz
Composite Signal = 308mVrms @ 1kHz +75mVrms
Noise + 31 mVrms Sub-Audio Signal
Noise Bandwidth = 5kHz Band Limited Gaussian

Static Values
Supply Voltage
Supply Current

4.5
(All Functions Enabled)
(Decoders only Enabled)
(Po~ersave All)

Analog Impedan
RX Sub-A
Audio I
Audio Bypass
Audio Bypass SvJFt1~hi';}ff.
RX Amp Input (+ and
Comparator Input (+ and -)
RX Sub-Audio Output
TX Sub-Audio Output (Encoder Enabled)
(Encoder Disabled)
Audio Output
(Enabled)
(Disabled)
RX Amp and Comparator Outputs
(Large Signal)
(Small Signal)

5.0
5.0
1.9
0.9

5.5
7.0
2.5
1.5

350
350
5
5

1.0
1.0
1.0

5
5

2.0
10.0
10.0
10.0
2.0

".".

V
mA
mA
mA
kQ
kQ
kQ
MQ
MQ
MQ
kQ
kQ
kQ
kQ
kQ
kQ
Q

Dynamic Values
Digital Interface
Input Logic "1"
Input logic "0"
Output Logic "1" (IOH = -120!lA)
Output Logic "0" (IOL - 360!lA)
lOUT Tristate (Logic "1" or "0")
Input Capacitance
Logic Input Current (V IN = 0 to 5.0V)
lOX (VOUT = 5:0V)
MX-COM, INC.

3.5
1.5
2
3
3

4

4.6
0.4
4.0
7.5
1.0
4.0

V
V
V
V
I1A
pF
I1A

!lA
Page 217

I

MX805A

Overall Performance
CTCSS - Decode
Sensitivity (Pure CTCSS Tone)
Response Time (Composite Signal)
100 Hz to 257 Hz Tone
65 Hz Tone
Tone Measurement Resolution
Tone Measurement Accuracy
Notone Response Time (Composite Signal)
False Tone Interrupts (Noise Input only)

I

6

-20

-26.0
250
375

9

7
10

+0.5
250
20.0

65.0

NRZ -TX
TX Bit Rate
TX LPF (3dB) Bandwidth
Sub-Audio TX Output Level
CTCSS
NRZ
Amplitude Adjustment Range
Adjustment Step Size (7 steps)
Sub-Audio Bandstop Filter
Passband
Passband Gain
Passband Gain (w.r.!. gain at 1.0 kHz)
Stopband Attenuation
at 250 Hz
at150 Hz
at 100 Hz
Residual Hum and Noise
Alias Frequency
Receive Lowpass Filter (see Figure 10)
Cut-off Frequency (-3dB)
Passband Gain

Page21B

ms
ms
%
%
ms
tHr.

0.2
-0.5

Tone
Tone Amplitude
Rise Time (to 90%)
Fall Time (to 10%)
Total Harmonic Distortion
NRZ - Decode
RX Bit Rate Sync Time
RX Bit Error Rate

dB

257
0.2
+1.0
30.0
50.0
5.0

-1.0

Hz

0/0
dB
ms
ms
%

edges
11

p(error)

67.0
75

bitsts
Hz
dB
V pop

0
0.871
-2.58
8

2.58

dB
dB

3000
0.5

Hz
dB
dB

-45.7
62.5

dB
dB
dB
dBp
kHz

0.86

297
0
-1.5
36.0
24.0
18.0
-50.0

280
6

Hz
dB

MX-COM, INC.

MX805A

Receive Lowpass Filter (cont'd)
Stopband Attenu~tron

6

@ 300 Hz
"c@ 350 Hz

Residual Hum and Noise

12
-50

XtaVClock Frequency (fXTAJ

4.0

,

Signal
Level
(dB)

~

...

~

c::

o

''5
en

~

~

Xtal
VDD

. ..

= 4.0 MHz :':"'.,':.'
= 5.0V

MHz

I

.

'\

"\ \1

is

6.1

. .•. >

':'.
'y-

dB
dB
dB

;v'

.-r-v~

V

o

100

200

300

400

500

600

700

800

Frequency (Hz)
Figure 10 - Typical Frequency Response of RX Lowpass Filter

NOTES:
1. Device control pins: Serial Clock, Command Data, Wake and CS.
2. Reply Data output.
3. Reply Data and IRQ outputs.
4. Leakage current into the "Off' IRQ output.
5. See Control Register
6. With input gain components set as recommended in Figure 2.
7. Probability 97%.
8. See Gain Set Register.
9. For fCTCSSIN of 65 Hz to 100 Hz, Response Time tR = (100/fTONE) x 250 ms.
10. Distributed across the RX frequency band.
11. With 10dB signal-to-noise ratio in a bit-rate bandwidth.

MX-COM, INC.

Page 219

I

Page 220

MX-COM, INC.

Technical Specifications

Section 3:
Sequential Tone
Encoders/Decoders

I

The following section contains specifications on
MX·COM's Sequentially Coded and Selective Call tone
products

Device
MX013
MX203
MX503
MX803A

MX-COM, INC.

Description
HSC Tone Decoder
Selective Call Codec
Sequential Tone Encoder
Audio Signaling Processor

Page

p.229
p.234
p.242
p.249

Page 221

I

Page 222

MX-COM, INC.

HEXADECIMAL SEQUENTIAL CODE (HSC) SIGNALING
SYSTEMS OVERVIEW
By William Farlow

MX-COM, INC.

INTRODUCTION
The Hexadecimal Sequential Code (HSC) is an
MX·COM sequential tone signaling protocol which utilizes the non-predictive capabilities of the MX'03 series of monolithic tone processors.
HSC permits address codes, instruction codes and
informational messages (data blocks) to be exchanged
on an unrestricted basis between all units in a network.
HSC provides the key to designing fully integrated
base/mobile/personal communications supervisory
control and data retrieval systems. The use of tone
encoded information insures that Signaling integrity is
maintained under poor communications conditions often conditions too poor for voice. HSC allows the
transmission of messages and unit addresses without
cross-code falsing. It allows different length addresses

to be used within the same network. HSC also confers virtual immunity to noise or voice falsing while providing a high signaling probability. MX.COM's HSC
products interface easily with microprocessors to minimize the required system hardware.
Subsets within the set of HSC tones are compatible
with the frequencies and protocols used for a variety
of international "5/6 tone sequential" selective signaling conventions. These national or international conventions dictate the use of specific tones, tone durations, etc. - each of which is accommodated by chip
mask changes for some of our devices or software
control in the case of the MX803A. Compliance with a
particular national tone format merely requires selection
of the desired component or microprocessor software.

Table 1: MX-COM HSC IC BUILDING BLOCKS1
* Suffix Code
A
C
E
Z

1

National Tone Sets
Metropage U.S.A.
CCIR International
EEA United Kingdom
ZVEI Germany
HSC Function
ENCODE
DECODE

MX013Q(*)
X

MX203Q(*)

-

MX503(*)
X
X
X
X

-

MX803A
X
X
X
X

-

X

X
X

X
X

X

-

X

Application Notes for the MX'03 HSC Series are available on request.

The HSC concept provides two information level capacities, or data payloads: quadradecimal and hexadecimal.
The part suffix "Q" represents a
quadradecimal (14 information levels) system specifically structured around the needs of personal radio
selective calling with an added data transfer capability. Selective calling uses an ID much like a telephone
number to allow selective radio-to-radio addressing. In
this quadradecimal system some HSC characters are
reserved for system control purposes to provide group
calls, multiple audible alert patterns, mixed address
lengths, and the transmission of data blocks. A hexadecimal set, possible with the MX503 or MX803A, affords a full 16 level data transmission capability, providing a reliable means for transferring 4-bit data between microprocessors over a noisy channel. System
control, for other than pure data transmission purposes,

MX-COM, INC.

is then dependent upon the processor's programming.
With a hexadecimal tone set, a seventeenth tone is
then required for the REPEAT function.

GENERAL DESCRIPTION
This application note describes the coding rules and
tone parameters used for quadradecimal HSC tone
sets. Data bulletins for each of the MX'03 Series products are included in this catalog. A closed code protocol (Le. no tone separation) is employed, in which each
sequence of information characters is preceded and
terminated by a "boundary" character. A particular
boundary character initiates signal activity and directs
the type of processing to be performed on the characters that follow. Two process modes are allowed one which uses unit address information of finite length

Page 223

I

and another which simply has informational messages
(data blocks) of any length.
Within the finite address mode are found several special function cc;lpabilities. These are: a) group-call and
all-call codes which may be programmed to output a
distinctive audible alerting sound, b) primary and secondary addresses with distinct audible sounds, and c)
a special function suffix code that inhibits the audible
output entirely while erasing any call message previously stored in memory. Further, signaling compatibility with systems employing a "preamble tone" is provided.

I

Beyond mere compatibility with six tone Signaling, HSC
affords a flexible means of achieving battery saving independent of the preamble tone method. This is accomplished by using the data block suffix capability in
a manner that directs variable length dormancy periods. The length of the dormancy period is controlled
by the dispatch control center. Thus a receiver or group
of receivers might be commanded into a battery saving state for several seconds, minutes or overnight.
During a dormancy period the only current drain requirement would be for a timing circuit. The receiver's
active duty cycle can then be reduced to just a few
milliseconds at appointed times separated by lengthy
quiescent intervals - the length of which may be dictated by the user's type of service, duty roster assignment, system traffic loading, etc.
The combination of address and data processing
modes permits HSC units to be selectively addressed,

and an informational message appended. An example
might be the transmission of a phone number to a
pager equipped with a digital display. The subscriber's
paging address may be followed by a phone number
that he or she is to call. The "air time" consumed in
the transmission of such a message varies with the
tone durations specified by different national protocols.
In the U.S. "Metropage'" convention the entire transmission comprising a five-digit discrete address and
seven digit phone number consumes less than 1/2
second. This, of course, contrasts quite favorably with
the air time used for an equivalent tone and voice
message which typically lasts several seconds.
Another example, using an address followed by control data and also a voice message, could be a taxicab dispatching system where the dispatcher sends
an address or instructions to a specified cab driver. The
message could be directed to a voice storage and retrieval system based the MX802 or MX812.

International 5/6 Tone Sequential
Signaling Conventions
Four national 5/6 tone sequential selective signalling
tone sets are currently offered: The international Telecommunications Union's CCIR recommendation, the
United Kingdom's EEA standard, the German ZVEI
standard, and in the U.S.A., a de facto standard employed by the Bell System and Radio Common Carriers compatible with Motorola's Metropage terminal.
These tone sets are described in the tables that follow.

Table 2: Nominal Tone Frequencies (in Hertz)
Character

Binary code

Metropage

CCIR

EEA

ZVEI

0
1
2
3
4
5
6
7
8
9
A
B
C2
D
E
F

0000
0001
0010
001 1
0100
01 01
01 1 0
o1 1 1
1000
1 001
1 01 0
1 01 1
1 1 00
1 10 1
1 110
1111

600
741
882
1023
1164
1305
1446
1587
1728
1869
2151
2435
2007
2295
459
NOTONE

1981
1124
1197
1275
1358
1446
1540
1640
1747
1860
2400
930
2247
991
2110
NOTONE

1981
1124
1197
1275
1358
1446
1540
1640
1747
1860
1055
930
2247
991
2110
NOTONE

2400
1060
1160
1270
1400
1530
1670
1830
2000
2200
2800
810
970
886
2600
NOTONE

'Metropage is a registered trademark of Motorola, Inc.
2Note: HSC tones not specified by national convention.

Page 224

MX-COM, INC.

Table 3: Encoder Requirements
Parameter
Tolerance
Duration
Maximum Inter-tone Gap
Minimum Inter-sequence Gap

EEA

Metropage
fo ±0.1%
33 ±0.5ms
none
33ms

CCIR
fo ±8Hz
100 ±10ms
7.5ms
290ms

Metropage
fo ±16Hz
not specified

CCIR

EEA

ZVEI

fo±1%
fo ±3%

fo ±1%
fo ±3%

fo±2%
fo ±4.5%

fo ±1%
40 ±4ms
4ms
100ms

ZVEI
fo ±1.5%
70 ±15ms
15ms
140ms

Table 4: Decoder Requirements
Parameter
Must Decode
Must Not Decode

HSC CHARACTER SET
In the system with a quadradecimal data capacity (part
number suffix "0") sixteen characters (four binary line
levels) are employed. Fifteen of these characters have
unique tone coded frequencies; the sixteenth character, the hexadecimal "F," is the code assigned to the
NOTONE state. The NOTONE "F" code and two of the
fifteen tone coded frequencies, the hexadecimal "8"
and "E," are reserved for system control purposes. Alternate use of "8" (when it is contained within an established data block) creates the code for a hyphen
(or optionally a character blank), thus yielding fourteen
usable data codes. The quadradecimal four line binary
code assignments follow industry practice.

MX803A Audio Signalling Processor: A twenty-four
pin PLCC or DIP full duplex device capable of working
in any standard or custom tone system through serial
microprocessor control of the tone set, timing, etc. The
MX803A is the most flexible member of our HSC product family.

HSC SYSTEM OPERATING RULES
Transmit: Tones are transmitted as individual single
frequencies, without inter-tone gaps, until the code sequence is complete. Where an inter-tone gap is unavoidable, the gap duration should not exceed 15ms.

HSC BUILDING BLOCKS: THE MX-03
SERIES

Each consecutive tone in a transmission must be of a
different frequency. Where consecutive characters are
identical a dedicated "REPEAT" character (E) should
be substituted automatically.

The functional blocks of the HSC system are enumerated and briefly described below. Operation is collectively governed by a set of HSC Operating Rules which
are presented in the next section.

Consecutively transmitted addresses or data blocks
are separated by an interval during which no tones are
transmitted. This interval should not be less than 28ms.

MX013Q* Sequential Tone Receiver: A twenty-four· Receive: HSC Tone Receivers process all valid single
pin PLCC on 0.6 inch centers requires an external tone coded characters (from the HSC tone sets of the
560kHz ceramic resonator. Performs the system A to appropriate national convention) without regard for their
D function, decoding tones to output 4-bit binary words. sequence. To be valid, a character's tone frequency
must fall within the band limits established for the naMX503* Sequential Tone Transmitter: A sixteen pin tional tone set. Further, the tone's duration must be at
DIP generates all hexadecimal and quadradecimal fre- least 25ms. The presence of an invalid tone frequency
quencies for tone coding in anyone of the four national at the input to an HSC tone receiver yields a NOTONE
sequential tone signaling formats according to HSC output code. This resets the address decoder or transponder software, as the case may be.
rules.
MX203Q* HSC EncoderlDecoder: A twenty-four pin
PLCC or DIP full duplex HSC device for the CCIR International tone set. Operates under microprocessor
control via a 4-bit I/O data port.

MX-COM, INC.

Group Calling: To effect a group or all call, the tone
code character "A" is substituted as an address digit.
"A" represents all digit values "0 through 9." In a system employing 5-digit addresses, an "A" encoded once

Page 225

I

in an address will signal a group of ten units. Two "A"
entries increases the group size to 100. Three "A" entries yields 1000 units in a group; four yields 10,000;

and, five yields 100,000. The latter comprises an all
call (in a five-digit address system). Sample group calls
and an all-call are listed below:

Table 5: Group Call Example
5-Digit Address
1234A
123A5
123AA
AAAAA

Entry
(10 Units)
(10 Units)
(100 Units)
(100K Units)

Note that according to HSC rules, repeated characters
are automatically transmitted as an "E." Thus, the actual transmission of the above all call example would
be "AEAEA."

Preamble Tone Operation: A preamble tone is used
as one method of reducing the continuous battery drain
of pagers in some systems. It may also be used as a
repeater wake-up tone. But, it can also offer a means
of expanding a system's code capacity. When the preamble mode is selected each address decoder should
be assigned a tone code that it must first detect in order to enable normal 1 to 5 digit decoding. A Preamble
Tone must be transmitted for slightly longer than the
device power-down time to ensure that the receiver will

Addresses Responding
12340 thru 12349
12305, 12315, 12325, ... , 12395
12300 thru 12399
00000 thru 99999

enable when it "awakens." If an address decoder's assigned preamble tone is not detected on power up the
unit can power down immediately for a preset period
of time. The addition of an external timer that periodically powers up the unit is assumed. The NOTONE "F"
detected between the preamble digit and the first digit
of the address should, in this case, be accepted without resetting the address decoder. Systems that do
not need the extra capacity can use the first digit of the
address as the preamble tone.
Examples of preamble tone operation follow. In these
examples a receiver is assumed to have the digit "6"
as preamble/enable with an address "12345."

Table 6: Preamble Tone Example
Address Received
F6F12345F
F7F12345F
F6F1234F

Tone Period Envelope Restriction: Some national
tone signalling protocols impose limits on tone or address envelope duration greater than those required for
HSC operation. These timing restrictions can be
handled in software with the aid of on-chip timers on
the MXB03A and MX203Q(*), while external timing is
required for the MX503(*) and MX013Q(*).
Data Mode Operation: Data mode operation commences upon receipt of the aSSigned DATA PREFIX
code "B," following either a valid address or the,
NOTONE code. The "B" code serves both to inhibit
address mode operation and to initiate the data mode.
All characters in a data block up to a NOTONE code
can thus be processed as data including characters/
tones normally reserved for system control purposes.

Page 226

Does Receiver Respond?
YES
NO (different preamble)
NO (different address)

Crosscode Falsing: The prevention of crosscode
falsing of non-HSC capable receivers by the transmission of HSC data blocks to MX·COM receivers may require special attention. First, the code reset means of
the non-HSC receivers must be considered. Generally
this is a time dependent control in which each succeeding digit must be detected within a minimum period. If
the minimum period is known, it is a simple matter to
sustain an HSC special function character, typically "B,"
for the reset interval of any non-HSC units. Crosscode
falsing is prevented because non-HSC receivers detect
the special function HSC tones as tone-gaps. Insertion
of an HSC special function character may be required
only once, or, if the data sequence is lengthy, at periodic intervals. A phone number is an example of a
transmission in which the data prefix "B" will typically

MX-COM, INC.

be followed by 7 to 10 decimal digits. To prevent these
digits from being decoded as paging addresses by nonHSC receivers, the "8" code should be entered as a
tone-gap at additional points to induce reset before a
cross coded error results. For example, the phone number 7480505 could be transmitted as 74880505. Within
a data block "8" may optionally be treated as a character blank, hyphen, or simply discarded by the HSC
receiver.

Transpond Mode Operation: Transponding serves
an echo function that acknowledges receipt of discrete
unit calls and serves polled status report data gathering applications.
Automatic Number Identification (ANI): ANI serves
the function of identifying the caller's ID and can easily
be implemented within the HSC framework using the
data payload portion of a tone sequence.

'note: Add suffix letter codes for national tone set designation as follows: A=Metropage, C=CCIR, E=EEA, Z=ZVEI.
This only applies to MX013, MX203, and MX503.

I

MX-COM, INC.

Page 227

Keyboard
0

1 2 3
5 6 7
8 9 A B
C D E F
4

~ocessor

or

PLA

Beep
One-way Selective Calling System

MX503
HSC
Tone Encoder

MX013Q
HSC
Tone Decoder

xmt

JlProcessor
or
PLA

One-way Voice Messaging System

I

xmt

MX013Q
HSC
Tone Decoder

~ocessor

MX802
CVSDCodec

/
'\.

Bob,
Please call the office!

Keyboard
0

1 2 3

4 5

6 7
8 9 A B
C D E F

Two-way Supervisory Control & Alarm

, - - - - - - - - , xmt
MX803A
~ocessor

Encoder/Decoder

MX803A

"'--i

Encoder/Decoder

xmt

/
DISPLAY

'\.
Beep

'\.
Beep

Page 228

MX-COM, INC.

MX013QALH

MX·~M,IN~.
HSC TONE DECODER
FEATURES
• Operates on 2.5 V Supply
• Low Current Drain
• USA METRO Toneset
• Chip Enable, Clock Frequency Select and Interrupt
Request Pin Functions

I

APPLICATIONS
• Pagers
• Mobile Radio Selective Call
• Remote Signaling

MX013QALH
PLCC-24

Description
The MX013QALH HSC Tone Decoder combines the
functions of the MX102LH and MX202QALH into a single
PLCC package. To the circuit designer, the MX013 offers a
smaller device "footprinf', reduced power and current requirements, and a lower device cost. The MX013's patented
autocorrelation algorithm ensures high signaling reliability in
noisy environments.

The MX013 operates within a 2.5V to 5.5V supply
voltage range and draws approximately half the current of
the older MX003 design. It is available exclusively in a 24-pin
PLCC package.
Three new pin selectable functions are incorporated
on the MX013: Chip Enable, Clock Frequency Select and
Interrupt Request.

----'-+---'cs

>:....

Change
[E;)~~fi~;,Data
Outputs
1 }

560 kHzkHzDIPDIP

-IJr;:::;:===::::::::=r;:~~::::::~~:::;32:+===:23.333
1.
C1 : 0.Q1~
C2: 0.001~
C3:47 pF

C4: 5·65 pF
C5: 47 pF

R1:1 Mil
R2:1 Mil

X1: 560 kHz

Figure 1 - External Components

MX-COM, INC.

Page 229

MX013

PIN FUNCTION CHART
Pin Function
3

Signal Input: HSC tones are AC coupled to this pin by a 1OOOpF capacitor. DC bias of the internal high gain
limiter is set up by an internal 3 MQ bias resistor connected between this pin and the signal bias pin. These
pins should not be loaded with any other circuitry.

5

Signal Bias: See signal input.

7

23.33 kHz Clock O/P: A 23.333 kHz buffered squarewave logic output directly derived from the oscillator
frequency (nominally 560.0 kHz). This pin may be used for auxiliary functions, e.g. external timing of received
tone periods and for other '03 series devices.

8

Xtal: Output from on-chip inverter (See XtaI/Clock).

9

Xtal/Clock: Input to on-chip inverter. May be used in conjunction with Xtal O/P and.a 560 kHz ceramic
resonator and trimming capacitor or a 4.48 MHz quartz crystal and fixed passive components. May also be
used as a buffered input to an externally derived 560.0 kHz or 4.48 MHz clock.

10

560 kHz buffered O/P: A buffered 560 kHz signal is output from this pin.

11

Clock Frequency Select: This pin is normally at logic "1" if a 560 kHz resonator is being used. If held at logic
"0," a divide by 8 is switched in after the oscillator circuit to divide down the 4.48 MHz frequency to 560 KHz.
This pin has a 1 MQ pullup.

12

Vss: Negative Supply (GND).

13

Hold liP: If taken to V 55 and a tone is input, the resulting Data Change output latches to logic "1" and the Data
lines output the code for the detected tone regardless of subsequent changes to the input tone, until Hold is
returned to V DO' This facilitates InterrupVHandshake routines for microprocessors when used in conjunction
with the Data change O/P. This pin has a 1 MQ pull up.

14

Power-up Reset: A logic level "1" is required at this pin for a duration of at least 1 ms after clock is applied
to reset internal circuitry on power-up. For slow rising supplies the recommended time constant should be
increased accordingly.

15

IRQ: Interrupt Request, an output, is latched to logic "0" when a tone is detected and the CS pin is atVoo ' i.e.
chip disabled. This pin is reset to logic "1 ," enabling is for use in wire-OR-ing with similar outputs from other
peripherals.

16

CS: Chip Select. When this pin is taken to Voo ' the chip is disabled and the data outputs 00-03 and Data
Change output go open circuit. When taken to V 5S the chip is enabled and the IRO output is reset to logic "1."

17

Data Change: A 1 ms pulse is generated at this pin upon detection of a valid tone and new data is presented
to the 00-03 outputs. The signal from this pin can be latched at a logic "1" after detection of a tone (see Hold
input). This output is tri-state.

19
20
22
23
24

03 Data Outputs:
02
01
00

A 4-bit word is output from these pins
after successful decode and represents
the HEX value of the decoded tone
frequency. These outputs are tri-state.

VDD: Positive Supply

1,2,4,6,18,21: Unused pins.

Page23D

MX-COM, INC.

MX013

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

OPERATING LIMITS

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following conditions
unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(refVss=OV)
Sink/Source Current (Total)
Total Device Dissipation
@ T AMB = 25°C
Derating
Operating Temperature
Storage Temperature

-0.3 to 7.0 V
-0.3 V to Voo + 0.3 V
20mA

Xtal/Clock fo = 560 kHz

800mWmax.
10mW/oC
-40°C to +85°C
-55°C to + 125°C

Characteristics are valid for all tones unless otherwise
stated.

Static Values
Supply Voltage (Vss=OV)
Supply Current

character response with no input tone).

V

4.5

2
3

35
±20

0.5

V

Vod2

mVrms
Hz
Hz

±60

4

V

f.lA

500

Logic "1" Output
1 Source = 1 mA
Logic "0" Output
1 Sink = 1 mA
Logic "1" Input Level is 3.5 V min.
Logic "0" Input Level is 1.5 V max.

Dynamic Values
Signal Input Range
Decode Bandwidth when P>0.995
Not-Decode Bandwidth when P<0.03
Noise Response Rate (hours per F - F - F single

5.5

2.5

hour

0.15

Decode Response Time:
Notone to tone (F - F)
Tone to notone, Tf (F - F)
Min. intertone gap for "F"

5

20

5
6

33
15

25

33
53
28

ms
ms
ms

Notes:
1) A.C. coupled sine/squarewave.
2) With minimum tone period (Tp) specified for toneset. P = Decode Probability. SNR = 3dB.
3) All conditions of input SNR and amplitude with maximum Tp specified for toneset.
4) Gaussian input noise, bandwidth 6 kHz, maximum input level corresponds to 1-digit code falsing rate. F=random single
character.
5) Delay from change of input (tone applied/removed) to change at 00-03 outputs (see Figure 2).
6) Included in tNT" Minimum tone gap requirement for "notone" recognition. Outputs = F after delay (see Figure 2).

MX-COM, INC.

Page 231

I

MX013

Binary Coded Output

Input Tone Frequency (fo in Hz)
MX013QA
600
741
882
1023
1164
1305
1446
1587
1728
1869
2151
2435
2007
2295
459
NOTONE

I

D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Quadradecimal Data
Character

DO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
2
3
4
5
6
7
8
9
A

B
C
D
E

F

Table 1 - MX013 Tone Table

Timing

X
)*,__
i '--------" I '-------"

Input _ _ _ _ _--.,.;No...;.to...;.ne_ _ _ _ _(

Tone 1

Tone 2

N_o_ton_e_ _ _ _ _ __

~

VDD-./

Clock

Y.

I.

I

-----<~~l

,,,--,

Data O/P

i

I

I

i

!

; l _________~.~
__~l_ _ _ __+--~·--t~--~-----.' ___~",!
"i'~
~!
----' ~
vY,---~'vV
~
~
-,,~
~",
-,/,!,--.. . .
!..

PUR

II

I,

i

1.

~

tRESP

f·..._-"'-_ _

'j

, ,_ _ _
F__

.•....

,..

Data

tRES,

DE

,,~

Data 1

_F_ __

__
Da_ta_2_ _

'1

rt

Cha~----------'

IA\

'------<-'!,
~
~tDCrj

I

/\

'-------'

t'UR

(PUR Time): 2 ms Min.

• 00,03 represents the input

t"

(Data "E' TIme): 33 ms Typ .

frequency present during and
after PUR [shown as F (Notone)]
in this example

t,ULS (DC Pulse Duration): 1 ms Typ.

I"'-

I...----~

toe

(Data to DC Pulse Time): .5 ms Min., 1 ms Max.

t"""

(Tone Response Time): 20 ms Min., 33 ms Max.

tNT

(Noton. Response Time): 33 ms Min., 53 ms Max.

Figure 2 - Normal Timing Operation (not drawn to scale)

Page 232

MX-COM, INC,

MX013

Timing

Inpul

=>(
..

X~_li_on_e_2_----"X,-_ _ __

Tone 1

I RESP

-i

DOJ~ ~~~~~~~~~~=X,--

I RESP : 20 ms Min" 33 ms Max,

__

--,>(

D_a_Ia_l_ _ _ _ _

~ loe!-

I DATA : 2 ms Max,
Dala 2

,-IDATA-,.IDC.

;1--,------'~~

Dala

Change - - - - - - - - - '

.,;

loe : ,5 ms Min" 1 ms Max.
I NORM : 120).ls Max.
I HOLO: 50).ls Min,

~

:1 ND~M

/r-------

HOld-----""""\~,

,'----"__ _ _ _--JA
; I HOLD

;

,~:

Figure 3 - HOLD Operation (not drawn to scale)

Inpul

~(

Valid Tone

~,~------------------------, I·
.:..

RIRQ

)' ,"

l/

iOO-------..\

.:'1..._--------'"

cs ------------.\..__I",,'RQ'-.--+.:

l

(\'--____---J/:

IRIRQ :

20,5 ms Min., 34 ms Max.

I IRQ

lOllS Max, (reduced if an

:

external pullup is used)
lACS : 250 ns Max.
IOHR : 100 ns Max.

/,--------':'~

DO)~ -------------,i----<(:

;\
"~
lACS ;

Valid D a l a ' > - -

~

IOHR ;
i~_______

Figure 4 - CS and IRQ Operation (not drawn to scale)

MX-COM, INC.

Page 233

MX·~,IN~.

MX203Q*

HSC ENCODER/DECODER
FEATURES
• HSC (5-lone) Encoding/Decoding
• CCIR, EEA or ZVEIISZVEI Tonesets
• Separate General Purpose 4-bil Inputl2-bit
Output port
• Mobile or Handheld SelCall
• 4-bit Microprocessor 110 Data Port
• Powersave Ability
• Low-Power 5-volt CMOS

MX203Q*J
24-pin CDiP

MX203Q*LH
24-pin PLCC

Description
The MX203Q* HSC Encoder/Decoder is a ~P peripheral intended for radio-selective calling systems. Three
international tone sets are supported: CCIR (C), EEA (E) or
ZVEI/SZVEI (Z), as indicated by a letter suffix.
A 4-bit bi-directional data bus provides 2-bit address, chip select, read/write and interrupt request to the
~P. Separate 4-bit input and 2-bit output ports allow ~P
access by external keyboards or hexadecimal switches
through the MX203. Functions such as PTT, RX Squelch,
Beepalerts and Lamp Drivers can operate through this bus.
An on-chip General Purpose Timer is provided for
such functions as RX and TX tone period timing. Time

periods of between 1Oms and 140 ms may be programmed
in 10 ms steps by the ~P interface.
The MX203 reference oscillator uses a low cost
4.0 MHz xtal or externally derived clock. The divide by 4
(1.0 MHz) output may be used to drive the clock circuitry of
other devices such as the MX365A CTCSS Encoder/
Decoder, MX004 Voice Band Inverter, orthe MX214 VSB
Audio Scrambler.
The MX203 requires a single 5V supply and utilizes
Chip Enable and Powersave functions for reduced current
usage in the Standby mode. It is available in 24-pin PLCC
and CDIP packages.

XTAl1ClOCK

CLOCK

4

Tit TONE OUTPUT

TOtIE ENCODER
AND
REGISTER

TIMER REGISTER

AUOIOINPUT

TONE DECODER
AND
REGISTER

STATUS
REGISTER

BI-DIRECTIONAL
CPU
INTERFACE

INSTRUCTION
REGISTER
AUDIO OUTPUT
j/PO

:;~ ------------------~

II.

INPUT PORT
AND
REGISTER

O/PO
O/P1

OUTPUT
PORT

Figure 1 - Internal Block Diagram

(*) specify CCIR (C), EEA (E) or ZVEIISZVEI (Z) tonesets.
Page 234

MX-COM, INC.

MX203

PIN FUNCTION CHART
Pin Function
1

VDD: Positive Supply

2

Audio Output: The received audio output, selected by the Audio Output Enable bit, 01, in the instruction
Register. This output could be the result of a squelch function.

3

Audio Input: The audio input to the Tone Decoder and audio output switching. The composite (voice and tone)
received audio requires coupling to this pin by capacitor C3. See Figures 1 and 2.

4

Vss: Negative supply (GNO).

5

Xtal/Clock: Input to clock oscillator inverter. A 4.0 MHz xtal or externally derived clock pulse input should be
connected here. See Figure 2.

6

Xtal: The output of the 4.0 MHz clock oscillator. See Figure 2.

7

Clock+4: a 1.0 MHz (X1 +4) clock is available at this output for external use. Note the output impedance and
source current limits.

8

CS: Chip Select. The chip select input. A logic "0" on this pin will select the MX203. See Figure 3.

9

IRQ: The interrupt logiC output. An active interrupt is set as a logic "0." This pin can be wire-OR-ed to external
circuitry. An external pullup resistor may be required on this output.
Conditions that cause Interrupt Requests are:
1) RX Ready (tone decoded)
2) Timer cycle expired

IRQ and Status bit DO

3) Input Port data change

IRQ and Status bit 02

IRQ and Status bit 01

10

AO:

Register address pins. These inputs, together with the RIW input, select the internal register

11

A1:

to be addressed by the CPU Interface (00-03) using the logic states as detailed below.
Register information is detailed in the following pages.

Write

Read

RJW

A1

AD

0

0

0
0

0
1

0
1
0

Instruction
Timer

1

0

0

Tone Decode

1

0
1

1

Status

0

Input Port

1
12

DO

The tri-state 4-bit microprocessor

13

01

interface for communication with the

14

02

internal registers as directed

15

03

by the AO, A 1 and RIW inputs.

MX-COM, INC.

Register
Tone Encode

Page 235

I

MX203

Pin Function
-

16

RIW: The ReadlWrite logic. which with the Ao and Al address inputs determines the Microprocessor/
Register communication. Read = logic "1", Write = logic "0".

17

TX Tone Output: The transmitted tone output of the Tone Encoder. Tone "0" (Notone) will cause this output
to go to VBIAS' When not enabled this output is high impedance.

18

VBIAS: The output of the on-chip bias circuitry, held at VDr/2. When the Encoder is not enabled this pin will be
at Vss. This pin requires decoupling to Vss with a capacitor, C4.

19
20

O/Po:
O/P 1:

The 2-bit logic output port whose state is controlled by the
Instruction Register (D2 , Ds)'

21
22
23
24

IIPo:
I/P 1:
I/P 2 :
liPs:

The 4-bit logic input
port. (See Figure 2.)
These pins each have an internal
1 MQ pullup resistor.

General and Operational Notes
Power-up Arrangements
It is recommended that the following sequence is used to set
all internal registers to a start-up state upon power-up.
Write - Hex "0" to Timer Register for a period greater than
Power-Up Reset Time (TS).
The following actions clear the Status Register and reset all
interrupts.
Read - Status Register.
Read - Input Port Register.
Write - To Output Port as required.
The data in the Decoder Register is not valid until after the
first active Decoder interrupt has been received.

Data written to the device by the CPU Interface is acted upon
at the end of the Data Set-up Time (tDSW)' when the CS input
goes high (logic "1").
The Timer may be written to at any time. The Timer is reset
when data is written to it. The new Timer period starts when
the CS input goes high (logic "1 ").

Layout
All external components (as recommended in Figure 2)
should be kept close to the package.
Tracks should be kept short, particularly the Audio and Vss
inputs.

Operation of the MX203 is Full Duplex. The receive mode is
achieved by writing any Timer setting except Hex "0."

Xtal/clock and digital tracks should be kept away from
analog circuitry. Analog inputs and outputs should be
screened whenever possible, and high level TX Tone Output
kept separate from other analog inputs and outputs.

The Tone Decode Register must be read before the expected
arrival of the nexttone, as register contents are overwritten.

A "ground plane" connected to Vss will assist in eliminating
external pick-up.

Operation

Page 236

MX-COM, INC.

MX203

External Register States
The following descriptions show the condition of each of the 6 registers used by the MX203 to communicate with
microprocessor and radio systems. Table 1 details the hexadecimal 4-bit data words used in these registers. Timing
information for the CPU Interface is given in Figure 3.

Instruction Register

Write Only

RIW

=0, Al =0, Ao =1

The Instruction Register addresses the functions of the MX203
Bit No

Do

Logic
1

Function
TxEnable:

Enables the Transmitter circuitry
Disables the Transmitter circuitry

o
Audio Output Enable:

Switches from Audio Input to Audio Output
Disables the Audio Output Switch (S 1)

10rO

Output Port OIP0:

The logic state of this line

10rO

Output Port O/P l :

The logic state of this line

1

o

Tone Encode Register

Write Only

RIW

=0, Al =0, Ao =°

D2
MSB
The 4-bit Hex. word written to this register will produce the required tone (Table 1) at the TX Tone Output.

Tone Decode Register

Read Only
D2
MSB

The 4-bit Hex. word in this register will indicate the frequency (Table 1) of the received tone.

Timer Register

Write Only

RIW

=0, A1 =1, Ao =°

D2
The 4-bit Hex. word written to this register wili automatically reset the timer and start a timing cycle as shown:

Hex Code

o

1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MX-COM, INC.

Function/Tone Period
Disable Receiver, Transmitter and Timer
Reset and start tone period of:
10ms
20ms
30ms
40ms
50ms
60ms
70ms
BOms
90ms
100ms
110ms
120ms
130ms
140ms
Disable Timer Operation Only
Page 237

MX203
Read Only

Status Register

The Status Register indicates the source of any interrupt.
Bit No.
Condition [A logic "1" in the Status Register indicates that the bit is
Set. The Interrupt line (IRQ) is a logic "0" when active.]
DO

Rx Ready:
DO and an interrupt are Set when the Tone Decoder has decoded a received tone and
latched the 4-bit Hex. word into the tone Deocde Register. This register must be read
before the next tone is decoded or the information will be overwritten.
and the interrupt are Cleared by reading the Status Register followed by reading the
Tone Decode Register.

o

01

02

Timer:
01 and an interrupt are Set when the intervals programmed by the Timer Register have
expired. 01 and the interrupt are Cleared after reading the Status Register.
Input Port (liP 0 - liP 3):

o and an interrupt are Set when the data state at the Input Port changes. D., and the
interrupt are Cleared by reading the Status Register followed by reading the Input Port
Register.

03

This bit is unallocated. Set at logic "0."

Input Port

Read Only

RIW

=1, A1 =1, Ao =0

0,
MSB
By reading this register the microprocessor can monitor the state of the 4 logic input pins (l/Po - I/P3). This facility allows
external systems to communicate with the microprocessor through this device.
The MX203 caters to CCIR, EEA and ZVEl/Suppressed ZVEI sequential tone system frequencies in three tone sets, "C,"
"E, "and "Z" respectively, as shown in Table 1. See the "Specifications" pages for overall MX203 Tone performance
characteristics.
Hex.
Input/Output
0
1
2
3
4
5
6
7
8
9
A
B
C
0
E

F

D3

D2

D,

Do

"C"ToneSet
fo (Hz)

"E"ToneSet
fo(Hz)

"Z/SZ" Tone Set
fo (Hz)

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1981
1124
1197
1275
1358
1446
1540
1640
1747
1860
2400
930
2247
991
2110
Notone

1981
1124
1197
1275
1358
1446
1540
1640
1747
1860
1055
930
2247
991
2110
Notone

2400
1060
1160
1270
1400
1530
1670
1830
2000
2200
2800
810
970
886
2600
Notone

Table 1 - Tone Frequency Programming Codes
Page 238

MX-COM, INC.

MX203
External Components
MX203
DO

2

AUDIO OUTPUT

TIMER

~

3

AUDIO IN PUT

TONE
·1I DECODE

4

Vss

c2::i::

::;:C1
XTAL/CLOCK
XTAL
1MHz CLOCK
OUT

6

~~

7

CS

-...:-

IRQ

Vss

Ao
A1

Do

r

~

+

! REGISTER
STATUS

8
9

I

10

IIP2

22

IIP1

~

t

IIPo

20

OIP1

19

OIPo

18
17
16
15

TX TONE
OUTPUT

O2

• • ••

13

01

Value
iMn
33pF
33pF

I

03

14

Component
Ri
C1
C2

--

RfIN

INTERFACE

11
12

alP

PORT

TONE
ENCODE

l

IIP3

21
~

CLOCK

24
23

lIP
~ PORT

·!INSTRUCTIONt
REGISTER

5

R1

.---

"'-./tI

v,T1

Component
C3
C4
X1

~

Vss

Value
0.1 !iF
1.0!iF
4.0MHz

Tolerances: R = ±i0%, C = ±20%
Figure 2 - External Component Connections

,
=x~,--------~X~

=x :

; X"..----

~~~

R/W

~~

~~~,
----~~t~~

~~
~~--------

. . .-------t--------~ ~

DATA OUT (;...R_EA_D.....;)_ _ _ _ _ _ _ _-----

...... tOHW ....
.'

Figure 3 - CPU Interface Timing Diagram
MX-COM, INC.

Page 239

MX203
SPECIFICATIONS
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not
suggested.
Supply voltage
Input voltage at any pin (ref Vss = OV)

-0.3t07.0V
-0.3 to (VDD + 0.3V)

Sinklsourcecurrent (supply pins)
(other pins)
Total device dissipation@TAMB25°C
Derating
Operating temperature range:
Storage temperature range:

±30mA
±20mA
800mWMax.

10mW/oC
-40°C to +85°C
-55°C to + 125°C

Operating Limits
All device characteristics are measured under the following conditions unless otherwise specified:
VDD = 5.0V, TAMB = 25°C. Xtal/Clock fo = 4.0 MHz. Audio level OdB ref: 775 mVrms.

ICharacteristics

See Note

Min.

Typ.

Max.

4.5

5.0

5.5

Unit

Static Values
Supply Voltage
Supply CurrentRX on, TX and Timer Disabled
RX on, TX Enabled, Timer Running

1.25
3.0

V
mA
mA

Interface Levels
CPU Data Port (Do - Os) InlOut
Logic "1"
Logic "0"
Output Logic "1" Source Current
Output Logic "0" Sink Current
Three State Output Leakage Current

8
3.5

9
10

Input Port (IlP o - liPs) & (R/W, Ao' A 1 , CS)
Logic "1"
Logic "0"
Output Port (O/P o - O/P 1 ), (IRQ)
Logic "1"
Logic "0"
Impedances
Input Port
Output Port
Audio Input
Audio Switch Sl "ON"
Audio Switch Sl "OFF"
Tx Tone Output (Enabled)
Tx Tone Output (Disabled)
Clock - 4 Output

Page 240

1.5
120.0
360.0
4.0

3.5

V
V
itA

ItA
ItA

1.5

V
V

1.0

V
V

2
4.0

0.1
11
11
11
14

0.1
1.0
1.0

1.0
15.0
1.0
2.0
10.0
1.0
10.0
3.0

50.0
5.0

10.0

MQ
kQ
MQ
kQ
MQ
kQ
MQ
kQ
MX-COM, INC.

MX203
See Note

ICharacteristics

Min.

IRQ Output (Logic "1")
IRQ Output (Logic "0")

Typ.

Max.

Unit

25.0
150.0

100.0
500.0

kQ

0

+1.0
+4.0
+0.3
+0.3

dB
Hz

Q

Encoder
Tone Output Level
Tone Frequency Accuracy "C"
Tone Frequency Accuracy "E"
Tone Frequency Accuracy "Z"
Tone Output Risetime
Total Harmonic Distortion

-1.0
-4.0
-0.3
-0.3

It>
It>
It>
1.0

3

0/0
0/0

5.0

ms
%

+7.0

dB

Decoder
Signallnpput Range
Decode BandwidthProbability> 0.995
Probability> 0.995
Probability > 0.995
Not Decode BandwidthProbability < 0.03
Probability < 0.03
Probability < 0.03
Noise Response Rate
Noise Response Rate
Noise Response Rate
Decode Response Time
Notone to Tone
Tone to Notone

"C"
"E"

"Z"
"C"
"E"

"Z"
"C"
" E"
"Z"

4

-28.0

5
5
5

±1.0
±1.0
±2.0

6
6
6
7,12
7,12
7,13
5

%
%
%
±3.0
±3.0
±4.5

%
%
%
Digits
Digits
Digits

Tp
53

ms
ms

1.0
1.0
1.0
20
33

25

Timing -(Figure3)
Address Set Up Time
ReadIWrite Set Up Time
Address Hold Time
ReadIWrite Recovery Time
Chip Select Access Time
Output Hold Time (Read)
Data Set Up Time (Write)
Data Hold Time (Write)
Power Up ResetTime

t AS
tRWS
tAH
t RWR
tACS
tOHR
t DSW
tDHW
TS

50
50
0
0
8
0
150
20
3.0

250
100

ns
ns
ns
ns
ns
ns
ns
ns
ms

Notes 1. No TX Tone load.
2.
3.
4.
5.
6.
7.

Sink/Source currents.s. 0.1 mA.
To 90% of nominal output, (from "F tone" to "not-F tone").
Sine or Square, a.c. coupled input.
With minimum tone period (Tp) for the tone set, SIN ratio OdS.
Under all conditions of input amplitude and SIN ratio, with maximum Tp specified for the tone set.
Gaussian Noise Input 6kHz band limited with a maximum input level corresponding to 1-digit code falsing
rate. (Random to random single characters.)
8. With each data line loaded as C = 50pf and R = 10ka.

9. Vau! = 4.6V
10. Vau! = O.4V
11. External connections on the Audio Output may alter these values.
12. Single digit response in a 40.0-hour period.
13. Single digit response in a 1.0-hour period.
14. An emitter follower output with an internal 1Oka pulldown resistor.
MX-COM, INC.

Page 241

I

MX· ~M, IN[!.

MX503

SEQUENTIAL TONE ENCODER

FEATURES

I

•
•
•
•
•

CMOS Low Power Requirements
No External Prefilters Needed
OdB Signal to Noise Performance
>30dB Dynamic Range
' .', <.'~,
25 ms Typical Respon.'1"im~}';>

• QuadradeCimalT~hllut "',., '• '"
• Automatic R!1I~i:l~he Tran~la.tion::':
,~

"."

APPLICATIONS:,
•
•
•
•
•

MX503QA: Metropage** - USA
MX503C: CCIR - International
MX503E: EEA - United Kingdom
MX503Z: ZVEI- West Germany
MX503ZS: Suppressed ZVEI

MX503*
16-pin side braize
MX503QA (USA), MX503C (CCIR),
MX503E (EEA), MX503Z (ZVEI) or
MX503ZS (SZVEI).

Description
The MX503 Sequential Tone Encoder accepts digital binary inputs to output audible tones that are compatible with
one of four international sequential tone signaling conventions. Fifteen individual frequencies are synthesized from an
external 560kHz ceramic resonator or quartz crystal. The output waveform is a sixteen step approximated sinewave output
VDD - V88 peak to peak amplitude with a nominal 1kQ source impedance. Total harmonic distortion without external filtering
is less than 10%. Unwanted harmonic signals are down at least 20dB from the fundamental over a 50 kHz bandwidth, and
down 44dB in the 5 kHz voice bandwidth.
Designed to perform the signal encoding function in the Hexadecimal Sequential Coding system, the MX503 permits
tone coded data, address codes and control commands to be transmitted manually through a keyboard or automatically from
stored programs. On-Chip timing provides an elapsed tone period (Tp) marker flag according to the tone duration standard
of the corresponding signal convention.
The MX503 Data Strobe/Latch input allows manual keyboard entry of data in real time. New data is entered by a 01 transition and latched by a 1-0 transition, so that a pulse from a keyswitch latches on a tone until the next key entry. In
quadradecimal operation, entry ofthe hexadecimal "F" terminates the transmission. For hexadecimal systems, the No Char
input yields a Notone output.
The MX503's low power consumption permits data origination from hand-held transceivers. Manual data entry
requires only a keyboard-to-binary encoder as supplemental hardware. To accomodate system rise time needs, the initial
output tone in a sequence may be delayed by using an external R-C time constant to control a Schmitt trigger provided on
the Output Enable input.

**Metropage is a trademark of Motorola, Inc.
Page 242

MX-COM, INC.

MX503
Output Enable - - - - - - - - - - - - - - - ,
Data Change - - - - - - - - - - - ,
Data {
Inputs ~;::::::::.::_-~...,

Auto R
CHAR

o----L_.._-J

Tp Output

Tone Output
Output Bias _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...J

Figure 1 - Internal Block Diagram

PIN

FUNCTION/DESCRIPTION

1

TONE OUTPUT: VDD-Vss peak-to -peak, 16 step pseudo sine-wave output, with nominal 1kQ source
impedance.

2

T p OUTPUT: This is the tone period expired output. It switches to logic "1" following a Data Strobe input after
tone interval (established by international convention) has elapsed.

3

OUTPUT BIAS: A logic "1" input here sets a Vor/2 bias on pin 1 (TONE OUTPUT).

4

OUTPUT ENABLE: A logic "1" input enables the TONE OUTPUT. The internal Schmitt trigger on this input
allows an external R-C time constant to create a transmission delay, if required (see Fig. Sand 6).

S

DATA STROBE/LATCH: This input should be left low, but strobed on data entry. A 0-1 transition strobes data
in and resets the T p OUTPUT. A 1-0 transition latches that data and tone output until the next 0-1 input.

6

AUTO REPEAT: A mode select input. A HIGH on this pin programs the MXS03 to automatically substitute
the repeat tone frequency if the same data character is entered twice in succession.

7

T p OUTPUT: For the MXS03QA only: The inverse of pin 2.
HEX/QUAD SELECT: For the MXS03C, E and Z, this is a mode select input. A HIGH on this pin programs the
MXS03 to transmit hexadecimal data (using 17 distincttones). A LOW on this pin programsquadradecimal data
transfer capacity (comprised of 14 data characters or symbols and a 1Sth system control tone).

8

Vss: Negative supply voltage.

9
10
11
12

Do:
D,:
D2 :
D3:

13

NO CHAR: Used only for hexadecimal operation ofthe MXS03. A logic "1" on this line along with a 1-0 transition
on the DATA STROBE/LATCH (pin S) results in a Notone output. The T p OUTPUT operates and the DC bias
of the TONE OUTPUT line (pin 1) is set at Vor/2. The DATA INPUT lines will be data entry and quadradecimal
operation.

14

CLOCK IN: This is the input to an internal inverter associated with the clock.

1S

CLOCK: This is the output from the internal inverter clock circuit.

16

Voo: Positive supply voltage.

MX-COM, INC.

Data input: Least significant bit.
Data input.
Data input.
Data input: Most significant bit.

Page 243

I

MX503

Tone Frequencies Output (in Hz)

I

MX503C

MX503E

MX503Z

MX503ZS

8

4

600
741
882
1023
1164
1305
1446
1587
1728
1869
2151
2435
2007
2295
459

1981
1124
1197
1275
1358
1446
1540
1640
1747
1860
2400
930
2247
991
2110

1981
1124
1197
1275
1358
1446
1540
1640
1747
1860
1055
930
2247
991
2110

2400
1060
1160
1270
1400
1530
1670
1830
2000
2200
2800
810
970
886
2600

2400
1060
1160
1270
1400
1530
1670
1830
2000
2200
886
810
740
680
970

NOTONE

NOTONE

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

NOTONE

NOTONE NOTONE

Code

Data Input

MX503QA

2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

1

Symbol

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
2
3
4
5
6
7
8
9

A
B

C
0

E
F

Table 1 - Quadradecimal Tone Table
1. By national or international convention, code A used in an address transmission is the Group Call flag,
and code E substitutes a sequentially repeated frequency.
2. Code F initiates and sometimes terminates each address transmission. (Refer to HSC System Overview
at the beginning of the HSC section.)
3. Tones for codes B, C and D are not specified by international convention.

NOTES:

Tone Frequencies Output (in Hz)

Code

Data Input

MX503C

MX503E

MX503Z

8

4

1981
1124
1197
1275
1358
1446
1540
1640
1747
1860
2400
930
2247
991
873
1055
2110

1981
1124
1197
1275
1358
1446
1540
1640
1747
1860
1055
930
2247
991
873

o

000

2110

2400
1060
1160
1270
1400
1530
1670
1830
2000
2200
2800
810
970
886
740
680
2600

NOTONE

NOTONE

NOTONE

2400

o

o
o
o
o
o
o
1
1
1
1
1
1
1
1

o
o

2

Symbol

o

1
0
1
0
1
0

2
3
4
5
6

1
1
1
000
o
0
1

8
9

o
1
1
1

o
o

0
1
1
0
0
1

1

1
1
1

1
1
0
0
1

0
1
0
1
0

1

1

1

REPEAT
DON'T CARE

1

7

A

B

C

o
E
F

X

NO CHAR

Table 2 - Hexadecirnal Tone Table

NOTES:

1. The tone frequency associated with code X is automatically substituted for the tone of any sequentially
repeated character, provided the Auto Repeat (pin 6) has been set HI.
2. NO CHAR operation blanks the data input lines and inhibits tone output; DC bias is maintained at VDd2,
Tp line outputs.
3. Tones for codes B, C, D and F are not specified by international convention.

Page 244

MX-COM, INC.

MX503

OUT PUT 81AS

J

OUTPUT EIlABLE . . /

n

41T4 ..

DATA IIilPUTS

TONE I

n

X

X

TONE 2

n

DATA CHANGE

n
X

TOIlE]

TONE 4

~

n

n

TONE OUTPUT

Figure 2 - Timing Diagram

(I)

I

(2)

VV\J
1 . 16-step pseudo-sinewave MX503 output
2. Same tone after simple filtering.

Figure 3 - Typical Waveform

10

See Note 4
20
30
40

2fo

dB
50

60
70

80

fo

II I I

1

I

I

.1. I

zvel TONE 5 - 1530 Hz

Figure 4 - Output Frequency Spectrum
MX-COM, INC.

Page 245

MX503
3 1--..----,-- Vss (-)

23

Voo

+5V)

> 1M
~

DO-D3 ~28

IN~t~

L-,../24

DATA STROBE
BEEP RESET
BEEP OUTPUT
HOLD
TRANSPOND MODE
CLOCK
CALL
CALL RESET
DATA FLAG

20

I

--+-I 1

----124

LOAD

PULSE
INCREMENT\
ADDRESS 10

;- - - - C2- 9
Vss

I

<>
R25-

I

.....

I

-_

NOTE
2
... --.

A3 13

OP2
OP1
OPO

A2 12
A1 11
AO 10

15
16
17
18

DPO
DP1
DP2
DP3

01

TP

Voo ----...---116
AUTO R.L 6

R1

I
I

I

I

1 NOTE 3

02 2
03 3
Q4 4

l:

16

---

<>> D1

I
I

C1
•
·:_VH
'j
•
- - 1- ____:
I

I

SS

I

OIP

t

5

~ 31 OIP ENABLE

BIAS 12hD
""3.----....
DATA
STROBE
11hD
""2.------I

MX503
:-. 14

'-TT-.'

0P3

: NOTE 1

I

2

,

14
13
12
11

----

I

: /' JIl-- :
I

h

CE
TX CONTROL '---~8- - f15
:=---....

(HM76LS03)

--~22

I

Vss

M 14

- -...... 7
--+-15
--+-I 6
--+-I 8
_---121

1M~

I

19

MX403

--~ 4

H LII-1---P-U"":R2=-t

560kHz
Resonator - Circuit

~~
TX ENABLE
220pF
+ - \ MC4081B

0.111F
Voo

~
~

8

10 D1

}

DATA
INPUTS

9 00
1 t - - - - - - - . TONE OUTPUT

HEX/OUADL 7
NO CHARL 13
Figure 5 - Circuit Connection Diagram (1)

Notes:
1) Include these components to provide a transmit delay.
2) Include these components to increase transmitted tone periods.
3) The system illustrated contains the local decode address (and transmit) code starting at memory address location 00001.
The transpond code is programmed starting from memory location 11001.

Page 246

MX-COM, INC.

MX503

I

4 BIT DATA>

8

9,10.11.12

16

2 I----..Tp

Data Strobe/Latch ~ 5
No CHAR~

MX503

13

7* I - - - - . . T p

1

Auto Repeat Select ~ 6

~Tone
.022~F

Hex/Quad Select ~ 7

15

14

4

3

1M

Ceramic
Resonator
Vernitron pin
FTF-V-559

R1

D1
5-65
.....-,.....-...... pF

47pF

47pF

--.
--.
Vss
Vss

i
--.

I

Enable with
Pre-TX Delay

C1

Vss

Vss

Figure 6 - Circuit Connection Diagram (2)

Notes:
1) Select values for R1 and C1 appropriate to the desired pre-transmit delay, if any.
2) Ceramic resonator sources are:
a. Raltron, part number POE-B560 kHz
b. Murata, part number BFB-560J
3) • Tp Output is available only on the MX503QA.

MX-COM, INC.

Page 247

MX503

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

OPERATING LIMITS

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following conditions
unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(ref V55 =OV)
Sink/Source Current (Total)
Operating Temperature
Storage Temperature

-0.3 to 7.0V
-0.3 V to Voo + 0.3 V
20mA
-30°C to +85°C
-55°C to +125°C

Xtal/Clock fo = 560 kHz
Characteristics are valid for all tones unless otherwise
stated.

Static Values
Supply Voltage (Voo)
Supply Current
Logic 1 Output Level (1 source = 0.1 mA)
Logic 0 Output Level (1 sink = 0.1 mA)
Logic 1 Input Level
Logic 0 Input Level

4.5
1
4.5

5.0
3

5.5
4

1.5

V
mA
V
V
V
V

10

Vp-p
kQ
%

0.5
3.5

Dynamic Values
Tone Output Level
Tone Source Impedance
THO

4.5

Tone Period Expired (T p OUTPUT, Pin 2) Time Table
Model

Signaling Convention

Tp

MX503QA
MX503C
MX503E
MX503Z1ZS

"Metropage"
CCIR
EEA
ZVEI/SZVEI

33ms±0.1%
100ms±0.1%
40ms±0.1%
70ms±0.1%

Frequency Accuracy @560kHz
Model

to :I:

Signaling Convention

to :I:

MX503QA
MX503C
MX503E
MX503Z1ZS

0.13%7Hz
0.3%
0.5%

"Metropage"
CCIR
EEA
ZVEI/ZVEI

0.1%
7Hz
0.3%
0.5%

-NOTE: The MX503QA's fo of ±0.13% provides a worst case transmit error of 2.85 Hz, well within
the ± 16 Hz "must accepf' bandwidth of the receiver.

Page24B

MX-COM, INC.

MX·~M,IN~.

MX803A

Advance Information

C·BUS
'COMPATIBLE

AUDIO SIGNALING PROCESSOR

DESCRIPTION
The MX803A, a member of the 08S800 IC family, is an audio signaling processor that
provides an in band tone signaling capability for LMR radio systems. Signaling systems
supported include SelCall (CCIR, EEA, ZVEI I, II, and III) 2-Tone SelCall and OTMF
encode.
Using a non-predictive decoder and versatile encoder gives the MX803A the capability
to work in any standard or non-standard tone system.
MX803AJ
24-pin COIP

The MX803A is a full-duplex device for use with Single Tone or Selective Call systems.
It consists of:

I

-A tone decoder with programmable NOTONE timer.
-Two individual tone encoders and a programmable TX period timer.
-An on-chip summing amplifier.
Under the control of the microcontroller (via C-8US, the 08S800 serial interface) the
MX803A will simultaneously encode and transmit 1 or 2 audio tones in the 208-3000Hz
range. It also will detect, decode, and indicate the frequency of any non-predicted input
tone in the frequency range of 313 to 6000Hz.
MX803ALH
24-pin PLCC

A general purpose logic input, interfacing directly with the Status Register, is provided.
This could be used as an auxiliary method of routing digital information to the

COMMAND DATA

•

REPLY DATA
AU!:lIN

E~~~~~~~~~~ ~8US

INTERFACE •

FREQUENCY

COUNTER

AND

CHIP SELECT

IFI'!mmJI!I'

CONTROL 1----'-.
LOGIC
SERIAL CLOCK
LOGIC INPUT

TONE 1 OUT
~

SUM

IN

SWITCHED SUM

OUT

SUM

OUT

CAlJCUES OUT

TONE 2 OUT

~AU~D~IO~~~~IN~_ _~~______-=======~

____________________~::::::~~SW~ITCH~UOUT~.

AUDIO
SWITCH

Figure 1 - MXB03A Audio Signaling Processor
MX-COM, INC.

Page 249

MX803A
DESCRIPTION ...
microcontroller via the C-8US. Output frequencies are produced from data loaded to the device. A programmable,
general purpose, on-chip timer sets the tone transmit periods. A Dual-Tone Multi-Frequency (DTMF) output is obtained
by combining the 2 independent output frequencies in the integral summing amplifier. This process can also be used
for level correction.
Tones produced by the MX803A can be used in the system as modulation calibration inputs and as "CUE" audio
indications to the operator. Received tones are measured and their frequency indicated to the microcontroller in the
form of a received data word. A poor quality or incoherent tone will indicate Notone.
The MX803A is a low-power 5-volt CMOS IC available in 24-pin CDIP and 24-lead plastic SMT packages.

PIN FUNCTION CHART

Xtal: The output of the on-Chip clock oscillator. External components are required at this output when
a Xtal is used. See Figure 2.

I

2

XtaVClock: The input to the on-Chip clock oscillator inverter. A Xtal or externally derived clock should
be connected here. See Figure 2.

3

Reply Data: This is the C-8US serial data output to the microcontroller. The transmission of Reply Data
bytes is synchronized to the Serial Clock under the control of the Chip Select input. This 3-state output
is held at high impedance when not sending data to the microcontroller. See Timing Diagrams.

4

;:Ielle(;Ll'",;:II;

The "C-8US" data loading control function. This input is provided by the microcontroller.
are initiated, completed or aborted by the CS signal. See Timing Diagrams.

5

serial data input from the microcontroller. Data is loaded to this device
last, synchronized to the Serial Clock. See Timing diagrams.

6

a general purpose logic input port which can be read

7

Interrupt Request (IRQ): The
by going to a logic "0." This is a "\0\1;'0_.",_.
1 interrupt port on the microcontroller.
and a high impedance when inactive.
conditions that cause interrupts are indicated in the

condition to the microcontroller
of up to 8 peripherals to
to logic "0" when active
to Voo' The

G/Purpose Timer Period Expired
RX Tone Measurement Complete
These interrupts are inactive during relevant powersave conditions and can be disabllet1;~
6 in the Control Register.

8

N/C: No internal connection.

9

NlC: No internal connection.

10

Audio Switch In: This is the input to the stand-alone on-chip Audio Switch. This function (Control
Register bit 7) may be used to break the system transmitter modulation path when it is required to provide
a CUE (beep) from Tone Generator 2 to the loudspeaker via the MX806A LMR Audio Processor.

11

Audio Switch Out: The output of the stand-alone on-chip Audio Switch.

12

Vss: Negative supply (GND).

Page 250

MX-COM, INC.

MX803A
PIN FUNCTION CHART

13

RX Audio In: The received audio tone signaling input. This input must be a.c. coupled and connected,
using external components, to the Signal Input Bias pin (See Figure 2).

14

Signal Input Bias: External components are required between this input and the RX Audio In pin (See
Figure 2).

15

VBIAS: The internal circuitry bias line, held at VDD/2. This pin should be decoupled to Vss by capacitor
C2 • See Figure 2.

16

Tone lOut: This is the Tone 1 Generator (2-/5-tone Selcall or DTMF 1) output. External gain and
coupling components will be required at this output when operating in a complete DBS 800 audio
installation. The frequency of this output is determined by writing to the TX Tone Generator 1 Register
(Table 5). See Figure 2.

17

Tone 2 Out: This is the Tone 2 Generator (2-/5-tone Selcall, CUES or DTMF 2) output. External gain
and coupling components will be required at this output when operating in a complete DBS 800 audio
installation. The frequency of this output is determined by writing to the TX Tone Generator 2 Register
(Table 5). See Figure 2.

18

CAUCU~$OutAn aUXill!i!1', selectable tone frequency output, providing a square wave CAlibration
signal fi'9rnthe:rone 2 Generator or a sine wave CUES (beep) signal from the Summing Amplifier. The
output mode (CAL or CUES} i$oSelected by bit 14 in the TX Tone Generator 2 Register (Table 5). In
a DBS 800 audio iristallation, this output should be connected to the Calibration Input of the MX806A
LMR Audio Processor. Whel'lTone Genetator2 is set to Notone, the CAL input is pulled to V BIAS; during
a powersave of Tone Generator 2 iUs held at VS$.

19

Sum In: The input to the on-chip SummingNnplifier. Thisamplifier~.available for combining Tone 1
and Tone 2 outputs (DTMF). Gain and coupiing compon~ntsshoLikjbe used at this input to provide
the required system gains. See Figures 2 and 3.::+\0:

20

Sum Out: The output of the on-Chip summing amplifier.
output. See Figures 2 and 3.

C~mbined ton~(1 and 2) areav~ilabl~ at this
0

00

21

Switched Sum Out: This is the combined tone output available for transmitter mOdufatiOn.111e switch
allows control of the MX803A final output to the MX806A. Control of this switch is by bit 4~ Control
Register. See Figures 2 and 3.;~

22

No internal connection.

23

Serial Clock: The "C-BUS" serial clock input. This clock, produced by the microcontroller, is used for
transfer timing of commands and data to and from the Audio Signaling Processor. See Timing diagrams.

24

Voo: Positive supply. A single +5 volt power supply is required. Levels and voltages within this Audio
Signaling Processor are dependent upon this supply.
NOTE: 1) Pins 8,9, and 22 may be connected to Vss to improve screening.
2) A glossary of abbreviations used in this document can be found on page 12.
C-BUS is MX-COM's proprietary standard for the transmission of commands and data between a
J.lController and DBS 800 ICs. It may be used with any J.lController, and can, if desired, take advantage
of hardware serial liD functions embodied into many types of J.lController. The C-BUS data rate is
determined solely by the J.lController.

MX-COM, INC.

Page 251

I

MX803A

Analog Application Information
SEE INSET

__

J:jXi'Ai...,..L.,

BELOW

AUDIO SWITC IN
AUDIO SW T H OUT

2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20

VDD

SERIAL CLOCK

MX803AJ19

TONE LEVEL

18
17

AND GAIN

COMPONENTS

Value
1.0MQ
2.0MQ
100kQ
82.0kQ
122kQ
100kQ
100kQ

Comgonent
Rl
R2
*R3
*R4
*Rs
*R6
*R7

Value
0.11lF
1.01lF
33.0pF*
33.0pF*
22.0pF
1.01lF
4.00MHz

Comgonent
Cl
C2
Ca
C4
Cs
C6
Xl

Tolerances: R = ± 10%, C = ±20%

*Note: For Xl> 5MHz, C3 = C. = 18pF

Figure 2 - External Components

NOTES
1. XtaVclock components described are recommended in
accordance with MX-COM's Application Note on Standard
and DBS 800 Crystal Oscillator Circuits (April 1990).
2. Resistors marked with an asterisk (*) are System
Components whose values are calculated to allow the
MX803A to operate with other DBS 800 microcircuits.
Figure 3 shows these components used in the system
signal paths.

3. R3 , R4 , R5 and C5 are tone mixing components calculated to provide a 3dB tone differential (twist) for use in a
DTMF configuration. Single tone output levels are set
independently or by the MX806A Modulator Drivers. R7
provides modulation level and matching for inputs to the
MX806A.
4. To improve screening and reduce noise levels around
the MX803A, pins 8, 9 and 22 should be connected to VS5'

r---"MA~T0U7

AUDIO SWITCH IN

ro
MX803A

TO MXBO/lA
SUM IN

0

~-.~~l~l~A~UD_'0-J~~O_~__~ffi

• ~~18~~~U+~g~
r-______________________________~~~~~~..
CAL

17

TONE

2~

CAUBRATION IN

~

l-

I

16
TONE lOUT

Figure 3 - Signal Switching
Page 252

MX-COM, INC.

MX803A

Controlling Protocol
Control of the MXS03A Audio Signaling Processor's operation is by communication between the !lControlier and
the MXS03A internal registers on the C-BUS using Address/Commands (AlCs) and appended instructions or data (see
Figure 7). The use and content of these instructions is detailed in the following pages.

MX803A Internal Registers
Control Register (30H) -- Write only, control and configuration of the MXS03A.
Status Register (31 H) -- Read only, reporting of device
functions.
RX Tone Frequency Register (32H) -- Read only, indicates frequency of the last received input.

TX Tone Generator 1 Register (34H) -- Write only, setting
the required output frequency from TX Tone Generator

1.
TX Tone Generator 2 Register (35H) -- Write only, setting
the required output frequency from TX Tone Generator

2.

Write only, setting of the RX

General Purpose Timer Register (36 H) -- Write only,
setting of a general purpose sequential time period.

The first byte of a loaded data sequence is always
recognized by the C-BUS as an Address/Command (AlC)
byte. Instruction and data transactions to and from this
device consist of an AlC byte followed by further instruc. tion/data or a status/data reply.

Instructions and data are loaded and transferred via
C-BUS in accordance with the timing information given in
Figures 7 and S.
Table 1 shows the list of AlC bytes relevant to the
MXS03A.

RX Notone Timer (33 H)
Notone period.

--

Address/Commands

General Reset
Write to Control Register
Read Status Register
Read RX Tone Frequency
Write to Notone Timer
Write to TX Tone Gen. 1
Write to TX Tone Gen. 2
Write to G/Purpose Timer

01
30
31
32
33
34
35
36

00000001
00110000
00110001
00110010
00110011
00110100
00110101
00110110

+ 1 byte instruction to Control Register
+ 1 byte reply from Status Register
+ 2 bytes reply from RX Tone Register
+ 1 byte instruction to Notone Register
+ 2 bytes instruction to TX Tone Gen. 1
+ 2 bytes instruction to TX Tone Gen. 2
+ 1 byte instruction to G/Purpose Timer

Table 1 - C-8US Address/Commands

o

1000

2000

3000

4000

5000

6000

5000

6000

1'''''''''1'''''''''1'''''''''1'''''''''1'''''''''1'I'''''''1
_.~
'"'~[;;;.;~"'.~~~~~.:.i.;~
....;:..; :.;.:. ;'._'.",,'r_t_1_·._an_d_2_...J1

L.-._
..... ......""
...

1250Hz

to 6000Hz •I;.!.:.]:~:':.';·
c"< .'"';;""~:"':: '

.

o

1000

2000

to 3000Hz

··(RJQExtended .Band .

r-~I~"·':::···• :j:::·;·,:::~;~:;(FOO~
.••~·.· ~.;. .·fiI';"'_~_·.'.;. B_an_d_ _~J
t(RX)MI~~1313HZ to

208Hz

625Hz

to 3000Hz

1500Hz
3000

4000

111111111111111111111111111I11111111111111111111111111111111

I

Frequency (Hz)

Figure 4 - MXB03A Frequencies
MX-COM, INC.

Page 253

I

MX803A

Controlling Protocol. ..
"Write to Control Register" - AlC 30H, followed by 1 byte of Command Data
Audio Switch
See the signal switching diagram (Figure 3) for application
examples.

General Purpose Timer
This should be set up before interrupts are enabled since
a General Reset command will set the timer period to OOH
- Oms (permanent interrupt).

MSB
Bit 7
1
0

Transmitted First
Audio Switch
Enable
Disable

6

G/Purpose Timer Interrupt
Enable
Disable

1
0

Oecoder Interrupts
Enable
Disable

5

Interrupt Enable Instructions

1
0

Status bits 0, 1 and 2 are produced regardless of the state
of these settings.

4

Bits 2 and 3 set the required frequency range. (See Figure
4, MX803A Frequencies.)

Summing Switch
Used to interrupt the MX803A drive to the MX806A Audio
Processor (see Figure 3, Signal Switching).

Summing Switch
Enable
Disable

1
0

Band Selection

3

2

0
0
1
1

0
1
0
1

Band Selection
High Band
Mid Band
Extended Band
Do not use this setting

1

Interrupt Designation
Decoder Interrupts:
Notone Timer and RX Tone Measurement
Transmitter Interrupt:
G/Purpose Timer Interrupt

Set to

0

"0"

0

Set to

0

"0"

Table 2 - Control Register

"Read Status Register" - AlC 31 H' followed by 1 byte of Reply Data
Interrupt Requests (IRQ)
MSB
Bit 7

o

Received First
Set to
"0"

6

Set to

5

Set to

0

"0"

4

Set to

0

"0"

3

Logic Input Status
"1 "

o

1
0

2
1

1
1

0
1

"0"

"0"

G/Purpose Timer Period
Expired
(Interrupt Generated)
Notone Timer Period
Expired
(Interrupt Generated)
RX Tone Measurement
Complete
(Interrupt Generated)

Table 3 - Status Register

Page 254

Interrupts on this device are available to draw the
attention of the microcontroller to a change in the
condition of the bit in the status register. However, bits
are set in the status register irrespective of the setting
of interrupt enable bits (Table 2) and these changes
may be recognized by polling the register.

General Purpose Timer Period
Set to a logic "1" when the timer period has expired.
Cleared to a logic "0" by:
a) Reading the Status Register, or
b) New G/Purpose Timer information, or
c) General Reset command

Notone Timer Period
Set to a logic "1" when the timer period has expired.
Cleared to a logic "0" by:
a) Reading the Status Register, or
b) New Notone Timer information, or
c) General Reset command

RX Tone Measurement
Set to a logic "1" when the RX Tone Measurement is
complete. Cleared to a logic "0" by:
a) Reading the Status Register, or
b) General Reset command

MX-COM, INC.

MX803A

Controlling Protocol ...
TX Tone Generator Regsiters 1 and 2
Each TX Tone Generator is controlled individually by writing a two-byte command to the relevant TX Tone Generator
Register. The format of this command word, which is different for each tone generator, is shown below with the
calculations required for tone frequency (fTONE) generation described in the following text.

"Write to TX Tone Generator 1 Register" - NC 34H , followed by 2 bytes of Command Data

Notone/
Enable

These 13 bits (0 to 12) are used to produce a binary number, designated "A."
"A" is used in the formulas below to set the TX Tone 1 frequency (fTONE 1).

Table 4 - TX Tone Generator 1
SETTING TX TONE GENERATOR 1
The binary number produced by bits 0 to 12 (MSB) is
designated "A." If "A" = all logic "0" TX Tone Generator 1
is Powersaved.
Bit 13 at logic "1" = Tone 1 Output at V B1AS (NOTONE)
"0" = Tone 1 Output Enabled
Bits 14 and 15 (MSB) must be logic "0."

SETTING TX TONE GENERATOR 2
The binary number produced by bits 0 to 12 (MSB) is
designated "B." If "B" = all logic "0" then TX Tone
Generator 2 is Powersaved.
Bit 13 at logic "1" = Tone 1 Output at V (NOTONE)
"0" = Tone 1 Output Enabled.
Bit 14 at logic "1" = Squarewave CAL Output.
"0" = Sinewave CUES Output.
Bit 15 (MSB) must be a logic "0."

"Write to TX Tone Generator 2 Register" - NC

Table 5 - TX Tone Generator 2
Notes: (1) Programming Tone Generator 2 to Notone will place the CAUCUES output at V S1AS via a 40kn internal
resistor.
(2) Programming Tone Generator 2 to Powersave will place the CAUCUES output at V ss.
(3) If both Tone Generators are Powersaved, the Input Amplifier is also Powersaved.
CALCULATIONS
As can be seen from Tables 4 and 5 (above), a binary number ("A" or "B" - bits 0 to 12) is loaded to the respective TX
Tone Generator. The formulas described below are used to produce the required output frequency.
Required TX Tone output frequency = fTONE 1 or 2
Xtal/clock frequency = fXTAL
Input Data Word (bits 0 to 12)
"A" or "8"

=

TX TONE FREQUENCIES
With reference to Tables 4 and 5 (above), while Input Data Words "A" or "8" can be programmed for frequencies outside
the stated limits of 208Hz and 3000Hz, any output frequencies obtained may not be within specified parameters (see
Specification page).

MX-COM, INC.

Page 255

I

MX803A

Controlling Protocol ...
"Read RX Tone Frequency Register" - AlC 32H, followed
Measurement of RX Signal Frequency SIN PUT
The measurements on this and the following page
are for a clock frequency of 4.032 MHz (see the bottom of
the page for a scaling formula for other crystal values).
The input audio signal, SINPUT' is measured in the
Frequency Counter over a specified measurement period
(9.125ms or 18.250ms).
The measuring function counts the number of complete input cycles occuring within the count period and then

1+--------Complete
Input
Cycle

by 2 bytes of Reply Data

the number of measuring clock cycles necessary to make
up the period.
When the count period of a successful decode is
complete, the RX Tone Measurement bit in the Status
Register and the Interrupt bit are set.
The RX Tone Frequency Register will now indicate
the signal frequency SINPUT in the form of 2 bytes (1 and 0)
as illustrated in Figure 6 below.

Measurement Period

Complete
Input
Cycle

Complete
Input
Cycle

FILTERED AUDIO INPUT SIGNAL

----------+1

Complete
Input
Cycle

Measuring
Clock
Cycles

Complete
Input
Cycle

\\\~

2 x ~NPUT

Figure 5 - Measurement of an RX Frequency
The Integer (N) - Byte 1
This is a binary number representing twice the number of complete input audio cycle periods. It is counted
during the specified measurement period, which is:
High Band Decode
Mid Band Decode
Extended Band Decode

9.125 ms = "f'
18.250 ms = "t"
9.125 ms ''f'

The Remainder (R) - Byte 0
This is a binary number representing the remainder
part, R, of twice the Input Signal Frequency. R "the
number of specified measuring-clock cycles" required to
complete the specified measurement period (See N). The
clock cycle frequencies are:

=

=

High Band Decode
Mid Band Decode
Extended Band Decode

See below for ''t'' and "I" scaling factors.

!~B~ ~smitted
15
'0'

t

14

Byte 1

Rrst

13

1

Byte 0

12 1 11 110 1 9

'0'

= 56.00 kHz = ''f'
= 28.00 kHz = ''f'
= 56.00 kHz = ''f'

I8

Integer (N)

cress

7

1 6

'0'

'0'

(Reply Data)
(LSB) - Transmitted Last

5141312111

0

Remainder (R)

RX Frequency Register

Figure 6 - Format of the RX Tone Frequency Register

fXTAL

Scaling Factors

The calculations above are for a Xtal of 4.032
MHz. The following formulas allow calculation of these
values using any Xtal value.

"f' scaled = t x (4.032)
fXTAL

"I" scaled = f x ( fXTAL )
4.032

Page 256

MX-COM, INC.

MX803A

Controlling Protocol ...
Frequency Measurement:

The following formulas show the derivation of the RX frequency SIN PUT from the

measured data bytes (N and R).

High Band Measurement
SINPUT - High Band
In the measurement period of 9.198ms, there are N
cycles at 2SINPUT and R clock cycles at 56.000kHz.
So

N

+

R

9.125ms

56000

2SINPUT
from which SINPUT

=

28000 x N
(511-R)

Hz

(1)

Nand R - High Band
The measurement period = 9.125ms
Clock frequency = 56.000kHz
The measured frequency = 2S INPUT Hz
In the measurement period there are:
2SINPUT x 9.125 x 10-3 cycles
Nh is the lower integer value of this decimal number:
N = INT (9.125 x 10-3 x 2SINPUT)
(4)
Rh is the lower integer value of this decimal number:
R = INT (9.125 x 10-3 - N) x 56000
(5)

I

2SINPUT

Mid Band Measurement
SINPUT - Mid Band
In the measurement period of 18.250ms, there are N
cycles at 2SINPUT and R clock cycles at 28.000kHz.
So

N

+

R

=

18.250ms

28000

2SINPUT

from which SINPUT =

14000 x N
(511-R)

Hz

(2)

Nand R - Mid Band
The measurement period = 18.250ms
Clock frequency = 28.000kHz
The measured frequency = 2SINPUTHz
In the measurement period there are:
2SINPUT x 18.250 x 10-3 cycles
Nm is the lower integer value of this decimal number:
N = INT (18.250 x 10-3 x 2SINPUT)
[6)
Rm is the lower integer value of this decimal number:
R INT (18.250 x 10-3 N) x 28000
(7)

=

2SINPUT

Extended Band Measurement
SINPUT - Extended Band
In the measurement period of 9.125ms, there are N
cycles at SINPUT and R clock cycles at 56.000kHz.
So

.l:!.
SINPUT

+

R

9.125ms

56000

from which SINPUT =

56000 x N
(511-R)

Hz

(3)

Nand R - Extended Band
The measurement period = 9.125ms
Clock frequency = 56.000kHz
The measured frequency = SIN PUT Hz
In the measurement period there are:
SINPUT x 9.125 x 10-3 cycles
N is the lower integer value of this decimal number:
N = INT (9.125 x 10-3 X SINPUT)
(8)
R is the lower integer value of this decimal number:
R = INT (9.125 x 10-3 56000
(9)

!iLx

SINPUT

MX-COM, INC.

Page 257

MX803A

Controlling Protocol ...
"Write to RX Notone Timer Register" - AlC 33H, followed by 1 byte of Command Data
MSB
7 6
o 0

4
0

1

0
High Band Mid Band
0 period (ms) 0
1
20 ±1%
40 ±1%
80 "
0
40 "
60 "
120 "
160 "
0
80 "
100 "
200 "
1
120 "
240 "
2BO"
1
140 "
160 "
320 "
0
180 "
1
360 "
200 "
400 "
0
220 "
440 "
240 "
480 "
0
260 "
1
520 "
560 "
0
280 "
300 "
600 "

3

2

o
o
o
o
o
o
o

o o
o o
o 1
o 1
o
o

0

1
0
0

0
0
0
0

Transmitted Bit 7 First
These 4 bits must be "0"

5
0

0
0

o

o

Operation of the RX Notone Timer
A NOTONE period is that period when no signal or a
consistently bad quality signal is received. The NOTONE
Timer is employed to indicate to the microcontroller that a
NOTONE situation has existed for a predetermined period.
The NOTONE Timer period is "primed" by writing to the
NOTONE Timer Register (33) using the instructions and
information (1 data byte) given in Table 6. This timer
register can be written-to and set in any mode of the
MXB03A except "Notone Timer Powersave." Priming the
timer sets the timing period; this period will not be allowed
to start until at least one frequency (tone) measurement
has been sucessfully completed.
The NOTONE Timer is a one-shot timer that is reset
only by successful tone measurements.
If the quality of the received signal drops to an unusable
level the NOTONE Timer will start its run-down. On
completion of this timer period, the NOTONE Timer Period
Expired bit in the Status Register and an Interrupt are set.
Upon detection of the Interrupt, the Status Register
should be read by the Controller to ascertain the source of
the Interrupt.
The NOTONE Timer Period Expired bit is cleared:
i By a read of the Status Register
ii New NOTONE Timer Information
iii General Reset Command

Table 6 - RX Notone Timer Settings

The timer is set to OOH by a General Reset command.

The following situations may be encountered by the
NOTONE Timer circuitry:
NO SIGNAL
The NOTONE Timer can only start its run down on
completion of a valid frequency measurement.

SIGNAL INPUT S'IRJT

'AX M!...ure
Complete' Set

NOTONE TIMER

Valid Tone

"AX

Jeasure

'RX M.!a.ure
Complete' Set

Complete' Set

I

TIming Period -Primed"

NO SIGNAL AFTER A VALID TONE MEASUREMENT
The timer will start to run down when the last RX Tone
Measurement complete bit is set. At the end of the
"primed" period the NOTONE Timer Period Expired bit in
the Status Register and the Interrupt will be set.
SIGNAL FADES AFTER A VALID TONE
MEASUREMENT
The timer will start to run down when the signal
becomes unreadable to the device. At the end of the
"primed" period the NOTONE Timer Period Expired bit in
the Status Register and the Interrupt will be set.

Signal Fades
'AX M!...sure
Complete' Set

NOTONE TIMER
Timing Period 'Prlmed~ I

Signal Lost and Recovered

1.l.aWMM\
I

"RX Measure
Complet.' Set

SIGNAL APPEARS AFTER THE TIMER HAS STARTED
If the frequency measurement is more than 75%
complete when the timer period expires, neither the
NOTONE bit nor the Interrupt will be set unless that
frequency measurement is subsequently aborted.

Page 258

TIming Period 'Not Reset'

'AX Nolone TImer Expired' and Set

"AX

~sure

I

·AX Measure

Complete' Set

Complete' Set

NOroNE TIMER
TIming Period

·Prim~

Timing Period "Reset"

'AX Nolon. TImer Expired' and Not Set

Figure 7 - Notone Timing

MX-COM, INC.

MX803A

Controlling Protocol ...
"Write to General Purpose Timer Register" - AlC 36H , followed by 1 byte of Command Data
MSB
7 6
0 0

5

4

0

0

3

2

1

0

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0

0
0
0
0

0
0
0

0
1
0

0
0

0

1
0
0

0
1
0
1
0

Transmitted Bit 7 First
These 4 bits must be "0"
High Band Mid Band
Reset Timer and Start Timing
period of 0
0
10ms±1% 20ms ±1%
40 "
20 "
30 "
60 "
40 "
80 "
50 "
100 "
120 "
60 "
70 "
140 "
80 "
160 "
90 "
180 "
100 "
200 "
110 "
220 "
120 "
240 "
130 "
260 "
140 "
280 "
150 "
300 "

Operation of the General Purpose Timer
This timer, which is not dedicated to any specific
function within the MX803A, can be used within the DBS
800 system to indicate time-elapsed periods of between
10-150ms in the High Band or 20-300ms in the Mid Band
to the microcontroller. Setting of the timer is by loading a
single byte data word via the C-BUS (see Table 7 at left)
to the MX803A through the Command Data line.
The timer will be reset and the run-down started on
completion of Timer Data Word loading.
When the programmed time period has expired, the
General Purpose Timer Expired bit (bit 2) in the Status
Register and the Interrupt are set.
The General Purpose Timer Expired bit is cleared:
(i) By a read of the Status Register, or
(ii) New G/P Timer information, or
(iii) General Reset Command.
When the programmed time period has expired, this timer
will reset, restart itself and continue sequencing until:
(i) New G/P Timer information is written, or
(ii) A General Reset Command is received.
The General Purpose Timer Expired bit and the interrupt
will remain set until cleared.
The timer is set to OOH (Oms) by a General Reset command.

Table 7 - General

Timer

Powersave
Various sections of the MX803A can be placed independently into a power-economical condition. Table 8
(below) gives a summary of these states available to the MX803A.

All bits = "0"

Tone Encoder 1

TX Tone Gen. 1 Reg. (34 H)

Tone Encoder 2
Input Amplifier

TX Tone Gen. 2 Reg. (35 H)
All bits = "0"
5
This action is automatic when both Tone Encoders are in the Powersave condition.

4

Table B - MXB03A Powersave Functions

Powersave Conditions
XtallClock and C-BUS: This circuitry is always active, on all DBS 800 ICs, under any depowered/powersaved
conditions

MX-COM, INC.

Page 259

I

MX803A

Controlling Protocol ...
Interrupt Requests
An Interrupt (IRQ), when enabled, is provided by the MX803A to indicate the following conditions to the JIControlier.

Enabled: By Control Register bit 5.

Enabled: By Control Register bit 6.

Enabled: By Control Register bit 5.

Set: When the preset Notone Flag is

Set: When the General Purpose

Set: When an RX Frequency Meas-

set.
Identified: By Status Register bit 1.
Cleared: By reading the Status
Register.

Timer has timed out.
Identified: By Status Register bit 2.
Cleared: By reading the Status
Register.

urement has been successfully
completed.
Identified: By Status Register bit
Cleared: By reading the Status
Register.

o.

On recognition of the "Read Status" Command byte, the interrupt output is cleared, the Status bits are transferred to
the JIControlier via the C-BUS Reply Data line and the internal Status bits are cleared.

Operational Recommendations
Following initial system power-up, a General Reset command should be sent.
Receive Sequence
1. Send Control Command for RX: Select Midband/
Highband and Digital Filter length.
2. Disable transmitters if desired by writing to Tone Frequency registers.
3. Prime the Notone timer by sending the required period
byte.
4. Enable/disable interrupts as desired.
5. When a valid tone has been detected by a successfully
completed measurement the Status Register is set to
"Tone Measurement Complete" and an interrupt is set to
the ~C.
6. The ~C examines the Status Register. If tone measurement is complete, it reads in the RX Tone Frequency in
the form N + R (Fig. 6).
7. RX Tone Measurement Complete interrupts are periodically sent to the ~C unless Notone is detected, in which
case a Notone Interrupt is sent.

Transmit Sequence
1. Set Tone Frequency Generators to Notone during the
transmitter initialization period.
2. Send Control Command for TX: Select Sum/Switched
Sum o/p and Audio Switch states.
3. Send General Purpose (GP) Timer information for the
Notone transmitter initialization period. This will initiate
the timer.
4. Enable/disable interrupts as desired.
5. ~C waits for "GP Timer Expired," reads the Status
Register to check interrupts due to timer, and resets the
Status Bit. If required, the ~C sends the next timer
period followed by the next tone(s} frequency information. A new timer period sent will reset the timer,
otherwise the timer is self-resetting.
6. The ~C monitors the interrupts and repeats 5 & 6 as
required.
7. After last loaded tone, ~C turns off Tone Generator(s}.

General Reset
Upon power-up the bits in the MX803A registers will be
random (either "0" or "1 "). A General Reset Command 01
will be required to reset all microcircuits on the C-BUS. t
has the following effect on the MX803A:

Glossary of Abbreviations
Below is a list of abbreviations used in this Data
Bulletin.

1}

Control Register
Status Register (bits 0, 1, 2)
Notone Timer
Tone Gen. 1 Reg. (2 bytes)
Tone Gen. 2 Reg. (2 bytes)
Gen. Purpose Reg.

Set
Set
Set
Set
Set
Set

as
as
as
as
as
as

OOH
OOH
OOH
OOOOH
OOOOH
OOH

fXTAL

XtallClock frequency.

SINPUT

Audio input signal.

fTONE

Tone frequency.

This sets the MX803A to Encoder High Band (625Hz to
3000Hz) with interrupts disabled and both timers set to
OOH·
Both timers should be set up before interrupts are enabled
to prevent initial, undesired interrupts.
Page 260

MX-COM, INC.

MX803A
Timing Information
Figure 8 shows timing parameters for two-way communication between the liControlier and the MX803A on the C-BUS.
tCSOFF

CHIP SELECT

I+-

-..j

1--- 1

~~---------------------------

_ _ _ _ _ _ _ _ _---'.

1-

-..j

COMMAND DATA
MSB

LSB
RRST DATA BYTE

ADDRESS/COMMAND
BYTE
REPLY DATA

~

MSB
Logic level Is not important

LSB
FIRST REPLY DATA BYTE

LAST REPLY DATA BYTE

Figure 8 - C-8US Timing

tesE
tesH
tesoFF
tNxT
tCK
tCH
tCL
tCDS
~DH

tRDS
tRDH
tHIZ

Chip Select Low to First Serial Clock Rising Edge
Last Serial Clock Rising Edge to Chip Select High
Chip Select High
Command Data Inter-Byte Time
Serial Clock Period
Decoder or Encoder Clock High
Decoder or Encoder Clock Low
Command Data Set-Up Time
Command Data Hold Time
Reply Data Set-Up Time
Reply Data Hold Time
Chip Select High to Reply Data High - Z

2.0
4.0
2.0
4.0
2.0
500
500
250
0
250
50.0
2.0

lis
lis
lis
lis
lis
ns
ns
ns
ns
ns
ns
lis

Notes: 1. Command Data is transmitted to the peripheral MSB (bit 7) first, LSB (bit 0) last. Reply Data
is read from the MX803A MSB (bit 7) first, LSB (bit 0) last.
2. Data is clocked into the MX803A and into the microcontroller on the rising Serial Clock edge.
3. Loaded data instructions are acted upon at the end of each individual, loaded byte.
4. To allow for differing microcontroller serial interface formats, the MX803A will work with either
polarity Serial Clock pulses.

:+-- tCK---+-:
SERIAL CLOCK
(from I'C)
1

-+-,

1

:-+-tcDH
1

t cDS .....:

=x=x=
1

:.... :

,,

COMMAND DATA
(from I'C)

1

t RDS
REPLY DATA
(10 I'C)

,
-+-'....
,

-+-,

:-+-tRDH

,,

=x~-x=
1

,

Figure 9 - Timing Relationships for C-8US Information Transfer
MX-COM, INC.

Page 261

I

MX803A

Specifications
Absolute Maximum Ratings

Operating Limits

Exceeding the maximum rating can result in
device damage. Operation of the device outside
the operating limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(Ref Vss OV)
Sink/source Current
(Supply pins)
(Other pins)
Total Device Dissipation

=

=5.0V

TAMB

-0.3V to (V DD + 0.3V)

=25°C

XtaVclock fXTAL

±30mA
±20mA

=4.0MHz
=

Audio level OdB ref. 308mVrms @ 1kHz
(60% deviation, FM)

800mW max.
10mW;oC
-40°C to +85°C
-55°C to + 125°C

@TAMB25°C
Derating

I

V DD

-0.3 to 7.0 V

Noise Bandwidth
Gaussian

Static Values
Supply Voltage
Supply Current
Decoder + Both Timers
Decoder, Both Timers + One TX only
All Functions Enabled

4.5

=5.0kHz Band-Limited

5.0

5.5

2.0
4.0
5.0

mA
mA
mA

20.0
20.0
1.0
10.0
5.0
10.0

MQ
MQ
kQ
kQ
kQ
kQ

Dynamic Values
Digital Interface
Input Logic "1"
Input Logic "0"
Output Logic "1" (IOH -120!lA)
Output Logic "0" (IOL 360!lA)
loUT Tristate (Logic "1" or "0")
Input Capacitance
lOX (VOUT 5V)

1.5

=
=

=

Overall Performances
RX - Decoding
High Band
Sensitivity
Tone Response Time
Good Signal
Tone-to-Noise Ratio OdB
Frequency
Band
Measurement Resolution
Measurement Accuracy

=

Page 262

-20.0
5,10
5,6,10
625

9

V

0.2
0.5

V
V
V
V
/!A
pF
/!A

dB
30.0
40.0

ms
ms

3000

Hz
%
%

MX-COM, INC.

MX803A

Mid-Band
Sensitivity
Tone Response Time
Good Signal
Tone-to-Noise Ratio", OdB
Frequency
Band
Measurement Resolution
Measurement Accuracy
Extended Band
Sensitivity
Tone Response Time
Good Signal
Frequency
Band
Measurement Resolution
MeasurerJlentAccuracy
TX - Encoders 1 and 2
Tone i=requency
Period (1 /fTONE) Error
Tone Amplitude
Total Harmonic Distortion
Rise Time to 90%
Fall Time to 10%
Frequency Change Time

Timers
General Purpose
Timing Period Range
High-Band
Mid-Band

-20.0
7,10
6,7,10

60.0
80.0

ms
ms

1500
0.2
0.5

Hz
%
%

-20.0

dB

313
9

dB

5,10
1250

20.0

ms

6000

Hz

0/0
0/0

0.2
0.5

9

208

3000
1.0
1.5
5.0

-1.5
3/fTONE

8

5.0
"

","

3/fTONE

JOO .....
;$

10.0
20.0

"

RX Notone
Timing Period Range
Hi-Band
Mid-Band
XtallClock Frequency (fXTAL)

20.0
40.0
4.0

.

Hz

As
dB

0/0
ms
ms
ms

oms
ms

300
600

ms
ms

6.0

MHz

Notes: 1. Device control pins; Serial Clock, Command Data, and CS.
2. Reply Data output.
3. Reply Data and IRQ outputs. _
4. Leakage current into the "Off" IRQ output.
5. Measurement period", 9.198ms.
6. Decode Probability '" 0.993.
7. Measurement period", 18.396ms.
8. When set to Powersave.
9. For a good input signal.
10. Inversely proportional to Xtal frequency, i.e. Spec* 4MHzlFXTAL. SO, for a 6MHz clock a 30ms tone
response time becomes 20ms.

MX-COM, INC.

Page 263

I

I

Page 264

MX-COM, INC.

Technical Specifications

Section 4:
Voice Processors
The following section contains specifications on several types of
filters, including AMPSfTACS/NMT, audio bandpass and audiol
sub-audio filters.

Device
MX316
MX336
MX346
MX366
MX386
MX806A
MX816
MX826
MX836

MX-COM, INC.

Description
NMT Audio Filter Array
Audio/Subaudio Filter Array
Cellular Audio Processing Array
Quad Filter Array (NAMPS/ETACS)
Quad Filter Array (NAMPSfTACS/AMPS/ACSB)
Audio Processor
NMT Audio Processor
AMPS/NAMPS Audio Processor
R2000 Audio Processor

I
Page
p.267
p.272
p.278
p.285
p. 291
p.295
p. 307
p. 319
p. 331

Page 265

I

Page 266

MX-COM, INC.

MX·~M,IN~.

MX316

NMT AUDIO FILTER ARRAY

FEATURES:
• 12th Order Lowpass Filter for S.A. T. * Rejection
.4 KHz S.A.T. Recovery Bandpass Filter
• Low Group Delay Distortion
• Single 5V CMOS Power Requirement

APPLICATIONS:

MX316J (COIP)
MX316P (POIP)
16 pins

• Nordic Mobile Telephone (NMT) 450/900 MHz
Mobile and Base Specifications

DESCRIPTION:
The MX316 is a low power CMOS switched capacitor filter array designed to meet Nordic
Mobile Telephone base and mobile specifications. As depicted in Figure 1, the device is
comprised of:
1) a 12th order, 3.4 KHz lowpass filter which meets NMT 450 and 900 MHz base and
mobile filter response specifications. Group delay distortion is minimized through this
filter.
2) a 6th order, 4 KHz narrow bandpass filter which meets NMT 450 and 900 MHz S.A.T.
recovery specifications.
3) an uncommitted amplifier, which may be used for a variety of applications, such as
pre-emphasis, de-emphasis, and buffering.

I
MX316lH
(24p PlCC)

An on-chip oscillator is driven by a 1 MHz crystal and provides all reference clocks for the
switched capacitor filters via a divider chain. Alternatively, an external clock may be used.
In standby mode, the chip enable feature Is used to disable the three circuit elements.
'Supervisory Audio Tone

XTALICLOCK
XTAL_---i
Voo

------I...

v,, _

..

f

SIGNA lI/P

BIAS

SIGNAL O/P

~

'"'-'
3.4kHz

..

12TH ORDER
lOWPASS FILTER

CHIP ENABLE

.~2
4kH~
BANDP ASS liP

BANDPASS O/P

~
± 200Hz
6TH ORDER
NARROW BANDPASS FILTER

BIAS I NPUT
INVERTING AMPLIFIER INPUT

Fig. 1 Internal Block Diagram

MX-COM, INC.

~

AMPLIFIER OUTPUT

'-

Page 267

MX316 PIN FUNCTION TABLE
PIN
MX316J
MX316P

I

FUNCTION

DESCRIPTION

Connect 1 MHz crystal or externally derived clock to this input. Drives
the on-chip inverting oscillator.

MX316lH

1

1

Xtal/Clock

2

2

Xtal

3

5

Chip Enable

Internally pulled to Vdd. A logic "0" applied to this pin will disable all
filters and the uncommitted amplifier (powersave).

4

6

Signal lIP

Inputto the lowpass filter. This input is internally biased and externally
a.c. coupled by C2.

5

7

SignalO/P

Lowpass filter output internally biased to Vdd/2.

6

8

V••

7

10

BP lIP

8

12

Vas

9

13

BP O/P

10

14

Bias

11

17

AmpO/P

,Uncommitted alJlplifier outpUt

12

18

Amp lIP

Unpoml:liittedampllfier inverting input

13

19

Bias lIP

Connect eXternally to "Bias" pin.

14

20

N/C

Internally connected. Leave open circuit.

15

23

N/C

Internally connected. Leave open circuit.

16

24

Vdd

Positive supply voltage

1 MHz crystal O/P. Inverting output of on-chip oscillator.

Negative supply voltage
Input to bandpass filter. Internally biased and externally a.c. coupled
byC3.
Negative supply voltage
Bandpass filter output. Internally biased to V &1:2.
,

Vd~ Bi,as

'

Pin. Externallydecoupled by>d (see fig. 2, note 1).

Note: MX316lH pin numbers 3,4,9,11,15,16,21, and 22 are not connected.

Page 268

MX-COM, INC.

Voo

-

XTAL/CLOCK

C~I~'$

111)

124) 16

t--

123) 15

NIC

I
I
I
I
I
I SEE
INOTE 1

QR'
2 12)

C,II

4

1201 14

3 151

SIGNALI~ 4 16)

Vss

-,J-

119) 13

5 17)

11BI 12

6 IB)

117) II

)

BIAS liP

I

AMP liP

=~c,
SEE
NOTE
2

AMP alP

BANDPASS liP

7 110)

114) 10

8 1121

113) 9

C,

1

I

NIC

MX316J

C,
SIGNAL
alP

Component

-7- C

XTAL

CHIP ENABLE

Component References
Typical

Unit Value

R,

1M

10%

C,
C,
C,
C,
C,
C,
CG

33p
0.1~

20%
20%

0.1~

20%

X,

lMHz

0.1~
0.1~

Min.

0.1~

SSp

20%
20%
20%
20%

BIAS
BANDPASS alP
NOTES:
ICs

1. Bias may be decoupled to Vss and

VDO using C~ C5 when input signals are
referenced to the bias pin. Far input
signals referenced to V ss, decouple Bias
to Vss using C5 onlV·

Vss

(MX316LH SHOWN IN BRACKETS. N/C

= NO

CONNECTlON)1
2.

Use

elY

when input signals are

referenced to Vss. to decouple V DD ·

Fig. 2

I

External Component Connections

SIMPLlFIEO AUDIO PROCESSING BLOCK DIAGRAM FOR NMT 900
BASE STATIONS AND MOBILES

I

4kHz

BASE

tfi'
MOBILE
STATION

NOTES:

1J, Not required in base station,
2). PreMemph and highpass (J1ter may be constructed using on-chip amplifier.
3), MX316 Lowpass Filter achieves both these functions.

~

MX316 (DEVICE A)

________ BASE STATION ONLY

FIG. 3: MX316 TYPICAL APPLICATION

MX-COM, INC.

Page 269

MX316 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not
implied.
-0.3V to 7.0V
Supply voltage
-0.3V to (Voo + 0.3V)
Input voltage at any pin (ref Vss = OV)
Output sink/source current (total)
20mA
MX316J
- 30°C to + 85°C
Operating temperature range:
MX316LH, MX316P
- 30°C to + 70°C
- 55°C to + 125°C
MX316J
Storage temperature range:
MX316LH, MX316P
- 40°C to + 85°C
Maximum device dissipation:
All versions 100mW

Operating Limits
All characteristics measured using the following parameters unless otherwise specified:
Voo = 5V, Tamb = 25°C, 0 = 1MHz, af0 = 0, fin = 1kHz.

Characteristics

I

See Note

Static Characteristics
Supply voltage
Supply current (Enabled)
Supply current (Disabled)
Input impedance (Filters & Amplifier)
Output impedance (Filters)
Output impedance (Amplifier open loop)
Output impedance (Amplifier closed loop)
Input logic '1'
Input logic '0'
Dynamic CharacteristiCS
Passband Rippll;)
(300-3000Hz) ,L.f'.
(4kHz ::!;55Hz)' BP
Cut off frequency
(-3dB)LP
(-6dB)BP
Attenuation
(3aOO-4200Hz) LP
«2000Hz,>6000Hz) BP
Group Delay Distortion (900-2100Hz) LP
(600-3000Hz) LP
Output Noise (rms)
LP
BP
Signal Input (rms)
LP
BP
Insertion loss (1 kHz) LP
(4kHz)" BP
Aliasing Frequency
Inverting Amplifier
Open loop gain
Gain bandwidth product

Min

Typ

Max

Unit

4.5

5
6.0

5.5

V
rnA

100

700

pA

1000
3

kn
kn
n

.000
3.5

,:'6'

n

...;;.

V
V

1.5

5
5
4,5
4,5
4,5
4,5

3000
4200
36
35

1
1
2
2

3450
46
37
80
450
1.6
1
0.4
0.4
0
0

50

3

Note: 1. Measured with input a.c. sic.
2. 'MAX' figure specified for nominal 3% distortion (3DdS SINAD).
'TYP' figure specified for minimum distortion (MAX SINAD).
3. Relative to 1kHz. 1DDmV rms input level.
4. Refer to Figs. 4 and 5.
5, Spf]cified over the full operating voltage and temperature range.
Page 270

30
1

2
2
3800
3800

dB
dB
Hz
Hz
dB
dB

f.LS

1.0
1.0

J.l..s
mV
mV
V
V
dB
dB
kHz

dB
MHz

MX-COM, INC.

}/ A

i-

)

+1
1
-3
-5

J.

1//

/

'/

~J~1(1

-9

~

13

~,

~

17 f----MX316 COMPARED WITH THE COMPOSITE NMT 900
BASE AND MOBILE Tx/Rx FILTER SPECIFICATIONS

~

;

21

I

~

25

/

dB

29

~

33

~

36
, 37

~

41

~

45

~
~

~
~

300

400

1000

800

600

2000

3000
4000
3400

6000

Hz

FIG. 4: TYPICAL MX316 LOWPASS FILTER RESPONSE

55-.-.jflooll--

FlECEIVER- TRANSMITTER COUPLING

0------

-6

-

-10

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

- -

-

-

MX316 COMPARED WITH THE NMT 900
MOBILE - BANDPASS SPECIFICATION

dB

-20

-

-

-

-

-25

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-30

1000

2000

3000 I 3400
3200

I 4000 I
3800 4200

5000

8000

Hz

MODULATION FREOUENCY

FIG.5: TYPICAL MX316 4kHz BANDPASS FILTER RESPONSE

MX-COM, INC.

Page 271

I

MX • ~M, IN!:!..

MX336

AUDIO/SUB-AUDIO FILTER ARRAY
FEATURES:
• High Order 300 Hz Highpass Filter
• Low Group Delay 2550 Hz Lowpass Filter
• On-chip 120-175 Hz Bandpass Filter
• Uncommitted Amplifier and Analog Switch
.50 dB Rejection Below 170 Hz
• Low Power CMOS
• Powersave Feature

MX336J (CDIP)
MX336P (PDIP)
22 pins

APPLICATIONS:
• R2000 Mobile Radio Trunking System
• Other Trunking Systems with Sub-Audible
Control Tones

DESCRIPTION:

I

The MX336 is a CMOS switched capacitor filter array used to process speech al1q
sub-audible data. As depicted in Figure 1, the device consists of:
..
1) a highpass audio filter with additional attenuation of sigQalsbeIOw170·Hz.
2) a lowpass audio filter for band-limiting speech, Gr<>tip·de!ay.:Characteristics ~e cOntrolled over the 900 to 2100 Hz range, al~irJgp~~e of 1200 Baud.MSi< data.
3) a narrow bandpass filter for sub-aul;iiodataprOcessing.
.
4) an uncommitted audio amp!ifi~
..... ... . "
5) a mute switch with e~~?f &mtrol

MX336LH
(24p PLCC)

HIGHPASS OUTPUT

300Hz

VDD
VSS
LOWPASS INPUT

LOWPASS OUTPUT

2550Hz

BANDPASS INPUT

BANDPASS OUTPUT

148Hz
CHIP ENABLE
NON-INVERTING AMP liP

AMPOIP

INVERTING AMP liP

AUDIOO/P

AUDIO liP

ANALOG

SWITCH CONTROL

Fig. 1 Internal Block Diagram

Page 272

MX-COM, INC

MX336 PIN FUNCTION TABLE

PIN
MX336P

FUNCTION/DESCRIPTION

MX336LH
XtallClock: This is the input to the clock oscillator inverter. 1MHz crystal input or
externally derived clock can be injected into this input.

1

2

2

Xtal: Output of clock oscillator inverter.

3

3

Chip Enable: This input has an internal 1MO pull up resistor to Vdd. When pulled to Vss
(logic '0') all internal amplifiers are disabled and current consumption is reduced.

4

4

No Connection.

5

5

HP liP: Input to highpass filter.

6

6&7

7

8

8

9 & 10

9

11

BP liP: Input to narrow bandpass filter.

10

12

V s .: Negative supply.

11

No Connection.
LP liP: Input to lowpass filter.
No Connection.

I

No Connection.

12

13

Amp Negative: Inverting input of uncommitted amplifier.

13

14

Amp POSitive:

14

15

Bias: This is the bias or analog ground pin and is set internally at Vdd/2. It should be
decoupled to Vss by an externally connected O.1fl-F (min) capacitor.

15

16

Amp Output: Output of uncommitted amplifier.

16

17

BP Output: Output of narrow bandpass filter.

17

18

LP Output: Output of lowpass filter.

18

19

HP Output: Output of highpass filter.

19

20

SW Output: Output of analog switch.

21

No connection.

22

SW Control: Control input of analog switch, internally pulled to Vdd by 1MO resistor with

20

Non~inverting

input of uncommitted amplifier.

switch in 'closed' position. When this input is pulled to VSS, the switch is in 'open' poSition.
21

23

SW Input: Input of analog switch.

22

24

Veld: Positive supply.

MX-COM, INC.

Page 273

MX336J

F

BEE NOTE a 'R2

124] 22

4 [4]

[20] 19 SWITCH Off'
[19] 18. HP OIP
118] 17 LPOff'

C50

[H] 16 'BP OIP
[16] 15 AMP 0If'

i,

6 [6]
7 IB]
B [9]

v..
Nle

9 [11]
10 [12]
11 [10]

[15] 14 BlAS
[14] 13 +VE AMP lIP
[13] 12 -VE AMP lIP

'::"

MX336LJI PIN NUMBERS ARE SHOWN IN BRACKETS;
PINS 4, 6, 7, 9, 10, & 21 ARE N/C ON THE IJj VERSION

(PRIME)

,

ITCH CONTROL

[22]20

5 [5]

V""

,

[23] 21
3 [3]

Component Value
R1
1Mf.l

1

:::;=

-,

~,

ill',

J

C6

R2
C1,C8
C2
SEE
C3
' NOTE 2
C4
,*,C7
C5
C6
C7
X1

*"

33pF
O.1J.lF
O.1J.lF
O.1J.lF
O.1J.lF
O.1J.lF
1x106 Hz

Tolerance
±10%
±10% (Note 3)
±20%
±20%
±20%
±20%
±20% (Note 1)
±20% (Note 1)
Notes 2 and 3
Selectable

Notes.:
1. Bias may be decoupled to V 88 and V00 using C5 and C6 when input signals are referenced to the. bias pin.
'
For input signals referenced to V88' decouple Bias to V88 using C6 only.
2. Use C1 when input signals are referenced to VS8 ' to decouple Voo.

I

3. Use R2 to assist decoupling of high frequency power supply noise (~2,:~1, typically 300!!s)
Figure 2 - External Component Connections

, 50 BAUD
: (MX406)

1200 BAUD
MSK MODEM (MX419j519)

,V'A.'U<;OV'I

300Hz

MX336
(DEVICE A)

3kHz

MX336
(OEVICE B)

Fig. 3 MX336 TYPICAL APPLICATION

Page 274

MX-COM, INC.

MX336 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not
implied.
Supply voltage
-0.3V to 7.0V
- 0.3V to (VDD + 0.3V)
Input voltage at any pin (ref VSS = OV)
Output sink/source current (total)
20mA
Operating temperature range:
MX336J
- 30°C to + 85°C
- 30°C to + 70°C
MX336LH, MX336P
Storage temperature range:
- 55°C to + 125°C
MX336J
- 40°C to + 85°C
MX336LH, MX336P

Operating Limits
All characteristics measured using the following parameters unless otherwise specified:
VDD = 5V, Tamb = 25°C,0 = 1MHz, ~f0 = 0, fin = 1kHz

Characteristics

See Note

Static Characteristics
Supply voltage
Supply current (Enabled)
Supply current (Disabled)
Input impedance (Filters & Amplifier)
Output impedance (Filters)
Output impedance (Amplifier open loop)
Output impedance (Amplifier closed loop)
Input logic '1'
Input logic '0'
Dynamic Characteristics
Passband Ripple
(300-2550Hz)
(12Q-175Hz)
(-3dB)
Cut-off Frequency
(-3dB)
(-6dB)
Attenuation
<170Hz
>9000Hz
<65Hz>290Hz
Group Delay Distortion{900-2100Hz)
(900-2100Hz)
(136-164Hz)
(rms)
Output Noise

Signal Input

(rms)

Insertion Loss

(1kHz)
(150Hz)

Aliasing Frequency

MX-COM, INC.

HP+LP
BP
HP
LP
BP
HP
LP
BP
LP
HP + LP
LP
HP
BP
LP
HP
BP
HP+LP
BP

Min

Typ

Max

4.5

5
3
500

5.5

100

2000
1.0
800
6

3.5
1.5

2
3

2
265
3800
110
43
40
30

3
4
4
4
5
5
5
-1
-1
50

180
55
47
40
30
200
100
1
1
4
0.4
0.4
0.4
0
0

60

1.0
1.0
1.0
+1
+1

Unit

V
mA
ILA
kn
kn
n
n
V
V

I

dB
dB
Hz
Hz
Hz
dB
dB
dB
ILs
ILs
ILS
mV
mV
mV
V
V
V
dB
dB
kHz

Page 275

Characteristics
Audio Switch
Output Noise
(rms)
Channel Resistance (on)
Channel Resistance (off)

See Note

Typ

Min

Max

4

Unit

mV

10

kfl
Mfl

50
200

dB

10

Uncommitted Amplifier
Open loop gain
Bandwidth

35

kHz

Notes: 1. Absolute ripple - see Fig. 4.
2. Absolute ripple - see Fig. 5.
3. Relative delay between 136 and 164Hz.
4. Measured with input a.c. sic.
5. 'MAX' figure specified for nominal 3% distortion (30dB)
'TYP' figure specified for minimum distortion (MAX SINAO).

+"

,i

0
-2

-6
-10

i· :

,'

:

:

:

-20

H-30

r-

,i

dB

;

T
-40

:

. !..: i

~+
j

-50

_L

:

.

::

:i

;

',

.

,i

-,
i
i i

! ;
.!

.l L

; i ;l
:: ' ;

·i . i
i i

l
200Hz

Fig. 4

Page 276

300Hz

1000Hz

, I

:
i
:

i:

. Ii

I

:1

i
2000Hz

3000Hz

FREQUENCY Hz

Typical audio bandpass filter frequency response versus R2000 filter specification.

MX-COM. INC.

!

:

! ! "

,

.1

0

II,;

:1

-2

:!i' :

:':

~!

I'

:'

ii:

.,

-3

":!

,i
:

:

'

:

:

.'

:

' ! .

:
-10

: i

:
:

: !

i
'. i

,
, ,: ' . ,,
:' i

dB

:

-20

i

:
t

i

,

'.!

,i

i

!
j

:
•

:,

II
I
H,

i'
••

,

it
!i

,

'ii'

.

, i

,

i

i

.

.

:

:=iUi;'

..

,i

1.-',
I.-'

,.

..
' j ::

~

:

.. '

i!

f-'

1
!

:

I

i

, !

!
:':!

ii!!

,

'

ii

:i

!

i

I' :i
it

I :

.

iii;

:: ."
!

:

i

U -'- -!
, !

! '
. i
!

! :

!

i

:

:::

:i

Y

I',"
i:
U

"

.,:1

:;.

;!

Iii·

":

:

1

.. 'Ii!
L
F

, i'

:
:

:

m:
.,"

;

':;.
:,

:.
I

:j

'

-30 ~

y

I

• : i

I 1L
L1
L i
••

50Hz

Fig. 5

65Hz

I

100Hz

V
i-'

III"
1

f

:

il

i
120Hz

:

175Hz

:;:

i'

,

ti:

il!iiii!Um:::Wm"

liii,,:HH"i'ilii •

300Hz

FREQUENCY Hz

Typical data bandpass filter frequency response versus R2000 filter specification.

MX-COM, INC.

Page 277

I

MX·~,IN~.

MX346

AUDIO PROCESSING ARRAY FOR CELLULAR TELEPHONES
FEATURES
•
•
•
•

.811 Okbit RX Wideband Data
Filter and Limiter
AMPS, TACS, NMT Audio + Data Processing
• Filters for Speech/MSK,
Speech, SAT and Data-Full Duplex Filtering
PreiDe-emphasis
Speech Bandpass and Deviation Limiter Filters
SAT 416kHz Bandpass Filters
• Input Gain Adjustment
MX346J (CDIP)
MX346P (PDIP)
24 pins

DESCRIPTION

I

The MX346 Audio Processing Array is a full-duplex Speech, SAT and Data
Processor designed to meet the composite specifications of AMPS (Advanced Mobile
Phone Service), TACS (Total Access Communication System), and NMT 450/900
(Nordic Mobile Telephone) cellular systems.
The RX Audio Path consists of a twelfth order lowpass filter, a fourth orderhighpass
filter, and Input gain adjustment and de-emphasis.
. .
The TX Audio Path consists of separate sixth and twelfth orq,er IOW~filters:a
fourth order highpass filter, a linear deviation limiter, and inputgain~jLi~m'li'ltrtand preemphasis.
' ..', .
..
MX346LH
The RX SAT and Data Path consists of a13kHz wlCieban

+

300 Hz

Out---.,

SAT &

3400 Hz

we UmIIBd
Data Channel
SAT _ OiJput

SAT AIIl> In

SlIT Tone

0u\>UI

_Band_
SAT " WB DIIfII Input
RX Amp

0uI---...,

DaIa Umllor

AX Audio Channel

RXAmpIn

RX Audo

RX Audio • IISK Input

t

VIlIl

'IBIAS

0u\lIIt

RX_(MSK)~

i

vss

i

XTA!.

~

i1f.iL

t

Sjstam SOled

t

~Enabl.

Figure 1 - External Components

Page 278

MX-COM, INC.

PIN FUN:CTION TABLE
Pin Function
1

Xtal/Clock: The input to the clock oscillator circuitry. The clock oscillator components are on chip and require
only a single 4MHz Xtal or clock pulse input. Clock oscillations are maintained in "powersave" (Chip Enable

= "0"). See Figure 2.
2

Xtal: The output of the clock oscillator circuitry. See Figure 2.

3

Chip Enable: The Chip Enable logic input. When at logic "0," the chip is put into the Powersave mode (with
a minimum amount of monitoring circuitry enabled) to reduce current consumption. A logic "1" will enable all
circuitry. This input operates in conjunction with the System Select Input; signal paths are as shown in Table

1.
4

System Select: A logic inputto select signal paths to either the AMPS/TACS or NMT specification. This input
operates in conjunction with the Chip Enable Input. Signal paths are shown in Table 1. Logic "1" = AMPS/
TACS, logic "0" = NMT.

5

TX Amp Out: The "gain output" pin of the Transmit Audio Channel input amplifier. This output, together with
the TX Amp In pin and external components, is used to set the required input gain/attenuation of this channel.
See Figures 1 and 2.

6

TX Amp In: The input pin to the Transmit Audio Channel. This inverting input, together with the TX Amp Out
pin and external components, is used to set the required input gain/attenuation of the channel. See Figures
1 and 2.

7

VBIAS: The output ofthe on-chip analog bias. circuitry, internally set to Vorl2, this pin requires decoupling to Vss
with a capacitor, Cr VBIAS is maintained during powersave (Chip Enable = "0".) See Figure 2 and Table 1.

8

SAT Amp In: The inputtothe Supervisory Audio Tone (SAT) and Wide band Data Channel. This inverting input,
together with the SAT Amp Out pin and external components, is used to set the required input gain/attenuation
of the channel. See· Figures 1 and 2.

9

SAT Amp Out: The "gain output" pin ofthe Supervisory Audio Tone (SAT) and Wide band Data Channel. This
pin, together with the SAT Amp In pin and external components, is used to set the required input gain/
attenuation of the channel. Special attention should be paid to the data circuit sensitivity (Specifications). See
Figures 1 and 2.

10

RX Amp Out: The "gain output" pin of the Receive Audio Channel. This pin, together with the RX Amp In pin
and external components, is used to set the required input gain/attenuation of the channel. See Figures 1 and

2.

MX-COM, INC.

Page 279

I

PIN FUNCTION TABLE
Pin Function
11

RX Amp In: The input to the Receive Audio Channel. This inverting input, together with the RX Amp Out pin
and external components, is used to set the required input gain/attenuation of the channel. See Figures 1 and

2.
12

Vss: Negative supply rail (GND).

13

SAT Tone Out: The filtered Supervisory Audio Tone (SAT) output.
AMPSITACS (-6dB) = 6kHz ± 200Hz. NMT (-6dB) = 4kHz ± 200Hz.

14

RX Wideband Data Out: The filtered, limited, wideband data output. This data channel produces a limited
rectangular wave output. Special attention should be given to the data circuit sensitivity (Specifications). See
Figures 1 and 2.

15

Limited SAT Tone Out: The filtered, limited Supervisory Audio Tone (SAT). SPeciatatt~nti~h should be given
to the data circuit sensitivity (Specifications). See Figures 1 and 2.

I

16

17

RX Audio Out: The bandpass filtered, de-emphasized

aU(ji(i~'Jt.Of the RX AudioChahn~.

RX Data Out: The de-emphasized, recl'liveddata.tlUtput. This data pr()cie!is ;';'ayrequlre filtering by low group
delay filters before demodulation .~y tnoderi'l$:suth as the MX4:)9;:MX429,or MX439.

18

TX Audio Out:

The.prO¢~ssed audio to the tra~mjSsiQninixing and modulation circuitry.
'~ ~",

19

TX LirniterGain:· the "gain outpuf' of thl:t1'X Uiniter Amplifier. This amplifier, using gain setting components,
is used to produce the correct sigriiillevei for application to the Deviation Limiter. For limiter levels refer to the
Specifications PCl.t!e. RecClmmended circuitry is shown in Figure 2.

20

TX Limiter In: The input to the TX Limiter Amplifier. This input should be connected by external components
to the TX Pre-emphasis Out pin as shown in Figure 2.

21

TX Pre-emphasis Out: The output of the on-Chip +6dB/octave pre-emphasis circuitry. This output should be
connected to the TX Limiter Amplifier by external components as shown in Figure 2.

22

TX Pre-emphasis In: The input to the on-chip transmitter pre-emphasis circuitry. This input would normally be
connected to the output of an external audio compressor circuit.

23

TX Bandpass Out: The output ofthe first stage of bandpass filtering in the Transmit Audio Channel. This output
will normally be connected to the input of an external audio compressor circuit. See Figures 1 and 2.

24

Page 280

VDD : Positive supply rail. A single +5 volt power supply is required.

MX-COM, INC.

External Components _

Voo
X1

XTAUCfock

•

XTAL

Chip Enable
System Select

R5

(;7

SAT & WB Data In

VaWl

AS

--ICB
C1.I.

----lC9

A1

24
23

2
3

22

4

21

5

20

6

19

MX346

Voo

TX Bandpass Out
Pre-emphasis In

-

TX Pre-emphasis Out

18

TX Audio Out

8

17

AX Data Out

9

16

AX Audio Out

7

I..C6

10

15

Limited SAT Tone Out

Pin

11

14

Wide Band Data Out

V

12

13 SAT Tone Out

I

Figure 2 - External Component Connections

Component Value Notes
R2 ' R" R4 ' Ra, R6 ' RSJ and Ral R7
Gain component combinations set the gains of the TX
Audio, SAT and WB Data, RX Audio and Limiter inputs.
Gain is calculated using the following formula and taking
into account the effect of the parallel feedback capacitor.
Gain =

Rle.dbaCk

It is recommended that all gain resistor values are
kept above 1OkQ.

C,
V SIAS decoupling capacitor = 1.0 IlF.
C2 , C4 , and Cs
Feedback capacitor values should be calculated (taking
into account gain resistors R" R2 , and Rs - Rs) to give a -3dB
point at approximately 15kHz for RX and TX Channels for
anti-alias filtering.

MX-COM, INC.

Ca
Feedback capacitor = 10.0pF

Cs
Power supply decoupling capacitor = 1.0 IlF.

C.
Input coupling capacitor = 0.1IlF.
C 7 , C.' and C'D
Input coupling capacitors = 1.0IlF.
Component Tolerances
Resistors ± 10%
Capacitors ± 20%
To maintain low current consumption, Output Buffers, anti-alias Clock Frequency Filters, and input internal
pull up or pulldown resistors are not included on-chip.
A noisy or badly regulated power supply can cause
instability and/or variance of selected gains.

Page 281

Application Information
The diagram in Figure 3 (below) demonstrates the audio and data functions performed by the MX346 Audio
Processing Array when employed in the audio stages of either an NMT or AMPS/TACS mobile application.

MX346 - TX Audio Channel

,

"
,
,------------------------------------,
,
416 kHz
6PoIe

1311Hz
4Pole

I

,
,;' :;·r~-:
I,

·r

,,

--'I

I

:
I

To Speaker
AX Audio

""~
__
-&13\
llHmphasia

CilOUils

t

EXpander

:

: MX346 - RX Audio Channel
Figure 3 - Example of MX346 Employed in the Audio Stages of a Typical NMT or AMPSffACS Mobile Operation
Table 1 (below) shows the signal and data path conditions relevant to the System Select and Chip Enable
inputs. Note that the oscillator circuitry and V BIAS line are active under all conditions.

FUNCTION
Oscillator

SIGNAL PATH
VB'AS

TXAudio

SAT Tone

we Data

RXAudio

RX Data

AMPSITACS
Chip Enable = "1"
Chip Enable = "0"

Enabled
Enabled

Enabled
Enabled

Enabled
Disabled

6kHz, Enabled
Disabled

Enabled
Enabled

Enabled
Disabled

Enabled
Disabled

,NMT
Chip Enable = "1"
Chip Enable = "0"

Enabled
Enabled

Enabled
Enabled

Enabled
Disabled

4kHz, Enabled
Disabled

Enabled
Disabled

Enabled
Disabled

Enabled
Enabled

Table 1 - Signal Path Selection
Page 282

MX-COM, INC.

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

OPERATING LIMITS

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(ref V55 = OV)
Sink/Source Current
(supply pins)
(other pins)
Total Device Dissipation
(@ 25°C)
Derating
Operating Temperature
Storage Temperature

-0.3 to 7.0 V
T AMB=25°C
-0.3 V to V DD + 0.3 V
Xtal/Clock fo = 4.0 MHz
±30mA
±20mA

Audio level OdB ref. = 300 mVrms

800mWmax.
10 mWrC
-40°C to +85°C
-55°C to + 125°C

Static Values
Supply Voltage(VDD)
Input Logic "1"
Input Logic "0"
Supply Current
- Enabled
- Disabled (Chip Enable = 0)
AMPSITACS
NMT

3
3
6

Impedance
Audio Amplifier Input
Audio Op-Amp Output
Audio Output
Digital Input
Digital Output

4.5
3.5

MX-COM, INC.

5.5
1.5

V
V
V

15.0

rnA

2.5
2.75

rnA
rnA

kQ

10.0
6.0
100

Dynamic Values
Xtal/Clock Frequency
Input Amplifier Gains

TX Audio Channel
Audio Input Level
Overall Gain
Deviation Limiter Levels
Bandpass Frequency Range (-3dB)
Pre-emphasis:
- Passband
- Response
- Gain at 1kHz
- Passband Deviation from Ideal
Channel Stopband Attenuation
~160 Hz
?5500 Hz
Output Noise

5.0

1,000
6.0

10.0
10.0

kQ

10.0

kQ

40.0

MHz
dB

1.0
4.0
3,400

mVrms
dB
V
Hz

4.0

300
1,7,8
3,5

8

-1.0
1.0
300

3,400

300
6.0
-1.0
-1.0

1.0
1.0
-20
-35
1.50

kQ
kQ

Hz
dBloct.
dB
dB
dB
dB
mVrms

Page 283

I

SAT and Wideband Data Channel
Input Level
Data Limiter Sensitivity
- Limited SAT Tone (4 & 6 kHz)
- Wideband Data

1
1,10

13kHz Lowpass Filter
- Passband (-3d B)
- Passband Gain (0 - 13kHz)
- Passband Ripple (0 - 13kHz)
- Stopband Attenuation (:225kHz)

10
20

mVrms
mVrms

15.0
1.0

kHz
dB
dB
dB

4,200

Hz
dB
'!:IB
dB
mVrms
kHz

2.0
30.0

4,9
3,800
11.5
2.0
-23.5

,25'~;.

2

-'

50.0

AMPSITACS 6kHz
- Passband Frequency Range (-6dB)
- Passband Gain
- Passband Ripple (6kHz ± 55Hz)
- Stopband Attenuation «4kHz, >8kHz)
- Output Noise

RX Data Channel
De-emphasis (Audio and Data)- Passband
- Response
- Gain at 1kHz
- Passband Deviation from Ideal

mVrms

-1.0

SAT Bandpass Filter
NMT 4kHz- Passband Frequency Range (-6dB)
- Passband Gain
- Passband Ripple (4kHz ± 55Hz)
- Stopband Attenuation «2kHz, >6kHz)
- Output Noise
- Aliasing Frequency

RX Audio Channel
"
Input Level ( RX Audip, RX Data)
Gain 1,7,8
"','
Passband Frequency Range (-3d B)
Output Noise"

300

9
,5;800,
',\ ...... :;:

"'~,,'

,.
12.0
2~Q,>
'<,-' ,

7,~

>,2 "

~"

'

',<",,''i'

300
+2.0

~:O

4
2

260

."",

'

to

~.,

~21

3,400
-6.0

-1.0
-1.0

dB
dB
dB
mVrms

mVrms
dB
3,400

1.5

300

Hz

6,200'
'

1.0
1.0

Hz
mVrms

Hz
dBloct.
dB
dB

Notes
1. With the Input Op-Amp gain(s) at unity.
2. Measured at the output with the channel input a.c. short circuit.
3. These levels are referenced to V DD'
4. Specified over the full operating voltage and temperature range.
5. Limiter Input at V BIAS'
6. To maintain low current consumption, buffers and clock filters are not included on-chip in series with outputs.
7. Input frequency is 1.0kHz.
8. With no pre-/de-emphasis effect.
9. Shows the SAT Tone Output specification in the selected mode.
10. The minimum level at the SAT Amp Input to produce a valid logic output.

Page 284

MX-COM, INC.

MX·~M,IN~.

MX366

Preliminary Information

QUAD FILTER ARRAY

Features
•
•
•
•
•

Pair of Independent Lowpass Filters
Pair of Audio Bandpass Filters (300-3000 Hz)
Input Gain Adjustments
Output Enable/Mute for Squelch Functions
Low Power CMOS

Applications

MX366P (PDIP)
18 Pins

• ACSB
• AMPSITACSIN-AMPS
• Cellular Phones

•

MX366DW
20-Pin SOIC

DESCRIPTION
The MX366 Quad Filter Array is comprised of 4
separate filter/gain blocks on a single IC as described
below:
1) A pair of 10th order 3.1 kHz lowpass filters.
2) A pair of 14th order channel bandpass filters (300-3000
Hz).
3) Op-amps that allow external components to set input
gains and pre- or de-emphasis.

BPF1 GAIN

4) A buffered low noise output with switching clock filter.
5) Output-enabled switching circuitry for squelch control.
This simple, comprehensive amplifier/filter combination eliminates the need for several separate ICs, and
therefore saves power and space.
The MX366 uses CMOS switched-capacitor filter
technology and requires a supply of 4.5 V to 5.5 V to
facilitate battery operation.

BPF1
OUT
LPF1 OUT

BIAS

Voo

~

XTAlfCLOCK

MX366

XTAL

Vss

VB1AS

~

BIAS

BIAS
LPF2 OUT

BPF2 IN
BPF2
OUT

Figure 1 - Simplified Signal Paths

MX-COM, INC.

Page 285

I

XTAUCLOCK
SEE INSET
BELOW

XTAL
1 GAIN

~

Vss

-

INSET

BPF1 OUT
N/C
LPF1 GAIN
LPF1 IN

19
18
17

2
3
4
5
6

MX366DW

16
15

14
13
12
11

7
8
9
10

LPF2 GAIN
LPF2 IN

XTALJCLOCK 1

Component

Rl
C1
C2
C5

. C6.
X1

Value
100kO
33pF
47pF ..

. ···l.OIXF
0.47!1F
See Table 1

Tolerances: R: ±10%, C: ±20%

Notes: 1. R2, R3, C3,A4:R5and C4 should be chosen with respect to the specific configuration
used.
2. Xtal circuitry shown is in accordance with MX-COM's Application Note on Crystal
Oscillators (page 354 of the 1991 Product Handbook).
3. Operation of any MX-COM IC without a Xtal or clock may cause damage to the
device. To minimize damage in the event of a X talldrive failure, a current limiting
device (resistor fast-reaction fuse) should be installed on the power supply line (VOO).

Figure 2 - Recommended External Components

TABLE 1 - MX366 CRYSTAL FREQUENCY/FILTER RELATIONSHIP
Crystal Frequency
4.433619 MHz
4.40 MHz
4.096 MHz
4.032 MHz
4.00 MHz
3.579545 MHz

Page 286

Bandpass Filter
300 -3000 Hz
298 -2977 Hz
277 -2772 Hz
272 - 2728 Hz
270 - 2706 Hz
242 - 2422 Hz

Lowpass Filter
3100 Hz
3076 Hz
2864 Hz
2819 Hz
2797 Hz
2503 Hz

MX-COM, INC.

PIN FUNCTION CHART

XtaUClock: A Xtal per Table 1 or an externally derived clock is injected at this pin.

2

2

3

3

LPF1 Out: This is the output of the LPF1 filter/gain block.

4

4

BPF1 Gain: This is the output of the BPF1 gain-adjusting amplifier. This output is used
with BPF1 In and external components.

5

5

BPF1 In: This is the input to the BPF1 filter/gain block.

6

6

V55: Negative supply (GNO).

7

7

BPF1 Out: This is the output of BPF1.

8

No Connect.

8

9

LPF1 Gain: This is the output of LPF1 gain-adjusting amplifier. This output is used with
LPF1 Input and external components.

9

10

LPF1 In: This is the input to the LPF1 filter/gain block.

10

11

LPF2 In: This is the input to the LPF2 filter/gain blOCk.

11

12

LPF2 Gain: This is the output of LPF2 gain-adjusting amplifier. This output is used with
LPF2 Input and external components.

13

No Connect.

12

14

BPF2 Out: This is the output of BPF2. It is under the control of the BPF2 Output
Enable Input.

13

15

BPF2 Output Enable: This controls the status of BPF2 Out. Logic 1 = Enable, Logic 0
= Muted. This pin has an internal 1MQ pullup resistor.

14

16

BPF2 In: This is the input to the BPF2 gain/filter block.

15

17

BPF2 Gain: This is the output of the BPF2 gain-adjusting amplifier. This output is used
with BPF2 In and external components.

16

18

Bias: This is the analog bias line at VDrJ2. It should be coupled to Vss by a 1.0 )IF
greater capacitor.

17

19

V DD : Positive supply. A Single +5 volt power supply is required. Levels and voltages
within this device are dependent upon this supply.

18

20

LPF2 Out: This is the output of LPF2.

MX-COM, INC.

This is the output of the clock oscillator inverter.

or

Page 287

I

-

The MX366 in a System

~

~

~

RX Audio Output

RX Channel

MX366
Mic. Gain

C)-1

To TX Modulator

TX Channel

SAT

~

8

~

~

Figure 3 - Example of the MX366 Used in the Audio Stages of a TAGS Operation

APPLICATION INFORMATION

Bandpass Section Performance
10

VDD
Input Level
Input Gain set to

Gain (dB)

o

5.0V
430mVrms
OdB

-10
-20
-30
-40

-50

Frequency (Hz)
~~~~~~~~~~~~~~~~~~~~~~~~~-.~~~~~~~

o

1000

2000

3000

4000

5000

6000

7000

8000

9000

Figure 4 - Example of the MX366 Bandpass (BPF1IBPF2) Frequency Response
When using the MX366 Quad Filter Array within a cellular system, the following should be considered:
(1) Each bandpass filter section has a frequency range of 300 Hz to 3000 Hz and a typical passband gain of
4.5 dB.
(2) Each lowpass filter section has a cut-off frequency of 3100 Hz and a typical passband gain of 0.5 dB
(3) BPF2 Output Enable has an enable/disable operating time as shown in "Specifications."

Lowpass Section Performance

10

VDD
Input Level
Input Gain set to

Gain (dB)

0

5.0V
430mVrms
OdB

-10
-20

-30
-40

-50

Frequency (Hz)
~4-~-L~~~~~~~L,~~~~~~L,-L~~~~~~~~-L~~~~

o

1000

2000

3000

4000

5000

6000

7000

8000

9000

Figure 5 - Example of the MX366 Lowpass (LPF1ILPF2) Frequency Response
MX-COM, INC.

Page 289

I

Specifications
Absolute Maximum Ratings

Operating Limits

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(Ref. 5S = OV)
Output sinK/source current
supply pins
other pins
Total Device Dissipation
@25°C
Derating
Operating Temperature
Storage Temperature

'!

I

-0.3V to (V DO + 0.3V)
±30mA
:t20mA

Clock = 4.433619 MHz

R'N
ROUT
Inverter D.C. Voltage Gain
Gain/Bandwidth Product
Dynamic Values
Input LogiC 1 Voltage
Input Logie 0 Voltage
;
Analog Signal tOpt1t !,evelll"
Lowpass Fi~r
Bandpass Finer
Analog Signal Output LeVels
Lowpass Filter
Bandpass Filter
Analog Output Noise
Bandpass Filter
Passband Frequencies
Passband Ripple
Low Frequency Roll-off «200 Hz)
High Frequency Attenuation at 3.4 kHz
Passband Gain
BPF2 Output Enable Time
BPF2 Output Disable Time
Lowpass Filter
Cut-off Frequency (-3d B)
Passband Ripple (300 to 3000 Hz)
Attenuation at 3.3 kHz
Attenuation at 3.6 kHz
Passband Gain
Distortion

Page 290

1.
2.
3.
4.

Audio Level OdB Ref. = 775 mVrms @ 1 kHz

800mWmax.
10mW/oC
-40°C to +85°C
-40°C to +85°C

Static Values
Supply Voltage
Supply Current
Input Impedance (Amplifiers)
Input Impedance (Digital)
Output Impedance (LP & BP Filters)
On-Chip Xtal Oscillator

NOTES:

Voo = 5.0V

-0.3 to 7.0 V

4.5
1.0
100

5.0
5.0
10,0

5~5

V
rnA
Mil

6.&

..

.kQ

; ;:a,()';<

kil

";;;1;0,0'"
~.

Mil

10:0
:i!Hl

kQ

VN
MHz

m.o

""

j;5;
-;:.

1.5

V
V

-30.0
-30.0

4.5
-1.5

dB
dB

-29.5
-26.0

5.0
2.5

dB
dB
dBp

3000

Hz
dB
dB/oct.
dB
dB
IlS
liS

2

-50.0

1,3
300
:t1.0
12
3.5

48.0
4.5
8.0
20.0

5.5

1,3

1,4

3100
:t1.0
30.0
45.0
0.5
2.0

Hz
dB
dB
dB
dB
%

Measured with Input Level -3.8 dB (500 mVrms).
Short circuit input, at any analog output and the measurement psophometrically weighted.
Op Amp gain 0 dB.
Measured in a 30kHz bandwidth.
MX-COM, INC.

MX·~,IN[!.

- ·X-38'6'
M
,:,

~

'..~

,

'.

'>

Prelimiriary Information

QUAD FILTER ARRAY

Features
e Pair of independent Lowpass Filters
• Pa'ir of Audio Bandpass Filters (300-3000 Hz)
• Input Gain Adjustments
• low Power CMOS

,Applications
eACSB

MX386DW
16-PinSOIC

• AMPSrrACS/N-AMPS
• C'ellular Phones

MX386P
16-pin PDIP

Description
The MX386 Quad Filter Array is comprised Of 4
separate filter/gain blocks on a single Ie as described
be'low:
1) A pair of 10th order 3. t kHz lowpass filters.
2) A pair of 14th order channel bandpass filters (300:.
3000 Hz).
3) Op-amps that alfow external components to set
input gains and pre- or de'-emphasis.

4) A buffered low noise output with switching clock
filter.
This Simple, comprehensive amplifier/filter combination eliminates the need for several separate ICs, and
therefore saves power and space.
The MX386 uses CMOS switched-capacitor filter
technology' and requires a supply of 4.5 V to 5.5 V to
facilitate battery operation.

LPF1 OUT,

B~¥

~"~ ~
BPF2 GAIN

1

LPF2 OUT

BPF2
OUT

Figure 1 - Simplified Signal Paths
MX-COM, INC.

Page 291

I

Voo

1
2
3
4
5
6
7
8

~

-

LPF1 GAIN
LPF1 IN

Component
C3
C4

16
15
14
13
12
11
10
9

MX386

VBIAS
BPF2 GAl
BPF2 IN
BPF2 OUT

R4

~

LPF2 GAIN
LPF2 IN

Value
1. R1, R2, C1, R3, R4 and C2 should be chosen with respect to the specific

Notes:

application.
2. Operation of any MX-COM IC without a clock may cause damage to the
device. To minimize damage in the event of a drive failure, the power supply
line (VDD) should have a current limiting device (resistor fast-reaction fuse)
installed.

Tolerances: R = ±10%, C = ±20%

Figure 2 - Recommended External Components

TABLE 1 - MX386 CLOCK FREQUENCY/FILTER
, .•... RELATIONSHIP.

I

Clock Frequency

Bandpass FiI.r

4.433619 MHz
4.40 MHz
4.096 MHz
4.032 MHz
4.00MHz.·

•••

300 - 3000Hz

~8-2977Hz

3.57~545MHi

.. ,

..

277 - 2772 Hz
272 - 27?8>Hi ,
270 ~276e.tli
242·c·a~22· Hz

Lowpass Filter
.3100 Hz
.. 3076 Hz
2864 Hz
2819 Hz
2797 Hz
2503 Hz

AX Audio Output

MX386
Mic. Gain

Q-!
1)( Channel

SAT

Figure 3 - Example of the MX386 in the Audio Stages of a TACS Operation
Page 292

MX-COM, INC.

PIN FUNCTION CHART

Clock: An externally derived clock (see Table 1) is injected at this pin.

2

2

LPF1 Out: This is the output of the LPF1 filter/gain block.

3

3

BPF1 Gain: This is the output of the BPF1 gain-adjusting amplifier. This output is used
with BPF1 In and external components.

4

4

BPF1 In: This is the input to the BPF1 filter/gain block.

5

5

Vss: Negative supply (GND).

6

6

BPF1 Out: This is the output of BPF1.

7

7

LPF1 Gain: This is the output of LPF1 gain-adjusting amplifier. This output is used with
LPF1 Input and external components.

8

8

LPF1 In: This is the input to the LPF1 filter/gain block.

9

9

LPF2 In: This is the input to the LPF2 filter/gain block.

10

10

LPF2 Gain: This is the output of LPF2 gain-adjusting amplifier. This output is used with
LPF2 Input and external components.

11

11

BPF2 Out: This is the output of BPF2.

12

12

BPF2 In: This is the input to the BPF2 gain/filter block.

13

13

BPF2 Gain: This is the output of the BPF2 gain-adjusting amplifier. This output is used
with BPF2 In and external components.

14

14

Bias: This is the analog bias line at V DJ2. It should be coupled to Vss by a 1.0 IlF or
greater capacitor.

15

15

Voo: Positive supply. A single +5 volt power supply is required. Levels and voltages
within this device are dependent upon this supply.

16

16

LPF2 Out: This is the output of LPF2.

MX-COM, INC.

Page 293

I

SPEelAC.ATtONS
Ab$o:lute Maximum Ratings

Oper,at.ing Limits

Exceeding the m.aximum rating can result in device
damage . .operation of the devi.ce outs.ide the operating
limits is notsuggested.
Supply Voltage
;Input Voltage at any pin
(Ref. V s =OV)
Qutput sinkTsource current
supply pins
other pins
Total Device Dissipation
@25°C
Derating
.operating Temperature
Storage Temperature

I

Page 294

V DD = 5.0 V

-0.3 to 7.0 V
-0.3V to (V DD + 0.3V)
±30mA
±20mA

Clock = 4.433619 MHz
Audio Level OdB Ref. = 500 mVrms @ 1 kHz

BOOmWmax.
10mW/oC
-30°C to +70°C
-40°C to +B5°C

Static Values
Supply Voltage
Supply Current
I nputlmpedance
Digital
Amplifiers
.output Impedance, LP & BP Filters
On-Chip Xtal OsciUator
HIN
ROUT
Inverter D.C. Voltage Gain
Gain/Bandwidth Product
Dynamic Values
Input Logic 1 Voltage
Input Logic 0 Voltage
Analog Signal 'Input Levets
.Lowpass Filter
Bandpass Filter
Analog Signal .output Levels
Lowpass Filter
Bandpass Filter
Analog .output Noise
Distortion
LowpassFilter
Cut-off Frequency (-3d B)
Passband Hipple (300 to 3000 Hz)
Attenuation at 3.3 kHz
Attenuation at 3.6 :kHz
Passband Gain
Bandpass Filter
Passband Frequencies
Passband Ripple
Low Frequency Roll-off «200 Hz)
High Frequency Attenuation at 3.4 kHz
Passband Gain
'NOTES:

AU devices were measured under the following
conditions unless otherwise noted.
.

..
4.5

5.0
5.0

100
1.0

10.0

,.",

'

5.5
:8.5

-

V
mA

kn
MQ
kQ

to.O
2.. 0

.. .,

MQ
kQ
VN
MHz

10.0
10.0
10.0

70% V DD
30% V DD
-26.0
-.26.0

B.5
2.5

dB
dB

-25.5
-22.0

9.0
6.5

dB
dB
dB
%

-42.0
2.0

2
1
1

3100
±1.0
30.0
45.0

Hz
dB
dB
dB
dB

0.5
1,3
300

3000
±1.0

12
3.5

4B.0
4.5

5.5

Hz
dB
dB/oct.
dB
dB

1. Measured with Input Level -3 dB.
2. Short circuit input, any analog output, in 30 kHz bandwidth.
3. Op Amp gain 0 dB.

MX-COM, INC.

MX·~M,IN~.

MX806A
c·.us

COMPATIBLE

AUDIO PROCESSOR
Description
The MX806A LMR audio processor is intended primarily to operate as the "Audio
Terminal" of radio systems using the DBS 800 Digitally-integrated Baseband Subsystem.
The MX806A half-duplex device has signal paths and level setting elements that
are configured and adjusted by digital information sent from the radio microcontroller
using C-BUS protocol. (C-BUS is the serial interface for all DBS 800 ICs.)

MX806AJ
24-pin CDIP

The signal path of the MX806A can be divided into three sections:

-Input Process
This stage has selectable TXlRX paths. Transmit voice signals pass through
microphone pre-amplifier, voltage controlled gain (VOGAD) and highpass filter
stages. Received audio is de-emphasized. This initial audio, after in-line gain
adjustment, may be switched to external audio processes (such as scrambling) or
to the internal Main Process stages.
- Main Process
Conditioning for the input or external process signals is completed in this stage. It
is comprised of pre-emphasis, high and lowpass switched-capacitor filters and a
deviation limiter.
-Mixing and Output Drives
Main audio for transmission is mixed with signaling and data from external sources
(other DBS 800 ICs) to provide the composite signal for the digitally adjustable
transmitter modulation drives. Received audio level is adjusted for output to
loudspeaker circuitry.

MX806ALH
24-lead PLCC

I
MX806ADW
24-pin SOIC

If selected, signal level stability and output accuracy of the MX806A is maintained by a voltage-controlled gain
system using selectable signal-level detectors. Signal levels can be dynamically controlled to provide "dynamic
compensation" for factors such as temperature drift, VCO non-linearity, etc.
MX806A audio output stages can be completely disabled - or the whole IC can be placed into powersave mode,
leaving only clock and C-BUS circuitry active.
The MX806A is a low-power 5V CMOS integrated circuit. It is available in 24-pin CDIP and SMT packages.
MOD
IN

1/

MAIN PROCESS

MODULATION
MIXER AMP

1/

TO EXTERNAL
EXTERNAL AUDIO
PROCESS IN
AUDIO PROCESSES

'

_ _ OOrrIIOI

Figure 1 - MXB06A Audio Processor
MX-COM, INC.

Page 295

MX806A

PIN FUNCTION CHART
Xtal: The output of the 4.032 MHz on-chip clock oscillator. External components are required
at this output when a Xtal is used. See Figure 2.

I

2

XtaVClock: The input to the on-chip 4.032 MHz clock oscillator inverter. A 4.032 MHz Xtal or
externally derived clock should be connected here. See Figure 2. This clock provides timing for
on-chip elements, filters, etc.

3

Serial Clock: The "C-8US" serial data loading clock input. This clock, produced by the
microcontroller, is used for transfer timing of Command Data to the Audio Processor. See
Timing diagrams.

4

Command Data: The "C-8US" serial data input from the microcontroller. Command Data is
loaded to this device in 8-bit bytes, MS8 (87) first and LS8 (80) last, synchronized to the Serial
Clock. The Command/Data instruction is acted upon at the end of loading the whole instruction.
Command information is detailed in Tables 1 - 5. See Timing diagrams.

5

Chip Select (CS): The "C-8US" data loading control function. This input is provided by the
microcontroller. Command Data transfer sequences are initiated, completed or aborted by the
CS signal. See Timing Diagrams.

6

VOGAD Out: The error-voltage output of the selected VOGAD sensor. This output, with
external attack and decay setting components, should be connected as in Figures 2 and 3, to
the VOGAD In pin.

7

RX Audio In: The audio input to the MX806A from the radio receiver's demodulator circuits.
This input, which requires a.c. coupling with capacitor C 12 , is selected via a Control Command
bit.

8

VOGAD In: The gain control signal from the selected VOGAD sensor (VOGAD Out) to the Input
Process voltage-controlled amplifier. The required sensor is selected via a Mode Command.
The choice of two sensors enables gain control from either the Input Process or an External
Process. External attack and decay setting components should be applied as recommended
in Figures 2 and 3.

9

V BIAS: The output of the on-chip analog circuitry bias system, held internally at V 0012. This pin
should be decoupled to V55 by capacitor CIO' See Figure 2.

10

Mic In (+): The non-inverting input to the microphone Op-Amp. This input requires external
components for Op-Amp gain/attenuation setting as shown in Figure 2.

11

Mic In (-): The inverting input to the microphone Op-Amp. This input requires external
components for Op-Amp gain/attenuation setting as shown in Figure 2.

12

Vss: Negative supply (GND).

Page 296

MX-COM, INC.

MX806A

PIN FUNCTION CHART

13

Mic Out: The output of the Microphone Op-Amp, used with the Mic In (-) input to provide the
required gain/attenuation using external components as shown in Figure 2. The external
components shown are to assist in the use of this amplifier with either inverting or non-inverting
inputs. During Powersave (Volume Command) this output is placed at V ss'

14

Processed Audio In: The input to the device from such external audio processes as Voice
Store and Retrieve or Frequency Domain Scrambling. This input, which requires a.c. coupling
with capacitor C 13 , is selected by a Mode Command bit.

15

External Audio Process: The buffered output of the Input Processing Stage. Its purpose is to
further external audio processing stages prior to re-introduction at the Processed Audio In pin.

16

Calibration Input: A unique audio input to be used for dynamic balancing of the modulator
drives and for measuring Deviation Limiter levels. A CUE (beep) input from the MX803 Audio
Tone Processor can be entered on this line. This audio input must be externally biased. It is
selected via a Mode Command bit.

17

Main Process Out: The output of the Main Process stage. This output should be mixed with
any additional system audio inputs (Audio, Sub-Audio Signaling, MSK) in the on-chip Modulation Summing Amplifier. External components shown in Figure 2 should be used as required.

18

Sum In:

19

Sum Out:

The input and output terminals of the on-chip Modulation Summing Amplifier.
External components are required for input signals and gain/attenuation setting
as shown in Figure 2. For single-signal, no-gain requirements, Main Process
Out may be linked directly to Modulation In.

20

Modulation In: The final, composite modulating signal to VCO (Mod 1) and Reference (Mod
2) Output Drives.

21

Audio Output: The processed audio signal output intended as a received audio (volume)
output. Though normally used in the RX mode, operation in TX is permitted. The output level
of this attenuator is controlled via a Volume Set command. During Powersave this output is
placed at Vss.

22

Modulation 1 Drive: The drive to the radio modulator Voltage Controlled Oscillator (VCO) from
the composite audio summing stage.

23

Modulation 2 Drive: The drive to the radio modulator Reference Oscillator from the composite
audio summing stage.
NOTE: These VCO output attenuators are individually adjustable using the Modulator Level
command. During Powersave these outputs are placed at V ss.

24

V DO: Positive supply. A single, stable +5 volt supply is required. Levels and voltages within this
Audio Processor are dependent upon this supply.

MX-COM, INC.

Page 297

I

MX806A

Analog Application Information
v""

...
SEE fNSEJ" f

----4'
AS

AU

IN

1
2
3
4
5
6
7
8
9

24
23

v

22
21

MX806AJ

13

A12

SEE INSET 2

Ala

INSET

t

INSET 2

I
C3

Value
10kn
10kn
20kn
20kn
10kn
2.2MU
100kn
100kO
100kn

100kn
100kn
2.2MU
470kn
.47j.lF
.47j.lF
270pF
270pF
0.1j.lF

Tolerance: R=± 10%. C=±20%.

Figure 2 - Recommended External Components

Notes:
Input Op-Amp gain/attenuation components (voltage gain
= 6.0dB) are shown in Inset 1 in a differential configuration
to demonstrate the versatility of this input. Components for
a single (+ or -) input may be used.
Resistor values R7 to R" (summation components) are
dependent upon application and configuration requirements.

33pF
5-65pF
1.0j.lF
1.0j.lF
1.0j.lF
22pF
0.1j.lF
0.01j.lF
O.Q1j.lF
4.0MHz

Xtal circuit capacitors Cs (CD) and C7 (C G) shown in Inset
2 are recommended in accordance with MX-COM's Crystal Oscillator Application Note, March 1990. Circuit drive
and drain resistors are incorporated on-chip. Operation of
any MX-COM IC without a Xtal or clock input may cause
device damage. To minimize damage in the event of a
Xtal/drive failure, you should install a current limiting
device (resistor or fast-reaction fuse) on the power input

(VDJ·

Page 298

MX-COM, INC.

MX806A

Analog Application Information
EXTERNAL INTEGRATION COMPONENTS
~r-----------~.Nv--t~~~---------,
MIC. OUT

TX

DRIVES

AX

DRIVE
To EXTERNAL AUDIO PROCESSES

PROCESSED AUDIO IN

Figure 3 - VOGAD Sensors and Timing Components (from Fig. 5)
The overall Gain Control system of the MX806A consists
of 2 selectable signal peak detectors whose output is fed
via external integrating components to adjust the gain of
the Voltage Controlled Amplifier positioned in the TX Input
Process Path. The transmit input signal is presented to
Peak Detector 1 or 2. The Peak Detectors are enabled
individually by a Mode command. When the input signal
exceeds the peak-to-peak threshold of the detector, a 5
volt level is produced at the VOGAD Out pin. This level
remains for as long as the signal exceeds the threshold.

The integrated level to the VOGAD In pin causes the
Voltage Controlled Amplifier gain to be reduced. As can be
seen from Figures 3 and 5, Peak Detector 1 allows control
of the audio level to the external audio process and Peak
Dector 2 allows control of transmit deviation levels.
VOGAD attack and decay times are set using the external
components shown in Figures 2 and 3. They are calculated as described below.

VOGAD Components Calculations - Figures 2 and 5
Provided Rs » 1.0kn and Rs

= R12 »

Rs
Then

= Rs x Cs
Decay Time (T D) = Rs x C s

Attack Time (TA)

2

Suggested Calibration Methods
To effectively null all internal IC tolerances, the following initial calibration routine is suggested:
TX Calibration: From Mic. In to Modulator Drives Out
Disable Peak Detectors (Mode Command).
Set Transmitter Drives to OdB (Mod. Levels Set).
Pre-emphasis may be employed as required (Control Command).
Set Input Level Amp to OdB (Control Command).
1) Mic. In = 250 mVrms at 1kHz. Set Process Gain Amp for output of 1440 mV p-p (100% deviation).
2) With Process Gain Amp set as 1 and with Mic. In = 25 mVrms at 1 kHz, set the Input Level Amp for an output
level of 308 mVrms (60% deviation).
RX Calibration: From RX Audio In to Audio Out
Set Audio Output Drive to OdB (Volume Set}
Leave Process Gain Amp set as 1 (see above).
3) With an RX Audio In level of between 154 mVrms and 308 mVrms (see Specifications) at 1 kHz, setthe Input
Level Amp for an output level of 308 mVrms.
MX-COM, INC.

Page 299

I

-

~
~

8

..

s::

~

.

~

EXTERNAL DATA , . - - - - - - - ,
RADIO
AND
CLUSTER
MICROCONTROLLER

Transmitter

MX802
," AUDIO

I DATA/VOICE

,>~ STORE AND

RETRIEVE
CODEC

MX803A

MX805A

MX809

AUDIO
SIGNALING
PROCESSOR

SUB-AUDIO
SIGNALING
PROCESSOR

MSK
MODEM

XTAL

XTAL

TX TONE AUDIO SIGNALS AND CUE

Receiver

l

~.

1200 BAUD MSK SIGNALS

I TX

SUB-AUDIO SIGNALS

! RX (AUDIO, MSK, TONE, SUB-AUDIO) S I G N A L S !

Figure 4 - MXB06A Interfaced with Other DBSBOO Elements

~

8
.s:
~

!

~

8
_s:
~

p

----------------------------------------------------------:

~

:
I VOGAO
I
IN
I1 ____ -

MIC. OUT

1

1

EXTERNAL INTEGRATION
COMPONENTS

I

VOGAO
OUT

I
I
I

~----------------------------------------------------- ---,

I
I
I

EXTERNAL SIGNAL MIXING

I
I

I

EXTERNAL

SIGNAl.,OATA
INPUTS

I

:

Gain Set By
External Components

r--t&I-#M3
H.P.F.

HI - LO PEAK
DETECTOR

I
I
I

I
I
I

MAIN PROCESS
OUT

SUM
IN

SUM
OUT

MODULATION
IN

+VE & -VE PEAKS

.V"""

TX Ll
OdB 0 1kHz

#C6 (ENABLE)

AX

DE·EMPHASIS

INPUT PROCESS

H.P.F.

MAIN PROCESS
OdB to -6.2dB

VBIAS

#M7-1&!1+'- - - - ,

OUTPUT DRIVES
)(TAL/CLOCK

#M3

!

me

#Vl}.4

PROCESS
L.P.F.

10dB CD 1kHz

PRE-EMPHASIS

Vss

EXTERNAL
COMPONENT

OdB

BUFFER
AMP

SERIAL CLOCK
COMMAND DATA
CHIP SELECT

:--------1

C-BUS INTERFACE
AND
CONTROL LOGIC

I

#
#
EXTERNAL AUDIO
PROCESSES

~
......

OdS to -48.OdB

KEY
PROCESSED
AUDIO IN
CALIBRATION
INPUT

# =
C =
M =
OdB

Controlling Logic Bit
DO=MOD2
Control Command
D1 = MOD 1
Mode Command
V = Volume Set
level = 308 mVrms (60% deviation)

s::

~

<

Figure 5 - LMR Audio Processor Explanatory Block Diagram

-

~
0')

»

MX806A

Controlling Protocol
Control of the functions and levels within the MX806A LMR Audio Processor is by a group of Address/
Commands and appended data instructions from the system microcontroller. The use of these instructions is
detailed in the following paragraphs and tables.

General Reset
Control Command
Mode Command
Mod. Levels Set
Volume Set

01
10
11
12
13

o0

0
000
000
000
000

0 0 0 0
1 000
1 000
1 001
1 001

1
0
0
1

2
3

1 byte
1 byte
2 bytes
1 byte

+
+

1

+

+

4

5

Table 1 - C-8US Address/Commands
In "C-BUS" protocol the MX806A is allocated Address/Command values 10H to 13H• C-BUS Command,
Mode, Modulation and Volume assignments and data
requirements are given in Table 1 and illustrated in Figure

5.

I

Commands and Data are only to be loaded in the
group configurations detailed since the "C-BUS" interface
recognizes the first byte after Chip Select (logic"O") as an
Address/Command.
Function or Level control data, which is detailed in
Tables 2, 3,4, and 5, is acted upon at the end of the loaded
instruction.

Loaded as OOH

Volume Set

Loaded as OOH

(MSB)
Bit 7

Drive Source

0
1

Disabled
Enabled

0
1

Signals
Calibration

6

Modulation Drives

0
1

Disabled
Enabled

6

Deviation Limiter

0
1

Disabled
Enabled

5

Pre-Emphasis

0
1

Bypass
Enabled

5

VOGAD

0

4

Input Select

1

Disabled
Enabled

0
1

RXln
Mic.ln

4

De-Emphasis

0
1

Enabled
Bypassed

3

Signal Select

0
1

Internal
External

0
0

0

0

0

0
1
1
1
1

0
0
0
0
1
1
1
1

1 0

Input Level Set

0
0
1
1
0
0
1
1

0

0

0
1
0
1
0

Input Amp Disabled
-4.OdB
-3.0dB
-2.OdB
-1.0dB
OdB
1.0dB
2.0dB
3.0dB
4.OdB
5.OdB
6.0dB
7.OdB
8.0dB
9.OdB
10.OdB

0
1
1
0
0
1
1

1

0
1

0
1
0

1

1
0
1

Table2 - Control Commands
Page 302

Loaded as OOH

Mode Address Command

Audio Output (RX)

0
0

0
0
0
1
1
1
1
1
1
1
1

Control Address Command

(MSB)
Bit 7

3 2

0

Upon power-up the value of the "bits" in this device
will be random (either "0" or "1"). A General Reset
Command (01 H) is required. This command is provided to
"reset" all devices on the Command Data line and has the
following effect on the MX806A:

2

1

0

Process Gain Set

0

0

0
0
0

0

0
1
0
1
0

-4.0dB
-3.OdB
-2.0dB
-l.OdB
OdB
1.0dB
2.OdB
3.OdB

1
1
0
0

1
1

1
0
1

Table 3 - Mode Commands
MX-COM, INC.

MX806A
Modulator Levels

.. ·:.r .Settfl1l9

"

B~te 1

7

~

0

0

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Chip Enabled
Powersaved

Last byte for transmission

1 0

VCO (Ref.) Drive Attenuation

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Enabled
Biased

Powersave

6.2dB
6.0dB
5.SdB
5.6dB
5AdB
5.2dB
5.0dB
4.SdB
4.6dB
4AdB
4.2dB
4.0dB
3.8dB
3.6dB
3AdB
3.2dB
3.0dB
2.8dB
2.6dB
2AdB
2.2dB
2.0dB
1.8dB
1.6dB
1AdB
1.2dB
1.0dB
0.8dB
0.6dB
OAdB
0.2dB
OdB

4 3 2

1 0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1

0
0
0
0
1
1

0
0
1
1
0
0

1

1

1
0
0
0
0

1
0
0
1

1

1

1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0

1
1

1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1

1
1
0
0
0
0
0
0
0
0
1
1
1

1
1
1

1
1

1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

.'

Main Process Out

0
1

0
1

4 3 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0

:~~lilm.e $et

5

Must be "0"

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

.'.

12AdB
12,OdB
11.6dB
11,2dB
10.SdB
10AdB
1O.0dB
9.6dB
9.2dB
S.SdB
SAdB
S.OdB
7.6dB
7.2dB
6.SdB
6AdB
6.0dB
5.6dB
5.2dB
4.8dB
4AdB
4.0dB
3.6dB
3.2dB
2.SdB
2AdB
2.0dB
1.6dB
1.2dB
O.SdB
OAdB
OdB

0

0

:.

VCO Drive Attenuation

( sB)
6 5

0

(Preceded by AlC 13J

(MsB)
7
6

Must be "0"

B~teO

7

:·....0·

sB)
6 5
0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

.MQdu,atot;DIi~ ..• · · . •. /···

Volume Set

First byte for transmission

4 3 2 1 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

(Preceded by AlC 12J

Volume Set Attenuation

0
1
0
1
0
1
0
1
0

1
0

1
0
1
0
1
0

1
0
1
0
1
0
1
0
1
0
1
0
1

Off
48.0dB
46AdB
44.8dB
43.2dB
41.6dB
40.0dB
38AdB
36.8dB
35.2dB
33.6dB
32.0dB
30AdB
28.8dB
27.2dB
25.6dB
24.0dB
22AdB
20.8dB
19.2dB
17.6dB
16.0dB
14AdB
12.8dB
11.2dB
9.6dB
8.0dB
6AdB
4.8dB
3.2dB
1.6dB
OdB

I

Table 5 - Volume Set
Notes
Command Loading: Address/Commands and
data bytes must be loaded in accordance with the
information given in Figure 6.
The Powersave function is enabled by bit 5 of
the Volume Set Command (Table 5).
During Powersave all internal elements except
the Clock Generator and "C-BUS" interface are off.
The Mic Op-Amp and Output Drive stage outputs are
connected to Vss'

Modulator Drives are controlled separately,
but the whole two-byte Modulator Drive command
must be loaded for each requirement adjustment.
Chip Select must be held at a logic "1" for the
period '\SOF/ between transactions.

Table 4 - Modulator Drive Levels
MX-COM, INC.

Page 303

MX806A

Timing Information

FIRST DATA BYTE

AODRESSICOMMAND

LAST DATA BYTE

BYtE

Figure 6 - C-8US Timing Information

"CS Enable" to "clock high"
Last "clock high" to "CS high"
"CS high" time between transactions
Inter byte time
Serial Clock Period

I

2.0
4.0
2.0
4.0
2.0

tCSE
tCSH
tCSOFF
tNXT
tCK

Notes
Command data is transmitted to the peripheral MSB (bit 7) first, LSB (bit 0) last.
Data is clocked into the peripheral on the rising clock edge.
Loaded data instructions are acted upon at the end of each individual, loaded byte.
To allow for different microcontroller serial interface formats, the MX806A is able to work with either
polarity Serial Clock pulses .

------Ira

Sels the Control, Mode and Volume Commands to

....
u_lIm....
II..",.,11_ _
"'"

GENERAL RESET

0\\

....

TABLE 2

CONTROL COMMAND

1 DATA BYTE

MODE COMMAND

1 DATA BYTE

VOLUME SET

1 DATA BYTE

TABLE

a

TABLE 5

mmfll~L~

....

rLJ

_7161514131211Io_7161514131211Io1m~1

....

MODULATOR LEVELS SET

2 DATA BYTES - BYTE 1 (loaded first)

TABLE

4

BYTE 0 (loaded last)

Figure 7 - Examples of Command Data Configurations

Application Information
To assist in rapid setting,
this quick-reference list
should be used with
Figure 5.

Control
7
6
5

4
3-0

Mode

-76
5

4
3
2-0

Page 304

AlC = 10
Audio Ou~ (RX) Enable
Modulator Drive Enable
Pre-Emphasis Select
Input Select (RXfTX)
Input Level Set (-4dB to 10dB)

Modulator Levels AlC = 12H
Byte 1
"0"
7-5
4-0
Mod 1 Attenuation
(0 to 12.4dB)
Byte 2
7-5
"0"
4-0
Mod 2 Attenuation
(0 to 6.2dB)

AlC=11 H
Drive Source
Deviation Limiter Enable
Volume Set
VOGAD Enable
7-6
De-Emphasis Enable
5
Signal Select
4-0
Process Gain Set (-4dB to 3dB)

AlC = 13 H
"0"
Powersave
Volume Set Attenuation
(0 to 48dB)

MX-COM, INC.

MX806A

Specifications
~~
~~~~~ ~~ii~Jf~~~~~~~~:~;~~tAf1:~~~
Exceeding the maximum rating can result in device
damage. Operation of the device outside the
operating limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.
VDD = 5.0V

Supply Voltage
Input Voltage at any pin

-0.3 to 7.0 V

(ref V ss = OV)
Sink/source current
(supply pins)
(other pins)
Total device dissipation
@ T AMB 25°C
Derating
Operating Temperature
Storage Temperature

-0.3 to (V DD+0.3V)

TAMB = 25°C
Xtal/Clock fo = 4.0MHz

±30mA
±20mA

Audio Level OdB ref = 30BmVrms @ 1kHz
(60% deviation, FM)

BOOmW Max.
10mW/oC
-40°C to +B5°C
-55°C to + 125°C

Static Values
Supply Voltage
Supply Current

4.5

(All elements enabled)
(Maximum Powersave)
"C-BUS" Interface
Input Logic "1"
Input Logic "0"
Input Current
Input Capacitance

Overall Performance
Microphone Input Level
Discriminator Input Level
Output Drive Level
(60% deviation)
(100% deviation)
Passband
Passband Ripple
Stopband Attenuation
@150Hz
@3400Hz
@6000Hz
@BOOO to 20,000 Hz
Signal Path Noise TX

3.5
1.5
-1.0

1,2
2,3
2,4
2,4,5
6
7
6,B

291

30
9
9

Total Harmonic Distortion
(RX or TX, 60% deviation)

MX-COM, INC.

30B
1440

V
mA
mA

V
V
1.0
7.5

IlA
pF

30B

mVrms
mVrms

326
3000
0.5

297
-2
10

mVrms
mV pk-pk
Hz
dB

12
2
36
60
-50
-45
-60
-55

dB
dB
dB
dB
dBp
dB
dB
dB

1.0

0/0

50.0

6.0
600

dB
kHz
MQ
kQ
Q

-6.0
0
1

dBloct.
dB
MQ

6.0
-24

dB
dB

20.0
10.0

2

5.5
15.0
1.5

25
154

RX

Circuit Elements - Figure 5
Mic. Amp or Mod. Summation Amp
Open Loop Gain
Bandwidth
Input Impedance
Output Impedance (Open Loop)
(Closed Loop)
De-emphasis
Slope
Gain (at 1.0kHz)
Input Impedance
Voltage Controlled Gain Amp (VOGAD)
Gain (Non-Compressing)
(Full Compression)

5.0
B.O
.7

Page 305

I

MX806A

I

Input Impedance
VOGAD Peak Detectors
Output Impedance logic "1" (Compress)
logic "0"
Hi/lo Peak Detector Threshold
10
Hi Peak Detector Threshold
10
Input (Low + Highpass) Filter
Gain (at 1.0 kHz)
Input Level Amp
Gain Range
Overall Tolerance
Step Size
External Audio Buffer
Gain
Pre-emphasis (Main Process and VOGAD)
Slope
Gain (at 1.0kHz)
Process Highpass Filter
Gain (at 1.0 kHz)
Deviation Limiter
Threshold
Gain
Process Lowpass Filter
Gain (at 1.0 kHz)
Process Gain Amp
Gain Range
Overall Tolerance
Step Size
Output Impedance
Transmitter Modulator Drives
Input Impedance
Mod. 1 Attenuator
Attenuation Range
Overall Tolerance
Step Size
Output Impedance
Mod. 2 Attenuator
Attenuation Range
Overall Tolerance
Step Size
Output Impedance
Audio Output Attenuator
Attenuation Range
Overall Tolerance
Step Size
Output Impedance
Miscellaneous Impedances
Processed Audio Input
Calibration Input
External Process Out
RX with De-emphasis Bypass

10.0

MO
1
10
1,300
650

-1.0

0

kO
MO
mVp-p
mV+ve pk
1.0

dB
dB
dB
dB
dB

0
-1.0
0.75

1.0

1.0
1.25

-0.1

0

0.1

6.0
10.0

dB/oct.
dB

-0.1

0

0.1

dB

708
-0.5

1300

1413
0.5

mVrms
dB

-0.1

0

0.1

dB

3.0
0.5
1.25

dB
dB
dB

-4.0
-0.5
0.75

1.0
600

0

15.0
0
-1
0.2
0
-0.5
0.1
0
-1.0
1.1

0.4
600

0.2
600

1.6
600
500
500
100
25.0

kO
12.4
1
0.6

dB
dB
dB

0
6.2
0.5
0.3

dB
dB
dB

0
48.0
1.0
2.1

dB
dB
dB

0
kO
kn
n
kn

Notes
1. Producing an output of OdB with the Mic. Op-Amp set to 6dB (as shown in Figure 2) and the Modulator
Drives set to OdB.
2. With Output Drives set to OdB and the system calibrated as described in the Application Notes.
3. Input level range for OdB output, by adjustment of the Input Level Amp.
4. It is recommended that these output levels will produce 60% or 100% deviation in the transmitter.
5. With the microphone input level 20dB above the level required to produce OdB at the Output Drives.
6. Between Microphone or RX inputs to Modulator or Audio Outputs.
7. Deviation from the ideal overall response including the pre- or de-emphasis slope.
8. Excluding the effect of pre- or de-emphasis slope.
9. In a 30kHz bandwidth.
10. Using pre-emphasis in the TX path.

Page 306

MX-COM, INC.

MX·~,IN~.

MX816
c-.us

Preliminary Information

COMPATIBLE

NMT AUDIO PROCESSOR
Features
• Full-Duplex Audio Processing for NMT Cellular System
• On-Chip Speech and SAT Abilities
TXlRXlSA T Filtering & Gain -- VOGAD -- Pre-iDe-Emphasis -- Deviation
Limiter
• Serial Microprocessor Interface
• Separate SAT Channel
• Sidetone Output Available
• HandsFree Compatibility
• Access to External Processes
Compression -- Expansion -- Signaling/Data Mixing -- VSR Codec (Store/Play)
• Powersave (Low Current) Settings

MX816J
28-pin CDIP

MX816DW
28-pin SOIC

Description
The MX816 is a microprocessor controlled full-duplex audio processor on a single chip with separate TX and RX
paths to provide all the filter/gain/limiting functions necessary to pre-process audio, data and signaling in the Nordic
Mobile Telephone (NMT) cellular communications system.
Selectable inputs to the transmit path include a choice of two microphones, DTMF/signaling or MSKldata with
access in this path to external compression circuitry. The TX path provides input/gain filtering, VOGAD, a deviation
limiter and TX Modulation Drive controls.
In the RX path the SAT signal is separated from the incoming audio via a gain/filter block and made available at
a separate pin for mixing externally with the TX Modulation Drive.
HOST SYSTEM (SERIAL) PROCESSOR BUS

TO

COMPRESSOR

FROM
COMPRESSOR

MIC.l

MIC.2
DTMF (1X)
SPEECH +
SIGNAUNG

RX AUDIO IN

MSK DATA OUT
MSKIPLAY
EAR AUDIO OlJT
MX816 NMT

RADIO'S

HOST

uPROCESSOR

Figure 1 - MX816 NMT Audio Processor Installed in a Cellular System
Page 307

MX816

I

MX816
Description ...
The RX path consists of an input gain/filter block for voice and data, inputs from an external audio expansion
system and an output gain (volume) control driving either a loudspeaker (handsfree) system or earpiece.
Unique to the MX816/826/836 cellular audio processors is the ability to route audio (TX or RX) to an external Voice
Storage and Retrieval device such as the MX802 or MX812, thus providing the radio system with a voice answering
and announcement capability using external DRAM.
The MX816, a low-power 5V CMOS integrated circuit, reduces the amount of components required in a cellular
audio system by providing more functions on a single chip. It is available in 28-pin Cerdip and small outline (SOIC)
packages.

Pin Function Chart
Xtal: The output of the 4.032 MHz on-chip clock oscillator. External components are required at this output
when a Xtal is used. See Figure 2.
2

XtaVClock: The input to the on-chip clock oscillator. A Xtal or externally derived clock should be connected
here. Note that operation of the MX816 without a suitable Xtal or clock input may cause device damage.
See Figure 2 (notes).

I

3

Serial Clock: The "C-8US" serial data clock input. This clock, produced by the microcontroller, is used for
transfer timing of commands and data to the MX816. See Timing diagrams.

4

Command Data: The "C-BUS" serial data input from the microcontroller. Data is loaded to this device in
8-bit bytes, MSB (B7) first and LSB (BO) last, synchronized to the Serial Clock. See Timing diagrams.

5

Chip Select (CS): The "C-BUS" data loading control function. This in~ is provided by the microcontroller.
Data transfer sequences are initiated, completed or aborted by the CS signal. See Timing Diagrams.

6

VBIAS: The internal circuitry bias line, held at V DD/2. This pin should be decoupled to V ss. See Figure 2.

7

RX Audio In: The audio inputto the MX816. Normally taken from the radio's discriminator output, this input
has a 1Mil internal resistor to VBIAS' and must be connected with a capacitor.

8

Expand/Store: This is a common output that can be used as either an input to an external audio expander
or the input to a voice storage medium such as the MX812. Components relevant to the external device
requirements should be used at this output. See Figures 2 and 3.

9

Expanded Audio In: This is the audio input, via SW5, from an external expander or audio mixing function.
This input has a 1Mil internal resistor to V BIAS' and must be connected via a capacitor. See Figures 2 and
3.

10

TX Mod Out: This is the composite TX audio output to the transmitter modulator from a variable attenuation
stage (11 H). This output is set to V BIAS via an internal 1Mil resistor when set to Powersave or OFF.

11

LS Audio Out: This is an audio output of the RX path (or selected audios - see Figures 3 and 4) for a
loudspeaker system. This is available for handsfree operation. This output can be connected to VBIAS when
not required, by SW6 (Configuration Command 10H). A driver amplifier may be required.

12

Ear Audio Out: This is an audio output of the RX path (or selected audios - see Figures 3 and 4), available
as an output for a handset earpiece. This output in parallel with the LS Audio Out function can be connected
to VBIAS when not required by SW7 (Configuration Command 10H). A driver amplifier may be required.

13

Sidetone: This is a switched "sidetone" from the microphone inputs made available for mixing externally
with the Ear audio. See Figure 3.

14

Vss: Negative supply (GND).

Page 308

MX-COM, INC.

MX816

Pin Function Chart
15

VOGAD: External components (R and C) at this pin control the attack and decay time constants of the onchip VOGAD function.

16

SAT Out: This is the output of the SAT bandpass filter. This level is recovered from the Input RX Audio.
This tone level can be modified by the SAT and Powersave Command (13 H) and is available for mixing
internally with the transmitter modulation. See Figures 3 and 4.

17

TX Mix In:

18

An input and an output available, with external components, to introduce signaling tones
into the TX Path prior to the final level adjustments.
TX Filter Out:

19

MSK Out: This is the de-emphasized RX audio output available for access to the received MSK data. It
could be directed to an MSK Modem such as the MX439.

20

Deviation Limiter In: This is the input to the on-chip deviation limiter. This input should be a.c. coupled
to the Pre-Emphasis Out pin. The a.c. coupling will achieve macimum possible symmetry of limiting as this
input has a 1Mil reisistor to VBIAS. See Figure 2.

21

Pre-Emphasis Out: Audio output from the VOGAD circuitry in the TX Input Gain/Pre-Emphasis function.
This output should be a.c. coupled to the Deviation Limiter In pin. See Figure 2.

22

DTMF In: This input, which introduces DTMF type audio to the TX path at a suitable level for transmission,
is controlled by SW2 (Configuration Command 10H). This input has an internal 1Mil resistor to VBIAS and
should be connected via a capacitor.

23

Compression In: This is the audio input from an external compression system. This input has an internal
1Mil resistor to VBIAS and should be connected via a capacitor.

24

Compression: This is the output to an external audio compression system. Currently available
compressor/expanders have op-amps incorporated. The compressor can be bypassed by SW2.

25

Mic 21n:

26

Mic 1 In:

27

MSK/Play In: This is the TX MSK data input via SW2. This can also be used to input (replay) from a voice
storage device such as the MX812. This "replayed" audio can be sent to RX or TX paths, allowing a
MessagingNoice Notepad/Answering function. Both the MX439 MSK Modem and the MX812 VSR Codec
outputs can be wired directly to this pin if the functions are activated one at a time. This input has an internal
1Mil resistor to VBIAS and should be connected via a capacitor.

28

V DD : Positive supply. A single, stable +5 volt supply is required. Levels and voltages within this Audio
Processor are dependent upon this supply.

These TX voice (Mic.) inputs, selectable by SW1, are available for handsfree mic.!
handset mic. or and TX audio input. Pre-amplification may be required at these inputs.
These inputs each have an internal 1Mil resistor to VBIAS and should be connected via a
capacitor.

C-8US is MX-COM's proprietary standard for the transmission of commands and data between a
jiController and D8S BOO IC's. It may be used with any jiController, and can, if desired, take advantage
of hardware serial liD functions embodied into many types of jiController. The C-8US data rate is
determined solely by the jiController.
Notes on Inputs: To minimize aliasing effects, lowpass filtering may be required at the inputs to this device
(especially thise supplied from switched-capacitor-type devices) to ensure the input spectrum is kept below
63 kHz.

Page 309

MXB16

I

MX816

cr.

11
C11T-!==fd9

Xi'AL

$X1

xrAUCLOCi<.
SERiAL CLock

COMMANb DATA

cHIP' sELECT
VBIAs

112

I

-='"

~H

RX AUDIO ,IN
ExPANr:i!S'TORE

~ I (EXPANDEDJ AlJ[)IO ,IN
I

TX MOD OUT

Ls AuDIO OUT

28

1

21 MSK'JPi.AY iN
26 MI6 i iN

2
3
4

20

1

MX816J

8
9
'10

EAR AUDIO OUT

11
12

SIOETONE OUT

'13

{,14

I

Mid, 2 iN

24 COMPRESS

5

e

"100

-'-'C10

ts,

:~
~
!~

~'

23 •_(C(jMpFiEssEO) AU(jf{)' IN
DTMF IN
i eli,
22
"'Mi:>ovt
PRE-E
21
20 DEY LfMrtEFi IN *bi
19 MSKJriATA OUT
18 TX FILTER OllT
I
17 1)( MIX IN
SAT
our
1'S

,r

1B

VOGAD

I

~

I

R2
S
<,.0'

,kAA
v~v

$C13

>' R1
<,

vatue
O. fllF
6.11lF

Value

1O'Okfl'
100'](0

2.2Tv10
C:UIlP
O'.1p;F
O".tIlF

33pF

O'.1IlF
33'pF
t.O~F

O.1p;F
O.1'Il'P
O'.1'p;F

j

O.1;IiF
4.O'32Tv1Hl
Tolerande: A'=±fo%. C=±20%~

• Figure 2 - Recommended External Components

Notes:
1. Xtallclock Operation
Operation of any MX-COM IC without a XtaJ or clock input
may Cause device damage. To minimize damage in the
event of. a Xtalldrive failure" you should install a cmrent
limiting device (resistor or fast-reaction fuse) on the power
input (V DD)'.

2. VOGAD Components
R1 , R2 , R3 , C13 and the VOGAD Pin internaf impedance'
form the VOC3AD timing circuitry.
Control-Voltage Attack Time is set by
C13 x Intemallmpedance'
Control~Volta'ge Decay Time is set by'
C1~ x Rs (ass't:li'ning R3»R1 and R2 )·

Page 310

3. IiIISK Modem'
The MX439, a general purpose MSi< Modem, could be
used within this NM'T system Audio Processor. 'The
MX439 is a non-formatted modem, whiCh with due regard
to Xtal!clock frequencies and Microprocessor interface, is
cornpatible with both MObile/Portable and Base Station
applications.

4. SAT Output
Due to the high output impedance of this output, an
external buffer amplifier may be required at this output
when interfacing or mixing with other system sections.

MX-COM, INC:

~

8

-~

~

Vee
SAT

..-

~~IMIC"N.J

rl

ALTEFI~TIVE METHOD OF
lNTFIODUCl1IG THE SAT SIGNAL
TO THE MOOULATlCN PATH

-"""

TX FL TER TX MIX
OUT

IN

MOD LEVEL

~I

~~MIC21N

II~I-I---

~

_I·"n~~"w"
COMMAND DATA

C-eUS
_
CONTROL

INPUTS
--+

CHIP
SELECT

I~
mt
I

XTAL/CLOCK
COMPONENTS'
SEE FIGURE 2

--11_1

M~W'V"

'I
~~~~~

AlARM
MSKDATA
TORE AUDIO

i

s:

C.:>

.....

Figure 3 - The MX816 Within an NMT Cellular Radio System

..
~

en

MX816

The Controlling System
C-BUS is designed for low IC pin-count, flexibility in handling variable amounts of data, and simplicity of system
design and IlControlier software. It may be used with any IlController, and can, if desired, take advantage of the
hardware and serial I/O functions built into many types of IlControlier. Because of this flexibility and because the BUS
data rate is determined solely by the IlController, the system designer has complete freedom to choose a IlControlier
appropriate to the overall system processing requirements.
Control of the functions and levels within the MX816 NMT Audio Processor is by a group of Address/Commands
and appended data instructions from the system microcontroller. The use of these instructions is detailed in the following
paragraphs and tables.

0000000 1
000 1 0 000
000 1 000 1
000 1 001 0
00010011

I

2
3

1 byte
1 byte
1 byte
1 byte

+
+
+
+

4
5

In C-BUS protocol the MX816 is allocated Address/
Command values 10H to 13H' Configuration, TXlRX Gains,
and SAT/Powersave aSSignments and data requirements
are given in Table 1.
Each instruction consists of an Address/Command
(AlC) byte followed by a data instruction formulated from
the following tables.
Commands and Data are only to be loaded in the
group configurations detailed, as the C-BUS interface

recognized the first byte after Chip Select (logic 0) as an
Address/Command. Function or Level control data, which
is detailed in Tables 2, 3, 4, and 5, is acted upon at the end
of the loaded instruction. See Timing Diagrams, Figures
5 and 6.
Upon power-up the value of the "bits" in this device
will be random (either "0" or "1"). A General Reset
Command (01 H) is required to set all MX816 registers to
00H'

Configuration Command

TX Gain & Mod. Command

(Preceded by AlC 10,1

(MSB)
Bit 7

Transmitted First
SW8 Sidetone

0
1

Sidetone Bias
Sidetone Enabled

6

swsn RX Audio

0
1

Ear Enabled, LS Bias
LS Enabled, Ear Bias

5

SW5 Expander

0
1

Expander Bypass
Expander Route

4

SW4 TXlRX Audio

0
1

TX Store/Audio
RX Store/Audio

3

SW3 Dev. Limiter

0
1

Dev. Limiter Bypass
Dev. Limiter Route

2

SW1 Mic. Inputs

0

Mic.1lnput
Mic. 2 Input

1

1

a

SW2 TX Function

0

0
1
0
1

DTMFln
Compressor In
Compressor Bypass
MSK/Playin

0
1
1

Table 2 - Configuration Commands
Page 312

(MSB)
7 6

5

0

0

0

0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

3

2

1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

4
0
1

(Preceded by AlC 11,1

Transmitted First
TX Mod. Level
OFF (Low Z to v BIAS)

1
0
1

-S.6dB
-S.2dB
-4.8dB
-4.4dB
-4.OdB
-3.6dB
-3.2dB
-2.8dB
-2.4dB
-2.0dB
-1.6dB
-1.2dB
-O.8dB
-O.4dB
OdB

a

TX Input Gain

0
1
0
1
0
1
0
1
0
1

0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

-2.6SdB
-2.0SdB
-1.S0dB
-O.9SdB
-O.45dB
OdB
O.4SdB
O.85dB
1.25dB
1.65dB
2.0SdB
2.40dB
2.70dB
3.0SdB
3.35dB
3.6SdB

Table 3 - TX Gain & Mod. Commands
MX-COM, INC.

MX816

The Controlling System
Configuration Command
:cc.

:::~

b.'

'''3'

....'"

(Preceded by AlC 10,)

TX Gain & Mod. Command

"':..c),,·,

·.c....

(MSB)

Transmitted First

7 6

5

4

RX LS Volume

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

OFF (Low Z to

3

2

1 0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

-28.0dB
-26.0dB
-24.0dB
-22.0dB
-20.OdB
-18.0dB
-16.OdB
-14.0dB
-12.0dB
-10.0dB
-8.0dB
-6.0dB
-4.0dB
-2.0dB
OdB

v

:.::,

(MSB)
Bit 7

Transmitted First

0

Must be a logic "0"

BIAS)

6
Must be a logic "0"

0

RX Input Gain

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

(Preceded by AlC 11,)
.·e,.,;;a;...I_.;

3.75dB
4.30dB
4.80dB
5.3OdB
5.80dB
6.20dB
6.55dB
7.05dB
7AOdB
7.80dB
8.15dB
8.50dB
8.80dB
9.10dB
9.40dB
9.70dB

5

4

3 2

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

SAT Tone Level
OFF (Low Z to vBIAS)
-1.95dB
-1 AOdB
-0.90dB
-OA5dB
OdB
OAOdB
0.85dB
1.20dB
1.60dB
1.95dB
2.30dB
2.60dB
2.90dB
3.25dB
3.50dB

1

Powersave RX Gain
Element

0
1

Powersave Element
Enable Element

0

Powersave MX816

0
1

(except RX Gain Element)
Powersave MX816
Enable MX816

I

Table 5 - SAT and Powersave Commands

Table 4 - RX Gain and Volume Commands

Reference Signal Levels

mV

%

(rms)

100 -

2£7

kHz

4.7

100%
4.7kHz
257mV

100%
4.7kHz
~7:::,V

I

90 -

ao ~

.:t.

205

3.76

70 -

~4:::.V

60 -

154

2.82

'Iii
.s:
., 40 0

103

1.66

51.5

0.94

c:

79%
3.7kHz
203mV

63.8%
3.0kHz

89.4%

U~
74.5%
3.5kHz

!22~

59.6%
2.8kHz

~3~

48.9%
2.3kHz

0

l!6~

50

21.3%
1.0kHz

30 20

-

10 -

Maximum
Deviation

1.OkHz
Tone

T

1.OkHz
Umit Tone

6.4%
a.3kHz

..

Umited
Signal

MSK
1200 Hz

MSK
Mean

MSK
1800Hz

LM.
Test Level

T

4015Hz
SAT Tone

Figure 4 - NMT Signal Deviation Levels and Corresponding TX Mod Outputs with the Mod Level set to OdB
Page 313

MX816

MX816

Timing Information

--I
__________________________

CHIP SELECT

~~

--I

~r--l~

___________

j.- tcse

FIRST DATA BYTE

ADDRESSICOMMAND
BYTE

II

j.-

tCSOFF

NEXT ADDRESSICOMMAND
BYTE

Inter-byte period logic level is not important.

Figure 5 - Control Timing Information

I

"CS Enable" to "clock high"
Last "clock high" to "CS high"
"CS high" time between transactions
Clock Cycle Time
Inter byte time
Serial Clock-High Period
Serial Clock-Low Period
Command Data Set-up Time
Command Data Hold Time

2.0
4.0
2.0
2.0
4.0
500
500
250
0

tCSE

1
1,2
1

tCSH
tCSOFF
tCK

t NXT
tCH
tCl

tCDS
tCDH

Ils
IlS
Ils
Ils
Ils
ns
ns
ns
ns

Notes
1. These minimum timing values are altered during operation of the MX812 VSR Codec.
2. Chip Select must be taken to a logic "1" between each individual transaction.

SERIAL CLOCK
(from I1C)
1

-.1

1

:+-tCDH
1

COMMAND DATA
(from I1C)

t CDS"':

:+:

1

1

=x=::x=

Figure 6 - Control Timing Relationships
Page 314

MX-COM, INC.

MX816

System Performance
10000

1000

100
20

Frequency (HI:)
10

·10

Mic.1 In tolX Mod. Out

·20

-30

Voo '" 5.0V
Signal Input Level 55mVrms
TX Gain set to OdB

·40

Mod Level set to OdB

=

Figure 7 - TX Frequency Response
100

1000

10000

20

Frequency (Hz)

I

10

o
-10

RX Audio In to LS/Ear Audio Out
Voo = 5.0V
Signal Input Level 164mVrms
RX Gain set to 3.75dB
Volume set to OdB

-20

=

-30

-40

Figure 8 - RX Frequency Response

10000

1000

10
Frequency (Hz)

o
-10

AX AudiO In to SAT Out
Vee = 5.0V
Signal Input Level::: 164mVrms
SAT Gain set to OdB

-25
-30

-40

FiguretJ - SAT Bandpass Filter Frequency Response

Page 315

MX816

MX816

Specifications
ng can
damage. Operation of the device outside the operating
limits is not suggested.
Supply Voltage
Input Voltage at any pin
(ref Vss = OV)
Sink/source current (supply pins)
(other pins)
Total device dissipation
@ TAMB 25°C
Derating
Operating Temperature
Storage Temperature

Static Values
Supply Voltage
Supply Current

I

-0.3 to 7.0 V

V DD = 5.0V

-0.3 to (V DD+0.3V)
±30mA
±20mA

TAMB = 25°C

SOOmW Max.
10mW/oC
-40°C to +S5°C
-55°C to +125°C

Audio Level OdB ref = 164mVrms @ 1kHz

Xtal/Clock fo = 4.032MHz

4.5
(All elements enabled)
(RX Data Mode)
(Maximum Powersave)

Alias Frequency
On-Chip Xtal Oscillator
RIN
ROUT
Inverter DC Voltage Gain
Gain/Bandwidth Product
Analog Input Impedances
Mic.1 & 2
MSKIPlay
Compo In
DTMF In
Deviation Limiter In
Expanded Audio In
TX Mix In
RX Audio In
Analog Output Impedances
Pre-Emphasis Out
TX Mod Out
Expand/Store
LS and Ear Audio
MSK Data Out
SAT Out
TX Filter Out
VOGAD
- ON
Switches
- OFF
Control Interface Parameters
Input Logic "1"
Input Logic "0"
Input Current
Input Capacitance

Page 316

All devices were measured under the following conditions unless otherwise noted.

5.0
6.0
1.0
0.6
63.0

5.5

MQ
kQ

10.0
10.0
10.0
10.0

MHz

500
500
500
500
100
47.0
100
100

kQ
kQ
kQ
kQ
kQ
kQ
kQ
kQ

600
600
600
1.0
600
10.0
600
500
1.0

Q
Q
Q
kQ
Q
kQ
Q
Q
kQ
MQ

VN

10.0
2
2
2
2

3.5
-1.0

V
rnA
rnA
rnA
kHz

1.5
1.0
7.5

V
V
itA
pF

MX-COM, INC.

MX816

Channel Performance, TX Signal Path
Analog Signal Input Levels
Mic, 1 & 2
MSK/Play
DTMF
Comp, In
TX Mix In
Analog Signal Output Levels
Pre-Emphasis Out
TX Filter Out
TX Mod, Out
Sidetone Out
Path Gains/Levels
TX Gain - 11H
Adjustment Range
Step Error
VOGAD
Gain (Non-Compressing)
(Full Compression)
Attack Time
Deviation Limiter
Threshold
Symmetry
Mod. Level Attenuation - 11 H
Adjustment Range
Step Size
Error of any Setting
Overall
TX Distortion
TX Hum and Noise

3
3
3
3
3

0
0
0
0
0

dB
dB
dB
dB
dB

3
3
3
3

0
0
0
0

dB
dB
dB
dB

-2,65
-0,2

4

-5,6
0,2
-1,0

3,65
0,2

dB
dB

0
-15,0
3,0

dB
dB
ms

713
7

mV p-p
%

0.4

0
0,6
1.0

dB
dB
dB

-40,0
-40,0

-32,0
-20,0

dB
dB

Channel Performance, RX Signal Path
RX Audio Input Level
LS/Ear Audio Output Level
Path Gains/Levels
RX Gain -12H
Adjustment Range
Error of any Setting
MSK Output
Frequency Range
Gain at 1kHz
Response
Volume -12H
Adjustment Range
Step Size
Error of any Setting
Overall
RX Distortion
RX Hum and Noise

Page 317

-7,0
0

3
3

3,75
-0,2
900
-1,0

-28,0
1,5
-1,0

dB
dB

9,70
0,2

dB
dB

2100
1,0

dB
dB
dB/oct.

2,0

0
2,5
1,0

dB
dB
dB

-40,0
-40,0

-32,0
-34,0

dBp
dB

0
6,0

MX816

I

MX816

Channel Performance. SAT Signal Path
Bandpass Filter
Frequency Range
Gain
SAT Level" 13H
Adjustment Range
Step Error

3945
-1.0

4055
1.0

Hz
dB

-1.95

3.50

-0.2

0.2

dB
dB

Notes
1. With reference to the Powersave Command and Figure 3, all functions with the exception of the RX Gain
Element may be powersaved. This will still allow signaling data through the MX816 to activate the system via
the I!Processor.
2. Serial Clock, Command Data and Chip Select Inputs.
3. Levels equivalent to ±3.0 kHz deviation with the settings below:
TX Gain = OdB
RX Gain = 7.05dB
SAT Level =OdB

I

Mod Level = OdB
Volume = OdB

Other levels can be achieved by adjusting the above variable gain blocks in accordance with Tables 1 - 5.
4. Using the components shown in Figure 2.

Page 318

MX-COM, INC.

MX·~,IN~.

MX826
C·BUS

Preliminary Information

COMPATIBLE

AMPSINAMPS SYSTEM AUDIO PROCESSOR

Features
• Full-Duplex Audio Processing for AMPSI
NAMPS Cellular Systems

• HandsFree Compatibility
• Powersave (Low-Current) Settings

• On-Chip Speech and SAT Capabilities
- TXlRX Filtering & Gain - SAT Channel
Pre-fDe-Emphasis - Deviation Limiter
• Serial JlProcessor Interface
• "Sidetone" Output Available
• Access to External Processes
- Compression - Expansion Signaling - VSR Codec (StorelPlay)

MX826DW
28-pin SOIC

MX826J
28-pin CDIP

HOST SYSTEM (SERIAL) PROCESSOR BUS

TO
COMPRESSOR

Mic.1
Mic.2

CELLULAR RADIO
AUDIO PROCESSING IC

DTMF{TX)

RX
DEMOD

sf~~~8~G

TXMODOUT
MIXING
NETWORK

SAT OUT
LSAUDIOOUT

RX AUDIO IN

SIDETONEOUT
EAR AUDIO OUT

RADIO'S
HOST
uPROCESSOR

HOST SYSTEM (SERIAL) PROCESSOR BUS

Figure 1 - The MX826 AMPSINAMPS Audio Processor Installed in

MX-COM, INC.

a Cellular System
Page 319

I

I

MX826
Description
The MX826 is a ~Processor controlled full-duplex
audio processor on a single-chip with separate TX and
RX paths to provide all the filter/gain/limiting functions
necessary to pre-process audio, wideband-data and
signalling in cellular communications systems using the
AMPS/NAMPS or TACS/ETACS/JTACS specifications.
Selectable inputs available to the transmit path are:
a choice of two microphones and DTMF/signaling, with
access, in this path, to external compression circuitry.
Operationally the TX path provides input gain/filtering, a
deviation limiter and TX Modulation Drive controls.
In the RX path the SAT signal is separated from the
incoming audio via a filter block and made available at a
separate pin for mixing externally with the TX Modulation
Drive.
The RX path consists of an input gain/filter block for

voice, inputs from an external audio expansion system
and an output gain control driving either a loudspeaker
system or earpiece.
Unique to the MX816/826/836 cellular audio
processors is the ability to route audio (TX or RX) to an
external Voice Store and Retrieve (VSR) device such as
the MX802 or MX812 thus providing the radio system
with a voice answering and announcement facility using
external DRAM.
As a member of the DBS800 family, the MX826
follows C-BUS protocol. (C-BUS is the serial interface
used by all DBS800 integrated circuits.)
The MX826, a low-power CMOS device which reduces
the amount of microcircuits and components required in
a cellular audio system by providing more functions on a
Single chip, is available in 28-pin SOIC and CDIP
packages.

1

Xtal: The output of the on-chip clock oscillator.

2

XtallClock: The input to the on-chip clock oscillator. A Xtal or externally derived clock (fXTAL) should be
connected here. Note that operation of the MX826 without a suitable Xtal or clock input may cause device
damage. See Figure 2 (notes).

3

Serial Clock: The "C-BUS" serial data clock input. This clock, produced by the
transfer timing of commands and data to the MX826. See Timing Diagrams.

4

Command Data: The "C-BUS" serial data input from the IJControlier. Data is loaded to the MX826 in
8-bit bytes, MSB (B7) first, and LSB (BO) last, synchronized to the Serial Clock. See Timing Diagrams.

5

Chip Select (CS): The "C-BUS" data loading control function. This input is provided by the ~Controller.
Data transfer sequences are initiated, completed or aborted by this signal. See Timing Diagrams.

6

VBIAS: The internal circuitry bias line, held at V orl2 this pin must be decoupled to VSS. See Figure 2.

7

Rx Audio In: Normally taken from the radio's discriminator output, this input has a 1MQ internal resistor
to VBIAS and requires to be connected via a capacitor.

S

Expand/Store: A common output that can be used as either an input to an external audio expander or
the input to a voice storage medium such as the MX812. Components relevant to the external device
requirements should be used at this output. See Figures 2 and 3.

9

(Expanded) Audio In: The audio input, via SW5, from an external expander or audio mixing function.
This input has a 1MQ internal resistor to VBIAS and requires to be connected via a capacitor. See Figures
2 and 3.

10

TX Mod Out: The composite TX audio output to the transmitter modulator from a variable attenuation
stage (11 H). This output is set to VBIAS via an internal 1MQ resistor when set to Powersave or OFF.

11

LS Audio Out: An audio output of the Rx path (or selected audios, see Figure 3) for a loudspeaker
system. This is available for handsfree operation. This output can be connected to VBIAS when not
required, by SW6 (Configuration Command (10 H A driver amplifier may be required.

~Controller,

is used for

».

Notes on Inputs: To minimize aliasing effects, lowpass filtering may be required at the inputs to this
device (especially those supplied from switched-capacitor-type devices) to ensure the input spectrum is
kept below 63kHz.

Page 320

MX-COM, INC.

MX826

12

Ear Audio Out: An audio output of the Rx path (or selected audios), available as an output for a
handset earpiece. This output, in parallel with the LS Audio Out function, can be connected to VBIAS
when not required, by SW7 (Configuration Command (10 H)). A driver amplifier may be required.

13

Sidetone: A switched "sidetone" from the microphone inputs made available for mixing externally with
the "Ear" audio. See Figure 3.

14

Vss: Negative supply rail. Signal ground.

15

TX Mix: The output of the TX Mix Amplifier. Used with external components, it allows the TX Filter
Out output to mix with externally generated signalling tones prior to the final level adjustment.

16

SAT Out: The output of the SAT Bandpass filter. This level is recovered from the input RX audio
and is available for mixing externally with the transmitter modulation. See Figure 3.

17

TX Mix In: The input to the TX Mix Amplifier. Used with external components, it allows the TX Filter
Out output to mix with externally generated signalling tones prior to the final level adjustment. The
recovered SAT signal may be introduced at this point. See Figures 2 and 3.

18

TX Filter Out: The output of the Deviation Limiter/Lowpass Filter stage. This stage can be bypassed using SW3 (Configuration Command). See Figure 3.

19

No internal connection - Leave open circuit.

20

Deviation Limiter In: Input to the on-chip deviation limiter. This input should be a.c. coupled to the
Pre-Emphasis Out pin. The a.c. coupling will achieve maximum possible symmetry of limiting as this
input has a 1MQ internal resistor to V BIAS' See Figure 2.

21

Pre-Emphasis Out: Audio output from the TX Gain/Pre-Emphasis function. This output should be
a.c. coupled to the Deviation Limiter In pin. See Figures 2 & 3.

22

DTMF In: To introduce DTMF type audio, at a suitable level for transmission, to the TX Path,
controlled by SW2 (Configuration Command (10 H)). This input has an internal 1MQ resistor to VBIAS
and should be connected via a capacitor.

23

Compression In: The audio input from an external compression system. This input has an internal
1MQ resistor to VBIAS and should be connected via a capacitor.

24

Compression: The output to an external audio compression system. Currently available compressor/
expanders have Op-Amps incorporated. The compressor can be by-passed by SW2.

25

Mic.2 In:

TX voice (Mic.) inputs, selectable by SW1 available for handsfree mic.!handset mic. or
any TX audio input. Pre-amplification may be required at these inputs. These inputs
each have an internal 1MQ resistor to VBIAS and should be connected via a capacitor.

26

Mic.1 In:

27

Play In: The input via SW2 from a voice storage device such as the MX812. This "replayed" audio
can be sent to RX or TX paths allowing a Messaging/voice Notepad/Answering facility. This input
has an internal 1MQ resistor to VBIAS and should be connected via a capacitor.

28

VDO: Positive supply rail. A single +5-volt power supply is required. Levels and voltages within this
Audio Processor are dependent upon this supply.

C-BUS is MX-COM's proprietary standard for the transmission of commands and data between a
j1Controller and the relevant Cellular microcircuits. It may be used with any J1Controller, and can, if
desired, take advantage of the hardware serial 110 functions embodied into many types of
J1Controller. The "C-8US" data rate is determined solely by the J1Controller.

MX-COM, INC.

Page 321

I

MX826
Application Information

VDD

5lTA[

~~C'
-=-

---i.

r

~

C'O

1
2
SERIAL CLOCK
3
COMMAND DATA
4
CHIP SELECT
5
v_
6
RXAUDIOIN
C.
7
EXPANDISTORE
8
(EXPANDED) AUDIO IIIL
9
TXMODOlTT
10
LS AUDIO OUT
11
EARAUDIOOlTT
12
SIDETONE OUT
13
~ 14

X'*

I

28
27
26
25
24
23

XTALICLOCK

MX826J

100kO
as required

100kO
as required

Tolerances -

100nF
100nF

C,
C.
C,
C.
C,

C'!I--

MIC.2IN

Coil--

,p-.

PRE-EMP

oUT' I

DEVUMIN

::;:C 7

- TX FILTER 0I[r C;SI L
TXMIXIN

..

SAT OUT

C;, ..
..

TXMIX

r

C;.

Wflf:!!:'i~

100nF
100nF
100nF
100nF
100nF

C.
C.

C,.
C"
C12

C;.

COMPRESS •

21
19
18
17
16
15

t

~

MlC.1IN

(COMPRESSED) AUDIO INlp
I
DTMFIN

20

~~

R,
R,
R,
R.
C,
C,

22

\too
PLAY IN

100nF
33pF
100nF
33pF
1.011F

~

-%-v
lAARo
"V"v"v
·V;;VRs

-b:.

n -A"

It.
vvv

C13
C14
C15
C16
X,

100nF
100nF
100pF
100nF
4.000MHz

Capacitors ±20%

Figure 2 - Recommended Extemal Components

Notes
1.

Xtal/clock operation

2.

Operation of any MX-COM IC without a Xtal or
clock input may cause device damage. To minimize
damage in the event of a Xtal/drive failure, you
should install a current limiting device (resistor or
fast-reaction fuse) on the power input (V DD ).

SAT Output
It is possible, due to the impedance of this output,
that an external buffer amplifier will be required
when interfacing or mixing with other cellular system
sections.

3.

TX Mix Gain
The value of R. should be chosen with R/C'5 in
order to provide the required gain.

Page 322

MX-COM, INC.

~

n
~

AMPS/NAMPS Cellular System Interfaces

~

q

Jl~~:k~~GD'l~~IN
-----tl

rl

DEV.

LIMITER IN

rA
I

Mixing SAT, TX Signal & Signaling

~~~ \~!~n~~~riX~d~~~md~rmay

be mixed prior to modulation.

T
60lfER

TX

TO
MODULATOR

TX MOD OUT

---+~
SIDETONE OUT

V,"'"
SAT OUT

EAR AUDIO OUT

~
LS AUDIO

MIXING

NETWORK

ou; 1------t>--tJ
~

I I - - - - - - -.....

HANDSFREE
LOUDSPEAKER

STORE AUDIO

DTMF

ALARM

s::

;;?

~
~
Co)

Figure 3 - The MX826 Internal and External Signal Paths within

a AMPSINAMPS Cellular Radio System

><

CO

I\)

en

MX826
The Controlling System: C-BUS Hardware Interface
C-BUS is MX-COM's proprietary standard for the transmission of commands and data between a IlControlier and MXCOM's New Generation integrated circuits. C-BUS has been designed for a low IC pin-count, flexibility in handling
variable amounts of data, and simplicity of system design and IlControlier software.
It may be used with any IlController, and can, if desired, take advantage of the hardware serial I/O functions built into
many types of IlControlier. Because of this flexibility and because the BUS data-rate is determined solely by the
IlController, the system designer has complete freedom to choose a IlControlier appropriate to the overall system
processing requirements.
Control of the functions and levels within the MX826 is by a group of Address/Commands and appended data
instructions from the system IlControlier to set/adjust the functions and elements of the device. The use of these
instructions is detailed in the following paragraphs and tables.

General Reset
Configuration Command
TX Gain & Mod. Command
RX Gain & Vol. Command

01
10
11
12

0
0
0
0

0
0
0
0

0
0
0
0

0

Powersave Command

13

0

0

0

1

0
0
0
0

0
0
0
0

1

0

0

0
0
0

1
0
1
0
1

+
+
+
+

1 byte
1 byte
1 byte

2
3
4

1 byte

5

Table 1 "C-Bus" Address/Commands

I

In C-BUS protocol the audio processor is allocated
Address/Command (AlC) values 10H to 13H• Configuration, Txt
RX Gains, Powersave assignments and data requirements are
given in Table 1. Each instruction consists of an Address!
Command (AlC) byte followed by a data instruction formulated
from the following tables.
Commands and Data are only to be loaded in the group
configurations detailed, as the C-BUS interface recognizes the

first byte after Chip Select (logic "0") as an Address/Command.
Function or Level control data, which is detailed in Tables 2, 3,
4 and 5, is acted upon at the end of the loaded instruction. See
Timing Diagrams, Figures 5 and 6.
Upon Power-Up the value of the "bits" in this device will be
random (either "0" or "1"). A General Reset Command (01 H)
will be required to set all MX826 registers to DOH'

Configuration Command (Preceded by AlC
Se~1ttg;
. . '.~i!"B#S

TX Gain & Mod. Command (Preceded by AlC 11,)

"'. ','

. M$Ii'

'.BIt,.,

J,

6
, '0
'1

5

o
1

4

o

.t

Transmitted First
Sw8 Sidetone
Sidetone Bias
Sidetone Enabled
Sw617 RX Audio
Ear Enabled, LS Bias
LS Enabled, Ear Bias
Sw5 Expandor
Expander By-Pass
Expander Route
Sw4 Tx/RX Audio
Tx Store/Audio
Rx Store/Audio
Sw3 Dev. Limiter
Dev. Limiter Bypass
Dev. Limiter Route
Sw1 Mic. Inputs
Mic.llnput
Mic.2lnput
Sw2 TX Function
DTMFln
Compressor Bypass
Compressor In
Play In

Table 2 Configuration Commands
Page 324

10,)

"SeJfli«!),;,:,,'

'Citi#rl'ri!~~}: "
Transmitted First
Tx Mod. Level
OFF (Low Z to VBIAS)
-5.6
-5.2
-4.8
-4.4
-4.0
-3.6
-3.2
-2.8
-2.4
-2.0
-1.6
-1.2
-0.8
-0.4

o

TX Input Gain
-2.65
-2.05
-1.50
-0.95
-0.45

o

0.45
0.85
1.25
1.65
2.05
2.40
2.70
3.05
3.35
3.65

Table 3 TX Gain & Mod. Commands

MX-COM, INC.

MX826

The Controlling System ..... .
RX Gain & Vol. Command
Setting
USB
7
6
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
0

0
1
1
1
1

3

2

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0

1

0
1
1
1
1

5

4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
0
1
1
0

0
1
1
0
0
1
1

1
0
0
1
1
0
0
1
1
0
0
1
1
0

Powersave Command

Gain (dSs)

0
0

1

(Preceded by Ale 12,)

0

1
0
1

1
1

0
1

Control Sits

USB

Transmitted First

Blf7

765

4

321

000

0

0

0

All must be a logic "0"

0

o
o

Powersave Setting
Powersave MXB26
Enable MXB26

1

Table 5 - Powersave Command

RX Input Gain
3.75
4.30
4.BO
5.30
5.BO
6.20
6.55
7.05
7.40
7.BO
8.15
B.50
8.BO
9.10
9.40
9.70

0
1
0
1
0
1
0
1
0
1
0

0

Betting

Transmitted First
RXVolume
OFF (Low Z to VBIAS)
-2B.0
-26.0
-24.0
-22.0
-20.0
-18.0
-16.0
-14.0
-12.0
-10.0
-B.O
-6.0
-4.0
-2.0
0

(Preceded by Ale 13,)

I

Table 4 - RX Gain and Vol. Commands

Reference Signal Levels
%
100

mV
(rms)

kHz

513

9.5

411

7.6

100%
9.5kHz
513mV

r-

90
BO

i

67.4%
6.4kHz

70

346mV

r-

Z

0

~
:>
W
Cl

60

30B

5.7

205

3.B

60.0%
5.7kHz
30BmV

r-

50
40

37.1%
3.52kHz
190mV

24.2%
2.3kHz

30
20

125mV

r103

1.9

10

Maximum
Deviation

1.0kHz
Tone

r17.9%
1.7kHz

12.6%
1.2kHz

92mV

T

SAT Tone
5970kHz
6000kHz
6030kHz

65mV

Sinpo~~9
8kHz
andWBD

Normal
Test

Modulation

T
DTMF

Min.
697Hz

Max.
1633Hz

Figure 4 - Signal Deviation Levels and corresponding TX Mod Outputs with the Mod Level set to OdB

MX-COM, INC.

Page 325

MX826
Control Timing Information
Characteristics

tesE
tesH
tesoFF
teK

tNXT
teH
tel
t eDs
teDH

See Note

"CS-Enable to Clock-High"
Last "Clock-High to CS-High"
"CS-High" Time between transactions
"Clock-Cycle" Time
"Inter-Byte" Time
"Serial Clock-High" Period
"Serial Clock-Low" Period
"Command Data Set-Up" Time
"Command Data Hold" Time

1,2

1
1

Min.

Typ.

Max.

Unit

2.0
4.0
2.0
2.0
4.0
500
500
250
0

/ls
/ls
/ls
/ls
/ls
ns
ns
ns
ns

Notes
1. These Minimum Timing values are altered during operation of the MX812 VSR Codec.
2. Chip Select must be taken to a logic "1" between each individual transaction.

CHIP SElECT
~~

tCSOFF

__________________________

~

\+_____________

~r--l~

~

I

ADDRESS/COMMAND
BYTE

II

FIRST DATA BYTE

NEXT
ADDRESS/COMMAND

BYTE

Inter..IJyte period Iogle level is not important.

Figure 5 - Control Timing Information

SERIAL CLOCK
(from ILC)

COMMAND DATA
(from ILC)

Figure 6 - Control Timing Relationships

Page 326

MX-COM, INC.

MX826

Frequency Responses
10

o
-10
-20

-40

50

100

1000

300

3000

10000
Frequency (Hz)

Figure 7 • Microphone Input Stages ·Combined Low and Hlghpass Filter Frequency Response

Figure 7
Mic.1/2 In to Compression Out

10

5.0V
·10
ElI-20

..'0 ..

Signal Input Level

55.0mVrms

MX826/
Typical Response
Figure 8
Dev limiter In to TX Filter Out
3000

4000

6000

5.0V

10000

Frequency (Hz)

Signal Input Level

55.0mVrms

Rgurf, 8 . Post Deviation Limiter Lowpass Filter Response

Figure 9
RX Audio In to SAT out
5.0V
Signal Input Level

MX-COM, INC.

=

100mVrms

Page 327

I

MX826

Specifications
Absolute Maximum Ratings

Operating Limits

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(Ref Vss = OV)
Sink/source Current
(Supply pins)
(Other pins)
Total Device Dissipation
@TAMB25°C
Derating
Operating Temperature
Storage Temperature

-0.3V to (V DO + 0.3V)
Xtal/clock fXTAL = 4.0MHz

±30mA
±20mA

Audio level OdB ref. = 308mVrms @ 1kHz

800mW max.
10mW/oC
-40°C to +85°C
-55°C to + 125°C

Characteristics

I

V DD = 5.0V

-0.3 to 7.0 V

See Note

Static Values
Supply Voltage
Supply Current
Operating
Powersave
Alias Frequency
On-Chip Xtal Oscillator

Max.

Unit

4.5

5.0

5.5

V

6.5
0.5
63.0

mA
mA
kHz

10.0
10.0
10.0
50.0

MO
kO
VIV
MHz
dB
kHz

20.0

Analog Input Impedances
Mic.1 & 2
Play
Comp In
DTMF In
Dev. Limiter In
(Expanded) Audio In
TX Mix In
RX Audio In

Page 328

Typ.

10.0

R'N
ROUT
Inverter d.c. Voltage Gain
Gain/Bandwidth Product
TX Mix Amp
(Open Loop Gain)
(Bandwidth)

Analog Output Impedances
Pre-Emp Out
TX Mod Out
Expand/Store
LS and Ear Audio
SAT Out
TX Filter Out
Comp Out
Sidetone Out
TXMix (Open Loop)
(Closed Loop)
Switches - ON
-OFF

Min.

500
500
500
500
100
47.0
10.0
100

600
600
600
1.0
1.0
600
600
2.0
6.0
600
1.0

3

10.0

kO
kO
kO
kO
kO
kO
MO
kO

0
0
0
kO
kO
0
0
kO
kO
0
kO
MO

MX-COM, INC.

MX826
Characteristics

See Note

Control Interface Parameters
Input Logic Levels
Logic "1"
Logic "0"
liN (logic "1" or "0")
Input Capacitance
Channel Performances
TX Path
Filter Specifications
Pre-Compression LlHPF Combination
Passband
Slope - below 300Hz
above 3000Hz
TX Gain Pre-Emphasis
Gain at 1.0kHz
Slope (300Hz - 3000Hz)
Post Deviation Limiter LPF
Attenuation Relative to 1.0kHz
3.0kHz - 5.9kHz
5.9kHz - 6.1 kHz
6.1kHz - 15kHz
>15kHz
Analog Signal Input Levels
Mic.1 and 2
Play
DTMF
Compo In
TX Mix In
Analog Signal Output Levels
Pre-Emp Out
TX Filter Out
TX Mod Out
Sidetone Out
Path Gains/Levels
TX Gain - 11H
Nominal Adjustment Range
Error of any Setting
Dev Limiter
Threshold
Symmetry
Mod Level Attenuation - 11 H
Nominal Adjustment Range
Step Size
Error of any Setting
Overall
TX Distortion
TX Hum and Noise
RX Signal Path
Filter Specifications
RX Gain De-Emphasis
Gain at 1.0kHz
Slope (300Hz - 3000Hz)
RX Channel Bandpass
Slope - below 300Hz
above 3000Hz

MX-COM, INC.

Min.

Typ.

Max.

Unit

1.5
1.0
7.5

V
V
IlA
pF

3.5
·1.0

300
+24.0
-24.0

3000

Hz
dB/oct.
dB/oct.

0
6.0

dB
dB/oct.

40 log(f/3000)
35.0
40 log(f/3000)
28.0

dB
dB
dB
dB

2
2
2
2
2

0
0
0
0
0

dB
dB
dB
dB
dB

2
2
2
2

0
0
0
0

dB
dB
dB
dB

-2.65
-0.2

3.65
0.2
1086
7.0

-5.6
0.2
-1.0

mVp-p
%

0.4

0
0.6
1.0

dB
dB
dB

-40.0
-40.0

-32.0
-20.0

dBp
dB

3000

dB
dB/oct.
Hz
dB/oct.
dB/oct.

3.75
-6.0
300
+24.0
-36.0

dB
dB

Page 329

I

MX826
Characteristics
RX Signal Path (cont'd)
Analog Signal Levels
RX Audio Input Level
LS/Ear Audio Output Level
Path Gains/Levels
RX Gain - 12H
Nominal Adjustment Range
Error of any Setting
Volume - 12H
Nominal Adjustment Range
Step Size
Error of any Setting
Overall
RX Distortion
RX Hum and Noise
SAT Signal Path
Bandpass Filter
Frequency Range
Gain

See Note

Min.

Typ.

Max.

-7.0
0

2
2

5970
19.0

dB
dB

9.70
0.2

dB
dB

2.0

0
2.5
1.0

dB
dB
dB

-40.0
-40.0

-32.0
-34.0

dBp
dB

20.0

6030
21.0

Hz
dB

3.75
-0.2
-28.0
1.5
-1.0

Unit

Notes
1. Serial Clock, Command Data and Chip Select inputs.
2. Levels equivalent to ±3.0kHz deviation with the settings below:
TX Gain = OdB
Mod Level = OdB
RX Gain = 7.05dB
Volume=OdB
Other levels can be achieved by adjusting the above variable gain blocks in accordance with
Tables 1 to 5.
3. Recommended load >10.0k,Q.

I

Page 330

MX-COM, INC.

MX·~M,IN~.

MX836
C·BUS

Preliminary Information

COMPATIBLE

RADIOCOM 2000 SYSTEM AUDIO PROCESSOR
Features
• Full-Duplex Audio Processing for R2000
Cellular System
• On-Chip Speech and Data Facilities

• Access to External Processes
- Compression - Expansion
- Signaling/Data Mixing
- VSR Codec (StoreIPlay)

- TXlRXlData Filtering & Gain
- Pre-lDe-Emphasis - Deviation Limiter

• Serial JLProcessor Interface
• TX and RX LF-Data Paths
• MSK and (50 Baud) LF-Data Facilities

MX8360W
28-pin SOIC

• Hands-Free Compatibility

MX836J
28-pin COIP

I

• Powersave (Low-Current) Settings

:JS SYS

V (S ~ A ) .JiQC SS::H JJS

TO
COMPRESSOR

~"\

,

A \ lS

[>~__~M~ic~.l~r---~-CEtI~~iArno-----~TXMODOUT
Mic.2
[> \0---"""'-'-"--1
v
\

DTMF (TX)

X \G

-W'J~-<

TX
MOD

TXLFDATA IN
LSAUDIOOUT

RX
Jc VQJI---"~,-",-_R_X_A_U_D_IO_I_NI
MSK DATA OUT

EAR AUDIO OUT

MSKIPLAY
o AY

EXPAND! STORE

VSR

hs~";:;-,- - - - - - - - i

CODEC
(MX812)

RADIO'S

HOST

uPROCESSOR
DRAM

Figure 1 - The MX836 R2000 Audio Processor within a Cellular System

MX-COM, INC.

Page 331

MX836
Description
The MX836 is a IlProcessor-controlled full-duplex
audio processor on a single-chip with separate TX, RX
and LF (50 baud) data paths to provide all the filterl
gain/limiting functions necessary to pre-process audio,
data and signaling in the Radiocom 2000 (R2000)
Cellular communications system.
Selectable inputs available for transmission include
a choice of two microphones, DTMF/signaling or MSKI
data, with access, in this path, to external voice
compression circuitry. Operationally the TX path
provides input gain/filtering, pre-emphasis, a deviation
limiter and TX Modulation Drive controls. Available to
the transmit function is a separate path to process LF
system control data for amalgamation externally with
TX voiceband audio.
The RX path consists of an input gain/de-emphasis/
filter block for voice and data, inputs from an external

audio expansion system and output gain controls driving
loudspeaker and earpiece circuitry.
In the RX path LF data signals are separated from
the incoming audio via an LF filter and made available
at a separate pin for use by the system IlProcessor
Unique to the MX816/826/836 cellular audio
processors is the ability to route audio (TX or RX) to an
external Voice Store and Retrieve (VSR) device such
as the MX802 or MX812, thus providing the radio
system with a voice answering and announcement
facility using external DRAM.
The MX836, a low-power CMOS device, which
reduces the amount of microcircuits and components
required in a cellular audio system by providing more
functions on a single chip, is available in 28-pin plastic
small outline (S.O.I.C.) surface mount and cerdip OIL
packages.

Xtal: The output of the on-chip clock oscillator.

I

2

Xtal/Clock: The input to the on-chip clock oscillator. A Xtal or externally derived clock (fXTAL) should
be connected here. Note that operation of the MX836 without a suitable Xtal or clock input may
cause device damage. See Figure 2 (notes).

3

Serial Clock: The "C-BUS" serial data clock input. This clock, produced by the IlController, is used
for transfer timing of commands and data to the MX836. See Timing Diagrams.

4

Command Data: The "C-BUS" serial data input from the IlController. Data is loaded to the MX836
in 8-bit bytes, MSB (B7) first, and LSB (BO) last, synchronized to the Serial Clock. See Timing
Diagrams.

5

Chip Select (CS): The "C-BUS" data loading control function. This input is provided by the
I1Controller. Data transfer sequences are initiated, completed or aborted by the CS signal. See
Timing Diagrams.

6

VBIAS: The internal Circuitry bias line, held at VDd2 this pin must be decoupled toV SS. See Figure 2.

7

RX Audio In: Normally taken from the radio's discriminator output. This input has a 1MQ internal
resistor to VBIAS and requires connecting via a capacitor.

S

Expand/Store: A common output that can be used as either an input to an external audio
expandor or the input to a voice storage medium such as the MX812. Components relevant to the
external device requirements should be used at this output. See Figures 2 and 4.

9

(Expanded) Audio In: The audio input, via SW5, from an external expander or audio mixing
function. This input has a 1MQ internal resistor to VBIAS and requires connecting via a capacitor. See
Figures 2 and 4.

10

TX Mod Out: The composite TX audio output to the transmitter modulator from a variable
attenuation stage (11 H)' This output is set to VBIAS via an internal 1MQ resistor when set to
Powersave or OFF.

11

LS Audio Out: An audio output of the RX Path (or audio selected by SW2 and SW4 Figure 4) for a
loudspeaker system. Available for handsfree operation this output is controlled by the RX Gain and
LS Volume Command (12H) and is internally connected to VBIAS when not required. A driver amplifier
may be required at this output.

Note: To minimize aliasing effects, lowpass filtering may be required at the inputs to this device (especially those
supplied from switched-capacitor-type devices) to ensure the input spectrum is kept below 63kHz.
Page 332

MX-COM, INC.

MX836

12

Ear Audio Out: An audio output of the RX Path (or audio selected by SW2 and SW4-Figure 4),
available as an output for a handset earpiece. Separate from the LS Audio Out function, this output
is controlled by the LF Data Gain and Ear Volume Command (13 H) and is internally connected to
VBIAS when not required. A driver amplifier may be required at this output.

13

TX LF Data Out: The output, if required, to the TX Modulator, of LF (50 baud) filtered and leveladjusted digital data.

14

Vss: Negative supply. Signal ground.

15

TX LF Data In: The input of LF (50 baud) digital data for transmission, from an external modem.
This input has an internal 1Mil resistor to VBIAS and should be connected via a capacitor.

16

RX LF Data Out: The output, to a 50 baud modem, of the received, filtered, LF data. This pin is
used with the 50 Baud Data, Slicer In pins and external components to filter and limit the received
LF data. See Figure 4.

17

Slicer In: The input to the data slicer. Employed as shown in Figure 4 to filter and limit the received
LF data.

18

RX 50 Baud Data Out: The output of the received 50 baud data. See Figures 2 and 4.

19

MSK Out: The de-emphasized RX audio output available for access to the received MSK data.
This output could be directed to an MSK Modem such as the MX439.

20

Deviation Limiter In: Input to the on-chip deviation Limiter. This input should be a.c. coupled to
the Pre-Emphasis Out pin. The a.c. coupling is required to achieve the best possible symmetry of
limiting as this input has a 1Mil internal resistor to VBIAS. See Figure 2.

21

Pre-Emphasis Out: Audio output from the TX Input Gain/Pre-Emphasis function. This output
should be a.c. coupled to the Deviation Limiter In pin. See Figures 2 and 4.

22

DTMF In: To introduce DTMF type audio, at a suitable level for transmission, to the TX Path,
controlled by SW2 (Configuration Command (10 H)). This input has an internal 1Mil resistor to V BIAS
and should be connected via a capacitor.

23

Compression In: The audio input from an external compression system. This input has an internal
1Mil resistor to VBIAS and should be connected via a capacitor.

24

Compression: The output to an external audio compression system. Currently available
compressor/expanders have Op-Amps incorporated. The compressor can be bypassed by SW2.

25

Mic.2 In:

26

Mic.1 In:

27

MSKIPlay In: The TX MSK data input via SW2. This can also be used to input (replay) from a
voice storage device such as the MX812. This "replayed" audio can be sent to RX or TX paths
allowing a MessagingNoice Notepad/Answering facility. Both MX439 MSK Modem and MX812 VSR
Codec outputs can be wired together at this pin (OR'd) if the functions are activated one-at-a-time.
This input has an internal 1Mil resistor to V BIAS and should be connected via a capacitor.

28

V DD : Positive supply. A single +5 volt power supply is required. Levels and voltages within this
audio processor are dependent upon this supply.

TX voice (Mic.) inputs, selectable by SW1 available for handsfree mic.!handset mic.
or any TX audio input. Pre-amplification may be required prior to these inputs. Each
input has an internal 1Mil resistor to VBIAS and should be connected via a capacitor.

C-8US is MX-COM's proprietary standard for the transmission of commands and data between a
JIController and the relevant Cellular IC's. It may be used with any JIController, and can, if desired, take
advantage of the hardware serial liD functions embodied into many types ofJIJlController. The "C-BUS" data
rate is determined solely by the JIController. For further details refer to the DBS 800 System Information
Document.

MX-COM, INC.

Page 333

I

I

MX836
Application Information

I

Cll

L--L

:$: Xl

=::!:C9

XTAUCLOCK
SERIAL CLOCK

COMMAND DATA
CHIP SELECT

VBWS
~ I-__RX:..::.:...A:..::U:::D::;IO::...,::;IN+J

EXPAND/STORE

~ (EXPANDED) AUDIO IN
1)(

MOD OUT

LS AUDIO OUT
EAR AUDIO OUT
1)(

LF DATA OUT

v

28 voo
27 MSKn>lAY

1
2
3
4

25
24
23

5
6
7
8
9
10
11
12
13

MX836

22
21
20
19
18
17

1.0MQ
O.1I1F
O.1I1F
O.1I1F

O.1I1F
O.1I1F
O.1I1F
O.1I1F

Tolerances - Resistors ± 10%

CapaCitors ±20%

~

MIC. 21N
COMPRESS

_(COMPRESSED) AUDIO IN

DTMF IN
PRE-EMP OUT

~

DEV LIMITER IN

*C7

MSKJDATA OUT
RX 50 BAUD DATA OUT
SLICER IN

C14

=*=

,A

'~lV]

RX LF DATA OUT

15

14

C.
Cs
C.
C7

:~

16r-----------~~-+---+

~ L--_ _ _ _ _ _ _--l
R,
C,
C,
C,

~ClO

~

IN

26 MIC.l IN

1)(

LF DATA IN

O.1I1F
33pF
O.1I1F
33pF

C.
C.
C 10
C l1

L-

.-

C13

C12
C13

1.011F
O.1I1F
O.1I1F
4.032MHz

C,.
X,

Figure 2 - Recommended External Components
1. Xtal/clock operation
Operation of any MX-COM IC without a Xtal or clock
input may cause device damage. To minimize damage
in the event of aX talldrive failure, it is recommended
that a current limiting device (resistor or fast-reaction
fuse) is installed on the power supply (Voo)'

2. MSK Modem
The MX439, a general purpose MSK Modem, could be
used with this R2000 system Audio Processor. The
MX439 is a non-formatted modem, which, with regard
to Xtallclock frequencies and I1Processor interface, is
compatible with both Mobile/Portable and Base Station
applications.

Reference Signal Levels

%
100-

mV

(rmsl
513

kHz

2.5

100%

100%

2.5kHz

2.5kHz
513mV

~3;::'V

I

90-

00-

411

2.0
60%
1.5kHz

308

1.5

205

1.0

103

0.5

70%

';28:::,V

1.75kHz

68%

1.7kHz
349mV

-I"'"
54.4%

395mV

1.36kHz

Limited
Signal

MSK
1200 Hz

2J.9plY

30
20

12%
300Hz

~~r

10
Maximum
Deviation

1.OkHz
Tone

50 Baud

Data

MSK
Mean

MSK
1SOOHz

Figure 3 - R2000 Signal Deviation Levels and corresponding TX Mod Outputs with the Mod Level set to OdB

Page 334

MX-COM, INC.

~

~
~

~~~

~
TOMCO..I..A.TOR

TXMOO OUT

'

......

Vw

!!e!.
TX IF DATA OUT

.•

~ ----------~

-II--I-~-~~-'-'-~

ENPECE

v"
LSALOIOOUf
HANOSFREE
LOl.IJSI'EN(ER

MSK DATA

~

STORENJDIO

s:
><

~

 3333 Hz)
(fin> 3633 Hz)
(fin < 250 Hz)
RX Inverted
Total Harmonic Distortion
Output Noise Level
Passband Ripple (300 - 3033 Hz)
Stopband Attenuation
(fin> 3333 Hz)
(fin> 3633 Hz)

Page 348

V oo=5.0V

-0.3 to 7.0 V

4.5

5.0

4

5.5

Voc

9.0
6.0
1.8

mA
mA
mA
MQ
kQ
MQ
kQ

10
0.5

5

100
70%
30%

2
2
0

2
-2

1,3
2,3
3

5

+2

Voo
Voo

%
mVrms
dB
dB

20
45
42

dB
dB
dB

4
4

%
mVrms
dB

4
50
60

dB
dB

MX-COM, INC.

Highpass Attenuation
(fin < 250 Hz)
TX Clear
Total Harmonic Distortion
Output Noise Level
Passband Gain
(fin =300 - 3033 Hz)
Passband ripple
(fin =300 - 3033 Hz)
Stopband Attenuation
(fin> 3333 Hz)
(fin> 3633 Hz)
(fin < 250 hz)
TX Inverted
Total Harmonic Distortion
Output Noise Level
Passband Ripple
(fin = 300 - 3333 Hz)
Stopband Attenuation
(fin> 3333 Hz)
(fin> 3633 Hz)
(fin < 250 Hz)
Pre-Emphasis
Frequency Response
Gain at 1 kHz
De-emphasis
Frequency response
Gain at 1 kHz

60

1
2

2
2

dB

5

%
mVrms
dB

0
3

dB

2

20
45
42

dB
dB
dB

1,3
2

4
4

%
mVrms

1,3
3
3
3

4

dB
dB
dB
dB

50
60
60

6
10

dB/Octave
dB

-6

dB/Octave
dB

0

Notes:
1. Input signal = 1kHz tone OdB (300 mV rms).
2. Input AC short circuit, audio path enabled. Measured in 30 kHz band.
3. Due to frequency inversion (and pre- and de-emphasis), this refers to deviation from expected ideal
response.
4. Standby occurs in RX with RX Audio Enable = 0, RX Audio Enable = 1, and PTL = 1.
5. TX Audio Out and RX Audio Out only.

MX-COM, INC.

Page 349

I

MX014 APPLICATIONS

Cf

TX ChameI

R2

-j 1-.1'11--..............,......."'+...

TX

I ____________________________________________________

~

8fAS

C3

I

I
I
I
L _______________________________________________ J I

On-chip functions are contained within the dotted lines.

I

Figure 3 - Voice Privacy Application (Add-on)

Cf

R9

'IX
I

I
I
I
I

I----------------------------------------------------~

~

_____________________________________________ J

On-chip functions are contained within the dotted lines.

Figure 4 - Voice Processing Application (OEM)
Page 350

MX-COM, INC.

MX214
MX224

MX·~M,IN~.
VARIABLE SPLIT BAND INVERTER
FEATURES:

APPLICATIONS:

•
•
•
•
•
•

• Mobile Radio Voice Security
• Cellular Telephone Voice
Security

CTCSS Highpass Filter
Good Recovered Audio Quality
Fixed and Rolling Code Modes
Serial/Parallel Loading Options
32 Programmable Split POints
Half-Duplex Capability

MX224J (CDIP)
MX224P (PDIP)
24 pins

MX214J (CDIP)
MX214P (PDIP)
22 pins

MX214LH
MX224LH
(24p PLCC)

I

AROUND (PS)ITHRQUGH

XTAL!CLOCK

LOAD/LATCH
SERIAL CLOCK

INPUT LATCHES

ENABLE/MUTE

ENIMUTE

CLEAR/SCRAMBLE

CLEAR/SCRAMBLE

Rx/TX,ISEAfPARI,--

Rx/TX

A,
A,

-VOD

- V S1AS

ROM

- vss

A,
A,
Rx/Tx

ISERIAL DATA IN)

Ck,

Ax IN

Rx OUT
Tx IN

Fig. 1 Functional Block Diagram

MX-COM, INC.

Page 351

DESCRIPTION:
The MX214/MX224 Variable Split Band Inverters are designed for mobile and cellular radio voice security applications.
Digital control functions are loaded serially into the MX214. The MX224 is loaded in parallel.
The MX214/MX224 ICs include a highpass filter which rejects subaudio frequencies, ensuring full CTCSS compatibility. This CTCSS filter is not included on the earlier-generation MX204 VSB Inverter.
The MX214/ MX224 splits the voiceband (300-2700 Hz) into upper and lower subbands, and inverts each subband
about itself. The "split point" (defined as the frequency where the voice band is subdivided), is externally programmable to
32 distinct values in the 300 to 3000 Hz range. In the "fixed code" mode, a single split point is used. Fixed mode operation
nets approximately 4 mutually exclusive voice channels.
In "rolling code" mode, the split point is changed many times per second, usually under control of a microprocessor.
Rolling code scrambling requires synchronization, offers higher security than fixed code operation, and provides a much
greater number of mutually exclusive secure channels.
The MX214/224 offers a recovered audio product close to that of a telephone. The on-chip "Mute" function is useful
when implementing rolling code continuous synchronization schemes. "Powersave" and "Clear/Scramble" controls are
also included on-chip. Timing and filter clocks are derived internally from an on-chip 1 MHz reference oscillator driven by a
1 MHz crystal or clock pulse input.

APPLICATIONS INFORMATION:
Recommended external component connections are shown in Figure 2. In "Scramble" mode, split point frequencies
are selected and set in accordance with the ROM address code present at the inputs Ao to A4(see Table 2). In "Clear"
mode, both the Upper and Lowerband filter limits are used (see Figures 5 or 6), the carrier frequencies are turned off, and
the balanced modulators are bypassed internally. The Low Band audio is removed from the output signal prior to
summing.
The MUTE function disables the MX214/224's audio outputs to allow periodic transmission of synchronization data. A
logic "0" atthis input isolates the device while leaving the audio input and output pins at bias level (see Table 1). When the
MX214/224 is in POWERSAVE mode, audio signals may be hardwired around the device since the input and output pins
are open circuit (see Table 1).

Component Connections

I

Fig. 21al Serial Load Options
Component References
C,

C,

C.

Ix IN

-+-It-t---='--.-j

Component

Rx IN

I

118) 22

AI

1M

(16) 20 Tx OUT

R2
C,
C2

Selectable
33p
68p

C3

15n

C4
C6

15n
1.0jJ
t.OjJ

C,
Ca
XI

lMHz

(15) 19 Rx OUT

5 123)

(141 18 N/C

' - - - - - - - \ 6 (24) MX214J,P (13) 17!--V"""'--_ _ _ _
XTALIClOCK
7 (1J (MX214LH)n2J 16
""XT"'Al':--_ _
12l

-+

C~

--Ia

='~~"'~""':""~Nc----I""'9
N/C
N/C

(3)
C,

10
a.;,"~

Unit Value

\17) 21!--V""",,-,- - - - - ,

_ _ _..;;'2;,j

N/C

1.0jJ
1.Of.!

Tolerance Resistors ± 10%
Capacitors ± 20%
C5 and Cs are coupling capacitors
between filter outputs and
balanced modulator inputs.

Fig. 21bl Parallel Load Options
XTALICLOCK

~x,

XTALICLOCK
XTAL

c.
t---+---i'\--T, IN

PROGRAMM1NG{
::2
INPUTS
c,

A,

C,

....------II---R"N

A,
Ax/Ix

17!-V-"""'-"-----.

CLEAR/~

ENABLE/rVi'D'TE
LOAD/lATcH

AROUND/~

16

15 f.!R"","'OU"'-T_ _ _--.-

"

14 N/C

12

R,

CT

XTAL

fC'
V"

Tx OUT

10

R,

Recommended XtBl ciicuitry-

13
C,

Page 352

MX-COM, INC.

MX214/224 PIN FUNCTION TABLE
PIN NUMBER

FUNCTION

214

224

214

224

J,P

J,P

LH

LH
Xtal/Clock: Input to the clock oscillator inverter. A 1 MHz xtal input or externally
derived 1 MHz clock is injected here.

7

8

2

g

2

3

Xtal: Output of the clock oscillator inverter.
Serial Data Input: This pin is used to input an a-bit word representing the digital
control functions. This word is loaded using the serial data clock and is input in the
following sequence: MUTE, CLEAR, RxITx, Ao, A 1 , A2 , A 3 , A 4. The load/latch pin is
operated on completion. Reference the timing diagram in Figure 7.

3
4
5

3
4
5

6
7

6
7

8

8

13

8

A4l Programming Inputs: In parallel mode, these five digital inputs define the
A3 split point frequency. Each of the 5 input pins have a 1M!l internal pullup
A2 resistor. See Table 2 for programming information.
A1 ;

AoJ

RxITx: This digital input selects the Receive or Transmit paths and configures
upperband and lowerband filter bandwidths while setting the CTCSS highpass filter
position on the signal path. See Table 1 and Figures 5 and 6. 1MH internal pullup
resistor (Rx).
Parallel/Serial: This pin must be connected to Vss for serial loading. Internal 1MH
pullup resistor.

g

g

Clear/Scramble: This digital input puts the device into "Clear" or "Scramble" mode
by controlling the application of carrier frequency to the Upper and l.ower band
balanced modulators. In "Scramble" mode, the balanced modulator carrier frequency values are selected by the split point address Ao-A4 (Table2). In "Clear"
mode, the carriers are disabled and the balanced modulators are bypassed internally,
i.e. the lower band signal is not added to the output signal. 1MH internal pullout
resistor (Clear).

10

10

Enable/Mute: This digital function is used to disable Receive or Transmit signal paths
for rolling code synchronization while maintaining bias conditions. Synchronization
data can be transmitted during the Mute periods, as is done in the MX1204 VSB
Scrambler module. Internal 1MO pullup resistor (Enable).

14

15

2

10

11

MX-COM, INC.

11

Serial Clock Input: This is the externally applied data clock frequency used to shift
input data along on devices wired in the Serial loading mode. One full data clock cycle
is required to shift one data bit completely into the register. See Timing Diagram
(Figure 7). 1MH internal pullup resistor.

11

Load/Latch: This pin controls the loading of the a digital function inputs (ENABLE,
CLEAR, RxITx, Ao-A4) into the internal register. When this pin is at logic "1," all eight
inputs are transparent and new ~acts directly. For controlled changing of parameters in the parallel mode, Load/Latch must be kept at logic "0" while a new function is
loaded, then strobed 0-1-0 !~~h the inputs in. For seriall~g, the serial data
should be loaded with Load/Latch at logic "0" and then Load/Latch strobed 0-1-0 on
completion of data loading. Internal 1MO pullup resistor (Load). See Figure 7.

Page 353

I

MX214/224 PIN FUNCTION TABLE
PIN NUMBER

I

FUNCTION

214

224

214

224

J,P

J,P

LH

LH

16

12

12

12

Powersave: This digital input is used to place the MX214/224 into Powersave mode,
where all parts of the device except for the 1 MHz oscillator are shut down. All signal
input and output lines are made open circuit, free of all bias. This allows signal paths
to be routed externally around the device, while reducing current consumption. A
logic "0" at this input enables the device to work normally as shown in Table 1. Internal
1MO pullup resistor.

17

13

13

13

Vss: Negative Supply (GND).

18

14

14

14

Internal Connection: This pin is internally connected. Leave open circuit.

19

15

15

15

Rx Output: This is the processed received audio signal output. This pin is held at a
DC "bias" voltage for all functions except Powersave. This buffered output is driven by
the Summing circuit in the Rx mode. Signal paths and bias levels are detailed in Table
1 and Figure 6.

20

16

16

16

Tx Output: This is the processed audio output for the transmission channel. This pin
is held at a DC "biaS' for all functions except Powersave. This summed and buffered
signal is passed through the CTCSS High Pass Filter to the output pin in the Tx mode.
Signal paths and bias levels are detailed in Table 1 and Figure 5.

21

17

17

17

V BIAS: Normally at Vool2, this pin requires an external decoupling capacitor (C 7 ) to
Vss·

22

18

18

18

Rx Input: This is the analog received audio signal input. This pin is held at a DC "biaS'
voltage by a 300 Kohm on-chip bias resistor which is selected for all functions except
Powersave. It must be connected to external circuitry by capacitor C3 (See Figure 2).
This input is routed through the CTCSS High Pass Filter in Rx mode to remove
subaudio frequencies from the voiceband. Signal paths and bias levels are detailed in
Table 1 and Figure 6.

1

19

19

19

Highband Filter Output: The output of the Input Filter of the Upperband limit. The
RxlTx function sets the lowpass filter at 3400 Hz or 2700 Hz respectively. This output
must be connected to the Highband Balanced Modulator input via capacitor Cs (See
Figure 2).

2

20

20

20

Highband Balanced Modulator Input: The input to the Balanced Modulator of the
Upperband limit. This input must be connected to the Highband Filter Output via
capacitor Cs (See Figure 2).

3

21

21

21

Lowband Balanced Modulator Input: The input to the Balanced Modulator of the
Lowerband limit. This input must be connected to the Lowband Filter Output via
capacitor C6 (See Figure 2).

4

22

22

22

Tx Input: This is the analog "Clear" audio input for the VSB scrambler. This pin is held
at a DC "biaS' voltage by a 300 Kohm on-Chip bias resistor, which is selected for all
functions except Powersave. It must be connected to external circuitry by capacitor C4
(See Figure 2). This input, in the Tx mode, is connected to Upper and Lowerband
input filters. Signal paths and bias levels are detailed in Table 1 and Figure 5.

Page 354

MX214/224 PIN FUNCTION TABLE
FUNCTION

PIN NUMBER
214
J,P

224
J,P

214

224

LH

LH

5

23

23

23

Lowband Filter Output: The output of the Input Filter of the Lowerband limit. The Rx!
See figures 5 and 6. This
output must be connected to the Lowband Balanced Modulator Input via capacitor C 6
(See Figure 2).

iX function determines which filter is used (Filter 1 or 2).

24

6

24

24

Voo: A single

+ 5V supply is required.

Note: Pins 10,11, and 12 on the MX214J and MX214P are not connected. Pins 4,5,6,7 and 9 on the MX214LH are not
connected.

MX214/224 TRUTH TABLE

Rx/Tx
Rx Path

R"/Tx

=0

MUTE

=0

POWERSAVE

Enabled

Disabled

Disabled

Disabled

Bias

Bias

Bias

High Impedance

Disabled

Enabled

Disabled

Disabled

Bias

Bias

Bias

High Impedance

RxOut Level
Tx Path

=1

Tx Out Level

TABLE 1 FUNCTIONS INFLUENCING SIGNAL PATHS

APPLICATIONS INFORMATION
The term "MX214" can be taken to mean MX214 or MX224.
Audio Quality
AMPLITUDE
CONTROL

(OPTIONALI

Fig. 3

PRE·EMPHASIS

MX214

FREOUENCY
INVERTER

Tx

MX214

Rx

FREQUENCY
INVERTER

DE-EMPHASIS

AMPLITUDE
CONTROL

(OPTIONAL!

Recommended Basic Communication Audio System Layout

Figure 3 shows the recommended basic audio system layout using added pre· and deemphasis circuitry to maintain good
recovered speech quality. In the Transmit mode, Do Not preemphasise the audio output of the MX214. In the Receive mode,
deemphasis should be used after the MX214.

MX·COM, INC.

Page 355

I

PRE-EMPHASIS

(ADDITIONAL)

MX214

DE-EMPHASIS PRE-EMPHASIS

FREQUENCY (ADDITIONAL!
INVERTER

Tx

MX214

DE-EMPHASIS

AMPLITUDE
CONTROL

FREQUENCY
INVERTER

(FITTED)

(OPTIONAL!

Rx

,------,

(FITTED)

Fig. 4 Recommended Basic Radio Communication Audio System Layout
Figure 4 shows the recommended basic audio system layout if it is necessary to install the MX214 within a radio having preand deemphasis circuitry as a standard. This is where post-emphasis access is not possible in the transmitter.

Ck3

Ck3

TxOUT
Tx IN

---~--4

BIAS

Ck.

I

Fig. 5

SCRAMBLE

BIAS

Basic Tx Path

During the Transmit function the Low Pass and CTCSS filters are configured automatically as shown in Figure 5, with cut-off
frequencies (-3dB) indicated.

Ck3

Rx IN

-,.....~.l'Jr-T----,

Rx· MUTE
BIAS

BIAS

Fig. 6 Basic Rx Path
During the Receive function the Low Pass and CTCSS filters are configured automatically as shown in Figure 6, with cut-off
frequencies (-3dB) indicated.

Page 356

MX-COM, INC.

MX214/224 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is
not implied.
Supply voltage
- 0.3V to 7.0V
Input voltage at any pin (ref. Vss = OV)
- 0.3V to (Voo + 0.3V)
Sink/source current (supply pins)
±30mA
±20mA
(other pins)
Total device dissipation @ 25°C
800mWMax.
Derating
10mWrC
- 30°C + 85°C (Ceramic) .
MX214J/224J
Operating temperature range:
MX214P/214LH/224P/224LH
-30°C + 70°C (Plastic)
MX214J/224J
- 55°C to + 125° (Ceramic)
Storage temperature range:
- 40° to + 85°C (Plastic)
MX214P/214LH/224P/224LH

Operating Limits:
All characteristics measured using the following parameters unless otherwise specified:
Voo = 5.0V, Tamb = 25°C, Fclk = 1.0MHz, Audio Level Ref: OdB = 775 mVrms.

Characteristics

See Note

Min

Typ

Max

Unit

4.5

5
8
1.2

5.5

V
rnA
rnA

Static Values
Supply Voltage
Supply Current (Enabled)
Supply Current (Powersave)

Analog Input Impedances
TXllnput (Enabled)
TXlRx Input (Powersave)
Balanced Modulator

100

k.!1
M.!1
k.!1

40

Analog Output Impedances
Rx Output (Tx Mode)
Rx Output (Rx Mode)
Rx Output (Powersave)
Tx Output (Tx Mode)
Tx Output (Rx Mode)
Tx Output (Powersave)
Input LPF

100
2
2
100

k.!1
k.!1
M.!1
k.!1
k.!1
M.!1
k.!1

Digital Values
Digital Input Impedance

100

k.!1

Dynamic Values
Input Logic '1'
Input Logic '0'
Xtal/Clock Frequency
Analog Input Level
Carrier Breakthrough
Baseband Breakthrough
Filter Clock Breakthrough
Output Noise
MX-COM, INC.

3.5
1.5

+6

-18
1,2or3
1,2, or 3
1,4

-55
-33
-50
-45

V
V
MHz
dB
dB
dB
dB
dB
Page 357

I

MX214/224 ELECTRICAL SPECIRCAnONS (cont)

Characteristics

See Note

Passband Characteristics
Clear Mode

7

Min

o

Passband Gain
Output Lower 3dB Point (Rx or Tx)
Output Upper 3dB Point (Ax or Tx)
Scramble-Descramble

Received Signal Passband Gain
Received Signal Lower 3dB Point
Received Signal Upper 3dB Point
Transmitted Signal Lower 3dB Point
Transmitted Signal Upper 3dB Point
~TCSS (Highpass

300
3400
5

o

6

400
2700

300
3400

Max

Unit

dB
Hz
Hz

dB
Hz
Hz
Hz
Hz

Filter)

-3dBPoint
Passband Gain
Stopband Attenuation at f < 250 Hz

I

lYP

300

o

40

Hz
dB
dB

Timing (Figure 7)

Serial Mode Enable Set Up (tsMS)
Serial Clock 'High' Pulse Width (tPWH)
Serial Clock 'Low' Pulse Width (tpwd
Data Set Up Time (tos)
Data Hold Time (t oHS)
Load/'GiiCii Set Up Time (tLd
Load/Latch Pulse Width (tLLW)
Data Set Up Time(tosp)
Data Hold Time (t OHP)

250
250
250
150
50
250
150
150
20

ns
ns
ns
ns
ns
ns
ns
ns
ns

Notes: 1. Measured at the output of a single device.

2.
3.
4.
5.

TxMode.
RxMode.
With input A.C. short-circuited to Vss.
Measured at the output of a receiving device in a scrambler-descrambler system with a transmission channel having a flat amplitude response and a bandwidth of 300Hz to 3400 Hz and measured relative
to the input signal at the transmitting device.
6. Excluding split point ± 150 Hz.
7. Measured at the Rx or Tx output pin of a single device.

Page 358

MX-COM, INC.

Serial Loading

~
~:,------------------I.'I-----------I
/I

PARALLEl/SERIAL _ _ _

14--- tSMS
I

SERIAL

---.a

..-...- t pWH ---'

I

I

I

CLOCK
I

: - t DS - :

OA~~R:~~UT "'XX""""XXX"""'""""X
I

_

I

I

:"-t

OHS

1st bit:
ENABLE

I

~tPWl-.j

---ao1

"X1..__-;:2c;-;"d:-;b-;:-"_ _ _v;;;t(
I -

~

CLEAR

________

LOAD/LATCH

~'h

bl'

~

XXXXXXX>
tLL----a.I

~'/r----J~tllW-~'-r4
I

Parallel Loading

LOAD/LATCH

PARALLEL

--------~;---\,'------------l
,,
,
.

I

________________

DATA INPUTS

NOTE: For 'Serial Load' devices the data loading sequence is: -

~r'''i
'1

-

;--""' ~

(\1..._______ 1

Enable- Clear - Ax/TX - Ao - A, - A 2 -A 3 -A4

Fig. 7 Loading Timing Diagram

I
ROM Address

Split Point
Hz

Low Band
Carrier, Hz
fe,

High Band
Carrier, Hz
fe,

ROM Address

A.-A.

A.-A.

Split Point
Hz

Low Band
Carrier, Hz
fe,

High Band
Carrier, Hz
fe,

00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111

2800
2625
2470
2333
2210
2100
2000
1909
1826
1750
1680
1555
1448
1354
1272
1200

3105
2923
2777
2631
2512
2403
2304
2212
2127
2049
1984
1858
1748
1655
1572
1501

6172
6024
5813
5681
5555
5494
5376
5263
5208
5102
5050
4950
4807
4716
4629
4587

10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

1135
1050
976
913
857
792
736
688
636
591
552
512
471
428
388
350

1436
1351
1278
1213
1157
1094
1037
988
936
891
853
813
772
728
688
650

4504
4424
4347
4310
4273
4166
4132
4065
4032
3968
3937
3906
3846
3816
3787
3731

Table 2

ROM Address Programming Table

MX-COM, INC.

Page 359

MX·~M,IN~.

MX118

FULL-DUPLEX SCRAMBLER FOR CORDLESS TELEPHONES

Features
•
•
•
•
•
•

Full-Duplex Audio Processing
On-Chip "Brick-wall" Filters (300-3000 HZ)
Low Voltage C M O S , " _ '. "
High Baseband and Carrier,.R~tk)ri .'
Excellent Audio Quality":"
ECPA* Qualified ¥~ic,,".Ftrotection

"

AppJi~;.9n~ _ "J,<"
'

MX118P
(16 pin PDIP)

• Cordl.ass feleD.h~n~s &'.Wireless PBXs
• Battery p,?wete(f Portability
.~::(

,. />'

Description

I

MX118DW
(SOIC-16)

The MX118 isa full-duplex frequency inversion scrambler that secures cordless telephone conversations. The
two audio paths, C1 and C2, are identical and independent. Each consists of the following:
1) A 10th order lowpass filter cut off at 3.1 kHz.
2) A balanced modulator with high baseband and carrier
rejection.

3) A 3.3 kHz inversion carrier (injection tone).
4) A 14th order bandpass filter (300-3000 Hz).
5) Input op-amps with externally adjustable gain.
The MX118 uses CMOS switched-capacitor filter
technology and operates from a single supply in the range
of 3.0 V to 5.5 V. The inversion carrier's frequency and
filter switching clock are generated on-chip using an
external 4.433619 MHz crystal or clock input.

TX Path

t-;.....-01--~1 %

1-1- ••

t

3.3 kHz

RX Path

t-;L----~--fl %

It-----..

Figure 1 - Simplified Signal Paths

• Electronics Communications Privacy Act (Title 18 US Code 2510 et seq.).

Page 360

MX-COM, INC.

MX118

SAL MOD

1 IN
S

ClOUT

+<
...I.
...I.

Q)

MX118
Application Information
5

o
-3
-10

crJ

~ -20
<:

V DO = 3.75 V

·iii
t!l

Audio Input Level

-30

OdB

\

-40

~04---------.------r--.---r--r~~-r-r--------~-----r----r---

0.1

0.2

0.3

0.5

1.0

2.0

3.0

5.0

Frequency (kHz)

Figure 5 - Typical Audio Frequency Response of a Single Scrambled or De-scrambled Channel

System Gains
When calculating the external components for the operation of the MX118 the following should be considered:
a) The input Lowpass Filter has a typical gain of 0.5 dB.
b) The Balanced Modulator has a typical attenuation of 4.0 dB.

I

c) The Output Bandpass Filter has a typical gain of 4.5 dB.

How the Inverter Works
Carrier Frequency minus Input Voice Frequency equals Scrambled Voice Frequency.
(1)

B

(2)
A

Lowpass Filtered Voiceband
for Input to
Balanced Modulator

Input Voiceband Frequencies

Speech Band

1000Hz

(3)

B

(4)
Carrier Frequency (3300Hz)
Generated On-Chip for Input to
Balanced Modulator

3000Hz

2000Hz

A

D
Bandpass Filtered Voiceband
Presented at the Output
after Mixing with the Carrier Frequency
in the Balanced Modulator

1000Hz

3000Hz 3300Hz

1000Hz

Hz

3000Hz

Figure 6 - An Explanation of the MX118 Scramble Operation

Page 364

MX-COM, INC.

MX118

Specifications
Absolute Maximum Ratings

Operating Limits

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(Ref. $8 = OV)
Output sinK/source current
supply pins
other pins
Total Device Dissipation
@ 25°C
Derating
Operating Temperature
Storage Temperature

'!

Static Values
Supply Voltage
Supply Current
Input Impedance, Amplifiers
Output Impedance
C1, C2
Amplifiers
Logic 1 Voltage
Logic 0 Voltage
On-Chip Xtal Oscillator
RIN

Voo = 3.75 V

-0.3 to 7.0 V
-0.3V to (VDO + 0.3V)

Clock = 4.433619 MHz

±30mA
±20mA

Audio Level OdB Ref. = 387 mVrms @ 1 kHz
SOOmW max.
10mW/oC
-10°C to +70°C
-40°C to +S5°C

Noise Bandwidth = 30kHz

3.0
1.0

3.75
3.0
10.0

5.5
4.0

V
mA
MO

n

200
10.0

kn
30% Voo

10.0

ROUT

10.0
10.0
10.0

Inverter Gain
Gain/Bandwidth Product
Dynamic Values (Single Channel)
-16.0
Analog Signal Input Levels
+3
Carrier Breakthrough
-64.0
1,2
-50.0
Baseband Breakthrough
1,2
3299
Carrier Frequency
5
-47.0
Analog Output Noise
-42.0
3
Upper Cut-off Frequency (-3dB)
3100
-1.5
Passband Ripple (300 to 2950 Hz)
+1.5
34.0
30.0
Attenuation at 3.3 kHz
-2
Passband Gain
0.5
+3
Overall Modulated or De-Modulated Channel Response (Scrambler-Descrambler End-to-End)
Passband Frequencies
300
2950
-3
+2
Passband Ripple
Passband Gain @ 1 kHz
4
0
1.0
3.0
Distortion
3.0
26
Low Frequency Attenuation @ 150 Hz
34

MO
kU
VN
MHz
dB
dB
dB
Hz
dB
Hz
dB
dB
dB
Hz
dB
dB
%
dB

NOTES
1. Measured with Input Level -3 dB.
2. Single MOdulated Channel.
3. Short circuit input, any analog output, in 30 kHz bandwidth.
4. Op Amp gain 0 dB.
5. Accuracy dependent on Xtal/clock.
MX-COM, INC.

Page 365

I

MX·~M,IN~.

MX128

Advance Information

LOW COST CORDLESS TELEPHONE SCRAMBLER

Features
•
•
•
•
•
•
•
•

MX-COM MiXed Signal CMOS
Full-Duplex Audio Processing
On-Chip Filters
High Baseband and Carrier Rejection
Two Selectable Clock Inputs
Excellent Audio Quality
Low Voltage, 3-Cell Operation
ECPA* Qualified Voice Protection
MX128P
16 pin PDIP

Applications
• Battery Powered Portability
• Cordless Telephones & Wireless PBXs

Description

I

The MX128 is a full-duplex frequency inversion
scrambler designed to provide secure conversations for
cordless telephone users. The RX and TX audio paths
consist of the following:
1) A switched-capacitor balanced modulator with high
baseband and carrier rejection.
2) A 3.3 kHz inversion carrier (injection tone).

MX128DW
16-pin SOIC

3) A 3100 Hz lowpass filter.
4) Input op-amps with externally adjustable gain.
The MX128 uses mixed signal CMOS switchedcapacitor filter technology and operates from a single
supply in the range of 2.7 to 5.5 volts. The inversion
carrier's frequency and filter switching clock are generated on-chip using an external 10.24 MHz or·3.58/
3.6864 MHz crystal or clock input (selectable).

P1 ~ --Q9---1I~

TX Path

1-1

1 - 1-

••

1 - 1-

••

1
1

VB1AS

3.3 kHz

AX Palh

~ ~ -----IQ9~--11 ~
1-1

VB1AS
Figure 1 - Simplified Signal Paths
'Electronics Communications Privacy Act (Title 18, US Code 2510 et seq.).

Page 366

MX-COM, INC.

MX128

RXIN
RXOUT

RX CHANNEL
14

ClR
XTALJClOCK

2

Xi'AL.
CLOCK SELECT

..

16

~
2

...

9

OV

...

8

10.24/3.58 MHz

15

Veo
VB1AS
Vss

1)( CHANNEL

4

r-----------~~1)(OUT

Figure 2 - Schematic Block Diagram

SEE INSET

BELOW

TXOUT

SEE {
FIG. 4

:rx

AIN AMP OUT
TXIN

N/C
Vss

2
3
4
5
6

MX128

7
8

16 voo
15 ClK SEl
14 ClR
13 RXOUT
12 RX GAIN
11 RXIN
10 NlC
9

I

VOO

I

C1

~

AMP OUT }

SEE
FIG. 4

VB1AS

.I c a
INSET

MX128

Component
Rl
Cl
C2

C3
+--------~ 2

Xl
Tolerances: R

Value
1.0MQ
0.471!F
22.0pF
22.0pF
10.24 MHz

Value
1.0MQ
0.471!F
33.0pF
47.0pF
3.58/3.6864 MHz

=±10%, C =±20%

Note: Xtal circuitry shown is in accordance with MX-COM's Application Note on Crystal Oscillators (see Applications
Section).

Figure 3 - Recommended External Components
MX-COM, INC.

Page 367

MX128

Pin Function Chart

Xtal: This is the output of the clock oscillator inverter.
2

Xtal/Clock: 10.24 MHZ or 3.58/3.6864 MHz or an externally derived clock is injected at this pin. See
Figure 3.

3

No connect.

4

TX Output: This is the analog output of the transmit channel. It is internally biased at V Drl2.

5

TX Gain Amp Output: This is the output pin of the channel 1 gain adjusting op-amp. See Figure 4
for gain setting components.
the analog signal input to channel 1. This input is to a gain adjusting op-amp whose
See Figure 4.

6

7

No

8

I

9

VBIAS: This is the analog bias line at
capacitor. See Figure 3.

10

No connect.

11

RX Input: This is the analog signal input to the receive channel. This
amp whose gain is set by internal components. See Figure 4.

12

RX Gain Amp Output: This is the output pin of the receive channel gain adjusting op-amp. See
Figure 4 for gain setting components.

13

RX Output: This is the analog output of the receive channel. It is internally biased at VDrl2.

14

CLR: A logic 1 on this input selects the invert mode. A logic 0 selects the bypass mode.

15

Clock Select: Selects either 10.24 or 3.58/3.6864 MHz clock frequency. A logic "1" selects 10.24
MHz, and a logic "0" selects 3.58/3.6864 MHz. This input is internally pulled high.

16

V DD : Positive supply of 2.7 V to 5.5 V.

Page 368

op-

MX-COM, INC.

~

BASE

8

~

~

o

TXOUT

TXIN

PORTABLE
RXOUT

RXIN

~IF

l~i

At>---ffi

PREEMP

II

"-

TXOUT

;;?

~

,w"j100k

AF
AMP

MIC.

~

~.1uF

"

TXIN

Note: Components shown set a gain of OdS.
Figure 4 - Block Diagram of a Typical Application of the MX128 (Cordless Phone)

~

~

><
......
N

CD

=.p

MX128

Passband
Figure 5 shows the MX128 overall frequency response of high and low-pass filters followed by a notch
centered at the carrier frequency.

0

-3

<0'

8

Q)

U

:J

I

:!::::

c

0>

0

:::!:

-40

300

Frequency (Hz)

Figure 5 - Overall Frequency Response of the MX128

Page 370

MX-COM, INC.

MX128

Specifications
Absolute Maximum Ratings

Operating Limits

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(Ref. Vss = DV)
Output sink/source current
supply pins
other pins
Total Device Dissipation
@ 25°C
Derating
Operating Temperature
Storage Temperature

=3.3 V

-0..3 to 7.0. V

Voo

-D.3V to (V 00 + D.3V)

TAMB = 25°C

±3DmA
±2DmA

Clock

= 10..24 MHz

Audio Level DdB Ref. = 250. mVrms @ 1 kHz
8DDmW max.
1DmW/oC
-10°C to +6DoC
-4DoC to +85°C

Static Values
2.7
Supply Voltage
Supply Current
Input Impedance
Digital
10.0.
1.0.
Amplifiers
Output Impedancfil.~OUT, TXOUT)
Input Logic 1 Vq~~,· .
70.%
Input Logico.:V~e';:
Dynamic Valdes:·~);·
.
Analog Signal Input ~els~i
-16.0.
Unwanted Modulation Products .
Carrier Breakthrough
Baseband Breakthrough
Carrier Frequency
Analog Output Noise
Cut-off Frequency (-3d B)
Passband Ripple (30.0. to 30.0.0. Hz)
-1.5
Filter Attenuation at 3.3 kHz
Filter Attenuation at 3.6 kHz
-2.0.
Passband Gain
Passband Frequency
30.0.
12
Low Frequency Roll-off «20.0. Hz)
Switched-Capacitor Filter Sampling Frequency
Overall Modulated or De-Modulated Channel ResRonse
Passband Frequencies
30.0.
Passband Ripple
-3
Low Frequency Roll-off «150. Hz)
12
Passband Gain
4
Distortion
1

6.0.

V
mA

30.%

kO
MO
kO
Voo
Voo

5.5

4.0.

10..0.
1.0.

3

-40..0.
-55.0.
-40..0.
3299
1.59
300.0.
+1.5
30.0
45.0.

...

3;0.
300.0.

..

,,'..

'

211.169

30.0.0.
2.0.
0.
2.5

dB
dB
dB
dB
Hz
mVrms
Hz
dB
dB
dB
dB
Hz
dB/oct.
kHz
Hz
dB
dB/oct.
dB
%

SPECIFICATION NOTES
1. Measured with Input Level 0. dB.
2. Single Modulated Channel.
3. Short circuit input, any analog output, in 3D kHz bandwidth.
4. Op Amp gain 0. dB.

MX-COM, INC.

Page 371

-- - - - - - - - -

I

I

Page 372

MX-COM, INC.

Technical Specifications

Section 6:
CVSD CODECS
The following section contains specifications on MX·COM's
CVSD Codecs. A brief description of CVSD begins on the
following page. For an audio delay application, see the Applications section of this catalog.

Device

Description

Page

MX109

Full Duplex CVSD Codec with Serial Control

p. 377

MX609

Full Duplex CVSD Codec with Companding

p. 384
p. 391

MX619/629

Delta Modulation Codec

MX709

Voice Storage and Retrieval (VSR) Codec wI SRAM

p. 403

MX802

VSR Codec with filter and DRAM Control

p.420

MX812

VSR Codec with DRAM Control

p.434

MX-COM, INC.

NEW

I

Page 373

CVSD
CVSD, or Continuously Variable Slope Delta Modulation, is a method by which a voice signal is converted
into a digital data stream for transmission, and then changed back into the analog voice signal for reception.
The digitization of voice signals is used in MX-COM's voice storage and retrieval devices. Advantages to digitization include making encryption easier and being able to multiplex many channels on a single wideband channel with inexpensive digital hardware. The reduction of channel crosstalk and noise interference are also results
of digitization.

VOINICE

~
"..J....__
~
__

DIGITAL

CV_S_D_----,t-n.ILJLJL
_ _ _ _ _ _---\
MODULATOR

CVSD
DEMODULATOR

VOICE
OUT

CVSD Compared to A to 0 and 0 to A PCM Transmission
CVSD and PCM (Pulse Code Modulation) can both be used to digitize voice. The methods of digitization
are, however, quite different.
The PCM system is as follows:
SERIAL DIGITAL

ENCODER

I

SERIAL TO
PARALLEL

DECODER

The following diagram shows a sampling of voice signal level using PCM.

/

VOICE IN

SAMPLE
ENCODER OUT

~,-------,

DECODER OUT

Page 374

MX-COM, INC.

Simple Delta Modulation
PCM can respond to quick level changes between samples, such as an analog signal which has been
analog multiplexed. Delta modulation, however, takes advantage of the fact that voice signals do not change
abruptly. There is usually only a small level change from one sample to the next. A good reproduction of the
original voice waveform can therefore be obtained by transmitting directions that tell whether the output needs
to go "up" or "down" in a given time interval. The following diagram shows a sampling of voice signal level using
delta modulation.

VOICE IN

~

:7
'GO UP'

ENCODER OUT

t

'GO DOWN'

DECODER OUT

o

DO

r

CVSD
Simple delta modulation is most efficient when voice signals are close to full scale input to the modulator.
However, severe distortion occurs when signal levels are very low.
To get around this problem, delta modulation can be combined with "companding" (compressing-expanding)
of the voice input and output. Low level signals are given increased gain during modulation, then restored to
their proper relative levels when demodulated. Because the CVSD companding scheme takes into account the
characteristics of human voice, excellent quality voice transmissions are the end result.

\Tv

\O/V

Voice In ---+I
Compressor

I

(\/\

{\/\

t - -.... Voice Out
Encoder

Decoder

Expander

Simplified Companding
CVSD allows lower data rates than PCM. More channels can therefore be multiplexed at the same bit rate.
The companded PCM used in standard US telephone systems requires a sample rate of 8,000 samples per
second and 8 bits per sample, which is the equivalent of 64kbits per second per channel. With CVSD, transmissions of equal or higher quality are obtained at 32kbits per second. Twice as many channels can be multiplexed
on the same transmission medium. CVSD also suffers from less serious sound degradation in the presence of
digital noise interference.
Digital CVSD is achieved with just one IC package which requires no initial or periodic adjustments. It
includes features such as automatic noise squelch during quiet intervals and a signal that can be used for
automatic gain control. CVSD is excellent for military communications, telephone systems and digital data
transmission systems. It can also be used in commercial radio communications where a number of channels
are multiplexed. Voice and data for storage and display can be intermixed, and security provisions added to
prevent unauthorized interception.
MX-COM, INC.

Page 375

I

Page 376

MX-COM, INC.

MX·~M,IN~.

MX109

Advance Information

LOW VOLTAGE, FULL DUPLEX CVSD CODEC
WITH SERIAL CONTROL
FEATURES
Single Chip Full Duplex CVSD CO DEC
On-chip Input & Output Filters
On-chip Volume Control
3V Operating Voltage
Wide Frequency Reference using
Ceramic Oscillator
• Low Power, Single Supply Analog CMOS

•
•
•
•

•
•
•
•
•

Digital Voice Storage
Multiplexers, Switches & Phones
Time Domain Scramblers
Rechargeable Cell Operation

APPLICATIONS
• Digital Cordless Phones
• Digital PCN/PCS Systems
• Digital Delay Lines

MX109J (CDIP)
MX109P (PDIP)
16 pins

MX109DW
16 pin SOIC

Description
an externally connected crystal or ceramic resonator.
The sampling clock frequency is output for the synchronization of external circuits.
The encoder has an enable function for use in
multiplexer applications. When not enabled the encoder output remains in a high-impedance "tri-state"
mode.
The MX109 is a low-power CMOS device. It is
available in PDIP, CDIP and SOIC packages.

The MX1 09 is a Continuously Variable Slope Delta
Modulation (CVSD) Codec designed for use in cordless
telephones. The device is suitable for applications in
delta multiplexers, switches and phones. Encoder input
and decoder output switched capacitor filters are incorporated on-chip.
Sampling clock rates can be externally injected in
the 8 to 64K bits/second range. The internal clocks are
derived from an on-chip reference oscillator driven by

, - -_ _ ENCODER DATA
ENABLE

ENCODER FEEDBACK
TX AU""D=IO,---+!

ENCODER OUT

vcc_

GND-:=~
--'
XTAL

=

______

~~~~~~~

_____________________

ENCODER
DATA CLOCK

'------------.L:=r~==~==========~----------DECODER
DATA CLOCK

RX AUDIO

1

---<:\.

14----

600n

o

9
 > > > f:2Q
I

I

I

I

I

SERIAL DATA

I I I I I I fooIl:r------- ~~~:~~ ~~~;~E
Page 377

I

MX109
PIN FUNCTION CHART

XtaliClock (liP): Input to the clock oscillator inverter. A 3.58 MHz Xtal input or externally derived
clock is injected here. See Figure 3.
2

Xtal (O/P): The 3.58 MHz output of the clock oscillator inverter.

3

Encoder Data Clock: A logic 110 port. External encode clock input.

4

Encoder Output: The encoder digital output.
made available at the encoder output pin by control of this input. Internal

5

input amplifier I the input to the encoder filter.

6

I

VDJ2, this input requires an external
1DOn. Output channel noise levels will

7

Encoder Input: The analog
coupling capacitor. The source
improve with an even lower source

8

Vss: Negative Supply

9

Bias Out: Normally at VDJ2 bias.

10

Decoder Output: The recovered analog signal is output at this pin. It is the
bandpass filter and requires external components.

11

Decoder Input: The received digital signal input. Internal 1 Mn pullup.

12

Decoder Data Clock: A logic 1/0 port. External decode clock input.

13

Serial Clock: This is the serial clock input.

14

Serial Data: This is the serial data input. Data is loaded in the following order: ALGO, VOL4, VOL3,
VOL2, VOL 1, FORCE IDLE.

15

Serial 110 Enable: A logic 1 applied to this input will enable serial programming.

16

VDD : Positive Supply.

Page 378

MX-COM, INC.

MX109
CODEC INTEGRATION

ANALOG
INPUT
INTERFACE
(BALUN &
BUFFER)

INPUT

ANALOG
OUTPUT
INTERFACE
(BALUN &
BUFFER)

3.58MHz

OUTPUT

3.58MHz

SYNCHRONOUS CLOCK
AND DATA SYSTEM

Figure 2 - System Configuration Showing the MX109

Voo

XTAUCLOCK

I

.J. X 1 A ' 11 1
f
XTAL
--c.,.-::r- ENCODER DATA CLOCK

C~

C1

-VYv

~o ________________-+10
16 ~-=~
15
SERIAL ENABLE
14
SERIAL DATA
-C4

1
2

1
I

3
~~_-'=E"'-'NC><

DECODER DATA
INPUT

------~~

---+:

••_

\'----

•

j

tsu ."
•

tH
DATA TRUE TIME

><'----~

•:
-----+I•

MULTIPLEXING FUNCTION
HIGH Z

I

DATA ENABLE

Figure 4.

-

Codec Timing

Abbreviation
tCH
tCl
tlR
tlF
tsu
tH

Description

1.011s min.

Clock pulse width (logic 0)
Clock rise time

1.01lS min.

Clock fall time
Data set-up time

100ns typo
100ns typo
450ns max.

Data hold time
Data true time
Clock to output delay time

600ns min.

tDR

Data rise time

100ns typo

tDF

Data fall time

100ns typo

tsu + tH
tpco

Xtal input frequency

Page 380

Time

Clock pulse width (logic 1)

1.51lS typo
750ns typo

3.58MHz

MX-COM, INC.

MX109

CODECPERFORMANCE
Output
Gain

o
-10

f

-

'"\

\

-20

dB
-30

-40

=
=

\

=

Input Level
-20dB
Xtal
3.S8MHz
Voo
4V
Data Rate
32kbps -

\.

\

,

=

\~

-50

o

1

3

2

4

5

"

6

Frequency (kHz)

7

8

Figure 5 - Typical Codec Frequency Response

Input Level = -20dB

35

30

~---

_ _ _ _ _ _ _- - - 64kbps

I

25

20

SIN
(dB)

- - - - - - 32kbps

15

10
16kbps

5

SOO

1000

1500

2000

2500

3000

3500

Frequency (Hz)
Figure 6 - Typical SIN Ratio with Input Frequency

MX-COM, INC.

Page 381

MX109
SPECIFICATIONS
Absolute Maximum Ratings

Operating Limits

Exceeding the maximum rating can result in
device damage. Operation of the device outside the
operating limits is not suggested.
Supply Voltage
Input Voltage at any pin
(ref V..=OV)
Sink/Source Current
(Supply)
(Other Pins)
Total Device Dissipation
(@ T amb=2S°C)
Derating
Operating Temperature
Storage Temperature

Voo = 4.0V

-0.3 to 7.0V

Audio Test Frequency = 820Hz
-0.3 to (Voo+ 0.3V)

TAMB = 2S'C

±30mA
±20mA

Sample Clock Rate = 32 kbps
Xtal/Clock fa = 3.S8MHz

800mW max.
10 mWrC
-30°C to + 70°C
-40'C to +8S'C

Static Values
Supply Voltage
Supply Current
Input Logic "1"
Input Logic "0"
Output Logic "1"
Output Logic "0"
Digital Input
Logic I/O
Logic Input

I

All devices were measured under the following
conditions unless otherwise noted.

Audio level OdB ref (0 dBmO) = SOOmVrms

2.7

5.S
3.S

70"loV oo
30"loV oo
80"loV oo
20"loV DO
10

Mn
kn
kn
kn
n
dB

300

4

Digital Output
Analog Input Impedance
Analog Output Impedance
Insertion Loss

V
mA
V
V
V
V

100

Dynamic Values
Encoder:
Analog Signal Input Levels
Principal Integrator Frequency
Encoder Passband
Compand Time Constant
Decoder:
Analog Signal Output Levels
Decoder Passband

Page 382

6

-30

dB
Hz
Hz
ms

4

6
3

-30

0
3700

+6

dB
Hz

MX-COM, INC.

MX109

Encoder/Decoder (Full Codec):
Passband
Stopband
Stopband Attenua~
Passband Gain.
,--,

300
6

3400
10

Hz
KHz
dB
dB
dB
dB

60
0
-3

Passband Rippfe - . :.Output Noise (InpUt?~tiort- Circuit) ....
Group Delay Distorli~ -.

+3
-60

4

(1000Hz-2600Hz)
(600Hz-2800Hz)
(500Hz-3000Hz)
XtallClock Frequency

450
750
1_5
4.0

Ils
Ils
ms
MHz

NOTES:
1. Dynamic characteristics specified at 4V only.
, ...
,
2. All logic inputs except Encoder and Decoder Data Clocks.
:;:::i'}~~~~~:::>- ,.
3. With passband gain of ±1dB.
4. Group Delay Distortion for the full codec is relative to the delay with an 820Hz, ...._..,.,.,...,.,.
input.
5. Relative Timings are shown in Figure 4.
6. Recommended values.
"

Sample Rate = 32 kbps
Ref: OdB Input Level = 500mVrms

35

at the encoder

Ref: OdB Input Level = 500mVrms
Input Frequency = 820 Hz

5

30

64 kbps

00
~

.~

C!:l

~

o,------==--=::::::::::::===_

32 kbps

20

<.'

__

,

- : tsu ,-

,

\'----

,

'

~--------

. - DATA TRUE T'ME - .

ENCODER

~~~U:!: ___ ~G!:!. z___

MULTIPLEXING' FUNCTION

-K.l-----------------t.l>:.
__
,

,

-,tOR ' -

..t"<:
--:tsu,-t,;-:

tlF: Clock Fall Time
100ns typo
tsu: Data Set-Up Time
450nsmax.
tH: Data Hold Time
600nsmin.

__

,t + -'-

ENCODER

Ql!!P~!. - -

_I:!!G!:!.

~- -

DATA TRUE TIME

,
-----+1

tpco: Clock to Output Delay
Time. 750ns max.

MULTIPLEXING FUNCTION

-K.;.---------------t.l~- -,

-,too _
DATA ENABLE

tsu + tH: Data True Time

,

..!:!IG.!:!. Z_ - - - - - - -

-.(:-

tDR: Data Rise Time
100nstyp.
tDF: Data Fall Time
100nstyp.
XTAL Input Frequency:
1.024 MHz

Figure 4 - CODEC Timing Diagrams

MX-COM, INC.

Page 395

I

I

MX619/MX629

Codec Performance (MX619)
Using the Bit Sequence Tests (a - g) at the Decoder Input pin in accordance with the Eurocom Specification D1IA8, the decoder output is as shown in Table 1.

MLA
Duty
Cycle

Typical
Output
Level

10110100100100101101
1011011010101001001001001001010101101101

0
0

-41.SdBmO
-42.0dBmO

16kbitls
32kbitls

11011001001001001101
1011011010101001001000100100101011011011

O.OS
O.OS

-2S.0dBmO
-2S.OdBmO

c.

16kbitls
32kbitls

10110101000100101011
1101101101010010001000100100101011011101

0.1
0.1

-19.0dBmO
-18.SdBmO

d.

16kbitls
32kbitls

11011001000010011011
1101110110010100010000100010011010111011

0.2
0.2

-11.0dBmO
-11.SdBmO

e.

16kbitls
32kbitls

11011010000010010111
111011101100100010000001001001101110111

0.3
0.3

-6.SdBmO
-6.SdBmO

f.

16kbitls
32kbitls

11011010000001001111
1111011101010001000000001000101011101111

0.4
0.4

-3.0dBmO
-3.0dBmO

g.

16kbitls
32kbitls

1110101000000010111
1111101110100010000000000100010111011111

O.S
O.S

OdBmO
OdBmO

Test

Sample
Rate

Bit Sequence at Decoder Input

a.

16kbitls
32kbitls

b.

Table 1 - Bit Sequence Test Table

Digital to Analog Performance (MX629)
Using the bit sequence tests shown in Table 2 (below) at the Decoder Input pin, the analog signals measured at
the Decoder Output pin are 800 Hz ± 10Hz at the levels described.

Sample Rate

Bit Sequence at Decoder Input

"Run of Threes"
(%)

Output Level
(dBmO)

16 kbitls
32 kbitls

11011011010010010010
1101101101010100100100100100101010110110

0
0

-29.2 ±2
-30.0 ±2

16 kbitls
32 kbitls

11111011010000010010
1111110110101010000100000010010101011110

30

0±1
0±1

30

at 800 Hz

Table 2 - Bit Sequence Tests and Results (MX629)

Page 396

MX-COM,INC

MX619/MX629

MX619 Codec Performance ...

MX629 Codec Performance ..'.

relative to the EUROCOM D1-IA8 Specification

relative to the Mil-Std-188-113 Specification

MX619

3

MX629

3
2

2

-I~--------~~--==~----~:-­

.§
til 0

E
«J!l -1

Ref: OdBmO lput Level = 489mVrms
Input Frequency = 820Hz

-2

-3

~
«

-2

-3

ref.

-50

-40

-30

-20

-10

0

+--===---+---===:...----~.~

0

"c
J!l -1

10

-20

-30

-10

0

10 ,.

Input Level (dBmO)

Input Level (dBmO)

Figure 5 - Gain vs Input Level (16kbitls)

3

3

MX619

2

MX629

2

CD

~

.§
til

-+----------,::=-+-==:::..----if-

0

"!Ii

~ -1
ti: o :t.'ti;2Wil

Ref: OdBmO Input Level = 489mVrms
Input Frequency = 820Hz

~

0

-+-~==----i----------~--­

" -1

«~

-2

-,,,,,,,,,.iiiI-2

-3

-3

ref.

-50

-40

-30

-20

-10

0

OdBmO Input Level = 489mVrms
Input Frequency = 800Hz
Ref. Level: -15dBmO = 87mVrms

10

-10

-20

-30

Figure 6 - Gain vs Input Level (32kbitls)

10 ,.

Note: Spec of ± 1dB sums a Mil-Std-188-113 spec of ±O.5dB with a test
measurement limitation of ±O.5dB (with OdB = 87mVrms, O.5dB = 1.2mVrms).

20

20

0

Input Level (dBmO)

Input Level (dBmO)

Ref: OdBmO Input Level = 489mVrms
Input Frequency = 820Hz
~
III
~

Ref: OdBmO Input Level = 489mVnns
Input Frequency = 800Hz

15

o

&!

10

~
5

10

MX619

8

-40

-30

-20

-10

MX629
o

Input Level (dBmO)

-30

-20

-10

o

Input Level (dBmO)

Figure 7 - SIN vs Input Level (16kbitls)
MX-COM, INC.

Page 397

I

MX61etMX629
MX619 Codec Performance ...

MX629 Codec 'Performance ...

relative to the EUROCOM D1-IA8 Specification

relative to the Mil-Std-188-113 Specification
Ref: :OdBmO Input J...evel= 489niVrms
Input 'Frequency = 800Hz

Ref: .OdBmO Input I~el = 489mVrms
Input Frequency = 820Hz

.25

15

15
-40

-20

-10

0
Input Level (dBmO)

-30

-30

-20

-10

0

Input Level (dBmO)

Figure 8 - SIN vs Input Level (32kbitls)

+10
,.6.

0, .•
-10
Input Level = -2OdBmO

00-20

:s

c: -30

'ijj

C)

-40 .

I

MX619

-50
-60

0.3

0

2

2.6

3

4

2.6

3

44.2

5
6
Frequency (kHz)

+10 -

"l.

,.5
0, ...

f

-10 -

00 -20-

:s

c: -30-

'ijj

C)

Input Level = -15dBmO

I

-40-

MX629

-50ref.
-60

0

0.3

O.B

I

I

1

2

5
6
Frequency (kHz)

Figure 9 - Attenuation Distortion vs Frequency (16kbitls)
Page 398

MX-COM,INC

MX619/MX629

MX619 Codec Performance ...

MX629 Codec Performance ...

relative to the EUROCOM D1-IA8 Specification

relative to the Mil-Std-188-113 Specification

Input Level

20

iii'

= -20dBmO

~X619

15

~

iii'

MX629

15

~

0

1a
cr:

Input Level = -15dBmO

20

.Q

10

1ii

cr:

10

z

~

en
5

5

o

I

I

I

o

I

I

I

3

Input Frequency (kHz)

Input Frequency (kHz)

Figure 10 - SIN vs Input Frequency (16kbitls)
30

30

Input Level = -20dBmO

25

25

iii'

20

iii'

15
cr:
z

en

20

~

~
0

Input Level = -15dBmO

15

0

~

15

cr:

~

10

MX619

5

10

2
3 3.4
Input Frequency (kHz)

0

2
3
Input Frequency (kHz)

0

MX629

5

Figure 11 - SIN vs Input Frequency (32kbitls)

0+----.. . .

0+------.

-6

iii'
~

-6

iii'
~

-12

(I)

(I)

"0

"0

:2

a.
~

:E

a.
~

-18

MX619

-24

10

100

-12
-18
-24

1k
10k
Frequency (Hz)

-6dB/octave

MX629

-30 -+--r--'-rnTTlT"--'--'-TT'1nnr-..--r~'TTTJ1r10
100
1k
10k
Frequency (Hz)

Figure 12 - Principal Integrator Response
MX-COM, INC.

Page 399

I

MX619/MX629

MX619 Codec Performance"""

MX629 Codec Performance"""

relative to the EUROCOM D1-IA8 Specification

relative to the Mil-Std-188-113 Specification

1.0' . . . . . . . . . ; _ - - - - - , . Amplituda of test
signal g (Table 1)

100' . • . • • . • . . _ _ - - - - - , . 30% "rurHlf-threas"

MX619

0.397· . . . . . . . . . . . . . . . . . .

MX629

Beginning of
-discharge

48· . . . . . _ . . . . . . . . . . .

10· . .

0.1· ..

Beginning of
-discharge

. . _ . . . . . . . . . . . , ..
: 0% "run..of-Ihrees"

0.00794'-i=~._:""'._ _ _ _ _ _....
- - - - - "......

8.76

3,-i==W==~~_ _ _ _ _....
-----"~

5.76

x

TIme (ms)

Time (ms)

Figure 13 - Compand Envelope
+10
2

0 ..
-10
Input Level = -2OdBmO

iii' -20
:g.
<:

'iiI

-30

(!)

MX619

-40

I

-50
-60
0

0.3

1.4

3

2

3.4

4

5

6

Frequency (kHz)

+10 3

0

1
2

-10 -

iii' -20 :g.

<:
'iiI -30(!)

I

-40-

Input Level = -15dBmO

MX629

-50 -

-60
0

0.3

I

1

1.4

Figure 14 - Attenuation Distortion vs Frequency (32kbitls)
Page 400

I

2

2.6

~

3.4

~ 4.2

5

~

Frequency (kHz)

MX-COM,INC

MX619/MX629

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

OPERATING LIMITS

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following conditions
unless otherwise noted.
Voo= 5.OV

-0.3 to 7.0V

Supply Voltage
Input Voltage at any pin

-0.3 V to Voo + 0.3 V

(ref V88 = OV)
Sink/Source Current: supply pins
other pins

±30mA

Audio Test Frequency = 800 Hz (MX619)
820 Hz (MX629)

±20mA

Sample Clock Rate = 32kb/sec

800mWmax.

Xtal/Clock fo = 1.024 MHz

Total Device Dissipation
@ TAMB =25°C

Derating

10mW/oC

Operating Temperature

-40°C to +85°C

Storage Temperature

-55°C to + 125°C

3-bit Compand Algorithm
Audio Level OdB ref. (0 dBmO) = 489 mVrms

Static Values
Supply Voltage
Supply Current (Enabled)
MX619
MX629
Supply Current (Powersave)
MX619
MX629
Input Logic "1"
Input Logic "0"
Output Logic "1 "
Output Logic "0"
Digital Input Impedance
Logic I/O Pins
Logic Input Pins, Pullup Resistor
Digital Output Impedance
MX619
MX629
Analog Input Impedance
Analog Output Impedance
Three State Output Leakage
Current (output disabled)
Insertion Loss

Dynamic Values
Encoder:
Analog Signal Input Levels
MX619
MX629
Principal Integrator Frequency
MX619
MX629

MX-COM, INC.

4.5

8
8
8
8

2

5.0

5.5

4.5
5.5

mA
mA

1.0
0.4

mA
mA
V
V
V

3.5
1.5
4.0
1.0
1.0
300

Mg
kg

10

4
4
4
7

3

V

800

kg
kg
kg
g

-4
-2

+4
+2

(.lA

-35
-35

+6
+12

dBmO
dBmO

212

Hz
Hz

dB

1,9

5,9
5,9

127

275
159

Page 401

I

MX619/MX629
3400

Encoder Passband
Compand Time Constant
MX619
MX629

4

Decoder:
Analog Signal Output Levels
MX619
MX629
Decoder Passband

I

Hz

5,9
5,9

Encoder Decoder (Full Codec)
Compression Ratio
MX619 (Cd=0.5 to Cd=O.O)
MX629 (Cd=0.3 to Cd=O.O)
Passband
Stopband
MX619
MX629
Stopband Attenuation
MX619
MX629
(4200Hz to 6000Hz)
(>6kH.:)
Passband Gain
(300Hz-1400Hz)
Passband Ripple
(1400Hz-2600Hz)
(2600Hz-3400Hz)
Output Noise (Input Short Circuit)
MX619
MX629
Perfect Idle Channel Noise (Encoder Forced)
MX619
MX629
Group Delay Distortion (1000Hz-2600Hz)
(600Hz-2800Hz)
(500Hz-3000Hz)
XtallClock Frequency

4.0

5.0

6.0

ms
ms

-35
-35
300

-10

+6
+12
3400

dBmO
dBmO
Hz

300

3400

Hz

6
4.2

10

kHz
kHz

50
16:1

60

dB
dB
dB
dB
dB
dB
dB

25
60
0
-1
-1
-2
9
9

9
6
6
6

+1

+3
+3

-55

-60

dBmOp
dBmO

-63
-57

dBmOp
dBmO
450
750
1.5

Ils
Ils
ms
kHz

1024

NOTES:
1. Dynamic characteristics are specified at 5V unless otherwise specified.
2. All logic inputs except Encoder and Decoder Data Clocks.
3. For an Encoder/Decoder combination, Insertion Loss contributed by a single component is half this figure.
4. Driven with a source impedance of < 100 Q.
5. Recommended values - See Figures 5, 6, 7 and 8.
6. Group Delay Distortion for the full codec is relative to the delay with an 820Hz, -20dB signal at the encoder input.
7. An Emitter Follower output stage.
8. 4V = 80% V DD , 3.5V = 70% V DD , 1.5V

=30% V

DD ,

1V = 20%VDD •

9. Analog Voltage Levels used: OdBmO = 489mVrms = -4dBm = OdB. -15dBmO = 87mVrms. -20dBmO = 49mVrms =
-24dBm.

Page 402

MX-COM,INC

MX· CDM,INI:!.

MX709

Voice Store :Retri.eve CV$:D \Codec
,

,"

., ..

'.

i,

"

.

f

'.

APPLICATIONS:

FE.ATURES:

•.

,eOelta Modulation Encoding
,e ;Bytewide Storage and Control
eprogrammable Sampling Rate ,and FiI~er
e Low ,Power CMOS Requiren;tents
e Micropr,0;C8ssor-Friendly

!

,

,e pigi~1 Speech Communications
,e Digi,tal Scrambling
,e :Vo.ice Message Mailbox
eSpeech Analysis
(e~oice Multiplexin,g
~ ~peech Compr.ession

DESCRIPTIO~,:

The MX7(l9 isa .continuously variable slope delta modulation (CVSD) codec for a wide
variety of digital audio processing' applications. Its primary use is in microprocessorcontrolled voice storage pnd retrieval systems.
In the encode mode, audio inputsignals,a~epand-limited by a lowpass filter and digitized
by a CVSD 1-:bit serial ,encoder. After conversion to 8-bit parallel format, encoded data is
read to the data ,bus for storage in memory.
In the decode mode, memory contents writt,en into the .data bus are converted back to
1-bit serial form ,and decoded by aGV~ decoder. The decoder output is lowpass filtered
and output as retrieved audio.
The audio.encode/decode functions ar.einc;lependently controlled, permitting concurrent
or asynchronous VSRoperations. Time and frequency companding is available via independently programmable .encode/decode ,data rates and filter cut-ofts.
Support of VOX functions .and "~ause" m~mory management is provided by the power
,assessment register. TNs register .con~ains two A-bit numbers representing the average
signal levels into the da~a ,encoder pnd :B. repli,ca .enco.der over a programmabl,e averaging
period.
, The deviceinstructiol) .set inCludes input/output signal switching and a standby pow.ersave function. The MX709 is a low power GMPS circuit and requires only a Single 5V
supply.

MX709J (CDIP)
MX709P (PDIP)
,28 pins

MX709LH8
(28p PLCC)

AUDIO INTERFACE

l_~
Fig. 1 System Schematic Diagram

MX-COM, INC.

Page 403

I

MX709 PIN FUNCTION TABLE

FUNCTIONIDESCRIPTION

PIN
MX709J, P
MX709LH

XtallClock: Output of a clock oscillator inverter.

2

Ao

3

A1- }

4

RIW

These pins determine which register may be addressed via the 1/0 Port.

Table

Ao

A1

RIW

0
1
0
1
0
1
0

0
0
1
1
0
0
1
1

0
0
0
0

5

CS: Chip select input, this input has 1Mfl pullup to Voo.

6
7

00
01

8

O2

9

03
04
05

10

11
12
13
14

Register

'A' instruction
'8' instruction
Decoder
No register
Status
Power
Encoder
No register

1/0 port

06
07
iRQ: Interrupt request output (100Kfl pullup), this pin is the output of the interrupt request generator.
This device can be "wire OR'd" with other active low components. See section on Interrupt Requests.

15
16

No Connection
No Connection

17

Analog output B: (See Fig. 4.)

18

Analog output A: (See Fig. 4.)

19

V Blaa : This is the bias or analog ground pin and is internally set to Voo/2. It should be decoupled to,Vs
with a capacitor of 1.0fJ-F (min.).

20

Analog input A: (See Fig. 2, Note 4 and FigA)

21

V DD : Positive supply.

22

Analog input B: (See Fig. 2, Note 4 and Fig. 4)

23

No Connection.

24

Analog input C: This is the analog input to the power encoder.

25

Analog output AlB: (See Fig. 4.)

26

No Connection.

Page 404

MX-COM, INC.

MX709 PIN FUNCTION TABLE
PIN
FUNCTION/DESCRIPTION
MX709J, P
MX709LH
27

Vss: Negative supply.

28

XtalfClock Input: This is the input to the clock oscillator inverter. 1MHz Xtal input or externally derived
clock is injected at this pin.

Voo

x,

lCG

c'INOTE 2

0

R,

MX709J

XTALI
CLOCK
liP

28
27

Vss

26

N/C

25
24
23

22
21

AlB

Vss

R,NOTE 1

alP

CliP
C,

N/C

:rC,NOTE 1

~NOTE3

BliP
Voo

C,

A liP ~I-------NOTE 3
c,
19 BIAS
Vss I
18 AOIP

20

p:... : :

17 B alP
AUDIO
INPUTSIOUTPUTS

Component References
Component

NOTES:
1. R2. C2 forms a lowpass filter
input to .. c.. Input power assessment
circuit. The values shown represent
a 820 Hz lowpass although other cutoff
frequencies may be selected depending
on the application.

3. To prevent unwanted internal oscillations
at the Encoder Input pins. the source
impedance to these inputs must be less
than 1 Kohm. Ideally. the source
Impedance should be less than 50 ohms
to minimize granular noise.

2. Additional decoupling may be necessary
for noisy supplies.

FIG. 2: EXTERNAL COMPONENT CONNECTIONS

MX-COM, INC.

R1
R2
CG
CD
C1
C2
C3
C.
C5
Ca

Value
Tolerance
>1M
±10%
5.6k
±10%
68p
33p
O.1j..l
±20%
.033p
±20%
O.1j..l
±20%
O.1j..l
±20%
1.0j..l min.
±20%
O.1j..l
±20%

Page 405

I

2 3

4

5

15

14'

2'-

'Li

r

I' r

19'

~4
C IN

25

20

~'

AlB OUT

A ..

B

18. 1i
A, B,

INTERNAl.
ANAI,.OGUE
GROUND

'i'i'T-Ti'TTT' NOTE: PIN NUMBERS'SHOWN FOR MX709J
Do

D7

FIG. 3 MX709 INTERNAL BLOCK DIAGRAM 6 THRU 13

ANALOG'SWITCHING
A
INPUT

IN~UT O"'-----.L+-----I
The input and output switching of'
analog signals is controlled by the

I

;!:::U:!i!!t~e~l~t~r4B~Dd D5 tn

A/B~
OUTPUT ~"'-J"
T

Fig. 4 Audio SwitchingSimplified Block Schematic

ENCODE
REGISTER

DECODE
REGISTER

Frequency'and Data 'Rate Control
Six bits of Instruction Register A (°2-07) control the data rates of the encoder and decoder and the bandwidths of
the filters for the encoder and decoder. The configuration of the frequency dividers is as shown in the diagrams
below and obtainable combinations of frequencies with various input clocks are listed.

ENCODE DATA RATE ClK,

ClK.lNo-

ENCODE FilTER ClK,

DECODE DATA RATE CLOCK

-

Fig. 5 Filter Clock and Data Rate divider control Block diagram

Page 406

DECODE FilTER ClK,

ref: Instruction Register' A'

MX-COM, INC.

Clock
Input

Encoder Clock
Programming Bits
in Register A

Decoder Clock
Programming Bits
in Register A

Filter
Clock
(Hz)

Lowpass
Filter BW
pb. ±1dB

Data
Clock
(kbs)

2MHz

010xxxxx
011xxxxx
110xxxxx
111xxxxx
OOOxxxxx
001xxxxx
010xxxxx
011xxxxx
100xxxxx
101xxxxx
110xxxxx
111xxxxx
010xxxxx
011xxxxx
110xxxxx
111xxxxx
OOOxxxxx
001xxxxx
010xxxxx
011xxxxx
100xxxxx
101xxxxx
110xxxxx
111xxxxx
001xxxxx
101xxxxx

xxx010xx
xxx011xx
xxx110xx
xxx111xx
xxxOOOxx
xxx001xx
xxx010xx
xxx011xx
xxx100xx
xxx101xx
xxx110xx
xxx111xx
xxx010xx
xxx011xx
xxx110xx
xxx111xx
xxxOOOxx
xxx001 xx
xxx010xx
xxx011xx
xxx100xx
xxx101xx
xxx110xx
xxx111xx
xxx001xx
xxx101xx

125k
125k
100k
100k
125k
125k
62.5k
62.5k
100k
100k
50k
50k
128k
128k
102.4k
102.4k
128k
128k
64k
64k
102.4k
102.4k
51.2k
51.2k
76.8k
76.8k

3320
3320
2656
2656
3320
3320
1660
1660
2656
2656
1328
1328
3400
3400
2720
2720
3400
3400
1700
1700
2720
2720
1360
1360
2040
2040

62.5
31.25
50.0
25.0
31.25
15.625
31.25'
15.625'
25.0
12.5
25.0'
12.5'
64.0
32.0
51.2
25.6
32.0
16.0
32.0'
16.0'
25.6
12.6
25.6'
12.6'
9.6'
9.6'

1MHz

2.048MHz

1.024MHz

614.4kHz
768.0kHz

Table 1 Possible combinations of clock input frequency, filter cutoff (Hz) and Data Clock (kbs)
'Caution: Although possible, the Codec insertion loss is not according to the specification at these settings.

MX-COM, INC.

Page 407

I

Register Truth Tables
The following tables describe the function of each bit within each register. 'Address Input' logic states are shown in the
top right hand corner of each table. The following registers are described below:
Instruction Register 'A' [IRA]
Instruction Register 'B' [IRB]
Status Register
[SRI
Power Register
[PRJ

Bit
Do

=0
Ao
=0
A1
RIW =0

INSTRUCTION REGISTER 'A'

IRA
Function
Name

Logic
State

Encoder
Idle

NOTES

References
SRD3

Do sets the encoder idle/normal mode of operation.

FORCED: Forces the encode register to fill with a
1010101 ... idle pattern. Note: incoming encoded data is

still available for the power assessment circuits.
NORMAL: Allows the encode register to till with
encoded data. Data is transferred to the encode buffer
during the last bit of the encode byte.

0

D1

Decoder
Data
Source

I

SRD4

ENCODER: Internally connects the output of the
encode register to the input of the decode register. This
condition effectively connects the audio straight
through. The encoded data may still be accessed via the
encode buffer, and data bus.

0

D2

D3

Decode
Data Rate
Clock
Divider

Fills the decoder register with idle pattern. In either case
data may be loaded into the decoder register via the
data bus. This automatically overwrites the current contents of the decoder register.
Fig. 5
Table 1

Decode
Filter
Clock
Divider

Page40B

Decode
Master
Clock
Divider

-;- 4
Fig. 5
Table 1

D3 sets the Decode Filter Clock Divider and hence the
Filter Cut-off Frequency.

-;-2

-;- 1
Fig. 5
Table 1

1
0

D2 sets the Decode data rate divider.

-;- 8

1
0

1
0
D4

D1 determines the source of data for the decoder.

D4 sets the Decode Master clock divider.

-;- 10
-;- 8

MX-COM, INC.

=0
=0
RIW =0

Ao

INSTRUCTION REGISTER 'A'

IRA

Bit
05

06

07

Function
Name
Encode
Clock
Divider

Encode
Filter
Clock
Divider

Encode
Master
Clock
Divider

Logic
State

A1

NOTES

References

0 5 sets the Encode Data Rate Divider.
Table 1
1
0

+ 8
+ 4
0 6 sets the Encode Filter Clock Divider and hence the
filter cut-off frequency.
Table 1

1
0
1
0

+ 2
+ 1
Table 1

0 7 sets the Encode Master Clock Divider
+ 10
+8

INSTRUCTION REGISTER 'B'

IRB

Bit

Function
Name

Do

Page Size Set

Logic
State

NOTES

References

0 0 -02 set the "page size" in Encode Data bytes. (one
byte = 8 serial data bits) in accordance with the table
below:
PAGE BYTES
Page period @
O2 0 1 Do
32 kbs
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

32
64
96
128
160
192
224
256

8ms
16ms
24ms
32ms
40ms
48ms
56ms
64ms

Page Period (sec) = 8 x Page Bytes/Data Rate (b/s)
Fig. 4

':A,/B"
Encode

o

0 3 defines which audio input A or B is connected to the
encoder via the encode filter. (See fig. 4).
AUDIO INPUT "A": Internally connects the ':A," audio
input to the encode filter input.
The ':A,/B OUT" pin outputs filtered audio ':A,." Audio
input "B" set to Voo/2.
AUDIO INPUT "B": Internally connects the "B" audio
input to the encode filter input.
The ':A,/B OUT" pin controls filtered audio "B." Audio
input ':A," set to Voo/2.

MX-COM, INC.

Page 409

I

Ao =1
At- =0

INSTRUCTION REGISTER 'B'

IRB

RIW =0
Bit
D4

Function
Name

References
Fig. 4

Fig. 4

1
0

NOTES
D4 controls the Output Audio Switch to determine which
source audio is connected to Audio Output ''A'' pin.

Input ''A'' to Output ''A'' (direct).
Decoder to Output ''A.''

1
0

Switch
Audio
Output
"B"

D6

State

Switch
Audio
Output

"Au
05

Logic

D5 controls the Output Audio Switch to determine which
source audio is connected to Audio Output "B" pin.

Decoder to Output "B."
Input "B" to Output "B" (direct).

0 6 controls the enablement and disablement of all analog circuit elements.

Powersave

POWERSAVE MODE: Disables the circuit elements,
thereby effectively reducing current consumption.

0

OPERATING MODE: All circuit elements enabled.
NOTE: During POWERSAVE, inputs are biased Voo/2.
Outputs are biased Voo/2 if IRB D4/D5 are set to
"direct."

D7

I

D7 determines the sensitivity range of the power measuring circuits.

Power
Sensitivity

HIGH: Low power input, assessment circuits have
+ 12dB gain over LDW Setting.

0

LOW: Normal power assessment sensitivity range.
NOTE: High input levels in the HIGH condition may lead
to overflow, producing an ambiguous reading.

Page 410

MX-COM, INC.

SR

Bit

Do

Function
Name

Logic
State

References

Encode
Data
Ready

NOTES

NOT READY/OVERSPILL: This condition occurs
when:
1. The last data byte in the encode data register has
been read.
2.Encode data overspill bit = 1
i.e. SRD3 = 1.

Decode
Data
Ready

0 1 indicates that a byte of data has been decoded and a
new byte should be written to the decode buffer.
SRD 4

WRITE BYTE: This condition occurs when the decode
register has been loaded from its buffer, i.e. after the last
bit of the previous byte has been clocked out of the
register.
NOT READY IOVERSPILL: This condition occurs when
data has been written into the decode buffer or the
decode data overspill condition is valid (SRD4 = 1).

0

O2

=0
A1_ =0
RJW =1

Do indicates that a byte of data has been encoded and
can be read from the encode buffer.
READ BYTE: Set high during the last bit of the byte
shifted into the encode register. This condition causes
an interrupt request.

0

01

An

STATUS REGISTER

Page
Ready

This bit indicates that a page of bytes has been
encoded.
READ PAGE: This condition occurs when the page
counter has completed the last byte of a page. This is
after power measurements have been written into PRD o
to PRD 7 inclusive.

0

D3

Encode
Overspill

NOT READY IOVERSPILL: This condition occurs when
Power Register "PR" has been read or the page overspill condition is valid.
OVERSPILL: Indicates that the encode data was not
read between two consecutive "encode data ready"
flags. Encoded data bytes have been lost, and no further
bytes will be transferred to the encode buffer.

0

MX-COM, INC.

SRD 5

NORMAL: This condition occurs when data has been
read from the encode buffer, following a data ready flag,
SRDo = 1, or by writing to the decode buffer if both
encode and decode overspill bits are set.

Page 411

I

SR

Ao
A1

STATUS REGISTER

=0
=0

RiW = 1

Bit

Function
Name

Logic
State

References

NOTES
OVERSPILL: When this bit is set data transfer from the
decode buffer to the decode register is inhibited. If the
"DECODER/ENCODER BUS" (IRAD,) is not set then
the deCQde register will fill with idle pattern.

Decode
Overspill

o

NORMAL: This condition occurs when data has been
written to the decode buffer following a data ready flag,
SRD 1 = 1, or by reading the contents of the encode
buffer if both encode and decode overspill bits are set.
OVERSPILL: This state indicates that the power register was not read before the next page was completed.

Page
Overspill

o

NORMAL: Power register "read" or IRB written.

=1
=0
RIW =1

Ao
PR

Bit

I

Do

POWER REGISTER

Function
Name
'~/B"

Power

LSB

01
O2
03

Logic
State

~

NOTES

0 0 -03 represent the average signal level of the last page of data in the
range from + adBm to - 24dBm (at 1kHz) for the A or B input. (OdBm =
775mVRMS)
The relationship between binary value and signal level is frequency
dependent and exhibits pre-emphasis characteristics. (see fig. 8.)

'~/B"

Power

MSB

04

"C" Power
LSB

Os
06
07

Page 412

0 4 -0 7 represent the average signal level of the last page of data in the
range from + 6dBm to - 24dBm (at 1kHz) for the C input.

"C" Power
MSB

MX-COM, INC.

Interrupts
Three conditions can cause interrupt requests to the host microprocessor.
(i) The encoder buffer contains an unread byte of data which is the most recent byte encoded.
(ii) The decode buffer is ready to receive the next consecutive byte for decoding.
(iii) The power register contains a power assessment for the most recent whole page encoded.
The status register indicates which of the above conditions are true.
If an interrupt condition remains unserviced and the condition becomes irrecoverably untrue, the status bit is cleared,
the corresponding overspill bit is set, and further interrupts are automatically inhibited. Also the encode and decode
data buffers retain the data present when the data bit was set, i.e. register-buffer update is inhibited. The power register
is updated at all times.
Condition (i) is serviced by a valid address to the encode buffer. Condition (ii) is serviced by a valid address to the
decode buffer. If conditions (i) and (ii) have both become UNTRUE, servicing either buffer resets both to a clear start
position. Condition (iii) is serviced by reading the Power Register.

TheClnput
By careful selection of the audio frequency filtering to the C input, the AlB and C power words can be used in the
processor to provide frequency as well as power information. This facility could be used for word, pause or voice
recognition.

MX709 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is
not implied.
- 0.3V to 7.0V
Supply voltage
Input voltage at any pin (ref. Vss = OV)
-0.3Vto(Voo + 0.3V)
Output sink/source current (total)
20mA
Operating temperature range:
MX709J
- 30°C to + 85°C
MX709LH,P
- 30°C to + 70°C
Storage temperature range:
MX709J
- 55°C to + 125°C
MX709LH,P
- 40°C to + 85°C

Operating Limits
All characteristics measured using the following parameters unless otherwise specified: Voo
0= fin = 1MHz

Characteristics

See Note

= 5V, Tamb = 25°C,

Min

Typ

Max

Unit

4.5

5.0
6

5.5

V
mA
mA
mV

Static Characteristics

Supply Voltage
Supply Current
Supply Current (Power Save)
Supply Ripple
Input Impedance (Audio)
Output Impedance (Audio)
Input Logic '1'
Input Logic '0'
Output Logic '1'

MX-COM, INC.

50
100
6

3.5
1.5
3.5

kO
kO

V
V
V

Page 413

I

MX709 ELECTRICAL SPECIFICATIONS (cont.)
See Note

Characteristics

Min

Typ

Max

Unit

1.5
1.0
7.5
120
360
4

V
fJ.A
pF

Static Characteristics (cont.)
Output Logic '0'
Input Current (Logic liP's)
Input capacitance (Logic liP's)
Output Logic '1' Source current
Output Logic '0' Sink current
Three State output leakage current

2
3

tJ.A
tJ.A
ILA

Dynamic Characteristics
Audio Input Level
Insertion Loss (Direct)
Attenuation distortion (See fig. 6)
Clock bit Rate
Idle Channel NOise
SignallNoise Ratio (see fig. 81

500
4,7

-1.5

5
4,6

8

+1.5
64
2.5

mV (rms)
dB
kbits/sec
mV (rms)

Timing Information

I

Address Set up time
Read Write Set up time
Address Hold time
Read Write Recovery
time
Chip Select Access
time
Output Hold time
(read)
Data Set up time
(write)
Data Hold time
(write)

(tAS)
(tRWS)
(tAH)

8
8
8

50
0

ns
ns
os

(tRWR)

8

0

ns

(tACS)

8

(tOHR)

8

0

(tDSW)

8

150

ns

(tDHW)

8

50

os

50

250

ns

100

ns

Notes
1. Load 5OpF, 200kfl
2. Vout = 4.6\1, not pins 12 (IRQ) and 15 (Wait), these pins have 100kll pullups to VDD.
3. Vout = O.4V
4. Measured from Codec audio input to audio output.
5. 2.048MHz master clock ... 32
6. 32kHz clock.
7. For a load of> 100kfl, serial switch impedance is 3kfllswitch (See Fig. 4).
8. See Figure 7 Timing Diagram

Page 414

MX-COM, INC.

Typical Performance
+10
Ref. 0

"\

-10

!\

-20

\

III

"C

-30
-40
-50

I

\
1.11J\

I,

!
!

"'V~ ~v l~ .1I

V

I

I

,

V :'-10

5
kHz

FIG. 6: TYPICAL MX709 SYSTEM RESPONSE MEASURED AT:
FIL TER 3320 HZ. VIN -24 dBm. 32 KB/S_EC
____._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...J

ADDRESS
Ao, A,
R/W

=><~~t:-A-S-:::O_------------~::J><(AH~===================:::
=:=><\....'---'.i______--!:::-:.1X.....______
~

tRWS

~

!--

CS~'AeSi

tRWR

I

/_'OHR~

\'----

DATAOUTIR~E~A~D~'_ _ _~----_<~1~:~~~~V~A~LHI_D~DD_A~:T~A~~~~~J~>---~----I

l---

-+j__-(~

'DSW

DATA IN (WR;;IT_E...;)_ _ _

~ lew ~
~----------------~'\~

,

---+

.

tWAIT'::::: twc
)

t RwR

Min. Typ. Mex.
50
50

0
0

tA.CS

-

tOHR

0

tosw

150
50

tOHW

tew
tWAIT
twe
t WNC

-2
0
2

---

Unhs

-

250
100

100

.~

-

n.n.
n.n.n.
n.n.
n.n.
n.

Xtal Cycle

Xtal Cycle

I for audio source.

R

Retrieve: Replays the stored audio from the selected audio buffer. Conditions of storage are saved
and retrieved with the audio data.

T

Set Storage Duration: Sets the basic audio storage time. This time will be amended by the software
with regard to clock rates and page size.

C

Set Clock Rate: Selects one of 6 stored sampling rates:
12.5 kb/sec
25.0 kb/sec
50.0 kb/sec

15.625 kb/sec
31.25 kb/sec
62.5
kb/sec

z

Set Page Size: Determines the measurement for the MX709 power assessment circuits by setting the
page size in bytes. 8 selections in the range 32 bytes to 256 bytes are available.

P&I

Set Retrieval Pause Elimination Parameters: For setting power threshold and intervals to produce
compression of speech pauses on replay.

"P

Set Storage Pause Elimination: Sets the A:B power threshold. Any page with input power value less
than threshold is not stored.

A

Select Assembly/Pascal Routines: Two languages for assessment with different speed systems.

V

Control Audio Levels: A and B input and speaker gains are independently variable. The current A
and B levels are displayed as vertical bars on the right of the 'menu.'

M

Modify Buffer Clock Rate: Alters the stored clock rate in a buffer to demonstrate compression or
expansion on retrieve.

?

Display Parameters: Displays current parameters controlling program operation. See Fig. 1.

W

Set Bus Switches: This command controls the switches for special purpose routing of audio signals.

N

MX709 Configuration: Sets the switch settings in the three evaluation program modes: Storage,
Retrieval, and Standby.
.

'G&D

Graph Page Power: To graph recorded page power against time. The <0> command sets the graph
scales. 'See Fig 2.
Histogram Audio Data: A statistical facility for examining the audio data.'

F
L&/

Page Power Ratios: A:B and C input power values for the active buffer are.listed in tabular form.

'Graphics are only available on machines with a color adaptor.

MX-COM, INC.

Page 417

I

Other Peripheral Commands Are:

E

Erase Buffer.

liS

Store Buffer to Disk.

IIR

Retrieve Buffer from Disk.

H

Help: Describes fully the instructions above.

Q

Quit.

SCREEN DISPLAYS
Basic Storage and Retrieval routines are demonstrated on the selected audio buffer using  and  commands.
These commands are also programmed in function keys for ease of operation. All available EVKIT commands are
displayed by the program menu. The full instructions, with comprehensive explanations, can be selected by the  or
'Help' function key.

Page Size (bytes): ' ...
Storage Duration (sec): ....
Clock rate (kb/s): ....
Store threshold (power): ... .
Retrieve threshold (power): ... .
Retrieve interval (pages): ... .
Buffer 1 status:
page size: ..... .
clock rate: ..... .
total pages: ..... .
Buffer 2 status:
page size: ..... .
clock rate: ..... .
total pages: ..... .
Power graph dimensions:max. power value: . . . . . .
max. pages: ......... .
Digital audio level control settings:
A input: ....
B input: ... .
Speaker: ... .
Power Sensitivity: ... .
Storage/Retrieval Routines: (Assembly or Pascali

I

> (Audio buffer on line)

1

Fig. 1
Page 418



Display Parameters

MX-COM, INC.

Power

Power

Number
of
Occurences
(iii!
Histogram
of Voice
Data

A:B
C
Inputs

Inputs

Time (pages)

Fig. 2

Voice Data Byte

Time (pages)

Typical Graphical Displays Available

CONTROL BUS

A AUDIO IN

J317

J3/10

I

elK
IN

J3Jll

AB OUT
J3J12

AUDIO BUS
ON/OFF (M(C)

J2

•

J3/13

elK IN
1 or 2M Hz

CLOCKRATE~~__________~~~--~

Fig. 3

PC7090 Basic Functional Block Diagram.

ORDERING INFORMATION
PC7090 EVKIT

comprises:

Plug-in printed circuit board.
Program on floppy disk.
Instruction manual.
Loudspeaker.
Microphone.
Physical dimensions PCB 13.4 in. x 3.94 in.

MX-COM, INC.

Page 419

MX·~M,IN~.
OVSR

MX802

cooec

Description
The MX802 Data/Voice Storage and Retrieval (DVSR) Codec contains a Continuosly
Variable Slope Delta Modulation (CVSD) encoder and decoder, as well as control and
timing circuitry for up to 4 Mbits of external DRAM. As a memberof the D8S 800 series,
it also contains interface and control logic for the "C-8US" serial interface.
When used with external DRAM, the MX802 has four primary functions:

MXS02J
2S-pin CDIP

• Speech Storage
Speech signals present at the Audio Input may be digitized by the CVSD encoder.
The resulting bit stream is stored in DRAM. This process also provides readings of
the speech signal power level. These readings are used by the system microcontroller for pause reduction.
•
Speech Playback
Digitzed speech may be read from DRAM and converted back into analog form by
the CVSD decoder.
•
Data Storage
Digital data derived via the C-8US from the Modem or system data may be stored
in DRAM.
Data Retrieval
Digital data may be read from DRAM and sent over the C-8US to the system
microcontroller.

MXS02LH
PLCC-24

MXS02LHS
PLCC-2S

Speech storage and playback may be performed concurrently with data storage or
retrieval.

I

The MX802 may also be used without DRAM (as a "stand alone" CVSD codec), in which case direct access is provided
to the CVSD Codec digital data and clock signals. All functions are controlled by C-8US commands from the system
microcontroller.
SERIAL

COMMAND

CLOCK

DATA

cs

REPLY
DATA

AUDIO
IN

AUDIO
OUT

1

DRAM Data In! DRAM Data 0utJ

M

MJ

A7

MJ

A5

AO/ENO
A4 A3/ECK A21DCK (ENmRER

Al/DEI

(DE~DER

- - - - - D R A M ADDRESS L l N E S - - - - -

Figure 1 - MXB02 DVSR Codec
Page 420

MX-COM, INC.

MX802
The storage, recovery and replay functions of the MX802 can be used for:
-Answering Machine applications, where an incoming speech message is stored for later recall.
-Busy Buffering, in which an outgoing speech message is stored temporarily until the TX channel becomes free.
-Automatic transmission of pre-recorded alarm or status announcements.
-Time Domain Scrambling of speech messages.
-VOX control of transmitter functions.
-Temporary Data Storage applications, such as buffering of over-air data transmissions.
On-chip the Delta Codec is supported by input and output analog switched-capacitor filters and audio output switching
circuitry. The DRAM control and timing circuitry provides all the necessary address, control and refresh signals to
interface to external DRAM.
The MX802 is a low-power 5-volt CMOS LSI device. It is offered in 24- and 28-lead SMT packages, as well as 28-pin
DIP packages.

Pin Function Chart
Row Address Strobe 2 (RAS2): This pin should be connected to the Row Address Strobe input
of the second 1 Mbit DRAM chip (if used).

2

3

Row Address Strobe 1 (RAS1): This pin should be connected to the Row Address Strobe input
of the first DRAM chip.

2

4

Write Enable (WE): The DRAM ReadlWrite control pin.
Xtal: This is the output of the 4.0 MHz on-chip clock oscillator. External components are required
at this output when a Xtal is used. A Xtal cannot be used with the 24-pin version.

5

3

Xtal/Clock: This is the input to the on-chip clock oscillator inverter. A 4.0MHz Xtal or externally
derived clock should be connected here (see component diagram). This clock provides timing for onchip elements, filters, etc. A Xtal cannot be used with the 24-pin version. Various Xtal frequencies
can be used with this device; see Table 3 for sampling rate variations.

6

4

Interrupt Request (IRQ): The output of this pin indicates an interrupt condition to the microcontroller
by going to logic "0." This is a "wire-or able" output, enabling the connection of up to 8 peripherals
to 1 interrupt port on the microcontroller. This pin is an open drain output. It therefore has a low
impedance pulldown to logic "0" when active and a high impedance when inactive. Conditions
indicated by this function are Power Reading Ready, Play Command Complete and Store Command
Complete.

7

5

Serial Clock: This is the C-BUS serial clock input. This clock, produced by the microcontroller, is
used for transfer timing of commands and data to and from the DVSR Codec. See timing diagrams.
Clock rate requirements vary for different MX802 functions.

8

6

Command Data: This is the C-BUS serial data input from the microcontroller. Data is loaded to this
device in 8-bit bytes, MSB (bit 7) first, and LSB (bit 0) last, synchronized to the Serial Clock. See
timing diagrams.

9

7

Chip Select (CS): The C-BUS data transfer control function, this input is provided by the
microcontroller. Command Data transfer sequences are initiated, completed or aborted by the CS
signal. See timing diagrams.

10

8

Reply Data: This is the C-BUS serial data output to the microcontroller. The transmission of Reply
Data bytes is synchronized to the Serial Data Clock under the control of the Chip Select input. This
3-state output is held at high impedance when not sending data to the microcontroller. See timing
diagrams.

MX-COM, INC.

Page 421

I

MX802

Pin Function Chart

25

Row Address Strobe 3 (RAS3): This pin should be connected to the Row Address Strobe input of
the third 1 Mbit DRAM chip (if used).

26

22

DRAM A9: This is DRAM address line A9. This pin is not connected when a 256 kbit DRAM is used.
Note: To simplify PCB layout, the DRAM address inputs AD-AS may be connected in any physical
order to the DVSR Codec output pins AD-AS.

27

23

Column Address Strobe (CAS): This is the DRAM Column Address Strobe pin. It should be
connected to the CAS pins of all DRAM chips.

28

24

V DO: Positive supply. A single, stable +5 volt supply is required. Levels and voltages within the DVSR
Codec are dependent upon this supply.

Page 422

MX-COM, INC.

MX802

External Components

r

"00
4 X 1 Mbit

~

VSS

.

R,

RASI

WE
iCfAL
SEE INSEr XTAUCLOCK

-w
--

IRQ

I-_

gj~

DRAM

AO'-::";;;9
WE

28
27

CAS

3

26

A9

COMMAND DATA

8

CS

Allnln niiT
--11

Allnln 1M

q,~

C.

*24

6
7

REPLY DATA
VB1AS

*25

4*
5

SERIAL CLOCK

-~~

MX802J

23

AS

22

A7

21

A6

9

20

10

19

11

18

12

17

13

16

14

15

T~

r'

/

RAS3

~

~
AniI"Mn

~~

~

~D

V
V
I---'"

+-- ~~
RAS

V

f-oD

1~

INSET

XTAL

R3
R2
XTALiCLOCK

Vss

4*
MXB02J

,

AO - A9

~WE

RAS
D

Component
Value
22.0kQ
R,
1.0MQ
R2
See Note 1
R3
1.0kQ
R.

5

,

Oro

' - - - ~~

A.

C,
C2
C3

Oro

~

Vss

,---------------------

0 ...

AO - MJ

AS

~

D

~WE

-

f--M----

Vss

,
, ]C, ]C.
,

r---- c:A!l
r---- RAS

I~

1*
2

1.0~F

C.
C,
C,

1.0~F
.OO1~F

X,
or
or

1.0~F

33.0pF
33.0pF

---------------------

1

of-.

Tolerance: R

4.00MHz
4.032MHz
4.096MHz

=±10%, C =±20%
'See Note 3

Figure 2 - Recommended External Component and DRAM Connections

Notes
1. Xtal circuitry shown in Inset is in accordance with the
MX-COM Standard and DBS BOO Crystal Oscillator Application Note.

6. Recommended DRAM Parameters:
256 kbit x 1 or 1 Mbit x 1 Dynamic Random Access Memory
with "CAS before RAS" refresh mode. Maximum Row
address access time = .200 lJSec.

2. External Xtal circuitry is not applicable to the 24 pin/lead
versions of this device. Only an externally derived clock
input can be used.

Example DRAM types:
256kbit (262, 144 bits)
Texas Instruments
Hitachi
1Mbit (1,04B,576 bits)
Texas Instruments
Hitachi

3. Functions whose pins are marked with an asterisk' in
Figure 2 are not available on the 24-pin/lead versions of
this device. Pin numbers illustrated are for 2B-pin versions.
4. Table 3 details the actual encoder/decoder sample rates
available using the Xtal frequencies recommended above.
5. Resistor Rl is used as the DBS BOO system common
pullup for the C-BUS Interrupt Request (IRQ) line. The
opti!!!!!.-m value will depend on the circuitry connected to
the IRQ line. Up to B peripherals may be connected to this
line.

MX-COM, INC.

TMS4256-20
HM51256-15
TMS4C1024-15
HM511000-15

7. Figure 2 above shows connections to 4 x 1 Mbit sections
of DRAM. If desired, to simplify PCB layout, the DRAM
inputs AO-AB may be connected in any order to the MXB02
DVSR Codec output pins AO-AB. Connections to 256 kbit
DRAM are similar, but A9 is left unconnected.
B. When using the MXB02 "stand alone" (Direct Access),
no DRAM sections should be connected.

Page 423

I

I

MX802

Controlling Protocol
Control of the functions of the MX802 DVSR Codec is by a group of Address/Commands (AlCs) and appended
instructions or data to and from the system microcontroller (See Figure 4). The use and content of these instructions
is detailed in the following pages.

General Reset

01

00000001

Write to Control Register

60

01100000

Read Status Register

61

01100001

Store "N" pages. Start page "X"

62

01100010

Store "N" pages. Start page "X"

63

01100011

Play "N" pages. Start page "X"

64

01100100

Play "N" pages. Start page "X"

65

01100101

Write Data. Start page "P"

66

01100110

+ 2 byte instruction to Control Register
+ 1 byte reply from Status Register
+ 2 bytes Command -- Immediate
+ 2 bytes Command -- Buffered
+ 2 bytes Command -- Immediate
+ 2 bytes Command -- Buffered
+ 2 bytes "P" + Write Data

Read Data. Start page "P"

67

01100111

+ 2 bytes "P" + Read Data

Write Data -- Continue

68

01101000

+ Write data

Read Data -- Continue

69

01101001

+ Read data

Table 1 - C-8US Address/Commands

Address/Commands
Instruction and data transactions to and from this device consist of an Address/Command (AlC) byte followed by
further instruction/data or a status/data reply.
Control and configuration is by writing instructions from the microcontrollerto the Control Register (60 H). Reporting
of MX802 configurations is by reading the Status Register (61 H).

Operation with DRAM
The MX802 can operate with up to 4 Mbits of Dynamic RAM (DRAM). When used with DRAM, the MX802
performs four main functions under the control of commands received over the C-BUS interface from the microcontroller:
Stores Speech: The MX802 stores speech by digitally
encoding the analog input signal and writing the resulting
digital data into the associated DRAM.
Plays Speech: The MX802 plays back stored speech by
reading the digital data stored in the DRAM and decoding
it to provide an analog output signal.

Page 424

Writes Data: The MX802 writes data sent over the C-BUS
from the microcontroller to DRAM.
Reads Data: The MX802 reads data from DRAM, sending
it to the microcontroller over the C-BUS.

Data is directed to and from DRAM by the on-chip DRAM
Controller.

MX-COM, INC.

MX802

Controlling Protocol
Speech
The CVSD encoder and decoder sampling rates are
independently set via the Control Register (see Tables 2,
3 & 4) to 16, 25, 32, 50 or 64 kbps. This allows the user to
choose between speech quality and storage time while
providing for time compression or expansion of the speech
signals.
The DVSR Codec can handle from 256 kbits to
4 Mbits of DRAM, giving, in the case of the 32 kbps
sampling rate, from 8 to 131 seconds of speech storage.
For speech storage purposes, the memory is divided
into "pages" of 1024 bits each, corresponding to 32ms at
a 32 kbps sampling rate.
256 "pages."
1024 "pages."
4096 "pages."

A 256 kbit DRAM contains
A 1 Mbit DRAM contains
A 4 Mbit DRAM contains

When used without DRAM, the decoder sampling
rate (8-64 kbps) is determined by an external clock source
applied to the Decoder Clock pin.
Store and Play Speech Commands
Speech storage and playback may take place simultaneously. These commands are transmitted, via C-BUS,
to the MX802 in the following form:
STORE OR PLAY "N" (1024-bit) PAGES ( of encoded
speech data) STARTING AT PAGE "X."
"N" can be any number between 0 and F (1-16
pages). "X" can be any number from 0 to 4095 (4Mbit
DRAM), as shown below. Preceded by AlC, this command
writes 16 bits (byte 1 and byte 0) of data from the
microcontroller to the Store or Play Command Buffer.

I

MSB
BYTE 1
BYTE 0
LSB
15 14 13 12 11 10 9 8 7. 6 5 4 3 2 1 0

X
Speech Store Commands
62H STORE "N" PAGES -- START PAGE "X" (immediate)
63H STORE "N" PAGES - START PAGE "X" (buffered)
The digitized speech from the CVSD encoder is
stored in consecutive DRAM locations with the Speech
Store Counters sequencing through the DRAM addresses
and counting the number of complete pages stored since
the start of the execution of the command.
As soon as the command has terminated, the following events take place:

MX-COM, INC.

1. The Store Command Complete bit in the Status
Register (Table 5) is set.
2. An Interrupt Request (IRQ) is sent, if enabled, to
the microcontroller.
3. The next speech storage command (if present) is
immediately taken from the Store Command Buffer
and execution of the new command commences.
The IRQ output is cleared by reading the Status Register:
61H

READ STATUS REGISTER

(Table 6).

To provide continuity of speech commands, both
Store and Play Commands can be presented to eh MX802
in one of two formats: immediate or buffered.
An immediate command will be started on completion of its loading, irrespective of the condition of the
current command.
A buffered command will begin after the completion
of the current Store or Play command, unless Speech
Synchronization Bits (Control Register) are set.
Buffe~ing of commands lets the DVSR Codec execute a series of commands without intervening gaps even
though the microcontroller may take several milliseconds
to respond to each "Command Complete" Interrupt Request.
In either case, the Store or Play Command Complete
bit of the status register will be cleared.
Speech Playback is controlled by similar commands
using the Speech Play Counters and Play Command
Buffer:
64H PLAY "N" PAGES - START PAGE "X" (immediate)
65H PLAY "N" PAGES - START PAGE "X" (buffered).
As soon as the Play Command has completed, the
"Play Command Complete" bit in the Status Register is set,
and an Interrupt Request is generated (if enabled).
If no "nexf' command is waiting in the Play Command
Buffer when a speech play command finishes, a continuous idle code (0101.. .. 0101) will be fed to the delta
decoder.
Speech data is stored or recovered at the selected
Encode or Decode sample rate (Table 3). Store or Play
Command Complete bits in the Status Register are cleared
by the next Store or Play Command received from the
microcontroller, or by a General Reset (01 H).

Page 425

I

MX802

Controlling Protocol
Speech ...
Store/Play Speech Synchronization (Table 4)
This capability is provided primarily for Time Domain
Scrambling applications.
Speech Synchronization bits in the Control Register
will produce the effects described below:
No Speech Sync Set: Store and Play operations may take
place completely independently.
Store after Play: The next buffered store command will
start on completion of a play command, while the next play
command sequence (if any) continues normally.
Play after Store: The next buffered play command will
start on completion of a store command, while the next
store command sequence (if any) continues normally.

These actions will continue while Speech Sync bits are set.

Data Handling
For the purpose of storing data sent via C-BUS from
the microcontroller, the memory (DRAM) is divided into
"data pages" of 64 bits (8 bytes).
A 256kbit DRAM contains

I

4096 data pages.

A 1Mbit DRAM contains

16384 data pages.

4Mbit DRAM contains

65536 data pages.

Read data), the C-BUS serial clock rate is limited to a
maximum of:
125kHz if the VSR Codec is executing store and play
commands.
250kHz if no speech Store or Play commands are
active.
This limitation is due to the rate at which data goes
into and out of the DRAM. All other commands and replies
(Control, Status, Reset) may use a maximum clock rate of
500kHz. See Figure 4.
Read Data

67 H

This command sets the Data Read Counter to "P,"
page, and then reads data bytes from successive DRAM
locations, sending them to the microcontroller as Reply
Data bytes. The Data Read Counter is incremented by 1
for each bit read.
69H

C-BUS Data Transfer Limitations
For those commands which transfer data over the CBUS between DRAM and the microcontroller (Write and

Page 426

READ DATA CONTINUE

This command reads data bytes from successive
DRAM locations determined by the Data Read Counter,
incrementing the counter by 1 for each bit read.
Write Data

66 H
In accordance with C-BUS timing specifications,
data is handled 8 bits (1 byte) at a time, although any
number of 8-bit blocks of data may be written to or read
from the DRAM by a single command.
Data transfer is terminated by the Chip Select line
going to a logic "1."

READ DATA -- START PAGE "P"

WRITE DATA -- START PAGE "P"

This command sets the Data Write Counter to "P"
page, and then writes data bytes to successive DRAM
locations, incrementing the Data Write Counter by 1 for
each bit received via the C-8US.
The Start Page, "P," is indicated by loading a 2-byte
word after the relevant Address/Command byte. This 16bit word allows data page addresses from 0 to 65535
(4Mbits DRAM).
68H

WRITE DATA CONTINUE

This command writes data bytes to successive DRAM
locations determined by the Data Write Counter,
incrementing the counter by 1 for each bit received over
the C-8US.

MX-COM, ING.

MX802

Controlling Protocol
DRAM Speech Capacity
28-pin/lead versions of the MX802 may be used with a single 256kbit DRAM, or with up to 4 x 1Mbit of DRAM. 24-pin/
lead versions may only be used with a single 256kbit or 1Mbit DRAM. The different encode and decode sampling clock
rates available enable the user to set voice store and play times against recovered speech quality. Table 2 gives
information on storage capacity and Store/Playback times. Speech data can be replayed at a different sample rate or
in a reversed sequence (see Control Register for details).
Nominal Sample Rates (llZ

"".,. .,-7"16'1'5'1-4"13'1'2'1-1'I0-&"'" ----MSB

Logic level Is not Important

LSB
FIRST REPLY DATA BYTE

LAST REPLY DATA BYTE

Figure 5 - C-8US Timing Information

tCSE
tCSH
tHIZ
ttCSOFF

Chip Select Low to First Serial Clock Rising Edge
Last Serial Clock Rising Edge to Chip Select High
Chip Select High to Reply Data High - Z
Chip Select High
Command Data Inter-Byte Time
Serial Clock Period

t~~T

2.0
4.0

4.0
4.0

8.0
8.0

2.0
4.0
2.0

4.0
8.0
4.0

8.0
16.0
8.0

1.0
1.0
.45
.60

Decoder or Encoder Clock High
Decoder or Encoder Clock Low
Decoder Data Set Up Time
Decoder Data Hold Time
Encoder Clock High to Encoder Data Valid
= Data True Time

.?5

Notes
1. Minimum Timing Values
(a) For all commands except "Read Data" and "Write Data" commands.
(b) For "Read Data" and "Write Data" commands when no "Speech Store" or "Speech Play" commands are
active.
(c) For "Read Data" and 'Write Data" commands when "Speech Store" or "Speech Play" commands are active.
2. Depending on the command, 1 or 2 bytes of Command Data are transmitted to the peripheral MSB (bit?) first, and
LSB (bitO) last. Reply data is read from the peripheral MSB (bit?) first, and LSB (bitO) last.
3. To allow for different microcontroller serial interface formats, C-BUS compatible ICs are able to work with either
polarity Serial Clock pulses.
4. Data is clocked into and out of the peripheral on the rising Serial Clock edge.
5. Loaded commands are acted upon at the end of each command.
ENCODER TIMING
ENCODER

ClOCK

DECODER CLOCK

EN~~~E~tPrATA ~L..I__...L...._-.JL...-_--L_ _....L..._
DaIa

DECODER TIMING

Sleeked

OEC~~~JATA "...-""'I~-_·+-I__...L...._ _L...-_---L_

l:gu~

i!:tHi
Data True
TIme

Figure 6 - Codec Direct Access Timing
MX-COM, INC.

Page 431

I

MX802

Codec Performance
Gain (dB)

+10

-OdB

0
-10

=
=

Input 0 dB Ref.
308 mVrms
-20 dB
Input Level
Sample Rates
16, 32 or 63 kbps

-20

=

-30
-40
-50
-60

2

0.2

3

4

5

6

Frequency (kHz)

Figure 7 - Typical Overall (Encoder + Decoder) Frequency Response

SINAD

SINAD

(dB)

(dB)
30

30

20

20

I

=

Sample Rate = 32 kbps
dB ref. = 308 mVrms

Input Frequency
1.0 kHz
dB ref. = 308 mVrrns

o

-30

-24

-18

-12

-6

o

o

-30

Figure 8 - SINAD vs Input Level at Different Sample Rates

+10

-24

-18

-12

-6

o

Figure 9 - SINAD vs Input Level at Different Frequencies

Gain (dB)
-OdB

0
-10

=
=

Input 0 dB Ref.
308 mVrms
-20 dB
Input Level
Sample Rates = 25 or 50 kbps

-20
-30
-40
-50
-60
0.2

2

3

4

5

6

Frequency (kHz)

Figure 10 - Typical Overall (Encoder + Decoder) Frequency Response
Page 432

MX-COM, INC.

MX802

Specifications
~ll:de 1 -> 0" to latch the new data
in. Data is executed on the falling edge of the strobe. If the Load/Latch input is used this pin should
be left open circuit - This input has an internal 1Mil pullup resistor.

3

Load/Latch: This is the inverted Load/Latch input. This function governs the loading and execution of
the control data. During serial data loading this input should be kept at a logical "1" to ensure that data
rippling past the latches has no effect. When all 8 bits have been loaded this input should be strobed
"1 -> 0 -> 1" to latch the new data in. Data is executed on the rising edge of the strobe. If the Load!
Latch input is used this pin should be left open circuit - This input has an internal 1Mil pulldown
resistor.

4

Ch 1 Input:

5

Ch 2 Input:

6

Ch 3 Input:

7

Ch 4 Input:

8

V B1AS : The output of the on-chip bias circuitry, held at Vod2. This pin should be decoupled to Vss as
shown in Figure 2.

9
10
11
12

Ch
Ch
Ch
Ch

13

V..: Negative supply rail (GND).

14
15
16
17

Ch
Ch
Ch
Ch

18

No internal connection. Do not use.

19
20
21
22

5
6
7
8

8
7
6
5

Input:
Input:
Input:
Input:

Output:
Output:
Output:
Output:

Analog Inputs:
These individual amplifier inputs are self-biasing; input
analog signals must be a.c. coupled to these pins, as shown in
Figure 2. In the powersave modes the inputs are biased at
Voo/2. Ch1 to Ch7 range from -3dB to +3dB in 0.43dB steps.
Ch8 could be utilized as a volume control ranging from -15dB
to + 15dB in 2.0 dB steps.

Analog Inputs

Analog Outputs: These are the individual "Gain Controlled" amplifier outputs.
Ch1 to Ch7 range from -3dB to +3dB in 0.43dB steps. Ch8 could be
used as a volume control, ranging from -14dB to +14dB in 2.0dB steps.
In the powersave modes the selected output is biased at Vod2.

Output: Analog Outputs
Output:
Output: Note that amplifiers Ch1 to Ch8
1 Output: are "inverting amplifiers."

23

Voo: Positive supply. A single +5-volt power supply is required.

24

Control (Data) Input: Operation of the 8 amplifier channels (Ch1 - Ch8) is controlled by the 8 bits of
data entered serially at this pin. The data is entered (bit 7 to bit 0) on the rising edge of the external
Serial Clock. The data format is described in Tables 1, 2 and Figure 4. This input has an internal 1Mil
pullup resistor.

Page 450

MX-COM, INC.

MX009

Application Notes

Serial Clock Inout

LoadIlaIch

LoadILaIch
Qbl[![]gl 1

!ci2W

Ql:]gnngl 2 IneW
~IiIDDeI

3 ICDld

Chan"" 4 Input

24

2

23

3

22

4

21

Voo

, C1

,C2
ICS

1'C4

l

-

Channel 5 Input
Channel 6 Input
Channel 7 Input

idliooal iii JopLa

I CS

1C6
I C7
ICS

_L!
Channel 1 OuInut

I

C10

Channel 2 OutDut

Channel 3 Outout
5
6

20
"hAnnAI

MXOO9

autn,.

19

7

18 I---X

8

17

9

16

10

15

11

14

12

13

VBIAS

CS ~

)'

Serial Control Data lnout
1

Channel 5 Outout
Channel 6 Outnut
('.hAnnAI 7 autn,.

Notes
(1) Channel Amplifiers 1 to 8 are inverting
amplifiers.
(2) Analog input capacitors C1 to Cs are only
required for a.c. input signals; d.c. input Signals
do not require these components.

Channel 8 Outout

VSS

Component

1

Unit Value

0.1J..lF
1.0J..lF
1.0J..lF

I

Tolerances ± 20%

Fig. 2 - External Component Connections

Application Recommendations
To avoid noise and instability the following
practices are recommended:

(d) Analog tracks should not run parallel to digital
tracks.

(a) Use a clean, well-regulated power supply.
(b) Keep leads short.

(e) A "Ground Plane" connected to Vss will assist in
eliminating external pick-up on the channel input and
output pins.

(c) Inputs and outputs should be shielded wherever
possible.

(f) Avoid running High Level Outputs adjacent to Low
Level Inputs.

(g) Input signal amplitudes should be applied with
regard to Figure 3.

MX-COM, INC.

Page 451

MX009

SINAD (dB)
60

50

Input Frequency = 1.0kHz
Input Level OdB ref. = 775mVrms
Ch1 to ChB Gain Set to OdB
40

10

25·

75

110

250

775

-20

-17

-10

o

1000

1730

30--h-+-r"T""T"T""T"T""T..,-L,~~~~+-r-n'-rr"T""T"T""T-+-r~~~~+'-+'....,..,--r\~~mVrms
dB
-40

-30

7

Input Level

Figure 3 - SINAD vs. Input Level: Typical Values

Control Data and Timing
The gain of each amplifier block (Channels 1 to 8) in the MX009 is set individually by an 8-bit data word (bit
7 to bit 0). This 8-bit word, consisting of 4 Address bits (bit 7 to bit 4) and 4 Gain Control bits (bit 3 to bit 0)
is serially loaded to the Control Data Input using the external data clock. Data is loaded to the MX009 on the
rising edge of the Serial Clock. Loaded data is executed on the falling edge of the Load/Latch pulse and on
the rising edge of the Load/Latch pulse. Table 1 shows the format of each 4-bit Address word. Table 2 shows
the format of each Gain Control word and Figure 4 shows the data loading operation and timing.

Table 2 Gain Control Word Format

Table 1 Address Word Format

I

0
0
0
0
1
1
1
1

Page 452

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
2
3
4
5
6
7
8

0
0
0
0

0
0
0
0
1
1
1

0
0
0
0
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Powersave Powersave
-3.0
-14.0d8
-2.571
-12.0d8
-2.143
-10.0d8
-1.714
-8.0d8
-1.286
-6.0d8
-0.857
-4.0d8
-0.428
-2.0d8
0
0.Od8
0.428
2.0d8
0.857
4.0d8
1.286
6.0d8
1.714
8.0d8
2.143
10.0d8
2.571
12.0d8
3.0
14.0d8

MX-COM, INC.

MX009
Data Loading
The 8-bit data word is loaded bit 7 first and bit 0 last. Bit 7 must be a logic "1" to address the chip. If
bit 7 in the word is a logic "0" that 8-bit word will not be executed. Figure 4 (below) shows the timing
information required to load and operate this device.

Serial Data Clock

•
.,......-t

08 --------"

•

.' t OOH •
...........

Serial Data In

~

~ ~

Logic '1"
loacfed first

Bit 7

)(
Bit 6

Bit 1

•

x~

Loaded last
Bit 0

..:<01(--..

t LL

----...:

-----'/~\

Load/Latch

:..--t LLW -----.:

\

Load/Latch

/

I

Timing

Serial Clock "High" Pulse Width

Data Set-up Time

Load/Latch Set-up Time

Serial Clock "Low" Pulse Width

Data Hold Time

Load/Latch Pulse Width

Figure 4 - Serial Control Data Loading Diagram

MX-COM, INC.

Page 453

MX009

Specifications
nr'Aratinn

Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits
is not implied.

All device characteristics are measured under the following conditions unless otherwise specified:

"

,

Supply voltage
Input voltage at any pin
(ref V ss OV)
Sink/source current (supply pins)
(other pins)
Total device dissipation
(@TAMB 25°C)
Derating
Operating temperature:
Storage temperature:

=

I

Limits

Absolute. Maximum. Ratings

-0.3V to 7.0V
-0.3V to (V 00 + 0.3V)
±30mA
±20mA

Voo

=5.0V

Audio level OdB ref = 775 mVrms.

800mW Max.
10mW/oC
-40°C to + 85°C
-55°C to + 125°C

Static Values
Supply Voltage (V 0 )
Supply Current
-~owersave
-All Stages Operating
Dynamic Values
Input Logic "1"
Input Logic "0"
Digital Input Impedances
Amplifier Stages (General)
Bandwidth (-3d B)
Output Impedance
Total Harmonic Distortion
1
Output Noise Level (per stage)
2
Onset of Clipping
3
4
Gain Variation
Interstage Isolation
"Trimmer" Stages (Ch 1 - Ch 7)
Gain
Gain Steps (15 in No.)
Step Error
5
Input Impedance
"Volume" Stage (Ch 8)
Gain
Gain Steps (15 in No.)
Step Error
5
Input Impedance
Timing (See Figure 4)
Serial Clock "High" Pulse Width (tpWH)
Serial Clock "Low" Pulse Width (tpWL)
Data Set-up Time (tos)
Data Hold Time (t oH )
Load/Latch Set-up Time (t LL)
Load/Latch Pulse Width (t LLW)
Serial Data Clock Frequency

4.5

5.0
0.16
4.0

5.5
1.0
8.0

V
mA
mA

1.5

V
V
MQ

3.5
1.0

0.5
15.0

0.8
0.35
65.0
1.73

3.0
0.5
0.1

60.0
-3.0

+3.0
0.43
±0.2

100.0
-14.0

+14.0
2.0
±0.4

50.0
250
250
150
50
250
150
2.0

kHz
kQ
%
IlVrms
Vrms
dB
dB
dB
dB
dB
kQ
dB
dB
dB
kQ
ns
ns
ns
ns
ns
ns
MHz

Notes
1.
2.
3.
4.
5.

Page 454

Gain Set OdB. Input Level 1kHz -3.0dB (S49mVrms).
a.c. short-circuit input, measured in a 30 kHz bandwidth.
See Figure 3.
Over temperature and supply voltage range.
With reference to a 1.0 kHz signal.

MX-COM, INC.

MX· ~M, IN[!.

MX019

Preliminary Information

QUAD DIGITAL CONTROL AMPLIFIER
Features
• 4 Digitally Controlled Amplifiers
• 15 Gain/Attenuation Steps
• 3 Amplifiers with a :t 3dB Range
in O.43dB Steps
• 1 'Volume' Amplifier with a
:t 14dB Range in 2dB Steps

MX019J
(16-pin CDIP)
MX019P
(16-pin PDIP)

• 8-Bit Serial Data Control
• Output Mute Function
• Audio and Data Gain Control
Applications
• Telecommunications, Radio
and Industrial Applications

MX019DW
16-pin SOIC

DESCRIPTION
The MX019 Digitally Adjustable Amplifier Array
replaces trimmer potentiometers and volume controls in
Cellular, LMR, Telephony and Communications
applications where voice or data signals need adjustment.
The MX019 is a single-chip LSI consisting of four
digitally controlled amplifier stages, each with 15 distinct
gain/attenuation steps. Control of each individual amplifier
is by an 8-bit serial data stream. Three of the amplifier
stages offer a +/-3dB range in steps of 0.43dB, while the
remaining amplifier offers a +/-14dB range in steps of 2dB,
and is suggested for volume control applications. Each
amplifier includes a 16th 'Off' state which, when applied,
mutes the output audio from that channel. This array uses
a Chip Select input to select one of two MX019s in a
system.

This product uses the host microprocessor to
digitally control the set-up of all audio levels during
development, production/calibration and operation.
Applications include:
(i) Control, adjustment and set-up of communications
equipment by an Intelligent ATE without manual
intervention - ego Deviation, Microphone and US
Levels, RX Audio Level etc.
(ii) Automatic Dynamic Compensation of drift caused
by variations in temperature, linearity, etc.
(iii) Fully automated servicing and re-alignment.
The MX019 is a low-power, single 5-volt CMOS
device available in 16-pin CDIP, PDIP and SOIC
package versions.

SERIAL CLOCKr-_ _ _ _ _ _ _ _ _ _--,
INPUT

LOAD/LATCH

SERIAL DATA
INPUT

LOAD/LATCH

Ch1

VOLUME

CHIP ADDRESS

•

~~"~
CONTROLLED AUDIO OUTPUT LINES

Figure 1 - Functional Block Diagram

MX-COM, INC.

Page 455

I

PIN FUNCTION TABLE

Serial Clock: This external clock pulse input is used to "clock in" the Control Data. See Figure 4,
Serial Control Data Load Timing. This input has an internal 1MQ pullup resistor.
2

Load/Latch: This input governs the loading and execution of the control data. During serial data
loading this input should be kept at a logical '0' to ensure that data rippling past the latches has no
effect. When all 8 bits have been loaded, this input should be strobed '0 - 1 - 0' to latch the new data
in. Data is executed on the falling edge of the strobe. If the Load/Latch input is used this pin should
be left open circuit. This input has an internal 1MQ pullup resistor.

3

Load/Latch: This inverted Load/Latch input governs the loading and execution of control data.
During serial data loading this input should be kept at a logical '1' to ensure that data rippling past
the latches has no effect. When all 8 bits have been loaded, this input should be strobed '1' - '0' - '1'
to latch the new data in. Data is executed on the rising edge of the strobe. If the Load/Latch input is
used this pin should be left open circuit. This input has an internal 1MQ pulldown resistor.

4

Ch1 Input:

5

Ch2lnput:

6

Ch3lnput:

7

Ch4lnput:

8

Vss: Negative supply rail (GND).

9

VBIAS: The output of the on-Chip bias circuitry, held at VDrl2. This pin should be decoupled to Vss as
shown in Figure 2.

10

Ch4 Output:

11

Ch3 Output:

12

Ch2 Output:

13

Ch1 Output:

14

Chip Address: A logic input to select one of two MX019 ICs in a system (see Table 1). This input
has an internal 1MQ pulldown resistor.

15

Control Data Input: Operation of the 4 amplifier channels (Ch1 - Ch4) is controlled by the 8 bits of
data entered serially at this pin. The data is entered (bit 7 to bit 0) on the rising edge of the external
Serial Clock. The data format is described in Tables 1, 2 and Figure 4. This input has an internal
1MQ pullup resistor.

16

Voo: Positive supply rail. A single +5-volt power supply is required.

Analog Inputs:

I

Page 456

These individual amplifier inputs are self-biasing, a.c. input analog
signals must be capacitively coupled to these pins, as shown in
Figure 2.
Note that amplifiers Ch1 to Ch4 are 'inverting amplifiers.'

Controlled Analog Outputs :
These are individual "Gain Controlled" amplifier outputs.
Ch1 to Ch3 range from -3dB to +3dB in 0.43dB steps, Ch4 can be
utilized as a volume control, ranging from -14dB to +14dB in
2.0dB steps.
In the "OFF" mode there is no output from the selected amplifier.

MX-COM, INC.

APPLICATION NOTES

s ERIAL

CLOCK INPUT

1

LOAD/LATCH

C HANNEL 1 INPUT
C HANNEL 2 INPUT
C HANNEL 3 INPUT
C HANNEL 4 INPUT

I~

I: C2
I: C3
I: C4
VSS

3

14 •

4

13

5

MX019

CHIP ADDRESS
CHANNEL 1 OUTPUT

11

7

10

Ca

•
•
•
•

CHANNEL 2 OUTPUT

12

6
8

-

CONTROL DATA INPUT

15 •

2

L
-OAD/LATCH

I
=f.

V DD

16

CHANNEL 3 OUTPUT
CHANNEL 4 OUTPUT

9 ~VBIAS

T.
Notes
(1) Channel Amplifiers 1 to 4 are inverting amplifiers.

Cs

Component

(2) Analog input capacitors C, to C. are only required for a.c. input
signals, d.c. input signals do not require these components.

Value

C,toC.

O.lI'F

C,
C,

1.01'F
1.01'F

Tolerances: C = ± 20%

Figure 2 - External Component Connections

Application Recommendations
To avoid excess noise and instability you should take note of the following:
(a) A noisy or badly regulated power supply can cause
instability and/or variance of selected gains.
(b) Care should be taken on the design and layout of
the printed circuit board.

(e) Tracks should be kept short.
(f) Analog tracks should not run parallel to digital
tracks.

(c) All external components (Figure 2) should be kept
close to the MX019 package.

(g) A "Ground Plane" connected to Vss will assist in
eliminating external pick-up on the channel input and
output pins.

(d) Inputs and outputs should be shielded wherever
possible.

(h) Do not run high-level output tracks close to lowlevel input tracks.

60

SINAD (dB)

50

Input Frequency = 1.0kHz
40

Input Level OdS ref = 775mVrms
Ch1 2, 3 or 4 Gain Set to OdS
1730.0

30~~lTO.~0~-rrT,-2r5r·0~-rrT~,-7~5.~0-r11rOr·0~-rrr2~5~Or·0rT~'-rT"'-+<~-rr.m_V_r_ms
-40
-30
-20 -17
-10
7.0
o
INPUT LEVEL dB

Figure 3 - SINAD vs Input Level - Typical Values

MX-COM, INC.

Page 457

I

Control Data and Timing
The gain of each amplifier block (Channel 1 to Channel
4) in the MX019 is set by a separate a-bit data word (
bit 7 to bit 0 ). This a-bit word, consisting of 4 Address
bits (bit 7 to bit 4) and 4 Gain Control bits (bit 3 to bit
0), is loaded to the Control Data Input in serial format
using the external data clock.

Data is loaded to the MX019 on the riSing edge of the
Serial Clock. Loaded data is executed on the falling
(rising) edge of the Load/Latch (Load/Latch) pulse.
Table 1 shows the format of each 4-bit Address word,
Table 2 shows the format of each Gain Control word
with Figure 4 describing the data loading operation and
timing.

Table 1 Address Bits Format

Table 2 Gain Control Bits Format

Bit7 Bit 6
MSB
1
1
1
1

0
0
0
0

1
1
1
1

1

- - r--1
1
1

BitS Bit 4
LSB
0
0
1
1

Chip
Channel
Chip
Address Address Number

0
1
0
1

1
2
3
4

0
0
0
0

1
0
1

2
3
4

BIt2

Bit 1

Bit 0
LSB

Stage 1, 2, 3
(O.43dB)

Stage 4
(2.0dB)

0

0

0

0

OFF

OFF

Chip

0

0

0

1

-3.0

-14.0dB

1

0

0

-2.571

-12.0

1

0

-2.143
-1.714

-10.0

0

0
1

1
1

0

0

---- --- - - --1
0
0
1
0
1
1

Bit 3
MSB

1

Chip

0

1

0

0
1

1
1

2

0

1

1

Data Loading
The a-bit data word is loaded bit 7 first and bit 0 last.
Bit 7 must be a logic "1" to address the chip.
If bit 7 in the word is a logic "0" that a-bit word will not be
executed. The Chip Address input permits the use of two
devices in a system by indicating to the chip what its
address is, a "1" or a "0." Bit 6 in the address section of
the control word is then used to select which device is
being controlled. Figure 4 (below) shows the timing
information required to load and operate this device.

-8.0

-1.286

-6.0

0

-0.857

-4.0
-2.0

0

1

1

1

-0.428

1

0

0

0

0

0

1

0

0

1

0.428

2.0

1

0

1

0

0.857

4.0

1

0

1

1

1.286

6.0

1

1

0

1.714

8.0

1

1

1

0

2.143
2.571

10.0

1

0
1

0
1

1

1

1

1

3.0

14.0

12.0

SERIAL DATA CLOCK

I

Logic '1'
Loaded
First
BIT 7

LOADILATCH

LOADILATCH

Timing
IPWH

IDS

Serial Clock ·'High" Pulse Width

Data Set-up Time

Load/Latch Set-up Time

IPWL

IDH

tLLW

Data Hold Time
I LW

tLLO

LoadiLatch Delay

Load/Latch Over Time

Serial Clock '·Low" Pulse Width

Fig.4 Serial Control Data Loading Diagram

Page 458

ILL

Load/Latch Pulse Width

MX-COM, INC.

SPECIFICATIONS
Absolute Maximum Ratings

Operating Limits

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.

Supply Voltage
Input Voltage at any pin
(ref Vss= OV)
Sink/Source Current
(supply pins)
(other pins)
Total Device Dissipation
@ TAMS 25°C
Derating
Operating Temperature
Storage Temperature

-0.3V to (V DD + 0.3V)

MX-COM, INC.

1.
2.
3.
4.

Audio Level OdB ref. = 775mVrms

±30mA
±20mA

Amplifier Gain Set = OdB
800mW max.
10mWrC
-40°C to +85°C
-55°C to + 125°C

Static Values
Supply Voltage (V DD )
Supply Current
Dynamic Values
Control Functions
Input Logic '1'
Input Logic '0'
Digital Input Impedances
Amplifier Stages (General)
Bandwidth (-3d B)
Output Impedance
Total Harmonic Distortion
Output Noise Level (per stage)
Onset of Clipping
Gain Variation
Interstage Isolation
"Trimmer" Stages (Ch1 - Ch3)
Gain
Gain per Step (15 in No.)
Step Error
Input Impedance
"Volume" Stage (Ch4)
Gain
Gain per Step (15 in No.)
Step Error
Input Impedance
Timing (Figure 4)
Serial Clock "High" Pulse Width
Serial Clock "Low" Pulse Width
Data Set-up Time
Data Hold Time
Load/Latch Set-up Time
Load/Latch Pulse Width
Load/Latch Delay
Load/Latch Over
Serial Data Clock Frequency
Notes

V DD =5.0V

-0.3 to 7.0 V

4.5

5.0
1.5

5.5

3.5
1.5
0.5

1.0

20.0
1.0
0.35
180.0
1.73

1
2
3
4

0.5
400.0
0.1

60.0
-3.0

+3.0
0.43
0.2

100.0
-14.0

+14.0
2.0
0.4

50.0
(tpWH)
(tpWL)
(t DS )
(t DH )
(t LL )
(t LLW )
(t LLD )
(t LLO )

250
250
150
50.0
250
150
200
50.0
2.0

V
mA

V
V
MQ
kHz
kQ
%
Il Vrms
Vrms
dB
dB
dB
dB
dB
kQ
dB
dB
dB
kQ
ns
ns
ns
ns
ns
ns
ns
ns
MHz

Gain Set OdB, Input Level 1kHz -3.0dB (549mVrms).
With an a.c short-circuit input, measured in a 30kHz bandwidth.
See Figure 3.
Over the temperature and supply voltage range.

Page 459

I

MX·~M,IN~.

MX029

Preliminary Information

DUAL DIGITALLY CONTROLLED AMPLIFIER

FEATURES
•
•
•
•
•
•

2 Digitally Controlled Amplifiers
±48dB Gain/Attenuation in 2dB Steps + Mute
Individual Control with a 14-Bit Serial Word
Output Mute/Powersave Function
Digitally Set Audio Control Levels
Separate Fixed Gain Buffer Amplifier

MX029DW
16-pin SOIC

MX029J
16-pin CDIP

APPLICATIONS
•
•
•
•

Cellular and LMR Radios
PABX's, Electronic Mail, TAM's
Automatic Test Equipment
Remote Gain Adjustments

eLK
DATA
LOAD

DESCRIPTION

I

The MX029 Digitally Controlled Amplifier Array replaces audio level controls in radio and wireline communications applications. It is a single-chip LSI circuit comprised of two discrete, digitally controlled gain sections.
Each section has 48 distinct gain steps (+/-48dB of range
in 2dB steps) plus MUTE. The "MUTE" state sets the
output to bias (VDD/2) and powersaves the addressed
section. Minimum current drain results from muting both
sections.
As shown in Figure 1 , both gain stages have switchable inputs. This switching allows for selection of three
different input signals on one channel and two on the other
channel. One of the channels also has output switching.
In addition to two digitally controlled gain stages,
there is a general purpose inverting amplifier. The gain of
this amplifier is controlled externally via negative feedback. Control of each gain control section is accomplished
through the serial interface. All switching is accomplished
using controlled rise and fall times, thereby assuring no
transients (clicks or pops).
The MX029 requires a single 5-volt supply and is
available in 16-pin CDIP and SOIC packages.

Page 460

TOOTAGE
CONTROL

REGISTER

INS

~
,.---i:!J
Vss

OUTIB

BIAS

f=t>----.

OUTS

BIAS

Figure 1 - Functional Block Diagram

MX-COM, INC.

MX029

Pin Function Table
Serial Clock: This external clock input is used to "clock in" the Control Data. See Figure 4 for timing
information. This input has an internal 1MO pullup resistor.
2

Control (Data) Input: Operation of the two amplifier channels (Ch1 - Ch2) is controlled by the data
entered serially at this pin. The data is entered (bit 13 to bit 0) on the rising edge of the external Serial
Clock. The data format is described in Tables 1-5 and Figure 3. This input has an internal 1MO pullup
resistor.

3

Load/Latch: This function governs the loading and execution of the control data. During serial data
loading this input should be kept at a logical "1" to ensure that data rippling past the latches has no
effect. When all 14 bits have been loaded this input should be strobed "1 -> 0 -> 1" to latch the new data
in. Data is executed on the rising edge of the strobe.

4

Ch 1 Input 1:

Analog Input.

5

Ch 1 Input 2:

Analog Input.

6

Ch 2 Input 1:

Analog Input.

7

Ch 2 Input 2:

Analog Input.

S

Vss: Negative supply rail (GND).

9

VB1AS : The output of the on-chip bias circuitry, held at Vorj2. This pin should be decoupled to Vss as
shown in Figure 2.

10

Ch 1 Input 3:

Analog Input. Normally used for FSK data.

11

Ch 2 Output 1:

Analog Output.

12

Ch 1 Output 1:

Analog Output.

13

Ch 1 Output 2:

Analog Output.

14

Universal Amplifier Output: Output from general purpose amplifier.

15

Universal Amplifier Input: Inverting input to general purpose amplifier.

16

V DD: Positive supply rail. A single +5-volt power supply is required.

MX-COM, INC.

I

Page 461

MX029

OV DO
Serial Clock Input

'--"

1
Serial Control Data Input

LoadIlatch
Ch 1 InPUt 1
Ch 1 Input 2
Ch 2 Input 1
Ch 2 Inpyt 2

I }C1
"C2

2

15

3

14

4

13

MX029

5

II C3

11C4
Vss

I

VDD
16

12

6

11

7

10

9

8

Universal Amp In
Universal Amp Out
Ch 1 OUlnut 1

==,C6

Ch 1 Output 2
Ch 2 OulDut
Ch 1 InDut 3

:~

V B1AS

--

Analog input capacitors C1 to C5 are only required
for a.c. input signals; d.c. input Signals do not
require these components.

Component
C1 toC5
C6

Value
O.1I1F
1.011F

Tolerances 20%

I

Figure 2 - External Component Connections

Application Recommendations
To avoid noise and instability the following practices are recommended:
(a) Use

a clean,

well-regulated power supply.

(b) Keep leads short.
(c) Inputs and outputs should be shielded wherever possible.
(d) Analog tracks should not run parallel to digital tracks.
(e) A "Ground Plane" connected to Vss will assist in eliminating external pick-up on the channel input and output
pins.
(f) Avoid running High Level Outputs adjacent to Low Level Inputs.
(g) The serial clock should not be running consecutively when not in the process of actually loading data.

Page 462

MX-COM, INC.

MX029

Control Data and Timing
The gain and 1/0 signal path for each section (Channels 1 and 2) is set individually by a 14-bit data word (00
to 013). Oata is loaded on the rising edge of the Serial Clock. Loaded data is executed on the rising edge of the
LoadlLatch pulse.The 14-bit word consists of 1 channel address bit (07) for selection of the channel to be programmed, 6 bits for setting the gain/attenuation level (08-013), 3 bits for input selection (04 and 06), and 4 bits for
output settings (00-03). This format is illustrated below in Figure 3.

GAIN/ATTN LEVEL

OUTPUT SETTINGS

INPUT
SELECT

Figure 3 - Data Word Format

Tables 1-5 show how the data word is used to control channel selection, gainlattenuation, input selection
and output settings, respectively.
To calculate the data word used to control channel gainlattenuation use the following formula:

25 +

gain dB)
( --2= the decimal equivalent of binary Oata Word

For example:
using a gain value of +34dB,
25 +

(+34 dB) = 42 = $2A = 013-08
2
101010

013

012

011

010

09

08

GAIN SET (dB)

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

MUTE
-48
-46
-44

-

-

1

0

0

1

0

0
1
0
1
0
1

+42
+44
+46
+48
+48
+48

-

0

-

1
1
1
1
1
1

-

1
-

0
0
1
1
1
1

-

-

1
1
0
0
0
0

-

-

1
1
0
0
0
0

-

-

1
1
0
0
1
1

-

I

-

-

Table 1 - Gain/Attenuation Level

MX-COM, INC.

Page 463

MX029
07

CHANNEL SELECTED

03

02

OUTPUT 2 SETTINGS

0
1

1

0
0

0

2

1
1

0

high impedance
amplifier output
VSS
VBIAS

Table2 - Channel Selection

06

05

04

INPUTS SELECTED

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

NONE
1
2
1&2
3
1&3
2&3
1,2, & 3

1
1

Table 4 - Settings for Output 2 (Ch 1 only)

01

DO

OUTPUT 1 SETTINGS

0
0
1
1

0
1
0
1

high impedance
amplifier output
VSS
VBIAS

Table 5 - Settings for Output 1

Table 3 - Input Select

Serial Interface Timing
Figure 4 shows the timing relationships for the ser'ial interface. See specifications page for more information.
I

tPWH :

"
, -'

, ,
,

,

,~tDS_"

I

~ ;'-tDH

~~---D-13----~!:><:~---D-12-----~---D1----~:><: ~

,
,_t
_
ll

~~{i

~_a_~
__ro_h__________________________~~~~.________~

_

Serial Clock "High" Pulse Width
Data Set-up Time
Load/Latch Set-up Time

~

DO
,

,
,,-tu.w~

Serial Clock "Low" Pulse Width
Data Hold Time
Load/Latch Pulse Width

Figure 4 - Serial Timing Diagram

Page 464

MX-COM, INC.

MX029

Specifications
Absolute Maximum Raltinl:ls
Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not implied.
Supply voltage
Input voltage at any pin
(ref Vss = OV)
Sink/source current (supply pins)
(other pins)
Total device dissipation
(@TAMB 25°C)
Derating
Operating temperature:
Storage temperature:

-0.3V to 7.0V

VDD = 5.0V

-0.3V to (VDD + 0.3V)
±30mA
±20mA
800mW Max.
10mW/oC
-40°C to + 85°C
-55°C to +125°C

Supply Voltage
Current - All Stages Mute
- All Stages Operating
Digital Inputs
Input Logic "1"
Input Logic "0"
Digital Input Impedances
Gain Control Amplifier Stages
Bandwidth (-3d B)
Output Impedance
Total Harmonic Distortion
Interstage Isolation
Gain/Attenuation
Gain/Attenuation Steps (48 total)
Step Error
Input Impedance
Input Referred Offset Voltage (V ,OS)
Universal Amplifier
Bandwidth (-3d B)
Output Impedance
Total Harmonic Distortion
Open Loop DC Gain
Timing (See Figure 4)
Serial Clock "High" Pulse Width (tpWH)
Serial Clock "Low" Pulse Width (tpWL)
Data Set-up Time (t DS )
Data Hold Time (tDH )
Load/Latch Set-up Time (t LL)
Load/Latch Pulse Width (tLLW)
Serial Data Clock Frequency

All device characteristics are measured under the following conditions unless otherwise specified:

TAMB = 25°C
Audio level OdB ref = 775 mVrms.
External Components as shown in Figure 2.

4.5

5.0
0.1
3.0

5.5

3.5
1.5
0.5

1.0

3.3
2
46

1.0
0.35
60.0
48
2.0

2.0
0.5

0.4
50.0
10
3

10
1.0
0.35
60

3

2.0
0.5

250
250
150
50
250
150
2

V
mA
mA
V
V
Mn
kHz
kn
0/0
dB
dB
dB
dB
kn
mV
kHz
kn
0/0
dB

I

ns
ns
ns
ns
ns
ns
MHz

Notes on Characteristics:
1. Gain set to maximum (+48 dB)
2. Gain Set OdB. Input Level 1kHz -3.0dB (549mVrms).
3. Gain externally set to 10 dB.

MX-COM, INC.

Page 465

I

Page 466

MX-COM, INC.

ITechnical

Specifications

Section 8:
Telephony
The following section contains specifications on MX-COM's SPM devices for
telephone systems.
Subscriber Pulse Metering (SPM) is a poular method of charge metering
telephone calls at the PABX and subscriber level in Europe. Belgium, Finland, France,
Germany, Spain, Switzerland and Sweden are among the countries with SPM
standards. Each specifies unique tone pulse repetition rates, pulse lengths, pulse
pause lengths, pulse levels and frequency "must" and "must not" decode bandwidths.

Device

Description

Page

MX613

Global Call Progress Detector

p. 469

NEW

MX623

Line-Powered Call Progress Detector

p. 477

NEW

MX631

Low-Power SPM Detector

p. 483

NEW

MX641

Dual SPM Detector

p. 490

NEW

I
MX-COM, INC.

Page 467

I

Page 468

MX-COM, INC.

MX·~M,IN~.

MX613

Advance Information

GLOBAL CALL PROGRESS DETECTOR
Features
• MX.COM MiXed Signal CMOS
• Covers Worldwide Call Progress Frequencies
(300Hz to 2,150Hz)
• 3 Volt <1 rnA Requirement
• Decodes Single or Modulated Tones
• Analog InlSerial Data Out
• Speech Discrimination Ability
• IJProcessor Compatible Outputs

• TelephonelTelecoms, Radio and Fax/Modem
Applications

•

MX613DW
16-PinSOIC

MX613P
14-PinPDIP

DATA OUT
012345 .....

TIME

lAO

Figure 1 - Functional Block Diagram

Description
The MX613 is a wide-band, 'N-Tone' non-predictive
tone decoder that measures telephone system call
progress tones in PABX, Pay/Feature-Phone, Fax and
Modem systems.
Adhering to Must/Must-Not Decode limits and able to
measure inband frequencies in outband modulation, this
decoder measures the frequency of input signals in the
range 300 to 2, 150Hz. The result of each measurement
is presented to a system J.LProcessor as a 6-bit serial
word.
The decode frequency range, which covers the
world's call progress application spectrum, is processed
internally as two bands: LO = 300 to 660Hz and HI = 900
to 2150Hz. Frequency measurement is achieved by
counting the number of cycles in a set time period
(LO = 39.47ms or HI = 13.16ms). Bad signal/level quality
MX-COM, INC.

or NOTONE results in a count-abort, liming-reset and no
output from the decoder.
Front-end filtering is achieved using MX·COM's
patented Auto-Correlator.
Current frequency
information is output for the J.LProcessor using a Serial
Data, Clock and Interrupt interface.
Data from the MX613 should be processed by a
J.LProcessor whose algorithms are able to recognize the
frequency, sequence and/or cadence of input signals as
national call progress information; e.g.: 'Dial,' 'Busy,'
'Number-Unobtainable,' 'Ringing' and automatic tones
used by fax and modem systems. Software can be
simply configured to reject speech frequencies.
Available in SOIC and PDIP packages, this low-cost,
mixed signal IC has a typical power requirement of less
than 1mA at 3 volts and utilizes a telecom-system clock
input of 3.579545MHz to maintain frequency accuracy.
Page 469

I

I

MX613

Xtal/Clock: The input to the on-chip clock oscillator inverter. A 3.579545MHz Xtal or
externally derived telephone system clock (fXTAL) should be connected here. Operation
of the MX613 without a suitable Xtal/Clock input may cause device damage.

2

2

Xtal: The output of the on-chip clock oscillator inverter. See Figure 2.

3

3

No internal connection.

4

4

VBIAS: The internal circuitry bias line, held at V00/2 this pin must be decoupled to Vss.

5

5

Level In: The input for level discrimination. This input is internally biased to V BIAS' Signals
must be a.c. coupled, and the audio signal must be fed to both this pin and the Signal
In pin. Correct level detection determines the operation of this device (see Principles of
Decqqer Operation). But if you wish to disregard the amplitude of the input levels, the
MX,~~~'m~ be permanently enabled by pulling this pin to V DO and disabled by pulling to

VS$}.··

~...
",\"<

X______

BIT 4

.

.

~

:

---'> ...

B_IT__
O____

tHIZ ...

IRQ

Figure 4 - Data-Read Timing

Decoder Timing Characteristics
With reference to Figure 4, Data-Read Timing.

I

Characteristics

Min.

tpWH

Serial Clock "High" Pulse Width

250

ns

tpWL

Serial Clock "Low" Pulse Width

250

ns

teye

Serial Clock-Cycle Time

600

ns

tesE

Chip Select Low to Clock "High" Edge

450

ns

tesH

Last Clock "High" Edge to CS "High"

600

ns

tOH

Data Out Hold Time

0

ns

teos

Clock Edge to Data Out Set Time

200

ns

t'R

Interrupt (IRQ) Reset Time

200

ns

tOE

Chip Select "Low" to Data Enable

200

ns

tHIZ

Chip Select "High" to Output Tri-State

1000

ns

Typ.

Max.

Unit

Notes
1 Data is output bit 5 first. Bit 5 can be clocked into the IJProcessor by the first Serial Clock rising edge.
If 8 Serial Clock pulses are employed the last 2 data-bits will be "0" and should be ignored by the software.
2 Chip Select should be used to react to Interrupts and then returned to a logic "1".
If Chip Select stays low there will be no further Interrupts and no Data Output update.

Page 474

MX-COM, INC.

MX613

Specifications
Absolute Maximum Ratings

Operating Limits

Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not suggested.

All devices were measured under the following
conditions unless otherwise noted.

Supply Voltage
Input Voltage at any pin

-0.3 to 7.0V

Voo = 3.3V

(ref Vss=OV)
Sink/Source Current
(supply pins)
(other pins)

-0.3 to (Voo+ 0.3V)

Top = -40 to +85°C

±30mA
±20mA

Audio Level OdB ref = 775 mVrms
Xtal/Clock fo = 3.579545 MHz

Total Device Dissipation

(@ T AMB=25°C)
Derating
Operating Temperature
Storage Temperature

800mW max.
10 mW/oC
-40°C to +85°C
-55°C to +125°C

;u.Wt:c:;;;;~
Static Values
3.0

Supply Voltage (V DO) at 25°C

0.3

Supply Current

5.5

V

1.0

mA

70.0

100

% Voo

Input Logic

o

30.0

%Voo

Output Lo

90.0

100

% Voo

10.0

%Voo

Impedances
MQ

10.0

Chip Select and Serial Clock Input
Signal Input

kQ

Level Input

kQ

IRQ Output (Logic "0")

Q

Data Output (Logic "0")

Q

(Logic "1")

kQ

Dynamic Values
On-Chip Xtal Oscillator
MQ

10.0

R'N

230

ROUT

825

kQ

DC Voltage Gain

25.0

42.0

VN

Bandwidth at Unity Gain

5.0

11.0

MHz

Single Tone Operation
Must-Decode Input Level

MX-COM, INC.

2

-25.2

dB

Page 475

I

MX613

Must-Not Decode Input Level

-46.0

dB

LO Band Frequency Range

4

300

660

Hz

HI Band Frequency Range

4

900

2150

Hz

LO Band

25.0

Hz

HI Band

75.0

Hz

2

Frequency Resolution (Table 1)

Input SignallWhite-Noise Ratio (HI & LO Bands)
Interrupt Rate

(LO Band)

18.0
3

19.0

3

57.0

6

dB
Isec
Isec

1.0

12 secs
10.0

%

Notes

1.
2.

Must decode signal above

-C.".C.UIU.

If a supply other than 3.3 volts is used,
3.

Under 'Pure Tone' input conditions.

4.

For input frequencies of between 661 Hz and 899Hz the

5.

With an amplitude modulating frequency of between 16.0Hz

6.

Test noise input

= 5.0kHz at 100mVrms

I

Page 476

MX-COM, INC.

MX·~M,IN~.

MX623

Advance Information

LINE-POWERED CALL PROGRESS TONE DETECTOR
Features
• MX·COM MiXed Signal CMOS
• Measures Call Progress Tone
Frequencies ('Busy', 'Dial', 'Fax-Tone'
etc.)
• Telephone, PABX, Fax and Dial-Up
Modem Applications
• Low-Power Requirement (600J,LA at 3.3
VoltsTYP) for Line-Powered Applications

SIGNAL IN

• Custom Tone Decoder (13 Call-Progress
Frequencies Recognized)
• Operates to a 3.579545MHz Telephone
System Clock
• Operates Under
Simple Logic or
IJ.Processor System Control

MEASUREMENT
AND
DECODE

MX623P
16-PinPDIP

v55

CHIP SELECT

XTAUCLOCK

DATA
CHANGE

HOLD

PURS

Figure 1 - Functional Block Diagram

Description
The MX623 is a low-power decoding integrated circuit
that measures the frequency of telephone system call
progress tones.
With progress signals input from the telephone line,
this single-chip product is programmed to recognize up
to thirteen of the World's most commonly used
call-progress frequencies, analyze signal quality, and
present the measured result as a 4-bit parallel data word
at the tri-state Data Output.
Using the parallel information from the MX623, the
host system, can recognize such call progress
information as: 'Dial', 'Busy', 'Number Unobtainable',
'Ringing' and Fax/Modem system signals.
MX-COM, INC.

This information can then be used in simple or
complex applications to control telephone operations.
The data output will require a software format that can
analyze the frequency information from the MX623.
Requiring only a single 3.0[MIN] volt power supply, the
MX623 may be line-powered and will operate under
simple logic or system IlProcessor control using the
'Data-Change, 'Hold' and 'Chip-Select' functions.
The MX623, whose small size and low power
consumption makes it ideal for remote applications,
requires a 3.579545MHz telephone system clock or Xtal
input, is available in a 16-pin PDIP.

Page 477

I

MX623

1
2
3
4

Q3:
Q2:
Q1:
QO:

Data Outputs: A 4-bit parallel data word, forming a HEX character representing the
decoded tone frequency. This word is output after a successful decode. Table 1 details the
Hex character output codes for the relevant decoded tone frequencies. Upon power-up this
output is set to 'EH" but no Data Change pulse generated. These are tri-state outputs.

5

VDD: Positive supply rail. A minimum supply voltage of 3.Q volts is required. Levels and voltages within
this decoder are dependent upon this supply.

6

Signal In: The composite audio input. Signals to this pin should be a.c. coupled. The d.c. bias of the
limiter section is set internally; this pin should not be loaded with any other circuitry.

7

No internal connection. Leave open circuit.

8
9

I

10

Xtal/Clock: The input t
should be connected here (see

11

Vss: Negative supply rail (GND).

12

Hold: An input to control the Output Latch condition;
output to facilitate, if required, Interrupt and/or
With Hold placed "Low", with a tone input, the Data Change output
change, and the current output code is locked in the Output Latches
input signal. The output code remains as held until this input is returned "High"
this input is "High" the output data, QQ - Q3, cycles normally with the input audio.
internal 1.0MQ pullup resistor.

13

PURS: Power-Up ReSet. To reset internal circuitry at power-up; a logic "1" level is required at this pin
for a duration of at least 2.5ms after the XtallClock input and full V DD levels are applied. The component
configuration shown in Figure 2 is recommended; for slow-rising power supplies the time constant of
components should be increased accordingly.

14

IRQ: Interrupt Request. An output for iJProcessor operation; normally "High" this output is latched
"Low" when an internal data change occurs if the Chip Select input is "High". This output is reset
("High") the when Chip Select line is taken "Low". To permit ''wire-OR'' connection with other
peripherals, this output has a low-impedance when "Low" and a high-impedance when "High".

15

CS: Chip Select- A controlling function. When held "High" the Data Outputs QQ, Q1, Q2 and Q3 and
the Data Change output are disabled. When taken "Low" the Data Outputs QO, Q1, Q2 and Q3 and
the Data Change output are enabled; the Interrupt Request (IRQ) is reset ("High") when CS is taken
"Low". See Figures 3 and 4.

16

Data Change: A positive-going pulse is generated at this output when the data changes (Tone or
NOToNE). New tone-data is presented to the QQ, Q1 , Q2 and Q3 Data Outputs if the Hold input is set
"High". This is a tri-state output.

Page 478

MX-COM, INC.

MX623
Application Information

03

DATA OUTPUTS
A HEX Code
Output representing
the decoded tone
frequency --

02
01

See Table 1

o(

!!!~

COMPOSITE SIGNAL IN

I:

16

2

15

3

00

--

1

4
Voo
SIGNAL IN

C2

-

C,
C,

PUR S
--

5

12 •

6

11

7

10

HOLD

VSS

;>

~CLOCK

9 -

J-<
-==-

X1111
1'1

R2

~~ C4

v

YQ!.u§.
1.OMQ
1.OMQ
.0471LF
.0047ILF

R,
R,

iii~

-

IRO

13

MX623P

8

Component

-

CS

14

XTAL

C3~~

DATA CHANGE

YQ!.u§.
33.0pF
33.0pF
1.OILF
3.579545MHz
Tolerances R = :± 70%, C = :±20%

Component

C3
C.
C5
X,

Figure 2 - Recommended External Components

Hex

output Code
Character Q3 Q2Q1 QO
0

1
2
3
4
5
6

7
8
9
A

B
C

0
E
F

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Band Edges (Hz) Nominal
Upper
Lower
Center
Freq.
Edge
Edge

364
488
520
580
386
412
436
463
900
1273
1350
1750
2062

386
520
580
618
412
436
463
487
1008
1325
1455
1855
2140

375

500
550
600
400
425

450
475

950
1300
1400
1800
2100

Timing Information
With CS Low - Figure 3

After initial power-up and the Hold input inactive
(High), as frequencies are input, with the Data
Change output as an active (High) indicator, the
data is presented at the Data Outputs.
If/when the Hold input is placed active (Low), the
data at the Data Outputs is frozen and the Data
Change output held High at its next active excursion
-until the Hold input is returned High.
With the Hold input held High - Figure 4

As frequencies are input a correct decode will
produce an active (Low) interrupt level.
This interrupt (IRQ) is serviced and reset by an
active (Low) CS input.
Note the 'valid data' period at the Data Outputs.

frequency not guaranteed
frequency not guaranteed

NOTONE

Table 1 - Tone Decode Frequencies
MX-COM, INC.

Page 479

8

MX623

Application Information - Decoder Timing

VDD

PURS

~i

I

I

I

~IPURS
-----------------------------------------------------

I

SIGNAL IN

NOTONE :

NOTONE
Tone 'N'

~
I

I

~ I NT ~

[ '----------./

DE

--->i ~IRESP~
"~----__

,

i

~
X
i
DATA C_HA_N_G_E_________-----'nL-__' ---'nL--___-:-----11

OUTPUTS
001003

~

I

HOLD

~ I DC

I HOLD

~
~n~1
fl

2

~-----------

~

i

~

I

PUL

~ ,*- I NORM

Figure 3 - Timing with the Chip Select Input Held "Low"; CS and IRQ are not used

~

PURS

~lpURS

~_----------------------------------------------

SIGNAL _'N_____-+i_N_OT_O_N_E_ _ _ _ _ _ _ _ _ _ _-«

Tone 1

i
OUTPUTS
00 -.03

~~

__________
F _________

n

(INTERNAL)
DATA CH_A_N_G_E____________---'

I

~~~

________________

n

-+-______-----'

L ______________

L _ _ _ _ _ _ _ _ _ _ _ __

~IRIRQ~

\,-------,1
\'---~/
DATA OUT 00 - 03

TRI-STATE

VALID DATA
(READ DATA)

TRI-STATE

VALID DATA
(READ DATA)

Figure 4 - Timing with the HOLD Input Held "High"; CS and IRQ are used

Page 480

MX-COM, INC_

MX623
Specifications

~2~~:·,~~,~;:.'~i:~g~:~::j:
Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating
limits is not implied.
Supply voltage
Input voltage at any pin
(ref V ss = OV)
Sink/source current
(supply pins)
(other pins)

-0.3 to 7.0V

+/- 30mA
+/- 20mA

Total device dissipation
@ TAMB 25°C
Derating
Storage temperature range

800mW Max.
10mW/oC
-40°C to +85°C

-0.3 to (V DD + 0.3V)

Supply Voltage (V DD)
at 25°C
Operating Temperature

Min.
3.0

Max.
5.5

-40

+85

Unit
V

All device characteristics are measured under the
following conditions unless otherwise specified:
V DD = 3.3V
Top = -40 to +85 °C
Audio Level OdB ref: = 775mVrms
Xtal/Clock Frequency 3.579545MHz

=

~~~,~~:.,
Static Values
Supply Current
Input Logic "1"
Input Logic "0"
Output Logic "1"
Output Logic.,j}~

0.6

1.0

0.7
0.3
0.8
0.2

mA
%VDD
%V DD
%VDD
%VDD

,'-'

Impedance
CS and PURS Input
Hold Input
Signal Input
IRO Output (logic "1")
IRO Output (logic "0")
00 - 03 & Data-Change Outputs (logic "1")
00 - 03 & Data-Change Outputs (logic "0")
00 - 03 & Data-Change Outputs (high Z)
Dynamic Values
Signal Input Range
Decode Bandedge Tolerance

10.0
0.5
30.0

100
500
2.0

1.0

2,5
3

Xtal Inverter
Voltage Gain
Input Impedance
Output Impedance

35.0
-1.0

mVrms
1.0

0/0

160

VIV
MQ
kQ

50.0

ms
ms
ms

20.0
10.0

Decoder Timing - Figures 3 and 4
Power Up Reset Time
Data 'E' Time
NOTONE to Tone Response Time

tpURS
tDE
tRESP

MX-COM, INC.

2.5
31.0
4

MQ
MQ
MQ
kQ
Q
kQ
Q
MQ

27.0

Page 481
---

---

I

MX623

Tone to NOToNE Response Time
Data to Data-Change Pulse Time
Data-Change
idth
Hold to
HOLD to
IRQT

tNT
toe
tpUL

4

60.0
1.15

0.625
1.25
63.0
29.0

150
52.0
250
250
100

ms
ms
ms
IJs
IJs
ms
ns
ns
ns

Notes

1. This pin has an on-chip 1.0MO pull up resistor.
2.
3.
4.
5.

An a.c. coupled sine or squarewave.
See Table 1, Tone Decode Frequencies.
Delay between the change of input (Tone/NoTONE) and the change
The signal input maximum value is determined by the formula V 0[/2.83.

I

Page 482

MX-COM, INC.

MX·~M,IN~.

MX631

Advance Information

LOW VOLTAGE SPM DETECTOR
Features
•
•
•
•
•

Detects 12 & 16kHz SPM Frequencies
Low Power (3.0 Volt M1N <1.0mA) Operation
High Speech band Rejection Properties
Tone-Follower and Packet Mode Outputs
Applications
oComplex and/or Simple Telephone Systems
oCall-Charge/-Logging Systems

MX631DW
16-Pin SOIC

MX631P
16-Pin PDIP

Vss

SYSTEM
(12kHz/16kHz)

PACKET MODE
,---L~, OUTPUT

AMP OUT

VerAS

Figure 1 - Functional Block Diagram

Description
The MX631 is a low-power, system-selectable
Subscriber Pulse Metering (SPM) detector that indicates
the presence of both 12kHz or 16kHz telephone callcharge frequencies on a telephone line.
Deriving its input directly from the telephone line,
input amplitude/sensitivities are component adjustable
to the user's national 'Must/Must-Not Decode'
specifications via an on-chip input amplifier, while the
12kHz and 16kHz frequency limits are accurately
defined by the use of an external 3.579545MHz
telephone-system Xtal or clock-pulse input.
The MX631, which demonstrates high 12kHz and
16kHz performance in the presence of both voice and
noise, can operate from either a single or differential
analog signal input from which it will produce two
MX-COM, INC.

individual logic outputs:
1. Tone Follower Output - A 'tone-following' logic
output producing a "Low" level for the period of a
correct decode and a "High" level for a bad decode
or NOTONE.
2. Packet (Cumulative. Tone) Mode Output - To
respond and/or de-respond after a cumulative
40ms of good tone (orNoTONE) in any 48ms period.
This process will ignore small fluctuations or fades
of a valid frequency input and is available for
ILProcessor 'Wake-Up', Minimum Tone detection,
NOTONE indication or transient avoidance.
This system (12kHz/16kHz) selectable integrated
circuit, which may be line-powered, is available in 16-pin
plastic DIP and SOIC surface mount packages.
Page 483

I

MX631

Xtal/Clock : The input to the on-chip clock oscillator; for use with a 3.579545MHz Xtal in
conjunction with the Xtal output (see Figure 2). Circuit components are on-chip. Using this mode of
clock operation, the Clock Out pin should be connected directly to the Clock In pin. If a clock pulse
input is employed to the Clock In pin, this pin must be connected directly to V DD (see Figure 2).
Xtal: The output of the on-chip clock oscillator inverter.
Clock Out: The buffered output of the on-chip clock oscillator inverter. If a Xtal input is employed
this output should be connected directly to the Clock In pin.
~4t1Mt1Z

clock pulse input to the internal clock-dividers. In the clock pulse input
1) should be connected to VDD • (See Figure 2.)

No

V BIAS: The output of the on-chip
decoupled to Vss (see Figure 2).
V ss: Negative supply (GND).

Signal In (+):
Signal In (-): .
Amp Out:

The positive and negative inputs to, and the ou
the input gain adjusting signal amplifier. Refer to
for guidance on setting level sensitivities to national
and the selection of gain adjusting components.

No internal connection, leave open circuit.

Tone Follower Output: This output provides a logic "0" (Low) for the period of a detected tone and
a logic "1" (High) for NOToNE detection. See Figure 5.
Packet Mode Output: A logic output that will be available after a cumUlation of 40ms of 'good' tone
has been received. This packet tone follower will only respond when a tone frequency of sufficient
quality has been received for sufficient time, i.e. a cumUlation of 40ms in any 48ms; short tone
bursts or breaks will be ignored. This output provides a logic "0" (Low) for a detected tone and a
logic "1" (High) for NOTONE detection. See Figure 6.
System: The logic input to select device operation to either 12kHz (logic "1" - High) or 16kHz (logic
"0" - Low) SPM systems. This input has an internal 1Mil pullup resistor (12kHz).
Voo: Positive supply. A single, stable power supply is required. Critical levels and voltages within the
MX631 are dependent upon this supply. This pin should be decoupled to Vssby a capacitor mounted
close to the pin.
Note that if this device is 'line' powered, the resulting supply must be stable. See notes on IC
Protection from high and spurious line voltages.

Page 484

MX-COM, INC.

MX631

Application Information: External Components

,
: XTAUCLOCK

XTAUCLOCK

.-----"i1'-------~

X1
For use with a Clock-Pulse Input
- Remove Xtal (X1)
- Connect Pin 1 to vee

=~~~o~~~~~rsi~: ~~LOCK IN

- - -- ~- - - -->
CLOCK IN

XTAL
CLOCK OUT

CLOCK IN

16
SYSTEM

2

15

3

14

4
5

VBIAS
VSS

MX631

13

CUMULATIVE TONE FOLLOWER OUTPUT
TONE FOLLOWER OUTPUT

12

6

11

7

10

8

9

AMP OUT
SIGNAL IN (-)

Figure 2 - Recommended External Components - Differential Input Mode

RFEEDBACK

R,N ,_)
R,N ,+)

RBIAS
1.01lF ±20%
1.01lF ±20%
C ,N ,_)

C ,N,+)
3.579545MHz

Differential Input

External Components
1. The values of the Input Amp gain components
illustrated are calculated using the Input Gain
Calculation Graph (Figure 4).
When calculating input gain components, for
correct operation, it is recommended that the
values of resistors R1 and R4 do not go below

100kQ.
2. Refer to following pages for advice on IC
Protection from high and spurious line voltages.
Common Mode Input

INPUT AMP

Tip (a)

--I

Ring (b)

--I~''''''~~H+

I

INPUT AMP

+
MX631

MX631

Figure 3 - Example Input Configurations
MX-COM, INC.

Page 485

..
~

~

-I>.

>

Application Information ......

~

r--------------------------------------------------------------------------------------,i~

~

~

a

-10

.......
.......
.......

(J)

I........

I"

G5
z -15

»

r

j

<

m
r

....

.....

" ....... " I"-. I....... ........
....

t-

-

I"":

c:: -25
t-

o

..... 1_1- ,_

MUST-NOT-DECODE

c.
OJ

.....

..... -r
LEVEL
I-..

I- t- f-

o·
j
~

" ~ r-..: '"I"":

(J)

~

-3o

I.......

""

I-..
"- "MUST-DECODE LEVEL

o

........

I"

hi-20

5j

1

.......

........
~

........

'"I"": ........
'".~

-30

~

'"

~

.......

" I........

" I" l"- '" ....... I"
........

'"

'"

0l-35
3

<

3
en

I"

........

"

"

........
........

........
........

.......

........

-40

........
.......

'" ........ I........ " I........

"

-45

MIMIMUM

AMPLIFIER

GAIN

MAXIMUM

AMPLIFIER

T1

.......

""
I........

"

I

-15

~

8
_s:
~

........

I"'..

-10

-5

0
AMPLIFIER

5
GAIN (dB)

10

VDD

Figure 4 - Input Gain Calculation Graph

........
........

I

-20

I"":

" I........ I........

GAIN

-50
-25

I .......

= 3.3

15

(±0.1) VOLTS

"'" ........
20

TEMP

= -40'

"

to +85' C

25

s:

)(

en
w
....10

MX631

Application Information ..... .
Input Gain Calculation

Input Gain Components

The input amplifier, with its external circuitry, is
provided on-chip to set the sensitivity of the MX631 to
conform to the user's national level specification with
regard to 'Must' and 'Must-Not' decode signal levels.
With reference to Figure 4, the following steps will
assist in the determination of the required gain!
attenuation.

The following paragraphs refer to the gain
components shown in Figures 2 and 3.
The user should calculate and select external
components (R 1 , R/C 3 , R/C., R.) to provide an amplifier
gain within the limits obtained in Steps 2 and 3.
Component tolerances should not move the gainfigure outside these limits.
It is recommended that the designed gain is near the
center of the calculated range. The graph in Figure 4 is
for calculations for the input gain components for an
MX631 using a VDD of 3.3 (±O.1) volts.

Step 1
Draw two horizontal lines from the V-axis (Signal
Levels (dS}). The upper line represents your
required 'Must' decode level. The lower line
represents your required 'Must-Not' decode level.
Step 2
Mark the intersection of the upper horizontal line
and the upper sloping line; drop a vertical line from
this point to the X-axis (Amplifier Gain (dS».
The point where the vertical line meets the X-axis
indicates the MINIMUM Input Amp gain required for
reliable decoding of valid signals.

Use this area to keep a permanent record
of your calculated gains and components

Step 3
Mark the intersection of the lower horizontal line
and the lower sloping line; drop a vertical line from
this pOint to the X-axis.
The point where the vertical line meets the X-axis
indicates the MAXIMUM allowable Input Amp gain.
Input signals at or below the 'Must-Not' decode
level will not be detected as long as the amplifier gain
is no higher than this level.

Implementation Notes
Aliasing
Due to the switched-capacitor filters employed in the
MX631 , be careful to avoid the effects of alias distortion
with the external components you choose.

Possible Alias Frequencies:
12kHz Mode= 52kHz
16kHz Mode= 69kHz
If these alias frequencies are liable to cause problems
and/or interference, it is recommended that anti-alias
capacitors are used across input resistors Rl and R•.
Values of anti-alias capacitors should be chosen to
provide a highpass cutoff frequency, in conjunction with
Rl (R4) of approximately 20kHz to 25kHz (12kHz system)
or 25kHz to 30kHz (16kHz system).
i.e. C
1
2x1txfoxRl

Signal Input Protection
Telephone systems may have high d.c. and a.c.
voltages present on the line. If the MX631 is part of host
equipment that has its own signal input protection
circuitry, there will be no need for further protection as
long as the voltage on any pin is limited to within VDD +
O.3V and Vss -O.3V.
If the host system does not have input protection, or
there are signals present outside the device's specified
limits, the MX631 will require protection diodes at its
signal inputs (+ and -). The breakdown voltage of
capacitors and the peak inverse voltage of the diodes
must be sufficient to withstand the sum of the d.c.
voltages plus all expected signal peaks.

When anti-alias capacitors are used, make allowance for
reduced gain at the SPM frequency (12kHz or 16kHz).
MX-COM, INC.

Page 487

I

MX631
Specifications
Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating limits is not implied.
Supply voltage
Input voltage at any pin
(ref Vss = OV)
Sink/source current (supply pins)
(other pins)
Total device dissipation
@ TAMB 25°C
Derating
Operating Temperature
Storage temperature range

I

-0.3 to 7.0V
-0.3 to (V DD +0.3V)
±30mA
±20mA
800mW Max.
10mW/oC
-40°C to +85°C
-40°C to +85°C

Supply Voltage (V DD) at 25°C
Supply Current
Input Logic "1"
Input Logic "0"
Output Logic "1"
Output Logic
Xtal/Cloc
"High"
"Low" External C
Input Amp
D.C. Gain
Bandwidth (-3dB open loop)
Input Impedance
Logic Impedances
Input (System)
(Clock In)
Output
Overall Performance
12kHz Detect Bandwidth
12kHz Not-Detect Frequencies (below 12kHz)
12kHz Not-Detect Frequencies (above 12kHz)
16kHz Detect Bandwidth
16kHz Not-Detect Frequencies (below 16kHz)
16kHz Not-Detect Frequencies (above 12kHz) 1
Sensitivity
2
Tone Operation Characteristics
Signal-to-Noise Requirements (Amp Input) 3,4,5,6
Signal-to-Voice Requirements (Amp Input) 3,4,5,7
Signal-to-Voice Requirements (Amp Output) 5,6
Tone Follower Output
Response and De-Response Times
1,8
Packet Mode Output
Response and De-Response Times
1,8
Page 488

All device characteristics are measured under the
following conditions unless otherwise specified:
V DD = 3.3V
T AMB = +25 °C
Audio Level OdB ref: = 775mVrms
Noise Bandwidth

=50kHz

Xtal/Clock or 'Clock In' Frequency

= 3.579545MHz

12kHz or 16kHz System Setting

5.5
1.0

3.0
2.3

1.0
2.9
0.4
3.589368

3.558918
0.1
0.1
60.0

dB
Hz
MQ
3.8

MQ
MQ
kQ

15.5

kHz
kHz
kHz
kHz
kHz
kHz
mVp-p

-29.0

dB
dB
dB

10.0

ms

48.0

ms

11.820
12.480
15.760
16.640
7.8
22.0
-36.0
-25.0

40.0

V
mA
V
V
V
V
MHz
Ils
Ils

,~

16.240
15.360
10.0
20.0
-40.0

MX-COM, INC.

MX631
Characteristics Notes
1.
2.
3.
4.
5.
6.

7.
8.

With adherence to Signal-to-Voice and Signal-to Noise specifications.
With Input Amp gain setting: 15.5dBM,i19.5dBMAx'
Common Mode SPM and balanced voice signal.
Immune to false responses.
Immune to false de-responses
With SPM and voice signal amplitudes balanced; To avoid false de-responses due to saturation, the
peak-to-peak voice+noise level at the output of the Input Amp (12116kHz Filter Input) should be no
greater than the dynamic range of the device.
Maximum voice frequencies = 3.4kHz
Response, De-Response and Power-up Response Timing.

Application Information ..... .
12.00kHz

F, - 4%

Fe - 1.5%

Fa

Fa + 1.5%

16.00kHz

Fo + 4%

Figure 5 - Wi/lIWiI/-Not Decode Frequencies

System Timing
SIGNAL INPUT

TONE

NOTONE

TONE FOLLOWER OUTPUT

RESPONSE

CUMULATIVE TONE FOLLOWER OUTPUT

DELAY

I

SIGNAL INPUT ......

TONE FOLLOWER OUTPUT ......
DERESPON8E

DELAY

PACKET MODE OUTPUT ......

Figure 6 - Examples of Input and Output Relationships
MX-COM, INC.

Page 489

MX·~M,IN~.

MX641

Advance Information

DUAL SUBSCRIBER PRIVATE METERING (SPM) DETECTOR

Features
• MX·COM MiXed Signal CMOS

• "Output Enable" Multiplexing Facility

• Two (12kHz/16kHz) SPM Detectors on a
Single Chip

• Call-Charge Applications on PABX Line
Cards

• Detects 12 or 16kHz SPM Frequencies
• "Controlled" (J,lC) & "Fixed" Signal
Sensitivity Modes
• Selectable Tone Follower or Packet
Mode Outputs
• High Speech-Band Rejection Properties

MX641DW
24-pin sOle

MX641P
24-pin PDIP

Description

I

preset period.
The MX641 low-power, system-selectable Dual
(3) High-impedance output -for device multiplexing.
Subscriber Private Metering (SPM) Detector has two
For non-I1Processor systems a preset sensitivity/
detectors on a single chip to indicate the presence, on a system input allows external channel level and system
telephone line, of either 12kHz or 16kHz telephone call- setting.
The MX641 is available in 24-pin plastic DIP and
charge frequencies. It is is designed for PBX and PABX
line-card and remote telephone installations.
small outline (SOIC) packages. It requires a supply of
Under I1Processor control via a common serial 4.5mA at 5 volts.
interface, each channel of the , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
MX641 will detect call-charge
1CLOCK IN
pulses from a telephone line and
XTAUC=LOC==-K--~,~
.r::::::l i
provide a digital output for
XTAL
~
recording, billing or security
purposes.
A common set of external
components and a stable
3.579545MHz Xtal/clock input
ensures thatthe MX641 adheres
accurately to most national
"Must and Must-Not" decode
SYSTEM
band-edges and threshold
OUTPUT
SELECT
levels.
The digital output is pinselectable to one ofthree modes:
(1) Tone Follower mode -a
logic level for the period of a
correct decode.
(2) Packet mode -respond/
TONE FOLLOWER
Ch2AMP OUT
MODE
de-respond after a cumulative
Figure 1 - Functional Block Diagram
period of tone or notone in a
12kHz/16kHz

Page 490

MX-COM, INC.

MX641

1

XtaVClock: The input to the on-chip clock oscillator; for use with a 3.579545MHz Xtal in conjunction
with the Xtal output; circuit components are on-chip. When using a Xtal input, the Clock Out pin should
be connected directly to the Clock In pin. If a clock pulse input is used at the Clock In pin, this (Xtall
Clock) pin must be connected directly to V 00 (see Figure 2). See Figure 4 for details of clock frequency
distribution.

2

Xtal: The output of the on-chip clock oscillator inverter.

3

Clock Out: The buffered output of the on-chip-clock oscillator inverter. If a Xtal input is used, this
output should be connected directly to the Clock In pin. This output can support up to 3 additional
MX641 ICs. See Figure 4 for details of clock frequency distribution.

4

Clock!ri: rh~3.579~~ pulse input to the internal clock dividers. If an externally generated
clockcpulse
is u~th&)~t?I/CIOCk input pin should be connected to V00'

iIlPlA
':·:;:i,
~r~.

5

'

..

~' ;-~~,;

",

,::.;~;

.~,

0

.~> ~

,

FO/~~P oUtput~i~~i!'lj);icontrols

Output Enable:
the state of both Ch1 and Ch2 outputs.
When this input is placed high (logijc~fj'fjoth,@l~;are setto a high impedance. When placed low
(logic 'O') both outputs are enabled.
' ,.. " , ; ;
,- "'
';~::~::~ ~.;5~2~ <:

6

.. "- ;" ~.' ,

..
).' ;'"~'i0·~·~ ,
The digital output of the Channel 2sPri:~~dtQt~;l~~(j,;~~tIhe format of the

Ch 2 Output:
signal at this pin, in common with Ch 1, is selectable to either'f'T:Ofre ~wer' 6~iPa .
"c' ' : ' : : . . J~f;':'
Output Select input.
"":"'~~l~~~:

de via the

.• :;~';'•.;;-." . .,. ,-

."~~~:;.~:;i~~,

7

Ch 1 Output: The digital output of the Channel 1 SPM detector when enabled. Thi!tlM.I!flt of the
signal at this pin, in common with Ch 2, is selectable to either 'Tone Follower' or 'Packet"fuode via the
Output Select input.

8

V B1AS : The output of the on-chip analog bias circuitry. Held internally at VoJ2, this pin should be
decoupled to Vss (see Figure 2).

9

Ch 1 Amp Out: The output of the Channel 1 Input Amplifier. See Figures 2 and 3.

10

Ch 1 Amp In (-): The negative input to the Channel 1 Input Amplifier. See Figures 2 and 3.

11

Ch 1 Amp In (+): The positive input to the Channel 1 Input Amplifier. See Figures 2 and 3.

12

Vss: Negative supply rail (GND).

MX-COM, INC.

Page 491

I

MX641

13

No internal connection; leave open circuit.

14

Ch 2 Amp In (+): The positive input to the Channel 2 Input Amplifier. See Figures 2 and 3.

15

Ch 2 Amp In (-): The negative input to the Channel 2 Input Amplifier. See Figures 2 and 3.

16

Ch 2 Amp Out: The output of the Channel 2 Input Amplier. See Figures 2 and 3.

17

Output Select: A logic input to set the Channel 1 and Channel 2 output modes. When high (logic '1'),
the outputs
in the Tone Follower mode; when low (logic '0'), the outputs are in the Packet mode.

18

The external components govern the input sensitivity; the
Inor"tl;nn When low (logic '0'), both channels are in the
selection are via the Chip SelecVSerial
on chip (Fixed Sensitivity Mode).

I

19

Chip Select: The Chip Select input for
Sensitivity mode (see Figure 9). The device is
MX641 is in the Fixed Sensitivity mode this input

20

Serial Clock: The Serial Clock input for use in data loading when
Sensitivity mode (see Figure 9). Data is loaded to the MX641 on this clock's
MX641 is in the Fixed Sensitivity mode this input should be connected to either V55

21

Serial Data: The Serial Data input for use in data loading when using the MX641 in the Controlled
Sensitivity mode (see Figure 9 and Table 2). When the device is in the Fixed Sensitivity mode this
input should be connected to either V55 or VDD.

22

System Select: In the Fixed Sensitivity mode this pin selects the system frequency.
High (logic '1') = 12kHz; Low (logic '0') = 16kHz. In the Controlled Sensitivity mode this pin is inactive
and may be left unconnected. This pin has an internal pullup resistor on Chip.

23

No internal connection; leave open circuit.

24

V DO: Positive supply rail; a Single, stable power supply is required. Critical levels and voltages within
the MX641 are dependant upon this supply. This pin should be decoupled to V55 by a capacitor
mounted close to the pin.

Page 492

MX-COM, INC.

MX641

Application Information

!XTAUCLOCK

XTAUC~

,--------------------.

If you use a Clock Pulse input:
- Remove Xtal (X,)
- Connect Pin 1 to Voo
- Do not short Pins 3 & 4
- Input clock pulses to CLOCK IN
See Figure 4
-----~

CLOCK IN

~

-

24

10

X'~2

23

I:

XTAL

SYSTEM SELECT

Ch1 OUTPUT

.-------------~

7

, -_______________V~B~IA=S_____i

8

Ch1 AMP OUT-AAA
Ch1 AMP IN

~III

R2

II

Component

R,
R2
R3
R.
Rs
R.
R7
R.

(-)1"
R,

Ch1 AMP IN (+)

SERIAL DATA

20
19

MX641DW

SERIAL CLOCK
CHIP SELECT
PRESET LEVEL

18
OUTPUT SELECT

17

9

16

10

15

Ra

J

-A R~ Ch2 AMP OUT

vVl Ch~
R.

14

11
,------ 12
Vss

Value

Tolerance

68kn
68kn
820kn
820kn
68kn
68kn
820kn
820kn

± 1%
±1%
±1%
±1%
± 1%
± 1%
±1%
±1%

--

21

Ch2 OUTPUT

.----------16

VDD

22

3
4
O""'UT"'P"'U-";T""'E"-NA-;;OB"'~~"'E 5
CLOCKOUT
IN

~I

r
C'=:E

r~~D~D~____________~

AMP IN (-)

Rs

Ch2 AMP IN (+)

13 -

C,
C2
C3
C.
Cs
C.

1.0j.JF
1.0j.JF
270pF
270pF
270pF
270pF

X,

3.579545MHz

I~
I·I~

1.C.

±20%
±20%
±5%
±5%
±5%
±5%

Figure 2 - Recommended External Components

Fixed Sensitivity Setting
Note that when calculating/selecting gain components, R3 , R4 , R7 and Rs should always be greater than or equal
to 100kO.
Differential Input

INPUT AMP

INPUT AMP
Tip (a)

Ring (b)

I

Common Mode Input

-I
-I

--I
MX641 (part)

.I
Figure 3 - Example Input Configurations
MX-COM, INC.

Page 493

MX641
Application Information ..... .

J.lController

110 Ports
Ch 2

Ch 1

Maximum number of driven clocks (including Master) = 4
Maximum capacitive load on Clock Out output = 15.0pF

Figure 4 - Examples of XtaVClock Distribution and Output Multiplexing

Xtal/Clock Distribution

Channel Outputs

The MX641 requires a 3.579545MHz Xtal or clock
pulse input. With the exception of the Xtal, all oscillator
components are incorporated on chip. IfaXtal input is
employed the Clock Out pin should be directly linked to
the Clock In pin.
To reduce component and layout complexity, the
clock requirements of up to 3 additional MX641
microcircuits may be supplied from a Xtal-driven MX641
acting as the system master clock. With reference to
Figure 4, the clock should be distributed as illustrated
and the Xtal/Clock pins of the driven microcircuits should
be connected directly to V DO. Note that the maximum load
on the master Clock Out pin should not be exceeded.

Channels 1 and 2 outputs operate together under the
control of the Output Enable and Output Select inputs.
Table 3 describes the operations.
The Front Page description describes the output
formats.

SIGNAL INPUT

TONE

NoroNE

TONE FOLLOWER OUTPUT

I

I

1lJ1,-------,

CUMULATIVE TONE FOLLOWER OUTPUT

RESPONSE
DELAY

SIGNAL INPUT ..... .

TONE FOLLOWER OUTPUT ..... .
DERESPONSE

DELAY

PACKET MODE OUTPUT ..... .

Figure 5 - Tone Follower and Packet Mode Outputs
Page 494

MX-COM, INC.

MX641
Sensitivity Setting
To enable the MX641 to operate correctly to most national 12kHz and 16kHz SPM specifications, the input
sensitivity can be accurately adjusted and set.
There are two different pin-selectable modes of sensitivity setting available to the MX641: Controlled Sensitivity
Mode and Fixed Sensitivity Mode
The Controlled Sensitivity mode allows the sensitivity setting from a IlControlier via a 6-bit serial data input. This
same serial input also sets operation (bit 0) to either 12kHz or 16kHz systems. Both channels are set identically.
The Fixed Sensitivity mode allows the sensitivity of each channel to be set to a fixed "gain" by external components
at the input amplifiers. Operation to either 12kHz or 16kHz is by the System Select input.

Controlled Sensitivity Setting
12kHz System
Bit Do '1'
Minimum
Nominal Maximum
Sensitivity Sensitivity Sensitivity
dB(ref.)
dB(ref.)
dB(ref.)

=

Serial Data
Bits

05

-

01

00000
00001
00010
0001 1
00100
00101
001 10
001 1 1
01000
01 001
01 010
01 01 1
01 100
01 1 01
01 1 1 0
o1 1 1 1
10000
10001
1 0010
1 001 1
10100
1 01 0 1
1 01 1 0
10 111
1 1000
1 1 001
1 1 01 0
1 10 1 1
1 1 1 00
1110 1
1 11 10
11111

Bandpass
Filter Gain
(dB)
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
19.0
20.0
21.0
22.0
23.0
24.0
25.0
26.0
27.0
28.0
29.0
30.0
31.0

-16.2
-17.2
-18.2
-19.2
-20.2
-21.2
-22.2
-23.2
-24.2
-25.2
-26.2
-27.2
-28.2
-29.2
-30.2
-31.2
-32.2
-33.2
-34.2
-35.2
-36.2
-37.2
-38.2
-39.2
-40.2
-41.2
-42.2
-43.2
-44.2
-45.2
-46.2
-47.2

-17.5
-18.5
-19.5
-20.5
-21.5
-22.5
-23.5
-24.5
-25.5
-26.5
-27.5
-28.5
-29.5
-30.5
-31.5
-32.5
-33.5
-34.5
-35.5
-36.5
-37.5
-38.5
-39.5
-40.5
-41.5
-42.5
-43.5
-44.5
-45.5
-46.5
-47.5
-48.5

-18.8
-19.8
-20.8
-21.8
-22.8
-23.8
-24.8
-25.8
-26.8
-27.8
-28.8
-29.8
-30.8
-31.8
-32.8
-33.8
-34.8
-35.8
-36.8
-37.8
-38.8
-39.8
-40.8
-41.8
-42.8
-43.8
-44.8
-45.8
-46.8
-47.8
-48.8
-49.8

16kHz System
elt Do '0'
Minimum Nominal Maximum
Sensitivity ··Sensltlvity Sensitivity
dB(ref.)
dB(ref.)
dB(ref.}

=

-16.9
-17.9
-18.9
-19.9
-20.9
-21.9
-22.9
-23.9
-24.9
-25.9
-26.9
-27.9
-28.9
-29.9
-SO.9
-31.9
-32.9

-18.2
-19.2
~20.2

-21.2
-22.2
-23.2
-24.2
-25.2
-26.2
-27.2
-28.2
-29.2
-30.2
~31.2

-32.2
·:00.2
. ~34.2
--35.2
·.,36.2
.. -37.2
--38.2
-39.2
40.2
-41.2
. :,4~.2

-33.9
-34.9
-35.9
-36.9
-37.9
-38.9
-39.9
-40.9
41.9
42.9
-43.9
-44.9
-45.9
-46.9
-47.9

.. =43.2
..

:~~~
;~;2

#7.2

'~ij~:
ci;AA;~:;

-19.5
-20.5
-21.5
-22.5
-23.5
-24.5
-25.5
-26.5
-27.5
-28.5
-29.5
-SO.5
-31.5
-32.5
-33.5
-34.5
-35:5
-36.5
-37.5
-38.5
-39.5
40.5
-41.5
-42.5
-43.5
-44.5
-45.5
-46.5
-47.5
-48.5
-495'':
c'
.. ... \;
-50.5:
"

Table 2 - Controlled Sensitivity Setting Information
Notes:

1. The recommended amplifier components (see Figure 2) are used, providing an amplifier gain at
16kHz of 20.5dB ±0.3dB or at 12kHz of 19.8dB ±0.3dB.
2. A comparator sensitivity of 2.3dB(ref.) ±1dB (the variation is due to filter gain error, filter output
offset, comparator input offset or a combination of all 3).
3. The applied Voo is 5.0 volts; OdB (ref.) = 775mVrms.

MX-COM, INC.

Page 495

I

MX641
Controlled Sensitivity Setting ..... .
With the external gain (sensitivity) components used as shown in Figure 2, the gain of the input stages is 19.8dB
(12kHz) or 20.5dB (16kHz). For controlled sensitivity setting the gain of each bandpass filter, and therefore the device
sensitivity, is adjusted by the applied serial bits 0 1 to 0 5 •
In the Controlled Sensitivity mode the system frequency is selected by bit 0 0 (,1' = 12kHz; '0' = 16kHz). Data is
loaded Bit 5 (0 5) first. Table 2 details the serial data inputs forthe required sensitivity. Minimum, Nominal and Maximum
Sensitivity figures are provided to make complete allowance for internal circuit offsets and component tolerances.
OdB(ref.) = 775mVrms at V DO = 5.0 volts; varies directly with V DO. Examples are provided as a guide to meeting different
national specifications.

German FTZ Specification

16kHz

The FTZ system has a Must Decode level of
-21dB (ref.) and a Must-Not Decode level of
-27dB (ref.). Reference to Table 2 shows that
Bandpass Filter Gain settings of 5dB, 6dB or 7dB will
enable an MX641 channel to meet this level
specification. Figure 6 illustrates the range of these
various settings.
To meet the German FTZ specification, the input
data (0 5 to Do) can be:

o0 1 0 1

0

5.0dB

MUST DECODE - - - - - - - - - ·17.36dB(ref.)

4.0dB
WILL·NOT DECODE

MUST·NOT DECODE - - - - - - - - ·23.8dB(ref.)

Figure 7 - French Specification -Possible Settings

System
Select
X
X
0
1
0
1
X

Preset
Level

Output
Select

Output
Enable

0
0
1
1
1
1
X

0
1
0
0
1
1
X

0
0
0
0
0
0
1

Table 3 Operating Mode Configurations
Page 496

5.0dB

7.0dB
WILL·NOT DECODE

or
00 110 0
6.0dS
or
001 1 1 0
7.0dB
Selecting the middle setting would give the greatest
noise immunity.

I

MUST DECODE - - - - - - - - - - -21dB(ref.)

MUST-NOT DECODE - - - - - - - - -

Figure 6 - German Specification -Possible Settings

French Specification

12kHz

This system has a Must Decode level of
-17.36dB (ref.) and a Must-Not Decode level of
-23.8dB (ref.). Reference to Table 2 shows that
Bandpass Filter Gain settings of 2dB, 3dB or 4dB will
enable an MX641 channel to meet this level
specification. Fig 7 illustrates the range of these
various settings.
To meet the French SPM specification, the input
data (0 5 to Do) can be:
00010
2.0dB
or
00 0 1 1
1
3. OdS
or
00100 1
4.0dB
Selecting the middle setting would give the greatest
noise immunity.

Operating Mode
Packet Mode Output;
Tone Follower Output;
Packet Mode Output;
Packet Mode Output;
Tone Follower Output;
Tone Follower Output;
Tristate Output

Serial Data Control
Serial Data Control
Preset Sensitivity 16kHz
Preset Sensitivity 12kHz
Preset Sensitivity 16kHz
Preset Sensitivity 12kHz
HighZ

X = don't care
MX-COM, INC.

MX641

\ . i:::','(

'\

CHIP SELECT

tCSE

~

)i'

SERIAL CLOCK
~~'
. t D S " tDH •

---"'X

SERIAL DAT_A_ _

BIT Ds

,

"

~:~

~
Min.

Parameter
Serial Clock 'High' Pulse Width
Serial Clock 'Low' Pulse Width
Serial Clock Period
Chip Select 'Low' to Clock 'High' Edge
Data Hold Time
Data Setup Time

~

BIT D4

Typ.

o XI
BIT Do

Max.

Unit

ns
ns
ns
ns
ns
ns

250
250
600
450
50.0
250

Figure 8 - Data Load Timing for the Controlled Sensitivity Mode

-10

-15

§ -20

>

E

~ +
~:fS~
" -25

~

!!la

-30

I
-20

-15

-10

-5

o

5

10

15

20

25

AMPLIFIER GAIN (dB)
V DD = 5.0 (+/- 0.1) VOLTS; TEMP = _40°C to +85°C

Figure 9 - Input Gain Calculation Graph for use in the Fixed Sensitivity Mode

MX-COM, INC.

Page 497

I

MX641
Fixed Sensitivity Setting
In this mode the sensitivity of each channel is set by
the correct selection of the components around the
Channel Input Amplifier. Note that the device sensitivity
is directly proportional to the applied power supply (VDO).

Input Gain Calculation
The input amplifier, with external circuitry, is used to
set the sensitivity of the MX641 to conform to the user's
national level specification with regard to 'Must' and
'Must-Not' decode signal levels.
With reference to the graph in Figure 9, the following
steps will assist in the determination of the required gain/
attenuation.
Step 1
Draw two horizontal lines from the Y-axis (Signal
Level) in Figure 9. The upper line represents your
required 'Must' decode level. The lower line represents
your required 'Must-Not' decode level.
Step 2
Mark the intersection of the upper horizontal line and
the upper sloping line; drop a vertical line from this pOint
to the X-axis {Amplifier Gain (dB».
The point where the vertical line meets the X-axis
indicates the MINIMUM Input Amp gain required for
reliable decoding of valid signals.
Step 3
Mark the intersection of the lower horizontal line and
the lower sloping line; drop a vertical line from this point
to the X-axis.
The point where the vertical line meets the X-axis will
indicate the MAXIMUM allowable Input Amp gain.
Input signals at or below the 'Must-Not' decode level
will not be detected as long as the amplifier gain is no
higher than this level.
Select the Input Gain Components as described.

Protection Against High Voltages
Telephone systems may have high d.c. and a.c.
voltages present on the line. If the MX641 is part of a host
equipment that has its own signal input protection circuitry,
there will be no need for further protection as long as the
voltage on any pin is limited to within V DO +0.3V and V

~.~.

~

If the host system does not have input protection, or
there are signals present outside the device's specified
limits, the MX641 wi" require protection diodes at its
signal inputs (+ and -). The breakdown voltage of
capacitors and the peak inverse voltage of the diodes
must be sufficient to withstand the sum of the d.c.
voltages plus a" expected signal peaks.

Aliasing
Due to the sampling nature of switched-capacitor
filters used in the MX641 , high frequency noise or
unwanted signals can alias into the passband, disrupting
detection. External components must be chosen carefully
to avoid alias effects.

Possible Alias Frequencies:
12kHz Mode
52kHz
16kHz Mode = 69kHz
If other filtering in the system has not attenuated
these alias frequencies, capacitors should be employed
across resistors R3 , R4 , R7 and Rs to provide anti-alias
filtering.
The lowpass cutoff frequency should be chosen to
be approximately 20kHz to 25kHz for a 12kHz system, or
25kHz to 30kHz for a 16kHz system.
i.e. C

2 x

1t X

fo

X

R3

When anti-alias capacitors are used, there will be
reduced gain at the SPM frequency (12kHz or 16kHz).

Input Gain Components
Refer to the gain components shown in Figure 2.
The user should calculate and select external components
(R/R/C 3 , RjR/C4 and R/R/Cs ' R/R/C s) to provide
amplifier gains within the limits obtained in Steps 2 and
3.
Component tolerances should not move the gainfigure outside these limits. The graph in Figure 9 is for the
calculation of input gain components for an MX641 using
a V DO of 5.0 (±0.1) volts.
It is recommended that the deSigned gain is near the
center of the calculated range.

Page 498

MX-COM, INC.

MX641
Specifications

~~~~~~:R~t~ii:?~~;~;:::
Exceeding the maximum rating can result in device
damage. Operation of the device outside the operating limits is not implied.
-0.3 to 7.0V
Supply voltage
Input voltage at any pin
(ref V ss = OV)
-0.3 to (V DD + 0.3V)
Sink/source current (supply pins) ±30mA
(other pins)
±20mA
Total device dissipation
800mW Max.
@ TAMB 25°C
10mW/oC
Derating
-40°C to +85°C
Operating Temperature
-40°C to +85°C
Storage temperature range

Supply Voltage (V DD)
Supply Current
Xtal/Clock/Clock In Frequency
Input/Output Parameters
Clock Out Load
Logie Inputs
Input Logic '1'
(-High)
'(l:ow)
Input Logic '0'
13
Input Lea~~~U~jimt (VIK "".0 toV DD )
14
Input Cutrent(VtK=;O) , , '
Channel Output!l,:~,§lf'
'.,
Output Logic '1' (loH)\ii:I:t29p,A}.(Enabted),.
Output Logic '0' (loL) = 36Op.AY'(Enabf.~.t ••
Output Leakage Current (High-Z Output>::':'
Input Amplifier
D. C. Gain
Bandwidth (-3d B)
Input Impedance
Overall Performance
12kHz Upper Decode Band Edge
3
12kHz Lower Decode Band Edge
3
16kHz Upper Decode Band Edge
3
16kHz Lower Decode Band Edge
3
Level Sensitivity
Controlled Sensitivity Mode
3,4,12,15
Preset Sensitivity Mode
3,4,5,16
Signal Quality Requirements
Signal-to-Noise (Amp Input)
4,8,9,10
Signal-to-Voice (Amp Input)
4,8,9,11
Signal-to-Voice (Amp Output)
4,8,10,11
Channel Outputs (Chl and Ch2) Figure 5
Mode Change Time
6
Tone Follower Mode (Table 3)
Response and De-Response Time
3,4,7
Packet Mode (Table 3)
Response and De-Response Time
3,4,7
o

All device characteristics are measured under the
following conditions unless otherwise specified:
VDD = 5.0V
TAMS = +25 °C
Audio Level OdB ref: = 775mVrms
Noise Bandwidth = 50kHz
Xtal/Clock or 'Clock In' Frequency = 3.579545MHz

12kHz or 16kHz System Setting

4.5
4.5
3.558918

MX-COM, INC.

0

,:".'.

V
mA
MHz

15.0

pF

1.5
5.0

V
V
IlA
IlA

3.5

o

0

5.5
6.0
3.589368

-5.0
-15.0

'.'

4.6
0.4
5.0

,~5.0

60.(j
~,

1.0

dB
Hz
MQ

109
'":

12.18
11.82
16.24
15.76

kHz
kHz
kHz
kHz

3.3
-24.7

2.3
-25.7

22.0
-36.0
-25.0

20.0
-40.0

40.0

V
V
flA

1.3
-26.7

dB (ref.)
dB(ref.)

-29.0

dB
dB
dB

500

ns

10.0

ms

48.0

ms
Page 499

I

MX641
Specification Notes
1.
Tone Follower or Packet mode enabled; see Table 3.
2.
Tristate selected; see Table 3.
3.
With adherence to Signal-to-Voice and Signal-to Noise specifications.
4.
12kHz and/or 16kHz system.
5.
With Input Amp gain setting = OdB.
6.
Time taken to change between any two of the operational modes: Tone Follower, Packet or Tristate,
and with a maximum capacitive load of 30pF on an output.
7.
The time delay, after a valid serial data load (or after device powerup), before the condition of the
outputs can be guaranteed correct.
8.
Immunity to false responses and/or de-responses.
9.
Common Mode SPM and balanced voice input signal.
10.
With SPM and voice signal amplitudes balanced; To avoid false de-responses due to saturation, the
peak-to-peak voice + noise level at the output of the Input Amp should be no greater than the dynamic
range of the device.
11.
Maximum voice frequencies = 3.4kHz.
12.
With the Input Amplifier gain at OdB and the Bandpass Filter gain set at OdB (Table 2); subtract 1.0dB
from this specification for each extra single dB of Bandpass Filter gain programmed.
Alternatively, with the input components as recommended in Figure 2, the sensitivity is as defined in
Table 2.
13.
Logic inputs with no internal pullup; Chip Select, Serial Data, Serial Clock, Output Enable, Output
Select and Clock In pins.
14.
Logic inputs with an internal pullup; Preset Level and System Select pins.
15.
Preset Level= '0', System Select = don't care; Chip Select, Serial Clock and Serial Data inputs active;
see Table 3.
16.
Preset Level = '1', System Select = input active; Chip Select, Serial Clock and Serial Data inputs
inactive; see Table 3.

I

Page 500

MX-COM, INC.

Technical Specifications

Section 9:
Signal Processing
The following section contains specifications on
MX·COM's devices used for signal processing.

Device

Description

Page

MX102

Autocorrelator

p. 503

MX105

Tone Detector

p. 509

I
MX-COM, INC.

Page 501

I
Page 502

MX-COM, INC.

MX·~M,IN~.

MX102

AUTOCORRELATING SIGNAL PROCESSOR

FEATURES

APPLICATIONS

• Low Signal Level Input of 20mVrms
• Wide Signal Frequency Range from 2Hz to 12kHz
• On-Chip Gain Amplifier
• On-Chip Xtal Oscillator
• Low Supply Voltage Operation of 2.5 V
• Low Current Drain
• SMT Package

• Medical Instruments
• Sonar Detection
• Remote Signaling
• Pagers
• Mobile Radio

BENEFITS
• Improved Signal Sensitivity
• No Timing Required
• Digital Output Signal
• Serves 2-Cell Applications

MX102DW
16-pinSOIC

MX102J
16-pinCDIP

VDD

ACOR
OUT

I
vss
CLK+6

Figure 1 - Block Diagram
MX-COM, INC.

Page 503

MX102

Description
The MX102 low power CMOS Autocorrelator extracts periodic signals from random noise environments. The
amplitude of non-periodic components is substantially reduced. Its patented autocorrelator compares the incoming signal
to itself. The more elements of the waveform that are seen as periodic, the higher the energy at the output at 4 times the
input frequency.
The MX1 02 cascades two autocorrelators, each one improving the signal to noise ratio. The signal between these
two autocorrelators is centered at twice the incoming frequency, and the output signal is centered at four times the
incoming signal, as shown in Figure 2. With random noise applied the output will swing rail-to-rail at random (peak-limited).
The output signal delay is fixed by the chip clock frequency and the length of the internal register.
The MX1 02 contains an input operational amplifier. The frequency response is shown in Figure 6. The low end
3dB frequency response can be adjusted to 2.0 Hz using an 0.68 ~F input capacitor.

5dBV

········:·········1······...:··· .. ·...: .... ·.. ··:· ...... ··: ........ ·:· ........ :......... :........

10dB
IDIV

............ ·····1·· .. ·.. · :......... :......... :......... :......... :......... :......... :...... ..
.

I

:

:

:

:

:

:

:

lue
I

-75

OHz

1kHz

5kHz

Frequency

Figure 2a - Input Signal-to-Noise = dB

11dBV1-----------------~--~--~--~--~~--~--~

........ :, ........ :...... , .. :..... , .. ':. "'~"

:'(:".~~ ~.'" ~;::

....... ': ..... '" ..... , .... :..... , ..

10dB
IDIV

I

.
.
.... ................................................
,

-69

OHz
Figure 2b - Output Signal
Page 504

Frequency

4kHz

5kHz

Note: All measurements made with 47.7 kHz bandwidth.

MX-COM, INC.

MX102

Input Frequency Range
The MX102 has a wide input frequency range, but care must be taken to choose the xtal frequency appropriate
for your application. The inputfrequency range is from 1/1200 to 1/190 ofthe xtal frequency. Th is results in the following
design equation:
fin max x 190 S; f xtol S; fin min x 1200
Once yourxtal frequency is chosen, it can be compared against Figure 3 to find the valid range of supply voltages.
The constraint on supply voltage is only important at the extremes of the frequency input range.
For example, if your maximum input frequency is 12kHz,
f xtol ~ 2.28MHz
and
V DD ~ 4 @ f xtol = 2.28MHz
If your minimum input frequency is 2Hz,
f Xtal S; 2400Hz
and
V DD S; 4.5 @ f Xtal =2400Hz

10M
Max.

--

1M

N

:I:

>
z 100k

0

w
:::)

"a::wu..

10k

~

Min.

0

0

..J

0

1k

100+------------1------------~------------~----------_1

2

3

4

5

6

SUPPLY (VOLTS)

Figure 3 - Clock Frequency vs Supply Voltage

MX-COM, INC.

Note: this graph is intended as a guideline;
the limits are not production-tested.

Page 505

I

MX102

PIN FUNCTIONS
Pin Function
AMP IN: Inverting input to analog amplifier/comparitor. This pin is normally 'AC' coupled to the incoming

1

signal with a feedback resistor to its output.
3

AMP OUT: Output of analog amplifier/comparitor. This pin does not have the drive capacity for any off chip
signaling. Feedback resistance should be greater than 200 kQ.

4

V DD: Positive Supply

5

BUFClK: Buffered inverter oscillator digital output. May be used as test point to align clock frequency or
to drive other circuitry.

6

ClK OUT: Output of oscillator inverter.

8

ClK IN: Input to oscillator inverter.

9

Vss: Negative Supply
"

11

ClK + 6: A digital output signal derived by dividing the clock input frequency by 6.

13

ACOR: Autocorrelator digital output signal. Frequency is at four times the input frequency.

16

V DD : Positive Supply

VDD
AMP IN

N/C
SIGNAL
C1
INPUY

R1

AMP OUT

VDD

VDD
BUFClK
ClK OUT

I

R2

N/C
ClK IN

16
2

15

3

14

4

MX102DW

VDD

13

5

12

6

11

7

10

8

9

AUTOCORRELATED
SIGNAL OUT

-C1: 0.01 uF
C2: 47 pF
C3: 47 pF

R1: 2.2 MQ
R2: 1 MQ

Figure 4 - External Components
Page 506

MX-COM, INC.

MX102

TIMING

Analog
Input

Autocorrelate - - 1 - - - - - - - - - - - '
Output

!.-_6.0ms-- 1
typo ~
Figure 5 - Timing Diagram

AMPLIFIER FREQUENCY RESPONSE

Input Amplifier
Feedback Resistor = 2.2 megohm

24
/"'"'

f..-'""I-

V

-

-

Io...~
1\

\
8

o

\
1\

1

10

1-

Input Cap

100
1000
Frequency (Hz)

= 0.68

uf -+- Input Cap

10000

= 0.01

100000

uf

Figure 6 - Input Amplifier Frequency Response
MX-COM, INC.

Page 507

I

I

MX102

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

OPERATING LIMITS

Exceeding the maximum rating can result in device damage. Operation ofthe device outside the operating limits is
not suggested.

All devices are measured under the following conditions
unless otherwise noted.

Supply Voltage

-0.3 to 7.0 volts

Input Voltage at any pin

-0.3to (Vdd+0.3 volts)

V DD

5.0 volts

TAMB

25°C
560 kHz

20mA

Xtal/Clock

Maximum Device Dissipation

100 milliwatts

Input Test Signal

1 kHz at 200 mV rms

Operating Temperature

-30°C to +85°C

External Connections

see Figure 1

Storage Temperature

-40°C to + 125°C

Sink/Source Current (Total)

Supply Voltage
Supply Current

2.5
2

Logic '1' Level
Logic '0' Level
Digital Output Impedance
Analog Amplifier DC voltage gain

Dynamic Values
Signal Input
Analog Amplifier Gain

Minimum Input Waveform Duty Cycle
Freq Out/Frequency In Ratio
Maximum Clock Frequency
Frequency Input Range
Input to Output Delay
Capture Range

5.0
1.0
4.0

5.5
2.0

V

4.0
1.0

20
20
9.0
10.0

100

1000

35

7
8
9
10

V

kQ
dB

4.0
50

3
4
5
6

V
mA
mA

mVrms
dB
dB
dB

%
4

4
2.5
500

3000
5.9

1A
3

MHz
Hz
ms
ms
dB

NOTES
1. Maximum Clock frequency varies with supply voltage.
2. Operating current at 2.24 MHz clock.
3. Signal input required to provide constant autocorrelated output.
4. Measured at 6000 kHz.
5. Measured at 2.5 vdc input.
6. Measured with 12 kHz input signal.
7. The frequency input range is 1/190 to 1/1200 of the xtal clock frequency (see "Frequency Input Range"
section).
8. Time from pulsed input signal to correlation output.
9. Time from pulsed input signal to correlation output with 2.24 MHz clock.
10. Two tone input, level difference

Page 508

MX-COM, INC.

MX·~M,IN~.

MX105

TONE DETECTOR
FEATURES:
•
•
•
•
•
•

Operates in High Noise Conditions
""'4OdB Signal Input Range
Simultaneous Tone Detection
Adjustable Bandwidth
Hermetically Sealed Ceramic Package
Wide Frequency Range

APPLICATIONS:
• Tone Decoding in Single and Multitone Signaling
Systems
• Decoding of Sequential or Simultaneous Tone
Signaling Systems

MX105J (CDIP)
MX105P (PDIP)
16 pins

DESCRIPTION
The MX105 is a monolithic PMOS tone operated switch, designed for tone decoding in
single and multitone signaling systems.
The device employs decoding techniques which allow tones to be recognized in the
presence of high noise levels or strong adjacent channel tones.
Tone channel center frequency and channel bandwidth can each be adjusted independently. The circuit has a high noise immunity against harmonic and sub-harmonic
responses and is able to maintain a constant bandwidth and high noise immunity over a
wide range of input signal levels.

I
FIG. 1: MX105 INTERNAL BLOCK DIAGRAM
MX-COM, INC.

Page 509

FIG. 2: V.C.O. SAMPLING WAVEFORMS

I
,:",'

I

I

C2A------------~_

"'··1

t

\,'

"

1<

',"

,......,....."...--.--- S1

I
I

J >"

I

I

I

i'

1

"'-::

82

DEVICE OPERATION

I

Input signals are A.C,eoupied to the buffer input,
which is internally biased at 50% of supply voltage. The
signal appears at the output of the buffer as an A.C.
voltage superimposed on the D.C. bias level. The signal
is then coupled via RV and RW to the voltage controlled
oscillator and word sampling switches, which sequentially connect C2 and C3 into circuit to form four sample
and hold RC integrators.
With no input" signal, each capacitor charges to the
D.C. bias level and differential voltages are zero. When
an input signal is applied, each capacitor receives an
additional charge. This charge is determined by the integrated average of the signal waveform during the interval the capacitor is switched into circuit.
Figure 2 shows the operating sequence of the V.C.O.
sampling switches and their phase relationship to a
locked-on inband signal. As can be seen, C2A and C2B
should not receive any additional charge, since they always sample the input as it crosses the D.C. bias level.
Should the signal not be locked to the V.C.O., then a
positive or negative charge voltage will appear on C2A

Page 510

or C2B. This voltage, when differentially amplified, is
applied to the V.C.O. as an error correcting signal to
enable V.C.O. "lock."
Figure 3 shows the operating sequence of the 'Word'
sampling switches and their relationship to a locked-on
inband signal. As can be seen, the charge being applied
to C3A should always be positive and the charge applied to C3B should always be negative (with respect to
the common bias level).
These capaCitor potentials are differentially amplified
and applied to a D.C. comparator, which switches at a
pre-determined threshold voltage. The comparator
output is a logic signal used to control a counter. This
counter switches the MX105 output ON when the
comparator output is maintained in the 'Word Present'
state for a minimum number of consecutive signal
samples. The activated output switch reduces the
comparator threshold by 50%, introducing threshold
hysteresis. Output chatter with marginal input signal
amplitudes is minimized.

MX-COM, INC.

FIG. 3: WORD SAMPLING WAVEFORMS

6

S3
C3A---~

C3B

,1.-_______- - '

'------S4

METHOD FOR CALCULATING
EXTERNAL COMPONENT VALUES
The externafcOmponents shown in Figure 4 are used
to adjust the various performance parameters of the
MX1 05. The signal to noise performance, turn on delay
and signal bandwidth are all interrelated factors which
should be optimized to meet the requirements of the
application.
By selecting component values in accordance with
the following graphs, nominally optimum circuit
performance is obtained for any given application.
FIG. 4: EXTERNAL COMPONENT CONNECTIONS

w.

S< GNIIL
IN PUT

lOW

~r-I

1__
130pf [

c'.-';::

RW

.-.RV

··Cl......

..
••

en ••

"

2

~Dl

..
..

C2~L

e2B ••

MX-COM, INC.

,

.,

14

13
12
11

7

IO

,

...

VR-'

"'

..

ClB

II

MXI05

6

•

"
CIA

~

I

"'
R:'"

The user should first define the following application
parameters:
A. The center frequency to be detected (f'o).
B. The MX105 Minimum Usable Bandwidth
(MUBW). This is obtained by taking into account
the worst case tolerances on the input tone frequency and variations in the MX105 f'o due to
supply voltage (0.07%1%) and ambienttemperature (0.02%1"C) changes.
C. The maximum permissible MX105 response
time.
D. The minimum input signal amplitude.
Using this information, the appropriate component
values can be calculated, and the signal to noise
performance can be read from a chart.
Using graphs 1-10, the following example is used to
demonstrate the calculation of component values for
any given application.
A. MX105 centre band frequency (f'o) = 2800Hz .
B. MX105 bandwidth = 6%.
C. MX105 maximum response time = 50ms.
D. Minimum input signal amplitude = 200mVrms.

I
Page 511

I

I

GRAPH 1

470pf

5000

Graph shov1n..,-~--""I

T'lock :::: lOmS

300K

-

ISmS

+---+---'''''"'1----11---_+--'=.., T' lock : :

30mS

1000 +-.--+---I-~:---1--_+---''''''IT'lock

1K

400K
SOOK
600K
700K
1M

500

2,

..

--,..-_--'T'lock :::: lOOmS

2M

6,

BANDWIDTH %

Page 512

500

8'

10

10,
BW ,

MX-COM, INC.

GRApH 5

GRAPH 4
Graph show~ng RW required for T'word for a g~ven signal input
assuming C3A "" C3B = 0.11-1F.
Formulae T'word '" RwC3A x K(given
~n Graph 5 )
1M

~

"
"
.5;

:#

;;

700

~

~

600

"

!

2.8

/

If

7

,,<

II

~ 500

~
400

300

200

100

~

/

2.4

2.0

V
I
V
I II
I I V
II V

~

0

SIGNAL INPUT AMPLITUDE.

3.2

g

..;
800

,/

if

~

900

GRAPH SHOWING K FACTOR VS

..,"

,,~

1.6

1.2

~?

.8

.4

~

y

II/V
1//

~

~y

\

\

I~ t---

.2

.4

.8

1.2

1.4

SIGNAL INPUT (VOLTS R.M.S.)
16

12

20

28

24

T'WORD IN ms

GRAPH 6
GRAPH SHOWING VALUE OF R2 (KD.)
TO YIELD SELECTED BANDWIDTH (%)

GRAPH 7
·26

MIN.

TYP.

MAX.

·24 ~------T-------t-----~----~7f------- M • 1

100
90
80
70

-22

60
50

II

20

:E

'"
0

=
:;!
'"
0

'"

:0

/

10

9

·20 +------+-------t-~L-__j--7"o..-_t----_::;7j M • 0.33

/

-18

II

1
II

L

30

;;;

I

/

40

·16 +------+---~--t7L---__j~~--_t-------

-14

II II

H·

0.1

·12 +------f--f~~~----__j------_i~O"---_i

-10

8
7

I

-8 +--~~+-r-----t---~L-r------t-------i

/

"",.

/

/

V /

II /
VV VV

'0

/

V

/

-6

V

-2

/

10
NO. OF BANDWIDTHS SEPARATION

/ / 1/

10

11

12

BW %

MX-COM, INC.

Page 513

Graph number 4 shows that for a signal amplitude of
200m Volts, a resistor value RW of 51 Ok ohms with a 0.1
microfarad capacitor for C3A and C3B will yield a 'Word'
time of 20ms. This in turn yields a response time of 9ms
+ 20ms = 29ms.
Graph 6 shows the range of values for R2 to yield a
given bandwidth. The exact bandwidth given by any
value of R2 will vary with differing production batches.
Therefore, in applications where an exact bandwidth is
required, R2 should be a variable resistor which is
adjusted on test.

GRAPH 8

so

.0

5
.

!.
!il
l!i

• Worst-case signal to noise calculations depend on
calculation of an "M" value using the following
formula:
M

fo x Bw
100

x

)0

~

~

0:

20

.'"
u

il

(Rw'C3A)

\

10

\

• substituting our example values:

..

M

..
..

x

2800 x 6
100

M

168 x 0.051

M

8.57

(0.51 mO x O.l .... F)

~
.1

:J"":' '

.2

Graphs9~10 s~Ow the approximate,tinJe the
MX1Q~WItl,@k(rto:turri off afteranltiit>andlligrial has

By substituting the value for M of 8.57 in graph
number 7, the signal to noise ratio of an adjacent tone
can be found. This then has to be decreased depe~hg ,
upon the tone amplitude. The figure to decrp~;$NRobyF
is calculated from graph 8.
.}. ',: . . . . <
-,'o~~~~
,u

,~ " "

,,~~r:et:nove'(l The turn-off tIl'rieis. ~ClJlated with a
~iqQaAfN914 orsi."ilar)betW9jiln pins 5 and 6, as
:llhown in Fig\.l$ 4:,TtiEl~eCt of this diode is to greatly
reduce~~r6~fftirtie'with signal input amplitudes
,gr.ter ~ri'36O'm\t R.M.S.
:~~;}:: '~>:>"

" .':, ;,' '

":;~~H','~~~

Graph .~boW~nQ T"~f

tu..'

GRAPH 10

for iii given

Sj.gnal _~U~~e C$~ .. O.luF and Diode
:: be~e:ef1 C3A " C38.
wC3A:

3.2

900

1.&

800

..

Graph showlng 'I(' factor for T'off vs SiQnal
S.
I nput Am p
1 l' tude ( VO It 5 RM)

700

..

600

j

/

0

II'

I

SOO

~
~

.2

I

400

300

.1

/

i/

200

100

50

100

150

200

T'off 1D ms

Page 514

250

100

350

2
K FACTOR

MX-COM, INC.

•

•

CIB

• CIA

eM

•

RI

•

0 l

VR
C'in
• e Rv
e
eL
e Rw
·H

0

TR

•
• C2B

•

•

eE

R2

• •

•

C2A

•

•

•

MX10si
• C3B

•

C3A

e

e
e
e

e

R3

e

e

R4

e

H

EDGE CONNECTIONS.
+ve
A
E = -ve

L
M

•

Signal Input
Switch Output
Buffer Output

To assist engineers in designing systems utilizing the
MX10S, MX-COM has produced a printed circuit board
with the necessary external component outlines (see
Fig. S), that demonstrates a full working system. Please
note there is no provision on the P.C.B. for capacitor C4
or diode D1 and it is recommended that these
components are added for improved system operation.
Due to the MX10S's ability to decode tones in the
presence of adjacent channel tones or noise, the device
is ideally suited to applications where a number of tones
are sequentially or simultaneously transmitted over a
common link. In the example shown in Figure 6, a
number of single tone transmitters (MX20S) are transmitting over a common link such as cable, radio, optical,
etc., to a number of receivers (MX1 OS). The transmitters
may transmit either individually or simultaneously to the
MX10Ss without the possibility of missing a call or
receiving a false call.

FIG. 6: SIMULTANEOUS TONE DECODING USING MX105 AND MX205

.VI:

O.lllf

I

10.

TUM?f1~O 1200 H. r-i~"""'+-+-,
O.lwf

MX-COM, INC.

Page 515

MX105 ELECTRICAL SPECIFICATION

MAX. RATINGS Failure to observe may result in device damage.
MAX. VOLTAGE BETWEEN ANY PIN AND +VE SUPPLY (pin 16) .......................................... -20Vand +0.3V
OPERATING TEMPERATURE RANGE ......................................................................................... -30°C to +85°C
STORAGE TEMPERATURE RANGE .......................................................................................... -55°C to + 125°C
DEVICE DISSIPATION (at 20°C ambient temperature) ................................................................................. 400mW
MAX. OUTPUT SWITCH LOAD CURRENT ..................................................................................................... 10mA

CHARACTERISTICS
Note: Due to A.C. signal coupling either supply polarity may be 'ground.'

SYMBOL

PARAMETER

NOTES

MIN.

TYP.

MAX.

UNITS

Vs
Is

Supply voltage
Supply current
Signal input

Ope~'ing range
Total, excluding loads
Signal + noise range

10

12
5

15

Volts
rnA
Volts
R.M.S.
kHz

Fo
Bw

Z;n

Channel
Frequency
Bandwidth
OIP switch
load current
Input impedance
Frequency
Stability.
Frequency .

IiSTAMB
Per 1% ch~~in supply volts

0.055

61

0,04

5

20/"

10%,
10
.·200
0.02%rC

rnA
kohm

0.07%

StabilitY
NOTE
1. For input voltages greater than VDD x 0.143, pins 1 and 2 should be open circuit and the signal applied via C'in to the
junction of RV and RW.

I
Page 516

MX-COM, INC.

Appendix

Section 10:
Appendix
Contents
Standards and References ............................................................................ p. 519
Applications
DBS800 C-BUS System Development ....................................................... p. 523
Pvt SQUELCH: Combining CTCSS with Voice Band Inversion ................. p. 534

Generation of Non-Standard CTCSS Tones .............................................. p. 538
Variable Split Band Scrambling ................................................................... p. 543
Switched Capacitor Interfacing ................................................................... p. 549
Audio Delay Circuit Based on the MX609 ................................................... p. 558
MX-COM Crystal Oscillators ....................................................................... p. 560
Wireless Data Modems: Getting the Best Performance ........................, .... p. 562
An RS-232 Asynchronous Modem using the MX439 ................................. p. 567
Error Detection & Correction of MPT1327 Formatted Messages ............... p. 571
MX·COM GMSK IC Modems ...................................................................... p. 579
Glossary ......................................................................................................... p. 585
Packaging and Handling ................................................................................ p. 591
Product Replacement Guide .......................................................................... P. 617
List of Xtals Compatible with MX-COM ICs ................................................... p. 619
Index .............................................................................................................. P. 621

NOTE: Application Notes are available for DCS, LTR, CTCSS and N-Tone Signaling
applications using our DBS800 IC set. Call us at 1-800-638-5577 for more information.

MX-COM, INC.

I
Page 517

I
Page 518

MX-COM, INC.

Appendix

STANDARDS & REFERENCES
Related Mobile Communications Industry Standards
CDPD (Cellular Digital Packet Data) Specification:
CDPD Industry Input Coordinator
650 Town Center Dr., Suite 820, Costa Mesa, CA 92626
Phone: 714-545-9400, ext. 235
Fax: 714-545-8600

MOBITEX protocol:
RAM Mobile Data
10 Woodbridge Center Drive, Woodbridge, NJ 07095
Phone: 908-602-5543
Fax: 908-750-0209

RCR STD-17, -18, -21, -29 & -30:
Research and Development Center for Radio Systems (RCR)
5-16 Toranomon 1, Minato-Ku, Tokyo 105, Japan
Phone: 813-3592-1101
Fax: 813-3592-1103

RD-LAP protocol:
ARDIS
300 Knightsbridge Parkway, Lincolnshire, IL 60069
Phone: (708) 913-1215

Mobile Communications Industry Standards Organizations
MX·COM is an early implementor of standards-based technology. As active participants in today's standards
committees, we will continue to give you early access to standard-based ICs.
The Telecommunications Industry Association (TIA) publishes bulletins, recommendations and standards applicable
to telecommunications equipment. The following subcommittees address mobile communications equipment:

1. TR-8 Land Mobile Services
Land Mobile radio products and systems including voice and data applications. TR-8 is responsible
for all technical matters of industry concern and the promulgation of standards including definition
of terms, methods of measurement and equipment specifications.

2. TR-32 Personal Communications Equipment
Standards for wireless consumer communications devices such as cordless telephones, citizen
band radio, and the like.

3. TR-45 Cellular and Common Carrier Mobile Radio System Standards
Performance, compatibility, inter-operability, and service standards for all cellular and common
carrier systems. These standards apply to service definition, wireless telephone equipment, wireless
base station equipment, wireless telephone switching office eqUipment, ancillary apparatus, intersystem operation and interfaces. The TR-45 Committee shall coordinate, for the purposes of
consistency, with other TR committees, and with other national standards bodies and appropriate
organizations as their work requires.

MX-COM, INC.

Page 519

I
,

Other agencies that publish relevant standards are the European Telecommunications Standards Institute (ETSI), the
Consultive Committee of the International Telephone and Telegraph (CCITT), the Electronics Industries Association
(EIA), and the Institute of Electrical and Electronics Engineers (IEEE). Addresses of these organizations are provided
below.

TIA

Telecommunications Industry Association
2001 Pennsylvania Avenue, NW
Suite 800
Washington, DC 2006-1813
USA
Phone: (202) 457-5430
Fax: (202) 457-4939

ETSI

European Telecommunications Standards Institute
06921 Sophia Antipolis Cedex
FRANCE
Phone: 33 92 94 42 00
Fax: 33 93 65 47 16

ITU-T

(Formerly CCITT and CCIR)
International Telecommunications Union
Place Des Nations
CH-1211 Geneva
Switzerland
Phone: (011) 4122 730 5851

EIA

Electronic Industries Association
1722 Eye Street, NW
Suite 440
Washington, DC 20006
USA
Phone (Headquarters): (202) 457-4936
Phone (Standards): (202) 457-4966

IEEE

Institute of Electrical and Electronics Engineers
Headquarters:
345 East 47th Street
New York, NY 10017
USA
Phone: (212) 705-7900
Standards Office:
IEEE Service Center
PO Box 1331
Piscataway, NJ 00855
USA
Phone: (201) 981-0060

I
Page 520

MX-COM, INC.

PRODUCT LISTING REFERENCES
MX·COM product information is available from a variety of sources, including electronic listing services. Some of the
sources for information are listed below:

CAPS (Computer Aided Product Selection) -- CD-ROM
Cahners Technical Information Service
275 Washington St.
Newton, MA 02158-1630
USA
Phone: 617-558-4960
Fax: 617-630-2168
CAPS Support Hotline: 408-257-0552

IC MASTER
Hearst Business Publishing, UTP Division
645 Stewart Ave.
Garden City, NY 11530
Phone: 516-227-1300
Fax: 516-227-1901

INFORMATION HANDLING SERVICES -- CD-ROM
Technical Information Data Service
15 Inverness Way East
PO Box 1154
Englewood, CO 80150
USA
Phone: 800-525-7052 or 303-790-0600

I
MX-COM, INC.

Page 521

I
Page 522

MX-COM, INC.

Applications

~~

~;~:~I
@

Digitally-integrated Baseband Subsystem
System Overview Including C-BUS Applications
and
DBS 800 Development Kit

This application note contains an introduction to the D8S800 devices and their
potential applications in Mobile Radio equipment, a description of MX-COM's
'C-8US,' and information about design & development support. Data bulletins
on individual devices can be found in the Technical Specifications section of this
catalog.

I

(~~)

MX-COM, INC.

Page 523

Digitally-integrated Baseband Sub-system (DBS800)
System Overview
MXB02 • MXB03A • MXB05A • MXB06A • MXB09
This family of audio processing and signaling devices is designed for use in two-way mobile or trunked
radio. While supporting all internationally mandated or system-specific requirements for processing and
signaling, DBS 800 also includes many high-level functions which offer a flexible, low-cost route to the
"Added Value" opportunities in the LMR market.
DBS 800 was created with the mobile radio hardware and software development engineer in mind. AlllC's
were designed as peripherals to the radio's host microprocessor. They require a minimum amount of
control software. A single address and data hardware bus (C-BUS) is used on alllC's for easy connections
to the host microprocessor and minimum track layout.
To support the product's functions there is a development kit including all DBS 800 integrated circuits, a
support microprocessor and software. It allows evaluation, demonstration and software development to
be completed in a fraction of the time normally required (see pages 532-533).

Complete audio processing (CEPT, EIA, etc.)

ANI (Automatic Number Identification)

Universal Signaling:

Half-duplex repeater

SelCall (CCIR, ZVEII, II, III, EEA, etc.)
CTCSS (EIA, EEA)
DPL TM, Digital Coded Squelch (DCS)
Digital Selcall, 1200 Baud MSK (MPT 1317/1327)
DTMFencode
L TRTM, NRZ Data
2-Tone,SpecmITones

Hardware Development Kit
Software Support:
Evaluation - Demonstration - Development
Electronic digital trimming and volume control

Data Communications with data storage and
buffering

Adaptive compensation for non-linear and
temperature effects

Voice/Data Scrambling

Two-Point Modulation for trunked/scanning
schemes

Voice Management
Voice storage, Mailbox, delay, busy buffer, a/arms
and status -- Reduced airtime usage -- Increased
spectrum efficiency -- VOXlHandsfree operation

System Management

I

Common Control and Data Bus ("C-BUS")

Over-air programming/re-configuration and cloning -Ca/I billing/monitoring/blocking -- TX time-out!
selective lockout -- Repeater access/control -- Direct
control of all system radio units

Fully automated test/alignment/servicing
Self-test mode
Single hardware design approach
Software reconfigurable
Full integration reduces PCB area
Greatly reduced development time
Multi-level powerdown modes

DPLTM is the registered trademark of Motorola, Inc. LTRTM is the registered trademark of E.F. Johnson Co.
Page 524

MX-COM, INC.

Benefits
• DBS 800 is compatible with most Selcall schemes such as DTMF, 5/6-Tone, 2-Tone and MSK. It is also
compatible with Sub-Audio CTCSS, DCS and LTRTM.
• Allows advanced signaling: Digital Selcall, ANI, overair re-configuration, cloning, channel dependent
signaling.
• A single design concept can be used for all models of mobile radio with different features or market
destinations. Software is reconfigurable.
• One microprocessor is required to control all radio functions. DBS 800 devices contain additional
hardware to minimize software overhead.
• Digitally controlled trimmers allow for "adaptive adjustment" of non-linear VCO conversion gain and
temperature effects. This allows use of cheaper, lower-tolerance components.
• Non-predictive decoding of signaling devices gives total design flexibility.
• Smaller, lighter equipment design possible, e.g. handhelds.
• Non-predictive decoding offers features such as recognition and identification of own repeater CTCSS
tone, multiple group call, etc.
• Voice management features voice security, voice mailbox, voice status, voice alarm, and voice buffering
when a channel busy condition exists.
• For data communications, there is the ability to connect directly to mobile radio with no external
interface, laptop PC's, printers, etc. RS232 interface or others are possible. Data storage and security
are software dependent.
• Inventory is simplified by using the standard DBS 800 chip set.
• Radios can be calibrated and tested when completely assembled by using a single external audio/datal
RF connection.
• Self test modes with audible/visual alert outputs.

I

• Simple field test unit can be used to test or reconfigure radios incorporating DBS 800.

MX-COM, INC.

Page 525

08S 800 System Introduction
EXTERNAL DAT.

Transmitter

.~

~

Radio ~
Controls ~

+---+

REF.

.~

rD~ ~ r

::v

~,

14.032MHZ XTAL
lJ(

Receiver

r

1
DEMOD

r

MX80SA
MX802
RECEIVE
DATNVOICE
AND
I:UDID~ STORE AND
TRANSMIT
RETRIEVE
AUDIO
CODEC
PROCESSOR

A.

RADIO
MICROCONTROLLER

JI

DRAM

~

XTAL

t

~

ROM

1

"C-BUS' SERIAL DATA SYSTEM

1 ·,r~

~~

~~

,Ir

,ir

MX803A

MX805A

MX809

AUDIO
SIGNALING
PROCESSOR

SUB-AUDIO
SIGNALING
PROCESSOR

MSK
MODEM

I

iI

XTAL

XTAL

T

TONE AUDIO SIGNALS AND CUE

1200 BPS MSK SIGNALS
lJ(

L

SUB-AUDIO SIGNALS

AX (AUDIO. MSK. TONE. SUB-AUDIO) SIGNALS

Figure 1 - DBS 800 Audio System

08S800
!he Digi~ally-Integrated Baseband Sub-system (DBS 800)
IS a family of low-power CMOS integrated circuits which
p!ovid,e a comprehensive range of audio processing and
signaling functions for use within two-way radio systems.
Each IC can be used as part ofthe complete DBS 800 audio
system, or as a "stand alone." The system and ICs are
partitioned in such a way that radio designers can easily
select the device(s) appropriate to their needs.
DBS800 ICs currently available are:

• MX802 DVSR Codec
This is a Continuously Variable Slope Delta Modulation
(CVSD) speech encoder and decoder with the ability to
store and retrieve voice and data within attached external
Dynamic Random Access Memory (DRAM) using an onchip DRAM controller.

I

• MX803A Audio Signaling Processor
This provides an in band tone signaling ability to LMR
Systems.
• MX805A Sub-Audio Signaling Processor
This provides a sub-audio and digital signaling (NRZ)
ability to LMR Systems.

Page 526

• MX806A LMR Audio Processor
This is a half-duplex audio processor providing all DBS 800
system audio signal conditioning and filtering capabilities
for the system transmit and receive paths.
• MX809 MSK Modem
This is an intelligent, half-duplex 1200 baud MSKIFFSK
Modem with a software programmable byte-synchronization system and checksum generation and checking.
Control of all DBS 800 ICs is by "C-BUS," a simple hardware
and software system for the two-way transmission of commands and data between a microcontroller and the ICs.
C-BUS may be used with any microcontroller and allows the
BUS data rate to be determined solely by the microcontroller,
Control may be achieved by either the radio's microcontroller
or a separate microcontroller dedicated to the purpose,
!hiS section. provi?es in,formation on DBS 800 IC analog
interconnections, Including recommendations on application-specific gain and mixing components. It also provides
C-BUS ha~dware and software information, including a
complete list of address allocations and software commands.

MX-COM, INC.

S stem Audio Interconnections

"""'==-++-ISC~
~lOOUTPUT
~
MODULATION 1
.>"0::,:_"'-_
_+-1SC2
.....

~LATION2

To TI8IlOI!1itter
Modulation
C~b

>""''''----++-1 .....
SC3

v...

MXBOZ DVSR CODEC

DRAM

-!SR2

UI

il
0

15
::I

C

I-

I

-

5

SR3

I

SR4

~

Z
:E

0

!u
VIllAS

MXB03A
AUDIO
SIGNALING
PROCESSOR

SRB

I

MXB09
MSKMODEM

JFigure 2 - System Audio Interconnections
MX-COM, INC.

Page 527

System Audio Interconnections
Figure 2 is an example of DBS 800 IC transmit and receive audio paths and interconnections. External components shown
are those recommended in the individual Data Bulletins. Components identified by an "S" are illustrated as system
components, which means that they are calculated to perform a specific function within the system. Table 1 shows
recommended system component values and notes on their calculation.
Notes - (refer to Figure 2)

System
Component

Recommended
Value

SC,
SC 2
SC3

See Notes

SR,

100ka

The feedback resistor of the MXB06A modulation summing amplifier. This
amplifier satisfies the input gain and matching requirements of the remaining
DBS BOO devices.

SR2

1.0MQ

Configured in conjunction with SR, to present a sub-audio signal content of
-20.0dB to the modulator.

SR3
SR.

100ka
100ka

Configured in conjunction with SR, to present an audio signal level of OdB to
the modulator.

SR5

100ka

The feedback resistor of the MX803A summing amplifier. This amplifier regulates the signal level output otTone Generators 1 and 2, which in turn are input
to the Transmit Audio BUS by switch 2 and SR •.

SR 6
SR?

62.0ka
122ka

Configured in conjunction with SR5 to produce a 3.0dB tone-differential
(twist) when the MXB03A is used as a DTMF decoder. For selcall applications
different output levels may be required, or the signal level from Tone Generator
1 may be attenuated by the MXB06A modulator drivers.

These modulation drive coupling component values should be chosen with
respect to the operational audio requirements and the radio's input
specifications.

Configured in conjunction with SR, to present an audio signal level of OdB to
the modulator.
Table 1 - Recommended System Component Values
SRa

100kQ

MX803A Sub-Audio Signaling Processor
The audio switch (SW1) is used in this example application
to allow interruption of the transmitter modulation path if it is
required to provide a Calibration tone from the tone generator to the loudspeaker.

I

XtaliClock Frequencies
All DBS BOO ICs will operate with Xtal/Clock frequencies
between 4.00 MHz and 4.10MHz. When considering a
common Xtal/Clock frequency for all DBS BOO ICs in a
system, it should be noted that:
a) A 4.032 MHz XtallClock input will produce an accurate
1200 bps rate in the MXB09 MSK Modem.
b) A 4.096 MHz XtallClock input will generate an accurate 16kbps and 32kbps sampling clock rate in the
MX802 DVSR Codec.
c) Driving all DBS 800 IC clock generators from a single
Xtallclock source prevents possible "beat-frequencies" and is therefore preferable.
DBS BOO IC audio frequency responses and internal sampling clock rates vary with respect to XtallClock frequency
(see Table 3).
Unused Pins
To improve screening and reduce noise levels around
DBS BOO ICs, it is recommended that any unused pins are
connected to VSS. This includes inputs to on-chip amplifiers and switches if not used within an application.
Page 528

MX806A LMR Audio Processor
This is the audio terminal of any DBS 800 "core" audio
installation. To demonstrate the versatility of the MXB06A
microphone input stage, Figure 2 shows the microphone
input components in a single-ended configuration, with Figure 2 in the MXB06A Data Bulletin showing a differential input
configuration. Relevant component values are the same for
both applications.
DBS 800 System Audio Level References
Table 2 gives a guide to the relevant signal levels used in the
DBS 800 system.
Signal Level
(dB)
-30.0
-20.0
-15.5
-9.6
-6.0
-3.5
-1.6

o

1.3
2.5
3.5
4.4

Amplitude
(mVrms)

TX Deviation
(%)

9.7
30.8
51.3
102

154
205
256
308
359
410
462
513

10
20
30

40
50
60
70
80

90
100

Table 2 - Audio Signal Levels
MX-COM, INC.

"C-BUS" Controllin

I

T

MX809
MSK MODEM

1

T

ADDRESS
SELECT

I

-

MX803A
AUDIO
SIGNALING

I

T

ADDRESS
SELECT

MX805A
SUB-AUDIO
SIGNALING

-

I

t "

l'COMMAND DATA

REPLY DATA

COMMAND DATA
TVDD

REPLY DATA
INTERRUPT REQUEST

III!

EXTERNAL DATA

MICROCONTROLLER

SERIAL CLOCK

CHIP SELECT 2

CHIP SELECT 1

~

~

CHIP SELECT
SERIAL CLOCK
COMMAND DATA

I

•I

AUDIO
MX806A
PROCESSOR

I

'" '" '" I

FUTURE
PERIPHERAL

I

MX802
DVSR
CODEC

l

I

Figure 3 - Example C-8US Hardware Interconnections
C-BUS Serial Interfacing
C-BUS is the controlling hardware and software interface for
all members of the DBS 800 family. It enables the serial, bidirectional transfer of commands and data throughout the
system, allowing total flexibility of operational control and
data handling. System upgrades can be achieved by a
simple software or firmware change.
C-BUS Hardware Interface
The BUS physically consists of 5 lines:
• Serial Clock line - driven by the microcontroller to all
peripherals. All C-BUS commands and data transfers
are synchronized, in bursts of 8 bits, to this clock.
• Command Data - to address, command, and transfer
data from the microcontroller to a selected peripheral.

• Reply Data line - transfer of requested (commanded)
data from the addressed peripheral as the result of a
specific Address/Command (AlC).
• Chip Select (CS) line - carries the CS timing command
from the microcontroller to all peripherals. All C-BUS
sequences are initiated, completed, or aborted by this CS
signal. (See Timing Diagrams in respective DBS 800
data bulletins.) All peripherals on the C-BUS will receive
the CS signal, but only the peripheral that is addressed
will react. Table 4 contains a list of all DBS 800 C-BUS
Address allocations.
• Interrupt Request (IRQ) line - interactive peripherals
have an Interrupt output (IRQ) for connection to the
microcontroller interrupt input.

Full-Duplex Configuration
Figure 4 shows the configuration of the Address Select
inputs when using 2 MX809 Modems on the C-BUS. MX805A
Sub-Audio Signaling Processors should be embodied in the
same manner when full-duplex operation is required.

Figure 4 - MXB09 Modems for Full-Duplex Operation
MX-COM, INC.

C-BUS Serial Clock Rate
Generally, C-BUS Serial Clock rates that are harmonically
related to the XtaVClock = 32 frequency cannot produce
alias effects within a microcircuit, therefore using a C-BUS
Serial Clock rate at this frequency is preferable. If is proves
impractical to select a synchronous C-BUS clock, coupling
between sensitive analog inputs (such as the MX806A Mic.
Inputs) and the C-BUS should be avoided.
Page 529

1
,

"C-BUS" Controlling System
The Use of C-BUS Software and Protocol

Each individual DBS 800 Data Bulletin contains a table
listing the C-BUS commands and instructions relevant to
that peripheral. Table 4 gives an abridged list of all DBS BOO
address allocations.
All transactions begin with the CS line going to a logic ·0"
level (Figure 5). The first byte that must be transmitted to the
peripheral, on the Command Data line, is an Address/
Command (AlC) byte. Generally, all bytes are transmitted
MSB first.
Address/Command (AlC) Byte

Part ofthis byte is the "Address" that specifies which IC (or
ICs) has been selected for that particular transaction. The
second part ofthe AlC is the "Command" to fulfill a particular
function (see Table 4).
The AlC may be followed by either
(a) a qualifying instruction, or
(b) data bytes from the microcontroller via the Command Data line or from the peripheral via the Reply
Data line.

Example C-BUS Transactions
Address/Command byte 61 is recognized as:

- and in this case would be followed by 1 byte of Status data
transmitted on the Reply Data line from the MXB02 to the
microcontroller.

- and in this case would be followed by 1 byte of Control data
transmitted on the Command Data line from the microcontroller to the MXB06A.

- and in this case will reset ALL DBS 800lCs connected to
the C-BUS. (IndividuallC Data Bulletins give details of the
General Reset actions.)

DBS 800 IC Sampling Rates

IC Functions
MX802DVSR Codec

Voice Filters
Voice Filters
Voice Sample Rates

at 16, 32 & 64 kbps
at 25 & 50 kbps
16.0kbps
25.0kbps
32.0kbps
(Nominal)
50.0kbps
64.0kbps
MX803A Audio Signaling Processor
Tone Filters
Max
Min.
Digital Filters
High
Mid.

Ext.

125
100
15.625
25.0
31.25
50.0
62.5

126
100.B
15.75
25.2
31.5
50.4
63.0

128
102.4
16.0
25.8
32.0
51.2
64.0

166
13.15
13.B
6.9
27.0

168
13. 2B
14.0
7.0
2B.0

170
13.47
14.2
7.1
2B.4

125
62.5
12.5
35.7
25.0
1.04

126
63.0
12.6
36.0
25.2
1.05

125

126

250
166
125

252
168
126

MX805A Sub-Audio Signaling Processor

Voice Filters
TX Filters

Max.
Min.

RX Filters

I

or
Digital Filters
MX806A LMR Audio Processor
Voice Filters
MX809 MSK Modem
TX Filters
or
RX Filters
Table 3 ofDBS BOO IC
Page 530

If the Xtal/Clock
frequency 4.096 MHz
is used with the
MXB05A, MXB06A, or
MXB09, it may result
in sampling clock
rates that place the
voice-filter passband
frequencies outside
CEPT specifications.

rates relative to XtallClock
MX-COM, INC.

"C-8US" Controlling Protocol
C-BUS Performance Testing
General (all device) Reset
Audio Processor
Control Command
Mode Command
Modulator Levels Set
Volume Set
Audio Signaling Processor
Write to Control Register
Read Status Register
Read RX Tone Frequency
Write to Notone Timer
Write to TX Tone Generator 1
Write to TX Tone Generator 2
Write to G/Purpose Timer
MSKModem1
Write to Control Register
Read Status Register
Read RX Data Buffer
Write to TX Data Buffer
Write to Sync Program
MSKModem2
Write to Control Register
Read Status Register
Read RX Data Buffer
Write to TX Data Buffer
Write to Sync Program
C-BUS Performance Testing

General Functions
Future Audio Processors
Future Speech Products
Future Audio Signaling Processors
Future MSK Modems
Future MSK Modems
Future DVSR Codecs

08 to OF
ABtoAF

00
01
MX806A
10
11
12
13
MX803A
30
31
32

33
34
35
36
MX809
40
41
42

43
44
MX809
48
49
4A
4B

4C
55

02 to 07
14t01F
20t02F
37 to 3F
45 to 47
4Dt04F
6A to 6F

50 to 54
BOtoBF

DVSRCodec
MX802
Write to Control Register
60
Read Status Register
61
Store uN" pages, Start page X (immediate)
62
Store UN" pages, Start page X (buffered)
63
Play "N" pages, Start page X (immediate)
64
Play "N" pages, Start page X (buffered)
65
Write Data,
Start page P
66
Read Data,
Start page P
67
Write Data,
Continue
68
Read Data,
Continue
69
Sub-Audio Signaling Processor 1
MX805A
Write to Control Register
70
71
Read Status Register
Read CTCSS RX Data
72
Write to CTCSS/NRZ TX
73
Read NRZ RX Data
74
Write to NRZ Data TX
75
Write to Gain Set
76
Sub-Audio Signaling Processor 2
MX805A
Write to Control Register
78
Read Status Register
79
Read CTCSS RX Data
7A
Write to CTCSSlNRZ TX
7B
Read NRZ RX Data
7C
Write to NRZ Data TX
70
7E
Write to Gain Set
C-BUS Performance Testing
AA
C-BUS Performance T
FF

Future Sub-Audio Signaling Processors
Future SUb-Audio Signaling Processors
Future Products
Future Products
Future Products
Future Products

56to5F
COtoCF

77
7F
80 to 8F
90t09F
DO to OF
EOtoEF

AOtoA9
FOto FE

Table 4 - C-BUS Address Allocations
General Reset
The General Reset command (01 H)' when transmitted from
the microcontroller, is non-selective and will reset all DBS 800
ICs connected to the C-BUS. Detailed information on the
way this command affects each DBS 800 device can be
found in individual Data Bulletins.
C-BUS Performance Testing
To enable the effect of C-BUS activity on audio noise levels
to be assessed, 4 addresses are allocated for C-BUS
performance testing:
MX-COM, INC.

00000000
01010101
10101010
11111111

-aIlO's
-bit reversals
-bit reversals
-aIl1's

These bytes, which do not produce any changes in current,
active DBS 800 settings and configurations, provide C-BUS
activity. These AlC bytes, when following a CS edge, are
ignored by the DBS BOO chip set and can be loaded as
Command Data individually, or in common or mixed groups.
Page 531

I

08S800 Oevkit Introduction
OVERVIEW
The D8S800 Development System (Devkit) is a general purpose hardware and software platform for:
- The evaluation and functional testing of D8S800 devices (the MX802, MX803A, MX805A, MX806A & MX809).
- The demonstration and evaluation of D8S800 group functions.
- A base for use in developing application-specific software routines.
This document provides a generalintroduction to the Development System. Additional software and supporting documentation is available that demonstrates D8S800 application-specific functions, such as Voice Management, Data Communications, Sub-Audio Signaling and Selective Calling.

SYSTEM COMPONENTS
The complete D8S800 Development System consists ofthree printed circuit boards (PC8380, PC8280 & PC8180) with their
interconnecting cables, software on diskette and EPROM, and supporting documentation. Access to the system is through
a 'Host' PC.

Hom PC

~

II~

DBS 800 Development System
- Hardware Components -

1 1~l li l l l l l l l l l l~
RS232

Vsup~

PC8380
Controller

I UART 1132~81
I68HC111132K
x81
uC EPROM
IV. REG I IEEPROM I

C-BUS

PC8280
Signaling

D EJ

I Test connections I

C-BUS

A~aIO~
signa

PC8180
Speech & Data ProceSSing

oooEJ
I Test connections I

I

I

I
Radio

I

I
Page 532

MX-COM, INC.

HARDWARE
The PC8180 Speech and Data Board is used for the evaluation of the MXS02 DVSR Codec, MXS06A Audio Processor
and MXS09 MSK Modem devices. It is controlled by a C-8US link from the PCS3S0 controller board, and includes peripheral
components, test links and connectors to allow the devices to be tested individually or in several representative
combinations. For a detailed description ofthis board, see the document "PCS1S0 Speech and Data DevKit Documentation."
The PC8280 Signaling Board provides a similar hardware platform for evaluation ofthe MXS03 Audio Signaling Processor
and MXS05 Sub-Audio Signaling Processor and is fully described in "PCS2S0 Signaling DevKit Documentation."
The PC8380 Controller Board contains a 6SHCll microcontroller with RAM, EPROM, EEPROM, C-8US and RS232
ports, and is used to control the D8SS00 devices on the attached PCS1S0 and/or PCS2S0 boards. For D8SS00 device
evaluation, the PCS3S0 may run under the direct control of the 'Host' PC or it may run a special test program downloaded
from the 'Host' PC. "PCS3S0 Controller DevKit Documentation" gives a complete description of this board.
In some circumstances you may wish to use two sets of boards, for example to evaluate the end to end performance of a
link using the (half duplex) MXS09 MSK Modem devices. You could use a separate 'Host' PC to control each set of boards,
but the Development System also lets you connect two sets of PCS1S0/S2S0/S3S0 boards to a single PC.
The 'Host' PC can be any IBM compatible SO*SS or SO*S6 based computer running MS-DOS (or PC-DOS) V 2.0 or greater
with at least 512k bytes of RAM, a disk drive and an RS232 port (COM 1 or COM2) capable of running at 9600 baud. A color
graphics display, hard disk drive, and a second RS232 port are useful but not essential. Although the software will run on
a PCIXT, a faster machine will give a smoother response to the user's input.

SOFTWARE
The software components of the Development System are DLlNKS6 (the 'Host' PC control software), DLlNK11 (which
controls the 6SHC11 microcontroller on the PCS3S0 board), and various special D8SS00 device evaluation programs.
DLlNK11 is contained in an EPROM on the PCS3S0 board. Other software is supplied on a diskette.
The Evaluation diskette supplied with the 08SS00 Development System contains all of the programs needed to run the
system:

DLlNK86.EXE:
Various '.HEX' files:

the 'Host' PC software.
specific device test programs.

You will also receive a diskette for LTR evaluation (pIn 40450005.001) and one for DCS evaluation (pIn 40450006.001).
The diskettes also contain contain source files, of interest to a programmer but not needed to actually run the system. In
addition, there may be a READ.ME text file on the disk, giving details of any recent updates to the programs or their use.
The D8SS00 Development System software may be run from diskette or from a hard disk.

I
MS-DOS is a trademark of Microsoft Corporation. PC-DOS is a trademark of IBM Corporation.
LTR is a trademark of EF Johnson Co.

MX-COM, INC.

Page 533

Pvt SQUELCH: COMBINING CTCSS WITH VOICE BAND INVERSION
Reprinted with permission of Mobile Radio Technology, February 1988. Copyright 1988lntertec Publishing,
Overland Park, KS.

By Chris Hayes
Radio channels are in short supply, and putting two or
more plumbers, electrical contractors or other competing businesses on the same shared frequency can conserve spectrum. Radio syslem operators have been
reluctant to do so because customers dislike knowing
that competitors can overhear their communications.
Private squelch combines continuous tone-controlled
squelch system (CTCSS) with inverted speech to prevent users from understanding each others' communications unless the transmissions are accompanied by
the group's assigned tone. Such privacy is easy to
implement under CTCSS control, and it is available to
all, making it possible for competitors to share the same
radio frequency with a minimum risk of complaints.

CTCSS background
CTCSS equipment was first installed around 1956.
Those early "Private Line" or "PL" systems employed
tuning forks to generate and detect subaudible tones,
tones still commonly used throughout the two-way radiO
industry. Since 1956, vacuum tubes have been set aside
for transistors, and later, transistors combined by the
thousands into integrated circuits, but CTCSS still dominates as the simplest, most dependable way to segregate the voice traffic of diverse user groups sharing the
same radio channel.
Private squelch carries this process one step further.
Speech transmissions are made private through fixed
frequency inversion. Only the detection of the user
group's unique CTCSS tone assignment enables clear
recovery of inverted speech. As with any CTCSS
application, the subaudible tone unmutes the radio's
speaker; remove the tone and the speaker is silent.
Thus, before making a call, the caller must check the
channel's occupancy to avoid "stepping on" the conversation of others. This necessary monitoring process

MIC

I

f\

PTTC

MIDLAND
70-3368

~

allows eavesdropping. In fact, monitoring requires
eavesdropping. Private squelch conversations are audible, but those outside the group cannot understand
what is being said.

Voice band Inverter
Privacy is achieved with a monolithic voice band inverter. This CMOS IC includes switched capaCitor highpass and lOW-pass filters, a double-balanced mixer, a
fixed-inversion carrier and analog gates for
receive/transmit and private/clear switching. Filtering
and carrier frequency generation derive from an external1MHz clock of the same kind most CTCSS encoderdecoder ICs use.
To invert, speech first passes through the high-pass
filter and then mixes with the carrier in the doublebalanced mixer. The resultant sum and difference product is fed to the low-pass filter, which attenuates all
components except the lower sideband. The lower sideband modulates the RF carrier. The net effect is that lowfrequency speech components are translated to the
high end of the speech band, and frequencies in the
high end are translated to the low end. Because speech
is, in effect, frequency-coded in the human brain, this
translation procedure renders the code unfamiliar and,
therefore, unintelligible.
To recover clear speech, the process is reversed. In
the private squelch application, the user's assigned
CTCSS tone controls clear recovery. Secause modern
CTCSS encoder-decoders are programmable to 38
CTCSS tones, there are 38 privacy keys per radio
channel.
Private squelch should be equally compatible with
digitally coded squelch, such as the Digital Private Line
or the Logic Trunked Radio trunking system, because
they use signaling frequencies in the subaudible range.

MARCONI
2955

DEMOD
OUTPUT

AUDIO
SPECTRUM
ANALYZER

-

PRINTER

FIGURE 1. To record and produce private squelch spectrum diagrams, low-level white noise is fed to a two-way
radio mlc input. A radio communications test set demodulates the RF output and feeds it to an audio spectrum
analyzer. The analyzer drives a printer that draws the diagrams.
Page 534

MX-COM, INC.

·15d8V

"_800ltz DEVllTION @'100Hz bess ~NE
lIlA. .11 OrAl

~

JIJIIW'"

.... A'4J ~

...

...

,

-y-

r"

~

,
Figure 2. The private squelch voice band inverter's filtered but uninverted audio, transmitted by a typical radiO, is shown with a 71.9Hz CTCSS frequency. The tone's deviation
is set to the usual 500 Hz.

t""I

241Hz

~

... ~

=38dsJ.
." UIVALENT_

NOISE-PRODUCED
DEVIATION OF
ONLY =2kHz
10 AVOID LlMmNG

I""

CARRIER
DEVIATION 6.3Hz

=

~

;

j

.1

cress @ =500Hz DEVIATION

~

1"'"\
3,333Hz
_ CARRIER

IA

11

~

S~KTH.wyGH\

tI\

Figure 3. The private squelch voice band inverter's passband is shown inverted. Lowfrequency speech components appear to the right; high frequencies to the left. At the
far left is an undisturbed 241.8Hz CTCSS tone. At the far right, an undesired residual
3,333Hz carrier with a deviation level of only 6.3Hz at a level38dB down from the CTCSS
tone.
Pre-emphasis effects
Speech inversion scrambling introduces some special application problems. The power spectrum of
speech is not flat but exhibits a peak near 800Hz. Radio
transmitters require voice to be pre-emphasized before
modulation. Receivers then must de-emphasize the
recovered speech equally to compensate for the original
pre-emphasis. The ideal result achieves a flat power
spectrum for transmission.
MX-COM, INC.

But when speech is modulated with a carrier for inversion, the speech power spectrum shifts away from the
normal 800Hz center on which the radio transmitter's
pre-emphasis filter design is based. The recovered
voice sounds distorted and unnatural.
To overcome this problem, the voice band inverter is
treated as a radio. AudiO is pre-emphasized 6dB/octave
on its way in, and de7emphasized the same amount on
Page 535

I

its way out. This renders an inverted product with a
power spectrum the radio can process at its microphone
port the same way it processes natural speech. The
result sounds sufficiently natural, and few can distinguish the recovered audio from the original. Some,
perhaps with a trained ear and the knowledge of which
is which, report they can hear a single-sideband radio
quality in the recovered audio.
The coexistence of voice with a CTCSS tone makes
private squelch filtering requirements more demanding.
Low-level CTCSS tones become prominent if translated
to the high end of the voice band. The fact that few
systems adequately block speech from the sub-300Hz
region where CTCSS tones are assigned aggravates
the problem.
Most radio transmitters provide only the 6dB/octave
pre-emphasis filter the FCC rules mandate for the
300Hz to 3,000Hz voice band. A linear extrapolation of
this curve into the subaudio band yields an attenuation
of speech energy at 250Hz (the highest of the CTCSS
tones) of only 1.6dB with reference to 300Hz. No doubt
this is why many CTCSS systems do not offer tones
much above 200Hz. But even at 200Hz, voice is down
only 3.4dB from the bottom of the speech band, 100Hz
removed. At that level, speech tends to interfere with
CTCSS decoding or, just as bad, the tone is audible in
speech.
The voice band inverter offers a solution. Used simply
as a microphone filter, it attenuates frequencies below
300Hz by 36dB to 4OdB, providing effective use of all
CTCSS tones (even in the clear mode) and preventing
CTCSS tones from being heard in the voice band. This

not only separates CTCSS from voice, but it assumes
ready passage of the joint tone and voice product
through repeaters.
If DTMF signals are used, they should be injected at
the radio's tone port, bypassing the audio inversion
process.
It would be a mistake to offer private squelch as a
speech security system. Although simple fixed-inversion products traditionally are called "scramblers" and
their inversion carriers are considered a "secret," such
"codes" easily are broken with ordinary laboratory
equipment. Even so, units of comparable security have
sold for as much as $1,000.
Ask the typical radio users, "Do you have anything to
hide?" "No," they answer. Then ask, "What rights do
others have to your radio dispatches?" That answer is,
"None." That is because a taxi dispatch is not ordinarily
viewed as something to hide. Why would such users pay
an appreciable sum to buy a scrambler for which they do
not perceive a need?
Private squelch is not designed for the radio user with
something to hide; it is offered rather as an enhanced
form of CTCSS. It offers a simple, low-cost method for
achieving privacy of the two-way radio: just enough privacy, at an incidental cost, such that radiO users are
blocked from an opportunity to eavesdrop. The perception of two-way radio is chal1ged from that of an openchannel free-for-all to something substantially less
public.
The security of any single-band inversion system may
be breached easily by the dedicated eavesdropper with
a signal generator and some filter expertise. The anal-

•
·10
·20

I

-40

+:~===============;~/

I

...

3,333Hz CARRtER-

BREAKTHROUGH

\

t,PlCKUP

"'-~

_

It
1,GOOHz

......

I

,

TX MIC AUDIO RA1IGE

a.osaHz

Figure 4. The audio response characteristics of a
private squelch voice band inverter, before preemphasis or de-emphasis and before installation.

Page 536

2.1OCtH1 UOOHz

Figure 5. The EIA-152-B Minimum Standard for Land
Mobile FM or PM Transmitters gives a 6dB/octave
pre-emphasis characteristic tor a radio transmitter's
300Hz to 3,OOOHz voice band. Notice that CTCSS
audio at 250Hz is down only 1.5dB from the filter's
300Hz passband on this slope.

MX-COM, INC.

access.

ogy might be made to a sealed letter, in contrast to a
postcard. Although easy for anyone to open, generally
only the addressee reads a letter.
With private squelch, perhaps the letter is locked in a
mailbox. To get the information, one must either have a
key or pick the lock. Without private squelch, radio messages are like postcards, with a content available to
anyone. This is no public right to the content, only ready

Private squelch offers a simple form of privacy to
millions who use radio party lines. The privacy is
achieved without reducing audio quality or adding highpriced hardware. It is achieved by applying integrated
circuit technology to a Signaling system an early CTCSS
equipment manufacturer had the foresight to call "Private Line."

DE-EMPHASIS

PRE-EMPHASIS
MIC

/

I----

I~

-

MXOO4
VOICE
FREQUENCY
INVERTER

TRANSMIT
MODULATOR

PTL
SPEAKER
AMP

RECEIVE
DEMOD

PTT

I

I

+

PRIVACY
ENABLE

SQUELCH
CONTROL

DO
CTCSS
PROGRAM
LINES

D1
D2
D3

MX 365
CTCSS
ENCODERDECODER

-

D4
CTCSS
TONE

D5

-

FIGURE 6. A block diagram of the typical private squelch encoder-decoder. A private squelch adapter, for
systems in which the CTCSS encoder-decoder already exists, need only include emphasis and speech
inverting filters. The adapter's monolithic implementation allows a board the size of a postage stamp, a board
that fits most radios.

I
MX-COM, INC.

Page 537

Generation of Non-Standard CTCSS Tones

MX·COM manufactures several integrated circuits which encode and decode CTCSS tones at the EIA RS-220
standard frequencies. In many instances, however, using tones of slightly different frequencies may be desirable.
Because these MX·COM ICs use switched capacitor technology, tone frequencies may shifted simply by changing the
crystal or clock input. The following three tables list altemative tones which can be encoded and decoded by the MX36SA
and the MX37S, and encoded by the MX31 SA.
Each table lists the tone frequencies for three crystal values for each Chip. The MX31SAand MX36SA use a nominal
crystal value of 1.0 MHz; the table lists tone frequencies for 1.008 MHz and 1.024 MHz crystals as well as for 1.0 MHz.
The MX375 uses a 4.0 MHz nominal crystal value; its table lists frequencies for 4.0 MHz, 4.032 MHz, and 4.096 MHz
crystals. The column labeled as "Divisor" for each table lists the quotient of the clock frequency divided by the tone
frequency. This column can be used to calculate the clock frequency required to generate other tone frequencies. Each
table also lists the (OS-~O) program code input associated with each divisor and tone frequency group. Each code is
listed in both binary and hexadecimal formats. As an example, to encode a 70.0 Hz tone with the program code input
OS-~O:: 011111 (1 F Hex), the required clock would be calculated in the following manner:
OS 04 03 02 01 DO
o 1 1
1 1
Divisor =13908
Tone frequency = 70.0 Hz
Required clock frequency = Divisor * Tone Frequency
=13908 * 70.0 Hz
= 973S60 Hz

When using these ICs in this manner, you must remember the following:
1) When the clock is changed, the audio pass band limits will change proportionately. These changes will
be fairly small, however. For example, in the MX36SA using a 1.024 MHz crystal, the lower limit will
change to (1.024/1.0) * 300 =307 Hz, and the upper limit will change to (1.024/1.0) • 3000 = 3072 Hz.
2) In the MX37S, the frequency inversion carrier frequency will also change proportionately from its
nominal value of 3333 Hz. For example, with a 4.096 MHz clock, the carrier frequency will change to
(4.096/4.0) ·3333 Hz = 3413 Hz. For proper communication, the transmitter and receiver must use the
same inversion carrier frequency.

I
Page 538

MX-COM, INC.

Device: MX365A

Divisor

Xtal Freq

1.0 MHz

Xtal Freq
1.0OB MHz

1.024 MHz

14914
14426
13908
13450
12994
12536
12108
11712
11285
10919
10553
10279
10004
9668
9333
9028
8723
8418
8143
7869
7595
7320
7076
6832
6619
6374
6161
5947
5764
5551
5368
5185
4910
4758
4575
4422
4270
4148
3996

67.05
69.32
71.90
74.35
76.96
79.77
82.59
85.38
88.61
91.58
94.76
97.29
99.96
103.43
107.15
110.77
114.64
118.80
122.80
127.08
131.67
136.61
141.32
146.37
151.09
156.88
162.31
168.14
173.48
180.15
186.29
192.86
203.65
210.17
218.58
226.12
234.19
241.08
250.28

67.59
69.87
72.48
74.94
77.58
80.41
83.25
86.06
89.32
92.31
95.52
98.07
100.76
104.26
108.01
111.66
115.56
119.75
123.78
128.10
132.72
137.70
142.45
147.54
152.30
158.14
163.61
169.49
174.87
181.59
187.78
194.40
205.28
211.85
220.33
227.93
236.06
243.01
252.28

68.66
70.98
73.63
76.13
78.81
81.68
84.57
87.43
90.74
93.78
97.03
99.62
102.36
105.91
109.72
113.43
117.39
121.65
125.75
130.13
134.83
139.89
144.71
149.88
154.72
160.65
166.21
172.18
177.64
184.47
190.76
197.49
208.54
215.21
223.83
231.55
239.81
246.87
256.29

MX-COM, INC.

Xtal Freq

1

1

1

3F

o

0

39
iF

o
o
o

0

1

1

1

o

0

o
o 0
o

o
1

o

1
1

o

o
1

1

o

0

o
o
o
o
o

00

lD
3A
1C

OC

1

lB

OB

19
09
18
08
17
07
16
06
15
05
14
04
13
03
12
02
11
01
10
00

o
o
o
o

0
0

o
o

o
o

0

1

OE

o
o

011
010
o 1 0

1

3C
3B

o
0

OF
3D
1E

1
1 0 1
010

0
100

0

3E

0

0 1
000
000

o

000
1
o 1 0 1
o
o
000
o 1 0
0 1
o 0 0
0 1
o 1 0 1 0 0
000 1 0 0
o 1 0 0
00001
o 1 000
00000
o
000
000001
o 1 0 0 0 0
000 0 0 0

1A

OA

Page 539

I

Device: MX375

I

Xtal Freq

Xtal Freq

Xtal Freq

Divisor

4.0 MHz

4.032 MHz

4.096 MHz

59657
55633
53800
51975
50144
48432
46849
45142
43678
42212
41114
40016
38673
37331
36111
34892
33670
32573
31476
30379
29280
28305
27328
26474
25497
24644
23790
23057
22204
21472
20740
19642
19032
18300
17690
17080
16592
15982

67.05
71.90
74.35
76.96
79.77
82.59
85.38
88.61
91.58
94.76
97.29
99.96
103.43
107.15
110.77
114.64
118.80
122.80
127.08
131.67
136.61
141.32
146.37
151.09
156.88
162.31
168.14
173.48
180.15
186.29
192.86
203.65
210.17
218.58
226.12
234.19
241.08
250.28

Page 540

67.59
72.48
74.94
77.58
80.41
83.25 .
86.06
89.32
92.31
95.52
98.07
100.76
104.26
108.01
111.66
115.56
119.75
123.78
128.10
132.72
137.70
142.45
147.54
152.30
158.14
163.61
169.49
174.87
181.59
187.78
194.40
205.28
211.85
220.33
227.93
236.06
243.Q1
252.28

68.66
73.63
76.13
78.81
81.68
84.57
87.43
90.74
93.78
97.03
99.62
102.36
105.91
109.72
113.43
117.39
121.65
125.75
130.13
134.83
139.89
144.71
149.88
154.72
160.65
166.21
172.18
177.64
184.47
190.76
197.49
208.54
215.21
223.83
231.55
239.81
246.87
256.29

1

3F

o
o

1

iF

o

3E

1

OF

0

o

1

o
1

1

o

0

o
1

1

o
o
o
o
o
o
o
o
o
o
o

0
0
0
1

0
0
1

0

1

0

3D
1E

o

0

3C

o

OE

o

1

1

0
1

1
0

o
o

0

1C

1 0 0
011
o
1

OC

o

o
o
o
o
o
o

1

o
o
0
0
0
0

0
0

010
000
010
o
o
000
o 1 0
0
00001
o
0
0 0
000 1 0 0
o 1 0 0
o 0 0 0
1
o
0 0
0
o 0 0 0 1 0
o 1 000
o 0 0 0 0
o 1 0 000
00000 0

38
10
3A

OD

18
08
1A

OA
19
09
18
08
17
07
16
06
15
05
14
04
13
03
12
02
11
01
10

00

MX-COM, INC.

Device: MX315A
Xtal Freq

Xtal Freq

Xtal Freq

Divisor

1.0 MHz

1.008 MHz

1.024 MHz

14912
14415
13920
13454
12989
12555
12121
11718
11284
10943
10540
10261
10013
9672
9331
9021
8711
8432
8122
7843
7595
7316
7068
6851
6603
6386
6169
5952
5766
5549
5363
5177
4929
4836
4743
4588
4433
4278
4123
3999

67.06
69.37
71.84
74.33
76.99
79.65
82.50
85.34
88.62
91.38
94.88
97.46
99.87
103.39
107.17
110.85
114.80
118.60
123.12
127.50
131.67
136.69
141.48
145.96
151.45
156.59
162.10
168.01
173.43
180.21
186.46
193.16
202.88
206.78
210.84
217.96
225.58
233.75
242.54
250.06

67.60
69.93
72.41
74.92
77.61
80.29
83.16
86.02
89.33
92.11
95.64
98.24
100.67
104.22
108.03
111.74
115.72
119.55
124.10
128.52
132.72
137.78
142.61
147.13
152.66
157.84
163.40
169.35
174.82
181.65
187.95
194.71
204.50
208.44
212.53
219.70
227.38
235.62
244.48
252.06

68.67
71.04
73.56
76.11
78.84
81.56
84.48
87.39
90.75
93.57
97.16
99.80
102.27
105.87
109.74
113.51
117.56
121.45
126.07
130.56
134.83
139.97
144.88
149.46
155.08
160.35
165.99
172.04
177.59
184.54
190.94
197.80
207.75
211.75
215.90
223.19
230.99
239.36
248.36
256.06

MX-COM, (NC.

3F

o

0

39

o
o

1

o

0

1

1

1.

o

o
o

1

o

1
1

0
0

o

0

o
o

0

o
o

0

OE
10

0

3A

1

00

0

1C

0

100

OC

1
0

o
o
o
o
o
o
o

0
1

0

1B

1

1

OB

0
0

OA

0
0

0 0
000

1

0
0

000
010
000
010
000

o

OF
3D
1E
3C
3B

o
o
o
o
o
o
o
o
o
o
o
o
o

1F
3E

0

o
1

0

o
o
o
o

0
0

1

000
o
0 0
000 0
1
1 0 0 0
00010
00001 0
o 1 000
o 0 0 0 0
o
0 0 0 0
00000 0

1A

19
09
18
08
17
07
16
06
15
05
14
04
13
03
38
12
02
11

01
10

00

Page 541

I

The EIA RS-220 specification divides the standard frequencies into three groups. They are tabulated below
with the program codes used in MX-COM ICs:

GroupS

Group A
Freq
67.0

n.0
88.5
100.0
107.2
114.8
123.0
131.8
141.3
151.4
162.2
173.8
186.2
203.5
218.1
233.6
250.3

Code
3F
OF
OE
00
OC
OB
OA
09
08
07
06
05
04
03
02
01

Freq
71.9
82.5
94.8
103.5
110.9
118.8
127.3
136.5
146.2
156.7
167.9
179.9
192.8
210.7
225.7
241.8

Code
1F
1E
10
1C
1B
1A
19
18
17
16
15
14
13
12
11
10

Groupe
Freq
74.4
79.7
85.4
91.5
97.4
69.3
206.5

Code
3E
3D
3C
3B
3A
39

38

00

Note that with the exception ofthe 67.0 Hz tone in Group A, the programming codes are in reverse sequential
order in relation to the tone frequencies for each group. Again, with the exception of 67.0 Hz, also note that the
first hexadecimal digit for Group A is 0, the first digit for Group B is 1, and the first digit for group C is 3.
For more general information about these ICs, see the MX-COM Product Handbook and the MX-COM
MX315A and MX365A Data Bulletins.
MX-COM does nottest its CTCSS ICs (MX315A, MX365A, MX375) at crystal or clock frequencies other than
the nominal frequency specified in the Product Handbook or Data Bulletin, and as such, makes no guarantee of
the performance of the device when used with a non-specified crystal or clock frequency. MX-COM does not
assume responsibility for the use of its ICs in the manner described in this application note in any circuit or product.

I
Page 542

MX-COM, INC.

II

MX-COM Inversion Security Devices

II

Split-Band Scrambling
Furnishes Voice Security
Voice scrambling offers tactical security for radio dispatch communications.
It takes so long, even for a dedicated eavesdropper, to unscramble
your transmissions that the information would be worthless by then.
0

By Steve Kelley and
Hank Wallace

-10

800Hz
REFERENCE
TONE"

RAT PASSBANO

/1PPlE. CHAAACTERISI1CS

-20

Unwanted consequences of thirdparty radio communications eavesdropping include foiled drug busts, unsolved burglaries and pirated business
opportunities. Some mobile radio users employ voice privacy and voice
security devices to scramble their communications. Most users who need
voice security continue to communicate in the clear, however, for several
reasons:
(1) Cost --They cannot justify the
captial expense.
(2) Techno/ogy-- The poor quality
of recovered audio and the radio range
reduction common to many voice security systems discourage their use.
(3) Availability -- Two principal
scrambling alternatives, frequency inversion and digital encryption, are not
suitable for many applications. Frequency inversion offers privacy but not
security; digital encryption offers high
security but with a high price tag.
Semiconductor technology advances have reduced costs and improved the quality of voice security
products. Variable Split-Band (VSB)
scrambling has become economical
because of such advances.

71h ORDER ElliPTIC.!

.3(J

~

ALlER fc .. 3,4QOHz

"10

1.000

MX-COM, INC.

3.000

4.000

Hz

Figure 1A - Audio output of VSB filter array IC in clear mode
0
-10
-20

1.=~

.3(J

~

"10

2,000

1.000

3,000

4,000

Hz

Figure 1B - Audio output of VSB filter array IC in "scramble" mode with
split point at 2,333Hz.

-10

SPlIT POINT, 1;!OOHz

_-:-_1

-20

~ CARRIER, l,solHz

How it works
Filters separate the voice band
(400Hz to 2700Hz) into a pair of subbands (32 pairs are possible). (See
Figures 1A, 1B and 1C.) A mixer fed
with a carrier signal inverts the subbands; a summing amplifier recombines them. Ordinary radio transceiv-

2.000

I

-70

1,000

2,000

3,000

4,000

Hz

Figure 1C - Audio output of VSB filter array IC in "scramble" mode with
split point at 1,200Hz.
Page 543

FOURTH
SPLIT POINT

PUSH-TO-TALK
BUTTON
PRESSED

FREQUENCY

~
SYNC

SYNC

TIME

Figure 2 - The effect of rolling code split points on the transmitted radio spectrum
ers transmit the resulting variable split-band-scrambled
output via an ordinary radio communications channel.
Microprocessor outputs control the split point (the frequency at which the voice band is subdivided) and change
itfrom 4 to 60 times per second. Figure 2 reveals the "rolling
code" nature of VSB scrambling. One of more than 65,000
unique user-programmable code keys initializes the pseudorandom sequence of split points. User programming
commands the split point's rate of change, or "hop rate," to
vary pseudorandomly or in a fixed fashion.

Microprocessor Control
The VSB microprocessor performs scramble system
control functions, including:
generation of split-point sequences
control of system synchronization
monitoring of the push-to-talk (PTI) line

Filtering Accuracy

code key selection

Optimum recovered audio quality depends upon highly
accurate voice filtering. Two pairs of 7th order, switchedcapacitor, elliptic filters in the VSB filter array integrated
circuit (Ie, on-chip) accomplish all the filtering (See Figure

code key loading

3).

I

sequence of split points. Table 1 shows the exact relationship between each split point and its associated carrier
frequencies.

The transceiver's mic. audio pre-amplifier or receiver
audio demodulator output feeds the VSB filter array Ie's
highband and lowband inputs. Within the Ie, audio from
each subband passes through a lowpass filter, a frequency
inverter and another lowpass filter. A summing amplifier
recombines the subbands. The chip includes a highpass
filter that permits VSB scrambling to be used with continuous-tone controlled squelch systems (eTeSS) and other
sub-audible signaling schemes.
On-chip programmable dividers with a 5-bit logic address control the 32 split points and their highband and
lowband carrier frequencies. The VSB microprocessor
uses the 5-bit address to generate a rapidly changing
Page 544

selection of the secure or clear mode.
The microprocessor generates pseudorandom strings
of split points initialized by one of four user-programmable
code keys. Non-volatile, electrically erasable, programmable read-only memory (EEPROM) stores the code keys
and other user-programmable system information (see
Figure 4).
To decode a rolling, VSB-scrambled message properly, the receiver(s) must "hop" in unison with the transmitter from one split point to the next. A continuous synchronization scheme accomplishes this task. The scheme
transmits 1200-baud minimum-shift keyed (MSK) data
bursts every three seconds. Authorized parties can descramble transmissions even if the beginning of the message is missed, preserving mobile radio's inherent "late
joining" feature.
MX-COM, INC.

~

8

~

~
Ck.
AX IN

iSS

~I

,

TX IN

J5S

BIAS
BIAS

'-IICs

Rgure 3 - Functional block diagram of the VSB filter array

~

cal

&

..

PS+EN·RX

• AX OUT

ROM Address Split Point
Hz
A4- A O

00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111

2800
2625
2470
2333
2210
2100
2000
1909
1826
1750
1680
1555
1448
1354
1272
1200

Low Band
Carrier, Hz

High Band
Carrier, Hz

fo1

fo2

3105
2923
2777
2631
2512
2403
2304
2212
2127
2049
1984
1858
1748
1655·
1572
1501

ROM Address Split Point
A 4-Ag
Hz

10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

6172
6024
5813
5681
5555
5494
5376
5263
5208
5102
5050
4950
4807
4716
4629
4587

1135
1050
976
913
857
792
736
688
636
591
552
512
471
428
388
350

Low Band
Carrier, Hz

High Band
Carrier, Hz

fe'

fo2

1436
1351
1278
1213
1157
1094
1037
988
936
891
853
813
772
728
688
650

4504
4424
4347
4310
4273
4166
4132
4065
4032
3968
3937
3906
3846
3816
3787
3731

Table 1 - ROM Address Programming
In the absence of valid synchronization bursts, receivers revert to clear mode. The automatic reversion to clear
mode ("clear voice override") makes scrambling easier to
use in systems that include some radios not equipped for
scrambling.
Only transmitting VSB units generate synchronizing
data bursts, so the system resynchronizes at the transmitting station's command. Transceivers automatically transmit 80ms data bursts every three seconds after beginning
a transmission. Each data burst includes:

Unit System Address -- Identifies the scrambler as part of a
designated group.
Code Key FileNumber--ldentifies which of the four stored code
keys to use.

uses the time-of-day signal and synchronization cue to
descramble the incoming message properly. Unless the
receiving unit receives the proper address and file combination, it processes incoming transmissions as though they
were unscrambled.
A robust error-detection algorithm, based on the British
MPT 1317 signaling protocol, minimizes synchronization
errors. As a safeguard, VSB scramblers retain synchronization even if a single synchronization burst is missed. If
the scrambler misses two synchronization bursts in a row,
EXTERNAl LOGIC CONTROLS

{)"
VSB

AX IN

AX OUT

FILTER
ARRAY
IC

TX IN

TX OUT

Time Of Day -- When mixed
with the secret code key, which
never is transmitted, time of day
tells the receiver on which part of
the 50-hour long split-point sequence to begin "hopping."

Synchronization Cue -- Tells

I

the receiver when to change split
pOints.
In the standby mode, VSB
scrambling units scan continuously
for incoming synchronization bursts
that have the proper system address and file number. After receiving one such data burst, a VSB unit
Page 546

b

~

~
MSK
MODEM
IC

I

A

VSB

A

lIP

EEPROM
IWDEKEY
ORAGE)

ft
I I

EXTERNAl LOGIC CONTROLS

Figure 4 - Block diagram of VSB scrambler mode
MX-COM, INC.

range.
An eavesdropper monitoring a VSB-scrambled transmission hears an unintelligible jumble, interrupted by bursts
of digital "static" every three seconds. Consider VSB
scrambling's security features:
(1) The split-point sequence permutation, which is
based on a mixture of the secret code key and the time-ofday Signal, changes automatically every three seconds.
The code knowledge that may be obtained from one
descrambled three-second sequence cannot be applied to
descramble subsequent segments because they are based
on different sets of pseudorandom permutations.
(2) The split-point "hop rate" may be varied pseudorandomly, further complicating the task.

the system reverts to the standby mode and scans once
again for synchronization burst data.
Minimum-shift keyed modulation offers excellent narrowband transmission properties and superior noise performance. With MSK modulation, voice intelligibility and
synchronization are lost more or less concurrently in fringe
reception areas and without an appreciable loss in radio

(3) Each VSB-equipped radio can transmit and receive
four programmed code keys, and VSB systems can accomodate as many as 16 unique code keys. Thus, a unit can
transmit on one code key and receive on another.
(4) The code keys may be changed at any time. They
never are transmitted. They cannot be deduced by visual
or mechanical means.
Given these security features, how difficult is it to

VSB Scrambling Multiple Codekey Capability
Within a VSB scrambling network, up to 16 codekeys can be allocated. Four of the sixteen codekeys can be
installed per radio. As illustrated below, this capability can create interesting subgroup segregation possibilities:
Scenario: Public safety departments of medium-sized cities need interagency, as well as private, intradepartmental secure communications.
Solution: A VSB Scrambling codekey allocation scheme allocates seven codekeys (A-G), fourto the police force,
and two each to the fire department, ambulance service, and detective unit.
USER
SUBGROUP

INSTALLED

CODEKEYS

COMMUNICATIONS
CAPABILITY

1) HQ/Supv.

All

Monitor all channels

2) Police

A
B
C
D

Intradepartment only
Police and fire
Police and detectives
Police and ambulance

3) Fire

B
E

Police and fire
Intradepartment only

4) Detectives

C

Police and detectives
Detectives only

F
5) Ambulance

D
G

Figure 5 - Multiple codekeys extend subgroup segregation possibilities in
department

MX-COM, INC.

I

Police and ambulance
Intrasquad, ambulance
and hospital

a medium-sized city's public safety
Page 547

descramble such a garbled transmission? According to two
experts, it is not easy.
According to Michael Washvill, a voice and data security specialist with a federal agency, "VSB scrambling can
be broken, but not in real time. The only practical attack is
through trial and error. The scrambled speech must first be
recorded, then divided into finite time segments according
to the hop rate. Each segment is processed through a
variety of split point combinations until clear speech results."
A TRW systems engineer and former U.S. Department
of Defense employee, Jim Walker, concurs: ''The 'brute
force' method oftrial and error is the only way to break VSBscrambled speech. Assuming that the 'bad guys' have a
stolen VSB unit and no prior knowledge of the code key or
code keys, 50 to 100 minutes of dedicated effort are
required to descramble one minute of VSB-scrambled
speech. A rule of thumb is 60: 1 'grunt time to clear speech
time'."
Walker continued, "For most eavesdroppers, the potential rewards do not justify the time and effort. Two
additional factors come into play. First, by the time the
information is decrypted, will it still be of any use? Second,
what percentage of the descrambled radio traffic will be of
value?"
Given the time and perseverance required to break a
VSB-scrambled transmission, two alternatives become
much more attractive to those who want to eavesdrop:
Steal a VSB-equipped radio or bribe someone who knows
the codekey. Strict code key management procedures
reduce system vulnerability to these attack methods.
To reduce the possibility of bribery, restrict code key
knowledge to one person. To guard against stolen VSB
units, change system code keys on a regular basis by using
the VSB keyloader.
The keyloader is a portable tool that reprograms VSBequipped radios in the field. A technician connects the
keyloader's data-loading cable to a VSB-equipped radio

and presses the load button to install as many as four new
code keys into each radio. Only the person with codekey
management authority can program the keyloader or read
its contents.

Tactical vs. Strategic
Voice security requirements can be divided into two
broad categories: tactical and strategic. Tactical applications are those in which the secrecy of the message is timedependent, such as battlefield tactical communications,
most municipal police communications and nearly all dispatch communications. The tactical message retains its
value for one or two hours at most. VSB scrambling serves
tactical security requirements.
James Bramford, in his book The Puzzle Palace, defines strategic communications as ''the high-level diplomatic, commercial and military communications that might
give away a nation's foreign policy venture, where and with
whom it was doing business, or what new weapons were
being developed over the next few years." Today's strategic applications demand some form of digital encryption.
In addition to the message security afforded by digital
encryption or VSB scrambling, transmission security can
be assured through spread-spectrum techniques, such as
frequency hopping, which render the radio signal both
undetectable and immune to jamming.
Most mobile radio users have tactical voice security
requirements. For these applications, VSB scrambling
offers a practical, economical alternative to digital encryption systems. VSB scrambling requires no modification of
the installed communications network. It has little or no
impact on radio range.
As dealers and users become more comfortable with
VSB and other new scrambling technologies, foiled drug
busts, unsolved burglaries and pirated business opportunities resulting from unauthorized eavesdropping will become things of the past.

MX·~,IN~.

I
Reprinted with permission from the May 1988 issue of Mobile Radio Technology. Copyright 1988, Intertec Publishing
Corp., Overland Park, KS. All rights reserved.

Page 548

MX-COM, INC.

SWITCHED CAPACITOR INTERFACING
Anti-Aliasing and Smoothing Filters
By Jim Kemerling
MX-COM, INC.

1.0 Introduction
Switched capacitor networks (SCNs) are sampled data systems and therefore are governed by the principles of
discrete time signal processing. In this context, "discrete time" means the signal is sampled prior to processing.
However, the amplitude is continuous - unlike digital signal processing (DSP) systems where both amplitude and
time are discrete.
VLSI technology (generally CMOS) has facilitated complete integration of SCNs on a single monolithic chip. Filters
utilizing switched capacitor techniques (SCFs) are composed of switches, capacitors and opamps. Notice resistors
are not mentioned. The resistors normally present in active filters are approximated by switched capacitors. By
taking advantage of matching properties of CMOS capacitors, SCFs can be fabricated with low tolerance levels
(less than 0.1 'Yo) and virtually any order.
The wireless and wireline telecom industries have made extensive use of SCFs. Even with the move towards digital technology and the ensuing popularity of DSP in the communications industry, SCNs are frequently employed
where cost and power consumption are critical. SCNs generally have relatively high sampling rates (typically greater
than 20 times the bandwidth of the interest) due to their discrete time nature, so aliasing and output smoothing
must be addressed. Often a simple Single pole filter (R-C network) suffices, but the location of these poles must be
carefully thought out in the design process. The world is still analog.
The purpose of this paper is to address the need for anti-aliasing and smoothing filters for SCFs. First, the basics
of sampling will be reviewed. The fundamentals of SCNs will follow this, and finally the design of antialiasing and
smoothing filters for SCFs is addressed.

2.0 Sampling [3]
Before a continuous signal is processed by a discrete time filter it must first be sampled. Referring to Figure 1a,
sampling is the process of instantaneously capturing the level of a continuous signal at some predetermined rate.
This predetermined rate is the sampling frequency. As the sampling rate increases (Figure 1b) the sampled signal
begins to approximate the original continuous signal.

I
MX-COM, INC.

Page 549

...

f(t)

fS(t)

--1

1\>2

:I
:I

I I
III(

III(

I
T

T

>

I I

I
I
•

I I

Figure 7 - Non-overlapping clocks for SC integrator

4.0 Anti-aliasing and Smoothing Filters for SCNs [2]

I

SCFs approximate active-RC filters by replacing resistors with switched capacitors. As the clock frequency (sampling rate) tends towards infinity the SCF becomes equivalent to the continuous time filter. In other words, higher
clock frequency yields a better approximation of the desired response. Also, higher clock frequency lessens the
requirements of the anti-aliasing filter (AAF) and smoothing filter (SMF). However, there are upper limits on clock
frequency. Although SCFs have been implemented with clock frequencies greater than 1MHz, typical telecom filters (8W less than 10kHz) are clocked at or below 250kHz.
One factor which opposes higher clock frequencies is large capacitor ratios. Referring to the example in section

Page 554

MX-COM, INC.

3.0, using 1MHz in place of 100kHz, C1 becomes 0.1885 pf. The ratio between C1 and C2 is now 53.05 where it
was 5.305. Large capacitor ratios consume more silicon area and are more sensitive to process and temperature
variations. Hence, the final sampling rate is a compromise between SCF implementation complexity and SMF/AAF
requirements.
SMFs and AAFs can be integrated, but they are subject to the same problems associated with the continuous time
RC integrator discussed in section 3.0 and are generally implemented externally. In some cases, where input and
output signals are band limited externally, additional circuitry for AAFs and SMFs is not required. A block diagram of
a typical SCF system, including AAF and SMF is shown in Figure 8.

IN

OUT

AAF

SCF

SMF

fclk

Figure 8 - SCF system with AAF and SMF
To determine AAF and SMF requirements the system designer must know the sampling frequency ({clk) and the
bandwidth (BW) or cutoff frequency ({co) of the SCF. For discussion purposes, assume/clk=1 OOkHz andfco=5kHz.
Recall from section 2.0, if any signal energy is present at the input, with frequency Is greater than 1121clk, it will be
aliased to fclk -Is. Hence, an input with Is=99kHz will be aliased to 1kHz. This aliased Signal will appear as noise
in the passband of the SCF. To eliminate or reduce the effect of this noise the AAF must band limit the input signal
to fclk - Ico (see Figure 9).

ANTIALIASING FILTER RESPONSE

IMI

..... .....
..... .....
..... .....
.....
fco

5kHz

fclk

2'"

fclk

100kHz

fclICfco

105kHz

Figure 9 - AAF requirements for SCF system

To obtain 20 dB suppression of aliased noise the minimum requirement for the AAF is a first order section (single
pole) with it's cutoff frequency set to 9.5kHz. (20 dB/decade/pole). Placing the pole at 9.5kHz minimizes the effect
on the SCF passband response. To obtain further suppression more poles are necessary.

MX-COM, INC.

Page 555

I

The single pole AAF can be implemented with a simple RC at the input to the SCF. The values for can be arrived at
by using

1
RC=--

(8)

27t.f\J

where, fp

= pole frequency.

For the AAF response depicted in Figure 9, RC = 16.75ms. Setting C = 0.1~f yields R = 16Sil. The simple RC
network should be used with caution-capacitive loading can cause stability problems. Also, the value of the resistor
should be insignificant compared to the SCF input impedance.
A superior solution makes use of an additional opamp forming a damped integrator (see Figure 10). Often this
opamp will be available on the SCF chip.
The complete network, including R1, C1, R2 and C2, forms a bandpass filter with a frequency response characteristic as shown in Figure 11.

C2

SCF

Figure 10 - Active RC AAF

20 dB/decade
-20 dB/decade

I

Figure 11 - AAF frequency response

Page 556

MX-COM, INC.

The highpass cutoff ((hp) and lowpass cutoff Vip) are determined by

(9)

and

(10)

The passband gain is set by
Gpb

= R2IR1

(11)

C1 is not required if the input signal is biased properly (SCF internal bias = external bias).
To meet the AAF requirements shown in figure 9 (assuming unity passband gain, lip
R1 = R2 = 100KQ, C2 = 168pf and C1 = 0.01591lf.

=9.5kHz and ihp = 100 Hz)

SMF requirements are similar to those of the AAF. The SCF output is a sampled signal and therefore contains
replicas of the SCF response at multiples of the sampling frequency. If left unfiltered these replicas appear as high
frequency (clock) noise. In some cases this is tolerable. However, in systems where minimum noise is critical the
SMF is required.

5.0 Conclusion
Switched capacitor filters are sampled data systems and hence require anti-aliasing filters at their inputs and smoothing filters at their outputs. The simplest form (and often sufficient) of these filters is the single pole RC network.
Other forms such as active RC networks and higher order filters can yield distinct benefits. In any case, application
of switched capacitor filters must be viewed at the system level in order to realize optimum performance.

REFERENCES
[1]
R. Gregorian, K. W. Martin, and G. C. Temes, "Switched-Capacitor Circuit Design,"
IEEE, pp. 941-966, August 1983.

Proceedings of the

L. P. Huelsman and P. E. Allen, Introduction to the Theory and Design of Active Filters, McGraw-Hili, New
[2]
York, 1980.
[3] A. B. Jerri, "The Shannon Sampling Theorem - Its Various Extensions and Applications: A Tutorial
Review," Proceedings of the IEEE, pp. 1565-1596, November 1977.

MX-COM, INC.

Page 557

I

An Audio Delay Circuit Based on the MX609 CVSD Codec

The schematic diagram shown on the following page
is an audio delay circuit based on the MX609 CVSD
Codec. In addition to the MX609, the circuit uses a Fujitsu
MB81 C71 64K x 1 bit RAM, two 4520 counter ICs, and a
4069 inverter chip. It provides up to two seconds of delay.
This circuit provides a starting point for a designer who
wishes to implement an audio delay circuit. MX-COM
makes no guarantee of its performance and assumes no
responsibility for its use in any product.

I

Circuit Operation
In the following operational description, a bar over a
signal name is used to indicate an active low signal. For
example, W is an active low write enable signal. On the
MX609P, Clock Mode 1, pin 22, is tied to V DD and Clock
Mode 2, pin 21, is tied to ground to set the encode and
decoder clocks for a sampling rate of 32 kb/s. The Encoder
Force Idle, Powersave, and Decoder Force Idle inputs,
pins 6, 15, and 16, respectively, are tied to VDD to set them
inactive. The Data Enable input, pin 7, is tied to VDD to make
the encoded data available at the Encoder Output, pin 5.
Pin 19, the Algorithm select input, is tied to ground to select
a four-bit companding algorithm. The other inputs are the
same as recommended for "External Component Connections" shown in the MX-COM data book.
The audio signal to be delayed is input to pin 10 of the
MX609, the Encoder Input, and is converted to a serial
stream of digital data. The serial data are output on pin 5,
the Encoder Output, and connected to pin 13, the D input,
of the MB81 C71 memory Chip. The Decoder Data Clock
output from pin 18 of the MX609 is connected to pin 1 of the
4069 inverter. The output of the inverter, pin 2, is connected to pin 10 of the MB81 C71 , the IN input, and to pin
3 of the 4069, the input to second inverter. Pin 4, the
inverter output, is connected to the enable input of the first
4520 counter.
The enable input is taken from the second inverter to
ensure thatthe 4520 counters increment after theW signal
into the 81C71 transitions from low to high. The clock
inputs of each ofthe 4520s, pins 1 and 9, are tied to ground
so that only the enable inputs control when the counters
increment. The reset inputs, pins 7 and 15, are also tied
to ground so that they never reset the counters. The
individual four bit counters in the 4520s are cascaded to
produce a 16 bit counter. The counter outputs, 015 - 00,

Page 558

are connected to the address inputs, A 15 - AO, of the
MB81C71.
There are switches between 015 and A15 and
between 014 and A 14. The switches allow the number of
bits of the counter, and therefore the length of the delay, to
be adjusted. When the Decoder Data Clock falls from high
to low, the counter, and therefore the address, increments.
Since the W input to the memory, pin 17, is the complement
of the clock, it rises from low to high, latching the encoded
databitatthe D input. The Einputtothe MB81 C71, pin 12,
is tied to ground so that the memory is always selected.
When W is high and the address is stable, a valid data bit
appears at the 0 output, pin 17, of the MB81C71. The
address of the data bit appearing at 0 is one greater than
the address of the bit that was just written, so the counter
must cycle through its entire range before a data bit that
has been written into the memory can be read. Therefore,
a data bit output from the MX609 at the Encoder Output pin
is delayed by the number of clock periods of the range of
the counter. The delay is given by
Delay = (T sec/cycle)' (2 N cycles)
where
T = period of Decoder Data Clock
N number of bits used in counter

=

If all 16 bits of the counter are used, and the decoder
clock frequency is 32 kHz, then the delay would be
Delay

=(1/32000) sec/cycle' (216) cycles
= 2.048 seconds

In this example, all locations of the memory are used.
If a shorter delay is desired, the switches connecting the
counter outputs and address inputs can be opened. If only
14 bits of the counter are used, then the delay is reduced
by a factor of four, to 0.512 seconds. The range of delays
could be increased even more by adding more switches
and by making the sampling clock frequency adjustable.
The 0 output, pin 9, of the MB81 C71 is connected to the
Decoder Input, pin 17, ofthe MX609. The decoder clocks
in the serial digital data stream from the memory and
converts it to an analog signal which is output at pin 13, the
Decoder Output. The Decoder Output is the delayed audio
signal.

MX-COM, INC.

+5
1?

"*"

10
1~

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MB81C71

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'

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-50

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2.5

FREQUENCY
BIT RATE

Figure 4 - GMSK Spectrum

The Effect of Modem Bandwidth on Bit Error Rate (BER)
The basic measure for rating one modem against another is its BER performance. BER is the ratio of error bits
to the total transmitted bits for a given level of signal-to-noise (SNR). BER performance is dependent on the noise
bandwidth at the modem's internal data detector circuit. The narrower the modem's bandwidth, the better BER for
same SNR at the modem's inputs. An MSK modem has a 1200Hz noise bandwidth where a Bell 202 type has
approximately 2500Hz. The improved performance using a typical FM receiver is shown in Figure 5, with the MSK
modem outperforming the Bell 202 by several dB.
In a given radio link, BER performance varies with signal-to-noise, and fringe area service decreases SNR. Noise
increases errors (see Figure 6). MSK-1200 performs several dB better than voice, on the premise that voice follows.
In trunking and SelCall systems, the data is used to set up a voice link, so there is no pOint in grossly over-reaching
the radio's voice range. A SINAD of 12 dB is the accepted limit of voice intelligibility, and 8 to 10 dB SINAD is the goal
of MSK-1200 service.
Poor performance under good signal conditions points to elements in the detection process that are not correctly
aligned. Modems made from discrete components typically need periodic re-alignment. Data carriers drift or the PLL
goes off center. IC Modems lock onto quartz crystals, use digital frequency dividers and switched capacitor filters that
don't drift, and don't need alignment because there's nothing to align.
Once the modem is in your radio system, you will test it. Modem testing is optimized for test time (cost) and

MX439/469
MSKModem
Radio Audio or Baseband

Data

I~=-------·-·:~
RF Amp

IF

IF Amplifier

Mixer

Filters

Discriminator

&

I

&

Carrier

Detector

Data
Carrier
Detect

~==:::::::t::~

r

Data

RF Carrier
Detectors

Local
Oscillator

,

./

l____.____.___.___._.___._______.___.__.____..._.____._._. ____._.__...__..._. __J

RF Transceiver (typ)
Figure 5 - MSK Modem Together With a Typical FM Receiver
Page 564

MX-COM, INC.

statistical significance of the test results.
For example, the MX439 1200 bps modem, rated at 10-3 BER at -117 dBm RF
signal level, will require 12000 bits to
detect up to 12 errors and will take 10
seconds to test. That is a reasonable
amount of test time. However, if this
modem is tested for BER of 10-4 at
another RF signal level, this will require
120,000 bits for the same statistical test
significance and the test time will zoom to
over 100 seconds!

0.1

0.01

. .

_-~.:=_

I

'-~ ~~~+.

.:l 0.001

,"

X

PO 0001
~:
.
:'1
~

~i 1 =-05

What happens to BER as RF levels
are varied? The result of comparative
E-06
testing performed with an MX439 and a
typical Bell 202 IC modem installed in a
,
typical UHF receiver is shown in Figure 6.
10-07
-118 -117 -116
-115 -114
- 120 ·-119
-122
121
With a signal of -117dBm (0.3J.1.v) the
Ill" Signal Level (dBrn)
4
MX439 delivers a BER of about 1 x 10
compared to the Bell 202 units about 1 x
Figure 6 - Bit Error Performance
10-3 • MSKs inherent narrower bandwidth ' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
allows filtering to remove more noise than the Bell FSK modem. This results in fewer bit errors.

Synchronous vs. Asynchronous Data
Data transmission systems are designed to operate with either synchronous or asynchronous serial data formats.
In a synchronous system, each bit is clocked in synchronism with the system master clock. The synchronizing signal
may be embedded in the data signal or provided on a separate clock line. In addition, synchronous transmission
requires the use of frame sync preamble to allow the receiver to determine the beginning and end of blocks of data.
This is achieved in MSK synchronous modems by encoding a preamble of 1-0-1-0 transitions (16 bits by
convention), allowing receiving stations time to lock onto the edges of the received data. This is done in MX·COM
modems with a digital PLL that controls a frequency divider incremented in 1/28th bit steps. A misaligned worst-case
signal may take as many as 14 bit times to lock. Lacking edges on which to lock, the DPLL free runs at 1200 bps.
In asynchronous systems, each character (or word) consists of a "start bif' that starts the receiver clock and
concludes with a "stop bit" that terminates the clocking. Typically, slower wireline modems use asynchronous
modulation while fast ones are synchronous. All benefit from a great deal of handshaking, and smart ones default to
slower speeds when the going gets tough.
FM Mobile radio is characterized by noise and fading, over a few short hops. Wirelines have noise, but little fading
carrier
De1ect

I
Figure 7 - MSK Receiver Block Diagram
MX-COM, INC.

Page 565

and fewer hops. These introduce group delay and isochronous distortion or jitter -- a source of difficulty for
synchronization and high Bit Error Rates (BER).
Forward Error Correction (FEC) functions best with synchronous data streams. If any single bit is corrupted, all
other bits stay in position and FEC can act to correct the bit error. In asynchronous data streams, any "start" corrupted
bit will result in offsetting all subsequent data bits, rendering the FEC useless.

Detecting Data Carriers in Wireline vs. Wireless
Data carrier detection methods vary depending on the transmission media characteristics. Wireline modem data
carrier detectors look for broadband energy. Detectors can differentiate between white noise and signal. But wireless
data carrier detection, as in the MX439, looks for a level differential between the energy in the data passband and the
energy at the MSK first null point (2400HZ). That's because the output of unsquelched RF discriminator is
characterized by high levels of broadband white noise which wireline broadband detectors will not be able to
differentiate from signal. The cirCUitry in the MX439 is a pair of envelope detectors looking for a signature characteristic
of MSK data.
One of the application problems of any carrier detection technique is trading off response time for false alarms.
The value ofthe detector integration capacitor shown
0.1 I
on the data sheet is 0.1 ufo Naturally, it plays an
important role in determining detector response
time, but also affects the false alarm rate. Increasing
]
.!'J!
the capacitor value, decreases the false alarm rate
[f)
but increases the time to detect the carrier. The level
~
~
0.01
of the noise which drives the detectors also controls
the false alarm rate. Care must be taken not to
saturate the filters in the MX439 or provide too low
of a level. In the particular receiver used for our
tests, RMS levels of unsquelched noise were twice
'0 0.001
that of data (data @ 3kHz deviation). The result of
substituting other values of integration capacitors is
shown in Figure 8. The MX439's data carrier detect
threshold is 125 mVrms. For best operation noise
I
0.000 1
should be kept in the 250 to 400 mVrms range.
650 600 550 500 450 400 350 300 250 200
Some RF receivers may require a pad or attenuator
Inpul Noise Level in rniIIivolls
to provide this optimum detection level. Another
Figure 8 - Fa/se Alarm Rates
option might be to adjust the Q of the radio receiver's
quadrature detector coil to establish the desired
recovered audio level that way.

~--l--L_O. .1'f"'IiF~
.

]

A by-product of increasing the size of the
capacitor on the carrier detector pin is chatter or
multiple edges in the carrier detector output. As the
detected data signal appears at the carrier detect
time constant pin, there is a much slower rise time
due to the increased size of the time constant
capacitor. As this signal has some of the detected
audio components present, it causes multiple edges
on the leading edge of the carrier detect output as
the signal passes through the threshold point of the
comparator.

I

[
Oinier Detect Time 0Jrstart
OA7UF

Modems working in concert with microprocessors may be able to overcome this with software by
O.047UF
multiple samples over time of the carrier detect
signal. An alternative is to add an inverter to the
output of the carrier detector and apply positive
Figure 9 - Adding Hysteresis
feedback at the carrier detector time constant pin to
accomplish a Schmidt trigger effect. This is shown in Figure 9. Capacitive feedback was selected instead of resistive
feedback because capacitor feedback is easier to control in this application.
Page 566

MX-COM, INC.

Using an MSK Synchronous Modem
with an Asynchronous Data 1/0
By Bud Simciak

Asynchronous Modem Circuitry
This application note, used with current MX439/MX469 product information, outlines the construction of a lowcost asynchronous modem for the transmission of RS-232 data in the form of Minimum Shift Keying (MSK), between
terminals by a radio or line medium (see page 157-170 for MX439/469 information).
The modem circuitry shown in Figure 1 accepts asynchronous data while transmitting synchronous data using
the MX439/469 series modem. The MX469 may be used to transmit data at either 1200 or 2400 bps, depending on
the setting of Switch 1 shown in Figure 1. The MX439 always transmits data at 1200 bps. Switch 1 must be set in
position A to use the MX439. The chart below details the devices used in this application.

RS-232 Driver/Receiver Level Translator
Async to Sync,
Sync to Async Conversion
Data Carrier Detection
Controlled RTS/CTS Delay
Generation of MSK Signals
Reception of MSK Signals
Interface into Radio System
RS-232 Handshake

Maxim MAX-232
Exar XR-2135 or Sipex MAS7838
MXoCOM MX439/469
74HC04 Delay Element
MX·COM MX439/469
MX·COM MX439/469
MX·COM MX439/469
Misc Circuitry

The signals required for an RS-232 handshake for asynchronous data are as follows. A complete definition of
each is given at the end of this application note.
DTR
DSR
RTS
CTS
TXD
RXD

Data Terminal Ready
Data Set Ready
Request to Send
Clear to Send
Transmit Data
Receive Data

The Maxim MAX-232 converts the TTUCOMS input/output levels to ±1 OV RS-232 input/output levels. On powerup, the data set ready (DSR) signal is set by the MAX-232's DC to DC converter. The incoming data terminal ready
(DTR) signal enables the transmitter keying signal.
The request to send (RTS) and clear to send (CTS) signals are level shifted from the RS-232 interface to TTU
CMOS signal levels. When the modem receives an RTS, the RF transmitter and the MSK tone are keyed immediately
and a 30 ms to 100 ms timer is started. At the completion of the timing, a CTS signal is generated for the data terminal
to allow serial data flow.
The transmit data (TXD) signal is level shifted to the TTUCMOS levels, and applied to the Exar 2135 sync to
async converter circuit. The random timed asynchronous input from the data terminal is synchronized with the transmit
clock pulses of the MX439/469. If a timing error builds up due to the difference of the external asynchronous clock
and the synchronous internal timing on the modem, the XR-2135 will skip a stop pulse to allow an adjustment to occur.
The receiving end XR-2135 will generate a stop pulse and add it into the data flow so that no information is lost.
From the sync to async convertor, synchronous information is then sent into the MX439/469, which converts the
digital '1' into one cycle of 1200 Hz sinewave and a digital '0' into one and a half cycles of 1800 Hz sinewave for 1200 bps
and 1200 and 2400 Hz for 2400 bps. This sinewave is then sent on the transmitter through a level adjustment. The
MX-COM, INC.

Page 567

I

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MX469J

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NOTES:

D2

1 . PTT LOW TO TRANSMIT
lN4148

2. SQUELCH HIGH WITH SIGNAL
3. XR~2135 BITl & BIT2 SELECT

RIO

••

I RXAUOIO

P3

lDK

10K

-=-

LENGTH OF ASYNC CHARACTER.

PIT
I

P4

L _____~ __ I

DATA BITS

BIT 1 BIT2

6
7
8

0
0
1

0
1
0

9

1

1

+12V

C4

I';:

ONE STOP AND ONE START
BIT WITH EACH GROUP OF

~

DATA BITS.

8

.:s:
~

I Figure 1 -

Schematic Diagram of an MX4391469 in a Typical Application

y,

r

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OOPF
.~"'"

~
~
~

Sl Settings:
Sl~A = 1200 bps. MX439/469
S1~B =240D bps. MX469 only

signal is sufficiently band limited and level controlled to pass FCC type acceptance testing without any additional inband filtering.
The incoming receiver signal is fed into the MX439/469 which is held in a power down mode until an RF carrier
is detected by the receiver squelch circuitry. This minimizes power drain and also prohibits false information from being
sent to the data terminal. If the receiver does not have a noise squelch signal, the chip's carrier detect must be used.
It will detect within 12 ms the presence of the data modulation tone. This event is output on the carrier detect pin which
should be used to disable the data output to minimize random data at the terminal. The use of the Schmidt trigger
circuitry would minimize the 'clatter' at the beginning of the detection signal.
The tones are translated into logic levels and a digital phase lock loop is locked onto the incoming data steam
within 16 bit reversals. The detected synchronous data and the recovered receive clock are sent into the XR-2135
for conversion back into asynchronous data. This information is then sent out to the data terminal through the Maxim
MAX-232.
Operation in either a synchronous or asynchronous mode is achieved with a jumper. If additional RS-232 level
shifting is needed for transmit and receive clocks and TX and RX enable, pins on the XR-2135 are brought low. Bringing
these pins low bypasses the conversion process and allows synchronous data to pass directly through the device.
Proper clock frequency for the MX439 device is provided by a 4.032 MHz crystal. Clock frequency for the XR2135 must be provided at 256 times the bit rate. This is accomplished by using a 2.4576 MHz crystal and dividing down
by eight to 301.2 kHz (1200 bps) or by four to 602.4 kHz (2400 bps). Power is derived from a single 7805 voltage
regulator. DC current measured on the first model is 12.75 mAo

Software Considerations
As with many data systems, there are certain items that should be addressed within software for proper operation.
These items are:
Bit Sync Pattern
Bit Sync Time
Noise Bits at End of Transmission
Since the MSK modem is a synchronous device, a pattern must be transmitted at the beginning of each RF burst
to allow the DPLL sufficient time and data transitions (a change from a one to a zero or a change from a zero to a one)
to synchronize. The device requires at least sixteen of these transitions for sync to occur. This may be accomplished
by appending two bytes of $55 or $AA onto the message. Once this is accomplished, adding a beginning of text
character and an end of text character would ensure a correct decode at the receiving end. This is especially true at
the end of the transmission. Once the RF signal ends, high level noise will be emitted from the receiver. Even if the
data carrier detect or the noise squelch signals are used to gate the data off, there will be a period of noise while these
circuits are making their decision. It is this random data which many times will cause a programmable logic controller
or point of sale terminal to lock up. Having the message bracketed and only dealing with the information between the
start and stop characters is one method of prohibiting random data from entering the actual message.

Operation with CTCSS or DCS Sub-Carriers
Because the MX439/469 modems contain a bandpass filter on the input, CTCS/DCS sub-carriers are filtered out
without extra circuitry.
It is important that no energy from the tone section appears within the transmitted data signal passband of 900
to 2100 Hz for 1200 bps or 600 to 3000 Hz for 2400 bps. It is equally important that the tone and data signals are not
summed together and sent into the limiter section of the transmitter. The limiter represents a nonlinearity and would
generate intermodulation products within the data bandpass which when received generate errors in the decoding of
the data. Tone is normally summed into an FM transmitter after the limiting.
Radios designed only for data do not require a speech limiter, allowing tone and data to be summed directly.

MX-COM, INC.

Page 569

I

RS-232 Handshake
The RS-232 handshake for asynchronous data requires the following signals:
Data Terminal Ready is a signal from the terminal or computer that indicates to the modem that the unit is
powered and active. An RF transmission should not be enabled if the Data Terminal is not active.
Data Set Ready is a signal from the modem that indicates to the terminal that the unit is powered and active.
Many terminals or computers will not allow data to flow without this condition being true.
Request to Send emanates from the terminal or computer. The software or user has decided that transmission
should begin and requests that the RF carrier be turned on.
Clear to Send is a signal that originates from the modem. It is sent in response to a RTS, the request to send
signal from the terminal or computer after certain criteria have been met. It is not sent until sufficient time has expired
after the transmitter keyed to allow adequate settling time for both the RF transmitter and receiver. It would not be
sent if there is an RF carrier on the channel indicating another user. Finally, it would not be sent if a high VSWR were
detected on the transmitter when it was keyed. (Not all transmitters are provided with a VSWR detector.)
Transmit Data and Receive Data is the actual asynchronous data flow. Transmit data is data coming from the
terminal and Receive data is data flowing into the terminal.
Another term often heard is DTE and DCE ends of RS-232. This refers to what part of the handshake is expected
and what the functions of the RS-232 connectors would be. Most often a computer would be programmed to be a DTE
or data terminal end of the information flow. When one computer wishes to talk to another computer, it's like two people
transmitting on their radios at the same time. Nobody hears the other! If one were to use a 'null' modem cable, the
wires are interchanged such that one of the data terminals is now wired like a data communication device. The same
is true of two modem devices. A modem device is a DCE (data communication device) which cannot be plugged into
another DCE. However, if a few additional signals are available, one DCE could be used to daisy chain into another
DCE as shown in Figure 2. As can be seen the data carrier detect lines are used to key the companion modem unit.
The originating end must be programmed with sufficient delay to allow the RTS/CTS delay of the modems to occur
prior to the beginning of any information transfer.

DaIa Set Ready

DaIa Set Ready

Data Terrrinal Ready

DaIa Terrrinal Ready
AequestloSerd
OearloSerd
Transrrit DaIa

ReceilieData
Data Garrier Detect

DeE Device

I

/
~

/

r

\
\
\

\

Request 10 Serd

OearloSerd
Transrrit DaIa

ReceiwData
Data camer DeIecI

DeE Device

Figure 2 - Modem Interconnect

Page 570

MX-COM, INC.

Error Detection & Correction of MPT1327
Formatted Messages
using MX419, MX429, MX439, MX469, MX489 or MX809 devices
by Pam Roberts

1.1 Background
MPT1327 messages are transmitted as 64-bit 'codewords', where each codeword contains 48 information bits
followed by 16 check bits:
~~:

~

information field

~

M

check bits

(Bit number 1 is transmitted first.)
These check bits allow the receive terminal to detect all odd numbers of errors, any 2 or 4 errors, and any errorburst up to length 16 in a codeword, and also to correct errors in the received codeword, although it should be
noted that the higher the degree of error correction applied, the more likely is false decoding.
This document gives algorithms for:
Generation of the check bits of a transmitted codeword.
Received codeword error detection.
Limited error correction of a received codeword.
These algorithms may be used with any bit or byte oriented modem, such as the MX419, 429, 439, 469, 489 or
809, although the MX429 and MX809 devices can perform check bit generation and error detection automatically
and the MX429 also provides a 16-bit 'Syndrome' output which may be used to aid error correction.

1.2 Generation of Transmit Codeword Check Bits
The first 15 check bits are derived from a (63,48) cyclic code by using codeword bits 1 to 48 as the
coefficients X62 to X 15 (in that order) of a 63 bit polynomial, which is then divided modulo-2 by the generating polynomial;
(1110100000010101 binary)
On completion of the division, the 15 coefficients X14 to XO of the remainder are used as the first 15 check
bits (codeword bits 49 to 63), with the XO coefficient (bit 63 of the complete codeword) inverted.
Finally, bit 64 of the codeword is added to provide an even parity check of the whole 64-bit codeword.

MX-COM, INC.

Page 571

I

1.2.2

Example of Transmit Codeword Generation

Information field; 6 data bytes
89

AB

CD

EF

12

34

10001001 10101011 11001101 11101111 00010010 00110100

Hex
Binary

Polynomial division

x62

••••••••••••••••••••••••••••••••••••••••.•••••••••••••••••••••••

10001001
11101000
1100001
1110100
10101
11101
1000
1110
110
111
1
1

10101011
00010101
10111110
00001010
10110100
00000010
10110110
10000001
00110111
010QOOOO
01110111
11010000
10100111
11101000
1001111
1110100
111011
111010
1
1

xO

11001101 11101111 00010010 00110100 00000000 0000000
1
1
010
101
1110
0101
10111
10101
0001010
0010101
00111111
00010101
00101010
00001010
00100000
00000101
00100101
11010000
11110101
111010QQ
11101
11101

1
1
01
01
0010111
0010101
00000101
Q0010101
00010000
00000010
10010
11101
1111
1110
1
1

000
101
10110010
00000010
10110000
10000001
00110001
1101000Q
11100001
11101000
1001
1110
111
111

001
101
1001
0101
1100010
0010101
11101110
00010101
11111011
10000001
01111010
01000000
111010
111010

0000
0101
01010
10101
11111000 00
00000101 01
11111101 0100000

Remainder with last bit inverted:
11111101 0100001

I

Complete COdeword, including parity bit:
64
Bit; 1
10001001 10101011 11001101 11101111 00010010 00110100 11111101 01000010
FD
42
89
AB
CD
EF
12
34

Page 572

MX-COM, INC.

1.2.3

'C' Language Algorithm

/***************************************************************************/

/*
/*
/*
/*
/*

Function gen_ckbits() returns the first 15 check bits of a transmit
codeword (codeword bits 49 to 63). Bit 15 of the returned value will
be codeword bit 49, bit 1 of the returned value will be codeword bit
63, and the lsb (bit 0) should be ignored.
The last bit (64) of the codeword must be derived separately, to
give even parity of the whole 64-bit codeword.

/*

*/
*/
*/
*/
*/
*/

gen_ckbits ()
{

int n,bit;
unsigned int ckbits = 0;
for(n=1;n <= 48;n++)
{

bit
getbit_tx(n);
if( 1 & (bit
(ckbits »
A

ckbits

Ox6815;

A

ckbits «= 1;

return(ckbits

/*
/*

A

Ox0002);

15»)

/* Clear check bits
*/
/* 48 information bits ...... */
/*
*/
/* Get each bit in turn ... */
/*
XOR tx bit with MSB */
of checkbits and if */
/*
the result -- 1
*/
/*
then XOR checkbits
*/
/*
with 6815 Hex
*/
/*
Shift check bit word */
/*
*/
/*
one bit left,
*/
/* Return checkbits with
/* codeword bit 63 inverted */

Function getbit_tx(n) should return bit 'n'
codeword information field.

(1 to 48) of the transmit*/
*/

getbit_tx(n)
{

return(/* 1 or 0 */);
}

I
MX-COM, INC.

Page 573

1.3 Receive Codeword Checking & Error Correction
1.3.1

Theory
The parity of the received 64-bit codeword is checked, then bit 63 of the codeword is inverted. The first 63 bits of
the resulting codeword are then used as the coefficients X77 to X15 of a 77 bit polynomial, which is then divided
modul0-2 by the 'generating polynomial'. If the remainder is zero, and the parity check is met, then no errors have
been detected.

The 15-bit remainder of this division is used as the least significant 15 bits of the 16-bit 'Syndrome' word generated by the MX429 (and by the algorithm of section 3.4), while the msb of the Syndrome word is set to '1' if the
parity of the received codeword is incorrect. The resulting Syndrome word value can give an indication of which
bit(s) of the codeword have been received incorrectly; see section 3.4.
1.3.2 Example of Receive Codeword Checking: No Errors
Received codeword: 6 bytes:
89

AB

CD

EF

12

34

FD

42

10001001 10101011 11001101 11101111 00010010 00110100 11111101 01000010
Bit;l
64

Step 1: even parity checked OK
Step 2: invert bit 63 then divide first 63 bits (shifted left 15 places) by generating polynomial:
x 77 • . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . • . . • . . . • . . • . . . . . • . . • . . . . . . xO
10001001
11101000
1100001
1110100
10101
11101
1000
1110
110
111
1
1

10101011
00010101
10111110
00001010
10110100
00000010
10110110
10000001
00110111
01000000
01110111
11010000
10100111
11101000
1001111
1110100
111011
111010
1
1

11001101 11101111 00010010 00110100 11111101 01000000 00000000 000000
1
1
010
101
1110
0101
10111
10101
0001010
0010101
00111111
00010101
00101010
00001010
00100000
00000101
00100101
11010000
11110101
11101000
11101
11101

I
Remainder =zero
MX429 'Syndrome' word:
No errors detected

Page 574

1
1
01
01
0010111
0010101
00000101
00010101
00010000
00000010
10010
11101
1111
1110
1
1

000
101
10110010
00000010
10110000
10000001
00110001
11010000
11100001
11101000
1001
1110
111
111

001
101
1001
0101
1100010
0010101
11101110
00010101
11111011
10000001
01111010
01000000
111010
111010
000000

1111
0101
10101
10101
00000101 01
00000101 01
00000000 00000000 00000000 000000

00000000 00000000

MX-COM, INC.

1.3.3

Example of Receive Codeword Checking: 2 Errors

Received codeword: 6 bytes: bits 9 & 10 in error
89
6B
CD
EF
12
34
FD
42
10001001 01101011 11001101 11101111 00010010 00110100 11111101 01000010

errors; xx
64

Bit;l
Step 1: even parity checked OK
Step 2: invert bit 63 then divide first 63 bits (shifted left 15 places) by generating polynomial:

x77

. . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . xO

10001001
11101000
1100001
1110100
10101
11101
1000
1110
110
111
1
1

01101011
00010101
01111110
00001010
01110100
00000010
01110110
10000001
11110111
01000000
10110111
11010000
1100111
1110100
10011
11101
1110
1110

MX-COM, INC.

11001101 11101111 00010010 00110100 11111101 01000000 00000000 000000
1
1
010
101
1110
0101
10111
10101
0001010
0010101
00111111
00001010
00110101
00000010
00110111
10000001
10110110
11101000
1011110
1110100
101010
111010
10000
11101
1101
1110
11
11

1
1
011
101
1100
0101
10011111
00010101
10001010
00001010
10000000
00000101
10000101
00000010
10000111
10000001
00000110
10100000
10100110
11101000
1001110
1110100
111010
111010

0
1
10
01
110
101
0111
0101
001000
010101
01110110
00010101
01100011
00001010
01101001
00000101
1101100
1110100
11000
11101
101
111
10
11
1
1

0
1
10
01
11110100
00001010
11111110
00000010
11111100
01000000
10111100
10100000
00011100
11010000
11001100
11101000
100100
111010
11110
11101
11
11

1
1
011
101
11011
10101
011101
010101
0010000
0010101
00001011
00010101
00011110
00000101
00011011
00000010
00011001
10100000

I

01
01
000
101
101000
010101

Page 575

10111001
111010QO
1010001
11101QO
100101
111010
11111
11101
10
11
1
1

11110100
000101Q1
11100001
00001010
11101011
00000101
11101110
QOOOO010
11101100
101000QO
01001100
11010000
10011100
111Q1QQO
1110100
111Q100

0
1
10
Q1
110
101
011000
Q10101
0011010
0010101
00011110
Q001Q101
00001011 0
00001010 1

Remainder; non zero
1 100000
MX429 'Syndrome' word:

00000000 01100000

Therefore, from the table in section 3.4, codeword bits 9 & 10 of the received codeword are incorrect.

I
Page 576

MX-COM, INC.

1.3.4

'C' Language Algorithm

The following algorithm produces a 16-bit 'Syndrome'similar to that generated by the MX429, which will have a
value of zero only if no errors have been detected in the received codeword.
/***************************************************************************/

/*
/*

Function calc_syndrome() returns the 16-bit 'Syndrome' of a received */
MPT1327 64-bit codeword.
*/

ca1c_syndrome()
{

int n,bit;
int parity=O;
int syndrome=O;
for(n = l;n <= 64;n++)
{

bit = getbit_rx(n);
parity ~= bit;
if(n == 63) bit ~= 1;
if(n < 64)
{

syndrome «= 1;
if( 1 & (bit ~ (syndrome »

syndrome

~

syndrome &= Ox7FFF;
if (parity)
syndrome 1= Ox8000;
return(syndrome);

Ox6815;

15)))

/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*

Clear parity register
Clear 16-bit syndrome
64-bit codeword ...

*/
*/
*/
*/

Get each bit in turn; ..
*/
update parity
*/
then invert bit 63
*/
for bits 1 to 63; .... */
shift parity word */
one bit left.
*/
XOR rx bit with
*/
MSB of parity word,*/
and if result == 1 */
then XOR syndrome */
with 6815 Hex.
*/
/*
*/
/* Finally, replace MSB of
/* syndrome word with the
/* calculated parity bit

*/
*/
*/

}

*/
Function getbit_rx(n) should return the bit 'n' of the received
codeword; Bit '1' is the first bit to be received, bit '64' the last.*/

/*

/*

getbit_rx(n)
{

return(/* 1 or 0 */);
}

I
MX-COM, INC.

Page 577

1.4 Error Correction
Single-bit and bit-pair errors in a received codeword may be corrected by comparing the 'Syndrome' word (generated by the MX429 or the algorithm of section 3.4) against the entries in the following table, and if a match is
found inverting the corresponding bits.
Syndrome
(Hex)
0003
0006
OOOC
0018
0030
0060
OOCO
0180
0300
0600
OCOO
15D3
1763
1800
18CD
193B
1E1B
21CD
220B
2867
2BA6
2D31
2E7D
2EC6
3000
3149
319A
3276
3657
3C36
439A
4416

Error
bits
14, 15
13, 14
12, 13
11, 12
10, 11
9, 10
8,
9
7,
8
6,
7
5,
6
4,
5
43, 44
20, 21
3,
4
28, 29
59, 60
31, 32
56, 57
38, 39
35, 36
42, 4~
49, 56
25, 26
19, 20
2,
3
51, 52
27, 28
58, 59
53, 54
30, 31
55, 56
37, 38

Syndrome
(Hex)
468D
4841
4989
4B7B
4BD7
4EOF
502A
50CE
51B7
51E1
530D
574C
5A62
5CD1
5CFA
5D8C
6000
6039
6292
6334
64EC
650F
6815
6CAE
6F21
740B
786C
7897
7B07
7EE3
7FBB
8000

Error
bits
40, 41
61, 62
33, 34
45, 46
22, 23
16, 17
62, 63
34, 35
46, 47
23, 24
17, 18
41, 42
48, 49
47, 48
24, 25
18, 19
1,
2
36, 37
50, 51
26, 27
57, 58
39, 40
63, 64
52, 53
54, 55
15, 16
29, 30
60, 61
32, 33
44, 45
21, 22
64

Syndrome
(Hex)
8001
8002
8004
8008
8010
8020
8040
8080
8100
8200
8400
8800
88E9
8A09
8CB1
8D21
9000
90C7
91D2
9412
9962
9A2B
9A42
AOOO
A017
A18E
A305
A3A4
A51F
A824
B2C4
B44F

Error
bits
15
14
13
12
11

10
9
8
7
6
5
4
60
32
44
21
3
52
59
31
43
26
20
2
37
51
40
58
55
30
42
48

Syndrome
(Hex)
B456
B484
B83F
B887
B929
B94D
BA05
COOO
C02E
C31C
C60A
C748
C885
CA3E
D048
E401
E588
E685
E815
E849
E89E
E8AC
E908
EE2D
F07E
FlOE
F252
F29A
F40A
F91F
FC69

Error
bits
25
19
62
34
46
23
17
1
36
50
39
57
28
54
29
38
41
56
63
35
47
24
18
49
61
33
45
22
16
27
53

Example:
Transmitted COdeword:
Bit; 1
64
10001001 10101011 11001101 11101111 00010010 00110100 11111101 01000010
errors; xx
Received codeword:
10001001 01101011 11001101 11101111 00010010 00110100 11111101 01000010

I

For this received codeword, the 'Syndrome' will be 0060H, which appears in the table, indicating that the 9th &
10th bits received are incorrect and should be inverted.

Page 578

MX-GOM, INC.

II

GMSK for High Speed Wireless Modems

II

By Bud Simciak and Sam Rizk

I. Introduction
FCC regulations limit the spectral emissions of mobile FM radio transmissions. These regulations state that outof-band radiated power in adjacent channels should be generally bounded 60-80 dB below that in the desired channel,
as shown in Figure 1. To meet these constraints, it is necessary to band-limit the RF output signal spectrum. The RF
power spectrum envelope is easier to control via the intermediate-frequency (IF) or the baseband rather than the final
RF stage because the transmitted power is variable. Gaussian filtered MSK (applied to the baseband, i.e. premodulation) yields a constant envelope, facilitating FCC compliance.

0

I

"0

§
::I

10

E
e

20

I
I
I
I

"0
0

::I

GI

:5

.2

30

~
.Q

40

\

\
\
\
\

I
II

~.~

-

-

Thelesserof50+1010gPd
or70dB

1\

\
\
\

I

70

-

-

-15+le" Id" 15+fc
157[og (fdl5.3)

I
I

60

-

-9.5+le < Id < +9.5+lc kHz
103 log (ld/3.9)

I

::1-

:li!8

I

1

\
\

I

50

.-~

=a B

[

1

fd <: 15kHz

ID

e
lD
e0"0

I

1

-6-25+le < Id " +6.25+lc
53 log (ld/2.5)

!!

"0

I
_I

-

Pd = Power (Watts)
Id = displacement Ireq. lrom
the carrier, Ie, in kHz

-

\

80
-50

-40

-30

-20

-10

Fe

+10

+20

+30

+40

+50
fd (kHz)

Figure 1 - Out-ot-band Emission Attenuation Data Input [2J

II. What is GMSK?
GMSK uses a premodulation low-pass filter with a Gaussian (be"-shaped) characteristic to smooth out the symbol
edges, narrowing the spectral bandwidth of the baseband data signal. The filtered symbol is then applied to the MSK
modulator as shown in Figure 2 [1]. MSK is a binary digital frequency modulation technique with a modulation index
of 0.5.
Modulated
Carrier

I

Premodulation
Gaussian
Filter

I

FM(MSK)
Transmitter

~

TX Data
Input

Figure 2 - A Typical GMSK Transmitter
MX-COM, INC.

Page 579

III. GMSK Power Spectral Density (PSD)
The GMSK output power spectrum is more compact than that of MSK, as shown in the following graphs.

i

o .

-o-r----+----t.---.-,--~
I
I

~

I

•

BbT'
:

... ~ --1.0

-20

:

; 0.1

.

iii"

99.8

i

··t-----..-t----r::-:f...
~

l

..

~

~

I

III

·_·-1····--·. _·_-

99.6

~ -40
~

J

99.4

-60

I:

o

-so

....

-loa
-120

L -_ _

o

~

_ __'__ _

0.5

1.0

~__'~_.I.>__'__...J

I
-···+..·..·..--_··..t-···-_·
i

!!

.__. ..1_._

99.2

_. . .--!

99.0

---+- .Hi'-tl-ft+--·-t-·---·_-·_·t····_-

!

1

1.0

I

V'-ED!
::

I

!

i

I.S

Z.O

98. 8 L _ _.L.....Ll.J.LUl:ll..L....---::'-:-----::'":---~. s

l. S

2.0

1.5

..

0.Z5
t::""::\
~-.

"iii

~'"

i

O~.IZ6
......__........- . ..

o

Normalized Frequency: (f-fclT

0.5

1.0

G.

Normalized Bandwidth: BiT

This figure shows Power Spectral Density versus the
normalized frequency difference from the carrier center frequency (f-fc)T, where the normalized 3 dB bandwidth of the premodulation Gaussian LPF (BT) is a
parameter.

This figure shows the fractional power in the desired
channel versus the normalized bandwidth of the LPF
(BT).

Figure 3 - Power Spectra of GMSK [1J

Figure 4 - Fractional Power Ratio of GMSK [1J

Or---~--~--~~--~--~
Bb T :

-@D

I

"\"\,~~~_ _,l. 0 ____.._ ...1___._._

-zo
._._--..

~

_---.i --i

This figure shows the out-of-band
radiation power in the adjacent
channel to the total power in the
desired channel where the normalized channel spacing (fsT) is
a parameter.

I'

··-·······-····T---o:2s

i

I

-·-··--···-·l··--······-·--j

-80

f

l !

----·-·-l--·---;

-lao

I

I

I

--t- --

I

-120 '--_ _~ _ _-'-_ ____''"__l_._..A__~_l

o

0.5

1.0

1.5

z.o

2.5

Normalized Channel Separation: fsT

Figure 5 - GMSK Adjacent Power Interference [1J
Page 580

MX-COM, ING.

IV. GMSK Demodulator
Figure 6 shows a typical GMSK receiver block diagram. The received RF modulated carrier is down-converted
in multiple stages. The output of the last stage is usually centered at an intermediate frequency (IF) of 455 kHz. The
modulated IF carrier is applied to a bandpass filter. The filtered signal is then applied to an amplitude limiter and the
output is applied to a conventional frequency discriminator. The discriminator output is passed through the premodulation filter and timing recovery subsystem. The data detector processes the analog waveform in order to decide which
bit has been transmitted.

900 MHz Input

Received
Data

Figure 6 - Functional Block Diagram of a GMSK Receiver

V. Bit Error Rate (BER)
The reliability of the data message produced by the GMSK receiver is highly dependent on the following:
1. Receiver thermal noise: this is introduced partly by the receive antenna and mostly by the radio receiver
front end.
2. Channel fading: This is caused by the multipath propagation nature of the radio channel.
3. Bandlimiting: This is mostly associated with the receiver IF frequency and phase characteristics.
4. DC drifts: may be caused by a number of factors such as temperature variations, asymmetry of the
frequency response of the receiver, frequency drifts of the receiver local oscillator.
5. Frequency offset: this refers to the receiver carrier frequency drift relative to the frequency transmitted
caused by the finite stability of all the frequency sources in the receiver. The shift is also caused partly by
Doppler shifts which result due to the relative transmitter/receiver motion. The frequency offset causes the
received IF signal to be off-center with respect to the IF filter response, and this causes more signal
distortion. The frequency offset also results in a proportional DC component at the discriminator output.
6. Timing errors: The timing reference causes the sampling instants to be offset from the center of the transmit
eye.
Figures 7 & a [2] show the theoretical BER performance of GMSK, with the receiver frequency offset as a
parameter and IF filter responses of non-equalized and phase equalized a-pole Butterworth, respectively.

I
MX-COM, INC.

Page 581

fc Offset
==
l.OOE+oom~~~
. . • • . 15OOHz1000Hz
·-·-·500Hz
l.OOE'()1

=

~~~~~~~§~§.~~~OH~Z~~~

fcOffset
1.00E+OOm~~g
. • . . • 1500Hz
- - - 1000Hz
·_·_·500Hz

1.00E'()1

I~I~I~~~~~~~~~O~H~Z~

\

l.OOE.()5~~~
\
l.OOE{)6

+--+--1------11----+--\---+--+---1
10

11

12

13

14

15

16

17

18

I.OOE{)6

+--+--t--I------1---+---I'L----f----j
10

11

12

SIN (dB)

Figure 7 - Theoretical Bit Error Rate Performance,
with Carrier Frequency Error as a Parameter [2]

13

14

15

16

17

18

SIN (dB)

Figure 8 - Theoretical Bit Error Rate Performance,
with Carrier Frequency Error as a Parameter [2]

VI. MX·COM GMSK Modem IC's
For optimum performance, the received signal applied to the MX589 for random transmitted data should be as
close as possible to the eye diagrams shown in Figure 9. The eye diagram is a measure of the Inter-Symbol-Interference
(lSI) caused by channel filtering. Of particular importance are general symmetry, cleanliness of the zero crossings, and
- for a BT of 0.3 - the relative amplitude of the inner eye opening.
To achieve this, attention must be paid to:
- Linearity and frequency/phase response of the TX frequency modulator. Unless the transmit data is especially
encoded to remove low frequency components, the modulator frequency response should extend down to a
few Hz, two-point modulation being necessary for synthesized radios.
- Bandwidth and phase response of the RX IF filters.
- Accuracy of the TX and RX carrier frequencies, as any difference will shift the received signal towards one of
the skirts of the IF filter response.
Ideally the RX demodulator should be DC coupled to the MX589 RX Signal In pin (with a DC bias added to center the
signal around V or!2), however AC coupling can be used if the following is true:
- The 3 dB cut-off frequency is 20 Hz or below (Le. a 0.1 IlF capacitor in series with 100kQ).

I

- The data does not contain long sequences of consecutive ones or zeroes.
- Sufficient time is allowed after a step change at the discriminator output (resulting from channel changing or
the appearance of an RF carrier) for the voltage into the MX589 to settle before the RXDCacq line is strobed.

Page 582

MX-COM, INC.

VII. Data Formats
The receive section of the MX589 works best with data which has a reasonably 'random' structure -the data
should contain approximately the same number of 'ones' as 'zeroes' with no long sequences (> 100 bits) of consecutive
'ones' or 'zeroes'.
Several techniques have been devised to randomize the data [5]. For example, a common method is 'exclusiveORing' it with the output of a binary pseudo-random pattern generator.
Where data is transmitted in bursts, each burst should be preceded by a preamble designed to allow the receive
modem to establish timing and level lock as quickly as possible. This preamble for BT=0.3 should be at least 16 bits
long, and should preferably consist of alternating pairs of '1's and 'O's i.e. '110011001100 .... .'; the eye of pattern
'10101010 ... .' has the most gradual slope and will yield poor peak levels for the RX circuits. For BT=0.5 the eye pattern
of '10101010 .. .' has less intersymbol interference (DC Acq pin should be held high during preamble) and may be used
as the preamble (see Figure 9).

BT

V

0.3

0.5

o

o

-0.5 '-----'=___=-___-==-_=-_

V

BT = 0.5

0.5

C>"--------.,=-------:::

o

-0.5

--==

-..:::=-_ _ _ _ _

t::::-_ _ _ _ _

Figure 9 -- Voltages with respect to Vod2

VIII. Acquisition & Hold Modes
The RXDCacq and PLLacq inputs must be held "high" for about 16 bit-times at the start of reception to ensure that
the DC measurement and Timing Extraction circuits lock onto the received signal correctly. Once lock has been
achieved, then the inputs should be taken "low" again.
In most applications, there will be a DC step in the output voltage from the receiver FM discriminator due to carrier
frequency offsets as channels are changed or when the distant transmitter is turned on. The MX589 can tolerate DC
offsets in the received signal of at least ±0.5V with respect to V BIAS' However to ensure that the DC offset compensation
circuit operates correctly and with minimum delay, the "low" to "high" transition of the RXDCacq and PLLacq inputs
should occur after the mean input voltage to the MX589 has settled to within about 0.1V of its final value. (Note that this
can place restrictions on the value of any series signal coupling capacitor.)
The RXHold input may be usued to freeze the Level Measuring and Clock Extraction circuits during a fade. It may
also be used in systems which employ a continuously transmitting control channel to freeze the receive circuitry during
transmission of a data packet, allowing reception to resume afterwards without losing bit synchronization. To achieve
this the MX589 Xtal clock needs to be accurate enough that the derived RXClock output does not drift by more than
about 0.1 bit time from the actual received data rate during the time that the RXHold input is "low." The RXDCacq input,
however, may need to be pulsed "high" to re-establish the level measurements if the RXHold input is "low" for more than
a few hundred bit-times.
The voltages on the Doc1 and Doc2 pins reflect the average peak positive and negative excursions of the (filtered)
receive signal, and could therefore be used to drive a measure of the data signal amplitude. Note, however, that these
pins are driven from very high impedance circuits, so that the DC load presented by any external circuitry should exceed
10 MO to V BIAS '

MX-COM, INC.

Page 583

I

IX. Conclusion
The maximum data rate that can be transmitted over a radio channel depends on:
- Channel spacing
- Allowable adjacent channel interference
- TX filter bandwidth (BT)
- Peak carrier deviation (modulation index)
- TX & RX carrier frequency accuracies and stabilities.
- Modulator & Demodulator linearity
- RX IF filter frequency & phase characteristics
- Use of radom data and block interleaving techniques
- Use of error correction techniques
- Acceptable error rate.
As a guide:
- For Mobitex operation, a raw data rate of 8000 bps at 12.5 kHz channel spacing is achievable using at BT of
0.3, ±2 kHz maximum deviation and no more than 1500 Hz discrepancy between TX & RX carrier frequencies.
- For CDPD operation, a raw data rate of 19.2 kbps at 30 kHz channel spacing is achievable using at BT of
0.5, ±8 kHz maximum deviation and no more than 3 kHz discrepancy between TX & RX carrier frequencies.
- Forward Error Correction (FEC) and interleaving are commonly incorporated in the protocols to reduce the
effect of burst errors.
- Reducing the data rate to 4800 bps is an alternative that would allow the BT to be increased to 0.5, improving the error rate performance.

References
1. Murota, K., et aI., "GMSK Modulation for Digital Mobile Radio Telephony", IEEE transactions on
communications. VoI.COM-29, NO.7 July 1981
2. RAM Mobile Data, Radio "Modem Reference Design Guide", Woodbridge, New Jersey, USA.

I

3. Anderson, J., et aI., "Digital Phase Modulation" Plenum, 1986.
4. Smith, D., "Digital Transmission Systems" Van Nostrand Reinhold, 1985
5. Couch II, L., "Digital and Analog Communication Systems" MacMillan, 1990.
6. Varrall, G., et aI., "Data Over Radio" Quantum, 1992.

Page 584

MX-COM, INC.

I

GLOSSARY

II

AMPS/NAMPS

Advanced Mobile Phone Service is a cellular system used in the United
States. NAMPS (Narrow AMPS) uses FDMA techniques to derive three voice
channels from one AMPS channel.

ANI

Automatic Number Identification: Identification of the transmitting party by a
preassigned number.

ANSI

American National Standards Institute: A voluntary organization in the United
States that coordinates standards.

Asynchronous transmission

A mode of data transmission in which each bit is not in sync. regarding
frequency or timing. Signals are sent as groups of a specified length with
start and stop bit indicators at the beginning and end of each group.

Bandwidth

The range of frequencies within which a device can transmit or receive.

Baseband

The band of frequencies which is modulated on a carrier or subcarrier in a
wire or radio transmission system to form the transmitted Signal.

Baud

A unit that measures signaling speed in signal events per second. This may
not be the same as bits per second.

BCD

Binary Coded Decimal: A binary (1,0) numbering system in which the digits 0
through 9 are represented by four bits.

BER

Bit Error Rate: A ratio of the number of transmitted bits that are incorrectly
received to the number that are correctly received.

Bit Rate

The speed at which bits are transmitted over a data channel, given in bits per
second (bps).

Carrier

A carrier is a wave capable of being modulated by an information-carrying
signal. The use of multiple carriers permits multiple voice frequency signals in
the same transmission, as in frequency division multiplexing.

C-BUS

MX-COM's serial control bus used to communicate digital information between
a CPu and a peripheral IC such as the MX802, MX803A, MX805A, MX806A
and MX809.

CCIR

International Radio Consultative Committee, a subisdiary organization of the
International Telegraphic Union dealing in radio standards (CCIR was recently
renamed ITU-T - see ITU-T for more information).

CCITT

The ConSUltative Committee on International Telegraph and Telephone is an
international telecommunications standard agency. It was recently renamed
ITU-T (see ITU-T).

CDPD

Cellular Digital Packet Data - an industry standard for data transmission.
CDPD utilizes the analog cellular networks already in place in the U.S. and
Canada to provide 2-way data communications for users of devices such as
laptops and PDAs.

Channel, Voice Grade

A channel with a frequency range of about 300 to 3400 Hz which is suitable
for transmission of data or speech in analog form.

CMOS

Complementary Metal-Oxide Semiconductor (an integrated circuit manufacturing process). MX-COM uses both Metal gate CMOS and Silicon gate CMOS
processes.

MX-COM, INC.

Page 585

I

II

I

GLOSSARY

II

CODEC

A single device comprising both an Encoder and a Decoder.

Compander

Acronym for Compressor-Expander, a circuit that compresses the dynamic
range of an input signal and expands it almost back to its original form on the
output.

Concatenation

Combining multiple data packets or frames in a contiguous series.

Crosstalk

Undesired crossover of voice transmissions from one circuit to another.

CS

Carrier Sense, a logic level supplied by the radio when an RF carrier is detected.

CTCSS

Continuous Tone-Controlled Squelch System: A type of tone coding used in
two-way radio systems in which a sub-audible tone, taken from a field of 32 or
more in the 67 to 250Hz range, is multiplexed continuously with speech to
engage repeaters and allocate traffic among talk groups on shared channels.
Trademarked by Motorola as Private Line or PL.

CVSD

Continuously Variable Slope Delta Modulation: A method by which a voice
signal is digitized for transmission, and then changed back to the analog voice
signal for reception.

DCE

Data Communications Equipment or Data Circuit-Terminating Equipment.
This equipment functions to establish and maintain a connection, and provides
signal conversion between a terminal and data or telephone line.

DSP

Digital Signal Processing.

DCS/CDCSS

Digital Coded Squelch (similar to CTCSS, but digital). Trademarked by
Motorola as Digital Private Line or DPL.

DTMF

Dual Tone Multi-Frequency: a telephone signaling system employing four
tones from a low group and three or four from a high group comprising twelve
to sixteen unique tone pairs. Radio applications of DTMF should avoid "twisf'
(differences in level between tone pairs) and time-limit digits to prevent signaling errors caused by fades.

DVSR

Data/Voice Storage & Retrieval, or at MX-COM, INC., Radio MailVox™.

ECPA

Electronic Communications Privacy Act of 1986: This amendment to Section
2510 of title 18, United States Code, established the illegality of intercepting
protected (Le., scrambled) communications.

EIA

Electronics Industry Association: A United States Manufacturer's group which,
as part of its function, sets and publishes electronics standards.

Eye Pattern/Eye Diagram

An oscilloscope display of the detector voltage waveform in a modem. The
openness of the eye gives a representation of the bit error rate (the more
open, the less distortion).

FSK

Frequency Shift Keying: A form of frequency modulation used to transmit two
states of a signal as two separate frequencies. FSK is characterized by
frequency spacing of 1.

FFSK

Fast Frequency Shift Keying. See MSK.

Full-Duplex

Simultaneous two-way communication.

Page 586

MX-COM, INC.

II

GLOSSARY

II

Gaussian Filter

A filter having the symmetrical l'ell shape of a Gaussian curve (normal distribution).

GMSK

Gaussian Minimum Shift Keying: A type of FSK that uses premodulation
Gaussian filtering to achieve high data rates in an FM communication channel
bandwidth.

GPS

Global Positioning System.

Half-duplex

Communications in which both transmit and receive occur, but not at the
same time.

HSC

Hexadecimal Sequential Coding, a tone signaling protocol comprising 16 tone
states. Ten represent decimals 0-9, a NOTONE, a Repeat tone, a Group tone,
an address/DATA frame Delineator, plus Reset and Control -- totaling 16 tonecoded logic states. HSC operation is predicated on a decoding technique able
to detect tones in random order. These must be contained within a frame
preceded and concluded by NOTONE.

HSC tonesets:
HSC-A: USA or Metropage™
A Motorola radio paging system
employing sequential tones comprising ten decimal and two special
function tones ("R" for repeat and "X" as an alternate address) and
NOTONE in a predictive code format.
HSC-C: CCIR toneset. A toneset developed by the International Radio
Consultative Committee (see separate listing under CCIR).
HSC-E: EEA toneset, An EEA (UK) variation of the CCIR HSC toneset
in which the lowest frequency tone is 930Hz, and the highest is 2247Hz.
Duration is 40ms.
HSC-Z: The ZVEI German HSC toneset.
HSC-ZS: SZVEI or Suppressed ZVEI HSC toneset.
IEEE

The Institute of Electrical and Electronics Engineers: one of the functions of
this association of engineers is to publish standards defining technical terms.

ITU-T

International Telegraphic Union - Telecommunications (includes the CCITT
and CCIR) is an international telecommunications standards agency.

Jitter

Small, abrupt, spurious variations in a waveform due to time, amplitude,
frequency or phase.

LMR

Land Mobile Radio System.

LSI

Large-Scale Integration.

LTRTM

EF Johnson trademarked trunking system.

MOBITEX

A data transmission protocol developed by Swedish Telecom.

MODEM

Modulator/Demodulator: This is a type of DCE that connects data terminal
equipment to a communication line/channel. It converts data to and from the
signal form needed for the communication channel.

MX-COM, INC.

Page 587

I

II

I

GLOSSARY

II

Modulation

The process of modulating a carrier or signal for transmission, also the result
of this process.

Monolithic

Constructed from a single crystal or piece of material.

MSK

Minimum Shift Keying: continuous phase FSK modulation (also called FFSK)
used to transmit two states of a signal as two separate frequencies using
coherent detection and a frequency spacing of 0.5.

Multiplexing

Combining multiple signals for transmission as a group over a single transmission facility.

NMT

Nordic Mobile Telephone is a cellular communications system used primarily
in Europe.

PABX

Private Automatic Branch Exchange.

PCM

Pulse Code Modulation: A process in which an analog signal is sampled and
converted to a binary code for transmission.

PCMCIA

Personal Computer Memory Card International Association: This association
defines and promotes an interchangeable standard for PC memory and
expansion cards. The PCMCIA standard applies to 68-pin I/O or interchange
type cards.

PDA

Personal Digital Assistant: A handheld computer that provides functions like a
notepad or messagepad. PDAs often include data transmission capabilities.

PL

Private Line (a Motorola trademarked name for CTCSS).

PSK

Phase Shift Keying: A form of phase modulation requiring coherent detection.
The most straightforward type of PSK shifts the carrier by 0° or 180°.

Psophometric

A weighting curve used to represent the energy density of speech.

PTM/PTL

"Push to Monitor" or "Push to Listen" is a control on two-way portable and
mobile radios that allows channel monitoring.

PTT

"Push to talk" is a control on two-way portable and mobile radios that enables
transmission.

PSTN

Public Switched Telephone Network.

PvtSQUELCH

MX-COM's combination of CTCSS and voice inversion to provide voice privacy.

QAM

Quadrature Amplitude Modulation: A hybrid amplitude/phase modulation
technique that allows the transmission of four bits of information during a
signaling interval, and therefore requires less bandwidth than normal amplitude
or phase modulation techniques.

Quick Call IFM

A Motorola trademarked 2-Tone sequential signaling format comprising 80
tones arranged in eight tone groups.

R2000

R2000 is a trunked communication system used in France.

Page 588

MX-COM, INC.

II

GLOSSARY

II

RD-LApTM

A FM radio data system that operates at 9.6 and 19.2 kbps. (RD-LAP is a
trademark of Motorola, Inc.)

Repeater

A device used as an intermediate point in a communications system to
receive and retransmit signals, often for the purpose of extending range.

SAT

Supervisory Audio Tone used in cellular systems.

SiGATE

Silicon Gate: a CMOS process used in manufacturing ICs that is smaller and
more modern than metal gate.

Simplex

A circuit which can communicate information in one direction only.

SINAD

A ratio of the total output power to the power of noise plus distortion only:
signal + noise + distortion
noise + distortion.

SMD/SMT

Surface Mount Device I Surface Mount Technology.

SMR

SpeCialized Mobile Radio system.

SS

Spread Spectrum: The spreading of a signal over a wider bandwidth than the
minimum required for transmission of the information.

Synchronous transmission

A type of data transmission in which the sending and receiving ends operate
continuously at the same frequency and in phase.

TACS/ETACS

Total Access Communication System is a cellular system used in the U.K.
ETACS is used in Europe and Japan.

TIA

Telecommunications Industry Association: A United States Manufacturer's
group which, as part of its function, sets and publishes telecommunications
standards.

Type 99™

A General Electric trademarked 2-Tone sequential format comprising 30
tones.

Trunking

A system sharing communication channels.

VCO

Voltage Controlled Oscillator.

VLSI

Very Large Scale Integration.

VOGAD

Voice Operated Gain Adjusting Device, similar in concept to an AGC (Automatic Gain Control) amplifier, used to ensure full modulation of all speech
levels.

VOX

Voice Operated Switching.

VSB

Variable Split Band: A type of high-level analog voice scrambling which splits
and inverts the voice band. VSB is utilized in MX·COM's IC and board level
products (see MX214/224).

MX-COM, INC.

Page 589

I

I
Page 590

MX-COM, INC.

Appendix

Packaging & Handling
The following section gives guidelines for the proper handling of MX·COM
integrated circuits.
It also contains illustrations and measurements of MX·COM's package
offerings. Both standard and special styles are included.
IC's may be shipped in anti-static tubes, conducting foam, or tape and reel.
Tape and reel packaging information begins on page 611.

I
MX-COM, INC.

Page 591

I
Page 592

MX-COM, {NC.

Handling Precautions for Semiconductor Components
To minimize the risk of ESD-induced device damage, the
following handling precautions are strongly recommended:
1) Upon removal from their shipping material (anti-static
tubes, conducting foam or tape and reel), CMOS IC's
should be placed leads down on a grounded surface.
Under no circumstances should they be placed in polystyrene foam or non-conducting plastic.
2) Individuals and tools should be grounded before
coming in contact with CMOS IC's.

II

3) Do not insert or remove devices in sockets with power
applied. Ensure that power supply transients, such as
occur during power turn-on or off, do not exceed maximum ratings.
4) In the system, all unused inputs must be grounded or
otherwise connected to a constant, unvarying input voltage level.
5) After assembly on PC boards, ensure that static
discharge cannot occur during handling, storage, or maintenance. Boards may be stored with their connectors
surrounded with conductive foam.

Soldering PLCC Packages

1. By hand-held soldering iron or pulse-heated
solder tool.
Apply the heating tool to the flat part of the lead only.
Contact time must be limited to 10 seconds at up to 300°C.
2. By wave.
Maximum permissable solder temperature is 260°C, and
maximum duration of package immersion in solder bath is
10 seconds, if allowed to cool to less than 150°C within 6
seconds. Typical dwell time is 4 seconds at 250°C.
3. By solder paste reflow.
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be

II

applied to the substrate by screen printing or pressuresyringe dispensing before device displacement.
Several techniques exist for reflowing, for example, thermal conduction by heated belt, infrared, and vapor-phase
reflow. Dwell times vary between 8 and 60 seconds
according to method. Typical reflow temperatures range
from 215 to 250°C.
Pre-heating is necessary to dry paste and evaporate
binding agent, and to reduce thermal shock on entry to
reflow zone.
4. Repairing soldered joints.
The same precautions and limits apply as in (1) above.

Source: Signetics Corp.

I
MX-COM, INC.

Page 593

Page 594

MX-COM, INC.

NUMBER OF DEVICES SHIPPED PER REELfTUBElTRAY

Number of packaged ICs on a reel:
Package Style

Qty.

LH

700

DW-16

1200
1200

DW-24

Number of packaged ICs in a tube:
Package Style

Qty.

LH

45

LH8
DW-14

28

DW-16

46

DW-24

30

J-14
J-16

25
25

J-22

18

46

J-24

15

P-14

25

P-16

25

P-22

18

P-24

15

Number of die in "waffle packs":
Most waffle packs contain 50 components.

I
MX-COM, INC.

Page 595

I
Page 596

MX-COM, INC.

PACKAGE/PRODUCT CROSS-REFERENCE GUIDE

II
PINS

PRODUCTS

II

DIMENSIONS

I. PLASTIC DUAL IN-LINE (PDIP)
14

MX315AP, MX326P, MX613P

p. 599

16

MX105P, MX109P, MX118P, MX128P, MX316P, MX386P, MX623P, MX631P

18
22

MX366P
MX214P, MX336P, MX406P, MX439P, MX609P

p.599
p.600

24

MX009P, MX014P, MX203Q*P, MX224P, MX346P, MX365AP,

28
40

MX375P, MX709P

p. 601

MX939P

p.602

p.600
p. 601

II. CERAMIC DUAL IN-LINE (CDIP)
14

MX315AJ

p.602

16

MX019J, MX029J, MX102J, MX105J, MX109J, MX316J

p.603

22

MX214J, MX336J, MX406J, MX439J, MX469J, MX609J,
MX619J, MX629J

p.603

24

MX203Q*J, MX803AJ, MX014J, MX224J, MX346J, MX365AJ, MX429J

p. 604

MX529J, MX806AJ, MX009J, MX589J, MX809J, MX909J, MX919J, MX929J
28

MX375J, MX709J, MX802J, MX812J, MX816J, MX826J, MX836J

p.604

III. PLASTIC J-LEADED CHIP CARRIER (PLCC)
24

MX009LH, MX013Q*LH, MX014LH, MX165BLH, MX165CLH, MX203Q*LH,

p. 605

MX214LH, MX224LH, MX275LH, MX316LH, MX336LH, MX346LH,
MX365ALH, MX375LH, MX406LH, MX429LH, MX439LH, MX469LH, MX529LH,
MX609LH, MX619LH, MX629LH, MX802LH, MX803ALH, MX805ALH, MX806ALH,
MX809LH, MX909LH, MX919LH, MX929LH
28

MX375LH8, MX709LH8, MX802LH8

p.605

IV. SMALL OUTLINE IC (SOl C)
16

MX019DW, MX029DW, MX102DW, MX109DW, MX118DW, MX128DW,

p. 606

MX315ADW, MX386DW, MX609DW, MX613DW, MX631DW
20
24

MX366DW
MX165BDW, MX165CDW, MX365ADW, MX439DW, MX469DW, MX589DW,

p. 606
p. 607

MX641 DW, MX806ADW
28

MX812DW, MX816DW, MX826DW, MX836DW

p.607

V. SPECIAL PACKAGES
16 Pin Hybrid (MX003Q)
16 Pin Dual In-Line Side Braize (MX503)

p.60S

16 Pin Thin Shrink Small Outline Package

p.609

28 Pin Thin Shrink Small Outline Package
48 Pin Thin Quad Flat Pack (MX939TG)

p. 609

MX-COM, INC.

p.60S

p. 610
Page 597

I

I
Page 598

MX-COM, INC.

14 PIN PLASTIC DUAL IN-LINE

"P"

cl(l
Pi~l

Package Tolerances
Dimension
in, (mm)
A
B
C
D
E

E

F
G

H

J

K

Min.

.740
.240
.290
.330
.150
.125
.015
.090
.040
.020

Max.

(18.796)
~6.096)

7.366~

(8.382
(3.175
(3.175)
(0.381~

(2.286
(1.016
(0.508)

.770
.260
.310
.370
.200
.150
.020
.110
.065
.070

(19.558)
(6.604)
(7.874)
(9.398)
(5.080)
(3.810)
(0.508)
(2.794)
(1.651)
(1.778)

16 PIN PLASTIC DUAL IN-LINE

cl(l

~---A---~

+

Package Tolerances

Pin 1

Dimension
in, (mm)

Min.

A

.740
.240
.290
.330
.150
.125
.015
.090
.040
.020

B

C

~
H
MX-COM, INC.

D
E
F
G
H

J
K

Max.

(18.796)
(6.096)
(7.366)
(8.382~

(3.175
(3.175

(0.381~

(2.286
(1.016
(0.508)

.770
.260
.310
.370
.200
.150
.020
.110
.065
.070

(19.558)
(6.604)
(7.874)
{9.398)
5.080)
3.810)
(0.508)
(2.794)
(1.651)
(1.778)
Page 599

I

18-PIN PLASTIC DUAL IN-LINE "P"

Package Tolerances

l[f

Dimension
in, (mm)
A
B
C
D
E

F

G

H

J

K

Min.

.830
.240
.290
.330
.150
.125
.015
.090
.040
.020

Max.

(19.1)
(6.096l
(7.366
(8.382
(3.175
(3.175)
(0.381j
(2.286
(1.016
(0.508)

22 PIN PLASTIC DUAL IN-LINE

.880
.260
.310
.370
.200
.150
.020
.110
.065
.070

(22.35)
(6.604
(7.874
(9.398
(5.080
(3.810
~0.508

2.794
1.651
(1.778)

"P"

cl[L
Package Tolerances
Dimension
[in. (mm)]
A
B
C

I

D
E

F
G
H

J
K
Page 600

Min.
1.080
0.330
0.390
0.430
0.150
0.125
0.015
0.040
0.090
0.020

Max.
(27.432)
(8.382)
(9.906)
(10.922)
(3.175)
(3.175)
(.381)
(1.016)
(2.286)
(0.508)

1.10 (27.940)
0.360 (8.382)
0.410 (10.414)
0.470 (11.938)
0.200 (5.080)
0.160 (4.064)
0.020 (0.508)
0.065 (1.651)
0.110 (2.794)
0.070 (1.778)
MX-COM, INC.

24 PIN PLASTIC DUAL IN-LINE

+

IIp ll

Package Tolerances

Pin 1

Dimension
[in. (mm)]
A
B

C
D
E
F
G
H

J
K

28 PIN PLASTIC DUAL IN-LINE
A

t

Min.

1.23 (31.24)
1.26 (32.004)
. 0.55 (13.97)
0.53 (13.46)
0.610 (15.49)
0.59 (14.98)
0.67 (17.018)
0.63 (16.002)
0.220 ( 5.588)
0.170 (4.318)
0.160 (4.064)
0.125 (3.175)
0.020 (.508)
0.Q15 (.381)
0.065 (1.651)
0.040 (1.016)
0.110 (2.794)
0.090 (2.286)
0.065 (.165)
0.015 (0.381)

lip"

1

cl[l

}
•

Package Tolerances

Pin 1

Dimension
in,(mm)

EI~"

FI~'
joI

~I~

G

H

A
B
C
D
E
F
G
H

J
K

MX-COM, INC.

Max.

Min.

Min.

1.44 (36.58)
0.530 (13.46)
0.590 (14.986)
0.630 (16.002)
0.170 (4.318)
0.125 (3.175)
0.090 (2.286)
0.015 (0.381)
0.040 ~1.016)
0.015 .381)

1.47 (37.338)
0.550 (13.970)
0.610 ~15.494~
0.670 17.018
0.220 (5.588)
0.160 (4.064)
0.11 0 ~2.794)
0.020 .508)
0.065 (1.651)
0.065 (1.651)

Page 601

I

40 PIN PLASTIC DUAL IN-LINE

lip"

l:::: :::::~::::::: Jr 1[E
t

Pin 1

Package Tolerances
Dimension

A
B
C
D
E
F
G
H

J
K

14 PIN CERAMIC DUAL IN-LINE

•

Pin 1

E
F
G
H

J
K
L
Page 602

Max.
in. (mm)

2.04 (51.82)
.53 (13.46)
.595 (15.11)
.600 (15.24)

2.06 (52.32)
.55 (13.97)
.625 (15.88)
.660 (16.76)
.310 (7.87)

.128 (3.25)
.018 (.457)
.050 (1.27)
.100 (2.54)
.015 (0.381)

typical
typical
typical

IIJII

Package Tolerances
Dimension
in,(mm)
A
B
C
D

I

Min.
in. (mm)

Min.

Max.

.754 (19.15)
.24 (6.22)
.31 (7.75)
.0098 (.25)
.38 (9.65)
.161 (4.10)
.199 (5.06)
.10 (2.54)
.60 (15.24)
.018 (.46)
.015 (.38)

.766 (19.45)
.25 (6.38)
.315 (8.00)
typical

.42 (10.67)
typical
typical
typical
typical
typical
typical
MX-COM, INC.

16 PIN CERAMIC DUAL IN-LINE

UJII

~

Pin 1

Package Tolerances
Dimension
in,(mm)

A
B

C
D

E
F
G
H

J

22 PIN CERAMIC DUAL IN-LINE

C
,......

'....

)1.)1..

A

A

r
~VVVVVVVLrLr'tJ

1
Dimension
in,(mm)
A

B
C
D
E
F
G

H

J
MX-COM, INC.

.767 (19.48)
.290 (7.40)
.31 (8.00)
typical
typical
typical
typical
typical

Package Tolerances

Pin 1

:i~J

.753 (19.12)
.285 (7.24)
.30 (7.80)
.70 (17.78)
.10 (2.54)
.018 (0.46)
.153 (3.89)
.168 (4.27)
.020 (0.50)

cl[

)1.. )]

l

Max.

IIJII

~

A

Min.

Min.

Max.

1.06 (26.98)
0.376 (9.55)
0.410 (10.40~
0.996 (25.30
0.10 (2.54)
0.018 ~0.46)
0.171 4.35)
0.157 (3.99)
0.020 (0.50)

1.08 (27.38)
0.384 (9.75)
0.417 (10.60)
1.00 (25.50)
typical
typical
typical
0.170 (4.27)

-------

Page 603

I

"J"

24 PIN CERAMIC DUAL IN-LINE

Package Tolerances
Dimension
[in. (mm)]

A
B

C

F

D

D
E
F
G
H
J

~

Pin 1

Dimension
in,(mm)
B

C
D

E
F
G
H

J
K
L
Page 604

1.24 (31.50)
0.514 (13.06)
0.60 (15.14)
1.10 (27.84)
.100 (2.54)
.018 (0.46)
.171 (4.35)
.171 (4.35)
.020 (0.50)

1.26 (32.03)
0.583 (14.81)
0.615 (15.61)
1.11 (28.04)
typical
typical
typical
.196 (4.99)

Package Tolerances
A

I

Max.

"J"

28 PIN CERAMIC DUAL IN-LINE

r:::::~::::l}

Min.

Min.

Max.

1.44 (36.58)
0.51 (13.06)
0.18 (4.49)
0.12 (3.0)
0.10 (2.54)
0.018 (0.45)
0.055 (1.39)
0.02 (.50)
0.61 (15.50)
0.670 (17.0)
0.009 (0.25)

1.46 (37.05)
0.53 (13.36)
0.220 (5.57)
0.15 (3.81)
typical
typical
typical
0.05 (1.30)
0.62 (15.70)
typical
typical
MX-COM, INC.

24 LEAD PLASTIC LEADED CHIP CARRIER

-I r

11

T

II

LH

II

•t K

--............all
I--J--I
Package Tolerances

I--H---1
+

Dimension
in,(mm)

Min.

A
8

.382
.417
.045
.050
.366
.018
.250
.128
.007

C
D
E
F
H

~

t

J
K

Max.

(9.7)
(10.60) 0
(1.15)x45
(1.27)
(9.30)
(0.45)
(6.35)
(3.25)
(.17)

.410 (10.40)
.435 (11.05)
typical
typical
typical
.022 (.55)
typical
.146 (3.70)
.011 (.27)

28 LEAD PLASTIC LEADED CHIP CARRIER ILH8"

-I r

11

Package Tolerances
Dimension
in,(mm)

-+
~

t

A
8
C
D
E
F
G
H

J
MX-COM, INC.

Min.

Max.

.450 (11.43)
.485 (12.32)
.045x45°
.165 (4.20)
.026 (0.66)
.017 (0.43)
.410 (10.41)
.050 (1.27)
.070 (1.78)

.453 (11.51)
.495 (12.57)
typical
.180 (4.57)
.030 (0.76)
.021 (0.53)
.430 (10.92)
typical
.085 (2.16)

Page 605

I

16-PIN SMALL OUTLINE INTEGRATED CIRCUIT

II

OW II

c! 0+t(DDDDDDDD~1
IH
-II- ---I I- ---F

E

G

Package Tolerances

Pin 1

Dimension
in,(mm)

A

0.398
0.291
0.092
0.004
0.014
0.050
0.026
0.096

B

C
D
E
F
G

H
J

5°

Max.

(10.11)
(7.39)
(2.33)
(0.102)
(0.36)
(1.27)
(0.66)
(2.43)

0.406 (10.31)
0.299 (7.59)
typical
0.012 (0.304)
0.018 (0.46)
typical
typical
0.104 (2.64)
typical
0.040 (1.02)
typical
typical
0.011 (0.28)
0.414 (10.51)

0.020 (0.51)
0.025 (0.63)
0.041 (1.04)
0.009 (0.23)
0.39 (9.91)

K
L
M
N

p

Min.

P

20-PIN SMALL OUTLINE INTEGRATED CIRCUIT IIOW II

L( 0-I0r-00000-I00r-00-I011

c

of

Pin 1

G

Package Tolerances
Dimension
in,(mm)

K
L
M
N

0.020
0.025
0.041
0.009

(0.51)
(0.63)
(1.04)
(0.23)

P
R

0.39 (9.91)

E
F
G

Page 606

Max.

(12:62)
(7.39)
(2.33)
(0.102)
(0.36)
(1.27)
(0.66)
(2.43)

B
C
D

R

Min.

0.496
0.291
0.092
0.004
0.014
0.050
0.026
0.096

A

I

H

F

E

H
J

5°

5°

0.506 (12.87)
0.299 (7.59)
typical
0.012 (0.304)
0.018 (0.46)
typical
typical
0.104 (2.64)
typical
0.040 (1.02)
typical
typical
0.011 (0.28)
typical
0.414 (10.51)

MX-COM, INC.

24-PIN SMALL OUTLINE INTEGRATED CIRCUIT nDw n

CLIo+I000000:» ~ 0+IO[E
~

ot

F

E

G

Pin 1

Package Tolerances
Dimension
in,(mm)
A
B

C
D
E
F
G
H

J
K

L
M

N

P

R

Min.

Max.

0.598 (15.19)
0.291 (7.39)
0.092 (2.33)
0.004 (0.102)
0.014 (0.36)
0.050 ~1.27)
0.026 0.66)
0.096 2.43)
5°
0.020 (0.51)
0.025 (0.63)
0.041 (1.04)
0.009 (0.23)
5°
0.39 (9.91)

0.606 (15.41)
0.299 (7.59)
typical

0.012 (0.304)
0.Q18 (0.46)
typical
typical

0.104 (2.64)
typical

0.040 (1.02)
typical
typical

0.011 (0.28)
typical

0.414 (10.51)

28-PIN SMALL OUTLINE INTEGRATED CIRCUIT nDw n

I·

CL(o-II-000000~ ~ 000-IO~
0+

-F

E

Package Tolerances

Pin 1

Dimension
in,(mm)
A

B
C
D

E
F
G
H

J
K
L
M
N
P
R

MX-COM, INC.

G

Min.

Max.

0.698 (17.72)
0.291 (7.39)
0.092 (2.33)
0.004 (0.102)
0.014 (0.36)
0.050 (1.27)
0.026 (0.66)
0.096 (2.43)
5°
0.020 (0.51)
0.025 (0.63)
0.041 (1.04)
0.009 (0.23)
5°
0.39 (9.91)

0.706 (17.97)
0.299 (7.59)
typical

0.012 (0.304)
0.018 (0.46)
typical
typical

I

0.104 (2.64)
typical

0.040 (1.02)
typical
typical

0.011 (0.28)
typical

0.414 (10.51)
Page 607

16 LEAD DUAL IN-LINE HYBRID

I.-..

--A

--~~I

-'1 I+0

B

E

i

I~~~~~~~~I

...

C

~

Nominal Package Dimensions
Dimension
A

B
C
D

E
F

G
H
I
J

in. (mm)
.80 (20.32)
.59 (15.0)
.77 (19.56)
.11 (2.79)
.01 (0.25)
.30 (7.62)
.70 (17.78)
.10 (2.54)
.018 (0.46)
.155 (3.94)

16 LEAD DUAL IN-LINE SIDE-BRAIZE

Nominal Package Dimensions
Dimension
A

8
C

D
E
F
G
H
I
J

I
Page60B

in. (mm)
.81 (20.6)
.30 (7.60)
.5 (12.7)
.11 (2.79)
.01 (0.25)
.26 (6.6)
.70 (17.78)
.10 (2.54)
.018 (0.46)
.13 (3.3)

MX-COM, INC.

16-PIN THIN SHRINK SMALL OUTLINE PACKAGE IITS II

B

Pin 1

P

a

Dimension
in,(mm)
A

B
C

lK

D

E

_t

J

-r-

~

...i M
IT

L

0(

F

G
H
K
L
M
N
P

~

0.240
0.295 t.11l
7.49
0.035 0.90
0.0004 t01l
0.0086 0.22
0.0256 0.65
0.037 (0.95)
50
0.014 ~O.35l
0.024 0.60
0.0047 (0.12)
0.355 (9.02)
0.00

J

N

, !laax." , , : ~~~~~\?'j:".,

Min.

·61r""'·"
0:305
0.043
0.006
0.015

7:1 . ;.,;:,:::;;:.
1.1·0' .;",'} .
0.15·····
0.38

typical
typical

0.047 (1.20)
typical

0.0256 (0.65)
0.039 (1.00)
0.0062 (0.16)
0.371 ~9.42l
0.004 0.10

28-PIN THIN SHRINK SMALL OUTLINE PACKAGE IITS II

B

Package

P

Pin 1

Dimension
in,(mm)

a

A
B
C
D
E

lK
r-:L
t

...i M
IT

J--

0(

N

~

F
G
H
J
K
L

M

N
P

MX-COM, INC.

TOI.,.a~s

Min.

;Max. ·

""~;

':',~::,\"

';:_;;.:'

: ..

,

~ \;~,::;<,"';

g~rl)
0.043 1.10

0.394 110.01)
0.295 7.49l
0.035 0.90
0.0004 ~0.01l
0.0086 0.22
0.0256 0.65
0.037 (0.95)

typical
typical

50
0.014 ~0.35l
0.024 0.60
0.0047 (0.12)
0.355 (9.02)
0.00

0.0256 (0.65)
0.039 (1.00)
0.0062 (0.16)
0.371 ~9.42l
0.004 0.10

0.006 0.15
0.015 0.38

I

0.047 (1.20)
typical

Page 609

48 PIN THIN QUAD FLAT PACKAGE

IITGII

Package Tolerances
Max.
in. (mm)
.362 (9.2)
.280 f7.1)
1 0.27)
.
1.45)
0.15)
typical
.063 (1.6)

7°

.008 (0.20)
ref.

typical
ty 'cal
.O~ (0.65)

I
Page 610

MX-COM, INC.

MX-COM Tape and Reel Specifications
1. Scope
The specification relates to the tape packaging of integrated circuits suitable for use in "surface mounf'
assembly. It includes only those dimensions which are essential for the purchaser to use the product.

2. Dimensions (Refer to Figure 1)
2.1 Tape Width

LG, LH, DW-24
DW-16

W = 24 ± 0.3 mm
W = 16 ± 0.3 mm

2.2 Carrier Tape Thickness

DW-16, DW-24
LG, LH

t = 0.3 mm max.
t = 0.3 ± 0.05 mm

2.3 Pitch of Sprocket Holes
2.4 Diameter of Sprocket Holes

Po = 4.0 ± 0.1 mm
DW-16,DW-24

o = 1.5 + 0.5 mm

LG, LH

o = 1.5 + 0.1

= 1.5 - 0.0 mm
mm

2.5 Distance
2.6 Distance, center to center

E=1.75±0.1 mm
LG, LH, DW-24
DW-16

2.7 Dimension, center of pocket to center of divider
2.7.1
2.7.2
2.7.3
2.7.4
2.8 Embossed Pocket Dimension Ao and Bo
2.8.1
2.8.2
2.8.3
2.8.4
2.8.5
2.8.6
2.8.7
2.8.8
2.9 Embossed Tape Dimension K
2.9.1
2.9.2
2.9.3
2.9.4
2.10 Pitch of Component Compartments
2.10.1
2.10.2
2.10.3
2.10.4

MX-COM, INC.

F = 11.5 ± 0.1 mm
F = 7.7 ± 0.1 mm

LG

LH
DW-16
DW-24

LG
LG

LH
LH
DW-16
DW-16
DW-24
DW-24

LG

LH
DW-16
DW-24

LG

LH
DW-16
DW-24

P2=10±0.1 mm
P2 = 8 ± 0.1 mm
P2 = 6 ± 0.1 mm
P2 = 6 ± 0.1 mm

Ao
Bo
Ao
Bo
Ao
Bo
Ao
Bo

=
=
=
=
=
=
=
=

15.8 ±
15.8 ±
11.5 ±
11.5 ±
10.9 ±
10.7 ±
10.9 ±
16.0 ±

K = 2.9
K = 4.1
K = 3.0
K = 3.0

±
±
±
±

0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1

0.1
0.1
0.1
0.1

P = 20 ± 0.1
P=16±0.1
P=12±0.1
P=12±0.1

mm
mm
mm
mm
mm
mm
min
mm

mm
mm
mm
mm

mm
mm
mm
mm

I
Page 611

2.11 Outside Dimension of Pocket
2.11.1
2.11.2
2.11.3
2.11.4

LG
LH
DW-16
DW-24

81 = 16.5 ± 0.2 mm
81 = 12.4 ± 0.1 mm
81=11.3±0.1mm
81 = 16.2 ± 0.1 mm

2.12 Pocket Center Holes
2.12.1
2.12.2
2.12.3
2.12.4

LG
LH
DW-16
DW-24

D1
D1
D1
D1

=
=
=
=

1.55 +1.0/-0.05 mm
1.55 +1.0/-0.05 mm
2.0 mm min
2.0 mm min

3. Polarity and Orientation of Components in Tape
3.1 All components will be placed so that Pin 1 is adjacent to the sprocket holes. (See Fig. 6.)
3.2 The mounting side of the component will be oriented to the bottom side of the tape. (See Fig. 2.)

4. Fixing of Components in Tape
4.1 Cover tapes will not cover the sprocket holes.
4.2 Tapes in adjacent layers will not stick together in the packing.
4.3 The adhesive of the cover tape will not adversely effect the mechanical and electrical characteristics
and marking of the components.
4.4 Components will not stick to the carrier tape or the cover tape.
4.5 The tapes will be suitable to withstand storage of the taped components without danger or migration
of the terminations or the giving off of vapors which would impair soldering or deteriorate the component
properties or termination by chemical action.
4.6 When the tape is bent with a minimum radius (See Fig. 5) of 30 mm, the tape shall not be damaged
and the components shall remain in their position and orientation in the tape.
4.7 Carrier tape will be conductive.
4.8 Cover tape will be anti-static.
4.9 The peel strength of the cover tape will be 70 + 40 grams measured at 1750 to 180 0 with respect to
the carrier tape along its longitudinal axis. The peel speed will be 240mm/min.
4.10 After baking at 60 0 for 24 hours or storage in ideal condition for two months, the peel strength shall
remain within the specified limits.

I
Page 612

MX-COM, INC.

5. Packaging
5.1 Tape will be wound on plastic reels (See Fig. 4).

5.1.1
5.1.2

A

C

330mm
180mm

12.7mm
12.7mm

Dimensions
N
62.5mm
62.5mm

W1
24.5mm
24.5mm

W2
28.8mm
28.8mm

5.2 There will be a leader of 230mm min. followed by a minimum of 40 empty compartments at the start
of each carrier tape (See Fig. 3).
5.3 There will be no missing components between the first and last part of working tape in any reel.
5.4 At the end of the tape there will be a trailer of a minimum of 75 empty compartments (cover tape
sealed). (See Fig. 3.)
5.5 The tape will release from the reel hub as the last portion of the carrier tape unwinds from the reel.
5.6 Components on a reel.
5.6.1
5.6.2
5.6.3
5.6.4

LG
LH
DW-16
DW-24

13"
700
700
1200
1200

5.7 The tape will be prevented from unreeling by winding a paper tape around the reel and fixing with
adhesive tape.
5.8 All reels will display the following:
Manufacturer's device type number
Quantity on reel
Date code
A static hazard warning label
5.9 Ideal storage conditions are 15° to 20°C with a relative humidity of 60-70%.

6.0 Maximum estimated shelf life when stored as above: 6 months.

Package Types
LG: 24-lead Plastic Gull Wing Package
LH: 24-lead Plastic Leaded Chip Carrier (PLCC)
DW-16: 16-lead Small Outline IC (SOl C)
DW-24: 24-lead Small Outline IC (SOl C)

I
MX-COM, INC.

Page 613

Embossed Carrier Dimensions

I
.... 1
I

o

P2

010 0
I

I
l+I

cD

0

01

Center lines
of cavity

User Direction of Feed
Figure 1

DDD
Direction of unreeling
)0

Tape
bottom side

Figure 2 - Tape Top and Bottom Orientation

I
Page 614

MX-COM, INC.

Direction of unreeling
~

Start

End
0000000000000000000000000

000000000000000000000000

00000000000000

0000000000

DDDDD [OJlOJ[QJ[Q][Q] DDD DD
Trailer
(Minimum 75
empty compartments)

Components

..

Minimum of
40 empty
compartments

Leader
(230mm min.)

Figure 3 - Layout of Tape

W1

1rA

1c

T

Figure 4 - Reel Dimensions

R

Figure 5 - Minimum Radius = 30mm.

I
MX-COM, INC.

Page 615

o

0

0 000 000

~

0

0 0

0

0

000 000

User direction of feed

LH Package

o

0

User direction of feed

LG Package

o

0 0

~

0

0 0

0

0

000 000 0

DDD
OW Package

User direction of feed

Figure 6 - Component Orientation

•

I
Page 616

MX-COM, INC.

REPLACEMENT PRODUCT GUIDE

II

II

0

i5
ca

a:

.!!

:c0

::i
>ca

Device

Description

==
N

1/1
CD

c
0

J::.

...ca

II.

]!
Gi

0

1/1

1/1
CD
C

E

J::.

'tI
0

II.
1/1
1/1
CD

'6
...
0

0

>-

CD

0

.;:
:::I
U
CD

>- ::i

C

0

J::.
DCD

Gi

l-

1/1
1/1
CD

e
~

Dl

t/)

c CD
'61 u
ca '0

II.

>

CD
1/1

0

'tI
CD_
'tic

II.
jij

CD E
E CD
E u
o.!!!

...D-:::I

...

CD

c

CD

Cl

C

CD

uDCD CD

a: a:

MXOO3

Selective Call Tone Decoder

II'

MX203l803A

MXOO4

Voice Band Inverter

II'

MX014

MX103

Address Selector

II'

MX165

CTCSS Encoder/Decoder with Audio Filter

II'

MX205

Tone Generator

MX265

CTCSS Encoder/Decoder

MX313/323 MUX/Display Driver

II'
MX165C

II'
II'

MX805A
MX165C

II'
II'

II'

MX315

CTCSS Encoder

MX326

Audio Bandpass Filter

MX335

CTCSS Encoder/Decoder

II'

II'

MX165C/805

MX355

CTCSS Encoder/Decoder

II'

II'

MX165C

MX365

CTCSS Encoder/Decoder

II'

II'

MX165C

MX403

Sequential Tone Transponder

II'

MX409

1200 bps MSK Modem

II'

II'

II'

MX469

MX419/519 1200 bps MSK Modem

II'

II'

II'

MX469

MX489

19.2 k bps GMSK Modem

II'

II'

II'

MX589

MX611

SPM Detector

II'

MX631

MX621

Low-Power SPM Detector

II'

MX631

MX803

Audio Signaling Processor

II'

II'

MX803A

MX805

Sub-Audio Signaling Processor

II'

MX805A

MX806

Audio Processor

II'

MX806A

MX-COM, INC.

II'

MX315A

II'
II'

II'

Page 617

I

I
Page 618
MX-COM, INC.

Manufacturers of Compatible Xtals
for use with MX-COM ICls

This is not a complete list of xtal manufacturers, but it should provide a few sources for xtals that
can be used with MX·COM ICs.

CTS Corporation
1201 Cumberland Ave.
West Lafayette, IN 47906
Phone: 317-463-2565
Ecliptek Corporation
3545-8 Cadillac Ave.
Costa Mesa, CA 92626-1401
Phone: 714-433-1200

Relm Communications
7707 Records St.
Indiannapolis, IN 46226
Phone: 800-228-8108

I
MX-COM, INC.

Page 619

I
Page 620
MX-COM, INC.

INDEX BY PART NUMBER

II
MX009

II

Octal Digital Control Amplifier ...................................................... p. 449

MX013

HSC Tone Decoder ..................................................................... p. 229

MX014

Voice Band Inverter ..................................................................... p. 345

MX019

Quad Digital Control Amplifier ..................................................... p. 455

MX029

Dual Digital Control Amplifier ....................................................... p. 460

MX102

Autocorrelator .............................................................................. p. 503

MX105

Tone Detector .............................................................................. p. 509

MX109

Full Duplex CVSD Codec with Serial Control .............................. p. 377

MX118

Full-Duplex Scrambler for Cordless Telephones.........................

MX128

Full-Duplex Scrambler for Cordless Telephones ......................... p. 366

MX165B

CTCSS Encoder/Decoder with Audio Filter ................................. p. 160

MX165C

CTCSS Encoder/Decoder with Audio Filter ................................. p. 169

p. 360

MX203

Selective Call Codec .................................................................... p. 234

MX214

VSB Inverter ................................................................................ p. 351

MX224

VSB Inverter ................................................................................ p. 351

MX275

Pvt SQUELCWM CTCSS Encoder/Decoder ............................... p. 187

MX315A

CTCSS Encoder .......................................................................... p. 155

MX316

NMT Audio Filter Array ................................................................ p. 267

MX336

Audio/Subaudio Filter Array ......................................................... p. 272

MX346

Cellular Audio Processing Array .................................................. p. 278

MX365A

CTCSS Encoder/Decoder with Audio Filter ................................. p. 178

MX366

Quad Filter Array (NAMPS/ETACS) ............................................ p. 285

MX375

Pvt SQUELCHTM CTCSS Encoder/Decoder ............................... p. 195

MX386

Q"ad Filter Array (NAMPSITACS/AMPS/ACSB) ........................ p. 291

MX429

1200 bps MSK Modem with Parallel BUS Control ....................... p. 15

MX439

1200 bps MSK Modem with Serial Control .................................. p. 29
An RS-232 Asynchronous Modem using the MX439 .................... p. 567

MX469

1200/2400 bps MSK Modem with Serial Control ......................... p. 35

MX503

Sequential Tone Encoder ............................................................ p. 242

MX529

1200 bps MSK Modem with Parallel BUS Control ....................... p. 15

MX589

40k bps GMSK Modem with Serial Control ................................. p. 43

MX609

Full Duplex CVSD Codec with Companding .............................. p. 384
An Audio Delay Circuit Based on the MX609 .............................. p. 558

MX613

Global Call Progress Detector .................................................... p. 469

MX619

Delta Modulation Codec .............................................................. p. 391

MX629

Delta Modulation Codec ............................................................... p. 391

MX623

Line-Powered Call Progress Detector ......................................... p. 477

MX631

Low-Power SPM Detector .......................................................... p. 483

MX641

Dual SPM Detector ..................................................................... p. 490

MX-COM, INC.

I
Page 621

MX709

Voice Storage and Retrieval (VSR) Codec w/ SRAM ................. p. 403

MX802

Full Duplex VSR Codec with DRAM Control ............................... p. 420

MX812

Half Duplex VSR Codec with DRAM Control .............................. p. 434

MX803A

Audio Signaling Processor ........................................................... p. 249

MX805A

Sub-Audio Signaling Processor ................................................... p. 204

MX806A

Audio Processor .......................................................................... p. 295

MX809

1200 bps MSK Modem with C-BUS Control .............................. p. 57

MX816

NMT Audio Processor ................................................................. p. 307

MX826

AMPS/NAMPS Audio Processor ................................................. p. 319

MX836

R2000 Audio Processor .............................................................. p. 331

MX909

High-Speed and MOBITEX GMSK Modem ............................... p. 70

MX919

High-Speed 4-Level FSK Modem/ARDIS .................................. p. 103

MX929

High-Speed 4-Level FSK Modem/ARDIS .................................. p. 103

MX939

CDPD/AMPS-WBD Full-Duplex Modem .................................... p. 140

Application Information:
CVSD CODEC Overview ............................................................................................. p. 374
Crystal Oscillator Circuits ............................................................................................. p. 560
DBS800 C-BUS System Development ........................................................................ p. 523
Definitions

..................................................................................................... p. 590

Error Detection & Correction of MPT1327 Formatted Messages .................................. p.571
Generation of Non-Standard CTCSS Tones ................................................................. p. 538
GMSK IC Modems

..................................................................................................... p. 579

HSC Product Overview ................................................................................................ p. 223
Packaging and Handling ............................................................................................... p. 591
Product Replacement Guide ......................................................................................... p. 617

Pvt SQUELCH: Combining CTCSS with Voice Band Inversion .................................... p. 534
Standards and References ............................................................................................ p. 519
Switched Capacitor Interfacing ...................................................................................... p.549
Variable Split Band Scrambling ..................................................................................... p. 543
Wireless Data Modems: Getting the Best Performance ................................................ p. 562
Wireless Modem Guide ................................................................................................ p. 14
Xtals Compatible with MX-COM ICs ............................................................................. p. 619

I
Page 622

MX-COM. INC.

MX·COM, INC. ICs are available throughout the world:
.In Korea
S-TEC INTERNATIONAL CO., LTD.
Yoido P.O. Box 577
Room # 130 1-1, Yoido Department Store Bldg.
36-2, Yoido Dong, Yeongdeungpo-Ku
Seoul, 150-010, Korea
Phone: (02) 784-6800
Fax: (02) 784-8600
Telex: K23456 STECI
.In Taiwan
MITRONICS INTERNATIONAL CORP.
7F, No. 104 Tung Hua South Road
Section 2
Taipei, Taiwan, R.O.C.
Phone: (02) 709-7626
Fax: (02) 755-3394
• In Hong Kong
TEKCOMP ELECTRONICS, LTD.
913-4 Bank Centre,
636 Nathan Rd.
Kowloon, Hong Kong
Phone: (852) 710-8121
Fax: (852) 710-9220
Telex: 38513 TEKHL HX
• In Australia & New Zealand
VELTEK PTY LTD.
18 Harker Sf.
Burwood, Victoria 3125 Australia
Phone: 61-3-808-7511
Fax: 61-3-808-5473
.In Israel
ELiNA ELECTRONICS, LTD.
14, Raoul Wallenberg SI.
P.O.B.13190
Tel-Aviv 61131 Israel
Phone: (972) 3-498543/4
Fax: (972) 3-498745

.In Japan
TEKSEL CO., LTD.
TBC, Higashi 2-27-10
Shibuya-ku, Tokyo 150 Japan
Phone: (03) 5467-9000
Fax: (03) 5467-0777

.In Turkey
OAKDALE/HANKUR LTD.
Catal Cesme Sok No. 27
Cagaloglu, Istanbul Turkey
Phone: 5270057
Fax: 511 0952

Osaka Office
2-20-10 Minamikaneda,
Suita-shi, Osaka-fu 564 Japan
Phone: (06) 368-9000
Fax: (06) 368-8880

• In Pakistan
OAKDALE/NADEEM TRADERS
Gul Plaza,Charsadda Road
Peshawar, Pakistan
Phone: 241958
Fax: 241977

Kyusyu Office
Nichiei-Ohkusu Bldg., 3F
2-6-9 Ohkusu, Minami-ku
Fukuoka-shi,
Fukuoka-ken 815 Japan
Phone: (092) 524-6401
Fax: (092)524-6566

• In Illinois USA
PHASE II MARKETING, INC.
2220 Hicks Rd., SUite 206
Rolling Meadows, IL 60008 USA
Phone: (708) 577-9401
Fax: (708) 577-9491

Nagano Office
OAU Bldg., 3F
2-1-22 Tenjin, Ueda-shi,
Nagano-ken 386 Japan
Phone: (0268) 23-7411
Fax: (0268) 23-7412

• In Northeast USA
HARWOOD ASSOCIATES
25 High Street
Huntington, NY 11743 USA
Phone: (516) 673-1900
Fax: (516) 673-2848

Nagoya Office
Wakayama Bldg.,
1-8-11 Ikeshita, Chikusa-ku,
Nagoya-shi. Aichi-ken 464 Japan
Phone: (052) 762-1355
Fax: (052) 761-9883

• In Northwest USA
SPS ELECTRONICS
128 North Shore Circle
Lake Oswego, OR 97034 USA
Phone: (503) 697-7768
Fax: (503) 697-7764

MX • [!1M, INt'...
4800 Bethania Station Rd.
Winston-Salem, NC 27105-1201
United States of America
Phone: (910) 744-5050
(800) 638-5577
Fax: (910) 744-5054

Washington Office
21303 52nd West C-216
Mounllake Terrace, WA 98043 USA
Phone: (206) 323-4140
Fax: (206) 672-8766

oo~

,s:

~

~~.=-

~
TX JJOD OUT

TOMCXll.l.ATOR

v'"

~

----II--I-~~;;;;;;;'~v
n:-",..-ll

dB

EAA""""'OUT

v..

11-------1
ENPIECE

LSALDlOot.rr

MSK O.... TA
OUT

MSK DATA

L~.

EXPA.ND

!STORE

(EXPAI«D)

.<
00
(0)
(7)

I

MX836

The Controlling System
C-BUS is designed for low IC pin-count, flexibility in handling variable amounts of data, and simplicity of system
design and ~Controller software. It may be used with any ~Controller, and can, if desired, take advantage of the
hardware and serial I/O functions built into many types of ~Controller. Because of this flexibility and because the BUS
data rate is determined solely by the ~Controller, the system designer has complete freedom to choose a ~Controller
appropriate to the overall system processing requirements.
Control of the functions and levels within the MX836 R2000 Audio Processor is by a group of Address/Commands
and appended data instructions from the system microcontroller. The use of these instructions is detailed in the
following paragraphs and tables.

00000001
000 1 0 0 0 0
000 1 000 1
000 1 001 0
00010011

1
1
1
1

+

+
+
+

byte
byte
byte
byte

2
3

4
5

In C-BUS protocol the MX836 is allocated Address/
Command values 10H to 13H" Configuration, Tx/RX Gains,
and SAT/Powersave assignments and data requirements
are given in Table 1.
Each instruction consists of an Address/Command
(AlC) byte followed by a data instruction formulated from
the following tables.
Commands and Data are only to be loaded in the
group configurations detailed, as the C-BUS interface

recognized the first byte after Chip Select (logic 0) as an
Address/Command. Function or Level control data, which
is detailed in Tables 2,3,4, and 5, is acted upon at the end
of the loaded instruction. See Timing Diagrams, Figures
5 and 6.
Upon power-up the value of the "bits" in this device will
be random (either "0" or "1"). A General Reset Command
(01 H) is required to set all MX816 registers to 00H"

Configuration Command

TX Gain & Mod. Command

(MSB)
Bit 7

a
1

6
1

5

(MSB)

RX Gain Element
Powersave
Enable

7

SW5 Expander
Expander Bypass
Expander Route

a
1

4

SW4 TX/RX Audio
TX Store/Audio
RX Store/Audio

a
1

3

SW3 Dev. Limiter
Dev. Limiter Bypass
Dev. Limiter Route

a
1

2

SW1 Mic. Inputs
Mic.llnput
Mic.2lnput

a
1

1
1

Transmitted First

All Functions
(except RX Gain Element)
Powersave
Enable

a

a
a

(Preceded by AlC 10,)

0

a
1

a
1

SW2 TX Function
DTMFln
Compressor In
Compressor Bypass
MSKlPlayin

Table2 - Configuration Commands
Page 336

a
a
a
a
a
a
a
a
1
1
1
1
1
1
1
1

Transmitted First

6

5

4

a a a
a a 1
a 1 a
a 1 1
1
a a
1
a 1
1
1 a
1
1 1
a a a
a a 1
a 1 a
a 1 1
1
a a
1
a 1
1
1 a
1

1

1

3

2

1

0

1
1
1
1
1
1
1
1

1

1

1

a
a
a
a
a
a
a
a

(Preceded by AlC 11,)

a a a
a a 1
a 1 a
a 1 1
1
a a
1
a 1
1 a
1
1
1 1
a a a
a a 1
a 1 a
a 1 1
1
a a
1
a 1
1
1 a

TX Mod. Level
OFF (Low Z to v BIAS)
-5.6dB
-5.2dB
-4.8dB
-4.4dB
-4.adB
-3.6dB
-3.2dB
-2.8dB
-2.4dB
-2.OdB
-l.6dB
-1.2dB
-a.8dB
-a.4dB
OdB
TX Input Gain
-2.65dB
-2.a5dB
-1.5OdB
-a.95dB
-a.45dB
OdB
a.45dB
a.85dB
1.25dB
1.65dB
2.a5dB
2.40dB
2.7OdB
3.a5dB
3.35dB
3.65dB

Table 3 - TX Gain & Mod. Commands
MX-COM, INC.
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