1994_NEC_K Series_Microcontrollers_Data_Book 1994 NEC K Series Microcontrollers Data Book
User Manual: 1994_NEC_K-Series_Microcontrollers_Data_Book
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NEC Electronics Inc.
NEe
1994
K-SERIES MICROCONTROLLERS
DATA BOOK
Document No. 50053-1
©1994 NEe Electronics Inc. All rights reserved.
Printed in the United States of America.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics Inc.
(NECEL). The information in this document is subjectto change without notice. Devices sold by NECELarecovered by the warranty and patent
indemnification provisions appearing in NECEL Terms and Conditions of Sale only. NECEL makes no warranty, express, statutory, implied,
or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. NECEL
makes no warranty of merchantability or fitness for any purpose. NECEL assumes no responsibility for any errors that may appear in this
document. NECEL makes no commitment to update or to keep current information contained in this document. The devices listed in this
document are not suitable for use in applications such as, but not limited to, aircraft, aerospace equipment, submarine cables, nuclear reactor
control systems and life support systems. If customers intend to use NEC devices in these applications or they intend to use ·standard" quality
grade NEC devices in applications not intended by NECEL, please contact our sales people in advance. "Standard" quality grade devices are
recommended for computers, office equipment, communication equipment, test and measurement equipment, machine tools, industrial
robots, audio and visual equipment, and other consumer products. "Special" quality grade devices are recommended for automotive and
transportation equipment, traffic control systems, anti-disaster and anti-crime systems, etc.
NEe
NEe
Reliability and Quality Control
IJPD78COO
IJPD78KO
IJPD78K2
IJPD78K3
Development Tools
Soldering
Package Drawings
NEe
NEe
Contents
Section 1
Reliability and Quality Control
Section 3 (cont)
I'PD7BKO Product Line
B-Bit, K-Series Microcontrollers
Section 2
I'PD7BCOO Product Line
B-Bit, Single-Chip Microcontrollers
I'PD78C14 Family
{fJPD78C10A/C11 A/C12A/C14/C14A/CP14)
8-Bit, Single-Chip Microcontrollers
With A/D Converter
2-a
I'PD78C18 Family
{fJPD78C17/C18/CP18)
8-Bit, Single-Chip Microcontrollers
With AID Converter
2-b
I'PD78COO Product Line
Programming Reference
2-c
I'PD78064 Family
{fJPD78062/063/064/P064)
8-Bit, K-Series Microcontrollers
With LCD Controller/Driver, UART, and A/D
Converter
3-g
I'PD78KO Product Line
Programming Reference
3-h
Section 4
I'PD7BK2 Product Line
B-Bit, K-Series Microcontrollers
Section 3
I'PD7BKO Product Line
B-Bit, K-Series Microcontrollers
I'PD78002 Family
{fJPD78001 B/002B/P014)
8-Bit, K-Series Microcontrollers
General Purpose
3-a
I'PD78002V Family
{fJPD78001 BV/002BY/P014y)
8-Bit, K-Series Microcontrollers
General Purpose with 12C Bus
3-b
I'PD78014 Family
{fJPD78011 B/012B/013/014/P014)
8-Bit, K-Series Microcontrollers
General Purpose with A/D Converter
3-c
I'PD78014V Family
{fJPD78011 BY/012BY/013Y/014Y/P014Y)
8-Bit, K-Series Microcontrollers
General Purpose with AID Converter and 12C
Bus
3-d
I'PD78044 Family
{fJPD78042/043/044/P044)
8-Bit, K-Series Microcontrollers
With FIP (VP) ControllerlDriver and AID
Converter
3-e
I'PD78054 Family
{fJPD78052/053/054/P054)
8-Bit, K-Series Microcontrollers
With UART, A/D and D/A Converters
3-f
I'PD78214 Family
{fJPD78212/213/214/P214)
8-Bit, K-Series Microcontrollers
With AID Converter, Real-Time Output Ports
4-a
I'PD78218A Family
{fJPD78217A/218A/P218A)
8-Bit, K-Series Microcontrollers
With AID Converter, Real-Time Output Ports
4-b
I'PD78224 Family
{fJPD78220/224/P224)
8-Bit, K-Series Microcontrollers
With Analog Comparators, Real-Time Output
Ports
4-c
I'PD78238 Family
{fJPD78233/234/237/238/P238)
8-Bit, K-Series Microcontrollers
With A/D and D/A Converters, Real-Time
Output Ports
4-d
I'PD78244 Family
{fJPD78243/244)
8-Bit, K-Series Microcontrollers
With AID Converter, EEPROM, Real-Time
Output Ports
4-e
I'PD78K2 Product Line
Programming Reference
4-f
v
NEe
Contents
Section 5
ILPD7BK3 Product Line
16-/B-Bit, K-Series Microcontrollers
Section 6 (cont)
Development Tools
",PD78312A Family
(pPD78310A/312A/P312A)
16-/B-Bit, K-Series Microcontrollers
With Real-Time Output Ports
5-a
",PD78322 Family
(pPD78320/322/P322)
16-/B-Bit, K-Series Microcontrollers
With AID Converter, Real-Time Output Ports
5-b
I'PD78352 Family
(pPD78350/352A/P352)
16-/B-Bit, K-Series Microcontrollers
With Real-Time Output Ports
5-c
I'PD78356 Family
(pPD78355/356/P356)
16-/B-Bit, K-Series Microcontrollers
With AID Converter and Convolution
Capability
5-d
SD78KO
Screen Debugger for the /-IPD7BKO Product
Line
6-j
pPD78K2 Product Line: 8-Bit Microcontrollers
Section 6
Development Tools
IE-78230-R
In-Circuit Emulator for the /-IPD78224/238
Families
6-k
IE-78240-R
In-Circuit Emulator for the /-IPD78214/218A/244
Families
6-1
DDB-78K2
Evaluation Board for the /-IPD78K2 Product
Line
6-m
EB-78230-PC
Evaluation Board for the /-IPD78238 Family
6-n
EB-78240-PC
Evaluation Board for the /-IPD78214!218A/244
Families
6-0
CC78K2
C Compiler for the /-IPD7BK2 Product Line
6-p
6-q
Development Tools Selection Guide
6-a
ROM Code Submission Guide
6-b
RA78K2
Relocatable Assembler Package for the
/-IPD78K2 Product Line
PG-1500 Series
PROM Programmer
6-c
pPD78K3 Product Line: 16-/8-Bit Microcontrollers
pPD78COO Product Line: 8-Bit Microcontrollers
IE-78C11-M
In-Circuit Emulator for the /-IPD78COO Product
Line
6-d
CC87
Micro-Series C Compiler Package for the
/-IPD7BCOO Product Line
6-e
~~
~
Relocatable Assembler Package for the
/-IPD78COO Product line
pPD78KO Product Line: 8-Bit Microcontrollers
IE-78310A-R
In-Circuit Emulator for the /-IPD78312A Family
6-r
IE-78327-R
In-Circuit Emulator for the /-IPD78322 Family
6-S
IE-78350-R
In-Circuit Emulator for the /-IPD78352/356
Families
6-t
EB-78320-PC
Evaluation Board for the /-IPD78322 Family
6-u
EB-78350-PC
Evaluation Board for the /-IPD78352 Family
6-v
IE-78000-R
In-Circuit Emulator for the /-IPD7BKO Product
Line
6-g
CC78K3
C Compiler for the /-IPD78K3 Product Line
6-W
6-x
CC78KO
C Compiler for the /-IPD78KO Product Line
6-h
RA78K3
Relocatable Assembler Package for the
/-IPD78K3 Product Line
RA78KO
Relocatable Assembler Package for the
/-IPD7BKO Product Line
vi
6-i
NEe
Contents
Section 7
Soldering
Section 8 (cont)
Package Drawings
"PD78COO Product Line;
Soldering and Packaging Information
7-1
64-Pin Plastic QFP (1.7-mm height)
(P64G-SO-22-1)
"PD78KO Product Line;
Soldering and Packaging Information
7-3
64-Pin Ceramic QFP for Engineering Samples
8-11
64-Pin Plastic QUIP (P64GQ-100-36)
8-12
"PD78K2 Product Line;
Soldering and Packaging Information
7-5
64-Pin Plastic QUIP (P64GQ-100-37)
8-13
64-Pin Ceramic QUIP w/window (P64RQ-100-A)
8-14
6S-Pin PLCC (P6SL-50A1-1)
8-15
"PD78K3 Product Line;
Soldering and Packaging Information
7-7
Soldering Conditions
'7-9
Section 8
Package Drawings
8-10
6S-Pin Ceramic LCC w/window (X6SKW-50A)
8-16
74-Pin Plastic QFP(S74GJ-100-SBJ-1)
8-17
8O-Pin Ceramic LCC w/window (XSOKW-SOA)
8-18
SO-Pin Ceramic LCC w/window (XSOKW-65A)
8-19
8-1
8O-Pin Plastic QFP (P80GF-SO-3B9-1)
8-20
64-Pin Ceramic Shrink DIP (P64DW-70-750A)
8-2
SO-Pin Plastic QFP (SSOGC-65-3B9-1)
8-21
64-Pin Ceramic Shrink DIP (P64DW-70-750A1)
8-3
8O-Pin Pla,stic TQFP (PSOGK-50-BE9-1)
8-22
64-Pin Ceramic LCC w/window (XSOKW-80B)
8-4
84-Pin PLCC (PS4L-50A3-1)
8-23
64-Pin Ceramic LCC w/window (X64KW-100A-1)
8-5
94-Pin Plastic QFP (S94GJ-SO-SBG-1)
8-24
64-Pin Plastic QFP (P64G-100-12, 1B-1)
8-6
94-Pin Ceramic LCC (X94KW-SOA)
8-25
64-Pin Plastic Shrink DIP (P64C-70-750A, C)
64-Pin Plastic QFP (P64GC-SO-ABS-2)
8-7
100-Pin Plastic QFP (P100GC-SO-7EA)
8-26
64-Pin Plastic QFP (P64GF-100-3BS, 3BE-1)
8-8
100-Pin Plastic QFP (P100GF-65-3BA)
8-27
64-Pin Plastic QFP (3.0-mm height)
(P64GC-SO- 3BE)
8-9
120-Pin Ceramic LCC (X120KW-SOA)
8-28
vii
NEe
Contents
Numerical Index
Device, "PD
78C10A
78C11A
78C12A
78C14
78C14A
78CP14
Page
208
78C17
78C18
78CP18
78001B
78002B
78001 BY
78002BY
2-b
78011B
78012B
78013
78014
78P014
78011 BY
78012BY
78013Y
78014Y
78P014Y
78042
78043
78044
78P044
78052
78053
78054
78P054
78062
78063
78064
78P064
3-c
viii
308
3-b
3-d
3-e
3-f
3-g
Device, "PD
78212
78213
78214
78P214
78217A
78218A
78P218A
78220
78224
78P224
78233
78234
78237
78238
78P238
Page
4-a
4-b
4-c
4-d
78243
78244
4-e
78310A
78312A
78P312A
78320
78322
78P322
78350
78352A
78P352
5-a
78355
78356
78P356
5-b
5-c
5-d
NEe
Reliability and Quality Control
NEe
o
Reliability and Quality Control
Section 1
Reliability and Quality Control
Introduction
1-1
Built-In TQC
1-2
Approaches to TQC
1-2
Zero Defects Program
1-2
Statistical Approach
1-3
Implementation of Quality Control
1-3
Product Development
1-4
Incoming Material Inspection
1-4
In-Process Quality Inspection
1-4
Electrical Testing and Screening
1-4
Outgoing Inspection
1-4
Reliability Assurance Test
1-5
Process/Product Changes
1-5
Reliability Theory
1-5
Life Distribution
1-5
Failure Distribution at NECEL
1-6
Infant Mortality Failure Screening
1-6
Accelerated Reliability Testing
1-7
Reliability Assurance Tests
1-7
Failure Rate Calculation/Prediction
1-8
Failure Rate Calculation Example
1-9
Failure Rate Goals
1-9
Failure Analysis
1-10
Summary
1-10
NEe
NEe Electronics Inc.
Reliability and Quality Control
NECEL Electronics Inc. is dedicated to the QCD principle of
providing the highest quality product at the lowest possible
cost with on-time delivery to our customers.
As large-scale integrated (LSI) circuits increase in density, the reliability of individual devices imposes a more
profound impact on system reliability. As a result, great
emphasis has been placed by LSI circuit manufacturers on assuring device reliability.
vanced technology combined with the practice of TOC
yields products as reliable as those from previous
technologies.
Conventionally, performing reliability tests and using
feedback from the field have been the only methods of
monitoring and measuring reliability. As LSI density
increases, however, internal device circuit elements
have become more difficult to activate from external
terminals and to detect their degradation. Testing and
feedback alone cannot provide enough information to
ensure today's demanding reliability requirements.
TOC activities are geared toward total customer satisfaction. The success of these activities depends on
management's commitment to enhancing employee
development, maintaining a customer-first attitude,
and fulfilling community responsibilities.
To guarantee and improve the reliability of LSI circuits,
a new philosophy and methodology are needed for
reliability assurance. Ouality and reliability must not
only be monitored and measured but, most importantly, must be built into the product.
BUlLT·IN TQC
NECEL introduced the concept of total quality control
(TOC) across its entire semiconductor product line to
implement this philosophy. Ouality control is now an
integral part of each process step and requires production, engineering, quality control staffs, and all management personnel to participate in TOC activities.
Figure 1 is a flowchart that shows how these activities
form a comprehensive quality control system at
NECEL.
In addition to TOC, NECEL introduced a pre-screening
method into the production line that eliminates potentially defective units. This combination of building in
quality and screening out projected early failures has
resulted in superior quality and reliability.
Most LSI circuits use high-density MOS technology.
Their state-of-the-art high performance improved fineline generation techniques. When physical parameters
are reduced, circuit density and performance increase
and active circuit power dissipation decreases.The
information presented here will show that this ad-
10002·3
APPROACHES TO TQC
TOC is implemented in the following steps. First, quality control is embedded into each process, allowing
early detection of possible failure mechanisms and
immediate feedback. Second, the reliability and quality
assurance policy is upheld through company-wide
quality control activities. Third, emphasis is placed on
research and development efforts to achieve even
higher standards of device quality and reliability.
Fourth, extensive failure analysis is performed periodically, and appropriate corrective actions are taken as
preventative measures.
Process control limits are based on statistical data
gathered from this analysis and used to determine the
effectiveness of the in-process quality control steps.
New standards are continuously upgraded, and the
iterative process continues. The goal is to maintain the
superior product quality and reliability that has become synonymous with the NEC name.
Zero Defects Program
One of the quality control activities that involves every
staff level is the "Zero Defects" (ZD) program. The
purpose of the ZO program is to minimize, if not
prevent, defects due to controllable causes. These
activities are organized by groups of workers around
these four premises.
• A group must have a target or purpose to pursue.
• Several groups can be organized to pursue a
common target.
• Each group must have a responsible leader.
• Each group is well supported by management.
1-1
NEe
Reliability and Quality Control
Figure 1. NECEt:s Quality Control System
Dept
liE
f
I
I
MarkeUng
Sales
CUstomer
Devel:ment
Market
Resesrch
Needs
I
Clrcure Design
Device Design
Production
Englneeq
I
I
I
R&QC
Manufactu~ng FacUlty
InspectloniManufacturlng
Planning
Technology
~
Ir=1
Sales
Plan
~
I
I
New DevIce Development and Sales Commlllee
~
'--
_I
-I
j
h
Development(
Device Design
Circuit DeSign
ProductlProcess Design
iii
~
F
..,
I
I
li
"
i'
.
c
I
DeSign Review
t
T~al
Spec/Eng. Support
-
I
t
I
Characte~zaUoni
H
Ii
Production Run
I
Rellabnlty
EvaluaUon
Eveluatlon
~
I
Mass ProductloniSales Committee
J
J
i
I
Rellabmty
EvaluaUon
~ Procuramentof
PartslMate~a1s
Q,
!
I
::;
I
I
Preparation of Spec for
ManufacturlngfTesUngfQA
~
I
t
Incoming
Inspection
WarahcuSing
r--
y
Archive of
Order
i
'--
Use
Complaint
(FIeld Data)
=:c
1
1
~
: Shipping
i::;
~
Receipt
Collection
I C
InvestlgaUOniAnalyslsfCountenneasure
Direction of Lot
t
~..
,
.J
t
C
Electrical Test
Reliability Test
QA InsplPacking
~
Manufactu~ng
Data Collection
)-~
In-Process Quality Monlto~ng;
In-Process Inspection;
Environment and Equipment
ControVC8l1breUon;
Lot Control;
Corrective Actions;
Data Analysis; Feedback; Etc.
83RIHfi14S (Q'93)
1-2
NEe
The group's target is selected from items relating to
specifications, inspections, operation standards, etc.
When past data is available, a Pareto diagram is created and reviewed to select an item most in need of
quality improvement. Target defects related to this item
are clearly defined. Records are analyzed to compute
numerical equivalents of the defects. Then, action is
taken to control these defects.
Reliability and Quality Control
Figure 2. New Product Development
• Circuit
Design
LSI Design
'Mesk
Pattem
Layout
• Process
and Product
Manufactu~ng
Statistical Approach
• Package
Design
Another approach to quality control is statistical analysis. NECEL uses statistical analysis at each stage of
LSI product development, trial runs, and mass production. These are some implementations of this statistical
approach:
• Process comparisons
• Control charts
• Data analysis
- Correlation, regression, multivariance, etc.
• Cp/Cpk studies
- Variables and attributes data (performed
monthly)
Process control sheets and other QC tools are used to
monitor important parameters such as Cp, Cpk, X, X-R,
electrical parameters, pattern dimensions, bond
strength, test percentage defects, etc. The results of
these studies are monitored by the production staff,
QC engineers, and other associated engineers. If any
out-of-control or out-of-specification limit is observed,
corrective procedures are quickly taken.
IMPLEMENTATION OF QUALITY CONTROL
Building quality into a product requires early detection
of possible failure mechanisms and immediate feedback to remove such problems. A fixed quality inspection station often cannot provide prompt and accurate
feedback about the process steps prior to the inspection. Quality control functions have therefore been
distributed into each process step including the conceptual stage. These are the most significant areas
where quality control has been placed:
•
•
•
•
•
•
•
•
Product development
Incoming material inspection
Wafer processing
Chip mounting and packaging
Electrical testing and infant mortality screening
Outgoing material inspection
Reliability assurance tests
Process/product changes
83Ro.7&12A
1-3
NEe
Reliability and Quality Control
Product Development
Incoming Material Inspection
New product development includes the product concept, device proposal review, physical element design
and organization, engineering evaluation, and, finally,
product transfer to manufacturi ng. Quality and reliability are considered at every step. The new product
development flow at NECEL is shown in figure 2.
NECEL has the following programs to control incoming
materials:
Design is the first and most important step in new
product development. NECEL believes that the foundation of device quality is determined at the design stage.
The four steps involved are circuit design, mask pattern
layout, package design, and the setting of process and
product manufacturing conditions. Design standards
have been established at NECEL to maximize quality
and reliability.
After completion of the design, a design review is
performed to check for conformity to design standards
and to consider other factors influencing reliability and
quality. At this stage, modification or re-design may be
necessary. NECEL believes that design reviews are
essential for product modifications as well as for newly
designed products.
Once a design successfully passes its review, a trial run
takes place in which the product's electrical and mechanical characteristics, quality, and reliability are
evaluated.
Additional runs are performed in which process conditions are varied deliberately, causing characteristic
factors to change in mass production. These samples
are evaluated to determine the best combination of
process conditions. Reliability tests are then conducted to check the new product's electrical and mechanical stress resistance. If no problems are found at
this stage, the product is approved for mass production.
Mass production begins after the product design department prepares a schedule that includes reliability
and quality control steps. The standards for production and control steps are continuously re-examined
for possible improvement, even after mass production
has started.
•
•
•
•
•
•
Vendor/material qualification system
Purchasing specifications for materials
Incoming materials inspection
Inspection data feedback
Meetings with vendors concerning quality
Vendor audits
If any parts or materials are rejected at incoming
inspection, they are returned to the vendor with a
rejection notification form specifying the failure items
and modes. The results of these inspections are used
to rate the vendors for future purchasing.
In-Process Quality Inspection
Typical in-process quality inspections performed at
wafer fabrication, chip mounting and packaging, and
device testing stages are listed in appendix 1A and
appendix 1B.
Electrical Testing and Screening
At the first electrical test, dc parameters are tested
according to electrical specifications on 100% of each
lot. This is a prescreening prior to any infant mortality
test. At the second electrical test, ac functional tests as
well as dc parameter tests are performed on 100% of
each lot. If the percentage of defective units in a lot is
unacceptably high in this test, the lot is subjected to an
infant mortality rescreen. During this time, any defective units undergo extensive failure analysis. The results of these analyses are fed back into the process
through corrective actions.
Figure 3 is a flowchart of the typical infant mortality
screening and electrical testing.
Outgoing Inspection
Prior to warehouse storage or shipment, lots are subjected to an outgoing inspection according to the
following sampling plan:
• Electrical
- Dc parameters, lot tolerance parts defective
(LTPD) 3%
-Ac functional LTPD 3%
• Appearance
- Major LTPD 3%
- Minor LTPD 7%
1-4
NEe
Reliability and Quality Control
Figure 3. Electrical Testing and Screening
• Dc parameter tesUng
• Full Ac/dc testing ff
nc 100% bum·ln
tain period of time. The concept of probability, the
definition of required function, and the knowledge of
how time affects the item of concern are therefore
necessary tools for the study of reliability.
Definition of a required function, by implication, treats
the definition of a failure. Failure of a device is defined
as the termination of a device's ability to perform its
required function. A device has failed if it is unable to
meet guaranteed values given in its electrical specifications.
• When raqulred
• Dc parameter tesUng
• Ac IuncUcnaI testing
No
Failures are categorized by the period of time in which
they occur. The critical times used in the discussion of
device reliability and failure are the periods of early,
random, and wearout failures. Probability is used to
quantitatively estimate reliability levels during these
periods as well as overall reliability. The relevant theories and methods of calculation will be discussed later.
Regarding individual devices, specific failure mechanisms seen in life tests and in infant mortality screening
tests are the parameters of concern in the determination of overall device failure rates, thus reliability levels.
• Electrical tesls
• Appaarance
• Dimensions
Regarding systems, the sum of individual device failure
rates is the expected failure rate of the system hardware.
83~7511A
Reliability Assurance Tests
Prior to shipment, representative samples from each
process family are taken on a regular basis and subjected to monitoring reliability tests. This testing is
performed to confirm that NECEL.:s products continuo
ally meet their field reliability targets.
Life Distribution
The fundamental principles of reliability engineering
predict that the failure rate of a group of devices will
follow the well-known bathtub curve in figure 4.
Figure 4. Reliability Ute (Bathtub) Curve
Process/Product Changes
As mentioned previously, a design review occurs for
product changes as well as for new products. Once a
design is approved and processes are altered for max·
imum quality, qualification testing is performed to
check reliability. If the test results are acceptable, the
product is internally qualified for mass production.
The typical reliability qualification tests performed at
NECEL are listed in appendix 3.
RELIABILITY THEORY
Wearout
Period
Random Fallura Period
l!i
~
~------------------------------~~
llme
Reliability is defined as a characteristic of an item
expressed by the probability that it will perform a
required function, under specific conditions, for a cer-
1-5
Reliability and Quality 'Control
The curve is divided into three regions: infant mortality,
random failures, and wearout failures.
The infant mortality sectiop. of the curve, where. the
failure rate is declini ng rapidly, represents the early-life
device failures. These failures are usually associated
with one or more manufacturing 'defects.
After a period of time, the failure rate reaches ai.ow
value. This random failure area of the curve represents
the useful portion of a device's life. During this random
failure period, a slight decline is observed due to the
depletion of potential random failures from the general
population.
Wearout failures occur at the end of useful device life.
These failures are observed in the rapidly rising failure
rate portion of the curve; devices are wearing out both
physically and electrically.
Therefore, for a device that has a very long life expectancy compared to the system that contains it, the
areas of concern will be the infant mortality and random failure portions of the bathtub curve.
Failure Distribution at NECEL
To eliminate infant mortality failures, NECEL subjects
its products to production burn-in whenever necessary.
This burn-in is performed at an elevated temperature
on 100% of the devices involved and is designed to
remove potentially defective units.
After elimination of early device failures: a system will
be left to the random failures of its components. To
make proper projections. of the fqilure rate,of a system
in the operating environment, random failure rates
must be predicted for the system's components.
To qualitatively study random failures, integrated circuits returned from the field, as well as in-house life
testing failures, undergo extensive failure analyses at
respective NEC manufacturing divisions. Failure mechanisms are identified and resulting data is fed back to
appropriate production and engineering groups. Longterm failure rates are determined from this data to
quantitatively study this random failure population.
Infant Mortality Failure Screening
Establishing infant mortality screening requires knowledge of likely failure mechanisms and their associated
activation energies.
1-6
NEe
Typical problems associated with infant mortality failures are manufacturing defects and process anomalies, which' consist of contamination, cracked chips,
wire bond shorts, or bad wire bonds. Since these
problems can result from a number of possible failure
mechanisms, the activation energy for infant mortality
can vary considerably. Correspondingly, the effectiveness of an infant mortality screening condition (preferably at some stress level to shorten the screening
time) varies greatly with the failure mechanism.
For example, failures due to ionic contamination have
an activation energy of approximately 1.0 eV. Therefore, a 15-hour stress at 125°C junction temperature
would be the equivalent of approximately 314 days of
operation at a junction temperature of 55°C. On the
other hand, failures due to oxide defects have an
activation energy of approximately 0.3 eV. A 15-hour
stress at 125°C junction temperature in this case would
be the equivalent of approximately 4 days of operation
at 55°C junction temperature. The condition and duration of infant mortality screening is determined by the
economic factors involved in the screening and by the
allowable rate of component failure. A component
failure causes a system failure.
Empirical data gathered at NECEL indicates that any
early failures generally occur after less than 4 hours of
stress at 125°C ambient temperature. This fact is supported by the bathtub curve created from actual life
test results. The failure rate after 4 hours of such stress
testing shows random distribution as opposed to the
rapidly decreasing failure rate observed in the early life
portion of the curve.
Whenever' necessary, NECEL has adopted this infant
mortality burn-in at 125°C as a standard production
screening procedure. NECEL believes it is imperative
that failure modes associated with such infant mortality sc~eens be understood and fixed at the manufacturing level. Failure analysis is performed on all infant
mortality failures for this purpose. This in-line data
coupled \\lith data accumulated from the field is used to
introduce corrective actions and quality improvement
measures. If the early-life failures of a device can be
minimized or eliminated and countermeasures appropriately monitored, then such screens can be eliminated. The result of such practices is that field reliability of NECEL devices is an order of magnitude higher
than NECEL's long-term failure rate goals.
NEe
Table t.
Reliability and Quality Control
Typical Reliability Test Results
Name
Type
HTB (1000H)
T/H (1000H)
PCT (192H)
T/C (300)
Micro
(Note 1)
NMOS
9/26169
(13 FIT)
3/15977
0/16928
0/3542
CMOS
7/29829
(4.3 FIT)
7/23123
0/23275
0/12238
1 Meg DRAM (Note 2)
44/38217
(43 FIT)
0/18210
0/6320
0/11300
4 Meg DRAM (Note 3)
12/8085
(2.2 FIT)
1/2866
0/2100
0/2020
256K SRAM (Note 4)
1/2812
(22 FIT)
1/2562
0/1900
0/3232
1 Meg SRAM (Note 4)
0/2136
(1.25 FIT)
2/1959
0/1080
0/1375
CMOS
7/8787
(21 FIT)
0/3577
5/13971
6/9693
BiCMOS
3/2801
(29 FIT)
0/3601
0/4535
0/5825
Memory
(HTOL)
ASIC
(Note 5)
Note:
Information in the table above has been extracted from NECEL report
numbers:
(1) IRQ-3Q-24163
(4) TRQ-93-07-0165
(2) TRQ-93-01-0142
(5) TRQ-93-07 -0163
(3) TRQ-93-01-0141
Accelerated Reliability Testing
NECEL performs extensive reliability testing at both
pre-production and post-production levels to ensure
that all products meet NECEL:s minimum expectations
and those of the field.
Assume an electronic system contains 1000 integrated
circuits and that 1% system failures per month can be
tolerated by this system. The allowable failure rate per
component is then calculated as follows:
1% failures
720 hours x 1000 pieces
(0.0014) % failures
1000 hours
14 FITs
The rate of 14 FITs corresponds to one failure in 85
devices during an operating test of approximately
10,000 hours. To demonstrate this reliability level in a
reasonable amount of time, a test condition is apparently required to accelerate the time-to-failure in a
predictable and understandable way.
The most common method for decreasing time-tofailure is the use of high temperature to accelerate
physiochemical reactions that can lead to device failure. Other stressful environmental conditions are voltage, current, humidity, vibration, or some combination
of these. Appendix 2 lists typical accelerated reliability
assurance tests performed at NECEL on molded integrated circuits. Table 1 shows the results of some of
these tests for various process types.
Reliability Assurance Tests
NECEL:s life tests consist of the high-temperature
operating/bias life (HTOL/HTB), the high-humidity storage life (HHSL), the high-temperature, high-humidity
(17H = HHSL + bias), and the high-temperature storage
life (HTSL). Additionally, NECEL performs various environmental and mechanical tests.
HTOL/HTB Test. These tests are used to accelerate
failure mechanisms by operating devices in a dynamic
(operating life) or static (bias) condition at an elevated
temperature of 125°C. The data obtained is translated
to a lower temperature to estimate device life expectancy using the Arrhenius relationship explained later.
1-7
Reliability and Quality Control
HHSL and 17H Tests. Integrated circuits are extremely
sensitive to the effects of humidity such as electrolytic
corrosion between biased lines. The high-temperature
and high-humidity tests are performed to detect failure
mechanisms accelerated by temperature and humidity,
such as leakage related problems and drifts in device
parameters due to process instability.
HTSL Test. Another common test is the high-temperature storage life test in which devices are subjected to
elevated temperatures with no applied bias. This test is
used to detect process instability and stress migration
problems.
Environmental Tests. Other environmental tests such
as the pressure cooker test (PCn or the temperature
cycling test (TIC) detect problems related to the package and/or interactions between materials as well as
the degradation of environmentally sensitive device
characteristics.
Failure Rate Calculation/Prediction
To predict the device failure rate from accelerated life
test data, the activation energies of the failure mechanisms involved should be considered. In some cases,
an average activation energy is assumed to accomplish a quick first-order approximation. NECEL assumes an average activation energy of 0.7 eV or 0.45 eV
for most products (0.3 eV for high-density memory
devices). These val ues have been assessed from extensive reliability test results and yield conservative failure
rates.
Since most semiconductor failures are temperature
dependent, the Arrhenius relationship is used to normalize failure rate predictions at a system operation
temperature of 55°C. It assumes that temperature dependence is an exponential function that defines the
probability of failure occurrence, and that degradation
of a performance parameter is linear with time. The
Arrhenius model includes the effects of temperature
and activation energies of the failure mechanisms in
the following Arrhenius equation:
A = exp-EA(TJ1 -TJV
k(TJ1)(TJV
Where:
Am = Acceleration factor
EA = Activation energy
TJl = Junction temperature (in K) at TAl = 55°C
TJ2 = Junction temperature (in K) at TA2 = 125°C
k = Boltzmann's constant = 8.62 x 10-5 eV/K
1-8
NEe
Because the thermal resistance and power dissipation
of a particular device type cannot be ignored, junction
temperatures (TJl and TJ2) are used instead of ambient
temperatures (TAl and TA2)' We calculate junction temperatures using the following formula:
TJ = TA + (thermal resistance)(power diss; at TN
With this information, a temperature acceleration factor can be calculated.
In some cases, the effect of voltage acceleration on
failure rate must also be considered. Voltage acceleration can be characterized by the following equation:
A(V) = exp [-f3(Vd - Vs)]
Where:
Vd = Operating voltage (5.5 V)
Vs = Life test stress voltage (7 V)
f3 = Empirically determined constant (dependent on
electric field constant and oxide thickness)
The constant f3 has been given the value"" 1, which is
a conservative figure. Therefore, the overall acceleration factor will be determined as the product:
A(T,V) = Am * A(V)
To estimate long-term failure rate, the acceleration
factor must be multiplied by the actual time to determine the simulated test time. From the hightemperature operating or bias life test results, failure
rates can then be predicted at a 60% confidence level
using the following equation:
L = (X2)1Q5
2T
Where:
L = Failure rate in %/1000 hours
X2 = The tabular value of Chi-squared distribution at a
given confidence level and calculated degrees of
freedom (21 + 2, where f = number of failures)
See note below.
T = # of equivalent device hours = (# of devices) x (#
of test hours) x (acceleration factor)
Note: Since the failures of concern here are the long-term
failures, not the infant mortality failures (that is, the end
of the downward slope and the middle constant section of the bathtub curve in figure 4), X2 is determined
by assuming a one-sided, fixed time test.
Another method of expressing failures is in FITs (failures in time). One FIT is equal to one failure in 109
hours. Since L is already expressed as %/1000 hours
(10- 5 failure/hr), an easy conversion from %/1000 hours
to FIT would be to multiply the value of L by 104.
NEe
Reliability and Quality Control
To accurately determine this failure rate, a statistically
large sample size must be accumulated. Depending on
the accuracy needed, the following conditions should
be imposed:
• A minimum of 1.2 million device hours (equal to
sample size multiplied by test period) at 125°C
should be accumulated to accurately predict a failure rate of 0.02% per 1000 hours at 55°C, with a 60%
confidence level.
• A minimum of 3 million device hours at 125°C should
be accumulated to accurately predict a failure rate
of 0.01% per 1000 hours at 55°C, with a 60% confidence level.
Failure Rate Calculation Example. As an example of
how this failure rate is calculated, assume a sample of
960 pieces was subjected to 1000 hours at 125°C burnin. One reject was observed. Given that the acceleration factor was calculated to be 34.6 using the Arrhenius equation, what is the failure rate normalized to
55°C using a confidence level of 60%. Express the
failure rate in FITs.
Solution:
For n = 2f
Then L
+
=
2
= 2(1) + 2 = 4, X2 = 4.046
(X2)105
(%/1000 hours)
2T
(X2)105 (%/1000 hours)
2(# devices)(# test hours)(accel. factor)
(4.046)105
2(960)(1000)(34.6)
Therefore, FIT
=
= 0.0061
(0.0061)(104)
(%/1000 hours)
= 61
Failure Rate Goals
Outgoing electrical and mechanical quality levels, as
well as mortality and long-term failure rates, are monitored and checked against quality and reliability targets. Long-term failure rate goals are based on mask
and process designs. NECEL's quality and reliability
targets are listed in tables 2 and 3.
Table 2. HECEL Quality Targets
OutgOing Electrical (PPM)
OutgOing Mechanical (PPM)
BIPolar
BiPolar
CMOS
ASIC
Micro
System
Micro
CMOS
ASIC
ECl
BiCMOS
RAM
G/A
G/A
80
Year
Memory
Micro
System
Micro
1993
10
60
50
50
80
300
80
10
60
50
50
80
300
1994
3.4
40
40
10
80
300
80
3.4
40
40
10
80
300
80
1995
3.4
40
30
5
80
150
50
3.4
40
30
5
80
150
50
ECl
BiCMOS
RAM
G/A
G/A
Memory
Table 3. HECEL Reliability Targets
Infant Mortality (FIT)
long-Term Reliability (FIT)
BiPolar
CMOS
ASIC
BiPolar
Year
Memory
Micro
System
Micro
1993
10
40
50
100
50
300
80
10
30
100
50
30
300
80
1994
3.4
30
40
50
50
300
80
3.4
20
100
10
30
300
80
1995
3.4
30
30
10
50
150
50
3.4
20
100
5
30
150
50
ECl
BiCMOS
RAM
G/A
G/A
Memory
Micro
System
Micro
CMOS
ASIC
ECl
BiCMOS
RAM
G/A
G/A
1-9
NEe
Reliability and Quality Control
FAILURE ANALYSIS
SUMMARY
At NECEL, failure analysis is performed not only on
reliability testing and field failures, but also on products that exhibit defects during production. This data is
closely checked for correlation process quality information, inspection results, and reliability test data.
Information derived from these failure analyses is fed
back into the process.
Building quality and reliability into products by forming
a total quality control system is the most efficient way
to ensure product success.
Since many failure mechanisms can be exhibited by
LSI devices, highly advanced analytical tools and
methodologies are required to investigate such LSI
failures in detail. The standard failure analysis flowchart relating to the returned products from customers
is shown in appendix 4.
Special Grade Devices
Some applications require a wider temperature range
and/or higher reliability than most, such as medical or
safety equipment, transportation control systems, etc.
For these requirements, NEC offers special grade devices based on a mutual quality agreement. The typical
differences between special and standard grade devices are shown in table 4. NEC's quality and reliability
targets for grade (A) microprocessor/controller products are shown in table 5.
The combination of building quality into products,
effective prescreening of potential failures, and monitoring of reliability through extensive testing has established a singularly high standard for NECEL's largescale integrated circuits.
The company's quality control program supports research and development activities, failure analyses,
and process improvements. With this extensive program, NECEL continuously sets and maintains higher
standards of quality and reliability.
Table 4. Standard Grade and Special Grade
Differences
Item
Standard Grade
Special Grade
Reliability Evaluation
HTB,17H
HTS
> 1000 hours
>2000 hours
17C
> 100 cy
>300 cy
PCT
> 96 hours
> 192 hous
Quality
Standard quality
control steps
Special control when
necessary
Screening
Standard burn·ln
Increased burn·in time
Electrical
testing
Standard
Addition of high
temperature testing (if
not performed already)
Storage
life
3 years
5 years
Table 5. Grade fA) Micro Reliability and Quality
Targets
1-10
Quality/ReI. Item
1993
1994
1995
Outgoing electrical (PPM)
10
3.4
3.4
Outgoing mechanical (PPM)
10
3.4
3.4
Infant mortality (FIl)
10
5
5
Long term rei. (FIT)
10
5
5
N EC
Appendix tA.
Reliability and Quality Control
Typical QC Flow for CMOS Fabrication
Wafer Fabrication Process QC Flow (CMOS)
Row
Process Material
In-process Inspection/quality Monitor
Silicon Wafer
Incoming
Inspection
Resistivity (sampling by lot)
Dimension (sampling by 101)
Visual (sampling by lot)
Well
FormaUon
Oxidation
Photo Uthography
Ion Implantation
Oxide thickness (sampling by lot)
Alignment and elchlng accuracy (sampling by lot)
Leyer resistance (sampling by lot)
Reid
FormaUon
DeposlUon
Photo Lllhography
OxldaUon
Deposit thickness (sampling by lot)
Alignment and etching accuracy (sampling by lot)
Oxide thickness (sampling by lot)
Channel Stopper
FonnaUon
Photo Uthography
Ion ImplantaUon
Oxidation
Alignment and elchlng accuracy (sampling by lot)
Leyer resistance (sampling by lot)
Oxide thickness (sampling by lot)
Gate
Formation
Deposition
Doping
Photo Uthography
Deposit thickness (sampling by lot)
Layer resistance (sampling by lot)
Alignment and etching accuracy (sampling by lot)
Gate electrode width (sampling by lot)
pin SD Formation
Pholo Uthography
Ion Implantation
Anneal
Alignment and etching accuracy (sampling by lot)
Leyer resistance (sampling by lot)
Contact
Hole
DeposlUon
Photo Uthography
Deposit Ihlckness (sampling by lot)
Alignment and etching accuracy (sampling by 101)
Metallization
Metal Deposition
Photo Uthography
Alloy
Metal thickness (sampling by lot)
Alignment and etching accuracy (sampling by lot)
ParamelMc lest (sampling by lot)
PasslvaUon
Deposition
Photo Uthography
Wafer Sort
Deposit thickness (sampling by lot)
Alignment and etching accuracy (sampling by lot)
Electrical tesl
Contacl hole and metallization sleps are repeated twice.
83RO-7509B
1-11
NEe
Reliability and. Quality Control
Appendix 1B.
Typical QC Flow for PLCC Assembly/Test
InspecUon of Manufactu~ng Qualities
InspecUon of Manufacturing CondlUons
Process/Mate~als
1
So~dWafers
2
Wafer Visual
3
Dicing
4
Break and Expand
5
Ole Visual Inspeellon
Inspection
Ilem
Frequency
Instrument
Inspected
by
Inspection
Item
Frequency
Instillment
Inspected
by
Wafer Visual
100%
Naked Eye
Operalor
Table Speed
01 Water
Blade Height
Every
Shift
Indlcalors
Gauges
P.C.
Sawing
Dimensions
Before
Running
Microscope
WllhRller
Eyepiece
Operator
WalerBreak
Condilions
Every
Shift
Indicators
Gauges
P.C.
Wafer Visual
100%
Naked Eye
Operator
Ole
Visual
Every Lot
Sampnng
(Or 100%)
Microscope
Operator
Ole Visual
Epoxy
Coverage
Every
Magazine
Naked Eye
Operator
Every Shift
Microscope
Wafer Expand
Conditions
Lead Frames
Ole Attached
Conditions
7
Ole Attached
Temperature
Epoxy Cure
(Not Done for Gold
Ole Attached product)
Heat
Temperature
N2 FIow
Every
Shift
Indicators
Gauges
P.C.
8
Shear
Strength
Every
Shift
Bonding
Conditions
Every
Shift
Indicators
P.C.
Visual
Every
Magazine
Microscope
Operator
Temperature
Every
Week
Thermocouple
and
Potentiometer
P.C.
Wire Pull
Test
Every
Shift
Tension
Gauge
Operator
Ole
VIsual
Every Lot
Sampling
(Or 100%)
Microscope
Inspeclcr
Visual
100%
Naked Eye
Operator
Visual
Every Lot
Naked Eye
Operator
6
9
Fine Wire
10
Wire Bonding
11
Pre·Seal Visual
Inspeellon
~
13
Molding Compound
Molding
. Temperature
of Pellet,
ExplraUon Date
Temperature
Proflleof
Ole Set
Every
Shift
Indicators
Thermocouple,
Potentiometer
P.C.
Thermocouple
P.C.
Every Shift Thermocouple,
Potentiometer
P.C.
Every
Shift
Dynamometer Operator
Preheat
Temperature
Pressure
Cure Time
14
Mold Aging
Temperature
Every Shift
Indlcetor
P.C.
Indicators
P.C.
Denashlng
Deflashlng
Conditions
Every Shift
15
TltraUon
Tech.
Concentration Every Week
Density
16
PlaUng
Every Week Density Meter
Tech.
Water Jet
Pressure
EveryDay
Gauge
Tech.
Plating
Conditions
EveryDay
Indicators
P.C.
TltraUon
Tech.
Concentration Every Week
83RD-75168
1·12
NEe
Appendix lB.
Reliability and Quality Control
Typical QC Flow for PLCC Assembly/Test (cont)
Inspection of Manufacturing Conditions
ProcessiMatenals
17
~
Inspection
Item
Marking Ink
Marking
20
Mark Cure
21
Lead Forming
Inspectlon of Manufacturing Qualities
Inspected
by
22
Rnal Assembly Inspection
23
Rrst Electrlcal Sorting
24
Burn-In (When Necessary)
25
Rrst Electrlcal Sorting
26
Reliability Assurance Test
In-Warehouse Inspection
Inspection
Item
Frequency
Instrument
Inspected
by
Visual
Plating
Thickness
Composition
Solderability
Every Lot
Naked Eye
Technician
Every Lot
Every Lot
Once/Day
X-ray
X-ray
Naked Eye
Technician
Technician
Technician
Marking
CondlUons
Every Shift
Indicators
P.C.
Visual
Every Lot
Naked Eye
Operator
Temperature
Every
Shift
Thermocouple
P.C.
Marking
Permanency
Twice/Shift
Automatic
Operalor
Every Shift
(Before
Running)
Test Jig.
caliper
VIsual
Every Lot
Naked Eye
Operator
Visual
Every Lot
Magnifying
Lamp
Operator
Electrical
Characteristics
100%
ICTester
Operator
Electrical
Characteristics
100%
ICTester
Operator
Electrical
Characteristics
Every Lot
ICTester
Inspector
Visual (Major)
Every Lot
Naked Eye
and
Microscope
Inspector
Visual (MInor)
Every Lot
Naked Eye
Inspector
Dimensions
28
Instrument
Plating Inspection
19
27
Frequency
Operator
P.M. Check
Every Day
P.M. Jig.
Sample
Check
Before
Testing
Test
Samples
8um~ln
Every
Batch
Indicator
P.C.
Every Day
P.M. Jig.
Before
Testing
Test
Samples
Operator
Operetor
Conditions
Operator
Operator
Tester
Every
Monlh
Every Day
P.M. Jig.
Before
Testing
Test
Samples
Warehousing
83RD-7516B
1-13
NEe
Reliability and Quality Control
Appendix 2. Typical Reliability Assurance Tests
Test
High-temperature operating/bias life (Note 1)
High-temperature storage life (Note 1)
High-temperature/high-humidity (Note 1)
Symbol
MIL-STD-883C
Method
Test Conditions
HTOL/HTB
1005
TA = 125'C; VDD specified per device type
HTSL
1008
TA = 150'C (175' or 200'C in some cases)
T/H
High-humidity storage life (Note 1)
TA
= 85'C;
RH
= 85%; VDD = 5.5 V
HHSL
TA = 85'C; RH
=
Pressure cooker (Note 1)
PCT
TA = 125'C; P
=
Temperature cycling (Note 1)
T/C
1010
85%
2.3 atm; RH
=
100%
-65'C to +150'C; 1 hour/cycle
Lead fatigue (Note 2)
C3
2004
gO-degree bends; 3 bends without breaking
Solderability (Note 3)
C4
2003
230'C; 5 sec; rosin base flux
Soldering heat/temperature cycle/
thermal shock (Note 1)
C6
1010
1011
(Note 4)
10 sec @ 230'C; rosin base flux
Ten I-hour cycles @ -65'C to +150'C
Fifteen 10-minute cycles @ O'C to +100'C
Notes:
(1) Electrical test per data sheet is performed. Devices that exceed
the data sheet limits are considered rejects.
(2) Broken lead is considered a reject.
(3) Less than 95% coverage is considered a reject.
(4) MIL-STD-750A, method 2031.
Appendix 3. New ProducUProcess Change Tests
Newly
Developed
Product
Shrink
Die
New
Package
Test Conditions
Test
Sample Size
Wafer
Assembly
High-temperature
operating/bias life
20 - 50 pieces;
1 -lots
0
0
0
0
0
See appendix 2;
1000H
High-temperature
storage life
10 - 20 pieces;
1 - 3 lots
0
0
0
0
0
T = 150'C (plastic);
T = 175'C (ceramic);
1000H
High-temperature/
high-humidity bias life
(plastic package)
20 - 50 pieces;
1 - 3 lots
0
0
0
0
0
See appendix 2;
1000H
Pressure cooker
(plastic package)
10 - 20 pieces;
1 - 3 lots
0
0
0
0
0
See appendix 2; 288H
Thermal environmental
10 - 20 pieces;
1 - 3 lots
0
X
0
X
0
See appendix 2
Mechanical environmental
(ceramic package)
10 - 20 pieces;
1 - 3 lots
0
X
0
X
0
20G, 10 - 2000Hz;
1500G, 0.5 ms;
20000G, 1 min
Lead fatigue
5 pieces; 1 - 3
lots
X
X
X
See appendix 2
Solderability
5 pieces; 1 - 3
lots
X
X
X
See appendix 2
ESD
20 pieces; 1 - 3
lots
0
0
0
X
(1) C = 200 pF, R
(2) C = 100 pF,
R = 1.5 k
Long term T/C
10 - 50 pieces;
1 - 3 lots
0
0
0
0
See appendix 2;
1000 cy
Notes:
0: Performed.
1-14
X: Perform if necessary.
-: Not performed.
0
=0
NEe
Reliability and Quality Control
Appendix 4_ Failure Analysis Flowchart
1+-----
Information requested
• Failure sltuaUon:
where, how, when, why
• Delac funcUon tesUng
by lesler/Curvetracer
Yes
• Test correlation
may be needed
• Speciflc tests: X-ray fluoroscope,
hermetical test, dew-polnt test,
curve tracer check, etc.
• Decapsulation, Intemal visual
check, 9lect~cal measurement,
drouH analysis
• Etching the pesslvallon, etc.
SEM, XMA, Cross-secUon, etc.
• EsUmaUon of causes
• Countenneasures
• CorrecUve ActIon
83R[).761M
1-15
Reliability and Quality Control
1-16
NEe
NEe
IIPD78COO
NEe
pPD78COO Product Line
Section 2
"PD78COO Product Line
a-Bit, Single-Chip Microcontrollers
"PD78C14 Family
(pPD78C10A/C11 A/C12A/C14/C14A/CP 14)
8-Bit, Single-Chip Microcontrollers
With AID Converter
2-a
"PD78C18 Family
(pPD78C17/C18/CP18)
8-Bit, Single-Chip Microcontrollers
With AID Converter
2-b
"PD78COO Product Line
Programming Reference
2-c
NEe
NEG Electronics Inc.
pPD78C14 Family
(pPD78C10A/C11A/C12A/C14/C14A/CP14)
8-Bit, Single-Chip Microcontrollers
With A/D Converter
September 1993
Description
Features
This family of microcontrollers integrates sophisticated on-chip peripheral functions normally provided
by external components. Their internal 16-bit ALU and
data paths, combined with a powerful instruction set
and addressing, make the devices appropriate in data
processing as well as control applications.
o CMOS technology
- 25 mA operating current
(78C10A/C11A/C12A)
-30 mA operating current (7SC14/C14A)
The devices integrate a 16-bit ALU, 4K, SK, or 16K-byte
ROM, 256-byte RAM, an eight-channel A/D converter, a
multifunction 16-bit timer/event counter, two S-bit timers, a USART, and two zero-cross detect inputs on a
single die, allowing their use in fast, high-end processing applications. This involves analog signal interface
and processing.
The pPD7SC14 family includes: 4K, SK, and 16K-byte
mask ROM devices, embedded with a custom customer program; ROMless devices for use with up to
64K-bytes of external memory; and 16K-byte EPROM or
OTP ROM devices for prototyping and low-volume
production. The pPD7SC11A/C12A/C14A also have
mask optional puliup resistors available on ports A, B,
andC.
o Complete single-chip microcontroller
-16-bit ALU
-4K, SK, or 16K x S ROM
- 256-byte RAM
o 44 I/O lines
o Mask optional pullup resistors
- Ports A, B, and C (j.iPD7SC11 A/C12A/C14A only)
o Two zero-cross detect inputs
o Two 8-bit timers
o Expansion capabilities
- SOS5A-like bus
- 60K-byte external memory address range
o Eight-channel, S-bit A/D converter
- Autoscan mode
- Channel select mode
o Full-duplex USART
- Synchronous and asynchronous
o 159 instructions
-16-bit arithmetic, multiply, and divide
- HALT and STOP instructions
o O.S-ps instruction cycle time (15-MHz operation)
o Prioritized interrupt structure
- Three external
- Eight internal
o Standby function
o On-chip clock generator
50604
_
.
•
I
NEe
pPD78C14 Family
Ordering Information
Part Number (Note 1)
Package
Package Drawing
Quality Grade (Note 3)
ROM/ess
IlPD78C10ACW
AGF-3BE
64-pln SDIP
P64C-70-750A, C
Standard
64-pin QFP (Note 2)
P64~F-100:3B8, 3BE-1
Standard
64-pin QUIP
P64GO-l00-36
68-pin PLCC
P68L-50Al -1
Special
AGF(A)-3BE
AGQ-36
AL
Standard
Special
AGQ(A)-36
Standard
Special
AL(A)
4KMaskROM
64-pin SDIP
P64C-70-750A, C
Standard
64-pin QFP (Note 2)
P64GF-l00-3B8,3BE-l
Standard
64-pin QUIP
P64GQ-l00-36
AGQ-xxx-37
64-pin QUIP (straight)
P64GQ-l00-37
AL-xxx
68-pin PLCC
P68L-50Al -1
IlPD78Cll ACW-xxx
AGF-xxx-3BE
Special
AGF(A)-xxx-3BE
AGQ-xxx-36
Standard
Special
AGQ(A)-xxx-36
Standard
Standard
Special
AL(A)-xxx
BKMaskROM
IlPD78Cl2ACW-xxx
64-pin SDIP
P64C-70-750A, C
Standard
AG-xxx-37
64-pin QUIP (straight)
P64GQ-l00-37
Standard
AG-xxx-36
64-pin QUIP
P64GO-l00-36
Standard
AGF-xxx-3BE
64-pin QFP (Note 2)
P64GF-l00-3B8, 3BE-l
Standard
AL-xxx
68-pin PLCC
P68L-50A 1-1
Standard
Special
AG(A)-xxx-36
Special
AL(A)-xxx
16K Mask ROM
IlPD78C14AG-xxx-AB8
64-pin QFP
P64GC-80 -AB8-2
CW-xxx
64-pin SDIP
P64C-70-750A, C
G-xxx-36
64-pin QUIP
P64GQ-l00-36
G-xxx-37
64-pin QUIP (straight)
P64GQ-l00-37
G-xxx-1B
64-pin QFP (Note 2)
P64G-l00-12,lB-l
GF-xxx-3BE
64-pln QFP (Note 2)
P64GF-l00-3B8, 3BE-l
L-xxx
68-pin PLCC
P68L-50Al -1
Standard
16KOTPROM
IlPD78CP14CW
2
64-pin SDIP
P64C-70-750A, C
G-36
64-pin QUIP
P64GQ-l00-36
G-37
64-pin QUIP (straight)
P64GO-l00-37
GF-3BE
64-pin QFP (Note 2)
P64GF-l00-3B8, 3BE-l
L
68-pin PLCC
P68L-50Al -1
Standard
NEe
IIPD78C14 Family
Ordering Information (cont)
Part Number (Note 1)
Package
Package Drawing
Quality Grade (Note 3)
16KUVEPROM
J.lPD78CPI4_D_W_ _ _ _ _ _ _ _
64_--'-p_in_C_E_R_S_D_IP_w-'-'w_in_d_ow
______
P6_4_D_W_-_7_0_-7_5_0A
_ _ _ _ _ _ Standard
R
64-pin CER QUIP w/window
P64RQ-tOO-A
64-pin QUIP
P64GQ-l00-36
16K OTP ROM
J.lPD78CPI4G(A)-36
Special
-
Notes:
(1) xxx indicates ROM code suffix
(2) Engineering samples supplied in a ceram ic QFP package
(3) Special grade devices have the symbol (A) embedded in the part
number
Pin Configurations
64-Pin QUIP or SDIP (Plastic or Ceramic)
PAl
VDO
STOP
PA2
P07
PAo
PA3
POe
PA4
PD5
PA5
PD4
PAe
PD3
PA7
PD2
PBo
PDt
PBl
PDO
PB2
PF7
PB3
PFe
PB4
PF5
PB5
PF4
PBe
PF3
PB7
pcorrxo
PF2
PCI/AxO
PFI
PC2/SCK
PFo
ALE
PC3ITVINT2
WR
PC4ITO
PC5/CI
PCe/COO
PC7/C01
NMI
RD
AVDD
VAREF
AN7
AN6
INTI
AN5
MODEl
AN4
RESET
AN3
MODEO
AN2
X2
ANt
XI
ANO
Vss
AVSS
83YL-9251A·7/93
3
NEe
pPD78C14 Family
Pin Configurations (cont)
64-Pin QFP (20mm x 14mm)
., .. '" '"
~
0
ell!> ... co ., .. '"
D':D':D':D':D':D':~!ii~~~~~
PAe
P02
0
SO
POl
3
49
PBl
4
48
POo
PF 7
PB2
S
47
PB3
4e
PF6
PF S
PB4
6
7
4S
PF4
PBs
8
PF3
PB6
9
44
43
42
41
40
39
36
37
36
3S
34
33
PA7
2
PBo
PB7
pcorrxo
10
PC1/Rxo
12
11
PC2/SCK
13
PC3/1NT2
14
pC4rro
lS
PCS/CI
16
PCe/COO
17
PC7/COl
18
NMI
19
o
~
1::1
~ ~ tq~l\irere~ ~ !;j
~
wltii
,-UJUlO ..... '" '"
z z
1O!:! x~:r~~~ <
<
'" '"
-8ffl8
::;; a: ::;;
PF2
PF 1
PFo
ALE
WR
R5
AVoo
VAREF
AN7
AN6
AN5
..
83YL-9605B
4
NEe
pPD78C14 Family
Pin Configurations (cont)
64-Pin QFP (14mm x 14mm)
~UIl"'
Q gl~ I~ ~ ~
.... (II)CN,..O
... u:.." .... CON.,...O .....
~~~ln~~~fffffffff
;Zl3fl1lDli!fllll!t;II!:8~~&lr;;~!I
PC7/C01
PA5
INTI
PA4
MODE1
PA3
RESET
PA2
MODED
PA1
X2
PAD
41
X1
Vss
VDD
STOP
AVss
AND
PD7
AN1
PDs
AN2
PD4
AN3
PD3
PDa
AN4
AN5
-
PAa
0
NMI
PD2
18
~~~2·C\i~fJ"~letit!lg:~(;PJ
PD1
I ~ >«~ 1I 5! I~ ~ ~ If tf' If' It If l It i
1
5
NEe.
pPD78C14 Family
Pin Configurations (cont)
6B-PinPLCC
PA7
PBo
PS1
PB2
PB3
PB4
PB5
PBe
POo
PF7
PFe
PFs
PF4
PFa
PF2
~
PF1
PCorrxo
PFo
PC1IRXO
PC21SCK
PCsIIVINT2
ALE
WR
IC
PC.tno
~ICI
PCeICOo
6
P01
RO
AVOO
Ie
VAREF
ANT
NEe
pPD78C14 Family
Pin Identification
PIN FUNCTIONS
Symbol
Function
ALE
Address latch enable output
ANO-AN7
AID converter analog inputs 0-7
ALE (Address Latch Enable). The ALE output is
used to latch the address of PDo - PD7 into an external
latch.
INT1
Interrupt request 1 input
MODEO
Mode 0 input; I/O memory output
MODE1
Mode 1 input
NMI
Nonmaskable interrupt input
PortA 1/0
Port B I/O
PCoITxD
Port C I/O line 0; transmit data output
Port C I/O line 1; receive data input
PC:!/SCK
Port C I/O line 2; serial clock I/O
PCalTI/INT2
Port C I/O line 3; timer input; interrupt request
2 input
PC4fTO
Port ClIO line 4; timer output
PCs/CI
Port C I/O line 5; counter input
Port C I/O lines 6, 7; counter outputs 0, 1
PDo- PD]
Port D I/O; expansion memory address, data
bus (bits ADo - AD7)
Port F I/O; expansion memory address,
(bits ABa - AB1sl
RD
Read strobe output
STOP
Stop mode control input
Reset input
AID converter reference voltage
WR
Write strobe output
X1,X2
Crystal connections 1, 2
AVoo
AID converter power supply voltage
AVss
AID converter power supply ground
Voo
5 V power supply
Vss
Ground
IC
Internal connection
ANO-AN7 (Analog Inputs). These are the eight analog
inputs to the A/D converter. AN4-AN7 can also be used
as a digital input for falling edge detection.
CI (Counter Input).
event counter.
External pulse input to timer/
COo, C01 (Counter Outputs). Programmable waveform outputs based on timer/event counter.
INT1 (Interrupt Request 1). INT1 is a rising edge
triggered, maskable interrupt input. It is also an acinput, zero-cross detection terminal.
If the optional pullup resistor is specified for this pin on
the pPD78C11 A/C12A/C14A, the zero-cross detection
circuitry will not function.
INT2 (Interrupt Request 2). INT2 is a falling edge
triggered, maskable interrupt input. It is also an acinput, zero-cross detection terminal.
MODEO, MODE1 (Mode 0, 1). The MODEO and
MODE1 inputs select the amount of external memory.
MODEO outputs the 10 signal and MODE 1 outputs the
M1 signal. An external pullup resistor to VDD is required
if the input is to be a logic high.
The value of this pullup resistor, R, is dependent on
tCYC and is calculated as follows: R in KQis 4 s R s 0.4
tCYC where tCYC is in ns units.
NMI (Nonmaskable Interrupt). Falling edge,
Schmitt-triggered nonmaskable interrupt input.
PAo - PA7 (Port A). Port A is an 8~bit three-state port.
Each bit is independently programmable as either
input or output. Reset makes all lines of port A inputs.
Mask optional pullup resistors are available on the
pPD78C11A/C12A/C14A.
PBo - PB 7 (Port B). Port B is an 8-bit three-state port.
Each bit is independently programmable as either
input or output. Reset makes all lines of port B inputs.
Mask optional pull up resistors are available on the
IlPD78C11A/C12A/C14A.
PCo - PC7 (Port C). Port C is an 8-bit three-state
port. Each bit is Independently programmable as either
input or output. Alternatively, the lines of port C can be
used as control lines for the USART, interrupts, and
timer. Reset makes all lines of port C inputs. Mask
optional pullup resistors are available on the
IlPD78C11A/C12A/C14A.
7
-
JlPD78C14 Family
PDo - PD7 (Port D). Port 0 is an 8-bitthree-state port.
It can be programmed as either 8 bits of input or 8 bits
of output. When external expansion memory is used,
port 0 acts as the multiplexed address/data bus.
PFo - PF7 (Port F). Port F is an 8-bit three-state port.
Each bit is independently programmable as either
input or output. When external expansion memory is
used, port F outputs the high-order address bits.
RD (Read Strobe). The three-state RD output goes
low tQJ;late data from external devices onto the data
bus. RD goes high during reset.
RESET (Reset). When the Schmitt-triggered RESET
input is brought low, it initializes the device.
RxD (Receive Data).
Serial data input terminal.
SCK (Serial Clock). Output for the serial clock when
internal clock is used. Input for serial clock when
external clock is used.
STOP (STOP Mode Control Input). A low-level input
on STOP (Schmitt-triggered input) stops the system
clock oscillator.
TI (Timer Input).
Timer input terminal.
TO (Timer Output). The output of TO is a square
wave with a frequency determined by the timer/counter.
TxD (Transmit Data).
Serial data output terminal.
VAREF (A/D Converter Reference). VAREF sets the
upper limit for the A/D conversion range.
WR (Write Strobe). The three-state WR output goes
low to indicate that the data bus holds valid data. ·It is a
strobe~nal for external memory or I/O write operations. WR goes high during reset.
X1, X2 (Crystal Connections). Xi and X2 are the
system clock crystal oscillator terminals. Xi is the
input for an external clock.
AVoo (A/D Converter Power). This is the power
supply voltage for the AID converter.
AVss (A/D Converter Power Ground). AVss is the
ground potential for the AID converter power supply.
Voo (Power Supply).
ply.
Vss (Ground).
8
Voo is the +S-volt power sup-
Ground potential.
NEe
NEe
pPD78C14 Family
Block Diagram
12
16
XI
X2
Latch
IncrementJDecremant
PC
SP
EA
v
A
B
C
o
E
H
NMI
INTI
-
Main
General
Register
L
EA'
B'
D'
A'
C'
E'
H'
L'
V'
Alternate
General
Raglster
Program
Memory
Data
Memory
[258·ByteJ
InsL
Decoder
ReacLIVV~te
Control
~
ALE
MODEl
MOOED RESET
Voo
(STOP)
t
VCC
(VOO)
t
Vss
Nola:
1. On-Chlp ROM
78C1OA
: D
78CllA
: 4096 Bytes
78C12A
: 8192 Bytes
78C141C14A: 18384 Bytes
78CP14
: 18384 Bytes EPROMIOTP ROM
BSYL·926BB (9IBS)
9
NEe
pPD78C14 Family
Figure 1. Memory Map
OH
Intarnal Program Memory
4,098 Bylas: 78C11A
8192 Bytes: 78C12A
:
18,384 Bytes: 78C14f
C14AfCP14
(External Memory on 78C10A)
OH
RESET
4H
NMI
8H
INTTMN1T1
10H
INT1I1NT2
18H
INTEOIINTE1
20H
INTEINIINTAD
28H
INTSRIINlST
OFFFH
1000H
:
External Memory
81,184 Bylas: 78C11A
57,088 Bylas: 78C12A
48,898 Bytes: 78C1
tAW
Min
3T-100
tLOW
Max
T+ 110
tCI2H. tCI2L
(Note 3)
Min
tUN
Min
T-50
tow
Min
4T-100
Min
2T-70
tllH. tilL
Min
48T (TI input - PC5)
36T (INT1)
Min/Max (ns)
Min
Calculation Formula
T-30
t12H. tl2L
Min
36T (INT2)
tWOH
tANH. tANL
Min
36T (AN4-AN7)
tWL
Min
2T-50
tww
Min
4T-50
tCYK
Min
12T (SCK input) (Note 1)
Min
24T (SCK output)
Min
5T + 5 (SCK input) (Note 1)
tAL
tLA
Min
Min
2T-100
T-30
tAR
Min
3T-100
tAD
Max
7T-220
itOR
Max
tKKL
5T-200
tRO
Max
4T-150
tLR
Min
T-5O
tKKH
Min
12T - 100 (SCK output)
Min
5T + 5 (SCK input) (Note 1)
Min
12T - 10C(SCK output)
tRL
Min
2T-5O
Notes:
tRR
Min
4T - 50 (Data read)
Min
7T - 50 (Opcode fetoh)
tLL
Min
2T-40
(1) 1 x baud rate in'synchronous or I/O interface mode; T
tCYC
1/txTAL'
The items not included In this list are Independent of oscillator
frequency.
tML
Min
2T-100
tLM
Min
T-30
tiL
Min
2T-100
=
=
(2)' Event counter mode.
(3) Pulse-width measurement mode.
Data Memory STOP Mode Data Retention Characteristics
= -40 to 85°C
TA
Parameter
Symbol
Min
Data retention power supply voltage
VOOOR
2.5
Data retention power supply current
IOOOR
Typ
15
Max
Unit
5.5
V
15
JiA
VOOOR
50
JiA
VOOOR
300
JiA
mA
VOO rise. fall time
tRVO' tFVO
200
Jis
STOP setup time to VOO
tSSTVO
12T+0.5
Jis
STOP hold time from VOO
tHVDST
12T+0.5
Jis
22
Conditions
= 2.5V
= 5.0 V :t10%
VOOOR = 2.4 V (J1PD7BCP14)
VOOOR = 5.0V :t5% (J1PD7BCP14)
NEe
pPD78C14 Family
Timing Waveforms
Data Retention
•
83RD-B147A
Read Operation
""CE------ T1----»~1~E__---- T2----~»;I·~E_---- T3-------l»~1
Xl
~--------~o--------~
AooRrAooRo
ALE
~----tRo------l»~1
~-------tRR-----~
MOoEO[IO)1
[Note 1)
.
L~~"
~tIL-I
~---------------------------
tu
Nota:
[1)
iO signal Is output to !he MOoEO pin [If MOoEO Is puRed up to V Dol during a
read or w~ta of special reglalelS sN112 or a write to register MM or MF. Refer
to de8c~ptlon 01 Port EmulaUon Mode [PEM) In !he User's Manual lor further
explanaUon. This signal Is not oulput on the !,P078CP14.
83YL.....a
23
NEe
pPD78C14 Family
Timing Waveforms (cant)
Write Operation
~----T1-----,J~fooE---- T2-----,J~fooE----T3---__l1oi
X1
Data-out
ALE
~---------tww----~~
MODEO[IO)1
[Note 1)
.
L~~II
~---------------------------
-!
1 + - - - tIL
tLi
Note:
[1)
iO signal Is output to the MOOED pin [If MODEO Is pulled up to V Dol du~ng a
read or write of specialraglsters sr-sr2 or a write to register MM or MF. Refer
to dascrlpUon of Port Ernulllllon Mode [PEM) In !he User's Manual for lurlher
explanation. 11118 signal Is not output on the "PD78CP14.
24
NEe
,.,PD78C14 Family
Timing Waveforms (cant)
Opcode Fetch Operation
""IE!----n _1""'«---12 ---l~~I~O(---T3 ---l)o~IE_--T4--~~1
X1
y:)
AOOR15 -ADORa
E
)
Opcode
AOOR7-ADDRO
I'LLALE
~'RDH
'AO
~----<
~'~~
«-'LA£~~
1 ""
~~~
L~
-
P<
V
I+-'RD'RR
'AR
Note:
[1)
Mi signa/is oUlpU' III ... MODE1 pin cilring 8V8I)' Opcoda FeIt;h If MODE1
pin Is puDed up III Voo- lilts signal Is not output on ... "PD78CP14.
25
NEe
pPD78C14 Family
Timing Waveforms (cont)
SerilllOperlltion TrllnsmiVReceive
~
'CVK
~'KKL---:+-
~
I-'KKH-
iF
I-,KTX).
TxD
RxD
I
).
tRXK~1 !. .
..
(
~
'KRX
B3RD-8861B
Timer Input
Interrupt Input
Timer/Event Counter Input:
Event Counter Mode
INrI
Timer/Event Counter Input:
Pulse-Width Measurement Mode
26
NEe
,.,PD78C14 Family
Timing Waveforms (cant)
RESET Input
AC Timing Test Points
VOO-1.0
0.45 V
J
2.2 V
0.8 V
2.2V
:::::::= Test Points :::::: O.BV
C
83YL-926M.
-
AN4-AN7 Edge Detection
Externsl Clock
X1
~-------t~c------~
27
!\I'Ee
pPD78C14 Family
"PD78CP14 PROGRAMMING
Table 3_
In the pPD78CP14, the mask ROM of the pPD78C14
family is replaced by a one-time programmabie ROM
(OTP ROM) or a reprogrammable, ultraviolet erasable
ROM (UV EPROM). The ROM is 16,384 by 8 bits and can
be programmed using a general-purpose PROM writer
with a pPD27C256A programming mode. Refer to tables 3 through 5 and the DC andAC Programming
Characteristics tables for specific information applicable to programming the pPD78CP14.
Pin Functions during EPROM
Programming
Descr i ptlon
Pin
Function
PAo - PA7
.Ao- A7.
Low-order a-bit address
PFo
As
High-order 7-bit address
NMI
Ag
PF2 - PFs
AlO- A14
PDo- PD7
00 - 0 7
Data inpuVoutput
PBs
CE
Chip enable input
PB7
OE
Output enable input
RESET
RESET
PROM programming mode requires a
low voltage on this pin
Mode 0
Mode 0
Enter PROM programming mode by
applying a high voltage to this pin
Mode 1
Mode j
Enter PROM programming mode by
applying a low voltage to this pin
STOP
Vpp
High-voltage input (write/verify) high
level (read)
Table 4. Summary of Operation Modes for EPROM Programming
Operation Mode
CE
OE
Vpp
VDD
RESET
MODEO
MODE1
A14
Program write
L
H
+12.5V
+6V
L
H
L
L
Program verify
H
L
+12.5V
+6V
L
H
L
L
Program Inhibit
H
H
+12.5V
+6V
L
H
L
L
Read
L
L
+5V
+5V
L
H
L
L
Output disable
L
H
+5V
+5V
L
H
L
L
Standby
H
L/H
+5V
+5V
L
H
L
L
Notes:
(1) The CE, OE, Vpp' and Voo pins are all compatible with the
IlPD27C256A pins.
Caution: When Vpp is set to +12.5 V and VOO is set to +6 V, you
cannot set both CE and OE to low level (L).
28
NEe
,.,PD78C14 Family
PROM Read Procedure
Table 5. Recommended Connections for
Unused Pins (EPROM Programming
Mode)
(1) Connect the RESET pin, the MODE1 pin, and A14
pin to a low level and connect the MODEO pin to a
high level.
Pin
Recommended Connection Method
INT1
Connect to Vss
X1
Connect to Vss
(2) Apply +5 V to the Voo and
X2
Leave this pin disconnected
ANO-AN7
Connect to Vss
(3) Input the address of the data to be read to pins
Ao - A14·
Vpp
pins.
AVoo
Connect to Vss
(4) Read mode is entered with a pulse (active low) on
both the CE and OE pins.
AVss
Connect to Vss
(5) Data is output to the Do - D7 pins.
Remaining pins
Connect each pin via a resistor to Vss
Connect to Vss
PROM Write Procedure
(1)
Connect the RESET pin, the MODE1 pin, and A14
pin to a low level and connect the MODEO pin to a
high level. Connect all unused pins as recommended in Table 5.
(2)
Apply +6 V to the Voo pin and + 12.5 V to the
pin.
(3)
Provide the initial address.
Vpp
(4)
Provide write data.
(5)
Provide 1-ms program pulse (active low) to the CE
pin.
(6)
This bit is now verified with a pulse (active low) to
the OE pin. If the data has been written, proceed to
step 8; if not, repeat steps 4 to 6. If the data cannot
be correctly written after 25 attempts, go to step 7.
(7)
Classify as defective and stop write operation.
(8)
Provide write data and supply program pulse (for
additional writing) for 3 ms times the number of
repeats performed between steps 4 to 6.
(9)
Increment the address.
EPROM Erasure
Data in an EPROM is erased by exposing the quartz
window in the ceramic package to light having a wavelength shorter than 400 nm, including ultraviolet rays,
direct sunlight, and fluorescent light. To prevent unintentional erasure, mask the window.
Typically, data is erased by 254-nm ultraviolet rays. A
minimum lighting level of 15W-s/cm2 (ultraviolet ray
intensity x exposure time) is required to completely
erase written data. Erasure by an ultraviolet lamp rated
at 12mW/cm2 takes approximately 15 to 20 minutes.
Remove any filter on the lamp and place the device
within 2.5 cm of the lamp tubes.
(10) Repeat steps 4 to 9 until the end address.
29
•
NEe
pPD78C14 Family
I'PD78CP14 DC Programming Characteristics
TA
=
=
25 ±5°C; MODEl
YIL; MODEO
=
YIH; YSS
=
OY
Parameter
Symbol
Symbol*
Min
High-level input voltage
YIH
YIH
2.2
-0.3
Low-level input voltage
YIL
YIL
Input leakage current
11iP
III
High-level output voltage
YOH
YOH
Low-level output voltage
VOL
VOL
Max
Unit
Yoop+0.3
Y
Typ
0.8
Y
±10
JlA
Output leakage current
ILO
YOOp
YCC
5.75
4.5
Ypp power voltage
Ypp
Ypp
12.2
IOH
0.45
Y
IOL
Ypp power current
JlA
Os Yo s YOOp; OE
Y
Program memory write mode
5.0
5.5
Y
Program memory read mode
12.5
12.8
Y
Program memory write mode
Y
Program memory read mode
30
mA
Program memory write mode
30
mA
Program memory read mode;
CE = YIL; YI = YIH
30
mA
Program memory read mode;
CE = YIL; OE = YIH
100
JlA
Program memory write mode
Ipp
Ipp
=
±10
Icc
100
= -1.0mA
= 2.0 mA
6.25
6.0
Ypp = YOOp
YOOp power current
Os Yl S YOOp
Y
YOO -1.0
YOOp power voltage
Condition
YIH
* Corresponding symbols of the JlPD27C256A.
I'PD78CP14 AC Programming Characteristics
TA
=
25 ±5°C; MODEl
=
YIL; YSS = OY
Parameter
Symbol
Symbol*
Address setup time to CE j
tSAC
tAS
2
JlS
Min
Typ
Max
Unit
Data to OE j delay time
tOOOO
tOES
2
Jls
Input data setup time to CE j
tSIOC
tos
2
Jls
Address hold time from CE I
tHCA
tAH
2
Jls
Input data hold time from CE I
tHCIO
tOH
2
Jls
Output data hold time from OE I
tHOOO
tOF
0
Ypp setup time to CE j
tsvPC
typs
2
YOop setup time to CE j
tsvOC
tvos
2
Initial program pulse width
tWLl
tpw
0.95
Additional program pulse width
tWL2
topw
2.85
MODEO/MODEI setup time vs. CE j
tSMC
Address to data output time
tOAOO
tACC
CE I to data output time
tOCOO
tCE
OE I to data output time
tOOOO
tOE
Data hold time from OE I or CE I
tHCOO
tOF
0
tOH
0
Data hold time from address
tHAOO
• Corresponding symbols of the JlPD27C256A.
30
130
Condition
ns
Jls
Jls
1.0
1.05
ms
78.75
ms
2
2
JlS
MODEl = YIL and MODEO = YIH
Jls
OE
=
YIL
Jls
Jls
130
ns
ns
OE = YIL
NEe
IlPD78C14 Family
PROM Timing Diagrams
pPD78CP14 PROM Write Mode
=>..
~tSAC
DaIs
~
......
=>..
K
EIIacIIVa Address
~
Input
~IOC
DsIa
Output
tHOIO
,.::
......
-
_tHOOD
I--
tHCA
I-
tHOIO
Dala
Inpul
!sloo . .
l-
.....
•
Mode 1 =VIL
ModeO=VIH
tSMe
~
Vpp
Vpp
VOOP
VOOP +1
VOOP
Voop
-.J
..
-.I
..
tSVPC
~
tsvoo
~
~
tWL1
..:.:.:.:.
.....
toooo
-loooo
~tWL.2--+
VIL
Notas:
(1)
(2)
VOOP must be applied before applying Vpp. It should be removed aller rarnovIng Vpp.
Vpp must not axcaed +13 V,lncIudlng owrahoot.
_.,....88
31
NEe
pPD78C14 Family
PROM Timing Diagrams (cont)
pPD7BCP14 PROM Read Mode
EIIactIva Addrasa
Notes:
(1) To read PROM within the tCAOO range, 1111 delay of OE -I. from CE -I. must be within t CAW t DOOO'
(2) tHCOD Is the time from the ._In which either OE or CE ftrst becomes VIH'
••''',.•••011
32
NEe
NEe Electronics Inc.
pPD78C18 Family
pPD78C17/C18/CP18
8-Bit, Single-Chip Microcontrollers
With A/D Converter
September 1993
Description
o 40 I/O lines
The IJPD78C18 family is an expanded memory version
of the IJPD78C14 family of 8-bit CMOS single-chip
micro controllers.
o Pull up resistors for the mask option
- Ports A, S, and C
-IJPD78C18 device only
These microcontrollers integrate sophisticated onchip peripheral functions normally provided by external components. Their internal 16-bit ALU and data
paths, combined with a powerful instruction set and
addressing capability, make the devices appropriate in
data processing as well as control applications.
The devices integrate a 16-bit ALU, 32K-byte ROM,
1024-byte RAM, an eight-channel AID converter, a mUltifunction 16-bit timer/event counter, two 8-bit timers, a
USART, and two zero-crossing detect inputs on a single
die, allowing their use in fast, high-end processing
applications.
The IJPD78C18 family includes a 32K-byte mask ROM
device, embedded with a customer program, a ROMless device for use with up to 64K bytes of external
memory, and a 32K-byte EPROM or OTP ROM device for
prototyping and low-volume production. The IJPD78C18
may also be ordered with pullup resistors that are
available as a mask option for ports A, S, and C.
Features
o CMOS technology
o 30 rnA operating current (J.IPD78C17/C18)
o Complete single-chip microcontroller
-16-bitALU
- 32K-byte ROM
-1024-byte RAM
o Two zero-crossing detect inputs
o Two 8-bit timers
o Four edge-detection inputs (AN4-AN7)
o Expansion capabilities
- 8085A-like bus
- 64K-byte external memory address range
o Eight-channel, 8-bit A/D converter
- Autoscan mode
- Channel select mode
o Full-duplex USART (synchronous and
asynchronous)
o 159 instructions
-16-bit arithmetic, multiply, and divide
- HALT and STOP instructions
o 0.8 JiS instruction cycle time (15 MHz operation)
o Prioritized interrupt structure
- Three external
- Eight internal
o Standby function
o On-chip clock generator
•
NEe·
,.,PD78C18 Family
Ordering Information
Part Number (Note 1)
Package
Package Drawing
Quality Grade (Note 3)
ROMIBSS
IlPD78C17CW
64-pln SDIP
P64C-70-750A, C
Standard
--------------~------------------------~~~----------~------~GF-3BE
64-pin QFP (Note 2)
P64GF-l00-3B8, 3BE-l
Standard
GF(A)-3BE
GQ-36
Special
64-pin QUIP
P64GQ-l00-36
GQ(A)-36
Stand!lrd
Speci!ll
32KMsskROM
IlPD78C18_C_W_-~
______________6_4~-p~l_n_S_D_IP__________________P_6_4_C_-7_0_q_50
__
A~,_C___________.s_t_a_nd_a_ro
______~~__~__
GF-~-3BE
64-pin QFP (Note 2)
P64GF-l00-3B8, 3BE-l
54-pin QUIP
P64GQ-l00-36
GF(A)-~-3BE
GQ-~-35
Standard
Special
GQ(A)-~-36
Standard
Special
32K OTP ROM
IlPD78CP18_C_W______________6_4_-~pi_n_S_D_IP___________________
P6_4_C_-7_0_-_75_0_A~,_C___________S_t_a_n_da_r_d_______________
GF-3BE
64-pin QFP (Note 2)
P64GF-l00-3B8,3BE-l
64-pin QUIP
P54GQ-l00-36
GF(A)-3BE
GO-36
Standard
Special
GQ(A)-36
Standard
Special
32KUVEPROM
IlPD78CP18DW
64-pin SDIP w/window
P64C-70-750A, C
64-pin ceramic LCC w/Window
X64KW-l00A-l
--------------~---------------------------------
KB
Note:
(1) xxx indiC!ltes ROM code suffix.
(2) Engineering samples supplied in a ceramic QFP package
(3) Special grade devices h!lve the symbol (A) embedded in the part
number
2
Standard
NEe
pPD78C18 Family
Pin Configurations
64-Pin Plastic QUIP or Plastic Shrink DIP
PAo
PA1
VDD
STOP
PA2
PD7
PAS
PDa
PA4
PDs
PAs
PD4
PAa
PDs
PA7
PD2
PBo
PD1
PB1
PDo
PB2
PF7
PBs
PB4
PFa
PBs
PBa
PB7
PCOrrxD
PC1/RxD
PC2/SCK
PCsfTVlNT2
PC4fTO
POs/OI
PCa/COO
P07/C01
NMI
..
PFs
PF4
PFs
PF2
PF1
PFo
ALE
WR
RD
AVDD
VAREF
AN7
ANa
INT1
ANS
MODE1
AN4
RESET
ANS
MODEO
AN2
X2
AN1
X1
ANO
Vss
AVss
83YL-82i1A ~ 7/93
3
NEe
pPD78C18 Family
64-Pin Plastic QFP or Ceramic LCC
52
53
54
55
56
57
32
27
AVss
PAo
PA1
PA2
56
59
26
25
Vss
X1
60
61
24
X2
23
MODEO
PA3
62
22
RESET
PA4
63
21
MODE1
PA5
64
20
INT1
P03
P04
P05
P06
P07
STOP
VOD
0
AN4
31
AN3
30
29
AN2
AN1
28
ANO
83Ml-8180B
4
NEe
pPD78C18 Family
Pin Identification
Symbol
Function
ALE
Address latch enable output
ANO-AN7
AID converter analog inputs 0-7
INTl
Interrupt request 1 input
MODEO
Mode 0 input; 1/0 memory output
MODEl
Mode 1 input
NMI
Nonmaskable interrupt input
PAO-PA7
Port A I/O lines 0-7
PBO-PB7
Port B I/O lines 0-7
PCoITxD
Port C I/O line 0; transmit data output
PC:!/SCK
Port C I/O line 2; serial clock I/O
PCalTI/lNT2
Port C I/O line 3; timer input; interrupt request
2 input
PC",TO
Port C I/O line 4; timer output
PCslCI
Port C I/O line 5; counter input
PC6 and PC7/
COo and COt
Port C I/O lines 6 and 7;
counter outputs 0 and 1
PD O-PD7
Port D I/O; expansion memory address, data
bus (bits ADo-AD7)
Port C I/O line 1; receive data input
Port F I/O; expansion memory address,
(bits ABs-ABts)
RD
Read strobe output
STOP
Stop mode control input
WR
Write strobe output
Reset input
A/D converter reference voltage
Xl and X2
Crystal connections 1 and 2
AVoo
AID converter power supply voltage
AVss
A/D converter power supply ground
Voo
+ 5 V power supply
Vss
Ground
IC
Internal connection
Pin Functions
ALE (Address Latch Enable). The ALE output is used
to strobe the address of PDo-PD7 into an external latch.
ANO-AN7 (Analog Inputs). AND-AN7 are the eight analog inputs to the AID converter. AN4-AN7 can also be
used as digital inputs for falling edge detection.
COo and C01 (Counter Outputs). COo and Cal are
programmable waveform outputs from the timer/event
counter.
INn (Interrupt Request 1). INT1 is a rising edgetriggered, maskable interrupt input, as well as an acinput, zero-crossing detection terminal.
INT2(lnterrupt Request 2). INT2 is a falling edgetriggered, maskable interrupt input, as well as an acinput, zero-crossing detection terminal ..
If the optional pullup resistor is specified forthis pin on
the pPD78C18, the zero-crossing detection circuitry will
not function.
MODEa and MODE1 (Mode). For the pPD78C17, the
size ofthe externally installed memory can be selected
as 4K, 16K, or 63K bytes by setting the MODED and
MODE1 pins.
ForthepPD78C18, the MOOED pin is set to D (logic lOW).
The MODE1 pin is pulled high with a pull up resistor.
For the pPD78C17/C18, an external pull up resistor to
is required, if the mode pin is to be a logic high. The
value of this pullup resistor, R, is dependent on tC;YC
and is calculated as follows: R in kO is 4 ,:; R -; 0.4
tCYC, where tCYC is in ns units.
VDD
NMI (Nonmaskable Interrupt). NMI is a falling odon,
Schmitt-triggered nonmaskable interrupt input.
PAo-PA7 (Port A). Port A is an 8-bit three-state port.
Each bit is independently programmable as either
input or output. The reset signal causes all lines of port
A to be inputs. Pullup resistors are available as a mask
option on the pPD78C18.
PB o-PB 7 (Port B). Port B is an 8-bit three-state port.
Each bit is independently programmable as either
input or output. The reset signal causes all lines of port
B to be inputs. Pull up resistors are available as a mask
option on the pPD78C18.
PCO-PC7 (Port C). Port C is an 8-bit three-state port.
Each bit is independently programmable as either
input or output. Alternatively, the lines of port C can be
used as control lines for the USART, interrupts, and
timer. The reset signal causes all lines of port C to be
inputs. Pull up resistors are available as a mask option
on the pPD78C18.
CI (Counter Input). CI isthe external pulse input tothe
timer/event counter.
5
IlPD78C18 Family
PDo-PD7 (Port D). Port 0 is an a-bit three-state port. It
can be programmed as either a bits of input or a bits of
output. When external expansion memory is used, port
o functions as the multiplexed address/data bus.
PFo-PF7 (Port F). Port F is an a-bit three-state port.
Each bit is independently programmable as either
input or output. When external expansion memory Is
used, port F outputs the high-order,address bits.
RD (Read Strobe). The strobe signal, when output for
read operation of external memory, operates as follows. The signal is high, except during a data read
machine cycle. It becomes a high output impedance
when the RESET signal is low or when the device is in
hardware stop mode.
RESET (Reset). When the Schmitt-triggered RESET input goes low, it initializes the device.
RxD (Receive Data). RxD is the serial data input terminal.
SCK (Se~ial Clock). SCK is the serial clock output
when the Internal clock is used. SCK is the input for the
serial clock when the external clock is used.
STOP (Stop Mode Control Input). Alow-I~vel input on
STOP (Schmitt-triggered input) stops the system clock
oscillator.
TI (Timer Input). TI is the timer input terminal.
6
NEe
T~ (Timer Output). The output of TO is a square wave
With a frequency determined by the timer/counter.
TxD (Transmit Data). TxD is the serial data output
terminal.
VARE F (A/D Converter Reference) • VAREF functions as
an input pin for the AID converter reference voltage
and as the control pin for AID converter operation.
WR (Write Strobe). The strobe signal, when output for
the write operation of external memory, operates as
follows. The signal is high, except during a data write
machine cycle. It becomes a high output impedance
when the RESET signal is low or when the device is in
hardware stop mode.
X1 and X2 (Crystal Connections). X1 and X2 are the
system clock crystal oscillator terminals. X1 is also the
input for an external clock.
AVoo (A/D Converter Power). This is the power supply
voltage for the AID converter.
AVss (A/D Converter Ground). AVss is the ground
potential for the AID converter power supply.
Voo (Power Supply). Voo is the +5-volt power supply.
Vss (Ground). Vss is the ground potential for the +5volt device power supply.
NEe
pPD78C18 Family
Block Diagram
Xl--O
X2t=J
15
10
Program
Oala
Memory
PCOfTxD -+-----1
PClIRxO--~
PC2ISCK-+--~
A
C
V
B
0
H
NMI--~
E
L
EA'
INT1--~
A'
C'
V'
B'
AN7-AN4
}-
General
Register
}General
Register
Memory
(1,024 Bytes)
PC3(
TVlNT2
PC4fTO~
PC5fClPC6(COo~
PC7(C01~
lnat
AN7-ANO
Decoder
ReadlWrite Control
I
System Control
l l l f f
AD
WR
ALE
MODEl MOOEO
t i
VOO
VSS
NolII:
1. On-Chip ROM
~P078C17
~P078C18
:0
: 32,768 Bytes
~P078CP18 : 32,768 Bytes EPROMfOTP ROM
7
NEe
pPD78C18 Family
FUNCTIONAL DESCRIPTION
Memory Map
The IIPD78C18 family can directly address up to 64K
bytes of memory. Except for the on-chip ROM (or
PROM) and RAM (FCOOH-FFFFH), any memory location can be used as ROM or RAM. The memory maps,
shown In fIgures 1 through 3, defIne the 0 to 64K-byte
memory space for the IIPD78C18 family.
The IIPD78CP18 can be programmed by software to
have 4K, 8K, 16K, or 32K bytes of internal program
memory. This programming is transparent to a ROMbased device, allowing easy transfer of code.
Figure t. MemoryMap (pPD78Ct7)
OOOOH
:
~
OOOOH
RESET
0004H
NMI
0008H
INTIOIINTT1
0010H
INT111NT2
0018H
INlEO/INTE1
OO2OH
INlElNIINTAD
0028H
INTSRIINTST
-------
:
External Memory
84,512Wx8
FBFFH
FCOOH
On-Chlp RAM*
1024 Wx8
~
}:.~
FFFFH
-I
Call Table
SOFTl
OOSOH
LowADRS
0081H
HlghADRS
0082H
LowADRS
0083H
HlghADRS
I
} 1=0
} 1=1
:~
* Can only be uaad When the RAE bit
oftha MM raglatarl81.
8
OOBEH
LowADRS
OOBFH
HlghADRS
} 1=31
NEe
pPD78C18 Family
Figure 2. Memory Map (pPD7BC1B)
OOOOH
~
On·ChlpROM
32,788Wx8
~
OOOOH
RESET
0004H
NMI
0008H
INTTOIINTT1
0010H
INT1flNT2
0018H
INTEOIINTE1
OO2OH
INTEINnNTAO
0028H
INTSRlINTST
7FFFH
..
BOOOH
Exlamal MerllO/Y
31,744Wx8
~
FBFFH
FCOOH
On.()hlp RAM
1024Wx8
*
}=by
FFFFH
-I
Call Table
SOFT!
OOBOH
Low AORS
0081H
High AORS
0082H
Low AORS
0083H
High AORS
I
} 1=0
} 1=1
~
OOBEH
Low AORS
OOBFH
HIgh AORS
} 1=31
OOCOH
~
User's Area
* Can only be used when 1118 RAEbR
011118 MM register Is 1.
9
NEe
pPD78C18 Family
Figure 3. Memory Map (pPD7BCPtB)
OOOOH
OOOOH
I-__....:R"'E=:S::ET"-_ _--I
0OO4H
NMI
r--------------;
On-Chip PROM
0008H 1-_--"IN.:..:TT..:..::Of.::.IN.:..:TT.:...:.1_--l
Mode
D78C11A: 4,096 x 8
D78Cl2A: 8,192 x8
D78Cl41Cl4A: 18,384 x 8
D78C18: 32,768 x 8
Vector
Area
OFFFH
1000H
0010H
I---...::..:..:..::.:..c'-"------I
INT1f1NT2
0018H
tNTEOI1NTE1
0020H
tNTEtNiINTAD
0028H
INTSRlINTST
1FFFH
2000H
3FFFH
4000H
7FFFH
8000H
External Memory
Mode
D78C11A: 61,148 X8
D78Cl2A: 57,088 X 8
D78Cl4114A: 48,986 X 8
D78C18: 31,744 X 8
FBFFH
FFOOH
1FEFFH
~:; ~
'" ~~
~""
~:;
~~
~~
""~
-I
som
0080H
LowADRS
0081H
HlghADRS
0082H
LowADRS
I
~ .-.
t=l
HlghADRS
On-Chlp RAM
LowADRS
Mode
D78C11A: 256X8
D78Cl2A: 256 X 8
D78Cl4114A: 256 X 8
D78C18: l,024X8
HlghADRS
UsefsArea
Remaining
On-chlp PROM
83YL0.9507B
10
NEe
Input/Output
The pPD78C18 family has 40 digital I/O lines, consisting
of five 8-bit ports (ports A, B, C, D, and F), and four
digital input lines (AN4-AN7).
,.,PD78C18 Family
Table 1. Memory Expansion Modes and Port
Configurations
Memory Expansion
Port
Port Configuration
None
PortO
110 port
Port F
110 port
256 bytes
PortO
Multiplexed addressl
data bus
Port F
110 port
4K bytes
Port 0
Multiplexed addressl
data bus
Port F (PFo-PF3)
Address bus
Port F (PF4-PF7)
110 port
Port 0
Multiplexed addressl
data bus
Port D. Port D can be programmed as a byte input or
Port F (PFo-PF5)
Address bus
a byte output.
Port F (PF6-PF7)
110 port
Port D
Multiplexed addressl
data bus
Port F
Address bus
Analog Input Lines. ANO-AN7 are configured as analog input lines for the on-chip A/D converter. Lines
AN4-AN7 can be used as digital input lines for falling
edge detection.
Port A, Port e, Port C, and Port F. Each line of these
ports can be individually programmed as an input or
output. When used as I/O ports, all have latched outputs and high impedance inputs. On the pPD78C18,
pull up resistors are available as a mask option for ports
A, B, and C.
16K bytes
Control Lines. Under software control, each line of
port C can be configured individually as a control line
for the serial interface, timer, and timer/counter or as an
I/O port.
32K/48K/56K/60K bytes
Memory Expansion. In addition to the single-chip op·
eration mode, the pPD78C18 family has four memory
expansion modes. Under software control, port D can
provide a multiplexed low-order address and data bus;
port F can provide a high-order address bus. Table 1
shows the relationship between the memory expansion
modes and the pin configurations of port D and port F.
(1) Set according to bits MM7 to MM5.
(Note 1)
Note:
11
NEe
,.,PD78C18 Family
Timers
8·Bit A/D Converter
The two 8-bit timers can be programmed independently or cascaded as a 16-bit timer. The timer can be
set by software to increment at intervals of four machine cycles (0.8J1s at 15 MHz operation) or 128 machine cycles (25.6J1s at 15 MHz), or to increment on
receipt of a pulse at TI. Figure 4 is the block diagram for
the timer.
The 8-bit A/D converter provides the following:
Timer/Event Counter
The 16-bit multifunctional timer/event counter, shown
in figure 5, can be used for the following operations:
•
•
•
•
•
Interval timing
External event counting
Frequency measurement
Pulse-width measurement
Programmable frequency and duty cycle waveform
output
• Single-pulse output
Figure 4_
• Eight input channels
• Four conversion result registers
• Two powerful operation modes
-Autoscan
- Channel select
• Successive approximation technique
• Absolute accuracy: 0.6% FSR ±1/2 LSB
• Conversion range: 0 to 5 V
• Conversion time: 38.4 J1S
• Interrupt generation
Timer Block Diagram
e3
~-------I
llmerO
I
PC:fT1
To llmer/Event Counter
or Serlal Clock Source
812----1
INTT1
INTTO
IntemalBus
e3
812
e384
fxtaJ
f xtaJ x 1/3
f xtaJ x 1/12
f xtaJ x 1/384
Input crystal frequency
83RD-63S8B (9193)
12
NEe
pPD78C18 Family
Figure 5. Block Diagram for the Timer/Event Counter
Internal Bus
612-1
TO::
from Interval
Output
Clock
Select
Control
'-------'
llmarFIF
1---+-........++1 CPO
1 - - - - INTEO
Interropt
Control
' - - - - - I 1-----.,-----1-+1 CPl
EIN
I----INTEI
• INTnN
912 =fxtal x 1/12
IxtaI: Input cryslal frequency
13
NEe
pPD78C18 Family
Analog/Digital Converter
Figure 6. AID Converter Block Diagram
The IlPD78C18 family features an 8-bit, high-speed,
high accuracy AID converter. The AID converter is
comprised of a 256-resistor ladder and a successive
approximation register (SAR). There are four conversion result registers (CRO-CAS).
AVoo
AVss
VAREF
n
i
ANO
AN1
The eight-channel analog input can be operated in two
different modes. In the select mode, the conversion
value of one analog input is sequentially stored in
CRO-CR3. In the scan mode, either the upper four
channels or the lower four channels may be specified.
The four channels specified will be consecutively selected and the conversion results stored sequentially in
the four conversion result registers.
AN2
AN3
AN4
AN5
ANa
AW
Figure 6 is the block diagram for the AID converter. To
stop the operation of the AID converter and reduce the
power consumption, set VAREF = 0 V.
AN4
AN5
Interrupt Structure
AN6
AW
There are 12 interrupt sources in the IlPD78C18 family.
Three are external and nine are internal interrupt
sources. Table 2 shows 11 interrupt sources divided
into seven priority levels, where IRQO is the highest and
IRQ6 is the lowest. See figure 7.
83RD-883M
Figure 7. Interrupt Structure Block Diagram
NMI
INTTO
INTT1
INTI
INT2
INTEO
INTE1
r-----v'~
.----''----, TF-L.::J--
t-----,
Skip Control
INTEIN
Interrupt
GeneraUon
INTAO
INTSR
INTST
EI
PrIortty
Control
ov
TF
Test
01
INTFNMI--
Rag
RegIster
R
~i
.-----v-EFnterrupt
Address
SOFTl....
~
-
'-------'
83RD-GB37B (Q'9S)
14
NEe
pPD78C18 Family
Table 2. Interrupt Sources
Interrupt Request
Interrupt Address
Type of Interrupt
Internal/External
IROO
4
NMI (nonmaskable interrupt)
External
IR01
8
INTTO, INTT1 (coincidence signals from timers 0, 1)
Internal
IR02
16
INT1, INT2 (maskable interrupts)
External
IR03
24
INTEO, INTE1 (coincidence signals from timer/event counter)
Internal
IR04
32
INTEIN (falling signal of CI or TO into the timer/event counter)
Internal or External
INTAD (A/D converter interrupt)
Internal
INTSR (serial receive interrupt)
Internal
IR05
40
INST (serial send interrupt)
96 _ _ _ _ _
IR06
_
__________
SO_F_T_I_in_s_tr_uc_ti_o_n_ _ _ _ _ _ _ _ _ _ _ _ _ _ _I_nl,_e_rn__
a_1- - -
Standby Modes
The pPD78C18 family has two standby modes: HALT
and STOP.
HALT Mode. The HALT mode reduces power consumption to 50% of normal operating requirements, while
maintaining the contents of on-chip registers, RAM,
and control status. The system clock and on-board
peripherals continue to operate, but the CPU stops
executing instructions. The HALT mode is initiated by
executing the HLT instruction and can be released by
any nonmasked interrupt or by RESET.
STOP Mode. The STOP mode reduces power consumption to less than 0.1 % of normal operating requirements. There are two stop modes: type A and type
B.
Type A is initiated by executing a STOP instruction. If
VDD is held above 2.5 V, the contents of the on-board
RAM are saved. The oscillator is stopped. The stop
mode can be released by an input on NMI or RESET.
The user can program oscillator stabilization time up
to 52.4 ms via timer 1. By checking the standby flag
(SB), the user can determine whether the processor
has been in the standby mode or has been powered up.
Type B is initiated by inputting a low level on the STOP
input. The RAM contents are saved if VDD is held above
2.5 V. The oscillator is stopped. The stop mode is
released by raising STOP to a high level. The oscillator
stabilization time is fixed at 52.4 ms; instructions will
automatically begin executing at location 0, 52.4 ms
after STOP is raised. You can increase the stabilization
time by holding RESET low forthe required time period.
first, for ease of interfacing to certain NEC peripheral
devices. Synchronous and asynchronous modes transfer data least significant bit (LSB) first. Synchronous
operation offers two modes of data reception: search
and nonsearch. In the search mode, data is transferred
one bit at a time from the serial register to the receive
buffer. This allows a software search for a synchronous
character. In the nonsearch mode, data going from the
serial registerto the transmit buffor is transferred oioht
bits at a time. Figure 8 shows tlH~ universal sorial
interface block diagram.
Zero-Crossing Detector
The INT1 and INT2 (common to TI and PC 3 ) terminals
can detect the zero-crossing point of low-frequency AC
signals. When driven directly, these pins respond as a
normal digital input. Figure 9 shows the zero-crossing
detection circuitry.
The zero-crossing detection capability allows you to
make the 50-60 Hz power signal the basis for system
timing and to control voltage phase-sensitive devices.
To use the zero-crossing detection mode, an AC signal
of 1.0 to 1.8 V (peak to peak) and a maximum frequency
of 1 kHz is coupled through an external capacitor to the
INT1 and INT2 pins.
For the INT1 pin, the internal digital state is sensed as
a 0 until the rising edge crosses the average DC level. It
then becomes a 1 and an INT1 interrupt is generated.
For the INT2 pin, the state is sensed as a 1 until the
falling edge crosses the average DC level. It then
becomes a 0 and INT2 is generated.
Universal Serial Interface
The serial interface can operate in one of three modes:
synchronous, asynchronous, and I/O interface. I/O interface mode transfers data most significant bit (MSB)
15
Eli
NEe
pPD78C18 Family
Figure 8. Universal Serial Interface Siock Diagram
r-::::l
Recelva
INTSR +-----f Buffer RlIIIlstar
~
(RxB)
Serial Reglatar
(S-P)
Receive Control
TransmR Buffer
(TxB)
Se~aI
Raglatar
(P-S)
ER
TransmIt ConllOl
~K--~-------4-----------------------------------------------"
e24
e24 Ixtal x ~
1------1~ B384
=
TlmerFIF
B384 Ixtal x ~
=
Ixtal : OscIlatlon lrequency (MHz) 01 crystal
~ar~------<~------------------------------------------------------~
Figure 9. Zero-Crossing Detection Circuit
I
AClnput
SIgnal
I
I
~
I
I ~I
;tI
~:
i~1
I
I
I=~
AC Input
I
---I 1-----,1-0----.----1
11'F
INTI
or
1NT2
16
I
I
1/
rI
To
0---
Internal
ClrcuRry
INTST
NEe
pPD78C18 Family
ELECTRICAL SPEC IFICATIONS
Capacitance
Absolute Maximum Ratings, I'PD78C17/C18
TA = 25°C
Power supply voltage, Voo
AVoo
AVss
Vpp (JJPD78CP18 only)
-0.5 to + 7.0 V
AVss to Voo +0.5 V
-0.5 to + 0.5 V
-0.5 to +13.5 V
Input voltage, VI
-0.5 to VOO+ 0.5 V
Output voltage, Vo
-0.5 to Voo+ 0.5 V
Output current, low; 10L
Each output pin
Total
4.0mA
100 mA
Output current, high; 10H
Each output pin
Total
-2.0mA
-50 mA
Reference Input voltage, VAREF
TA
= 25°C; Voo = Vss = OV
Parameter
Symbol
Max
Unit
Input capacitance
CI
10
pF
Output capacitance
Co
20
pF
1/0 capacitance
CIO
20
pF
Conditions
Ic = 1 MHz;
unmeasured pins
returned to 0 V
..
-0.5 to AVoo + 0.3 V
Operating temperature, TOPR
(txTAL S 15 MHz)
-40 to +85°C
Storage temperature, TSTG
-65 to +150°C
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent damage. The device should ba operated within the limits
specified under DC and AC Characteristics.
Oscillation Characteristics
TA
= -40 to +85°C; Voo = AVoo = 5 V ±
10%; Vss
= AVss = 0 V; Voo -
0.8 V
Recommended
Circuit
Parameter
Ceramic resonator (Note 1) or
crystal oscillator (XTAL) (Note 2)
(Note 3)
Oscillation frequency (!xx)
External clock
(Note 4)
Xl input frequency (Ix)
Resonator
s
AVoo
s
Voo; 3.4 V
s
VAREF
:S
AVoo
Max
Unit
Conditions
4
15
MHz
AID converter not used
5.8
15
MHz
AID converter used
4
15
MHz
AID converter not used
5.8
15
MHz
AID converter used
Xl Input, rise, fall time (t r, tf)
0
20
ns
X1 input low- and high-level
width (~L' ~H)
20
250
ns
Min
Typ
Notes:
(1) Refer to the Resonator and Capacitance Requirements table for
the recommended ceramic resonators.
(3) For XTAL, see the Recommended XTAL or Ceramic Resonator
Oscillation Circuit Diagram.
(2) When using a crystal oscillator, it should be a paralle~resonant,
fundamental mode, ''AT cut" crystal. Capacitors 01 and 02 are
required for frequency stability. The values of Cl and C2 (Cl =
C2) can ba calculated from the load capacitance (00, specified
by the crystal manufacturer:
(4) See the Recommended External Clock Diagram.
CL =
Cl x C2 +Cs
Cl + C2
Where Cs is any stray capacitance in parallel with the crystal.
17
NEe
pPD78C18 Family
Recommended XTAL or Ceramic Resonator
Oscillation Circuit Diagram
Resonator and Capacitance Requirements
TA = -40 to +85"C
Manufacturer
Product Number
Murata
CSA15.00MXOOl
CST15.00MXW001
CSA10.0MT
CST10.0MTW
X2
CSAB.OOMT
Exlamal oscIIlallon clrcuft should be as close \0 the
Xl and X2 pins as possible.
TDK
Do not place other signal linea In the shaded area.
Recommended External Clock Diagram
CIOck-l>
Xl
HCMOS
Inverters
4>-
X2
B3Rt>e848A
18
Cl, C2 (pF)
22
None required
30
None required
30
CST8.00MTW
None required
FCR15.0MC
None required
FCR10.0
None required
FCR8.0
None required
NEe
I'PD78C18 Family
DC Characteristics
TA = -40 to +85°C; Voo = AVoo = +5.0V ±10%; Vss = AVss =
Parameter
Symbol
Min
Typ
Input voltage, low
Input voltage, high
Output voltage, low
ov
Max
Unit
0.8
V
0.2VOO
V
Note 1 in puts
VOO
V
All except XI, X2, and the Note 1 inputs
VOO
V
XI, X2, and the Note 1 inputs
0.45
V
IOL = 2.0mA
V
IOH = -1.0 mA
Output voltage, high
V
Conditions
All except the Note 1 inputs
IOH = -100JlA
Input current
±200
JiA
INTI (Note 2); TI (PC3) (Note 3); 0 V ,; VI
,; Voo
Input leakage current
±10
JiA
All except INTI; TI (PC3); 0 V ,; VI ,; Voo
±1
JiA
AN7-0; 0 V,; VI'; Voo {JiPD78CI7(A)/
CI8(A)/CPI8(A) only)
Output leakage current
AVOO supply current
Voo supply current
ILO
0.5
Alool
±10
JiA
OV,; VO'; VOO
1.3
mA
f = 15 MHz
Stop mode
AI002
10
20
JiA
1001
16
30
mA
Normal operation; f = 15MHz
1002
7
13
mA
Halt mode; f = 15 MHz
----,,-~--
Data retention voltage
VOOOR
Data retention current
1000R
Pullup resistor
RL
2.5
17
V
Stop mode
15
JiA
VOOOR = 2.5 V (Note 4)
10
50
JiA
VOOOR = 5.0 V ±10% (Noto 4)
27
75
kO
Ports A, B, C; 3.5 V ,; Voo ,; 5.5 V;
VI = 0 V {JiPD78CI8/CI8(A) only)
Notes:
(1) Inputs RESET, STOP, NMI, SCK, INTI, TI, and AN4-AN7.
(2) Assuming ZCM register is set to self-bias.
(3) Assuming ZCM register is set to self-bias and the MCC register is
set to the control mode.
(4) Hardware/software stop mode and assuming ZCM register is set
so that self-bias is not selected.
19
mil
NEe
I1PD78C18 Family
AC Characteristics
TA = -40 to +85'C; Voo = AVoo = +5.0V ±10%; Vss = AVss = OV
Parameter
Symbol
RESET pulse width high, low
tRSH, tRSL
Min
NMI pulse width high, low
tNIH, tNIH
10
Xl input cycle time
teye
66
Max
10
~
Address hold from ALE
Address to RD
RD
~
~
delay time
to address floating
Address to data input
Jis
250
ns
ns
tAL
30
tLA
35
ns
(Notes 2, 3)
tAR
100
ns
(Notes 2,3)
tAFR
ns
(Note 3)
ns
(Notes 2, 3)
(Notes 2, 3)
tAO
tLOR
135
ns
RD ~ to data input
tRO
120
to RD
~
delay time
Data hold time from RD
RD
t to ALE t delay time
RDwidth low
ALE width high
Ml setup time to ALE
~
Ml hold time after ALE I
101M setup time to ALE I
101M hold time after ALE I
Address to WR I delay
ALE
~
to data output
WR ~ to data output
ALE
~
to WR I delay time
Data setup time to WR
t
Data hold time from WR
WR
ns
(Notes 2, 3)
15
ns
(Notes 2,3)
tROH
0
ns
(Note 3)
tRL
80
ns
(Notes 2,3)
tRR
215
ns
Data read (Notes 2, 3)
415
ns
Opcode fetch (Notes 2, 3)
tLL
90
ns
(Notes 2,3)
tML
30
ns
(Note 3)
tLM
35
ns
(Note 3)
tiL
30
ns
(Note 3)
tLi
35
ns
(Note3)
tAW
100
ns
(Notes 2,3)
tLOW
180
ns
(Notes 2,3)
two
100
ns
(Note3)
tLR
t
t
t to ALE t delay time
WRwidth low
t[W
15
ns
(Notes 2, 3)
tow
165
ns
(Notes 2, 3)
127
ns
(Note 1)
60
ns
(Notes 2, 3)
tWL
80
ns
(Notes 2, 3)
tww
215
ns
(Notes 2,3)
tWOH
Notes:
(1) JiPD78CP18 only.
(2) Load capacitance CL = 100 pF.
(3) Values are for 15 MHz operation. For operation at other frequencies, refer to the table labeled Bus Timing Dependent on teye.
20
(Notes 2, 3)
20
ALE ~ to data input
~
(Note 1)
ns
250
ALE
Conditions
Jis
167
Address setup to ALE ~
Unit
NEe
pPD78C18 Family
Serial Operation
Parameter
Symbol
Min
SCK cycle time
tCYK
0.8
/ls
0.4
/ls
SCK input (Note 2)
1.6
/ls
SCK output (Note 3)
SCK width low
tKKL
SCK width high
tKKH
Max
Unit
Conditions
SCK input (Notes 1, 3)
335
ns
SCK input (Notes 1, 3)
160
ns
SCK input (Note 2)
700
ns
SCK output (Note 3)
335
ns
SCK input (Notes 1, 3)
160
ns
SCK input (Note 2)
700
ns
SCK output (Note 3)
RxO setup time to SCK t
tRXK
80
ns
(Note 1)
RxO hold time after SCK t
tKRX
80
ns
(Note 1)
SCK ~ TxO delay time
tKTX
ns
(Note 1)
210
Notes:
(1) 1 x baud rate in asynchronous, synchronous, and VO interface
modes.
(2) 16 x baud rate or 64 x baud rate in asynchronous mode.
(3) IxTAL
= 15 MHz.
Zero-Crossing Characteristics
Parameter
Symbol
Max
Min
Unit
Condition
AC cOLiploci
VlX.
1.8
Zero-crossing accuracy
AlX.
±135
Zero-crossing detection input frequency
flX.
Zero-crossing detection input
no III
olno
WIIV"
mV
kHz
0.05
AID Converter Characteristics
TA
= -40 to +85"C; voo = +5.0 V ±10%; Vss = AVss = 0 V; voo -
Parameter
Symbol
Resolution
Min
Typ
8
Sampling time
tcoNV
tSAMP
VIAN
Analog input Impedance
RAN
Reference voltage
VAREF
VAREF current
:s AVoo :s Voo; 3.4 V :s VAREF S AVoo
Unit
Conditions
%FSR
±0.6
%FSR
66 ns
:s tCYC S 170 ns; 4.0 V :s VAREF S AVoo
±0.8
%FSR
66 ns
:s tevc s 170 ns; 3.4 V :s VAREF :s AVoo
:s tCYC silO ns
576
TA = -10to +70"C; 66ns
4.0 V s VAREF :s AVoo
tevc
66 ns
432
tCYC
110 ns S tCYc:S 170 ns
96
tCYC
66 ns S tCYC
tCYC
110 ns S tCYC S 170 ns
0
VAREF
tCYc:S 170ns;
:s 110 ns
V
MO
1000
AVoo
V
IAREFI
1.5
3.0
mA
Operation mode
IAREF2
0.7
1.5
mA
Stop mode
3.4
s
±0.4
72
Analog input voltage
0.5 V
bits
Absolute accuracy
(Note 1)
Conversion time
Max
21
..
NEe
pPD78C18 Family
AID Converter Characteristics (cont)
Parameter
Symbol
Typ
Max
Unit
Conditions
AVoo supply current
AIOOt
Min
0.5
1.3
mA
Operation mode; IxTAL = 15 MHz
AI002
10
20
JlA
Stop mode
Notes:
(1) Quantizing error (:tl/2LSB) is not Included.
(2) FSR = full-scale resolution.
Bus Timing Dependent on tCYC
Symbol
Calculation Formula
Symbol
tTIH. IrIL
Min
6T (TI Input - PCa)
tLW
tCltH. tCltL
(Note 2)
Min
6T (TI input -
tCI2H. tCI2L
(Note 3)
Min
tltH. tltL
Min/Max (ns) .
Min
pes>
Min
4T - 100/4T -140 (Note 7)
Min
2T-70
tWL
Min
2T-50
36T (INTI)
tww
Min
4T-50
tCYK
Min
24T (SCK output)
48T (TI Input - PCS>
Min
36T (INT2)
Min
36T (AN4-AN7)
tAL
Min
2T-l00
tLA
Min
T-30
Max
7T-220
tLOR
Max
5T -200
Max
tKKL
aT-l00
tAD
tRO
Calculation Formula
T-50
tow
t12H. tl2L
Min
Min
tWDH
tANH. iANL
tAR
Min/Max (ns)
4T-I50
a,
tKKH
Min
12T (SCK input) (Note 1)
Min
6T (Note 6)
Min
12T - 100 (SCK output)
Min
5T
Min
2.5T + 5 (Note 6)
+ 5 (SCK input) (Note 1)
Min
12T -100(SCK output)
Min
5T
Min
2.5T + 5 (Note 6)
+ 5 (SCK input)
(Note 1)
tLR
Min
T-50
tRL
Min
2T-50
tRR
Min
4T - 50 (Data read)
Min
7T - 50 (Opcode fetch)
tLL
Min
2T-40
tML
Min
2T-l00
tLM
Min
T-30
tiL
Min
2T-l00
(5) The Items not included in this list are independent of oscillator
frequency (lxTAU.
tLi
Min
T-30
(6) 16 x baud rate or 64 x baud rate in asynchronous mode
tAW
Min
aT-l00
(7) JlPD78CPI8/CPI8(A) only.
tLOW
Max
T
22
+
T+
110
130 (Note 7)
(1) 1 x baud rate in asynchronous. synchronous. and I/O interface
modes.
(2) Event counter mode.
(3) Pulse width measurement mode.
(4) T
= icyc = I/1XTAL.
NEe
pPD78C18 Family
Data Memory Stop Mode Data Retention Characteristics
TA = -40 to +85'C
Parameter
Symbol
Min
Data retention power supply voltage
VOOOR
2.5
Data retention power supply ourrent
IOOOR
Typ
15
VOO rise. fall time
tAVO. tFVO
Max
Unit
5.5
V
Conditions
15
JlA
VOOOR = 2.5V
50
JlA
VOOOR = 5.0 V ±10%
200
Jls
STOP setup time to VOO
tSSTVO
12T+O.5
Jls
STOP hold time from VOO
tHVOST
12T+O.5
Jls
23
ABls-ABa
[PFrPFo]
~----------------~D----------------~
AD7"ADO
[PDrPDo]
ALE
~----IRD'-----~
I+------IRR------~
MODEOP~l
[Notal]
.
L~,~"
J.E----IIL-I
~-----------------------------------------------------IU
Not.:
[1]
iO signal Is oulpul to !he MODEO pin [If MODEO Is puned up to V001 durlng a
read or wrlte 01 special registers sr-sr2.
13'/LoI&118
24
NEe
pPD78C18 Family
Timing Waveforms (cont)
Data Write Operation
""'cf----- T1-----i·~I~c----T2-------l.~II""'Ei-----T3-------l·~1
Xl
ADDR15 -ADORa
Data-oul
ALE
~-----Iww----~~
MODEO [101
[Note 11
1 L",~"
~---------------------------
.
t+---IIL~
III
Note:
[11
iO signal Is outpul to the MODEO pin [If MODEO Is puned up to V Dol during a
read or write of spacial reglstalll ....sr2.
83YL-9512B
25
NEe
I'PD78C18 Family
Timing Waveforms (cont)
Opcode Fetch Operation
I
I
1+0--- T1 ---+1_---1"2 --_~....Cfo,---- 1'3 ---~....Cfo,----T4,--~~1
X1
-y:)
ADDR15 -ADDRa
r
tAD
)
I
ALE
Opcode
ADDR7-ADDRO
tLL_
~.~~
L
,
tAR
~----1
r-'~~
i'""~
1
KX
tRDH
I+-tLA
W.
I"E-tRDtRR
.~
~
Note:
[1]
M1 signal .. OIJ1pUtto 1118 MODE1 pin cIu~ng every Opcode Fetch" MODE1
pin Is puned up to VDo- ThIs signal Is not output on 1118 I1PD78CP14.
Timer!Event Counter Input:
Event Counter Mode
26
Timer!Event Counter Input:
Pulse Width Measurement Mode
V
NEe
IIPD78C18 Family
Timing Waveforms (cant)
Serial Operation Transmit!Receive
ICYK
0(
>
_ I K K L _ _ I _ I K K H_ _
t
1-IKlX-
).
TxO
).
RxO
I
(
~tRXK~1 !E
>
IKRX
Timer Input
_1).8951.
External Clock
X1
AC Timing Test Points
VOO-1.0
==::>(2.2V
0.45 V
1+-----tCYC------lI~
83YL-9281A
2.2VC
Test Polnts-0.8 v"'- 0.8 V
Interrupt Input
AN4-AN7 Edge Detection
AN4-7
INT1
RESET Input
27
NEe
pPD78C18 Family
"PD78CP18 PROGRAMMING
In the pPD78CP18, the mask ROM of the pPD78C18
family is replaced by a one-time programmable ROM
(OTP ROM) or a reprogrammable, ultraviolet erasable
ROM (UV EPROM). The ROM is 32,768 by 8 bits and can
be programmed using a general-purpose PROM writer
with a pPD27C256A programming mode. Refer to tables 3 through 5 and the DC and AC Programming
Characteristics tables for specific information applicable to programming the pPD78CP18.
Table 3_
Pin Functions during EPROM
Programming
Pin
Function
PAa-PA7
Aa-A7
Low-order 8-bit address
High-order 7-bit address
PFo
As
NMI
Ag
PFz-PFe
A10-A14
DescriptIon
Data input/output
PDo-POr
0 0-07
PBs
CE
Chip enable input
PB7
DE
Output enable input
RESET
RESET
PROM programming mode requires a
low voltage on this pin
Mode 0
Mode 0
Enter PROM programming mode by
applying a high voltage to this pin
Mode 1
Mode 1
Enter PROM programming mode by
applying a low voltage to this pin
STOP
Vpp
High-voltage input (write/verify) high
level (read)
Table 4. Summary of Operation Modes for EPROM Programming
CE
OE
VDD
Vpp
Operation Mode
RESET
MOOED
Program write
L
H
+12.5V
+6V
L
H
L
Program verify
H
L
+12.5V
+6V
L
H
L
Program inhibit
H
H
+12.5V
+6V
L
H
L
Read
L
L
+5V
+5V
L
H
L
Output disable
L
.H
+5V
+5V
L
H
L
Standby
H
L/H
+5V
+5V
L
H
L
Notes:
(1) The CE, DE, VPP ' and Voo pins are all compatible with the
JlPD27C256A pins.
Caution: When Vpp is set to +12.5 V and VOO is set to +6 V, you
cannot set both CE and DE to low level (L).
Table 5_ Recommended Connections for
Unused Pins (EPROM Programming
Mode)
Pin
Recommended Connection Method
INTI
Connect to Vss
XI
Connect to Vss
X2
Leave this pin disconnected
AND-AN7
Connect to Vss
Connect to Vss
AVoo
Connect to Vss
AVss
Connect to VSS
Remaining pins
Connect each pin via a resistor to Vss
28
MODEl
NEe
pPD78C18 Family
PROM Write Procedure
PROM Read Procedure
(1)
Connect the RESET pin, the MODE1 pin, and A14
pin to a low level and connect the MODEO pin to a
high level. Connect all unused pins as recommended in Table 5.
(1) Connect the RESET pin and the MODE1 pin to a low
level and connect the MODEO pin to a high level.
(2)
Apply + 6 V to the Voo pin and + 12.5 V to the Vpp
pin.
(3) Input the address of the data to be read to pins
Ao-A14'
(3)
Provide the initial address.
(4) Read mode is entered with a pulse (active low) on
both the CE and OE pins.
(4)
Provide write data.
(5)
Provide 1-ms program pulse (active low) to the CE
pin.
(6)
This bit is now verified with a pulse (active low) to
the OE pin. Ifthe data has been written, proceed to
step 8; if not, repeat steps 4 to 6. If the data cannot
be correctly written after 25 attempts, go to step 7.
(7)
Classify as defective and stop write operation.
(8)
Provide write data and supply program pulse (for
additional writing) for 3 ms times the number of
repeats performed between steps 4 to 6.
(9) Increment the address.
(10) Repeat steps 4 to 9 until the end address.
(2) Apply +5 V to the Voo and Vpp pins.
(5) Data is output to the 00-07 pins.
EPROM Erasure
.,.
Data in an EPROM is erased by exposing the quartz . . .
window in the ceramic package to light having a wavelength shorter than 400 nm, including ultraviolet rays,
direct sunlight, and fluorescent light. To prevent unintentional erasure, mask the window.
Typically, data is erased by 254-nm ultraviolet rays. A
minimum lighting level of 15W-s/cm2 (ultraviolet ray
intenSity x exposure time) is required to completely
erase written data Erasure by an ultraviolet lump rated
at 12 mW/cm2 takes approximately 15 to 20 lllinuWs.
Remove any filter on the lamp and place the dovico
within 2.5 cm of the lamp tubes.
29
NEe
IIPD78C18 Family
I'PD78CP18 DC Programming Characteristics
TA = 25 ±5°C; MODEl = Vll; MODEO = VIH; VSS = OV
Parameter
Symbol
Symbol*
Min
High-level input voltage
VIH
VIH
2.2
Low-level input voltage
Vil
Vil
-0.3
Input leakage current
11iP
III
High-level output voltage
VOH
VOH
Low-level output voltage
VOL
VOL
Output leakage current
ILO
Voop power voltage
Voop
Vpp power voltage
Max
Unit
VOOp+0.3
V
0.8
V
±10
pA
IOH = -1.0 mA
V
IOL = 2.0mA
±10
pA
5.75
6.0
6.25
V
Program memory write mode
4.5
5.0
5.5
V
Program memory read mode
12.2
12.5
12.8
V
Program memory write mode
V
Program memory read mode
Vpp
Vpp power current
* Corresponding
Icc
100
Ipp
Os V1 S VOOP
0.45
Vpp=Voop
Voop power current
Condition
V
Voo-l.0
VCC
Vpp
Typ
Os Vo s VOOP; OE = VIH
5.0
50
mA
Program memory write mode
5.0
50
mA
Program memory read mode;
CE = VIL; VI = VIH
30
mA
Program memory read mode;
CE = VIL; OE = VIH
100
pA
Program memory write mode
Ipp
symbols of the pPD27C256A.
I'PD78CP18 AC Programming Characteristics
TA = 25 ±5°C; MODEl = VIL; Vss = OV
Parameter
Symbol
Address setup time to CE !
tSAC
Data to OE ! delay time
tOOOO
Input data setup time to CE !
Address hold time from CE I
Input data hold time from CE I
Output data hold time from OE I
tSIDC
tHCA
tHCIO
tHOOO
Symbol*
Min
tAS
2
ps
tos
2
ps
tAH
2
ps
tOH
2
tOF
0
2
tsvPC
tyPS
tSVOC
tvos
2
Initial program pulse width
tWL1
tpw
0.95
Additional program pulse width
tWL2
topw
2.85
MODEO/MODEl setup time vs. CE I
tSMC
Address to data output time
tOAOO
tAce
CE I to data output time
toeoo
teE
OE I to data output time
tOOOO
tOE
Data hold time from OE I or CE 1
tHeoo
tOF
0
Data hold time from address
tHAOO
tOH
0
30
Unit
tOES
VOOP setup time to CE !
symbols of the pPD27C256A.
Max
ps
Vpp setup time to C E !
* Corresponding
Typ
2
Condition
ps
130
ns
ps
ps
1.0
1.05
ms
78.75
ms
2
2
ps
MODEl = Vil and MODEO = VIH
ps
OE = VIL
ps
ps
130
ns
ns
OE = VIL
NEe
pPD78C18 Family
PROM Timing Diagrams
pPD78CP18 PROM Write Mode
==>
---
EffecUve Address
Data
tnput
~
--
~IOC __
I4=-
Vpp
---
VOOP
--.!
VOOP +1
---
==>
Vpp
VOOP
VOOP
--.!
---
....
I - tSAC
>---<
_
Data
Output
~CIO
--
tHOOO
Data
Input
tSIOC _
I-
-
K
tHCA
~ tHCIO
Mode 1 =VIL
ModeO=VIH
tSMC
tsvpc
I-
tsvoc
i+=.
~
tWLl
r--
---
f.""'l_
I-tWL2-
s
Notes:
(1)
VOOP must be applied balore applying Vpp. H should be removed after removing Vpp.
(2)
Vpp must not exceed +13 V, Including overshoot.
BaRD-6948B
31
NEe
pPD78C18 Family
PROM Timing Diagrams (cant)
pPD78CP18 PROM Read Mode
ElfacUva Address
tHAOO
Data Output
Notes:
(1) To read PROM within the t DAOD range. Ihe delay 01 OE +from eel. must be wfthIn t DAOD" t DODD'
(2) tHCOD Is the !me 110m the _In which either OE or CE ftl1ll beoomea VIH'
32
HI.z
NEe
NEC Electronics Inc.
IIPD78COO Product Line
Programming Reference
September 1993
Operand Definitions
INSTRUCTION SET
Operand Symbols
Symbol
Special registers (sr-sr4)
Allowable Operands
Registers
r
r1
r2
V,A, B,C, 0, E, H, L
EAH,EAL,B,C, 0, E, H, L
A,B,C
Special Registers
sr
PA, PB, PC, PO, PF, MKH, MKL, ANM,
SMH, SML, EOM, ETMM, TMM, MM,
MCC, MA, MB, MC, MF, TXB, TMO,
TM1, ZCM
sr1
PA, PB, PC, PO, PF, MKH, MKL, ANM,
SMH, EOM, TMM, RXB, CRO, CR1,
CR2, CR3
sr2
PA, PB, PC, PO, PF, MKH, ANM, MKL,
SMH, EOM, TMM
ETMO, ETMl
ECNT, ECPT
sr3
sr4
Register Pairs
rp
rp1
rp2
rp3
SP, B, 0, H
V,B,D,H, EA
SP, B, 0, H, EA
B, 0, H
PA = PortA
PB = Port B
PC = Port C
PO = Port
PF = Port F
MA = Mode A
MB = Mode B
MC = Mode C
MCC = Mode control C
MF = Mode F
°
MM = Memory mapping
TMO = Timer register 0
TMl = Timer register 1
TMM = Timing mode
ETMO = Timer/ event
counter register 0
ETM1 = Timer/event
counter register 1
ZCM = Zero-cross mode
control register
ECNT = Timer/event counter
upcounter
ECPT = Timer/event counter capture
ETMM = Timer/event counter mode
EOM = Timer/event counter output
mode
TXB = Transmit buffer
RXB = Receive buffer
SMH = Serial mode high
SML = Serial mode low
MKH = Mask high
MKL = Mask low
ANM = AID channel mode
CRO to CR3 = A/D conversion result
0-3
Register Pairs (rp-rp3)
SP = Stack pointer
B = BC
D = DE
H = HL
V = VA
EA = Extended accumulator
Register Pair Addressing
Register Pair Addressing (rpa-rpa3)
rpa
rpa1
B, 0, H, 0+, H+, 0-, HB,D, H
B = (BC)
rpa2
B, 0, H, 0+, H+, 0-, H-, 0+ byte,
H+A, H+B, H+EA, H+byte
rpa3
0, H, 0++, H++, 0+ byte, H+A,
H+ B, H+ EA, H+ byte
Flags
Interrupt Flags
word
byte
bit
50637
CY = Carry
HC = Half-carry
Z = Zero
Interrupt Flags (lrf)
INTFNMI, INTFTO, INTFT1, INTF1,
INTF2, INTFEO, INTFE1, INTFEIN,
INTFAD, INTFSR, INTFST, ER, OV,
AN4, AN5, ANS, AN?, SB
Immediate Data
wa
D++ = (DE)++
H++ = (HL)++
D+ byte = (DE+ byte)
H+ byte = (HL+ byte)
H+A = (HL+A)
H+B=(HL+B)
H+ EA = (HL+ EA)
Flags (f)
CY, HC, Z
irf
D = (DE)
H = (HL)
D+ = (DE)+
H+ = (HL)+
0- = (DE)H- = (HL)-
B-bit immediate data (low byte of
working register address)
1S-bit immediate data
B-bit immediate data
3-bit immediate data (b2, b j , bo)
INTFNMI = NMI interrupt
flag
INTFTO = FTO
INTFTl = FTl
INTFl = Fl
INTF2 = F2
INTFEO = FED
INTFEl = FEl
INTFEIN = FEIN
INTFAD = FAD
INTFSR = FSR
INTFST = FST
ER = Error
OV = Overflow
AN4 to AN? = Analog input 4-7
SB = Standby
NEe',
IIPD78COO Product Line
Operand Codes
Registers (r, r2)
R2
R1
Ro
0
0
0
0
0
0
0
,,
,, ,,
1
0
0
0
Reg
Special Registers (sr3)
Applicable to
V
A
B
C
0
0
0
E
H
L
r,
Tl
To
0
0
0
0
0
0
0
,,
,,
,
,
1
0
1
0
0
0
0
S4
Sa
S2
SI
So
Special Reg
Applicable to
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
sr, sr', sr2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
PA
PB
PC
PO
PF
MKH
MKL
ANM
SMH
0
SML
sr
EOM
sr, sr1, sr2
ETMM
sr
TMM
sr, sr1, sr2
MM
MCC
MA
MB
MC
MF
TXB
sr
AXB
sr1
0
1
TMO
TMl
sr
0
srI
sr
, ,
,
,,
,
0
0
0
0
1
0
1
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
,
ECNT
ECPT
P2
PI
Po
Reg Pair
Applicable to
0
0
0
SP
rp, rp2
0
0
0
0
1
rp, rp2, rp3
1
0
BC
DE
HL
0
0
EA
rp2
Register Pairs (rp1)
S5
,, ,
Special Reg
Register Pairs (rp, rp2, rp3)
Special Registers (sr, sr1, sr2)
a
Vo
0
EAH
EAL
B
C
E
H
L
ETMO
ETM1
Special Registers (sr4)
Reg
0
Special Reg
1
r2
Register (r1)
T2
Uo
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
1
0
,
0
1
1
CRO
CRl
CR2
CAS
0
0
ZCM
1
Q2
Ql
0
0
0
0
0
,
Qo
1
1
,
,
0
0
a
0
0
Reg Pair
VA
BC
DE
HL
EA
Register Pair Addressing (rpa, rpa1, rpa2)
A3
A2
AI
Ao
0
0
0
0
0
0
0
0
0
0
0
a
1
0
0
0
0
0
0
,
0
1
1
1
1
0
0
a
1
0
1
0
1
0
1
Addressing
Applicable to
rpa, rpa1, rpa2
(BC)
(DE)
(HL)
(DE)+
(HL)+
(DE)(HL)(OE+ byte)
(HL+A)
(HL+B)
(HL+EA)
' (HL+ byte)
'rpa, rps2
rps2
Register Pair Addressing (rpa3)
C3
C2
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
,
Co
Addressing
0
1
0
0
1
(DE)
(HL)
(DE)++
(HL)++
(DE+ byte)
(HL+A)
(HL+B)
(HL+EA)
(HL+byte)
Cl
1
0
1
1
0
0
0
1
1
0
1
1
NEe
IIPD78COO Product Line
Operand Codes (cant)
Graphic Symbols
Flags (f)
Symbol
F2
F1
Fo
0
0
0
0
0
0
1
0
1
1
1
0
Transfer direction, result
Flag
CY
HC
Z
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
1
1
1
0
0
1
1
0
0
0
1
1
1
0
Logical product (logical AND)
V
Logical sum (logical OR)
Exclusive-OR
Complement
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1\
¥-
Interrupt Flags (irf)
1
1
Description
0
Flag
Concatenation
NMI
FTO
FTl
Fl
F2
FEO
FE1
FEIN
FAD
FSR
FST
ER
OV
AN4
AN5
AN6
AN7
SB
3
NEe
pPD78COO Product Line
Instruction Set
Mnemonic
Operand
Operation
Bytes
States
(Note 1)
Skip
Conditions
Operation Code
7
6
5
4.
3
2
0
8-Bit Data Transfer
MOV
rl, A
-rl -A
4
0
0
0
A, rl
A-rl
4
0
0
0
0
*sr, A
sr-A
10
0
0
0
$5
$4
*A, srl
r. word
A+- srl
r-
(word)
2
2
4
10
17
0
0
0
0
$5
$4
T1
To
T2
T1
To
0
1
$0
$3
~
$1
0
0
$3
$2
$1
$0
0
0
0
~ R1
RO
0
1
0
T2
0
Lowaddr
High addr
word, r
(word) - r
4
17
0
0
0
0
0
0
1
~
R1
Ro
R2
R1
Ro
0
0
S2
$1
$0
0
0
0
A1
Lowaddr
High addr
MVI
or, byte
r - byte
2
7
0
0
Data
sr2, byte
sr2 - byte
3
14
0
$3
0
0
0
0
0
0
Data
MVIW
*wa, byte
(yowa) +- byte
3
13
0
0
Offset
Data
MVIX
*rpa1, byte
(rpa1) - byte
2
10
0
0
0
Ao
Data
STAW
*wa
(yowa) -A
2
10
0
0
0
0
Offset
LDAW
*wa
A .... (yowa)
2
10
0
0
0
0
0
0
0
Offset
STAX
LDAX
*rpa2
*rpa2
(rpa2) - A
A- (rpa2)
2
2
7/13
(Note 3)
As
7/13
(Note 3)
A3
Ao
Data (Note 2)
0
0
1 A2
A1
Ao
Data (Note 2)
EXX
B .. B', C ... C', 0 .. 0'
E .. E', H .. H', L .. L.:
4
0
0
EXA
V .. V', A .. A', EA .. EA'
4
0
0
EXH
H-H', L-L.:
4
0
BLOCK
(DE) .... (HL), DE - DE + 1, HL +- HL
+ l,C-C-l
End if borrow
13x
(C+ 1)
0
4
1 A2 A1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NEe
IIPD78COO Product Line
Instruction Set (cont)
States
Mnemonic
Operand
Operation
Bytes
(Note 1)
Skip
Conditions
Operation Code
7
6
5
2
4
3
0
P1
Po
0
0
P1
Po
0
16-8;1 Dsis Trsnsfer
DMOV
rp3, EA
rp3L +- EAL, rp3H +- EAH
4
0
EA, rp3
EAL +- rp3L, EAH +- rp3H
4
0
sr3, EA
sr3 +- EA
2
14
0
0
0
0
EA, sr4
SeeD
word
2
EA +- sr4
(word) +- C, (word
+
1) +- B
4
14
20
0
0
0
0
0
0
0
0
0
0
0
0
0
Uo
0
0
0
0
0
0
Vo
0
0
0
0
0
0
Lowaddr
High addr
SDED
word
(word) +- E, (word
+
1) +- D
4
20
0
0
1
0
0
0
0
0
0
0
Lowaddr
High addr
SHLD
word
(word) +- L, (word
+
1) +- H
4
20
1
0
0
0
0
0
0
0
0
Lowaddr
High addr
SSPD
word
(word) +- SPL' (word
+
1) +- SP H
4
20
·1
0
0
0
0
0
0
0
0
0
0
Lowaddr
High addr
STEAX
rpa3
(rpa3) +- EAL, (rpa3
+
1) +- EAH
3
14120
(Note 3)
0
20
0
0
0
0
0
C3
0
0
0
C:!
C1
Co
0
0
0
0
0
0
0
0
0
Data (Note 4)
LBCD
word
C +- (word), B +- (word
+
1)
4
0
0
0
0
Lowaddr
High addr
LDED
word
E +- (word), 0 +- (word
+
1)
4
20
0
0
0
0
0
Lowaddr
High addr
LHLD
word
L +- (word), H +- (word
+
1)
4
20
0
0
0
0
Lowaddr
High addr
5
•
\
NEe
pPD78COO Product Line
Instruction Set (cant)
Mnemonic
Operand
Operation
~Byte.
States
(Note 1)
4
20
Skip
Conditions
Operation Code
7
6
5
4
0
0
0
3
2
0
0
0
0
0
0
0
C2 Cl
Co
0
16·Bit Osta Transfer (cont)
LSPD
word
SPL .... (word), SPH .... (word + 1)
0
0
Lowaddr
High addr
LDEAX
EAL .... (rpa3),
EAH .... (rps3 + 1)
rps3
3
14/20
(Note 3)
0
0
0
0
0
0
Ca
Data (Note 4)
PUSH
rp1
(SP -1) .... rp1H'
(SP - 2) .... rp1L, SP .... SP - 2
13
0
POP
rp1
rp1L"" (SP), rp1H - (SP + 1)
SP-SP+ 2
10
0
LXI
*rp2, word
rp2-word
3
10
0
1
P2 PI
1
0 O2 0 1 00
0
0 02 01 00
Po
0
0
0
0
0
0
0
0
0
Low byte
High byte
TABLE
C .... (PC + 3 + A),
B - (PC + 3 + A + 1)
8~Bit Arithmetic
ADD
A, r
2
0
17
0
0
A-A+r
2
0
8
r - r+ A
2
0
8
0
ADO
A, r
A-A+r+OY
2
0
0
8
0
0
0
0
0
0
0
R:!
Rl
Ro
0
0
0
0
0
0
0 R2 Rl
Ro
0
0
0
r, A
r-r+A+OY
2
0
8
0
0
ADDDNC
A, r
r, A
A-A+r
r - r+ A
2
2
8
8
No carry
No carry
A, r
A:'-A-r
2
8
0
Rl
Ro
0
0
0
R2 Rl
Ro
0
0
0
0
0
0
0 R2
Rl
Ro
0
0
0
0
0
0
R:!
Rl
Ro
0
0
0
r, A
r-r-A-CY
2
8
0
0
0
0
R:!
0
8
0
0
0
0
2
8
0
0
A-A-r-CY
2
0
Ro
0
A, r
r - r-A
a a a a
a R:! Rl Ro
0 0 a 0
0
a
6
0
0
0
0
0
0 R2 Rl
0
a
a
a
a
r, A
SBB
0
0
0
SUB
1
(Register)
0
r, A
0
0
R2 Rl
Ro
0
a
0
R2
Rl
Ro
NEe
JlPD78COO Product Line
Instruction Set (cont)
Mnemonic
Operand
Operation
Bytes
States
(Note 1)
2
8
Skip
Conditions
Operation Code
7
6
5
o
4
3
2
o
0
0
0
0
o
0
0
0
0
0
0000.
8-Bit Arithmetic (Register) (cont)
SUBNB
A, r
r, A
ANA
A, r
A-A-r
r - r-A
A-A!\r
2
2
8
No
borrow
o
No
borrow
o
8
o
o
o
0
o
r, A
ORA
XRA
GTA
2
R:!
R1
Ro
0
0
0
o
0
0
0
0
o
0
0
0
0
o
0
0
0
0
a
o a a
o
0
a
0
0
No
borrow
o
o
0
a
a
0
No
borrow
o
o
o
0
0
0
0
0
0
0
A-AVr
2
8
o
r, A
r<- rV A
2
8
o
o
o
A, r
A <- A ¥-r
2
8
r, A
r<-r¥-A
2
8
A, r
A-r-1
2
8
A, r
r-A-1
A-r
2
2
8
8
0
0
o
o
8
A, r
r, A
LTA
r-r!\A
0
Borrow
o
0
0
0
0
0
o
0
0
o
0
1R2R1
r, A
r-A
2
8
Borrow
0
EQA
ONA
A, r
A-r
2
8
No zero
0
r, A
r-A
2
8
No zero
A, r
A-r
2
8
Zero
o
r, A
r-A
2
8
Zero
o
o
A, r
A!\r
2
8
No zero
A, r
A!\r
2
8
Zero
R1
Ro
0
0
0
0
o
lR2R1RO
0
0
0
0
o
0
0
0
0
o
0
0
0
0
0
0
0
0
0
------------------00
OFFA
R2
0
0
0
RO
00000
0
NEA
0
-----------------o
-----------------o
------------------o
------------------o
o
o
o
R:!R1Ro
0
0
0
0
7
NEe
JlPD78COO Product Line
Instruction Set (cont)
States
Mnemonic
Operand
Operation
Bytes
(Note 1)
2
11
Operation Code
Skip
Conditions
7
6
5
4
0
0
3
2
0
0
0
0
0
A2
A1
Ao
0
0
0
0
0
A2
A1
Ao
0
0
0
0
0
A2
A1
Ao
0
0
0
0
0
A2
A1
Ao
0
0
0
0
0
A2
A1
Ao
0
0
0
0
0
A2
A1
Ao
0
0
0
A1
Ao
0
8·Bit Arithmetic (Memory)
ADDX
ADCX
rpa
rpa
A
A
+-
+-
A
A
+
+
(rpa)
(rpa)
+
CY
2
0
11
0
0
ADDNCX
rpa
A
+-
A
+
(rpa)
2
11
No carry
0
0
SUBX
rpa
A
+-
A - (rpa)
2
11
0
0
0
SBBX
SUBNBX
ANAX
rpa
rpa
rpa
A
A
A
+-
+-
+-
A - (rpa) - CY
A - (rpa)
A A (rpa)
2
2
2
11
11
0
No
borrow
11
0
0
0
0
0
ORAX
XRAX
GTAX
LTAX
rpa
rpa
rpa
rpa
A
A
+-
+-
A V (rpa)
A ¥-(rpa)
A- (rpa)-l
A- (rpa)
2
2
2
2
11
11
0
0
No
borrow
0
Borrow
0
A2
0
0
0
0
0
0
11
11
0
rpa
A- (rpa)
2
11
No zero
0
0
0
A1
Ao
0
ONAX
rpa
rpa
A- (rpa)
AA (rpa)
2
2
11
11
Zero
No zero
0
OF FAX
rpa
AA (rpa)
2
11
Zero
0
0
0
0
A2
A1
Ao
0
0
Ao
0
0
0
1 A2 A1
Ao
0
0
1 A2 A1
Ao
0
0
8
0
0
Ao
A1
0
0
0
A1
0
0
0
0
A2
A2
0
0
EQAX
Ao
A2
0
0
0
A1
0
0
NEAX
0
A2
0
0
0
0
0
0
0
0
A2
A1
Ao
NEe
pPD78COO Product Line
Instruction Set (cant)
Mnemonic
Operand
Operation
Bytes
States
(Note 1)
2
7
Skip
Conditions
Operation Code
7
6
5
4
0
0
3
2
0
Immediate Data
ADI
*A, byte
A- A + byte
0
0
0
Data
r, byte
r - r + byte
3
11
0
0
0
0
0
0
0
0
R:!
R1
Ro
0
0
S2
S1
So
Data
sr2, byte
sr2 -
sr2 + byte
3
20
0
S3
0
0
0
0
0
0
0
Data
ACI
*A, byte
A - A + byte + CY
2
7
0
0
Data
r, byte
r-r+ byte + CY
3
11
0
0
0
0
0
0
0
R2
R1
Ro
0
0
82
S1
So
Data
Sr2, byte
sr2 -
sr2 + byte + CY
3
20
0
0
0
S3
0
0
Data
ADINC
*A, byte
A-A+ byte
2
7
No oarry
0
0
0
0
0
Data
r, byte
r - r + byte
3
11
No oarry
0
0
0
0
0
0
R2
0
0
R1
Ro
Data
sr2, byte
sr2 -
sr2 + byte
3
20
No oarry
0
S3
0
0
0
0
0
0
0
S2 S1
So
Data
SUI
*A, byte
A .... A- byte
2
7
0
0
0
0
Data
r, byte
r .... r-byte
3
11
0
0
R2
R1
Ro
0
0
S2
S1
So
0
0
0
0
0
0
0
0
S3
0
0
Data
Sr2, byte
sr2 .... Sr2 - byte
3
20
Data
9
I
BII
NEe
pPD78COO Product Line
Instruction Set (cant)
Mnemonic
Operand
Operation
Bytes
States
(Note 1)
2
7
Skip
Conditions
Operation Code
7
6
5
4
3
2
0
Immediate Data (cont)
SBI
*A, byte
A-A-byte-CY
0
0
0
Data
r, byte
r - r-byte-CY
3
11
0
0
0
0
0
0
Rt
Ro
0
0
S1
So
R:!
Data
sr2, byte
sr2 .... sr2 - byte - CY
3
20
0
0
0
0
S3
S2
Data
SUINB
*A, byte
r, byte
A+- A- byte
r - r-byte
2
3
7
11
No
borrow
0
No
borrow
0
0
0
0
Data
0
0
0
0
0
0
R:!
Rt
Ro
0
0
~
St
So
0
0
R:!
Rt
Ro
0
0
S2
S1
So
0
0
R2
Rt
Ro
0
0
S2
S1
So
Data
sr2, byte
sr2 .... sr2 - byte
3
20
No
borrow
0
0
S3
0
0
0
Data
ANI
*A, byte
A- A/\ byte
2
7
0
0
0
0
0
Data
r, byte
r .... r/\ byte
3
11
0
0
0
0
0
0
Data
sr2, byte
sr2 - sr2 /\ byte
3
20
0
0
S3
0
0
0
0
0
0
0
Data
ORI
*A, byte
A ..... AV byte
2
7
0
Data
r, byte
r ..... rV byte
3
11
0
0
0
0
0
Data
sr2, byte
sr2 .... sr2 V byte
3
20
0
S3
0
0
0
0
Data
10
NEe
IIPD78COO Product Line
Instruction Set (cont)
Mnemonic
Operand
Operation
Bytes
States
(Note 1)
2
7
Operation Code
Skip
Conditions
7
6
5
0
0
0
4
3
2
0
Immediate Data (cont)
XRi
*A, byte
A~A.l,Lbyte
0
0
Data
r, byte
r
<-
r .l,Lbyte
3
11
0
0
0
0
0
0
0
0
R2
R1
Ro
0
0
S2
S1
So
0
0
R2
R1
Ro
a
0
S2
81
So
0
0
R2
A1
Ao
0
0
82
81
80
0
0
A2
A1
Ao
0
0
81
So
Data
sr2, byte
sr2
<-
sr2 .l,L byte
3
20
0
S3
0
0
0
0
0
Data
GTI
*A, byte
r, byte
A - byte - 1
r - byte - 1
2
3
7
11
No
borrow
0
No
0
borrow
0
0
0
Data
0
0
0
0
Data
sr2, byte
sr2 - byte-1
3
14
No
borrow
a
0
Sa
0
0
0
a
0
Data
LTI
*A, byte
A - byte
2
7
Borrow
0
Data
r, byte
r- byte
3
11
Borrow
0
0
0
0
Data
sr2, byte
sr2 - byte
3
14
Borrow
0
0
Sa
0
0
Data
NEI
*A, byte
A - byte
2
7
No zero
0
0
0
Data
r, byte
r- byte
3
11
No zero
0
0
0
0
0
0
Data
sr2, byte
sr2 - byte
3
14
No zero
Sa
0
82
0
Data
11
--
NEe
pPD78COO Product Line
Instruction Set (cont)
States
Mnemonic
Operand
Operation
Bytes
(Note 1)
2
7
Operation Code
Skip
Conditions
7
6
5
4
3
0
2
Immediate Data (cont)
EQI
*A, byte
A- byte
Zero
0
0
Data
r, byte
r- byte
3
11
Zero
0
0
0
R2
0
0
R1
Ro
0
0
Data
sr2, byte
sr2 - byte
3
14
Zero
0
0
0
1 8 2 8 1 80
83
Data
ONI
*A, byte
A /\ byte
2
7
no zero
0
0
0
0
Data
r, byte
r /\ byte
3
11
no zero
0
0
0
0
0
0
0
1 R2 R1
Ro
Data
sr2, byte
sr2/\ byte
3
14
no zero
0
0
0
83
0
0
0
0
82
8 1 80
0
0
R2
R1
Ro
0
0
82
81
80
0
0
0
0
Data
OFFI
*A, byte
A /\ byte
2
7
zero
0
0
0
Data
r, byte
r /\ byte
3
11
zero
0
0
0
0
Data
sr2, byte
sr2 /\ byte
3
14
zero
0
0
83
0
0
Data
Working Register
ADDW
wa
A <-- A
+ f:Jowa)
3
14
0
0
0
0
0
0
Offset
ADCW
wa
A <-- A
+ f:Jowa) + CY
3
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Offset
ADDNCW
wa
A <-- A
+ f:Jowa)
3
14
No carry
0
0
0
0
0
Offset
8UBW
wa
A<-- A- f:Jowa)
3
14
0
0
Offset
12
0
NEe
pPD78COO Product Line
Instruction Set (cont)
States
Mnemonic
Operand
Operation
Bytes
(Note 1)
3
14
Operation Code
Skip
Conditions
7
6
5
4
3
0
2
Working Register (cont)
SBBW
wa
A
~
A - CJowa) - CY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Offset
SUBNBW
wa
A
~
A- CJowa)
3
14
No
borrow
0
0
0
0
Offset
ANAW
wa
A ~ A /\ CJowa)
3
14
0
0
0
0
0
Offset
ORAW
wa
A ~ A V CJowa)
3
0
14
0
0
0
Offset
XRAW
wa
A ~ AVCJowa)
3
0
14
0
0
0
0
Offset
GTAW
wa
A - CJ owa)-1
3
14
No
borrow
0
Borrow
0
0
0
0
Offset
LTAW
wa
A - CJowa)
3
14
a
0
0
Offset
NEAW
wa
A - CJowa)
3
14
No Zero
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
a
0
0
0
0
0
0
Offset
EOAW
wa
A - CJowa)
3
14
Zero
0
Offset
ONAW
wa
A/\ (Vowa)
3
14
No zero
0
0
0
0
Offset
OFFAW
wa
A /\ /yowa)
3
14
Zero
0
0
0
Offset
ANIW
*wa, byte
CJowa) ~ CJowa) /\ byte
3
19
0
0
0
0
0
0
Offset
Data
ORIW
·wa, byte
CJowa) +- CJowa) V byte
3
19
0
0
0
0
0
Offset
Data
13
•
NEe
pPD78COO Product Line
Instruction Set (cant)
Mnemonic
Operand
Operation
Bytes
States
(Note 1)
3
13
Skip
Conditions
Operation Code
7
6
No
borrow
0
0
Borrow
0
5
4
3
0
0
2
0
Working Register (cont)
GTIW
*wa, byte
rt-wa) - byte - 1
0
Offset
Data
LTIW
*wa, byte
3
rt-wa) - byte
13
0
0
0
Offset
Data
NEIW
'wa, byte
3
rt-wa) - byte
13
No zero
0
0
0
0
Offset
Data
EQIW
'wa, byte
3
rt°wa) - byte
13
Zero
0
0
0
Offset
Data
ONIW
'wa, byte
3
rt°wa) /\ byte
13
No zero
0
0
0
0
0
Offset
Data
OFFIW
'wa, byte
rt°wa) /\ byte
3
13
Zero
0
0
0
0
Offset
Data
16-Bit Arithmetic
EADD
EA, r2
EA <- EA +r2
2
11
0
0
DADO
DADC
EA, rp3
EA, rp3
EA <- EA + rp3
EA <- EA + rp3
2
+
CY
2
11
0
0
0
0
0
11
0
0
DADDNC
EA, rp3
EA<- EA + rp3
2
11
No carry
0
0
0
ESUB
EA, r2
EA <- EA- r2
2
11
0
0
0
DSUB
EA, rp3
EA .... EA-rp3
2
11
DSUBNB
DAN
DOR
14
EA, rp3
EA, rp3
EA, rp3
EA, rp3
EA<-EA-rp3-CY
EA <- EA- rp3
EA <- EA /\ rp3
EA <- EA V rp3
2
2
2
2
11
11
11
11
0
No
borrow
0
0
0
0
Rl
Ro
0
0
0
0
Pl
Po
0
0
0
0
Pl
Po
0
0
0
0
Pl
Po
0
0
0
0
0
0
Rl
Ro
0
0
1
Pl
Po
0
0
0
DSBB
0
0
0
0
0
0
0
Pl
Po
0
0
0
0
0
0
0
0
0
0
0
0
0
1
P1 Po
0
0
P1 Po
0
0
0
0
Pl
Po
NEe
pPD78COO Product Line
Instruction Set (cant)
States
Mnemonic
Operand
Operation
Bytes
(Note 1)
2
11
Skip
Conditions
Operation Code
7
6
5
o
0
4
3
o
2
16-Bit Arithmetic (cont)
DXR
DGT
DLT
EA, rp3
EA, rp3
EA, rp3
EA--- EAVrp3
EA-rp3-1
2
EA- rp3
2
11
11
o
No
borrow
o
Borrow
0
o
o
o
0
o
o
o
0
o
o
o
ONE
EA, rp3
EA- rp3
2
11
No zero
DEQ
EA, rp3
EA- rp3
2
11
Zero
DON
EA, rp3
EA f\ rp3
2
11
No zero
0
o
o
0
0
0
0
0
PI
Po
0
0
0
0
PI
Po
o
0
------------------------------------o
0
DOFF
EA, rp3
EA f\ rp3
2
11
Zero
o
o
o
Multiply/Divide
MUL
12
EA---Axr2
2
o
32
0
000
0
000
DIV
12
EA --- EA + 12, 12 --- Remainder
2
59
o
o
0
o
o
o
0
000
0
Increment/Decrement
INR
12
12---12+1
INRW
·wa
/Y°wa) --- /yowa)
+ 1
2
4
Carry
16
Carry
o
0
0
0
0
Offset
INX
rp
rp--- rp + 1
7
EA
EA---EA+1
7
OCR
12
12+-12-1
4
Borrow
DCRW
'wa
/y°wa) <- /yowa) - 1
16
Borrow
2
o
0
PI
Po
o
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Rl
Ro
0
0
0
0
------------------Offset
DCX
rp
rp --- rp-1
7
EA
EA +- EA-1
7
o
0
PI
Po
o
1
0
o
0
0
0
0
0
0
0
Others
o
OM
Decimal Adjust Accumulator
STC
CY+-1
2
8
o
o
o
CLC
Cy ... O
2
8
000
NEGA
A---A+1
2
8
4
o
0
0
000
o
000
000
o
o
000
o
0
0
0
o
0
0
15
NEe
pPD78COO Product Line
Instruction Set (cant)
States
Operand
Mnemonic
Operation
Bytes
Skip
(Note 1) Conditions
Operation Code
7
6
5
4
3
o
2
RotatEland Shift
RLD
RRD
RLL
12
RLR
12
2
Rotate right digit (HL)7_4 +- A3-0,
(HL)3-o .... (HL)7_4, ~-o .... (HLl3_o
2
17
2
8
o
2
8
o
o
o
12m _ 1 +- 12m, r27 +- CY, CY +- 120
17
o
SLL
12
2
8
SLR
12
2
8
SLLC
000
Rotate left digit Aa-o .... (HL)7-4,
(HLh_4 .... (HL)3_0, (HL)3-0 +- A3-0
12
2
8
Carry
000
0
000
000
000
o
o
o
o
o
0
0
000
0
0
0
o
0
000
DRLL
DRLR
DSLL
DSLR
12
EA
EA
EA
EA
12m - 1 +- 12m, r2r +- 0,
CY +- 120
2
EAn + 1 .... EAn, EAo +- CY,
CY- EA15
2
EAn _ 1 .... EAn, EA15 .... CY,
CY .... EAo
2
EAn + 1 .... EAn, EAo .... 0,
CY .... EA15
2
EAn _ 1 .... EAn, EA15 .... 0,
CY +- EAo
2
PC -word
3
8
Carry
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rl
Ro
0
0
0
00000
SLRC
0
o
o
0
0
R1Ro
0
0
0
000000R1Ro
8
o
0
0
o
8
o
0
0
o
8
o
0
0
o
8
o
0
0
0
0
0
o
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o
0
0
0
0
0
Jump
JMP
·word
10
o
o
o
Lowaddr
High addr
JB
4
JR
word
JRE
·word
o
o
0
0
0
0
+ 1 + jdisp1
PC .... PC + 2 + jdisp
2
10
o
o
0
PC .... EA
2
8
o
o
o
0
000
o
000
PC .... PC
jdisp1
10
jdisp
JEA
16
0
NEe
pPD78COO Product Line
Instruction Set (cont)
Operand
Mnemonic
Operation
Bytes
States
Skip
(Note 1) Conditions
Operation Code
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
Call
CALL
"word
(SP - 1) ..... (PC + 3)H,
(SP - 2) ..... (PC + 3)l,
PC +- word, SP +- SP - 2
3
(SP - 1) ..... (PC + 2)H,
(SP - 2) ..... (PC + 2)l, PCH <- B,
PCl ..... C, SP +- SP - 2
2
(SP - 1) ..... (PC + 2)H,
(SP - 2) ..... (PC + 2lL,
PC1S-11 ..... 00001,
PC lO -0 <- la, SP ..... SP - 2
2
16
0
0
Low Addr
High Addr
CALB
CALF
*word
CALT
word
(SP -1) ..... (PC + l)H,
(SP - 2) ..... (PC + I)L,
PCl <- (128 + 21a),
PCH <-- (129 + 21a), SP
SOFTI
word
(SP - 1) <-- PSw,
(SP - 2) ..... (PC + I)H,
(SP - 3) <-- (PC + Ill, PC
SP ..... SP-3
17
0
0
13
0
0
1
0
0
ISH
faL
16
<--
0
0
ta
SP - 2
16
<--
0
0
0
0
0060H,
Return
RET
PCL ..... (SP), PCH ..... (SP + 1),
SP ..... SP + 2
10
RETS
PCL <- (SP), PCH ..... (SP + 1),
SP ..... SP + 2, PC <- PC + n
10
RETI
PCL ..... (SP),
PCH +- (SP + 1), PSW +- SP + 2,
SP +- SP +3
13
Unconditional
Skip
0
0
0
0
0
0
0
0
0
0
0
0
Skip
BIT
"bit, wa
Skip il (y"Wa) bit = 1
2
10
Bit Test
0
0
B2
Bl
Bo
Offset
SK
Skip iff
=1
2
8
1= 1
0
0
SKN
Skip iff
=0
2
8
1= 0
0
0
SKIT
SKNIT
ir!
irl
Skip if ir! = 1, then reset ir!
Skip il ir! = 0; Reset irl il irl = 1 and
don' skip
2
2
8
8
ir! = 1
ir! = 0
0
0
0
0
0
0
0
0
0
F2
F1
Fo
0
0
0
0
0
0
0
0
14
0
0
0
0
0
F1
Fo
0
0
0
13
12
11
10
0
0
0
13
12
11
10
0
14
0
F2
17
•
NEe
pPD78COO Product Line
Instruction Set (cant)
States
Mnemonic
Operand
Operation
Bytes
Operation Code
Skip
(Note 1) Conditions
7
6
5
4
3
0
0
0
0
2
0
CPUContro/
NOP
No operation
4
EI
Enable Interrupt
4
01
Disable Interrupt
HLT
Set HALT mode
0
0
4
2
12
0
0
0
STOP
Set STOP mode
2
12
0
(1) For the skip condition. the idle states are as follows:
1-byte instructions: 4 states
2-byte instructions: 8 states
3-byte instructions: 11 states
2-byte instructions with*: 7 states
3-byte instructions with*: 10 states
4-byte instructions: 14 states
(2) B2 (Data): rpa2 = 0+ byte or H+ byte.
(3) Right side of slash (!) in states indicates the case when rpa2
or rpa3 = 0+ byte. H+ A. H+ B. H+ EA. or H+ byte.
(4) B3 (Data): rpaa = 0+ byte or H+ byte.
18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Notes:
0
0
0
0
NEe
NEe
pPD78KO Product Line
Section 3
"PD78KO Product Line
8-Blt, K-Serles Mlcrocontrollers
3-e
3-b
"PD78044 Family
(IlPD78042/043/044/P044)
8-Bit, K-Series Microcontrollers
With FIP (VP) ControlierlDriver and AID
Converter
3-f
"PD78014 Family
(IlPD78011 B/012B/013/014/P014)
8-Bit, K-Series Microcontrollers
General Purpose with AID Converter
3-c
"PD78054 Family
(IlPD78052/053!054/P054)
8-Bit, K-Series Microcontrollers
With UART, AID and D/A Converters
"PD78014Y Family
(IlPD78011 BY/012BY/013Y/014Y/P014V)
8-Bit, K-Seiies Microcontrollers
General Purpose with AID Converter and 12C
Bus
3-d
"PD78002 Family
(IlPD78001 B/OO2B/P014)
8-Bit, K-Series Microcontrollers
General Purpose
3-8
"PD78002Y Family
(IlPD78001 BY/OO2BY/P014V)
8-Bit, K-Series Microcontrollers
General Purpose with 12C Bus
"PD78064 Family
(IlPD78062/063/064/P064)
8-Bit, K-Series Microcontrollers
With LCD Controller!Driver, UART, and AID
Converter
3-g
"PD78KO Product Line
Programming Reference
3-h
NEe
NEG Electronics Inc.
IIPD78002 Family
(pPD78001 B/002B/P014)
8-Bit, K-Series Microcontrollers
General Purpose
September 1993
Description
The pPD78001B, pPD78002B, and pPD78P014* are
members of the K-Series® of microcontrollers. The
pPD78P014 is used for prototyping since the pPD78014
family is pin and function compatible with, and the
features are a superset of, the pPD78002 family. The
features of the pPD78002 family include bit manipulation instructions, four banks of main registers, an
advanced interrupt handling facility, and a powerful set
of memory-mapped on-chip peripherals. On-board
data memory includes 256,384, or 1024 bytes of internal high-speed RAM. Program memory options include
8K or 16K bytes of mask ROM, or 32K bytes of internal
UV EPROM or one-time programmable (OTP) ROM.
o Timers
- Watchdog timer
- Two 8-bit timer/event counters usable as one
16-bit timer/event counter
- Clock (watch) timer (time of day tick from either
oscillator)
o 53 I/O lines
- Two CMOS input-only lines
-47 CMOS I/O lines
- Four n-channel, open-drain I/O lines at 15 V
maximum
o I/O port pullup resistors
-Software controllable on 47 lines
- Mask option on four lines on ROM versions
o Program memory
-/JPD7B001B: BK bytes ROM
-pPD7B002B: 16K bytes ROM
- pPD7BP014: 32K bytes EPROM/OTP
The /JPD78002 family operates over a wide voltage
range: 2.7 to 6.0 volts. Timing is generated by two
built-in oscillators. A main oscillator normally drives
the CPU and most peripherals and at 10 MHz provides
a minimum instruction time of 0.4 ps. A subsystem
oscillator at 32.768 kHz provides time keeping, and
optionally a slow clock for the CPU. Si nce CMOS power
dissipation is directly proportional to clock rate, the
pPD78002 family provides a software variable CPU
clock. The HALT and STOP modes are two additional
power saving features that turn off parts of the microcontroller to reduce power consumption. A data retention mode permits RAM contents to be saved down to 2
volts.
o Powerful instruction set
-16-bit arithmetic and data transfer instructions
-i-bit and 8-bit logic instructions
The range of peripherals, including timers and a serial
port, makes these devices ideal for applications in
portable battery-powered equipment, office automation, communications, consumer electronics, home
appliances, and fitness equipment.
o Minimum instruction execution times:
- 0.4/0.8/1.6/3.2/6.4 ps program selectable using
10-MHz main system clock
-122 ps selectable using 32.76B-kHz subsystem
clock
Features
o Memory-mapped on-Chip peripherals (special
function registers)
o One-channel serial communication interface
- 8-bit clock synchronous interface 0
- Full-duplex, three-wire mode
- NEC serial bus interface (SBI) mode
- Half-duplex, two-wire mode
• See the tIP078014 family data sheet for the tIP078P014
electrical and functional specifications.
K-Serles is a registered trademark of NEe Electronics, Inc.
50807
o Internal high-speed data memory
-pPD7B001B: 256 bytes RAM
-pPD7B002B: 384 bytes RAM
- pPD78P014: 1024 bytes RAM
o External memory expansion
- 64K byte total memory space
o Programmable priority, vectored-interrupt
controller (two levels)
o Buzzer and clock outputs
o Power saving and battery operation features
- Variable CPU clock rate
-HALT mode
-STOP mode
-2-V data retention mode
o CMOS operation; Voo from 2.7 to 6.0 V
NEe
pPD78002 Family
Pin Configurations
Ordering Information
Part Number
ROM
JlPD78001 BCW.xxx
8Kmask ROM
JlPD78002BCW-xxx
16K mask ROM
JlPD78001 BGC-xxx-AB8
8Kmask ROM
JlPD78002BGC-xxx-AB8
16K mask ROM
JlPD78P014GC-AB8
(Note 3)
32KOTP ROM
JlPD78P014DW (Note 3)
32KlN EPROM
Package
(Package Dwg.)
64-pin plastic
shrink DIP
(P64C-70-750 A. C)
64-pin plastic QFP
(P64GC·80-AB8-2)
64-pin ceramic
shrink DIP w/window
(P64DW-70-750A)
Notes:
(1) xxx indicates ROM code suffix
(2) All devices listed are standard quality grade
(3) See the JlPD78014 family data sheetfor the JlPD78P014 electrical
and functional specifications
64-Pin Plastic Shrink DIP
P20
P21
P22
P2a
~
P2sfSIOISBO
P:!eISOOISBI
I'2JISOKO
P3Q
P31fTOi
P32fT02
P3:fT11
P34T12
P3sfPOL
P3efBUZ
103
102
P17
Pie
P15
P14
P13
P12
P11
P10
101
P04fXT1
XT2
ICO
XI'
P37
X2
vss
VOO
POaflNTP3
P02-'lNTP2
POlnNTPI
POonNTPO
RESET
P&pASTB
P8&'WAIT
P6sfWR
P6.vRD
o
P4ofAO
P411ADI
P42-'~
P4a1A03
P44fA04
P4s1ADS
P4efAD6
P471AD?
PSoIAe
P511Ae
P52-'Al0
P5a1All
P54fA I2
P5s1A13
VSS
Pea
P62
PSI
P80
PfryA15
PSelA14
Notes:
(1) Ccnnect ICO, 101, and 103 Qnlernally ccnnected) pins to VSS.
(2) Ccnnect 102 to VOo-
2
NEe
pPD78002 Family
Pin Configurations (cont)
64-Pin Plastic QFP
M~~~OO~~s~~~ro~~oo~
0
P30
1
P3lfTOl
2
Pl0
P3;!T02
3
ICl
48
Pll
P3afTil
P04lXTl
P34T12
XT2
P3s/PCL
ICO
P3eJBUZ
Xl
P37
X2
Vss
VDD
P4o'ADO
P4l/AD1
P03l'INTP3
P42fAD2
P01/1NTPl
P431'AD3
POo'lNTPO
P02flNTP2
P441'AD4
RESET
P4s/AD s
P67/ASTB
a
P6s'WAIT
P4&,AD
Noles:
(1) ConnecllCO, IC1, and 1C3 (Intemally connected)
pins to VSS'
(2) Connect IC2 to VDD'
83R0-947BB
3
NEe
pPD78002 Family
Pin Functions; Normal Operating Mode
Symbol
Plo- P17
FIrst Function
Symbol
Alternate Function
Port 0; 5-bit, bit sele.ctable 110 port
(Bits 0 and 4 are Input only)
INTPO
INTPl
INTP2
INTP3
External maskable interrupt
XT1
Crystal oscillator or external clock input for
subsystem clock
SIO
SBO
Serial data input 3-wlre serial I/O mode
2/3-wire serial I/O mode
SOO
SBl
Serial data output 3-wlre serial I/O mode
2/3-wire serial 110 mode
SCKO
Serial clock I/O for serial interface 0
Port 1; B-bit, bit-selectable
110 port
Port 2; B-bit, bit-selectable I/O port
P2s
Port 3; B-bit, bit-selectable I/O port
P30
P~
TOl
Timer output from timer 1
T02
Timer output from timer 2
Til
External count clock input to timer 1
TI2
External count clock input to timer 2
P3s
PCl
Programmable clock output
PSs
PSr
BUZ
Programmable buzzer output
ADo-AD?
low-order B-blt multiplexed address/data bus
for external memory
110 port
P40 - P47
Port 4; B-bit
P50 - P57
Port 5; B-bit, bit selectable
110 port
Port 6; B-bit, bit selectable (P60 to P63 n-channel
open-drain 110 with mask option pullup resistors;
P64 - P67 I/O). See note.
P6S
High-order B-bit address bus for external
memory
RD
External memory read strobe
WR
External memory write strobe
ASTB
Address strobe used to latch address for
external memory
P6s
External memory wait signal input
P67
RESET
External system reset input
Xl
Crystallceramic resonator connection or external
clock input for main system clock
X2
Crystallceramic resonator connection or Inverse of
external clock for main system clock
XT2
Crystal osci lIator or left open when using external
clock for subsystem clock
Voo
Power supply input
Vss
Power supply ground
ICOto IC3
Internal connection
Note:
4
See table 3 and figure 4 for details.
NEe
pPD78002 Family
Block Diagram
1011P31 ~ 8·bltTlmerl ~
TI11P33
Evant Counter 1
General Reg.
Intarnal
Program Memory
(ROM)
Notal
Watch TImer
::::
SCKOIP27
INTPOIPOo·
I<=>
ADoIP4oAD-r1P47
:jse~lnW~o~
:::1. .____..~
~
InWrrupt
BUZIP3s
~
'---_......!'n"
INTP3IP03 ~
Controllar
PCUP3S
AsIPSO·
Extemal
A1SIP5 7
Access ~ RDlP64
P04/XTl XT2 Xl X2
t
~WRlP65
I I I
RESET VOO
VSS
~WAITfP66
~ASTBIP67
ICO·
103
NoIaa:
(1) 1ba Intama! ROM and RAM aim dependent on Iha device.
83AD-9477B
5
NEe
pPD78002 Family
"PD78002 and "PD78014 Family Differences
Internal System Clock Generator
The JlPD78002 family is pin compatible with the
IlPD7B014 family and shares the same programmable
device, the IlPD7BP014. The IlPD7BOO2 family offers a
reduced set of features. Table 1 lists only the differences between the two families. All other features not
listed are identical for both.
The internal system clocks of the IlPD78002 family are
derived from either the main system or the subsystem
oscillator. See figure 1. The clocks for the watch timer
and programmable clock output are derived from either
the subsystem clock (fXT) or the main system clock. The
clocks for all other peripheral hardware are derived
from the main system clock.
Table 1. Differences Between pPD7BOO2 and
pPD7B014 Families
The CPU clock (>------1
Voo
date~
OUtputdlsable~
ryp. 2 (POD' RESET)
IN
----'[90>-----;>~
.----,>-*--<> IN/OUT
..
0-0
Schmitt IIIgger Input WIth hysteresis characteristics
!
pullup enable
-------11>
pullup enable
-------1>>------1
Voo
date
t----,-+--<>
----.--r----.....j>-__H_>-
IN/OUT
t---
IN/OUT
open drain
output disable - - _ - - I - , ; '
In~.~e------~
Type 13-8 (PlIo' P83l
Voo
~
pullup enable
-------11>
[Mask OpUon)
Voo
t--1.......--<> IN/OUT
~
~
,..---t---<>
date _ _ _ _ _~
output disable
~
IN/OUT
N-ch
Voo
Ro----I~
Inputanable - - - - - - - - - '
Middle-High Voltage Input Buffer
83CL·9481B
(WI>
13
NEe
pPD78002 Family
Serial Interface
The JlPD78002 family has one serial interface. Serial
interface 0 is an 8-bit clock synchronous serial interface (figure 5). It can be operated in either a three-wire
serial I/O mode, NEC serial bus interface (561) mode, or
two-wire serial I/O mode. The serial clock can be provided from one of eight internal clocks, the output of
8-bit timer register 2, or the external clock line SCKO.
Figure 5. Serial Interface 0
SIOI
SBO{
P2s
0
soot
SB11
0
P2e
FromP2e
OUtput Latch
Internal Bus
14
NEe
pPD78002 Family
In the three-wire serial I/O mode, the 8-bit shift register
(SIOO) is loaded with a byte of data and eight clock
pulses are generated. The falling edge of these eight
pulses shifts the byte of data out of the SOO line (either
MSB or LSB first) while the rising edge of these pulses
shifts the data in from the SIO line providing full-duplex
operation. The INTCSIO interrupt is generated after
each 8-bit transfer.
The NEC SBI mode is a two-wire high-speed proprietary
serial interface available on most devices in the NEC
JlPD75xxx and JlPD78xxx product lines. Devices are
connected in a master/slave configuration (see figure
6). There is only one master device at a time; all others
are slaves. The master sends addresses, commands,
and data over one of the serial bus lines (SBO or SB1)
using a fixed hardware protocol synchronized with the
SCKO line. Each slave device of the JlPD78002 family
can be programmed to respond in hardware to anyone
of 256 addresses set in its slave address register (SVA).
There are also 256 commands and 256 data types.
Since all commands are user definable, many software
protocols, simple or complex, can be defined. It is even
possible to develop commands to change a slave into a
master and the previous master into a slave.
Figure 6. 5S1 Mode Master/Slave Configuration
DO
Master CPU
Slave cpu
(881),sao
S80,(881)
Address 1
SCK
SCK
Slave CPU
I-~'II
Address 2
~ISCK
,
:~:)
t-t~
AddressN
The two-wire serial I/O mode provides half-duplex operation using either the SBO or SB1 line and the SCKO
line. Communication format and handshaking can be
handled in software by controlling the output levels of
the data and clock lines between transfers. For data
transmission, the 8-bit shift register (SIOO) is loaded
with a byte of data and eight clock pulses are generated. The falling edge of these eight pulses shifts the
byte of data out of either the SBO or SB1 line MSB first.
In addition, this byte of data is also shifted back into
SIOO on the rising edge of these pulses providing a way
of verifying that the transmission was correct.
For data reception, the SIOO register is pre loaded with
the value FFH. As this data value is shifted out on the
falling edge of the serial clock, it disables the n-channel
open-drain driver. This allows the receive data to be
driven on to the serial line and shifted into the SIOO
register on the rising edge of the serial clock. The
INTCSIO interrupt is generated after each 8-bit transfer.
Timers
The JlPD78002 family has two 8-bit timer/event
counters that can be combined for use as a 16-bit
timer/event counter, a watch timer, and a watchdog
timer. All of these can be programmed to count a
number of prescaled values of the main system clock.
In addition, the watch timer can also count the subsystem clock. The two timer/event counters can count
external events.
8-Bit Timer/Event Counters 1 and 2. Timer/event
counters 1 and 2 (figure 7) each consist of an 8-bit
timer (TM1 or TM2), an 8-bit compare register (CR10 or
CR20), and a timer output control logic (T01 or T02).
The timers are controlled by registers TCL1, TMC1, and
TOC1 via five seletors. Timer/event counters 1 and 2 can
each be used as an 8-bit interval timer, to count
external events onthetimer input pins (T11 orTI2), orto
output a programmable square wave. In addition, timers 1 and 2 also can be combined as a 16-bit timer/
event counter and used as a 16-bit interval timer, to
count external events on T11, or to output a programmable square wave on T02.
SCK
83YL-9347A (9193)
15
•
.
1,,:'
'
NEe
pPD78002 Family
Figure 7. 8-8lt Timer!Event Counters 1 and 2
IntemaiBus
1----t_----------_INTTM1
8·BII
llrnar/Event
Counter 2
Oulpul
Control LogIc
T02IP32
Clear
1----f--~T011P31
* Rising or taRing edga can be selecll!d.
16
NEe
IIPD78002 Family
Watch Timer. The watch timer (figure 8) is a 5-bit timer
that can be used as a time source to keep track of time
of day, to release the STOP or HALT modes at regular
intervals, or to initiate any other task that must be
performed at regular intervals. When driven by the
subsystem clock, the watch timer continues to operate
in the STOP mode.
The watch timer can function as both a watch timer and
an interval timer simultaneously. When used as a watch
timer, interrupt request INTWT (not a vectored interrupt) can be generated using a main system clock or a
subsystem clock every 0.5 or 0.25 seconds.
When used as an interval timer, vectored interrupt
request INTTM3 is generated at preselected time intervals. With a main system clock of 8.38 MHz or a
subsystem clock of 32.768 kHz, the following time
intervals can be selected: 489 jJs, 978 jJs, 1.96 ms, 3.91
ms, 7.82 ms or 15.6 ms.
Figure 8.
•
Watch Timer
r -_ _ _ _~Selector
Selector
INlWT
Clear
fX128 _
Selector I--'-fw.......~1
P"'-=-,---+I
Salector
1---+----+-----+--~INTTM3
Clear
Intemal Bus
83CL....... (7Il13)
17
NEe
pPD78002 Family
Watchdog Timer. The watchdog timer (figure 9) can be
used as either a watchdog timer or an interval timer.
When used as a watchdog timer, it protects against
program run·away. It can be selected to generate a
nonmaskable interrupt (INTWOl), which vectors to address 0004H, or to generate an internal reset signal,
which vectors to the restart address OOOOH if the timer
is not cleared by the program before it overflows. Eight
program-selectable intervals based on the main system clock are available. With a main system clock of
8.38 MHz, the program selectable intervals are 0.489,
0.978, 1.96, 3.91, 7.82, 15.6, 31.3, and 125 ms. Once the
watchdog timer is initialized and started, the timer's
mode cannot be changed and the timer can only be
stopped by an external reset.
When used as an interval timer, maskable interrupts
(I NTWOl) , which vector to address 0004H, are generated repeatedly at a preset interval. The time intervals
available are the same as in the watchdog timer mode.
Figure 9.
Watchdog Timer
Run
INlWDT
Maskable
Interrupt
Request
8-Blt
Counter
ConttOl
logic
1-----------+----.. RESET
INlWDT
Nonmaskable
Interrupt
Request
Internal Bus
B3YL-9352B (8(93)
18
NEe
IIPD78002 Family
Programmable Clock Output
Buzzer Output
The J.lPD78002 family has a programmable clock output
(PCl) that can be used for carrier output for remote
controlled transmissions or as a clock output for peripheral devices. The main system clock (fx) divided by
8, 16, 32, 64, 128, or 256 or the subsystem clock (fXT)
can be output on the PCl pin. Frequencies of 1050, 524,
262, 131, 65.5 and 32.7 kHz are available with a main
system clock of 8.38 MHz. See figure 10.
The J.lPD78002 family also has a programmable buzzer
output (BUZ). The buzzer output frequency can be
programmed to be equal to the main system clock (fx)
divided by 1024, 2048, or 4096. With a main system
clock of 8.38 MHz, the buzzer cal) be set to 8.2, 4.1 or 2.0
kHz. See figure 11.
Figure 10. Programmable Clock Output
'XI23_--~
'XI24--~~
'XI25--~~
'x126 ---~ Selector
'x127 -----,~
'xI28_--~
'XT---~
Figure 11. Buzzer Output
'x1210 ---~
'x/211 ---~ Selector
1-----------'1_>-____--1
'x12 12 ---~
I13YL-f364B
19
NEe
pPD78002 Family
Interrupts
The J.lP078002 family has 11 maskable hardware interrupt sources (5 external and 6 internaQ. Of these 11
interrupt sources, 9 cause a vectored interrupt while
the 2 testable inputs only generate an interrupt request. All of the 11 maskable interrupts can be used to
release the HALT mode except INTPO. INTPO cannot be
used to release the STOP mode and cannot release the
HALT mode when register SCS = O. In addition, there is
one nonmaskable interrupt from the watchdog timer,
one software interrupt, and a RESET interrupt. The
watchdog timer overflow interrupt (interrupt vector
table address 0004H) can be initialized to be a nonmaskable interrupt orthe highest default priority maskable interrupt. The software interrupt, generated by the
BRK instruction, is not maskable. See table 4 and figure
12.
Table 4. Interrupt Sources and Vector Addresses
Type of
Request
Default
Priority
Restart
Nonmaskable
Maskable
0
Signal Name
Vector
Interrupt
Address Configuration
OOOOH
RESET
RESET input pin
External
Watchdog timer overflow (when reset mode
selected)
Internal
INTWDT
Watchdog timer overflow
(when nonmaskable interrupt selected)
Internal
0OO4H
A
INTWDT
Watchdog timer overflow
(when interval timer selected)
Internal
0OO4H
B
INTPO
External interrupt edge detection
External
0OO6H
C
2
INTP1
External interrupt edge detection
External
0006H
D
3
INTP2
External interrupt edge detection
External
OOOAH
D
4
INTP3
External interrupt edge detection
External
OOOCH
0
5
INTCSIO
End of clocked ·serlallnterface 0 transfer
Internal
OOOEH
B
6
INTTM3
Watch timer reference time interval signal
Internal
0012H
B
7
INTTM1
B-blt timer/event counter 1 coincidence signal
Internal
0016H
B
8
INTTM2
8-bit timer/event counter 2 coincidence signal
Internal
001BH
B
BRK Instruction
Internal
003EH
E
INTWT
Watch timer overflow
Internal
F
INTPT4
Port 4 falling edge detection
External
F
Interrupt Servicing. The J.lP078002 family provides
two levels of programmable hardware priority control
and services all interrupt requests, except the two
testable interrupts (INTWT and INTPT4). Using vectored Interrupts, the programmer can choose the priority of servicing each maskable interrupt by using the
interrupt control registers.
Interrupt Control Registers. TheJ.lP078002family has
three 16-bit interrupt control registers. The interrupt
request flag register (IFO) contains an interrupt request
flag for each interrupt except INTPT4. The interrupt
mask register (MKO) is used to enable or disable any
interrupt except INTPT4. The priority flag register (PRO)
can be used to specify a high or a low priority level for
each interrupt except the two testable interrupts.
Four other S-bit registers are associated with Interrupt
processing. The key return mode register (KRM) contains the KRIF interrupt request flag associated with
20
Location
INTWDT
Software
Test input
Interupt Source
falling-edge detection on port 4 and the KRMK mask
flag used to enable or disable clearing of the standby
mode if a falling edge is detected on port 4. The
external interrupt mode register (INTMO) is used to
select a rising, falling, or both edges as the valid edge
for each of the external interrupts INTPO to INTP2
(INTP3 is always falling edge). The sampling clock
select register (SCS) is used to select a sampling clock
for the noise eliminator circuit on external interrupt
INTPO.
The IE and the ISP bit of the program status word are
also used to control interrupts. If the IE bit is 0, all
maskable interrupts are disabled. The IE bit can be set
or cleared using the EI and 01 instructions, respectively, or by directly writing to the PSW The IE bit is
cleared each time an interrupt is accepted. The ISP bit
is used by hardware to hold the priority level flag of the
interrupt being serviced.
NEe
pPD78002 Family
Figure 12. Interrupt Configurations
Type A:. Intemal nonmaskable Interrupt
Interrupt _ _......_ _ _.....
Request
Type B: Intemal makable Interrupt
•
Vec\or Table
Address Generator
Standby
' - - - - - - - - - - - Release
Signal
Type C: External makable Interrupt (lNTPO)
Vector Table
Address Generator
'---------~~~:~
Signal
83'fl..996611.(1)
21
pPD78002 Family
Figure 12. Interrupt Configurations (cant)
Type D: External maakablelnterrupt (except INTPO)
Interrupt _ _ _ _~
Request
Type E: Software Interrupt
Interrupt _ _ _ _ _ _~
Request
Type F: Test Input
Abbrevla1lons:
IF: Interrupt request flag
IE: Interrupt enable flag
ISP: In-aervlCe p~orl\y flag
MK: Interrupt mask neg
PR: P~orl\y specify neg
22
NEe
NEe
Interrupt Priority. If the watchdog timer overflow interrupt (INlWD1) has been initialized to be a nonmaskable interrupt, it has priority over all other interrupts.
Two hardware-controlled priority levels are available
for all maskable interrupts that generate a vectored
interrupt (i.e., all except the two testable interrupts).
Either a high or a low priority level can be assigned by
software to each of the maskable interrupts. Interrupt
requests of the same' priority or a priority higher than
the processor's current priority level are held pending
until interrupts in the current service routine are enabled by software or until one instruction has been
executed after returning from the current service routine. Interrupt requests of a lower priority are always
held pending until one instruction has been executed
after returning from the current service routine.
The default priorities listed in table 4 are fixed by
hardware and are effective only when it is necessary to
choose between two interrupt requests of the same
software-assigned priority. For example, the default
priorities would be used after the completion of a
high-priority routine, if two interrupts of the same
software priority were pending.
The software interrupt, initiated by the BRK instruction, is executed regardless of the processor's priority
level and the state of the IE bit. It does not alter the
processor's priority level.
Vectored Interrupt Servicing. When a vectored interrupt is acknowledged, the program status word and
the program counter are saved on the stack, the processor's priority is set to that specified for the interrupt,
the IE bit in the PSW is set to zero, and the routine
whose address is in the interrupt vector table is entered. Atthe completion of the service routine, the RETI
instruction (RETB instruction for the software interrupt) reverses the process and the pPD78002 family
microcontroller resumes the interrupted routine.
Standby Modes
HALT, STOP, and data retention modes are provided to
reduce power consumption when CPU action is not
required.
The HALT mode is entered by executing a HALT instruction while the CPU is operating from the main
system or subsystem clock. In HALT mode, the CPU
clock is stopped while the main system and the subsystem clock continue to run. The HALT mode is released by any unmasked interrupt request (except
INTPO if register SCS= 0), a nonmaskable interrupt
request, an unmasked test input, or an external reset
pulse.
pPD78002 Fami I y
Power consumption may be further reduced by using
the STOP mode. The STOP mode is entered by executing a STOP instruction while operating from the main
system clock. In STOP mode, the main system clock
input pin X1 is internally grounded stopping both the
CPU and the peripheral hardware clock. The STOP
mode is released by any unmasked interrupt request
except INTPO, a nonmaskable interrupt request, an
unmasked test input, or an external reset pulse. Any
peripheral using the main oscillator as a clock source
will also be disabled in the STOP mode and interrupts
from such a peripheral cannot be used to exit the STOP
mode. Table 5 summarizes both the HALT and STOP
standby modes.
Tab/e5_
.~
Standby Mode Operation Status
Item
HALT Mode
STOP Mode
Setting
instruction
HALT instruction
STOP instruction
System
clock when
setting
Main system or
subsystem clock
Main system clock
Clock
oscillator
Main system and
subsystem clocks can
oscillate; CPU clock is
stopped.
Subsystem clock can
oscillate; CPU clock
and main system
clock are stopped.
CPU
Operation stopped
Operation stopped
Ports
Maintain previous
state
Maintain previous
state
B·bit timerl
event
counters
Operational from main
system clock
Operational only with
Til and TI2 as count
clock
Watch timer
Operational from main
system clock or with
fXT as count clock
Operational only with
fXT as count clock
Watchdog
limer
Operational from main
system clock
Operation stopped
Serial
interface 0
Operational from main
system clock
Operational only with
external clock
External
interrupts
Operational except for
INTPO when its
sampling clock is
based on the CPU
clock
INTPO not operational;
INTPl to INTP3
operational
When exiting the STOP mode, a wait time occurs before
the CPU begins execution to allow the main system
clock oscillator circuit to stabilize. The oscillator stabilization time is selected by programming the OSTS
register with one of five values before entering the
STOP mode. The values range from 0.98 msec to 31.3
msec at fx= 8.38 MHz.
23
pPD78002 Family
Once in the STOP mode, power consumption can be
further minimized by lowering the power supply voltage Voo to as little as 2 V. This places the device in the
data retention mode. The contents of Internal RAM and
the registers are retained. This mode is released by first
raising Voo to the proper operating range and then
releasing the STOP mode.
External Reset
The IlPD78002 family is reset by taking the RESET pin
low or by an overflow of the watchdog timer (if enabled). The RESET input pin is a schmitt-trigger input
with hysteresis characteristics to protect against spurious system resets caused by noise. On power-up, the
RESET pin must remain low for a minimum of 10lls after
the power supply reaches its operating voltage.
There is no functional difference between an external
reset and an internal reset caused by the overflow of
the watchdog timer. In both cases, the main system
clock oscillation is stopped and the subsystem clock
oscillation continues. During reset, the program
counter is loaded with the address contained in the
reset vector (addresses OOOOH, 0001 H). Once the reset
is cleared and the oscillation stabilization time of 218/fx
has elapsed, program execution starts at that address.
24
NEe
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pPD78002 Family
CapaCitance
ELECTRICAL SPECIFICATIONS
TA = +25"C; Voo = VSS = 0 V
The following specifications are for the J.lPD78001 Bf
oo2B devices only. Refer to the J.lPD78014 data sheet for
J.lPD78P014 device specifications.
Parameter
Symbol Max Unit Conditions
Input
CIN
capacitance
Absolute Maximum Ratings
Output
TA = +25"C
COUT
capacitance
Supply voltage, Voo
-0.3 to + 7.0 V
Input voltage, VI1 (except P60 to P6al
Input/output CIO
capacitance
-0.3 to Voo+ 0.3 V
-0.3 to +16 V
Input voltage, VI2 (P60 to P63; open
drain)
Output voltage, Vo
15
pF
20
pF
Except P60 to P63 f = 1 MHz;
unmeasured
P60 to P63
pins returned
Except P60 to P63 to ground
15
pF
20
pF
PSo to P63
15
pF
Exce pt P60 to P63
20
pF
P60 to P63
-0.3 to Voo+ 0.3 V
Output current, high; IOH
Each output pin
Total: ports 1 to 3
Total: ports 0 and ports 4 to 6
Output current, low, IOl t
Each output pin
Total: P40 to P47 and
P50 to P55
Total: POI to P03, P56, P57' and P60
to P67
Total: POI to P03 and P64 to P67
Total: ports 1 to 3
-10 mA
-15 mA
-15 mA
•
30 mA peak, 15 mA rms
100 mA peak, 70 mA rms
100 mA peak, 70 mA rms
50 mA peak, 20 mA rms
50 mA peak, 20 mA rms
Operating temperature, TOPT
-40 to +85"C
Storage temperature, TSTG
-65 to +150"C
t rms value = peak value x (duty cycle) 1/2
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent damage. The device should be operated within the limits
specified under DC and AC characteristics.
Main System Clock Oscillator
TA = -40 to +85"C; Voo = 2.7 to 6.0 V; refer to figure ;3.
Type
Parameter
Symbol
Min
Ceramic resonator Oscillation frequency (Note 1)
fX
(Figure 13A)
Oscillation stabilization time (Note 2)
1.0
Ix
1.0
Crystal resonator
(Figure 13A)
External clock
(Figure 13B)
Oscillation frequency (Note 1)
Typ
8.38
Max
Unit Conditions
10.0
MHz Voo = oscillator voltage range
4.0
ms
10.0
MHz
After VOO reaches oscillator operating voltage
Oscillation stabilization time (Note 2) _ _ _ _ _ _ _ _ _10
_ _m_s__
V.:::o:::;o_=_4_.5_t_o_6_.0_V_ _ _ _ _ _ _ _ __
30
ms
XI input frequency (Note 1)
fX
1.0
10.0
MHz
XI input high/low-level width
txH, txl
50
500
ns
Notes:
(1) Oscillator and Xl inputfrequencies are included only to show the
oscillator characteristics. Refer to the AC Characteristics table
for actual instruction execution times.
(2) Time required for the oscillator to stabilize after reset or STOP
mode is released. The values shown are for the recommended
resonators. Values for resonators not shown in this data sheet
should be obtained from the manufacturer's specification sheets.
25
NEe
pPD78002 Family
Subsystem Clock Oscillator
TA = -40 to +85°C; Voo = 2.7 to 6.0 V; refer to figure 14.
Type
Parameter
Symbol
Crystal resonator
(Figure 14A)
Osciiiation frequency (Note 1)
txT
External clock
(Figure 14B)
Min
Typ
Max
Unit
32
32.768
35
kHz
Oscillation stabilization time (Note 2)
2
s
10
s
1.2
XT1 input frequency (Note 1)
fXT
32
100
kHz
XTl input high/low-level width
txTH, tXTL
5
15
J1s
Conditions
VDD = 4.5 to 6.0 V
Notes:
(1) The oscillator and XT1 input frequencies are included only to
show the oscillator characteristics. Refer to the AC Characteristics table for actual instruction execution times.
(2) Time required for the oscillator to stabilize after reset or STOP
mode is released. The values shown are for the recommended
resonators. Values for resonators not shown in this data sheet
should be obtained from the manufacturers specification sheets.
Figure 13. Main System Clock Configurations
Figure 14. Subsystem Clock Configurations
A. Crystal Resonator
A. Ceramlc:lCrystal Resonator
1
"~T
XT1
ca.L
C4 T
XT2
R2
R1
B. External Clock
B_ External Clock
---I>
q~
I
83YL-9357A
Note: When the Inpulls an external clock, the STOP
mode can not be sat because the X1 pin Is connected
to systsm ground (VSS)'
83YL-9356A.
26
NEe
IIPD78002 Family
Recommended Main System Clock Ceramic Resonators
TA
= -40 to +85'C; refer to figure 13A
Part Number
(Notes 1 and 2)
Recommended Circuit Constant
Oscillator Voltage Range
Frequency
(MHz)
Cl (pF)
C2 (pF)
Rl (kll)
Min (V)
Max (V)
CSB1000J
100
100
6.8
2.7
6.0
1.00
CSBxxxxJ
100
100
4.7
2.7
6.0
1.01 to 1.25
CSAx.xxxMK
100
100
CSAx.xxMG
100
100
CSTx.xxMG
(Note 3)
(Note 3)
CSAx.xxMG
30
30
(Note 3)
(Note 3)
30
30
(Note 3)
(Note 3)
a
a
a
a
a
a
a
30
30
0
(Note 3)
(Note 3)
a
CSTx.xxMGW
CSAx.xxMG
CSTx.xxMGW
CSAx.xxMT
CSTx.xxMTW
2.7
6.0
1.26 to 1.79
2.7
6.0
1.80 to 2.44
2.7
6.0
1.80 to 2.44
2.7
6.0
2.45 to 4.18
2.7
6.0
2.45 to 4.18
2.7
6.0
4.19 to 6.00
2.7
6.0
4.19 to 6.00
2.7
6.0
6.01 to 10.0
2.7
6.0
6.01 to 10.0
Notes:
(1) Manufactured by Murata Mfg. Co., Ltd.
(3) Cl and C2 are contained in the ceramic resonators.
(2) x.xx indicates frequency
Recommended Subsystem Clock Crystal Resonators
TA = -40 to + 60'C; refer to figure 14A
Part Number
t
DT-38 (HA252 EOO, load capacitance 6.3 pF)
t
Recommended Circuit Constant
Oscillator Voltage Range
Frequency
(kHz)
C3 (pF)
C4 (pF)
R2 (kll)
Min (V)
Max (V)
32.768
12
12
100
2.7
6.0
Manufactured by Daishlnku
27
--
NEe
pPD78002 Family
DC Characteristics
= -40 to +85·0; Voo =
TA
+2.7 to 6.0 V; refer to figures 15-20
Parameter
Symbol
Max
Unit
High-level input voltage
VIHI
0.7Voo
Voo
V
Other than below
VIH2
0.8 VOO
VOO
V
POQ to PO~P22' P24 to P27,
P33, P34, AESET
Low-level input voltage
High-level output voltage
Low-level output voltage
High-level input leakage
current
Min
Typ
VIH3
0.7 Voo
15
V
Pea to Pe3; open-drain
VIH4
VoO-0.5
Voo
V
Xl,X2
VIH5
Voo-0.5
Voo
V
VOO
Vll1
0
0.3VOO
V
Other than below
VIL2
0
0.2Voo
V
POQ to P04, P20, P22, P24 to P27,
P33, P34, AESET
VIL3
0
0.3Voo
V
P6Q to P63; V DO
0
0.2Voo
V
P6Q to P63
VIl4
0
0.4
V
Xl,X2
VIl5
0
0.4
V
XT1, XT2; Voo
0
0.3
V
XT1, XT2
Voo-l.0
V
Voo
Voo-0.5
V
IOH
2.0
V
P50 to P57, P6Q to Pe3;
VOO = 4.5 to 6.0 V, IOl
0.4
V
Other than above; V DO
Iol = 1.6 mA
VOL2
0.2VOO
V
SBO, SB1, SOKO; VDO = 4.5 to 6.0 V,
open-drain, pullup resistance = 1 kO
VOl3
0.5
V
IUHl
3
/lA
VOHI
0.4
VOl1
IUH2
20
/lA
IUH3
80
/lA
IUlt
-3
/lA
IUL2
-20
/lA
ILIl3
-3
/lA
Output leakage current high
IlOHt
3
/lA
Output leakage current low
IlOl
Low-level input leakage
current
Mask option pullup resistor
Software pullup resistor
Conditions
-3
/lA
At
20
40
90
kO
~
15
40
90
kO
500
kO
= 4.5 to 6.0 V; XT1, XT2
= 4.5 to 6.0 V
= 4.5 to 6.0 V
= 4.5 to 6.0V, IOH = -1.0 mA
= -100/lA
28
15 mA
= 400/lA
= Voo; except XI, X2, XTt, XT2
VIN = VOO; XI, X2, XT1, XT2
VIN = 15 V; P60 to P63
VIN = 0 V; except XI, X2, XT1, XT2
VIN = OV; XI, X2, XT1, XT2
VIN = 0 V; P60 to P63 (Note 1)
Your = Voo
Your = OV
VIN = 0 V; P60 to P63
VOO = 4.5 to 6.0 V; VIN = 0 V, POt to P03,
Iol
VIN
ports 1 to 5, P64 to
20
=
= 4.5 to 6.0 V,
P~
Voo = 2.7 to 4.5 V; VIN = 0 V, POt to P03,
ports 1 to 5, P64 to P67
NEe
pPD78002 Family
DC Characteristics (cont)
Parameter
Symbol
Power supply current
1003
Min
Typ
Max
Unit
Conditions
7.5
22.5
mA
8.38 MHz crystal oscillation operating mode;
VOO = 5.0 V :tl0% (Note 2)
0.8
2.4
mA
8.38 MHz crystal oscillation operating mode;
Voo = 3.0 V :tl0% (Note 3)
1.4
4.2
mA
8.38 MHz crystal oscillation HALT mode;
Voo = 5.0V :t10%
550
1650
f.1A
8.38 MHz crystal oscillation HALT mode;
VOO = 3.0V :tlO%
60
120
f.1A
32.768 kHz crystal oscillation operating mode;
VOO = 5.0V :t10%, XI STOP mode, CPU
operating from subsystem clock
35
70
f.1A
32.768 kHz crystal oscillation operating mode;
VOO = 3.0V :tl0%, XI STOP mode, CPU
operating from subsystem clock
25
50
32.768 kHz crystal oscillation HALT mode;
Voo = 5.0 V :tlO%, XI STOP mode
5
10
32.768 kHz crystal oscillation HALT mode;
VOO = 3.0V :tlO%, XI STOP mode
20
XTI = 0 V STOP mode when feedback resistor
is connected; VOO = 5.0V :tl0%
0.5
10
XTI = 0 V STOP mode when feedback resistor
is connected; VOO = 3.0V :t10%
0.1
20
XTI = 0 V STOP mode when feedback resistor
is disconnected; VOO = 5.0 V :tlO%
0.05
10
XTI = 0 V STOP mode when feedback resistor
is disconnected; Voo = 3.0 V :tl0%
1005
loos
Notes:
(1) P60 to P63 become -200 pA (max.) for only 1 clock cycle during
input instruction execution (no wait) and -3 f.1A (max.) during
instruction other than input.
(2) When operated in the high-speed mode with the processor clock
control register set to OOH.
(3) When operated in low-speed mode with the processor clock
control register set to 04H.
29
•
NEe
pPD78002 Family
Figure lB. 100 l'S VOO (ix
Figure 15. 100 l'S Voo (ix = 8.38 MHz)
PCC=OOH(!ey=.48t.IS)'
10.0
PCC=OIH(! cv=.95!tS)'
&.0
--...
T ~~
,;'
-1001
J
1.0
~ .....-::::
~
PCC:02Hgcv=1.91 ~s)'
PCC=03H cr-s.81~s)·
PCC=04Hgcv=7.~s)·
PCC = 30H cv=1~)"
HALT
10.0
5.0
r
cv=3.82~)·
02H
PCC=
PCC=03H tcy=7.64l's),
PCC=04H tcv=15.27~)·
PCC=30H ICv=12~s)"
HALT (XI oscUlatlon)
fXT=3r88 kHi
PCC
,;'
r-
BOH(IC
(Xl
HALT (Xl STO
.....
1003
,/
./
V
j,/
0.01
0.01
0.005
r - 10D4
~10D4
• CPU Clock from main system clock.
i
o
2
3
I
CPU ~Iock frOj sUb~Lm clr·
4
5
6
Power Supply Voltage V DO (V)
30
PCC=OOH(!cv=.95~)·
PCC=OIH(tCv=1.91~)'
TA=25° C; fx= 4.19 MHz;
!
PCCaBOH(tc
(Xl
HALT (Xl STO
.....
-1003
0.001
-
1001
i 0.1
a, 0.05
0.005
..-
:.....-::: ~ ~
1=
1001
r--
TA=25°C; fx=8.38 MHz; fxr = 32.788 kHz
~
I
........
/"
0.5 :=:'1002
I
= 4.19 MHz)
7
8
0.001
o
2
I
elr·
• CPU Clock from main system clock.
i
CPU ~IOCk froj su,stem
3
4
5
6
Power Supply Voltege VOO (V)
7
8
I
NEe
pPD78002 Family
Figure 17. IOL" VOL (Ports 0, 2-6, PB4 - PBT)
Figure 19. 'OL" VOL {P6o - PBa}
301-----=:--rr+r='---~-+_----_I
VOO=3V
! ~ 1-------t~~L.;;.,L--_t_-_=;;:;_..-=__j
01
<"
.s.
5
-10~~~---+-----~----__4
OL-----~-----~----~I
o
1.0
0.5
vOLM
<"
.s.
9
10~--~~~~----~----__4
~----~------~----~I
VOL (V)
Figure 20.
Figure 18. IOL" VOL (Port 1)
1.0
0.5
IOH .. Voo - VOH (ports 0-6, PB4 - P6TJ
:B
~~r-------~7L~~~------~
1.0
0.5
vOLM
1.0
0.5
______
~
-
L
________L -______
~
10~-~~L--+-----~----__4
~
<"
.s.
9
I
VOO-VOH (V)
31
NEe
pPD78002 Family
AC Characteristics
TA = -40 to +85°C; Voo = 2.7 to 6 V ; refer to figures 21 through 26
Parameter
Symbol
Min
Cycle time
(Min. instruction
execution time)
tCY
0.4
Typ
TI input high/
low-level width
trlH, tTiL
Interrupt input
high/low-level
width
RESET low-level width
Operating on main system clock
/ls
0
4
MHz
0
275
kHz
Conditions
Operating on subsystem clock
Voo
= 4.5 to 6.0 V
Voo
= 4.5 to 6.0 V
100
ns
1.8
/ls
B/f5am (Note 1)
/ls
INTPO
10
/ls
INTPl to INTP3
10
/ls
KRO to KR7 (Note 2)
10
/ls
(1) By using bits 0 and 1 of the sampling clock select (SCS) register
in conjunction with bits 0 to 2 of the processor clock control
(PCC) register, fsam can be set to fx/2N+ 1 (where N = 0 to 4),
fx/64, or fx/12B.
32
Voo = 4.5 to 6.0 V; operating on main system
clock
/lS
122
Notes:
(2) Port 4 falling-edge detection input.
/ls
64
114
fori
Unit
64
125
0.96
TI input
frequency
Max
NEe
IIPD78002 Family
Figure 21. Main System Clock Operation;
tcywVoo
Figure 24.
TI Timing
=1 I hI I I I 1
p
,
r
3.0
p
'p
,
~J~d
83C..........
Figure 25. Interrupt Input Timing
OperaUng
Range
I
=
TA -40" to +850
c
1\
\,
1\
0.5
OA
or: r :r
2
1
3
:
1
4
I
1
5
:~
11'5
6
Supply voltage VDO M
Figure 22. AC Timing Measurements Points
(except XI and XTl)
Figure 26. RESET Input Timing
~I
0.8 VOO-Measurement- 0.8 VOO
O.2VOO......
Points
""'0.2VOO
Figure 23. Clock AC Timing Points XI and XTI
X11nput
XT11nput
0.4 V
OAV
33
NEe
"PD78002 Family
Read/Write Operation
= -40 to +85"C. VDD = 2.7 to 6.0 V; refer to figures 27 through so
TA
Parameter
Symbol
Min
ASTB high-level width
tASTH
0.5 tCY
ns
Address setup time to ASTB 4
tAOS
0.5tev- SO
ns
Address hold time from ASTB 4
tADH
10
Data input time from address
1.4001
Unit
Conditions
ns
Load resistor," 5 kO
(2+2n)tev - 50
ns
Instruction fetch
(S+2n)lcy - 100
ns
Data access
tRDD1
(1+2n)tCY - 25
ns
Instruction fetch
tRDD2
(2.5+ 2n)lcy - 100
ns
Data access
tADD2
Data Input time from RD 4
Max
5
Read data hold time
tROH
0
RD low-level width
tROLl
(1.5+ 2n)tCY - 20
ns
tRDL2
(2.5+ 2n)tCy - 20
ns
Data access
0.5tCY
ns
Instruction fetch
tRDWT2
1.5 tCY
ns
Data access
twRWT
0.5tCY
ns
(2+2n)tcy
ns
WAIT ~ input time from RD ~
tRDWTl
WAIT ~ input time from WR 4
WAIT low-level width
Write data setup time to WR
t
Write data hold time from WR
t
ns
twTL
(0.5+2n)tCy + 10
twos
100
ns
twDH
5
ns
WR low-level width
twRLl
(2.5+ 2n)tCY - 20
ns
RD ~ delay time from ASTB ~
tASTRO
0.5 tCY-SO
ns
WR ~ delay time from ASTB ~
ns
tASTWR
1.5 tCY-SO
t delay time from RD ! (external fetch)
tRDAST
tCy-l0
tCY + 40
ns
Address hold time from RD ! (external fetch)
tRDADH
tCY
tCY + 50
ns
tRDWD
10
twDWR
0.5 tCy-12O
ASTB
Write data output time from RD !
WR
~
delay time from write data
Address hold time from WR
t
RD
t delay time from WAIT t
WR
t delay time from WAIT t
Notes:
(1) tCY
= tCy/4
(2) n indicates number of waits.
(S) CL
34
=
100 pF
twRADH
IwTRD
twTWR
Instruction fetch
ns
0.5 tCY
ns
0.5 tCy-170
0.5 tCY
ns
tCY
tCY+ 60
ns
Icy
tCY+ 100
ns
0.5 tCY
2.5tCY + 80
ns
0.5tCY
2.5 tCY + 80
ns
VDD
= 4.5 to 6.0 V
VOD
= 4.5 to 6.0 V
NEe
IIPD78002 Family
Figure 27. Read Operation; External Fetch (No Wait)
Upper Mitt Add",..
~------------~tADD1------------~~
HI.z
ASTB
r-
Operation Code
H.tRDADH
I
1-'
~j-E-----tRDL1-==il,,~
83FM-93718
Figure 28. Read Operation; External Fetch (Wait Insertion)
As-A15
Upper 8·Btt Add",..
~--------------'tADD1------------~~
HI·Z
Operation Code
ASTB
83FM-9372B
35
NEe
I'PD78002 Family
Figure 29_ Read/Write Operation; Externa' Data Access (No Wait)
)J
Aa-A15
K=
Upper S-Bft Address
tAD02
)J
lowerS-Bit"'
Address
HI·Z
~---------<
r'' '-'
tADS
ASTB
ReadOata
WrtteData
C
tAOH
J4
tASTRO
tROH- ~
I
\
tR01.2
.f~
I I
twos
tWOWR
I.
36
HI·Z
~--
\
tASlWR
lWRL1-
~,~~ J
-tWRAOH
NEe
"PD78002 Family
Figure 30. Read/WTlte Operation; External Data Access (Walt Insertion)
)
Ae-A1S
K=
Upper 8-8ft Addreee
'ADD2
)
IAwarS.aJt
Addreee
~---~----<
'ADH
'ADS
:H
r-~
HI·Z
~--
WrlteOata
Read Data
'"'"T
I
'*'ASTRO·
\
itROL2
K=
"'
~,-,
...
•
I I
twos
~
..-tWOH"
-tWOWR
I.
'RDW12
I
'ASlWR
I
\
-tWRL1-
~J
'WTL-. foE-'WTRO-.i 'WRWT- ~ -'WTL- ~ r-tWTWR
I
\
\
&1FM-93748
37
NEe.
pPD78002 Family
Serial Interface, a-Wire, I/O Modej Intemal SC.K put put
TA = -40 to +B5D C; Voo = 2.7 to 6.0 V; refer to figure 31
Parameter
Symbol
Min
Unit
.ConditIons
SCK cycle time
tKCYl
800
ns.
Voo
3200
.ns
tKCY1/2-50
ns
tKCY1/2 - 150
ns
na
SCK high· and low-level width
tKH1, tKll
SI setup time to SCK t
tSIKl
100
SI hold time from SCK t
tKSll
400
SO output delay time from SCK ~
tKSOl
Typ
Max
= 4.5 to 6.0 V
VOO. = 4.5 to 6.0 V
na
300
ns
Voe = 4.5 to 6.0 V; C = 100 pF (Note 1)
1000
ns
C = 100 pF (Note 1)
Note 1: C is the load capacitance of the SO output line.
Serial Interface, a-Wire I/O Modej External SCK Input
TA = -40 to +B5D C; Voe = 2.7 to 6.0 V; refer to figure 31
Parameter
SCK cycle time
SCK high· and low-level width
SI setup time to SCK
t
Symbol
Min
Unit
Conditions
tKCY2
BOO
ns
Vee = 4.5 to 6.0 V
3200
ns
tKH2' tKl2
Typ
Max
400
ns
1600
ns
ns
tSII<2
100
SI hold time from SCK t
tKSI2
400
SO output delay time from SCK ~
tKS02
Vee = 4.5 to 6.0 V
ns
= 4.5 to 6.0 V; C = 100 pF (Note 1)
300
ns
Vee
1000
ns
C = 100 pF (Note 1)
Note 1: C is the load capacitance of the SO output line.
Serial Interface, SBI Modej Internal SCK Output
TA
= -40 to +B5 C; voe = 2.7 to 6.0 V; refer to figure 32
D
Parameter
Symbol
Min
Unit
Conditions
SCK cycle time
tKCY3
800
ns
Voo
= 4.5 to 6.0 V
3200
ns
tKCya/2-50
ns
Vee
= 4.5 to 6.0 V
tKCya/2 -150
ns
100
ns
Veo
= 4.5 to 6.0 V
300
ns
SCK high· and low-level width
SBO, SBI setup time to SCK
t
tKH3, tKl3
tSIK3
Typ
Max
SBO, SBl hold time from SCK t
tKSI3
tKCya/2
SBO,SBl output delay time from SCK ~
tKS03
0
250
ns
0
1000
ns
ns
t
tKSB
tKCY3
ns
SCK ~ from SBO, SBl ~
tSBK
tKCY3
ns
SBO, SBl high·level width
IaBH
tKCY3
ns
SBO, SBl low-level width
IaBl
tKCY3
ns
SBO, SBl ~ from SCK
Note 1: Rand C are the load resistance and load capacitance of the
SBO and SBl output linea.
38
=
= 1 ko,
=
R = 1 ko, C = 100 pF (Note 1)
Vee
4.5 to 6.0 V; R
C
100 pF (Note 1)
NEe
pPD78002 Family
Serial Interface, S81 Mode; External SCK Input
TA = -40 to +85"C; Voo = 2.7 to 6.0 V; refer to figure 32
Max
Parameter
Symbol
Min
Unit
Conditions
SCK cycle time
tKCY4
800
ns
Voo = 4.5 to 6.0 V
3200
ns
SCK high- and low-level width
tKH4, tKL4
400
ns
1600
ns
100
ns
300
ns
SBO, SB1 setup time to SCK !
tSIK4
SBO, SB1 hold time from SCK!
SBO, SB1 output delay time from SCK
S80, SB1
~
~
from SCK !
Typ
Voo = 4.5 to 6.0 V
Voo = 4.5 to 6.0 V
ns
tKSI4
tKCy.v2
tKS04
0
300
ns
Voo = 4.5 to 6.0 V; R = 1
(Note 1)
0
1000
ns
R= 1
tKSB
tKCY4
ns
ko,
ko,
C = 100 pF.
C = 100 pF (Note 1)
--~--~~----------BI
SCK ~ from SBO, SB1 I
tsBK
tKCY4
ns
S80,SB1 high-level width
tSBH
tKCY4
ns
S80, SB1 low-level width
tSBL
tKCY4
ns
Note 1: Rand C are the load resistance and load capacitance of the
SBO and SB1 output lines.
Serial Interface, 2-Wire, I/O Mode; Internal SCK Output
TA = -40 to +85'C; Voo = 2.7 to 6.0 V; refer to figure 33
Parameter
Symbol
Min
Unit
Conditions
SCK cycle time
tKCY5
1600
ns
Voo = 4.5 to 6.0 V
3600
ns
SCK high-level width
tKH5
tKCY5/2 - 5O
ns
SCK low-level width
tKL5
tKCY5/2- 50
ns
tSIK5
300
ns
SBO, SB1 hold time from SCK t
tKSI5
600
SBO, SB1 output delay time from SCK I
tKS05
0
250
ns
VOO = 4.5 to 6.0 V
R = 1 ko, C = 1DO pF (Note 1)
0
1000
ns
R = 1 ko, C
S80, SB1 setup time to SCK
t
Typ
Max
ns
=
100 pF (Note 1)
Note 1: Rand C are load resistance and load capacitance of the
SCKO, SBO, and SB1 output lines.
39
NEe
pPD78002 Family
Serial Interface, 2-Wire, 1/0 Mode; External SCK Input
TA
= -40 to +S5°C; Voo = 2.7 to 6.0 V; refer to figure 33
Typ
Symbol
Min
Unit
Conditions
tKCY6
1600
ns
Voo = 4.5 to 6.0 V
3800
ns
SCK high-level width
tKH6
650
ns
SCK low-level width
tKL6
SOD
ns
SBO, SBl setup time (to SCK t)
tSIK6
100
ns
SBO, SBl hold time (from SCK t)
tKSI6
tKCye/2
SBO, SBl output delay time from SCK I
tKS06
0
300
ns
Voo = 4.5 to 6.0 V
R = 1ko, C"= 100 pF (Note 1)
o
1000
ns
R = lko, C = 100 pF (Note 1)
Parameter
SCK cycle time
Note 1: Rand C are load resistance and load capacitance of the
SCKO, SBO, and SBl output lines.
Figure 31. Serial Interface Timing;
3-Wire Serial If0 Mode
1..(!------'tKCY1,2-----.J
tKL1,2-
181Kl,2 -+-~~~f- tKS11,2
81-+----<1-\ Input Dsta
so
40
I. ~_tKS01'2
)(
_ ) (
output Data
"
Max
ns
NEe
JlPD78002 Family
Figure 32. Serial Interface Timing; S81 Mode
SBI Bus Release Signal Transfer Timing
tKSB
S80,1
SBI Bus Command Signal Transfer Timing
SBO,1
83Cl-9378B
Figure 33. Serial Interface Timing;
2-Wire Serial If0 Mode
SBO,1
41
NEe
pPD78002 Family
Data Memory STOP Mode; Low-Voltage Data Retention
TA
= -40 to +8SoC; refer to figure 34
Parameter
Symbol
Min
Data retention supply voltage
VOOOR
2.0
Data retention power supply current
IOOOR
Release signal set time
tSREL
Oscillation stabilization walt time
tWAIT
Typ
0.1
0
Unit
6.0
V
10
JlA
Conditions
VOOOR = 2.0 V; subsystem clock stop and
feedback resistor disconnected
Jls
218/1x
ms
Release by RESET
(Note 1)
ms
Release by interrupt
Note: 2 13/fx. 2 15/1x. 216/1x. 217/1x or 2 18/1x can be chosen by using
bits 0 to 2 of the oscillation stabilization time select (OSTS)
register.
42
Max
NEe
,",PD78002 Family
Figure 34. Data Retention Timing
A. STOP mode la releaaed by RESET Input
Intema! reset
operation
t:
YOO
I
II
STOP mode
YOOOR
I
1
Data retention mode -
i
HALT mode
OperaUon
mode
/
Execution of
STOP InstruCifon
\
_
"--'
tSREL
tWAIT
B. STOP mode la released by Interrupt algnal
t:
_
YOO
i
HALTrnode
rs-----STOPmode
I
--------1--'-1~._ =tion
Oata retention mode
YOOOR
ExecuUonof
STOP InstruCifon
Standby release signal
(Interrupt request)
83RD-6466B
43
IIPD78002 Family
44
NEe
NEe
NEG Electronics Inc.
JlPD78002Y Family
(JIPD78001 BY/002BY/P014y)
8-Bit, K-Series Microcontrollers
General Purpose With 12C Bus
Preliminary
September 1993
Description
Features
The JlPD78001 BY, JlPD78002BY, and JlPD78P014Y* are
members of the K-SeriesCOl of microcontrollers. The
JlPD78002Y family is a variation of the JlPD78002 family
with the addition of an 12C bus mode in serial interface
O. The JlPD78P014Y is used for prototyping since the
JlPD78014Y family is pin and function compatible with,
and the features are a superset of, the JlPD78002Y
family. The JlPD78002Y features include bit manipulation instructions, four banks of main registers, an
advanced interrupt handling facility, and a powerful set
of memory-mapped on-chip peripherals. On-board
data memory includes 256,384, or 1024 bytes of internal high-speed RAM. Program memory options include
8K or 16K bytes of mask ROM, or 32K bytes of internal
UV EPROM or one-time programmable (OTP) ROM.
o One-channel serial communication interface
- 8-bit clock synchronous interface 0
_12C bus mode
- Full-duplex, three-wire mode
- NEC serial bus interface (SBI) mode
- Half-duplex, two-wire mode
The JlPD78002Y family operates over a wide voltage
range: 2.7 to 6.0 volts. Timing is generated by two
built-in oscillators. A main oscillator normally drives
the CPU and most peripherals and at 10 MHz provides
a minimum instruction time of 0.4 Jls. A subsystem
oscillator at 32.768 kHz provides time keeping, and
optionally a slow clock for the CPU. Since CMOS power
dissipation is directly proportional to clock rate, the
JlPD78002Y family provides a software variable CPU
clock. The HALT and STOP modes are two additional
power saving features that turn off parts of the microcontroller for additional power saving. A data retention
mode permits RAM contents to be saved down to 2
volts.
The range of peripherals, including timers and a serial
port, makes these devices ideal for applications in
portable battery-powered equipment, office automation, communications, consumer electronics, home
appliances, and fitness equipment.
* See the /lPD78014Y family data sheetforthe /lPD78P014Y eleotrioal
and funotional speoifioations.
K-Serles Is a registered trademark of NEO Electronios, Ino.
Purchase of NEO 120 oomponents oonveys a lIoense under the Philips
t20 Patents Right to usa the.e components in an 120 system,
provided thatthe system oonforms to the 120 speolflcatlon as defined
by Philips.
o Timers
- Watchdog timer
- Two 8-bit timer/event counters usable as one
16-bit timer/event counter
- Clock (watCh) timer (time of day tick from either
oscillator)
o 531/0 lines
- Two CMOS input-only lines
-47 CMOS I/O lines
- Four n-channel, open-drain I/O lines at 15 V
maximum
o I/O port pullup resistors
-Software controllable on 47 lines
- Mask option on four lines on ROM versions
o Program memory
- JlPD78001 BY: 8K bytes ROM
-JlPD78002BY: 16K bytes ROM
-JlPD78P014Y: 32K bytes EPROM/OTP
o Internal high-speed data memory
- JlPD78001 BY: 256 bytes RAM
-JlPD78002BY: 384 bytes RAM
- JlPD78P014Y: 1024 bytes RAM
o External memory expansion
- 64K byte total memory space
o Powerful instruction set
-16-bit arithmetic and data transfer instructions
-1-bit and 8-bit logic instructions
o Minimum instruction execution times:
- 0.4/0.8/1.6/3.2/6.4 Jls program selectable using
10-MHz main system clock
-122 JlS selectable using 32.768-kHz subsystem
clock
o Memory-mapped on-chip peripherals (special
function registers)
o Programmable priority, vectored-interrupt
controller (two levels) . '
. '
,
,:
NEe
pPD78002Y Family
Features (cont)
Pin Configurations
I:l
Buzzer and clock outputs
I:l
Power saving and battery operation features
- Variable CPU clock rate
-HALT mode
-STOP mode
- 2-V data retention mode
I:l
64-Pin Plastic Shrink DIP
CMOS operation; Voo from 2.7 to 6.0 V
Ordering Information
Part Number
ROM
jJP078001 BYCW-xxx
8K mask ROM
jJP078002BYCW·xxx
16K mask ROM
jJPD78001 BYGC-xxx-AB8
8K mask ROM
jJPD78002BYGC-xxx-AB8
16K mask ROM
jJPD78P014YGC-AB8
(Note 3)
32KOTP ROM
jJPD78P014YDW (Note 3)
32KlN EPROM
.P20
P21
P22
P31fT01
P32fT02
P3afTJl
P34fT12
P3sfPCL
103
102
P17
P1e
P15
P14
P13
P12
P1l
P10
101
POlf/XTl
XT2
ICO
P3&'BUZ
Xl
P37
X2
P23
P~
P2sfSIOISBotsDAo
P2efSOOISB11SDAl
P¥SOKOISOL
P30
Package
(Package Dwg.)
64'pin plastic
shrink DIP
(P64C-70·750 A, C)
64-pin plastic QFP
(P64GC-80-AB8-2)
Vss
P40fADQ
P41fADl
P42I'AD2
P4a1AD3
P44fAD4
P4sfAD5
P4efADs
P4]/AO]
PSofAa
P51fAa
P5a/A l0
P5a1All
P54fA12
PSsfA13
Vss --...;'--_ _ _•
64-pin ceramic
shrink DIP w/window
(P64DW-70-750A)
Notes:
(1) xxx indicates ROM code suffix
(2) All devices listed are standard quality grade
(3) See the /JPD78014Y family data sheet for the jJPD78P014Y
electrical and functional specifications
VDD
PO:tINTP3
POlfINTP2
POlf1NTP1
POofiNTPO
RESET
Pe7/ASTB
Pe&'WAIT
PSs/WR
Pe4fRD
P63
P62
PSl
Peo
P5.,tA15
P5WA14
NoI88:
(1) Connsct ICO, 101, and 103 OnternaRy connected) pins to Vss.
(2) Connect 102 to VDD'
2
NEe
JlPD78002Y Family
Pin Configurations (cant)
64-Pin Plastic QFP
M~~~~~M~~~M~~~~~
P3010
P31fT01
2
P3~02
48
P11
P10
IC1
3
P3afT11
P04/XTl
P34fTI2
XT2
P3sfPCL
ICO
Xl
P:JeIBUZ
41
P37
Vss
P4o'AOo
P41/A01
P42fA02
P43fA03
P44fA04
P4s'AOS
P4&'A 08
..
X2
VOO
P03fINTP3
P02flNTP2
P01flNTP1
POoflNTPO
RESET
I'67IASlB
18
33
P8&'WAIT
v~~~~~~~~~v~~~~~
NoIe8:
connect
(1)
ICO,IC1, and IC3 QntemaHy connected) pIns to VSS (2) Connect 102 to VOO83YL-94918
3
NEe
pPD78002Y Family
Pin Functions; Normal Operating Mode
Symbol
First Function
Symbol
Alternate Function
Port 0; 5-bit, bit selectable I/O port
(Bits 0 and 4 are input only)
INTPO
INTPl
INTP2
INTP3
External maskable interrupt
XTl
Crystal oscillator or external clock Input for
subsystem clock
SID
Serial data input 3-wire serial I/O mode
2/3-wlre serial I/O mode
Serial data bus 0 for 120 bus mode
Port 1; S-bit, bit-selectable I/O port
Port 2; S-bit, bit-selectable I/O port
P25
SBO
SOAO
SOO
SBl
SOAl
Serial data output 3-wire serial I/O mode
2/3-wire serial I/O mode
Serial data bus 1 for 12C bus mode
SCKO
SCl
Serial clock I/O for serial interface 0
Serial clock I/O for 12C bus mode
TOl
Timer output from timer 1
T02
Timer output from timer 2
TIl
External count clock input to timer 1
TI2
External count clock input to timer 2
PCl
Programmable clock output
BUZ
Programmable buzzer output
ADO-A~
low-order S-bit multiplexed address/data bus
for external memory
Port 3; S-bit, bit-selectable I/O port
P30
P36
P40 - P4r
Port 4; S-bit I/O port
P5a - P5-r
Port 5; S-bit, bit selectable I/O port
P6a - P63
Port 6; S-bit, bit selectable (P6a to P63 nchannel open-drain I/O with mask option pullup
resistors; P64 - P67 I/O). See note.
High-order S-bit address bus for external
memory
RD
External memory read strobe
P65
WR
External memory write strobe
P66
WAIT
External memory wait signal input
ASTB
Address strobe used to latch address for
external ~emory
External system reset input
Xl
Crystal/ceramic resonator connection or
external clock Input for main system clock
X2
Crystal/ceramic resonator connection or inverse
of external clock for main system clock
XT2
Crystal oscillator or left open when using
external clock for subsystem clock
Voo
Power supply Input
Vss
Power supply ground
ICOto IC3
Note:
4
Internal connection
See table 3 and figure 4 for details
NEe
pPD78002Y Family
Block Diagram
General Reg.
Internal
Program Memory
(ROM)
Note 1
~
~
~
~
SIOISBOISDA0IP25::i
SOOISB1/SDA1/P26
In:: 0
SCKOISCUP2-,
P
INTPO/POoINTP3IP03
ADOIP40AD71P47
AelP5oExtemal
Aj slPS7
-RotP64
t I I I
RESET VDD
Vss
WRIP65
-WAITIP66
ASll!IP67
ICO1C3
Not.:
(1) The Intema! ROM and RAM size dependent on Ihe device.
83YL.......
5
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pPD78002Y Family
"PD7B002Y and "PD7B014Y Family Differences
Internal System Clock Generator
The JIPD78002Y family is pin compatible with the
JIPD78014Y family and shares the same programmable
device, the JIPD78P014Y. The JIPD78002Y family offers a
reduced set of features. Table 1 lists only the differences between the two families. All other features not
listed are identical for both families.
The internal system clocks of the JIPD78002Y fam ily are
derived from either the main system or the subsystem
oscillator. See figure 1. The clocks for the watch timer
and programmable clock output are derived from either
the subsystem clock (fXT) or the main system clock. The
clocks for all other peripheral hardware are derived
from the main system clock.
Table 1. Differences Between pPD7B002Y and
pPD78014Y Families
The CPU clock (114788
7
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JlPD78002V Family
Memory Space
The pPD78002Y family has a 64K-byte address space.
Some of this address space (OOOOH-FFFFH) can be
used as both program and data memory as shown in
figure 2.
Figure 2. Memory Mllp
i
OOOOH
(1) RelatIVe
AddreSsing
COOOH
Intemal
Program
Memory
(ROM)
003FH
0040H
C07FH
OOSOH ~
(2) Immediate
Addressing
07FFH
OSOOH
(3) Table Indirect
Addressing
(1) Olreel
Add resslng
(2) Regtster Indirect
Add resslng
(3) Based
Addressing
(4) Register
Addressing
1
(4) Based Index
Note 1
Extemal
Memory
FA7FH
FASOH
Note 2
Add resslng
'"
Register lddreSSlng
FEFFH
FFOOH
SFR
Add1ss1ng
FFFFH
1
CALLT Table Area
Program Area
CALLF Entry
Area
Program Area
Note1T
Program
Memo ry
ce
1
I
T
Use
Prohibited
saddr Addressing
Intemal
High-Speed
RAM
FEOFH
FEEOH
~
~
OFFFHI
10COH
Interrupt Vector
Address Table Area
I
General I
Registers I
Special
Function
Register
(SFR)
FE20H
--------
General RAM
FEOFH
FEEOH
FEFFH
FFOOH
---------
FF1FH
--------General Registers
--------32 Bytes of
SFRArea
I
Short 01rect
Addre sslng
tes)
J
HolM:
(1) 1FFFH on "P078001Y
3FFFH on "PD78002Y
(2) FOFFH on "PD78001 Y
FD7FH on "P078002Y
8m..g4938
8
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Internal Program Memory
All devices in the pPD78002Y family have internal program memory. The pPD78001 BY contains 8K bytes
while the pPD78002BY contains 16K bytes of internal
ROM. The pPD78P014Y contains 32K bytes of UV
EPROM or one time programmable ROM. To allow the
pPD78P014Y to emulate the mask ROM devices, the
amount of internal program memory available in the
pPD78P014Y can be selected using the memory size
switching register (IMS).
Internal RAM
The pPD78001 BY contai ns 256 bytes (FEOOH to FE F FH)
while the pPD78002BY contains 384 bytes (FD80H to
FEFFH) of high-speed Internal RAM. The high-speed
Internal RAM contains the general register banks and
the stack. The remainder of the high-speed Internal
RAM and any unused register bank locations are available for general storage.
To allow the pPD78P014Y to emulate the mask ROM
devices, the amount of high-speed Internal RAM in the
pPD78P014Y can also be selected using the IMS.
pPD78002Y Family
program counter is loaded with the address stored in
locations OOOOH and 0001H.
Stack Pointer. The stack pointer is a 16-bit register that
holds the address of the last item pushed onto the
stack. It is decremented before new data is pushed
onto the stack and incremented after data is popped
off the stack.
Program Status Word. The program status word
(PSW) is an 8-bit register that contains flags that are
set or reset depending on the results obtained during
the execution of an instruction. This register can be
written to or read from 1 bit or 8 bits at a time. The
assignment of PSW bits follows.
o
7
I
IE
z
CY
ISP
RBSO, RBS1
AC
Z
IE
I RBS1 I
AC
I RBSO I
0
liSP
CY
Carry flag
In-service (interrupt) priority flag
Register bank selection flags
Auxiliary carry flag
Zero flag
Interrupt request enable flag
External Memory
General Registers
The pPD78002Y family can access 0,256, 4K, 16K or all
available bytes of external memory. The pPD78002Y
family has an 8-bit wide external data bus and a 16-bit
wide external address bus. The low-order 8 bits of the
address bus are multiplexed and also provide the 8-bit
data bus and are supplied by port 4. The high-order
address bits of the 16-bit address bus are taken from
port 5 as required. The address latch, read, and write
strobes, and the external WAIT signal are supplied by
port 6.
The general-purpose registers (figure 3) consist of four
banks of registers located at addresses FEEOH to
FEFFH in Internal RAM. Each bank consists of eight
8-bit general registers that can also be used in pairs to
function as four 16-bit registers. Two bits in the PSW
(RBSO and RSB 1) specify which of the register banks is
active at any time and are set under program control.
The memory expansion mode register (MM) controls
the size of external memory. It can be programmed to
use 0, 4, 6, or 8 bits from port 5 for the high-order
address. Any remaining port 5 bits can be used for I/O.
The MM register also can be used to specify one
additional wait state or the use of the external WAIT
signal for low-speed external memory or external peripheral devices.
Registers have both functional names (A, X, B, C, D, E,
H or L for 8-bit registers and AX, BC, DE and HL for
16-bit registers) and absolute names (R1, RO, R3, R2,
R5, R4, R7, or R6 for 8-bit registers and RPO, RP1, RP2,
or RP3 for 16-bit registers). Either the functional or
absolute register names can be used in instructions
that use the operand identifiers rand rp.
Addressing
CPU Control Registers
The program memory addressing (ROM) modes provided are relative, imediate, table indirect and register
addressing. The operand addressing modes provided
are implied, register, direct, short direct (saddr),
special-function (SFR), register indirect, based, based
indexed, and stack addressing.
Program Counter. The program counter is a 16-bit
binary counter register that holds the address of the
next instruction to be executed. During reset, the
The 'SFR addressing' and 'saddr addressing' modes
use direct addressing, and require only 1 byte in the
instruction to address RAM. Normally a 65K byte ad-
When only internal ROM and RAM are used and no
external memory is required, ports 4, 5 and 6 are
available as general purpose I/O ports.
9
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pPD78002V Family
Figure 3. General Registers
FEEOH Register
Bank
3
ForS-Blt
Processing
2
I
FEFFH
0
\
FEFFH
FEF8H -
- - - - -
For 16-Bk
Processing
(RPO) PJ(
(Rl)A
(RO) X
(R3)B
(R2)C
(RP1)BC
FEFAH
(AS) D
(R4)E
(RP2) DE
FEFCH
(R7)H
(R6)L
(RP3) HL
FEFEH
F~F~ _ _
- - --
FEF8H
)=Absolute Name
83YL......
dress space requires 2 bytes to address it. One-byte
addressing results in faster access times, since the
instructions are shorter. SFR addressing addresses the
entire 256-byte SFR address space from FFOOH to
FFFFH. Saddr addressing (see figure 2) addresses the
256 byte address space FE20H to FF1FH. FE20H to
FEFFH are composed of 224 bytes of internal high
speed RAM; FFOOH to FF1FH contain the first 32 bytes
in the special function register area.
One byte addressing is accomplished by using the first
byte of the instruction for the opcode (and one operand if register A or AX is used) and the second byte of
the instruction as an address (offset) into the 256-byte
area. If register A or AX is used, the instructions are 2
bytes long, thereby providing fast access times. If
immediate data is used, the instruction will be 3 or 4
bytes long depending upon whether the immediate
data is a byte or a word. Many 16-bit SFRs are in the
space FFOOH to FF1FH. Using AX as an operand to
these SFRs will provide fast access, since the instructions will be only 2 bytes long.
10
Special Function Registers
The input/output ports, timers, capture and compare
registers, and mode and control registers for both the
peripherals and CPU are collectively known as special
function registers. They are all memory-mapped between FFOOH and FFFFH and can be accessed either
by main memory addressing or by SFR addressing.
FFOOH to FF1FH can also be accessed using saddr
addressing. They are either a or 16 bits as required, and
many of the a-bit registers are bit addressable.
Locations FFDOH through FFDFH are known as the
external access SFR area. Registers in external circuitry interfaced and mapped to these addresses can
only be addressed by main memory addressing. Table
2 lists the special function registers.
NEe
pPD78002Y Family
Table 2. Special Function Registers
Access Units (Bits)
Address
Register (SFR)
Symbol
R/W
FFOOH
PortO
PO
R/W
x
x
FF01H
Port 1
PI
R/W
x
x
OOH
FF02H
Port 2
P2
R/W
x
x
DOH
FF03H
Port 3
P3
R/W
x
x
DOH
FF04H
Port 4
P4
R/W
x
x
Undefined
FF05H
Port 5
P5
R/W
x
x
Undefined
FF06H
Port 6
P6
R/W
x
x
Undefined
FF16H
Compare register 10
CR10
R/W
x
Undefined
R/W
8
16
State After Reset
DOH
FF17H
Compare register 20
CR20
x
Undefined
FF1BH
B·bit timer register 1
TMI
R
x
x
DOH
x
x
FF19H
B·bit timer register 2
TM2
R
FF1BH·FFI9H
16·bit timer register
TMS
R
FFIAH
Serial I/O shift register 0
SIOO
R/W
FF20H
Port mode register 0
PMO
R/W
x
x
lFH
FF21H
Port mode register 1
PMl
R/W
x
x
FFH
DOH
x
x
OOOOH
Undefined
FF22H
Port mode register 2
PM2
R/W
x
x
FFH
FF23H
Port mode register 3
PM3
R/W
x
x
FFH
FF25H
Port mode register 5
PM5
RfW
x
x
FFH
FF26H
Port mode register 6
PM6
R/W
x
x
FFH
FF40H
Timer clock select register 0
TClO
R/W
x
x
OOH
FF41H
Timer clock select register 1
TCll
R/W
x
DOH
FF42H
Timer clock select register 2
TCl2
R/W
x
DOH
FF43H
Timer clock select register 3
TCl3
R/W
x
88H
FF47H
Sampling clock select register
SCS
R/W
x
DOH
FF49H
B·bit timer mode control register
TMCI
R/W
x
x
DOH
FF4AH
Watch timer mode control register
TMC2
RfW
x
x
DOH
FF4FH
8·bit timer output control register
TOCI
R/W
x
x
DOH
FF60H
Serial operating mode register 0
CSIMO
RfW
x
x
DOH
FF61H
Serial bus interface control register
SBIC
R/W
x
x
DOH
FF62H
Slave address register
SVA
FF63H
Interrupt timing specify register
SINT
FFDOH·FFDFH
External SFR access area(Note 1)
FFEOH
Interrupt flag register l
IFOl
FFE1H
Interrupt flag register H
IFOH
FFEOH-FFEI H
Interrupt flag register
IFO
R/W
FFE4H
Interrupt mask flag register l
MKOl
R/W
x
x
FFE5H
Interrupt mask flag register H
MKOH
R/W
x
x
FFE4H-FFE5H
Interrrupt mask flag register
MKO
RfW
FFEBH
Priority order specify flag register l
PROl
R/W
x
x
FFH
FFE9H
Priority order specify flag register H
PROH
R/W
x
x
FFH
RfW
x
Undefined
x
DOH
R/W
x
R/W
x
x
Undefined
R/W
x
x
DOH
R/W
x
x
DOH
x
OOOOH
FFH
FFH
x
FFFFH
11
NEe
pPD78002Y Fami.ly
Table 2. Special Function Registers (cont)
Access Units (Bits)
Address
Register (SFR)
Symbol
R/W
FFE8H-FFE9H
Priority order specify flag register
PRO
R/W
FFECH
External interrupt mode register
INTMO
R/W
8
16
x
State After Reset
FFFFH
x
OOH
FFF6H
Key return mode register
KRM
R/W
x
x
02H
FFF7H
Pullup resistor option register
PUO
R/W
x
x
OOH
FFFBH
Memory expanded mode register
MM
R/W
x
x
10H
FFF9H
Watchdog timer mode register
WDTM
R/W
x
x
OOH
FFFAH
Oscillation stabilization time select register
OSTS
R/W
x
04H
FFFBH
Processor clock control register
PCC
R/W
x
x
04H
Note: The external access area cannot be accessed using SFR
addressing. It can only be accessed using main memory
addressing.
Input/Output Ports
The pPD78002Y family has up to 53 port lines. Table 3
lists the features of each port and figure 4 shows the
structure of each port pin.
Table 3. Digital Port Functions
Port
Operational Features
Configuration·
Direct Drive Capability
Software Pullup Resistor Connection
(Note 1)
Port 0 (Note 2)
S-bit input or output
Bit selectable
Byte selectable, input bits only
Port 1
B-bit input or output
Bit selectable
Byte selectable, input bits only
Port 2
B-bit input or output
Bit selectable
Byte selectable, input bits only
Port 3
S-bit input or output
Bit selectable
Byte selectable, input bits only
Port 4
B-bit input or output
Byte selectable
Byte selectable, input bits only
PortS
B-bit input or output
Bit selectable
LED
Byte selectable, input bits only
Port 6
B-blt input or output
(P6a - P63 n-c hannel)
Bit selectable
15 V max (P6a - P63)
Byte selectable, input bits only
P6a - P63 - mask option only (Note 3)
P64 - P67 - software
Notes:
(1) Software pullup resistors can be internally connected (only on a
port-by-port basis) to port bits set to input mode. Pull up resistors are not connected to port bits set to output mode.
(2) POa and P04 are input only and do not have a software pull up
resistor.
(3) All devices except jlPD7BPOI4Y.
12
NEe
Figure 4.
IlPD78002Y Family
Pin Input/Output Circuits
~
"--tF
pullup enable
Voo
data~
Type 2 (POo • RESET)
IN
-------1[>><>----1
output disable
0>-----1[90-----.;. .
~
~_>-4--<:>
INfOUT
Schmitt t~gger Input with hysteresis cheractertsUcs
pullup enable
pullupenable
[>
------~[>~-__I
VOO
data
output disable
-r__):>-_-jp....
data - - -.....
~
INfOUT
.....--<1>-"*--<:> INfOUT
opon drain
output disable
-----i-"
Input enable
Type 50B (P40' P4r1
Type 13-B (P60' P631
VOO
Voo
-
~
[Mask OpUon)
~
~
.---+---<>
Voo
data
~
output disable _ _ _ _"""'~
INfOUT
INfOUT
N-ch
Voo
RO
----If-:.-
Input enable
Middle-High Voltage Input Buffer
B3CL·0481. (1193)
13
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pPD78002Y Family
Serial Interface
The f.lPD78002Y family has one serial interface. Serial
interface 0 is an 8-bit clock synchronous serial interface (figure 5). It can be operated in either a three-wire
serial 1/0 mode, NEC serial bus interface (SBI) mode,
two-wire serial 1/0 mode, or 12C bus mode. The serial
clock can be provided from one of eight internal clocks,
the output of 8-bit timer register 2, orthe external clock
line SCKO (SCl for 12C bus mode).
In the three-wire serial I/O mode, the 8-bit shift register
(SIOO) is loaded with a byte of data and eight clock
pulses are generated. The falling edge of these eight
pulses shifts the byte of data out of the SOO line (either
MSB or lSB first) while the rising edge of these pulses
shifts the data in from the SIO line providing full-duplex
operation. The INTCSIO interrupt is generated after
each 8-bit transfer.
Figure 5. Serial Interface 0
SQAO(
SIOI
SBOI
P2s
SCAlI
soot
SB11
P26
From P2e
OUtput Latch
Internal Bus
83YL......
14
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IIPD78002Y Family
The NEC SBI mode is a two-wire high-speed proprietary
serial interface available on most devices in the NEC
J.lPD75xxx and J.lPD78xxx product lines. Devices are
connected in a master/slave configuration (see figure
6). There is only one master device at a time; all others
are slaves. The master sends addresses, commands,
and data over one of the serial bus lines (SBO or SB1)
using a fixed hardware protocol synchronized with the
SCKO line. Each slave device of the J.lPD78002Y family
can be programmed to respond in hardware to any one
of 256 addresses set in its slave address register (SVA).
There are also 256 commands and 256 data types.
Since all commands are user definable, many software
protocols, simple or complex, can be defined. It is even
possible to develop commands to change a slave into a
master and the previous master into a slave.
SCK
SIeVe CPU
Figure 7. PC Bus Master/Slave Configuration
V v,DD
Master CPU
SlsveCPU
(SB1),S80
S80. (581)
Address 1
S80. (SB1)
Address 2
t
f----- SCK
,
The 12C bus is a two-wire, high-speed serial bus developed by Philips. The 12C bus configuration has asingle
master and up to 128 slave devices (see figure 7). The
master sends the start condition, 7-bit slave address,
one bit indicating the direction of the upcoming data
transfer, and the stop condition over one of the serial
bus lines (SOAO or SOA1) using a fixed hardware
protocol synchronized with the serial clock line (SCL).
Each slave device of the J.lPD78002Y family can be
programmed to respond in hardware to anyone of 128
addresses set in its slave address register (SVA). OePhending on thehstalte ofdth~ tranlSfer dirded~ti?n blitd' either ~
t emasterort esave eVlcepacesa Itlona ataon . . . . .'
the 12C bus. The device receiving the data returns an
acknowledge signal each time it receives 8 bits of data.
The slave device can also notify the master device
when it is busy by holding SCL low.
Figure 6. SBI Mode Master/Slave Configuration
SCK
For data reception, the SIOO register is preloaded with
the value FFH. As this data value is shifted out on the
falling edge of the serial clock, it disables the n-channel
open-drain driver. This allows the receive data to be
driven on to the serial line and shifted into the SIOO
register on the rising edge of the serial clock. The
INTCSIO interrupt is generated after each 8-bit transfer.
Master CPU
SCL
SlavelC
SDAO(SDA1)
SlsveCPUl
Serial Clock
SCL
Serlal
Data Bus
SDAO(SDA1)
S80,(581)
AddressN
Slave CPU2
~
SCK
'V
~ SCL
83YL09347A (9193)
The two-wire serial I/O mode provides half-duplex operation using either the SBO or SB1 line and the SCKO
line. Communication format and handshaking can be
handled in software by controlling the output levels of
the data and clock lines between transfers. For data
transmission, the 8-bit shift register (SIOO) is loaded
with a byte of data and eight clock pulses are generated. The falling edge of these eight pulses shifts the
byte of data out of either the SBO or SB1 line MSB first.
In addition, this byte of data is also shifted back into
SIOO on the rising edge of these pulses providing a way
of verifying that the transmission was correct.
SDAO(SDA1)
,
.
I~
~
fl3RD-9447A
15
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pPD78002Y Family
Timers
The pPD78002Y family has two 8-bit timer/event
counters that can be combined for use as a 16-bit
timer/event counter, a watch timer, and a watchdog
timer. All of these can be programmed to count a
number of prescaled values of the main system clock.
In addition, the watch timer can also count the subsystem clock. The two timer/event counters can count
external events.
8-Bit Timer/Event Counters 1 and 2. Timer/event
counters 1 and 2 (figure 8) each consist of an 8-bit
timer (TM1 or TM2), an 8-bit compare register (CR10 or
CR20) , and a timer output control logic (T01 or T02).
The timers are controlled by registers TCl 1, TMC1, and
TOC1 via five selectors. Timer/event counters 1 and 2
can each be used as an 8-bit interval timer, to count
external events onthetimer input pins (T11 orTI2), orto
output a programmable square wave. In addition, timers 1 and 2 also can be combined as a 16-bit timer/
event counter and used as a 16-bit interval timer, to
count external events on T11, or to output a programmable square wave on T02.
Figure 8. 8-Bit Timer/Event Counters 1 and 2
Intemal Bus
------~--------------------~INnM1
* .
TI1IP33-
8-BII
llmer/Event
Counter 2
Outpul
Conlrol logic
T02IP32
.-----t---~
INnM2
I-------t----~
T01IP31
'X/4
'xf8
'x/18
'xl32
'X /84
'x/128
'x1258
'X1512
'x'x/1024
Selector
/4098
TI2IP3t_
* Rising or ,ailing edge can be selected.
16
83Yl-906OB
NEe
pPD78002Y Family
Watch Timer. The watch timer 3 (figure 9) is as-bit
timer that can be used as a time source to keep track of
time of day, to release the STOP or HALT modes at
regular intervals, or to initiate any other task that must
be performed at regular intervals. When driven by the
subsystem clock, the watch timer continues to operate
in the STOP mode.
The watch timer can function as both watch timer and
an interval timer simultaneously.
When used as a watch timer, interrupt requests INTWT
(not a vectored interrupt) can be generated using the
main system or subsystem clock every 0.5 or 0.25
seconds. When used as an interval timer, vectored
interrupt request INTTM3 is generated at preselected
time intervals. With a main system clock of 8.38 MHz or
a subsystem clock of 32.768 kHz, the following time
intervals can be selected: 489 ps, 978 ps, 1.96 ms, 3.91
ms, 7.82 ms or 15.6 ms.
Figure 9.
Watch Timer
•
~--------------------------------------------------------------------~
r--Selector
fw f29
Xf28 _
f
xr -
)
I
fwf2 13
Clear
Selector I---INlWT
-~
fw f27
fW
Prescaler
Timer Clock Select
Register 2 (TC1.2)
f w f2 6
INTIM3
Selector
fw f25
-:--
fw f2 4
jClear
I
'--.--
508ft
Timer
-
fw l28
,...-Selector
1
---1
f w f2 14
t
I
I
I
I
I
Watdl Timer Mode
Conbol Register (TMC2)
Intemal Bus
~
I
<.
B3CL-848OII(7111O,
17
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IlPD78002Y Famil y
Watchdog Timer. The watchdog timer (figure 10) can
be used as either a watchdog timer or an interval timer.
When used as a watchdog timer, it protects against
program run-away. It can be selected to generate a
nonmaskable interrupt (INTWDl), which vectors to address 0004H, or to generate an internal reset signal,
which vectors to the restart address OOOOH if the timer
is not cleared by the program before it overflows. Eight
program-selectable intervals based on the main system clock are available. With a main system clock of
8.38 MHz, the program selectable intervals are 0.489,
0.978, 1.96,3.91, 7.82, 15.6,31.3, and 125 ms. Once the
watchdog timer is initialized and started, the timer's
mode cannot be changed and the timer can only be
stopped by an external reset.
When used as an interval timer, maskable interrupts
(I NTWDl) , which vector to address 0004H, are generated repeatedly at a preset interval. The time intervals
available are the same as in the watchdog timer mode.
Figure 10.
Watchdog Timer
Run
f (25
f (26
f (27
fX(24
PrescaJer
f (28
f (29
f (210
f (212
Selector
8Counter
INlWDT
Maskable
Interrupt
Request
Control
logic
RESET
INlWDT
Nonmaskable
Interrupt
Request
Internal Bus
83YL·935.2B (8193)
18
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pPD78002Y Family
Programmable Clock Output
Buzzer Output
The pPD78002Y family has a programmable clock output (PCl) that can be used for carrier output for remote
controlled transmissions or as a clock output for peripheral devices. The main system clock (f0 divided by
8, 16, 32, 64, 128, or 256 or the subsystem clock (fXT)
can be output on the PCl pin. Frequencies of 1050, 524,
262, 131, 65.5 and 32.7 kHz are available with a main
system clock of 8.38 MHz. See figure 11.
The pPD78002Y fami Iy also has a programmable buzzer
output (8UZ). The buzzer output frequency can be
programmed to be equal to the main system clock (f0
divided by 1024, 2048, or 4096. With a main system
clock of 8.38 MHz, the buzzer can be set to 8.2, 4.1 or 2.0
kHz. See figure 12.
Figure ". Programmable Clock Output
'XI23---~
'x124 ----~
'x/25---~
'X/26 ---~ Selector
fx/27---~
'x/28---~
'XT
------,~
Figure 12. Buzzer Output
'XI210_--~
f x 12 11 ----;~ Selector
I - - - - - - - - - - l " " - ' > -_ _ _ _--I
fxI212_--~
19
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pPD78002Y, Family
Interrupts
The pPD78002Y family has 11 maskable hardware interrupt sources (5 external and 6 internal). Of these 11
interrupt sources, 9 cause a vectored interrupt while
the 2 testable inputs only generate an interrupt request. All of the 11 maskable interrupts can be used to
release the HALT mode except INTPO. INTPO cannot be
used to release the STOP mode and cannot release the
HALT mode when regiser SCS = O. In addition, there is
one nonmaskable interrupt from the watchdog timer,
one software interrupt, and a RESET interrupt. The
watchdog timer overflow interrupt (interrupt vector
table address 0004H) can be initialized to be a nonmaskable interrupt or the highest default priority maskable interrupt. The software interrupt, generated by the
BRK instruction, is not maskable. See table 4 and figure
13.
Table 4. Interrupt Sources and Vector Addresses
Type of
Request
Default
Priority
Vector
Interrupt
Address Configuration
Signal Name
Interupt Source
Location
Restart
RESET
INTWDT
RESET Input Pin
Watchdog timer overflow
(when reset mode selected)
External
Internal
OOOOH
Nonmaskable
iNTWDT
Watchdog timer overflow
(when nonmaskable interrupt selected)
Internal
0OO4H
A
INTWDT
Watchdog timer overflow
(when interval timer selected)
Internal
0OO4H
B
Maskable
0
INTPO
External Interrupt edge detection
External
0OO6H
C
2
INTPI
External interrupt edge detection
External
OOOSH
0
3
INTP2
External interrupt edge detection
External
OOOAH
0
4
INTP3
External interrupt edg!! detection
External
OOOCH
0
5
INTCSIO
End of clOCked serial interface 0 transfer
Internal
OOOEH
B
6
INTTM3
Watch timer reference time interval signal
Internal
0012H
B
7
INTTMI
S-blt timer/event counter 1 coincidence signal
Internal
0016H
B
8
INTTM2
B-bit timer/event counter 2 coincidence signal
Internal
0018H
B
BRK instruction
Internal
003EH
E
INTWT
Watch timer overflow
Internal
F
INTPT4
Port 4 failing edge detection
External
F
Software
Test input
Interrupt Servicing. The pPD78002Y family provides
two levels of programmable hardware priority control
and services all interrupt requests, except the two
testable interrupts (INlWT and INTPT4). Using vectored interrupts, the programmer can choose the priority of servicing each masKable interrupt by using the
interrupt control registers.
Interrupt Control Registers. The pPD78002Y family
has three 16-bit interrupt control registers. The interrupt request flag register (IFO) contains an interrupt
request flag for each interrupt except INTPT4. The
interrupt mask register· (MKO) is used to enable or
disable any interrupt except INTPT4. The priority flag
register (PRO) can be used to specify a high or a.low
priority level for each interrupt except the two testable
interrupts.
20
Four other 8-bit registers are associated with interrupt
processing. The key return mode register (KRM) contains the KRIF interrupt request flag associated with
falling-edge detection on port 4 and the KRMK mask
flag used to enable or disable clearing of the standby
mode if a falling edge is detected on port 4. The
external interrupt mode register (INTMO) is used to
select a rising, falling, or both edges as the valid edge
for each of the external interrupts INTPO to INTP2
(INTP3 is always falling edge). The sampling clock
select register (SCS) is used to select a sampling clock
for the noise eliminator circuit on external interrupt
INTPO.
The IE and the ISP bit of the program status word are
also used to control interrupts. If the IE bit is 0, all
maskable interrupts are disabled. The IE bit can be set
or cleared using the EI and DI instructions, respectively, or by directly writing to the PSW The IE bit is
NEe
IIPD78002Y Family
cleared each time an interrupt is accepted. The ISP bit
is used by hardware to hold the priority level flag of the
interrupt being serviced.
Figure 13. Interrupt Configurations
Type A: Intemal nonmaskablelnterrupt
Interrupt _ _-+_ _ _.....
Request
Standby
~----------~Re~ae
Signal
Type B: Intemal maskable Interrupt
Type C: External maskablelnterrupt (lHTPO)
Vector Table
Addrass Generator
~----------,~
Standby
Release
SIgnal
83YL..fDi68('1)
21
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pPD78002Y Family
Figure 13. Interrupt Configurations (cont)
Type D: External maskable Interrupt (except INTPO)
Vector Table
Address Generator
Interrupt _ _ _ _~
Request
Standby
' - - - - - - - - - - - - - c... Release
Signal
Type E: Software Interrupt
I
Interrupt
Priority
Request -------~~ Control Circuit
Type F: Test Input
Standby
}---~ Release
r----,'---'
Signal
AbbrevlaUons:
IF: Interrupt request flag
IE: Interrupt enable flag
ISP: In-servlce p~orlty flag
MK: Interrupt mask flag
PRo P~orlty specify flag
83Yl-9356B (2)
22
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JlPD78002Y Family
Interrupt Priority. If the watchdog timer overflow interrupt (INlW01) has been initialized to be a nonmaskable interrupt, it has priority over all other interrupts.
Two hardware-controlled priority levels are available
for all maskable interrupts that generate a vectored
interrupt (i.e., all except the two testable interrupts).
Either a high or a low priority level can be assigned by
software to each of the maskable interrupts. Interrupt
requests of the same priority or a priority higher than
the processor's current priority level are held pending
until interrupts in the current service routine are enabled by software or until one instruction has been
executed after returning from the current service routine. Interrupt requests of a lower priority are always
held pending until one instruction has been executed
after returning from the current service routine.
Power consumption may be further reduced by using
the STOP mode. The STOP mode is entered by executing a STOP instruction while operating from the main
system clock. In STOP mode, the main system clock
input pin X1 is internally grounded stopping both the
CPU and the peripheral hardware clock. The STOP
mode is released by any unmasked interrupt request
except INTPO, a nonmaskable interrupt request, an
unmasked test input, or an external reset pulse. Any
peripheral using the main oscillator as a clock source
will also be disabled in the STOP mode and interrupts
from such a peripheral cannot be used to exit the STOP
mode. Table 5 summarizes both the HALT and STOP
standby modes.
The default priorities listed in table 4 are fixed by
hardware and are effective only when it is necessary to
choose between two interrupt requests of the same
software-assigned priority. For example, the default
priorities would be used after the completion of a
high-priority routine, if two interrupts of the same
software priority were pending.
Item
HALT Mode
STOP Mode
Setting
instruction
HALT instruction
STOP instruction
System
clock when
setting
Main system or
subsystem clock
Main system clock
Clock
oscillator
Main system and
subsystem clocks can
oscillate; CPU clock is
stopped.
Subsystem clock can
oscillate; CPU clock
and main system
clock are stopped.
CPU
Operation stopped
Operation stopped
Ports
Maintain previous
state
Maintain previous
state
8-bit timer/
Operational from main
system clock
Operational only with
TI1 and TI2 as count
clock
Watch timer
Operational from main
system clock or with
txT as count clock
Operational only with
txT as count clock
Watchdog
Operational from main
system clock
Operation stopped
timer
Serial
interface 0
Operational from main
system clock
Operational only with
external clock
External
interrupts
Operational except for
INTPO when its
sampling clock is
based on the CPU
clock
INTPO not operational;
INTP1 to INTP3
operational
The software interrupt, initiated by the BRK instruction, is executed regardless of the processor's priority
level and the state of the IE bit. It does not alter the
processor's priority level.
Vectored Interrupt Servicing. When a vectored interrupt is acknowledged, the program status word and
the program counter are saved on the stack, the processor's priority is set to that specified for the interrupt,
the IE bit in the PSW is set to zero, and the routine
whose address is in the interrupt vector table is entered. At the completion of the service routine, the RETI
instruction (RETB instruction for the software interrupt) reverses the process and the JlP078002Y family
microcontroller resumes the interrupted routine.
Standby Modes
HALT, STOP, and data retention modes are provided to
reduce power consumption when CPU action is not
required.
The HALT mode is entered by executing a HALT instruction while the CPU is operating from the main
system or subsystem clock. In HALT mode, the CPU
clock is stopped while the main system and the subsystem clock continue to run. The HALT mode is released by any unmasked interrupt request (except
INTPO if register SCS = 0), a nonmaskable interrupt
request, an unmasked test input, or an external reset
pulse.
TableS.
event
counters
Standby Mode Operation Status
a;;
if'
When exiti ng the STOP mode, a wait time occurs before
the CPU begins execution to allow the main system
clock oscillator circuit to stabilize. The oscillator stabilization time is selected by programming the OSTS
register with one of five values before entering the
STOP mode. The values range from 0.98 msec to 31.3
msec at fx = 8.38 MHZ.
23
pPD78002V Family
Once in the STOP mode, power consumption can be
further minimized by lowering the power supply voltage Voo to as little as 2 V. This places the device in the
data retention mode. The contents of Internal RAM and
the registers are retained. This mode is released by first
raising Voo to the proper operating range and then
releasing the STOP mode.
External Reset
The JlPD78002Y family is reset by taking the RESET pin
low or by an overflow of the watchdog timer (if enabled). The RESET input pin is a schmitt-trigger input
with hysteresis characteristics to protect against spurious system resets caused by noise. On power-up, the
RESET pin must remain low for a minimum of 10Jls after
the power supply reaches its operating voltage.
There is no functional difference between an external
reset and an internal reset caused by the overflow of
the watchdog timer. In both cases, the main system
clock oscillation is stopped and the subsystem clock
oscillation continues. During reset, the program
counter is loaded with the address contained in the
reset vector (addresses OOOOH, 0001H). Once the reset
is cleared and the oscillation stabilization time of 218/fx
has elapsed, program execution starts at that address.
24
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pPD78002Y Family
Capacitance
ELECTRICAL SPECIFICATIONS
TA = +25'C; Voo = VSS = 0 V
The following specifications are for the pPD78001 BY/
002BY devices only. Refer to the pPD78014Y data sheet
for pPD78P014Y device specifications.
Parameter
Symbol
Max
Unit
Conditions
Input
capacitance
CIN
15
pF
Except P60
to P6a
20
pF
P60 to P6a
Output
capacitance
COUT
15
pF
Except P60
to P63
20
pF
P60 to P6a
Input/output
capacitance
CIO
15
pF
Except P60
to P6a
20
pF
P60 to P63
Absolute Maximum Ratings
TA = +25'C
Supply voltage, Voo
-0.3 to +7.0 V
Input voltage, V11 (except P60 to P63l
-0.3 to Voo+ 0.3 V
-0.3 to +16 V
Input voltage, VI2 (P60 to P63; open
drain)
Output voltage, Vo
-0.3 to Voo+ 0.3 V
Output current, high; IOH
Each output pin
Total: ports 1 to 3
Total: port 0 and ports 4 to 6
Output current, low, IOL t
Each output pin
Total: P4 0 to P47 and
P50 to P55
Total: POI to POa, P5e, P57, and P60
to P67
Total: POt to PDa and P64 to P67
Total: ports 1 to 3
f = 1 MHz;
unmeasured
pins returned
to ground
-10 mA
-15mA
-15mA
30 mA peak, 15 mA rms
100 mA peak, 70 mA rms
100 mA peak, 70 mA rms
50 mA peak, 20 mA rms
50 mA peak, 20 mA rms
Operating temperature, TOPT
-40 to +85'C
Storage temperature, TSTG
-65 to +l50'C
t rms value = peak value x (duty cycle) 1/2
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent damage. The device should be operated within the 11m its
specified under DC and AC characteristics.
Main System Clock Oscillator
= -40 to +85'C; VOO = 2.7 to 6.0 v; refer to figure 14.
TA
Type
Parameter
Symbol
Min
Ceramic resonator
(Figure 14A)
Oscillation frequency (Note 1)
fX
1.0
Crystal resonator
(Figure 14A)
Oscillation frequency (Note 1)
External clock
(Figure 148)
Xl input frequency (Note 1)
Typ
Oscillation stabilization time
(Note 2)
fX
1.0
Oscillation stabilization time
(Note 2)
fX
XI input high/low-Ievel width
8.38
Max
Unit
Conditions
10.0 .-
MHz
VOO = oscillator voltage range
4.0
ms
10.0
MHz
10
ms
30
ms
1.0
10.0
MHz
50
500
ns
After Voo reaches oscillator
operating voltage
Voo = 4.5 to 6.0 V
Notes:
(1) Oscillator and Xl input frequencies are included only to show the
oscillator characteristics. Refer to the AC Characteristics table
for actual instruction execution times.
(2) Time required for the oscillator to stabilize after reset or STOP
mode is released. The values shown are for the recommended
resonators. Values for resonators not shown in this data sheet
should be obtained from the manufacturer's specification sheets.
25
N-EC
pPD78002Y Family
Subsystem Clock Oscillator
TA
= -40 to +85°C; Voo = 2.7 to 6.0 V; refer to figure 15..
Type
Parameter
Symbol
Crystal resonator
(Figure 15A)
Oscillation frequency (Note 1)
IXT
External clock
(Figure 158)
Min
Typ
Max
Unit
32
32.768
35
kHz
2
s
10
s
32
100
kHz
5
15
JlS
1.2
Oscillation stabilization time (Note 2)
XT1 input frequency (Note 1)
IXT
XT1 input high/low-level width
txTH, txTL
Conditions
Voo = 4.5 to 6.0 V
Notes:
(1) The oscillator and XT1 input frequencies are included only to
show the oscillator characteristics. Refer to the AC Characteristics table for actual instruction execution times.
(2) Time required for the oscillator to stabilize after reset or STOP
Figure 14. Main System Clock Configurations
Figure 15. Subsystem Clock Configurations
mode is released. The values shown are for the recommended
resonators. Values for resonators not shown in this data sheet
should be obtained from the manufacturer's specification sheets.
A. Crystal Resonator
A. CeramlclCryatal Resonator
r-_>----IXl
r-~---IXT1
XT2
X2
R2
Rl
B. External Clock
B. External Clock
Xl
XTl
X2
XT2
I'P074HCU04
83YL..fI367A
Note: When the Input Is an extemal clock, the STOP
mode can not be set because the Xl pin Is connected
to system ground (Vss).
26
NEe
pPD78002V Family
Recommended Main System Clock Ceramic Resonators
TA = -40 to +85'C; refer to figure 14A.
Part Number
(Notes 1 and 2)
Recommended Circuit Constant
C1 (pF)
Oscillator Voltage Range
C2 (pF)
R1 (kO)
Min (V)
Max (V)
Frequency
(MHz)
CSB1000J
100
100
6.8
2.7
6.0
1.00
CSBxxxxJ
100
100
4.7
2.7
6.0
1.01 to 1.25
1.26 to 1.79
CSAx.xxxMK
100
100
0
2.7
6.0
CSAx.xxMG
100
100
0
2.7
6.0
1.80 to 2.44
CSTx.xxMG
(Note 3)
(Note 3)
0
2.7
6.0
1.80 to 2.44
2.45 to 4.18
CSAx.xxMG
CSTx.xxMGW
30
30
0
2.7
6.0
(Note 3)
(Note 3)
0
2.7
6.0
2.45 to 4.18
30
30
0
2.7
6.0
4.19 to 6.00
(Note 3)
(Note 3)
0
2.7
6.0
4.19 to 6.00
30
30
0
2.7
6.0
6.01 to 10.0
(Note 3)
(Note 3)
0
2.7
6.0
6.01 to 10.0
CSAx.xxMG
CSTx.xxMGW
CSAx.xxMT
CSTx.xxMTW
Notes:
(1) Manufactured by Murata Mfg. Co., Ltd.
(3) Cl and C2 are contained in the ceramic resonators.
(2) x.xx indicates frequency
I
Recommended Subsystem Clock Crystal Resonators
TA = -40 to +60'C; refer to figure 15A.
Part Number
t
DT-38 (1TA252 EOO, load capacitance 6.3 pF)
..
Frequency
(kHz)
32.768
Recommended Circuit Constant
C3 (pF)
12
Oscillator Voltage Range
C4 (pF)
R2 (kll)
Min (V)
Max (V)
12
100
2.7
6.0
t Manufactured by Daishinku
27
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pPD78002Y Famil y
DC Characteristics
TA = -40 to +85°0; Voo = +2.7 to S.O V; refer to figures 1S-21
Parameter
Symbol
Max
Unit
High'level input voltage
VIH1
0.7 Voo
Voo
V
Other than below
VIH2
0.8 VOO
Voo
V
POo to PO~P22' P24 to P27,
P33, P34, RESET
Low-level input voltage
Low-level output voltage
High-level input leakage
current
Low-level input leakage
current
Typ
Conditions
VIH3
0.7Voo
15
V
Paoto P63; open-drain
VIH4
Voo,-0.5
Voo
V
X1,X2
VIH5
Voo-0.5
Voo
V
Voo = 4.5 to S.OV; XT1, XT2
VIL1
0
0.3 Voo
V
Other than below
VIL2
0
0.2Voo
V
POo to P04, P20, P22, P24 to P27,
P33, P34, RESET
0
PSo to PS3; V 00 = 4.5 to S.O V
ci. 3Voo
V
0
0.2VOO
V
PSo to PS3
VIL4
0
0.4
V
X1,X2
VIL5
0
0.4
V
XT1, XT2; V 00 = 4.5 to S.O V
0
0.3
V
XT1, XT2
voo-1.ci
V
VOO = 4.5 to S.O
VOO - 0.5
V
IOH = -100 JlA
2.0
V
P50to P57, peo to PS3;
Voo = 4.5toS.OV,IOL =:' 15mA
, 0.4
V
Other than above; V 00 = 4.5 to 6.0 V,
IOL = 1.S mA
S80, S81, SOKO; V00 = 4.5 to S.O V,
open-drain, 'pullup resistance = 1 kO
VIL3
High-level output voltage
Min
VOH1
0.4
VOL1
V, IOH =
-1.0 mA
VOL2
0.2VOO
V
VOL3
0.5
V
IUH1
3
JlA
VIN = Voo; except X1, X2, XT1, XT2
IUH2
20
JlA
VIN = VOO; X1, X2, XT1, XT2
IUH3
80
JlA
VIN = 15 V; PSo to PS3
IUL'
-3
JlA
VIN = 0 V; except X1, X2, XT1, XT2
IUL2
-20
JlA
VIN = OV; X1, X2, XT1, XT2
JlA
VIN = 0 V; PSo to PS3 (Note 1)
IoL = 400JlA
IUL3
-3
Output leakage current high
ILOH,
3
JlA
VOUT = Voo
Output leakage current low
ILOL
-3
JlA
VOUT= OV
Mask option pull up resistor
R,
20
40
90
kO
VIN = 0 V; P60 to PS3
Software pullup resistor
R2
15
40
90
kO
Voo = 4.5 to 6.0 V; VIN = 0 V, PO, to P03,
ports 1 to 5, PS4 to P67
500
kO
Voo= 2.7t04.5V;VIN= OV,PO,toP03,
ports 1 to 5, P64 to P67
20
28
NEe
pPD78002Y Family
DC Characteristics (cent)
Parameter
Symbol
Power supply current
1001
Min
Typ
Max
Unit
Conditions
7.5
22.5
rnA
8.38 MHz crystal oscillation operating mode;
Voo = 5.0 V ±10% (Note 2)
0.8
2.4
rnA
8.38 MHz crystal oscillation operating mode;
Voo = 3.0 V ±10% (Note 3)
1.4
4.2
rnA
8.38 MHz crystal oscillation HALT mode;
VOO = 5.0 V ±10%
1003
550
1650
f.JA
8.38 MHz crystal oscillation HALT mode;
Voo= 3.OV±10%
60
120
f.JA
32.768 kHz crystal oscillation operating mode;
Voo = 5.0 V ±10%, XI STOP mode, CPU
operating from subsystem clock
35
70
f.JA
32.768 kHz crystal oscillation operating mode;
Voo = 3.0 V ±10%, XI STOP mode, CPU
operating from subsystem clock
1004
25
50
32.768 kHz crystal oscillation HALT mode;
Voo = 5.0V ±10%,XI STOP mode
5
10
32.768 kHz crystal oscillation HALT mode;
VOO = 3.OV ±10%,Xl STOP mode
20
XTI = 0 V STOP mode when feedback resistor
is connected; Voo = 5.0 V ±10%
0.5
10
XTt = 0 V STOP mode when feedback resistor
is connected; Voo = 3.OV ±10%
0.1
20
XTI = 0 V STOP mode when feedback resistor
is disconnected; Voo = 5.0V ±10%
0.05
10
XTI = 0 V STOP mode when feedback resistor
is disconnected; Voo = 3.OV ±10%
1005
1006
Notes:
(1) P60 to P63 become -200 f.JA (max.) for only 1 clock cycle during
input instruction execution (no wait) and -3 f.JA (max.) during
Instruction other than input.
(2) When operated in the high-speed mode with the processor clock
control register set to OOH.
(3) When operated in low-speed mode with the processor clock
control register set to 04H.
29
•
NEe
pPD78002Y Family
Figure 16. 100 vs Voo (Ix = 8.38 MHz)
PCC = OOH (I C'f='o48!IADD2
)
lowerS-BIt'
I>----!l~----I
Address
r--
HI·Z
Write Data
C
IADH
lADS
ASTB
RaedData
J-~(
~IASTRD~
'"~r
I I
I
\
i
IRDL2
~II
~
~
-
I.IRDWT2~
I
IASlWR
+-IWTL
I
-J ..
IWDS
IWOWR
!
\
IWTRD-I IWRWT-
_IWRL1-
W A I T - U - l
_IWRADH-
~-
_IWTL-
i - -IWlWR
B3FM-9374B
37
NEe
pPD78002Y' Family
Serial Interface, 3-Wire, I/O Mode; Internal SCK Output
TA
= -40 to + 85°C; V00 = 2.7 to 6.0 V; refer to figure 32
Parameter
Symbol
Min
SCK cycle time
tKCY1
800
3200
ns
SCK hlgh- and low-level width
tKH1, tKll
tKCY1!2-50
ns
tKCY1!2 - 150
ns
ns
SI setup time to SCK t
tSIKl
100
SI hold time from SCK t
tKSll
400
SO output delay time from SCK ,
tKSOl
Typ
Max
Unit
Conditions
ns
Voo = 4.5 to 6,0 V
Voo = 4.5 to 6.0 V
ns
300
ns
Voo = 4.5 to 6,0 V; C = 100 pF (Note 1)
1000
ns
C = 100 pF (Note 1)
Note 1: C is the load capacitance of the SO output line.
Serial Interface, a-Wire, I/O Mode; External SCK Input
TA
= -40 to +85°C; Voo = 2.7 to 6.0 V; refer to figure 32
Parameter
Symbol
Min
SCK cycle time
tKCY2
800
SCK high- and low-level width
tKH2, tKl2
Typ
Max
Unit
Conditions
ns
Voo = 4.5 to 6.0 V
3200
ns
400
ns
1600
ns
ns
SI setup time to SCK t
tSIK2
100
SI hold time from SCK t
tKSI2
400
SO output delay time from SCK ,
tKS02
Voo = 4.5 to 6,0 V
ns
300
ns
Voo = 4.5 to 6,0 V; C = 100 pF (Note 1)
1000
ns
C = 100 pF (Note 1)
Max
Note 1: C Is the load capacitance of the SO output line.
Serial Interface, SBI Mode; Internal SCK Output
TA
= -40 to + 85°C; Voo = 2.7 to 6.0 V; refer to figure 33
Parameter
SCK cycle time
SCK high- and low-level width
SBO, S81 setup time to SCK t
SBO, S81 hold time from SCK t
Symbol
Min
Unit
Conditions
tKCY3
800
ns
Voo = 4,5 to 6,0 V
3200
ns
tKCy:y2 - 5O
ns
tKCy312 - 150
ns
tKH3, tKl3
tSIK3
Typ
100
ns
300
ns
Voo = 4,5 to 6.0 V
Voo = 4.5 to 6,0 V
ns
tKSI3
tKCy312
SBO,SBI output delay time from SCK ,
tKS03
a
250
ns
Voo = 4.5 to 6.0 V; R = 1 ko,
C = 100 pF (Note 1)
a
1000
ns
R = 1 ko, C = 100 pF (Note 1)
SBO, SBI 'from SCK t
tKSB
tKCY3
ns
SCK , from SBO, SBI ,
tSBK
tKCY3
ns
SBO, SBI high-level width
tSBH
tKCY3
ns
SBO, SBI low-level width
tSBl
tKCY3
ns
Note 1: Rand C are the load resistance and load capacitance of the
SBO and SBl output lines.
38
NEe
pPD78002V Family
Serial Interface, S81 Mode; External SCK Input
TA = -40 to +85'C; Voo = 2.7 to 8.0 V; refer to figure 33
Parameter
SCK cycle time
SCK high- and low-level width
Symbol
Min
Unit
Conditions
tKCY4
BOO
ns
Voo = 4.5 to 6.0 V
3200
ns
400
ns
1800
ns
100
ns
300
ns
tKH4, tKl4
SBO, SBl setup time to SCK !
tSIK4
SBO, SBl hold time from SCK!
Typ
Max
Voo = 4.5 to 6.0 V
Voo = 4.5 to 6.0 V
ns
tKSI4
tKCy.v2
tKS04
0
300
ns
Voo = 4.5 to 6.0 V; R
(Note 1)
0
1000
ns
R = 1 ko, C = 100 pF (Note 1)
tKSB
tKCY4
ns
SCK I from SBO, SBl I
tSBK
tKCY4
ns
SBO, SBl high-level width
leBH
tKCY4
ns
SBO, SBl low-level width
tSBl
tKCY4
ns
SBO, SBl output delay time from SCK
SBO, SBl
~
from SCK
~
t
= 1 ko, C = 100 pF.
..
Note 1: Rand C are the load resistance and load capacitanoe of the
SBO and SBl output lines.
I
Serial Interface, 2-Wire, I/O Mode; Internal SCK Output
TA = -40 to +85'C; Voo = 2.7 to 8.0 V; refer to figure 34
Parameter
Symbol
Min
Unit
Conditions
SCK oycle time
tKCY5
1800
Typ
ns
Voo
3BOO
ns
Max
= 4.5 to 8.0 V
SCK high-level width
tKH5
tKCY5/2 - 50
ns
SCK low-level width
tKl5
tKCY5/2-50
ns
SBO, SBl setup time to SCK t
tSIKS
300
ns
SBO, SBl hold time from SCK t
tKSI5
600
SBO, SBl output delay time from SCK ~
tKS05
0
250
ns
Voo = 4.5 to 6.0 V
R = 1 ko, C = 100 pF (Note 1)
o
1000
ns
R = 1 ko, C = 100 pF (Note 1)
ns
Note 1: Rand C are load resistanoe and load capaoitance of the
SCKO, SBO, and SBl output lines.
39
NEe
pPD78002Y Family
Serial Interface, 2-Wire, I/O Mode; External SCK Input
TA = -40 to +85°C; voo = 2.7 to 6.0 V; refer to figure 34
Parameter
Symbol
Min
Unit
Conditions
SCK cycle time
tKCY6
1600
Typ
ns
Voo
3800
ns
Max
=
4.5 to 6.0 V
SCK high-level width
tKH6
650
ns
SCK low-level width
tKL6
800
ns
SBO, S81 setup time (to SCK t)
tSIK6
100
ns
S80, S81 hold time (from SCK t)
tKSI6
tKCY6/2
S80, S81 output delay time from SCK ~
tKS06
0
300
ns
Voo = 4.5 to 6.0 V
R = lko, C = 100 pF (Note 1)
o
1000
ns
R
Note 1: Rand C are load resistance and load capacitance of the
SCKO, S80, and S81 output lines.
Figure 32. Serial Interface Timing;
3-Wire Serial If0 Mode
I..EE------tKCY1,2----~
tSIK1,2
...
-+_~.~
Sl--:--------++-
I KS05,8
8BO,1
41
N,EC
pPD78002Y':Famlly
Serial Interface, 12C Bus
Refer to figure 35
Parameter
Symbol
SCL input clock frequency
fSCL
0
Min
typ
Max
Unit
100
kHz
Bus release time before start of transfer
tBUF
4,7
j./s
Start condition hold time
tHOST'"
4,0
j./s
SCL low-level time
tLOW
4.7
j./s
SCL hlgh.level time
tHIGH
4.0
j./s
Start condition setup time
tSUSTA
4.7
j./s
Data hold time
tHDDAT
0
j./s
Data setup time
IsUDAT
250
ns
SOA, SOAO, SOA1, SCL signal rise time
tR
SOA, SOAO, S0A1, SCL signal fall time
tF
Stop condition setup time
IsUSTO
j./s
300
4.7
Figure 35. Serial Interface Timing; PC Bus Mode
SOL
SDAO,SDA1
42
ns
j./s
Conditions
SCL fall time: data retention
NEe
pPD78002V Family
Data Memory STOP Mode; Low-Voltage Data Retention
TA = -40 to +85"C; refer to figure 36
Parameter
Symbol
Min
Data retention supply voltage
VOOOR
2.0
Data retention power supply current
IOOOR
Release signal set time
tSREL
Oscillation stabilization wait time
tWAIT
Typ
0.1
Max
Unit
6.0
V
10
I1A
0
Conditions
VOOOR = 2.0 V; subsystem clock stop and
feedback resistor disconnected
I1s
218tlx
ms
Release by RESET
(Note 1)
ms
Release by interrupt
Note: 213tfx, 215tfx, 21Sffx, 217ffx or 2 18ftx can be chosen by using
bits 0 to 2 of the oscillation stabilization time select (OSTS)
register.
Figure 36. Data Retention Timing
A. STOP mode is released by RESET input
•
Internal reset
cperatlon
t:'
t
VOO
I
II
STOP mode
HALT mode
I
I
Data retention mode - - -
VOOOR
Operation
mode
/
Execution of
STOP Instruction
\
\.....J
tWAIT
_tSREL
B. STOP mode is released by interrupt signal
HALT mode
VOO
t:
t
Execution 01
STOP Instruction
Standby release signal
Clocks to Pe ~pheral
Hardwara
Ix
22 2i 24
4r-..,.
I I--ft)
~
Standby
Control
Circuit
.-
r
t
INTPO
1
Proceseor Clock Control RlI1Ptar
(Poo)
B
."
8
IT
Sampling Clock
To Subsystem
Clock OsciIator
STOP
Walt
Control
Circuit
CPU Clock
NEe
pPD78014 Family
Memory Space
Since the shortest instruction takes four CPU clocks to
execute, the fastest minimum instruction execution
time (tCY) of 0.4 /ls is achieved when using a main
system clock at 10 MHz (Voo equals 4.5 to 6.0 V).
However, if the clock timer must generate an interrupt
every 0.5 or 0.25 seconds, tCY is 0.48 /ls at 8.38 MHz.
The fastest minimum instruction execution time available across the full voltage range of 2.7 to 6.0 V is 0.96
/ls when using a main system clock of 8.38 MHz. For the
lowest power consumption, the CPU can be operated
from the subsystem clock and the minimum instruction
execution time is 122 /ls at 32.768 kHz.
The /lPD78014 family has a 64K-byte address space.
Some of this address space (OOOOH-FFFFH) can be
used as both program and data memory as shown in
figure 2.
Figure 2. Memory Map
OOOOH
1- Relat1va
Addressing
OOOOH
Intemal
Program
Memory
(ROM/PROM)
003FH
OO4OH
007FH
0080H
2 - Immediate
Addressing
07FFH
OBOOH
3 - Table Indirect
Addressing
Exlemal
Memory
1 - DIrect Address1ng
FA7FH
FABOH
2 - Register Indirect
Addressing
3 - Based Addresslng
FABFH
FACOH
4 - Based Indexed
Addressing
FADFH
FAEOH
Note 2
11
Register
Address1ng
FEEOH
r:
FEFFH
SFR
Address1ng
FFFFH
N_:
(1) 1FFFH on I'PD78011
3FFFH on I'PD78012
5FFFH on I'PD78013
7FFFH on I'PD780141P014
(2) FCFFH on I'PD780111012
FAFFH on I'PD7801310141P014
Program Area
CALLFEntry
Area
~
OFFFHI
1000H
~
FE20H
Program Area
NoteJ
Program
Memory
Space
tf
Use
ProhibIted
Buffer
RAM
Use
Prohibited
saddr Addressing
Intemal
Hlgh-Spead
RAM
FEDFH
CALLT Table Area
~
Note 1
4- Register
Addressing
Interrupt Vector
Address Table Area
I
General
RegIsters
Special
Function
RegIster
(SFR)
I
-------
General RAM
FEDFH
FEEOH
--------
FEFFH
FFOOH
--------
FF1F
General Registers
Short DIrect
AddressIng
(256 bytes)
32 Bytes of
SFRArea
9
NEe
pPD78014 Family
Internal Program Memory
All devices in the pPD78014 family have internal program memory. The pPD78011B/012B/013/014 contain
8K, 16K, 24K, and 32K bytes of internal ROM, respectively. The pPD78P014 contains 32K bytes of UV EPROM
or one time programmable ROM. To allow the
pPD78P014 to emulate the mask ROM devices, the
amount of internal program memory available in the
pPD78P014 can be selected using the memory size
switching register (IMS).
Internal RAM
The pPD78011 B/012B have 544 bytes and the
pPD78013/014/P014 have 1056 bytes of Internal RAM.
This Internal RAM consists of two types: high-speed
Internal RAM and buffer RAM.
The pPD78011B/012B contain 512 bytes (FDOOH to
FEFFH) while the pPD78013/014/P014 contain 1024
bytes (FBOOH to FEFFH) of high-speed Internal RAM.
The high-speed Internal RAM contains the general
register banks and the stack. The remainder of the
high-speed Internal RAM and any unused register bank
locations are available for general storage.
All devices also contain 32 bytes of buffer RAM (FACOH
to FADFH). The buffer RAM is accessed at the same
speed as external memory and is used as the buffer
area for the automatic transfer mode of serial interface
1 or for general storage.
To allow the pPD78P014 to emulate the mask ROM
devices, the amount of high-speed Internal RAM available in the pPD78P014 can also be selected using the
IMS.
External Memory
The pPD78014 family can access 0, 256, 4K, 16K or all
available bytes of external memory. The pPD78014
family has an 8-bit wide external data bus and a 16-bit
wide external address bus. The low-order 8 bits of the
address bus are multiplexed to provide the 8-bit data
bus and are supplied by port 4. The high-order address
bits of the 16-bit address bus are taken from port 5 as
required. The address latch, read, and write strobes,
and the external WAIT signal are supplied by port 6.
The memory expansion mode register (MM) controls
the size of external memory. It can be programmed to
use 0, 4, 6, or 8 bits from port 5 for the high-order
address. Any remaining port 5 bits can be used for I/O.
The MM register also can be used to specify one
10
additional wait state or the use of the external WAIT
signal for low-speed external memory or external peripheral devices.
When only internal ROM and RAM are used and no
external memory is required, ports 4, 5 and 6 are
available as general purpose I{O ports.
CPU Control Registers
Program Counter. The program counter is a 16-bit
binary counter register thi:lt holds the address of the
next instruction to be executed. During reset, the
program counter is loaded with the address stored in
locations OOOOH and 0001 H.
Stack Pointer. The stack pointer is a 16-bit register
that holds the address of the last item pushed onto the
stack. It is decremented before new data is pushed
onto the stack and incremented after data is popped
off the stack.
Program Status Word, The program status word
(PSW) is an 8-bit register that contains flags that are
set or reset depending on the results of an instruction.
This register can be written to or read from 8 bits at a
time. The individual flags can also be manipulated on a
bit-by-bit basis. The assignment of PSW bits follows.
7
I
IE
0
I
z
CY
ISP
RBSO, RBS1
AC
Z
IE
I RBS1 I
AC
I RBSO I
0
liSP
I
Cy
I
Carry flag
In-service (interrupt) priority flag
Register bank selection flags
Auxiliary carry flag
Zero flag
Interrupt request enable flag
General Registers
The general-purpose registers (figure 3) consist of four
banks of registers located at addresses FEEOH to
FEFFH in Internal RAM. Each bank consists of eight
8-bit general registers that can also be used in pairs to
function as four 16-bit registers. Two bits in the PSW
(RBSO and RBS1) specify which of the register banks is
active at any time and are set under program control.
Registers have both functional names (like A, X, B, C, D,
E, H or L for 8-bit registers and AX, Be, DE and HL for
16-bit registers) and absolute names (like R1, RO, R3,
R2, R5, R4, R7 or R6 for 8-bit registers and RPO, RP1,
RP2 or RP3 for 16-bit registers). Either the functional or
absolute register names can be used in instructions
that use the operand identifiers rand rp.
NEe
JlPD78014 Family
Figure 3. General Registers
FEEOH Register
Bank
3
For8-Blt
Processing
2
I
FEFFH
0
,
- - - -
FEFFH
FEF8H
For l6-Bft
Processing
------
(Rl)A
(RO) X
(RPO) AX
FEF8H
(R3)B
(R2)C
(RP1)BC
FEFAH
(RS)D
(R4)E
(RP2) DE
FEFCH
(R7) H
(R6)L
(RP3) HL
FEFEH
FEFEH
- - - --
) = Absolute Name
.3Y'.-I'6038
Addressing
The program memory addressing (ROM) modes provided are relative, immediate, table indirect and register addressing. The operand addressing modes provided are relative, immediate, table indirect and
register addressing. The operand addressing modes
provided are implied, register, direct, short direct
(saddr), special function (SFR), register indirect,
based, based indexed, and stack addressing.
The 'SFR addressing' and 'saddr addressing' modes
use direct addressing, and require only 1 byte in the
instruction to address RAM. Normally, a 65K byte address space requires 2 bytes to address it. One-byte
addressing results in faster access times, since the
instructions are shorter. SFR addressing addresses the
entire 256-byte SFR address space from FFOOH to
FFFFH. Saddr addressing (see figure 2) addresses the
256-byte address space FE20H to FF1 FH. FE20H to
FEFFH are composed of 224 bytes of internal high
speed RAM; FFOOH to FF1FH contain the first 32 bytes
in the special function register area.
One-byte addressing is accomplished by using the first
byte of the instruction for the opcode (and one operand if register A or AX is used) and the second byte of
the instruction as an address (offset) into the 256-byte
area. If register A or AX is used, the instructions are 2
bytes long, thereby providing fast access times. If
immediate data is used, the instruction will be 3 or 4
bytes long depending upon whether the immediate
data is a byte or a word. Many 16-bit SFRs are in the
space FFOOH to FF1FH. Using AX as an operand to
these SFRs will provide fast access, since the instructions will be only 2 bytes long.
Special Function Registers
The input/output ports, timers, capture and compare
registers, and mode and control registers for both the
peripherals and CPU are collectively known as special
function registers. They are all memory-mapped between FFOOH and FFFFH and can be accessed either
by main memory addressing or by SFR addressing.
FFOOH to FF1H can also be accessed using saddr
addressing. They are either a or 16 bits as required, and
many of the a-bit registers are bit addressable.
Locations FFDOH through FFDFH are known as the
external SFR area. Registers in external circuitry interfaced and mapped to these addresses can only be
addressed by main memory addressing. Table 1 lists
the special function registers.
Table 1. Special Function Registers
Access Units (Bits)
16
Address
Register (SFR)
Symbol
R/W
FFOOH
PortO
PO
R/W
x
x
OOH
8
State After Reset
FF01H
Port 1
Pl
R/W
x
x
OOH
FF02H
Port 2
P2
R/W
x
x
OOH
FF03H
Port 3
P3
R/W
x
x
OOH
FF04H
Port 4
P4
R/W
x
x
Undefined
FF05H
Port 5
P5
R/W
x
x
Undefined
FF06H
Port 6
P6
R/W
'x
x
Undefined
11
a:
i
NEe
pPD78014 Family
Table f. Special Function Registers (cont)
Access Units (Bits)
Address
Register (SFR)
Symbol
FF10H-FFllH
Compare register 00
CROO
FF12H-FF13H
Compare register 01
CROl
R
FF14H-FF15H
lS-bit timer register
TMO
R
FF1SH
Compare register 10
CR10
R/W
FF17H
Compare register 20
CR20
R/W
FF1SH
S-bit timer register 1
TMl
R
FF19H
S-bit timer register 2
TM2
R
FF1BH-FF19H
lS-bit timer register 1
TMS
R
R/W
1
8
R/W
FF1AH
Serial
VO shift register 0
SIOO
R/W
FF1BH
Serial
VO shift register 1
SIOl
R/W
FF1FH
NO conversion result register
ADCR
FF20H
Port mode register 0
PMO
R/W
FF21H
Port mode register 1
PMl
R/W
x
x
16
Stata After Reset
x
x
x
Undefined
x
x
x
x
R
FF22H
Port mode register 2
PM2
R/W
FF23H
Port mode register 3
PM3
R/W
FF25H
Port mode register 5
PM5
R/W
FF26H
Port mode register S
PMS
R/W
x
x
x
x
x
x
FF40H
Timer clock select register 0
TCLO
R/W
x
FF41H
Timer clock select register 1
TCLl
FF42H
Timer clock select register 2
TCL2
FF43H
Timer clock select register 3
FF47H
OOH
Undefined
Undefined
OOH
OOH
x
x
x
x
x
x
x
x
x
Undefined
OoaOH
Undefined
Undefined
Undefined
lFH
FFH
FFH
FFH
FFH
x
FFH
x
OOH
R/W
x
OOH
R/W
x
OOH
TCL3
R/W
x
68H
Sampling clock select register
SCS
R/W
x
OOH
FF4SH
lS-bit timer mode control register
TMCO
R/W
x
x
OOH
FF49H
S-bit timer mode control register
TMCl
R/W
x
x
OOH
FF4AH
Watch (clock) timer "mode control register
TMC2
R/W
x
x
OOH
FF4EH
lS-bit timer output control register
TOCO
R/W
x
x
OOH
FF4FH
S-bit timer output control register
TOCl
R/W
x
x
OOH
FFSOH
Serial operating mode register 0
CSIMO
R/W
x
x
OOH
FFS1H
Serial bus Interface control register
SBIC
R/W
x
x
OOH
FFS2H
Slave address register
SVA
R/W
FF63H
Interrupt timing specify register
SINT
R/W
x
Undefined
x
x
OOH
FFSSH
Serial operation mode register 1
CSIMl
R/W
x
x
OOH
FFS9H
Automatic data transmit/receive control register
ADTC
R/W
x
x
OOH
FFSAH
Automatic data transmit/receive address pointer
register
ADTP
R/W
x
OOH
FF60H
NO converter mode register
ADM
R/W
FFB4H
A/D converter input select register
ADIS
R/W
x
x
01H
x
OOH
FFDOH-FFDFH
External SFR access area(Note 1)
R/W
x
x
Undefined
FFEOH
Interrupt flag register L
IFOL
R/W
x
x
OOH
FFE1H
Interrupt flag register H
IFOH
R/W
x
x
OOH
12
NEe
Table t.
pPD78014 Family
Special Function Registers (cont)
Access Units (Bits)
8
16
State After Reset
x
OOOOH
Address
Register (SFR)
Symbol
R/W
FFEOH-FFEI H
Interrupt flag register
IFO
R/W
FFE4H
Interrupt mask flag register L
MKOL
RfIN
x
x
FFH
FFE5H
Interrupt mask flag register H
MKOH
RfIN
x
x
FFH
x
FFFFH
FFE4H-FFE5H
Interrrupt mask flag register
MKO
RfIN
FFE8H
Priority order specify flag register L
PROL
RfIN
x
x
FFE9H
Priority order specify flag register H
PROH
RfIN
x
x
FFE8H-FFE9H
Priority order specify flag register
PRO
RfIN
FFECH
External interrupt mode register
INTMO
RfIN
x
OOH
FFFOH
Memory size switch register (Note 2)
IMS
W
x
C8H
FFF6H
Key return mode register
KRM
RfIN
x
x
02H
FFF7H
Pullup resistor option register
PUO
RfIN
x
x
OOH
FFF8H
Memory expanded mode register
MM
RfIN
x
x
10H
FFF9H
Watchdog timer mode register
WDTM
RfIN
x
x
OOH
FFFAH
Oscillation stabilization time select register
OSTS
Rf\N
x
04H
FFFBH
Processor clock control register
PCC
RfIN
x
04H
FFH
FFH
x
x
FFFFH
1lI1~
Notes:
(1) The external access area cannot be accessed using SFR addressing. It can only be accessed using main memory addressing.
(2) JIPD78P014 only.
13
NEe
pPD78014 Family
Input/Output Ports
The pPD78014 family has up to 53 port lines. Table 2
lists the features of each port and figure 4 shows the
structure of each port pin.
Table 2. Digital Port Functions
Software Pull up Resistor Connection
(Note 1)
Port
Operational Features
Configuration
Port D (Note 2)
5-bit input or output
Bit selectable
Byte selectable, input bits only
Port 1
8-bit input or output
Bit selectable
Byte selectable, input bits only
Port 2
8-bit input or output
Bit selectable
Byte selectable, input bits only
Port 3
8-bit input or output
Bit selectable
Byte selectable, input bits only
Port 4
8-bit input or output
Byte selectable
Byte selectable, input bits only
Port 5
8-bit input or output
Bit selectable
LED
Byte selectable, input bits only
Port 6
8-bit input or output
(P6o - P63 n-channel)
Bit selectable
15 V max (P6o - P63)
Byte selectable, input bits only
P60 - P63 - mask option only (Note 3)
P64 - P67 - software
Notes:
(1) Software pullup resistors can be internally connected (only on a
port-by-port basis) to port bits set to input mode. Pullup resistors are not connected to port bits set to output mode.
(2) PDo and PD4 are input only and do not have a software pullup
resistor.
(3) All devices except J.1PD78PDI4
14
Direct Drive Capability
NEe
Figure 4.
pPD78014 Family
Pin Input/Output Circuits
~
"--tr---
Type 2 (POo. RESET)
IN
O>---------1(9a----c..~
pUIiUp enable
-------[>o~---I
Voo
data~
OUtputdlsabl.~
t-_>-+---{) IN/OUT
Schmitt t~gger Input with hysteresis characteristics
Type 9-B (P10 .P17)
pullup enable
-----------1[>o~---l
Voo
Input enable
-------[>0----1
data~
data~
OUtputdlsable~
pullup enable
t - _ - - - Q IN/OUT
outPutdlsable~
t-------<~-o IN/OUT
...L
-"'----9;---'
Type5-B(p40·P47)
VREF (Threshold Voltage)
Input enable - - - - - - - - '
pullup enable
-----------1[>o>-----l~~
data~
Outputdlsable~
t------ IN/OUT
Input enable - - - - - - - - '
83Yl-9344B (1)
15
NEe
pPD78014 Family
Figure 4. Pin Input/Output Circuits (cont)
Type 13-a (PIO' Pea: "PD7801x)
Vee
-.-
[Mask Option]
puftup enable -------11>><>-----1
ouIpUt~ -------;[)0--1
data ------<>--'),_---11 ~
t-_-4>--o
~
~
.---+--<> INfOUT
INfOUT
Nodi
Vee
opandl8ln
OUIput disable - - 4 - - - L /
Ri5----I~
Middle-High Voltage Input Buffer
Type 13 (Peo' Pe3: "PD78P014)
Middle-High Voltage Input Buffer
83YL-8344B (2)
16
NEe
JlPD78014 Family
Analog-to-Digital (AID) Converter
The pPD78014 family AID converter (see figure 5) uses
the successive-approximation method for converting
one of eight multiplexed analog inputs into 8-bit digital
data The conversion time per input is 19.1 ps at 8.38
MHz operation.
The AID converter input select register (ADIS) selects
the number of inputs that are used in AID conversion.
The remaining inputs are used as ports. The AID input
to be converted is selected by programming the AID
converter mode register (ADM). AID conversion is
started by external interrupt INTP3, or by writing to
ADM. When the conversion is completed, the results are
stored in the AID conversion result register (ADCR) and
an INTAD interrupt is generated.
If the AID converter was started by an external interrupt, the AID converter stops after the interrupt is
generated. If the AID converter was started by software, the AID converter repeats the conversion until
new data is written to the ADM register.
Figure 5. AID Converter
FlIlmADM
Resistor Strtng
----------1
ANIOIP10
ANI1/P11
Sample and
ANI2fP12
Hold Circuit
ANI3fP13
ANI4IP14
Input
Selector
(1)
,---1
:"-0
Input
Selector
(2)
1
ANI6IP1a
ANI71P17
INTP3IP03
1
1
I
I
I
I
I
f T A VREF
I
I
I
1
r---~~
1
ANI5fP15
1:
I Tap I
I Selector I
I
I
I
I
L ___ ..J
(note 1)
1
1
(note 2)
Conversion Trigger
II
1-----""""'»»011
I
II
I
I
I
I
1
I
I
I
I
I
I
I
I
I
I
LL
!
~~~~ _____ J
I
I
AVSS
I
--_» INTP3
L...
Trigger Enable
8
To Input Selector (2)
AID Conversion Result
Register (AOCR)
8
Internal Bus
NoIea:
(1) Selects number 01 port 1 Inputs to be used lor AID oonverslon.
(2) Selects tile channel for AID oonverslon.
83Yl.......
17
NEe
pPD78014 Family
Serial Interfaces
The pPD78014 family has two independent serial interfaces: serial interface 0 and serial interface 1.
Serial Interface O. Serial interface 0 is an 8-bit clock
synchronous serial interface (figure 6). It can be operated in either a three-wire serial I/O mode, NEC serial
bus interface (SSI) mode, or two-wire serial I/O mode.
The serial clock can be provided from one of eight
internal clocks, the output of 8-bit timer register 2, or
the external clock line SCKO.
In the three-wire serial I/O mode, the 8-bit shift register
(SIOO) is loaded with a byte of data and eight clock
pulses are generated. The falling edge of these eight
pulses shifts the byte of data out of the SOO line (either
MSS or LSB first) while the rising edge of these pulses
shifts the data in from the SIO line providing full-duplex
operation. The INTCSIO interrupt is generated after
each 8-bit transfer.
Figure 6. Serial Interface 0
SIOf
SBar
P25
SOOf
SB1f
0
0
P2a
From P26
Output Latch
IntemalBus
83YL-9348B
18
NEe:
IIPD78014 Family
The NEC SBI mode is a two-wire high-speed proprietary
serial interface available on most devices in the NEC
JlPD75XXX and JlPD78xxx product lines. Devices are
connected in a master/slave configuration (see figure
7). There is only one master device at a time; all others
are slaves. The master sends addresses, commands,
and data over one of the serial bus lines (SBO or SB1)
using a fixed hardware protocol synchronized with the
SCKO line . Each slave device of the JlPD78014 family
can be programmed to respond in hardware to any one
of 256 addresses set in its slave address register (SVA).
There are also 256 commands and 256 data types.
Since all commands are user definable, many software
protocols, simple or complex, can be defined. It is even
possible to develop commands to change a slave into a
master and the previous master into a slave.
Figure 7_ SBt Mode Master/Stare Configuration
DO
Slave cPU
MastarCPU
~
(881).SBO
SCK
Address 1
SCK
Slave cPU
I-~')I
AddraatI2
"""---"ISCK
~~
Slave IC
SBO,{SSl)
-
AddraISN
SCK
83YLofI347A (9193)
The two-wire serial I/O mode provides half-duplex operation using either the SBO or SB1 line and the SCKO
line. Communication format and handshaking can be
handled in software by controlling the output levels of
the data and clock lines between transfers. For data
transmission, the 8-bit shift register (SIOO) is loaded
with a byte of data and eight clock pulses are generated. The falling edge of these eight pulses shifts the
byte of data out of either the SBO or SB 1 Ii ne (MSB first).
In addition, this byte of data is also shifted back into
SIOO on the rising edge of these pulses providing a way
of verifying that the transmission was correct.
falling edge of the serial clock, it disables the n-channel
open-drain driver. This allows the receive data to be
driven on to the serial line and shifted into the SIOO
register on the rising edge of the serial clock. The
INTCSIO interrupt is generated after each 8-bit transfer.
Serial Interface 1. Serial interface 1 is also an 8-bit
clock synchronous serial interface (figure B). It can be
operated in either a three-wire serial I/O mode, or
three-wire- serial I/O mode with automatic transmit/
receive. The serial clock can also be provided from one
of eight internal clocks (common clock for both interfaces), the output of B-bit timer register 2, or the
external clock line SCK1.
--i
In the three-wire serial I/O mode, the B-bit shift register
(SI01) is loaded with a byte of data and eight clock
.
pulses are generated. The falling edge of these eight
pulses shifts the byte of data out of the S01 line (either . .
MSB or LSB first) while the rising edge of these pulses
shifts the data in from the SI1 line providing full-duplex
operation. The INTCSI1 interrupt is generated after
each B-bit transfer.
In the three-wire serial I/O mode with automatic
transmit/receive, up to 32 bytes of data can be transferred with minimal CPU overhead. The data to be
transmitted and received is stored in the buffer RAM.
Handshaking using either the BUSY input line, the
strobe (STB) output line, or both, can be selected by
the program. Error detection of bit drift due to noise is
available for each byte transferred when using the
BUSY input line. This automatic transmit/receive mode
is ideally suited for transferring data to/from external
peripheral devices such as onscreen display (OSO) and
LCD controller/driver devices.
While in three-wire serial interface mode with automatic data transfer, the interface can be operated as
either a full-duplex interface or a transmit-only interface in single or repetitive operation mode. In the fullduplex mode, a byte of data is transferred from the first
location in the buffer RAM and shifted out of the S01
line (either MSB or LSB first) while the received data is
shifted into the SI1 line and stored back in the first
buffer location. After the preset number of bytes has
been transferred, the INTCSI1 interrupt is generated.
In single-operation transmit mode, the preset number
of bytes from the buffer RAM are transmitted out of the
S01 line (either MSB or LSB first) and the INTCSI1
interrupt is generated after all bytes are transferred. In
the repetitive operation transmit mode, data in the
buffer is transmitted repeatedly.
For data reception, the SIOO register is preloaded with
the value FFH. As this data value is shifted out on the
19
NEe
IlPD78014 Family
Figure 8. Serial Interface 1
(CSIM1) --.---1
FromP21
OUIput Latch
~23 0~----4--------r""''''''-'
~-+--------------~
0)-----1------+\.......,..-'
BUSYfP24
t-+-----...-+---------!L..../----+-+-
INTCSI1
FromP22
Output Latch
..YL-.....
20
NEe
IIPD78014 Family
Timers
The pPD78014 family has one 16-bit timer/event
counter, two 8-bit timer/event counters that can be
combined for use as a 16-bit timer/event counter, a
clock timer, and a watchdog timer. All of these can be
programmed to count a number of prescaled values of
the main system clock. In addition, the clock timer can
also count the subsystem clock. All of the timer/event
counters can count external events.
16-Bit Timer/Event Counter O.
Timer/event counter
o (figure 9) consists of a 16-bit counter (TMO), a 16-bit
compare register (CROO), a 16-bit capture register
(CR01), and a timer output (TOO). Timer 0 can be used
as an interval timer, to count external events on the
timer input (TID) pin, to output a programmable square
wave, a 14-bit pulse width modulated output, or to
measure pulse widths.
Figure 9.
16-8il Timer/Evenl Counter 0
c,
Internal Bus
D
r-------~---~--------------~INTIMO
'XI2~
'xI4~
'xIS ~ Selector
TOOIP30
TIOfPOO'
INlPO
I-----------t----------+----+--+--------+ INTPO
16-Btt Capture Register
(CR01)
InlemalBus
21
NEe'
pPD78014 Family
a-Bit Timer/Event Counters 1 and 2. Timer/event
counters 1 and 2 (figure 10) each consist of an a-bit
timer (TM1 or TM2), an a-bit compare register (CR10 or
CR20) , and timer output control logic (T01 or T02). The
timers are controlled by registers TCL1, TMC1, and
TOC1 via five selectors. Timer/event counters 1 and 2
can each be used as an a-bit interval timer, to count
external events on the timer input pins (Tl1 orTI2), orto
output a programmable square wave. In addition, timers 1 and 2 also can be combined as a 16-bit timer/
event counter and used as a 16-bit interval timer, to
count external events on T11, or to output a programmable square wave on T02.
Figure 10. 8-Bit Timer/Event Counters 1 and 2
Internal Bus
------~--------------------~1~1
8·BII
T1merlEvenl
Counter 2
OUtpul
Conlrol LogIc
T02IP32
'X/4
'x18/18
'x'xl32
'x/84
/128
Clear
'x'xl258
'X1512
'X/1024
'x/4096
Selector
T12/P3t-
1------t----~T011P31
* Rising or faDing edge can be eelected.
22
NEe
Clock Timer 3. Clock timer 3 (figure 11) is a 5-bit timer
that can be used as a time source to keep track of time
of day, to release the STOP or HALT modes at regular
intervals, or to initiate any other task that must be
performed at regular intervals. When driven by the
subsystem clock, the clock timer continues to operate
in the STOP mode.
The clock timer can function as both an interval timer
and a clock timer simultaneously. When used as a clock
timer, interrupt request INlWr (not a vectored interrupts) can be generated using the main system or
subsystem clock every 0.5 or 0.25 seconds.when used
as an interval timer, vectored interrupt request INTTM3
is generated at preselected time intervals. With a main
system clock of 8.38 MHz or a subsystem clock of
32.768 kHz, the following time intervals can be selected: 489 Jis, 978 Jis, 1.96 ms, 3.91 ms, 7.82 ms or 15.6
ms.
pPD78014 Family
Watchdog Timer. The watchdog timer (figure 12) can
be used as either a watchdog timer or an interval timer.'
When used as a watchdog timer, it protects against
inadvertent program run-away. It can be selected to
generate a nonmaskable interrupt (INTW01), which
vectors to address 0004H, or to generate an internal
reset signal, which vectors to the restart address OOOOH
if the timer is not cleared by the program before it
overflows. Eight program-selectable intervals based
on the main system clock are available. With a main
system clock of 8.38 MHz, the program selectable
intervals are 0.489, 0.978,1.96, 3.91, 7.82,15.6, 31.3, and
125 ms. Once the watchdog timer is initialized and
started, the timer's mode cannot be changed and the
timer can only be stopped by an external reset.
When used as an interval timer, maskable interrupts . '
(I NTWD1) , which vector to address 0004H, are gener,r
ated repeatedly at a preset interval. The time intervals
available are the same as in the watchdog timer mode.
23
NEe
I'PD78014 Family
Figure ft.
Clock Timer 3
.----Selector
'w129
'w12 8
.-----
x128 _
'XT-
Selector
1
'--,--
Praacaler
Selector _IN lWT
-r--
Claar
Selactor
'w12B5
INTTM3
'wf24
+
11mar Clock Select
Register 2 (TCl2)
I
I
I
I
I
CIockllmarModa
Control
Register (TlIIC2)
)
Figure 12.
-
'w12
'--r--
)
llmer
I 'w1213
'w12 7
'w
jClesr
I
H
'w1214
5-Bft
InlemalBus
t
I
<,
Watchdog Timer
Run
INlWOT
Maskable
Interrupt
Request
I-A.:'---,l~
Selector
8·BIt
Counter
Control
logic
Praacaler I-A.:':--cl~
1-----------+--- RESET
INlWOT
Nonmaskable
Interrupt
Request
IntemalBus
83Yl-9362B (8193)
24
NEe
pPD78014 Family
Programmable Clock Output
Buzzer Output
The J.lPD78014 family has a programmable clock output
(PCl) that can be used for carrier output for remote
controlled transmissions or as a clock output for peripheral devices. The main system clock (fx) divided by
8, 16, 32, 64, 128, or 256 or the subsystem clock (fXT)
can be output on the pcl pi n. Frequencies of 1050, 524,
262, 131, 65.5 and 32.7 kHz are available with a main
system clock of 8.38 MHz. See figure 13.
The J.lPD78014 family also has a programmable buzzer
output (BUZ). The buzzer output frequency can be
programmed to be equal to the main system clock (fx)
divided by 1024, 2048, or 4096. With a main system
clock of 8.38 MHz, the buzzer can be set to 8.2, 4.1 or 2.0
kHz. See figure 14.
Figure 13. Programmable Clock Output
fXI23---~
•
fxI24---~
fXI25---~
f X126 ---~ Selector
fx/27---~
fxI28--~~
fXT---~
Figure 14. Buzzer Output
'X/2 10 -----c~
'X/211 --~~ Selector
1----------'\---.....>-____-1
'X1212 -----c~
83Yl.......
25
I
NEe
pPD78014 Family
Interrupts
The pPD78014 family has 14 maskable hardware interrupt sources (5 external and 9 internal). Of these 14
interrupt sources, 12 cause a vectored interrupt while
the 2 testable inputs only generate an interrupt request. All of the 14 maskable interrupts can be used to
release the HALT mode except INTPO. INTPO cannot be
used to release the STOP mode and cannot release the
HALT mode when register SCS = O. In addition, there is
one nonmaskable interrupt from the watchdog timer,
one software interrupt, and a reset interrupt. The
watchdog timer overflow interrupt (interrupt vector
table address 0004H) can be initialized to be a nonmaskable interrupt orthe highest default priority maskable interrupt. The software interrupt, generated by the
BRK instruction, is not maskable. See table 3 and figure
15.
Table 3_ Interrupt Sources and Vector Addresses
Type of
Request
Default
Priority
Restart
Vector
Interrupt
Address Configuration
OOOOH
RESET input pin
External
Watchdog timer overflow
(when reset mode selected)
Internal
INTWDT
Watchdog timer overflow
(when nonmaskable interrupt selected)
Internal
0OO4H
A
0
INTWDT
Watchdog timer overflow
(when interval timer selected)
Internal
0OO4H
B
INTPO
External interrupt edge detection
External
OOOSH
C
2
INTPI
External interrupt edge detection
External
OOOSH
D
3
INTP2
External interrupt edge detection
External
OOOAH
D
4
INTP3
External interrupt edge detection
External
OOOCH
D
5
INTCSIO
End of clocked serial interface 0 transfer
Internal
OOOEH
B
S
INTCSII
End of clocked serial interface 1 transfer
Internal
0010H
B
7
INTTM3
Clock timer reference time interval signal
Internal
0012H
B
B
INTTMO
IS-bit timer/event counter coincidence signal
Internal
0014H
B
9
INTTMI
B-bit timer/event counter 1 coincidence signal
Internal
001SH
B
10
INTTM2
S-bit timer/event counter 2 coincidence signal
Internal
001SH
B
11
INTAD
End of A/D Conversion
Internal
001AH
B
BRK instruction
Internal
003EH
E
INTWT
Clock timer overflow
Internal
F
INTPT4
Port 4 falling edge detection
External
F
Interrupt Servicing. The pPD78014 family provides
two levels of programmable hardware priority control
and services all interrupt requests, except the two
testable interrupts (INTWT and INTPT4) using vectored
interrupts. The programmer can choose the priority of
servicing each maskable interrupt by using the interrupt control registers.
Interrupt Control Registers. The pPD78014 family
has three 16-bit interrupt control registers. The interrupt request flag register (IFO) contains an interrupt
request flag for each interrupt except IN TPT4. The
interrupt mask register (MKO) is used to enable or
disable any interrupt except INTPT4. The priority flag
26
Location
RESET
Software
Test input
Interupt Source
INTWDT
Nonmaskable
Maskable
Signal Name
register (PRO) can be used to specify a high or a low
priority level for each interrupt except the two testable
interrupts.
Four other 8-bit registers are associated with interrupt
processing. The key return mode register (KRM) contains the KRIF interrupt request flag associated with
falling-edge detection on port 4 and the KRMK mask
flag used to enable or disable clearing of the standby
mode if a falling edge is detected on port 4. The
external interrupt mode register (INTMO) is used to
select a rising, falling, or both edges as the valid edge
for each of the external interrupts INTPO to INTP2
(INTP3 is always falling edge). The sampling clock
NEe
IIPD78014 Family
select register (SCS) is used to select a sampling clock
for the noise eliminator circuit on external interrupt
INTPO.
The IE and the ISP bit of the program status word are
also used to control interrupts. If the IE bit is 0, all
maskable interrupts are disabled. The IE bit can be set
or cleared using the EI and 01 instructions, respectively, or by directly writing to the PSw. The IE bit is
cleared each time an interrupt is accepted. The ISP bit
is used by hardware to hold the priority level flag of the
interrupt being serviced.
Figure 15_ Interrupt Configurations
Type A: Internal nonmaskable Interrupt
Interrupt _ _-+-_ _ _~
Request
Standby
' - - - - - - - - - - - - - Release
SIgnal
Type B: Internal maskable Interrupt
Vector Table
Address Generator
L - -_ _ _ _ _ _. . .
:=
Signal
Type C: External maskable Interrupt (INTPO)
'-------------;~
Stendby
Release
Signal
83YIAI06&8 (1)
27
IIPD78014· Family
Figure 16. Inte"upt Configurations (cont)
Type D: External maakablelnterrupt (except INTPO)
Vector Table
Address Generator
Interrupt _ _ _ _~
Request
'-------------i~
Standby
Release
Signal
Type E: Softwerelnterrupt
Interrupt _ _ _ _ _ _....
Request
Type F: Test Input
I---~:=~
Signal
'---L_
Abbreviations:
IF: Interrupt request flag
IE: Interrupl-'lle flag
ISP: In-eervlce p~orlty ftag
MK: Interrupt mask fleg
PRo Poorlty specify fleg
83Yt-913668(2)
28
NEe
Interrupt Priority. If the watchdog timer overflow
interrupt (INlWDl) has been initialized to be a nonmaskable interrupt, it has priority over all other interrupts. Two hardware-controlled priority levels are available for all maskable interrupts that generate a
vectored interrupt (i.e., all except the two testable
interrupts). Either a high or a low priority level can be
assigned by software to each of the maskable interrupts. Interrupt requests of the same priority or a
priority higher than the processor's current priority
level are held pending until interrupts in the current
service routine are enabled by software or until one
instruction has been executed after returning from the
current service routine. Interrupt requests of a lower
priority are always held pending until one instruction
has been executed after returning from the current
service routine.
The default priorities listed in table 3 are fixed by
hardware and are effective only when it is necessary to
choose between two interrupt requests of the same
software-assigned priority. For example, the default
priorities would be used after the completion of a
high-priority routine, if two interrupts of the same
software priority were pending.
The software interrupt, initiated by the BRK instruction, is executed regardless of the processor's priority
level and the state of the IE bit. It does not alter the
processor's priority level.
Vectored Interrupt Servicing. When a vectored interrupt is acknowledged, the program status word and
the program counter are saved on the stack, the processor's priority is set to that specified for the interrupt,
the IE bit in the PSW is set to zero, and the routine
whose address is in the interrupt vector table is entered. At the completion of the service routine, the RETI
instruction (RETB instruction for the software interrupt) reverses the process and the pPD78014 family
microcontroller resumes the interrupted routine.
pPD78014 Family
INTPO if register SCS = 0), a nonmaskable interrupt
request, an unmasked test input, or an external reset
pulse.
Power consumption may be further reduced by using
the STOP mode. The STOP mode is entered by executing a STOP instruction while operating from the main
system clock. In STOP mode, the main system clock
input pin X1 is internally grounded stopping both the
CPU and the peripheral hardware clock. The STOP
mode is released by any unmasked interrupt request
except INTPO, a nonmaskable interrupt request, an
unmasked test input, or an external reset pulse. Any
peripheral using the main oscillator as a clock source
will also be disabled in the STOP mode and interrupts
from such a peripheral cannot be used to exit the STOP
mode. Table 4 summarizes both the HALT and STOP
standby modes.
Table 4_
Standby Mode Operation Status
Item
HALT Mode
STOP Mode
Setting instruction
HALT instruction
STOP instruction
System clock when Main system or
setting
subsystem clock
Main system clock
Clock oscillator
Subsystem clock can
oscillate; CPU clock
and main system
clock are stopped.
CPU
Operation stopped
Operation stopped
Ports
Maintain previous
state
Maintain previous
state
16·bit timer/event
counter
Operational from main Operation stopped
system clock
B·bit timer/event
counters
Operational from main Operational only with
system clock
Til and TI2 as count
clock
Clock timer
Operational from main Operational only with
system clock ?nd with fXT as count clock
fXT as count clock
Watchdog timer
Operational from main Operation stopped
system clock
Serial interface 0
Operational from main Operational only with
system clock
external clock
Serial interface 1
Operational from main
system clock; no
automatic transmit!
receive mode
A/D converter
Operational from main Operation stopped
system clock
Standby Modes
HALT, STOP, and data retention modes are provided to
reduce power consumption when CPU action is not
required.
The HALT mode is entered by executing a HALT instruction while the CPU is operating from the main
system or subsystem clock. In HALT mode, the CPU
clock is stopped while the main system and the subsystem clock continue to run. The HALT mode is released by any unmasked interrupt request (except
Main system and
subsystem clocks can
oscillate; CPU clock is
stopped.
Operational only with
external clock; no
automatic transmit!
receive mode
External interrupts Operational except for INTPO not operational;
INTPO when its
INTPl to INTP3
operational
sampling clock is
based on the CPU
clock
29
NEe
IIPD78014 Family
When exiti ng the STOP mode, a wait time occurs before
the CPU begins execution to allow the main system
clock oscillator circuit to stabilize. The oscillator stabilization time is selected by programming the OSTS
register with, one of five values before' entering the
STOP mode. The values range from 0.98 msec to 31.3
msec atfx = 8.3S'MHz. Once in the STOP mode, power
consumption can be further minimized by lowering the
power supply voltage VDD to 2 V. This places the device
in the data retention mode. The coritents of internal
RAM and the registers are retained. This mode is
released by first raising VDD to the proper operating
range and then releasing the STOP mode.
External Reset
I
!
The pPD78014 family is reset by taking the RESET pin
low or by an overflow of the watchdog timer (if enabled). The RESET input pin is a schmitt-trigger input
with hysteresis characteristics to protect against spurious system resets caused by noise. On power-up, the
RESET pin must remain low for aminimum of 10ps after
the power supply reaches its operating voltage.
There is no functional difference between an external
reset and an internal reset caused by the overflow of
the watchdog timer. In both cases, the main system
clock oscillation is stopped and the subsystem clock
oscillation continues. During reset, the program
counter is loaded with the address contained in the
reset vector (addresses OOooH, 0001 H). Once the reset
is cleared and the oscillation stabilization time of 2 18/fx
has elapsed, program execution starts at that address.
ELECTRICAL SPECIFICATIONS
Absolute Maximum
R~tings
TA = +25°0
Supply voltage, VOO
-0.3 to +7.0 V
Supply voltage, Vpp
-0.3 to +13.5 V
Supply voltage, AVOO
-0.3 to VOO+ 0.3 V
Supply voltage, AVREF
-0.3 to Voo+ 0.3 V
Supply voltage, AV ss
-0.3 to + 0.3 V
Input voltage, Vll (except P60 to P6a)
-0.3 to VOO+ 0.3 V
Input voltage, VI2 (P60 to P6a; open
drain)
-0.3 to +16 V
Output voltage, Vo
-0.3 to Voo+ 0.3 V
!\.nalog, input voltage, VAN
(port 1; analog Input pin)
AVss -0.3 to AVREF+ 0.3 V
Output current, high; IOH
Each output pin
Total: ports 2 and 3
Total: port 0 and ports 4 to 6
-10 mA
-15 mA
-15 mA
Output current, low, IOL t
Each output pin
Total: P40 to P47 and
, P50 to P5 5
Total: POl to POa, P5s, P57, and P60
to P67
Total: POl ,to POa and P64 to per
Total: ports 2 and 3
30 mA peak, 15 mA, rms
100 mA peak,70 mA rms
100 mA peak, 70 mA rms
50 mA peak, 20 mA rms
50 mA peak, 20 mA rms
Operating temperature, TOPT
-40 to +85°0
Storage temperature, TSTG
-65 to +150°0
t rms value = peak value x (duty cycle) 1/2
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent damage. The device should be operated within the limits
specified under DO and AO characteristics.
Capacitance
TA = +25°0; Voo = VSS = 0 V
Parameter
Symbol Max Unit Conditions
Input
capacitance
°IN
Output
°OUT
capacitance,
Input/output 010
capacl tance
30
15
pF
Except P60
to P6a
20
pF
15
pI'
P60 to P6a
Except P60
to P63
20
pF
P60 to P6a
15
pF
Except P60
to P63
20
pF
P60 to P6a
= 1 MHz;
unmeasured
pins returned
to ground
f
NEe
I'PD78014 Family
Main System Clock Oscillator
TA = -40 to +8S·C; Voo = 2.7 to 6.0 V; refer to figure 16.
Type
Parameter
Symbol Min
Typ
Max Unit ConditIons
Ceramic resonator Oscillation frequency (Note 1)
fX
(Figure 16A)
Oscillation stabilization time (Note 2)
1.0
Crystal resonator
(Figure 16A)
Oscillation frequency (Note 1)
1.0
External clock
(Figure 168)
Xl input frequency (Note 1)
fX
1.0
10.0 MHz
Xl input high/low-level width
txH, txL
SO
SOO
10.0 MHz Voo = oscillator voltage range
4.0
tx
8.38
ms
After Voo reaches oscillator operating voltage
10.0 MHz
Oscillation stabilization time (Note 2) _ _ _ _ _ _ _ _ _1_0__m_s_V""o::.:o"-=_4_.S_t_o_6_._0_V_ _ _ _ _ _ _ _ __
30
Notes:
(1) Oscilletor and Xl inputfrequencies are included only to show the
oscillator characteristics. Refer to the AC Characteristics table
for actual instruction execution times.
ms
ns
(2) Time required for the oscillator to stabilize after reset or STOP
mode is released. The values shown are for the recommended
resonators. Values for resonators not shown in this data sheet
should be obtained from the manufacturer's specification sheets.
Subsystem Clock Oscillator
TA = -40 to +8S·C; Voo = 2.7 to 6.0 V; refer to figure 17.
Type
Parameter
Symbol
Crystal resonator
(Figure 17A)
Oscillation frequency (Note 1)
txT
External clock
(Figure 178)
Min
Typ
Max
Unit
32
32.768
3S
kHz
Oscillation stabilization time (Note 2)
1.2
2
s
10
s
XTI input frequency (Note 1)
fXT
32
100
kHz
XTl input high/low-level width
txTH, txTL
S
15
J1s
Notes:
(1) The oscillator and XTl input frequencies are included only to
show the oscillator characteristics. Refer to the AC Characteristics table for actual instruction execution times.
Conditions
Voo = 4.S to 6.0 V
(2) Time required for the oscillator to stabilize after reset or STOP
mode is released. The values shown are for the recommended
resonators. Values for resonators not shown in this data sheet
should be obtained from the manufacturer's specification sheets.
31
NEe
-I'PD78014 Family
Figure 16. Main System Clock Configurations
Figure 17. Subsystem Clock Configurations
A.- Crystal Resonator
A. CeramlclCrystal Resonator
.----.---1 X1
C3~
,,01
T
C4,
XT1
XT2
R2
R1
B. External Clock
B. External Clock
1>>--1'~--I X1
~PD74HCU04
X2
Note: When the Input Is an extemal clock. the STOP
mode can not be set because the X1 pin Is connected
to system ground (VSS)'
32
1
-{>
q~
I
83YL-9367A
NEe
pPD78014 Family
Recommended Main System Clock Ceramic Resonators
TA = -40 to +85'C, refer to figure 16a
·Recommended Circuit Constant
Oscillator Voltage Range
C1 (pF)
C2 (pF)
R1 (kll)
Min (V)
Max (V)
Frequency
(MHz)
CSB1000J
100
100
6.8
2.7 (Note 3)
2.8 (Note 4)
6.0
1.00
CSBxxxxJ
toO
100
4.7
2.7 (Note 3)
2.8 (Note 4)
6.0
1.01 to 1.25
CSAx.xxxMK
100
100
0
2.7 (Note 3)
2.8 (Note 4)
6.0
1.26 to 1.79
100
100
(NoteS)
o (Note 5)
100
100
(Note 5)
o (Note 5)
0
0
0
0
2.7
2.7
2.7
2.7
6.0
6.0
6.0
6.0
1.8 to 2.44
30
(NoteS)
30
(Note 5)
0
0
2.7
2.7
6.0
6.0
2.45 to 4.18
30
30
(NoteS)
o (Note 5)
30
30
(Note 5)
o (Note 5)
0
0
0
0
2.7
2.7
2.7
2.7
6.0
6.0
6.0
6.0
4.19 to 6.00 •
30
30
0
2.7 (Note 3)
3.0 (Note 4)
6.0
6.01 to 10.0
(NoteS)
(NoteS)
0
2.7 (Note 3)
3.0 (Note 4)
6.0
Part Number
(Notes 1 and 2)
CSAx.xxMG (Note 3)
CSAx.xxMG093( Note 4)
CSTx.xxMG (Note 3)
CSTx.xxMG093 (Note 4)
CSAx.xxMG
CSTx.xxMGW
CSAx.xxMG (Note 3)
CSAx.xxMGU( Note 4)
CSTx.xxMGW (Note 3)
CSTx.xxMGWU (Note 4)
CSAx.xxMT
CSTx.xxMTW
Notes:
(1) Manufactured by Murata Mfg. Co., Ltd.
(4) JlP078P014 only
(2) x.xx indicates frequency
(5) C1 and C2 are contained in the ceramic resonators.
(3) JlP07801x only
Recommended Subsystem Clock Crystal Resonators (/LPD7801x)
TA = -40 to +60'C , refer to figure 17a
Part Number
t
OT-38 (1TA252 EOO, load capacitance 6.3 pF)
Recommended Circuit Constant
Oscillator Voltage Range
Frequency
(kHz)
C3 (pF)
C4 (pF)
R2 (kll)
Min (V)
Max (V)
32.768
12
12
100
2.7
6.0
t Manufactured by Oaishinku
DC Characteristics
TA = -40 to +85'C; Voo = +2.7 to 6.0 V; refer to figures 18-23
Parameter
High-level input voltage
Symbol
Max
Unit
VIH1
0.7 VOO
Min
VOO
V
Other than below
VIH2
0.8 VOO
VOO
V
POO to P04, P20, P22, P24 to P27,
P33, P34, RESET
VIH3
0.7V OO
15
V
P60 to P63; open-drain
VIH4
Voo-0.5
VOO
V
X1,X2
VIH5
Voo-0.5
Voo
V
Voo = 4.5 to 6.0V; XT1, XT2
Voo-0.3
VOO
V
JlP07801x; XT1, XT2
VOO-0.2
VOO
V
JlP078P014
Typ
Conditions
33
NEe
"PD78014 Family
DC Characteristics (cont)
Symbol
Low-level input voltage
Vll1
0
0.3VOO
V
Other than below
VIL2
0
0.2VOO
V
POQto P04, P2Q, P22' P24 to P27'
P33, P34, RESET
0
0.3VOO
V
P60 to P63; V 00
0
0.2VOO
V
P60 to P63
VIL3
High-level output voltage
Low-level output voltage
Min
Mal(
Parameter
Typ
Low-level input leakage
current
Conditions
= 4.5 to 6.0 V
VIl4
0
0.4
V
X1,X2
VIl5
0
0.4
V
XT1, XT2; V00
0
0.3
V
XT1, XT2
VOO -1.0
V
VOO
VOO- 0.5
V
IOH
2.0
V
P50 to P57, P60 to P63;
VOO = 4.5 to 6.0 V, IOl
0.4
V
Other than above; VOO
IOl = 1.6 mA
V
SBO, SB1, SCKO; Voo = 4.5 to 6.0 V,
open-drain, pullup resistance = 1 kO
VOHl
0.4
VOl1
0.2VOO
VOl2
High-level input leakage
current
Unit
VOl3
0.5
V
IUHl
3
JiA
IUH2
20
JiA
IUH3
80
JiA
= 4.5 to 6.0 V
= 4.5 to 6.0 V, IOH = -1.0 mA
= -100 JiA
= 15mA
= 4.5 to 6.0 V,
= 400JiA
= Voo; except Xl, X2, XT1, XT2
VIN = Voo; X1, X2, XT1, XT2
VIN = 15 V; P60 to P63
VIN = 0 V; except Xl, X2, XT1, XT2
VIN = OV; X1, X2, XT1, XT2
VIN = 0 V; P60 to P63 (Note 1)
VOUT = Voo
VOUT = OV
VIN = 0 V; P60 TO P63, JiPD7801x only
VOO = 4.5 to 6.0V; VIN = OV, POl to P03,
Iol
VIN
lUll
-3
JiA
IUL2
-20
JiA
Illl3
-3
JiA
Output leakage current high
IlOHl
3
JiA
Output leakage current low
IlOl
-3
JiA
Mask option pullup resistor
Rl
20
40
90
kO
Software pullup resistor
R2
15
40
90
kO
500
kO
Voo = = 2.7 to 4.5 V; VIN
ports 1 to 5, P64 to P6l
7.5
22.5
mA
8.38 MHz crystal oscillation operating mode;
VOO = 5.0 V ±10% (Note 2)
0.8
2.4
mA
8.38 MHz crystal oscillation operating mode;
Voo = 3.0V ±10% (Note 3)
1.4
4.2
mA
8.38 MHz crystal oscillation HALT mode;
Voo = 5.0V ±10%
550
1650
JiA
8.38 MHz crystal oscillation HALT mode;
Voo = 3.0 V ±10%
60
120
JiA
32.768 kHz crystal oscillation operating mode;
Voo = 5.0 V ±10%, X1 STOP mode, CPU
operating from sUbsystem clock
35
70
JiA
32.768 kHz crystal oscillation operating mode;
Voo = 3.0 V ±10%, Xl STOP mode, CPU
operating from subsystem clock
ports 1 to 5, P64 to P67
20
Power supply current
I}.JPD7801x)
1001
1002
10D3
34
= 0 V, POl to P03,
NEe
pPD78014 Family
DC Characteristics (cant)
Parameter
Symbol
Power supply current
(J1PD7801 x) (cont)
1004
Min
Typ
Max
Unit
Conditions
25
50
J1A
32.768 kHz crystal oscillation HALT mode;
Voo = 5.0 V ±10%, X1 STOP mode
5
10
J1A
32.768 kHz crystal oscillation HALT mode;
VOO = 3.0V ±10%, X1 STOP mode
20
J1A
XT1 = 0 V STOP mode when feedback resistor
Is connected; VOO = 5.0 V ±10%
0.5
10
J1A
XT1 = 0 V STOP mode when feedback resistor
is connected; Voo = 3.0V ±10%
0.1
20
J1A
XT1 = 0 V STOP mode when feedback resistor
is disconnected; VOO = 5.0 V ±10%
0.05
10
J1A
XT1 = 0 V STOP mode when feedback resistor
is disconnected; Voo = 3.0 V ±10%
9
27
mA
8.38 MHz crystal oscillation operating mode;
VOO = 5.0V ±10% (Note 2)
3
mA
8.38 MHz crystal oscillation operating mode;
Voo = 3.0V ±10% (Note 3)
1.4
4.2
mA
8.38 MHz crystal oscillation HALT mode; Voo =
5.0V ±10%
550
1650
J1A
8.38 MHz crystal oscillation HALT mode; Voo =
3.0V ±10%
90
180
pA
32.768 kHz crystal oscillation operating mode;
Voo = 5.0V ±10%, X1 STOP mode, CPU
operating from subsystem clock
50
100
pA
32.768 kHz crystal oscillation operating mode;
Voo = 3.0 V ±10%, X1 STOP mode, CPU
operating from subsystem clock
25
50
pA
32.768 kHz crystal oscillation HALT mode;
Voo = 5.0V ±10%, X1 STOP mode
5
10
pA
32.768 kHz crystal oscillation HALT mode;
Voo = 3.0V ±10%, X1 STOP mode
30
pA
XT1 = 0 V STOP mode when feedback resistor
is connected; Voo = 5.0 V ±10%
0.5
10
pA
XT1 = 0 V STOP mode when feedback resistor
is connected; Voo = 3.0 V ±10%
0.1
30
pA
XT1 = 0 V STOP mode when feedback resistor
is disconnected; Voo = 5.0 V ±10%
0.05
10
pA
XT1 = 0 V STOP mode when feedback resistor
is disconnectec;i; Voo = 3.0 V ±10%
1005
1000
Power supply current
(J1PD78P014)
1001
1002
1003
1004
1005
1000
Notes:
(1) P6a to P63 become -200 pA (max.) for only 1 clock cycle during
input instruction execution (no wait) and -3 pA (max.) during
instruction other than input.
(2) When operated in the high-speed mode with the processor clock
control register set to OOH.
(3) When operated in low-speed mode with the processor clock
control register set to 04H.
35
NEe
JlPD78014 Family
Figure 18. 'DO lIS Voo (pPD7801xj
PCC =OOH (tCY""48)ts)"
10.0
V
g
PCC = 03H Cv=3.81I's)"
.........: PCC=02H
~~
~
TA=25°C; Ix=8.38 MHz;-
IxT = 32.768 kHz
~
j
,o.os
0.1
1--1003
1001
J
0.5 ==1 1002
1
V
./
1
PCC= BOH (Icv=1221'8)"'
(X1 STOp)
HALT (X1 STOP)
....
.... ~
1.0
i
a
I
PCC = BOH (ICY = 1221'S)"
(X1Sl1OP)
_
0.1
lo.os
L
r-- 1DD3'"
2
0.005
" CPU ClOCk lrom main system clock.
"j CPU 910ck lroj su,stam dr"
3
4
5
8
7
1
HALT (Xl STOP)
V
/"
/
0.01
o
/'V
TA = 25'C ; fX= 8.38 MHz ;
fXT = 32.788 kHz
1--1004'
I
PCC=03H(tCy--3.811'S)·
PCC=04H(ICy=7.83I'S)·
................:: ~ HALT
0.5 ==1002
I
0.005
0.001
L
PCC=02H(ICy=1.911'S)·
....
~
V
0.01
,.
PCC=04Hg cv=7.83!'8)"
PCC=30H t cv=122I'S)"
HALT
, ~ q;; ~
1.0
I
5.0
cv=1.911'8)"
- 1 0 ,1
~
PCC = OOH (tev=-48)ts).
PCC=OlH(ICy=.95I'S)·
10.0
PCC.01H (tC'f"'o95I'8)"
5.0
~
Figure 19. 'DO lIS VOO (pPD78POI4)
/
L
V
STOP (XT1 osclllaUon)
and reset
~1004
L
,
cr
• CPU Clock from main system clock. _
k froj SUbSystm CIOCi'
CPU
i
8
Power Supply Voltage V DO M
0.001 0
2
3
4
5
8
Power Supply Voltage V DO M
36
7
8
NEe
Figure 20.
pPD78014 Family
IOL VS VOL (Ports 0, 2-5, P6~P67)
301-----=~r+.,==---
Figure 22.
IOL VS VOL (P6rrP6:J
____-_t_----___j
iil
!~I---~~~.4-----_t_----___j
<5
S
-101--~~---+-----_t_----___j
~----~----~----~I
1.0
0.5
VOL (V)
Figure2t.
VOL (V)
Figure 23.
IOL VS VOL (Port t)
IOH VS Voo - VOH (Ports 0-5, P6~P6n
i ~ I-------~~.L--:;;o...-::..-__j_----_I
I
9
101-----7.~L--t-----__j_----_I
1.0
0.5
VOL (V)
1.0
voo-voHM
37
NEe
pPD78014 Family
AC Characteristics
TA = -40 to +85'C; Voo = 2.7 to 6 V ; refer to figures 24 through 30
Parameter
Symbol
Min
Max
Unit
Cycle time
(Min. instruction
ex.ecution time)
tCY
0.4
64
JiS
0.96
64
Jis
Operating on main system clock (JlP07801x)
0.48
64
JiS
VOO = 4.5 to 6.0V; operating on main system
clock (JlP078P014)
1.91
64
JiS
Operating on main system clock (JlP078P014)
0.4
64
Jis
TA = -40 to +40'C, Voo = 4.75 to 6.0 V;
operating on main system clock (JlP078POI4)
0.96
64
JlS
TA = -40 to +40'C; operating on main system
clock (JlP078POI4)
114
TI input
frequency
fori
Typ
125
Jis
0
122
4
MHz
0
275
kHz
Conditions
VOO = 4.5 to 6.0 V; operating on main system
clock (JlP 07801 x)
Operating on subsystem clock
VOO
= 4.5t06.0V
Voo
= 4.5 to 6.0 V
TI input high/
low-level width
100
ns
1.8
JiS
Interrupt input
high/low-level
width -
8/fsam (Note 1)
Jis
INTPO
10
JiS
INTPI to INTP3
10
Jis
KRO to KR7 (Note 2)
10
Jis
RESET low-level width
Notes:
(1) By usin9 bits 0 and 1 ofthe sampling clock select (SCS) register
in conjunotion with bits 0 to 2 of the processor clock control
(PCC) register, f5am can be set to fx/2N+ 1 (where N = 0 to 4),
fx/64, or fx/128.
(2) Port 4 falling-edge detection input.
38
NEe
IIPD78014 Family
Figure 24. Main System Clock Operation tcy
VB
Figure 25. Main System Clock Operation tcy
Voo (pPD7B01X)
=1Ilriir
t'
'~
,,:-
3.0
VB
Voo (pPD7BP014)
I I1
=1 I I II Ir I I 1
,
:-
GUaJteed
Operating
Range
,
3.0
GuaJteed
OperaUng
Range
-;;- 2.0
~
,\
~
S-JI
I
(TA=-40to45'C)
I\
1.0
--
\
\
0.5
\
\.
\\
\
~
,
,
,
,
,
l~~r__~r__~r__~r__r~_rL-~~
M
23456
Supply Voltage V DO M
\.
0.5
\.
1\
~\
,
oi'-__r'----'r__-'-r__. . Lr__-'-r__
1
234
I:5
.- -
\.
0.4
5
...L..r--Jr~
,
6
Supply Voltage VDO M
Note:
When TA = -40 to +4O"C, guaranteed operaUng range
Is extended to the dotted lIne.
39
NEe
pPD78014 Family
Figure 26. AC Timing Measurements Points
(except Xtand XTt)
,
=x
Figure 29. InterruptlnputTiming
VooooC
0.8VOo-Measurament .... 0.8V
0.2 "DO""
Points
..... 0.2
Figure 27. Clock AC Timing Points X111nd XTt
83CL-93B9A
Figure 30. RESET Input Timing
X11nput
0.4 V
83CL-937M
XT1lnput
Figure 28.
40
0.4 V
71 Timing
NEe
pPD78014 Family
Read/Write Operation
= -40 to +85·C, VOO = 2.7 to 6.0V; refertofigures3t
TA
Parameter
ASTB high-level width
Address setup time to ASTB ~
Address hold time from ASTB
~
Data input time from address
Min
tASTH
0.5tCY
ns
tAOS
0.5tCy-30
ns
tAOH
to
~
Max
(2+ 2n)lcy - SO
tADOl
tAOO2
Data input time from RD
through 34
Symbol
S
tROOl
tROO2
Unit
Conditions
ns
Load resistor", 5 kQ
ns
Instruction fetch
(3+2n)tCy-tOO
ns
Data access
(1+ 2n)tCY - 25
ns
Instruction fetch
(2.S+2n)tev -tOO
ns
Data access
Read data hold time
tROH
0
ns
RD low-level width
tROLl
(t .S+2n)tCY - 20
ns
tROL2
(2.S+2n)tev - 20
ns
Data access
O.S tCY
ns
Instruction fetch
Data access
WAIT' input time from RD
~
tRDWTl
tRDWT2
I.S Icy
ns
WAIT ~ input time from WR I
twRWT
0.5 tCY
ns
WAIT low-level width
twn
(2+2n)tcy
ns
Write data setup time to WR
t
(0.S+2n)tcy+l0
twos
100
ns
twOH
S
ns
WR low-level width
!wRLt
(2.S+2n)tCY - 20
ns
RD I delay time from ASTB I
tASTRD
O.S lcy-30
ns
Write data hold time from WR
WR I delay time from ASTB
t
~
t delay time from RD t (external fetch)
Address hold time froni RD t (external fetch)
Write data output time fr,?m RD t
ASTB
WR
~
delay time from write data
Address hold time from WR !
RD t delay time from WAIT!
WR ! delay time from WAIT t
Notes:
(1) tCY
•
ns
tASTWR
1.5 lcy-30
tRDAST
lcy-l0
tCy+40
ns
tRDAOH
Icy
Icy + SO
ns
tRDWO
10
!wOWR
0.5 tCy-120
O.StCY
ns
0.5 tCy-170
O.StCY
ns
Icy
tCy+60
ns
tCY
tCy+l00
ns
twTRO
0.5 Icy
2.S tCy+80
ns
1WTWR
0.5 Icy
2.S tCy+80
ns
!wRAOH
Instruction fetch
ns
VOO
= 4.S to 6.0 V
VOO
= 4.S to 6.0 V
= tCy/4
(2) n indicates number of waits.
(3) CL
=
100 pF
41
NEe
pPD78014 Family
Figure 31. Read Operation; External Fetch (No Wait)
-Upper 8-Btt Address
k--------tADD1-------~
Hi·Z
ASTB
L,~j--E-------tRDL1--===il.~
Figure 32. Read Operation; External Fetch (Wait Insertion)
Upper 8-Btt Address
k--------tADD1--------i~
HJ-Z
ADo-AD7
l..o«-----·tRDD1---~
ASTB
..
+-tASTRD-~ o«-------tRDL1-----~1
~n-tWT-L
...
~
42
NEe
IIPD78014 Family
Figure 33. Read/Write Operation; External Data Access (No Wait)
)
C
Upper 8-8tt Address
IADD2
)
Lower8-BI~
I>- ___
~!:Z
___ _<
Read Data
Address
lADS
HI-Z
Write Data
C
IADH
:8
+--IRDD2--
IRDH- ~
ASTB
'ABTRD
I
\
I-
'RDL2
~I
'RDWD
J
<
IWDS
..
~IWDWR
-'»
I.
•
I I
~IWDH"
_IWRADH-
\
tABlWR
'WRL1-83FM-9373B
43
NEe
pPD78014 Family
Figure 34. Read/Write Operation; External Data Access (Wait Insertion)
)
K=
Upper 8-Bft Address
tADD2
)
HI-Z
Lower 8-BII"'
Address ~--------~
tADS
AS1'B
tADH
J--1
r"=~
~tASTRD~
Read Data
'-r
I
\
-
tRDWD
tRDWT2---j
+-tWDWR
tASTWR
Iwn-'
I
tWTRD~
,.._tWRL1_
tWRWT-
~J
--J
~-
+-tWTL- -
W A I T - U - l
44
,..
tWDS
\
I
C
I I
1-I
tRDL.2
I.
o-!:!I~
WrfteData
I-tWTWR
NEe
pPD78014 Family
Serial Interface, 3-Wire, I/O Mode; Internal SCK Output
= -40 to +8S0C; Vee = 2.7 to 6.0 V; refer to figure 35
TA
Parameter
SCK cycle time
SCK high- and low-level width
SI setup time to SCK t
SI hold time from SCK t
SO output delay time from SCK ~
Symbol
Min
Unit
Conditions
tKCY1
800
ns
Vee
=
4.5 to 6.0 V
3200
ns
Vee
=
4.5 to 6.0 V
Typ
Max
tKCY1!2-S0
ns
tKCY1/2 - 150
ns
tSlK1
100
ns
tKSI1
400
tKH1. tKL1
ns
tKS01
= 4.5 to 6.0 V; C = 100 pF (Note 1)
= 100 pF (Note 1)
300
ns
Vee
1000
ns
C
Note 1: C is the loed capacitance of the SO output line.
--
Serial Interface, 3-Wire, I/O Mode; External SCK Input
= -40 to +85°C; Vee = 2.7 to 6.0 V; refer to figure 35
TA
Parameter
SCK cycle time
SCK high- and low-level width
SI setup time to SCK t
SI hold time from SCK t
SO output delay time from SCK ~
Symbol
Min
UnIt
CondItions
tKCY2
800
n8
Vee
=
3200
ns
400
ns
Vee
= 4.5 to 6.0 V
1600
ns
tSIK2
100
ns
tKSI2
400
tKH2' tKL2
tKS02
Typ
Max
I
4.5 to 6.0 V
ns
= 4.5 to 6.0 V; C = 100 pF (Note 1)
= 100 pF (Note 1)
300
ns
Vee
1000
ns
C
Note 1: C is the loed capacitance of the SO output line.
45
NEe:·
"PD78014 ,Family
Serial Interface, SBI Mode; Internal 'SCi( Output
TA = -40 to +85°0; Voo = 2.7 to 6.0 V; refer to figure 36
Parameter
Symbol
Min
SOK cycle time
tKCY3
800
n8
3200
n8
SOK high- and low-level width
tKH3, tKl3
tKCya/2-50
n8
tKCya/2 - 150
ns
100
ns
300
ns
SBO, SBl setup time to SOK t
tSIK3
SBO, SB1 hold time from SOK t
SBO,SBl output delay time from SOK
~
TyP
Max
, Unit
Voo = 4.5 to 6.0 V.
ns
tKCya/2
tKS03
0
250
ns
Voo = 4.5 to 6.0 V; R = 1 ko,
0= 100 pF (Note 1)
0
1000
ns
R = 1 ko, 0 = 100 pF (Note 1)
tKSB
tKCY3
SOK ~ from SBO, SBl ~
tsBK
tKCY3
ns
~
Voo = 4.5 .to· 6.0 V
tKSI3
from SOK t
SBO, SBl
Ccindltlons
Voo = 4.5 to 6.0 V
ns
SBO, SBl high-level width
tsBH
tKCY3
ns
SBO, SBl low-level width
tsBl
tKCY3
ns
Note 1: Rand 0 are the load resistance and load capacitance of the
SBO and SBl output lines.
Serial Interface, SBI Mode; External SCK Input
TA = -40 to +85°0; Voo = 2.7 to 6.0 V; refer to figure 36
Parameter
Symbol
Min
Unit
Conditions
SOK cycle time
tKCY4
800
ns
Voo = 4.5 to 6.0 V
3200
ns
SOK high- and low-level width
tKH4, tKl4
400
ns
1600
ns
100
ns
300
ns
SBO, SBl setup time to SOK t
tSIK4
SBO, SBl hold time from SOK t
SBO, SBl output delay time from SOK
~
Typ
Max
ns
tKCy-t/2
tKS04
0
300
ns
Voo = 4.5 to 6.0 V; R = 1 ko, 0 = 100 pF.
(Note 1)
0
1000
ns
R = 1 ko, 0 = 100 pF
tKsB
tKCY4
ns
SOK ~ from SBO, SBl ~
tSBK
tKCY4
ns
SBO, SBl high-level width
tsBH
tKCY4
ns
SBO, SBl low-level width
tSBl
tKCY4
ns
~
Note 1: Rand 0 are the load resistance and load capacitance of the
SBO and SBl output lines.
46
VOO = 4.5 to 6.0 V
tKSI4
from SOK t
SBO, SBl
Voo = 4.5 to 6.0 V
NEe
JlPD78014 Family
Serial Interface, 2·Wire, I/O Modej Internal SCK Output
TA = -40 to +85°C; Voo = 2.7 to 6.0 V; refer to figure 37
Parameter
SOK cycle time
SCK high-level width
SCK low-level width
Symbol
Min
Unit
Conditions
tKCY5
1600
ns
Voo = 4.5 to 6.0 V
3800
ns
tKH5
tKCys/2-50
ns
ns
ns
Typ
Max
tKL5
tKcvsl2 -50
SBO, S81 setup time to SCK t
tSIK1
300
S80, S8t hold time from SCK f
tKSI5
600
tKS05
0
250
ns
Voo = 4.5 to 6.0 V
R = 1 ko, C = 100 pF (Note 1)
o
1000
ns
A
SBO, S8t output delay time from SCK ,
ns
= 1 ko, C = 100 pF (Note 1)
-
Note 1: A and C are load resistance and load capacitance of the
SCKO, SBO, and S8t output lines.
Serial Interface, 2·Wire, I/O Modej External SCK Input
TA = -40 to +85°0; Voo = 2.7 to 6.0 V; refer to figure 37
Parameter
SOK cycle time
SCK high-level width
SCK low-level width
Symbol
Min
Typ
Max
Unit
Conditions
Voo = 4.5 to 6.0 V
t600
ns
3800
ns
tKH6
650
ns
ns
ns
tKCV6
tKL6
800
SBO, S81 setup time to SCK f
tSIKS
100
S80, S8t hold time from SOK f
tKSI6
tKCys/2
tKS06
0
300
ns
o
1000
ns
SBO, S8t output delay time from SCK ,
ns
Voo = 4.5 to 6.0 V
R = lko, C
=
100 pF (Note 1)
Note 1: A and C are load resistance and load capacitance of the
SCKO, SBO, and S81 output lines.
47
pPD78014 Family
Serial Interface, 3·Wire, I/O Mode with Automatic Transmit/Receive Function; Internal SCK Output
TA = -40 to +85°C; Voo = 2.7 to 6.0 V; refer to figure 38
Parameter
Symbol
SCK cycle time
tKCY?
SCK high- and low-level width
tKH7. tKL?
.,
Min
TypMax
Unit
Conditions
800
ns
Voo
3200
ns
tKCY7/2-50
ns
tKCY7/2 - 150
ns
ns
SI setup time to 5CK !
tSIK?
100
51 hold time from SCK!
tKSI?
400
5CK ~ to SO output delay time
tKs07
= 4.5 to 6.0 V
Voo = 4.5 to 6.0 V
ns
300
ns
Voo = 4.5 to 6.0 V; C = 100 pF (Note 1)
1000
ns
C = 100 pF (Note 1)
5TB ! from 5CK t
tSBO
400
tKCY7
ns
Strobe signal high-level width
tSBW
tKCY7-30
tKCY7 +30
ns
Busy signal set-up time (to busy signal
detection timing)
tBYS
100
ns
Busy signal hold time (from busy signal
detection timing)
tBYH
100
ns
5CK j from busy inactive
tsps
ns
2tKCY7
Note 1: C is the load capacitance for the 50 output line.
Serial Interface, 3·Wire, I/O Mode with Automatic Transmit/Receive Function; External'SCK Input'
TA = -40 to +85°C; Voo = 2.7 to 6.0 V; refer to figure 38
Parameter
5CK cycle time
5CK high- and low-level width
51 setup time to SCK !
51 hold time from 5CK t
SCK j to SO output delay time
SCK ~ (after STB) from SCK t
Symbol
Min
Unit
Conditions
tKCYS
800
ns
Voo = 4.5 to 6.0 V
3200
ns
tKHS' tKLS
.400
ns
1600
ns
tSIKS
100
ns
tKSIS
400
tKSOS
tSPSt
2tKCYS
Note 1: C is the load capacitance for the SO output line.
46
Typ
Max
Voo = 4.5 to 6.0 V
ns
300
ns
Voo = 4.5 to 6.0 V; C = 100 pF (Note 1)
1000
ns
C = 100 pF (Note 1)
ns
pPD78014 Family
Figure 35. Serial Interface Timing;
3-Wire Serial If0 Mode
1+----·IKCY1,2----~
IKl1,2-
ISIK1,2 -+_--"~~_I-IKSI1,2
SI--+I<--~--<=
--
83CL-937!iA
Figure 36. Serial Interface Timing; S81 Mode
SBI Bus Release Signal Transfer Timing
SCK
S8O,l
-t-f-
1KS03,4
SBI Bus Command Signal Transfer Timing
S8O,l
83CL-93788
49
NEe
pPD78014 Family
Figure 37. Serial Interlace Timing;
2-Wire Serial/fO Mode
IKL5,6 -+_-~
""0---<++-
I KS05 ,6
SBO,1
Figure 38. Serial Interlace Timing; 3-Wire Serial I/O Mode with Automatic Transmit/Receive Function
so
02
SI _____J
___rn~X~__oo~X~________~::~__~X
~-~--~ ~
_ _ _ _ _J
~
__________
00
~:===><__-oo---
1+-------ISPS1------:j~
_
~~(.\...J
~
ISB~~~
_______________________________
____________
~S~Sr_-------------
Busy Processing
\
9"','
'----'
\
10+n""
\,~s--./
~1~H--S->:t~~~~I_SP_S______________
BUSY
(ActIve high)
'" SCK does not actually become low here; II Is shown this way
to Indicate timing.
50
NEe
pPD78014 Family
AID Converter
= -40 to +85°C; AVoo = Voo = 2.7 to 6.0 V, AVss = Vss = ov
TA
Parameter
Symbol
Min
Typ
Max
Unit
8
8
8
bit
±1.5
LSB
Resolution
Absolute accuracy (Note 1)
Conversion time
tCONV
160ltx
JiS
tx
fX = 1 to 4.19 MHz
80IIx
JiS
Sampling time
tSAMP
241fx
JiS
Analog input voltage
VIAN
'AVss
AVoo
v
v
1.5
mA
Reference voltage
AVREF
AVREF current
IREF
2.7
0.5
Conditions
=
4.19 to 8.38 MHz
Note 1: Absolute accuracy does not include the quantization error
(±112 LSB).
I
Data Memory STOP Mode; Low-Voltage Data Retention
TA
____
____
= -40 to +85°C; refer
to figure
39
~--------~
~
~~_____________________________________________________
Parameter
Symbol
Min
Data retention supply voltage
VOOOR
2.0
Data retention power supply current
IOOOR
Release signal set time
tSREl
Oscillation stabilization wait time
tWAIT
Typ
0.1
0
Max
Unit
6.0
V
10
Conditions
VOOOR = 2.0 V; subsystem' clock stop and
feedback resistor disconnected
JiS
2181fx
ms
Release by RESET
(Note 1)
ms
Release by interrupt
Note:
(1) 2131fx, 215/tx, 2161tx, 2 171fx or 2 181fx canbe chosen by using bits
o to 2 of the oscillation stabilization time select (OSTS) register.
51
~ii
~
I
NEe
pPD78014 Family
Figure 39. O.t. Retention Timing
A. STOP mode Is released by RESET Input
fnlllmalreset
operallon
I
I
t:
i
I
STOP mode
I
I
Data Illten110n mode - -
vDOOR
HALTmode
Operation
mode
I
Exacullonof
STOP InstrucUon
\
~
-tSREL
tWAIT
B. STOP mode Is released by Interrupt signal
HALT mode
t:
s-s- - - - S T O P
_
i
ExecuUonof
STOP instruction
Standby release signal
(Interrupt request)
52
mode
I
-------+foo.-:-I--.j.- =uon
Data ratenUon mode
NEe
pPD78014 Family
PROM PROGRAMMING
PROM Programming Modes
The PROM in the IlPD78P014 is an OTP or UV EPROM.
The 32,768 x 8-bit PROM has the programmi ng characteristics of an NEC IlPD27C256A. Table 5 shows the
functions of the IlPD78P014 pins in both normal operating and PROM programming mode.
When the RESET pin is set low and Vpp is set to +5 V or
+12.5 V, the IlPD78P014 enters the programming mode
of operation. Operation in this mode is determined by
the setting ofthe CE, OE, Vpp and VDD pins as indicated
in Table 6.
Table 5_ Pin Functions During PROM
Programming
Function
Normal Operating Mode
Programming Mode
Address Input
P40 - P47. P50. POo.
P5:!- P56
Ao-A14
Data input
P30- P37
00- 07
Chip enable/
program pulse
P6sfWR
CE
Output enable
P64fRD
OE
Program voltage
IC
Vpp
Mode voltage
RESET
Logical 0
TableS.
Programming Operation Modes
Mode
RESET
Vpp
VDD
CE
OE
00 to 07
Program write
L
+12.5 V
+6V
L
H
Data input
Program verify
L
+12.5 V
+6V
H
L
Data output
Program Inhibit
L
+12.5V
+6V
H
H
High impedance
Data output
Read
L
+5V
+5V
L
L
Output dlsble
L
+5V
+5V
L
H
High impedance
Standby
L
+5V
+5V
H
L/H
High impedance
53
NEe
pPD78014 Family
Figure 40. PROM Programming Mode Pin Function;
64-Pin Plastic or Ceramic Shrink DIP
N_:
(1) L: Connect these pins separately to Vss through
reslato.. (10 kSl).
(2) Vss: Connect to Ills ground.
(3) RESET: Set to Ills low level.
(4) Open: Do not connect these pIns.
83YL-9G7M,
54
NEe
Figure 41.
JlPD78014 Family
PROM Programming Mode Pin Functions; 64-pin Plastic QFP
1£ !3 fll
10
!il III :g iO ffl :8
~
fa
f)l :;;
:5
~
48
o
}L
L
VSS
Open
Vpp
L
41
ILPD78P014GC
Open
..
Voo
}L
Ag
RESET
}L
..
«
C:O....J
IW
««§J< '---v-----" I0W0
0
~ '" '" Ul ...
...J
Notae:
(1) L: ConnecttheaeplnsseparatelytoVSS through.
",sIstO.. (10 1<11).
(2) VSS: Connect to the ground.
(3) RESET: Set to the low level.
(4) Open: Do not connect these pins.
83YL-938OB
55
NEe
pPD78014 Family
PROM Write Procedure
PROM Read Procedure
Data can be written to the PROM by usi ng the following
procedure.
The contents of the PROM can be read out of the
external data bus (Do - 07) by using the following
procedure.
(1) Set the pins not used for programming as indicated in figures 40 and 4t Set the RESET pin low
and the Voo and Vpp pins to +5 V. The CE and OE
pins should be high.
(2) Supply +6.0 V to the Voo pin and + 12.5 V to the
Vpp pin.
(3) Provide the initial address to the Ao - A14 pins.
(4) Provide the write data.
(5) Provide a 1-ms program pulse (active low) to the
CEpin.
(6) Use the verify mode (pulse OE low) to test the
data. If data is written correctly, proceed to step
8; if data is not written correctly, repeat steps 4 to
6 up to 25 times. If data is still incorrect, 'go to step
7.
(7) Classify the PROM as defective and cease write
operation.
(8) Perform one additional write with a program
pulse width (in ms) equal to three times the number of writes performed in step 5.
(9) Increment the address.
(10) Repeat steps 4-9 until the last adress is programmed.
56
(1) Set the pins not used for programming as indicated in figures 40 and 41. Set the RESET ~ low
and the Vpp pin and Voo pin to +5 V. The CE and
OE pins should be high.
(2) Input the address of the data to be read to the
Ao - A14 pins.
(3) Put an active-low pulse on CE and OE pins.
(4) Data is output to pins Do - 07.
Program Erasure
The UV EPROM can be erased (all locations FFH) by
exposing the window to light having a wavelength
shorter than 400 nm, including ultraviolet, direct sunlight, and fluorescent light. To prevent unintentional
erasure, mask the window.
Typically, data is erased by 254-nm ultraviolet rays. A
minimum lighting level of 15 W s/cm 2 (ultraviolet ray
intensity x exposure time) is' required to completely
erase the written data Erasure by ali ultraviolet lamp
rated at 12,000 pW/cm 2 takes approximately 15 to 20
minutes. Remove any filter on the lamp and place the
device within 2.5 cm of the lamp tubes.
NEe
pPD78014 Family
DC Programming Characteristics
TA= 25 ±5°C,Vss = DV.
Parameter
Symbol
Symbol"
Min
Max
Unit
High-level input voltage
VIH
VIH
D.7 Voop
Voop
V
0
0.3 Voop
V
10
/1A
Os VI s Voop
IOH = -400/1A
Typ
Condition
Low-level input voltage
VIL
VIL
Input leakage current
IliP
III
High-level output voltage
VOH1
VOH1
2.4
V
VOH2
VOH2
VOO-D.7
V
IOH = -100/1A
0.45
V
IOL = 2.1 mA
Low-level output voltage
VOL
Output leakage current
ILO
Voop power voltage
VOOP
Vpp power voltage
Vpp
VOL
VCC
Vpp
10
/1A
5.75
6.0
6.25
V
Program memory write mode
4.5
5.0
5.5
V
Program memory read mode
12.2
12.5
12.8
V
Program memory write mode
V
Program memory read mode
Vpp = Voop
Voop power current
Vpp power current
100
Ipp
Icc
Ipp
Os Vo s Voop, OE = VIH
5
30
mA
Program memory write mode
5
30
mA
Program memory read mode
CE = VIL, VI = VIH
5
30
mA
Program memory write mode
CE = VIL, OE = V IH
100
/1A
Program memory read mode
,
'Corresponding symbols of the /1PD27C256A.
AC Programming Characteristics (Write Mode)
TA = 25 ±5°C, Vss = OV, Voo =6 ±0.25V, Vpp = 12.5 ±0.3V.
Parameter
Symbol
Address setup time to CE I
tSAC
Symbol"
Min
Typ
Max
Unit
tAS
2
/1s
Data input to OE I delay time
tOOOO
tOES
2
/1s
Input data setup time to CE I
tSIOC
tos
2
/1s
Address hold time from CE !
tHCA
tAH
2
/1s
Input data hold time from CE !
tHCIO
tOH
2
Output data hold time from OE f
tHOOO
tOF
0
Vpp setup time to CE I
tsvPC
tyPS
Voop setup time to CE I
tsvOC
tvcs
Initial program pulse width
twL1
tpw
0.95
Additional program pulse width
twL2
topw
2.85
DE I to data output time
tOOOO
tOE
Conditions
/1s
130
ns
ms
ms
1.0
.'
1.05
ms
78.75
ms
150
ns
" Corresponding symbols of the /1PD27C256A.
57
NEe
pPD78014 Family
AC Programming Characteristics (Read Mode)
= 25 ±5°C Vss = 0 V, ¥oo = 5 ±O.5 V, Vpp = Voo.
TA
Parameter
Symbol
Max
Unit
Address to data output time
tOAOO
tACC
200
ns
CE
CE I to data output time
tocoO
tCE
200
ns
OE
75
ns
60
ns
Symbol*
Min
OE I to data output time
tOOOO
tOE
Data hold time from OE t
tHCOO
tOF
o
Data hold time from address
tHAOO
tOH
o
Typ
ns
Condition
= OE = VIL
= VIL
CE = VIL
CE = V 1L
CE = OE = VIL
* Corresponding symbols of the IIPD27C256A.
AC Programming Characteristics (PROM Mode)
TA = 25 ±5°C, VSS = OV
Parameter
Symbol
PROM mode setup time
tSMA
58
Min
Typ
Max
Unit
10
liS
Condition
NEe
pPD78014 Family
PROM Timing Diagrams
PROM Write/llerify Mode
=>- r~
ISIDe_
Vpp
Vpp
VDDP
EfIecIIve Addr_
Data
Input
r-
-j
1SAC
1
~.
Data
0UIpu1
I--tH~ID
I
- ~-
.t-
r-- IHOOD
K
IHCA
~ r- -1 t.:
Data
Inpul
--
tSlDe
~
~
.,.
J--tsvoc
~
~
tWL1
JrL~tDOOD
,
J
I+-t~
Notw:
(1) VDDP must be applad before applying Vpp. ft should be removed before removing Vpp.
(2) Vpp must not exceed +13V, Including OV8I8hoot.
B3YL-9:!828 (1VB3)
59
NEe
pPD78014 Family
PROM Timing Diagrams (cont)
PROM Relld Mode
tHAOD
Data Output
PROM Mode Setting
o
RESeT---""
\
Vpp
o
tSMA
AO·A14 _ _ _ _- - J)
EffecIIve Add,...
83Yl-038tA (1183)
60
H1.z
NEe
NEC Electronics Inc.
pPD78014Y Family
(pPD78011 BY/012BY/013Y/014Y/P014y)
8-Bit, K-Series Microcontrollers
General Purpose With AID Converter and 12C Bus
Preliminary
September 1993
Description
Features
The J.lPD780ii BY, J.lPD780i2BY, J.lPD780i3Y, J.lPD780i4Y,
and J.lPD78POi4Y are members of NEC's K-Series@ of
microcontrollers. The J.lPD78014Y family is a variation
of the J.lPD780i4 family with the addition of an 12C bus
mode in serial interface O. These 8-bit, single-chip
microcontrollers feature an A/D converter, two serial
interface ports, 8-bit hardware multiply and divide
instructions, bit manipulation instructions, four banks
of main registers, an advanced interrupt handling facility, and a powerful set of memory-mapped on-chip
peripherals.
o Eight-channel 8-bit A/D converter
- Operates from 2.7 to 6.0 V
On-board data memory includes 512 or 1024 bytes of
internal high-speed RAM plus 32 bytes of serial buffer
RAM. Program memory options include SK, 16K, 24K, or
32K bytes of mask ROM, or 32K bytes of UV EPROM or
one-time programmable (OTP) ROM.
The J.lPD78014Y family operates over a wide voltage
range: 2.7 to 6.0 volts. Timing is generated by two
built-in oscillators. A main oscillator normally drives
the CPU and most peripherals and at 10 MHz provides
a minimum instruction time of 0.4 J.lsec. A subsystem
oscillator at 32.768 kHz provides time keeping, and
optionally a slow clock for the CPU. Since CMOS power
dissipation is directly proportional to clock rate, the
J.lPD78014Y family provides a software variable CPU
clock. The HALT and STOP modes are two additional
power saving features that turn off parts of the microcontroller to reduce power consumption. A data retention mode permits RAM contents to be saved down to 2
volts.
The range of peripherals, including an A/D converter,
timers, and two serial ports (one with an IC2 bus
interface) makes these devices ideal for applications in
portable battery-powered eqUipment, office automation, comunications, consumer electronics, home appliances, and fitness equipment.
o Two-channel serial communication interface
- S-bit clock-synchronous interface 0
12C bus mode
Full-duplex, three-wire mode
NEC serial bus interface (SBI) mode
Half-duplex, two-wire mode
- S-bit clock-synchronous interface 1
Full-duplex, three-wire mode with automatic
transmit/receive
Half-duplex, two-wire mode
o Timers
- Watchdog timer
-16-bit timer/event counter
- Two 8-bit timer/event counters usable as one
16-bit timer event/counter
- Clock (watCh) timer (time of day tick from either
oscillator)
o 531/0 lines
- Two CMOS input-only lines
-47 CMOS I/O lines
- Four n-channel, open-drain I/O lines at 15 V
maximum
o I/O port pullup resistors
-Software controllable on 47 lines
- Mask option on four lines on ROM version
o Program memory
- J.lPD78011 BY: SK bytes ROM
-J.lPD78012BY: 16K bytes ROM
-J.lPD7S013Y: 24K bytes ROM
- J.lPD78014Y: 32K bytes ROM
-J.lPD78P014Y: 32K bytes EPROM/OTP
o Internal high-speed data memory (RAM)
-J.lPD78011BY/Oi2BY: 512 bytes
-J.lPD780i3Y/Oi4Y/POi4Y: 1024 bytes
o Specialized memory
- Serial buffer RAM: 32 bytes
o External memory expansion
- 64K bytes total memory space
K-Serles is a registered trademark of NEC Electronics, Inc.
Purchase of NEC 12C components conveys a license under the Philips
12C Patents Rights to use these components In an 12C system,
provided that the system conforms to the 12C standard specification
as defined by Philips.
150808
o Powerful instruction set
- 8-bit unsigned multiply and divide
-i6-bit arithmetic and data transfer instructions
-i-bit and 8-bit logic instructions
•
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pPD78014Y Family
Features (cont)
o Minimum instruction times:
- 0.4/0.8/1.6/3.2/6.4 Jls program selectable using
10-MHz main system clock
-122 J.ls selectable using 32.768-kHz subsystem
clock
.
o Memory-mapped on-chip peripherals (special
function registers)
o Programmable priority, vectored-interrupt
controller (two levels)
CJ
Buzzer and clock outputs
CJ
Power saving and battery operation features
- Variable CPU clock rate
-HALT mode
-STOP mode
- 2-V data retention mode
- CMOS operation; VDD from 2.7 to 6.0 V
Ordering Information
Part Number
ROM
Package
Package Drawing
IlPD78011 BYCW-xxx
8Kmask ROM
64-pin plastic shrink DIP
P64C-70-750 A. C
IlPD78012BYCW-xxx
16K mask ROM
64-pin plastic QFP
P64GC-80 -AB8-2
64-pin ceramic shrink DIP w/window
P64DW-70-750 A
IlPD78013YCW-xxx
24Kmask ROM
IlPD78014YCW-xxx
32Kmask ROM
IlPD78P014YCW
32KOTP ROM
IlPD78011 BYGC-xxx-AB8
8Kmask ROM
IlPD78012BYGC-xxx-AB8
16K mask ROM
IlPD78013YGC-xxx-AB8
24Kmask ROM
IlPD78014YGC-xxx-AB8
32Kmask ROM
IlPD78P014YGC-AB8
32KOTP ROM
IlPD78P014YDW
32KUV EPROM
Notes:
(1) xxx indicates ROM code suffix
(2) All devices listed are standard quality grade
2
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"PD78014V Family
Pin Configurations
64-Pin Plastic or Ceramic Shrink DIP
P2o'S11
1'>211501
P2:tSCK1
f'23ISTB
AVREF
AVDD
PI7/ANI7
PletANI6
P24fBUSY
f'2sISDAOISIOISBO
P2sfSDA1/SOO1SB1
PIS/ANIS
P141'ANI4
P27/SCLJSCKO
P1:tANI2
P13/AN13
P3ofTOO
P11/AN11
P31fT01
P32fT02
P101ANIO
P3a'rI1
P34fT12
AVSS
P04/XT1
XT2
P3sfPCL
IC(Vpp)
P3&'8UZ
Xl
P37
Vss
X2
I
Ell
P4ofADo
P41/AD1
VDD
PO:jINTP3
PO:ilN1P2
P4:tAD2
P0111NTP1
P4atAD3
P441'AD4
P4s1ADs
POoIINTPOITIO
RESET
P67(ASlB
P4s1ADs
PSalWAfT
P47/A~
P6&'WR
P6.vRO
PSoIAa
PS1/Ag
PS:tA10
PS:iA11
P54IA12
PSs/A13
VSS
I
P63
P62
PS1
PSo
PS7/A1S
PS&,A14
Note:
Connect IC (lntemally Connected) Pin
(Vpp on "PD78P014y) to VSS.
83AD-9461A (8193)
3
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pPD78014YFamily
Pin Configurations (cant)
64-Pin Plastic QFP
P30'TOO
P3lrrOl
P1j/ANll
Plo1ANIO
P32"f02
AVSS
paaml
P3.4fTI2
I'll4IXTl
XT2
P3&,!,CL
IC(Vpp)
P3s/BUZ
Xl
X2
P37
VSS
P4dADO
P4l/ADl
P421AD2
P4:fAD3
P44fAD4
VDD
POa'lNTP3
P02IINTP2
POl/lNTPl
POofINTPOITIO
RESET
P4s1ADS
P6r1ASTB
P4&,ADe
PSefWAIT
Note:
Connect IC (Intemally Connected) Pin
(Vpp on ~PD78P014Y) to VSS.
83RD-9438B (W93)
4
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I'PD78014Y Family
Pin Functions; Normal Operating Mode
Symbol
First Function
Symbol
Alternate Function
POo
Port 0; S-bit, bit selectable 1/0 port
(Bits 0 and 4 are input only)
INTPO
TIO
External maskable interrupt
External count clock input to timer 0
INTP1
INTP2
INTP3
External maskable interrupt
XT1
Crystal oscillator or external clock input for
subsystem clock
Analog input to AID converter
P1 0 - P17
Port 1; B-bit, bit-selectable I/O port
ANIO-ANI7
P20
Port 2; B-bit, bit-selectable 1/0 port
SI1
Serial data input three-wire serial I/O mode
S01
Serial data output three-wire serial I/O mode
SCKt
Serial clock I/O for serial interface 1
STB
Serial interface automatic transmit/receive
strobe output
BUSY
Serial interface automatic transmit/receive busy
input
SIO
SBO
Serial data input three-wire serial 1/0 mode
2/3-wire serial 1/0 mode
Serial data bus a for 12C bus mode
P~
SOAO
SOO
S0A1
Serial data output three-wire serial I/O mode
2/3-wire serial I/O mode
Serial data bus 1 for 12C bus mode
SCKO
SCl
Serial clock I/O for serial interface 0
Serial clock 1/0 for 12C bus mode
SBt
P27
P30
Port 3; B-bit, bit-selectable 1/0 port
P36
P4o- P47
Port 4; B-bit 1/0 port
P50 - P57
Port 5; B-bit, bit selectable I/O port
Port 6; B-bit, bit selectable (P6o to P63 nchannel open-drain 1/0 with mask option pullup
resistors (P64 - P67 I/O). See note.
TOO
Timer output from timer 0
T01
Timer output from timer 1
T02
Timer output from timer 2
Tit
External count clock input to timer 1
TI2
External count clock input to timer 2
PCl
Programmable clock output
BUZ
Programmable buzzer output
ADO-AD?
low-order B-bit multiplexed addressldata bus
for external memory
~~
High-order B-bit address bus for external
memory
RD
External memory read strobe
WAIT
External memory wait signal input
ASTB
Address strobe used to latch address for
external memory
External memory write strobe
P6r
_:
5
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JlPD78014Y Family
Pin Functions; Normal Operating Mode (cant)
Symbol
First Function
RESET
External system reset input
Xl
CrystaVceramic reaonator connection or
external clock input for main system clock
X2
CrystaVceramic resonator connection or
inverse of external clock for main system clock
XT2
Crystal oscillator or left open when using
external clock for subsystem clock
AID converter reference voltage
AVoo
AID converter power supply input
AVss
AID converter ground
Voo
Power-supply input
Vpp
iIPD78P014Y PROM programming powersupply input
Vss
Power-supply ground
IC
Note:
6
Internal connection
See table 2 and figure 4 for details
Symbol
Alternate Function
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JlPD78014Y Family
Block Diagram
TOOIP30
TIOIII'lTPOIPOO
=I
1&bftTbnerf
Evant Counter 0
~
General Reg.
Internal
Program Memory
(ROMIPROM)
Note 1
S111P20S011P21
SCK11P22 ....... Serial Interlace 1
STBIP23
BUSYIP24 -
ADrfP4rr
......_ - - - - '
AOJIP47
ANICYP10AN17/P1 7
AVOOAVSS
AVREF-
A&'P5oA1sfP57
RDlP84
....... WRIP85
--------'
INTPOIPOo- ~
11'lTP3/P03
Interrupt
Controller
~
'-------'
il 1 1
RESET VOO
Vss
....... WAITIP88
ASTBIP87
Ie
(Vpp)
Note 2
Not..:
(1) The Intemal ROM and RAM size depends on the device.
(2) Pin name In parentheses for Ihe ~P078P014Y only.
83.1>84300(813)
7
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pPD78014V Family
FUNCTIONAL DESCRIPTION
Internal System Clock Generator
Central Processing Unit
Th~ internal sy~tem .clocks of the pPD78014Y family
are
denved from either the main system or the subsystem
oscillator. See figure 1. The clocks for the clock timer
and programmable clock output are derived from either
the subsystem clock (fXT) or the main system clock. The
clocks for all other peripheral hardware are derived
from the main system clock.
The. central processing unit (CPU) of the pPD78014Y
fa~lly fe~tures 8- a~d 16-bit arithmetic including an 8 x
8-blt unsigned multiply and 16 x 8-bit unsigned divide
(producing a 16-bit quotient and an 8-bit remainder).
Th~ multiply executes in 3.2 ps and the divide in 5 ps
uSing the fastest clock cycle with a main system clock
of 10 MHz.
.
The CPU clock ()cO----II~
Vee
data~
outputdl8able~
Type 2 (PlIo. RESET)
IN
o>----B>---~~
+---.--+--<>
INIOUT
TypeIJoB(P10·P171
Vee
pullUpenable
•
Vee
------11>
I>
pullup enable
Vee
data
data
INIOUT
output disable
output disable
f£;
INIOUT
..L
Input enable - - - - - - - '
Type IJoB (P4o. P47)
VREF (Threshold Voltage)
Vee
Input enable _ _ _ _--==---.J
pullupa_ -------II>)C---I~
...-_-+---o INIOUT
Input_bIe - - - - - - - '
83Cl-84... (1)
15
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pPD78014Y"Family
Figure 4.
Pin Input!Output Circuits (cont)
Type 13-B (PeO· Pea)
Type 1o.A <'25· P27>
Voo
--.-
puUup enable -------I!>>O----If;a>
Voo
output
data ----_--1f;a>
...-_._---0
INfOUT
dis:: ----[)0---1
N-ch
Voo
opmd~n_~-l_~~~-1~
ouIput disable
RO----If..
Mlddle·Hlgh Voltage Input Buffar
Type 13 (PeO· Pea)
Middle-High Voltage Input Buffar
16
,
~
,---+--o
[Mask Option]
INfOUT
NEe
JlPD78014Y Family
Analog-to-Digital (AID) Converter
The JiPD78014Y family AID converter (see figure 5) u~es
the successive-approximation method for converting
one of eight multiplexed analog inputs into 8-bit digital
data The conversion time per input is 19.1 Jis at 8.38
MHz operation.
The AID converter input select register (ADIS) selects
the number of inputs that are used in AID conversion.
The remaining inputs are used as ports. The AID input
to be converted is selected by programming the AID
converter mode register (ADM). AID conversion is
started by external interrupt INTP3, or by writing to the
ADM. When the conversion is completed, the results are
stored in the AID conversion result register (ADCR) and
an INTAD interrupt is generated.
If the AID converter was started by an external interrupt, the AID converter stops after the interrupt is
generated. If the AID converter was started by software, the AID converter repeats the conversion until
new data is written to the ADM register.
Figure 5. AID Converter
From ADM
-
Resistor St~ng
----------
I
I
I
I
I
I
I
I
r------'
I
I
I
I Tap I
ISelector I
I
I
I
I
Sample and
Hold Circuit
r---l
I
I
I:
L ___ .J
(ncta 1)
(nete 2)
II
1----l~~1
I
I
Ccnverslon ~gger
II
I
I
I
I
I
fTAVREF
I
I
I
I
!
LL
~~~ _____ J
L .- - _ )
I
I
I
I
I
I
I
I
I
AVSS
I
INTP3
Tdgger Enable
8
TO Input Selector (2)
AID Ccnverslon Result
Register (ADCR)
8
Internal Bus
Notaa:
(1) Selects number of port 1 Inputs to be used for AID conversion.
(2) Selects the channel for AID conversion.
83Yl-9346B
17
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pPD78014V Family
Serial Interfaces
The JlPD78014Y family has two independent serif,ll interfaces: serial interface 0 and serial interface 1..
Serial Interface O. Serial interface 0 is an 8-bit clock
synchronous serial interface (figure 6). It can be operated in either a three-wire serial I/O mode,NEC serial
bus interface (SBI) mode, two-wire serial I/O mode, or
12C bus mode. The serial clock can be provided from
one of eight internal clocks, the output of 8-bit timer
register 2, or the external clock line SCKO (SCL for 12C
bus mode).
In the three-wire serial I/O mode, the 8-bit shift register
(S 100) is loaded with a byte of data and eight clock
pulses are generated; The falling edge of these eight
pulses shifts the byte of data out of the SOO line (either
MSB or LSB first) while the rising edge of these pulses
Shifts the data in from the SIO line providing full-duplex
operation. The INTCSIO interrupt is generated after
each 8-bit transfer.
TheNEC SBI mode is a two-wire high-speed proprietary
serial interface available on most devices in the NEC
JlPD75xxx and JlPD78xxx product lines. Devices are
Figure 6_ Serial Interface 0
SDAO/
SIOl
SBOI
0
P25
SDA1f
SOOI
SB1f
0
P2a
FromP2a
OutputLatc:h
SCU
SOKOl
P2]
0
IntemalBus
18
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pPD78014Y Family
connected in a master/slave configuration (see figure
7). There is only one master device at a time; all others
are slaves. The master sends addresses, commands,
and data over one of the serial bus lines (SBO or SB1)
using a fixed hardware protocol synchronized with the
SCKO line. Each slave device of the IIPD78014Y family
can be programmed to respond in hardware to anyone
of 256 addresses set in its slave address register (SVA).
There are also 256 commands and 256 data types.
Since all commands are user definable, many software
protocols, simple or complex, can be defined. It is even
possible to develop commands to change a slave into a
master and the previous master into a slave.
Figure 7. 5B/ Mode MasterlS/ave Configuration
V
DO
Slave CPU
MastarCPU
~
(SB1),SBO
SCK
Address 1
driven on to the serial line and shifted into the SIOO
register on the rising edge of the serial clock. The
INTCSIO interrupt is generated after each 8-bit transfer.
The 12C bus is a two-wire, high-speed serial bus developed by Phi lips. The 12C bus configuration has a si ngle
master and up to 128 slave devices (see figure 8). The
master sends the start condition, 7-bit slave address,
one bit indicating the direction of the upcoming data
transfer, and the stop condition over one of the serial
bus lines (SDAD or SDA1) using a fixed hardware
protocol synchronized with the output of the serial
clock line (SCL).
Each slave device of the JlPD78014Y family can be
programmed to respond in hardware to any of 128
addresses set in its SVA. Depending on the state of the
transfer direction bit, either the master or the slave
device places additional data on the 12C bus. The
device receiving the data returns an acknowledge signal each time it receives 8 bits of data. The slave device
can also notify the master device when it is busy by
holding SCL low.
SCK
Figure 8. /2C Bus MasterlS/ave Configuration
SlavaCPU
SBO,IBB1)
r---+
t-t
Slave CPU1
Master CPU
Addraas2
Serial Clock
SCL
SCL
SCK
Serial
Data Bus
SDAO(SDA1)
SDAOISDA1)
SlavalC
SBO,ISB1)
AddraasN
--
Slave CPU2
'V
SCK
83YL-9347A (9IS3)
~
SCL
SDAO(SDA1)
The two-wire serial 1/0 mode provides half-duplex operation using either the SBO or SB1 line and the SCKO
line. Communication format and handshaking can be
handled in software by controlling the output levels of
the data and clock lines between transfers. When the
8-bit shift register (SIOO) is loaded with a byte of data,
eight clock pulses are generated. The falling edge of
these eight pulses shifts the byte of data out of either
the SBO or SB1 line MSB first. In addition, this byte of
data is also shifted back into SIOO on the rising edge of
these pulses providing a way of verifying that the
transmission was correct.
..
83RD-9447A
For data reception, the SIOO register is preloaded with
the value FFH. As this data value is shifted out on the
falling edge of the serial clock, it disables the n-channel
open-drain driver. This allows the receive data to be
19
a
•
ii.
,)
:
JlPD78014V Family
Serial Interface 1. Serial interface 1 is also an a-bit
clock synchronous serial interface (figure 9). It can be
operated in either a three-wire serial I/O mode, or
three-wire serial I/O mode with automatic transmit!
receive. The serial clock can also be provided from one
of eight internal clocks (common clock for both interfaces), the output of a-bit timer register 2, or the
external clock line SCK1.
Figure 9. Serial Interface 1
(CSIM1) - -......--1
'--'---~
FromP21
Output Latch
~23 o~--~---~------,
BUSYIP24 o)---I---~
~-+-------~
__-r-'
1-j-_-...-j-----i.-.lI-----1I--j-~ INTCSI1
From P22
Outpull.atch
20
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In the three-wire serial I/O mode, the 8-bit shift register
(SI01) is loaded with a byte of data and eight clock
pulses are generated. The falling edge of these eight
pulses shifts the byte of data out of the S01 line (either
MSB or LSB first) while the rising edge of these pulses
shifts the data in from the SI1 line providing full-duplex
operation. The INTCSI1 interrupt is generated after
each 8-bit transfer.
In the three-wire serial I/O mode with automatic
transmit/receive, up to 32 bytes of data can be transferred with minimal CPU overhead. The data to be
transmitted and received is stored in the buffer RAM.
Handshaking using either the BUSY input line, the
strobe (STB) output line, or both, can be selected by
the program. Error detection of bit drift due to noise is
available for each byte transferred when using the
BUSY input line. This automatic transmit/receive mode
is ideally suited for transferring data to/from external
peripheral devices such as onscreen display (OSD) and
LCD controller/driver devices.
IIPD78014Y Family
While in three-wire serial interface mode with automatic data transfer, the interface can be operated as
either a full-duplex interface or a transmit-only interface in single or repetitive operation mode. In the fullduplex mode, a byte of data is transferred from the first
location in the buffer RAM and shifted out of the 801
line (either M8B or L8B first) while the received data is
shifted into the 811 line and stored back in the first
buffer location. After the preset number of bytes has
been transferred, the INTC811 interrupt is generated.
In single-operation transmit mode, the preset number
of bytes from the buffer RAM are transmitted out of the
801 line (either MSB or L8B first) and the INTC811
interrupt is generated after all bytes are transferred. In
the repetitive operation transmit mode, data in the
buffer is transmitted repeatedly.
21
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pPD78014V Family
Timers
The pPD7aD14Y family has one 16-bit timer/event
counter, two a-bit timer/event counters that can be
combined for use as a 16-bit timer/event counter, a
clock timer, and a watchdog timer. All of these can be
programmed to count a number of prescaled values of
the main system clock. In addition, the clock timer can
also count the subsystem clock. All of the timer/event
counters can count external events.
16-Bit Timer/Event Counter O. Timer/event counter 0
(figure 10) consists of a 16-bit counter (TMD), a 16-bit
compare register (CROO), a 16-bit capture register
(CR01), and a timer output (TOO). Timer 0 can be used
as an interval timer, to count external events on the
timer input (TID) pin, to output a programmable square
wave, a 14-bit pulse width modulated output, or to
measure pulse widths.
Figure 10_
16-Bit Timer/Event Counter 0
IntemalBus
D
r-------~--~------------~IKnMO
'xl2'X/4 'xiS -
T00IP30
Selector
TlOIPOOI
INlPO
----------~--~~r_~--4r~------~INT~
16-Bft capture Aeglslllr
(CR01)
IntemalBus
22
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pPD78014Y Family
8-Bit Timer/Event Counters 1 and 2. Timer/event
counters 1 and 2 (figure 11) each consist of an a-bit
timer (TM1 or TM2), an a-bit compare register (CR10 or
CR20), and timer output control logic (T01 or T02). The
timers are controlled by registers TCL1, TMC1, and
TOC1 via five selectors. Timer/event counters 1 and 2
can each be used as an a-bit interval timer, to count
external events on the timer input pins (T11 or TI2), or to
output a programmable square wave. In addition, timers 1 and 2 also can be combined as a 16-bit timer/
event counter and used as a 16-bit interval timer, to
count external events on T11, or to output a programmable square wave on T02.
Figure 11. 8-Bit Timer/Erent Counters 1 and 2
..
IntemalBus
1------~----------------------~INTIM1
8·BII
llmerlEvent
Counter 2
Oulpul
Conlrol logic
T02/P32
IX/4
IX/8
IX/1S
Ixl32
Ix/84
IXI128
~----+---_INTIM2
IX/256
IX1512
Ix/1024
Ix/40gB
Salector
Tl2JP3t-
1---------i----+T01IP31
* RISIng or failing edge can be selected.
23
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pPD78014Y Family
Clock Timer 3. Clock timer 3 (figure 12) is a 5-bit timer
that can be used as a time source to keep track of time
of day, to release the STOP or HALT modes at regular
intervals, or to initiate any other task that must be
performed at regular intervals. When driven by the
subsystem clock, the clock timer continues to operate
in the STOP mode. The clock timer can function as
both an interval timer and a clock timer simultaneously.
When used as an interval timer, vectored interrupt
request INTTM3 is generated at preselected time intervals. With a main system clock of 8.38 MHz or a
subsystem clock of 32.768 kHz, the following time
intervals can be selected: 489 ps, 978ps, 1.96 ms, 3.91
ms, 7.82 ms or 15.6 ms.
When used as a clock timer, interrupt request INTWT
(not a vectored interrupt) can be generated using the
main system clock or subsystem clock every 0.5 or 0.25
seconds.
Watchdog Timer. The watchdog timer (figure 13) can
be used as either a watchdog timer or an interval timer.
When used as a watchdog timer, it protects against
inadvertent program run-away. It can be selected to
generate a nonmaskable interupt (INTWDT), which vectors to address 0004H, or to generate an internal reset
signal, which vectors to the restart address OOOOH if the
timer is not cleared by the program before it overflows.
Eight program-selectable intervals based on the main
system clock are avai lable. With a mai n system clock of
8.38 MHz, the program selectable intervals are 0.489,
0.978, 1.96,3.91,7.82, 15.6,31.3, and 125 ms. Once the
watchdog .timer is initialized and started, the timer's
mode cannot be changed and the timer can only be
stopped by an external reset. When used as an interval
timer, maskable interrupts (INTWDT), which vector to
address 0004H, are generated repeatedly at a preset
interval. The time intervals available are the same as in
the watchdog timer mode.
Programmable Clock Output
The pPD78014Y family has a programmable clock output (PCL) that can be used for carrier output for remote
controlled transmissions or as a clock output for peripheral devices. The main system clock (fx) divided by
8, 16, 32, 64, 128, or 256 or the subsystem clock (fXT)
can be output on the PCl pin. Frequencies of 1050, 524,
262, 131, 65.5 and 32.7 kHz are available with a main
system clock of 8.38 MHz. See figure 14.
Figure 12. Clock Timer 3
r---
-1
'--....Selector
'w129
'x128 _
'XT- '--....-
'w
Prescaler
I
)
)
Selector
r--- IN1WT
-r--
Clear
'w
/26
INTTM3
Selector
'w125
'w124
jClear
Timer Clock Select
Register 2 (TCL2)
-
'w128
fw12 7
r--Selector
1
I5-Bft
Timer
1214
I ''ww1213
,
I
I
I
I
I
Clock Timer Mode
ConllOl Register (TMC2)
IntemaiBus
~
I
<,
B3YW(l61B
24
NEe
Figure 13.
pPD78014V Family
WIItchdog TImer
Run
INTWDT
Maskable
Interrupt
Request
12",7+1 Saleclor
...-1:.0.:.::
8·BII
Counter
ConllOl
Logic
...-----------+--_ RESET
INTWDT
Nonmaskable
Interrupl
Request
....-.'
"....
Internal Bus
B3Yl·9352B (eI93)
Figure 14. Programmable Clock Output
IXI23---~
Ix124 - - - - + I
IX125 - - - - + I
Ix128 - - - - + I Selaclor
IxI27---~
IxI28---~
fxr
------;~
25
NEe
pPD78014Y Family
Buzzer Output
The IIPD78014Y family also has a programmable buzzer
output (BUZ). The buzzer output· frequency can be
programmed to be equal to the main system clock (fx)
divided by 1024, 2048, or 4096. With a main system
clock of 8.38 MHz, the buzzer can be set to 8.2, 4.1 or 2.0
kHz. See figure 15.
Figure 15. Buzzer Output
'xx
--~'"'
1210
I 12 11 ----.;"'1 Selector
I----------r"'>____--I
IX12 12 ----.;"'1
Interrupts
The IIPD78014Y family has 14 maskable hardware interrupt sources (5 external and 9 internal). Of these 14
interrupt sources, 12 cause a vectored interrupt while
the 2 testable inputs only generate an interrupt request. All of the 14 maskable interrupts can be used to
release the HALT mode except INTPO. INTPO cannot be
used to release the STOP mode and cannot release the
HALT mode when register SCS = O. In addition, there is
one nonmaskable interrupt from the watchdog timer,
one software interrupt, and a reset interrupt. The
watchdog timer overflow interrupt Onterrupt vector
table address 0004H) can be initialized to be a nonmaskable interrupt or the highest default priority maskable interrupt. The software interrupt, generated by the
BRK instruction, is not maskable. See table 3 and figure
16.
26
>---'----('0 BUZlP3e
NEe
Table 3.
Interrupt Sources and Vector Addresses
Type of
Request
Vector
Signal Name
Interupt Source
Location
Interrupt
Address Configuration
RESET
RESET input pin
External
OOOOH
INTWDT
Watchdog timer overflow
(when reset mode selected)
Internal
INTWDT
Watchdog timer overflow
(when nonmaskable interrupt selected)
Internal
0004H
A
0
INTWDT
Watchdog timer overflow
(when interval timer selected)
Internal
0004H
B
INTPO
External interrupt edge detection
External
OOOSH
C
2
INTP1
External interrupt edge detection
External
0008H
D
3
INTP2
External interrupt edge detection
External
OOOAH
D
4
INTP3
External interrupt edge detection
External
OOOCH
D
5
INTCSIO
End of clocked serial interface 0 transfer
Internal
OOOEH
B
S
INTCSII
End of clocked serial interface 1 transfer
Internal
0010H
B
7
INTTM3
Clock timer reference time interval signal
Internal
0012H
B
8
INTTMO
IS-bit timer/event counter coincidence signal
Internal
0014H
B
9
INTTMI
8-bit timer/event counter 1 coincidence signal
Internal
001SH
B
10
INTTM2
8-bit timer/event counter 2 coincidence signal
Internal
0018H
B
11
INTAD
End of A/D Conversion
Internal
001AH
B
BRK instruction
Internal
003EH
E
INTWT
Clock timer overflow
Internal
F
INTPT4
Port 4 falling edge detection
External
F
Default
Priority
Restart
Nonmaskable
Maskable
pPD78014Y Family
Software
Test input
Interrupt Servicing. The /lPD78014Y family provides
two levels of programmable hardware priority control
and services all interrupt requests, except the two
testable interrupts (lNTWT and INTPT4), using vectored
interrupts. The programmer can choose the priority of
servicing each maskable interrupt by using the interrupt control registers.
Interrupt Control Registers. The /lPD78014Y family
has three 16-bit interrupt control registers. The interrupt request flag register (IFO) contains an interrupt
request flag for each interrupt except INTPT4. The
interrupt mask register (MKO) is used to enable or
disable any interrupt except INTPT4. The priority flag
register (PRO) can be used to specify a high or a low
priority level for each interrupt except the two testable
interrupts.
Four other 8-bit registers are associated with interrupt
processing. The key return mode register (KRM) contains the KRIF interrupt request flag associated with
_i~
falling-edge detection on port 4 and the KRMK mask
flag used to enable or disable clearing of the standby
mode if a falling edge is detected on port 4. The
external interrupt mode register (INTMO) is used to
select a rising, falling, or both edges as the valid edge
for each of the external interrupts INTPO to INTP2
(INTP3 is always falling edge). The sampling clock
select register (SCS) is used to select a sampli ng clock
for the noise eliminator circuit on external interrupt
INTPO.
The IE and the ISP bit of the program status word are
also used to control interrupts. If the IE bit is 0, all
maskable interrupts are disabled. The IE bit can be set
or cleared using the EI and 01 instructions, respectively, or by directly writing to the PSW The IE bit is
cleared each time an interrupt is accepted. The ISP bit
is used by hardware to hold the priority level flag of the
interrupt being serviced.
27
NEe
pPD78014Y Family
Figure 16. Interrupt Configurations
Type A:. Internal nonmaskable Interrupt
Interrupt _ _....._ _ _.....,
Priority
Request
~ Control Clroult
Type B: Internal maakable Interrupt
Type C: External maakable Interrupt (lNTPO)
Vector Table
AddIllSS Generator
L-_ _ _ _ _ _ _~
~==
Signal
28
NEe
pPD78014Y Family
Figure 16. Interrupt Configurations (cont)
Type D: External maskable Interrupt (except INTPO)
Vector Table
Address Generator
Interrupt _ _ _ _~
Request
'------------;~
Standby
Release
Signal
Type E: Software Interrupt
Interrupt _ _ _ _ _ _~
Request
Type F: Test Input
AbbrevlaUons:
IF: Interrupt request lIag
IE: Interrupt enable IIag
ISP: In-aarvtca p~orlty IIag
MK: Interrupt mask 118g
PRo P~orlty specify lIag
.'YIA••668(2)
29
NEe
IIPD78014Y Family
Interrupt Priority. If the watchdog timer overflow i nterrupt (INlWDT) has been initialized to be a nonmaskable interrupt, it has priority over all other interrupts.
Two hardware-controlled priority levels are available
for all maskable interrupts that generate a vectored
interrupt (i.e., all except the two testable interrupts).
Either a high or a low priority level can be assigned by
software to each of the maskable interrupts. Interrupt
requests of the same priority or a priority higher than
the processor's current priority level are held pending
until interrupts in the current service routine are enabled by software or until one instruction has been
executed after returning from the current service routine. Interrupt requests of a lower priority are always
held pending until one instruction has been executed
after returning from the current service routine.
The default priorities listed in table 3 are fixed by
hardware and are effective only when it is necessary to
choose between two interrupt requests of the same
software-assigned priority. For example, the default
priorities would be used after the completion of a
high-priority routine, if two interrupts of the same
software priority were pending.
The software interrupt, initiated by the BRK instruction, is executed regardless of the processor's priority
level and the state of the IE bit. It does not alter the
processor's priority level.
Vectored Interrupt Servicing. When a vectored interrupt is acknowledged, the program status word and
the program counter are saved on the stack, the processor's priority is set to that specified for the interrupt,
the IE bit in the PSW is set to zero, and the routine
whose address is in the interrupt vector table is entered. At the completion of the service routine, the RET!
instruction (RETB instruction for the software interrupt) reverses the process and the JlPD78014Y family
microcontroller resumes the interrupted routine.
Standby Modes
HALT, STOP, and data retention modes are provided to
reduce power consumption when CPU action is not
required.
The HALT mode is entered by executing a HALT instruction while the CPU is operating from the main
system or subsystem clock. In HALT mode, the CPU
clock is stopped while the main system and the subsystem clock continue to run. The HALT mode is released by any unmasked interrupt request (except
INTPO if register SCS = 0), a nonmaskable interrupt
request, an unmasked test input, or an external reset
pulse.
30
Power consumption may be .further reduced by using
the STOP mode. The STOP mode is entered by executing a STOP instruction while operating from the main
system clock. In STOP mode, the main system clock
input pin X1 is internally grounded stopping both the
CPU and the peripheral hardware clock. The STOP
mode is released by any unmasked interrupt request
except INTPO, a nonmaskable interrupt request, an
unmasked test input, or an external reset pulse. Any
peripheral using the main oscillator as a clock source
will also be disabled in the STOP mode and interrupts
from such a peripheral cannot be used to exit the STOP
mode. Table 4 summarizes both the HALT and STOP
standby modes.
Table 4. Standby Mode Operation Status
Item
HALT Mode
STOP Mode
Setting instruction
HALT instruction
STOP instruction
System clock when Main system or
setting
subsystem clock
Main system clock
Clock oscillator
Main system and
subsystem clocks can
oscillate; CPU clock is
stopped.
Subsystem clock can
oscillate; CPU clock
and main system
clock are stopped.
CPU
Operation stopped
Operation stopped
Ports
Maintain previous
state
Maintain previous
state
16-bit timer/event
counter
Operational from main Operation stopped
system clock
S-bit timer/event
counters
Operational from main Operational only with
Til and TI2 as count
system clock
clock
Clock timer
Operational from main Operational only with
system clock or with
fXT as count clock
fXT as a count clock
Watchdog timer
Operational from main Operation stopped
system clock
Serial interface 0
Operational from main Operational only with
system clock
external clock
Serial interface 1
Operational from main
system clock; no
automatic transm it!
receive mode
A/D converter
Operational from main Operation stopped
system clock
Operational only with
external olock; no
automatic transmit!
receive mode
External interrupts Operational except for INTPO not operational;
INTPO when its
INTPI to INTP3
operational
sampling. clock is
based on the CPU
clock
NEe
When exiting the STOP mode, a wait time occurs before
the CPU ?egins execution to allow the main system
clock oscillator circuit to stabilize. The oscillator stabilization time is selected by programming the OSTS
register with one of the five values before entering the
STOP mode. The values range from 0.98 msec to 31.3
msec at fx = 8.38 MHz.
Once in the STOP mode, power consumption can be
further minimized by lowering the power supply voltage Voo to as little as 2 V. This places the device in the
data retention mode. The contents of Internal RAM and
th~ ~egisters are retained. This mode is released by first
ralsmg Voo to the proper operating range and then
releasing the STOP mode.
pPD78014YFamily
External Reset
The JlPD78014Y family is reset by taking the RESET pin
low or by an overflow of the watchdog timer (if enabled). The RESET input pin is a schmitt-trigger input
",:,ith hysteresis characteristics to protect against spuriOUS system resets caused by noise. On power-up, the
RESET pin must remain low for a minimum of 10 JlS after
the power supply reaches its operating voltage.
There is no functional difference between an external
reset and an internal reset caused by the overflow of
the watchdog timer. In both cases, the main system
clock oscillation is stopped and the subsystem clock
oscillation continues. During reset, the program
counter is loaded with the address contained in the
reset vector (addresses OOOOH, 0001 H). Once the reset
is cleared and the oscillation stabilization time of 218/fx
has elapsed, program execution starts at that address.
31
NEe
pPD78014Y Family
ELECTRICAL SPECIFICATIONS
Capacitance
= +25°0; Voo = Vss = 0 v
TA
Absolute Maximum Ratings
TA = +25"0
Parameter
Symbol
Max
Unit
Supply voltage, Voo
-0.3 to + 7.0 V
Input
capacitance
C'N
15
pF
Supply voltage, Vpp
-0.3 to +13.5 V
20
pF
Output
capacitance
°OUT
15
pF
20
pF
P60 to P~
Input/output
capacitance
C,O
15
pF
Except P60
to P63
20
pF
PSoto~
Supply voltage, AVoo
-0.3 to Voo+ 0.3 V
Supply voltage, AVREF
-0.3 to Voo+ 0.3 V
Supply voltage, AV ss
-0.3 to + 0.3 V
Input voltage, V,l (except P60 to
P6al
-'0.3 to Voo+0.3 V
Input voltage, VI2 (PSo to P63; open
drain)
-0.3 to +16 V
Output voltage, Vo
Conditions
-0.3 to VOO+ 0.3 V
Analog input voltage, VAN
(port 1 ; analog input pin)
AVss -0.3 to AVREF+0.3 V
Output current, high; 10H
Each output pin
Total: ports 2 and 3
Total: port 0 and ports 4 to 6
Output current, low, 10L t
Each output pin
Total: P40 to P47 and
P50to P55
Total: P01 to P03 , P~, P57, and
P60to P67
Total: POl to P03 and P64 to P67
Total: ports 2 and 3
-10mA
-15mA
-15 mA
30 mA peak, 15 mA rms
100 mA peak, 70 mA rms
100 mA peak, 70 mA rms
50 mA peak, 20 mA rms
50 mA peak, 20 mA rms
Operating temperature, ToPT
-40 to +85°0
Storage temperature, TSTG
-65 to +150°0
t rms value = peak value x (duty cycle) 1/2
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent damage. The device should be operated within the limits
specified under 00 and AC characteristics.
Main System Clock Oscillator
= -40 to +85°0; Voo = 2.7 to 6.0 V; refer to figure 17.
TA
Type
Parameter
Symbol Min
Ceramic resonator Oscillation frequency (Note 1)
1)(
(Figure HA)
Oscillation stabilization time (Note 2)
1.0
Orystal resonator
(Figure HA)
1.0
External clock
(Figure 178)
Oscillation frequency (Note 1)
1)(
Typ
Max Unit Conditions
10.0 MHz V00
4.0
Oscillation stabilization time (Note 2)
ms
=
oscillator voltage range
After Voo reaches oscillator operating voltage
8.38 10.0 MHz
10
ms
30
ms
Xl inputfrequency (Note 1)
fx
1.0
10.0 MHz
Xl Input high/low-level width
txH, txL
50
500
VOO
= 4.5 to 6.0V
ns
Notes:
(1) Oscillator and Xl input frequencies are Included only to show the
oscillator characteristics. Refer to the AO Oharacteristics table
for actual Instruction execution times.
32
(2) Time required for the oscillator to stabilize after reset or STOP
mode is released. The values shown are for the recommended
resonators. Values for resonators not shown in this data sheet
should be obtained from the manufacturer's specification sheets.
NEe
pPD78014Y Family
Subsystem Clock Oscillator
TA = -40 to +85"C; Voo = 2.7 to 6.0 V; refer to figure 18.
Type
Parameter
Symbol
Crystal resonator
(Figure 18A)
Oscillation frequency (Note 1)
fXT
External clock
(Figure 18B)
Min
Typ
Max
Unit
32
32.768
35
kHz
Oscillation stabilization time (Note 2)
2
s
10
s
1.2
XT1 input frequency (Note 1)
IxT
32
100
kHz
XT1 input high/low-level width
txTH, txTL
5
15
J.lS
Notes:
(1) The oscillator and XTI Input frequencies are included only to
show the oscillator characteristics. Refer to the AC Characteristics table for actual instruction execution times.
Figure 17. Main System Clock Configurations
A. CeramldCrystal Resonator
.--<1>----1 XI
Conditions
Voo = 4.5 to 6.0 V
(2) Time required for the oscillator to stabilize after reset or STOP
mode Is released. The values shown are for the recommended
resonators. Values for resonators not shown in this data sheet
should be obtained from the manufacturer's specification sheets.
Figure 18. Subsystem Clock Configurations
•
A. Crystal Resonator
.--<1>----1 XTI
R2
Rl
B. External Clock
B. External Clock
» ......- - - - 1 XI
Do-t----I XTI
I1P074HCU04
X2
Note: When 1he Input Is an extemal clock, 1he STOP
mode can not be sat because 1he XI pin Is ccnnscted
\0 system ground (VSS).
33
NEe
pPD78014Y Family
Recommended MaIn System Clock Ceramic Resonators
TA = -40 to +85'C, refer to figure 17A
Part Number
(Notes 1 and 2)
Recommended Circuit Constant
OscillatOr Voltage Range
Frequency
C1 (pF)
C2 (pF)
Rl (Idl)
Min (V)
Max (V)
(MHz)
CSB1000J
100
100
6.8
2.7 (Note 3)
2.8 (Note 4)
6.0
1.00
CSBxxxxJ
100
100
4.7
2.7 (Note 3)
2.8 (Note 4)
6.0
1.01 to 1.25
CSAx.xxxMK
100
100
a
2.7 (Note 3)
2.8 (Note 4)
6.0
1.26 to 1.79
CSAx.xxMG (Note 3)
CSAx.xxMG093 ( Note 4)
CSTx.xxMG (Note 3)
CSTx.xxMG093 (Note 4)
100
100
a (Note 5)
a (Note 5)
100
100
a (Note 5)
a (Note 5)
a
a
2.7
2.7
2.7
2.7
6.0
6.0
6.0
6.0
1.8 to 2.44
CSAx.xxMG
CSTx.xxMGW
30
a (Note 5)
a
2.7
2.7
6.0
6.0
2.45 to 4.18
a (Note 5)
30
30
30
2.7
2.7
2.7
2.7
6.0
6.0
6.0
6.0
4.19 to 6.00
30
2.7 (Note 3)
3.0 (Note 4)
6.0
6.01 to 10.0
2.7 (Note 3)
3.0 (Note 4)
6.0
30
CSAx.xxMG (Note 3)
CSAx.xxMGU ( Note 4)
CSTx.xxMGW (Note 3)
CSTx.xxMGWU (Note 4)
CSAx.xxMT
CSTx.xxMTW
o·
a (Note 5)
a (Note 5)
a (Note 5)
a (Note 5)
30
30
a
a
a
a
a
o (Note 5)
a (Note 5)
a
Notea:
(1) Manufactured by Murata Mfg. Co., Ltd.
(4) pP078P014Yonly
(2) x.xx indicates frequency
(5) Cl and C2 are contained in the ceramic resonators.
(3) pP07801xYonly.
Recommended Subsystem Clock Crystal Resonators ("PD7801xy)
TA = -40 to +600C, refer to figure 18A
Frequency
Part Number
t
OT·38 (ITA252 EOO, load capacitanoe 6.3 pF)
t Manufactured by Oaishinku
34
(kHz)
32.768
Recommended Circuit constant
C3 (pF)
12
C4 (pF)
12
R2 (kO)
100
Oscillator Voltage Range
Min
M
2.7
Max (V)
6.0
NEe
DC Characteristics
= -40 to +85·0; Voo =
TA
pPD78014Y Family
+2.7 to 6.0 V; refer to figures 19-25
Parameter
Symbol
High-level input voltage
VIHI
VIH2
Low-level input voltage
Min
Typ
Conditions
Max
Unit
0.7Voo
Voo
V
Other than below
0.8 VOO
Voo
V
POo to PO~P22, P24 to P27,
P33, P34, RESET
VIH3
0.7Voo
15
V
P60 to P63; open-drain
VIH4
VOO-0.5
VOO
V
Xl,X2
VIH5
VOO-0.5
=
VOO
V
VOO
VOO-0.3
VOO
V
JlPD7801xY; XT1, XT2
VOO-0.2
VOO
V
JlPD78POI4Y; XT1, XT2
VILt
0
0.3Voo
V
Other than below
VIl2
0
0.2Voo
V
POo to P04, P2o, P22, P24 to P27,
P33, P34, RESET
VIl3
0
0.3VOO
V
P60 to P63; Voo
0
0.2VOO
V
P60 to PB3
VIl4
0
0.4
V
XI, X2
VIl5
0
0.4
V
XTI, XT2; VOO
0
0.3
V
XTI, XT2
V
Voo
High-level output voltage
VOHI
Low-level output voltage
VOlt
VOO-I.O
V
Voo-0.5
= 4.5 to 6.0 V
= 4.5 to 6.0V, IOH = -1.0 mA
IOH = -100JlA
V
P50 to P5], P6 0 to P63;
Voo = 4.5 to 6.0 V, IOl
0.4
V
Other than above; Voo
IOl = 1.6mA
VOl 2
0.2Voo
V
SBO, SB1, SOKO; Voo = 4.5 to 6.0 V,
open-drain, pullup resistance = I kO
VOl3
0.5
V
IUHl
3
/lA
IUH2
20
JlA
IUH3
80
JlA
lUll
-3
JlA
IUl2
-20
JlA
IUl3
-3
JlA
Output leakage current high
IlOHl
3
JlA
Output leakage current low
IlOl
-3
JlA
Mask option pullup resistor
Rl
20
40
90
kO
Software pullup resistor
R2
15
40
90
kO
500
kO
Low-level input leakage
current
•
= 4.5 to 6.0 V
2.0
High-level input leakage
current
0.4
4.5 to 6.0 V; XT1, XT2
= 15mA
= 4.5 to 6.0 V,
= 400JlA
= Voo; except XI, X2, XT1, XT2
VIN = VOO; XI, X2, XT1, XT2
VIN = 15 V; P60 to P63
VIN = 0 V; except XI, X2, XT1, XT2
VIN = OV;Xl,X2,XT1,XT2
VIN = 0 V; P60 to P63 (Note 1)
VOUT = Voo
VOUT = OV
VIN = 0 V; P60 TO P6 3, JlPD7801xY only
Voo = 4.5 to 6.0 V; VIN = 0 V, POI to P03,
bl
VIN
ports I to 5, P64 to P67
20
VOO = 2.7t04.5V; VIN = OV, POI to P03,
ports 1 to 5, P64 to PSJ
35
NEe
pPD78014Y Family
DC Characteristics (cont)
Parameter
Symbol
Power supply current
fI,IPD7801xy)
IDOl
1002
10D3
10D4
Min
Typ
Max
Unit
Conditions
7.5
22.5
mA
8.38 MHz crystal oscillation operating mode;
Voo = 5.0V ±10% (Note 2)
0.8
2.4
mA
8.38 MHz crystal oscillation operating mode;
Voo = 3.0 V ±10% (Note 3)
1.4
4.2
mA
8.38 MHz crystal oscillation HALT mode;
VOO = 5.0V ±10%
550
1650
f.1A
8.38 MHz crystal oscillation HALT mode;
Voo = 3.0V ±10%
60
120
f.1A
32.768 kHz crystal oscillation operating mode;
Voo = 5.0V ±10%, Xl STOP mode, CPU
operating from subsystem clock.
35
70
f.1A
32.768 kHz crystal oscillation operating mode;
Voo = 3.0V ±10%, Xl STOP mode, CPU
operating from subsystem clock.
25
50
f.1A
32.768 kHz crystal oscillation HALT mode; Voo
= 5.0 V ±10%, Xl STOP mode
5
10
f.1A
32.768 kHz crystal oscillation HALT mode; Voo
= 3.0 V ±10%, Xl STOP mode
20
f.1A
XTl = 0 V STOP mode when feedback resistor
is connected; Voo = 5.0 V ±10%
0.5
10
f.1A
XTl = 0 V STOP mode when feedback resistor
is connected; Voo = 3.0 V ±10%
0.1
20
f.1A
XTl = 0 V STOP mode when feedback resistor
is disconnected; Voo = 5.0 V ±10%
0.05
10
f.1A
XTl = 0 V STOP mode when feedback resistor
is disconnected; Voo = 3.0 V ±10%
9
27
mA
8.38 MHz crystal oscillation operating mode;
Voo = 5.0V ±10% (Note 2)
3
mA
8.38 MHz crystal oscillation operating mode;
Voo = 3.0V ±10% (Note 3)
1.4
4.2
mA
8.38 MHz crystal oscillation HALT mode; Voo
5.0V ±10%
=
550
1650
f.1A
8.38 MHz crystal oscillation HALT mode; Voo
3.0V ±10%
=
90
180
f.1A
32.768 kHz crystal oscillation operating mode;
Voo = 5.0 V ±10%, Xl STOP mode, CPU
operating from subsystem clock.
50
100
f.1A
32.768 kHz crystal oscillation operating mode;
Voo = 3.0V ±10%, Xl STOP mode, CPU
operating from subsystem clock.
25
50
f.1A
32.768 kHz crystal oscillation HALT mode;
Voo = 5.0V ±10%, Xl STOP mode
5
10
f.1A
32.768 kHz crystal oscillation HALT mode;
Voo = 3.0 V ±10%, Xl STOP mode
30
f.1A
XTl = 0 V STOP mode when feedback resistor
is connected; VOO = S.OV ±10%
10
f.1A
XTl = 0 V STOP mode when feedback resistor
is connected; VOO = 3.0V ±10%
1005
10DS
Power supp:y current
fI,IPD78P014y)
IDOl
1002
10D3
1004
1005
0.5
36
NEe
IIPD78014V Family
DC Characteristics (cont)
Parameter
Symbol
Power supply current
(uPD78P014y) (cont)
1006
Min
Typ
Max
Unit
0.1
30
/J.A
0.05
10
Conditions
XT1 = 0 V STOP mode when feedback resistor
is disconnected; Voo = 5.0 V ±10%
XT1 = 0 V STOP mode when feedback resistor
is disconnected; Voo = 3.0V ±10%
Notes:
(1) P60 to P63 become -200/J.A (max.) for only 1 clock cycle during
input instruction execution (no wait) and -3 /J.A (max.) during
instruction other than input.
(2) When operated in the high-speed mode with the processor clock
control register set to OOH.
Figure 19. 100 vs VO'" fx = 8.38 MHz (pPD7801xy)
Figure 20.
10.0
I
f::
..........-:
.... ................:: V_
5.0 i - - - f -
I--fr-- IOD1
I
1.0
I
I
... ~ ~ ~
r=~
i
0.5
10.0
PCC=01H(ICy=.951's)*
5.0
PCC=03H I CY =3.81!'S *
PCC=04H!ICy=7.631's)*
PCC=30H ICy=1221's)HALT Mode
V
V
1.0
0.1
0.05
f---- 1003
......-
V
= 4.19 MHz (pPD7801xy)
-
PCC = OOH (ICY = 0. 95118)*
,,- ~
~~
PCC=OlH(lcy = 1.911's)*
PCC= 02H (ICY = 3.B2JtS)*
PCC=03H (ICY =7.64JtS)*
PCC=04Hgcy = 15.271's)*
PCC=30H Icy = 1221's)**
TA=25"C;!x=4.19MHz _
fxr = 32.768 kHz
PCC=BOH(ICy=122!'Sy*
(X1 STOP)
HALT (X1 stop)
PCC
~
/
BOH(lcy = 122JtS)"
(Xl STOP)
HALT (Xl STOP)
1003
1004
0.Q1
/
10D4
0.005
/
0.005
* CPU Clock from main system clock.
CPU llOCk !roj sUbs~stem Click.
i
o"
2
345
6
Power Supply Voltage V DO (V)
7
8
0.001
* CPU clock from main system clock.
.. CPU clock from subsyslem clock.
o
2
Ell
,
.
';
I
HALT Mode
-'1002 _
TA=25°C; !X=8.38 MHz;-
fxr = 32.768 kHz
0.001
VOOI fx
PCC=02H~1 cy=1.91I'S!*
1002
<'3
I
PCC=OOH (lcy=.481's)·
100 VB
=1001
~
i
(3) When operated in low-speed mode with the processor clock
control register set to 04H.
4
7
3
5
6
Power Supply Voltags V DO (V)
37
NEe
pPD78014Y Family
Figure 21. 100 VB Voo (pPD78P014y)
10.0
5.0
....
-1001
I....
!
I .....
1.0
i/""
1002
'xr = 32.788 kHz
£}
~
_
8
10i---~~~_+-----_j_----___j
TA = 25°C; Ix= 8.38 MHz;
c
i
i"'"
PCC=OOH(tCY='48p.s)*
PCC=OlH (tCY =.9S~8)*
PCC = 02H (tCY =1.91~8)*
PCC = 03H (tCY =3.61~s)*
POC = 04H (tCY =7.631<8)*
HALT (Xl oscH laDan)
...... 1-"'..........-: :::::-----
~V
~
1
0.5
r7l
-
Figure 23. IOL VB VOL (Port 1)
I
PCC= B,H (ICY
(x1S
0.1
1.0
0.5
VOLM
0.05
HALT (Xl stop)
,
J
1000
./
Figure 24. IOL VB VOL (P6trP6a)
/'
/'
0.01
10D4
TA=25"C
301----=.::...----+----..,.+:;=--7""-__j
0.005
• CPU Clock
0.001 0
"u
i
2
CPU Cljk
3
flOm main system clock.
flOj SUbsYSj C"
456
_
7
8
Power Supply Voltage VOO M
Figure 22. IOL VB VOL (ports 0, Ports 2-5,
P6~P67)
1.0
0.5
TA=25"C
vOLM
301-----""""~r+r:_'----~-+--.....:..:-__j
Figure 25. IOH VB Voo - VOH {ports 0-5, P6~P6TJ
O!
.g, 20 i - - - - J ' F - I ' - - 7 ' l - - - - - - _ j _ - - - - _ _ _ j
~
<"
.§.
~----~----~--~I
1.0
0.5
VOLM
1.0
voo-voHM
38
NEe
IIPD78014Y Family
AC Characteristics
TA
= -40 to +85'C; VDD = 2.7 to 6 V : refer to figures 26 through 32
Parameter
Symbol
Min
Max
Unit
Cycle time
(Min. Instruction
execution time)
tCY
0.4
64
JlS
0.96
64
Jls
Operating on main system clock (JlPD7801xy)
0.48
64
JlS
Voo
1.91
64
JlS
Operating on main system clock (JlPD78POI4y)
0.4
64
Jls
TA = -40 to +40'C, Voo = 4.75 to 6.0 V;
operating on main system clock (JlPD78POI4y)
0.96
64
Jls
TA = -40 to +40'C; operating on main system
clock (JlP078POI4y)
114
TI input
frequency
frl
Typ
125
JlS
0
122
4
MHz
0
275
kHz
Tllnput highl
low-level width
100
ns
1.8
JlS
Interrupt input
high/low-Ievel
width
8/fsam (Note 1)
RESET low-level width
Conditions
= 4.5 to 6.0 V; operating on main system
clock (JlPD7801xy)
Voo
= 4.5 to 6.0 V; operating on main system
clock (JlPD78POI4Y)
Operating on SUbsystem clock
VOO
= 4.5 to 6.0 V
Voo
= 4.5 to 6.0 V
Jls
INTPO
10
Jls
INTPI to INTP3
10
Jls
KRO to KR7 (Note 2)
10
Jls
.~
Notes:
(1) By using bits 0 and 1 of the sampling clock select (SCS) register
in conjunction with bits 0 to 2 of the processor clock control
(PCC) register, fsam can be set to fx/2N+ 1 (where N = 0 to 4),
f",64, or f x/128.
(2) Port 4 falling-edge detection input.
39
NEe
IIPD78014V Family
Figure 26. Main System Clock Operation
ter va
Figure 27. Main System Clock Operation
VDD (pPD7B01xy)
=1 I I II I I I 1
=1 I I II I I I 1
3.0
3.0
P
f"P
1:
2.0
~
P
P
,
P
.. p
Ouarantaed
Ouaranfaed
Operating
I
Ran9j
(TA
r-..
o
P
..
=- 40 10 ..a5·C)
I" 1\
•
~ 1.0
\.
\.
\
0.5
\
0.4
P
Operating
TA. -40" to +85. C
0.5
p
p'p
M
I
~~
2
345
Supply Voltage Veo M
II
~
\.
\
\
.-- I
"
01"L.--.....J1"L----11"_-L1"_-L1"_..J...1"_1".l..---'rl
OA
,
1
\.
,~
2
3
4
,~:
~
5
Supply Voltage VOO M
NOIe:
When TA. -40 to +4O'C, guarantaed operaUng range
18 extended to the dolled Rna.
40
ter
VDD (pPD7BP014y)
8
VS
NEe
"PD78014Y Family
Figure 28. AC Timing Measurements Points
(except Xt and XTt)
=:x
0.8 Voo-Measurament- O.8 Voo
0.2 voo....
Points
..... 0.2 Voo
Figure 3t. Interrupt Input Timing
C
Figure 29. Clock AC Timing Points Xt and XT1
Figure 32. RESET Input Timing
X11npu1
0.4 V
XT1lnput
Figure 3D.
0.4 V
11 Timing
41
NEe'
IIPD78014Y Family
Read/Write Operation
TA
= -40 to +85"C, VOO = 2.7 to 6.0 v: refer to figures 33 through 36
Symbol
Parameter
Min
Max
Unit
ASTB high-level width
tASTH
0.5tev
ns
Address setup time to ASTB l .
lADs
0.5 tev-3O
ns
Address hold time from ASTB l
IAOH
10
Data Input time from address
ns
Load resistor;;, 5 kQ
ns
Instruction fetch
(3+2n)tcv - 100
ns
Data access
~OOI
(1+2n)tcv - 25
ns
Instruction fetch
tROD2
(2.5+ 2n)lcv - 100
ns
Data access
(2+2n)1cv -
tAOOI
IAOD2
Data Input time from RD l
Read data hold time
WAIT llnput time from RD l
5
50
0
ns
tROLl
(1.5+2n)lcv - 20
ns
tROL2
(2.5+ 2n)lcv - 20
ns
Data access
0.5 tev
ns
Instruction fetch
Data access
. tROH
RD low-level width
tRDWT1
tRDWT2
1.5tev
ns
WAIT , input time from WR ,
twRWT
0.5 tev
ns
WAIT low-level width
twn
(0.5+2n)lcv+ 10
(2+2n)lcv
ns
twos
100
ns
twOH
5
ns
Write data setup time to WR
t
Write data hold time from WR
t
WR low-level width
twRL1
(2.5+ 2n)lcv - 20
ns
RD , delay time from ASTB ,
tASTRO
0.5tev- 3O
ns
WR , delay time from ASTB ,
tASTWR
1.5tcv- 3O
t delay time from
tROAST
Icv- 1O
tcv + 40
ns
tcv + 50
ns
t (external fetch)
Address hold time from RD t (external fetch)
Write data output time from RD t
ASTB
RD
WR , delay time from write dala
Address hold time from WR
t
t delay time from WAIT t
WR t delay time from WAIT t
RD
Notes:
(1) tcv
= Icv/4
(2) n indicates number of walts.
(3) CL
42
= 100 pF
Conditions
ns
~DAOH
tcv·
tRDWO
10
twOWR
0.5tev-120
0.5 lev
ns
0.5Iev-170
0.5 lev
ns
Icv
Icv + 60
ns
ns
twRAOH
Instruction fetch
ns
Icv
Icv + 100
twTRo
0.5tev
2.5tev + 80
ns
twTWR
0.5 lev
2.5 lev + 80
ns
Voo
= 4.5 to 6.0 V
VOO
= 4.5 to 6.0 V
NEe
pPD78014Y Family
Figure 33. Read Operation; External Fetch (No Wait)
)
(
Upper 8-8ft Address
tADDt
)
lowerS-Bit
Address
tADStASTH
ASTB
L
I
..-: -tADH-
HI-Z
~-----------------~
r
(
Operation Code
"I
fl
itRDADH--
tRDDl
tRDAST
Figure 34. Read Operation; External Fetch (Wait Insertion)
Upper 8-8lt Address
k--------tADDt---------l~
HI-Z
OperatIOn Code
ASTB
83FM-9372B
43
NEe
pPD78014Y Family
Figure 35. Read/Write Operation; External Data Access (No Walt)
)
K=
Upper 8-Bft Addrass
1ADD2
)
Lower 8-B1t' ~
Add_
tADS
AS1B
___ !fl:.Z___ -<
ReedDe1a
tADH
r'-~
~
tRDH-
~!:!!:!
WrltBDe1a
-
tASTRD
I
\
I I
j.
tRDL2
J
tRDWD
I
twos
--.
I.
)0
~twDWR
\
tASlWR
C
:JJ
tWRL183FM-11373B
44
NEe
pPD78014Y Family
Figure 36. Read/Write Operation; Externa' Data Access (Wait Insertion)
)
Ae-A15
Upper 8.a~ Address
IAD02
)
Lowar8-Blt
AdeI_
~---~~---~
tADS
ReadData
H1-Z
>---
Write Data
C
C
IADH
P.
r~
AS1B
~~T
~IASTAD.
I I
I
\
~
i
IRDL2
~I
twos
..
~tWDH"
tWDWR
I.
\
I
tASTWR
tR0WT2
tWTL-'
\
I
-tWTRD~
+--IWRL1tWRWT-
- . _tWTL_
--J
~ I--tWTWR
\
83FM-93748
45
NEe
IlPD78014Y Family
Serial Interface, 3-Wire, I/O Modej Internal SCK Output
TA = -40 to +85°C; Voo = 2.7 to 6.0 V; refer to figure 37
Parameter
Symbol
Min
Unit
Conditions
SCK cycle time
tKCYl
800
ns
Voo = 4.5 to 6.0 V
3200
ns
SCK high- and low-level width
tKH1. tKll
tKCYl/2-50
ns
tKCYt/2-150
ns
ns
SI setup time to SCK
t
tSIKl
100
SI hold time from SCK t
tKSll
400
SO output delay time from SCK I
tKSOl
Typ
Max
VOO = 4.5 to 6.0 V
ns
300
ns
Voo
1000
ns
C = 100 pF (See note)
= 4.5 to 6.0
V; C
= 100 pF (See note)
Note: C is the load capacitance of the SO output line.
Serial Interface, 3-Wire, I/O Mode; External SCK Input
TA = -40 to +85°C; voo = 2.7 to 6.0 V; refer to figure 37
Parameter
Symbol
Min
Unit
Conditions
SCK cycle time
tKCY2
800
Typ
Max
ns
Voo = 4.5 to 6.0 V
3200
ns
SCK high- and low-level width
tKH2. tKl2
400
ns
1600
ns
SI setup time to SCK t
tSIK2
100
ns
SI hold time from SCK t
tKSI2
400
ns
SO output delay time from SCK I
tKS02
Note: C is the load capacitance of the SO output line.
46
Voo
= 4.5 to 6.0
V
300
ns
Voo = 4.5 to 6.0 V; C = 100 pF (See note)
1000
ns
C = 100 pF (See note)
NEe
IIPD78014Y Family
Serial Interface, SBI Mode; Internal seK Output
TA
= -40 to +85'C; voo = 2.7 to 6.0 V; refer to figure 38
Parameter
Symbol
Min
Unit
Conditions
SCK cycle time
tKCY3
800
ns
Voo
= 4.5 to 6.0 V
3200
ns
Voo
= 4.5 to 6.0 V
Voo
= 4.5 to 6.0 V
SCK hlgh- and low-level width
tKH3, tKl3
S80, S81 setup time to SCK t
tSIK3
S80, S81 hold time from SCK t
S80,S81 output delay time from SCK
~
Typ
Max
tKCY3O'2-50
ns
tKCy3f2 - 150
ns
100
ns
300
ns
tKSI3
tKCy3f2
tKS03
0
ns
250
= 4.5 to 6.0 V; R = 1 kQ
= 100 pF (See note)
R = 1 ko, C = 100 pF (See note)
Voo
ns
C
1000
0
ns
S80, S81 ~ from SCK
t
tKSB
tKCY3
ns
SCK ~ from S80, S81
~
isBK
tKCY3
ns
tSBH
tKCY3
ns
tKCY3
ns
S80, S81 high-level width
S80, S81 low-level width
tSBl
..
Note: Rand C are the load resistance and load capacitance of the
S80 and S8l output lines.
Serial Interface, SBI Mode; External SCK Input
TA = -40 to +B5'C; Voo = 2.7 to 6.0 V; refer to figure 38
Parameter
Symbol
Min
Unit
Conditions
SCK cycle time
tKCY4
800
ns
Voo
= 4.5 to 6.0 V
3200
ns
400
ns
Voo
= 4.5 to 6.0 V
1600
ns
100
ns
Voo
= 4.5 to 6.0 V
300
ns
ns
Voo
=
ns
R
SCK high- and low-level width
S80, S81 setup time to SCK
t
tKH4, tKl4
tSIK4
Typ
Max
S80, S81 hold time from SCK t
tKSI4
tKCy4O'2
S80, S81 output delay' time from' SCK ~
tKS04
0
300
0
1000
S80, S81 ~ f.rom SCK t
tKSB
tKCY4
ns
4.5 to 6.0 V; R
(See note)
=
1 kQ C
= 100 pF.
= 1 kQ C = 100 pF
ns
SCK I from S80, S81 ~
tSBK
tKCY4
ns
S80, S81 high-level width
tSBH
tKCY4
ns
S80, S81 low-level width
tSBl
tKCY4
ns
Note: Rand C are the load resistance and load capacitance of the
S80 lind S81 output lines.
47
NEe
pPD78014Y Family
Serial Interface, 2-Wire, I/O Mode; Internal ~ Output
TA" -40 to +85°0; Voo
= 2.7 to 6.0 V; refer to figure 39
Parameter
SOK cycle time
SOK high-level width
SOK low-level width
SBO, SB1 setup time to SOK
t
SBO, SB1 hold time from SOK
t
SBO, SB1 output delay time from SOK ~
Nla
Symbol
Min
Unit
CondItione
ft----0*+-
t KSOS ,8
880,1
83CL477A
Figure 4D. Berial Transfer Timing; PC Bus Mode
SCL
SOAO,SDAI
51
NEe
JlPD78014Y Family
Figure 41. Serial Interface Timing; 3-Wire Serial If0 Mode with Automatic Transmit/Receive Function
-1_---JX
DO
01
SO_02
X
::=x
t~." J~tKS-17-.8------..X
DO
SI _ _0_2_.....
IKS07.8
X
::
-+'>1
ISPS1
07
07
~
~~7~
STB
5)
Busy Processing
\
9* /
IBYS]
•
(ActiveBUSY
high) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---J
~'_~~I_S_PS_n~
_ _ _ _ _ _ __
* SCK does nol actually become low here; II Is shown this way
to Indicate timing.
83FM·9378B
52
NEe
IIPD78014Y Family
AID Converter
ov
TA = -40 to +85'C; AVoo = Voo = 2.7 to 6.0 V, AVss = Vss =
Parameter
Symbol
Min
Typ
Max
Unit
8
8
8
bit
±1.5
LSB
Resolution
Absolute accuracy (See note)
Conditions
tCONV
160/1)(
Jis
I)( =4.19 to 8.38 MHz
80ffX
Jis
fX = 1 to 4.19 MHz
Sampling time
tSAMP
24/1)(
JiS
Analog input voltage
VIAN
AVss
AVoo
v
v
1.5
mA
Conversion time
Reference voltage
AVREF
AVREF current
IREF
2.7
0.5
Note: Absolute accuracy doe.s not include the quantization error
(±1/2 LSB).
Data Memory STOP Mode; Low-Voltage Data Retention
TA = -40 to +85'C; refer to figure 42
Parameter
Data retention supply voltage
Symbol
Min
VOOOR
2.0
Data retention power supply current
IOOOR
Release signal set time
tSREL
Oscillation stabilization wait time
tWAIT
Typ
0.1
0
Max
Unit
6.0
V
10
JiA
Conditions
Ell"
•
VOOOR = 2.0 V; subsystem clock stop and
feedback resistor disconnected
Jis
2 181fx
ms
Release by RESET
(Note 1)
ms
Release by interrupt
Note:
(1) 2 131fx, 215/1)(, 216/1)(, 217/1)( or 218/1)( can be chosen by using bits
o to 2 of the oscillation stabilization time select (OSTS) register.
53
::1
I
NEe
JlPD78014Y Family
Figure 42. Data Retention Timing
A. STOP mode Is released by RESET input
Internal reset
operation
t:
t
VOO
I
II
STOP mode
HALT mode
I
I
Deta retenllOn mode - -
VOOOR
OpeI8\1on
mode
I
Execution 01
STOP InsIrucUon
\
~
tWAIT
_tSREL
B. STOP mode is released by interrupt signal
HALT mode
I
t:
t
ExecuUonof
STOP lnsIrucUon
Standby ref_signal
(Intsnupt request)
I
STOP mode
Oeta IBIenUon mode _ _
VOOOR
Opera\Ion
mode
/
tSREL
J
~
54
_
NEe
pPD78014Y Family
PROM PROGRAMMING
PROM Programming Modes
The PROM in the IlPD78P014Y is an OTP or UV EPROM.
The 32,768 x 8-bit PROM has the programmi ng characteristics of an NEC IlPD27C256A Table 5 shows the
functions of the IlPD78P014Y pins in both normal operating and PROM programming mode.
When the RESET pin is set low and Vpp is set to + 5 V or
+ 12.5 V, the IlPD78P014Y enters the programming
mode of operation. Operation in this mode is determined by the setting ofthe CE, OE, Vpp and VDD pins as
indicated in Table 6.
Table 5. Pin Functions During PROM
Programming
Function
Normal Operating Mode
Programming Mode
Address input
P40 - P47, P50. POo,
Ao-A14
Data input
P30- P37
00. 07
Chip enable/
program pulse
P6sJWR
CE
P~-P56
Output enable
P64fRD
OE
Program voltage
IC
Vpp
Mode voltage
RESET
Logical 0
Table 6. Programming Operation Modes
RESET
Vpp
voo
CE
OE
Program write
L
+12.5 V
+6V
L
H
Program verify
L
+12.5 V
+6V
H
L
Data output
Program inhibit
L
+12.5 V
+6V
H
H
High impedance
Mode
Data input
Read
L
+5V
+5V
L
L
Data output
Output disble
L
+5V
+5V
L
H
High impedanoe
Standby
L
+5V
+5V
H
L/H
High impedance
55
NEe
IIPD78014Y Family
Figure 43.
PROM Programming Mode Pin Function;
64-Pin plastic or Ceramic Shrink DIP
~PD78P014YCWIDW
64
L
L
NoIa8:
(1) L: Connect these pins separately to Vss through
resistors (10 kg).
(2) Vss: Connect to the ground.
(3) RESET: Set to the loW leval.
(4) Open: Do not connect these pins.
56
NEe
pPD78014Y Family
Flflure 4f. ",,011 ",..."""",. Mode Pin Fum:lionll; H-Pin PI••'ic QFP
o
Vss
L
Open
D4
..
Vpp
Os
De
D;o
L
Open
!1PD78P014YGC
Vss
VDD
Ao
}L
A1
Aa
A3
A4
As
15
~
~
t:
=' =g Iii 1:1 I .un: In: :UI 0; III
~
NDIw:
(1) L: Connact .... pln...parately ID Vss IhlllUgh
mllIIOII (10 IIA).
(2)
VSS: Connact ID the gnlUnd.
(3) FlESET: Set ID the low IIMII.
(4) Opan: Do not GaIIIIIICIIhnI pInI.
83CL..g44SB
57
NEe
pPD78014Y Family
PROM Write Procedure
PROM Read Procedure
Data can be written to the PROM by using the following
procedure.
The contents of the PROM can be read out of the
external data bus (Do - 07) by using the following
procedure.
(1) Set the pins not used for programming as indicated in figures 43 and 44. Set the RESET pin low
and the Voo and Vpp pins to +5 V. The CE and OE
pins should be high.
(2) Supply + 6.0 V to the Voo pin and + 12.5 V to the
Vpp pin.
(3) Provide the initial address to theAo - A14 pins.
(4) Provide the write data
(5) Provide a 1-ms program pulse (active low) to the
CE pin.
(6) Use the verify mode (pulse OE low) to test the
data. If data is written correctly, proceed to step
8; if data is not written correctly, repeat steps 4 to
6 up to 25 times. If data is still incorrect, go to step
7.
(7) Classify the PROM as defective and cease write
operation.
(8) Perform one additional write with a program
pulse width (in ms) equal to three times the number of writes performed in step 5.
(9) Increment the address.
(10) Repeat steps 4-9 until the last adress is programmed.
58
(1) Set the pins not used for programming as indicated in Figures 43 and 44. Set the RESET.2!!llow
and the Vpp pin and VDD pin to +5 V. The CE and
OE pins should be high.
(2) Input the address of the data to be read to the
Ao - A14 pins.
(3) Put an active-low pulse on CE and OE pins.
(4) Data is output to pins Do - 07.
Program Erasure
The UV EPROM can be erased
exposing the window to light
shorter than 400 nm, Including
light, and fluorescent light. To
erasure, mask the window.
(all locations FFH) by
having a wavelength
ultraviolet, direct sunprevent unintentional
Typically, data is erased by 254-nm ultraviolet rays. A
minimum lighting level of 15 W s/cm 2 (ultraviolet ray
intensity x exposure time) is required to completely
erase the written data. Erasure by an ultraviolet lamp
rated at 12,000 pW/cm 2 takes approximately 15 to 20
minutes. Remove any filter on the lamp and place the
device within 2.5 cm of the lamp tubes.
NEe
pPD78014Y Family
DC Programming Characteristics
TA = 25 ±5'C, VSS
=
OV.
Parameter
Symbol
Symbol"
Max
Unit
High-level input voltage
VIH
VIH
0.7 VOOP
VOOP
V
0
0.3 VOOP
V
10
Min
Typ
Condition
Low-level input voltage
VIL
VIL
Input leakage current
ILiP
III
/1A
0,; VI'; Voop
High-level output voltage
VOHI
VOHI
2.4
V
IOH = -400/1A
VOH2
VOH2
Voo-O.7
V
IOH
VOL
VOL
0.45
V
IOL
Low-level output voltage
Output leakage current
ILO
Voop power voltage
Voop
Vpp power voltage
Vpp
Vcc
Vpp
10
/1A
5.75
6.0
6.25
V
Program memory write mode
4.5
5.0
5.5
V
Program memory read mode
12.2
12.5
12.8
V
Program memory write mode
V
Program memory read mode
Vpp = Voop
Voop power current
Vpp power current
100
Ipp
= -100 /1A
= 2.1 mA
Icc
Ipp
0,; Vo ,; Voop, OE = VIH
5
30
mA
Program memory write mode
5
30
mA
Program memory read mode
CE = VIL, VI = VIH
5
30
mA
Program memory write mode
CE = VIL, OE = VIH
100
/1A
Program memory read mode
"Corresponding symbols of the /1PD27C256A.
AC Programming Characteristics (Write Mode)
TA = 25 ±5'C, VSS = OV, Voo =6 ±0.25V, Vpp = 12.5 ±0.3V.
Parameter
Symbol
Symbol"
Min
Address setup time to CE I
tSAC
tAS
2
Data input to OE I delay time
tOOOO
tOES
2
/1s
Input data setup time to CE I
tSIOC
tos
2
/1s
/1s
Address hold time from CE !
tHCA
tAH
2
Input data hold time from CE !
tHCIO
tOH
2
Output data hold time from OE I
tHOOO
tOF
0
Vpp setup time to CE I
tsvPC
tvps
Voop setup time to CE I
tsvOC
tvcs
Initial program pulse width
1w11
tpw
0.95
Additional program pulse width
tWL2
topw
2.85
OE I to data output time
toooo
tOE
Typ
Max
Unit
Conditions
/1S
/1s
130
ns
ms
ms
1.0
1.05
ms
78.75
ms
150
ns
• Corresponding symbols of the /1PD27C256A.
59
.'
NEe
IIPD78014Y Family
AC Programming Characteristics (Read Mode)
TA= 25 ±5'C,Vss = OV,Voo=5 ±0.5V,Vpp= VOO.
Typ
Parameter
Symbol
Symbol"
Max
Unit
Address to data output time
tOAOO
tACC
200
ns
CE = OE = VIL
CE I to data output time
tOCOO
tCE
200
ns
OE = VIL
OE I to data output time
toooo
tOE
75
ns
CE = VIL
Data hold time from OE t
tHCOO
tOF
60
ns
CE = V1L
Data hold time from address
tHAOO
tOH
ns
CE = OE = VIL
Min
o
o
Condition
" Corresponding symbols of the pPD27C256A.
AC Programming Characteristics (PROM Mode)
TA = 25 ±5'C, Vss = OV
Parameter
Symbol
PROM mode setup time
tSMA
60
Min
Typ
Max
Unit
10
ps
Condition
NEe
pPD78014V Family
PROM Timing Diagrams
PROM Write/Verify Mode
I-
x Repetitions
:
I
r--Wrtte-r--v.~fy!f---""*"--AddlUonafWdte--j
=>-- rr~
tSIOC_
Vpp
Vpp
VOOP
ElfacllY8 Address
-,
tSAC
Data
tnput
-1
~
Data
Output
I+- tHdlD
I
- ~-
r---
I+- tHOOD
K
tHCA
t~
'r~
I
-1
Data
Input
tHOIO
tSIOC
-.-I
-.I
--
I--tsvoc
['---J
f4:-tWLl
JrL
T ~tDOOO
..-tWL2_
"
NotM:
(1) VOOP must be applied before applying Vpp. It should be relllOY8d before removing Vpp.
(2) Vpp must not exceed +13'1, Including overshoot.
83YL-9382B (11193)
61
NEe
pPD78014Y Family
PROM Timing Diagrams (cant)
PROM Read Mode
Effective Address
CE
tHAOD
HI-Z
DataOulput
83Ml-6997B (7193)
PROM Mode Setting
RESET---"\
\
Vpp
tSMA
\i
AO -A14 _ _ _---JI-I\...-_
Effective_
Address
_
83YL-9381A (8193)
62
NEe
NEC Electronics Inc.
pPD78044 Family
(pPD78042/043/044/P044)
8·Bit, K·Series Microcontrollers
With FIP Controller/Driver and A/D Converter
Prel iminary
Description
The I-IPD78042, I-IPD78043, I-IPD78044, and I-IPD78P044
are members of the K-Series® of microcontrollers featuring a Flp® (VF) controller/driver, A/D converter, 8-bit
hardware multiply and divide instructions, bit manipulation instructions, four banks of main registers, an
advanced interrupt handling facility, and a powerful set
of memory-mapped on-chip peripherals.
Timing is generated by two oscillators. The main oscillator normally drives the CPU and most peripherals.
The 32.768-kHz subsystem oscillator provides time
keeping when the main oscillator is turned off. Since
CMOS power dissipation is proportional to clock rate,
the I-IPD78044 family provides a software selectable
instruction cycle time from 0.481-1s to 1221-1s. The STOP
and HALT modes turn off parts of the microcontroller
for additional savings. The data retention mode keeps
RAM contents valid down to 2.0 V.
These devices are ideally suited for applications in
portable battery-powered equipment, office automation, communications, automotive and consumer electronics, home appliances, and PC peripherals.
K-Series and FIP are registered trademarks of NEC Electronics Inc.
Features
o FIP controller/driver
- Up to 34 lines of direct-drive, high-voltage
output
- Eight software-controller intensity levels
- 48 bytes of display RAM
- Refresh of display without CPU intervention
- Key scan capability
o Eight-channel, 8-bit A/D converter
o Two-channel serial communications interface
- 8-bit clock-synchronous interface 0
Full-duplex, three-wire mode
NEC serial bus interface (S61) mode
Half-duplex, two-wire mode
-8-bit clock-synchronous interface 1
Full-duplex, three-wire mode
Automatic transfer, full-duplex three-wire
mode
o Timers; six channels
- Watchdog timer
-16-bit timer/event counter
- Two 8-bit timer/event counters usable as one
16-bit timer/event counter
September 1993
- 6-bit up/down counter for external events
- Watch (clock) timer
o 68 I/O and bidirectional I/O lines, including high
voltage lines for FIP drive
- Two CMOS input-only lines
-27 CMOS bidirectional I/O lines
- Five n-channel, open-drain I/O lines at 15 V
maximum
-16 p-channel, open-drain I/O lines at 35 V
maximum
-18 p-channel, open-drain output lines at 35 V
maximum
-Software or mask selectable pullup or pulldown
resistors available on many port lines
o Powerful instruction set
- 8-bit unsigned multiply and divide
-16-bit arithmetic and data transfer instructions
-1-bit and 8-bit logic instructions
o Minimum instruction execution times
- 0.48/0.95/1.91/3.81/7.63I-1S using 4.19-MHz main
system clock
-122l-1s using 32.768-kHz subsystem clock
o Memory-mapped on-chip peripherals
- Special function registers
o Programmable priority, vectored-interrupt
controller (two levels)
o Programmable buzzer and clock outputs
o Power-saving and battery back up
- Variable CPU clock rate
-STOP mode
-HALT mode
- 2-V data retention mode
o CMOS operation; Vee from 2.7 to 6.0 V
Internal High-Capacity ROM and RAM
78042
78043
78044
16K bytes
24K bytes
32K bytes
High-speed
RAM
512 bytes
1024 bytes
1024 bytes
1024 bytes
Serial buffer
RAM
64 bytes
64 bytes
64 bytes
64 bytes
FIP display
RAM
48 bytes
48 bytes
48 bytes
48 bytes
ROM
78P044
32K bytes
PROM
NEe
pPD78044 Family
Ordering Information
Part Number
ROM
#PD78042GF-xxx-3B9
16K mask ROM
#PD78043GF-xxx-3B9
24K mask ROM
#P078044GF-xxx-3B9
32K mask ROM
#P078P044GF-3B9
#P078P044KL-S
Package
(package Dwg)
80-pln plastic QFP
(PSOGF-80-3B9-1)
32KOTPROM
32KUV EPROM
SO-pin ceramic LCC
with window
(X80KW-8OA)
Notes:
(1) xxx Indicates ROM code suffix
(2) All devices listed are Standard Quality Grade.
2
NEe
JlPD78044 Family
Pin Configurations
SO-Pin Plastic QFP or Ceramic LCC With Windolilf
P94/F1pa
P9S/FIP5
P92/F1P4
P91/F1PS
P901F1P2
P81/F1P1
P8oIFIPO
P1141F1P22
P1151F1P23
P11a/FIP24
P1171F1P25
P120/FIP28
P1211F1P27
P1221F1P28
P12SIFIP29
P124/F1P30
P1251F1P31
P12alFlP32
P127/F1P33
voo
P2,ofSCKO
P2aISOO'SB1
P251SIOfSBO
P24IBUSY
P2s/STB
P22fSCK1
P211S01
P20fS11
RESET
P74
P7s
AVss
P17/ANI7
P1a/ANIa
P15/ANI5
P14/ANI4
--
Voo
14
15
51
41
P70
P71
P72
IC(Vpp)
POonNTPOlllo
P01nNTP1
P02nNTP2
POsnNTP3IC1O
PSolTOo
PS11T01
PS21T02
Nollie:
(1) Connect IC Onternally connactad) pin (V PP on "P078P044) to Vss.
(2) AVOO should be connactad to VOl)
(3) AVSS ahouldbaconnactadtoVSS·
83YL-95188 (VI93)
3
NEe
I'PD78044 Family
Pin Functions; Normal Operating Mode
Symbol
FIrst FunctIon
Symbol
Alternate Functions
Port 0; 5-bit, blt-selectable I/O. (Bits 0 and 4 are
input only)
INTPO
TIO
External maskable interrupt
External count clock input to timer 0
INTPI
External maskable interrupt
INTP2
External maskable interrupt
INTP3
CIO
External maskable Interrupt
Up/down counter clock input
XTI
Crystal oscillator or external clock Input for
subsystem clock
AID converter
Plo - PI7
Port I ; 8-bit, bit-selectable I/O port.
ANIO -ANI7
Analog inpufto
P20
Port 2; 8-bit, bit-selectable I/O port.
Sil
Serial data input; three-wire serial I/O mode
SOl
Serial data output; three-wire serial I/O mode
SCKI
Serial clock I/O for serial interface 1
STB
Serial Interface; automatic transmit/receive
strobe output
BUSY
Serial interface; automatic transmit/receive
busy Input
SIO
SBO
Serial data input; three-wire serial I/O mode
Two- or three-wire serial I/O mode
800
Serial data output; three-wire serial I/O mode
Two- or three-wire serial I/O mode
P2.4
SBI
P30
Port 3; 8-bit, bit-selectable I/O port.
P3:!
8CKO
Serial clock I/O for serial interface 0
TOO
Timer output from timer 0
TOI
Timer output from timer I
T02
Timer output from timer 2
Tit
External count clock input to timer I
TI2
External count clock input to timer 2
P3s
PCL
Programmable clock output
Pas
BUZ
Programmable buzzer output
par
Port 7; 5-bit,bit selectable I/O port. N-channel,
open drain.
Pao-
per
PIOo- P10s
PIGs-PIer
Port 8; 2-bit, output port. P-channel, open drain.
FIPO, FIPI
. FIP digit select outputs
Port 9; 8-bit, output port. P-channel, open drain.
FIP2 - FIPa
FIP digit select outputs
Port 10; 8-bit, output port. P-channel, open
drain.
FIPIO - FIP15
FIP digit select or segment outputs
FIP16 - FIP17
FIP segment outputs
Pl10-P117
Port 11; 8-blt, bit selectable
P-channel open drain.
VO port.
FIP18 - FIP25
FIP digit select outputs
PI20- PI2r
Port 12; 8-bit, bit selectable
P-channel open drain.
VO port.
FIP26 - FIP33
FIP digit select outputs
FIP controller/driver; pulldown resistor
connection.
RESET
External system reset input
XI
Crystal/ceramic resonator connection or
external clock input for main system clock
4
NEe
pPD78044 Family
Pin Functions; Normal Operating Mode (cant)
Symbol
First Function
X2
CrystaVceramic resonator connection or inverse
of external clock for main system clock
XT2
Crystal oscillator or left open when not using
the subsystem clock
AVREF
AID converter reference voltage
AVoo
AID converter power supply input
AVSS
AID converter ground
VOO
Power supply Input
Vpp
IlPD78P044 PROM programming power supply
Input
Vss
Power supply ground
IC
Internal connection
Symbol
Alternate Functions
--
5
NEe
pPD78044 Family
Block Diagram, I'PD78044 Family
TOOIP30
~
11011NTPQlPOO _
lS-Bltl1merf
Event Counter 0
I<=>
Pl0-P17
General Reg.
I
Watchdog l1mer
I<=>
Intemal
Program Memory
(ROMIPROM)
Note 1
Decode
and
Control
Watch11mer
SIOISB0II'25 ~
SOOISB1IP2S ~ Serlallnterfaoe 0
SCKOII'27~ L..-_ _--.J
S11IP20_
SOlIP21
P90-P9r
SCK1IP22 ~ Serlallnterfaoe 1
ST13IP23
BUSY/P24-~
________J
P1Oc-P10 7
AN10II' 10-
<=>B<=>
ANI7IP17
AVDDAVSSAVREF-~________J
INTPOITIOII'OOINTP3ICI0II'03
..-t'J Interrupt ~
'--v'1L..-_
Control
_--.J
jill
RESET VDD
VSS
P120- P127
IC
(Vpp)
Note 2
CIOIINTP3IP03 ~
¢::::>8<=>
Pll0-P117
<=>
FIP
Controllerl
Driver
FIPO-FIP33
VLOAD
Nolas:
(1) The Intemal ROM and RAM size depend on the device.
(2) Pin name In parentheses lor ~ "PD78P044 only.
83YL-9519B (9/93)
6
NEe
pPD78044 Family
FUNCTIONAL DESCRIPTION
Memory Space
Central Processing Unit
Program and data memory are mapped into the 64Kbyte address space (OOOOH-FFFFH). See figure 2. The
pPD78044 family is optimized for single-chip operation
and does not permit external memory.
The central processing unit (CPU) of the pPD7B044
family features B- and 16-bit arithmetic including an Bby B-bit unsigned multiply and a 16- by B-bit unsigned
divide (producing a 16-bit quotient and an B-bit remainder). The multiply executes in 3.B2ps and the divide in
5.97 ps using the fastest clock cycle with a 4.19-MHz
main system clock.
A CALLT vector table and a CALLF area decrease the
number of bytes in the call instructions for commonly
used subroutines. A one-byte call instruction can access up to 32 subroutines through their addresses
contained in the CALLT vector table (40H to 7FH). A
two-byte call instruction can access any routine beginning in a specific CALLF area (0800H to OFFFH).
Internal System Clock Generator
The internal system clocks of the pPD7B044 family are
derived from the main system or subsystem clock
oscillator. See figure 1. The clocks for the watch timer
and programmable clock output are derived from the
subsystem clock (fXT) or main system clock (fx). The
clocks for all other peripheral hardware are derived
from the main system clock.
The CPU clock (1)) can be supplied from the main
system clock (f0 or subsystem clock (fXT). Using the
processor clock control register (PCG), a CPU clock
frequency equal to fx, fx/2, fx/4, fx/8, fx/16 or the subsystem clock fXT can be selected. The CPU clock
selected should be based on the power supply voltage
available and the desired power consumption. On
power up, the CPU clock defaults to the lowest speed
from the main system clock and can be changed while
the microcomputer is running.
Since the shortest instruction takes two CPU clocks to
execute, the fastest instruction execution time (tCY) of
0.48 fls is achieved with a 4.19-MHz main system clock
and a Vee of 4.5 to 6.0 volts. The fastest instruction
execution time available across the full voltage range
of 2.7 to 6.0 volts is 0.96 ps with a 4.19-MHz main system
clock. For the lowest power consumption, the CPU can
be operated from the subsystem clock and the fastest
instruction execution time is 122 ps at 32.768 kHz.
Internal Program Memory
All devices in the pPD7B044 family have internal program memory. The pPD78042, pPD7B043, and
pPD78044 contain 16K, 24K, and 32K bytes of internal
ROM, respectively. The pPD78P044 contains 32K bytes
of UV EPROM or one-time programmable ROM. To allow
the pPD7BP044 to emulate the mask ROM devices, the
amount of internal program memory available in the
pPD78P044 can be selected using the memory size
switching register (IMS).
_
Internal RAM
Internal RAM comprises three types: high-speed,
buffer, and FIP display. The pPD7B042 has 624 bytes of
internal RAM and the pPD7B043/044/P044 have 1136
bytes.
High-speed RAM contains the general register banks
and the stack. Unused portions of RAM and unused
register bank locations are available for general storage. The pPD78042 has 512 bytes (FDOOH-FEFFH) of
high.speed RAM; the pPD78043/044/P044 has 1024
bytes (FBOOH-FEFFH).
All devices contain 64 bytes (FA80H-FAFFH) of buffer
RAM and 48 bytes (FA50H-FA7FH) of FIP display RAM.
The buffer area is used for the automatic transfer mode
of serial interface 1 or for general storage. The FIP
display area is for display data; unused portions are
available for general storage.
CPU Control Registers
Program Counter. The program counter is a 16-bit
binary counter register that holds the address of the
next instruction to be executed. During reset, the
program counter is loaded with the address stored in
locations OOOOH and 0001H.
Stack Pointer. The stack pointer is a 16-bit register that
holds the address of the last item pushed onto the
stack. It is decremented before new data is pushed
onto the stack and incremented after data is popped
off the stack.
7
NEe
pPD78044 Family
Figure 1. Internal System Clock Generator
XT1 n>lI4
.-
SUbsystem
IxT
Clock
XT2-
L
OscIllator
Noise
EDmlnatlon
CIrcuIt
~
Ix18 -
Programmable Clock Output Functton
Selector
Waldl TImer 3
-
Salector
1x/18_
i
J
Xl
-
X2 -
Main System
Clock
OsCIllator
Ix
watchdog lImer
.I
I
Prescaler
I
.!!. .!!. .!!. .!!.
2
4
8
18
--
Standby
Control
CIrcuit
Saledor
~
~
II
STOP
Processor Clod<
Control Re~r(PCC)
8
)
8
ClocI><0>----11-+ P-ch
oamr=t=D--1
~
P-ch
oamr=t=D--1 t-_---.--o
Voo
PUllup enable
--------1[>0
Voo
INfOUT
I
I
~ [Mask opUon)
I
m
P-ch
+-_-+--0
INfOUT
~Tn-~-1-~-~-5~.-~-7~)----------~-O-O-----;~
PUllup enable - - - - - - [ > o > - - - - j l t - P-ch
Inputenab~-------~
Dam ----~'),----111--
P-ch
.......-1.......- - 0 INfOUT
Pullup enable
-------i[>o><>----il-+
P-ch
Opendlllfn
Output disable ------L..-"
oamr=t=D--1
Outpuldlsable
~
t---1-+-"--O
INfOUT
I
~ [Mask opUon)
Voo
I
Inputenab~ ------~
rh
Pullup enable ------[>o>----t~
..
Dam---~,"""
PUllup enable
t-----t---<
-------i[>o
oamr=t=D--1 t-_---o
OUlpUldlsable~
INfOUT
INfOUT
Comparator
VREF (Threshold Voltage)
83YL·9523B·l (1!Vl13)
15
NEe
"PD78044 Family
Figure 4. Pin Input/Output Circuits (cont)
r----------l~...
INfOUT
Voo
-{
---<---- XT2)
Voo
Feedback
Cut-off
p-chl
I
I
~ [Mask opUon)
I
I
or- -- - - 0
VLOAO
: [Mask option)
rh
(XT1)
IN
(XT2)
OUT
B3YL.9523B-2 (10193)
16
NEe
pPD78044 Family
AID Converter
The pPD78044 family's analog-to-digital converter (figure 5) uses the successive-approximation method for
converting one of eight multiplexed analog inputs into
8-bit digital data The minimum conversion time per
input is 38.1 ps at 4.19-MHz operation.
The AID converter input select register (ADIS) selects
the number of inputs that are used in AID conversion.
The remaining inputs are used as ports. The analog
input to be converted is selected by programming the
AID converter mode register (ADM). Conversion is
started by external interrupt INTP3, or by writing to the
ADM register. When conversion is completed, the results are stored in the AID conversion result register
(ADCR) and an INTAD interrupt is generated.
If the AID converter was started by an external interrupt, it stops after the interrupt is generated. If the AID
converter was started by software, it repeats the conversion until new data is written to the ADM register.
Figure 5. AID Converter
•
Resistor Strtng
----------
Semple and
Hold CIrculI
,---1
Input
Selector 1---'-<>
1
1
1
1
1
1
r------'
1
(NoI82)
1
1
I:
1
1
:
L ___ --1
1
1 Tap 1
1
1
1Selector 1
1
1
1
I I !
1
1
1
1
11
1
:
1
1
1
1
T~gger
1
1
1----i.~1
Converalon
1
1
rTAVREF
1
11
1
1
1
LL
AVSS
~~~~--------~~
L-.
T~ggar
Enable
INTP3
8
NO Conversion Result
Register (ADCR)
8
Internal Bus
·Notee:
(1) Selects number of port 1 InpuIa to be used lor NO con""....on.
(2) Selects Ihe channel tor NO conversion.
83YL-95248 (9193)
17
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pPD78044 Family
Serial Interface 0
Serial interface 0 is an 8-bit, clock-synchronous interface. It can be operated in three-wire serial I/O mode,
NEC serial bus interface (S81) mode, or two-wire serial
I/O mode. Th.e serial clock can be provided from one of
eight internal clocks, the output of 8-bittimer register 2,
or external clock line SCKO. See figure 6.
Figure B. Ser/a/lnterface D
SIOI
SBOI
0
P25
SOOI
8811 CCo'J-.-lIn_-++,
P2e
FromP2e
Internal Bus
18
NEe
IIPD78044 Family
Three-Wire Interface. In the three-wire serial I/O mode,
the 8-bit shift register (SIOO) is loaded with a data byte
and eight clock pulses are generated. The clock pulse
falling edges shift the data byte out to the SOO line
(either MSB or LSB first), while the rising edges shift
data in from the SIO line, providing full-duplex operation. The INTCSIO interrupt is generated after each
8-bit transfer.
S81 Interface. The NEC SBI mode is a two-wire, highspeed, proprietary serial interface available on most
devices in the NEC pPD75xxx and pPD78xxx families.
Devices are connected in a master/slave configuration.
See figure 7. There is only one master device at a time;
all others are slaves. The master sends addresses,
commands, and data over one of the serial bus lines
(SBO or SB1) using a fixed hardware protocol synchronized with the SCKO line.
Each slave device of the pPD78044 family can be
programmed to respond in hardware to anyone of 256
addresses set in its slave address register (SVA). There
are also 256 commands and 256 data types. Since all
commands are user definable, many software protocols, simple or complex, can be defined. It is even
possible to develop commands that change a slave
into a master and the previous master into a slave.
Figure 7. SBI Mode Master/Slave Configurtlon
DD
Slav. CPU
MaslarCPU
bJ
(SBll.sao
SCK
Address 1
SCK
Slave CPU
SBO.(SB11
Address 2
f----
,
SCK
Two-Wire Interface. The two-wire serial I/O mode provides half-duplex operation using either the SBO or SB 1
line and the SCKO line. Communication format and
handshaking can be handled in software by controlling
the output levels of the data and clock lines between
transfers. For data transmission, when 8-bit shift register (SIOO) is loaded with a data byte and eight clock
pulses are generated. The falling edges shift the data
byte out either the SBO or SB1 line, MSB first. In
addition, this data byte is also shifted back into SIOO on
the rising pulse edges providing a means of verifying
that the transmission was correct.
For data reception, the SIOO register is preloaded with
the value FFH. As this data value is shifted out on the
falling edge of the serial clock, it disables the n-channel
open-drain driver. This allows the receive data to be
'
driven onto the serial line and shifted into the SIOO . .~
register on the rising edge of the serial clock. The . . . .:
INTCSIO interrupt is generated after each 8-bit transfer.
Serial Interface 1
Serial interface 1 is also an 8-bit, clock-synchronous
interface (figure 8). It can be operated in either a
three-wire serial I/O mode or a three-wire serial I/O
mode with automatic transmit/receive. The serial clock
can also be provided from one of eight internal clocks
(common clock for both interfaces), the output of 8-bit
timer register 2, or the external clock line SCK1.
Three-Wire. In the three-wire serial I/O mode, the 8-bit
shift register (SI01) is loaded with a data byte and eight
clock pulses are generated. The clock pulse falling
edges shift the data byte out of the S01 line (MSB or
LSB first) while the rising edges shift the data in from
the SI1 line, providing full-duplex operation. The INTCSli interrupt is generated after each 8-bit transfer.
Three-Wire With Auto Xmt/Rcv. In the three-wire serial
I/O mode with automatic transmit/receive, up to 64 data
bytes can be transferred with minimal CPU overhead.
The data to be transmitted and received is stored in the
buffer RAM. Handshaking over the BUSY input line or
the strobe (STB) output line, or both, can be selected
by the program. Error detection of bit drift due to noise
is available for each byte transferred when using the
BUSY input line. This automatic transmit/receive mode
is ideally suited for transferring data to!from external
peripheral devices such as on-screen display (OSD)
and LSC controller/driver devices.
19
NEe
pPD78044 Family
Figure B. Serilllinterfllce 1
CSIMI - - - . - I
I:>~-
=
SlOl WrIbI
STBIP2S
0---1---1
BUSY/P24
o}---I--'~I
HandShaking .....- - - - - - - - t - - - '
I-+~----'+------L..t-+-I--'~ INTCSII
113Y\.·9I52BB (10'93)
20
NEe
pPD78044 Family
While in three-wire serial I/O mode with automatic data
transfer, the interface can be operated full duplex or
transmit only in single or repetitive operation. In full
duplex, a data byte is transferred from the first location
in the buffer RAM and shifted out the S01 line (MSB or
LSB first) while the received data is shifted in the SI1
line and stored back in the first buffer location. After
the preset number of bytes have been transferred, the
INTCSI1 interrupt is generated.
In single-operation transmit mode, the preset number
of bytes from the buffer RAM are transmitted out the
S01 line (MSB or LSB first) and the INTCSI1 interrupt is
generated after all bytes have been transferred. In
repetitive-operation transmit mode, data in the buffer
is transmitted repeatedly.
Timers
The pPD78044 family has a 16-bit timer/event counter,
two 8-bit timer/event counters (combinable for 16-bit
operation), a 6-bit up/down counter, a watch timer, and
a watchdog timer. All except the up/down counter can
be programmed to count a number of prescaled values
of the main system clock. The watch timer can also
count the subsystem clock. All timer/event counters
and the up/down counter can count external events.
16-Bit Timer/Event Counter O. Timer/event counter 0
(figure 9) includes a 16-bit counter (TMO), a 16-bit
compare register (CROO), a 16-bit capture register
(CR01), and a timer output (TOO). Timer 0 can be used
(1) as an interval timer, (2) to count external events on
the timer input (TID) pin, (3) to output a programmable
square wave or a 14-bit pulse-width modulated output,
or (4) to measure pulse widths.
Figure 9. 16-Bit Timer/Event Counter 0
Internal Bus
D
r-----~~--~------------~INTIMO
Too/P30
TlOIPO o'
INTPO
----------+-------<>-I-~--+_+------~ INTPO
Intemal Bus
21
.~
-
.
NEe
pPD78044 Family
8-Bit Timer/Event Counters 1 and 2. Timer/event
c.ounters 1 and 2 (figure 10) each consists of an 8-bit
timer register (TM1 or TM2), an 8-bit compare register
(CR1O or CR20), and a timer output control logic (T01
or T02). The timers are controlled by registers TCl1,
TMC1, and TOC1 via five selectors. Timer/event
counters 1 and 2 each can be used as an 8-bit interval
timer, to count external events on timer input pin TI1 or
T12, or to output a programmable square wave. Also,
timers 1 and 2 can be combined as a 16-bit timer/event
counter and used as a 16-bit interval timer, to count
external events on T11, or to output a programmable
square wave on T02.
Figure 10_ 8-Bit Timer/Event Counters 1 and 2
IntemalBus
1--------~--------------------~INTTM1
8-Blt
llmer/Event
Counter 2
Output
Control logic
T02/P32
IX/4
Ix/8
Ixl16
IX/32
~----t---~INTTM2
Clear
IX/84
Ix/128
Ix/256
fx/512
I /1024
I /4096
x
x
Selector
TI2IP34*_
t--------t---~
* Rising or lalling edge can be selected.
22
T011P31
B3YL-936OB
NEe
fJPD78044 Family
6-Bit Up/Down Counter. The up/down counter (figure
11) includes counter UDC and compare register UDCC.
It cOunts external events (up or down) on the counter
input pin (CIO) and generates an interrupt (INTUD)
when the count matches the compare register. The
counter is loaded with -1 (down-count mode) or
cleared (up-count mode) upon interrupt generation.
Figure ". 6-Bit UplDown Counter
INTP:lI
INTUD
CIOlP03l
0
INTP3
B3YL-952BB (9193)
23
NEe
pPD78044 Family
Watch Timer 3. Watch timer 3 (figure 12) is a 5-bit timer
that can be used as a time source to keep track of time
of day, to release the STOP or HALT mode at regular
intervals, or to initiate any other task that must be
performed at regular intervals. When driven by the
subsystem clock, the watch timer continues to operate
in the STOP mode.
The watch timer can function as both a watch timer and
an interval timer simultaneously. In watch timing, interrupt request INTWT (not a vectored interrupt) can be
generated using the main system clock every 0.5 or 1.0
second or by using the subsystem clock every 0.5 or
0.25 second.
In interval timing, vectored interrupt request INTTM3 is
generated at preselected time intervals. With a 4.19MHz main system clock, the following time intervals
can be selected: 978ps; 1.96,3.91,7.82,15.6, or 31.3 ms.
With a 32.768-kHz subsystem clock, the following time
intervals can be selected: 488 or 978ps; 1.96,3.91,7.82,
or 15.6 ms.
Watchdog Timer. The watchdog timer (figure 13) can
also perform interval timing. As a watchdog timer, it
protects against inadvertent program run-away. It can
be selected to generate a nonmaskable interrupt (INTWDT), which vectors to address 0004H, or to generate
an internal reset signal, which vectors to the restart
address OOOOH if the timer is not cleared by the program before it overflows. Eight program-selectable
intervals based on the main system clock are available.
With a 4.19-MHz main system clock, they are 0.489,
0.978, 1.96, 3.91, 7.82, 15.6, 31.3, and 125 ms. Once
initialized and started, the timer cannot change modes
and can be stopped only by an external reset.
In interval timing, maskable interrupts (INTWDT), which
vector to address 0004H, are generated repeatedly at a
preset interval. The time intervals available are the
same as in the watchdog timer mode.
Programmable Clock Output
The pPD78044 family has a programmable clock output
(PCl) that can be used as carrier output for remote
controlled transmissions or as clock output for peripheral devices. The main system clock (fx) divided by 8,
16,32, 64, 128, or 256 or the subsystem clock (fXT) can
be output on the PCl pin. With a4.19-MHz main system
clock, the following frequencies are available: 524, 262,
131, 65.5, 32.7, and 16.4 kHz. With a 32.768-kHz subsystem clock, 32.768 kHz is also available. See figure
14.
24
Buzzer Output
The pPD78044 family also has a programmable buzzer
output (8UZ). The buzzer output frequency can be
programmed to equal the main system clock (fx) divided by 1024, 2048, or 4096. With a 4.19-MHz main
system clock, the buzzer can be set to 4.1, 2.0, or 1.0
kHz. See figure 15.
FIP Controller/Driver
The pPD78044 family can directly drive up to 34 FIP
(fluorescent indicator panel) display output lines of
which 9 to 24 segments and 2 to 16 digits can be
selected through software. The number of digits is
selected by display mode register 0 (DSPMO) and the
number of segments by display mode register 1
(DSPM1). If an attempt is made to select a total of more
than 34 digit and segment outputs, the digit selection
will take priority. Any unused pins can be used as
outputs or I/O depending on the type.
There are 48 bytes of display data RAM mapped from
FA50H to FA7FH. Each display memory bit corresponds to a specific display element. Any bits not used
for FIP display can be used for general purpose.
Segment and digit signal output is automatically controlled by a DMA operation from the FIP controller to
the display data RAM. The display cycle period is
1024/fx or 2048/fx. Register DSPM1 selects the display
cycle and one of eight intensity levels. The on-chip
circuitry controls the intensity level by varying the
driving signal pulse width.
The on-chip circuitry has been designed to allow easy
interface to a keyboard. At the end of the display cycle,
vectored interrupt INTKS is generated and the controller outputs key scan data (ports 11 and 12) on segment
output pins FIP18 to FIP33. Flag KSF indicates key scan
or display timing to the key scan software routine.
Pulldown resistors for all FIP lines are mask-selected
and can be connected to VLOAD or Vss. Pulldown
resistors for FIPO to FIP17 lines are incorporated in the
pPD78P044 and are connected to VLOAO.
NEe
pPD78044 Family
Figure 12. Watch Timer3
-
r----
Selector
xf28 _
fw f2 9
fw f28
SeIactor
!HIft
1lmer
I fwf213
r---- INlWT
'--~
crear
-~
Selector
fwf2 7
fW
Pl8S08Ier
fxr-
fwf28
Selector
INTIM3
fw f2 5
-~
fw f24
i
I
1
H
fw f214
1lmer Clock Select
ResPler 2 (TCL2)
Olear
+
II I
I
)
I
watch TImer Mode
Control Regleler (lMC2)
Internal Bus
~
•
I
,
Figure 13. Watchdog Timer
INlWDT
MaskabIa
Interrupt
Request
Selector
~-------------~------~ RES~
INlWDT
Nonmaskable
Inlerrupt
Request
Internal Bus
83Yl.-853011 (9183) .
25
NEe
pPD78044 Family
Figure 14. Programmable Clock Output
'x123 - - - - + I
'x124 - - - - + I
'x125 - - - - + I
'x128 ---~ Selector
'XI27---~
'x128 - - - - + I
txT
-----l~
Figure 15. Buzzer Output
'x1210 ---~
'X12 11 ---~ Selector
'XI212---~
26
1------------")_____-1
NEe
IIPD78044 Family
Figure ftl. FlP Conlrolle,/Dr/".,
Port Output LaICh
F1PO
F1P 1
F1P83
83YL-8\I31B (l1I93)
pPD78044 Family
Interrupts
The IlPD78044 family has 14 maskable hardware interrupt sources: four are external, nine are internal, and
one (INlP3/1NTUD) can be set for either external or
internal. Thirteen of them cause a vectored interrupt;
one testable input-only generates an interrupt request.
All 14 maskable interrupts can be used to release the
HALT mode except INTPO (when SCS = 0) and INTKS;
all except INTKS and INlPO can release the STOP
mode.
In addition, there is one nonmaskable interrupUromthe
watchdog timer, one software interrrupt, and a RESET
interrupt. The watchdog timer overflow interrupt (interrupt vectortable address 0OO4H) can be initialized to
be a nonmaskable interrupt or the highest default
priority maskable interrupt. The software interrupt generated bY the BRK instruction is not maskable. See
table 3 and figure 17.
Table 3. Interrupt Sources and Vector Addresses
Type of
Requelt
Default
Priority
Restart
28
location
Vector
Interrupt
Addre.. Configuration
OOOOH
RESET
RESET Input pin
External
Watchdog timer overflow (when reset mode
selected)
Internal
INTWDT
Watchdog timer cwerflow
(when nonmaskable interrupt selected)
Internal
OO04H
A
INTWDT
Watchdog tim~r overflow
(when Interval timer selected)
Internal
0004H
B
INTPO··
Extemallnterrupt edge detection
External
0006H
C
2
INTPI
Exterhallnterrupt edge detection
External
0008H
D
3
INTP2
External Interrupt edge detection
External
OOOAH
0
4
INTP3
External interrupt edge detectl!!n
External
OOOCH
D
INTUD
Up/down counter coincidence signal
Int.rnal
5
INTCSIO
End of clocked serial Interface 0 transfer
Internal
6
INTCSII
End of clocked serial interface 1 transfer
7
INTTM3
Watch timer reference time interval signal
B
INTTMO
9
10
0
B
OOOEH
B
Internal
0010H
B
Internal
0012H
B
16-blt timer/event count.r coincidence signal
Internal
0014H
B
INTTMI
B-blt timer/event counter 1 coincidence signal
Int.rnal
0016H
B
INTTM2
B-bit timer/event counter 2 coincidence 8ignal
Internal
001BH
B
11
INTAD
End of AID conversion
Internal
001AH
B
12
INTKS
Key scan Interrupt generated by FIP controller
Internal
001CH
B
BRK instruction
Internal
003EH
E
Clock timer overflow
Internal
Software
Test input
Interupt Source
INTWDT
Nonmaskable
Maskable
Signal Name
INTWT
F
NEe
pPD78044 Family
Figure 17. Interrupt Configuration
Type A: Internal nonmaskable Interrupt
Interrupt _ _--.._ _ _ _~
Request
Standby
' - - - - - - - - - - - - - - Release
Signal
Type B: Internal maskable Interrupt
Vector Table
Address Generator
'--------------l~
Standby
Release
Signal
Type c: External maskable Interrupt (lNTPO)
Vector Table
Address Generalor
'-------------l~
Standby
Release
Signal
83YL-9366B(1)
29
NEe
pPD78044 Family
Figure 17. Interrupt Configuration (cont)
Type D: External maskablelnterrupt (except INTPO)
Interrupt _ _ _ _~
Request
'--------=
Signal
Type E: Software Interrupt
Interrupt _ _ _ _ _ _~
Request
Type F: Test Input
}---~=
Signal
.----.....-
Abbrevlallons:
IF: Interrupt request nag
IE: Interrupt enable nag
ISP: In-aarvlce prtorlty nag
MK: Interrupt mask ftag
PRo Prtorlty specify nag
30
NEe
Interrupt Servicing. The ~P078044 family provides
two levels of programmable hardware priority control
and services all interrupt requests except the testable
interrupt (INTWT) using vectored interrupts. The programmer can choose the priority of servicing each
maskable interrupt by the interrupt control registers.
Interrupt Control Registers. The ~P078044 family has
three 16-bit interrupt control registers. The interrupt
request flag register (IFO) contains an interrupt request
flag for each interrupt. The interrupt mask register
(MKO) is used to enable or disable any individual interrupt. The priority flag register (PRO) can specify a high
or a low priority level for each interrupt except the
testable interrupt (INTWT).
Three other 8-bit registers are associated with interrupt
processing. The external interrupt mode register
(INTMO) selects a rising or falling edge (or both) as the
valid edge for external interrupts INTPO, INTP1, and
INTP2 (INTP3 is always falling edge). The sampling
clock select register (SCS) selects a sampling clock for
the noise eliminator circuit on external interrupt INTPO.
The IE and ISP bits of the program status word also
control interrrupts. If the IE bit is zero, all maskable
interrupts are disabled. The IE bit can be set or cleared
by the EI or 01 instruction, respectively, or by directly
writing to the PSW The IE bit is cleared each time an
interrupt is accepted. The ISP bit is used by hardware
to hold the priority level flag of the interrupt being
serviced.
Interrupt Priority. If the watchdog timer overflow interrupt (INTWOl) has been initialized to be a nonmaskable interrupt, it has priority over all other interrupts.
Two hardware-controlled priority levels are available
for all maskable interrupts that generate a vectored
interrupt (that is, all except the testable interrupt).
Either a high or a low priority level can be assigned by
software to each of the maskable interrupts.
Interrupt requests of the same priority or a priority
higher than the processor's current priority level are
held pending until interrupts in the current service
routine are enabled by software or until one instruction
has been executed after returning from the current
service routine. Interrupt requests of a lower priority
are always held pending until one instruction has been
executed after returning from the current service routine.
The default priorities in table 3 are fixed by hardware;
they are effective only when necessary to choose
between two interrupt requests of the same softwareassigned priority. For example, after the completion of
pPD78044 Family
a high-priority routine, if two interrupts of the same
software priority were pending.
The software interrupt, initiated by the BRK instruction, is executed regardless of the procesor's priority
and the state of the IE bit. It does not alter the processor's priority.
Vectored Interrupt Servicing. When a vectored interrupt is acknowledged, the program status word and
the program counter are saved on the stack, the processor's priority is set to that specified for the interrupt, the IE bit in the PSW is set to zero, and the routine
whose address is in the interrupt vector table is entered. At the completion of the service routine, the REll
instruction (RETB instruction for the software interrupt) reverses the process and the pP078044 family
microcomputer resumes the interrupted routine.
Standby Modes
II!IIIIIIII"
~<
I
The HALT, STOP, and data retention modes reduce
power consumption when CPU action is not required.
The HALT mode is entered by executing a HALT instruction while the CPU is operating from the main
system or subsystem clock. In HALT mode, the CPU
clock is stopped while the main system and the subsystem clock continue to run. The HALT mode is released by any unmasked interrupt request (except
INTPO if register SCS = 0 and INTKS), a nonmaskable
interrupt request, an unmasked test input, or an external reset pulse. '
Power consumption may be further reduced by the
STOP mode. The STOP mode is entered by executing a
STOP instruction while operating from the main system clock. In STOP mode, the main system clock input
pin X1 is internally grounded, stopping both the CPU
and the peripheral hardware clock. The STOP mode is
released by any unmasked interrupt request except
INTPO and INTKS, a nonmaskable interrupt request, an
unmasked test input, or an external reset pulse.
Any peripheral using the main oscillator as a clock
source will also be disabled in the STOP mode and
interrupts from such a peripheral cannot be used to
exit the STOP mode. Table 4 summarizes the HALT and
STOP standby modes.
When exiting the STOP mode, a wait time occurs before
the CPU begins code execution to allow the main
system clock oscillator circuit to stabilize. The oscillation stabilization time is selected by. programming the
OSTS register with one of five values before entering
the STOP mode and ranges from 212/fx to 217/fx seconds.
31
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pPD78044 Family
Table 4. Standby Mode Operation Status
Item
HALT Mode
STOP Mode
Setting instruction
HALT instruction
STOP instruction
System clock when setting
Main system or subsystem clock
Main system clock
Clock oscillator
Main system and subsystem clocks can
oscillate; CPU clock is stopped.
Subsystem clock can oscil/ate; CPU and main
system clocks are stopped.
Operation stopped
CPU
Operation stopped
Ports
Maintain previous state
Maintain previous state
lS-bit timer/event counter
Operational from' main system clock
Operation stopped
B-bit timer/event counters
Operational from main system clock or with Til
and TI2 selected as the count clock
Operational only with Til and TI2 as count
clock
S-bit up/down counter
Operable
Operable
FIP controller/driver
Inoperable
Inoperable
Watch timer
Operational from main system clock or with fXT
as coulit clock
Operational only with fXT as count clock
Watchdog timer
Operational from main system clock
Operation stopped
Serial interface 0
Operational from main system clock or with
. external clock
Operational only with external clock
Serial interface 1
Operational from main system clock or with
external clock; no automatic transmit/receive
mode
AID converter
Operational frQm main system clock
Operation stopped
External interrupts
Operational except for INTPO when its sampling
clock is based on the CPU clock
INTPO not operational; INTPl to INTP3
operational
Once in the STOP mode, power consumption can be
further minimized by lowering the power supply voltage Voo to 2 volts. This places the device. in the data
retention mode. The contents of internal RAM and the
registers are retained. This mode' is released by first
raising Voo to the proper operating range and then
releasing the STOP mode.
External Reset
The JiPD78044 family is reset by taking the RESET pin
low or by an overflow of the watchdog timer (if enabled). The RESET input pin is a Schmitt trigger input
with hysteresis characteristics to protect against spurious system resets by noiSe. On power-up, the RESET
pin must remain low for 10 Jis minimum after the power
supply reaches its operating voltage.
There is no functional difference between an external
reset and an internal reset caused by watchdog timer
overflow. In both cases, the main system clock oscillation is stopped and the subsystem clock oscillation
continues. During reset, the program counter is loaded
with the address in the reset vector (addresses OOOOH,
0001 H). Once the reset is cleared and the oscillation
stabilization time of 217/fx has elapsed, program execution starts at that address.
32
Operational only with external clock; no
automatic transmit/receive mode
NEe
NEG Electronics Inc.
IIPD78054 Family
(pPD78052/053/054/P054)
8-Bit, K·Series Microcontrollers
With UART, A/D and D/A Converters
Prel iminary
Description
The I1PD78052, I1PD78053, I1PD78054, and I1PD78P054
are members of the K-Series® of microcontrollers featuring an AID and a D/A converter, UART, 8-bit hardware multiply and divide instructions, bit manipulation
instructions, four banks of main registers, an advanced
interrupt handling facility, and a powerful set of
memory-mapped on-Chip peripherals.
Timing is generated by two oscillators. The main oscillator normally drives the CPU amd most peripherals.
The 32.768-kHz subsystem oscillator provides time
keeping when the main oscillator is turned off. Since
CMOS power dissipation is proportional to clock rate,
the 78054 family provides a software selectable instruction cycle time from 0.40 liS t0122 liS. The STOP
and HALT modes turn off parts of the microcontroller
for additional power savings. The data retention mode
keeps RAM contents valid down to 2.0 volts.
These devices are ideally suited for applications in
portable battery-powered eqUipment, office automation, communications, consumer electronics, home
appliances, and fitness equipment.
September 1993
o 691/0 lines
- Two CMOS input-only lines
- 63 CMOS bidirectionalI/O lines
- One real-time output port operable in one 8-bit
or two 4-bit units
- Four n-channel, open-drain I/O lines at 15 V
maximum
-Software selectable pull up resistors on 63 lines
- Mask option pullup resistors on four lines
available on ROM versions
o External memory expansion
- 64K bytes total memory space
o Powerful instruction set
- 8-bit unsigned multiply and divide
-16-bit arithmetic and data transfer instructions
-1-bit and 8-bit logic instructions
o Minimum instruction execution times:
- 0.4/0.8/1.6/3.216.4 lis program selectable using
5-MHz main system clock
-122I1S using 32.768-kHz subsystem clock
o Memory-mapped on-chip peripherals
- Special function registers
K-Series Is a registered trademark of NEe Electronics, Inc.
o Programmable priority, vectored-interrupt
controller (two levels)
Features
o Programmable buzzer and clock outputs
o Eight-channel 8-bit A/D converter
o Two-channel 8-bit D/A converter
- Real-time output capability
o Three-channel serial communication interface
- 8-bit clock-synchronous interface 0
Full-duplex, three-wire mode
Half-duplex, two-wire mode
NEC serial bus interface (S61) mode
- 8-bit clock-synchronous interface 1
Full-duplex, three-wire mode
Automatic transfer, full-duplex, three-wire mode
-Serial interface 2
Full-duplex, three-wire mode
UARTmode
o Timers: five channels
- Watchdog timer
-16-bit timer/event counter
- Two 8-bit timer/event counters usable as one
16-bit timer/event counter
- Watch (clock) timer
50624
o Power saving and battery back up
- Variable CPU clock rate
-STOP mode
-HALT mode
- 2-V data retention mode
o CMOS operation; Vee from 2.7 to 6.0 V
Internal High-Capacity ROM and RAM
ROM
78052
78053
78054
16K bytes
24K bytes
32K bytes
512 bytes
1024 bytes
1024 bytes
1024 bytes
32 bytes
32 bytes
32 bytes
32 bytes
PROM
High-speed
78P054
32K bytes
RAM
Serial buffer
RAM
•
NEe
pPD78054 Family
Ordering Information
Part Number
ROM
Package
JlPD78052GC-xxx-3B9
16K mask ROM
80-pin plastic QFP
saOGC-65-3B9-1
JlPD78053GC-xxx-3B9
24K mask ROM
80-pln plastic TQFP
P80GK-50-BE9-1
80-pin ceramic LCC w/Window
X80KW-65A
JlPD78054GC-xxx-3B9
32K mask ROM
JlPD78P054GC-3B9
32KOTPROM
JlPD78052GK-xxx-BE9
16K mask ROM
JlPD78053GK-xxx-BE9
24Kmask ROM
JlPD78054GK-xxx-BE9
32K mask ROM
JlPD78P054GK-BE9
32K OTP ROM
JlPD78P054KK-T
32K IN EPROM
Notes:
(I) xxx indicates ROM code suffix
(2) All devices listed are standard quality grade
2
NEe
pPD78054 Family
Pin Configurations
SO-Pin Plastic QFp, Plastic TQFp, or Ceramic LCC
P1sfANI5
P1efANIB
P17fANI7
AVSS
P13ofANOO
P131fAN01
RESET
P12)ofRTP7
P12efRlP6
P12sfRlP5
4
P1~fRlP4
P12;lfRlP3
P122fRlP2
P121fRlP1
P12ofRlPO
AVREF1
P7ofSI2fRxD
P71fS02fTxD
P721SCK2fASCK
P2ofSI1
P21fS01
P22fSCK1
P2WSTB
P33f111
P2,veUSY
P2sfSIOfSBO
P2efSOOfSB1
I'27fSCKO
P4cfADo
P41fAD1
No...:
(1) Comact IC (Internally connected) pin ry ppon I'PD78P054) to V
(2) AVDD should be connected 10 V DO.
(3) AVSS should be connected IoVSS'
-
P37
P3e/BUZ
PSsfPCL
P34/ll2
P32fT02
P311T01
P3ofTOO
Pa7fASTB
PeeJWAlT
P6sIWR
ss
83RC-95488 (9193)
3
!
NEe
pPD78054 Family
Pin Functions; Normal Operating Mode
Symbol
Firat Function
Symbol
Alternate Function
Port 0; B-blt, bit selectable VO port
(Bits 0 and 7 are input only)
INTPO
TIO
External maskable Interrupt
External count clock Input to timer 0 or timer 0
capture trigger to capture registers CROO and CROl
INTPl
TIOl
External maskable interrupt
Timer 0 capture trigger to capture register CROO
INTP2
INTP3
External maskable interrupt
P0 1
INTP4
INTP5
INTP6
P1o- P17
XTl
Crystal oscillator or external clock input for
subsystem clock
Port 1; B-bit, bit-selectable VO port
ANI0-ANI7
Analog input to A/D converter
Port 2; B-bit, bit-selectable VO port
Sil
Serial data Input three-wire serial VO mode
SOl
Serial data output three-wire serial I/O mode
SCKI
Serial clock I/O for serial interface 1
STB
Serial interface automatic transmit/receive strobe
output
P2s
P30
Port 3; B-blt, blt-selectable VO port
BUSY
Serial interface automatic transmit/receive busy Input
SIO
SBO
Serial data input three-wire serial I/O mode
213-wire serial VO mode
SOO
SBl
Serial data output three-wire serial VO mode
2/3-wlre serial VO mode
SCKO
Serial clock VO for serial interface 0
TOO
Timer output from timer 0
TOI
Timer output from timer 1
T02
Timer output from timer 2
Til
External count clock input to timer 1
TI2
External count clock input to timer 2
P3s
PCL
Programmable clock output
P3s
BUZ
Programmable buzzer output
ADo-ADr
Low-order B-bit multiplexed address/data bus for
external memory
Port 4; B-bit VO port
P50- P5r
Port 5; B-bit, bit selectable VO port
Port 6; B-bit, bit selectable (P60 to P63
n-channel, open-drain VO with mask option
pullup resistors; P64 - P67 VOl. See note.
High-order B-blt address bus for external memory
RD
External memory read strobe
WR
External memory write strobe
ASTB
Address strobe used to latch address for external
memory
External memory wait signal input
4
NEe
pPD78054 Family
Pin Functions; Normal Operating Mode (cant)
Symbol
First Function
Symbol
Alternate Function
P70
Port 7; 3-bit • bit-selectable I/O port
SI2
RxD
Serial data input three-wire serial I/O mode
Asynchronous serial data input
S02
TxD
Serial data output three-wire serial 1/0 mode
Asynchronous serial data output
SCK2
ASCK
Serial clock 1/0 for serial interface 2
Asynchronous serial clock input
Port 12; 8-bit selectable 1/0 port
RTPORTP7
Rea~time
Port 13; 2-bit selectable 1/0 port
ANOD.
ANOI
Analog output for D/A converter
RESET
External system reset input
XI
CrystaVceramic resonator connection or
external clock input for main system clock
X2
CrystaVceramic resonator connection or
inverse of external clock for main system
clock
XT2
Crystal oscillator or left open when not
using the subsystem clock
port
-
AID converter reference voltage
D/A converter reference voltage
AVoo
AID converter power supply input
AVss
AID and D/A converter ground
Voo
Power-supply input
Vpp
JlPD78P054 PROM programming powersupply input
Vss
Power-supply ground
IC
Internal connection
Note: See table 2 and figure 4 for details.
5
NEe
pPD78054 Family
Block Diagram
'TOM'30
llOOllNlPOIPOO
1l0llNlP11P01 ---,-L-_ _ _--J
T01IP31
TI1IP33
General Reg.
Internal
Program Mernol)l
(ROMIPROM)
Note 1
S11IP20 _ _
S01IP21
SCK1IP22
STBIP2a
BUSYIP24
ANIO/P10·
ANI7IP1 7
AVec
AVSS
AVREFO
o-
AN00/P13
AN01/P131
AVSS
i
I I I
RESET Vee
VSS
IC
(Vpp)
Access
AVREF1
RTPOIP12oRTP7IP127
NoteB:
(1) Internal ROM 8nd RAM size dependent on \he devloe.
(2) PIn nama In parentheses for \he ~pe78P054 only.
B3RC-9545B (BI93)
6
NEe
pPD78054 Family
FUNCTIONAL DESCRIPTION
Central Processing Unit
The central processing unit (CPU) of the pPD78054
family features 8- and 16-bit arithmetic including an 8 x
8-bit unsigned multiply and 16 x 8-bit unsigned divide
(producing a 16-bit quotient and an 8-bit remainder).
The multiply executes in 3.2 ps and the divide in 5 ps
using the fastest clock cycle with a main system clock
of 5.0 MHz.
A CALLT vector table and a CALLF area decrease the
number of bytes in the call instructions for commonly
used subroutines. A 1-byte call instruction can access
up to 32 subroutines through their addresses contained in the CALLT vector table (40H to 7FH). A 2-byte
call instruction can access any routine beginning in a
specific CALLF area (0800H to OFFFH).
Internal System Clock Generator
The internal system clocks of the pPD78054 family are
derived from either the main system or the subsystem
oscillator. See figure 1. The clocks for the watch timer
and programmable clock output are derived from either
the subsystem clock (fXT) or the main system clock. The
clocks for all other peripheral hardware are derived
from the main system clock.
Figure 1. Internal System Clock Generator
FromPCC
I--fXT
_ _ _ _ _ _ _ _ _ _ _ _ _ _-.-_ _ _ _ _ _ _ _ WatchTImer,Progammable
Clock Oulpul
' - -_ _---,/ Clocks to Perlpheral Hardware
Slandby
Conlrol
Watt Conlrol
Circuli
Circuli
TO Subsyelam
INTPO
Clock Oscillator
Sampling Clock
CPU Clock
STOP
83RC-9552B (9193)
7
NEe
pPD78054 Family
The CPU clock (CP) can be supplied from either the main
system clock (fx) or the subsystem clock (fXT)' A selector, which is controlled by the oscillation mode selection register (OSMS), determines whether the main
system clock (fx) or the scaled main system clock (fx/2)
is provided to the prescalar (fxx). Using the processor
clock control register (PCC), a CPU clock frequency
equal to fxx, fxx/2, fxx/4, fxx/8, fxx/16 or the subsystem
clock fXT can be selected. The CPU clock selected
should be based on the power supply voltage available
and the desired power consumption. On power up, the
CPU clock defaults to the lowest speed from the main
system clock (fxx/16 with fxx = fx/2) and can be
changed while the microcomputer is running.
Since the shortest instruction takes two CPU clocks to
execute, the fastest minimum instruction execution
time (tCY) of 0.4 J.ls is achieved with a main system clock
at 5.0 MHz (fxx = fx) and a Vee of 4.5 to 6.0 volts.
However, if the watch timer must generate an interrupt
every 0.5 or 0.25 seconds, tCY is 0.48 J.ls at 4.19 MHz
with fxx = fx. The fastest minimum instruction execution time available across the full voltage range of 2.7to
6.0 volts is 0.96 J.ls with a 4.19 MHz main system clock
(fxx = fx). For the lowest power consumption, the CPU
can be operated from the subsystem clock and the
minimum instruction execution time is 122J.lS at 32.768
kHz.
Memory Space
The J.lPD78054 family has a 64K-byte address space
(see figure 2). This address space (OOOOH-FFFFH) can
be used as both program and data memory.
Internal Program Memory
All devices in the J.lPD78054 family have internal program memory. TheJ.lPD78052/053/054co·ntain 16K, 24K,
and 32K bytes of internal ROM, respectively. The
J.lPD78P054 contains 32K bytes of UV EPROM or one
time programmable ROM. To allow the J.lPD78P054 to
emulate the mask ROM devices, the amount of internal
program memory available in the J.lPD78P054 can be
selected using the memory size switching register
(lMS).
Internal RAM
The pPD78052 has 544 bytes and the J.lPD78053/054/
P054 have 1056 bytes of Internal RAM. This Internal RAM
consists of two types: high-speed Internal RAM and
buffer RAM.
The J.lPD78052 contains 512 bytes (FDOOH to FEFFH)
while the J.lPD78053/054/P054 contai n 1024 bytes
8
(FBOOH to FEFFH) of high-speed Internal RAM. The
high-speed Internal RAM contains the general register
banks and the stack. The remainder of the high-speed
Internal RAM and any unused register bank locations
are available for general storage.
All devices also contain 32 bytes of buffer RAM (FACOH
to FADFH). The buffer RAM is used for the automatic
transfer mode of serial interface 1 or for general storage.
To allow the J.lPD78P054 to emulate the mask ROM
devices, the amount of high-speed Internal RAM available in the J.lPD78P054 can also be selected using the
IMS.
External Memory
The J.lPD78054 family can access 0, 256, 41<, 16K or all
available bytes of external memory. The J.lPD78054
family has an 8-bit wide external data bus and a 16-bit
wide external address bus. The low-order 8 bits of the
address bus are multiplexed and also provide the 8-bit
data bus and are supplied by port 4. The high-order
address bits of the 16-bit address bus are taken from
port 5 as required. The address latCh, read, and write
strobes, and the external WAIT signal are supplied by
port 6.
The memory expansion mode register (MM) controls
the size of external memory. It can be programmed to
use 0, 4, 6, or 8 bits from port 5 for the high-order
address. Any remaining port 5 bits can be used for I/O.
The MM register also can be used to specify one
additional wait state or the use of the external WAIT
signal for low-speed external memory or external peripheral devices.
When only internal ROM and RAM are used and no
external memory is required, ports 4, 5 and 6 are
available as general purpose I/O ports.
CPU Control Registers
Program Counter. The program counter is a 16-bit
binary counter register that holds the address of the
next instruction to be executed. During reset, the
program counter is loaded with the address stored in
locations OOOOH and 0001H.
Stack Pointer. The stack pointer is a 16-bit register that
holds the address of the last item pushed onto the
stack. It is decremented before new data is pushed
onto the stack and incremented after data is popped
off the stack.
NEe
I'PD78054 Family
Program Status Word. The program status word
(PSW) is an a-bit register that contains fl~gs that .are
set or reset depending on the results of an instruction.
This register can be written to or read from a bits at a
time. The individual flags can also be manipulated on a
bit-by-bit basis. The assignment of PSW bits follows.
o
7
IE
ISP
CY
Carry flag
In-service (interrupt) priority flag
Register bank selection flags
Auxiliary carry flag
Zero flag
Interrupt request enable flag
ISP
RBSa, RBS1
AC
Z
IE
l
Figure 2. Memory Map
OOOOH
OOOOH
Internal
Program
Memory
(ROMIPROM)
003FH
OO4OH
007FH
~
:
Register
addressing
Use
Prohibited
f
r
Internal
High-Speed
RAM
Oaneral
FFOOH
Special
FUnction
Register
(SFR)
add1a1ng
v----
Program Area
J
11
saddr Addressing
I
FE20H
~
1
FEFFH. Registers I
SFR
..
Program
Memory
Space
Buffer
RAM
Note 2
FEDFH
FEEOH
_
CALLF Entry
Area
Use
Prohibited
FADFH
FAEOH
I
::r
Note
FABFH
FACOH
+'
'I
•
Program Area
OFFFH~-----i
1000H
External
Memory
FA7FH
FASOH
CALLT Table Area
1
Note 1
1) Direct Addressing
2) Regl8lerlndlrect
Addresslng
3)Baeed Index
addresslng
Interrupt Vector
AddI8ll8 Table Area
OOSOH
07FFH,
OSOOH
Cy
r---.....
I
::i::: t---------;;:;.;-.;;;.;:FEFFH
FFOOH
32 Bytes of
T
Short Direct
___~FF~1F~H~_ _SF_R~Area
_ _~
~
FFFFH
NoItIII:
(1) 3FFFH on "PD78052
5FFFH on "PD78053
7FFFH on "PD780541P054
(2) FCFFH on "PD78052
FAFFH on "PD7805310541P054
9
NEe
pPD78054 Family
General Registers
Figure 3. General Registers
FEEOH Register
Bank
3
2
FEFFH
0
\
_
!E~
forM!
For16-B~
Procasafng
ProcaasIng
(R1)A
(RO)X FEF8H -
(R3)B
(R2)C
(RP1)BC
FEFAH
(R5)D
(R4)E
(RP2)DE
FEFCH
(R7)H
(Re)L
(RP3)HL
FEFEH
F.!§F~
-
-
_____
(RPO) AX
FEF8H
)=Absolute Name
The general-purpose registers (figure 3) consist of four
banks of registers located at addresses FEEOH to
FEFFH in Internal RAM. Each bank consists of eight
8-bit general registers that can also be used in pairs to
function as four 16-bit registers. Two bits in the PSW
(RBSO and RBS1) specify which of the register banks is
active at any time and are set under program control.
Registers have both functional names (A, X, B, C, 0, E,
H, or L for 8-bit registers and AX, BC, DE, and HL for
16-bit registers) and absolute names (R1, RO, R3, R2,
RS, R4, R7, or R6 for 8-bit registers and RPO, RP1, RP2,
or RP3 for 16-bit registers). Either the functional or
absolute register names can be used in instructions
that use the operand identifiers rand rp.
Addressing
The program memory addressing (ROM) modes provided are relative, immediate, table indirect and register addressing. The operand addressing modes provided are implied, register, direct, short direct (saddr),
special function (SFR), register indirect, based, based
indexed, and stack addressing.
The SFR addressing and saddr addressing modes use
direct addressing and require only 1 byte in the instruction to address RAM. Normally a 6SK byte address
space requires 2 bytes to address it. One-byte addressing results in faster access times, since the instructions
are shorter. SFR addressing addresses the entire 256byte SFR address space from FFOOH to FFFFH. Saddr
addressing (see figure 2) addresses the 256-byte address space FE20H to FF1FH. FE20H to FEFFH are
composed of· 224 bytes of internal high speed RAM;
FFOOH to FF1FH contain the first 32 bytes in the special
function register area
10
One-byte addressing is accomplished by using the first
byte of the instruction for the opcode (and one operand if register A or AX is used) and the second byte of
the instruction as an address (offset) into the 2S6-byte
area. If register A or AX is used, the instructions are 2
bytes long, thereby providing fast access times. If
immediate data is used, the instruction will be 3 or 4
bytes long depending upon whether the immediate
data is a byte or a word. Many 16-bit SFRs are in the
space FFOOH to FF1FH. Using AX as an operand to
these SFRs will provide fast access, since·the instructions will be only 2 bytes long.
Special Function Registers
The input/output ports, timers, capture and compare
registers, and mode and control registers for both the
peripherals and CPU are collectively known as special
function registers. They are all memory-mapped between FFOOH and FFFFH and can be accessed either
by main memory addressing or by SFR addressing.
FFOOH to FF1H can also be accessed using saddr
addressing. They are either 8 or 16 bits as required, and
many of the 8-bit registers are bit addressable. Table 1
lists the special function registers.
Input/Output Ports
Each device in the pPD78054 family has 69 port lines.
Table 2 lists the features of each port and figure 4
shows the structure of each port pin.
NEe
pPD78054 Family
Table t. Special Function Registers
Access Units (Bits)
R/W
1
8
R/'N
x
x
OOH
R/'N
x
x
OOH
R/'N
x
x
x
OOH
x
OOH
x
Undefined
R/'N
x
x
x
Undefined
R/'N
x
x
Undefined
R/'N
x
x
x
x
OOH
x
x
OOH
Address
Register (SFR)
Symbol
FFOOH
Port 0
PO
FF01H
Port 1
PI
FF02H
Port 2
P2
FF03H
Port 3
P3
R/'N
FF04H
Port 4
P4
R/'N
FF05H
Port 5
P5
FF06H
Port 6
P6
FF07H
Port 7
P7
FFOCH
Port 12
P12
R/W
FFOOH
Port 13
P13
R/'N
FF10H·FF11H
Capture/compare register 00
CROO
R/W
FFI2H·FFI3H
Capture/compare register 01
CROI
R/W
FFI4H·FFI5H
16·blt timer register
TMO
R
16
State After Reset
OOH
x
x
x
Undefined
FF16H
Compare register 10
CR10
R/W
x
FF17H
Compare register 20
CR20
R/'N
x
Undefined
FF18H
8·blt timer register 1
TMI
R
x
x
OOH
x
x
Undefined
OOH
FF19H
8·blt timer register 2
TM2
R
FFI8H·FFI9H
16·blt timer register
TMS
R
FFIAH
Serial I/O shift register 0
SIOO
R/'N
x
Undefined
FF1BH
Serial I/O shift register 1
SIOI
R/W
x
Undefined
FF1FH
NO conversion result register
AOCR
R
Undefined
FF20H
Port mode register 0
PMO
R/'N
FF21H
Port mode register 1
PMl
R/'N
x
x
x
x
x
FF22H
Port mode register 2
PM2
R/'N
x
x
FFH
FF23H
Port mode register 3
PM3
R/W
Port mode register 5
PM5
RIW
FF26H
Port mode register 6
PM6
R/'N
FF27H
Port mode register 7
PM7
R/'N
FF2CH
Port mode register 12
PM12
R/W
FF20H
Port mode register 13
PM13
R/'N
FF30H
Rea~time
output port buffer register L
RTBL
R/'N
FF31H
Real·time output port buffer register H
RTBH
R/'N
FF34H
Rea~time
RTPM
R/'N
x
FF36H
Real·time output port control register
RTPC
R/'N
x
FF40H
Timer clock select register 0
TCLO
R/'N
x
FF41H
Timer clock select register 1
TCLI
R/'N
FF42H
Timer clock select register 2
TCL2
R/'N
FF43H
Timer clock select register 3
TCL3
R/'N
FF47H
Sampling clock select register
SCS
R/W
FF48H
16·blt timer mode control register
TMCO
R/'N
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
FFH
FF25H
x
x
x
x
x
x
output port mode register
x
x
•
Undefined
OOH
OOOOH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
88H
OOH
OOH
11
NEe
pPD78054 Family
Tabl_ 1. Specl., Function Registers (conI)
Access Units (Bits)
Address
Register (SFR)
Symbol
R/W
1
8
FF49H
S·bit timer mode control register
TMC1
RfW
x
x
OOH
FF4AH
Watch timer mode control register
TMC2
RfW
x
x
OOH
FF4CH
Capture/compare control reg Iter 0
CRCO
RfW
x
x
04H
FF4EH
16·blt timer output oontrol register
TOCO
RfW
x
x
OOH
FF4FH
8·blt timer output control register
TOC1
RfW
x
x
OOH
FF60H
Serial operating mode register 0
CSIMO
RfW
x
x
OOH
FF61H
Serial bus Interface control register
SBIC
RfW
x
x
OOH
FF62H
Slave address register
SVA
RfW
FF63H
Interrupt timing specify register
SINT
RfW
16
State After Reset
x
Undefined
x
x
OOH
FF68H
Serial operation mode register 1
CSIM1
RfW
x
x
OOH
FF69H
Automatic data transmit/receive control
register
ADTC
RfW
x
x
OOH
FF6AH
Automatic data transmit/receive address
pointer register
ADTP
RfW
x
OOH
FF6BH
Automatic data transmission/reception
interval specification register
ADT1
RfW
x
x
OOH
FF70H
Asynchronous serial Interface mode register
ASIM
RfW
x
x
OOH
FF71H
Asynchronous serial Interface status register
ASIS
R
x
x
OOH
FF72H
Serial Interface operating mode register 2
CSIM2
RfW
x
x
OOH
FF73H
Baud rate generator control register
BRGC
RfW
x
OOH
FF74H
(Note 1)
Transmit shift register
Serial
shift register
Receive buffer register
TXS
SI02
AXB
W
RfW
x
x
x
FFH
FFH
FFH
FF80H
AID converter mode register
ADM
RfW
x
01H
FF84H
AID converter Input select register
ADIS
RfW
x
OOH
FF90H
D/A converter data register 0
DACSO
RfW
x
OOH
FF91H
D/A converter data register 1
DACS1
RfW
FF98H
D/A oonverter mode register
DAM
FFDOH·FFDFH
External SFR access area (Note 2)
FFEOH
Interrupt flag regl8ter L
IFOL
FFE1H
Interrupt flag register H
IFOH
FFEOH·FFE1 H
Interrupt flag register
IFO
RfW
FFE2H
Interr uptflag register 1L
IF1L
FFE4H
Interrupt mask flag register L
MKOL
FFE5H
Interrupt mask flag register H
FFE4H-FFE5H
va
R
x
x
OOH
RfW
x
x
OOH
RfW
x
x
Undefined
RfW
x
x
OOH
RfW
x
x
OOH
x
OOOOH
RfW
x
x
OOH
RfW
x
x
FFH
MKOH
RfW
x
x
Interrrupt mask flag register
MKO
RfW
FFE6H
Interrupt mask flag regl8ter 1L
MK1L
RfW
x
x
FFH
FFE8H
Priority order specify flag register L
PROL
RfW
x
x
FFH
FFE9H
Priority order specify flag regl8ter H
PROH
RfW
x
x
FFE8H·FFE9H
Priority order specify flag regl8ter
PRO
RfW
FFEAH
Priority order specify flag register 1L
PR1L
RfW
12
FFH
x
FFH
x
x
x
FFFFH
FFFFH
FFH
NEe
pPD78054 Family
Table 1. Special Function Registers (cant)
Access Units (Bits)
Address
Register (SFR)
Symbol
R/W
8
FFECH
External interrupt mode register 0
INTMO
R/W
x
OOH
FFEDH
External interrupt mode register 1
INTM1
R/W
x
OOH
FFFOH
Memory size switch register
IMS
W
x
(Note 3)
FFF2H
Oscillation mode select register
OSMS
R/W
x
OOH
x
16
State After Reset
FFF3H
Pullup resistor option register H
PUOH
R/W
x
x
OOH
FFF6H
Key return mode register
KRM
R/W
x
x
02H
FFF7H
Pullup resistor option register L
PUOL
R/W
x
x
OOH
FFF8H
Memory expanded mode register
MM
R/W
x
x
10H
FFF9H
Watchdog timer mode register
WDTM
R/W
x
x
OOH
FFFAH
Oscillation stabilization time select register
OSTS
R/W
x
04H
FFFBH
Processor clock control register
PCC
R/W
x
04H
x
•
Notes:
(1) SI02 can be used instead ofTXS and RXB. SI02 is not a register;
it is another symbol which can be used to reference the TXS and
RXB registers. Awriteto SI02 causes the CPU to write to the TXS
register, and a read from SI02 causes the CPU to read the AXB
register.
(2) The external access area cannot be accessed using SFR addressing. It can only be accessed using main memory addressing.
(3) Value after reset depends on device
IlPD78052: 44H
IlPD78053: C6H
IlPD78054: C8H
IlPD78P054: C8H.
Table 2. Digital Port Functions
Port
Operational Features
Configuration
Direct Drive Capability
Software Pull up Resistor Connection
(Note 1)
Port 0 (Note 3)
8-bit input or output
Bit selectable
Byte selectable, input bits only
Port 1 (Note 2)
8-bit input or output
Bit selectable
Byte selectable, input bits only
Port 2
8-bit input or output
Bit selectable
Byte selectable, input bits only
Port 3
8-bit input or output
Bit selectable
Byte selectable, input bits only
Port 4
8-bit input or output
Byte selectable
PortS
8-bit input or output
Bit selectable
LED
Byte selectable, input bits only
Port 6
8-bit input or output
(P6a - P63 n-channel)
Bit selectable
LED (P6a-P63)
Byte selectable, input bits only
P6a - P63 - mask option only (Note 4)
P64 - P&, - software
Port 7
3-bit input or output
Bit selectable
Byte selectable, input bits only
Port 12
8-bit input or output
Bit selectable
Byte selectable, input bits only
Port 13
2-bit input or output
Bit selectable
Byte selectable, input bits only
Byte selectable, input bits only
Notes:
(1) Software pullup resistors can be internally connected (only on a
port-by-port basis) to port bits set to input mode. Pullup resistors are not connected to port bits set to output mode.
(2) Pullup resistors are automatically disconnected on pins used for
AID converter analog inputs.
(3) POa and POl are input only and do not have a software pullup
resistor. When using PO] as an input, the feedback resistor for the
subsystem clock should be disconnected with bit 6 (FRC) of the
processor control register (PCC).
(4) All devices except IlPD78P054
13
NEe
,.,PD78054 Family
Figure 4. Pin Input/Output Circuits
Type 2 (POo. RESET)
Voo
puBUp anable
-------11>
Voo
IN
0
j90-----'~~
dam
[=f=D--1
;-;---0 IN/OUT
OUtputdlsable~
Schmitt t~gger Input with hysteresis ChsracteMtics
Type5oA(P2 1. P23' P30- P32. P3S-P37. PSo- PS7. P64- P67. P71.
P120-P127)
Typelll-A (P2S- P27)
Voo
Voo
pullup enable
puRup enable
I>
I>
Voo
dam
Voo
IN/OUT
IN/OUT
open drain
output disable
Input enable
Type 11 (Pl0- P17)
Type 50E (P40· P47)
VOO
pullup enable
Voo
I>
Voo
dam
pullup enable
I>
IN/OUT
Voo
dam
output disable
IN/OUT
Comparator
output disable
VREF (Threshold Voltage)
Input enable
14
BSRc..9548B·l (1M13)
NEe
,.,PD78054 Family
Figure 4. Pin Input/Output Circuits (cont)
Type 12·A (P13o· P131)
punup enable
-------!>>------I~~
[Mask Option)
+--_-+---0
output disable
[>-J
INIOUT
data _ _ _ _ _
output disable
-
,---...--<>
INIOUT
N~h
Vee
----ai41B
the main or subsystem clock of 0.5 or 0.25 seconds.
When used as an interval timer, vectored interrupt
request INTTM3 is generated at preselected time intervals. With a main system clock of 4.19 MHz and fxx = fx
or if using the subsystem clock of 32.768 kHz, the
following time intervals can be selected: 48911 s, 978 lis,
1.96 ms, 3.91 ms, 7.82 ms or 15.6 ms.
The watch timer can function as both a watch timer and
an interval timer simultaneously. When used as a watch
timer, interrupt request INlWT can be generated using
25
NEe
pPD78054 Family
Figure 14.
Watch Timer 3
, -_ _ _ _... Selector
,)O(n7_
'---1-'~n~9l-r---l
I n8
L::;::::..r=~
Selector
INTWT
Clear
, n7
Selector I-I-'-'W........,~I Prescaler ,
'xr-
nS
Selector t---I------t--------i---INTTM3
, nS
To la-Bit
, n4
TIrnerlEvent
Counter Clrouft
Clear
Intema/Bus
83RC-9539B (9193)
Watchdog Timer. The watchdog timer (figure 15) can
be used as either a watchdog timer or an interval timer.
When used as a watchdog timer it protects against
program runaway. It can be selected to generate a
nonmaskable interrupt (INTWOT), which vectors to address 0004H, or to generate an internal reset signal,
which vectors to the restart address OOOOH if the timer
is not cleared by the program before it overflows. Eight
program-selectable intervals based on the main system clock are available. With a main system clock of
4.19 MHz and fxx = fx, they are 0.489,0.978, 1.96,3.91,
7.82, 15.6,31.3, and 125 ms. With a main system clock of
4.19 MHz and fxx = fx/2, they are 0.978, 1.96,3.91,7.82,
~~,~, ~1.3, 62.6, and 250 ms. Once the watchdog timer is
Initialized and started, the timer's mode cannot be
changed and the timer can only be stopped by a reset.
When used as an interval timer, maskable interrupts
(INTWOT) which vector to address 0004H are generated
repeatedly at a preset interval. The time intervals available are the same as in the watchdog timer mode.
26
Programmable Clock Output
The JlP078054 family has a programmable clock output
(PCL) that can be used for carrier output for remote
controlled transmissions or as a clock output for peripheral devices. The main system clock (fxX> divided
by 1,2, 4, 8, 16, 32, 64, or 128 or the subsystem clock
(fXT) can be output on the PCL pin. See figure 16. If the
main system clock is 4.19 MHz and fxx = fx, the
following frequencies are available: 4.19 MHz, 2.1 MHz,
1.05 MHz, 524 kHz, 262 kHz, 131 kHz, 65.5 kHz, and 32.7
kHz. With a main system clock of 4.19 MHz and fxx =
fx/2, the following frequencies are available: 2.1 MHz,
1.05 MHz, 524 kHz, 262 kHz, 131 kHz, 65.5 kHz, 32.7 kHz
and 16.4 kHz. With a subsystem clock of 32.768 kHz,
32.768 kHz is also available.
NEe
pPD78054 Family
Flgul'fl ,.. "'tclJdog Time,
Run
INlWDT
f
PreIcIIer
Maskable
Inter!Upl
Request
8
f~7
Control
SeIacIar
logic
f~
r---------t---
RESET
f~8
INlWDT
Nonmeskable
Interrupt
f~11
Request
InIamaiBUI
'xx ----..
fX1lf2 - -......
f~2 _ _---;...
fxxI23 ----..
fxx/2" ----..
1'#12' - - - - I..
1X1lf28 ----l~
1X1lf27
----l-t
'xf----..
N,EC
pPD78054 Family
Figure 17. Buzzer Output
1'AXf29
1'AXf210 -----;~ Selector
1---------,>____-/
1'AXf211 -----,~
Figure 1B. Real-Time Output Port
InIamaI Bua
INTP2
1N11M1
1N11M2
ReaI·Tlme Output Buffer
RegIster HIgher 4 BIIs
(RlBH)
Real-TIme 0u1put Buffer
RegtsI8r Lower 4 BIIs
(RlBI.)
Real-TIme Port Mode RegIster
(RTPM)
P120
28
-------------
P127
NEe
pPD78054 Family
Buzzer Output
The IlPD78054 family also has a programmable buzzer
output (BUZ). The buzzer output frequency can be
programmed to be equal to the main system clock (fxx)
divided by 512, 1024, or 2048. With a main system clock
of 4.19 MHz and fxx = fx, the buzzer can be set to 8.2,
4.1 or 2.0 kHz. With a main system clock of 4.19 MHz
and fxx = fx/2, the buzzer can be set to 4.1, 2.0, or 1.0
kHz. See figure 17.
Real-Time Output Port
The real-time output port (figure 18) shares pins with
port 12. Each bit of port 12 is specified by the real-time
output port mode register (RTPM) to be used in the port
mode or real-time output port mode. If the real-time
output port mode is selected, the real-time output port
control register (RTPC) is used to specify the high and
low nibbles to be treated separately or together. In the
real-time output port mode, the previously written data
in the real-time output buffer registers (RTBH, RTBL) is
transferred to the output latch simultaneously with the
generation of either a timer interrupt (INTTM1, INTTM2) or external interrupt (INTP2).
Interrupts
The IlPD78054 family has 21 maskable hardware interrupt sources; 8 are external and 13 are internal. Of
these 21 interrupt sources, 19 cause a vectored interrupt while the 2 testable inputs only generate an
interrupt request. All of the 21 maskable interrupts can
be used to release the HALT mode except INTPO. INTPO
cannot be used to release the STOP mode and cannot
release the HALT mode when SCS = O. In addition,
there is one nonmaskable interrupt from the watchdog
timer, one software interrupt, and a reset interrupt. The
watchdog timer overflow interrupt (interrupt vector
table address 0004H) can be initialized to be a nonmaskable interrupt or the highest default priority maskable interrupt. The software interrupt, generated by the • . . .
BRK instruction, is not maskable. See table 3 and figure
19.
Table 3. Interrupt Sources and Vector Addresses
Type of
Request
Default
Priority
Restart
Interrupt Source
Location
Vector
Address
OOOOH
Interrupt*
Confi guration
RESET
RESET input pin
External
INTWDT
Watchdog timer overflow (when reset mode
selected)
Internal
INTWDT
Watchdog timer overflow
(when nonmaskable interrupt selected)
Internal
0004H
A
0
INTWDT
Watchdog timer overflow
(when interval timer selected)
Internal
0004H
B
INTPO
External interrupt edge detection
External
OOOSH
C
2
INTPl
External interrupt edge detection
External
0008H
0
3
INTP2
External interrupt edge detection
External
OOOAH
0
4
INTP3
External interrupt edge detection
External
OOOCH
0
5
INTP4
External interrupt edge detection
External
OOOEH
0
S
INTP5
External interrupt edge detection
External
0010H
0
7
INTPS
External interrupt edge detection
External
0012H
0
8
INTCSIO
End of clocked serial interface 0 transfer
Internal
0014H
B
9
INTCSll
End of clocked serial interface 1 transfer
Internal
001SH
B
10
INTSER
Serial interface 2 UART reception error
Internal
0018H
B
11
INTSR
End of serial interface 2 .UART reception
Internal
00lAH
B
INTCSl2
End of serial interface 2 thre&-wi re transfer
Nonmaskable
Maskable
Signal
Name
12
INTST
End of serial interface 2 UART transmission
Internal
001CH
B
13
INTTM3
Watch timer reference time interval signal
Internal
00lEH
B
14
INTTMOO
lS-bit timer/event counter capture/compare (CROO)
coincidence signal
Internal
0020H
B
29
NEe
pPD78054 Family
Table 3. Interrupt Source. and Vector Addre.... {cont}
Type of
Request
Default
Priority
'SIgnal
Name
Maskable
15
Interrupt Source
location
Vector
Addre••
INTTM01
16-bit timer/event counter capture/compare (CR01)
coincidence signal
Internal
0022H
B
16
INTTM1
8-blt timer/event counter 1 coincidence .ignal
Internal
0024H
B
17
INTTM2
8-blt timer/event counter 2 coincidence signal
Internal
0026H
B
18
INTAO
End of AID conversion
Internal
0028H
B
BRK instruction
Internal
003EH
E
INTWT
Watch timer overflow
Internal
F
INTPT4
Port 4 falling edge detection
External
F
Scftware
Test Input
I.
* See figure 19
Interrupt Servicing. The JlP078054 family provides
two levels of programmable hardware priority control
and services all interrupt requests, except the two
testable interrupts (INTWT and INTPT4) using vectored
interrupts. The programmer can choose the priority of
servicing each maskable Interrupt by using the interrupt control registers.
Interrupt Control Registers. The JlP078054 family has
three 3-byte interrupt control registers. The interrupt
request flag registers (IFOL, IFOH, and IF1 L) contain an
interrupt request flag for each interrupt. The interrupt
mask registers (MKOL, MKOH, and MK1 L) are used to
enable or disable any individual interrupt. The priority
flag registers (PROL, PROH, and PR1L) can be used to
specify a high or a low priority level for each interrupt
except the two testable interrupts (INTWT and INTPT4).
Five other B-bit registers are associated with interrupt
processing. The key return mode register (KRM) contains the KRIF interrupt request flag associated with
falling-edge detection on port 4 and the KRMK mask
flag used to enable or disable clearing of the standby
mode if a falling edge is detected on port 4. The
external interrupt mode registers (INTMO and INTM1)
are used to select a rising, falling, or both edges as the
valid edge for each of the external interrupts INTPO to
INTP6. The sampling clock select register (SCS) Is used
to select a sampling clock for the noise eliminator
circuit on external interrupt INTPO.
The IE and the ISP bit of the program status word are
also used to control interrupts. If the IE bit is 0, all
maskable interrupts are disabled~ The IE bit can be set
or cleared using the EI and 01 Instructions, respectively, or by directly writing to the PSW The IE bit is
cleared each time an interrupt Is accepted. The ISP bit
is used by hardware to hold the priority level flag of the
interrupt being serviced.
Interrupt Priority. If the watchdog timer overflow interrupt (INlWOT) has been Initialized to be a nonmask30
Interrupt*
Configuration
able interrupt, it has priority over ali other interrupts.
Two hardware-controlled priority levels are available
for ali maskable interrupts that generate a vectored
interrupt (i.e., all except the two testable interrupts).
Either a high or a low priority level can be assigned by
software to each of the maskable interrupts.
Interrupt requests of the same priority or a priority
higher than the processor's current priority level are
held pending until interrupts in the current service
routine are enabled by software or until one instruction
has been executed after returning from the current
service routine. Interrupt requests of a lower priority
are always held pending until one instruction has been
executed after returning from the current service routine.
The default priorities listed in table 3 are fixed by
hardware and are effective only when it is necessary to
choose between two interrupt requests of the same
software-assigned priority. For example, the default
priorities would be used after the completion of a
high-priority routine, if two interrupts of the same
software priority were pending.
The software Interrupt, initiated by the BRK instruction, is executed regardless of the processor's priority
level and the state of the IE bit. It does not alter the
processor's priority level.
Vectored Interrupt Servicing. When a vectored interrupt is acknowledged, the program status word and
the program counter are saved on the staCk. the processor's priority is set to that specified for the interrupt,
the IE bit in the PSW is set to zero, aM the routine
whose address is in the interrupt vector table is entered. At the completion of the service routine, the RET!
instruction (RETB instruction for the software interrupt) reverses the process and the JlP078054 family
microcomputer resumes the Interrupted routine.
NEe
pPD78054 Family
Figure 19. Interrupt Configurations
Type A: Internal nonmaskable Intenvpt
Interrupt - -.......- - - - . 1
Request
Type B: Internal maskable Interrupt
..
'---------~~=
Signal
Type
c:
External maskable Interrupt (lNTPO)
Vector Table
Address Generator
'--------.. ==
Signal
B3Rc-&1B-1
31
NEe
pPD78054 Family
Figure 19. Interrupt Configurations {contJ
Type D: External maskable Interrupt (except INTPO)
Vector Table
Interrupt _ _ _----;~
Address Generator
Request
'------------l~
Type E: Softw_lnterrupt
Interrupt _ _ _ _ _ _~
Request
Type F: Test Input
I-----,~
r----L_
Abbreviations:
IF: Interrupt request flag
IE: Interrupt enable flag
ISP: In-eervlce priority flag
MK: Interrupt mask fleg
PRo Pdorlty epecIfy flag
32
standby
Release
SIgnal
standby
Release
Signal
NEe
"PD78054 Family
Standby Modes
Table 4. Standby Mode Operation Status
HALT, STOP, and data retention modes are provided to
reduce power consumption when CPU action is not
required.
Item
The HALT mode is entered by executing a HALT instruction while the CPU is operating from the main
system or subsystem clock. In HALT mode, the CPU
clock is stopped while the main system and the subsystem clock continue to run. The HALT mode is released by any unmasked interrupt request, a nonmaskable interrupt request, an unmasked test input, or an
external reset pulse.
Power consumption may be further reduced by using
the STOP mode. The STOP mode is entered by executing a STOP instruction while operating from the main
system clock. In STOP mode, the main system clock
input pin X1 is internally grounded stopping both the
CPU and the peripheral hardware clock. The STOP
mode is released by any unmasked interrupt request
(except INTPO if register SCS = 0), a nonmaskable
interrupt request, an unmasked test input, or an external reset pulse. Any peripheral using the main oscillator
as a clock source will also be disabled in the STOP
mode and interrupts from such a peripheral can not be
used to exit the STOP mode. Table 4 summarizes both
the HALT and STOP standby modes.
When exiting the STOP mode, a wait time occurs before
the CPU begins code execution to allow the main
system clock oscillator circuit to stabilize. The oscillation stabilization time is selected by programming the
OSTS register with one of five values before entering
the STOP mode; the values range from 0.8 msec to 52.4
msec at fx = 5 MHz.
HALT Mode
STOP Mode
Setting instruction HALT instruction
STOP instruction
System clock when Main system or
setting
subsystem clock
Main system clock
Clock oscillator
Main system and
subsystem clocks can
oscillate; CPU clock is
stopped.
Subsystem clock can
oscillate; CPU clock
and main system
clock are stopped.
CPU
Operation stopped
Operation stopped
Ports
Maintain previous
state
Maintain previous
state
l6-bit timer/event
counter
Operational from main
system clock, or with
watch timer output, or
TIOO selected as the
count clock
Operational only with
watch timer output or
TIOO selected as count
clock.
S-bit timer/event
counters
Operational from main Operational only with
system clock or with
TIl and TI2 selected
Til and TI2 selected
as count clock
as the count clock
Watch timer
Operational from main Operational only with
system clock or with
fXT as count clock
fXT as count clock
Watchdog timer
Operational from main Operation stopped
system clock
Serial Interface 0
Operational from main Operational only with
external clock
system clock or with
external clock
Serial interface 1
Operational from main
system clock; no
automatic transmit!
receive mode
Serial interface 2
Operational from main Operation stopped
system clock or with
external clock
A/D converter
Operational from main Operation stopped
system clock
D/A converter
Operational
Operational
Rea~time
Operational
Operational with
external trigger or
when Til and TI2
count clocks are
selected
port
output
Operational only with
external clock; no
automatic transmit!
receive mode
External interrupts Operational except for INTPO not operational;
INTPl tolNTP6
INTPO when its
operational
sampling clock is
based on the CPU
clock
33
.i
I~
pPD.78054 Family
Once in the STOP mode, power consumption can be
further minimized by lowering the power supply voltage Voo to 2 volts; This places the device in the data
retention mode. The contents of Internal RAM and the
registers are retained. This mode is released by first
raising Voo to the proper operating range and then
releasing the STOP mode.
External Reset
The IIPD78054 family is reset by taking the RESET pin
low or by an overflow of the watchdog timer (if enabled). The RESET input pin is a schmitt-trigger input
with hysteresis characteristics to protect against spurious system resets caused by noise. On power-up, the
RESET pin must remain low for a minimum of 10 lis after
the power supply reaches its operating voltage.
There is no functional difference between an external
reset and an internal reset caused by the overflow of
the watchdog timer. In both cases, the main system
clock oscillation is stopped and the subsystem clock
oscillation continues. During reset, the program
counter is loaded with the address contained in the
reset vector (addresses OoaOH, 0001 H). Once the reset
is cleared and the oscillation stabilization time of 216!fx
has elapsed, program execution starts at that address.
34
NEe
NEe
NEG Electronics Inc.
pPD78064 Family
(pPD78062/063/064/P064)
8-Bit, K·Series Microcontrollers With
LCD Controller/Driver, UART, and A/D Converter
Preliminary
Description
The pPD78062, pPD78063, pPD78064, and pPD78P064
are members of the K-Series@ of microcontrollers featuring an LCD controller/driver, A/D converter, UART,
8-bit hardware multiply and divide instructions, bit
manipulation instructions, four banks of main registers, an advanced interrupt handling facility, and a
powerful set of memory-mapped on-chip peripherals.
Timing is generated by two oscillators. The main oscillator normally drives the CPU and most peripherals.
The 32.768-kHz subsystem oscillator provides time
keeping when the main oscillator is turned off. Since
CMOS power dissipation is proportional to clock rate,
the 78064 provides a software selectable instruction
cycle time from 0.40 ps to 122 ps. The STOP and HALT
modes turn off parts of the microcontroller for additional power saving. The data retention mode permits
RAM contents valid down to 2 volts.
September 1993
o 571/0 lines
- Two CMOS input-only lines
- 55 CMOS bidirectional I/O lines with software
selectable pullup resistors
o Powerful instruction set
- 8-bit unsigned multiply and divide
-16-bit arithmetic and data transfer instructions
-i-bit and 8-bit logic instructions
o Minimum instruction execution times:
-0.4/0.8/1.6/3.2/6.4/12.8 ps using 5-MHz main
system clock
-122 ps selectable using 32.768-kHz subsystem
clock
o Memory-mapped on-chip peripherals
- Special function registers
o Programmable priority, vectored-interrupt
controller (two levels)
o Programmable buzzer and clock outputs
These devices are ideally suited for applications in
portable battery-power equipment, office automation,
communications, consumer electronics, home appliances, exercise and fitness equipment.
o Power saving and battery back up
- Variable CPU clock rate
-HALT mode
-STOP mode
- 2-V data retention mode
K-Series is a registered trademark of NEC Electronics, Inc.
o CMOS operation; VDD from 2.7 to 6.0 V
Features
o LCD controller/driver for up to 160 segments
-40 segment lines
- 4 common lines
- Static, 1/2 or 1/3 bias
- LCD resistor ladder available on ROM version
o Eight-channel 8-bit A/D converter
o Two-channel serial communication interface
- 8-bit clock synchronous interface 0
Full duplex, three-wire mode
NEC serial bus interface (SBI) mode
Half-duplex, two-wire mode
- Serial interface 2
Full-duplex, three-wire mode
UART mode
o Timers: five channels
-Watchdog timer
-16-bit timer/event counter with two i6-bit
capture and compare registers
- Two 8-bit timer/event counters usable as one
16-bit timer/event counter
- Watch (clock) timer
50633
Internal High-Capacity ROM and RAM
ROM
78062
78063
78064
16K bytes
24K bytes
32K bytes
512 bytes
1024 bytes
1024 bytes
1024 bytes
40 nibbles
40 nibbles
40 nibbles
40 nibbles
PROM
High-speed
78P064
32K bytes
RAM
LCD display
RAM
NEe
,.,PD78064 Family
Ordering Information
Part Number
ROM
Package
Package Drawing
~P078062GC-xxx-7EA
16K mask ROM
100-pin plastic OFP (14 x 14 mm)
P100GC-65,7EA
~P078063Ge-xxx-7EA
24K mask ROM
~P078064GC-xxx-7EA
32K mask ROM
~P078P064Ge-7EA
32KOTP ROM
100-pin plastic OFP (14 x 20 mm)
P100GF-65-3BA
/lP078062GF-xxx-3BA
16K mask ROM
/lP078063GF-xxx-3BA
24K mask ROM
/lP078064GF-xxx-3BA
32Kmask ROM
/lP076P064GF-3BA
32KOTPROM
/lP078P064KL-T (Note 3)
32K UV EPROM
Notes:
(1) xxx indicates ROM code suffix
(2) All devices listed are standard quality grade
(3) Under development
2
100-pin ceramic Lee wlwindow (14 x 20 mm)
NEe
pPD78064 Family
Pin Configurations
100-Pin Plastic QFP (14 x 14 mm)
Pll/ANll
P70/S12IRxO
P13/ANI3
3
P2 7 /SCKO
P2e/SOOISBl
P14/ANI4
4
P25/SIOISBO
P12/ANI2
P15/ANI5
P80/S39
Ple/ANle
P81/S36
P17/ANI7
7
AVoo
AVREF
8
9
P821S37
PB3/S3e
P100
P841S35
P8 5 /S34
P10l
P8a/S33
VSS
P102
P901S31
P87/S32
P103
P911S30
P30rroo
P92/S29
P31rro1
P93/S28
P32rro2
P94/S27
P33m1
P951S26
P34m2
P981S25
P35IPCL
P971S24
P3aIBUZ
S23
S22
P37
..
i
COMO
S21
COMl
S20
COM2
S19
Notes:
(1) Connect·IC QnlemaHyconnecled) pin (Vppon ,"PD78P064) to VSS
(2) AVOO should be connected to VOO
(3) AVSS should be cennected to VSS
83YL-9694B
3
NEe
pPD78064 FamUy
Pin Configurations (cont)
100-Pin Plastic QFP or Ceramic LCC With Window (14 x 20 mm)
:i!
~~~~~~~~~~~~~I~~~
~O~N~.~~~O~N~·~~~R~~
~~~~~~~~~~~~~~~~~
~
820
P2e/SOOISBl
P271SCKO
P701S12IRxD
P71 IS02ITxD
P72/SCK2IASCK
IC (Vpp)
X2
Xl
Voo
XTl1P07
XT2
RESET
POo IINTPOITIOO
POl11NTP11T101
P0211NTP2
P03 11NTP3
P0411NTP4
P05 11NTP5
P110
P11l
P112
P113
P114
Pl15
P11e
P117
819
S18
S17
816
S15
814
S13
812
S11
810
10
11
12
13
14
15
89
S8
S7
sa
16
S5
S4
sa
82
Sl
so
VSS
VLC2
vLCl
VLCO
BIAS
COM3
COM2
COMl
COMO
AVSS
P10/ANI0
Pl1/ANI1
P12fANI2
~~~~~~~~~~~~~~~~~~~~
~~~~~$~8c~~~8~aEEd~~
~~z~z
~~~~~~~g~
~~
~~~~~~~~~
rlfft
<
iii
l~
~~~
~ii
Nol8II:
(1) Connect IC ~ntemally comected) pIn (Vppon I,P078P064) to VSS
(2) AVoo should be connected to Voo
(3) AVSS should be connected to Vss
..Y\........
4
NEe
pPD78064 Family
Pin Functions; Normal Operating Mode
Symbol
First Function
Symbol
Alternate Function
POo
Port 0; 7-bit, bit selectable I/O port
(Bits 0 and 7 are input only)
INTPO
TIO
External mask able interrupt
External count clock input to timer a or timer a
capture trigger to capture registers CROO and CROI
INTP1
TI01
External maskable interrupt
Timer a capture trigger to capture register CROO
INTP2
INTP3
INTP4
INTP5
External maskable interrupt
XTI
Crystal oscillator or external clock input for
subsystem clock
Port I; a-bit, bit-selectable I/O port
ANIO - ANI7
Analog input to AID converter
Port 2; 3-bit, bit-selectable I/O port
SIO
SBO
Serial data input, three-wire serial I/O mode
2/3-wire serial I/O mode
SOO
SBI
Serial data output, three-wire serial I/O mode
2I3-wire serial I/O mode
P25
P26
P30
Port 3; a-bit, bit-selectable I/O port
SCKO
Serial clock I/O for serial interface
TOO
Timer output from timer
T01
Timer output from timer 1
T02
Timer output from timer 2
Til
External count clock input to timer I
TI2
External count clock input to timer 2
P35
PCl
Programmable clock output
P36
BUZ
Programmable buzzer output
SI2
RxD
Serial data input, three-wire serial I/O mode
Asynchronous serial data input
S02
TxD
Serial data output, three-wire serial I/O mode
Asynchronous serial data output
SCK2
ASCK
Serial clock I/O for serial interface 2
Asynchronous serial clock input
Port a; a-bit, bit-selectable I/O port
S39- S32
LCD controller/driver segment signal output
Port 9; B-bit, bit-selectable I/O port
S31 - S24
LCD controller/driver segment signal output
P70
pao - PB-,
Port 7; 3-bit, bit-selectable I/O port
•
a
a
Port 10; 4-bit, bit-selectable I/O port
P110-PI1?
Port 11 ; B-bit, bit-selectable I/O port
SO-S23
LCD controller/driver segment signal output
COMO-COM3
LCD controller/driver common signal output
LCD drive voltage input pins
BIAS
LCD drive power supply output
RESET
External system reset input
XI
Crystal/ceram ic reaonator connection or
external clock input for main system clock
X2
Crystal/ceramic resonator connection or inverse
of external clock for main system clock
XT2
Crystal oscillator or left open when not using
the subsystem clock
5
NEe
pPD78064 Family
Pin Functions; Normal Operating Mode (cont)
Symbol
First Function
AID converter reference voltage
AVoo
NO converter power supply input
AVss
NO converter ground
Voo
Power-supply input
Vpp
JlPD78P064 PROM programming power-supply
input
Vss
Ie
Power-supply ground
Internal connection
Note: See table 2 and figure 4 for details.
6
Symbol
Alternate Function
NEe
pPD78064 Family
Block Diagram
TOOIP30
TIOOIINTPOIPOo
TI0111NTP1IPOl
1011P31
Tll1P33
General Reg.
I Watchdog
Timer
Clock
Timer
p
P
Program Memory
(ROMIPROM)
Nota 1
SIOISBOIP2S
•
P9a-P97
SOO/SB11P26
SCKOIP27
Pl0a-Pl03
-§
0
ANIOIP1
ANI71P17
AVOO
AVSS
Pll0.p117
SO-S23
S241P97S311P90
AID
Converter
S321PBr
S391PBO
AVREF
INTPOIPOO INTP5IPOS
r-AJ
'--v'!
Interrupt
ConlroUer
~
f'n/
t
C0M0><>----1
Voo
data~
OUtputdiSable~
Schmitt trigger Input with hysterasls characteristics
t----0
Voo
VOO
data
data
output disable
~
-------[>o>----Ir..-
+-----<.......>---<>
-----...--1,
'P--'t-"IO---0>----1
data~
data~
OUtputdlsable~
+---........>---0
--------1[>0
IN/OUT
output disable
~
Voo
t-----<~--c
IN/OUT
.L
Input enable _ _ _ _ _ _ _...J
VREF (Threshold Voltage)
Input enable ---------------'
B3Rc-9589B-l (Ql93)
15
NEe
pPD78064 Family
Figure 4. Pin Input/Output Circuits (cont)
pullup enable
IN (XT1)o---+-----.,
OUT~)o--~~------~~~----~
--------Ir>>---I
-~
IN/OUT
output disable
Input enable
...L
Typa17 (SO • 823)
VLCO
...L
P-ch...L
VLCl
----c
N-ch,
V L C 1 - - - -....
SEG
-ch
SEG
date
N-ch
date
----c
N·eIl
OUT
P-ch...L
VLC2
N-ch,
...LP-ch
V L C 2 - - - -....
Type 18 (COMO· C0M3)
...L
VLCO
P-ch ...L
VLC1----~
t-----i,----oOUt
COM _ _ _ _ _ _---1
date
VLC2----~
83RC-95B9B-2 (8193)
16
NEe
pPD78064 Family
AID Converter
The pPD78064 family analog-to-digital (AID) converter
(see figure 5) uses the successive-approximation
method for converting one of eight multiplexed analog
inputs into 8-bit digital data. The minimum conversion
time per input is 19.1 ps.
The AID converter input select register (AD IS) selects
the number of inputs that are used in AID conversion.
The remaining inputs are used as ports. The analog
input to be converted is selected by programming the
AID converter mode register (ADM). AID conversion is
started by external interrupt INTP3 or by writing to the
ADM. When the conversion is completed, the results are
stored in the AID conversion result register (ADCR) and
an INTAD interrupt is generated.
If the AID converter was started by an external interrupt, the AID converter stops after the interrupt is
generated. If the AID converter was started by software, the AID converter repeats the conversion until
new data is written to the ADM register.
Figure 5. AID Converter
Resistor St~ng
1--1------1
1
1
1
rTAVREFO
1
1
1
1
1
Sample and
Input
Seiector2
Hold CIrcuit
,---l
r------'
NoIe2
1
1
I:
L ___ ...I
From ADM
1
I
1
1
I
1
1 Tap 1
1
1Selecto'l
I
1
1
1
1
1
1
1
1
1
1
1
1
I------~~:
1
1
1
1
:
I
~
1
i
1
1
~AVSS
I ___ L _____ J
INTP3/P03
I---------;~~ INTAD
Edge
I---------;~~ INTP3
Selecllon
TO Input Selector 2
8
AID Conversion Result
Regfster (ADCR)
8
Noter.
(1) Selects number of Port 1 Inputs to be used for AID oonvarslon.
(2) Selects the channel for AID oonvarslon.
B3RC-95B3B (10013)
17
NEe
pPD78064 Family
Serial Interfaces
The pPD78064 family has two independent serial interfaces: serial interface b and serial interface 2.
Serial Interface O. Serial interface 0 is an a-bit clock
synchronous serial. interface (figl,Jre 6). It can be operated in either a three-wire serial I/O mode, NEC serial
bus interface (S81) mode, Or two~wire serial I/O mode.
The serial clock can be prOvided from one of eight
internal clocks, the output of 8-bit timer register 2, or
the external clock line SCKO.
.
Figure 6. Serial Interface 0
SIOI
SBOI 0
P25
SOOf
SB11
P2a
0
Internal Bus
83RC-95428 (1!i93)
18
NEe
pPD78064 Family
In the three-wire serial I/O mode, the 8-bit shift register
(SIOO) is loaded with a byte of data and eight clock
pulses are generated. The falling edge of these eight
pulses shifts the byte of data out of the SOD line (either
MSB or LSB first) while the rising edge of these pulses
shifts the data in from the SID line providing full-duplex
operation. The INTCSIO interrupt is generated after
each 8-bit transfer.
The NEC SBI mode is a two-wire high-speed proprietary
serial interface available on most devices in the NEC
pPD75xxx and pPD78xxx product lines. Devices are
connected in a master/slave configuration (see figure
7). There is only one master device at a time; all others
are slaves. The master sends addresses, commands,
and data over one of the serial bus lines (SBO or SB1)
using a fixed hardware protocol synchronized with the
SCKO line. Each slave device of the pPD78064 family
can be programmed to respond in hardware to anyone
of 256 addresses set in its slave address register (SVA).
There are also 256 commands and 256 data types.
Since all commands are user definable, many software
protocols, simple or complex, can be defined. It is even
possible to develop commands to change a slave into a
master and the previous master into a slave.
Figure 7. 581 Mode Master/Slave Configuration
~
DO
MaslerCPU
Slave CPU
(S81).S80
S80.(S81)
Address 1
SCK
SCK
Slave CPU
S80.(SB1)
Address 2
,
~
~
SCK
SIaveIC
S80.(SB1)
AddressN
SCK
83YL-6347A (9193)
The two-wire serial I/O mode provides half-duple~
eration using either the SBO or SB1 line and the SCKO
line. Communication format and handshaking can be
handled in software by controlling the output levels of
the data and clock lines between transfers. For data
transmission, when the 8-bit shift register (SIOO) is
loaded with a byte of data, eight clock pulses are
generated. The falling edge of these eight pulses shifts
the byte of data out of either the SBO or SB1 line (MSB
first). In addition, this byte of data is also shifted back
into SIOO on the rising edge of these pulses providing a
means of verifying that the transmission was correct.
For data reception, the SIOO register is preloaded with
the value FFH. As this data value is shifted out on the
falling edge of the serial clock, it disables the n-channel
open-drain driver. This allows the receive data to be
driven on to the serial line and shifted into the SIOO
register on the rising edge of the serial clock. The
INTCSIO interrupt is generated after each 8-bit transfer.
Serial Interface 2. Serial interface 2 is an 8-bit serial
interface (figure 8) that can be operated in either a
UART mode or a three-wire serial I/O mode. The internal
baud rate generator circuit (figure 9) scales an internal
clock to provide standard baud rates from 75 to 38400
bps. For non-standard baud rates, the internal baud
rate generator circuit scales an external clock input on
the ASCK pin. The output of the baud rate generator
circuit is used as the data transmission and sampling
clock in the UART mode or the data clock in the
three-wire serial I/O mode.
In the UART mode, half or full-duplex operation with
various protocols is programmable. The asynchronous
serial interface mode register (AS 1M) is used to specify
the number of stop bits (1 or 2), data character length
(7 or 8 bits), parity (none, even, or odd), receive operation control (enable or disable), and transmit operatiM control (enable or disable). The ASIM register is
also used to enable or disable the generation of an
interrupt when a reception error occurs and if an
internal or external clock will be supplied to the baud
rate generator circuit.
A transmit operation is started by writing a data
character to the transmit shift register (TXS) register.
The start bit, parity bit, and stop bits are automatically
added by the hardware to the data character in the TXS
register. The data in the TXS register is shifted out of the
TxD line and when the TXS register is empty, a transmission complete interrupt (INTSn is generated.
When the receive operation control is enabled, the RXD
line is sampled using the clock specified by the ASIM
register. When the RxD line is detected low, sampling
starts at the midpoint of each bit. If the first sample
yields a low, it is identified as a start bit. The RxD line
continues to be sampled at the midpoint of each bit.
Reception of one frame of data is complete when the
data character bits, parity bit (if being transmitted),
and one stop bit are detected after the start bit. Even if
19
~~
~1:
NEe
pPD78064 Family
Figure 8. Serial Interface 2
To Baud Rate
Generator
Transmit Shift
Register (TXSIS102)
SCK OUtput Control
Circuit
INTSER
Receive Control
Circuit
INTST
INTSRlINTCSI2
FromASIM
ASCKlSCK2Cqo}-----+--+-------.
Baud Rate Generator Control Register
(BRGC)
83RC-95S4B (9193)
the protocol is set for two stop bits, only one stop bit is
used for the end of reception detection.
When one frame of data has been received, the received data in the shift register is transferred to the
receive buffer (AXB) and a reception complete vectored
interrupt (INTSR) is generated even if an error (parity
and/or framing) is detected. The data must be read
20
from the AXB register before another frame is received
or an overrun error will be generated. If an error occurs,
the appropriate flag is set in the asynchronous serial
interface status register (ASIS) and a receive error
interrupt (INTSER) is generated.
In the three·wire serial I/O mode, the TXS register is
loaded with a byte of data and eight clock pulses are
NEe
IIPD78064 Family
Figure 9. Internal Baud Rate Generator
CSIE2
Start Bit
Sampling Clock
TXE
S..alt Counter
Transmtt Clock
Coincidence
~-----
From BRGC
~-------------SCK
FromBRGC
----------r-~~-------------CSCK
Decoder
Receive Clock
i
Coincidence
rn
AXE
Start Bit OetecUon
generated. The falling edge of these eight pulses shifts
the byte of data out of the S02line (either MSB or LSB
first) while the rising edge of these pulses shifts the
data in from the SI2 line providing full-duplex operation. The INTCSI2 interrupt is generated after each
8-bit transfer.
21
NEe
pPD78064 Family
Timers
16-Bit Timer/Event Counter O. Timer/event counter 0
(figure 10) consists of a 16-bit counter (TMO), two 16-~it
capture/compare registers (CROO, CR01), control registers (TMCO, TOCO, and CRCO), clock select register
(CLCO), and a timer output control circuit (TOO). Timer
o can be used as an interval timer, to count external
events on the timer input (TIDO) pin, to output a programmable square wave, a 14-bit pulse-width modulated output, a one-shot pulse output, or to measure
pulse widths.
The pPD78064 family has one 16-bit timer/event
counter, two 8-bit timer/event counters that can be
combined for use as a 16-bit timer/event counter, a
clock timer, and a watchdog timer. All of these can be
programmed to count a number of prescaled values of
the main system clock. In addition, the clock timer can
also count the subsystem clock. All of the timer/event
counters can count external events.
Figure 10.
16-8it Timer/Event Counter 0
)
Internal Bus
\,
r
<
1CaptureiCompare Conlrol Register 0 ~TO OROl
(ORCO)
". INTP1
~
1 16·BII
CaptureiCompere
RegISter 0 (CROO)
TI01IP0 1flNTP1
I
INTTMOO
0--
Selector
J.
--
'r
olock TImer Oulpul- _ r - fXXfXX/2fXXf4fxxf8-
11oar
POof
INTPO
J-
Edge
DetecUon
r- Selector
r-
~
J.
J16-BH TImer RegISter
L
(TMO)
,
r-L.....;r-
IOverflow
I Rag
Clear
!r
.....
PWM
Coincidence
Oulpul
Conlrol
ClrcuH
r-
Oulput
Control
Logic
f- TOO/P30
TolMCO
Clear
Clrcuft
I
.J
Coincidence
..... 1NTTM01
<
I....,....
!r
7
I
)
lImar Clock Select
Register 0 (TCLC)
I1
r
INTPO
From ORCO
16-Bft CaptureiCompere
Register 1(OR01)
Il
Internal BUB
lImar Mode
Control Register (TMCO)
1
J
lImar Oulpul
Control RegISter (TOCO)
J
J
~
83Rc-959OB (9193)
22
NEe
IIPD78064 Family
a-Bit Timer/Event Counters 1 and 2. Timer/event
counters 1 and 2 (figure 11) each consist of an 8-bit
timer (TM1 or TM2), an 8-bit compare register (CR10 or
CR20), and timer output control logic (T01 or T02). The
timers are controlled by registers TCL1, TMC1, and
TOC1 via five selectors. Timer/event counters 1 and 2
can each be used as an a-bit interval timer, to count
external events on the timer input pins (Tl1 orTI2), orto
output a programmable square wave. In addition, timers 1 and 2 also can be combined as a 16-bit timer/
event counter and used as a 16-bit interval timer, to
count external events on T11, or to output a programmable square wave on T02.
Figure 11. 8-Bit Timer/Event Counters 1 and 2
IntemalBuB
1-------.--------------------~1~1
S-BR
'xx12
TlmeriEvent
Counter 2
OUlput
Control logic
T02IP32
'xxt4
'xxf8
'xxt18
t-----t-:---~ I~
'xxf32
'xxf84
'xxt128
'xx1258
'XXJ512
'xxf2048
t-------+--- T011P31
* RISIng or ,ailing edge can be aalacted.
aaRc.a&41B
23
NEe
,.,PD78064 Family
Clock Timer 3. Clock timer 3 (figure 12) is a 5-bit timer
that can be used as a time source to keep track of time
of day, to release the STOP or HALT modes at regular
intervals, or to initiate any other task that must be
performed at regular intervals. When driven by the
subsystem clock, the clock timer continues to operate
in the STOP mode.
The clock timer can function as both a clock timer and
interval timer simultaneously. When used as a clock
timer, interrupt request INTWT (not a vectored interrupt) can be generated using a main or subsystem
clock every 0.5 or 0.25 seconds. When used as an
interval timer, vectored interrupt request INTTM3 is
generated at preselected time intervals. With a main
system clock of 4.19 MHz and flO( = fx or if using the
subsystem clock of 32.768 kHz, the following time
intervals can be selected: 489I1s, 97811S, 1.96 ms, 3.91
ms, 7.82 ms or 15.6 ms.
Figure 12_ Clock Timer 3
r--Selector
.......
fw f2 9
fXXi127_
~
5-Bft
TImer
I fw1213
r-Selector ~I NTWT
"-r--
Clear
fwf2 8
r--Selector
r-I
!wf214
fw f27
fw
Prescaier
fxr-
fw f26
Selector
L"
fwf2 5
L-r--
fwf24
i
TTM3
To 18·BII
Tlmer/Evenl
Counter Clrcuft
,.
Clear
I
'\
Timer Clock Select
Register 2 (TCL2)
)
I
l+-fLCD
(to LCD Controller)
IntemalBus
II
I
Waldl TImer Mode
Control Register (TMC2)
.~
I
J,
83RC-9586B (9193)
24
NEe
JlPD78064 Family
watchdog Timer. The watchdog timer (figure 13) can
be used as either a watchdog timer or an interval timer.
When used as a watchdog timer it protects against
program run-away. It can be selected to generate a
nonmaskable interrupt (INTWDT), which vectors to address 0004H, or to generate an internal reset signal
which vectors to the restart address OOOOH if the time~
is not cleared by the program before it overflows. Eight
program-selectable intervals based on the main system clock are available. With a main system clock of
4.19 MHz and fxx
fx, they are 0.489, 0.978, 1.96, 3.91,
7.82, 15.6,31.3, and 125 ms. With a main system clock of
4.19 MHz and fxx = fx/2, they are 0.978, 1.96,3.91, 7.82,
~~,~, ~1.3, 62.6, and 250 ms. Once the watchdog timer is
Initialized and started, the timer's mode cannot be
changed and the timer can only be stopped by reset.
=
Programmable Clock Output
The pPD78064 family has a programmable clock output
(PCl) that can be used for carrier output for remotecontrolled transmissions or as a clock output for peripheral devices. The main system clock (fxx)divided by
1,2,4, 8, 16,32,64, or 128 or the subsystem clock (fXT)
?an be output on the PCl pin. If the main system clock
IS 4.19 MHz and fxx = fx, the following frequencies are
available: 4.19 MHz, 2.1 MHz, 1.05 MHz, 524 kHz, 262
kHz, 131 kHz, 65.5 kHz, and 32.7 kHz. With a main
system clock of 4.19 MHz and fxx = fx/2, the following
frequencies are available: 2.1 MHz, 1.05 MHz, 524 kHz,
262 kHz, 131 kHz, 65.5 kHz, 32.7 kHz and 16.4 kHz. With
a subsystem clock of 32.768 kHz, 32.768 kHz is also
available. See figure 14.
When used as an interval timer, maskable interrupts
(INTWDT), which vector to address 0004H, are generated repeatedly at a preset interval. The time intervals
available are the same as in the watchdog timer mode.
Figure 13. Watchdog Timer
I~
INlWDT
Maskable
Interrupt
Request
IXYf25
IXYf28
IXX123
Prescaler
IXYf27
Selector
RESET
IXYf28
INlWDT
Nonmaskable
Interrupt
Request
IXYf29
IXYf211
Internal Bus
83RC-9536B (9193)
25
NEe
pPD78064 Family
Figure 14. Programmable Clock Output
Ixx_--~
IXJt!2 ----;~
IXJt!22 ----;~
IxxI23_--~
IXX124 ---~ Selector
IXJt!25 ----i~
IXJt!26 ---~
IXJt!27 ---~
IXT---~
Buzzer Output
The pPD78064 family also has a programmable buzzer
output (BUZ). The buzzer output frequency can be
programmed to be equal to the main system clock (fxX>
divided by 512, 1024, or 2048. With a main system clock
of 4.19 MHz and fxx = fx, the buzzer can be set to 8.2,
4.1, or 2.0 kHz. With a main system clock of 4.19 MHz
and fxx fx/2, the buzzer can be set to 4.1,2.0, or 1.0
kHz. See figure 15.
=
Figure 15. Buzzer Output
IXJt!29
IXJt!210 ---~ Selector
IXX1211 --~~
26
I----------r-.....>-____- I
NEe
pPD78064 Family
LCD Controller/Driver
The liquid crystal display (LCD) controller/driver (figure
16) has 4 common plus 40 segment lines and can be
programmed to operate in any of four modes. It can
operate in the static mode (drive 40 segments), the
duplexed mode (drive 80 segments), the triplexed
mode (drive 120 segments), or quadruplexed mode
(drive 160 segments). The duplexed mode uses 1/2
bias, the triplexed mode can use either 1/2 or 1/3 bias,
and the quadruplexed mode uses 1/3 bias.
Figure 16.
The LCD controller automatically refreshes the LCD by
taking data from the LCD data RAM and uses display
data multiplexers, segment drivers SO-S39, and common drivers COMO-COM3 to drive the LCD. The clock
timer provides a clock signal (flCD) that is derived from
the clock timer (figure 17). Using the LCD display mode
register (LCDM), the main LCD clock (LCDCL) is selected as flCD (or prescaled values flcoI2, fLcoI4, or
f l cD/8) yielding frame frequencies of 64, 128,256, or 512
Hz with a main system clock of 4.19 MHz or a subsystem clock of 32.768 kHz.
LCD Contro//er/Oriver
IntemaiBus
Display Data Memory
FA7FH
FA7EH
FA68H
76543210 76543210
FA67H
FA66H
76543210 76543210 76543210
FA58H
76543210
LCD Clock
Selection
Circuli
fLCD(fwf26)
llmlng
Controller
Display 3 2 1 0
Data
LCD Display
Control Register
(LCDC)
Segment
Selection
Circuit
*
*
*
o
o
0
SO
S1 -------- S23
* Segrnant Driver
LCD Drive
Voltage Control
Circuit
Common
Driver
83RC-95B8B (8193)
27
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pPD78064 Family
Figure 17. LCD Clock Selection Circuit
fW126
fLC0f2 3
Prescalar
(From Clock TIme r)
I
fLC[)l22
Selector
LCDCL
fLC0f2
fLCD
LCD Display
Mode Register
(LOOM)
I
~~
IntemalBus
\
B3RC-9587B (Q'B3)
The LCDON bit in the LCDM register is used to enable
or disable (blank) the display. The LCDMO·LCDM2 bits
in the LCDM register are used to select the bias method
and LCDM4-LCDM6 are used to set the frame frequency.
The LCD col'ltroller/driver can operate in the STOP
mode as long as the clock timer is driven by the
subsystem clock.
Drive levels can be set internally by ordering the resistor ladder mask option on the IlPD7806x mask ROM
devices; otherwise, external resistors can be connected to pins VLCO-VLC2 and the BIAS pin. The BIAS pin
can be used to control the contrast of the LCD.
The LCDC register is used to select P801S39 to P9]/S24
pin functions and the LCD power supply. The pins
P801S39 to P9]/S24 are selected in groups of two to be
port pins or segment pins S24 to S39. The LCD power
supply selections are: (a) LCD power not supplied by
the IlPD78064 device, (b) LCD drive power supplied
from Voo, or (c) LCD drive power supplied from the BIAS
pin.
28
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pPD78064 Family
Interrupts
The pPD78064 family has 19 maskable hardware interrupt sources; 7 are external and 12 are internal. Of
these 19 interrupt sources, 17 cause a vectored interrupt while the 2 testable inputs only generate an
interrupt request. All 19 maskable interrupts can be
used to release the HALT mode except INTPO. INTPO
cannot be used to release the STOP mode and cannot
release the HALT mode when register SCS = O. In
addition, there is one nonmaskable interrupt from the
watchdog timer, one software interrupt, and a reset
interrupt. The watchdog timer overflow interrupt (interrupt vector table address 0OO4H) can be initialized to
be a nonmaskable interrupt or the highest default
priority maskable interrupt. The software interrupt,
generated by the BRK instruction, is not maskable. See
table 3 and figure 18.
Table 3. Interrupt Sources and Vector Addresses
Type of
Request
Default
Priority
Restart
Nonmaskable
Maskable
0
2
Signal
Name
* See figure
Location
Vector
Address
OOOOH
Interrupt"
Configuration
RESET
RESET input pin
External
INTWDT
Watchdog timer overflow
(when reset mode selected)
Internal
INTWDT
Watchdog timer overflow
(when nonmaskable interrupt selected)
Inter,nal
0004H
A
INTWDT
Watchdog timer overflow
(when interval timer selected)
Internal
0004H
B
INTPO
External interrupt edge detection
External
0006H
C
INTP1
External interrupt edge detection
External
0008H
D
3
INTP2
External interrupt edge detection
External
OOOAH
D
4
INTP3
External interrupt edge detection
External
OOOCH
D
5
INTP4
External interrupt edge detection
External
OOOEH
D
6
INTP5
External interrupt edge detection
External
0010H
D
7
INTCSIO
End of clocked serial interface 0 transfer
Internal
0014H
B
8
INTSER
Serial interface 2 UART reception error
Internal
0018H
B
9
INTSR
End of serial interface 2 UART reception
Internal
001AH
B
INTCSl2
End of serial interface 2 three-wire transfer
10
INTST
End of serial interface 2 UART transmission
Internal
001CH
B
11
INTTM3
Clock timer reference time interval signal
Internal
001EH
B
12
INTTMOO
16-bit timer/event counter capture/compare
(CROO) coincidence signal
Internal
0020H
B
13
INTTM01
16-bit timer/event counter capture/compare
(CR01) coincidence signal
Internal
0022H
B
14
INTTM1
S-bit timer/event counter 1 coincidence
signal
Internal
0024H
B
15
INTTM2
S-bit timer/event counter 2 coincidence
signal
Internal
0026H
B
16
INTAD
End of AID conversion
Internal
0028H
B
BRK instruction
Internal
003EH
E
INTWT
Clock timer overflow
Internal
F
INTPT11
Port 11 falling edge detection
External
F
Software
Test input
Interrupt Source
•
.
1S.
29
."
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pPD78064 Family
Figure 18. Interrupt Configurations
Type A: Internal nonmaslrable Interrupt
1
Interrupt _ _....._ _ _.....1
Request
Type B: Internal maslrable Interrupt
Type C: External maslrable Interrupt (lNTPO)
30
)0
Priority
Control Clrcuft
NEe
pPD78064 Family
Figure 18. Interrupt Configurations (cont)
Type D: External maskable Interrupt (except INTPO)
Interrupt
Request
Vector Table
Address Generator
-----+I
'----------~
Standby
Release
Signal
•
Type E: Software Interrupt
Interrupt
Request
-------l~~l•
____
....1
Type F: Test Input
I---~:=
Signal
,---...-
AbbreviallOns:
IF: Interrupt request flag
IE: Interrupt enable flag
ISP: In-servloe priority flag
MK: Interrupt mask flag
PR: Priority speCIfy flag
31
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pPD78064 Family
Interrupt Servicing. The J.lP078064 family provides
two levels of programmable hardware priority control
and services a" interrupt requests except the two
testable interrupts (INTWr and INTPT11) using vectrored interrupts. The programmer can choose the
priority of servicing each maskable interrupt by using
the interrupt control registers.
Interrupt Control Registers. The J.lP078064 family has
three 3-byte interrupt control registers. The interrupt
requestflag registers (IFOl, IFOH, and IF1L) contain an
interrupt request flag for each interrupt. The interrupt
mask registers (MKOl, MKOH, and MK1l) are used to
enable or disable any individual interrupt. The priority
flag registers (PROl, PROH, and PR1L) can be used to
specify a high or a low priority level for each interrupt
except the two testable interrupts (INTWr and INTPT11).
Five other 8-bit registers are associated with interrupt
processing. The key return mode regi!!ter (KRM) contains the KRIF interrupt request flag associated with
falling-edge detection on port 11 and the KRMK mask
flag used to enable or disable clearing of the standby
mode if a falling edge is detected on8 (P110 - P117),
6(P112 - P1h), 4(P114 - P117), or 1(P117) bit (s) of port
11 as determined by the KRM2 and KRM3 bits. The
external interrupt mode registers (INTMO and INTM1)
are used to select a rising, falling, or both edges as the
valid edge for each of the external interrupts INTPO to
INTP5. The sampling clock select register (SCS) is used
to select a sampling clock for the noise eliminator
circuit on external interrupt INTPO.
rupt requests of a lower priority are always held pending until one instruction has been executed after returning from the current service routine.
The default priorities listed in table 3 are fixed by
hardware and are effective only when it is necessary to
choose between two interrupt requests of the same
software-assigned priority. For example, the default
priorities would be used after the completion of a
high-priority routine, if two interrupts of the same
software priority were pending.
The software interrupt, initiated by the BRK instruction, is executed regardless of the processor's priority
level and the state of the IE bit. It does not alter the
processor's priority level.
Vectored Interrupt Servicing. When a vectored interrupt is acknowledged, the program status word and
the program counter are saved on the stack, the processor's priority is set to that specified for the interrupt,
the IE bit in the PSW is set to zero, and the routine
whose address is in the interrupt vector table is entered. At the completion of the service routine, the RETI
instruction (RETB instruction for the software interrupt) reverses the process and the J.lP078064 family
microcomputer resumes the interrupted routine.
Standby Modes
HALT, STOP, and data retention modes are provided to
reduce power consumption when CPU action is not
required.
The IE and the ISP bit of the program status word are
also used to control interrupts. If the IE bit is 0, a"
maskable interrupts are disabled. The IE bit can be set
or cleared using the EI and 01 instructions, respectively, or by directly writing to the PSw. The IE bit is
cleared each time an interrupt is accepted. The ISP bit
is used by hardware to hold the priority level flag of the
interrupt being serviced.
The HALT mode is entered by executing a HALT instruction while the CPU is operating from the main
system or subsystem clock. In HALT mode, the CPU
clock is stopped while the main system and the subsystem clock continue to run. The HALT mode is released by any unmasked interrupt request (except
INTPO if register SCS =0), a nonmaskable interrupt
request, an unmasked test input, or an external reset
pulse.
Interrupt Priority. If the watchdog timer overflow interrupt (INlWOT) has been initialized to be a nonmaskable interrupt, it has priority over a" other interrupts.
Two hardware-controlled priority levels are available
for a" maskable interrupts that generate a vectored
interrupt (i.e., a" except the testable interrupt). Either a
high or a low priority level can be assigned by software
to each of the maskable interrupts. Interrupt requests of
the same priority or a priority higher than the processor's current priority level are held pending until interrupts in the current service routine are enabled by
software or until one instruction has been executed
after returning from the current service routine. Inter-
Power consumption may be further reduced by using
the STOP mode. The STOP mode is entered byexecuting a STOP instruction while operating from the main
system clock. In STOP mode, the main system clock
input pin X1 is internally grounded stopping both the
CPU and the peripheral hardware clock. The STOP
mode is released by any unmasked interrupt request
except INTPO, a nonmaskable interrupt request, an
unmasked test input, or an external reset pulse. Any
peripheral using the main oscillator as a clock source
will also be disabled in the STOP mode and interrupts
32
NEe
from such a peripheral can not be used to exit the STOP
mode. Table 4 summarizes both the HALT and STOP
standby modes.
When exiting the STOP mode, a wait time occurs before
the CPU begins code execution to allow the main
system clock oscillator circuit to stabilize. The oscillation stabilization time is selected by programming the
OSTS register with one of five values before entering
the STOP mode; the values range from 0.8 msec to 52.4
msec at fx = 5 MHz.
Once in the STOP mode, power consumption can be
further minimized by lowering the power supply voltage VDD to 2 volts. This places the device in the data
retention mode. The contents of Internal RAM and the
registers are retained. This mode is released by first
raising VDD to the proper operating range and then
releasing the STOP mode.
External Reset
The pPD78064 family is reset by taking the RESET pin
low or by an overflow of the watchdog timer (if enabled). The RESET input pin is a schmitt-trigger input
with hysteresis characteristics to protect against spurious system resets caused by noise.
There is no functional difference between an external
reset and an internal reset caused by the overflow of
the watchdog timer. In both cases, the main system
clock oscillation is stopped and the subsystem clock
oscillation continues. During reset, the program
counter is loaded with the address contained in the
reset vector (addresses OOOOH, 0001 H). Once the reset
is cleared and the oscillation stabilization time of 2l6/fx
has elapsed, program execution starts at that address.
,.,PD78064 Family
Table 4.
Standby Mode Operation Status
Item
HALT Mode
STOP Mode
Setting instruction
HALT instruction
STOP instruction
System clock when Main system or
setting
subsystem clock
Main system clock
Clock oscillator
Main system and
subsystem clocks can
oscillate; CPU clock is
stopped.
Subsystem clock can
oscillate; CPU clock
and main system
clock are stopped.
CPU
Operation stopped
Operation stopped
Ports
Maintain previous
state
Maintain previous
state
l6-bit timer/event
counter
Operational from main
system clock, or with
clock timer output, or
TIOO selected as the
count clock
Operational only with
clock timer output or
TIOO selected as count
clock.
8-bit timer/event
Operational from main Operational only with
system clock or with
Til and TI2 selected
Til and TI2 selected
as count clock
as the count clock
counters
Clock timer
Operational from main Operational only with
fXT as count clock
system clock or with
fXT as count clock
Watchdog timer
Operational from main Operation stopped
system clock
Serial interface 0
Operational from main Operational only with
external clock
system clock or with
external clock
Serial interface 2
Operational from main Operation stopped
system clock or with
external clock
LCD controller/
driver
Operational from main Operational when fXT
system clock or when is selected as count
clock to clock timer
txT is selected as
count clock to clock
timer
A/D converter
Operational from main Operation stopped
system clock
External interrupts Operational except for INTPO not operational;
INTPl to INTP5
INTPO when its
sampling clock is
operational
based on the CPU
clock
33
.'
pPD78064 Family
34
NEe
NEe
NEC Electronics Inc.
,.,PD78KO Product Line
Programming Reference
September 1993
j£PD78KO Product Line
Operands and Operations
The pPD78KO product line's instruction set features
both 8- and 16-bit data transfer and arithmetic instructions, 8-bit logic instructions, and single-bit manipulation instructions. Multiply and divide instructions are
also included except as noted in the pPD78KO Instruction Set table. Branch instructions exist to test individual bits in the program status word, the 8-bit accumulator, the special function registers, and in the short
address (saddr) portion of memory. Instructions range
in length from 1 to 4 bytes, depending on the instruction and addressing mode.
Refer to the following tables for the definitions of
symbols in the operand and operation columns of the
Instruction Set table.
This programming reference contains the following
three tables for the pPD78KO product line: (1) instruction set, (2) special function registers, and (3) interrupt
vectors and test inputs.
Specify operands in accordance with the rules of operand representation; for details, refer to the assembler
specifications. If two or more items are available in the
description method, select one.
Uppercase letters, such as "PI' or "PSV\(" are key symbols and must be written as shown in the Registers,
Flags, and Symbols table. See the Registers, Flags and
Symbols table for the list of key symbols. Lowercase
letters, such as "sfr" or "mem" are not key symbols and
an absolute value or label must be substituted by the
user when writing the instruction. For example, "MOV
A, sfr" may be written as "MOV A, PO." When the
symbols + , -, #, !, $, and [ I are used as a prefix of a
word, the symbol remains while lower case letters are
replaced by a value. For example, "ADD A, #byte" may
be written as "ADD A, #OAFH ," or "BR $addr16" may be
written as "BR $LOOP1."
Symbols rand rp can be described using the functional
name or absolute name.
50632
•
I
NEe
pPD78KO Product Line
Operands
Registers, Flags, and Symbols (cont)
Symbol
Definitions
Symbol
#
Immediate data
Definitions
Register pair (AX); 16-bit accumulator
Absolute address
BC
Register pair (BC)
$
Relative address
DE
Register pair (DE)
[ 1
Indirect addressing
HL
Register pair (HL)
Register
Functional name: X, A, C, B, E, D, L, H
Absolute name: RO to R7
RPORP3
Register pairs 0 to 3 (absolute names)
rp
Register pair
Functional name: AX, BC, DE, HL
Absolute name: RPO to RP3
sfr
Special Function Registers (8-bit).
See the table "Special Function Registers (!lPD78KO
Product Line)." This table shows the SFRs included in
each device family, access units usable with each SFR,
and the reserved symbol and address of each SFR.
sfrp
Special Function Register Pair (16-bit).
See the table "Special Function Registers (!lPD78KO
Product Line)." This table shows the SFRs included in
each device family, access units usable with each SFR,
and the reserved symbol and address of each SFR.
saddr
Memory address addressed by means of short direct
addressing: FE20H-FFl FH immediate data or label.
saddrp
Memory address addressed by means of short direct
addressing pair: FE20H-FFl EH immediate data or label
(even address only)
addr16
l6-bit address: OOOOH-FFFFH immediate data or label
(even address only)
addrll
II-bit address: 0800H-OFFFH immediate data or label
addr5
5-bit address: 40H-7EH immediate data or label (even
address only)
PC
Program counter
SP
Stack pointer
PSW
Program status word
Cy
Carry flag
AC
Auxi liary carry flag
Z
Zero flag
RBS1RBSO
Register bank select flags
IE
Interrupt enable flag
jdisp8
Signed 2's complement data (8 bits) indicating
relative address distance between first address of
next instruction and branch destination address
( )
Memory contents indicated by address or register
contents in ( )
xxH
Hexadecimal number
Higher 8 bits and lower B bits of l6-bit register
pair
/\
Logical product (AND)
v
Logical SUM (OR)
Exclusive logical sum (exclusive OR)
Inverted data
word
l6-bit data: 16-bit immediate data or label
byte
B-bit data: 8-bit immediate data or label
bit
3-bit immediate data (bit position in byte) or label
Flag Column Indicators
RBn
Register bank: RBO-RB3
Symbol
Action
Blank
No change
Registers, Flags, and Symbols
Symbol
Definitions
A
A register; 8-blt accumulator
X
X register
B
B register
C
C register
D
D register
E
E register
H
H register
L
L register
RO-R7
Registers 0 to 7 (absolute names)
2
o
Cleared to 0
Set to 1
x
Set or cleared depending on the result
R
Value previously saved is restored
NEe
pPD78KO Product Line
Instruction Set (jLPD78KO Product Line)
Flags
Mnemonic
Operand
Operation
Bytes
Z
AC
CY
x
x
x
x
x
x
8·Bit Data Transfer
MOV
r, #byte
r <- byte
2
seddr, #byte
(saddr) <- byte
3
sfr, #byte
sfr <- byte
3
A,r (Note 1)
A<-r
r,A (Note 1)
r <- A
A, saddr
A ..... (saddr)
2
saddr, A
(saddr)
2
A,sfr
A <- sfr
sfr, A
sfr ..... A
2
A, !addr16
A <- (addr16)
3
!addr16, A
(addr16)
A
3
PSW, #byte
PSW <- byte
3
A,PSW
A ..... PSW
2
PSW,A
PSW <- A
2
A, [DE]
A <- (DE)
<-
[DE], A
(DE) ..... A
A ..... (HL)
(HL) ..... A
[HL], A
[HL
+
A, [HL
[HL
+
A, [HL
[HL
+
A
2
A, [HL]
A, [HL
XCH
<-
+
byte]
A ..... (HL
+
byte)
2
2
(HL
+
A+- (HL
B]
+
B], A
(HL
+
A ..... (HL
C]
C], A
A, r (Note 1)
(HL
+
+
byte) ..... A
byte], A
+
B)
B) +- A
+
C)
C) ..... A
A"'r
A, saddr
A- (saddr)
A, sfr
A-sfr
2
A, !addr16
A ... (addr16)
3
A, [DE]
A- (DE)
A, [HL]
+
[HL +
[HL +
2
A ... (HL)
+
+
(HL +
A, [HL
byte]
A ... (HL
byte)
2
A,
B]
A ... (HL
B)
2
C]
A ...
C)
2
A,
3
..
i
NEe
JlPD78KO Product Line
Instruction Set ("PD78KO Product Line) (cont)
Flags
Mnemonic
Operand
Operation
Bytes
Z
AC
CY
16-Bit Data Transfer
MOVW
XCHW
rp,#Word
rp
saddrp, #Word
(saddrp)
word
<-
sfrp, #Word
sfrp
fJo---'---~
Schmitt trigger Input with hysteresis characteristic.
IN
O_---I~------;~~
Schmitt !IIpr klput with hysteresis characte~stIc.
pullup enable - - - - - - - [ > 0 > - - - - - 1
Voo
date~
OUtputdlsable~
Push-pun output where the output can be placed In
hlgh~mpedanca (both P and N channels are tumed off).
...-.......-..-- 0 > - - - - - - 1
Voo
pullup enable
------[>o>----II~
Voo
date~
Outputdlsable~
...-.. . . --<>
INfOUT
...L
...-......._ - - 0 INfOUT
VREF (Threshold Voltage)
Input enable _ _ _ _ _ _---J
83YL-9171B
14
NEe
pPD78214 Family
Input/Output Ports
There are up to 54 port lines on the pPD78212/214/P214
and upt036 port lines onthepPD78213. (Ports 4,5, and
two bits of port 6 are not available on the pPD78213
since the pPD78213 must always use external memory.) Table 2 lists the features of each port and figure 3
shows the structure of each port pin. The pin levels of
all port 2, 3, and 7 pins can always be read or tested
regardless of the dual pin function.
Table 2_ Digital Port Functions
Configuration
Direct Drive
Capability
Software Pull up
Resistor Connection
Port
Operational Features
PortO
8-bit high impedance output
Port 2
8-bit Schmitt trigger input
Port 3
8-bit input or output
Bit selectable
Port 4
8-bit input or output
Byte selectable
LED
Byte selectable
PortS
8-bit input or output
Byte selectable
LED
Byte selectable, input bits only
Port 6
4-bit output (bits 0 to 3)
4-bit input or output (bits 4 to ?)
Bit selectable
Port?
6-bit input
Transistor
In 6-bit unit (P22 - P27)
Byte selectable, input bits only
•
In 4-bit unit, input bits only
Note: Software pullup resistors can be internally connected only on
a port-by-port basis to port bits set to input mode. Pullup
resistors are not connected to port bits set to output mode.
Real-time Output Port
The real-time output port (RTPC) shares pins with port
O. It can be used as two independent 4-bit real-time
output ports or one 8-bit real-time output port. In the
real-time output mode, data stored beforehand in the
buffer registers, POH and POL, is transferred immediately to the output latch of PO on the occurrence of a
timer 1 interrupt (INTC10 or INTC11) or external interrupt (INTPO) (see figure 4). By using the real-time
output port with the macro service function, port 0 can
be used to output preprogrammed patterns at preprogrammed variable time intervals. In this mode, two
independent stepper motors can accurately be driven
at a fixed or variable rate.
15
pPD78214 Family
Figure 4.
Rea~ Time
NEe
Output Port
83Yl·01728
16
NEe
pPD78214 Family
Analog-to-Digital (AID) Converter
The pPD78214 family AID converter (see figure 5) uses
the successive-approximation method for converting
up to eight multiplexed analog inputs into a-bit digital
data The conversion time per input is 30 ps at 12 MHz
operation. AID conversion can be started by an external interrupt, INTP5, or under software control.
The AID converter can operate in either scan mode or
select mode. In scan mode, from one to eight sequential inputs can be programmed for conversion. The AID
data, stores it in the AID conversion result (ADCR)
register, and generates an interrupt (INTAD). This converted data can be easily transferred to memory by
using the macro service function.
In select mode, only one of the eight AID inputs can be
selected for conversion. The ADCR register is continually updated and can be read at any time. If the AID
converter is started by an external interrupt, an INTAD
interrupt occurs at the completion of each conversion.
If the AID converter is started by software, no interrupts are generated.
Figure 5. AID Converter
Register St~ng
r--I-----~
ANO
Sample and
Hold Clrouft
AN1
AN2
AN3
AN4
AN5
ANa
1---- 1
1
:
1
1
1
1
1
1
1
1
1
1
1
Rl2rAVREF
1
1
R
1
1
1
1
I:
1
1
1
1
1
1
1
1
1
1
~--------.;
Tap
1Seleclor
1
1
1
1
1
1 T:
rh
1
:
1
1
1
1
Input
I-----i--o
Seleclor
1
1
1
1_ _ _ _ -'
AW
:
:
-----_)01
~
~2~
:
~AVSS
!.-. ___L ____ .J
INTAD
P2e/lNTPS
1
•
Selector
r
Interrupt Request
8
Trigger Enable
Internal Bus
17
NEe
pPD78214 Family
Serial Interface
The pPD78214 family has two independent serial interfaces. The first is a standard UART. The UART (figure 6)
permits full-duplex operation and can be programmed
for 7- or 8-bits of data after the start bit, followed by one
or two stop bits. Odd, even, zero or no parity can also
be selected. The serial clock for the UART can be
provided by an on-chip baud rate generator or timer 3.
By using either the internal system clock or an external
clock input into the ASCK pin, the baud rate generator
is capable of generating all of the commonly used
baud rates. The UART generates three interrupts: INTST (transmission complete), INTSR (reception complete), and INTSER (reception error).
Figure 6. Asynchronous Serial Interface
Internal Bus
L - - - - - - - - r__------~----.
Baud Rale Generator
1- - - - - -
- - - - - - I
BRGC
fClK
INTP4IASCK
a-8ttllmer3
83YL-9174B
18
NEe
pPD78214 Family
The second interface is an a-bit clock-synchronized
serial interface (figure 7). It can be operated in either a
three-wire serial I/O mode or NEC serial bus interface
(SBI) mode.
In the three-wire serial I/O mode, the a-bit shift register
(SIO) is loaded with a byte of data and eight clock
pulses are generated. These eight pulses shift the byte
of data out of the SO line (MSB first) and in from the SI
line providing full-duplex operation. This interface can
also be set to receive or to transmit data only. The
INTCSI interrupt is generated after each a-bit transfer.
One of three internal clocks or an external clock clocks
the data.
Figure 7. Clock-Synchronized Serial Interface
Selector
N-ch Open·Draln
Oulpul Possible
~
I
I
Bus Release!
Command!
Acknowledge
Detecllon
CirculI
8·BII lImer 3
83YL-9176B
19
NEe
pPD78214 Family
The NEC SSI mode is a two-wire high-speed proprietary
serial interface available on most devices in the NEC
IlPD75xxx and IlPD78xxx product lines. Devices are
connected in a master/slave configuration (see figure
8). There is only one master device at a time; all others
are slaves. The master sends addresses, commands,
and data over the serial bus line (SSO) using a fixed
hardware protocol synchronized with the SCK line.
Each slave IlPD78214 family device can be programmed in software to respond to anyone of 256
addresses. There are also 256 commands and 256 data
types. Since all commands are user definable, any
software protocol, simple or complex, can be defined.
It is even possible to develop commands to change a
slave into a master and the previous master into a
slave.
Figure 8. S8t Mode Master!Stave Configuration
Slave cpu
(J
(J
Master CPU
BO
SBO
_
SCK
Address 1
SCK
Slave
cpu
BO
_
t
,
20
Address 2
,
SlavelC
SBa
~
The IlPD78214 family has one 16-bit timer and three
8-bit timers. The 16-bit timer counts the internal system
clock (feLKl8) while the three 8-bit timers can be programmed to count a number of prescaled values of the
internal system clock. One of the 8-bit timers can also
count external events.
Timer 0 consists of a 16-bit timer (TMO), two 16-bit
compare registers (CROO and CR01), and a 16-bit capture register (CR02). Timer 0 can be used as two
interval timers, to output a programmable square wave
or two pulse-width modulated signals, or to measure
pulse widths (see figure 9).
Timer 1 consists of an 8-bit timer (TM1), 8-bit compare
register (CR10), and 8-bit capture/compare register
(CR11). Timer 1 can be used as two interval timers or to
measure pulse widths. In addition, it can be used to
generate the output trigger for the real-ti me output port
(see figure 10).
Timer/counter 2 consists of an 8-bit timer (TM2), two
8-bit compare registers (CR20 and CR21), and an 8-bit
capture register (CR22). Timer/counter 2 can also be
used as two interval timers, to output a programmable
square wave or two pulse-width modulated Signals, or
to measure pulse widths. In addition, it can be used to
count external events sensed on the CI line or as a
one-shot timer (see figure 11).
Timer 3 consists of an 8-bit timer (TM3) and an 8-bit
compare register (CR30). Timer 3 can be used as an
interval timer or as a clock for the clock-synchronized
serial interface (see figure 12).
~I SCK
Fl
Timers
AddressN
S3Yl·9178A.
NEe
Figure 9.
pPD78214 Family
16-Bit Timer 0
Pulse
Output
Control
P3SfT01
'----------~
INTCOO
' - - - - - - - - - INTC01
83YL-9177B
Figure 10.
B-Bit Timer 1
1,
fCLK1512
•
fCLKI256
fCLK/128
fCLK/64
fCLKI32
fCLKI16
1-_-"CO"'I"'ncI""dence="'--_-+-_ INTC10
To ReaI·11mB
} OulputPort
1-_--=CO='"C::Id::B::..:nce=--_......._
INTC11
83YL-9178B
21
~.
:
NEe
pPD78214 Family
Figure 11. 8-Bit Timer/Counter 2
fCLK/512fCLK/256-
IOve~w I
fCLK/128fCLK/64
Flag
fCLK/32
fCLK/16
Pulse
Output
Control
'-------~ INTC20
' - - - - - - - - - 4 > INTC21
83Yl.-91795
Figure 12. 8-Bit Timer 3
fCLK/512fCLK'256-fCLK/128fCLK/64 -
MPX
Clear
UART
fCLK/32fCLK/16
fCLK/8
Clock·Synchronlzed Serial Interface
Coincidence
INTP4IINTC30
83YL·9180B
22
NEe
pPD78214 Family
Interrupts
The pP078214 family has 18 maskable hardware interrupt sources; 6 are external and 12 are internal. Since
there are only 16 interrupt vectors and sets of control
flags, 2 of the 6 external maskable interrupts, INTP4
and INTP5, share interrupt vectors and control flags
with INTC30 and INTAO respectively. The active interrupt source for each shared vector must be chosen by
the program. In addition, there is one nonmaskable
interrupt and one software interrupt. The software
interrupt, generated by the BRK instruction, is not
maskable (see table 3).
TBble 3. Interrupt Sources Bnd Vector Addresses
Interrupt
Request
Type
Default
Priority
Software
None
BRK instruction execution
Nonmaskable
None
NMI (pin input edge detection)
Maskable
Interrupt Request Generation Source
Macro Service
Type
Vector
Table
Address
003EH
0002H
o
INTPO (pin input edge detection)
A, B
INTPl (pin input edge detection)
A, B
OOOBH
2
INTP2 (pin input edge detection)
A, B
OOOAH
3
INTP3 (pin input edge detection)
B
OOOCH
4
INTCOO (TMO-CROO coincidence signal generation)
B
0014H
5
INTCOl (TMO-CROl coincidence signal generation)
B
0016H
6
INTC10 (TM1-CR10 coincidence signal generation)
A, B, C
001BH
0006H
_ _ _7_ _ _ _IN_TC_l_l_(T_M_l_-C_R_l_l_c_o_in_ci_de_n_c_e_s_ig_na_l_g_en_e_ra_t_io_n)_ _ _ _ _ _ _ _ _A_,_B_,_C_ _ _ _0_0_1A_H_
B
INTC21 (TM2-CR21 coincidence signal generation)
9
INTP4 (pin input edge detection)
INTC30 (TM3-CR30 coincidence signal generation)
10
INTP5 (pin input edge detection)
A, B
001 CH
B
OOOEH
A, B
B
INTAD (end of AID conversion)
A, B
11
INTC20 (TM2-CR20 coincidence signal generation)
A, B
12
INTSER (generation of asynchronous serial interface receive error)
0010H
0012H
0020H
13
INTSR (end of asynchronous serial interface reception)
A, B
0022H
14
INTST (end of asynchronous serial interface transmission)
A, B
0024H
15
INTCSI (end of clocked serial interface transmission)
A, B
0026H
Interrupt Servicing. The pPD78214 family provides
two levels of programmable hardware priority control
and two different methods of handling maskable interrupt requests: standard vectoring and macro service.
The programmer can choose the priority and mode of
servicing each maskable interrupt by using the interrupt control registers.
Interrupt Control Registers. The pP078214 family has
four 16-bit interrupt control registers. Each bit in each
register is dedicated to one of the 16 active maskable
interrupt sources. The interrupt request flag register
(IFO) contains an interrupt request flag for each interrupt. The interrupt mask register (MKO) is used to
enable or disable any interrupt. The interrupt service
mode register (ISMO) specifies whether an interrupt is
processed by vectoring or macro service. The priority
flag register (PRO) can be used to specify a high or a low
priority level for each interrupt.
Two other 8-bit registers are associated with interrupt
processing. The interrupt status register (1ST) indicates if a nonmaskable interrupt request on the NMI pin
is being processed and can be used to allow nesting of
nonmaskable interrupt requests. The IE and the ISP bits
of the program status word are also used to control
interrupts. If the IE bit is zero, all maskable interrupts,
but not macro service, are disabled. The IE bit can be
set or cleared using the EI and 01 instructions, respectively, or by directly writing to the PSW The IE bit is
cleared each time an interrupt is accepted. The ISP bit
is used by hardware to hold the priority level flag of the
interrupt being serviced.
23
~
~J
NEe
pPD78214 Family
Interrupt Priority. The nonmaskable interrupt (NMI)
has priority over all other interrupts. Two hardware
controlled priority levels are available for the m~kable
interrupts. Either a high or a low priority level can be
assigned by software to each of the maskable interrupts. Interrupt requests of a priority higher than the
processor's current priority level are accepted; requests of the same or lower priority are held pending
until the processor's priority state is lowered by program control within the current service routine or by a
return instruction from the current service routine.
Vectored Interrupt. When vectored interrupt is specified for a given interrupt request, (1) the program
status word and the program counter are saved on the
stack, (2) the processor's priority is set to that specified for the interrupt, (3) the IE bit in the PSW is set to
zero, and (4) the routine whose address is in the
interrupt vector table is entered. At the completion of
the service routine, theRETI instruction (RETB instruction for the software interrupt) reverses the process
and the IlPD78214 family device resumes the interrupted routine.
Interrupt requests programmed to be handled by
macro service have priority over all vectored interrupt
service regardless of the assigned priority level, and
macro service requests are accepted even when the
interrupt enable bit in the PSW is set to the disable state
(see figure 13).
Macro Service
The default priorities listed in table 3 are fixed by
hardware and are effective only when it is necessary to
choose between two interrupt requests of the same
software-assigned priority. For example, the default
priorities would be used after the completion of a high
priority routine if two interrupts of the same priority
routine were pending.
The software interrupt, initiated by the BRK instruction, is executed regardless of the processor's priority
level and the state of the IE bit. It does not alter the
processor's priority level.
Figure 13. Interrupt Service Sequence
Interrupt Requesl
L
xxMK • 1· (Interrupt Masked) Interrupt Pending.
xxMK = 0 (Unmasked)
I
ISM = 1 MaclO Service.
t:::SM =0 VecIOrad Interrupt Service.
b
m, - - EI VecIOAld Interrupt
24
When macro service is specified for a given interrupt,
the macro service hardware temporarily stops the
executing program and begins to transfer data between the special function register area and the memory space. One byte is transferred each interrupt. When
the data transfer is complete, control is returned to the
executing program, providing a completely transparent method of interrupt service. Macro service significantly improves response time and makes it unnecessary to save any registers.
For each request on the interrupt line, one operation is
performed, and an 8-bit counter is decremented. When
the counter reaches zero, a vectored interrupt service
routine is entered according to the specified priority.
Macro service is provided for all of the maskable interrupt requests except INTSER, the asynchronous serial
interface receive error interrupt request. Each interrupt
request has a dedicated macro service control word
stored in Internal RAM (see figure 14). The function to
be performed is specified in the control word.
The IlPD78214 family provides three different types of
macro service transfers.
NEe
IlPD78214 Family
Figure 14. Macro Service Control Wont Map
OFEOFH
OFEDEH
Channel Pc*Iter
OFEDDH
Channel PoInter
OFEDCH
Mode RegIatar
OFEDBH
OFEDAH
Channel PoInter
Mode Register
OFED9H
OFED8H
Channel PoInlar
OFED7H
Channel PoInlar
OFED8H
Mode Register
OFED6H
OFED4H
Channel PoInter
OFED3H
Channel PoInter
OFED2H
Mode Register
OFED1H
Channel PoInter
OFEDOH
OFECFH
Mode Register
Channel PoInter
OFECEH
Mode Regle\ar
OFECDH
OFECCH
Channel PoInter
OFECBH
OFECAH
Channel PoInter
OFEC9H
OFECSH
Channel Polnlar
OFEC7H
Channel Polnlar
OFECSH
Mode RegIster
OFECSH
OFEC4H
Channel Pointer
OFEC3H
OFEC2H
Channel Polnlar
Mode Raglslar
Mode Reg/slar
Mode Register
Mode Register
Mode Register
Mode Register
Mode Register
Mode Register
INTSR
INTST
INTCSI
1NTC10
INTell
IN1P4IINTC30
Table 4. Macro Service Type A Interrupts and
Assigned SFRs
Interrupt Request
Source/Destination SFR
INTC10: TM1-CR10 coincidence
CR10: Timer 1 B-bit compare
register
INTC11: TM1-CR11 coincidence
CR11: Timer 1 B-bitcapture/
compare register
INTC20: TM2-CR20 coincidence
CR20: Timer 2 B-bit compare
register
INTC21: TM2-CR21 coincidence
CR21: Timer 2 B·bit compare
register
INTC30: TM3·CR30 coincidence
CR30: Timer 3 B·bit compare
register
INTSR: End of asynchronous serial RxB: Serial receive buffer
interface reception
INlP5IINTAD
INTST: End of asynchronous serial TxS: Serial transmit shift
interface transmission
register
INTCOO
INTCSI: End of clocked serial
SID: Serial shift register
interface transmission
INTCOI
INTAD: End of A/D conversion
ADCR: A/D conversion result
register
INTC20
p_t_p_in_p_o_1__
P
_IN_TP_O:_Ex_t_er_n_al_i_nt_er_r_u
CR_1_1_:_T_im_e_r_1_B_-b_it_c_a_
.,'
_
compare register t_u_re_/_._
1NTC21
INTPO
INTP1: External interrupt pin P02
CR22: Timer 2 B·bit capture
register
INTP2: External interrupt pin P03
TM2: Timer 2 B·bit timer
register
INTPI
INTP2
INTP3
1tI'/I._
Macro Service Type A. A byte of data is transferred in
either direction between a special function register,
preassigned for each interrupt request, and a buffer in
Internal RAM (FExx). The preassigned SFRs for the 12
interrupt requests that support macro service Type A
transfers are listed in table 4.
Macro Service Type B. A byte of data is transferred in
either direction between any specified special function
register and a buffer anywhere in the 64K byte address
space. Macro service Type B transfers can be initiated
by any maskable interrupt except INTSER.
Macro Service Type C. A byte of data is transferred
from a buffer anywhere in the 64K byte address space to
one of the 8-bit compare registers of timer 1. At the
same time, a second byte of data is transferred from a
buffer anywhere in the 64K byte address space to the
real-time output port buffer. Macro service Type C
transfers can be initiated by INTC10 with data transferred to CR10 and POL or POH, or by INTC11 with data
transferred to CR11 and POL or POH.
In addition, the macro service Type C transfer can be
initialized to automatically alter timer compare regiSter values or to repeatedly output a prespecified pattern at a fixed or variable rate. By using macro service
Type C transfers to control the real·time output ports,
the pPD78214 family can easily and accurately drive
two independent stepper motors.
25
NEe
pPD78214 Family
Refresh
The refresh signal is used with any pseudostatic RAM
equivalent of the NEC pPD428128. The refresh cycle can
be set to one of four intervals: 16, 32, 64, or 128/fcLK
(2.6, 5.3, 10.7, and 21.3 ps at 12 MHz). The refresh cycle
is timed to follow a read or write operation to avoid
interference with external memory access cycles.
Standby Modes
HALT and STOP modes are provided to reduce power
consumption when CPU action is not required. In HALT
mode, the CPU is stopped but the system clock continues to run. The HALT mode is released by any
unmasked interrupt, an external NMI, or an external
reset pulse. In STOP mode, both the CPU and the
system clock are stopped, further minimizing the
power consumption. The STOP mode is released by
either an external reset pulse or an external NMI. The
HALT and STOP modes are entered by programming
the standby control register (STBC). This register is a
protected location and can be written to only by a
special instruction. If the third and fourth bytes of the
instruction are not complements of each other, the
data is not written and the next instruction is executed.
External Reset
The pPD78214 family is reset by taking the RESET pin
low. The RESET input pin contains a noise filter to
protect against spurious system resets caused by
noise. On power-up, the RESET pin must remain low
until the power supply reaches its operating voltage
and the oscillator has stabilized. During reset, the
program counter is loaded with the address contained
in the reset vector table (address OOOOH, 0001 H); program execution starts at that address upon the RESET
pin going high. While RESET is low, all external lines
except Vss, VDD, AVss, AVREF, X1, and X2 are in the high
impedance state.
26
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
TA = +25'C
Operating voltage, VDD
AVREF
AVss
-0.5 to + 7.0 V
-0.5 to VDD + 0.5 V
-O.!i to + 0.5 V
Input voltage, V11
VI2 (Note 1)
V13 (Note 2 for JlPD78P214)
-0.5 to VDD + 0.5 V
-0.5 to AVREF + 0.5 V
-0.5 to +13.5 V
Output voltage, Vo
-0.5 to VDD + 0.5 V
Low-level output current, IOL
per pin
total, all output pins
15 mA
100mA
High-level output current, IOH
per pin
total, all output pins
-10mA
-SOmA
Operating temperature, TOPT
-40 to +85'C
Storage temperature, TSTG
-65 to +l50'C
Notes:
(1) Pins P701ANO - P751AN5, PSelWAI17AN6, and P67/REFRQ/AN7
when the pin is used as the AID converter input or is selected by
bits AN10-AN12 of the ADM register when the AID converter is
not in operation. However, Vll absolute maximum ratings should
also be satisfied.
(2) P2o/NMI, EA/V pp, and P21/1NTPO/Ag pins in the PROM programming mode
Exposure to absolute maximum ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent damage. The device should be operated within the limits
specified under DC and AC characteristics.
Operating Conditions
Oscillation Frequency
VDD
-40 to +85'C
IXX = 4 to 12 MHz
Capacitance
TA = +25'C; VDD = Vss =
ov
Item
Symbol
Input capacitance'
+5V ±10%
Max
Unit
Conditions
20
pF
1= 1 MHz;
Output capacitance
Co
20
pF
Input/output capacitance
Cro
20
pF
pins not
used lor
measurement
are atOV
NEe
,.,PD78214 Family
DC Characteristics
TA = -40 to +85'C; VOO = +5 V ±10%; Vss = 0 v
Item
Symbol
Min
Low-level input voltage
High-level input voltage
Max
Unit
a
0.8
V
2.2
VOO
V
Except the specified pins (Notes 1, 2)
V
Specified pins (Note 1)
Typ
2.2
VIH2
VOO
V
Specified pins (Note 2)
VOL1
0,45
V
IOl = 2.0 mA
VOl 2
1.0
V
IOl = 8.0 mA (Note 3)
0. 8VOO
Low-level output voltage
High-level output voltage
Conditions
VOHl
VOO-l.0
V
IOH = -1.0 mA
VOH2
VOO-0.5
V
IOH = -100 IlA
VOH3
2.0
V
IOH = -5.0 mA (Note 4)
Xl low-level input current
III
-100
IlA
a :S
Xl high-level input current
IIH
100
IlA
VIH3 :S VI S VOO
Input leakage current
III
±10
IlA
OVsVI sVOO
±10
IlA
OVsVo sVOO
1.5
5.0
mA
Operating mode,
20
40
mA
Operating mode, fxx = 12 MHz
Output leakage current
AV REF current
AIREF
VOO power supply current
7
Data retention voltage
V OOOR
Data retention current
IOOOR
Pullup resistor
!xx =
12 MHz
III
HALT mode, fxx = 12 MHz
20
mA
5.5
V
2
20
IlA
5
50
IlA
STOP mode; VOOOR = 5 V ±10%
40
80
kO
VI = OV
2.5
15
VI :S Vil
STOP mode
I
STOP mode; VOOOR = 2.5 V
Notes:
(1) Pins P701ANO - P7:;1AN5, P6sJWAIl7AN6, and P67/REFRQJAN7
when the pin is used as the A/D converter input or is selected by
bits AN10 - AN12 of the ADM register when the ND converter is
not in operation.
(2) Xl, X2, RESET, P201NMI, P21/1NTPO, P22/iNTPl,P2alINTP2/CI,
P2.vINTP3, P2...sL!NTP4/ASCK, P2s1INTP5, P27/SI, P~/SCK, P3a1
SO/S80, and EA pins.
(3) Pins P401ADo - P47/A~, and P501As - P57/A 15.
(4) Pins POo - P07.
27
NEe
pPD78214 Family
AC Characteristics-Read/Write Operation
TA = -40 to +85°C; VOO = +5
v ±10%; VSS =
Item
0 V;
Symbol
XI input clock cycle time
tcvx
Address setup time to ASTB ~
tsAST
Address hold time from ASTB I (Note 1)
Address hold time from RD!
Address hold time from WR
t
Address to RD I delay time
fxx
= 12 MHz; CL = 100 pF
Calculation Formula (2, 3)
Min
Max
Unit
82
250
ns
52
ns
tHSTA
25
ns
tHRA
30
ns
tHWA
30
ns
tDAR
tcvx- 3O
2tcvx- 35
129
ns
11
ns
Conditions
Address float time to RD I
tFAR
tcvxl2-30
Address to data input time
tOAIO
(4+ 2n)tcvx - 100
228
ns
No wait states
tOSTIO
(3+ 2n)tcvx - 65
181
ns
No walt s1ates
ns
No wait states
ASTB
~
to data input time
RD ~ to data input time
100
tORIO
(2+ 2n)tcvx - 64
ASTB ~ to RD I delay time
tOSTR
tcvx- 3O
52
Data hold time from RD !
tHAIO
0
ns
124
ns
ns
ns
RD ! to address active time
tORA
2tcvx-4O
RD ! to ASTB ! delay time
tORST
2tcvx-4O
124
twRL
(2+ 2n)tcvx - 40
124
ns
twSTH
tcvx- 3O
52
ns
129
RD low-level width
ASTB high-level width
Address to WR I delay time
tOAW
2tcvx-35
ASTB I to data output time
tOSTOO
tcvx + 60
No wait states
ns
142
ns
60
ns
WR ~ to data output time
tOWOO
ASTB ~ to WR ~ delay time
tOSTWl
tCYX- 3O
52
ns
tOSTW2
2tcvx-35
129
ns
Refresh mode
t
tSOOWR
(3+ 2n)tcvx - 100
146
ns
No wait states
Data setup time to WR ~
tsoOWF
tCYX-60
22
ns
Refresh mode
20
ns
Data setup time to WR
Data hold time from WR
WR
t (Note 1)
t to ASTB t delay time
WR low-level width
tHWOO
tOWST
tcvx- 4O
42
ns
twWLl
(3 + 2n)tcvx - 50
196
ns
No wait states
twWL2
(2+2n)tcvx- 5O
114
ns
Refresh mode; No wait
states
Address to WAIT I Input time
tOAWT
3tcvx-IOO
146
ns
ASTB I to WAIT ~ input time
tOSTWT
2tcvx- 8O
84
ns
WArr hold time from ASTB ~
tHSTWT
2Xtcvx + 10
ASTB I to WAIT t delay time
tosTWlH
2(1 + X)tcvx - 55
RD I to WAIT input time
tORWTL
tcvx- 6O
WArr hold time from RD I
tHRWT
(2X-l)tcvx + 5
ns
One external wait state
RD I to WAIT t delay time
tORWTH
(2X+l)tcvx - 60
186
ns
One external wait state
WAIT t to data input time
tOWTIO
tcvx- 2O
62
ns
WAIT t to WR
tOWTW
2tcVX-1O
154
tOWTA
tCYX-10
72
tOWWTL
tCYX-60
WAIT t to RD
t delay time
t delay time
WR I to WArr il1put time
28
174
ns
One external wait state
273
ns
One external wait state
22
ns
87
ns
ns
22
ns
Refresh disabled
NEe
pPD78214 Family
AC Characteristics-Read/Write Operation (cont)
Item
WAIT hold time from WR
WR
+
+to WAIT f delay time
RD f to REFRQ
+delay time
+delay time
Symbol
Calculation Formula (2, 3)
tHWWTl
(2X-l)tcyx + 5
Min
87
Max
Unit
ns
One external wai t state;
refresh disabled
tHWWT2
2(X-l)tCYX + 5
5
ns
One external wait state;
refresh enabled
tOWWTHl
(2X+l)tcyx-60
186
ns
One external wait state;
refresh di sabled
tOWWTH2
2Xtcvx-60
104
ns
One external wait state;
refresh enabled
tORRFQ
2tcyx-l0
154
ns
tOWRFQ
tcvx- 1O
72
ns
REFRQ low-level width
twRFQL
2tcyx-44
120
ns
REFRQ f to ASTB t delay time
tORFQST
4tcyx-48
280
ns
WR f to REFRQ
Conditions
Notes:
(1) The hold time includes the time during which VOH and VOL are
retained under the following load conditions: CL
100 pF and
RL
2 kQ
=
=
(2) n indicates the number of internal wait states.
•
(3) x indicates the number of external walt states (I, 2, 3, ...)
Serial Port Operation
TA
= -40 to +85'C; VOO = +5 V ±10%; vss = 0 V; !xx = 12 MHz; CL = 100 pF
Item
Symbol
Serial clock cycle time
tCYSK
Serial clock low-level width
Serial clock high-level width
twSKL
tWSKH
Min
Max
Unit
Conditions
1.0
Jis
External clock input
1.3
Jis
Internal clock/16 output
Internal clock/64 output
5.3
JiS
420
ns
External clock input
556
ns
Internal clock/16 output
Internal clock/64 output
2.5
JiS
420
ns
External clock input
556
ns
Internal clock/16 output
Internal clock/64 output
2.5
JiS
tSSSK
150
ns
SI, SBO hold time from SCK t
tHSSK
400
SO/SBO output delay time from SCK +
tOSBSKl
a
300
ns
CMOS push-pull output
(3-line serial I/O mode)
tOSBSK2
a
800
ns
Open-drain output
(SBI mode), RL
1 kO
tHSBSK
4
toyx
SBI mode
SBI mode
SI,
sao setup time to SCK t
seo high,
hold time from SCK t
SBO low, setup time to SCK +
sao low-level width
seo high-level width
ns
tSSBSK
4
tcyx
twSBL
4
tcyx
twSBH
4
tcyx
=
29
I
NEe
IlPD78214 Family
AID Converter Operation
TA
= -40 to +85°C; Voo = +5 V ±10%; Vss = AVss = 0 v
Item
Symbol
MinTyp
Resolution
Max
Full-scale error (Note 1)
Quantization error
teONV
Sampling time
tsAMP
Analog input voltage
VIAN
Analog input impedanoe
RAN
Analog reference voltage
AV REF = 4.0VtoV oo
LSB
83 ns s tcvx os; 125 ns (Note 2)
tevx
125 ns :s tevx
72
tevx·
83 ns
48
tevx
125 ns
-0.3
V
AVAEF + 0.3
AIAEF
V
mA
Operating mode,
0.2
1.5
mA
STOP mode
Symbol Min Max Unit Conditions
NMllow-level width
twNll
10
/.Is
NMI high-level width
twNIH
10
/.Is
tevx
twlTl
24
tcvx
RESET low-level width
twASl
10
/.Is
RESET high-level width
twASH
10
/.Is
MO
5.0
+5 V ±10%; Vss = 0 V
INTPO-INTP5 high-level width twlTH
s 250 ns (Note 3)
s 125 ns (Note 2)
s tevx s 250 ns (Note 3)
tcvx
Voo
Item
24
s
1.5
3.4
Interrupt Timing Operation
30
%
240
(3) FR bit of ADM registers is 1.
INTPO-INTPS low-level width
AVREF = 3.4 V to Voo; TA = -10 to + 70°C
0.8
tevx
(2) FR bit of ADM register is O.
= -40 to +85°C; Voo =
AVREF = 4.0V to Voo; TA = -10 to +70°C
%
360
Note:
(1) Quantization emor is not included. Unit is defined as percent of
ful~scale value.
TA
%
0.8
1000
AVREF
AVAEF current
Conditions
0.4
±1/2
Conversion time
Unit
Bit
8
fxx ,.
12 MHz
NEe
JlPD78214 Family
Data Retention Characteristics
TA = -40 to +85"C
Item
Symbol
Min
Data retention voltage
V OOOR
2.5
Data retention current
IOOOR
Typ
Max
Unit
Conditions
5.5
V
STOP mode
2
20
/lA
VOOOR = 2.5 V
5
50
/lA
VOOOR = 5 V ±10%
VOO rise time
tRVO
200
VOO fall time
tFVO
200
/ls
VOO retention time
(from STOP mode setting)
tHVO
0
ms
STOP release signal input time
tOREl
0
ms
Oscillation stabilization wait time
twAIT
30
ms
5
ms
/lS
Crystal resonator
Ceramic resonator
Low-level input voltage
VIL
0
0.1 V OOOR
V
Specified pins (Note 1)
High-level input voltage
VIH
0.9 VOOOR
VOOOR
V
Specified pins (Note I)
External Clock Operation
Note: RESET, P201NMI, P21/INTPO, P22iINTPI, P2a/INTP2/CI, P24/
INTP3, P25/INTP4/ASCK, P2s1INTP5, P27/SI, P32/SCK, P3a/SO/
SBO, and EA pins.
TA
Recommended Resonator Circuit
XI input low-level width
XI input high-level width
=
-40 to +85"C; VOO
Item
=
0V
Min
Max
Unit
twXL
30
130
ns
twXH
30
130
ns
30
ns
tXR
a
XI input fall time
tXF
0
30
ns
XI input clock cycle time
tcyx
82
250
ns
Conditions
Recommended Ceramic Resonators
X2
Manufacturer
Ceramic or crystal resonator frequency f xx = 4 to 12 MHz
Extemal osclllaUon clrcuft should be as close to U1e XI and
X2 pins as possible
Do not place oU1er signal lines In U1e shaded area
Murata Mfg.
Frequency
(MHz)
Part Number
Cl (pF)
CSAI2.0MT
12
CSTI2.0MTW (1)
83YL-918M
4
Recommended External Clock Circuit
Kyocera Corp.
~-1------I
+5 V ±10%; Vss
Symbol
XI input rise time
Cicek
=
30
None (2)
None (2)
CSA4.00MG040
100
100
CST4.00MG040
None (2)
None (2)
33
33
KBRI2.0M
12
C2 (pF)
30
Notes:
XI
(1) Recommended for /lPD78212/213/214 only.
HCMOS
Inverters
(2) Cl and C2 are contained in the resonator.
Recommended Crystal Resonators
X2
Manufacturer
Clodk frequency fxx = 4 to 12 MHz
In STOP mode, XI Is Internally shorted to Vssto prevent
leakage current. Therefore, STOP mode Is not available
when using this extemal clock circuit.
Kinseki
Frequency
(MHz)
Part
Number
Cl (pF)
C2 (pF)
12
HC-49/U
18
18
83YL·919M
31
-
i
I
NEe
pPD78214 Family
Timing Waveforms
Voltage Thresholds for AC Timing Measurements
v::~ ========X,--O_.8_V...:~~.8~~:....2_.2_V-JX,--
___
Read Operation
X1
,....- - - - - - - - - IOAIO - - - - - - + /
Input Data
Address
I+-~I---+/ IFAR
I 'osno
ASTB
IORIO
~----_IWRL--------~
83YW1B2.
32
NEe
pPD78214 Family
Timing Waveforms (cont)
Write Operation
X1
r-Output Data
tHWA
Address
ASTB
1+------;--- tWWL1
tWWL2
33
NEe
pPD78214 Family
Timing Waveforms (cant)
External WAIT Signal Input (Read Operation)
Input Data
Address
IOWTlO
ASlB
~-------tO~H------~
1+------- tHSTWT
..
I
------~--_7--------. ====:~:~~
RO
L
IOSTWT
I
tORWTL
IOWTR
s:m.-91848
34
NEe
,.,PD78214 Family
Timing Waveforms (cont)
Externlll WAIT Signlllinput (Write Operlltion)
Outpul Data
Address
ASTB
~----------I~nrrH----------~>1
~----------I~nrr----------~>I
1...E------IDWWTH1------~
I
:=:=i
1.."".------IHWWT1-----+l>
WR
""
L~
IOWlW
100WT
WAIT
83YL-9186B
35
NEe
"PD78214 Family
Timing Waveforms (cont)
Refresh After Read
1
ASlB
RO
/
tORFQST
tORRFQ
I
.1
REFRQ
I
1
tWRFQL
83YL-91868
Refresh After Write
1
ASlB
WR
/
tORFQST
tOWRFQ
I
-'
REFRQ
'I
I
I
~
tWRFQL
I
83YL-9187B
36
NEe
pPD78214 Family
Timing Waveforms (cont)
Serial Operation
Three-Line Serial va Timing
Input Data
Sl------{
....JX"-________ ~
so _ _
____~X~______~x~___
•
SBIMode
Bus Release Signal Transfer Timing
~ =1=~'----..J/
\
/
\'----
SBo---'L_.-========='X'-____--'>C
Command Signal Transfer Timing
seo
37
I
NEe
pPD78214 Family
Timing Waveforms (cont)
Interrupt Input
External Clock
Xl
NMI
1------tCYX----~
83ML-5995A
INTPO·
INTP5
Reset Input
RESET
Data Retention Characteristics
Set STOP Mode
t
VOO
tHVO
~
~tFVO
tRVO~
I",
~
0.8Voo
VOOOR
NMI
(Release by
0.8Voo
V OOOR
failing
edge Input)
NMI
(Release by
tWAIT
1\
O.8V
1\
0.8V
/
;0.1
V
0. 8V
oo
rising
edge Input)
0.8 V
83YL-92:2GB
38
NEe
JlPD78214 Family
Table 5. Pin Functions During PROM
Programming
"PD78P214 PROGRAMMING
In the JlPD78P214, the mask ROM of pPD78214 is replaced by a one-time programmable ROM (OTP ROM)
or a reprogrammable, ultraviolet erasable ROM (UV
EPROM). The ROM is 16,384 x 8 bits and can be
programmed using a general-purpose PROM writer
with apPD27C256A programming mode.
The PA-78P214CW/GC/GJ/GQ/L are the socket adaptors
used for configuring the pPD78P214 to fit a standard
PROM socket.
Refer to tables 5 and 6 and figures 15 through 18 for
special information applicable to PROM programming.
Pin
Pin·
Function
POo - P07
Ao-A7
Address input pins for PROM
operations
P50IAs
As
Address input pin for PROM
operations
P21/INTPO
Ag.
Address input pin for PROM
operations
P5:!/A 10 - P5efA14
A10 - A14 Address input pins for PROM
operations
P401ADo - P47/AD7 Do- D7
Data pins for PROM operations
P6sJWR
CE
P6~RD
OE
Strobes data into the PROM
Enables a data read from the PROM
P201NMI
NMI
PROM programming mode is
entered by applying +12.5 volts to
this pin
RESET
RESET
PROM programming mode requires
applying a low voltage to this pin
EA
Vpp
High voltage applied to this pin for
program write/verify
VDD
VDD
Positive power supply pin
VSS
VSS
Ground
• Pin name in PROM programming mode.
Table 6. Summary of Operation Modes for PROM Programming
Mode
Program write
NMI
RESET
CE
OE
Vpp
Voo
00- 07
+12.5V
L
L
H
+12.5V
+6V
Data input
Data output
Program verify
+12.5V
L
H
L
+12.5V
+6V
Program inhibit
+12.5V
L
H
H
+12.5V
+6V
High Z
Read out
+12.5V
L
L
L
+5V
+5V
Data output
Output disable
+12.5V
L
L
H
+5V
+5V
High Z
Standby
+12.5V
L
H
L/H
+5V
+5V
High Z
Note: When +12.5 V is applied to Vpp and +6 V to VDD • both CE and
OE cannot be set to low level (L) simultaneously.
39
..
NEe
pPD78214 Family
Pin Functions in I'PD7BP214 PROM Programming Mode
Figure 15. 64-Pin Plastic and Ceramic Shrink DIP
64-Pin Plastic QUIP
"PD78P214CW
"P078P2140W
"P078P214 GQ
A3
84
A4
A5
AS
4
A7
L{
CE
L
RESET
Open
G
Vss
L
VOO
Vpp
}L
} Open
}Notae:
(1) L: CoMEICI these pins separately to VSS through
resistors.
(2) G: Connect these pins to VSS'
(3) Open: 00 not connect these pins.
83YW19,...
40
NEe
pPD78214 Family
Pin Functions in I£PD78P214 PROM Programming Mode (cant)
Figure 16. 64-Pin Plastic QFP
w
....
.... '" "' ., .. tn.JP<~««
a:
NoIea:
(1) L: Comect these pins separately to Vss through
resistors.
(2) G: Connect these pine to VSS'
(3) Open: Do not connect these pins.
83YL-91938
42
NEe
JlPD78214 Family
Pin Functions in IlPD78P214 PROM Programming Mode (cont)
Figure 18. 74-Pin Plastic QFP
CE
}L
A7
Open
AS
A5
A4
A3
IlPD78P214GJ
NC
A2
A1
AO
•
} Open
39
m
~.~ ~ ~ ~ ~ ~
re
~
re
~ ~ ~ ~ ~ ~ ~ ~ ~
M
NC
Open
L
NOkI8:
(1) L: =:.th9Se pins separately \0 VSS through
(2) G: CoMect these pins \0 VSS'
(3) Open: Do not connect these pins.
83YL-811MB
43
NEe
pPD78214 Famll y
PROM Write Procedure
PROM Read Procedure
(1)
Set the pins not used for programming as indicated in figures 15 through 18. Connect the RESET pin to a low level, the Voo and Vpp pins to +5
V, and apply + 12.5 V to the NMI pin. The CE and
OE pins should be high.
(1)
Set the pins not used for programming as indicated in figures 15through 18. Fix the RESET pin to
a low level, the Voo and Vpp pins to +5 V, and
apply +12.5 Vtothe NMI pin. The CE and OE pins
should be high.
(2)
Apply +6VtotheVoo pin and +12.5VtotheVpp
pin.
(2)
Input the address of the data to be read to pins
Ao -A14'
(3)
Provide the initial address to the
(3)
(4)
Provide write data
Read mode is entered with a pulse (active low) on
both the CE and OE pins.
(5)
Provide 1-ms program pulse (active low) to the
CEpin.
(4)
Data is output to the Do to 07 pins.
Ao to A14 pins.
(6) This data is now verified with a pulse (active low)
to the OE pin. If the data has been written,
proceed to step 8; if not, repeat steps 4 to 6. If the
data cannot be correctly written after 25 attempts, go to step 7.
(7)
Classify as defective and stop write operation.
(8)
Provide write data and supply program pulse (for
additional writing) for 3 ms times the number of
writes performed in step 5.
(9) Increment the address.
(10)
44
Repeat steps 4 to 9 until the end address. NEC
reserves address 4000H for future functional extension. If a PROM writer cannot specify a final
programming address, FFH must be written in
address 4000H.
EPROM Erasure
Data in an EPROM is erased by exposing the quartz
window in the ceramic package to light having a wavelength shorter than 400 nm, including ultraviolet rays,
direct sunlight, and fluorescent light. To prevent unintentional erasure, mask the window.
Typically, data is erased by 254-nm ultraviolet rays. A
minimum lighting level of 15 Ws/cm2 (ultraviolet ray
intensity x exposure time) is required to completely
erase written data. Erasure by an ultraviolet lamp rated
at 12 mW/cm2 takes approximately 15 to 20 minutes.
Remove any filter on the lamp and place the device
within 2.5 cm of the lamp tubes.
NEe
I'PD78214 Family
DC Programming Characteristics
TA = 25 :l:5'C; VIP = 12.5 :1:0.5 V applied to NMI pin; Vss = 0 V
Parameter
Symbol
Symbol·
Min
Max
Unit
High-level input voltage
VIH
VIH
2.4
Voop+0.3
V
-0.3
0.8
V
10
JiA
Os VI S VOOP
IOH = -400JiA
Typ
Condition
Low-level input voltage
VIL
VIL
Input leakage current
ILiP
III
High-level output voltage
VOHl
VOHl
2.4
V
VOH2
VOH2
Voo-0.7
V
IOH = -100JiA
Low-level output voltage
VOL
VOL
0.45
V
IOL = 2.1 rnA
Output leakage current
ILO
10
JiA
NMI pin high-voltage input current
liP
:1:10
JiA
Voop power voltage
Voop
Vpp power voltage
Vpp
VCC
Vpp
5.75
6.0
6.25
V
Program memory write mode
4.5
5.0
5.5
V
Program memory read mode
12.2
12.5
12.8
V
Program memory write mode
Vpp = Voop
VODP power current
Vpp power current
IDD
Ipp
Os Vo s Voop, OE = VIH
Icc
Ipp
V
Program memory read mode
5
30
rnA
Program memory write mode
5
30
rnA
Program memory read mode
CE = VIL, VI = VIH
5
30
rnA
Program memory write mode
CE = VIL, OE = VIH
100
JiA
Program memory read mode
• Corresponding symbols of the JiPD27C256A.
AC Programming Characteristics (Write Mode)
TA = 25 :l:5'C; VIP = 12.5 :1:0.5 V applied to NMI pin; Vss = 0 V; VOD =6 :1:0.25 V; Vpp = 12.5 :1:0.3 V
Parameter
Symbol
Symbol·
Address setup time to CE I
tSAC
tAS
2
JiS
Min
Typ
Max
Unit
Data input to OE I delay time
tDDOO
toES
2
Jis
Input data setup time to CE I
tSIDC
tos
2
Jis
Address hold time from CE !
tHCA
tAH
2
Jis
Input data hold time from CE !
tHCID
tOH
2
Output data hold time from OE !
tHOOD
tOF
0
Vpp setup time to CE I
tsvPC
tvps
VODP setup time to CE I
tSVDC
tvcs
Initial program pulse width
Additional program pulse width
NMI high-voltage Input setup time to CE I
OE I to data output time
tWLl
twL2
tDOOD
Jis
130
ms
tpw
topw
2.85
1.0
1.05
ms
78.75
ms
2
tOE
ns
ms
0.95
tspc
Conditions
Jis
150
ns
• Corresponding symbols of the JiPD27C256A.
45
-
!
NEe
pPD78214 Family
AC Programming Characteristics (Read Mode)
= 25 :t5"C; VIP = 12.5 :to.5 V applied to NMI pin; Vss = 0 V;
TA
Parameter
Symbol
Address to data output time
Symbol*
VOO
= 5 :to.5 V; Vpp = VOOP
Typ
Min
Max
Unit
ns
CE
OE
tOAOO
200
CE ~ to data output time
tocoo
200
ns
OE ~ to data output time
10000
75
ns
60
ns
tOE
o
Data hold time from OE t
Data hold time from address
tHAOO
o
tOH
ns
* Corresponding symbols of the JlPD27C256A.
PROM Timing Diagrams
PROM Write/Verify Mode
~W~
AO-A14
Do.[)7
=>- r~
'sIDCVIP
NMI
VIL
Vpp
Vpp
Voo
Voop
Veo
VOO
VIH
I-
tSAC
Data
Input
-1
--1
VIL
~
rI ~r- -1 t.~
-I
Data
Output
. - ItiJlo
I
-tHOOO
--1
-
tHCA
Data
Input
I-tsvpc
I-tsvoc
I'----'
j~L
t ~tDOoo
\
1Iotee:
(1) VOO must be applied before applying Vpp. It should be removed after removfng Vpp.
(2) Vpp must not axceed +13V,lncludlng overshoot.
46
K
~tspc
tWL1
VIH
Additional W~te-1
--1
~
OE
:1-
Verffy
EffecUve Address
CE
VIL
x RepeUtlons
.. ,-
_tWL2_
HJ·Z
Condition
= OE = VIL
= VIL
CE = VIL
CE = VIL
CE = OE = VIL
NEe
pPD78214 Family
PROM Timing Diagrams (cent)
PROM Read Mode
EffecUve Address
HJ·Z
83ML-6997B {7f93}
47
pPD78214 Family
48
NEe·
NEe
NEe Electronics Inc.
pPD78218A Family
(pPD78217A/218A/P218A)
8·Bit, K·Series Microcontrollers
With AID Converter, Real·Time Output Ports
July 1993
Description
o Pin compatible with pPD78214 family
The pPD78217A, pPD78218A, and pPD78P218A are
members of the K-Series® of microcontrollers and are
designed for real-time embedded control applications.
The pPD78218A family is pin compatible with the
pPD78214 family and offers increased internal memory
with enhanced timer and macro service facilities.
These 8-bit, single-chip microcontrollers have a minimum instruction time of 333 ns at 12 MHz (500 ns for
the pPD78217A). They feature 8-bit hardware multiply
and divide instructions, four banks of main registers,
an advanced interrupt handling facility, a powerful set
of memory mapped on-Chip peripherals, and the ability
to address up to 1M bytes of external data memory. On
board memory includes 1024 bytes of RAM, 32K bytes
of mask ROM, or 32K bytes of UV EPROM or one-time
programmable (OTP) ROM.
o Powerful instruction set
- 8-bit unsigned multiply and divide
-16-bit arithmetic instructions
-1-bit and 8-bit logic instructions
The advanced interrupt handling facility provides two
levels of programmable hardware priority control and
two separate methods of servicing interrupt requests:
vectored and macro service. The macro service facility
reduces the overhead involved in servicing peripheral
interrupts by transferring data between the memorymapped speCial function registers (SFRs) and memory
without the use of time consuming interrupt service
routines. In addition, the macro service facility can be
initialized to automatically alter timer compare register values or to repeatedly output a prespecified pattern at a fixed or variable rate. By using macro service
to control the real-time output ports, the pPD78218A
family can easily and accurately drive two independent
stepper motors.
The combination of the macro service facility, four
banks of main registers, extended data memory address space, and powerful on-chip peripherals makes
these devices ideal for applications in office automation, communication, HVAC, and industrial control.
Features
o Complete single-chip microcontroller
-8-bitALU
- Program memory (ROM)
pPD78217A: ROMless
pPD78218A/P218A: 32K bytes
- Data memory (RAM): 1024 bytes
K-series is a registered trademark of NEe Electronics, Inc.
50599
o Minimum instruction time
- 333 ns at 12 MHz (pPD78218A/P218A)
- 500 ns at 12 MHz (pPD78217A)
o Memory expansion
- 8085 bus-compatible
- 64K program address space
- 1M data address space
o Large I/O capacity
- Up to 54 I/O port Ii nes on pPD78218A/P218A
- Up to 361/0 port lines on pPD78217A
-Software programmable pullup resistors
o Memory-mapped on-Chip peripherals (special
function registers)
o Timer/counter unit
-16-bit timer 0:
Two 16-bit compare registers
One 16-bit capture register
One external interrupt/capture line
- 8-bit timer 1:
One 8-bit compare register
One 8-bit capture/compare register
One external interrupt/capture line
- 8-bit timer/counter 2:
Two 8-bit compare registers
One 8-bit capture register
One external interrupt/capture line
One external event counter .line
- 8-bit timer 3:
One 8-bit compare register
o Four 8-bit precision timer-controlled pulse-width
modulated (PWM) output lines
o Two 4-bit (or one 8-bit) real-time output ports
o Eight-channel 8-bit A/D converter
o Programmable priority interrupt controller (two
levels)
o Two methods of interrupt service
- Vectored interrupts
- Macro service mode with choice of three
different types
NEe
pPD78218A Family
Features (cont)
Pin Configurations
o Two-channel serial communication interface
-Asynchronous serial interface (UAR"T)
Dedicated baud rate generator
- Clock-synchronized interface
Full-duplex, three-wire mode
NEC serial bus interface (S81) mode
64-Pin Shrink DIP (plastic or Ceramic)
o Refresh output for pseudostatic RAM
o STOP and HALT standby functions
P03
P02
P04
POl
P0 5
POo
POa
P37rro3
P0 7
P3arro2
P67fREFRQlAN7
P35rrol
P66fWAITfAN6
P34rroo
o 5-volt CMOS technology
P65fWR
P70fANO
P64fRD
P7l fANl
Ordering Information
P63fA19
P72fAN2
P62fAla
P73fAN3
ROM
Part Number
Package
Package Drawing
/lPD78217ACW
64-pin plast ic
shrink DIP
(P64C-70-750A, C) ROMless
JIPD78217AGC
64-pin plastic
QFP
(P64GC-80-AB8-2)
/lPD78218ACW-xxx 64-pin plastic
shrink DIP
(P64C-70 -750A, C) 32K mask
ROM
/lPD78218AGC-xxx 64-pin plastic
QFP
(P64GC-80-AB8-2)
/lPD78P218ACW
64-pin plastic
shrink DIP
(P64C-70-750A, C) 32KOTP
ROM
64-pin plastic
QFP
(P64GC-80-AB8-2)
64-pin shrink
cerdip wi
window
(P64DW-70-750A1) 32K UV
EPROM
/lPD78P218AGC
/lPD78P218ADW
Note: xxx indicates ROM code suffix
P6l fA17
P74fAN4
P60fA16
RESET
P75fAN5
AVREF
X2
AVSS
Xl
':'QD
EA
VSS
P5 7 fA 15
P33fSOfSBO
P56fA14
P5 5 fA 13
P3l rrxD
P54fA12
P30fRxD
P32fSCK
P53fAl1
P27fSI
P52fAl0
P26f1NTP5
P5lfA9
P25f1NTP4fASCK
P50fAa
P24f1NTP3
P47fAD7
P23 fINTP2fCI
P46fAD6
P22f1NTPl
P45fAD5
P2l f1NTPO
P44fAD4
P20fNMI
P43fAD3
ASTB
P42fAD2
P40fADo
VSS
P4lfADl
83YL-9221A
2
NEe
pPD78218A Family
Pin Configurations (cont)
64-Pin Plastic QFP
P641RO
P63 1A19
P621A18
P6l IA17
PSoIA16
RESET
X2
Xl
VSS
P57 1A15
P5S 'A14
P5s 1A13
P54'A12
PS3'All
P52'Al0
P51 'A9
P7l'ANl
P72'AN2
P731AN3
P74'AN4
P7s 'AN5
AVREF
AVSS
VOO
Eli
P331SOISBO
P321SCK
P3lfTxO
P30IRxO
P271S1
P2SflNTP5
P2sIINTP4IASCK
B3YL-91668
3
•
I
NEe
pPD78218A Family
Pin Functions; Normal Operating Mode
Symbol
First Function
poo - pcry.
Port 0; 8-bit tristate output port/real time output port
P20
Port 2; 8-bit input port
P2l
P22
Symbol
Second Function
NMI
External nonmaskable interrupt
INTPO
INTPl
Maskable external interrupts
INTP2
Maskable external interrupt
CI
External clock input to timer/counter 2
INTP3
Maskable external Interrupt
INTP4
Maskable external interrupt
ASCK
Asynchronous serial clock input
INTP5
Maskable external interrupt
SI
Serial data input for three-wire serial I/O mode
_P_3,,-O___ Port 3; 8-bit, bit-selectable tristate input/output port
RxD
Asynchronous serial receive data input
P3l
TxD
Asynchronous serial transmit data output
SCK
Serial shift clock input/output
SO
Serial data output for three-wire serial I/O mode
P34- P37
SBO
I/O bus for NEC serial bus interface (SBI)
TOO - T03
Timers TO to T3 outputs
P40 - P4r
Port 4; 8-bit tristate input/output port
ADO - AD7
Low-order 8-bit multiplexed address/data bus
P50- P5-r
Port 5; B-blt, bit-selectable tristate input/output port
As - A15
High-order .B-bit address bus
Peo- P63
Port 6; 4-bit output port
A16 - A19
Extended memory address bus
Pe4
Port 6; 4-blt, bit-selectable tristate input/output port
RD
External memory read strobe
P65
WR
External memory write strobe
P66
WAIT
External memory wait signal input
AN6
Analog voltage input to AID converter
REFRQ
Refresh pulse output used by external
pseudostatic memory
AN7
Analog voltage input to AID converter
ANO - AN5
Analog voltage inputs to AID converter
P70 - P75
Port 7; 6-bit input port
ASTB
Address strobe output used to latch the
low-order 8 address for external memory
RESET
External system reset input
EA
Internal ROM or external memory control signal input. Low-level
input selects external memory. High-level input selects internal
ROM. A low-level input on a j./PD782l8A or j./PD78P2l8A places
the device in ROM less mode and external memory is accessed.
Xl
CrystaVceramic resonator connection or external clock input
X2
CrystaVceramic resonator connection or Inverse of external
clock
A/D converter reference voltage
AVss
AID converter ground
VDD
+5 volt power supply input
Vss
Power supply ground
NC
No connection
4
NEe
IIPD78218A Family
Block Diagram
Bus Control
PeO/A1SP63/A19
SFR AddrasslData Bus
P20INMI
P50/ASPS7/A1S
P2l nNlPOP2enNTPS
P30IRxO
P40fAOOP47fA07
_.r-----,
P3l/TxD
P25n~~~-
I......,;;~.;.;;;;.;..-'
P321SCK __.w------,
P64fRD
P331SCYSBO
P271S1 ---L._ _ _--I
P6SIWR
INlP3
PeSIWAITf
ANS
-~-----,
P34fTOO
P67IREFROf
AN7
P35fTOl ~,------I
ASTB
~
llmerl
h
INlPO
1r..._--,~
INlPl
_.w------,
Temporary
Registers
System Control
It=Xl
P2a nNTP2fCI
P3SfT02
P37fT03 _4_-t..._ _ _--I
~:&
- - VOO
- - Vss
Peripheral RAM
Data Bus
788Bytas
Pe~pharal
Bus VF
D
PSo
-P57
PSO Pe4
-Pe3 -Pe7
P70
-P75
83YL-9200B
5
NEe
pPD78218A Family
"PD78218A and "PD78214 Differences
FUNCTIONAL DESCRIPTION
The JlPD78218A family is a pin compatible enhanced
version of the JlPD78214 family. Some of the enhancements include a larger internal program ROM and data
RAM memory space, an improved 16-bit timer 0, and an
enhanced macro service facility. Table 1 highlights the
differences between the JlPD78218A and JlPD78214 families.
Central Processing Unit (CPU)
Table 1. Differences Between the pPD7821BA and
pPD78214 Families
Item
,.PD7B21BA Family
,.PD7B214 Family
Maximum on-Chip
ROM
32K bytes
16K bytes
Maximum on-chlp
RAM
1024 bytes
512 bytes
16-bit timer
Software-triggered
one-shot pulse
output
Not available
Macro service
counter
8/16-bit selectable
(except Type A
transfers)
8·bit only
Type C macro
service pointer, MPT
and MPD
Increments full 16
bits
Increments only
lower 8 bits
Macro service
execution times
Execution times
differ; refer to
hardware user's
manual
Execution times
differ; refer to
hardware user's
manual
PUSH PSW
Instruction
Execution times
differ; refer to
software user's
manual
Execution times
differ; refer to
software user's
manual
Oscillation
stabilization time
when exiting STOP
mode
Time equivalent to
NMI active pulse
width 'plus 16 bits of
dedicated counter or
15 bits of dedicated
counter
Time equivalent to
NMI active pulse
width plus 16 bits of
dedicated counter
NO converter
3.6 V to Voo
3.4V toVoo
Programmable
device operating
voltage
5V ±0.3V
5V ±10%
Package
64-pln plastic shrink
DIP
64-pln plastic shrink
DIP
reference voltage
64-pln plastic QFP
64-pln plastic QFP
64-pin shrink cerdip
w/Wlndow
64-pin shrink cerdip
w/window
64-pin plastic QUIP
68-pln PLCC
74-pin plastic QFP
6
The JlPD78218A family CPU features 8- and 16-bit arithmetic including an 8 x 8-bit unsigned multiply and 16 x
8-bit unsigned divide (producing a 16-bit quotient and
an 8-bit remainder). The multiply executes in 3.67 /ls
and the divide in 12.36/ls at 12 MHz (4.00 and 12.69/ls
respectively for /lPD78217A).
A CALLT vector table and a CALLF program area
decrease the number of bytes in the call instructions
for commonly used subroutines. A 1-byte call instruction (CALLT) can access up to 32 subroutines through
the addresses contained in the CALLT vector table. A
2-byte call instruction (CALLF) can access any routine
beginning at a specific address in the CALLF area
The internal system clock (fcUQ is generated by dividing the oscillator frequency by two. Therefore, at the
maximum oscillator frequency of 12 MHz, the internal
system clock is 6 MHz. The minimum instruction execution time for an instruction fetched from internal
ROM is 333 ns (500 ns when fetched from external
memory).
Memory Space
The /lPD78218A family has a 1M byte address space
(see figure 1). The first 64K bytes of this address space
(OOOOOH-OFFFFH) can be used as both program and
data memory. The remaining 960K bytes of this address
space (10000H-FFFFFH) can only be used as data
memory and is known as expanded memory.
External Memory
The /lPD78218A family has an 8-bit wide external data
bus and a 16-bit wide external address bus (20-bit wide
if expanded memory is enabled). The low-order a bits
of the address bus are multiplexed to provide the a-bit
data bus and are supplied by I/O port 4. The high-order
address bits of the 16-bit address bus are taken from
port 5. If expanded memory is enabled, the expanded
address nibble is provided by P60 to P63. Address latch,
read, and write strobes are also provided.
The memory expansion mode register (MM) is used to
enable external memory, to specify up to two additional wait states or the use of the WAIT input pin for the
first 64K bytes of memory, and to enable the high-speed
internal ROM fetch. Ports 4, 5, and 6 are available as
general purpose I/O ports when only internal ROM is
used and no external program or data space is required.
NEe
pPD78218A Family
Figure 1. Memory Map
OOOOOH
OOOOOH
r
On-Chlp
Program Memory
32,768 Bytes
Extema! Memory
CALLT Table Area
0007FH
00080H
(Must be extema!
memory
In !,PD78217A)
07FFFH
O8OOOH
Interrupt VeClar
Address Table Area
0003FH
00040H
Program Area
007FFH
OOSOOH
~~
CALLFEntry
Area
OOFFFHI
01000H
Program Araa
07FFFHI
OFAFFH
OFBOOH
OFBOOH
+
Peripheral
On-ChIp RAM
saddr Addressing
VOFE20H
RAM
and
Register Area
General RAM
OFDFFH{ - - - - - - - General Storage
OFEC1 H
- - - - - - - 4----"'-'="'.!!..!.i1- - - - - - RegIsters
OFEC2H
Macro Service
OFFFFH
10000H
Intema! RAM
Extema!
Memory
(Expanded
1
Address
Area)
OFFOOH
J
Special Funcllon
Register Area
-
OFEDFH __C~~ '!'!.o!!!.s__
I- - - - - - - -
~
OFEEOH
OFEFFH
General Reglslers
OFFOOH - - - - - - - -
OFFFFH
OFF1FH 32BytesofSFRArea
......
FFFFFH
~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~~~~O~1. ~
Expanded Data Memory
The MM register is also used to enable the external
expanded data memory space, addresses 10000H to
FFFFFH. When the expanded data memory is enabled,
the entire 1M byte address space is divided into 16
banks of 64K bytes each. The low-order 4-bits of the P6
or the PM6 registers are used as bank selection registers to supply the address information to A16 to A19.
Data can easily be transferred from one memory bank
to another by using the appropriate instructions. Address lines A16 to A19 are only active when an instruction that uses expanded addressi ng is bei ng executed.
A programmable wait control register (PW) allows the
programmer to specify up to two additional wait states
or the use of the WAIT input pin for expanded data
memory space.
On-Chip RAM
The IlPD78218A family has a total of 1024 bytes of.
on-chip RAM. The upper 256-byte area (FEOOH-FEFFH)
features high-speed access and is known as "Internal
RAM." The remaining 768 bytes (FBooH-FDFFH ) are
accessed at the same speed as external memory and
are known as "Peripheral RAM." The general register
banks and the macro service control words are stored
in Internal RAM. The remainder of Internal RAM and any
unused register bank locations are available for general storage.
On-Chip Program Memory
The IlPD78218A contains 32K bytes of internal ROM
respectively. The IlPD78P218A contai ns 32K bytes of UV
EPROM or one-time programmable ROM. Instructions
from on-Chip program memory can be fetched at high
speed or at the same rate as from external memory.
The IlPD78217A does not have on-chip program memory.
CPU Control Registers
Program Counter. The program counter is a 16-bit
binary counter register that holds the address of the
next instruction to be executed. During reset, the
program counter is loaded with the address stored in
locations ooooH and 00001 H.
Stack Pointer. The stack pointer is a 16-bit register
that holds the address of the last item pushed onto the
7
NEe
pPD78218AFamily
Addressing
stack. It is decremented before new data is pushed
onto the stack and incremented after data is popped
off the stack.
The JlPD7821BA family features 1-byte addressing of
both the special function registers and the portion of
on-chip RAM from FE20H to FEFFH. The 1-byte sfr
addressing accesses .the entire SFR area, while the
1-byte saddr addressing accesses the first 32 bytes of
the SFR area and 224 bytes of Internal RAM. The 16-bit
SFRs and words of memory in these areas can be
addressed by 1-byte saddrp addressing, which is valid
for even addresses only. Since many instructions use
1-byte addressing, access to these locations is almost
as fast and versatile as access to the general registers.
There are seven addressing modes for data in main
memory: direct, register, register indirect with autoincrement and decrement, saddr, SFR, based, and indexed. There are also both 8-bit and 16-bit immediate
operands.
Program Status Word. The program status word
(PSW) is an 8-bit register that contains flags that are
set or reset depending on the results of an'instruction.
This register can be written to or read from 8 bits at a
time. The individual flags can also be manipulated on a
bit-by-bit basis. The assignment of PSW bits follows.
7
IE
0
Z
CY
ISP
RBSO,RBS1
AC
Z
IE
I RBSt I
AC
IRBSO I
0
liSP I
CY
Carry flag
Interrupt priority status flag
Register bank selection flags
Auxiliary carry flag
Zero flag
Interrupt request enable flag
Special Function Registers
The input/output ports, timers, capture and compare
registers, and mode and control registers for both the
peripherals and the CPU are collectively known as
special function registers. They are all memorymapped between FFOOH and FFFFH and can be accessed either by main memory addressing or by 1-byte
sfr addressing. They are either 8 or 16 bits as required,
and many ofthe B-bit registers are capable of single-bit
access as well. Locations FFDOH through FFDFH are
known as the external SFR area. Registers in external
circuitry interfaced and mapped to these addresses
can be addressed with sfr addressing. Table 2 is a list of
the special function registers.
General Registers
The general-purpose registers (figure 2) consist of four
banks of registers located at addresses FEEOH to
FEFFH in Internal RAM. Each bank consists of eight
8-bit general registers that can also be used in pairs to
function as four 16-bit registers. Two bits in the PSW
(RBSO and RBS1) specify which of the register banks is
active. The bits are set under program control. Registers have both functional names (like A, X, B, C for S-bit
registers and AX, BC for 16-bit registers) and absolute
names (like R1, RO, R3, R2 for 8-bit registers and RPO,
RP1 for 16-bit registers). Each instruction determines
whether a register is referred to by its functional or
absolute name and whether it is 80r 16 bits. '
Figure 2. General Registers
OFEEOH
ForS-Blt
Piocesslng
OFEFFH
\
(R1)A
(RO) X OFEF8H-
(R3)B
(R2)C
(R5)O
(R4)E
(R7)H
(R6)l
. (
O£EF~H _
_ _ _ _ _ L...:.......:..-.I
)= Absolute Name
83YL·9170B
8
NEe
pPD78218A Family
Table 2. Special Function Registers
Access Units (Bits)
State After Reset
Address
Register (SFR)
Symbol
R/W
OFFOOH
Port 0
PO
R/W
x
x
Undefined
OFF02H
Port 2
P2
R
x
x
Undefined
OF F03H
Port 3
P3
R/W
x
x
Undefined
OFF04H
Port 4
P4
R/W
x
x
Undefined
OFF05H
Port 5
P5
R/W
x
x
Undefined
OFF06H
Port 6
P6
R/VV
x
x
xOH
OFF07H
Port 7
P7
R
x
x
Undefined
OFFOAH
Port 0 buffer register (low)
POL
R/W
x
x
Undefined
OFFOBH
Port 0 buffer register (high)
POH
Rm
x
x
Undefined
OFFOCH
Rea~time
RTPC
R/VV
x
x
OFF10H-OFFllH
16-bit compare register 0 (16-bittimer 0)
CROO
R/VV
OFF12H-OFF13H
16-bit compare register (16-bit timer 0)
CROl
R/W
OFF14H
S-bit compare register (S-bittimer 1)
CR10
Rm
x
Undefined
OFF15H
S-bit compare register (S-bit timer/counter 2)
CR20
R/VV
x
Undefined
OFF16H
S-bit compare register (S-bit timer/counter 2)
CR21
R/W
x
Undefined
OFF17H
S-bit compare register (S-bit timer 3)
CR30
Rm
x
OFF1SH-OFF19H
16-bit capture register (16-bit timer 0)
CR02
R
output port control register
8
16
OOH
x
x
Undefined
Undefined
Undefined
x
Undefined
OFF1AH
S-bit capture register (S-bit timer/counter 2)
CR22
R
x
Undefined
---'------"---'------'---------OFFl CH
S-bit capture/compare register (S-bit timer 1)
CRll
R/VV
x
Undefined
OFF20H
Port 0 mode register
PMO
W
x
FFH
OFF23H
Port 3 mode register
PM3
W
x
FFH
OFF25H
Port 5 mode register
PM5
W
x
FFH
OFF26H
Port 6 mode register
PM6
R/VV
x
FxH
OFF30H
Capture/compare control register 0
CRCO
W
x
10H
OFF31 H
Timer output control register
TOC
W
x
OOH
OFF32H
Capture/compare control register 1
CRCl
W
x
OOH
OFF34H
Capture/compare control register 2
CRC2
W
x
OOH
OFF40H
Pullup resistor option register
PUO
R/W
x
x
OOH
OFF43H
Port 3 mode control register
PMC3
R/W
x
x
OFF50H-OFF51 H
16-bit timer register 0
TMO
R
OFF52H
S-bit timer register 1
TMl
R
x
OOH
OFF54H
S-blt timer register 2
TM2
R
x
OOH
OFF56H
S-bit timer register 3
TM3
R
x
OOH
OFF5CH
Prescaler mode register 0
PRMO
W
x
OOH
OFF5DH
Timer control register 0
TMCO
R/W
x
OOH
OFF5EH
Prescaler mode register 1
PRMl
W
x
OOH
OFF5FH
Timer control register 1
TMCl
R/VV
x
OOH
OFF6SH
AID converter mode register
ADM
R/W
OFF6AH
AID conversion result register
ADCR
R
OFF7DH
One-shot pulse output control register
OSPC
R/W
x
x
OOOOH
x
OOH
x
Undefined
x·x
~.
I
OOH
x
III
OOH
9
NEe
pPD78218A Family
Teble2. Speciel Function Registers (conI)
Access Units (Bits)
Address
Register (SFR)
Symbol
R/W
OFF80H
Clocked serial interface mode register
CSIM
R/W
x
x
OFF82H
Serial bus interface control register
SBIC
R/W
x
x
OOH
OFF86H
Serial shift register
SIO
R/W
x
Undefined
8
16
State After Reset
OOH
OFF86H
Asynchronous serial interface mode register
ASIM
R/W
x
x
SOH
OFFBAH
Asynchronous serial interface status
register
ASIS
R
x
x
OOH
OFF8CH
Serial receive buffer: UART
RxB
R
x
Undefined
OFF8EH
Serial transmit shift register: UART
TxS
W
x
Undefined
OFF90H
Baud rate generator control register
BRGC
W
x
OOH
OFFCOH
Standby control register
STBC
R/W
x
OOOOxOOOB
OFFC4H
Memory expansion mode register
MM
R/W
x
x
20H
OFFC5H
Programmable wait control register
PW
R/W
x
x
SOH
OFFC6H
Refresh mode register
RFM
R/W
x
x
OOH
OFFDOH-OFFDFH
External SFR area
R/W
x
x
Undefined
OFFEOH
Interrupt request flag register L
IFOL
R/W
x
x
OOH
OFFE1H
Interrupt request flag register H
IFOH
R/W
x
x
OFFEOH-OFFE1 H
Interrupt request flag register
IFO
R/W
OFFE4H
Interrupt mask flag register L
MKOL
R/W
x
x
OFFE5H
Interrupt mask flag register H
MKOH
R/W
x
x
OFFE4H-OFFE5H
Interrupt mask flag register
MKO
R/W
OFFE8H
Priority specification flag register L
PROL
R/W
x
x
FFH
OFFE9H
Priority specification flag register H
PROH
R/W
x
x
FFH
OOH
x
OOOH
FFH
FFH
x
x
FFFH
OFFE8H-OFFE9H
Priority specification flag register
PRO
R/W
OFFECH
Interrupt service mode specification flag
register L
ISMOL
R/W
x
x
OOH
OFFEDH
Interrupt service mode specification flag
register H
ISMOH
R/W
x
x
OOH
OFFECH-OFFEDH
Interrupt service mode specification flag
register
ISMO
R/W
OFFF4H
External interrupt mode register 0
INTMO
R/W
x
x
OOH
OFFF5H
External interrupt mode register 1
INTM1
R/W
x
x
OOH
OFFF8H
Interrupt status register
1ST
R/W
x
x
OOH
10
x
FFFH
OOOH
NEe
IIPD78218A Family
Figure 3. Pin I/O Circuits
Type' (EA)
I-----<....A~--- pullup
""""-I
enable
Type 2
IN
o-----L'TJ>o-----...,.
Schmitt trigger Input with hysteresis characteristic.
IN
0>-----1[90...---->>Yoo
Schmltlt~gger Input with
hysteresis characieMUc.
TJpe4(PO, P60· P63,ASTB)
pullup enable
-------!>~--_I
Yoo
dam~
outPutdlsable~
Push·pun oulpul whare the output can be placed In
(both P and N channels are tumed off).
+--+-----<>
IN/OUT
hlgh~mpedance
Input enable - - - - - - - - '
I-TJpe~_._A_~~32~)_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~---------------------~
Type 9 (P7)
Yoo
IN
pullup --------1r--....>c>-----H...
enable
V
Yoo
0--"",-""",
YREF (Threshold Yolmge)
+--+----0
' -_ _ _ _ _ _ _ _ Input
enable
IN/OUT
Yoo
pullupenable
Yoo
pullup enable
-------1!>~---I
dam~
-------!>~--_I
OUtputdlsable~
Yoo
.....-.---<0--0
IN/OUT
...L
+--+----0
IN/OUT
YREF (Threshold Volmge)
Input enable _ _ _ _ _=C-J
83YL-91718
11
. .
~.
NEe
pPD78218A Family
Input/Output Ports
There are up to 54 port lines on the JlPD78218A(P218A
and up to 36 port lines on the JlPD78217A. (Ports 4,5,
and two bits of port 6 are not available on the
JlPD78217A since the JlPD78217A must always use
external memory.) Table 3 lists the features of each
port and figure 3 shows the structure of each port pin.
The pin levels of all port 2,3, and 7 pins can always be
read or tested regardless of the dual pin function.
real-time output mode, data stored beforehand in the
buffer registers, POH and POL, is transferred immediately to the output latch of PO on the occurrence of a
timer 1 interrupt (lNTC1O or INTC11) or external interrupt (lNTPO) (see figure 4). By using the real-time
output port with the macro service function, port 0 can
be used to output preprogrammed patterns at preprogrammed variable time intervals. In this mode, two
independent stepper motors can accurately be driven
at a fixed or variable rate.
Real-time Output Port
The real-time output port (RTPC) shares pins with port
O. It can be used as two independent 4-bit real-time
output ports or one 8-bit real-time output port. In the
Table 3. Digital Port Functions
Port
Port
Operational Features
a
Configuration
S-bit high impedance output
Direct Drive
Capability
Software Pull up
Resistor Connection
Transistor
Port 2
S-bit Schmitt trigger input
Port 3
S-bit input or output
Bit selectable
In 6-bit units (P22 - P27)
Port 4
S-bit input or output
Byte selectable
LED
Byte selectable
Port 5
S-bit input or output
Byte selectable
LED
Byte selectable, input bits only
Port 6
4-bit output (bits a to 3)
4-bit input or output (bits 4 to 7)
Bit selectable
Port 7
6-bit input
Note: Software pullup resistors can be internally connected only on
a port-by-port basis to port bits set to input mode. Pullup
resistors are not connected to port bits set to output mode.
12
Byte selectable, input bits only
In 4-bit unit, input bits only
NEe
pPD78218A Family
Figure 4. Real-Time Output Port
83YL·9172B
13
•
I
i
NEe
pPD78218A Family
Analog-to-Digital (AID) Converter
The IlPD78218A family AID converter (see figure 5) uses
the successive-approximation method for converting
up to eight multiplexed analog inputs into 8-bit digital
data The conversion time per input is 30 Ils at 12 MHz
operation. AID conversion can be started by an external interrupt, INTP5, or under software control.
The AID converter can operate in either scan mode or
select mode. In scan mode, from one to eight sequential inputs can I:>e programmed for conversion. The AID
converter selects each input in order, converts the
data, stores it in the AID conversion result (ADCR)
register, and generates an interrupt (INTAD). This converted data can be easily transferred to memory by
using the macro service function.
In select mode, only one ofthe eight A/D inputs can be
selected for conversion. The ADCR register is continually updated and can be read at any time. If the AID
converter is started by an external interrupt, an INTAD
interrupt occurs at the completion of each conversion.
If the AID converter is started by software, no interrupts are generated.
Figure 5. AID Converter
Register String
r--I-----~
:1
AND
AN1
AN2
AN3
AN4
AN5
ANa
AI2
rT
l AVREF
1
Sample and
1
Hold Clrcuft
1
,----
:
1
Tap 1
Selector 1
1
1
1
1
I:
I------i---o
1 T:
rh
1
1
1 _ _ _ _ --'
Am
------~I
INTAD
Trigger Enable
1
1
1
1
1
1
1
1
1
1
1
A12LLI
:
1
:
L.. __ J _____ .J
~~_s.:.e. :.le.:.cto:. r.Jr
___
i
1
1
R
AVSS
Interrupt Request
8
Intemai Bus
83YL-91738
14
NEe
f,lPD78218A Family
Serial Interface
The pPD78218A family has two independent serial interfaces. The first is a standard UART. The UART (figure
6) permits full-duplex operation and can be programmed for 7- or 8-bits of data after the start bit,
followed by one or two stop bits. Odd, even, zero or no
parity can also be selected. The serial clock for the
UART can be provided by an on-chip baud rate generator or timer 3. By using either the internal system
clock or an external clock input into the ASCK pin, the
baud rate generator is capable of generating all of the
commonly used baud rates. The UART generates three
interrupts: INTST (transmission complete), INTSR (reception complete), and INTSER (reception error).
The second interface is an 8-bit clock-synchronized
serial interface (figure 7). It can be operated in either a
three-wire serial I/O mode or NEC serial bus interface
(SBI) mode.
In the three-wire serial I/O mode, the 8-bit shift register
(SIO) is loaded with a byte of data and eight clock
pulses are generated. These eight pulses shift the byte
of data out of the SO line (MSB first) and in from the SI
line providing full-duplex operation. This interface can
also be set to receive or to transmit data only. The
INTCSI interrupt is generated after each 8-bit transfer.
One of three internal clocks or an external clock clocks
the data.
Figure 6. Asynchronous Serial Interface
IntemalSus
L -_ _ _ _ _ _ _ _~~--------~----~
,-
Baud Aate Generator
- - - - -
1
SAGC
II
INTP4IASCK
8-B~Tim.r3
83YL-9174B
15
NEe
pPD78218A Family
Figure 7. Clock-Synchronized Serial Interface
Selector
N-ch Open-Dr-lin
Outpul Possible
Busyl
Acknowledge
Output CIrcuit
Bus Release!
Comrnandl
Acknowledge
Detection
Clrcutt
8-BII TImer 3
83't'L-9176B
16
NEe
IIPD78218A Family
Figure B. SBI Mode Master/Slave Configuration
MaslerCPU
Slave CPU
sao
SBO
SCK
SCK
Address 1
Slave CPU
(]
Address 2
~ISCK
~
~
tfcl--'
83YL-9178A
The NEC SBI mode is a two-wire high-speed propri etary
serial interface available on most devices in the NEC
pPD75xxx and pPD78xxx product lines. Devices are
connected in a master/slave configuration (see figure
8). There is only one master device at a time; all others
Figure 9.
are slaves. The master sends addresses, commands,
and data over the serial bus line (SBO) usin~ fixed
hardware protocol synchronized with the SCK line.
Each slave pPD78218A family device can be programmed in software to respond to anyone of 256
addresses. There are also 256 commands and 256 data
types. Since all commands are user definable, any
software protocol, simple or complex, can be defined.
It is even possible to develop commands to change a
slave into a master and the previous master into a
slave.
Timers
The pPD78218A family has one 16-bit timer and three
8-bittimers. The 16-bit timer counts the internal system
clock (felK/8) while the three 8-bit timers can be programmed to count a number of prescaled values of the
internal system clock. One of the 8-bit timers can also
count external events.
Timer 0 consists of a 16-bit timer (TMO), two 16-bit
compare registers (CROO and CR01), and a 16-bit capture register (CR02). Timer 0 can be used as two
interval timers, to output a programmable square wave
or two pulse-width modulated Signals, to measure pulse . .
widths, or to generate a software-triggered one-shot
~.
output pulse (see figure 9).
.
tB-Bit Timer 0
Pulse
OUtput
Control
P3SfTOl
L -_ _ _ _ _
L--_ _ _ _ _ _+
INTCOO
INTCOl
83YL-9177B
17
NEe
pPD78218A Family
Timer 1 consists of an 8-bit timer (TM1), 8-bit compare
register (CR10), and 8-bit capture/compare register
(CR11). Timer 1 can be used as two interval timers orto
measure pulse widths. In addition, it can be used to
generate the outputtriggerforthe real-time output port
(see figure 10).
Timer/counter 2 consists of an 8-bit timer (TM2) , two
8-bit compare registers (CR20 and CR21), and an 8-bit
capture register (CR22). Timer/counter 2 can also be
used as two interval timers, to output a programmable
square wave or two pulse-width modulated signals, or
to measure pulse widths. In addition, it can be used to
count external events sensed on the CI line or as a
one-shot timer (see figure 11).
Timer 3 consists of an 8-bit timer (TM3) and an 8-bit
compare register (CR30). Timer 3 can be used as an
interval timer or as a clock for the clock-synchronized
serial interface (see figure 12).
Figure 10. B-Bit Timer 1
'CLK1512
'CLKI256
'CLK/l28
'CLK/84
IOve~ow I
Rag
'CLK/32
'CLKI18
I--.......:==='---------II>---~
INTC10
} To Real-TIme
Output Port
I--===:......~>---~
INTCll
S3YL-917SB
Figure 11. B-Bit Timer/Counter 2
'CLK I512-....
'CLK12SS-'CLK/128 - - MPX
P23/INTP2ICI
~
Pulse
Output
Control
L.._ _ _ _ _~
L.._ _ _ _ _ _
~
INTC20
INTC21
83YL-9179B
18
NEe
JlPD78218A Family
Figure 12. 8-Bit Timer 3
fCLKi32
UART
fCLK/le
Clock-Bynchronized Serial Interface
fCLK/8
P25I1NTP4IASCK
INTP4/lNTC30
~
83YLo.9180B
Interrupts
The JlPD78218A family has 18 maskable hardware interrupt sources; 6 are external and 12 are internal. Since
there are only 16 interrupt vectors and sets of control
flags, 2 of the 6 external maskable interrupts, INTP4
and INTP5, share interrupt vectors and control flags
with INTC30 and INTAD respectively. The active interrupt source for each shared vector must be chosen by
the program. In addition, there is one nonmaskable
interrupt and one software interrupt. The software
interrupt, generated by the BRK instruction, is not
maskable (see table 4).
Tllble4. Interrupt Sources lind Vector Addresses
Interrupt
Request
Type
Default
Priority
Software
None
Nonmaskable
None
Maskable
0
Interrupt Request Generation Source
Macro Service
Type
BRK instruction execution
Vector
Table
Address
003EH
0OO2H
NMI (pin input edge detection)
INTPO (pin Input edge detection)
A.B
0006H
INTPI (pin input edge detection)
A,B
OOOBH
2
INTP2 (pin input edge detection)
A, B
OOOAH
3
INTP3 (pin input edge detection)
B
OOOCH
4
INTCOO (TMO-CRCO coincidence signal generation)
B
0014H
5
INTCOI (TMO-CROI coincidence signal generation)
B
0016H
6
INTC10 (TM1-CR10 coincidence signal generation)
A,B,C
001BH
7
INTCII (TM1-CRII coincidence signal generation)
A,B,C
001AH
8
INTC21 (TM2;'cR21 coincidence signal generation)
A, B
00lCH
9
INTP4 (pin input edge detection)
B
OOOEH
INTC30 (TM3-CR30 coincidence signal generation)
10
INTP5 (pin Input edge detection)
A,B
B
0010H
INTAD (end of AID conversion)
A, B
A,B
0012H
11
INTC20 (TM2-CR20 colncidence signal generation)
12
INTSER (generation of asynchronous serial Interface receive error)
13
INTSR (end of asynchronous serial Interface reception)
A,B
0022H
14
INTST (end of asynchronous serial interface transmission)
A, B
0024H
15
INTCSI (end of clocked serial interface transmission)
A,B
0026H
0020H
19
~
NEe
pPD78218A Family
Interrupt Servicing.
The J.lP078218A family provides two levels of programmable hardware priority
control and two different methods of handling maskable interrupt requests: standard vectoring and macro
service. The programmer can choose the priority and
mode of servicing each maskable interrupt by using
the interrupt control registers.
Interrupt Control Registers.
The J.lP078218A family
has four 16-bit interrupt control registers. Each bit in
each register is dedicated to one of the 16 active
maskable interrupt sources. The interrupt request flag
register (IFO) contains an interrupt request flag for each
interrupt. The interrupt mask register (MKO) is used to
enable or disable any interrupt. The interrupt service
mode register (ISMO) specifies whether an interrupt is
processed by vectoring or macro service. The priority
flag register (PRO) can be used to specify a high or a low
priority level for each interrupt.
Two other 8-bit registers are associated with interrupt
processing. The interrupt status register (1ST) indicates if a nonmaskable interrupt request on the NMI pin
is being processed and can be used to allow nesting of
nonmaskable interrupt requests. The IE and the ISP bits
of the program status word are also used to control
interrupts. If the IE bit is zero, all maskable interrupts,
but not macro service, are disabled. The IE bit can be
set or cleared using the EI and 01 instructions, respectively, or by directly writing to the PSW The IE bit is
cleared each time an interrupt is accepted. The ISP bit
is used by hardware to hold the priority level flag of the
interrupt being serviced.
Interrupt Priority. The nonmaskable interrupt (NMI)
has priority over all other interrupts. Two hardware
controlled priority levels are available for the maskable
interrupts. Either a high or a low priority level can be
assigned by software to each of the maskable interrupts. Interrupt requests of a priority higher than the
processor's current priority level are accepted; requests of the same or lower priority are held pending
until the processor's priority state is lowered by program control within the current service routine or by a
return instruction from the current service routine.
Interrupt requests programmed to be handled by
macro service have priority over all vectored interrupt
service regardless of the assigned priority level, and
macro service requests are accepted even when the
interrupt enable bit in the PSW is set to the disable state
(see figure 13).
The default priorities listed in table 4 are fixed by
hardware and are effective only when it is necessary to
choose between two interrupt requests of the same
20
software assigned priority. For example, the default
priorities would be used after the completion of a high
priority routine, if two interrupts of the same priority
routine were pending.
The software interrupt, initiated by the BRK instruction, is executed regardless of the processor's priority
level and the state of the IE bit. It does not alter the
processor's priority level.
Figure 13. Interrupt Service Sequence
Interrupt Request
L
xxMK
=1 Onterrupt Masked) Interrupt PendIng.
=
xxMK 0 (Unmasked)
I
SM = 1 Macro Service.
t:SM
=0 Vectored Interrupt Service.
b·
v
---
EI Vectored Interrupt
83Yt-9181A
Vectored Interrupt.
When vectored interrupt is
specified for a given interrupt request, (1) the program
status word and the program counter are saved on the
stack, (2) the processor's priority is set to that specified for the interrupt, (3) the IE bit in the PSW is set to
zero, and (4) the routine whose address is in the
interrupt vector table is entered. At the completion of
the service routine, the RETI instruction (RETB instruction for the software interrupt) reverses the process
and the J.lP078218A family device resumes the interrupted routine.
Macro Service
When macro service is specified for a given interrupt,
the macro service hardware temporarily stops the
executing program and begins to transfer data between the special function register area and the memory space. One byte is transferred each interrupt. When
the data transfer is complete, control is returned to the
executing program, providing a completely transparent method of interrupt service. Macro service significantly improves response time and makes it unnecessary to save any registers.
For each request on the interrupt line, one operation is
performed, and an 8- or 16-bit counter is decremented.
When the counter reaches zero, a vectored interrupt
service routine is entered according to the specified
priority.
NEe
pPD78218A Family
Macro service is provided for all of the maskable interrupt requests except INTSER, the asynchronous serial
interface receive error interrupt request. Each interrupt
request has a dedicated macro service control word
stored in Internal RAM (see figure 14). The function to
be performed is specified in the control word.
Interrupt Request
Source/Destination SFR
INTC10: TM1-CR10 coincidence
CR10: Timer 1 8-bit compare
register
INTCll: TM1-CRll coincidence
CRll: Timer 1 8-bit capture/
compare register
INTC20: TM2-CR20 coincidence
CR20: Timer 2 8-bit compare
register
INTC21: TM2-CR21 coincidence
CR21: Timer 2 8-bit compare
register
INTC30: TM3-CR30 coincidence
CR30: Timer 3 8-bit compare
register
INTCSI
INTSR: End of asynchronous serial
interface reception
RxB: Serial receive buffer
INTC10
INTST: End of asynchronous serial
interface transmission
TxS: Serial transmit shift
register
INTCll
INTCSI: End of clocked serial
interface transmission
SID: Serial shift register
Figure 14. Macro Service Control Word Map
OFEDFH
Channel PoInter
OFEDEH
Mode RegIster
OFEDDH
Channel PoInter
OFEDCH
Mode Register
OFEDBH
Channel PoInter
OFEDAH
Mode Register
OFED9H
Channel PoInter
OFED8H
Mode Register
OFED7H
Chamel PoInter
OFEDSH
Mode Register
OFED5H
Channel PoInter
OFED4H
Mode RegIster
OFED3H
Chamsi Pointer
OFED2H
Mode RegIster
OFED1H
Channel PoInter
OFEDOH
OFECFH
Mode RegIster
Channel PoInter
OFECEH
Mode Register
OFECDH
Channel PoInter
OFECCH
Mode Register
OFECBH
Channel PoInter
OFECAH
Mode Register
OFEC9H
Channel PoInter
OFEC8H
Mode Register
OFEC7H
Channel PoInter
OFECSH
Mode Register
OFEC5H
Channel PoInter
OFEC4H
Mode RegIster
OFEC3H
Channel PoInter
OFEC2H
Mode Register
Table 5. Macro Service Type A Interrupts and
Assigned SFRs
INTSR
INTST
INTAD: End of
INTP4IINTC30
ND
conversion
INTPO: External interrupt pin POl
INTP5IINTAD
ADCR: A/D conversion result
register
CRll: Timer 1 8-bit capture/
compare register
p_tu_re_ • •,
C_R_22_:_T_i..:.m_e_r
_2_8_-b_it_c_a_
_IN_T_P_l_:_E_x_te_rn_a_l_in_te_r_ru_p_t_p_in_p_O_2__
register
•
INTCOO
INTP2: External interrupt pin P03
INTCOl
INTC20
TM2: Timer 2 8-bit timer
register
Macro Service Type B.
A byte of data is transferred
in either direction between any specified special function register and a buffer anywhere in the 64K byte
address space. The macro service counter can be
programmed either to be an 8- or 16-bit counter. Macro
service Type B transfers can be initiated by any maskable interrupt except INTSER.
INTC2l
INTPO
INTPl
INTP2
INTP3
83YL-922M
The J,lPD78218A family provides three different types of
macro service transfers:
Macro Service Type A.
A byte of data is transferred
in either direction between a special function register,
preassigned for each interrupt request, and a buffer in
Internal RAM (FExx). Only the 8-bit macro service
counter is available for Type A transfers. The preassigned SFRs for the 12 interrupt requests that support
macro service Type A transfers are listed in table 5.
Macro Service Type C.
A byte of data is transferred
from a buffer anywhere in the 64K byte address space to
one of the 8-bit compare registers of timer 1. At the
same time, a second byte of data is transferred from a
buffer anywhere in the 64K byte address space to the
real-time output port buffer. The macro service counter
can be programmed either to be an 8- or 16-bit counter.
Macro service Type C transfers can be initiated by
INTC10 with data transferred to CR10 and POL or POH,
or by INTC11 with data transferred to CR11 and POL or
POH.
In addition, the macro service Type C transfer can be
initialized to automatically alter timer compare register values or to repeatedly output a prespecified pattern at a fixed or variable rate. By using macro service
Type C transfers to control the real-time output ports,
21
NEe
pPD78218A Family
the JlPD78218A family can easily and accurately drive
two independent stepper motors.
Refresh
The refresh signal is used with any pseudostatic RAM
equivalent of the NEC JlPD428128. The refresh cycle can
be set to one of four intervals: 16, 32, 64, or 128/fCLK
~2.~, 5.3, 10.7, and 21.3 Jls at 12 MHz). The refresh cycle
IS timed to follow a read or write operation to avoid
interference with external memory access cycles.
Standby Modes
HALT and STOP modes are provided to reduce power
consumption when CPU action is not required. In HALT
mode, the CPU is stopped but the system clock continues to run. The HALT mode is released by any
unmasked interrupt, an external NMI, or an external
reset pulse. In STOP mode, both the CPU and the
system clock are stopped, further minimizing the
power consumption. The STOP mode is released by
either an external reset pulse or an external NMI. The
22
HALT and STOP modes are entered by programming
the standby control register (STBC). This register is a
protected location and can be written to only by a
special instruction. If the third and fourth bytes of the
instruction are not complements of each other, the
data is not written and the next instruction is executed.
External Reset
The JlPD78218A family is reset by taking the RESET pin
low. The RESET input pin contains a noise filter to
pr~tect against spurious system resets caused by
nOise. On power-up, the RESET pin must remain low
until the power supply reaches its operating VOltage
and the oscillator has stabilized. During reset the
program counter is loaded with the address contained
in the reset vector table (address OOOOH, 0001H~
gram execution starts at that address upon the RESET
pin going high. While RESET is low, all external lines
except Vss, VDD, AVss, AVREF, X1, and X2 are in the high
impedance state.
NEe
IIPD78218A Family
ELECTRICAL SPECIFICATIONS
Operating Conditions
Absolute Maximum Ratings
Oscillation
Frequency,
TA = +25'C
'xx
4 to 12 MHz
TA
VDD
-40 to +85'C
+5 V ±10% (J1PD78217A/218A);
+5 V ±0.3 V (J1PD78P218A)
Operating voltage, Voo
AVREF
AVss
-0.5 to + 7.0 V
-0.5 to Voo + 0.5 V
-0.5 to + 0.5 V
Input voltage, VII
VI2 (Note 1)
V13 (Note 2 for JiPD78P218A)
-0.5 to Voo + 0.5 V
-0.5 to AV REF + 0.5 V
-0.5 to +13.5 V
TA
Item
Symbol
Output voltage, Vo
-0.5 to VOO + 0.5 V
Input capacitance
CI
Low-level output current, 10L
per pin
total, all output pins
Output capacitance
15mA
100 rnA
Input/output
capacitance
High-level output current, 10H
per pin
total, all output pins
-10 rnA
-50 rnA
Operating temperature, TOPT
-40 to +85'C
Storage temperature, TSTO
-65 to +150'C
Capacitance
= +25'C; voo = vss = 0 V
Max
Unit
20
pF
Co
20
pF
CIO
20
pF
Conditions
f = 1 MHz;
pins not used
for
measurement
are at 0 V
Notes:
(1) Pins P701ANO - P7s1AN5, P6a/WAI17AN6, and P67/REFRQJAN7
when used as the A/D converter input pins. However, the absolute maximum rating of VII must also be satisfied.
(2) P2ofNMI, EA/Vpp, and P21/INTPO/Ag pins in the PROM programming mode
Exposure to absolute maximum ratings for extended periods may
affect device reliability; exceeding the ratings could cause perma'
nent damage. The device should be operated within the limits
specified under DC and AC characteristics.
DC Characteristics
= -40 to +85'C; vss = 0 V;
TA
Item
voo
Xl low-level input current
+5 V ±0.3 V for JiPD78P218A)
Conditions
Unit
0.8
V
VIHI
2.2
VOO
V
Except the specified pins (Notes 1, 2)
VIH2
2.2
AVREF
V
Specified pins (Note 1)
V IH3
0.8 VOO
VIL
Min
=
Max
High-level input voltage
High-level output voltage
+5 V ±10% (Yoo
0
Low-level input voltage
Low-level output voltage
=
Symbol
Typ
VOO
V
Specified pins (Note 2)
VOlt
0.45
V
10L
VOL2
1.0
V
10L
V
VOHI
Voo-l.0
VOH2
VOO-0.5
V
VOH3
2.0
V
= 2.0 rnA
= 8.0 rnA (Note 3)
10H = -1.0 rnA
IOH = -100 JiA
10H = -5.0 rnA (Note 4)
IlL
-100
JiA
Xl high-level input current
IIH
100
JiA
VIH3 :S VI :S VOO
Input leakage current
III
±10
JiA
OV:s VI:S Voo
OV :S VI :S VIL
Output leakage current
ILO
±10
JiA
OV:s Vo:S Voo
AVREF current
AIREF
1.5
5.0
rnA
Operating mode,
VOO power supply current
1001
20
40
rnA
Operating mode, fXX
1002
7
20
rnA
HALT mode,
Ixx =
12 MHz
=
12 MHz
!xx =
12 MHz
23
NEe
pPD78218AFami Iy
DC Characteristics (cont)
Item
Symbol
Min
Data retention voltage
VOOOR
2.5
Data retention current
IOOOR
Pullup resistor
15
Conditions
Max
Unit
5.5
V
STOP mode
2
20
/lA
STOP mode; V DOOR
5
50
/lA
STOP mode; VOOOR
40
80
kO
VI
Typ
=
=
=
2.5 V
5 V ±10%
OV
Notes:
(3) Pins P401ADo - P47/A~, and P50/As - P57/AI5.
(1) Pins P701ANO - P7s1AN5, P6eJWAI17AN6, and P67/REFRQJAN7
when the pin is used as an AID converter input pin.
(4) Pins POo - P07.
(2) XI, X2, RESET, P201NMI, P21/INTPO, P22/INTP1,P23lINTP2/CI,
P2~INTP3, PS[!NTP4/ASCK, P2e1INTP5, P2 7/SI, P32/SCK, P3s!
SO/SBO, and EA pins.
AC Characteristics-Read/Write Operation
= -40 to +85"C; VSS = 0 V; !xx = 12 MHz; CL = 100 pF; VOO =
TA
Item
Symbol
XI input clock cycle time
tcyx
Address selup time to ASTB I
tSAST
Address hold time from ASTB I (Note 1)
Address hold time from RDt
+5 V ±10% (VOO
Calculation Formula (2, 3)
=
+5 V ±0.3 V for /lPD78P218A)
Min
Max
Unit
82
250
ns
52
ns
tHSTA
25
ns
Icyx-30
Conditions
tHRA
30
ns
Address hold time from WR t
tHWA
30
ns
Address to RD I delay time
tOAR
2tcyx-35
129
ns
tFAR
lcyx/2-30
11
tOAIO
(4+2n) tcyx -100
228
ns
No wait stales
181
ns
No wait states
100
ns
No wait states
Address float time to RD I
Address to data input time
ASTB 110 dala inpullime
ns
tOSTIO
(3+ 2n)lcYX - 65
RD I to data inpullime
tORIO
(2+2n)tcYX - 64
ASTB I to RD I delay time
tOSTR
Icyx- 30
52
ns
Data hold time from RD !
tHRIO
0
ns
RD f to address active lime
tORA
2tcyx-40
124
ns
RD t 10 ASTB t delay time
tORST
2tcYX -40
124
ns
RD low-level width
tWRL
(2+ 2n)tcyx - 40
124
ns
ASTB high-level widlh
twSTH
ICyx-30
52
ns
129
No wait states
ns
Address 10 WR I delay lime
IOAW
21cyx - 35
ASTB 110 data oulpul time
IOSTOO
ICYX + 60
WR I to data output time
toweD
ASTB I to WR I delay time
tOSTWl
tcvx- 30
52
tOSTW2
2tcYX -35
129
ns
Refresh mode
Data setup time to WR t
IsOOWR
(3 + 2n)lcYX -100
146
ns
No wait states
Data setup time to WR I
tsooWF
tcYX- 60
22
ns
Refresh mode
Data hold time from WR t (Note 1)
tHWOO
20
ns
WR ! to ASTB f delay time
tOWST
tcyx-40
42
ns
WR low-level width
twWL1
(3+2n)tcyx - 50
196
ns
No walt states
twWL2
(2+ 2n)tcYX - 50
114
ns
Refresh mode; No wait
states
tOAWT
3tCYX -100
Address to WAIT I Input time
24
142
ns
60
ns
ns
146
ns
NEe
IIPD78218A Family
AC Characteristics-Read/Write Operation (cont)
Item
ASTB
~
Symbol
Calculation Formula (2, 3)
to WAIT ~ input time
tOSTWT
2tCVX - 80
~
tHSTWT
2Xtcvx + 10
tOSTWTH
tORWTL
WAIT hold time from ASTB
ASTB
RD
~
~
to WAIT t delay time
to WAIT ~ input time
~
Min
Max
Unit
84
ns
ns
One external wait state
2(1+ x)tcvx - 55
273
ns
One external wait state
tcvx- 6O
22
ns
174
tHRWT
(2X -I)tcvx + 5
ns
One external wait state
to WAIT t delay time
tORWTH
(2X+l)tcvx - 60
186
ns
One external wait state
WAIT t to data input time
tOWTlO
tcvx- 2O
62
ns
WAIT hold time from RD
RD
~
87
Conditions
WAIT t to WR t delay time
tOWTW
2tCVX -10
154
ns
WAIT t to RD t delay time
tOWTR
tcvx- 1O
72
ns
tOWWTL
tcvx- 60
ns
Refresh disabled
tHWWT1
(2X-I)tcvx + 5
87
ns
One external wait state;
refresh disabled
tHWWT2
2(X-I)tcvx + 5
5
ns
One external wait state;
refresh enabled
tOWWTH1
(2X+l)tcvx- 6O
186
ns
One external wait state;
refresh disabled
tOWWTH2
2XtCVX-6O
104
ns
One external wait state;
refresh enabled
WR
~
to WAIT input time
WAIT hold time from WR ~
WR
~
to WAIT t delay time
22
RD t to REFRQ
~
delay time
tORRFQ
2tcvx -10
154
WR t to REFRQ
~
delay time
tOWRFQ
tcvx- 1O
72
no
REFRQ low-level width
twRFQL
2tcvx -44
120
ns
REFRQ t to ASTB t delay time
tORFQST
4tcvx -48
280
no
ns
IDI
Notes:
(1) The hold time includes the time during which VOH and VOL are
retained under the following load conditions: CL = 100 pF and
RL=2ko'
(2) n indicates the number of internal wait states.
(3) X indicates the number of external wait states (1, 2, 3, ...)
Serial Port Operation
TA = -40 to +85'C;Vss = OV;!xx = 12 MHz; CL = 100 pF;VOO = +5V j:10% (VOO = +5V ±0.3VforJlPD78P218A)
Item
Symbol
Min
Serial clock cycle time
tevSK
1.0
Jls
External clock input
1.3
Jls
Internal clock/16 output
Internal clock/64 output
Serial clock low-level width
Serial clock high-level width
twSKL
twSKH
Max
Unit
Conditions
5.3
Jls
420
ns
External clock input
556
ns
Internal clock/16 output
Internal clock/64 output
2.5
Jls
420
ns
External clock input
556
ns
Internal clock/16 output
Internal clock/64 output
2.5
Jls
SI, SBO setup time to SCK t
tSSSK
150
ns
SI, SBO hold time from SCK t
tHSSK
400
ns
25
NEe
pPD78218A Family
Serial Port Operation (cant)
Item
Symbol
Min
Max
Unit
SO/SBO output delay time from
SCKI
tOSBSK1
0
300
ns
CMOS push-pull output
(3-line serial 1/0 mode)
tOSBSK2
0
800
ns
Open-drain output
(SBI mode), RL = 1 kO
t
Conditions
4
tcyx
SBI mode
SBO low, setup time to SCK I
tsSBSK
4
tcyx
SBI mode
SBO low-level width
twSBL
4
1cyx
SBO high-level width
twSBH
4
tCYX
AID Converter Operation
= -40 to +85·C; vss = AVss = 0 V; voo =
+5"V :1:10% (Voo
SBO high, hold time from SCK
TA
Item
Min
Symbol
Resolution
=
Quantization error
Sampling time
Analog input voltage
1cONV
tsAMP
Analog input impedance
RAN
Analog reference voltage
AVREF
AVREF current
%
AVREF
0.8
%
AVREF
0.8
%
AVREF
:1:1/2
LSB
240
tcyx
125 ns " tcyx < 250 ns
(FR bit of ADM register is 1)
72
tcyx
82 ns " tCYX < 125 ns
(FR bit of ADM register is 0)
48
1cYX
125 ns " tCYX < 250 ns
(FR bit of ADM register is 1)
AVREF + 0.3
1000
Voo
V
1.5
5.0
mA
Operating mode, fxx
0.2
1.5
mA
STOP mode
+5V :1:10% (VOO
=
+5V
Item
Symbol Min Max Unit Conditions
NMllow-level width
twNIL
10
IlS
NMI high-level width
tWNIH
10
IlS
INTPO-INTP5 low-level width
twlTL
24
tcy)(
INTPO-INTP5 high-level width twlTH
24
1cYX
RESET low-level width
twRSL
10
Ils
RESET high-level width
twRSH
10
Ils
V
MO
3.6
Interrupt Timing Operation
= OV; VOO =
= 4.0V to Voo; TA = -10 to +70·C
= 3.6 V to Voo; TA = -10 to + 70·C
= 4.0V to Voo
82 ns " tcyx < 125 ns
(FR bit of ADM register is 0)
• Quantization errror is not included. Unit is defined as percent of
full-scale value.
26
0.4
tcyx
AIREF
TA = -40 to +85·C; VSS
:1:0.3 V for IlPD78P218A)
Conditions
360
-0.3
VIAN
Unit
Bit
8
Ful~scale error •
Conversion time
+5 V :1:0.3 V for IlPD78P218A)
Max
Typ
= 12 MHz
NEe
IJPD78218A Family
Data Retention Characteristics
TA = -40 to +85'C
Item
Symbol
MIn
Data retention voltage
VOOOR
2.5
Data retention current
IOOOR
Max
Unit
Conditions
5.5
V
STOP mode
2
20
JiA
VODDA = 2.5 V
5
50
JiA
VDDDR = 5V ±10%
Typ
VOO rise time
tAVO
200
VOOfalitime
tFVO
200
Jis
VOO retention time
(from STOP mode setting)
tHVO
0
ms
STOP release signal input time
tOREL
0
ms
twAIT
30
ms
Crystal resonator
5
ms
Ceramic resonator
Oscillation stabilization wait time
Low-level input voltage
High-level input voltage
Jis
0
VIL
0.1 VOOOR
V
Specified pins'
VOOOR
V
Specified pins'
0.9 VOOOR
VIH
* RESET, P201NMI, P2l/INTPO, P22/INTP1, P2:!/INTP2/CI, P~INTP3,
P2s1INTP4/ASCK, P26,tASCK, P2s1INTP5, P27/SI, P3:!/SCK, P3~SO/
S60, and EA pins.
Recommended Resonator Circuit
Recommended External Clock Circuit
.>0_----\ Xl
Clock
HCMOS
Inverters
X2
=
Clock frequency fxx 4 to 12 MHz
In STOP mode, XI Is Internally shorted to Vssto prevent
leakage curren~ Therefore, STOP mode Is not available
when using this external clock cln:ul~
Ceramic or crystal resonatorfraquency fxx= 4 to 12 MHz
External oscUlation cln:uft should be as close to the XI and
X2 pins as possible
Do not place oIher signal Ones In the shaded area
83YL·919M
Recommended Ceramic Resonators
(I'PD78217A1218A only)
Manufacturer
Murata Mfg.
External Clock Operation
TA = -40 to +85'C;
= +5 V ±10%;
twXL
30
130
ns
twXH
30
130
ns
txR
0
30
ns
txF
a
30
ns
tCYX
82
250
ns
XI Input low-level width
30
XI input high-level width
None*
None*
XI input rise time
CSAI2.0MTZ
CSTI2.0MTW
XI input fall time
XI input clock cycle time
aV
Unit
30
12
=
Max
C2(pF)
Cl (pF)
vss
Min
Symbol
Part Number
*Cl and C2 are contained in the resonator.
voo
Item
Frequency
(MHz)
Conditions
27
NEe
pPD78218A Family
Timing Waveforms
Voltage Thresholds for AC Timing Measurements
Vco- 1------~)(\._0_~_v~~~~~:~2_.2_V~)(, ________
0.45 v
--------'
Read Operation
X1
AS-A19
tOA1O
Input Dala
ADO-AD7
Address
tFAR
I '=0
AS1B
IDRID~
tWRL
AD
83YL-9182B'
28
NEe
pPD78218A Family
Timing Waveforms (cant)
Write Operation
X1
Address
•
t-----:-----IWWL1
IWWl2
------.....;...----.!- - - - -
IOSlW2 - - - - . j
83YL-91838
29
NEe
pPD78218A Family
Timing Waveforms (cont)
External WAIT Signal Input (Read Operation)
Input Oata
AOO-A07
Address
ASlB
>
~---- tOSTWTH
I
-:=1
1 + - - - - tHSTWT
L,~~'~
)0
tOWTR
83YL-9184B
30
NEe
IIPD78218A Family
Timing Waveforms (cant)
External WAIT Signal Input (Write Operation)
Output Data
Address
ASlB
j < E - - - - - - tDSTWTH ------l>~1
j---
s
B3YL-9187B
NEe
pPD78218A Family
Timing Waveforms (cont)
Serial Operation
Three-Une Serial VO Timing
SI------{
--'X'--______. .
so _ _ _
~
____---'x'--______~x~____
SB/Mode
..
Bus Release Signal Transfer Timing
~ =1=~~-----..J/
\'-----1/
\~-
SBO--'-[_-_-=--=--=--=--=-=)('--_____)(
Command Signal Transfer Timing
SBO
33
NEe
pPD78218AFami Iy
Timing Waveforms (cont)
Interrupt Input
External Clock
Xl
NMI
~----tCYX:----~
83ML-6995A
INTPOINTP5
Reset Input
Data Retention Characteristics
Set STOP Mode
t
I~~~-----IWAIT---~>~I
VOOOR
0.8 V
NMI
(Release by
VOOOR
failing
edge Input)
NMI
(Release by
O.BV
O.BVOO
rising
edge Inpul)
S3Yl.0.922GB
34
NEe
pPD78218A Family
Table 6. Pin Functions During PROM
Programming (cont)
"PD78P218A PROGRAMMING
In the pPD78P218A, the mask ROM of pPD78218A is
replaced by a one-time programmable ROM (OTP ROM)
or a reprogrammable, ultraviolet erasable ROM (UV
EPROM). The ROM is 32,768 x 8 bits and can be
programmed using a general-purpose PROM writer
with apPD27C256A programming mode.
The PA-78P214CW/GC are the socket adaptors used for
configuring the pPD78P218A to fit a standard PROM
socket.
Refer to tables 6 and 7 and figures 15 and 16 for special
information applicable to PROM programming.
Table 6. Pin Functions During PROM
Programming
Pin
Pin·
Function
POo- P07
Ao'A7
Address input pins for
PROM operations
PSoIAs
AS
Address input pin for PROM
operations
P21/INTPO
Ag
Address input pin for PROM
operations
P&.!/Al0' PSelA14
A1O'A14
Address input pins for
PROM operations
Pin
Pin*
Function
P401ADo' P47/
AD?
0 0 .07
Data pins for PROM
operations
P6sfWR
CE
Strobes data into the PROM
P64/RD
OE
Enables a data read from
the PROM
P201NMI
NMI
PROM programming mode
is entered by applying
+12.S volts to this pin
RESET
RESET
PROM programming mode
requires applying a low
voltage to this pin
EA
vpp
High voltage applied to this
pin for program write/verify
VOO
VOO
Positive power supply pin
Vss
Vss
Ground
*Pin name in PROM programming mode.
..
Table 7. Summary of Operation Modes for PROM Programming
NMI
RESET
CE
OE
Vpp
Voo
0 0 ,07
Program write
+12.SV
L
L
H
+12.SV
+6V
Data input
Data output
Mode
Program verify
+12.SV
L
H
L
+12.5V
+6V
Program inhibit
+12.5V
L
H
H
+12.5V
+6V
High Z
Read out
+12.SV
L
L
L
+SV
+5V
Data output
Output disable
+12.5V
L
L
H
+5V
+5V
High Z
Standby
+12.5V
L
H
L/H
+5V
+5V
High Z
Note: When +12.S V is applied to Vpp and +6 V to Vo o , both CE and
OE cannot be set to low level (L) simultaneously.
35
NEe
IIPD78218A Family
Figure 15. Pin Functions in pPD7BP218A PROM
Programming Mode; 64-Pin Plastic and
Ceramic Shrink DIP, 64-Pin Plastic QUIP
1
(5) Provide 1-ms program pulse (active low) to the CE
pin.
(6) This data is now verified with a pulse (active low) to
the OE pin. If the data has been written, proceed to
step 8; if not, repeat steps 4 to 6. If the data cannot
be correctly written after 25 attempts, go to step 7.
~PD78P218ACW
~PD78P218AOW
AS
(4) Provide write data.
64
A4
A5
(7) Classify as defective and stop write operation.
Aa
A7
(8) Provide write data and supply program pulse (for
additional writing) for 3 ms times the number of
writes performed in step 5.
L{
(9) Increment the address.
L
(10) Repeat steps 4 to 9 until the end address.
PROM Read Procedure
Open
G
vss
VOO
vPP
L
}L
A14
A1S
A12
A11
A10
L
Aa
07
} Open
},
(1) Set the pins not used for programming as indicated in figures 15 and 16. Fix the RESET pin to a
low level, the Voo and Vpp Rins to +5 V, and apply
+ 12.5 VtotheNMI pin. The CE and OE pins should
be high.
(2) Input the address of the data to be read to pins
Ao-A14·
(3) Read mode is entered with a pulse (active low) on
both the CE and OE pins.
(4) Data is output to the Do to D7 Pins.
°a0 5
EPROM Erasure
04
Data in an EPROM is erased by exposing the quartz
window in the ceramic package to light having a wavelength shorter than 400 nm, including ultraviolet rays,
direct sunlight, and fluorescent light. To prevent unintentional erasure, mask the window.
Os
02
VSS -..::::......_--.::::..r
NoIa8:
(1) L: Connectlhese pins separately to VSS through
nlSlstors.
(2) G: Connect these pins to VSS.
(S) Open: Do not connect these pins.
PROM Write Procedure
(1) Set the pins not used for programming as indicated in figures 15 and 16. Connect the RESET pin
to a low level, the Voo and Vpp pins to +5 V, and
apply + 12.5 V to the NMI pin. The CE and OE pins
should be high.
(2) Apply +6 V to the Voo pin and + 12.5 V to the Vpp
pin.
(3) Provide the initial address to the
36
Ao to A14 pins.
Typica"y, data is erased by 254-nm ultraviolet rays. A
minimum lighting level of 15 Ws/cm 2 (ultraviolet ray
intensity x exposure time) is required to completely
erase written data. Erasure by an ultraviolet lamp rated
at 12 mW/cm2 takes approximately 15 to 20 minutes.
Remove any filter on the lamp and place the devicewithin 2.5 cm of the lamp tubes.
NEe
JlPD78218A Family
Figure 16. Pin Functions in pPD78P21BA PROM Programming Mode; 64-Pin Plastic QFP
RESET
Open
G
IlPD78P218AGC
Vss
A,S
41
VOO
Vpp
}L
}OpBn
A'4
A'3
A'2
All
~O
L
Not..:
(1) L: Connect these pins ..pal8tely to VSS through
resfstors.
(2) G: ConnecttheseplnstoVSS'
(3) Open: Do not connect the.. pins.
DC Programming Characteristics
TA = 25 :!:5"C; VIP = 12.5 :!:0.5V applied to NMI pin; Vss = OV
Parameter
High-level input voltage
Low-level input voltage
Symbol·
Min
Max
Unit
VIH
VIH
2.4
Voop+ 0.3
V
VIL
VIL
-0.3
0.8
V
10
Symbol
Typ
Condition
Input leakage current
ILiP
/lA
O:S VI:S Voop
High-level output voltage
VOHl
VOHl
2.4
V
IOH = -400/lA
VOH2
VOH2
VOo-O.7
V
IOH = -100 /lA
0.45
V
IOL = 2.1 mA
Low-level output voltage
VOL
Output leakage current
III
VOL
ILO
10
/lA
NMI pin high-voltage input current
liP
:!:10
/lA
VDDP power voltage
VDDP
Vpp power voltage
Vpp
Vee
Vpp
Os VO:S VODP, OE = VIH
5.75
6.0
6.25
V
Program memory write mode
4.5
5.0
5.5
V
Program memory read mode
12.2
12.5
12.8
V
Program memory write mode
V
Program memory read mode
Vpp = VDDP
37
NEe
,.,PD78218A Family
DC Programming Characteristics (cont)
Parameter
Symbol
Voop power current
lOOp
Vpp power current
Symbol*
Min
Typ
Max
Unit
Condition
5
30
mA
Program memory write mode
5
30
mA
Program memory read mode
CE = VIL. VI = VIH
5
30
mA
Program memory write mode
CE = VIL. OE = VIH
100
/1A
Program memory read mode
ICC
Ipp
Ipp
·Corresponding symbols of the /1PD27C256A.
AC Programming Characteristics (Write Mode)
TA = 25 :l:5°C; VIP = 12.5 :1:0.5 V applied to NMI pin; Vss = 0 V; Voo = 6 :1:0.25 V; Vpp = 12.5 :1:0.3 V
Parameter
Symbol
Address setup time to CE I
tsAC
tAS
2
/1s
Data input to OE I delay time
toooo
toES
2
/1s
Input data setup time to CE I
tSIDC
tos
2
/1s
tHCA
tAH
2
/1s
tHCIO
tOH
2
tHOOO
tOF
0
tsvPC
!YPS
VOOP setup time to CE I
ts,VOC
!Ycs
Initial program pulse width
twL1
tpw
0.95
Additional program pulse width
twL2
tOPW
2.85
NMI high-voltage input setup time to CE •
tspc
OE I to data output time
toooo
Address hold time from CE
t
Input data hold time from CE
t
Output data hold time from OE
t
Vpp setup time to CE I
Symbol*
Min
Max
Typ
Unit
Conditions
/1s
ns
130
ms
ms
1.0
1.05
ms
78.75
ms
2
/1s
150
tOE
ns
·Correspondlng symbols of the /1PD27C256A.
AC Programming Characteristics (Read Mode)
TA
= 25 :l:5°C; VIP = 12.5 :1:0.5 V applied to NMI pin; VSS = 0 V; VOO =5 :1:0.5 V; Vpp =
Max
Unit
Address to data output time,
tDAOO
tACc
200
ns
CE = OE = VIL
CE I to data output time
tOCOO
icE
200
ns
OE = VIL
OE I to data output tlmll
tOOOD
tOE
75
ns
CE = VIL
Data hold tlmll from OE t
tHCOO
tOF
0
60
ns
CE = VIL
Data hold time from address
tHAOO
toH
0
ns
CE = OE = VIL
38
Min
Typ
Condition
Symbol
* Corresponding symbols of the /1PD27C256A.
Symbol*
Voop
Parameter
NEe
pPD78218A Family
PROM Timing Diagrams
PROM Write/Verifying Mode
~w~ "I"
x RepellUons
AO-A14
00-07
~
tSAC
Data
Input
IsI0C-
I
-
VOO
-.I
Vpp
VOOP
VOO
Voo
VIH
Additional W~te--1
-1
Data
Output
-
r--
I+- tHOOO
~ rtSIOC
-.I
Vpp
VIL
~
I+- tHJIO
VIP
NMI
:1-
ElfecUve Address
-r
~
Verify
Data
Input
~
K
tHCA
t.~'"
HI-Z
i-tspc
I+-tsvpc
-.I
-
III
I+-tsvoc
CE
VIL
Notee:
(1) VOO must be epplled before applying Vpp. It should be removed after removing V pp.
(2) Vpp must not exoaed +13V, IncludIng overshoot.
83ML05996B
39
NEe
"PD78218A ·Fami Iy
PROM Read Mode
EfIadIve AddreM
tHAOD
Data Output
HI-Z
83ML-5997B
40
pPD78224 Family
(pPD78220/224/P224)
8·Bit, K·Series Microcontrollers
NEG Electronics Inc.
With Analog Comparators, Real·Time Output Ports·
NEe
August 1993
Description
The JlPD78220, JlPD78224, and JlPD78P224 are members of the K-Series® of microcontrollers. These 8-bit,
single-chip microcontrollers contain extended addressing capabilities for up to 1M byte of external
memory. The devices also integrate sophisticated analog and digital peripherals as well as two low-power
standby modes that make them ideal for low-power/
battery backup applications.
The /-lPD78224 family focuses on embedded control
with features such as hardware multiply and divide, two
levels of interrupt response, four banks of main registers for multitasking, and macro service for processorindependent peripheral and memory DMA. Augmenting this high-performance core are advanced
components; for example, eight analog voltage comparators, two independent serial interfaces, several
counter/timers for PWM outputs, and a real-time output
port. On board memory includes 640 bytes of RAM and
16K bytes of mask ROM or OTP ROM.
The macro service routi ne allows data to be transferred
between any combination of memory and peripherals
independent of the current program execution. The
four banks of processor registers allow simplified context switching to be performed. Both features, combined with powerful on-Chip peripherals, make the
JlPD78224 family ideal for a wide variety of embedded
control applications.
Features
o Complete single-chip microcontroller
-8-bitALU
-16K ROM
- 640 bytes RAM
- Both 1-bit and 8-bit logic
o Four timer-controlled PWM channels
o Two 4-bit real-time output ports
o Extensive interrupt handler
- Vectored interrupt handling
- Programmable priority
- Macro service mode
o Two independent serial ports
o Refresh output for pseudostatic RAM
o On-chip clock generator
-12-MHz maximum CPU clock frequency
- 0.33-/-ls instruction cycle
o CMOS silicon gate technology
o 5-volt power supply
Ordering Information
Part Number
ROM
IlPD78220L
ROMless
IlPD78224L-xxx
16K mask ROM
IlPD78P224L
16K OTP ROM
IlPD78220GJ-58G
ROM less
IlPD78224GJ-xxx-58G
16K mask ROM
IlPD78P224GJ-5BG
16K OTP ROM
Package (Dwg)
84-pin PLCC
(P84L-50A3-1)
~
~
94-pin plastic QFP
(S94GJ-80-58G-l )
Pin Identification
Function
Symbol
POo - P07
Output port 0
Pl 0 - P17
I/O port 1
P20INMI
Input port 2/Nonmaskable interrupt input
P21 - P22/INTPO - INTPI
Input port 2/Ext interrupt input/timer trigger
P2:y'INTP2/CI
Input port 2/Ext interrupt input/Clock input
P24/INTP3
Input port 2/Ext interrupt input/timer trigger
o Instruction prefetch queue
P2s1INTP4
Input port 2/Ext interrupt input
o Hardware multiply and divide
P2a1INTP5
Input port 2/Ext interrupt input
o Memory expansion
- 8085 bus-compatible
- 64K program address space
- 1M data address space
P27/INTP6/SI
Input port 2/Ext interrupt input/Serial input
P301RxD
I/O port 3/Serial receive input
P3l/ TxD
I/O port 3/Serial transmit output
o Large I/O capacity: up to 71 I/O port lines
o Extensive timer/counter functions
-One 16-bit timer/counter/event counter
- Two 8-bit timer/counter/event counters
K-Series is a registered trademark of NEC Electronics,lnc.
50113
P32/SCK
I/O port 3/Serial clock input/output
P3:y'SO/S80
I/O port 3/Serial output/Serial bus I/O
P34 - P37/TOO - T03
I/O port 3/Timer output
P40 - P47/ADo - AD7
I/O port 4/Lower address byte/data bus
P50 - P57/AS - A 15
I/O port 5/Upper address byte
,
NEe
pPD78224 Family
Pin Identification
Symbol
Function
Function
Symbol
Output port 6/Extended address nibble
ASTB
Address strobe output
P6.vRD
I/O port 6/Read strobe output
RESET
External reset input
PSsfWR
I/O port 6IWrite strobe output
EA
External memory access control input
PSafWAIT
I/O port 6IWait input
XI, X2
External crystal or external clock input
PS7/REFREQ
I/O port 6/Rerresh output
VDD
Positive power supply input
P7o· P76
I/O port 7
Vss
Power return; normailly ground
PTO· PT7
Port T analog inputs to voltage comparators
NC
No connection
IC
Internal connection; connect to Vss
P60 • P631'A16 • A19
Pin Configurations
84-PinPLCC
P74
P7S
P7e
P20fNMI
P21f1NTPO
P22f1NTPt
P42fAD2
P43fAD3
P44fAD4
P4sfADs
P46fAD6
P47fAD7
P23nNTP2 fCI
P24nNTP3
P50fAS
P51fA9
P2SnNTP4
P52fAl0
P2enNTPS
P27nNTPe fSl
P53fA 11
P54fA12
P30fRxD
P55fA13
P3t fTxD
P56fA14
P32fSCK
P57fA15
P60fA16
P33fSOISBO
P34fTOO
P3SfTOI
P3efT02
P37fTOO
PTO
P61fA17
P62fA1S
P63f~9
P64fRD
P65~
P66IWAIT
PTI
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pPD78224 Family
Pin Functions
pOo - P~. Port 0 is an 8-bit, tristate output port. Port 0
can also be configured as two 4-bit, real-time (timercontrolled) output ports.
P10 - P17' Port 1 is an 8-bit bidirectional tristate port.
Bits are individually programmable as input/output.
Each pin is capable of driving an LED directly (8 mA).
P20 - P27' Port 2 is an 8-bit input port.
NMI. Nonmaskable interrupt input.
INTPO - INTP6. External interrupt inputs. INTPO, INTP1,
and INTP3 are timer capture trigger inputs.
CI. External clock input to the timer.
SI. Serial data input for three-line serial I/O mode.
P30 - P37' Port 3 is an 8-bit tristate I/O port, each bit
programmable as input/output.
RxD. Receive serial data input.
TxD. Transmit serial data output.
SCK. Serial shift clock output!input.
SO. Serial data output for three-line serial I/O mode.
SBO. I/O bus for the clocked serial interface.
TOO - T03. Timer flip-flop outputs
P40 - P47' Port 4 is an 8-bit, bidirectional tristate port.
ADo - AD 7• Multiplexed address/data bus used with external memory or expanded I/O.
P50 - P57' Port 5 is an 8-bit, tristate output port.
As - A15' Upper-order address bus used with external
memory or expanded I/O.
P60 - P63' Pins P60 - P63 of port 6 are outputs.
A16 - A19' Extended-order address bus used with external memory.
4
P64 - per. Pins P64 - P6r of port 6 are individually programmable tristate input/output pins.
RD. Read strobe output used by external memory (or
data registers) to place data on the I/O bus during a
read operation.
WR. Write strobe output used by external memory (or
data registers) to latch data from the I/O bus during a
write operation.
WAIT. Wait signal input.
RE FRQ. Refresh pulse output used by external pseudostatic memory.
P70 - P76' Port 7 has seven individually programmable
tristate I/O pins.
PTO - PT7. Port T is an eight-line input port. The analog
voltage on each line is compared continuously with a
programmable threshold voltage.
ASTB. Address strobe output used by external circuitry to latch the low-order 8 address bits during the
first part of a read or write cycle.
RESET. A low level on this external reset input sets all
registers to their specified reset values. This pin, together with P2oINMI, sets the pPD78P224 in the PROM
programming mode.
EA. Control signal input that selects external memory
or internal ROM as the program memory. When EA is
low, ROM less mode is initiated and external memory is
accessed.
X1, X2. For frequency control of the internal clock
oscillator, a crystal is connected to X1 and X2. If the
clock is supplied by an external source, the clock signal
is connected to X1 and the inverted clock signal is
connected to X2.
NEe
pPD78224 Family
Block Diagram
Bus Control
PSO-PS 71
AS-A15
P40-P471
ADO-AD7
P30/RxD
P311TxD ~I-----I
P80-P8 31
A18-A19
P32/SCK
P84 1RD
P33IS01SBO
P27/1NTP6ISI
P8SIWR
INTP3 -
......- - - . . . . ,
P34iTOO
P66IWAIT
P3siTOl
P67/REFRQ
..
ASTB
System Control
Xl
X2
RESET
EA
PTO-PT7
VDD
Internal Data Bus
VSS
DetaBus
Peripheral Bus VF
83ML-8D8OB
5
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pPD78224 "Family
FUNCTIONAL DESCRIPTION
Timing
The maximum clock frequency is 12 MHz. The clock is
derived from an external crystal or an external oscillator. The internal processor clock is two-phase and the
machine states are executed at a rate of 6 MHz. The
shortest instructions require two states (333 ns). The
CPU contains a one-byte instruction prefetch. This
allows a subsequent instruction to be fetched during
the execution of an instruction that does not reference
memory.
Memory Map
The JlPD78224 family has 1M bytes of address space.
This address space is partitioned into 64K bytes of
program memory starting at address OOOOOH. (See
figure 1). The remainder of the 1M bytes can be accessed as data memory space.
Figure 1. MemoryMap
OOOOOH
OOOOOH
On·ChlpROM
Interrupt Vector
Address Table Area
OOOSFH
OOO4OH
1------1
0007FH
OOO8OH
1-----'--1
CALLT Table Area
18,384 Bytes
r
(Must be extemal
memory
In ~PD78220)
Program Area
007FFH 1-_ _ _ _- ;
OOeooH
CALLFEntry
OSFFFH 1 - - - - - - 1 -
OOFFFHI_ _ _
A_rea_ _{
~
04000H
~
r
:rI
OFCeOH
On-ChipRAM
On·Chlp
RAM
840 Bytes
OFEFFH
OFFOOH
Special FuncUon
RegISter (SFR)
Area
OFFFFH
10000H
,
1
FFFFFH
6
l~
external
Memory
(Extended
Address
Area)
:rI
Program Area
OSFFFH
'-:..:.---'"--------'
Extemal Memory ~
OFC7FH
OFC80H
01000H
1
OFEDFH
OFEEOH
OFEFFH
Genera~Purpos8
Registers
NEe
pPD78224 Family
External memory is supported by I/O port 4, an 8-bit
multiplexed address/data bus. The memory mapping
register controls the size of external memory as well as
the number of added wait states. The upper address
byte is derived from port 5, and the extended address
nibble is derived from port 6.
The /iPD78224 has on-Chip mask ROM occupying the
space from OOOOOH to 03FFFH. When the ROM is used
and no other program or data space is required, ports
4, 5, and 6 are available as additional I/O ports.
General-Purpose Registers
The general-purpose registers are mapped into specific addresses in data memory. They are made up of
four banks, each bank consisting of eight 8-bit or four
16-bit registers. The register bank used is specified by
a CPU instruction. This can be checked by reading
RBSO and RBS1 in the program status word (PSW). The
general-purpose register configuration is shown in
figure 2.
Special Registers
There are three different special registers. The first is a
16-bit binary counter that holds the next program
address to be executed and is named the program
counter. The stack pointer is the second special 16-bit
register. The stack pointer holds the address of the
stack area (a last in, first out system). The third special
register is an 8-bit program status word. This register
contains various flags that are set or preset depending
on the results of instruction execution. The program
status word format is as follows:
o
7
IE
I
I RBS1 I
z
CY
AC
I RBSD I
0
ISP
CY
Carry flag
Interrupt priority status flag
Register bank selection flags
Auxiliary carry flag
Zero flag
Interrupt request enable flag
ISP
RBSO, RBS1
AC
Z
IE
I
.~
Special Function Registers
I
These registers are assigned to special functions such
as the mode and control registers for on-Chip peripheral hardware. They are mapped into the 256-byte
memory space from OFFOOH to OFFFFH. Table 1 is a list
of special function registers.
Figure 2. Register Mapping
OFEEOH Register
Bank
3
For8·Blt
Processing
2
I
OFEFFH
0
\
OFEF9H
-
-
-
- -
For 16-Btt
Processing
(R1) A
(RO) X OFEF8H
(R3)B
(R2)C
(RP1)BC
OFEFAH
(R5)D
(R4)E
(RP2) DE
OFEFCH
(R7)H
(R6)L
(RP3) HL
OFEFEH
O£EF~H
- - - - -
(RPO) AX
OFEF8H
) = Absolute Name
B3YL-9170B
7
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pPD78224 Family
Table 1. Special Function Registers
Access UnIts (BIts)
Address
RegIster (SFR)
Symbol
R/W
1
8
16
State After Reset
OFFOOH
PortO
PO
R!W
x
x
Undefined
OFF01H
Port 1
Pl
R!W
x
x
Undefined
OFF02H
Port 2
P2
R
x
x
Undefined
OF F03H
Port 3
P3
R!W
x
x
Undefined
OFF04H
Port 4
P4
R!W
x
x
Undefined
OFF05H
Port 5
P5
R/W
x
x
Undefined
OFF06H
PortS
P6
R/W
x
x
xOH
OF F07H
Port 7
P7
R/W
x
x
Undefined
OF FOAH
Port 0 buffer register (low)
POL
R!W
x
x
Undefined
OFFOBH
Port 0 buffer register (high)
POH
RfW
x
x
Undefined
OFFOCH
Rea~time output port control register
RTPC
R/W
x
x
OOH
OFF10H·
FFllH
IS-bit compare register 0 (IS-bit timer/counter)
CROO
R!W
x
Undefined
OFF12HFF13H
IS-bit compare register 1 (lS-bit timer/counter)
CROl
R!W
x
Undefined
OFF14H
8-bit compare register (8-bit timer/counter 1)
CR10
R!W
x
OFF1SH
8·bit compare register (8-bit timer/counter 2)
CR20
R!W
x
Undefined
OFF1SH
8-bit compare register (8·bit timer/counter 2)
CR21
R/W
x
Undefined
OFF17H
BRG 8-bit compare register
CR30
R/W
x
OFF18HFF19H
lS-bit capture register (lS-bit timer/counter)
CR02
R
OFF1AH
8·bit capture register (8-bit timer/counter 2)
CR22
R
x
Undefined
OFF1CH
8·bit capture/compare register (8-bit timer/counter 1)
CRll
R!W
x
Undefined
OFF20H
Port 0 mode register
PMO
W
x
FFH
OFF21H
Port 1 mode register
PMl
W
x
FFH
OFF23H
Port 3 mode register
PM3
W
x
FFH
OFF25H
Port 5 mode register
PM5
W
x
FFH
OFF2SH
Port S mode register
PMS
R!W
x
FFH
OFF27H
Port 7 mode register
PM7
W
x
7FH
Undefined
Undefined
x
Undefined
OFF30H
Capture/compare control register 0
CRCO
W
x
10H
OFF31H
Timer output control register
TOC
W
x
OOH
OFF32H
Capture/compare control register 1
CRCl
W
x
OOH
OFF34H
Capture/compare control register 2
CRC2
W
x
OOH
OFF43H
Port 3 mode control register
PMC3
R/W
OFF50HFF51H
lS·bit timer register 0
TMO
R
OFF52H
8-bit timer register 1: CH -1
TMl
R
OFF54H
8·bit timer register 2: CH-2
TM2
R
OFF5SH
BRG 8-bit timer register
TM3
R
OFF5CH
Prescaler mode register 0
PRMO
W
OFF5DH
Timer control register 0
TMCO
R!W
8
x
x
OOH
x
x
x
x
x
x
OOOOH
OOH
OOH
OOH
OOH
OOH
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Table 1.
IJPD78224 Family
Special Function Registers (cont)
Access Units (Bits)
Address
Register (SFR)
Symbol
OFF5EH
Prescaler mode register 1
OFF5FH
Timer control register 1
16
State After Reset
R/W
8
PRM1
W
x
OOH
TMC1
R/W
x
OOH
R/W
x
x
OOH
R
x
x
Undefined
OFF6EH
Port T mode register
PMT
OFF6FH
PortT
PT
OFF80H
Clocked serial interface mode register
CSIM
R/W
x
x
OOH
OFF82H
Serial bus interface control register
SBIC
R/W
x
x
OOH
OFF86H
Serial shift register
SIO
R/W
OFF88H
Asynchronous serial interface mode register
ASIM
R/W
OFF8AH
Asynchronous serial interface status register
ASIS
R
OFF8CH
Serial receive buffer: UART
RxB
R
x
Undefined
OFF8EH
Serial transmit shift register: UART
TxS
W
x
Undefined
x
OOOOxOOOB
x
Undefined
x
x
BOH
x
x
OOH
OF FCOH
Standby control register
STBC
R/W
OFFC4H
Memory expansion mode register
MM
R/W
x
x
20H
OFFC5H
Programmable wait control register
PW
R/W
x
x
80H
OFFC6H
Refresh mode register
RFM
OFFEOH
Interrupt request flag register L
IFOL
OFFE1H
Interrupt request flag register H
IFOH
OFFE4H
Interrupt mask flag register L
MKOL
OFFE5H
Interrupt mask flag register H
MKOH
OFFE8H
Priority specification flag register L
PROL
OFFE9H
Priority specification flag register H
PROH
OFFECH
Interrupt service mode speification flag register L
ISMOL
IFO
MKO
PRO
ISMO
R/W
x
x
R/W
x
x
R/W
x
x
R/W
x
x
R/W
x
x
R/W
x
x
R/W
x
x
R/W
x
x
OOH
x
.~
Undefined
I
I
Undefined
x
FFFFH
x
FFFFH
x
OOOOH
FFFFH
FFFFH
OFFEDH
Interrupt service mode specification flag register H
ISMOH
R/W
x
x
OOOOH
OFFF4H
External interrupt mode register 0
INTMO
R/W
x
x
OOH
OFFF5H
External interrupt mode register 1
INTM1
R/W
x
x
OOH
OFFFBH
Interrupt status register
1ST
R/W
x
x
OOH
9
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pPD78224 Family
Input/Output Ports
Real-time Output Port
Functions of ports PO - P7 and port PT are explained
below. All ports are 8 bits wide except P7, which is 7 bits
wide.
The real-time output port (figure 3) shares pins with
port o. The high and low nibbles may be treated
separately or together. In the real-time output function,
data stored beforehand in the buffer register is transferred to the output latch simultaneously with the
generation of either a timer interrupt or external interrupt. Using the real-time output function in conjunction
with the macro service function enables port 0 to
output preprogrammed patterns at preprogrammed
variable time intervals.
Port
Function
PO
8-bit output port or two 4-bit real time output
ports
P1
Bit programmable for input or output; large
current capacity
P2
Input
P3
Bit programmable for input or output
Port T
P4
Input or output
P5
Output
As shown in figure 4, the analog input voltage on each
line of port T is compared with a programmable threshold vOltage. The comparator output is 1 if the input
voltage is higher than the threshold, or a if it is lower.
Output
Bit programmable for input or output
P7
Bit programmable for input or output
PT
Inputs to eight voltage comparators
Four bits from the PTM regster are decoded to set the
threshold voltage at one of 15 steps: Voo x 1/16 through
Voo x 15/16. Each comparator operates continously as
follows.
Figure 3_ Real-Time Output Port
IntemalBu.
RTPC
Buffer 7eglster
4-B1t
Real-Time
Output (POH)
POH
POL
4-81t Real-Time
Output (POL)
8
4
4
8-Blt Real-Time
Output (PO)
EXTR
83ML-G089:B
10
NEe
(1) Threshold voltage is set by writing the PTM register.
"PD78224 Family
Figure 4.
(2) As each comparison is completed, the result is
latched in port T and the next comparison begins.
Comparator Port T
Pull·Up
Resistors
(3) Unless the PTM regiser is written, the threshold
voltage is not changed.
Two bits from the PTM register specify the connection
of pullup resistors in 4-bit units. When PTM is set to
OOH, the resistor ladder is released and threshold
voltage is not supplied to the comparators. This can be
done in the standby mode to eliminate unnecessary
current drain.
Serial Interface
PTO
o--+---e:JI------~
PT1 o--+--~I---+--+-[~
PT2 o---+---f'1-----l---l-~
The pPD78224 family has two independent serial interfaces.
• Asynchronous serial interface (UART) (figure 5)
• Clock-synchronized serial interface (figure 6)
A universal asynchronous receiver transmitter (UART)
is used as an asynchronous serial interface. This interface transfers one byte of data following a start bit. The
IlPD78224 contains a baud rate generator. This allows
data to be transferred over a wide range of transfer
rates.
The clock-synchronized serial interface has two different modes of operation:
• Three-line serial I/O mode.
In this mode, data 8 bits long is transferred along
three lines: a serial clock (SCI<) line and two serial
bus lines lines (SO and SI). This mode is convenient
when a pPD78224 device is connected to peripheral
II0s and display controllers that have the conventional clock-synchronized serial interface.
• Serial bus interface mode (SBI)
In this mode, the pPD78224 family can communicate
data with several devices using the serial clock
(SCI<) and the serial data bus (SBO) lines. This mode
conforms to NEC's serial bus format. In SBI mode,
addresses that select a device to communicate with,
commands that direct the device, and actual data
are output to the serial data bus. A handshake line,
which was required for connecting several devices in
the conventional clock-synchronized serial interface, is not needed.
PT5 o-+---P'}----+-+--+--I~
PT6
o--+----fI:.....-+--+--+-{~
Pl7
o-+--...p.}----+-+--+--I~
Threshold
Voltage
Resistor
Ladder
DeCOder
4
(16 Seclions)
PortTMode
Register
PTM
83ML-8084A.
11
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pPD78224 Family
Figure 5. Asynchronous Serillllnterfllce
Internal Bus
L--'==-.r--
'CLK
INTSR
I
I TransmlllReceive Baud
,--..I..--"...:..J
L Rate
_ _Generator
_ _ Oulput
_ _ _ _ _ _
'--_ _...r~- 'CLK/8
Baud Rate Genarator
83RD-6S618
12
NEe
IIPD78224 Family
Figure 6. Clock-Synchronized Serial Interface
Selector
BUSY!
Acknowledge
Output Clrcuft
N-ch Open-Drain
Output Possible
<=>
•
Bus Release!
Command!
Acknowledge
Dstecllon
Clrcuft
83RD-6352B
13
NEe
IlPD78224 Family
Timer/Counters
The pPD78224 family has three timer/counters: one
16-bit and two 8-bit. The 16-bit timer/counter (figure 7)
has the basic functionality of an interval timer, a programmable square wave output, and a pulse-width
measurer. These functions can provide a digital delayed one-shot output, a pulse-width modulated output, and a cycle measurer.
The two 8-bit timer/counters can provide the basic
functions of an interval timer and a pulse-width measurer. Timer/counter 1 can also be used as a timer for
output trigger generation for the real-time output port.
Timer/counter 2 can also provide an external event
counter, a one-shot timer, a programmable squarewave output, a pulse-width modulated output, and a
cycle measurer. See figures 8 and 9.
Figure 7.
16-8it Timer/Counter
Internal Bus
Extemal
Capture!
Interrupl
Mode Register
(1N1M1)
Compare
Control
Register
(CRCO)
P2311NTP2
.--.J.-..........£..-,
~~I
1..--,1,,...----1 Register
(lMCO)
16
83ML-607EIB
14
NEe
pPD78224 Family
Figure B. B-Bit Timer/Counter t
Internal Bus
8
8
Extemallnterrupt
Mode RegIster 0
(INTMO)
Capture!
Compare
Cont Reg 1 L...-,--'"-r--'--,---'
(CRCf)
INTPO
-*c--...::..::cc.:.==-=-------+-+--......,~~ INTCfO
fCLK 15f2
fCLK1256
fCLK/f28
f CLK 184
'CLK /32
fCLKI16
Selector
1---+--"'1
Overflow
8·BR11mer
(TMf)
•
Capture
T~gger
Prescaler
Mode RegIster
(PRM1)
L-_.....l.--,:,.,.....-'-_---I
f-----+--+---L.JJ-O~---- INTCff
...--'--r---'---. 11mer
Control
RegIster f
(TMC1)
'--_*_---'
8
Internal Bus
83ML-6077B
15
NEe
pPD78224 Family
Figure 9. B-Bit Timer/Counter 2
INTP1
' - - - - - - - 1 i - - -.. INTC21
Prescal8r
Mode Register
(PRM1)
8
Internal Bus
83ML-6078B
Interrupts
There are 18 interrupt request sources; each source is
allocated a location in the vector table. (See table 2).
There is one software interrupt request and one of the
remaining 17 interrupts is nonmaskable. The software
interrupt and the nonmaskable interrupt are uncondi·
tionally received even in the 01 state. These two interrupts possess the maximum priority. The maskable
interrupt requests are subject to mask control by the
setting of the interrupt mask flag.
There are default priorities associated with each maskable interrupt and these can be assigned to either of
two programmable priority levels. Interrupts may be
serviced by the vectored interrupt method where a
branch to a desired service program is executed.
Interrupts may also be handled by the macro service
function where a preassigned process is performed
without program intervention.
16
NEe
pPD78224 Family
Table 2. Interrupt Sources and Vector Addresses
Interrupt
Request
Type
Default
Priority
Interrupt Request Source
Software
None
BRK instruction execution
003EH
Nonmaskable
None
NMI (pin input edge detection)
0OO2H
INTPO (pin input edge detection)
0OO6H
Maskable
o
Macro Service
Handling
Vector
Table
Address
INTPl (pin input edge detection)
0008H
2
INTP2 (pin input edge detection)
OOOAH
3
INTP3 (pin input edge detection)
OOOCH
4
INTCOO (TMO-CROO coincidence signal generation)
0014H
5
INTCOl (TMO-CAOl coincidence signal generation)
6
INTC10 (TM1-CR10 coincidence signal generation)
Yes
0018H
7
INTC11 (TM1-CRll coincidence signal generation)
Yes
001AH
8
INTC21 (TM2-CR21 coincidence signal generation)
9
INTP4 (pin input edge detection)
10
INTP5 (pin input edge detection)
0010H
11
INTP6 (pin input edge detection)
0012H
0016H
001CH
OOOEH
Yes
12
INTSER (generation of asynchronous serial interface receive error)
13
INTSR (end of asynchronous serial interface reception)
Yes
0022H
14
INTST (end of asynchronous serial interface transmission)
Yes
0024H
15
INTCSI (end of clocked serial interface transfer)
Yes
0026H
Macro Service
When macro service function can be programmed to
transfer data from a special function register to memory or from memory to a special function register.
Transfer events are triggered by interrupt requests and
take place without software intervention. There are six
interrupt requests where macro servicing can be executed. The macro service function is controlled by the
macro service mode register and the macro service
channel pointer. The macro service mode register assigns the macro servicing mode and the macro service
channel pointer indicates the address of the memory
location pointers. The location of each register and its
corresponding interrupt is shown in figure 10.
Refresh
The refresh signal is used with a pseudostatic RAM. The
refresh cycle can be set to one of four intervals ranging
from 2.6 to 21.3 Jis. The refresh is timed to follow a read
or write operation to avoid interference.
0020H
is initiated by an unmasked interrupt request, an NMI,
or a RESET input. In the STOP mode, the CPU and
system clock are both stopped, reducing the power
consumption even further. The STOP mode is released
by an NMI input or a RESET input. .
Figure 10. Macro Service Control Word Map
OFEDFH
Channel Pointer
OFEDEH
Mode Register
OFEDDH
Channel Pointer
OFEDCH
Mode Register
OFEDBH
Channel Pointer
OFEDAH
Mode Register
OFED9H
Chamel Pointer
OFED8H
Mode Register
OFED7H
Channel Pointer
OFEDBH
Mode Register
OFED5H
Channel Pointer
OFED4H
Mode Register
INTSR
INTST
INTeSI
INTC10
INTCll
INTP4
Standby Modes
HALT and STOP functions reduce system power consumption. In HALT mode, the CPU stops and the system clock continues to run. A release of the HALT mode
17
•
NEe
pPD78224 Family
ELECTRICAL SPECIFICATIONS
Operating Conditions
Absolute Maximum Ratings
!xx =
VDD
Oscillation Frequency
TA = +25°C
4 to 12 MHz
Operating voltage, Voo
-0.5 to +7.0V
Input voltage, VI
-0.5 to Voo + 0.5 V
Capacitance
Output voltage, Vo
-0.5 to VOO + 0.5 V
TA = +25°C; VOO = Vss = ov
Low-level output current, 10l
per pin
total, all output pins
30 mA (peak), 15 mA (mean)
150 mA (peak), 100 mA (mean)
High-level output current, 10H
per pin
total, all output pins
-2mA
-50 mA
Operating temperature, TOPT
-40 to +85°C
Storage temperature, TSTG
-65 to +l50°C
-40 to +85°C
+5 V ±5%
-10to +70°C
+5 V ±10%
Item
Symbol
Max
Unit
Input capacitance
CI
20
pF
Output capacitance
Co
20
pF
Input/output
capaci tance
CIO
20
pF
Conditions
f = 1 MHz;
pins not
used for
measurement
are atOV
Exposure to absolute maximum ratings for extended p.eriods may
affect device reliability; exceeding the ratings could cause permanent damage. The device should be operated within the limits
specified under DC and AC characteristics.
DC Characteristics
TA = -40 to +85°C; voo = +5 V ±10%; VSS = 0 V
Conditions
Item
Symbol
Max
Unit
Low-level input voltage
Vil
o
0.8
V
Except PT pins
High-level input voltage
VIHI
2.2
VOO
V
Except PT pins and pins in Note 1
VIH2
0. 8VOO
VOO
V
Pins in Note 1
0.45
V
IOl = 2.0 mA
1.0
V
IOl = 8.0 mA (Port PI pins)
Low-level output voltage
Min
Typ
VOlt
VOl2
High-level output voltage
= -1.0 mA
VOHI
VOO-l.0
V
IOH
VOH2
VOO-0.5
V
10H = -100 JIA
Input leakage current
III
±10
JIA
VI=OtoVoo
Output leakage current
IlO
±10
JIA
Vo= OtoV oo
Pullup current
IIPT
-150
-400
JIA
VI
VOD power supply current
1001
16
40
mA
Operating mode,
1002
7
20
mA
HALT mode, fxX = 12 MHz
Data retention voltage
VOOOR
Data retention current
1000R
2.5
Notes:
(1) Xl, X2, RESET, P2oINMI, P21/INTPO, P22/INTP1, P2s[INTP2!CI,
P241'INTP3, P~NTP4, P2e1INTP5, P27/INTP6/SI, P32/SCK, P3a1
SO/S80, and EA pins.
18
= OV; PTpins
txx
= 12 MHz
STOP mode
5.5
V
2
20
JIA
STOP mode; VOOOR = 2.5 V
5
50
JIA
STOP mode; VOOOR = 5 V ±10%
NEe
"PD78224 Family
Read/Write Operation
= -40 to +85"C; VOO = +5 V ±10%; VSS =
TA
0 V; Ixx
=
12 MHz; CL
=
100 pF
Item
Symbol
Min
Max
Unit
Xl input clock cycle time
leYX
82
250
ns
Address setup time to ASTB ~
tSAST
52
ns
Address hold time from ASTB ~ (Note 2)
tHSTA
25
ns
Address to RD ~ delay time
tOAR
129
ns
Address float time from RD ~
tFAR
11
Address to data input time
tDAIO
228
ns
ASTB • to data input time
tOSTIO
181
ns
99
ns
ns
RD ~ to data input time
tORIO
ASTB I to RD I delay time
tOSTR
52
ns
t
tHRIO
0
ns
Data hold time from RD
RD
RD
t to address active time
t to ASTB t delay time
tORA
124
ns
10RST
124
ns
RO low-level width
twRL
124
ns
ASTB high-level width
twSTH
52
ns
129
Address to WR ~ delay time
tOAW
ASTB ~ to data output time
tOSTOO
WR ~ to data output time
towoo
ASTB ~ to WR ~ delay time
tOSTW1
52
t
Data setup time to WR
Data setup time to WR ~ (Note 1)
Data hold time from WR
WR
t (Note 2)
t to ASTB ! delay time
WR low-level width
WAIT setup time to X1
t
ns
•
ns
ns
146
ns
tSOOWF
22
ns
tHWOO
20
ns
tOWST
42
ns
twWL1
196
ns
twWL2
114
tOAWT
~
60
129
toSTWT
WAIT hold time from Xl
ns
tOSTW2
ASTB ~ to WAIT ~ input time
No wait states
ns
142
tSOOWR
Address to WAIT ~ input time
Conditions
ns
146
ns
84
ns
tHWTX
0
ns
t&NTX'
0
ns
Refresh mode
Refresh mode
Refresh mode
Notes:
(1) When accessing a pseudostatic RAM (pPD4168, etc.) that clocks
in data at the falling edge of WR, use !sOOWF instead of IsoOWR
as the data setup time.
(2) The hold time includes the time during which VOH and VOL are
retained under the following load conditions: CL = 100 pF and
RL = 2 kCl
19
I
NEe
JlPD78224 Family
Serial Port Operation
= -40 to +85°C; VOO = +5V
TA
2:10%; VSS
= OV; 'xx =
Item
Serial clock cycle time
Serial clock low-level width
12 MHz; Cl
Min
tCYSK
1.0
/.IS
External clock i'nput
1.3
/.Is
Internal clock/16 output
Internal clock/64 output
twSKl
Serial clock high-level width
= 100 pF
Symbol
twSKH
Max
Unit
Conditions
5.3
/.Is
420
ns
External clock input
556
ns
Internal clock/16 output
Internal clock/64 output
2.5
/.Is
420
ns
External clock input
556
ns
Internal clock/16 output
Internal clock/64 output
2.5
/.Is
SI, SBO setup time to SCK I
tSSSK
150
ns
SI, SBO hold time from SCK j
tHSSK
400
SO/SBO output delay time from SCK j
tOSBSKI
0
300
ns
CMOS push-pull output
(3-line serial 1/0 mode)
tOSBSK2
0
800
ns
Open-drain output
(SBI mode), Rl = 1 kO
SBO high, hold time from SCK t
tHSBSK
4
tcvx
SBI mode
SBO low, setup time to SCK j
tSSBSK
4
tcvx
SBI mode
SBO low-level width
twSBl
4
tcvx
seo high-level width
tWSBH
4
tcvx
RxD setup time to SCK t
tSRXSK
80
ns
tHSKAX
80
RxD hold time after SCK
t
SCK j to TxD delay time
Comparison accuracy
Comparison time
Sampling time
PT input voltage
ns
210
tOSKTX
Comparator Port Operation
Item
ns
Symbol
VACOMP
tCOMP
tsAMP
Min
Max
Unit
Conditions
100
mV
----------------100
mV
/.IPD78P224
128
256
62
o
tcvx
tcyx
VOO
V
ns
Interrupt Timing Operation
= -40 to +85°C; VOO = +5 V 2:10%; VSS =
TA
Item
Symbol
NMI low-level width
twNll
Min
Max
0V
Unit
10
/.Is
NMI high-level width
twNIH
10
/.Is
INTPO-INTP6 low-level
width
twrrl
24
tcyx
INTPO-INTP6 hlghlevel width
twrrH
24
tCYX
RESET low-level width
twASl
10
/.Is
RESET high-level
width
tWASH
10
/.Is
Conditions
Data Retention Characteristics
Item
Symbol
Min
Data retention voltage
VOOOA
2.5
Data retention current
IODOA
VOO rise time
VOOfalltlme
20
Max
Unit
Conditions
5.5
V
STOP mode
2
20
/.IA
VOODA = 2.5V
5
50
/.IA
VOOOA = 5 V 2:10%
Typ
tRVD
200
/.Is
tFVO
200
/.Is
NEe
pPD78224 Family
Data Retention Characteristics (cant)
Typ
Item
Symbol
VOO retention time
(from STOP mode
setting)
tHVO
0
ms
STOP release signal
input time
tOREL
0
ms
Oscillation
stabilization wait time
!wArT
30
ms
5
ms
Low-level input
voltage
VIL
High-level input
voltage
VIH
Min
0
0.9
VOOOR
Max
Unit
Conditions
Crystal resonator
Ceramic resonator
0.1
VOOOR
V
Specified pins
(Note)
VOOOR
V
Specified pins
(Note)
Note: RESET, P2oINMI, P21/INTPO, P22/INTP1, P2a/INTP2/CI, P2",
INTP3, P2s1INTP4, P2e1INTP5, P27/1NTP6/SI, P32/SCK, P3a/SO/
S80, and EA pins.
•
21
,
NEe
pPD78224 Family
Timing Dependent on tcyx
Item
Symbol
Xl input clock cycle time
tcvx
Address setup time to ASTB
~
Calculation Formula (1,2)
Min/Max
12 MHz
UnIt
Min
82
ns
tSAST
tcvx- 3O
Min
52
ns
tOAR
2tcvx- 35
Min
129
ns
tFAR
tcvx/2-30
Min
11
ns
Address to data input time
tDAIO
(4+2n)tcvx- 1OO
Max
228
ns
ASTB ~ to data input time
tOSTIO
(3+ 2n)tcvx - 65
Max
181
ns
RD ~ to data input time
tORIO
(2+2n)tcvx - 65
Max
99
ns
tOSTR
tcvx- 30
Min
52
ns
t to address active time
RD t to ASTB t delay time
tORA
2tcvx-4O
Min
124
ns
tORST
2tcvx- 4O
Min
124
ns
RD low-level width
twRL
(2+ 2n)tcvx - 40
Min
124
ns
ASTB high-level width
twSTH
tcvx- 3O
Min
52
ns
tDAW
2tCVX-35
Min
129
ns
ASTB ~ to data output time
tosToO
tcvx + 60
Max
142
ns
ASTB j to WR j delay time
tOSTW1
tcvx- 30
Min
52
ns
tOSTW2
2tCVX - 35 (refresh mode)
Min
129
ns
Data setup time to WR t
tSOOWR
(3+2n)tcvx - 100
Min
146
ns
~
IsOOWF
tcvx - 60 (refresh mode)
Min
22
ns
tOWST
tcvx -40
Min
42
ns
twWL1
(3+2n)tcvx - 50
Min
196
ns
twWL2
(2+2n)tcvx - 50 (refresh mode)
Min
114
ns
Address to WAIT j input time
tDAWT
3tcvx-1OO
Max
146
ns
ASTB j to WAIT ~ input time
tOSTWT
2tcvx-8O
Max
84
ns
Address to RD ~ delay time
Address float time from RD
ASTB
~
to RD
~
~
delay time
RD
Address to WR
~
delay time
Data setup time to WR
WR
t to ASTB t delay time
WR low-level width
Note:
(1) n indicates the number of internal wait states.
Recommended Oscillator Circuit
Cl1.
15~~
II
15~T
~
T
Recommended External Clock Circuit
Clock
Xl
HCMOS
Inverters
~PD7822x
X2
~PD7822x
X2
Crystal frequency fxx = 410 12 MHz
Clock frequency
83Rl>8:!68A
22
.::»-..---/ Xl
!xx =410 12 MHz
....D«!67A
NEe
IIPD78224 Family
External Clock Operation
TA = -40 to +85°C; VOO = +5 V :t10%; Vss = 0 v
Item
Symbol
Min
Max
X1 input low-level width
tWXL
30
130
ns
X1 input high-level width
twxH
30
130
ns
X1 input rise time
txR
0
30
ns
X1 input fall time
tXF
0
30
ns
82
250
ns
X1 input clock cycle time tcyx
Unit Conditions
Timing Waveforms
Voltage Thresholds for Timing Measurements
VOO-1
X
0.45 V
O.S Voo or 2.2 V
O.SV
x=
External Clock
X1
~l-608M
_-_-_-_IC_Y_X:~~~~~~~::_ _
L-_ _ _ _: : _-_-_-_-_-
..:83:::.Mt:::.:..::996A=.J •
Read Operation
X1
14------IDAIO
------...r
IHSTA
I+'-.~-+I
IFAR
14----+IOSTIO----~
ASlB
. - I OSTR
IORIO
...---IWRL----~
RO
83ML·6091B
23
NEe
,.,PD78224 Family
Write Operation
Xl
output Data
-+----i~--tSODWR---I
ASTB
1+-....-1+-+1 t SODWF
i - - - - t - - t WWL1
t WW12 -
tDSTW2--~
83Mt-6092B
External WAIT Input
Xl
I+----'!DAWT----.I
ASlB
WAIT
8SML-69938
24
NEe
pPD78224 Family
Clock-Synchronized Serial Interface; Three-Line I/O Mode
SCK
SI------<
OO ______
-J)(~_______~ ~_________J)(~______~)(~________
83A0-6368B
Clock-Synchronized Serial Interface; 581 Mode
Bus Release Signal Transfer Timing
SCK~----.JI
SBO
::
~
'woo<
:
_
\ _______1
\'---
•
)(~-===>C
_--'_ _ _ _ _ _ _ _--'
L
Command Signal Transfer Timing
seo
83RD-63648
25
NEe
pPD78224 FamHy
Asynchronous Mode
tCYSK
I---tWSKL- r-tWSKH-
II
\
\
)
TxO
I+--tOSKlX-
RxD
).
K
tSRXSK
tHSKRX
83ML-6989B
Interrupt Input
NMI
INTPGINTP6
Reset Input
26
NEe
pPD78224 Family
Data Retention Characteristics
Set STOP Mode
t
VDD
VDDDR
i----tWAIT ---~
tHVD
tRVD
tFVD
VDDDR
0.8 V
NMI
(Release by failIng
edge Input)
VDDDR
0.8V
NMI
(Release by rlslng
edge Input)
83ML......
27
NEe
pPD78224 Family
p.PD78P224 PROGRAMMING
Table 3. Pin Functions During PROM
Programming (conI)
In the JlPD78P224, the mask ROM of JlPD78224 is replaced by a one-time programmable ROM (OTP ROM).
The ROM is 16,384 x 8 bits and can be programmed
using a general-purpose PROM writer with a
JlPD27C256A programming mode.
Pln*
Function
P52/Al0'
PSalA14
Al0'
A14
Input pins for PROM write/verify
operations
P401ADo'
P47/AD7
Do'
07
Data pins for PROM operations
P6sfWR
CE
Strobes data into the PROM
P64fRD
OE
Enables a data read from the PROM
P20fNMI
NMI
PROM programming mode is
entered by applying a high voltage
to this pin
RESET
RESET
PROM programming mode requires
applying a low voltage to this pin
Table 3. Pin Functions During PROM
Programming
EA
Vpp
High voltage applied to this pin for
program write/verify
Pin
Function
Voo
Voo
Positive power supply pin
Input pins for PROM write/verify
operations
VSS
VSS
Ground
The PA-78P224GJ/L are the socket adaptors used for
configuring the JlPD78P224 to fit a standard PROM
socket.
Refer to tables 3 through 6 and the PROM timing
diagrams for special information applicable to PROM
programming.
POo' P07
Pin*
Ao·A7
P50IAs
As
Input pin for PROM write/verify
operations
P2 l /INTPO
A9
Input pin for PROM write/verify
operations
Pin
• Pin name in PROM programming mode.
Table 4. Summary of Operation Modes for PROM Programming
Mode
NMI
RESET
CE
OE
Vpp
VDD
00 - 07
Program write
+12.SV
L
L
H
+12.SV
+6V
Data input
Program verify
+12.SV
L
H
L
+12.SV
+6V
Data output
Program inhibit
+12.SV
L
H
H
+12.SV
+6V
High Z
Read out
+12.SV
L
L
L
+SV
+SV
Data output
Output disable
+12.SV
L
L
H
+5V
+SV
High Z
Standby
+12.SV
L
H
L/H
+5V
+SV
High Z
Note: When +12.S V is applied to Vpp and +6 V to Voo. both CE and
OE cannot be set to low level (Ll simultaneously.
28
NEe
IIPD78224 Family
DC Programming Characteristics
= 25 ±5"C; V,P = 12.5 ±0.5 V applied to NMI pin; Vss = 0 V
TA
Parameter
Symbol
Symbol·
Min
Max
Unit
High-level input voltage
V,H
V,H
2.4
Voop+0.3
V
Low-level input voltage
V,L
V,L
-0.3
0.8
V
10
J1A
Typ
Condition
Input leakage current
IUp
IU
High-level output voltage
VOH1
VOH1
2.4
V
IOH
VOH2
VOH2
VOO- 0.7
V
IOH
= -400J1A
= -100J1A
VOL
VOL
IOL
= 2.1
Low-level output voltage
0.45
V
ILO
10
J1A
NMI pin high-voltage input current
liP
±10
J1A
Voop power voltage
VOOP
Output leakage current
VPP power voltage
Vpp
VCC
Vpp
Vpp power current
Ipp
= V,H
6.0
6.25
V
Program memory write mode
4.5
5.0
5.5
V
Program memory read mode
12.2
12.5
12.8
V
Program memory write mode
V
Program memory read mode
Icc
100
mA
Os Vo s VOOP. OE
5.75
Vpp
Voop power current
Os V, s VOOP
Ipp
= VOOP
5
30
mA
Program memory write mode
5
30
mA
Program memory read mode
CE = V,L. V, = V,H
5
30
mA
Program memory write mode
CE = V,L. OE = V,H
100
J1A
Program memory read mode
* Corresponding symbols of the J1PD27C256A.
AC Programming Characteristics (Write Mode)
= 25 ±5"C; V,P = 12.5 ±0.5 V applied to NMI pin; Vss = 0 V;
TA
Parameter
Symbol
Address setup time to CE
Data input to OE
~
~
delay time
Input data setup time to CE
~
Address hold time from CE !
Input data hold time from CE
t
VOO
= 6 ±0.25 V; Vpp =
Symbol·
Min
tAs
toOOO
tOES
2
tSIDC
tos
2
J1s
tHCA
tAH
2
J1s
tOH
2
tOF
0
tsvPC
tvps
VOOP setup time to CE ~
tsvOC
!Ycs
Initial program pulse width
tWL1
tpw
0.95
Additional program pulse width
twL2
tOPW
2.85
Vpp setup time to CE
~
NMI high-voltage input setup time to CE
~
Unit
tSAC
tHCIO
t
Max
2
tHoOO
Output data hold time from OE
12.5 ±0.3V
Typ
J1s
J1s
130
ns
ms
ms
1.0
1.05
ms
7B.75
ms
2
tspc
J1s
J1s
Address to data output time
tOAOO
tACC
200
ns
CE I to data output time
tOCOO
tCE
200
ns
OE I to data output time
tOOOO
tOE
75
ns
tHcOO
tOF
0
60
ns
tHAOO
tOH
0
Data hold time from OE
t
Data hold time from address
Conditions
CE
=
OE
=
V,L
ns
* Corresponding symbols of the J1PD27C256A.
29
.-
NEe
pPD78224 Family
PROM Write Procedure
I
i,.
PROM Read Procedure
(1)
Connect the RESET pin to a low level, and apply
+12.5Vtothe NMI pin.
(1)
(2)
Apply + 6 V to the Voo pin and + 12.5 V to the Vpp
pin.
(2)
(3)
Provide the initial address.
(3)
(4)
Provide write data
Read mode is entered with a pulse (active low) on
both the CE and OE pins.
(5)
Provide 1-ms program pulse (active low) to the
CEpin.
(4)
Data is output to the Do to 0 7 Pins.
(6)
This data is now verified with a pulse (active low)
to the OE pin. If the data has been written,
proceed to step 8; if not, repeat steps 4 to 6. If the
data cannot be correctly written after 25 attempts, go to step 7.
(7)
Classify as defective and stop write operation.
(8)
Provide write data and supply program pulse (for
additional writing) for 3 ms times the number of
writes performed in steps 5.
(9)
(10)
30
Increment the address.
Repeat steps 4 to 9 until the end address.
Fixthe RESET pinto a low level, and apply +12.5 V
to the NMI pin.
Input the address of the data to be read to pins
Ao-A14'
NEe
pPD78224 Family
PROM Timing Diagrams
PROM Write Mode
~~~--------xR~ew~'--------~:~1
.1"
j--Wrlte
=>- r00-0 7
~
!sIOC .....
VIP
NMI
VIL
Vpp
Vpp
Voo
Voop
Voo
Voo
VIH
CE
VIL
Verlfy'-----f-oo->---AddIUonal wrlte-1
EffecUve Address
tSAC
Data
Input
~ -1
~
-1
Data
Output
f4- JIO
I
r--
f4- tHOOO
~ rtSIOC
Data
Input
~
K
tHCA
t.~
HI-Z
~
-
_tspc
~
-
f4- t svpc
-
f4- t svoc
~
I'--'
tWLl
~
jrL~toooo
,
f4-tw~
]
Notes:
(1) Voo must be applied before applying Vpp. It should be removed after removing V pp.
(2) Vpp must not exceed +13V, Including overshoot
fl3ML-6996B
31
NEe
"PD78224 Family
PROM Timing Diagrams
PROM Relld Mode
ElfacUYII Address
HI·Z
83ML-5997B (7/93)
32
NEe
NEe Electronics Inc.
pPD78238 Family
(fJPD78233/234/237/238/P238)
8-Bit, K-Series Microcontrollers With
A/D and D/A Converters, Real-Time Output Ports
June 1993
Description
The IlPD78233, IlPD78234, IlPD78237, IlPD78238, and
IlPD78P238 are members of the K-Series@ of microcontrollers and are designed for real-time embedded control applications. These 8-bit, single-chip microcontrollers have a minimum instruction time of 333 ns at 12
MHz (SOO ns for the IlPD78233/237). They feature 8-bit
hardware multiply and divide instructions, four banks
of main registers, an advanced interrupt handling facility, a powerful set of memory mapped on-chip peripherals, and the ability to address up to 1M bytes of
external data memory. On board memory includes 640
or 1024 bytes of RAM, 16K or 32K bytes of mask ROM, or
32K bytes of UV EPROM or one-time programmable
(OTP) ROM.
The advanced interrupt handling facility provides two
levels of programmable hardware priority control and
two separate methods of servicing interrupt requests:
vectored and macro service. The macro service facility
reduces the overhead involved in servicing peripheral
interrupts by transferring data between the memorymapped special function registers (SFRs) and memory
without the use of time consuming interrupt service
routines. In addition, the macro service facility can be
initialized to automatically alter timer compare register values or to repeatedly output a prespecified pattern at a fixed or variable rate. By using macro service
to control the real-time output ports, the IlPD78238
family can easily and accurately drive two independent
stepper motors.
The combination of the macro service facility, four
banks of main registers, extended data memory address space, and powerful on-Chip peripherals makes
these devices ideal for applications in office automation, communication, HVAC, and industrial control.
Features
o Complete single-chip microcontroller
-8-bit ALU
- Program memory (ROM)
IlPD78233/237: ROM less
IlPD78234: 16K bytes
pPD78238/P238: 32K bytes
- Data memory (RAM)
pPD78233/234: 640 bytes
pPD78237/238/P238: 1024 bytes
K-series is a registered trademark of NEe Electronics. Inc.
50601
o Powerful instruction set
- 8-bit unsigned multiply and divide
-16-bit arithmetic instructions
-i-bit and 8-bit logic instructions
o Minimum instruction time
-333 ns at 12 MHz (J.lPD78234/238/P238)
-500 ns at 12 MHz (J.lPD78233/237)
o Memory expansion
- 8085 bus-compatible
- 64K program address space
- 1M data address space
o Large I/O capacity
- Up to 64 I/O port lines on pPD78234/238/P238
- Up to 46 I/O port lines on pPD78233/237
-Software programmable pullup resistors
o Memory-mapped on-Chip peripherals (special
function registers)
o Timer/counter unit
-16-bit timer 0:
Two 16-bit compare registers
One 16-bit capture register
One external interrupt/capture line
- 8-bit timer 1:
One 8-bit compare register
One 8-bit capture/compare register
One external interrupt/capture line
- 8-bit timer/counter 2:
Two 8-bit compare registers
One 8-bit capture register
One external interrupt/capture line
One external event counter line
- 8-bit timer 3:
One 8-bit compare register
o Pulse-width modulated (PWM) outputs
- Two 12-bit precision hardware controlled
- Four 8-bit precision timer controlled
o Two 4-bit (or one 8-bit) real-time output ports
o Eight-channel 8-bit A/D converter
o Two-channel 8-bit D/A converter
o Programmable priority interrupt controller (two
levels)
o Two methods of interrupt service
- Vectored interrupts
- Macro service mode with choice of three
different types
•
!
NEe
,.,PD78238 Family
Features (cont)
Cl
Two-channel serial communication interface
- Asynchronous serial interface (UAR1)
Dedicated baud rate generator
- Clock-synchronized interface
Full-duplex, three-wire mode
NEC serial bus interface (SBI) mode
Cl
Refresh output for pseudostatic RAM
Cl
STOP and HALT standby functions
Cl
5-volt CMOS technology
Ordering Information
Part Number
ROM
Package
Package Drawing
pPD78233GC
ROMless
80-pin plastic QFP
S80GC-65-3B9-1
pPD78234GC-xxx
16K mask ROM
94-pin plastic QFP
S94GJ-80:5BG-1
84-pin PLCC
P84L-50A3-1
94-pin ceramic LCC with window
X94KW-80A
pPD78237GC
ROM less
pPD78238GC-xxx
32K mask ROM
pPD78P238GC
32KOTP ROM
pPD78233GJ
ROM less
pPD78234GJ-xxx
16K mask ROM
pPD78237GJ
ROM less
pPD78238GJ-xxx
32K mask ROM
pPD78P238GJ
32KOTP ROM
pPD78233LQ
ROM less
pPD78234LQ-xxx
16K mask ROM
pPD78237LQ
ROMless
pPD78238LQ-xxx
32Kmask ROM
pPD78P238LQ
32KOTP ROM
pPD78P238KF
32KlN EPROM
Note:
2
xXx indicates ROM code suffix.
:!
~
"'0
5'
S' oo
::J
~ (5
aa
C
I)'
~
~Il!;g;g;g;g;g;l!;g~ x
O.::rQ)UI~""N""OC/)"""
=::4
PesJWAIT
0)
0'
~
'1:i ::J
;s
'11 "'U "'tI
zm
n
til
'11~ CS
0: !lll~ ~ ~ ~ m ~I
~o!!1G>IG-g~"
eft
~lTxD
P30fRxD
P6sJWR
P¥lD
P27 /s1
P2anNTPS
P2snNTP4IASCK
P24nNTP3
P6alA19
PB:!/A18
P&j/A17
PBofA16
P5]/A1S
,,¥NTP2/C1
PSafA14
P5sfA13
P21nNTPO
P54IA12
P5alAll
AVREF3
~NTP1
P20fNMI
AVREF2
ANOl
P~Al0
PS1/Ag
ANOO
pSoIAa
AVSS
P47/AD-,
P44IAD4
AVREF1
AVDD
P77/AN17
P7S/ANI6
P4alAD3
P7s'ANI5
P4alAD6
P4sfADS
"~~~
" " ~ &lO~-:~~~~~~O~~~~~
< ;: " " " " " " " " < " " ." ." ."
~~~
0
~
o~~·~~~
m::E
000
1\)
....
3:3:
0
0-
ZZZZZ
S~i\5C3:E
1:
".....c
~
w
Q)
-:
III
c.J
~.
i
'<
I
NEe
pPD78238 Family
Pin Configurations (cant)
84-Pln PLCC (plastic Leaded Chip Carrier)
P74fANI4
P7sfANIS
P7afANI8
P17/ANrT
74
P4tAD2
73
P4a/AD3
72
P44AD4
71
P4sfAD5
AVDD
70
P4e'AD6
AVREFl
69
P~/AD7
AVss
P5a1AB
P5a/All
P21nNTPO
68
67
68
65
64
63
62
P22'1NTPl
61
P57/A15
P2aflNTP2ICI
P24/INTP3
P2&'INTP4IASCK
P2&'INTP5
I'27/SI
60
59
P6a1A16
P61/A17
ANOO
ANOl
AVREF2
AVREF3
P2o'NMI
P54fA12
P5sfA13
P5s1A14
58
P62fA18
57
P6a/A19
58
P64fRo
P30IAxD
55
P6s'WR
P311TxD
54
P6&'WA1T
~~~~~~~~~~~~~~~~~~~~~
4
P51/A9
P52fAl0
NEe
pPD78238 Family
Pin Configurations (cont)
94-Pin Plastic QFP and Ceramic LCC with Window
71
P73/AN13
P¥CK
70
NC
PSa/SOISBO
P3ifOO
P3e'TOl
P3gro2
P3iT0 3
69
P72fANI2
P71/ANll
P701ANIO
68
67
66
65
64
03
62
61
60
59
58
57
RESET
Voo
X2
Xl
VSS
VSS
Voo
Voo
P17
P16
P15
P14
NC
POl
56
P13
P12
PlllPWMl
PlofPWMO
P02
P03
55
54
MOOE
P04
53
NC
POs
POO
52
51
50
49
NC
POo
NC
1'0]
I'67/REFRQ
~
~
..
I
NC
VSS
Vss
ASlB
o
P401AD
P41/AOl
~~re~re~g~~~~~~~~~i~~~;~~~
83RD-64268
5
NEe
PPD78238 Family
Pin Functions; Normal Operating Mode
Symbol
Firat Function
Symbol
Second Function
PWMO
PWMI
Pulse-width modulated outputs
Port 0; S-bit tristate output port/real time output port
Port 1; S-bit, bit-selectable tristate input/output port
Port 2; S-bit input port
P23
P2s
P26
P30
Port 3; S-bit, bit-selectable tristate input/output port
P33
P40- P4r
Port 4; S-bit tristate input/output port
P50- P5r
Port 5; S-blt, bit-selectable tristate input/output port
NMI
External nonmaskable interrupt
INTPO
INTP1
Maskable external interrupts
INTP2
CI
Maskable external interrupt
External clock input to timer/counter 2
INTP3
Maskable external interrupt
INTP4
ASCK
Maskable external interrupt
Asynchronous serial clock input
INTP5
Maskable external interrupt
SI
Serial data input for three-wire serial I/O mode
RxD
Asynchronous serial receive data input
TxD
Asynchronous serial transmit data input
SCK
Serial shift clock input/output
SO
SBO
Serial data output for three-wire serial I/O mode
I/O bus for NEC serial bus interface (SBI)
TOO- TOO
Timers TO to T3 outputs
ADO- AOr
Port 6; 4-bit output port
Port 6; 4-blt, bit-selectable tristate input/output port
P70 - P77
Port 7; S-blt Input port
ANOO,AN01
Analog voltage output from D/A converter
ASTB
Address strobe output used to latch the
low-order S address for external memory
RESET
External system reset input
MODE
Internal ROM or external memory control signal input. A
low-level Input selects internal ROM. A high-level input
selects external memory. The pPD78234/23B can be used
in ROMless mode by setting the MODE pin high.
However, the pPD78P238 cannot be used in ROMless
mode and Its MODE pin must only be set low.
XI
CrystaVceramic resonator connection or
external clock input
X2
CrystaVceramlc resonator connection or
Inverse of external clock
ND
6
converter reference voltage
Low-order B-bit multiplexed address/data bus
High-order B-blt address bus
Extended memory address bus
RD
External memory read strobe
WR
External memory write strobe
WAIT
External memory wait signal input
REFRQ
Refresh pulse output used by external
pseudostatic memory
ANIO - ANI7
Analog voltage Input to
ND
converter
NEe
IIPD78238 Family
Pin Functions; Normal Operating Mode (cont)
Symbol
First Function
Symbol
Second Function
DIA converter reference voltages
AVoo
AID converter power supply
AVss
AID converter ground
Voo
+5 volt power supply input
Vss
Power supply ground
NC
No connection
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The I1PD78238 family CPU features 8- and 16-bit arithmetic including an 8 x 8-bit unsigned multiply and 16 x
8-bit unsigned divide (producing a 16-bit quotient and
an 8-bit remainder). The multiply executes in 3.67 I1s
and the divide in 12.3611S at 12 MHz (4.00 and 12.6911s
respectively for I1PD78233/237).
A CALLT vector table and a CALLF program area
decrease the number of bytes in the call instructions
for commonly used subroutines. A 1-byte call instruction (CALLT) can access up to 32 subroutines through
the addresses contained in the CALLT vector table. A
2-byte call instruction (CALLF) can access any routine
beginning at a specific address in the CALLF area.
The internal system clock (fcu<> is generated by dividing the oscillator frequency by two. Therefore, at the
maximum oscillator frequency of 12 MHz, the internal
system clock is 6 MHz. The minimum instruction execution time for an instruction fetched from internal
ROM is 333 ns (500 ns when fetched from external
memory).
Memory Space
The I1PD78238 family has a 1M byte address space (see
figure 1). The first 64K bytes of this address space
(OOOOOH-OFFFFH) can be used as both program and
data memory. The remaining 960K bytes of this address _ _
space (10000H-FFFFFH) can only be used as data
~
,
memory and is known as expanded memory.
'
,
7
NEe
pPD78238 Family
Block Diagram
Bus Control
PSO/A1S"
SFR AddressIData Bus
P53 /A 19
P20INMI
P50/AS"
P57/A1S
P21I1NTPO"
P2SIINTP5
P30lRxD
P31 fTxD -",,-=-=::"::":':""'--1(
P2sIlNTP4I _
_r----...,
ASCK
L-==:::""....I
P32ISCK
~- ..- - - - - - .
faa ISCVSBO
INTP33
P3s fT01
Intemal Program
Memory
--
P271S1~~
P3.! (TOO
P40/AOO"
P47/A07
_____~
TlmsrO
P54/RD
OK Bytss : I,PD762331237
16K Bytes: I,PD78234
32K Bytes: "PD762381P238
P
P5sIWR
P56 IWAIT
(16 Bits)
' -_____~
ASTB
INTPO
Temporary
Registers
System Control
X1
~ :SET
~
L:::J
MODE
Internal RAM
- - VDO
General
Registers
- - VSS
Macro Service
Control Words
(256 Bytss)
PWMO
PWM1
Pe~pheral
RAM
384 Bytes:
"PD782331234
768 Bytes:
"PD78237f2381P238
I
Data Bus
Port
I
8BBBBBBBB
83YL"'29B
8
NEe
pPD78238 Family
Figure 1. Memory Map
OOOOOH
OOOOOH
On-Chlp
Program Memory
16Kbyles:
"PD78234
32Kbyles:
"PD782381P238
Inmrrupt Vector
Address Table Area
0003FH
OOO4OH
CALLT Table Area
:
0007FH
1---------1
007FFH
1-_ _ _ _ _-1
OOO8OH
Program Area
OOSOOH
(Must be extemal
memory
In "P078233(237)
IJ
CAlLFEntry
IT
I---------l~ ~:~ 1---------1
Notal
~
Extemal Memory ~
Area
Program Area
~~N=o=m~I~________..J
Nom 2
Nom 2
OnoChlp RAM
and
Register Area
OFE20H
Genera/ RAM
OFEC1H
---- -- -OFEC2H
Macro Service
OFEDFH
Control Words
OFEEOH - - - - - - - -
Inmmal RAM
Exmmal
Memory
1
I
OFDFFH{ - - - - - - - Genera/Storage
- - - - - - - Registers
OFFFOH - - - - - - - -
OFFFFH
l0000H
FFFFFH
peRAM~pheral
saddr Addressing
(Expanded
Address
Area)
1
Special Functfon
Register Area
OFFFFH
~
General Reglsmrs
OFEFFH _ _ _ _ _ _ _ _
OFFOOH
32 Bytes of SFR Area
-.:O::F.:..F.:.:1F.:..:H~__________..J
-
Not..:
(1) 03FFFH on "PD78234
07FFFH on "PD782381P238
(2) OFCSOH on "PD782331234
OFBOOH on "PD782381P238
83Yl-92048
External Memory
Expanded Data Memory
The J,lPD78238 family has an 8-bit wide external data
bus and a 16-bit wide external address bus (20-bit wide
if expanded memory is enabled). The low-order 8 bits
of the address bus are multiplexed to provide the 8-bit
data bus and are supplied by I/O port 4. The high-order
address bits of the 16-bit address bus are taken from
port 5. If expanded memory is enabled, the expanded
address nibble is provided by P60 to P63. Address latch,
read, and write strobes are also provided.
The MM register is also used to enable the external
expanded data memory space, addresses 10000H to
FF FF FH. When the expanded data memory is enabled,
the entire 1M byte address space is divided into 16
banks of 64K bytes each. The low-order 4-bits of the P6
or the PM6 registers are used as bank selection registers to supply the address information to A16 to A19.
Data can easily be transferred from one memory bank
to another by using the appropriate instructions. Address lines A16 to A19 are only active when an instruction that uses expanded addressing is being executed.
A programmable wait control register (PW) allows the
programmer to specify up to two additional wait states
or the use of the WAIT input pin for expanded data
memory space.
The memory expansion mode register (MM) is used to
enable external memory, to specify up to two additional wait states or the use ofthe WAIT input pin for the
first 64K bytes of memory, and to enable the high-speed
internal ROM fetch. Ports 4, 5, and 6 are available as
general purpose I/O ports when only internal ROM is
used and no external program or data space is required.
9
NEe
pPD78238 Family
On-Chip RAM
The pPD78237/238 have a total of 1024 bytes of on-chip
RAM (640 bytes in the pPD78233/234).
The pPD78P238 also contains 1024 bytes of on-chip
RAM. By using the memory size select (IMS) register,
the pPD78P238 can be programmed to emulate either a
pPD78234 device with 640 bytes of on-chip RAM or a
pPD78238 with 1024 bytes. The programming of this
register is transparent to the ROM-based device, allowing easy transfer of code to a ROM-based device.
The upper 256-byte area (FEOOH-FEFFH) features highspeed access and is known as "Internal RAM." The
remainder (FBOOH-FDFFH and FC80H-FDFFH in the
pPD78233/234) is accessed at the same speed as external memory and is known as "Peripheral RAM." The
general register banks and the macro service control
words are stored in Internal RAM. The remainder of
Internal RAM and any unused register bank locations
are available for general storage.
On-Chip Program Memory
The pPD78234/238 contain 16K and 32K bytes of internal ROM respectively. The pPD78P238 contains 32K
bytes of UV EPROM or one-time programmable ROM.
By using the IMS register, the pPD78P238 can be
programmed to emulate a pPD78234 device with 16K
bytes of internal PROM or a pPD78238 with 32K bytes.
This programming is transparent to the ROM-based
device, allowing easy transfer of code to a ROM-based
device. Instructions from on-Chip program memory can
be fetched at high speed or at the same rate as from
external memory. The pPD78233 and the pPD78237 do
not have on-Chip program memory.
CPU Control Registers
Program Counter. The program counter is a 16-bit
binary counter register that holds the address of the
next instruction to be executed. During reset, the
program counter is loaded with the address stored in
locations OOOOH and 0001H.
Stack Pointer. The stack pointer is a 16-bit register
that holds the address of the last item pushed onto the
stack. It is decremented before new data is pushed
onto the stack and incremented after data is popped
off the stack.
Program Status Word. The program status word
(PSW) is an 8-bit register that contains flags that are
set or reset depending on the results of an instruction.
10
This register can be written to or read from 8 bits at a
time. The individual flags can also be manipulated on a
bit-by-bit basis. The assignment of PSW bits follows.
o
7
IE
z
CY
ISP
RBSO, RBS1
AC
Z
IE
I RBSl I
AC
I RBSO I
0
ISP
CY
Carry flag
Interrupt priority status flag
Register bank selection flags
Auxiliary carry flag
Zero flag
Interrupt request enable flag
General Registers
The general-purpose registers (figure 2) consist of four
banks of registers located at addresses FEEOH to
FEFFH in Internal RAM. Each bank consists of eight
8-bit general registers that can also be used in pairs to
function as four 16-bit registers. Two bits in the PSW
(RBSO and RBS1) specify which of the register banks is
active. The bits are set under program control. Registers have both functional names (like A, X, B, C for 8-bit
registers and AX, BC for 16-bit registers) and absolute
names (like R1, RO, R3, R2 for- 8-bit registers and RPO,
RP1 for 16-bit registers). Each instruction determines
whether a register is referred to by its functional or
absolute name and whether it is 8 or 16 bits.
Addressing
The pPD78238 family features 1-byte addressing of
both the special function registers and the portion of
on-Chip RAM from FE20H to FEFFH. The 1-byte sfr
addressing accesses the entire SFR area, while the
1-byte saddr addressing accesses the first 32 bytes of
the SFR area and 224 bytes of internal RAM. Sixteen-bit
SFRs and words of memory in these areas can be
addressed by 1-byte saddrp addressing, which is valid
for even addresses only. Since many instructions use
1-byte addressing, access to these locations is almost
as fast and versatile as access to the general registers.
There are seven addressing modes for data in main
memory: direct, register, register indirect with autoincrement and decrement, saddr, SFR, based, and indexed. There are also both 8-bit and 16-bit immediate
operands.
NEe
pPD78238 Family
Figure 2. General Registers
OFEEOH Register
Bank
3
Fora-BII
Processing
2
I
OFEFFH
0
,
For1S-Bft
Processing
(R1)A
(RO) X OFEF8H -
(RPO)PJ<
OFEF8H
(R3)B
(R2)C
(RP1) BC
OFEFAH
(R5)D
(R4)E
(RP2) DE
OFEFCH
(R7)H
(RS)L
(RP3) HL
OFEFEH
) = Absolute Name
83YL-817OB
Special Function Registers
The input/output ports, timers, capture and compare
registers, and mode and control registers for both the
peripherals and the CPU are collectively known as
special function registers. They are all memory·
mapped between FFOOH and FFFFH and can be ac-
cessed either by main memory addressing or by 1-byte
sfr addressing. They are either 8 or 16 bits as required,
and many of the 8-bit registers are capable of single-bit
access as well. Locations FFDOH through FFDFH are
known as the external SFR area Registers in external
circuitry interfaced and mapped to these addresses
can be addressed with SFR addressing. Table 1 is a list
of the special function registers.
..
I
I
11
NEe
pPD78238 Family
Table 1. Special Function Registers
Access Units (Bits)
Address
Register (SFR)
Symbol
R/W
1
8
OFFOOH
PortO
PO
R/V'I
Port 1
Pl
R/W
OFF02H
Port 2
P2
R
OFF03H
Port 3
P3
R/W
OFF04H
Port 4
P4
R/W
OFF05H
Port 5
P5
R/W
OFFOSH
PortS
PS
R/W
OFF07H
Port 7
P7
R
x
x
x
x
x
x
x
x
x
Undefined
OFF01H
x
x
x
x
x
x
x
16
OFFOAH
Port 0 buffer register (low)
POL
R/W
x
x
Undefined
OFFOBH
Port 0 buffer register (high)
POH
R/W
x
Undefined
OFFOCH
Real·time output port control register
RTPC
R/W
x
x
OFF10H-OFFllH
lS-bit compare register 0 (lS-bit timer 0)
CROO
R/W
OFF12H-OFF13H
lS-bit compare register (lS-blt timer 0)
CROl
R/V'I
OFF14H
B-bit compare register (B-bit timer 1)
CR10
R/W
State After Reset
Undefined
Undefined
Undefined
Undefined
Undefined
xOH
Undefined
x
OOH
x
x
Undefined
Undefined
Undefined
x
OFF15H
B-bit compare register (B-bit timer/counter 2)
CR20
R/W
x
Undefined
OFF1SH
B-bit compare register (B-bit timer/counter 2)
CR21
R/V'I
Undefined
OFF17H
B-bit compare register (B-bit timer 3)
CR30
R/W
x
x
OFF1BH-OFF19H
lS-blt capture register (lS-bit timer 0)
CR02
R
OFF1AH
B-bit capture register (B-bit timer/counter 2)
CR22
R
OFF1CH
B-bit capture/compare register (B-bit timer 1)
CRll
R/V'I
OFF20H
Port 0 mode register
PMO
W
OFF21H
Port 1 mode register
PMl
OFF23H
Port 3 mode register
PM3
OFF25H
Port 5 mode register
PM5
W
OFF2SH
Port S mode register
PMS
R/V'I
OFF30H
Capture/compare control register 0
CRCO
W
OFF31H
Timer output control register
TOC
W
OFF32H
Capture/compare control register 1
CRCl
W
OFF34H
Capture/compare control register 2
CRC2
W
OFF40H
Pullup resistor option register
PUO
R/W
x
OFF43H
Port 3 mode control register
PMC3
R/W
x
OFF50H-OFF51 H
lS-bit timer register 0
TMO
OFF52H
B-bit timer register 1
TMl
R
OFF54H
B-bit timer register 2
TM2
R
OFF5SH
B-bit timer register 3
TM3
R
OFF5CH
Prescaler mode register 0
PRMO
W
OFF5DH
Timer control register 0
TMCO
OFF5EH
Prescaler mode register 1
OFF5FH
OFFSOH
12
Undefined
x
Undefined
Undefined
W
x
x
x
x
W
x
FFH
x
x
x
x
x
x
x
x
FFH
x
Undefined
FFH
FFH
FxH
10H
OOH
OOH
OOH
OOH
OOH
x
R
OOOOH
OOH
R/W
x
x
x
x
x
PRMl
W
x
OOH
Timer control register 1
TMCl
R/W
x
OOH
D/A converter value setting register 0
DACSO
R/V'I
x
OOH
OOH
OOH
OOH
OOH
NEe
pPD78238 Family
Table 1. Special Function Registers (cont)
Access Units (Bits)
Address
Register (SFR)
Symbol
R/W
8
OFF61H
DIA converter value setting register 1
DACSl
R{W
x
OFF68H
NO
ADM
R/W
OFF6AH
AID conversion result register
ADCR
OFF70H
PWM control register
OFF72H-OFF73H
PWM modulo register 0
converter mode register
x
16
State After Reset
OOH
x
OOH
R
x
Undefined
PWMC
R{W
x
PWMO
W
05H
x
Undefined
x
Undefined
OFF74H-OFF75H
PWM modulo register 1
PWMl
W
OFF7DH
One-shot pulse output control register
OSPC
R{W
x
x
OOH
OFFBOH
Clocked serial Interface mode register
CSIM
R{W
x
x
OOH
OFF82H
Serial bus interface control register
SBIC
R/W
x
x
OOH
OFF86H
Serial shift register
SID
R{W
x
Undefined
OFF88H
Asynchronous serial interface mode register
ASIM
R/W
x
x
80H
OFF8AH
Asynchronous serial interface status
register
ASIS
R
x
x
OOH
OFF8CH
Serial receive buffer: UART
RxB
R
x
Undefined
OFF8EH
Serial transmit shift register: UART
TxS
W
x
Undefined
OFF90H
Baud rate generator control register
BRGC
W
x
OOH
OFFCOH
Standby control register
STBC
R/W
x
OOOOxOOOB
OFFC4H
Memory expansion mode register
MM
R{W
x
x
20H
OFFC5H
Programmable wait control register
PW
R{W
x
x
80H
x
x
OOH
x
Undefined
OFFC6H
Refresh mode register
RFM
R{W
OFFCFH
Memory size select register
IMS
W
OFFOOH-OFFDFH
External SFR area
R{W
x
x
Undefined
OFFEOH
Interrupt request flag register L
IFOL
R{W
x
x
OOH
OFFE1H
Interrupt request flag register H
IFOH
R{W
x
x
OFFEOH-OFFEl H
Interrupt request flag register H
IFO
R{W
OFFE4H
Interrupt mask flag register L
MKOL
R{W
x
x
FFH
OFFE5H
Interrupt mask flag register H
MKOH
R/W
x
x
FFH
OFFE4H-OFFE5H
Interrupt mask flag register H
MKOH
R/W
OFFE8H
Priority specification flag register L
PROL
R{W
x
x
OFFE9H
Priori ty specification flag regl ster H
PROH
R/W
x
x
OFFE8H-OFFE9H
Priority specification flag regi ster H
IFO
R/W
OFFECH
Interrupt service mode specification flag
register L
IS MOL
R/W
x
x
OOH
OFFEDH
Interrupt service mode specification flag
register H
ISMOH
R/W
x
x
OOH
OFFECH-OFFEDH
Interrupt service mode specification flag
register
ISMO
R/W
OFFF4H
External interrupt mode register a
INTMO
R/W
x
x
OOH
OFFF5H
External interrupt mode register 1
INTMl
R{W
x
x
OOH
OFFF8H
Interrupt status register
1ST
R/W
x
x
OOH
-
OOH
x
x
OOOOH
FFFH
FFH
FFH
x
x
FFFH
OOH
13
NEe
pPD78238 Family
Figure 3. Pin I/O Circuits
Type 1 (MODE)
~II-_ _«../II-_ _ _ pullup
"'"
enable
IN 0---<>---[11 " ) > 0 - - - - - _
IN
Schmitt trigger Input with hysteresis characteristic.
---[90------c)o~
0-0
Schmitt t~gger Input with hystaresls charectarisUC.
Voo
pUliup enable -------11>><>-----1
data~
outputdlsable~
Push-puD output whe" the output can be plaosd In
(both P and N channels are turned 011).
hlgh~mpedance
t--...,...~--<>
INfOUT
TypeN(P32)
Input enable - - - - - - - - - - '
!::-------II>~---I
Type9(P7)
...L
......---<> INfOUT
IN o--t----i~
~
VREF (Threshold Voltage)
1..-_ _ _ _ _ _ _ _
Type 12 (ANOO end ANOt)
pullup enable
--------11>><>-----1
Analog
p..L
voltage
NT
output~OUT
. . . _-_<>
~
14
INfOUT
Input
enable
NEe
fJPD78238 Family
Input/Output Ports
There are up to 64 port Ii nes on the pPD78234/238/P238
and up to 46 port lines on the pPD78233/37. (Ports 4, 5,
and two bits of port 6 are not available on the
pPD78233/237 since the pPD78233/237 must always
use external memory.) Table 2 lists the features of each
port and figure 3 shows the structure of each port pin.
The pin levels of all port 2,3, and 7 pins can always be
read or tested regardless of the dual pin function.
Table 2. Digital Port Functions
Port
Operational Features
Configuration
Direct Drive
Capability
Software Pull up
Resistor Connection
Porta
a-bit high impedance output
Port 1
a-bit input or output
Port 2
a-bit Schmitt trigger input
Port 3
a-bit input or output
Bi t selectab Ie
Port 4
a-bit input or output
Byte selectable
LED
Byte selectable
Port 5
a-bit input or output
Byte selectable
LED
Byte selectable, input bits only
Port 6
4-bit output (bits a to 3)
4-bit input or output (bits 4 to 7)
Bit selectable
Port 7
a-bit input
Transistor
Bit selectable
LED
Byte selectable, input bits only
In 6-bit unit (P22-P27)
Byte selectable, input bits only
In 4-bit unit, input bits only
Note:
(1) Software pullup resistors can be internally connected only on a
port-by-port bits to port bits set to input mode. Pullup resistors
are not connected to port bits set to output mode.
--
Real-time Output Port
The real-time output port (RTPC) shares pins with port
O. It can be used as two independent 4-bit real-time
output ports or one 8-bit real-time output port. In the
real-time output mode, data stored beforehand in the
buffer registers, POH and POL, is trallsferred immediately to the output latch of PO on the occurrence of a
timer 1 interrupt (INTC10 or INTC11) or external interrupt (INTPO) (see figure 4). By using the real-time
output port with the macro service function, port 0 can
be used to output preprogrammed patterns at preprogrammed variable time intervals. In this mode, two
independent stepper motors can accurately be driven
at a fixed or variable rate.
15
NEe
pPD78238 Family
Figure 4. Real-tIme Output Port
Intema! Bus
RTPC
Buffer Register
POH
4·Blt
Real-lime
Output (POH)
INTPO
1NT10
INTC11
Oulput
Trigger
Control
Circuit
4-Blt Reel-TIme
output (POL
I
I
POL
8
4
4
8-BIt Reel-l1me
PO)
83YL-91 ...
16
NEe
IIPD78238 Family
Analog-to-Digital (AID) Converter
The IIPD78238 family AID converter (see figure 5) uses
the successive-approximation method for converting
up to eight multiplexed analog inputs into a-bit digital
data The conversion time per input is 30 lis at 12 MHz
operation. AID conversion can be started by an external interrupt, INTP5, or under software control.
The AID converter can operate in either scan mode or
select mode. In scan mode, from one to eight sequential inputs can be programmed for conversion. The AID
converter selects each input in order, converts the
data, stores it in the AID conversion result (ADCR)
register, and generates an interrupt (INTAD). This converted data can be easily transferred to memory by
using the macro service function.
In select mode, only one of the eight AID inputs can be
selected for conversion. The ADCRregister is continually updated and can be read at any time. If the AID
converter is started by an external interrupt, an INTAD
interrupt occurs at the completion of each conversion.
If the AID converter is started by software, no interrupts are generated.
Figure 5. AID Converter
Register String
r--I-----~
ANI2
ANI3
ANI4
ANI5
ANIS
1
1
I
I
Hold ClrcuR
I
I
,----1
r - - - - - - i Tap
1 T:
rh
1
1
REF1
B'2 f T A
1 V
I
I
R
I
::
(----i-o
1
1_ _ _ _ - '
ANI7
I------~~
~
I
I
1
I
I Selec!or I
I:
I
I
I
1
I
I
I
I
1
I
I
I
I
1
I
I
I
I
.
I
B'2
I
I
I
I
I
LL
I
I
I
!.. __ J _____ .J
INTAD
T~gger
1
Sample and
ANIO
ANll
1
Selec!or
I-
AVSS
Interrupt Request
8
Enable
Intemaleus
83YL......
17
NEe
pPD78238 Family
Digital-to-Analog (D/A) Converter
Hardware Pulse-Width Modulated Outputs
The ~PD78238 family has two D/A converters as shown
in figure 6. The 8-bit digital data, written to the DACSn
register (n= 0, 1), selects one of the 256 taps on a
resistor ladder between AVREF2 and AVAEF3' The selected voltage becomes the analog output at the ANOn
pin. The ANOn is a high-impedance output and requires
an external buffer to drive a low-impedance load.
The pPD78238 family has two 12-bit resolution pulsewidth modulated (PWM) outputs (see figure 7) with a
repetition rate of 23.4 kHz at 12 MHz (felK = 6 MHz).
The polarity of each output can be selected under
program control. The two PWM outputs, PWMO and
PWM1, share pins with port 1, bits a and 1 respectively.
These outputs are designed for controlling DC motors.
Figure 6. D/A Converter
Figure 7. Hardware Pulse:-Width Modulator
1-----1--,
AVREF2
G - - -.......- , - - - - ,
R
1
I
I
1
Internal Bus
1
1
R
1
I
I
s!:'ctIL--o ANOn
I
1
1
R
1
1
1
R
1
1
1
4-Bft Counter
Note: n=0,1
83R1J.8427A
Note: n=O,1
18
NEe
"PD78238 Family
Serial Interface
The JlPD78238/P238 have two independent serial interfaces. The first is a standard UART. The UART (figure 8)
permits full-duplex operation and can be programmed
for 7- or 8-bits of data after the start bit, followed by one
or two stop bits. Odd, even, zero or no parity can also
be selected. The serial clock for the UART can be
provided by an on-chip baud rate generator or timer 3.
By using either the internal system clock or an external
clock input into the ASCK pin, the baud rate generator
is capable of generating all of the commonly used
baud rates. The UART generates three interrupts: INTST (transmission complete), INTSR (reception complete), and INTSER (reception error).
Figure B.
Asynchronous Serial Interface
Internal Bus
~--------~--------~-----.
Baud Rate Generalor
1- - - - - -
-- - - - I
BRGC
!ClK
INTP4IASCK
a-Bftllmar3
19
NEe
pPD78238 Family
The second interface is an a-bit clock-synchronized
serial interface (figure 9). It can be operated in either a
three-wire serial I/O mode or NEe serial bus interface
(SBI) mode.
Figure 9. Clock-Synchronized Ser/allnterface
BUSY'
N-ch Open-Drain
Ou1put Possible
Acknowledge
Output Clrcuft
Bus Releasel
Commano-
X2
CIockll8quenoy 1)0(= 4 to 12 MHz
In STOP mode, X1 "Internally shOrted to Vss to pravent
leakage current. 1l1el1llore, STOP mode Is not avanabls
when uaIng .... extemal clock ctlllUlt.
I3YL-919M.
33
..
NEe
pPD78238 Family
Timing Waveforms
Voltage Thresholds for AC Timing Measurements
VOO -1
-------.X'--0_.8_v-'~""~8::..;0V'_r2_.2_V_JX'-_ _ __
0.45 V - - - - - '
-
-
Read Operation
X1
I+------'OAIO -------<~
Address
Input Data
14--+i'">----.j 'FAR
I
',,"0
ASlB
tORST
tORIO---l
14-------tWRL------~
83YL-91828
34
NEe
IIPD78238 Family
Timing Waveforms (cont)
Write Operation
Xl
OutpulOata
Address
ASTB
I-- tWWLl
IOWST
14------7
-
IWWL2
IOSTW2 - - - . j
83YL-9183B
35
NEe
pPD78238 Family
Timing Waveforms (cont)
External WAIT Signal Input (Read Operation)
Input Data
Address
ASlB
~----tOSTWTH
~
~I
1 + - - - - tHSTWT
'=1
L~_·o-
RO
0(
tOWTR
tDAWT - - - - - . j
83Yl.-9184B
36
NEe
pPD78238 Family
Timing Waveforms (cant)
External WAIT Signal Input (Write Operation)
OutpUt Data
Address
ASlB
~-----tDSTWTH-----~~1
~-----tHSTWT
WR
tDW¥nH1
c
tHWWT1
----:--~---~---,
0(
l~
~I
c
~
~I
:=:=1
towrw
tOAWT
WAIT
83YL-9186B
37
38
NEe
JlPD78238 Family
Timing Waveforms (cant)
Serial Operation
Three-Line Serial
va Timing
SI-------{
oo ___
~)(~______~ ~
____~x~______~x~____
SB/Mode
Bus Release Signal Transfer Timing
SCK~~/
~'-'-:
---L..[~:::~~~~_='X~
SBO
___
\'---
•
________'>C
Command Signal Transfer Timing
SBO
39
NEe'
pPD78238 Family
Interrupt Input
External Clock
Xl
NMI
1+-----tCYX----~
INTPO·
1NTP5
Reset Input
Data Retention Characteristics
Set STOP Mode
r
tHVO
~
tFVO
I",
tRVO
O.8Voo
VOOOR
NMI
(ReI-by
laDing
edge Input)
0.8Voo
VOOOR
NMI
(Rei_by
rising
edge Input)
40
1\
O.BV
1\
0.8 V
/
O.BV
O.8Voo
tWAIT
>'
/
NEe
pPD78238 Family
I'PD78P238 PROGRAMMING
Table 5.
In the J1PD78P238, the mask ROM of J1PD78234 is replaced by a one-time programmable ROM (OTP ROM)
or a reprogram mable, ultraviolet erasable ROM (UV
EPROM). The ROM is 32K x 8 bits and can be programmed using a general-purpose PROM writer with a
IlPD27C256A programming mode.
Pin Functions During PROM
Programming (cont)
Pin
Table 5.
The PA-78P238GC/GJ/LQ/KF are the socket adaptors
used for configuring the IlPD78P238 to fit a standard
PROM socket.
Pin*
Function
Pin Functions During PROM Programming
Pin
Pin"
Function
P52/A1OP5s1A14
Al0A14
Address input pins for PROM
operations
P401ADo -
Do07
Data pins for PROM operations
P6sfWR
CE
Strobes data into the PROM
Enables a data read from the
PROM
P47/A~
P6~RD
OE
Refer to tables 5 and 6 and figures 17 through 19 for
special information applicable to PROM programming.
RESET
RESET
Table 5. Pin Functions During PROM
Programming
PROM programming mode
requires applying a low voltage to
this pin
MODE
Vpp
High voltage applied to this pin
for program write/verify
Address input pins for PROM
operations
Voo
VOO
Positive power supply pin
VSS
Vss
Ground
As
Address input pin for PROM
operations
• Pin name in PROM programming mode.
Ag
Address input pin for PROM
operations
Pin-
Function
Pin
POo -
Pin*
par
P501AS
Pin
Function
III
Table 6. Summary of Operation Modes for PROM Programming
Mode
RESET
CE
OE
Vpp
V DD
Program write
L
L
H
+12.5V
+6V
Data input
Program verify
L
H
L
+12.5V
+6V
Data output
Program inhibit
L
H
H
+12.5V
+6V
High Z
Read out
L
L
L
+5V
+5V
Data output
Output disable
L
L
H
+5V
+5V
High Z
Standby
L
H
L/H
+5V
+5V
High Z
Note: When +12.5 V is applied to Vpp and +6 V to Voo, both CE and
OE cannot be set to low level (L) simultaneously.
41
NEe
IIPD78238 Family
Pin Functions in ",PD78P238 PROM Programming Mode
Figure 17. 80-Pin Plastic QFP
}Voo
RESET
VOO
Open
L
L
9
"PD78P238GC
VSS
AO
Al
A2
A3
A4
A5
AS
A7
Open
Notas:
(1) L: Connect these pins separately to VSSthrough
resistors.
(2) VSS: Connect these pins to VSS.
(3) Open: Do not connect these pins.
(4) RESET: Set to a low level.
83YL·9207B
42
NEe
pPD78238 Family
Pin Functions in "PD78P238 PROM Programming Mode (cont)
Figure 18. B4-Pin PLCC
-{
Voo
vss{
Opan{
vss{
"PD78P238LQ
A9
VM{
opan{
CE
Open
~
..
II- C! . .
'----v---' IJlc
!
I!! "
~
0- N., ..
OJ co .. ;
m««««
;s.
oJ'
0
Nol8a:
(1) L: Connactthase p/nsseparately 10 Vsslhrough
1118181018.
(2) VSS: Connect lhess pIns 10 VSS'
(3) Open: Do not connect these pInS.
(4) RESET: Set 10 a low leval.
83'I\.o02Oe8
43
NEe
pPD78238 Family
Pin Functions in "PD78P238 PROM Programming Mode (cant)
Figure 19. 94-Pin Plastic QFP 94-Pln Ceramic LCC with Window
~{
3i~~imm~~~~~ti~S~~~~~~~~
71
70
-{ ,
",PD78P238KF/GJ
Vss {
Open
Open
AO
A1
A2
A3
A4
AS
AS
Open
A7
Open
i IW IW
~(Jo
'--v-----' Iii ... .. '" Iii is generated by dividing the oscillator frequency by two. Therefore, at the
maximum oscillator frequency of 12 MHz, the internal
system clock is 6 MHz. The minimum instruction exe-
NEe
pPD78244 Family
Figure 1. Memory Map
OOOOOH
OOOOOH
On-ChlpROM
18,384 Bytes
(Must be external
memory
In "PD7S243)
~
I
CALLFEntry
Area
OOFFFH
~
Extemal Memory
~
~ 01~H
On·Chlp EEPROM
512 Bytes
Program Area
03FFFHT
OFDOOH
RAM
~~{ f-------General Storage
OFFFFH
l0000H
IntemaiRAM
Extemal
Memory
(Expanded
Address
Area)
1
l
Pe~pheral
On-Chip RAM
and
Register Area
FFFFFH
Program Area
007FFH
ooeooH
04~H
OFCFFH
OFDOOH
CALLT Table Area
0007FH
OOO8OH
03FFFH
OFBFFH
OFCOOH
Interrupt Vec:Ior
Address Table Area
0003FH
OOO4OH
OFFOOH
J
f------Registers
f-------Spacial Function
Register Area
OFFFFH
cution time for an instruction fetched from internal
ROM is 333 ns (500 ns when fetched from external
memory).
Memory Space
The pPD78244 family has a 1M byte address space (see
figure 1). The first 64K bytes of this address space
(OOOOOH-OFFFFH) can be used as both program and
data memory. The remaining 960K bytes ofthis address
space (10000H-FFFFFH) can only be used as data
memory and is known as expanded memory.
External Memory
The pPD78244 family has an 8-bit wide external data
bus and a 16-bit wide external address bus (20-bit wide
if expanded memory is enabled). The low-order 8 bits
of the address bus are multiplexed to provide the 8-bit
data bus and are supplied by I/O port 4. The high-order
address bits of the 16-bit address bus are taken from
port 5. If expanded memory is enabled, the expanded
address nibble is provided by P6a to P63. Address latch,
read, and write strobes are also provided.
The memory expansion mode register (MM) is used to
enable external memory, to specify up to two addi-
;--
saddr Addressing
General RAM
------
OFEC1H
OFEC2H
Macro Service
Control Words
OFEDFH
OFEEOH
--------
OFEFFH
OFFOOH
--------
OFF1FH
General Registers
32 Bytes of SFR Area
B3YL'-
tional wait states or the use of the WAIT input pin for the
fi rst 64K bytes of memory, and to enable the high-speed
internal ROM fetch. Ports 4, 5, and 6 are available as
general purpose 1/0 ports when only internal ROM is
used and no external program or data space is ra,quired.
Expanded Data Memory
The MM register is also used to enable the external
expanded data memory space, addresses 10000H to
FFFFFH. When the expanded data memory is enabled,
the entire 1M byte address space is divided into 16
banks of 64K bytes each. The low-order 4-bits of the P6
or the PM6 registers are used as bank selection registers to supply the address information to A16 to A19 .
Data can easily be transferred from one memory bank
to another by using the appropriate instructions. Address lines A16 to A19 are only active when an instruction that uses expanded addressing is being executed.
A programmable wait control register (PW) allows the
programmer to specify up to two additional wait states
or the use of the WAIT input pin for expanded data
memory space.
7
•
!
NEe
pPD78244 Family
On-Chip RAM
CPU Control Registers
The J.lPD78244 family has a total of 512 bytes of on-chip
RAM. The upper 256-byte area (FEOOH-FEF FH) features
high-speed access and is known as "Internal RAM." The
remaining 256 bytes (FDOOH-FDFFH) are accessed at
the same speed as external memory and is known as
"Peripheral RAM." The general register banks and the
macro service control words are stored in Internal RAM.
The remainder of Internal RAM and any unused register
bank locations are available for general storage.
Program Counter. The program counter is a 16-bit
binary counter register that holds the address of the
next instruction to be executed. During reset, the
program counter is loaded with the address stored in
locations OOOOH and 0001H.
On-Chip EEPROM
The J.lPD78244 family has 512 bytes of on-chip EEPROM
(FBOOH-FCFFH) usable as internal data memory. A user
program can read from it or write to it usi ng most of the
same instructions available for use with internal RAM.
Any address of the EEPROM can be read at any time
even during a write cycle at the same address. Data is
read from EEPROM at the same speed as from peripheral RAM and the EEPROM is guaranteed for 100,000
repetitive rewrites.
Each write cycle, consisting of an auto erase cycle
followed by an auto write cycle, takes approximately
10 ms to complete. On completion of a write cycle, an
EEPROM write termination interrupt (INTEPW) is generated. If another write cycle is started before the
previous cycle is finished, an EEPROM write error
interrupt (INTEER) will be generated. Two status flags
are also available to indicate whether a write operation
is currently in progress and whether a write error has
occurred.
The EEPROM can be write protected in 128-byte
blocks. The area to be protected can be assigned and
enabled only once following reset. It cannot be
changed once it has been set by the program.
On-Chip Program Memory
The J.lPD78244 contains 16K bytes of internal ROM.
Instructions from on-chip program memory can be
fetched at high speed or at the same rate as from
external memory. The J.lPD78243 does not have on-chip
program memory.
8
Stack Pointer. The stack pointer is a 16-bit register
that holds the address of the last item pushed onto the
stack. It is decremented before new data is pushed
onto the stack and incremented after data is popped
off the stack.
Program Status Word. The program status word
(PSW) is an 8-bit register that contains flags that are
set or reset depending on the results of an instruction.
This register can be written to or read from 8 bits at a
time. The individual flags can also be manipulated on a
bit-by-bit basis. The assignment of PSW bits follows.
7
IE
0
I
z
CY
ISP
RBSO, RBS1
AC
Z
IE
I
RSSt
I
AC
I
RSSO
I
0
liSP
CY
Carry flag
Interrupt priority status flag
Register bank selection flags
Auxiliary carry flag
Zero flag
Interrupt request enable flag
General Registers
The general-purpose registers (figure 2) consist of four
banks of registers located at addresses FEEOH to
FEFFH in Internal RAM. Each bank consists of eight
a-bit general registers that can also be used in pairs to
function as four 16-bit registers. Two bits in the PSW
(RBSO and RBS1) specify which of the register banks is
active. The bits are set under program control. Registers have both functional names (like A, X, B, C for a-bit
registers and AX, BC for 16-bit registers) and absolute
names (like R1, RO, R3, R2 for 8-bit registers and RPO,
RP1 for i6-bit registers). Each instruction determines
whether a register is referred to by its functional or
absolute name and whether it is 8 or 16 bits.
NEe
pPD78244 Family
Figure 2. General Registers
OFEEOH RegIster
Bank
3
I
OFEFFH
For 16-Bft
Processing
For8-BIt
Processing
2
0
\
-
OFEFiH
(R1)A
(RO) X OFEFSH-
(RPO) AX
OFEF8H
(R3)B
(R2)C
(RP1) BC
OFEFAH
(R5)D
(R4)E
(RP2) DE
OFEFCH
(R7) H
(R6)L
(RP3) HL
OFEFEH
O£EF~H
__
)=Absolute Name
83Yl-9170B
Addressing
Special Function Registers
The pPD78244 family features 1·byte addressing of
both the special function registers and the portion of
on-chip RAM from FE20H to FEFFH. The 1-byte sfr
addressing accesses the entire SFR area, while the
1-byte saddr addressing accesses the first 32 bytes of
the SFR area and 224 bytes of Internal RAM. The 16-bit
SFRs and words of memory in these areas can be
addressed by 1-byte saddrp addressing, which is valid
for even addresses only. Since many instructions use
1-byte addressing, access to these locations is almost
as fast and versatile as access to the general registers.
There are seven addressing modes for data in main
memory: direct, register, register indirect with autoincrement and decrement, sad dr, SFR, based, and indexed. There are also both 8-bit and 16-bit immediate
operands.
The input/output ports, timers, capture and compare
registers, and mode and control registers for both the
peripherals and the CPU are collectively known as
special function registers. They are a/l memorymapped between FFOOH and FFFFH and can be accessed either by main memory addressing or by 1-byte
sfr addressing. They are either 8 or 16 bits as required, •
and many ofthe 8-bit registers are capable of single-bit
~access as well. Locations FFDOH through FFDFH are
known as the external SFR area. Registers in external
circuitry interfaced and mapped to these addresses
can be addressed with SFR addressing. Table 2 is a list
of the special function registers.
9
NEe
pPD78244 Family
Table 2. Special Function Registers
Access Units (Bits)
Address
Register (SFR)
Symbol
R/W
8
16
State After Reset
OFFOOH
PortO
PO
RI'N
x
x
Undefined
OFF02H
Port 2
P2
R
x
x
Undefined
OFF03H
Port 3
P3
RI'N
x
x
Undefined
OFF04H
Port 4
P4
RI'N
x
x
Undefined
OFF05H
Port 5
P5
RI'N
x
x
Undefined
OFFOSH
Port S
PS
RI'N
x
x
xOH
OF F07H
Port 7
P7
R
x
x
Undefined
OF FOAH
Port 0 buffer register (low)
POL
RI'N
x
x
Undefined
OFFOBH
Port 0 buffer register (high)
POH
RI'N
x
x
Undefined
OFFOCH
Real-time output port control register
RTPC
RI'N
x
x
DOH
OFF10H-OFF11H
is-bit compare register 0 (1S-bit timer 0)
CROO
RI'N
x
OFF12H-OFF13H
is-bit compare register (is-bit timer 0)
CR01
RI'N
x
OFF14H
8-bit compare register (8-bit timer 1)
CR10
RI'N
x
Undefined
Undefined
Undefined
OFF15H
8-bit compare register (8-bit timer/counter 2)
CR20
RI'N
x
Undefined
OFF1SH
8-bit compare register (8-bit timer/counter 2)
CR21
RI'N
x
Undefined
OFF17H
8-bit compare register (8-bit timer 3)
CR30
RI'N
x
OFF18H-OFF19H
1S-bit capture register (1S-bit timer 0)
CR02
R
OFF1AH
8-blt capture register (8-bit timer/counter 2)
CR22
R
x
OFF1CH
8-bit capture/compare register (8-bit timer 1)
CR11
RI'N
x
Undefined
OFF20H
Port 0 mode register
PMO
W
x
FFH
OFF23H
Port 3 mode register
PM3
W
x
FFH
OFF25H
Port 5 mode register
PM5
W
x
FFH
OFF2SH
Port S mode register
PMS
RI'N
OFF30H
Capture/compare control register 0
CRCO
OFF31H
Timer output control register
OFF32H
Capture/compare control register 1
OFF34H
Capture/compare control register 2
CRC2
x
OOH
OFF40H
Pullup resistor option register
PUO
RI'N
x
x
DOH
RI'N
x
x
Undefined
x
x
Undefined
Undefined
x
FxH
W
x
10H
TOC
W
x
OOH
CRC1
W
x
DOH
W
OFF43H
Port 3 mode control register
PMC3
OFF50H-OFF51 H
1S-bit timer register 0
TMO
R
OFF52H
8-bit timer register 1
TM1
R
OFF54H
8-bit timer register 2
TM2
OFF5SH
8-bit timer register 3
TM3
OFF5CH
Prescaler mode register 0
OFF5DH
OOH
x
OOOOH
x
DOH
R
x
DOH
R
x
DOH
PRMO
W
x
DOH
Timer control register 0
TMCO
RI'N
x
DOH
OFF5EH
Prescaler mode register 1
PRM1
W
x
DOH
OFF5FH
Timer control register 1
TMC1
RI'N
x
OOH
OFFS8H
ND converter mode register
ADM
RI'N
x
DOH
OFFSAH
ND conversion result register
ADCR
R
OFF78H
EEPROM write control register
EWC
RI'N
10
x
x
x
Undefined
x
00110100B
NEe
I'PD78244 Family
Table 2. Special Function Registers (cont)
Access Units (Bits)
Symbol
8
16
State After Reset
Address
Register (SFR)
OFF7DH
One-shot pulse output control register
OSPC
R/W
x
x
OFF80H
Clocked serial interface mode register
CSIM
R/W
x
x
OOH
OFF82H
Serial bus interface control register
SBIC
R/W
x
x
OOH
OFF86H
Serial shift register
SID
R/W
OFF88H
Asynchronous serial interface mode register
ASIM
R/W
x
OFF8AH
Asynchronous serial interface status register
ASIS
R
x
OFF8CH
Serial receive buffer: UART
RxB
R
OFF8EH
Serial transmit shift register: UART
TxS
W
x
Undefined
OFFOOH
Baud rate generator control register
BRGC
W
x
OOH
OFFCOH
Standby control register
STBC
R/W
x
OOH
OFFC4H
Memory expansion mode register
MM
OFFCSH
Programmable wait control register
PW
OFFC6H
Refresh mode register
RFM
OFFDOH-OFFDFH
External SFR area
OFFEOH
Interrupt request flag register OL
OFFE1H
OFFEOH-OFFEl H
R/W
OOH
x
Undefined
x
80H
x
OOH
x
Undefined
R/W
x
x
20H
R/W
x
x
80H
R/W
x
x
OOH
R/W
x
x
Undefined
IFOL
R/W
x
x
OOH
Interrupt request flag register OH
IFOH
R/W
x
x
Interrupt request flag register 0
IFO
R/W
OFFE2H
Interrupt request flag register 1 L
IFIL
R/W
x
x
xxxxxxOOB
OFFE4H
Interrupt mask flag register OL
MKOL
R/W
x
x
FFH
x
x
OOOOH
OFFESH
Interrupt mask flag register OH
MKOH
R/W
OFFE4H-OFFESH
Interrupt mask flag register 0
MKO
R/W
OFFE6H
Interrupt mask flag register 1 L
MKIL
R/W
x
x
xxxxxxllB
FFH
FFH
x
FFFFH
OFFE8H
Priority specification flag register OL
PROL
R/W
x
x
OFFE9H
Priority specification flag register OH
PROH
R/W
x
x
OFFE8H·OFFE9H
Priority specification flag register 0
PRO
R/W
OFFEAH
Priority specification flag register 1L
PR1L
R/W
x
x
xxxxxxllB
OFFECH
Interrupt service. mode specification flag register OL
ISMOL
R/W
x
x
OOH
OFFEDH
Interrupt service mode specification flag register OH
ISMOH
R/W
x
x
OFFECHOFFEDH
Interrupt servioe mode specification flag register 0
ISMO
R/W
FFH
x
FFFFH
OOH
x
OOOOH
OFFEEH
Interrupt servioe mode specifioation flag register 1L
ISM1L
R/W
x
x
xxxxxxOOB
OFFF4H
External Interrupt mode register 0
INTMO
R/W
x
x
OOH
OFFFSH
External interrupt mode register 1
INTMl
R/W
x
x
OOH
OFFF8H
Interrupt status register
1ST
R/W
x
x
OOH
Input/Output Ports
There are up to 54 port lines on the pPD78244 and up to
36 port lines on the pPD78243. (Ports 4, 5, and two bits
of port 6 are not available on the pPD78243 since the
pPD78243 must always use external memory.) Table 3
--
OOH
x
lists the features of each port and figure 3 shows the
structure of each port pin_ The pin levels of all port 2,3,
and 7 pins can always be read or tested regardless of
the dual pin function.
11
NEe
pPD78244 Family
Figure 3. Pin I/O Circuits
Type 1 (EA)
.,1-_ _-<../1>(1-_ _ _ pullup
'"'"'I
IN
enable
<>'----Lrr;>o-----.....
Schmllllrlgger Input willi hyslerasls characlerlstlc.
Type 5-A (p30' P31 , P34' P37, P4, PS, Pe4, Pe5)
Voo
Schmllllrtgger Inpul willi hysteresis characterlsllc.
pullup enable
-------1[>0
dam~
OIllpUldlsable~
i
Push-pUU output Whera lIIe olllput can be placed In
P and N channels ara turned off).
hlgh~mpedanoe (boIh
+-......-*--0 IN/OUT
Input enable _ _ _ _ _ _--1
Type 8-A (P32)
Typa9(P7)
Voo
INo--.--i;O+
pUllup -------1"-----t~
enable
V
Voo
VREF (Thrashold Volmge)
.-....----0
L -_ _ _ _ _ _ _ _
IN/OUT
Input
enable
Voo
pullup enable
-------1[>0><>-----1
Voo
pullup enable
.-....--4---0
------[>o>-----II~
.-....-_--0
IN/OUT
INIOUT
VREF (Thrashokl Voltage)
Input enable _ _ _ _ _-==--1
83Yl-91718
12
NEe
"PD78244 Family
Table 3. Digital Port Functions
Port
Operational Features
Port 0
S-bit high impedance output
Port 2
S-bit Schmitt trigger input
Configuration
Direct Drive
Capability
Software Pull up
Resistor Connection
Transistor
Port 3
8-bit input or output
Bit selectable
Port 4
8-bit input or output
Byte selectable
LED
Byte selectable
Port 5
8-bit input or output
Byte selectable
LED
Byte selectable, input bits only
Port 6
4-bit output (bits 0 to 3)
4-bit Input or output (bits 4 to 7)
Bit selectable
Port 7
6-bit input
Byte selectable, input bits only
In 4-bit unit, input bits only
Note: Software pullup resistors can be internally connected only on
a port-by-port basis to port bits set to input mode. Pullup
resistors are not connected to port bits set to output mode.
Real-time Output Port
The real-time output port (RTPC) shares pins with port
O. It can be used as two independent 4-bit real-time
output ports or one B-bit real-time output port. In the
real-time output mode, data stored beforehand in the
buffer registers, POH and POL, is transferred immediately to the output latch of PO on the occurrence of a
timer 1 interrupt (INTC10 or INTC11) or external interrupt (lNTPO) (see figure 4). By using the real-time
output port with the macro service function, port 0 can
be used to output preprogrammed patterns at preprogrammed variable time intervals. In this mode, two
independent stepper motors can accurately be driven
at a fixed or variable rate.
Figure 4. Real-time Output Port
Internal Bus
RTPC
Buller Register
POH
4-Blt
Real-TIme
Output (POH)
INTPO
INT10
OUtput
TrIgger
Control
CIrcuit
4-Blt Real-TIme
Output (POL)
I
I
POL
8
4
4
INTC11
83YL-01728
13
III!IIIII.
lIMa!
NEe
pPD78244 Family
Figure 5. AID Converter
Register Strtng
r---r----,
Rf2rT: AVREF
ANO
AN1
Sample and
AN2
1---- 1
AN3
AN4
AN5
ANa
Hold ClR:U1t
Input
Selector
R
/--~--T_'
SO/S80, and EA pins.
AC Characteristics-Read/Write Operation
= -10 to + 70°C; VOO = +5 V :tl0%; VSS = 0 V; !xx = 12 MHz; CL =
TA
Item
Symbol
Xl input clock cycle time
Icvx
Address setup time to ASTB
~
100 pF
Calculation Formula (Note 2, 3)
Min
Max
Unit
82
250
ns
Conditions
52
ns
tHSTA
25
ns
Address hold time from Rot
tHRA
30
ns
Address hold time from WR t
tHWA
30
ns
Address to RD • delay time
tOAR
2tcvx -35
129
ns
tFAR
Icvx/2-30
11
tOAIO
(4+2n) tcvx -100
228
ns
No wait states
tOSTIO
(3+2n)tcvx - 65
181
ns
No wait states
RD ~ to data input time
tORIO
(2+2n)tcvx - 64
100
ns
No wait states
ASTB • to RD • delay time
tOSTR
Icvx- 30
52
ns
Data hold time from RD t
tHRIO
0
ns
RD t to address active time
tORA
2tcvx- 4O
124
ns
RD t to ASTB t delay time
tORST
2tcvx- 4O
124
ns
ns
ns
Address hold time from ASTB
Address float time to RD
tSAST
~
(Note 1)
~
Address to data input time
ASTB
~
to data input time
RD low-level width
tcvx- 30
twRL
(2+2n)tcvx- 40
124
ASTB high-level width
twSTH
tcvx- 3O
52
Address to WR • delay time
tOAW
2tcvx- 35
129
ASTB • to data output time
WR I to data output time
ASTB • to WR • delay time
Data setup time to WR t
tOSTOO
tcvx + 60
tOWOO
ns
tOSTW2
129
ns
146
ns
No wait states
22
ns
Refresh mode
tsooWF
Data hold time from WR t (Note 1)
tHwOO
24
ns
2tcvx- 35
Icvx- 6O
Address to WAIT. Input time
ns
60
tosTWl
tSOOWR
WR low-level width
ns
142
52
Data setup time to WR •
t to ASTB t delay time
No wait states
tcvx- 3O
(3+2n)tcvx - 100
WR
ns
Refresh mode
20
ns
tOWST
tcvx- 4O
42
ns
twWLl
(3+ 2n)tcvx - 50
196
ns
No wal t states
twWL2
(2+2n)tcvx - 50
114
ns
Refresh mode; No wait
states
tOAWT
3lcvx -100
146
ns
NEe
pPD78244 Family
AC Characteristics-Read/Write Operation (cont)
Item
Symbol
Calculation Formula (Note 2, 3)
ASTB j to WAIT j input time
toSTWT
2tcvx- 80
WAIT hold time from ASTB j
tHSTWT
2XtCVX + 10
ns
One external wait state
tOSTWTH
2(1+ X)tcvx - 55
273
ns
One external wait state
RD j to WAIT input time
tOAWTl
tcvx- 6O
22
ns
WAIT hold time from RD j
tHRWT
(2X-l)tCVX + 5
ASTB j to WAIT
t delay time
Min
Max
Unit
84
ns
174
Conditions
ns
One external wait state
186
ns
One external wait state
62
ns
87
RD j to WAIT t delay time
tORWTH
(2X+l)tcvx- 6O
WAIT t to data Input time
tOWTID
tcvx-20
t delay time
tOWTW
2tcvx-1O
154
tOWTA
tcvx- 1O
72
tOWWTl
tcvx- 60
ns
Refresh disabled
tHWWTl
(2X-l )tcvx + 5
87
ns
One external wait state;
refresh disabled
tHWWT2
2(X-l)tcvx + 5
5
ns
One external wait state;
refresh enabled
tOWWTHl
(2X + 1)tcvx - 60
186
ns
One external wait state;
refresh disabled
104
ns
One external wait state;
refresh enabled
WAIT t to WR
WAIT t to RD t delay time
WR j to WAIT input time
WAIT hold time from WR
j
WR j to WAIT t delay time
RD
t to REFRQ I delay time
t to REFRQ j delay time
ns
22
tOWWTH2 2Xtcvx-6O
WR
ns
tORAFQ
2tCVX-1O
154
ns
72
ns
tOWRFQ
tcvx- 1O
REFRQ low-level width
twRFQl
2Icvx- 44
120
ns
REFRQ t to ASTB t delay time
tOAFQST
4tcvx- 48
280
ns
Notes:
(1) The hold time includes the time during which VOH and VOL are
retained under the following load conditions: Cl = 100 pF and
Rl = 2 kn
(2) n indicates the number of internal wait states.
(3) X indicates the number of external wait states (1, 2, 3, ...)
Serial Port Operation
= -10 to + 70'C; Voo = +5 V ±10%; VSS = 0 V; !xx = 12 MHz; Cl =
TA
100 pF.
Item
Symbol
Min
Serial clock cycle time
tCYSK
1.0
J.ls
External clock input
1.3
J.ls
Internal clock/16 output
Internal clock/64 output
Serial clock low-level width
tWSKl
Serial clock high-level width
twSKH
SI, SBO setup time to SCK t
SI, SBO hold time from SCK
t
Max
Unit
Conditions
5.3
J.ls
420
ns
External clock input
556
ns
Internal clock/16 output
Internal clock/64 output
2.5
J.ls
420
ns
External clock input
556
ns
Internal clock/16 output
Internal clock/64 output
2.5
J.ls
tSSSK
150
ns
tHSSK
400
ns
25
•
I
NEe
pPD78244 Family
Serial Port Operation (cont)
Item
Symbol
Min
Max
Unit
SO/SOO output delay time
from SCK~
tOSBSK1
0
300
ns
CMOS push-pull
output
(3-line serial I/O mode)
tOSBSK2
0
800
ns
Open-drain output
(SBI mode), Rl = 1 kO
tHSBSK
4
teyx
SBI mode
tSSBSK
4
teyx
SBI mode
SOO low-level width
twSBl
4
teyx
SBO hig h-Ievel width
twSBH
4
teyx
SOO high, hold time from
SCKt
SOO low, setup time to SCK
~
Conditions
AID Converter Operation
TA = -10 to +70'C; voo = +5 V ±10%; vss = AVss = 0 v.
Item
Symbol
Resolution
Min
Typ
Quantization error
Sampling time
tsAMP
0.4
%
AVAEF = 4.0 V to VOO
%
AVAEF = 3.6 V to Voo
240
teyx
125 ns s teyx s 250 ns
72
teyx
83 ns s tcyx s 125 ns
tcyx
125 ns
Analog input impedance
AVAEF + 0.3
1000
tcyx
s
V
5.0
mA
Operating mode,
0.2
1.5
mA
(Note 2)
(1) Quantization errror is not included. Unit is defined as percent of
full-scale value.
(2) When CS bit of the ADM register is set to 0
Interrupt Timing Operation
Item
Symbol Min Max Unit Conditions
NMllow-level width
twNll
10
NMI high-level width
twNIH
10
Jls
INlPO-INTP5 low-level width
twITl
24
teyx
INTPO-INTP5 high-level width twITH
24
teyx
RESET low-level width
twASl
10
JlS
RESET high-level width
twASH
10
Jls
250 ns
MO
1.5
Notes:
Jls
s
V
Voo
3.6
AVAEF current
26
83 ns S tcyx s 125 ns
tcyx
48
Analog reference voltage
LSB
360
-0.3
Analog input voltage
Conditions
O.B
±1/2
teONV
Unit
Bit
Full-scale error (Note 1)
Conversion time
Max
8
!xx =
12 MHz
NEe
pPD78244 Family
Data Retention Characteristics
TA = -10 to
+ 70"C.
Item
Symbol
Min
Data retention voltage
VOOOR
2.5
Data retention current
IOOOR
Max
Unit
Conditions
5.5
V
STOP mode
2
20
JiA
VDOOR
5
50
IlA
VOOOR = 5 V ±10%
Typ
= 2.5 V
VOO rise time
tRVO
200
Voofalltime
tFVO
200
IlS
V00 retention time
(from STOP mode setting)
tHVO
0
ms
STOP release signal input time
tOREL
0
ms
!wAIT
30
ms
5
ms
Ceramic resonator
Oscillation stabilization wait time
JiS
Crystal resonator
Low-level input voltage
VIL
0
0.1 VOOOR
V
Specified pins (Note 1)
High-level input voltage
VIH
0.9 VOOOR
VOOOR
V
Specified pins (Note 1)
Note: RESET, P201NMI, P21/INTPO, P22/INTP1, P2a1INTP2/CI, P2,tf
INTP3, P2s/INTP4/ASCK, P2s1INTP5, P27/SI, P32/SCK, and
P3a1S0/SBO
Recommended Resonator Circuit
,...R_e_co_m_m_e_n_tt_e_d_Ext
__e_r_n_tl'_C_t_o_C_k_C_i_TC_U_'_'-_ _ _ _-, . .
Clock
»--..---1 Xl
HOMOS
Inverters
X2
=
Ceramic or crystal resonator frequency fxx 4 to 12 MHz
External oscmatlon clrcuft should be as close to the Xl and
X2 pins as possible
Do not place other signal Unes In the shaded area
Clock frequency f xx = 4 to 12 MHz
In SlOP mode, Xl Is Internally ahorJad to VSS to prevent
leakage current Therefore, SlOP mode Is not avaUable
when using this external clock circuit.
27
NEe
pPD78244 Family
Timing Waveforms
Voltage Thresholds for AC Timing Measurements
Voo -1
-----.X'__O_.8_V....:~~.8~O~:....2_.2_V__'X'___ __
O.45V - - - - - '
-
-
Read Operation
Xl
I+------'DAIO ----~
Input Data
Add",ss
l4-..roo-~ 'FAR
1-'
ASlB
'OSTR
tORIO~
~----tWRL--------~
BSYL-9182B
28
NEe
pPD78244 Family
Timing Waveforms (cont)
Write Operation
Xl
output Data
Address
ASTB
•
1+-----+--tWWLl
tWWL2
29
NEe
pPD78244 Family
Timing Waveforms (cant)
External WAIT Signal Input (Read Operation)
Input Data
ADO-AD7
lowno
AS1B
IOSTWTH
iii
U-
'~1
IHAVVT
IOSlWT _ _
lOAVVT
30
~
»1
IHSlWT
,~
IOVVTA
Address
NEe
pPD78244 Family
Timing Waveforms (cont)
External WAIT Signal Input (Write Operation)
Output Data
Address
ASTB
~-----tDS1WTH-----,»"1
»/
~-----tHSTWT
or
0(
tDWWTH1----i~
t HWWT1
..0(--
---!
tDWWTH2
- tHWWT2 - -
L,~
WR
0(
tDAWT---~
83YL-9186B
31
NEe
pPD78244 Family
Timing waveforms (cont)
Refre"" After Read
AS1B
RD
f
I
toRRFQ
I
.1
-I
tORFQST
r
REFRQ
I
1
IWRFQL
83YLo81868
Refresh After Write
AS1B
WR
f
I
tORFQST
tOWRFQ
I
I
REFRQ
r
I
IWRFQL
1rlYW1B7B
32
NEe
pPD78244 Family
Timing Waveforms (cant)
Serial Operation
Three-Line Serial va Timing
Sl------{
SO _ _ _
_JX. . ______-' ~____--JX~_______JX~____
SS/Mode
•
Bus Release Signal Transfer Timing
SCK~----'/
sao
~
'-
"""
_(
:
\'--~/
\"---
)(~-===>C
_.....l. _ _ _ _ _ _ _---J
Command Signal Transfer Timing
sao
33
NEe
pPD78244 Family
Timing waveforms (cant)
Interrupt Input
External Clock
X1
NMI
~-------t~x------~
INTPO·
ImP5
Reset Input
Data Retention Characteristics
Set STOP Mode
f
VOOOR
.....- - - - - - tWAIT ----.......,~
tFVO
VOOOR
0.8 V
NMI
(Release by
faRing
edge Input)
O.BV
O.8Voo
34
NEe
NEG Electronics Inc.
IlPD78K2 Product Line
Programming Reference
September 1993
JLPD78K2 Product Line
Operands and Operations
This programming reference contains the instruction
set and the interrupt vector tables for the J.lPD78K2
product line.
Refer to the following tables for the definitions of
symbols in the operand and operation columns of the
Instruction Set table.
The instruction set features both 8- and 16-bit data
transfer and arithmetic instructions, 8-bit logic instructions, and single-bit manipulation instructions. Branch
instructions exist to test individual bits in the program
status word, the 16-bit accumulator, the special function registers and in the saddr portion of Internal RAM.
Instructions range in length from 1 to 5 bytes, depending on the instruction and addressing mode.
Uppercase letters, such as "p.:' or "PSw," are key symbols and must be written as shown in the Registers and
Flags table. See the Registers and Flags table for the
list of key symbols. Lowercase letters, such as "sfr" or
"mem" are not key symbols and an absolute value or
label must be substituted by the user when writing the
instruction. For example, "MOV A, sfr" may be written
as "MOV A, PD." When the symbols +, -, #, !, $, /, [ ],
and & are used as a prefix of a word, the symbol
remains while lower case letters are replaced by a
value. For example, "ADD A, #byte" may be written as
"ADD A, #OAFH," or "BR $addr16" may be written as
"BR $LOOP1."
Symbols rand rp can be described using the functiomil
name or absolute name.
50836
NEe
pPD78K2 Product Line
Operands
Registers and Flags
Symbol
Definitions
Symbol
Definitions
+
Autoincrement
A
A register; a-bit accumulator
Autodecrement
X
X register
Immediate data
B
B register
Absolute address
C
C register
#
$
Relative address
o
o register
Bit Inversion
E
E register
H register
Indirect addressing
H
&
Subbank
L
L register
r,r'
Register
Functional name: X, A, C, B, E, 0, L, H
Absolute name: RO to R7
RO-R7
Registers 0 to 7 (absolute names)
AX
Register pair (AX); l6-bit accumulator
BC
Register pair (BC)
rl
rp, rp'
sfr
Register group 1: C, B
Register pair
Functional name: AX, BC, DE, HL
Absolute name: RPO to RP3
DE
Register pair (DE)
HL
Register pair (HL)
RPO-RP3
Register pairs 0 to 3 (absolute names)
Special function register (S-bit):
See individual data sheets for specific sfr names.
PC
Program counter
SP
Stack pointer
sfrp
Special function register pair (16-blt):
See individual data sheets for specific sfrp names.
mem
Memory address indirectly addressed
Register indirect mode: [DE], [HL], [DE+]. [HL+],
[DE-) , [HL-]
Base mode: [DE+ byte), [HL+ byte), [SP+ byte)
Indexed mode: word[A), word[B), word [DE), word[HL]
meml
Group 1 memory address indirectly addressed: [DE),
[HL)
saddr,
saddr'
Memory address addressed by means of short direct
addressing: FE20H-FF1FH immediate data or label
saddrp
Memory address addressed by means of short direct
addressing pair: FE20H-FFl EH immediate data(LSB =
0; even address) or label
Registers and Flags
Symbol
Program status word
CY
Carry flag
AC
Auxiliary carry flag
Z
Zero flag
RBS1-RBSO
Register bank select flags
IE
Interrupt enable flag
STBC
Standby control register
jdispS
Signed 2's complement data (S bits) indicating
relative address distance between first address of
next instruction and branch destination address
Memory contents indicated by address or register
contents in ( )
addr16
l6-bit address: OOOOH-FEFFH immediate data or label
addrll
ll-bit address: aOOH-FFFH immediate data or label
()
addr5
5-blt address: 40H-7EH immediate data or label (even
address only)
xxH
word
l6-bit data: l6-bit immediate data or label
byte
S-bit data: S-bit immediate data or label
bit
3-bit data: 3-bit immediate data or label
n
Number of shift bits: 3-blt immediate data (0-7)
RBn
Register bank: RBO-RB3
Definitions
PSW
Hexadecimal number
Higher a bits and lower 8 bits of l6-bit register
pair
/\
v
Logical product (AND)
Logical sump (OR)
Exclusive logical sum (exclusive OR)
Inverted data
2
NEe
IIPD78K2 Product Line
Flag Column Indicators
Bytes
Blank
No change
o
Cleared to 0
The number of bytes for instructions with a mem or
&mem operand depends on the particular instruction
and the memory addressing mode (register indirect,
base, and or indexed).
Set to 1
x
Set or cleared depending on the result
R
Value previously saved is restored
A MOV instruction with register indirect mode specified
for mem is a special 1-byte instruction. When base
mode or indexed mode is specified for mem, the a-bit
or 16-bit offset data corresponding to byte and word,
respectively, is added from the third byte onward.
Bytes for Instructions With "mem" and "&mem" Operands
Register Indirect
Mode
(SP+byteJ
word(A)
word (B)
word(DEJ
word(HL)
A,mem
3
3
4
mem,A
3
3
4
4
4
5
(DE+)
(HL+)
(DE-)
(HL-)
Instruction
MOV
XCH
ADD, ADDC, SUB,
SUBC, AND, OR,
XOR, CMP
Indexed
Mode
Base Mode
(DE)
(HL)
A,&mem
2
2
(DE+byte)
(HL+byte)
&mem,A
2
2
4
4
5
A,mem
2
2
3
3
4
A, &mem
3
3
4
4
5
A,mem
2
2
3
3
4
A, &mem
3
3
4
4
5
•
3
NEe
pPD78K2 Product Line
Instruction Set
Flags
Mnemonic
Operand
Operation
Bytes
Z
AC CY
8-Bit Data Transfer
MOV
XCH
*
4
r, #byte
r .... byte
2
saddr, #byte
(saddr) .... byte
3
afr, #byte
sfr +- byte
3
r,r'
r
r'
2
A,r
A-r
+-
A, saddr
A .... (saddr)
saddr, A
(saddr) +- A
2
saddr, saddr'
(saddr)
3
+-
(saddr)
2
A,sfr
A+- sfr
sfr, A
sfr- A
A,mem*
A+- (mem)
1-4
A,&mem*
A- (&mem)
2-5
mem,A*
(mem) -A
1-4
&mem,A*
(&mem) -A
2-5
2
2
A,laddr16
A - (laddr16)
4
A, &!addr16
A - (&laddr16)
5
laddr16,A
(laddr16) - A
4
&laddr16,A
(&!addr16) - A
5
PSw, #byte
PSW - byte
3
x
x
x
PSW,A
PSW-A
2
x
x
x
A,PSW
A-PSW
2
A,r
A-r
r,r'
,,,",r'
A,mem
A- (mem)
2-4
A,&mem
A- (&mem)
3-5
A, saddr
A ... (saddr)
2
A, sfr
A-sfr
3
saddr, saddr'
(saddr) ... (saddr')
3
H [DE], [HL], [DE+], [DE-] , [HL+] or [HL-] is described as mem,
these instructions are used as dedicated 1-byte codes. Hthe
register name is described as &mem, the instructions are used as
dedicated 2-bytee codes.
2
NEe
IlPD78K2 Product Line
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
Z
AC CY
16-Bit Data Transfer
MOVW
rp, #word
rp
saddrp, #Word
(saddrp)
sfrp, #Word
sfrp +- word
rp, rp'
rp
PIX, saddrp
PIX +- (saddrp)
2
saddrp, PIX
(saddrp)
2
PIX, sfrp
PIX
sfrp, PIX
sfrp
PIX, meml
PIX
+-
(meml)
2
PIX, &meml
PIX
+-
(&meml)
3
meml,PIX
(mem 1)
&meml,PIX
(&meml)
+-
+-
word
3
word
+-
4
2
rp'
+-
4
+-
PIX
sfrp
2
AX
2
+-
+-
2
PIX
+-
AX
3
8-Bit Operations
ADD
AD DC
A, #byte
A,CY +- A + byte
2
x
x
x
saddr, #byte
(saddr),CY
3
x
x
x
sfr, #byte
sfr,CY
4
x
x
x
rlr'
r,CY~
2
x
x
x
+-
+-
(saddr) + byte
sfr + byte
r+ r'
A, saddr
A,CY
2
x
x
x
A, sfr
A,CY +- A +sfr
3
x
x
x
saddr, saddr'
(saddr),CY +- (saddr) + (saddr')
3
x
x
x
A,mem
A,CY
+-
A + (mem)
2-4
x
x
x
A,&mem
A,CY
+-
A + (&mem)
3-5
x
x
x
A, #byte
A,CY +- A + byte + CY
2
x
x
x
saddr, #byte
(saddr),CY
3
x
x
x
sfr, #byte
sfr,CY
4
x
x
r,r'
r,CY
2
x
x
x
x
A + (saddr)
+-
+-
+-
+-
(saddr) + byte + CY
sfr + byte + CY
r + r' +CY
A, saddr
A ,CY
2
x
x
x
A, sfr
A,CY +- A +sfr +CY
3
x
x
x
sad dr, saddr'
(saddr),CY
3
x
x
x
A,mem
A,CY
2-4
x
A,&mem
A,CY +- A + (&mem) + CY
3-5
x
x
x
x
x
+-
+-
A + (saddr) + CY
+-
(saddr) + (saddr') + CY
A + (mem) +CY
5
•
NEe
pPD78K2 Product Line
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
Z
x
x
x
x
x
x
x
x
x
x
x
x
x
AC CY
8-BIt Opefstions (cont)
SUB
SUBC
AND
OR
6
A, #byte
A,CY - A - byte
2
saddr, #byte
(saddr),CY -
3
sfr, #byte
sfr,CY - sfr - byte
4
r,r'
r,CY-r-r'
2
A, saddr
A,CY - A - (saddr)
2
A, sfr
A,CY -A-sfr
3
x
x
x
x
x
x
(saddr) - byte
sad dr, saddr'
(saddr),CY -
3
x
x
A,mem
A,CY - A - (mem)
2·4
x
x
x
A,&mem
A,CY - A - (&mem)
3·5
x
x
x
A, #byte
A,CY .... A - byte - CY
2
x
x
x
saddr, #byte
(saddr),CY -
3
x
x
x
sfr, #byte
sfr,CY .... sfr - byte - CY
4
x
x
x
r,r'
r,CY .... r - r' - CY
2
x
x
x
A, saddr
A,CY .... A - (saddr) - CY
2
x
x
x
A, sfr
A,CY - A- sfr- CY
3
x
x
x
3
x
x
x
x
x
x
x
(saddr) - (saddr')
(saddr) - byte - CY
saddr, saddr'
(saddr),CY -
A,mem
A,CY - A - (mem) - CY
2·4
A,&mem
A,CY - A - (&mem) - CY
3·5
A,#byte
A .... Al\byte
(saddr) - (saddr') - CY
saddr, #byte
(saddr) -
sfr, #byte
sfr ... sfr 1\ byte
4
x
x
x
x
x
2
x
(saddr) 1\ byte
3
"r'
r
A, saddr
A - A 1\ (saddr)
2
x
A, sfr
A-Al\sfr
3
x
saddr, saddr'
(saddr) -
3
x
A,mem
A-AI\ (mem)
2·4
x
A,&mem
A ... A 1\ (&mem)
3-5
x
A, #byte
A-AVbyte
2
x
sad dr, #byte
(saddr) ... (saddr) V byte
3
x
sfr, #byte
sfr ... sfr V byte
4
x
4-
r /\ r'
2
(saddr) 1\ (saddr1
r,r'
r+- rVr'
2
x
A, saddr
A -A V (saddr)
2
x
A, sfr
A-AVsfr
3
x
saddr, saddr'
(saddr) -
3
x
A,mem
A-AV (mem)
2·4
x
A,&mem
A-AV (&mem)
3-5
x
(saddr) V (saddr)
NEe
pPD78K2 Product Line
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
Z
AC CY
8·8ft Operations (cont)
XOR
CMP
A, #byte
A-A'ifbyte
2
x
saddr, #byte
(saddr) _ (sadd~ 'if byte
3
x
sIr, #byte
sIr _ sIr 'if byte
4
x
r,r'
r - r'ifr'
2
x
A, saddr
A _ A 'if (saddr)
2
x
A, sIr
A-A'ifsfr
3
x
saddr, saddr'
(saddr)
3
x
<-
(saddr) 'if (saddr')
A,mem
A<-A'if(mem)
2-4
x
A,&mem
A _ A 'if (&mem)
3-5
x
A, #byte
A- byte
2
x
x
x
saddr, #byte
(saddr) - byte
3
x
x
x
sfr, #byte
sfr - byte
4
x
x
x
r,r'
r- r'
2
x
x
x
A, saddr
A- (saddr)
2
x
x
x
A, sIr
A-sIr
3
x
x
X
saddr, saddr'
(saddr) - (saddr')
3
x
x
x
A,mem
A- (mem)
2-4
x
x
x
A,&mem
A- (&mem)
3-5
x
x
x
SUBW
CMPW
~
I
16-8it Operations
ADDW
I
AX,#Word
AX,CY _ AX +word
3
x
x
AX,rp
AX,CY _ AX + rp
2
x
x
x
AX, saddrp
AX,CY ... AX + (saddrp)
2
x
x
x
AX,slrp
AX,CY - AX + sfrp
3
x
x
x
AX,#Word
AX,CY +- AX - word
3
x
x
x
AX,rp
AX,CY +- AX - rp
2
x
x
AX, saddrp
AX,CY _ AX - (saddrp)
2
x
x
x
x
AX, sfrp
AX,CY ... AX - sfrp
3
x
x
x
AX, #Word
AX-word
3
x
x
x
x
AX,rp
AX-rp
2
x
x
x
AX, saddrp
AX - (saddrp)
2
x
x
x
AX, sfrp
AX - sfrp
3
x
x
x
MULU
AX-Axr
2
DIVUW
AX(quotient),r(remainder) - AX -;.- r
2
Multiplication/Division
7
NEe
pPD78K2 Pl'oduct Line
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
Z
AC CY
Increment/Decrement
INC
r-r+1
sOOdr
DEC
2
(saddr) +- (saddr) + 1
r-r-1
saddr
2
(saddr) +- (saddr) - 1
INCW
rp
rp+-rp+1
DECW
rp
rp- rp-1
ROR
r, n
(CY,r7 -
ro, rm-l -
ROL
r, n
(CY,ro -
r7, rm+l - rm) x n times, n
RORC
r, n
(CY -
x
x
x
x
x
x
x
x
Shift/Rotate
rm) x n times, n
= 0-7
= 0-7
2
x
2
x
ROLC
r, n
SHR
r, n
SHL
r, n
SHAW
rp, n
SHLW
rp, n
= 0-7
(CY -r7, ro - CY, rm+ 1 - rm) x n times, n = 0-7
(CY -ro, r7 - 0, rm-l ..... rm) x n times, n = 0-7
(CY ... r7, ro ... 0, rm+ 1 - rm) x n times, n = 0-7
(CY - rpo, rP15 +- 0, rPm-l - rPm) x n times, n = 0-7
(CY - rP15, rpo - 0, rPm+l - rPm) x n times, n = 0-7
ROR4
mem1
~-o -
(mem1)3_0, (mem1)7_4 +- A3-0,
(mem1)3_0 ..... (mem1)7_4
2
&mem1
~-O +- (&meml)3_0, (&meml)7_4 -
3
ro, r7
(&meml)3-O
ROL4
<-
<-
CY, rm-l -
rm) x n times, n
A3-0,
x
2
2
x
2
x
0
x
2
x
0
x
2
x
0
x
2
x
0
x
(&mem1)7_4
meml
~-O -
(memlh_4' (memlb-O - A3-0,
(mem1)7_4'" (meml)3_0
2
&meml
A3-0 +- (&memlh_4' (&meml)3_0 +- A3-0,
(&meml)7_4 - (&mem1ho
3
BCD Adjustment
ADJBA
Decimal adjust accumulator alter addition
x
x
x
ADJBS
Decimal adjust· acccumulator alter subtraction
x
x
x
Bit Manipulation
MOVl
8
3
x
CY - slr.bit
3
x
CY +- A.bit
2
CY, X.bit
CY +- X.bit
2
"x
CY, PSWbit
CY -
2
x
saddr.bit, CY
(saddr.bit) - CY
3
CY, saddr.bit
CY -
CY, slr.bit
CY, A.bit
(saddr.bit)
PSWbit
slr.bit, CY
slr.bit +- CY
3
A.bit, CY
A.bit +- CY
2
X.bit, CY
X.bit +- CY
2
PSWbit, CY
PSW.bit- CY
2
x
x
NEe
IIPD78K2 Product Line
Instruction Set (cant)
Flags
Mnemonic
Operand
Bytes
Operation
Z
AC CY
Bit Manipulation (cont)
AND1
ORI
XORI
SETI
CLRt
CY, saddr.bit
CY
<-
CY 1\ (saddr.bit)
3
x
CY, Isaddr.bit
CY
+-
CY 1\ (saddr.bit)
3
x
CY, sfr.bit
CY <- CY 1\ sfr.bit
3
x
CY, Isfr.bit
CY <- CY 1\ sfr.bit
3
x
CY, Abit
CY
CY 1\ A.bit
2
x
CY, IAbit
CY .... CY 1\ A.bit
2
x
CY, X.bit
CY .... CY 1\ X.bit
2
x
CY, /X.bit
CY <- CY 1\ X.bit
2
x
CY, PSW.bit
CY <- CY 1\ PSW.bit
2
x
CY, IPSW.bit
CY
CY 1\ PSW.bit
2
x
CY, saddr.bit
CY <- CY V (saddr.bit)
3
x
CY, Isaddr.bit
CY <- CY V (saddr.bit)
3
x
CY, sfr.bit
CY <- CY V sfr.bit
3
CY, Isfr.bit
CY <- CY V sfr.bit
3
CY, A.bit
CY <- CY V A.bit
2
CY, IA.bit
CY +- CY V A.bit
2
CY, X.bit
CY +- CY V X.bit
2
CY, /X.bit
CY
<-
CY V X.bit
2
CY, PSW.bit
CY
+-
CY V PSW.bit
2
x
x
x
x
x
x
x
CY, IPSW.bit
CY
+-
CY V PSW.bit
2
x
CY, saddr.bit
CY
+-
CY'if (saddr.bit)
3
x
CY, sfr.bit
CY <- CY 'if sfr.bit
3
x
CY, Abit
CY <- CY 'if Abit
2
x
CY,X.bit
CY <- CY'ifX.bit
2
x
CY, PSW.bit
CY
2
x
saddr.bit
(saddr.bit)
sfr.bit
sfr.bit
Abit
A.bit <- 1
X.bit
X.bit <- 1
PSW.bit
PSW.bit
CY
CY<-1
+-
<-
<-
Cy'if PSW.bit
+-
saddr.bit
(saddr.bit)
sfr.bit
sfr.bit
A.bit
X.bit <- 0
PSW.bit
PSW.bit
CY
CY
+-
0
2
2
+-
2
1
+-
0
x
x
x
x
x
2
3
2
0
A.bit
2
3
0
X.bit
+-
t
1
+-
<-
+-
2
0
2
x
0
9
•
NEe
pPD78K2 Product Line
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
Z
AC CY
Bit ManIpulation (cont)
saddr.bit
(saddr.bit) .... (saddr.bit)
3
sfr.bit
sfr.bit .... sfr.blt
3
A.bit
A.bit- A.bit
2
X.bit
X.bit .... X.bit
2
PSW,blt
PSW,bit .... PSW,blt
2
CY
Cy .... CY
laddr16
(SP-1) .... (PC + 3)H,
(SP - 2) - (PC + 3)l,
PC .... addr16, SP .... SP - 2
3
rp
(SP - 1) .... (PC + 2)H,
(SP - 2) - (PC + 2)l,
PCH - rpH, PCl - rPl, SP - SP - 2
2
CALLF
laddr11
(SP - 1) - (PC + 2)H, (SP - 2) - (PC + 2)l,
PC 15-11 - 00001, PC10-O .... addr11, SP .... SP - 2
2
CALLT
[addr5)
(SP - 1) - (PC + l)H, (SP - 2) - (PC + llL,
PCH'" (2 x addr5 + 41H), PCl - (2 x addr5 + 40H),
SP-SP-2
NOT1
x
x
x
x
Call/Return
CALL
BRK
(SP - 1) - PSw, (SP - 2) - (PC + l)H,
(SP - 3) - (PC + l)l,
PCl - (003EH),
PCH - (003FH), SP - SP - 3, IE ... 0
RET
PCl - (SP), PCH -
RET1
PCl .... (SP) , PCH ... (SP + 1), PSW SP - SP + 3, NMIS - 0
RETB
PCl'" (SP), PCH - (SP + 1),
PSW .... (SP+2), SP - SP + 3
(SP + 1), SP - SP + 2
(SP +2),
R
R
R
R
R
R
R
R
R
Stack Manipulation
PUSH
POP
MOVW
PSW
(SP-1) -
sIr
(SP-1) - sIr, SP - SP-1
rp
(SP-1) .... rpH, (SP-2) - rpl, SP - SP-2
Psw, SP - SP-1
PSW
psw - (SP), SP - SP + 1
sIr
sIr -
(SP), SP - SP + 1
2
2
rp
rpl .... (SP) , rpH -
SP, #Word
SP - word
4
SP,AX
SP-AX
2
(SP +1), SP - SP + 2
AX,SP
AX .... SP
2
INCW
SP
SP-SP+1
2
DECW
SP
SP-SP-1
2
10
NEe
pPD78K2 Product Line
Instruction Set (cant)
Flags
Mnemonic
Operand
Operation
Bytes
Z
AC CY
Unconditional Branch
BA
!addr16
PC
+-
addr16
3
$addr16
PC
+-
PC
+ 2 + jdisp8
2
$addr16
PC
+-
PC
+2 + jdlsp8 If CY = 1
2
--BNL
BNC
$addr16
PC
+-
PC
+2 + jdlsp8 if CY = 0
2
-----
BZ
$addr16
PC
+-
PC
+2 + jdlsp8 If CZ = 1
2
-----
BNZ
$addr16
PC +- PC
+2 + jdlsp8 If CZ = 0
2
BT
saddr.bit, $addr16
PC
+3 + jdisp8
3
sfr.bit, $addr16
PC +- PC
A.bit, $addr16
PC .... PC
X.bit, $addr16
PC +- PC
PSWbit, $addr16
PC .... PC
+ 4 + jdisp8 if sfr.blt = 1
+ 3 + jdlsp8 if A.blt = 1
+ 3 + jdisp8 if X.bit = 1
+ 3 + jdlsp8 if PSWbit = 1
saddr.bit, $addr16
PC +- PC
+4 + jdlsp8 If (saddr.blt) = 0
4
sfr.bit, $addr16
PC
+-
PC
4
A.bit, $addr16
PC
+-
PC
X.bit, $addr16
PC
+-
PC
PSWbit, $addr16
PC
+-
PC
+ 4 + jdlsp8 If sfr.blt = 0
+ 3 + jdisp8 If A,blt = 0
+ 3 + jdisp8 If X.bit = 0
+ 3 + jdlsp8 If PSIN.bit =
+-
PC
-----------------------------------------------------------------------------rp
PCH +- rPH, PCl +- rPl
2
Conditional Branch
BC
BL
BE
BNE
BF
BTCLA
DBNZ
+-
PC
if (saddr.bit) = 1
4
3
3
3
3
3
0
+4 + jdisp8 if (saddr.blt) = 1 then reset (saddr.bit)
4
4
PC
+ 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit
+ 3 + jdisp8 if A.bit = 1 then reset A.bit
+-
PC
+
3
<-
PC
+ 3 + jdisp8 if PSIN.bit =
saddr.blt, $addr16
PC
sfr.bit, $addr16
PC .... PC
A.bit, $addr16
PC
+-
X.bit, $addr16
PC
PSW.bit, $addr16
PC
r1, $addr16
r1 ..... r1 - 1, then PC ..... PC
saddr, $addr16
(saddr) ..... (saddr) - 1, then PC .... PC
3
•
3
+ jdisp8 if X.blt = 1 then
3
reset X.bit
3
1 then reset PSWbit
+ 2 + jdisp8 if r1
+
3
+ jdisp8 if (saddr)
x
x
x
2
"0
" 0
3
CPU Control
MOV
STBC, #byte
STBC
SEL
ABn
RBS1-0 ..... n, n =0-3
+-
byte
NOP
No Operation
EI
IE .... 1 (Enable Interrupt)
01
IE
+-
4
2
0 (Disable Interrupt)
11
N·EC
pPD78K2 Product Line
Interrupt Vectors: (,£PD78214, I'PD78218, I'PD78238, and I'PD78244 Families)
Default
Priority
Level
(Note 1)
Signal Name
Interrupt
Source
Register
Flag
Mask
Flag
Service
Mode
Priority
Flag
Vector
Table
Address
Macro
Service
Type
Macro
Service
Mode Reg.
Address
Software
BRK Instruction
None
Software
None
External signal
None
Nonmaskable
None
NMI (pin input edge)
Maskable
PIFO
PMKO
PISMO
PPRO
0OO6H
A,B
FECBH
INTPl (pin input
edge)
PIFl
PMKl
PISMl
PPRl
0OO8H
A,B
FEC6H
2
INTP2 (pin input
edge)
PIF2
PMK2
PISM2
PPR2
OOOAH
A, B
FEC4H
3
INTP3 (pin input
edge)
PIF3
PMK3
PISM3
PPR3
OOOCH
B
FEC2H
4
INTCOO (TMO·CROO
match signal)
CIFOO
CMKOO
CISMOO
CPROO
0014H
B
FE DOH
5
INTCOl (TMO·CROl
match signal)
CIFOl
CMKOl
CISMOl
CPROl
0016H
B
FECEH
6
INTC10 (TM1·CR10
match signal)
CIF10
CMK10
CISM10
CPR10
0018H
A,B,C
FED8H
7
INTC11 (TM1·CRll
match signal)
CIFll
CMK11
CISMll
CPR11
00lAH
A,B,C
FED6H
a
INTC2l (TM2·CR2l
match signal)
a·bit timer/counter 2
CIF2l
CMK21
CISM21
CPR21
00lCH
A,B
FECAH
9
INTP4 (pin input
edge)
External signal
PIF4
PMK4
PISM4
PPR4
OOOEH
B
FED4H
0
INTPO (pin input
edge)
1
INTC30 (TM3·CR30
match signal)
10
INTP5 (pin input
edge)
INTAO (AID
conversion complete)
External signal
l6·bit timer 0
8·bittimerl
B·bit timer 3
External signal
A,B
PIF5
PMK5
PISM5
PPRS
0010H
AID converter
B
FED2H
A, B
11
INTC20 (TM2·CR20
match signal)
B·bit timer/counter 2
CIF20
CMK20
CISM20
CPR20
0012H
A, B
FECDH
12
INTSER
(asynchronous serial
receive error)
Asynchronous
serial
interface
SERIF
SERMK
-
SERPR
0020H
None
None
13
INTSR (asynchronous
serial receive
complete)
SRIF
SRMK
SRISM
SRPR
0022H
A,B
FEDEH
14
INTST (asynchronous
serial transmit
complete)
STIF
STMK
STISM
STPR
0024H
A, B
FEDCH
15
INTCSI (clocked serial
interface transfer
complete)
CSIIF
CSIMK
CSIISM
CSIPR
0026H
A,B
FEDAH
12
Clocked serial
interface
NEe
IIPD78K2 Product Line
Interrupt Vectors: (p.PD78214, p.PD78218, p.PD78238, and I'PD78244 Families) (cont)
Default
Priority
Level
(Note 1)
Signal Name
Interrupt
Source
Register
Flag
Mask
Flag
Service
Mode
Priority
Flag
Vector
Table
Address
Macro
Service
Type
Macro
Service
Mode Reg.
Address
16
INTEER (EEPROM
error)
(J1PD78244 family
only)
EEPROM
EERIF
EERMK
-
EERPR
0028H
None
None
17
INTEPW( EEPROM
write)
(J1PD78244 family
only)
EEPROM
EPWIF
EPWMK
-
EPWPR
002AH
None
None
Notes:
(1) The default priority is a fixed numeric value indicating which
interrupt takes precedence when more than one interrupt with
the same priority has simultaneously occurred.
Interrupt Vectors: (p.PD78224 Family)
Default
Priority
Level
(Note 1)
Signal Name
Interrupt
Source
Register
Flag
Mask
Flag
Service
Mode
Priority
Flag
Vector
Table
Address
Macro
Service
Type
Macro
Service
Mode Reg.
Address
Software
None
BRK instruction
Software
None
Nonmaskable
_N_on_e__
~_N_M_I~(~pi_n_in~p_u_t_e_dg~e~)__~_E_x_t_e_rn_a_IS_ig~n_a_I__~______~____~______~____~______~______~___N_on_e___ ~
Maskable
PIFO
PMKO
-
PPRO
0OO6H
INTPI (pin input
edge)
PIF1
PMK1
-
PPRI
0OO8H
None
None
2
INTP2 (pin input
edge)
PIF2
PMK2
-
PPR2
OOOAH
None
None
3
INTP3 (pin input
edge)
PIF3
PMK3
-
PPR3
OOOCH
None
None
4
INTCOO (TMO·CROO
match signal)
CIFOO
CMKOO
-
CPROO
0014H
None
None
5
INTCOI (TMO-CROI
matoh signal)
CIFOI
CMK01
-
CPROI
0016H
None
None
6
INTC10 (TM1-CR10
match signal)
CIF10
CMK10
CISM10
CPR10
0018H
A,B,C
FED8H
7
INTC11 (TM1-CR11
matoh signal)
CIF11
CMK11
CISMll
CPRll
001AH
A,B,C
FED6H
8
INTC21 (TM2·CR21
match signal)
8-bit timer/counter 2
CIF21
CMK21
-
CPR21
001CH
None
None
9
INTP4 (pin input
edge)
External signal
PIF4
PMK4
PISM4
PPR4
OOOEH
B
FED4H
10
INTP5 (pin input
edge)
PIF5
PMK5
-
PPR5
0010H
None
None
11
INTP6 (pin input
edge)
CIF20
CMK20
-
CPR20
0012H
None
None
0
INTPO (pin input
edge)
1
External signal
16·bit timer 0
8·bittimer 1
None
13
NEe
pPD78K2 Product Line
Interrupt Vectors'· (jlPD78224 Family) (cont)
Default
Priority
Level
(Note 1)
Signal Name
Macro
Service
Type
Macro
Service
Mode Reg.
Address
Interrupt
Source
Register
Flag
Mask
Flag
Service
Mode
Priority
Flag
Vector
Table
Address
Asynchronous
serial
Interface
SERIF
SERMK
-
SERPR
0020H
None
None
12
INTSER
(asynchronous serial
receive error)
13
INTSR (asynchronous
serial receive
complete)
SRIF
SRMK
SRISM
SRPR
0022H
A,S
FEDEH
14
INTST (asynchronous
serial transmit
complete)
STIF
STMK
STISM
STPR
0024H
A,S
FEDCH
15
INTeSI (clocked serial
interface transfer
complete)
CSIIF
CSIMK
CSIISM
CSIPR
0026H
A, S
FEDAH
Clocked serial
interface
Notes:
(1) The default priority is a fixed numeric value indicating which
Interrupt takes precedence when more than one Interrupt with
the same priority has simultaneously occurred.
14
NEe
JlPD78K3
NEe
IIPD78K3 Product Line
Section 5
",PD78K3 Product Line
16-/8-Bit, K-Series Microcontrollers
I'PD78312A Family
(pPD78310A/312A/P312A)
i6-/S-Bit, K-Series Microcontrollers
With Real-Time Output Ports
5-a
I'PD78322 Family
(pPD78320/322/P322)
i6-/S-Bit, K-Series Microcontrollers
With AID Converter, Real-Time Output Ports
5-b
I'PD78352 Family
5-c
(pPD78350/352A/P352)
i6-/S-Bit, K-Series Microcontrollers
With Real-Time Output Ports
I'PD78356 Family
(pPD78355/356/P356)
i6-/S-Bit, K-Series Microcontrollers
With AID Converter and Convolution
Capability
5-d
NEe
NEG Electronics Inc.
IIPD78312A Family
(JIPD78310A/312A/P312A)
16-/8-Bit, K-Series Microcontrollers
With Real-Time Output Ports
September 1993
Description
The pPD783i0A, pPD783i2A, and pPD78P3i2A are
members of the K-SerieS® of microcontrollers and are
designed for use in process control. They perform all
the usual process control functions and are particularly well-suited for driving stepping motors and dc
motors in servo loops. The processors include on-chip
memory, timers, input/output registers, and a powerful
interrupt handling facility. The pPD783i0A/3i2A is constructed of high-speed CMOS circuitry and operates
from a single +5-volt power supply.
The input frequency (maximum 12 MHz) is derived from
an external crystal or an external oscillator. The internal processor clock is two-phase, and thus machine
states are executed at a rate of 6 MHz. The shortest
instructions require three states, making the minimum
time 500 ns. The CPU contains a three-byte instruction
prefetch queue, which allows a subsequent instruction
to be fetched during execution of an instruction that
does not reference memory.
Program memory is 8K bytes of mask-programmable
ROM (pPD783i2A only), and data memory is 256 bytes
of static RAM. The pPD783i0A is the ROM less version.
pPD78P3i2A is a prototypi ng chip for pPD783i2A. It has
an on-Chip 8K EPROM instead of a mask ROM.
Features
o Complete single-chip microcontroller
-i6-bitALU
- 8K ROM (pPD783i2A only)
- 256 bytes RAM
-i-bit and 8-bit logic
o Instruction prefetch queue
o i6-bit unsigned multiply and divide
o String instructions
K-Serles is a registered trademark of NEe Electronics, Inc.
e02SO
o Memory expansion
- 8085A bus-compatible
- Total 64K address space
o Large I/O capacity: up to 32 I/O port lines
o Extensive timer/counter system
- Two i6-bit up/down counters
- Quadrature counting
- Two i6-bit timers
- Free-running counter with two i6-bit capture
registers
- Pulse-width modulated outputs
- Timebase counter
o Four-channel 8-bit A/D converter
o Two 4-bit real-time output ports
o Two nonmaskable interrupts
o Eight hardware priority interrupt levels
o Macro service facility for interrupts gives the effect
of eight DMA channels
o Bidirectional serial port
- Either UART or interface mode
- Dedicated baud rate generator
o Watchdog timer
o Refresh output for pseudostatic RAM
o Programmable HALT and STOP modes
o One-byte call instruction
o On-chip clock generator
o CMOS silicon gate technology
o +5-volt power supply
.I
NEe
pPD78312A Family
Ordering Information
Part Number
ROM
Package
Package Drawing
t1PD78310ACW
t1PD78312ACW-xxx
t1PD78P312ACW
ROMless
8Kmask ROM
8KOTPROM
64-pin plastic shrink DIP
P64C-70-750 A,C
t1PD78310AGF-3BE
t1PD78312AGF-xxx-3BE
t1PD78P312AGF-3BE
ROMless
8Kmask ROM
8Kmask ROM
64-pin plastic QFP
P64GF-100-3B8, 3BE-1
t1PD78310AG0-36
t1PD783l2AGQ-xxx-36
t1PD78P312AGQ-36
ROMless
8KMask ROM
8KOTP ROM
64-pin plastic QUIP
P64GQ-l00-36
t1PD783l0AL
t1PD783l2AL-xxx
t1PD78P3l2AL
ROMless
8K Mask ROM
8KOTPROM
68-pin plastic PLCC
P68L-50A1-1
t1PD78P3l2ADW
EPROM
64-pin ceramic shrink DIP with window (350 mil)
P64DW-70-750A
t1PD78P3l2AR
EPROM
64-pln ceramic QUIP with window
P64RQ-l00-A
xxx Is the ROM code number.
Pin Configurations
64-Pin Shrink DIP lind QUIP. Pillstic lind Cerllmic
POo
VDD
POl
P47 fAD 7
P02
P04
P4efADe
P45fAD5
P44fAD4
P05
P4sfADs
POs
POe
P42/AD2
P07
P4l/ADl
Pl0
PH
P40/ADO
ALE
P12
WR
P1s
iii
P14
RESETIPROG
P15
EA/Vpp
Ple
P57/A1S
P17
P20INMI
P5e/A 14
P21nNTEO
P2iJNTE1
P241TXD
P5a/A 11
PS2/A10
P5lfAg
P251RxD
P2&'SCK
P50/AS
P87 ICLR1IT01
P27/CTS
P8e/CLROITOO
P2i1NTE2
RFSH
pao/CIO
P8l/CTRLO
P8l!(Cll
P8a1CTRL1
Xl
X2
Vss
2
P5s /A1S
P54 /A12
P8S/PWMl
P84/PWMO
AVss
AVREF
AN3
AN2
AN1
ANO
NEe
pPD78312A Family
Pin Configurations (cont)
64-Pin Plastic QFP
....
"' .... Cf)"I ...
fDlI)
....
O')C\I
§~~~~~
",.j'''''Cf)C'\rI
oc ....
f f f f f f >0:: ::
Q;, :: :: ::
POa
P4,.,AD,
P07
P40/ADO
P10
ALE
P',
P12
WR
PIa
RESETIPROG
P14
EA/VPP
PIS
P57 /At5
PIa
P5a/At4
RD
P17
P5s/A13
P201NMI
P2,nNTEO
P54/A'2
P22nNTEl
P52/A'0
P23nNTE2
P5,/Ag
P24/TxD
P50/Aa
P2stRxD
P37/CLRlrrOl
P2e/scK
P3aICLROITDO
P27/CTS
P3sIPWMl
RFSH
P341PWMO
P53 /Atl
.-
8iij~)(
~ >gj~i~i 11::::
Ibgj
..
C\I
f ~ f ...
f
f
!
~
3
NEe
pPD78312A Family
Pin Configurations (cant)
6B-Pin PLCC (plastic Leaded Chip Carrier)
P40'ADo
P07
ALE
WR
RD
RESETIPROG
EANpp
P57"A15
P5&'A14
P5sfA1a
P54fA12
P5a1A11
f'52IA10
'P51/A9
NC
P10
P11
P12
P1a
P14
P1s
P1e
P17
P20INMI
P2111NTEO
P2211NTE1
P2aIINTE2
P2.4fI'xD
P2sJRxD
P2&'SCK
P27/CTS
4
28
~~~g~~~~~m~m~~~~~
45
44
P5Q1A a
P37/CLR1fT01
PaatCLRorroo
NEe
IIPD78312A Family
Pin Identification
Symbol
Function
ANO-AN3
ND converter inputs
ALE
Address latch enable output
ENVpp
External access control input; programming
voltage
I/O portO
P1r P10
I/O port 1
P20INMI
Nonmaskable interrupt input
P21- P2a1
INTEO - INTE2
Maskable interrupt inputs
P2.vTxD
I/O port 2; serial transmit output
P251RxO
I/O port 2; serial receive input
P2slSCK
I/O port 2; serial clock output
I/O port 2; clear to send input
P301CIO
Up/down counter 0 input
Up/down counter 0 control input
Up/down counter 1 input
P3a1CTRLl
Up/down counter 1 control input
P3.vPWMO
I/O port 3; pulse width modulated output 0
P351pWMl
I/O port 3; pulse width modulated output 1
P3s1CLRO/TOO
I/O port 3; counter 0 clear input timer 0 output
I/O port 3; counter 1 clear input; timer 1 output
I/O port 4; external address/data bus
PSr - PSofA 15 - As
I/O port 5; high address byte output
RO
Read st robe output
RESE17PROG
External reset input; PROM programming mode
RFSH
Refresh output
WR
Write strobe output
XI
External crystal or external clock input
X2
External crystal
NO reference voltage
AVss
Analog ground
Voo
Power supply
Vss
Power return
Pin Functions
ANO - AN3 (A/D Converter Inputs). ANO - AN3 are the
four program selectable input channels for the AID
converter.
ALE (Address Latch Enable). ALE is the address latch
enable. It is to be used by external circuitry to latch the
low-order 8 address bits during the first part of a read
or write cycle.
EANpp. On pPD78312A, a low on EA enables use of
external memory in place of on-chip ROM. The EA pin
must be low on pPD78310A. On the pPD78P312A, this
pin is used for programming voltage. In normal operation, it must be connected to VOD.
P0 7 - POo (Port 0). Port 0 consists of 8 bits, individually
programmable for input/output or two 4-bit real-time
(timer controlled) output ports.
P1 7 - P1 0 (Port 1). Port 1 consists of 8 bits, individually
programmable for input/output.
P201NMI (Port 2; Nonmaskable Interrupt). Port P20 is
dedicated to NMI, the nonmaskable external interrupt
request.
P21 - P2a!INTEO-INTE2 (Port 2; Maskable
Interrupts). Ports P21 - P23 are dedicated to INTEO,
INTE1, and INTE2, the maskable external interrupt
,
requests.
.P24/TxD (Port 2; Serial Transmit). P~ is an I/O port bit ~
or the transmitted serial data output.
P2s/R xD (Port 2; Serial Receive). P25 is an I/O port bit
or the received serial data input.
P2s/SCK (Port 2; Serial Clock). P2s is an I/O port bit or
the serial shift clock output.
P27/CTS (Port 2; Clear to Send). P27 is an I/O port bit
or clear-to-send input (external serial transmission
control) in the asynchronous communication mode. In
the serial I/O interface mode, it becomes the serial
receive clock I/O pin.
5
pPD78312A Family
P301CI0 (Port 3; Counter 0). Port P30 is dedicated to
CIO, the external count input for up/down counter O.
P31/CTRLO (Port 3; Counter 0 Control). Port P30 is
dedicated to CTRLO, the external control input for
up/down counter O.
P321C11 (Port 3; Counter 1). Port P3:! is dedicated to
C11, the external count input for up/down counter 1.
P331CTRL 1 (Port 3; Counter 1 Control). Port P33 is
dedicated to CTRL 1, the external control input for
up/down counter 1.
P3,JPWMO (Port 3; Pulse Width 0). P34 is an I/O port
bit or the pulse-width modulated output o.
P3s/PWM1 (Port 3; Pulse Width 1). P3s is an I/O port
bit or the pulse-width modulated output 1.
P3a/CLRO/TOO (Port 3; Counter 0 Clear; Timer 0). P3a
is an I/O port bit, or the clear input for up/down counter
0, or the timer 0 flip-flop output.
P37/CLR1/T01 (Port 3; Counter 1 Clear; Timer 1).
P37 is an I/O port bit, or the clear input for up/down
counter 1, or the timer 1 flip-flop output.
P40 - P47/ADo - AD7 (Port 4; External Address/Data
Bus). Port 4 consists of 8 bits, programmable as a unit
for input or output, or as the multiplexed address/data
bus if external memory or external interface circuitry is
used. The port is controlled by the memory mapping
registet If the EA pin is low, port 4 is always an
address/data bus.
P50 - P57/Aa - A1S (Port 5; High-Address Byte). Port 5
consists of 8 bits, individually programmable for input
or output, or the high-order address bits for external
memory. Under control of the memory mask register,
bits PSa - P50 are used for 4K memory expansion, bits
P5s - P50 for 16K memory expansion, or bits P~ - P50
for56K memory expansion. 1fthe EA pin is low, port 5 is
always the high-order address bus.
6
NEe
RD (Read Strobe). RD is the read strobe output. It is to
be used by external memory (or data registers) to
place data on the I/O bus during a read operation.
RESET/PROG. This pin is used for the external reset
input. A low level sets all registers to their specified
reset values. During programming of the J.lPD78P312A,
this pin is used to place the device into PROM programmingmode.
'FiFSH (Refresh). RFSH is the refresh pulse output to be
used for external pseudostatic RAM.
WR (Write Strobe). WR is the write strobe output. It is
to be used by external memory (or data registers) to
latch data from the I/O bus during a write operation.
X1, X2 (External Crystal or Clock Input). X1 and X2
are the external oscillator inputs or the connections for
an external crystal. If an external clock is used, it is
connected to X1 and its inverse is connected to X2. The
system clock frequency is half the input frequency.
AVREF (A/D Reference Voltage). AVREF isthe reference
voltage input for the A/D convertet
AVss (Analog Ground). AVss is the analog ground pin.
Vee (Power Supply). VDD is the positive power supply
input.
Vss (Power Return). Vss is the power supply return,
normally ground.
NEe
pPD78312A Family
Block Diagram
P2QlNM1
P21I1NTEO
P22f1NTE1
.~NTE2
P3ofCIO
P311CTR1..O
P3:2fCI1
P3sfCTRL1
P3dCLRO
I'37fCLR1
X1
X2
Gan
I
RegIster I
Storage & I
Macro Sve :
----,
Channels I
P21I1NTEO
P22"1NTE1
RESET
SS! Ii5'
VDD
III
1 ;;: l
VSS
P34/PWMO
P3&'J'WM1
Six 8-BIt VO Ports
Port 1 Dedicated
AD OIhers Shared
AVss
PO
P1
P2
P3
P4
P5
8SR<>0466B (111'93)
7
NEe
pPD78312A Family
FUNCTIONAL DESCRIPTION
On-chip features designed to facilitate process control
include two 16-bit timers, quadrature counting, two
16-bit up/down counters, two pulse-width modulated
outputs, a free-running counter with two capture registers, two 4-bit real-time (timer-controlled) output ports,
an 8-bit AJD converter with four input channels, a
timebase counter to generate widely spaced interrupts,
and a watchdog timer to guard against infinite program loops.
Figure 1_ MemoryMap
FFFFH
FEOOH
Addressing
ThepPD78312A family features 1-byte addressing ofthe
special function registers and 1-byte addressing of the
internal RAM. There are nine modes of addressing main
memory, including autoincrement, autodecrement, indexing, and double indexing. There are 8- and 16-bit
immediate operands.
External Memory
External memory (figure 1) is supported by I/O port 4,
an 8-bit multiplexed address/data bus. The memory
mapping register controls the size of external memory
as well as the number of additional wait states. Highorder address bits are taken from I/O port 5 as required.
No bits are required for 256 bytes of external memory;
bits P53 - P50 are used for 4K bytes, P5s - P50 for 16K
bytes, and P5-, - P50 for 56K bytes. Any remaining port 5
bits are available for I/O.
Refresh
The pPD78312A has a refresh signal for use with the
pseudostatic RAM. The refresh cycle can be set to one
of four intervals ranging from 2.67 to 21.3ps. The
refresh is timed to follow a read or write operation so
that there is no interference.
8
Special FuncUon
FFOOH
----r---
FE80H
Storage -II Intemal
___
Reglste/S
"
,
I
RegIster
,,
,
In addition, a serial I/O port can be used in either an
interface mode or an asynchronous communication
mode. HALT and STOP modes are provided to conserve
power at times when CPU action is not required.
All I/O, timer, and control registers are defined as
special function registers and assigned addresses in
the top 256 bytes of memory. The special function
registers may be operated on directly by many of the
arithmetic, logic, and move instructions of the CPU.
Table 1 describes the registers.
FFFFH
r _____ _
Extemal
Memory Only
AvaDable
I RAM
\..!'~OO..!:lJ...-Sto_I8_ge-L1 _ _...I
{OFFFH
I
I
I
I
CalIF Area
I
I
I
0800H
1--------
I
lFFFH
I
r------
I
I
Intemal
ROM
I
I
!,PD78312A
or
OFFFH
r------
J
PROM
!,PD78P312A
OOOOH " -_ _ _ _..1-
I
007FH /- _ _ _ _ _ _ _
Table
Area
0040H /- CalIT
___
__
__
_ _ _~O_H"'__y,_ecto_rT_ab_le_A_re_a......
83RC!'~_1. _E.£R~2!..
\
\
OE[RP8)
\
\
\
\
,..! ~~_1. _L.!.R~!..
Pulse·Width Modulated Outputs
HL[RP7]
83~
Program Status Word
Following is the program status word format.
I
IE
0
o
8
15
s
I
z
I
RSS
AC
UF
P/V
SUB
RB2- RBo
IE
S
Z
RSS
AC
UF
PN
SUB
CY
I
o
7
Cy
I
Active register bank number
Interrupt enable
Sign (1 if last result was negative)
Zero (1 if last result was zero)
Register set select
Auxiliary carry (carry out of 3rd bit)
User flag
Parity or arithmetic overflow
Subtract (1 if last operation was
subtract)
Carry
The two independent pulse-width modulated outputs
are controlled by two 16-bit modulus registers and . counters. There are four programmable repetition rates
~
ranging from 91.6 Hzto 23.4 MHz. Figure 3 shows one of
•
these outputs.
Timers
The pPD78312A has two 16-bit timers. The inputs to
these timers may be the internal clock divided by 6;
12(TMO) or 128. Each timer has an associated modulus
register to store the timer count. The timer counts down
to zero, sets a flag, reloads from the modulus register,
and then counts down again. The timer flags can be
used under program control to generate interrupt requests and/or a square-wave output. TMO also functions optionally as two one-shot timers.
Figure 4 is a diagram of the interval timers.
There is a free-running counter that counts the internal
clock divided by 4 or by 16. The counter has two 16-bit
capture registers. Capture is triggered by an external
interrupt request or by the up/down counter clock.
The timebase counter generates a signal at one of four
intervals ranging from 170 ps to 175 ms. The signal can
be used to generate an interrupt request and/or an
up/down counter capture.
9
NEe
IIPD78312A Family
Figure 3. Pu/s.Width Modulated Output
r---------------,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
!CLKi258
!CLK/1024
! CLK/4098
!CLKI85538
PWMO
Q
I
I
I
I------'-<~s
I
I
I
R
!ClK
I
I
I
r----------------o PVVM1
I
IL _______________
I
~
Figure 4. Timer Block Diagram
r----------------------------------------------------,
I
I
I
I
I
I
T01
!CLK/128
!CLK/12
fClKI128
!CLK/S
!CLK/12
!CLK/128
TOO
L-------------]1-------------------------------------~
\
10
Internal Bus
NEe
IlPD78312A Family
Up/Down Counters
The J.lPD78312A has two 16-bit up/down counters, each
of which has two capture/compare registers. There are
three modes of operation: compare and interrupt, capture on external command, and capture on timebase
counter command. There are five sources of counts:
the internal clock divided by 3, the external clock,
external independent up and down inputs, external
clock with direction control, and external clock with
automatic up/down discrimination. Figure 5 shows an
up/down counter.
Figure 5_ Up/Down Counter Block Diagram
r----------------------------------------------------------,
Cl1~
:
CTRLlC;>
I
CLR16
I
I
I
r----------------------------------------------------------~
I
I
I
I
I
From
I
Tlmebasa
I
Counter
I
Capture
.--...:----.:
1...-_--1 I
CIO
Clear
CLRO
L--_--I:
I
CROO(16)
I
I
I
I
---------------------------------IJ-----------------------~
IntamaiBus
119RM481B(101113)
11
NEe
IIPD78312A Fami'ly
Quadrature Counting
The two up/down counters, UDCO and UDC1, have an
optional quadrature counting mode, which is activated
by specifying mode 4 in the counter unit input mode
register, CUlM. It is designed to count the output of a
two-phase pulsed optical shaft angle encoder. The
input for phase A is the CIO (or C(1) pin, and the input
for phase B is the CTRLO (or CTRL1) pin. The counter
UDCO (or UDC1) is incremented or decremented at
both positive and negative transitions of both input
signals. Whether it is incremented or decremented is
dependent upon the relative phase of the two signals as
illustrated in figure 6.
Figure 6. Counter Operation (Mode 4)
t+------COuntUp.-------I
CIO
(Cll)
i------COuntDown'-----
--tJ
CTRLO
(CTRL1)
UDCO
(UDC1)
83Yl-6837B
Standby Modes
AID Converter
HALT and STOP modes conserve power when CPU
action is not required. In HALT mode, the CPU stops
and the clock continues to run. Maskable interrupts can
restart the CPU.
The AID converter has four input channels and can
operate in either scan or select mode. The AID converter performs 8-bit successive approximation conversions, has a 30-j.ls conversion time, and is triggered
either internally or externally. The AID converter includes an on-Chip sample and hold amplifier.
In STOP mode, the CPU and clock are both stopped. A
RESET pulse or the nonmaskable external interrupt is
required to restart them. There is also the option of
slowing the system clock by a factor of four. The
standby control register controls the standby modes
and is a protected location written to only by a special
instruction.
Watchdog Timer
The watchdog timer protects against inadvertent program loops. A nonmaskable interrupt occurs if the
timer is not reset before a timeout occurs. There are
four program-selectable intervals ranging from 5.5 to
349.3 ms. The watchdog timer can be disabled by
software. The watchdog timer mode register controls
the watchdog timer and is a protected location written
to only by a special instruction.
12
Interrupts
There are two nonmaskable interrupt sources: the external nonmaskable interrupt and the watchdog timer.
Their relative priorities are software selectable.
There are eight hardware priority interrupt levels, level
ohaving the highest priority and level7the lowest. The
15 maskable interrupt sources (table 2) are divided into
five groups, and each group can, under program contrOl, be assigned to any one of the priority levels.
Interrupts may be serviced by routines entered either
by vectoring or by context switching. Context switching automatically saves all the general registers, the
NEe
,.,PD78312A Family
program status word, and the program counter. Figure
7 illustrates the mechanism of context switching.
Figure B. Macroservice Pointer Addresses
15
Finally, an optional macro service function transfers
data between any one special function register and
memory without program intervention.
o
7
FEE3H
SFRP4
FEE7H
SFRP5
I
FEEOH} 4
MSC4
MSP5
Figure 7. Hardware Context Switching
CurrentAcUve Register
Bank
8
MSP4
New AcUve Register
Bank
AX
AX
BC
BC
Register
Bank 1
I
FEE4H }
MSCS
MSP6
FEEBH
SFRP6
FEEFH
SFRP7
I
RP2
PC
~
PSW
Save Area
UP
DE
HL
HL
SFRPO
FEF7H
SFRP1
Register
BankO
UP
DE
FEECH} 7
FEEEH
I
I
MSCO
FEFOH}
FEF2H
0
MSP1
VP
VP
FEF3H
FEF4H} 1
MSC1
MSP2
FEFBH
SFRP2
FEFEH
SFRP3
I
Program
Counter
FEF6H
FEF8H} 2
MSC2
MSP3
I
FEEAH
MSC7 '
MSPO
Save Area
RP3
I
5
FEE6H
FEE8H} 6
MSC6
MSP7
Save
FEE2H
FEFAH
FEFCH} 3
MSC3
FEFEH
Note:
[1]lhe macro service pointers share storage WIth register banks 0 and 1.
[2] MSP=Memory address pointer
SFRP=Speclal funcUon register pointer
bLoad
Program
Status Word
. .
..R<>9472A
O.BV
LE-x-te-r-n-a-,-C-,-O-C-k--------------'''---..;:;.;.J
Count Timing Specification (Mode 4)
!+------ICYC4 ----~
CIO
(Cll)
Xl
IH4CTCI~-~
CTRLO
(CTRL1)
___
IS4CTCI-to~--l~
~---ICYK--~~
B3RC-9473A
-"
B3R1>947OA
Data Retention Timing
VOO
~:VOO
~_v..;;o..;;o_ __
IFVO
=1[
IRVO
83RC-9474A.
25
. '
•
,
NEe
"PD78312A Famil y
PROM PROGRAMMING
Pin Functions, PROM Programming Mode
The PROM inthepPD78P312A is an OTP orUVE EPROM
with an 8,192 x 8-bit configuration. The pins listed in
the table below are used to program the PROM.
64-Pin Shrink DIP and QUIP, Plastic and Ceramic
...{
When used in the normal operation mode,S V ±10% is
applied to the Voo and Vpp pins. A voltage higher than
Voo should not be applied to other pins.
The programming characteristics of the pPD78P312A
are identical to those of the pPD27C256A.
Pin
Function
vpp
High voltage input (write/verify mode),
high·level input (read mode)
PROG
High voltage input (write/verify mode, read mode)
Open {
Address input (upper 8 bits)
Data input (write mode), data output (verify mode)
Program pulse input
OE
Output enable Input
Voo
Power supply pin
Notes:
(1) Mask the window olthe UVE EPROM version to protectthe PROM
from being erased accidentally.
(2) The OTP EPROM version cannot be erased by ultraviolet rays
because it does not have a window.
os
04
03
CE
02
OE
01
AO
A1
00
A2
} Open
PROG
A4
AS
AS
vpp
A7
} Open
'M{
A12
-{
AS
AS
,~{
Programming Setup
Programming socket adaptors PA-78P312CW/GF/GQ/l
are used to configure the pPD78P312A to fit a standard
PROM socket. Set the PROM programmer to program
the 27C256A. If the PROM programmer is an older
model, check that the programming voltage does not
exceed 12.5 volts.
07
De
A3
Address input (lower 8 bits)
CE
voo
A11
A10
}~
},~
Open
vSS
NoIe8:
(1)
VSS:
Ground this pIn.
[2] Open: 00 not connect this pin.
83YL-eB41A
26
NEe
IIPD78312A Family
Pin Functions, PROM Programming Mode (cont)
64-Pin Plastic QFP (bent leads)
CE
01
OE
DO
AD
A1
}open
AA
Vpp
PROG
AS
}open
~P078P312AGF
A7
11
Vss {
A12
A11
A10
A9
-{
AS
}Open
Not. .:
Vss: GIIIUnd this pin
Open: Do not connect this pin
Z7
NEe
pPD78312A Family
Pin Functions, PROM Programming Mode (cant)
6B-PinPLCC
OE
DO
0
ArJ
A1
} Open
A2
1<3
A4
AS
PROG
VPP
AIJ
A7
} Open
~PD78P312AL
~{
-{
A12
A11
A10
AS
Ie
A8
28~
re
Iii 'Co
0
!ll Ii! ;; III t:l ~ til III :;; III
$
~!'
,
rn
~
m~
:t
} Open
~
!;i44
/ '--r-'
IiiCo
0
Notes:
[1) Vss: Ground this pin.
[2) Open: Do not COM8Ct this pin.
83YL-8843B
28
NEe
pPD78312A Family
PROM Programming Mode
When + 6 V is applied to the Voo pin and + 12.5 V is
applied to the PROG pin and Vpp pin, the IlPD78P312A
enters the program write/verify mode. Operation in this
mode is determined by the setting of CE and OE pins
as indicated in the table below.
Mode
CE
OE
Vpp
V DD
PROG
Write
L
H
+12.5 V
+6V
+12.5 V
Verify
H
L
Program inhibit
H
H
Read (Note 2)
L/H
L
Read (Note 3)
L/H
H
(5) Use the verify mode to test the data. If the data has
been written, proceed to (7), if not, repeat steps (3)
to (5). If the data cannot be correctly written in 25
attempts, go to step (6).
(6) Classify the PROM as defective and cease write
operation.
(7) Provide write data and supply program pulse (for
additional writing) for 3 ms times the number of
repeats performed between steps (3) to (5).
(8) Increment the address.
+5V
+5V
+12.5V
(9) Repeat steps (3) to (8) until the last address is
reached.
PROM Read Procedure
Notes:
(1) When +12.5 V is applied to Vpp and +6V is applied to Voo , both
CE and OE must not be set to the low level (L) simultaneously.
(2) Data is output from the 00.07 pins.
The contents of the PROM can be read out to the
external data bus Do - 07 by using the following procedure.
(3) DO - 0 7 are high impedance.
(1) Set the unused pins as indicated in table 3.
Recommended Conditions for Unused Pins
(2) Supply + 5 V to the Voo pin and Vpp pin, and
+ 12.5 V to the PROG pin.
Table 3 describes how to set unused pins when programming the PROM.
(3) Input the address of the data to be read to the Ao to
A12 pins.
Table 3. Recommended Conditions for
Unused Pins
Pin
Recommended Connection
pOo- P03
Connect to Vss
Open
P20- P23
P25 - P27, RFSH
Connect to Vss
Open
Connect to Vss
X2
Open
ANO-AN3, AVREF, AVss
Connect to vss
P34 - P37, P55 - P5], RO, WR, ALE
Open
PROM Write Procedure
Data can be written to the PROM by using the following
procedure.
(4) Put an active low pulse of at least 1 Ils on the OE
pin.
(5) Data is output to the Do to 07 pins.
•.
Erasure
The UVE EPROM can be erased by exposing the window to light having a wavelength shorter than 400 nm,
including ultraviolet rays, direct sunlight, and fluorescent light. To prevent unintentional erasure, mask the
window.
Typically, data is erased by 254-nm ultraviolet rays. A
minimum lighting level of 15 W s/cm2 (ultraviolet ray
intensity x exposure time) is required to completely
erase written data Erasure by an ultraviolet lamp rated
at 12,OOOIlW/cm2 takes approximately 15to 20 minutes.
Remove any filter on the lamp and place the device
within 2.5 cm of the lamp tubes.
(1) Set the pins not used for programming as indicated
in table 3, and supply +6 V to the Voo pin, and
+ 12.5 V to the Vpp and PROG pins.
(2) Provide the initial address.
(3) Provide write data.
(4) Provide a 1 ms program pulse (active low) to the CE
pin.
29
NEe
pPD78312A Family
DC Programming Characteristics
TA
= 25 ±5"C; VIP = 12.0 ±0.5 V; Vss = 0 V
Parameter
Symbol
Symbol (Note)
Min
Max
Unit
High-level input voltage
VIH
VIIi
2.2
VOOP +0.3
V
-0.3
0.8
Y
10
JiA
Low-level input voltage
VIL
VIL
Input leakage current
YLIP
VlI
High-level output voltage
YOH
YOH
Low-level output voltage
VOL
VOL
Output leakage current
PROG pin high voltage
input current
YOOp power supply
voltage
VOOP
Ypp power supply
voltage
Vpp
Voop power supply
current
100
Ypp power supply current
Ipp
Typ
Condition
Os YI S Yoop
Y
IOH
0.45
V
IOL
ILO
10
IlA
liP
±10
IlA
YOlr1
VOO
Vpp
= -1.0 mA
= 2.0 mA
Os Yo s YOOP. OE
= YIH
5.75
6.0
6.25
V
Program memory write mode
4.5
5.0
5.5
V
Program memory read mode
12.2
12.5
12.8
Y
Program memory write mode
V
Program memory read mode
Ypp
100
Ipp
= VOOP
10
30
mA
Program memory write mode
10
30
mA
Program memory read mode
CE = YIL. YI = VIH
10
30
mA
Program memory write mode
CE = YIL. OE = YIH
100
IlA
Program memory read mode
Notes:
(1) Corresponding symbols for the IlPD27C256A
AC Programming Characteristics
TA
= 25 ±5°C; VIP =
12.0 ±0.5 Y; Vss
=0V
Parameter
2
Ils
Data to OE ~ delay time
tOOOO
toES
2
Ils
Input data setup time to CE I
!sIOC
tos
2
IlS
Address hold time after CE t
tHCA
tAH
2
Ils
Input data hold time after CE t
tHCID
toH
2
Output data hold time after OE t
tHOOO
tOF
0
Vpp setup time before CE I
!svpc
!YPS
2
YOOp setup time· before CE I
!sVDC
!Yos
2
Initial program pulse width
twLl
tpw
0.95
Additional program pulse width
twL2
topw
2.85
PROG high-voltage input setup
time before CE I
!sPC
tOAOO
tACC
OE I to data output time
tOOOO
toE
Data hold time after OE t
tHCOO
tOF
0
Data hold time after address not valid
tHAOO
toH
0
(1) Corresponding symbols for the IlPD27C256A
30
Condition
Ils
130
ns
Ils
IlS
1.0
1.05
ms
78.75
ms
2
Address to data output time
Notes:
Typ
Unit
Symbol (Note)
tAS
~
Min
Max
Symbol
tsAC
Address setup time to CE
Ils
2
Ils
OE = YIL
Ils
130
ns
ns
OE = YIL
NEe
IIPD78312A Family
PROM Write Mode Timing
A12-AO
~
~
07-DO
-
r-
-1
tSAC
~
Data Input
tSIDC~
(
Effective address
--
~
-1
I+- tHOOD
Data output
--
Data Input
tSIDC~
- - tHdlD
t HCA
I+-
~
'-I",
.i
- - tHCID
--.l
~
- - tspc
Vpp
Vpp
V DDP
-.-J
~
~ tsvPC
--.J
~
- - tSVDC
.fL
CE
~
I~
~
ri r::
tDDOO
tWL2
~I
tDOOD
"
5
J
Noles:
(1) VDDP must be applied before VPP Is applied and
must be removed after Vpp Is removed.
(2) V pp must not excead +13 V InclUding overshoot voltage.
SSYl-6844B
PROM Read Mode Timing
)
K
Effective address
----tHooD
!.--IOOODtDAOD
~
IHAOD~
HI-Z
--------------~
Data output
r--
HI-Z
-------83YL-6845B
31
NEe
IIPD78312A Family
INSTRUCTION SET
Instruction Set Symbols (cont)
The pPD78312A family instruction set features 8- and
16-bit data transfer, arithmetic, and logic instructions
and single-bit manipulation instructions. String manipulation instructions are also included. Branch instructions exist to test individual bits in the program status
word, the 16-bit accumulator, the special function registers, and the saddr portion of on-chip RAM. Instructions range in length from 1 to 6 bytes depending on the
instruction and addressing mode.
Symbol
Definition
word
16 bits of immediate data or label
byte
8 bits of Immediate data or label
jdisp8
a·bit two's complement displacement (immediate
data displacement value -128 to +127)
bit
3 bits of immediate data (bit position in byte), or
label
n
3 bits of immediate data
laddr16
16·bit absolute address specified by an immediate
address or label
Flag Column Indicators
Symbol
Action
(blank)
No change
0
Set to 0
Set to 1
X
Set or cleared according to result
P
P/V indicates parity of result
$addrl6
Relative branch address or label
addr16
16·bit address
!addrl1
11·bit immediate address or label
addrll
0800H-OFFFH: 0800H + (11-bit immediate
address), or label
addr5
0040H-007EH: 0040H + 2 X (5'bit immediate
address), or label
V
P/V indicates arithmetic overflow
A
A register (8·blt accumulator)
R
Restored from saved PSW
X
X register
B
B register
C
C register
Definition
D
o register
RO, Rl, R2, R3, R4, R5, R6, R7, R8, R9, RIO, Rll,
R12, R13, R14, R15
E
E register
H
H register
Instruction Set Symbols
Symliol
rl
RO,Rl,R2,R3,R4,R5,R6, R7
r2
C,B
rp
RPO, RP1,RP2,RP3,RP4,RP5,RP6,RP7*
rpl
RPO, RP1, RP2, RP3, RP4,RP5,RP6, RP7*
rp2
DE, HL, VP, UP
sfr
Special function register, 8 bits
sfrp
Special function register, 16 bits
post
RPO, RP1, RP2, RP3, RP4, RP5/PSW, RP6, RP7. Bits
set to 1 indicate register pairs to be pushed!
popped to/from stack; RP5 pushed/popped by
PUSH/POP, SP is stack pointer; PSW pushed/
popped by PUSHU/POPU, RP5 is stack pointer.
RP7
mem
saddrp
32
L register
RO-R15
Register 0 to register 15
AX
Register pair AX (16-bit accumulator)
BC
Register pair BC
DE
Register pair DE
HL
Register pair HL
RPO-
Register pair 0 to register pair 7
PC
Program counter
SP
Stack pointer
UP
User stack pointer (RP5)
Register indirect: [DEI, [HLI, [DE+ I, [HL+ I, [DE-I,
[HL-I, [vPI, [UPI
PSW
Program status word
Base Index Mode: [DE+ AI, [HL+ AI, [DE+ BI,
[HL+ BI, [VP+ DEI, [VP+ HLI
PSWH
High·order 8 bits of PSW
PSWL
Low-order 8 bits of PSW
Base Mode: [DE+ by tel, [HL+ by tel, [VP+ by tel,
[UP+ by tel, [SP+ by tel
CY
Carry flag
AC
Auxiliary carry flag
Z
Zero flag
Index Mode: word [AI, word [BI, word [DE], word
[HLI
saddr
L
FE20-FFI FH: Immediate byte addresses one byte
in RAM, or label
FE20-FF1FH: Immediate byte (bit 0 = 0)
addresses one word in RAM, or label
P/V
Parity/overflow flag
S
Sign flag
TPF
Table position flag
NEe
pPD78312A Family
Instruction Set Symbols (cant)
Symbol
Definition
RSS
Register bank select flag
RSS
Register set select flag
IE
Interrupt enable flag
STSC
Standby control register
WDM
Watchdog timer mode register
( )
Contents of the location whose address is within
parentheses; (+) and (-) indicate that the address
is incremented after or decremented after it is
used
(0)
Contents of the memory location defined by the
quantity within the sets of parentheses
xxH
Hexadecimal quantity
High-order 8 bits and low-order 8 bits of X
• rp and rp1 describe the same registers but generate different
machine code.
33
NEe
pPD78312A Family
Instruction Set
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
AC
PN
CY
SUB
X
X
X
X
X
X
X
X
X
X
X
X
8-Sit Data Transfer
MOV
XCH
n, #byte
r1 - byte
2
saddr, #byte
(aaddr) - byte
3
afr, #byte
afr - byte
3
r,r1
r - r1
2
A, r1
A- r1
A, saddr
A- (saddr)
2
saddr, A
(saddr) - A
2
saddr, aaddr
(saddr) -
3
A, afr
A <-8fr
2
sfr, A
8fr-A
2
A, mem (Note 1)
A- (mem)
A,mem
A- (mem)
mem, A (Note 1)
(mem) -A
(saddr)
2-4
2-4
mem,A
(mem) -A
A, [aaddrp)
A-
((saddrp))
2
[aaddrp), A
«saddrp)) - A
2
A, 'addr16
A-
4
!addr16, A
(addr16) - A
4
PSWL, #byte
PSWL - byte
3
PSWH, #byte
PSWH - byte
3
PSWL,A
PSWL -A
2
PSWH, A
PSWH - A
2
A, PSWL
A- PSWL
2
A, PSWH
A
2
A,r1
A-r1
<-
(addr16)
PSWH
2
r,r1
r ... r1
A,mem
A- (mem)
2-4
A, saddr
A ... (saddr)
2
A, sfr
A-sfr
3
A, [saddrp)
A - «saddrp))
2
aaddr, saddr
(saddr) ... (saddr)
3
16-Sit Data Transfer
MOVW
34
rp1, #Word
rp1 -word
3
aaddrp, #Word
(saddrp) +- word
4
afrp, #Word
sfrp _word
4
rp, rp1
rp -
2
AX, aaddrp
AX -
aaddrp, AX
(saddrp) - AX
2
saddrp, saddrp
(saddrp) ..... (saddrp)
3
rp1
(saddrp)
2
NEe
pPD78312A Family
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
AC
PN
CY
SUB
18·Blt Data Transfer (cont)
MOVW~on~
XOHW
_AX
__'_s_fr_p_________
AX
__-__
sf_rp~______________________________
2 ______________________________
sfrp, AX
sfrp - AX
2
rpl, iaddr16
rpl - (addr16)
4
iaddr16, rp1
(addr16) - rp1
4
AX, saddrp
AX .. (saddrp)
2
AX, sfrp
AX .. sfrp
3
saddrp, saddrp
(saddrp) .. (saddrp)
3
rp, rp1
rp" rp1
2
8·Bit Arithmetic
ADD
ADDO
SUB
_A_,_#_b~y_te_________
A_,O_Y
__-__A__
+_b~y_te__________________________
2 _____
X___X____X
_____V
_____X
______
O__
saddr, #byte
(saddr), OY - (saddr) + byte
3
X
X
X
V
X
sfr, #byte
sfr, OY - sfr + byte
4
X
X
X
V
X
0
r,r1
r,OY-r+r1
2
X
X
X
V
X
0
A, saddr
A, OY-A + (saddr)
2
X
X
X
V
X
0
A, sfr
A, OY -
saddr, saddr
(saddr), OY - (saddr) + (saddr)
A,mem
A, OY -
mem, A
(mem), OY- (mem) + A
A + sfr
A + (mem)
0
3
X
X
X
V
X
0
3
X
X
X
V
X
0
2-4
X
X
X
V
X
0
2-4
X
X
X
V
X
0
_A_,_#_b~yt_e________A_,_O_Y_-_A
__+__
by~t_e_+__
O_Y____________________2_____X___X
____X
_____V_____
X_____
O__
saddr, #byte
(saddr), OY - (saddr) + byte + OY
3
X
X
X
V
X
0
sfr, #byte
sfr, OY - sfr + byte + OY
4
X
X
X
V
X
0
0
r,r1
r,OY-r+r1+0Y
2
X
X
X
V
X
A, saddr
A, OY-A + (saddr) + OY
2
X
X
X
V
X
0
A,sfr
A,OY-A+ sfr+ OY
3
X
X
X
V
X
0
saddr, saddr
(saddr), OY - (saddr) + (saddr) + OY
3
X
X
X
V
X
0
A, mem
A, OY - A + (mem) + OY
2-4
X
X
X
V
X
0
mem, A
(mem), OY - (mem) + A + OY
2-4
X
X
X
V
X
0
A, #byte
A,OY-A-byte
2
X
X
X
V
X
saddr, #byte
(saddr), OY .... (saddr) - byte
3
X
X
X
V
X
sfr, #byte
sfr, OY <-- sfr - byte
4
X
X
X
V
X
r,r1
r,OY-r-r1
2
X
X
X
V
X
A, saddr
A, OY-A- (saddr)
2
X
X
X
V
X
A, sfr
A,OY-A-sfr
3
X
X
X
V
X
saddr, saddr
(saddr), OY .... (saddr) - (saddr)
3
X
X
X
V
X
A, mem
A, OY - A - (mem)
2-4
X
X
X
V
X
mem, A
(mem), OY - (mem) - A
2-4
X
X
X
V
X
lP.!!IIIi,.
~
35
NEe
pPD78312AFamily
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes'
S
Z
AC
PN
CY
SUB
8·Blt Arithmetic (cont)
SUBC
A, #byte
A, CY - A - byte - CY
2
X
X
X
V
X
saddr, #byte
(saddr), CY - (saddr) - byte - CY
3
X
X
X
V
X
sfr, #byte
sfr, CY - sfr - byte - CY
4
X
X
X
V
X
r, rl
r,CY-r-rl-CY
2
X
X
X
V
X
A, saddr
A, CY - A - (saddr) - CY
2
X
X
X
V
X
A, sfr
A, CY -A- sfr- CY
3
X
X
X
V
X
saddr, saddr
(saddr), CY - (saddr) - (saddr) - CY
3
X
X
X
V
X
A,mem
A, CY - A - (mam) - CY
2-4
X
X
X
V
X
mem, A
(mem), Cy .... (mem) - A - CY
2-4
X
X
X
V
X
A, #byte
A-AI\ byte
2
X
X
P
0
saddr, #byte
(saddr) .... (saddr) 1\ byte
3
X
X
P
0
sfr, #byte
sfr - sfr 1\ byte
4
X
X
P
0
r, r1
r-rl\ rl
2
X
X
P
0
A, saddr
A- A 1\ (saddr)
2
X
X
P
0
A, sfr
A-Al\sfr
3
X
X
P
0
saddr, saddr
(saddr)+- (saddr) 1\ (saddr)
3
X
X
P
0
A,mem
A-AI\ (mem)
2-4
X
X
P
0
mem, A
(mem) .... (mem) 1\ A
2-4
X
X
P
0
A, #byte
A-A V byte
2
X
X
P
0
saddr, #byte
(saddr) +- (saddr) V byte
3
X
X
P
0
sfr, #byte
sfr _ sfr V byte
4
X
X
P
0
r,rl
r-rVrl
2
X
X
P
0
0
8·BltLogic
AND
OR
XOR
36
A, saddr
A - A V (saddr)
2
X
X
p
A, sfr
A-AVsfr
3
X
X
P
0
saddr, saddr
(saddr)- (saddr) V (saddr)
3
X
X
P
0
A,mam
A-A V (mem)
2-4
X
X
P
0
mem, A
(mem) _ (mam) V A
2·4
X
X
P
0
A, #byte
A-AVbyte
2
X
X
P
0
saddr, #byte
(saddr) - (saddr) V byte
3
X
X
P
0
sfr, #byte
sfr - sfr V byte
4
X
X
p
0
r,rl
r-rVrl
2
X
X
P
0
A, saddr
A - A V (saddr)
2
X
X
P
0
A, sfr
A-AVsfr
3
X
X
p
0
saddr, saddr
(saddr)- (saddr) V (saddr)
3
X
X
P
0
A,mem
A-A V (mem)
2-4
X
X
p
0
mem, A
(mem) - (mem) V A
2-4
X
X
P
0
NEe
pPD78312A Family
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
AC
PN
CY
X
v
v
v
x
SUB
8-8it Logic (cont)
CMP
A, #byte
A- byte
2
x
saddr, #byte
(saddr) - byte
3
sfr, #byte
sfr- byte
4
X
X
X
X
x
r, r1
r-rl
2
X
X
X
X
v
X
A, saddr
A - (saddr)
2
X
X
x
X
A, sfr
A-str
3
(saddr) - (saddr)
3
X
X
X
saddr, saddr
X
X
A,mem
A- (mem)
2-4
X
X
X
mem,A
(mem) - A
2-4
X
X
X
v
v
v
v
v
X
X
X
X
X
X
X
X
16-8it Arithmetic
ADDW
SUBW
CMPW
3
X
X
X
v
X
o
(saddrp) + word
4
X
X
X
x
+
5
x
x
X
X
o
o
v
v
X
o
X
X
X
X
X
X
X
X
X
o
o
X
v
v
X
o
X
v
X
X
X
2
X
X
X
3
X
X
X
X
v
v
v
v
v
v
v
v
v
v
v
v
X
2
X
X
X
X
X
X
X
X
X
X
v
v
X
v
+ word
AX, #Word
AX, CY +- AX
saddrp, #Word
(saddrp), CY
strp, #Word
strp, CY +- strp
+-
+
word
rp, rpl
rp, CY <- rp
AX, saddrp
AX, CY <- AX
+ (saddrp)
rpl
2
AX, strp
AX, CY <- AX
+ strp
3
2
+
X
X
saddrp, saddrp
(saddrp), CY <- (saddrp)
AX, #word
AX, CY +- AX - word
3
saddrp, #Word
(saddrp), CY <- (saddrp) - word
4
strp, #Word
strp, CY <- strp - word
5
rp, rpl
rp, CY
AX, saddrp
AX, CY <- AX - (saddrp)
AX, strp
AX, CY
saddrp, saddrp
(saddrp), CY +- (saddrp) - (saddrp)
3
X
X
AX, #word
AX-word
3
X
X
X
saddrp, #Word
(saddrp) - word
4
X
X
X
strp, #Word
strp - word
5
X
X
X
rp, rpl
rp- rpl
2
X
X
X
AX, saddrp
AX - (saddrp)
2
AX - strp
3
saddrp, saddrp
(saddrp) - (saddrp)
3
X
X
X
X
X
X
X
AX, strp
<-
(saddrp)
3
rp - rpl
+-
AX - strp
X
X
--
X
X
X
X
X
X
X
X
X
X
X
X
Multiplication/Division
MULU
rl
AX-Ax rl
DIVUW
rl
AX (quotient), rl (remainder)
MULUW
rpl
AX (high-order 16 bits), rpl (low-order 16 bits)
+- AX x rpl
DIVUX
rpl
AXDE (quotient), rpl (remainder)
2
+-
AX
+-
+ rl
AXDE + rpl
2
2
2
37
NEe
pPD78312A Family
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
AC
PN
X
X
X
V
0
2
X
X
X
V
0
X
X
X
V
X
X
X
V
CY
SUB
Increment/Decrement
INC
DEC
INCW
+ 1
rl
rl ... rl
saddr
(saddr) .... (saddr)
rl
rl .... rl-l
+ 1
saddr
(saddr) .... (saddr) - 1
rp2
rp2-rp2
2
+ 1
+
saddrp
(saddrp) .... (saddrp)
rp2
rp2-rp2-l
saddrp
(saddrp) .... (saddrp) - 1
ROR
rl. n
(CY, r17 .... rlo. rlrn-l .... rlml x n times
2
P
X
0
ROL
rl. n
(CY. rl0 .... r17. rlm+ 1 .... rlm) x n times
2
P
X
0
RORC
rl. n
(CY .... rl0. r17
2
P
X
0
ROLC
rl. n
(CY .... r17. rl0 .... CY, rlm+ 1 .... rlm) x n times
2
P-
X
0
SHR
rl. n
(CY ... rl0. r17'" O. rl m_l
2
X
X
0
P
X
0
SHL
rl. n
(CY .... r17. rlo
2
X
X
0
P
X
0
SHAW
rpl. n
(CY -
2
X
X
0
P
X
0
SHLW
rpl. n
(CY... rp115. rplo .... O. rpl m+ 1 ... rpl m) x n times
2
X
X
0
P
X
0
ROR4
[rpl]
A3-o"- (rpl)3-0. (rpl)7_4'" A3-0.
(rpl)3-0 - (rpl)7_4
2
ROL4
[rpl]
A3-o'" (rpl 17_4. (rpl)3-0 (rpl17_4 .... (rpl )3-0
2
X
X
X
P
X
DECW
3
3
Shift/Rotate
<--
<--
CY, rl m-l ... rlml x n times
<--
rlm) x n times
O. rlm+ 1 .... rlm) x n times
rplo. rp115'" O. rplrn-l
<--
A:3-0.
rplml x n times
BCD Adjustment
ADJ4
Decimal adjust accumulator
Bit Manipulation
MOVl
38
CY, saddr.bit
CY .... (saddr.bit)
3
X
CY, sfr.bit
CY-sfr.bit
3
X
CY, Abit
CY"'A.bit
2
X
CY, X.bit
CY ... X.bit
2
X
CY, PSWH.bit
CY ... PSWH.bit
2
X
CY, PSWL.bit
CY .... PSWL.bit
2
X
saddr.bit. CY
(saddr.bit) <-- CY
3
sfr.bit. CY
sfr.bit+- CY
3
Abit. CY
A.bit .... CY
2
X.bit. CY
X.bit+- CY
2
PSWH.bit, CY
PSWH.bit <-- CY
2
PSWL.bit. CY
PSWL.bil <-- CY
2
\
X
X
X
X
X
NEe
pPD78312A Family
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
AC
PN
CY·
SUB
Bit Manipulation (cont)
AND1
OR1
XOR1
SET1
CY, saddr.bit
CY - Cy /\ (saddr.bit)
3
X
CY, Isaddr.bit
CY - Cy /\ (saddr.bit)
3
X
CY, sfr.blt
CY - CY /\ sfr.bit
3
X
CY, Isfr.bit
CY - Cy /\ sfr.bit
3
X
CY, A.bit
CY - CY /\ A.bit
2
X
CY, IA.bit
CY - CY /\ A.bit
2
X
CY, X.bit
CY - Cy /\ X.bit
2
X
CY, /X.bit
CY - CY /\ X.bit
2
X
CY, PSWH.bit
CY- CY /\ PSWH.bit
2
X
CY, IPSWH.bit
Cy - CY /\ PSWH.bit
2
X
CY, PSWL.bit
Cy - CY /\ PSWL.bit
2
X
CY, IPSWL.bit
Cy - Cy /\ PSWL.bit
2
X
CY, saddr.bit
CY - Cy V (saddr.bit)
3
X
CY, Isaddr.bit
CY - Cy V (saddr.bit)
3
X
CY, sfr.bit
CY
Cy V sfr.bit
3
X
CY, Isfr.bit
CY - Cy V sfr.blt
3
X
CY, A.bit
CY - CY V A.bit
2
X
+-
CY, IA.bit
CY
+-
CY V A.bit
2
X
CY, X.bit
CY
+-
Cy V X.bit
2
X
CY, /X.bit
CY - Cy V X.bit
2
X
CY, PSWH.bit
CY +- CY V PSWH.bit
2
X
CY, IPSWH.bit
CY - CY V PSWH.bit
2
X
CY, PSWL.bit
CY +- CY V PSWL.bit
2
X
CY, IPSWL.bit
CY
CY V PSWL.bit
2
X
CY, saddr.bit
CY .... CY 'if (saddr.bit)
3
X
CY, sfr.bit
CY - Cy 'if sfr.bit
3
X
CY, A.bit
cy
+-
CY 'if A.bit
2
X
CY, X.bit
CY
+-
Cy 'if X.bit
2
X
CY, PSWH.bit
cy - Cy 'if PSWH.bit
2
X
CY, PSWL.bit
Cy
CY'if PSWL.bit
2
X
saddr.bit
(saddr.bit) - 1
2
+-
+-
sfr.bit
sfr.bit +-1
3
A.bit
A.bit .... 1
2
X.bit
X.bit .... 1
2
PSWH.bit
PSWH.bit .... 1
2
PSWL.blt
PSWL.bit-1
2
X
X
X
X
..
X
39
NEe
pPD78312A Family
Instruction Set (cant)
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
AC
PN
CY
SUB
X
X
X
X
X
X
X
X
X
X
X
X
Bit Manipulation (cont)
CLRl
NOTl
~
0
saddr.bit
(saddr.bit)
slr.bit
slr.bit - 0
3
2
A.bit
A.bit-O
2
X.bit
X.bit - 0
2
PSWH.bit
PSWH.bit - 0
2
PSWL.bit
PSWL.bit <- 0
2
saddr.bit
(saddr.bit) - (saddr.bit)
3
slr.bit
sIr. bit <- slr.bit
3
A.bit
A.bit - A.bit
2
X.bit
X.bit <- X.bit
2
PSWH.bit
PSWH.bit - PSWH.bit
2
PSWL.bit
PSWL.bit - PSWL.bit
2
CY
CY-l
CLRI
CY
CY-O
0
NOTl
CY
CY-CY
X
!addr16
(SP-l) - (PC + 3)H. (SP - 2) <- (PC + 3lL.
PC - addr16. SP +- SP - 2
3
rpl
(SP-l) - (PC + 2)H. (SP - 2) +- (PC + 2)l.
PCH - rpl H. PCl - rpl l. SP +- SP - 2
2
[rpl]
(SP-l) <- (PC + 2)H. (SP-2) <- (PC + 2)l.
PCH <- (rpl + 1). PCl +- (rpl). SP <- SP - 2
2
CALLF
laddrl1
(SP-l) - (PC + 2)H. (SP - 2) - (PC + 2)l.
PC 1S-11 <- 00001. PC 1O -0 !addrl1. SP <- SP - 2
2
CALLT
[addr5]
(SP-l) <- (PC + l)H. (SP - 2) <- (PC + l)l.
PCH - (TPFx8000H + addr5 + 1).
PCl <- (TPFx8000H + addr5). SP 873,.
3
_i'
....,
NEe
pPD78322 Family
Pin Configurations (cont)
SO-Pin PllIstic QFP or Cerllmic LCC
10 .... "'''1,..0
~~~~~~:e
LI.!Z~~~2
~~iill~~g~~~~~~f
D.D.>«
D.
D.D.D.
~~~n~~~~nn~m~~~~
~ntnP&'f1
Ne
NO
0
P3Q/1lID
P31/RXD
P3~
P3afS1fSB1
P34fSOK
P71fAN1
60
59
58
AVss
P81fTOO1
10
55
PB2fTOO2
PBafTOO3
11
54
NO
P7(/ANO
VDD
PS7fA15
P5f(A14
PS&,A13
P54fA 12
12
53
PSatA 11
P8.VT010
NO
13
52
P5~A10
14
51
PS1/Ag
P8sf1011
15
RESET
18
50
49
PS(/As
P4-,1AD7
X2
X1
17
48
47
P4&,AD
P4&,AD5
Vss
46
P44fAD4
Wiffi)
RTP(/POo
45
P4atAD3
NO
NO
*
61
58
RTP1fP01
NO
NO
NO
57
P6ofTOOO
P7~AN2
64
63
62
44
43
42
e
NO
NO
P4~AD2
No connectfon; may be COIVIecIad to V ss to prevent noise.
Vpp on ~PD78P322.
83Cl-9322B
4
NEe
JlPD78322 Family
Pin Functions
Symbol
First Function
Symbol
Second Function
Port 0; S-bit, bit-selectable I/O port
RTPo - RTP7
Bit-selectable, timer-controlled,
port
Port 2; S-bit input port
NMI
INTPO -INTP5
INTP6/TI
External nonmaskable interrupt
Maskable external interrupts; edge-selectable
Maskable external interrupt or timer input
Port 3; 5-bit, bit selectable 110 port
TxD
RxD
Asynchronous serial transmit
Asysnchronous serial receive
SO/SBO
SO: serial data output for 3-wire serial I/O mode.
SBO: I/O bus for NEC serial bus interface (SBQ.
SIISBl
SI: serial data input for 3-wire serial I/O mode.
SB1: I/O bus for NEC serial bus interface (SBI).
P33
SCK
rea~time
output
Serial clock input or output
Low-order byte of external address/data bus
Port 4; S-bit, byte-selectable I/O port
Port 5; S-bit, bit-selectable 110 port
High-order byte of external address bus
Port 7; S-bit input port
ANO-AN7
Inputs for ND converter
Port S; 6-bit, bit-selectable I/O port
TODD
TOOl
Timer (RPU) output lines
T002
TOO3
TOlD
TOll
Port 9; 4-bit, bit-selectable 110 port
ASTB
External address latch strobe
EA
External access control on JlPD7S320/
322; a high level enables access to onchip ROM; a low level is applied if all
program memory is external. Must be
tied low for the JlPD7S320.
RESET
External system reset input
WDTO
Watchdog timer output
Xl
Crystal connection or external clock
input.
X2
Crystal connection; not necessary to
connect with external clock input.
AVoo
A/D converter +5-volt power input
AVss
ND converter ground
RD
WR
I
External read strobe
External write strobe
A/D converter reference voltage input
Voo
+5-volt power input
Vss
Ground
Vpp
PROM write-verify power input on
JlPD7SP322 only. Must be tied to Voo for
normal operation
NC
Not connected internally. May be
connected to Vss
5
NEe
pPD78322 Family
"PD78322 Family Block Diagram
Execution
Memory
NMI(P2ol
Programmable
INTPO ·INTPB
Interrupt
ControRer
Internal
Program
(p21·P2 a)
Memory
16KBytas*
TOO2(PB2l
TOO3(PB3l
1010(PB.,)
1011 (P8S>
TUlNTPB (P27)
SCK(P34)
SOISBO (P3Z)
SVS81 (P33)
TxD(P3 0)
RxD( P31)
Unft
Mlcrosaquenca
Control
PulA Unft)
Micro ROM
nmarlCounter
(ReaI·nma
Serlallnlerlaca
(S81)
(UART)
I
I
~
~
AVoo
AVss
RD(P9o)
WR(P91)
Peripheral
RAM
384Bytas
AS·A15
(PSO·PS7)
ADO·ADr
(P40· P47)
P90· P93
PSo· P8 S
P70· P77
PSo· P5 7
P40· P4 7
ANO • PN1 (P7)
INTPS
Xl
X2
RESET
ASlB
EANpp**
TOOO(PBol
1"001 (pal)
Control
P30·P34
/lID Convar18r
(10-811)
(8 Channels)
PZO·P27
AVREF
POo·P07
(RTPO·RTPr)
* "P0783221P322.
* * vPP on "PD78P322
83CL·932SB
6
NEe
FUNCTIONAL DESCRIPTION
Central Processing Unit
pPD78322 Family
address bus. The low-order 8 bits of the address bus
are multiplexed to provide the 8-bit data bus and are
supplied by I/O port 4.
The central processing unit (CPU) of the pPD78322
family features 16-bit arithmetic including 16-by-16-bit
multiply, both unsigned and Signed, and 32-by-16-bit
unsigned divide (producing a 32-bit quotient and a
16-bit remainder). The signed multiply executes in 3.5
ps and the divide in 5.38 ps at 16 MHz.
High-order address bits are taken from port 5 as required. Address latch, read, and write strobes are also
provided. The memory mode register (MM) controls the
size of the external memory. It can be programmed for
0, 4, 6, or 8 bits from port 5 for the high-order address.
Any remaining port 5 bits can be used for I/O.
A CALLT vector table and a CALLF area decrease the
number of bytes in the call instructions for commonly
used subroutines. A 1-byte call instruction can access
up to 32 subroutines through their addresses in the
CALLT vector table. A2-byte call instruction can access
any routine beginning in a specific CALLF area.
The pPD78320 does not have ports 4 and 5. It has eight
dedicated high-order address lines and eight dedicated address/data lines. All memory below address
FC 80H must be external.
The internal system clock (fCUQ is generated by dividing the oscillator frequency by 2. Therefore, at the
maximum oscillator frequency of 16 MHz, the clock is 8
MHz. Since some instructions execute in two cycles,
the minimum instruction time is 250 ns.
On-Chip RAM
The pPD78322 fami Iy has a total of 640 bytes of on-chip
RAM. The upper 256-byte area (FEOOH-FEFFH) features
high-speed access of one word of data per internal
system clock and is known as "main RAM." The remainder (FC80H-FDFFH) is accessed at the same speed as
external memory (1 byte per three internal system
clocks) and is known as "peripheral RAM." The general
register banks and the macro service control words are
stored in main RAM. The remainder of main RAM and
any unused register bank locations are available for
general storage.
On-Chip PROM
The pPD78322 contains 16K bytes of internal ROM; the
pPD78P322 contains 16K bytes of UV EPROM or onetime programmable ROM. Instructions are fetched from
this on-Chip memory at a maximum rate of 1 byte every
internal system clock through the high-speed fetch
mode. The pPD78320 does not have on-Chip PROM.
External Memory
The pPD78322 family has a 64K-byte address space.
The pPD78322/P322 can access 0, 256, 41<, 16K, or 48K
bytes of external memory in the area from 4000H to
FFFFH. External memory can be either ROM or RAM
(or both) as required. The pPD78322/P322 have an 8-bit
wide external data bus and a 16-bit wide external
The programmable wait control register (PWC) allows
the programmer to specify one or two additional wait
states if they are required for low-speed memory or
external peripheral devices. These wait states for internal and external memory are specified independently.
Program Fetch
The pPD78322 family allows opcode fetch in the area
between OoaOH and FFFFH under the following constraints: from FC80H to FDFFH, opcodes will be
fetched from the peripheral RAM; from FFEOH to
FFFFH, opcodeswill be fetched from external memory
only. ThepPD78322 family contains a3-byte instruction
prefetch queue. The bus control unit can fetch an
instruction byte from memory during cycles in which
the execution unit is not using the memory bus.
,
BIIIIIIIi
Instruction bytes can be fetched from on-chip memory ~
in either high-speed or ordinary fetch cycle mode. The
i
fetch cycle control register (FCC) is used to select the
mode. In high-speed fetch cycle mode, one internal
system clock is required to fetch each instruction byte
from on-Chip memory. In ordinary fetch cycle mode,
each byte to be fetched requires three, four, or five
internal system clocks depending on the setting of the
PWC register.
Each instruction byte fetched from external memory
requires three, four, or five internal system clocks depending on the setting of the PWC register.
CPU Control Registers
Program Counter. The program counter is a 16-bit
register that holds the address of the next instruction
to be executed. During reset, the program counter is
loaded with the address stored in locations OOOOH and
0001H.
7
NEe
IIPD78322 Family
Stack Pointer. The stack pointer is a 16-bit register
that holds the address of the last item pushed onto the
stack. It is decremented before new data is pushed
onto the stack and incremented after data is popped
off the stack.
CPU Control Word. The CPU control word (CCW)
selects the origin of the interrupt vector and CALLT
tables. If the TPF bit (bit 1) is zero, the origin is OOOOH;
if the TPF bit is one, the origin is aOOOH. The CCW is a
special function register located at address FFC1H.
The a~dresses of the vectors for the RESET input,
operation-code trap, and BRK instruction are fixed at
OOOOH, 0003CH, and 003EH, respectively, and are not
altered by the TPF bit.
The program status word
Program Status Word.
(PSW) is a 16-bit register containing flags that are set or
reset depending on the results of an instruction. This
register can be written to or read from a bits at a time.
The high-order a bits are called the PSWH and the
low-order a bits are called the PSWL. The individual
flags can also be manipulated on a bit-by-bit basis. The
assignment of PSW bits follows.
7
PSWH
PSWL
S
PN
LT
CY
a
5
4
UF ! RBS2! RBSt! RBSO!
7
6
S
z
UF
RBS2-RBSO
Z
RSS
AC
IE
6
5
! RSS
4
I AC
3
2
0
o
3
2
IE
o
!
0
I PN I LT
! 0
!
o
CY
User flag
Active register bank number
Sign flag (1 if last result was negative)
Zero flag (1 if last result was zero)
Register set selection flag
Auxiliary carry flag (carry out of 3 bit)
Interrupt enable flag
Parity or arithmetic overflow flag
Interrupt priority level transition flag
Carry bit (or 1-bit accumulator for logic)
General Registers
There are sixteen a-bit general registers, which can
also be paired to function as 16-bit registers. A complete set of 16 registers is mapped into each of eight
program-selectable register banks stored in main RAM.
Three bits in the PSW identify activ~ register banks.
Registers have functional names (like A, X, B, C for a-bit
registers and AX, BC for 16-bit registers) and absolute
names (like R1, RO, R3, R2 for a-bit registers and RPO,
RP1 for 16-bit registers). Each instruction determines
whether a register is referred to by functional or absolute name and whether it is 8 or 16 bits.
Two possible relationships may exist between the absolute and functional names of the first four register
pairs. The RSS bit in the PSW determines which of these
is active at any time. The effect is that the accumulator
and counter registers can be saved, and a new set can
be specified by toggling the RSS bit. Figure 1 illustrates the general register configuration.
NEe
IIPD78322 Family
Figure 1. General Registers
Register Storage
FESOH
Bank 7
Bank 6
Bank 5
Bank 4
RSS=O
lH
OH
_~~J_~~_
RSS=1
AX (RPO)
RO_ _
_ _Rl_ -1I _ _
B (R3) ---1I ____
C (R2)
___
RPO
BC(RP1)
_ _ _ -1 _ _ _ _
R5 ---1I ____
R4
___
RPl
RP2
_~~J_~R~_
R7
R6_ _
__
_ -1I _ _
AX (RP2)
RP3
_~~J_~~_
R3
Bank 3
VPH(R9) I VPL(R8)
f----1---VP(RP4)
Bank 2
f---~----
UPH (Rll)
I
I
R2
BC(RP3)
UPL(Rl0)
UP (RP5)
Bank 1
f-~R~J_E~l~_
DE (RP8)
FEFOH
BankO
f-
J
~R~ _L~l~_
HL(RP7)
FEFFH
~
FH
EH
________________________________________________________________~_~~~~B
Addressing
The pPD78322 family features 1-byte addressing of
both the special function registers and the portion of
on-chip RAM from FE20H to FEFFH. The 1-byte sfr
addressing accesses the entire SFR area, whereas the
1-byte saddr addressing accesses the first 32 bytes Qf
the SFR area and 224 bytes of the main RAM.
The 16-bit SFRs and words of memory in these areas
can be addressed by 1-byte saddrp addressing, which
is valid for even addresses only. Since many instructions use 1-byte addressing, access to these locations
is almost as fast and as versatile as access to the
general registers.
There are nine addressing modes for data in main
memory: direct, register, register indirect with autoincrement or decrement, saddr, saddr indirect, SFR,
based, indexed, and based indexed. There are also
8-bit and 16-bit immediate operands. Figure 3 is the
memory map of the pPD78322 family.
9
IEI!II
NEe
pPD78322 Family
Figure 2. Memory Map
Primary Vector Table
OOOOH
Interrupt
Vector Table
64 Bytes
(32 Addresses)
003FH
OO4OH
CALLT
OOOOH
OSOOH
OFFFH
Vector Table
64 Bytes
(32 Addl1lsses)
General Memory
--------CALLFAraa
007FH
Address Space
64KBytea
Alternate Vector Table
~Hr-------~-------;
8000H
Interrupt
Vector Table
64 Bytes
(32 Addresses)
Internal Program
Memory
(lLPD783221P322)
3FFFH
4000H
803FH
8040H
CALLT
Vector Table
648ytes
(32 Addl1lsses)
7FFFH _ _ _ _ _ _ _ _ _F-____________--=8c:.07"'F-"H"-_ _ _ _ _ _ _ _
FC80H
saddr Addressing
Pe~pheral
External
Memory
Area
General RAM
Main! -
FFOOH
FC7FH
FFFFH---------
FE20H
RAM
FDFFH
RAM
-
~;-SIora; -
-1-_ _--'-'FE7:::..:..;FH"-I.
---;;'-ste-;;";--
---------
FE80H - - - - - - - - Register
Special Function
Register AI1Ia
SIorage
Area
FFFFH
FF1FH
10
~
32 Bytes of SFR Area
NEe
pPD78322 Family
Special Function Registers
The input/output ports, timers, capture and compare
registers, and mode and control registers for both the
peripherals and the CPU are collectively known as
special function registers. They are all memorymapped between FFOOH and FFFFH and can be accessed either by main memory addressing or by 1-byte
SFR addressing. All exceptthe port mode registers and
the asynchronous serial transmission shift register can
be read under program control, and most can also be
written. They are either a or 16 bits, as required, and
many of the a·bit registers are capable of single-bit
access as well.
Locations FFDOH through FFDFH are known as the
external access area. Registers in external circuitry,
interfaced and mapped to these addresses, can be
addressed with SFR addressing. Table 1 lists the special function registers.
Table 1. Special Function Registers
Access Unit (Bits)
Address
Register
Symbol
R/W
1
8
FFOOH
Port 0
PO
A/W
x
X
16
Undefined
State After Reset
FF02H
Port 2
P2
A
X
Undefined
FF03H
Port 3
P3
A/W
X
X
Undefined
FF04H
Port 4
P4
A/W
X
X
Undefined
FF05H
Port 5
P5
R/W
X
X
Undefined
FF07H
Port 7
P7
A
X
Undefined
FFOBH
Port B
PB
R/W
X
X
Undefined
FF09H
Port 9
P9
R/W
X
X
Undefined
FFOAH-FFOBH
Free-running counter (lower 16 bits)*
TMOLW
A
X
FF10H-FF11H
Capture register XO (lower 16 bits)*
CTXOLW
A
X
OOOOH
Undefined
FF12H-FF13H
Capture register 01 (lower 16 bits)*
CT01LW
A
X
Undefined
FF14H-FF15H
Capture register 02 (lower 16 bits)*
CT02LW
A
X
Undefined
FF16H·FF17H
Capture register 03 (lower 16 blts)*
CT03LW
A
X
Undefined
c_a~Pt_u_re~~_o_m~p_a_re_r_e~g_is_te_r_X_O~(I_ower_'_6_b_it_s~)* C_C_X_O-~-W----A~/W-----------------XX------UU-nn-ddee-ff-il.nn-ee-dd----- ~,j'
_FF_FF"_BA_HH_·.FF_FF_',_9BH_H_______
__
___
Capture/compare register 01 (lower 16 bits)*
CC01 LW
A/W
FF20H
Port 0 mode register
PMO
W
X
FFH
FF23H
Port 3 mode register
PM3
W
X
xxx1 1111 B
FF25H
Port 5 mode register
PM5
W
X
FFH
FF2BH
Port B mode register
PMB
W
X
xx11 1111 B
X
~
FF29H
Port 9 mode register
PM9
W
FF2AH·FF2BH
Free running counter (hIgh 16 bits)*
TMOUW
A
X
OOOOH
FF2CH·FF2DH
Timer register 1
TM1
A
X
OOOOH
FF30H-FF31 H
Capture register XO (high 16 bits)*
CTXOUW
A
X
Undefined
FF32H·FF33H
Capture register 01 (high 16 bits)*
CT01UW
A
X
Undefined
FF34H·FF35H
Capture register 02 (high 16 bits)*
CT02UW
A
X
Undefined
FF36H·FF37H
Capture register 03 (high 16 bits)*
CT03UW
A
X
Undefined
FF3BH·FF39H
Capture/compare register XO
(high 16 bits)*
CCXOUW
R/W
X
Undefined
FF3AH-FF3BH
Capture/compare register 01
(high 16 bits)*
CC01UW
A/W
X
Undefined
FF40H
Port 0 mode control register
PMCO
W
FF41H
Aea~time
ATPS
output port set register
X
xxxx 1111 B
X
OOH
X
OOH
11
NEe
pPD78322 Family
Table 1. Special Function Registers (cont)
Access Unit (Bits)
Address
Register
Symbol
R/W
FF43H
Port 3 mode control register
PMC3
W
FF48H
Port 8 mode control register
PMC8
W
FF4CH·FF4DH
Baud rate generator
BRG
R/W
FF60H
Rea~time
RTP
R/W
FF61H
Real·time output port reset register
RTPR
R/W
output port register
FF62H
Port read control register
PRDC
R/W
FF68H
AID converter mode register
ADM
R/W
FF6AH
AID converter result register
ADCR
R
ADCRH
R
1
8
16
x
x
xxOO OOOOB
x
x
x
x
x
State After Reset
xxxO OOOOB
Undefined
x
Undefined
x
x
x
OOH
OOH
OOH
x
Undefined
(16·bit access)
FF6BH
AID converter result register
x
Undefined
(high 8 bits)
x
x
x
x
x
x
FF70H·FF71 H
Compare register 00
CMOO
R/W
FF72H·FF73H
Compare register 01
CM01
R/W
FF74H·FF75H
Compare register 02
CM02
R/W
FF76H·FF77H
Compare register 03
CM03
R/W
FF7CH·FF7DH
Compare register 10
CM10
R/W
FF7EH·FF7FH
Compare register 11
CM11
R/W
FF80H
Clock synchronized serial interface mode
register
CSIM
R/W
x
x
OOH
FF82H
Serial bus interface control register
SBIC
R/W
x
Serial I/O shift register
SIO
R/W
FF88H
Asynchronous serial interface mode register
ASIM
R/W
x
x
x
x
OOH
FF86H
x
80H
FF8AH
Asynchronous serial interface status register
ASIS
R
Serial receive buffer: UART
AXB
R
x
x
OOH
FF8CH
FF8EH
Serial transmit shift register: UART
TXS
W
x
Undefined
FFBOH
Timer control register
TMC
R/W
x
x
x
x
x
x
x
x
OOH
x
OOH
x
OOH
x
22H
x
x
x
OOH
x
x
x
x
x
FFB1H
Baud rate generator mode register
BRGM
R/W
FFB2H
Prescalar mode register
PRM
R/W
FFB8H
Timer output control register 0
TOCO
R/W
FFB9H
Timer output control register 1
TOCl
R/W
FFBFH
Rea~time
RPUM
R/W
FFCOH
Standby control register
STBC
R/W"
FFC1H
CPU control word
CCW
R/W
FFC2H
Watchdog timer mode register
WDM
R/W"
FFC4H
Memory extension mode register
MM
R/W
FFC6H
Programmable wait control register
PWC
R/W
FFC9H
Fetch cycle control register
FCC
R/W
x
x
x
FFDOH·FFDFH
External access area
R/W
x
FFEOH
Interrupt request flag register OL
IFOL/IFO
R/W
x
FFE1H
Interrupt request flag register OH
IFOH
R/W
x
x
FFE2H
Interrupt request flag register 1L
IF1L/IFl
R/W
x
x
12
pulse unit mode register
x
x
x
x
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
OOH
OOH
OOH
OOH
OOH
OOOOXOOOB
OOH
Undefined
x
OOH
x
OOH
OOH
NEe
I'PD78322 Family
Table t. Special Function Registers (cont)
Access Unit (Bits)
Address
Register
Symbol
RNI
1
8
16
State After Reset
FFE4H
Interrupt mask flag register OL
MKOL/
MKO
RNI
X
X
X
FFH
FFE5H
Interrupt mask flag register OH
MKOH
R/W
X
X
FFE6H
Interrupt mask flag register 1L
MK1L1
MK1
R/W
X
X
X
xxxx x111B
FFE8H
Priority selection buffer register OL
PBOL/
PBO
R/W
X
X
X
OOH
FFH
FFE9H
Priority selection buffer register OH
PBOH
R/W
X
X
FFEAH
Priority selection buffer register 1L
PB1L/
PB1
Rf\N
X
X
X
OOH
FFECH
Interrupt service mode selection register OL
ISMOLI
ISMO
Rf\N
X
X
X
OOH
FFEDH
Interrupt service mode selection register OH
ISMOH
R/W
X
X
FFEEH
Interrupt service mode selection register 1L
ISM1L/
ISM1
Rf\N
X
X
X
OOH
FFFOH
Context switch enable register OL
CSEOL/
CSEO
Rf\N
X
X
X
OOH
FFF1H
Context switch enable register OH
CSEOH
R/W
X
X
FFF2H
Context switch enable regi ster 1L
CSE1L/
CSE1
Rf\N
X
X
OOH
OOH
OOH
X
OOH
FFF4H
External interrupt mode register 0
INTMO
R/W
X
X
OOH
FFF5H
External interrupt mode register 1
INTM1
Rf\N
X
X
OOH
FFF8H
In-service priority register
ISPR
R
X
OOH
FFF9H
Priority selection register
PRSL
Rf\N
X
OOH
•
X
Lower or upper 16 bits of an 18-bit register.
• * Protected location: special instruction required for write.
Input/Output Ports
The pPD78322 family has six ports providing a total of
371/0 lines. po, P3, P8, and P9 are tri-state input/output
ports of 8, 5, 6, and 2 bits, respectively; each bit can be
individually selected for input or output. P2 and P7 are
8-bit input ports.
P2 functions only in the control mode as input pins for
the NMI Signal, the INTPO to INTP5 interrupt Signals,
and the INTP6/T1 interrupt signal or external count
clock for timer 1 (TI). However, any masked interrupt
automatically becomes an input line and the state of
all the pins can be read by the program using a read
instruction to port 2. Each pin of P2 can be programmed for rising, falling, or both rising and falling
edge detection.
The output level of the PO, P3, P8, and P9 I/O pins can
be tested to determine whether they agree with the
contents of the output latch. When the low-order bit of
port read control register PRDC is set to 1, the output
level of the I/O pins can be read with the port still in the
output mode. These data values can be compared with
the data known to be in the output latch to determine if
the port is functioning correctly. Figure 3 shows the
structure of each port pin.
The J..IPD78322/P322 have two additional input/output
ports, P4 and P5, and two additional I/O pins in P9. All
these I/O lines are available if external memory or
memory-mapped external circuitry is not being used.
Port 4 is shared with the low-order address/data bus
(ADo to AD7) and is byte-selectable for input or output.
Port 5 is shared with the high-order address bus (As to
A15). Depending on the amount of external memory
used, either 8, 6, 4, or 0 bits are available for bitselectable I/O. Port 9 is a 4-bit, bit-selectable I/O port;
two of its pins are shared with the read and write
strobes.
13
NEe
pPD78322 Family
Figure 3. 110 Circuits
Type1.
EX
Type 5. PO, P3g, P31, P4, PI, PB, P9
Voo
Data
P-ell
op--.---o
INfOUT
N·ch
Output Olsable
Input Enable - - - - - - - '
Type 7.
Type 2. P2, RESET
INo-{g>-
IN
-L
0
Schmitt trigger Input with hysteresis characteristics.
:: rnT+--"':1--~
I ~
VREF (Threshold Voltage)
Type3. WDTO
Voo
Voo
Dsla~
OUT
OUtPut~
P-ell
op--......--o
INfOUT
N·ch
DIsable
Type9. P7
Type4. ASTB
Voo
Data
-rfD-H{~
-'"""~f-""
Push1lull outputlhal can be placed In high
VREF (Threshold Voltsge)
L--_ _ _ _ _ _ _
~~~Ie
Impedanoa (both P-ell and N-ch 011).
83CL-932iB
14
NEe
JlPD78322 Family
Real·Time Output Port
Port 0 can function on a bit-selectable basis as a
real-time output port. Selected bits can be directly
written under program control, or they can be set or
cleared under control of timing signals generated by
the real-time pulse unit. Timing by the latter method is
independent of interrupt latency.
AID Converter
The analog-to-digital (AID) converter (figure 4) uses the
successive-approximation method for converting up to
eight multiplexed analog inputs into 1D-bit digital data.
The conversion time per input is 18 fls at 16-MHz
operation. AID conversion can be started by an external interrupt, INTP5, or under software control.
The AID converter can operate in scan mode or select
mode. In scan mode, inputs AND - AN3 or AN4 - AN7
can be programmed for conversion. The AID converter
selects each of the four inputs in order, converts the
data, stores it in the AID conversion result (ADCR)
register, and generates an interrupt (INTAD). This converted data can be easily transferred to memory by the
macro service function. In select mode, any one of the
eight AID inputs can be selected for conversion.
Once the AID converter is started by INTP5 or software,
conversion continues until it is disabled by software.
The ADCR register is continually updated and either
the full1D bits or only the upper 8 bits of the conversion
can be read at any time.
Figure 4. AID Converter
AND
,----1
Sample and
Hold ClraJlt
AN1
AN2
AN3
1-----,--0
1 T:
AN4
AN5
rh
1
1
1_ _ _ _ --'
ANB
AN7
INTPS
•
_INTAD
T~gger
10
Enable
IntemaiBus
83CW328B
15
NEe
IIPD78322 Family
Serial Interface
The JlPD78322 family has two independent serial interfaces with a dedicated baud-rate generator. The first is
a standard universal asynchronous receiver transmitter (UART). The UART (figure 5) permits full-duplex
operation and can be programmed for 7 or 8 bits of
data after the start bit, followed by one or two stop bits.
Odd, even, zero, or no parity can also be selected.
Figure 5. Asynchronous Serial Interface
r
Clear
INTST
1-----......---'
Clock-Synchronized
Serial Interface
Baud-Rate Generator
83CL-9327B
16
NEe
pPD78322 Family
The source of the serial clock for the UART is the
internal system clock (divided by 4) or the on-chip
baud-rate generator. The UART generates three interrupts: INTST (transmission complete), INTSR (reception complete), and INTSER (reception error).
The second interface is an 8-bit clock-synchronized
serial interface (figure 6). It can be operated in either
three-wire serial I/O mode or NEe serial bus interface
(S61) mode.
Figure 6. Clock-Synchronized Serial Interface
Selector
Busy!
N-ch Open-DraIn
OUIpUt Possible
Acknowledge
Output Clrouft
..
Bus Release!
Commend(
Acknowledge
DetecUon
Clrcuft
!
INTCSI
Baud-Rate Generator
'CLK/S
'CLKI32
83CL-93288
17
NEe
pPD78322 Family
In the three-wire serial I/O mode, the 8-bit shift register
(SIO) is loaded with a byte of data and eight clock
pulses are generated. These eight pulses shift the byte
of data out on the SO line (either MSB or LSB first) and
in on the Siline, providing full-duplex operation. This
interface can also be set to receive only or to transmit
only. The INTCSI interrupt is generated after each 8-bit
transfer. One of two internal clocks, an external clock,
or the internal baud-rate generator clocks the data.
The NEC SBI mode is a two-wire, high-speed proprietary serial interface available on most devices in the
NEC IlPD75xxx and IlPD78xxx product lines. Devices
are connected in a master/slave configuration (figure
7). There is only one master device at a time; all others
are slaves. The master sends addresses, commands,
and data over one of the serial bus lines (SBO or
SB1)usi~ fixed hardware protocol sysnchronized
with the SCK line.
Figure 7. 8B1 Mode Master/Slave Configuration
r
MasIlIrCPU
(S81).SBO
Slaw CPU
I~~)I
-
Address 1
SCK
SCK
S1iiV8CPU
I--~')I
Address 2
------ISCK
t-~
.
.
".
.
880. (SB1)
AddressN
SCK
II9CWG2M
18
Each slave IlPD78322 family can be programmed in
software to respond to any one of 256 addresses. There
are also 256 commands and 256 data types. Since all
commands are user-definable, any software protocol,
simple or complex, can be defined. It is even possible
to develop commands to change a slave into a master
and the previous master into a slave.
A dedicated baud-rate generator can be programmed
to provide the serial clock to both asynchronous and
clock-synchronized serial interfaces. By choosing the
correct oscillator frequency, the baud-rate generator is
capable of generating all of the commonly used baud
rates from 75 to 19,200 b/s.
Real·Time Pulse Unit
The real-time pulse unit (RPU, figure 8) can function as
an interval timer to measure pulse widths and frequencies, generate pulse-width modulated outputs, count
external events, and control the real-time output port. It
consists of 18-bit free-running timer TMO, 16-bit timer/
counter TM1, six 16-bit compare registers, four 18-bit
capture registers, two 18-bit registers (capture or compare), and six timed output latches.
TMO always counts the internal system clock (divided
by 4 or 8) and can be reset by an external reset pulse
only. TM1 can count either the internal system clock
(divided by 8 or 16) or external events. TM1 can be reset
by a compare event (a match between a timer and an
associated compare register) or by an external signal
in INTPO.
Capture events can be triggered by external maskable
interrupts INTPO - INTP5, and compare events can generate interrupts, control timed output pins. or both. In
addition, interrupts INTCM03 and INTCCXO can control
the real-time output port
The timed output latches share the six pins of port P8.
Four latches can be toggled or set and reset by compare events, and the remaining two can be toggled.
These latches, with the macro service facility, can
generate up to four pulse-width modulated outputs.
NEe
pPD78322 Family
Figure 8. Real-Time Pulse Unit
TMO
TM1
INTPO
r7---- (Opposite Edge)
INTP6ITI~
'CLK"16
L._--r--_..J
'CLK"8
INTCMOO
Compara Reg CMll
INTCMOl
INTCM02
TOl0
T
TOO3
INTPO
----L----Captura Register CTOl
INTP1~~__~____~______~
INTP2 _
INTP3 ~
TOll
Captura Register CT02
~1----c-ap'-tu-ra--R-eg'-lste--r-C-T03----"'"
-1-__ _ _ _ _. ,._ _ _ -'
INTCCXO~
INTPS
TOOO
INTCCOl
MedeO
Mode 1
TOOl
INTPO _
INTP4
Captura Reg
CTXO
_1(Cap;;tu;;;re/fcc;;;o;:;m~p~R;eg;;CCcxCXio)"1~.--------l
TOO2
19
NEe
IIPD78322 Family
Interrupts
The JlPD78322 family has 19 maskable hardware interrupt sources: 7 external and 12 internal. The external
maskable interrupts share pins with port P2. Six of
them, INTPO to INTP5, can also be used to trigger
capture events in the real-time pulse unit. In addition,
there are two nonmaskable interrupts, two software
interrupts, and RESET. The software interrupts, generated by the BRK or BRKeS instruction and the operation code trap, are not maskable. See table 2.
Table 2. Interrupt Sources
Type of
Request
Default
Priority
Signal
Name
Source
Location
Operation code trap
Break instruction
CPU
CPU
NMI
INTWDT
NMllnput pin
Watchdog timer overflow
External
Internal
INTOV
Timer 0 overflow
Internal
INTPO
INTPO pin
External
2
INTP1
INTP1 pin
External
3
INTP2
INTP2 pin
4
INTP3
INTP3 pin
5
INTP4
INTCCXO
6
INTP5
INTCC01
Software
Nonmaskable
Maskable
0
Macro Service
Control Word
Vector Address
TPF
=0
TPF
=1
003CH
003EH
0002H
0004H
8002H
B004H
FE06H
0006H
B006H
FE06H
OOOBH
BOOBH
FEOAH
OOOAH
BOOAH
External
FEOCH
OOOCH
800CH
External
FEOEH
OOOEH
800EH
INTP4 pin
CCXO coincidence
External
Internal
FE10H
0010H
B010H
INTP5 pin
CC01 coincidence
External
Internal
FE12H
0012H
B012H
7
INTP6
INTP6 pin
External
FE14H
0014H
B014H
B
INTCMOO
CMOO coincidence
Internal
FE16H
0016H
8016H
9
INTCM01
CM01 coincidence
Internal
FE18H
0018H
8018H
10
INTCM02
CM02 coincidence
Internal
FE1AH
001AH
801AH
11
INTCM03
C M03 coi ncidence
Internal
FE1CH
001CH
801CH
12
INTCM10
CM10 coincidence
Internal
FE1EH
001EH
801EH
FE20H
0020H
8020H
0022H
8022H
13
INTCM11
CM11 coincidence
Internal
14
INTSER
Asynchronous serial
Interface reception error
Internal
15
INTSR
End of asynchronous serial
Interface reception
Internal
FE24H
0024H
8024H
16
INTST
End of asynchronous serial
Interface transmission
Internal
FE26H
0026H
8026H
17
INTCSI
End of clocked serial
Interface transmission/reception
Internal
FE28H
0028H
8028H
18
INTAD
End of AID conversion
Internal
FE2AH
002AH
RESET
RESET pin
External
Reset
802AH
OOaOH
Interrupt Servicing
Interrupt Control Registers
The JlPD78322 family provides three levels of programmable hardware priority control and three different
methods of handling maskable interrupt requests:
standard vectoring, context switching, and macro service. The programmer can choose the priority and
mode of servicing each maskable interrupt by using
the interrupt control registers.
The JlPD78322 family has ten 16-bit interrupt control
registers. Each bit in each register is dedicated to one
of the 19 maskable interrupt sources. The interrupt
request flag registers (IFO, IF1) contain an interrupt
request flag for each interrupt. The interrupt mask
registers (MKO, MK1) are used to enable or disable any
interrupt. The interrupt service mode registers (ISMO,
20
NEe
ISM1) specify whether an interrupt is processed by
vectoring or macro service.
The priority specification buffer registers (PBO, PB1), in
conjunction with the a-bit priority specification register
(PRSL), can be used to specify one of three priority
levels for each interrupt. The context switching enable
flag registers (CSEO, CSE1) specify whether an interrupt is processed by vectoring or context switching.
Two other a-bit registers are associated with interrupt
processing. The in-service priority register (ISPR) is
used by the hardware to hold the priority level of the
interrupt request currently being serviced. It is manipulated by hardware only, but it can be read by software.
The IE and LT bits of the program status word (PSW) are
also used to control interrupts. If the IE bit is zero, all
maskable interrupts, but not macro service, are disabled. The IE bit can be set or cleared using the EI and
DI instructions, respectively, or by directly writing to
the PSW The IE bit is cleared each time an interrupt is
accepted. The LT bit is set by hardware when a newly
accepted maskable interrupt request is assigned a
priority higher than the interrupt currently being serviced. The LT flag is used to control resetting the ISPR
register when a return instruction from an interrupt
service routine is executed.
pPD78322 Family
The "Default Priorities" listed in table 2 are fixed by
hardware; they are effective only when it is necessary
to choose between two interrupt requests of the same
software-assigned priority. For example, the default
priorities would be used after the completion of a
high-priority routine if two interrupts of the same lower
priority were pending.
Software interrupts, the BRK and BRKCS instructions,
and the operation code trap are executed regardless of
the processor's priority level and the state of the IE bit.
They do not alter the processor's priority level.
Figure 9. Interrupt Service Sequence
Interl\lpt Request
L
xxMKxx = 1 (Interl\lpt Masked) Interrupt Pending.
xxMKxx = 0 (Unmasked)
b.....·,-xxlSMxx
~m
Three hardware-controlled priority levels are available
for the maskable interrupts. Anyone of the three levels
can be assigned by software to each of the maskable
interrupt lines. Interrupt requests of a priority equal to
or higher than the processor's current priority level are
accepted; lower priority requests are held pending until
the processor's priority state is lowered by a return
instruction from the current service routine.
Interrupt requests programmed to be handled by
macro service have priority over all software interrupt
service regardless of the assigned priority level, and
macro service requests are accepted even when the
interrupt enable bit in the PSW is set to the disable
state. See figure 9.
..... _ .........
EI
~--.,,-~,-.
Interrupt Priority
The two nonmaskable interrupts, NMI and WDT, have
priority over all others. Their priority relative to each
other is under program control.
=0 Soltware Service.
xxCSExx= 1 Context Switch.
~L-933OA
Vectored Interrupt
_
When vectored interrupt is specified for a given interrupt request, the program status word and the program
counter are saved on the stack. The processor's priority is raised to that specified for the interrupt, the IE bit
in the PSW is set to zero, and the routine whose address
is in the interrupt vector table is entered.
At completion of the service routine, the RETI instruction (or RETB instruction for software interrupts) reverses the process, and the pPD78322 family resumes
the interrupted routine.
21
"
'
NEe
pPD78322 Family
Context Switch
special function register area and the memory space.
Control is then returned to the executing program,
providing a completely transparent method of interrupt
service. Macro Service significantly improves response
time and makes it unnecessary to save any registers.
When context switching (figure 10) is specified for a
given interrupt, the active register bank is changed to
the register bank specified by the three low-order bits
of the word in the interrupt vector table. The program
counter is loaded from RP2 of the new register bank,
the old program counter and program status word are
saved in RP2 and RP3 of the new register bank, and the
IE bit in the PSW is set to zero.
For each request on the interrupt line, one operation is
performed, and an a-bit counter is decremented. When
the counter reaches 0 (or when some other completion
condition is met), a software service routine is entered.
Either vectored interrupt or context switch can be
specified for entry to this routine, which is known as the
macro service completion routine, and the routine is
entered according to the specified priority.
At completion of the service routine, the RETCS instruction for routines entered from hardware requests,
or the RETCSB instruction for routines entered from
the BRKCS instruction, reverse the process. The old
program counter and program status word are restored from RP2 and RP3 of the new register bank. The
entry address of the service routine, which must be
specified in the 16-bit immediate operand of these
return instructions, is stored again in RP2.
Macro service is provided for all of the maskable interrupt requests except INTSER, the asynchronous serial
interface receive error interrupt request. Each request
has a dedicated macro service control word stored in
on-chip main RAM. The function to be performed is
specified in the control word. See table 3.
Macro Service
When macro service is specified for a given interrupt,
the macro service hardware temporarily stops the
executing program and transfers data between the
Figure 10. Context Switching and Return
Context Switch
Return From Context Switch
CUrrent AcUve
Register Bank
NewAcUve
RegIster Bank
AX
AX
'.
BC
BC
PC
Save Area
~
ImmedIate
Data, 16 BIts
I
I
Former AcUve
Register Bank
AX
AX
BC
BC
PC
SaveAraa
-'
RP2
PSW
SsveAraa
PSW
Save Area
-
RP3
VP
VP
VP
VP
UP
UP
UP
UP
DE
DE
DE
DE
HL
HL
HL
HL
RP2
~
I
CUrrent AcUve
RegIster Bank
RP3
1
Program
Counter
I.
Program
S1alusWord
~
~
Program
Counter
1
Program
S1alus Word
1
83AE>
tDAIO
P47-P40
HlghZ
M«<
Address (Low Byte)
-tSAST~
ASTB
~
Address (High Byte)
P57-P50
~
--tVVSTH-
-
~tHSTA-
+tOSTR~
Read Data
~
Address 0-7
\
/
HlghZ
tHRIO
~tFRA
~tORA_
-tORI01--tVVRL
E
tOAR
>
83RD-6739B
30
NEe
pPD78322 Family
Timing Waveforms (cont)
Write Operation
Clock
X
Address (High Byte)
Address (Low Byte)
~tSAST-
K
Undefined
Write Data
~
Address 0-7
~
/
I+tHWOo~
~tHSTA~
tDSTOD
ASTB
).
)I
--.I
fOII-tWSTH~
+tDSTW~
_tDWOD- ~tSODW~
-tDWST-=i
tWWL
!DAW
~
•
Interrupt Input
NMI
INTPn
n=Oto8
31
I
I
NEe
IIPD78322 Family
Timing Waveforms (cant)
Serial Port Operation
~---------lf~SK----------~
fOSKlX
so
SI ________________________fS_R_xS__,~-I:<:======-lfH-S-~-X~~~~~~_-~~---------------83FM-9333B
Reset Input
TJlnpuf
11
32
NEe
I'PD78322 Family
PROM PROGRAMMING
The PROM in the IlPD78P322 is one-time programmable
(OTP) or ultraviolet erasable (UV EPROM). The 16,384 x
8-bit PROM has the programming characteristics of an
NEC IlPD27C256A. Table 3 shows the functions of the
IlPD78P322 pins in normal operating mode and PROM
programming mode.
PROM Programming Mode
When the RESET pin is set high and AVoo is set low, the
IlPD78P322 enters the PROM programming mode. Operation in this mode is determined by the setting of the
CE, OE, Vpp, and Voo pins as indicated in table 4.
Table 3. Pin Functions During PROM
Programming
Normal Operating
Mode
Programming
Mode
Address input
POo - PO?, P8o, P20,
P8l - P8?
Ao -A14
Data input
P40 - P47
00- D]
Chip enablel
program pulse
P3 l
CE
Function
Output enable
P30
OE
Program voltage
Vpp
Vpp
Mode voltage
RESET, AVoo
RESET, AVOO
Table 4. Operation Modes For Programming
Mode
Program write
RESET
AVDD
CE
OE
Vpp
VDD
+6.0V
Data input
00 - 07
H
l
l
H
+12.5 V
l
+12.5V
+6.0V
Data output
+6.0V
High impedance
Program verify
H
l
H
Program inhibit
H
l
H
H
+12.5 V
Read
H
l
l
l
+5.0V
+5.0V
Data output
Ouput disable
H
l
l
H
+5.0V
+5.0V
High impedance
Standby
H
l
H
l/H
+5.0 V
+5.0V
High impedance
33
NEe
pPD78322 Family
Figure 11. Pin Functions in pPD78P322 PROM Programming Mode; 68-Pin PLee or Lee
c§l
Cl
-
. .,0).
c>
Cl
-
~<><~
m=~~~~~N-m~m~~~~~
OE
CE
o
(L){
As
A10
A11
A12
A13
A14
RESET
(Open)
(G)
~PD78P322
VSS
(Open)
Ao
NoIII:
Reconvnended connecUons for pins not used du~ng
PROM progl8lllmlng:
(L) Connect to VSS through a resistor.
(G) Connect to VSS'
(Open) No connection.
83CL-933iB
34
NEe
pPD78322 Family
Figure 12. Pin Functions in pPD7BP322 PROM Programming Mode; SO-Pin QFP or LCC
~
c
~
~
So
8~
52-~~><~
80 79 78 77 78 75 74 73 72 71 70 89
(G)
(NC)
(NC)
OE
CE
(L){
As
A'0
A11
A12
A'3
(NC)
A'4
RESET
(Open)
(G)
VSS
(Open)
Ao
(NC)
A,
(NC)
2
3
4
5
8
7
8
9
10
11
12
13
14
15
18
17
18
19
20
21
22
23
24
sa S7 sa 65
84
S3
S2
81
80
59
58
0
57
"P078P322
58
55
54
53
52
51
50
49
48
47
48
45
44
43
42
41
(Open)
•
Note:
Recommended connect!ons for pfns not used durtng
PROM programming:
(L) Connect to Vss through a resistor.
.
1
,:
I
(G) ConnacttoVSS.
(Open) No connection
(NC) Connect to VSS to prevent noise.
83Cl-9336B
35
NEe
pPD78322 Family
PROM Write Procedure
PROM Read Procedure
Data can be written to the PROM by the following
procedure.
The contents of the PROM can be read out to the
external data bus (Do - 07) by the following procedure.
(1) Set the pins not used for Qrogramming as indicated in figure 11 or 12. Set RESET high and AVoo
low. CE and OE should be high.
(1) Set the pins not used for programming as indicated
infi~ 11 or 12. Set RESET high and AVOD low. CE
and OE should be active high.
(2) Supply + 6.0 V to Voo pin and + 12.5 V to Vpp pin.
(2) Supply +5 V to VOD pin and Vpp pin.
(3) Provide initial address to pins Ao - A14.
(3) Input address of data to be read to pins Ao - A14.
(4) Provide write data.
(4) Put an active-low pulse on CE and OE pins.
(5) Input a 1-ms program pulse (active low) to CE pin.
(5) Data is output to pins Do - 07.
(6) Use verify mode (pulse OE low) to test data. If data
has been written, proceed to step 8; if not, repeat
steps 4-6. If data cannot be written in 25 attempts,
go to step 7.
Program Erasure
(7) Classify PROM as defective and cease write operation.
(8) Perform one additional write with a program pulse
width (in ms) equal to 3 times the number of writes
performed in step 5.
(9) Increment address.
(10) Repeat steps 4-9 until last address is programmed.
36
The UV EPROM can be erased by exposing the window
to light having a wavelength shorter than 400 nm,
including ultraviolet, direct sunlight, and fluorescent
light. To prevent unintentional erasure, mask the window.
Typically, data is erased by 254-nm ultraviolet rays. A
minimum lighting level of 15 Ws/cm 2 (ultraviolet ray
intensity x exposure time) is required to completely
erase the written data. Erasure by an ultraviolet lamp
rated at 12,000 pW/cm 2 takes 15 to 20 minutes. Remove
any filter on the lamp and place the device within 2.5 cm
of the lamp tubes.
NEe
pPD78322 Family
DC Programming Characteristics
TA = 25 ±5'C; Vss = OV
Parameter
Symbol
Symbol (Note 1)
Min
High-level input voltage
VIH
VIH
2.2
-0.3
Low-level input voltage
VIL
VIL
Input leakage current
ILiP
III
High-level output voltage
VOH
VOH
VOL
Low-level output voltage
VOL
A9 pin input current
lAg
Max
Typ
Voop
+
Unit
0.3
0.6
V
±10
/JA
2.4
0.45
V
IOL = 2.0 mA
±10
/J A
A9 (P201NMQ
O:s Vo :s VOOP. OE = VIH
ILO
10
/J A
liP
±10
/JA
Voop power supply voltage
Voop
Vpp
Vpp
5.75
6.0
6.25
V
4.5
5.0
5.5
V
12.6
V
12.2
12.5
Vpp
V~~p
power supply current
100
Vpp power supply current
100
Ipp
Ipp
VI :s VOOP (Note 2)
IOH = -400/JA
Output leakage current
VPP power supply voltage
o :s
V
PROG pin high-voltage input current
Voo
Condition
V
= Voop
Program memory write mode
V
10
30
mA
10
30
mA
Program memory read mode
CE = VIL. VI = VIH
10
30
mA
Program memory write mode
CE = VIL. OE = VIH
100
/J A
Program memory read mode
Notes:
(1) Corresponding symbols for the /JPD27C256A
(2) VOOP is the VOO pin during programming
AC Programming Characteristics
TA = 25 ±5'C; VSS = 0 V
Parameter
Address setup time to CE
Symbol
~
Data to to OE ~ delay time
Input data setup time to CE
Symbol (Note 1)
tSAC
~
Min
tOES
2
/Js
tSIOC
tos
2
/Js
2
/Js
Input data hold time after CE t
tHCID
tOH
2
Output data hold time after OE t
tHOOO
tOF
o
tsvPc
!yps
2
Voop setup time before CE ~
tsvoc
!Yos
Initial program pulse width
twL1
0.95
Additional program pulse width
twL2
2.65
Address to data output time
tOAOO
DE
toooo
toE
Data hold time after OE ~
tHCOO
tOF
Data hold time after address not valid
tHAOO
j
to data output time
Unit
toooo
tHCA
~
Max
/Js
Address hold time after CE t
Vpp setup time before CE
Typ
2
Condition
/Js
130
ns
/Js
2
/Js
1.0
1.05
ms
78.75
ms
2
/Js
OE = VIL
/JS
o
o
130
ns
ns
OE = VIL
Notes:
(1) Corresponding symbols for the /JPD27C256A.
37
NEe
pPD78322 Family
PROM Timing Diagrams
Write Mode
X Repetitions
A
~w~loE
AcrA12
~
-.
~
tSIDC-
Verily
"1'"
EtIecIIw address
r-
-1
tSAC
~
Da1a1npul
Da1aoutput
-. ~tJID
I+-
-,
I+-tHOOD
~j
Da1alnput
I-
Vpp
vpp
-1
-.
,.
AddItional Write
I+- tSVPC
~
tsvoc
1/
"
'----'
tWLl
~
-.
i i: l~tDOOD
tDDOO
S
"'
No1ae:
[1) VDDP must be applied before Vpp Is appled and
must be removed after Vpp Is removed.
(2) Vpp must not exceed +13 V Including overshoot voltage.
38
X-
l
I
J
tWL2
I
tHCA
~
-l.~
-'
-
(
NEe
IlPD78322 Family
PROM Timing Diagrams (cent)
Read Mode
).
(
Effective addrass
tHCOD
r--
!+-tOOODt DAOD
HI-Z
---------------4
tHAoD -+
Detaoutput
~
>--
HI-Z
-------83YL.....e
..
I
39
NEe
pPD78322 Family
INSTRUCTION SET
The pPD78322 family instruction set features 8- and
is-bit data transfer, arithmetic, and logic instructions
and single-bit manipulation instructions. String manipulation instructions are also included. Branch instructions exist to test individual bits in the program status
word, the i6-bit accumulator, the special function registers, and the saddr portion of on-chip RAM. Instructions range in length from 1 to 6 bytes depending on the
instruction and addressing mode.
Instruction Set Symbols (cont)
Symbol
Definition
word
16 bits of immediate data or label
byte
8 bits-of immediate data or label
jdisp8
8-bit two's complement displacement (immediate
data displacement value -128 to +127)
bit
3 bits of immediate data (bit position in byte), or
label
n
3 bits of immediate data
!addrl6
16-bit absolute address specified by an immediate
address or label
Flag Column Indicators
Symbol
Action
(blank)
No change
o
Setto 0
Set to 1
$addrl6
Relative branch address or label
addr16
16-bit address
!addrl1
II-bit immediate address or label
addrll
0800H-OFFFH: 0800H + (II-bit immediate
address), or label
addr5
0040H-007EH: 0040H + 2 X (5-bit immediate
address), or label
x
Set or cleared according to result
P
PIV indicates parity of result
v
PIV indicates arithmetic overflow
A
A register (8-bit accumulator)
R
Restored from saved PSW
x
X register
B
B register
Instruction Set Symbols
C
C register
Symbol
Definition
D
D register
RO, Rl, R2, R3, R4, R5, R6, R7, R8, R9, RIO, Rll,
R12, R13, R14, R15
E
E register
H
H register
rl
RO,Rl,R2,R3,R4,R5,R6,R7
L
L register
r2
C,B
RO-RI5
Register 0 to register 15
Register pair AX (16-bit accumulator)
rp
RPO,RP1,RP2, RP3,RP4, RP5, RP6, RP7*
AX
rpl
RPO,RP1,RP2,RP3,RP4,RP5,RP6,RP7*
BC
Register pair BC
rp2
DE, HL, VP, UP
DE
Register pair DE
sfr
Special function register, 8 bits
HL
Register pair HL
sfrp
Special function register, 16 bits
RPO-
Register pair 0 to register pair 7
post
RPO, RP1, RP2, RP3, RP4, RP5/PSW, RP6, RP7. Bits
set to 1 indicate register pairs to be pushed/
popped to/from stack; RP5 pushed/popped by
PUSH/POP, SP is stack pointer; PSW pushed/
popped by PUSHU/POPU, RP5 is stack pointer.
RP7
Register indirect: [DE], [HL], [DE+], [HL+], [DE-] ,
[HL-], [VP], [UP]
mem
Base Index Mode: [DE+ A], [HL+ A], [DE+ B],
[HL+ B], [VP+ DE], [VP+ HL]
Base Mode: [DE+ byte], [HL+ byte], [VP+ byte],
[UP+ byte], [SP+ byte]
Index Mode: word [A]. word [B], word [DE], word
[HL]
saddr
saddrp
40
FE20-FFI FH: Immediate byte addresses one byte
in RAM, or label
FE20-FF1FH: Immediate byte (bit 0=0) addresses
one word in RAM, or label
PC
Program counter
SP
Stack pointer
UP
User stack pointer (RP5)
psw
Program status word
PSWH
High-order 8 bits of PSW
PSWL
Low-order 8 bits of PSW
CY
Carry flag
AC
Auxiliary carry flag
Z
Zero flag
PIV
Parity/overflow flag
S
Sign flag
TPF
Table position flag
NEe
pPD78322 Family
Instruction Set Symbols (cont)
Symbol
Definition
RBS
Register bank select flag
RSS
Register set select flag
IE
Interrupt enable flag
STBC
Standby control register
WDM
Watchdog timer mode register
( )
Contents of the location whose address is within
parentheses; (+) and (-) indicate that the address
is incremented after or decremented after it is
used
(()
Contents of the memory location defined by the
quantity within the sets of parentheses
xxH
Hexadecimal quantity
High-order 8 bits and low-order 8 bits of X
• rp and rpl describe the same registers but generate different
machine code.
41
NEe
JlPD78322 Family
Instruction Set
Flags
Mnemonic
Operand
Operation
Bytes
S
z
AC
PN
CY
X
X
X
X
X
X
X
X
X
X
8·Bit Data Transfer
MOV
XCH
rl, #byte
rl - byte
2
saddr, #byte
(saddr) - byte
3
sfr, #byte (Note 1)
sfr - byte
3
r,r1
r-rl
2
A,rt
A-rl
A, saddr
A - (saddr)
saddr, A
(saddr) .... A
2
saddr, saddr
(saddr)
3
A, sfr
A-sfr
2
sfr,A
sfr-A
2
A, mem (Note 2)
A- (mem)
A,mem
A - (mem)
mem, A (Note 2)
(mem) -A
<-
2
(saddr)
2-4
mem,A
(mem) -A
A, [saddrp]
A ... «saddrp»
2
[saddrp], A
«saddrp» - A
2
A,laddrl6
A .... (addrI6)
4
laddrl6, A
(addrI6) .... A
4
PSWL, #byte
PSWL .... byte
3
PSWH, #byte
PSWH .... byte
3
2-4
PSWL,A
PSWL .... A
2
PSWH,A
PSWH-A
2
A, PSWL
A -PSWL
2
A, PSWH
A-PSWH
2
A, rl
A-rl
r,rl
r - rl
A,mem
A- (mem)
2-4
2
A, saddr
A - (saddr)
2
A, sfr
A-sfr
3
A, [saddrp]
A ... «saddrp»
2
saddr, saddr
(saddr) ... (saddr)
3
16-Bit Data Transfer
MOVW
42
rpl, #Word
rpl -word
3
saddrp, #Word
(saddrp)
4
sfrp, #Word
sfrp - word
4
rp, rpl
rp- rpl
2
AX, saddrp
AX .... (saddrp)
2
saddrp, AX
(saddrp) .... AX
2
saddrp, saddrp
(saddrp) .... (saddrp)
3
<-
word
NEe
pPD78322 Family
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
s
z
AC
PN
CY
16-Bit Dsts Trsnsfer (cont)
MOVW
(oonl)
XCHW
AX, sfrp
AX +- sfrp
2
sfrp, AX
sfrp +- AX
2
rp1, laddr16
rp1 +- (addr16)
4
!addr16, rp1
(addr16) - rp1
4
AX,mem
AX -
(mem)
2-4
mem, AX
(mem) +- AX
2-4
AX, saddrp
AX ... (saddrp)
2
AX,sfrp
AX -sfrp
3
saddrp, saddrp
(saddrp) ... (saddrp)
3
rp, rp1
rp ... rp1
2
AX, mem
AX- (mem)
2-4
8·Bit Arithmetic
ADD
ADDC
SUB
__
A_,_#_by~t_e__________
A_,_C_Y__
+-_A__+~by~t_e__________________________
2 _____X
____X
_____X
______V_____X__
saddr, #byte
(saddr), CY +- (saddr) + byte
3
X
X
X
V
X
sfr, #byte
sfr, CY - sfr + byte
4
X
X
X
V
X
r,r1
r,CY+-r+r1
2
X
X
X
V
X
A, saddr
A, CY+-A + (saddr)
2
X
X
X
V
X
A,sfr
A,CY+- A+ sfr
3
X
X
X
V
X
3
X
X
X
V
X
2-4
X
X
X
V
X
saddr, saddr
(saddr), CY - (saddr) + (saddr)
A, mem
A, CY -
A + (mem)
m_e_m_,~A
(m~em
~.
___________(m
__
em_)_,_C_Y___ __
)_+_A
______________________2_-4_____X____X
_____X______V_____XX__
_ _A,#byte
A,CY+-A+ byte + CY
2
X
X
X
V
....
saddr, #byte
(saddr), CY - (saddr) + byte + CY
3
X
X
X
V
X
sfr, #byte
sfr, CY +- sfr + byte + CY
4
X
X
X
V
X
X
r,r1
r,CY+-r+r1+CY
2
X
X
X
V
A, saddr
A, CY +- A + (saddr) + CY
2
X
X
X
V
X
A,sfr
A,CY-A+ sfr+ CY
3
X
X
X
V
X
saddr, saddr
(saddr), CY ... (saddr) + (saddr) + CY
3
X
X
X
V
X
A, mem
A, CY ... A + (mem) + CY
2-4
X
X
X
V
X
mem, A
(mem). CY +- (mem) + A + CY
2-4
X
X
X
V
X
A,#byte
A,CY+-A-byte
2
X
X
X
V
X
saddr, #byte
(saddr). CY +- (saddr) - byte
3
X
X
X
V
X
sfr, #byte
sfr, CY +- sfr - byte
4
X
X
X
V
X
r,r1
r,CY-r-r1
2
X
X
X
V
X
A, saddr
A, CY+-A- (saddr)
2
X
X
X
V
X
A,sfr
A,CY+-A-sfr
3
X
X
X
.v
X
saddr, saddr
(saddr), CY +- (saddr) - (saddr)
3
X
X
X
V
X
A,mem
A,CY+-A-(mem)
2-4
X
X
X
V
X
mem, A
(mem), CY +- (mem) - A
2-4
X
X
X
V
X
43
NEe
IIPD78322 Family
Instruction Set (cont)
Flags
MnemonIc
Operand
Operation
Bytes
S
Z
AC
PN
CY
S·Bit Arithmetic (cont)
SUBC
A, #byte
A, CY -A- byte- CY
2
X
X
X
V
X
saddr, #byte
(saddr), CY +- (saddr) - byte - CY
3
X
X
X
V
X
sir, #byte
sir, CY - sir - byte - CY
4
X
X
X
V
X
r,r1
r,CY-r-rl-CY
2
X
X
X
V
X
A, saddr
A, CY - A- (saddr) - CY
2
X
X
X
V
X
A, sir
A, CY-A-slr-CY
3
X
X
X
V
X
sad dr, saddr
(saddr), CY - (saddr) - (saddr) - CY
3
X
X
X
V
X
A,mem
A, CY-A- (mem) -CY
2-4
X
X
X
V
X
mem, A
(mem), CY +- (mem) - A - CY
2-4
X
X
X
V
X
A, #byte
A - A /\ byte
2
X
X
P
saddr, #byte
(saddr) +- (saddr) /\ byte
3
X
X
P
sir, #byte
sir +- sir /\ byte
4
X
X
P
r,rl
r<- r/\ rl
2
X
X
P
A, saddr
A- A /\ (saddr)
2
X
X
P
A, sir
A- A/\ sir
3
X
X
P
saddr, saddr
(saddr)<- (saddr) /\ (saddr)
3
X
X
P
A,mem
A +- A /\ (mem)
2-4
X
X
P
mem, A
(mem) - (mem) /\ A
2-4
X
X
P
A, #byte
A-A V byte
2
X
X
P
saddr, #byte
(saddr) <- (saddr) V byte
3
X
X
P
sir, #byte
sir +- sir V byte
4
X
X
P
r,rl
r+- rV rl
2
X
X
P
A, saddr
A - A V (saddr)
2
X
X
P
A, sir
A<-A V sir
3
X
X
P
saddr, saddr
(saddr)+- (saddr) V (saddr)
3
X
X
P
A,mem
A-A V (mem)
2-4
X
X
P
mem, A
(mem) - (mem) V A
2-4
X
X
P
A, #byte
A-AVbyte
2
X
X
P
saddr, #byte
(saddr) - (saddr) V byte
3
X
X
P
sir, #byte
sir <- sir V byte
4
X
X
P
r,rl
r-rVrl
2
X
X
P
A, saddr
A _ A V (saddr)
2
X
X
P
A, sir
A-AVslr
3
X
X
P
saddr, saddr
(saddr)- (saddr) V (saddr)
3
X
X
P
A,mem
A-AV(mem)
2-4
X
X
P
mem, A
(mem) - (mem) V A
2-4
X
X
P
S·BitLogic
AND
OR
XOR
44
NEe
pPD78322 Family
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
5
z
AC
PN
CY
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
v
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
v
v
v
8·Bit Logic (cont)
CMP
A, #byte
A-byte
2
.add" #byte
(sadd,) - byte
3
sf" #byte
sf,- byte
4
",1
,-,1
2
A, sadd'
A - (sadd,)
2
A, sf'
A -sf'
3
sad dr, sadd,
(sadd,) - (sadd,)
A,mem
A-(mem)
2-4
mem,A
(mem) - A
2-4
3
x
x
x
v
v
v
v
v
v
v
v
16-Bit Arithmetic
ADDW
SUBW
CMPW
AX, #Wo,d
AX, CY ~ AX + wo,d
sadd,p, #Wo,d
(sadd,p), CY ~ (sadd,p)
sf,p, #Wo,d
sf,p, CY +- sfrp
wo,d
5
'p, 'pi
'p, CY ~ 'p
2
AX, sadd,p
AX,
+ 'pi
CY +- AX + (saddrp)
2
AX, sf,p
AX, CY ~ AX + sfrp
3
x
x
x
x
x
x
saddrp, saddrp
(saddrp), CY ~ (sadd,p) + (saddrp)
3
x
x
AX, #Word
AX, CY +- AX - wo,d
3
x
x
x
x
x
x
+
3
+
wo,d
4
x
v
v
x
v
x
v
v
v
v
sadd,p, #Wo,d
(saddrp), CY ~ (sadd,p) - wo,d
4
sfrp, #Word
sfrp, CY ~ sfrp - word
5
rp, rpl
rp, CY +-- 'p - rpl
2
AX, saddrp
AX, CY
~
2
x
x
x
x
x
X
x
x
AX, sfrp
AX, CY ... AX - sf,p
3
X
X
X
saddrp, saddrp
(saddrp), CY ~ (saddrp) - (saddrp)
3
X
X
AX, #Wo,d
AX -word
3
X
X
saddrp, #Wo,d
(saddrp) - wo,d
4
X
X
X
sfrp, #Word
sfrp - word
5
X
X
X
rp, rpl
rp - rpl
.2
X
X
AX, saddrp
AX - (sadd,p)
2
X
AX, sfrp
AX -sfrp
3
saddrp, saddrp
(saddrp) - (saddrp)
3
AX - (sadd,p)
X
x
x
x
x
x
x
x
x
X
X
v
v
v
x
x
X
v
X
X
v
v
X
X
X
v
v
X
X
v
X
X
X
X
X
X
X
X
v
v
X
X
X
X
Multiplication/Division
MULU
rl
AX +-A x rl
2
DIVlJIIV
rl
AX (quotient), rl (remainder) +-- AX + rl
2
MULlJIIV
rpl
AX (high-order 16 bits), rpl (low-order 16 bits)
+--AX x rpl
2
DIVUX
rpl
AXDE (quotient), rpl (remainder)
MULW
(Note 3)
rpl
AX (high-order 16 bits), rpl (low-order 16
bits) +- AX x rpl
+-
AXDE + rpl
2
2
45
..
NEe
pPD78322 Family
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
S
z
X
X
AC
PN
X
X
V
X
X
V
X
X
X
V
X
X
X
V
CY
Incren7enV£Jecren7ent
INC
DEC
INCW
rl
rl-rl + 1
saddr
(sadd~ -
rl
rl-rl-l
saddr
(saddr) - (saddr) - 1
rp2
rp2-rp2+1
(sadd~ + 1
2
2
saddrp
(saddrp) - (saddrp) + 1
rp2
rp2-rp2-1
saddrp
(saddrp) - (saddrp) - 1
3
ROR
r1, n
(CY, rI 7 -rl o, rl m_1-rlm! xntimes
2
P
X
ROL
rl, n
(CY, rio - r17' rlm+ 1 - rim! x n times
2
P
X
RORC
rl, n
(CY - rio, r17 - CY, rl m-1 - rim) x n times
2
P
X
ROLC
rl, n
(CY - r17' rio - CY, rlm+ 1 - rim) x n times
2
P
X
SHR
r1, n
(CY- rio, r17 - 0, rlm-1 - rim) x n times
2
X
X
0
P
X
SHL
rl, n
(CY- r1 7, rio - 0, rlm+ 1 - rlm) x n times
2
X
X
0
P
X
SHRW
rpl, n
(CY- rplo, rp115 - 0, rpl m-1 - rpl ml x n times
2
X
X
0
P
X
SHLW
rpl, n
(CY- rp115, rplo - 0, rpl m+ 1 - rpl m) x n times
2
X
X
0
P
X
ROR4
[rpl]
A3-0 - (rpl)3-0' (rplh-4 (rpl)3-0 - (rplh_4
A3-0'
2
ROL4
[rpl]
A3-0 - (rpl)7_4' (rpl)3-0 (rplh_4 - (rpl)3-Q
A3-0'
2
DECW
3
ShifVRotatB
Be£J AdjusttnBnt
ADJBA
Decimal adjust accumulator after add
2
X
X
X
P
X
ADJBS
Decimal adjust accumulator after subtract
2
X
X
X
P
X
£Jata Expansion
CVTBW
X - A, Ae-o-A7
Bit Manipulation
MOVI
46
CY, saddr. bit
CY ... (saddr.bit)
3
X
CY, sfr.bit
CY-sfr.bit
3
X
CY, A.bit
CY-A.bit
2
X
CY, X.bit
CY-X.bit
2
X
CY, PSWH.bit
CY - PSWH.bit
2
X
CY, PSWL.bit
CY - PSWL.blt
2
X
saddr.blt, CY
(saddr.bit) - CY
3
sfr.blt, CY
sfr.bit +- CY
3
A.bit, CY
A.bit-CY
2
X.bit, CY
X.bit+- CY
2
PSWH.blt, CY
PSWH.bit - CY
2
PSWL.bit, CY
PSWL.bit-CY
2
X
X
X
X
NEe
pPD78322 Family
Instruction Set (cant)
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
AC
PN
CY
Bit Manipulation (cont)
AND1
OR1
XOR1
SET1
CY, saddr. bit
CY +- CY A (saddr.bit)
3
X
CY, Isaddr.bit
CY +- CY A (saddr.bit)
3
X
CY, sfr.bit
CY +- CY A sfr.bit
3
X
CY, Isfr.bit
CY +- CY A sfr.bit
3
X
CY, A.blt
CY +- CY A A.blt
2
X
CY, IA.bit
CY +- CY A A.bit
2
X
CY, X.bit
Cy ... Cy A X.bit
2
X
CY, /X.bit
CY ... CY A X.bit
2
X
CY, PSWH.bit
CY +- CY A PSWH.bit
2
X
CY, IPSWH.bit
CY +- CY A PSWH.blt
2
X
CY, PSWL.blt
CY +- CY A PSWL.bit
2
X
CY, IPSWL.bit
Cy ... CY A PSWL.blt
2
X
CY, saddr. bit
CY - CY V (saddr.bit)
3
X
CY,/saddr.bit
CY +- CY V (saddr.blt)
3
X
CY, sfr.bit
Cy ... CY V sfr.bit
3
X
CY,/sfr.bit
CY +- CY V sfr.bit
3
X
CY, Abit
CY +- CY V Abit
2
X
CY,/A.bit
CY +- CY V Abit
2
X
CY, X.bit
Cy ... CY V X.blt
2
X
CY, /X.blt
CY +- CY V X.bit
2
X
CY, PSWH.bit
CY +- CY V PSWH.blt
2
X
CY, IPSWH.bit
CY +- CY V PSWH.bit
2
X
CY, PSWL.bit
CY +- CY V PSWL.bit
2
X
CY, IPSWL.bit
CY +- CY V PSWL.bit
2
X
CY, saddr.bit
CY +- CY'if (saddr.bit)
3
X
CY, sfr.bit
CY +- CY 'if sfr.bit
3
X
CY, Abit
CY +- CY 'if A.bit
2
X
CY, X.bit
CY +- CY 'if X.bit
2
X
CY, PSWH.bit
CY +- CY 'if PSWH.bit
2
X
CY, PSWL.bit
CY +- CY 'if PSWL.bit
2
X
saddr.bit
(saddr.bit) - 1
2
3
sfr.bit
sfr.bit +- 1
A.bit
A.bit-1
2
X.blt
X.bit+-1
2
PSWH.bit
PSWH.bit .... 1
2
PSWL.bit
PSWL.bit-1
2
X
X
X
X
X
47
•
NEe
IIPD78322 Family
Instruction Set (cant)
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
AC
PN
CY
X
X
X
X
X
X
X
X
X
X
Bit Manipulation (cont)
CLAI
NOT1
saddr.bit
(saddr.blt) - 0
2
sfr.bit
sfr.bit - 0
3
A.bit
A.bit-O
2
X.bit
X.bit-O
2
PSWH.bit
PSWH.blt-O
2
PSWL.bit
PSWL.bit-O
2
saddr.bit
(saddr.bit) <- (saddr.bit)
3
sfr.bit
sfr.blt -
3
sfr.bit
A.bit
A.bit - A.bit
X.bit
X.bit <- X.bit
2
PSWH.bit
PSWH.bit <- PSWH.bit
2
2
2
PSWL.bit
PSWL.bit- PSWL.bit
SETI
CY
CY ... 1
CLAI
CY
CY<-O
0
NOT1
CY
Cy ... CY
X
Subroutine Linkage
!addrl6
(SP-l)'" (PC + 3)H, (SP - 2) PC - addr16, SP ... SP - 2
3lL,
3
rp1
(SP-1) <- (PC + 2)H, (SP - 2) --- (PC + 2)l,
PC H - rp1 H, PCl <- rp1 l' SP ... SP - 2
2
[rp11
(SP-1) <- (PC + 2)H, (SP - 2) <- (PC + 2)l,
PCH - (rp1 + 1), PCl .... (rp1), SP --- SP - 2
2
CALLF
laddr11
(SP-1) <- (PC + 2)H, (SP - 2) <- (PC + 2)l,
PC I 5-11 <- 00001, PC lO- 0 <- addr11, SP <- SP - 2
2
CALLT
[addrS1
(SP-1) <- (PC + 1)H, (SP - 2) ... (PC + 1lL,
PCH <- (TPFx8000H + 2 x addrS + 41 H),
PCl'" (TPFx8000H + 2 x addrS + 40H), SP a:<
WDTO
ADe
IC:VDD
47
AD5
MODEl
48
AD4
Voo
45
ADa
CLKOUT
44
AD2
MODEO
43
AD1
X2
42
ADo
Xl
41
I'D7
9
40
POe
VSS
RESET
10
39
P05
P2(YNMI
11
38
P04
P2111NTPO
12
37
P03
P2i1NTPl
13
38
Voo
P2s11NTP2
14
35
P02
P24fINTP3
15
34
POl
P2&'TI
le
33
POo
CD
~ ~ ~ ~ N ~ ~ ~ ~ ~ ~ N
en
N
0
(f)
,...
C')
!)j
....
"""""
2
NEe
IIPD78352 Family
Pin Configurations (cont)
64-Pin Plastic QFP and Ceramic LCC (pPD78352A/P352)
WDTO
2
47
P4&,ADs
MOOE1
3
4S
P44AD4
Voo
4
45
P4iA03
CLKOUT
5
44
P42'A02
MOOED
S
43
P41/A01
X2
7
42
p4o'ADo
X1
8
9
41
~
40
POe
Pas
PD4
VSS
RESET
~
P4&'AOS
Voo
10
39
P2o'NMI
11
39
P21f1NTPO
12
37
PD3
P22'1NTP1
13
39
VOO
P2:i1NTP2
14
35
P02
P24fINTP3
15
34
P01
P25"J1
18
33
POe
~ ~ ~ ~
N
~ ~ ~ ~ ~ ~ ~ ~
2
~
::J
a~~_.
________________________________________________~________________________~
3
i
NEe
pPD7'S352 Family
Pin Functions; Normal Operating Mode
Symbol
Function
POo- PO]
Port 0; B-bit, blt-seleotable 110 port
Alternate Symbol
Alternate Function
Port I; B-blt, bit-seleo1able VO port
P20
Port 2; 6-bit input port
NMI
External nonmaskable interrupt
INTPO
INTPI
INTP2
INTP3
Maskable external interrupts
TI
External input for timer I
Port 3; a-bit, bit-seleo1able VO port
PWMO
PWMI
Pulse-width modulated outputs
P40 - P47
Port 4; byte-seleotable VO port ClIPD78352A/
P352)
ADo-AIq
Low-order a bits of the multiplexed external
address/data bus
P50 - P57
Port 5; bit-seleotable VO port ClIPD78352A/P352)
PSo
Port 9; 4-bit, bit-seleo1able VO port
ClIPD78352A/P352). For 78350, P90 functions as
RD and PSt functions as WRsignals only. P92
and P93 are not provided for 78350.
P~-
P3-r
ASTB
Address strobe output; used to latoh address for
external memory.
CLKOUT
Output of the system olook
IC
Internally oonneoted; must be left open ..
MODEO
Conneot to VDD for pPD78350 and pPD78P352
In programing mode. Conneot to Vss for normal
operation of pPD78352A/P352.
The level of this pin cannot be ohanged during
normal operation.
MODEl
Always oonneot to Vss. The level of this pin
cannot be ohanged during normal operation.
RESET
External system reset Input
WAIT
A low-level input adds wait states to the
external bus oyole; used by very-slow memory
andlor peripherals (only for 78352A/P352).
WDro
Open-drain output from the watohdog timer
XI
Crystal oonneo1ion or external olook input
X2
Crystal oonneo1lon or open for external olook
VDD
+5-volt power Input
Vss
Ground
4
High-order a bits of the external address bus
RD
External read strobe output
WR
External write strobe output
IC
IC
Internally connected; must be left open
ClIPD78350).
NEe
pPD78352 Family
Block Diagram
Execution
BCU
_X1
P2dNMI
Intemal
Program
Memory
32KBytes*
P21J1NTPO
P2~NTP1
P2aIINTP2
X2
RESET
ASTB
System
Control
P24INTP3
&
Bus
Control
Peripheral
P2sfT1
-I
llmer Untt
I<=:>
Micro Sequence
I
Control
Micro ROM
&
Prefetch
Control
ClKOUT
RD( P90)
WR(P91)
WAIT
_MODE1
_MODEO
RAM
384 Bytes
I
:~=~ ~ PWMOu~ut I<=:>
WDTO
+----i
WDT
* 32K bytes mask ROM on ~PD78352A;
32K bytes UV EPROM or OTP ROM on ~PD78P352.
5
NEe
IIPD78352 Family
FUNCTIONAL DESCRIPTION
Internal Program Memory
Central Processing Unit
The pPD78352A contains 32K bytes of mask ROM;
pPD78P352 contains 32K bytes of UV EPROM or onetime programmable ROM. Instructions are fetched from
this program memory at a maximum rate of 1 byte
every two internal system clocks. The pPD78350 does
not have internal program memory.
The central processing unit (CPU) of the pPD78352
family features 16-bit arithmetic including 16 x 16-bit
multiply, both unsigned and signed, and 32 x 16-bit
unsigned divide (producing a 32-bit' quotient and a
16-bit remainder). The signed multiply executes in 1.12
ps and the divide in 3.44 ps at 25 MHz (0.875 and 2.69
ps, respectively, for pPD78352A/P352 at 32 MHz).
Also, a multiply-and-accumulate instruction, "MACW
n," performs a signed multiply on factors from a pair of
tables and sums the results in the 32-bit register AXDE.
The total execution time for 10 terms is 17.2 ps at 25
MHz for the pPD78350 and 13.44 ps at 32 MHz for the
pPD78352A/P352.
A CALLT vector table and a CALLF area decrease the
number of bytes in the call instructions for commonly
used subroutines. A i-byte call instruction can access
up to 32 subroutines through their addresses in the
CALLTvectortable. A 2-byte call instruction can access
any routine beginning in a specific CALLF area.
The internal system clock (fcuo is generated by dividing the oscillator frequency by 2. Therefore, at the
maximum oscillator frequency of 25 MHz for the
pPD78350, the clock is 12.5 MHz. Since instructions
execute in two or more cycles, the minimum instruction
time is 160 ns. For the pPD78352A/P352 running at 32
MHz, the clock is 16 MHz and the minimum instruction
time is 125 ns.
Internal RAM
The pPD78352 family has total of 640 bytes of internal
RAM. The upper 256-byte area (FEOOH-FEFFH) features
high-speed access of one ortwo internal system clocks
per word of data depending on the addressing mode
and is known as "Main RAM." The remainder (FC80HFDFFH) is accessed at the same speed as external
memory (1 byte per three internal system clocks) and is
known as "Peripheral RAM." The general register banks
and the macro service control words are stored in Main
RAM. The remainder of Main RAM and any unused
register bank locations are available for general storage.
Main RAM Access Speed
Access Mode
Memory access
Saddr access
Register access
6
Internel System Clocks (fcud
2
External Memory
The pPD78352 family has a 64K-byte address space.
The pPD78352A/P352 can access 0, 256, 4K, 16K, or 32K
bytes of external memory in the area from 8000H to
FDFFH. External memory can be either ROM, RAM, or
peripheral as required. The pPD78352A/P352 has an
8-bit wide external data bus and a 16-bit wide external
address bus. The low-order 8 bits of the address bus
are multiplexed to provide the 8-bit data bus at 110 port
4.
High-order address bits are taken from port 5 as required. Address latch, read, and write strobes are also
provided. In the pPD78352A/P352, the memory mode
register (MM) controls the size of the external memory
It can be programmed to use 0, 4, 6, or 8 bits from port
5 for the high-order address. Any remaining port 5 bits
can be used for I/O.
The pPD78350 does not have ports 4 and 5. It has eight
dedicated high-order address lines and eight dedicated address/data lines. All memory below address
FC80H must be external, and the MM register is not
used.
The programmable wait control register (PWC) allows
the programmer to specify one or two additional wait
states if they are required for slow-speed memory or
external peripheral devices. These wait states for internal and external memory are specified independently
in 16K-blocks. If additional wait states are required, an
external WAIT pin is provided.
In addition, by using the AWO and AW1 bits of the PWC
register, the width of the ASTB signal can be increased
by one cycle to allow more precharge time for dynamic
RAMs or more address decoding time. This address
wait signal can be enabled in 32K-byte blocks. See
figure 1.
NEe
pPD78352 Family
Figure t. Programmed Wait Control Register
15
16K Memory Block
Walt Control Register Bits
o
7
8
Walt States
Data Access Clocks
Fetch Cycle Mode
Fetch Clocks
00OOH-3FFFH
PWC1, PWCO
00
01
10
0
1
2
3
4
5
Normal
3
4
5
11
0
4
High-speed
2
4000H-7FFFH
PWC3, PWC2
00
01
10
0
1
2
3
4
5
Normal
3
4
5
11
0
4
High-speed
2
8000H-BFFFH
PWC5, PWC4
00
01
10
0
1
2
3
4
5
Normal
3
4
5
11
-
N/A
N/A
N/A
COOOH-FC7FH,
*FFDOH-FFDFH
PWC7, PWC6
00
01
10
0
1
2
3
4
5
Normal
3
4
5
11
-
N/A
N/A
N/A
FCBOH-FDFFH
PWC7, PWC6
00
01
10
0
Normal
0
0
3
3
3
3
3
11
-
N/A
N/A
3
N/A
* Data in the SFR external aooess area, FFDOH-FFDFH, oannot be
fetohed.
32K Memory Block
OOOOH-7FFFH
8000H-FC7FH
Address Wait
Walt Control Register Bits
AWO
AW1
0
Disabled
1
Enabled
0
Disabled
1
Enabled
/
7
NEe
pPD78352 Family
Program Fetch
The pPD78352 family devices allow opcode fetch in the
area between OOOOH and FDFFH; they contain a 5-byte
instruction prefetch queue.The bus control unit can
fetch an instruction byte from memory during cycles in
which the execution unit is not using the memory bus.
If the instruction byte is fetched from on-chip memory,
two internal system clocks are required for each byte,
and the queue can hold 5 bytes. If the instruction is
fetched from external memory, three internal system
clocks are required for each byte, and the queue can
hold 3 bytes. For programs located in internal memory,
the PWC register also can be programmed to allow 1
byte to be fetched every two, three, four, or five internal
system clocks.
CPU Control Registers
Program Counter. The program counter is a 16-bit
register that holds the address of the next instruction
to be executed. After reset line goes high, the program
counter is loaded with the address stored in locations
OOOOH and 0001H.
Stack Pointer. The stack pointer is a 16-bit register
that holds the address of the last item pushed onto the
stack. It is decremented before new data is pushed
onto the stack and incremented after data is popped
off the stack.
CPU Control Word. The CPU control word (CCW)
selects the origin of the interrupt vector and CALLT
tables. If the TPF bit (bit 1) is zero, the origin is OOOOH;
if the TPF bit is one, the origin is 8000H. The CCW is a
special function register located at address FFC1H.
The addresses of the vectors for the RESET input,
operation-code trap, and BRK instruction are fixed at
OOOOH, 003CH, and 003EH, respectively, and are not
altered by the TPF bit.
Program Status Word. The program status word
(PSW) is a 16-bit register containing flags that are set or
reset depending on the results of an instruction. This
register can be written to or read from 8 bits at a time.
The high-order 8 bits are called the PSWH and the
low-order 8 bits are called the PSWL. The individual
flags can also be manipulated on a bit-by-bit basis. The
assignment of PSW bits follows.
8
7
6
5
4
3
2
o
7
6
5
4
3
2
o
PSWLI~_s~__z~I_R_ss~I_A_C~_IE~_P_N~I_O__~C~Y
UF
RBS2-RBSO
S
Z
RSS
AC
IE
PN
CY
User flag
Active register bank number
Sign flag (1 if last result was negative)
Zero flag (1 if last result was zero)
Register set selection flag
Auxiliary carry flag (carry out of 3 bit)
Interrupt enable flag
Parity or arithmetic overflow flag
Carry bit (or 1-bit accumulator for logic)
General Registers
There are sixteen 8-bit general registers, which can
also be paired to function as 16-bit registers. A complete set of 16 registers is mapped into each of eight
program-selectable register banks stored in Main RAM.
Three bits in the PSW specify the active register bank.
Registers have functional names (like A, X, B, C for 8-bit
registers and AX, BC for 16-bit registers) and absolute
names (like R1, RO, R3, R2 for 8-bit registers and RPO,
RP1 for 16-bit registers). Each instruction determines
whether a register is referred to by functional or absolute name and whether it is 8 or 16 bits.
Two possible relationships may exist between the absolute and functional names of the first four register
pairs. The RSS bit in the PSW determines which of these
is active at any time. The effect is that the accumulator
and counter registers can be saved, and a new set can
be specified by toggling the RSS bit. Figure 2 illustrates the general register configuration.
NEe
pPD78352 Family
Figure 2. General Registers
RegIster Storsge
FE80H
Bank 7
lH
RSS=O
OH
r--~~J-~~1OX.(RPO)
Bank 8
r--~~J_~R2~_
BC(RP1)
BankS
R4_ _
' - _AS
_ ...1I _ _
!
R8_ _
,- _R7
_ ...1 _ _
RP3
Bank 3
Bank 2
!
R3
I R2
r----...1--RPl
r~~J-~~
RP2
Bank 4
RSS=1
Rl
RO
r----...1--RPO
VPH (R9) I VPdR8)
r--..J---VP(RP4)
1OX.(RP2)
r--~~J-~~
BC(RP3)
UPH(Rll).:.JI ____
UPdRl0)
___
UP (RP5)
Bank 1
_~R~J_E~~_
..
DE (RP8)
FEFOH
BankO
_~~J_L~l~_
HL(RP7)
FEFFH
FH
EH
1
Addressing
The pPD78352 family features 1-byte addressing of
both the special function registers and the portion of
on-chip RAM from FE20H to FEFFH. The 1-byte sfr
addressing accesses the entire SFR area, while the
1-byte saddr addressing accesses the first 32 bytes of
the SFR area and 224 bytes of the Main RAM.
There are nine addressing modes for data in main
memory: direct, register, register indirect with autoincrement or autodecrement, saddr, saddr indirect, SFR,
based, indexed, and based indexed. There are also
8-bit and 16-bit immediate operands. Figure 3 is the
memory map of the pPD78352 family.
The 16-bit SFRs and words of memory in these areas
can be addressed by 1-byte saddrp addressing, which
is valid for even addresses only. Since many instructions use 1-byte addressing, access to these locations
is almost as fast and as versatile as access to the
general registers.
9
NEe
JlPD78352 Family
Figure 3. Memory Map
Primary Vector Table
OOOOH
Intenupt
Vector Table
64 Bytes
(32 Addresses)
OOSFH
OO4OH
OOOOH
O8OOH
CALLT
Vector Table
64Bytas
(32 Addressas)
General Memory
--------CALLFArea
OFFFH
007FH
Address Space
64K Bytes
Alternate Vector Table
OOOOHr-...............~...............-1
8000H
Intenupt
Vector Table
64 Bytaa
(32Addressas)
Intemal
803FH
Mask ROM: ~PD78352A
PROM: ~PD78P352
8040H
Program Memory
CALLT
Vector Table
64 Bytes
(32 Addresses)
7FFFH _ _ _ _ _ _ _ _ _.F-____________...:807
:=F..:.;H:l...._ _ _ _ _ _ _ _...J
FCSOH
saddr Addressing
FE20H
Peripheral RAM
Extemal
Memory
Area
1--
FOFFH
Main
RAM
FFOOH
FC7FH
FFFFH - - - - - - - - -
~;:;-;,.;
-
-
-;e;-sta-;-~";
-- -
General RAM
-1-_ _--'-'FE7:::..;.FH,
FE80H -
---------
-
-
-
-
-
--
Register
Storage
Area
Special Function
Register Area
FFFFH
FF1FH
10
-
32 Bytaa 01 SFR Area
NEe
pPD78352 Family
Special Function Registers
The input/output ports, timers, capture and compare
registers, and mode and control registers for both the
peripherals and the CPU are collectively known as
special function registers. They are all memorymapped between F FOOH and F F F FH and can be accessed either by main memory addressing or by 1-byte
SFR addressing. All can be read under program control, and most can also be written. They are either a or
16 bits, as required, and many of the a-bit registers are
capable of single-bit access as well.
Locations FFDOH through FFDFH are known as the
external access area. Registers in external circuitry,
interfaced and mapped to these addresses, can be
addressed with SFR addressing. Table 1 lists the special function registers.
Table 1. Special Function Registers
Access Units (Bits)
Address
Register (SFR)
Symbol
R/W
1
8
FFOOH
PortO
PO
R/W
x
x
Undefined
FF01H
Port 1
Pl
R/W
x
x
Undefined
FF02H
Port 2
P2
R
x
x
Undefined
FF03H
Port 3
P3
R/W
x
x
Undefined
FF04H
Port 4 (Note 1)
P4
R/W
x
x
Undefined
FF05H
Port 5 (Note 1)
P5
R/W
x
x
Undefined
FF09H
Port 9 (Note 1)
P9
R/W
x
x
Undefined
16
State After Reset
FF10H-FF11H
Compare register 00
CTOO
R/W
x
FF12H-FF13H
Compare register 01
CT01
R/W
x
Undefined
FF14H-FF15H
Compare register 10
CM10
R/W
x
Undefined
FFl EH-FFl FH
Compare register 20
CM20
R/W
x
Undefined
FF20H
Port 0 mode register
PMO
R/W
x
x
FF21H
Port 1 mode register
PM1
R/W
x
x
FFH
FF23H
Port 3 mode register
PM3
R/W
x
x
FFH
FF25H
Port 5 mode register (Note 1)
PM5
R/W
x
x
FFH
FF29H
Port 9 mode register (Note 1)
PM9
R/W
x
x
xFH
Undefined
FFH
FF30H-FF31H
Timer register 0
TMO
R
x
OOH
FF32H-FF33H
Timer register 1
TM1
R
x
OOH
FF34H-FF35H
Timer register 2
TM2
R
x
OOH
FF38H
Timer control register 0
TMCO
R/W
x
x
OOH
FF39H
Timer control register 1
TMC1
R/W
x
x
OOH
FF3CH
External Interrupt mode register 0
INTMO
R/W
x
x
OOH
FF3DH
External Interrupt mode register 1
INTM1
R/W
x
x
OOH
FF43H
Port 3 mode control register 0
PMC3
R/W
x
x
OOH
FF62H
Port read control register
PRDC
R/W
x
x
OOH
FF64H
PWM control register
PWMC
R/W
x
x
OOH
FF66H
PWM buffer register 0
PWMO
R/W
PWM buffer register 1
PWM1
R/W
x
x
Undefined
FF6EH
x
x
FFA8H
In-service priority register
ISPR
R
x
x
OOH
FFAAH
Interrupt mode control register
IMC
R/W
x
x
80H
FFACH
Interrupt mask flag register
MKL
R/W
x
x
7FH
Undefined
11
NEe
pPD78352 'Family
Table 1. Special Function Registers (cont)
Access Units (Bits)
Address
Register (SFR)
FFACH-FFADH
Interrupt mask flag register (Note 2)
FFCOH
FFC1H
Symbol
R/W
MK
R!W
Standby control register (Note 3)
STBC
R!W
CPU control word
CCW
R!W
FFC2H
Watchdog timer mode register (Note 3)
WDM
R!W
FFC4H
Memory expansion mode register
MM
R!W
FFC6H-FFC7H
Programmable wait control register
PWC
R!W
FFDOH-FFDFH
External access area
FFEOH
Interrupt control register (INTOV)
FFE1H
FFE2H
1
x
x
8
16
State After Reset
x
xx7FH
x
0000 xOOOB
x
OOH
x
OOH
x
OOH
x
COAAH
x
Undefined
x
43H
FFE3H
Interrupt control register (INTCM10)
CMIC10
R!W
x
x
x
x
x
FFE4H
Interrupt control register (INTCM20)
CMIC20
R!W
x
x
43H
FFE5H
Interrupt control register (INTP2)
PIC2
R!W
x
x
43H
FFE6H
Interrupt control register (INTP3)
PIC3
R!W
x
x
43H
R!W
OVIC
R!W
Interrupt control register (INTPO)
PICO
R!W
Interrupt control register (INTP1)
PICI
R!W
Notes:
(1) IlPD78352A/P352 only.
(2) Used only when a word is accessed by an instruction with the
sfrp operand.
x
43H
x
43H
x
43H
(3) These are protected registers, which can be written by a special
instruction only.
Input/Output Ports
The J.lPD78350 has four I/O ports providing a total of 30
I/O lines. The J.lPD78352A/P352 have an additional three
I/O ports for a total of 50 I/O lines.
Ports PO, P1, and P3 are 8-bit input/output ports and P2
is a 6-bit input port. All the bits in PO, P1, .and P3 can be
individually selected for either input or output using
port mode registers PMO, PM1, and PM3. Bits P30 and
P31 can also be programmed for use as PWM outputs
PWMO and PWM1 by using port 3 mode control register
PMC3.
Port P2functions only in the control mode as input pins
for the NMI Signal, the INTPO to INTP3 interrupt Signals,
and the external count clock for timer 1 (TI). However,
any masked interrupt automatically becomes an input
12
line and the state of all the pins can be read by the
program using a read instruction to port 2. Each pin of
P2 can be programmed for rising, falling, or both rising
and falling edge detection.
The output level of the PO, P1, and P31/0 pins can be
tested to determine whether they agree with the contents of the output latch. When the low-order bit of port
read control register PRDC is set to 1, the output level
of the I/O pins can be read with the port still in the
output mode. These data values can be compared with
the data known to be in the output latch to determine if
the port is functioning correctly. Figure 4 shows the
structure of each port pin,
NEe
JlPD78352 Family
Figure 4. I/O Circuits
Type 1. WAIT. MOOED, MODE1
Type 4..
Port PI. RD. WR. ASTB
With bo1h P-ch and N-dl off, 1ha output IS high Impedance.
Type2. Port P2. RESET
Type S.
Porte po. P1. P3, P4, Pa; ADcrAD7\ AltA 15
Data
IN
---[90o------,~~
Output Disable
Schmnt trigger Input with hysteresIS characteristics.
InputEneble
Type 3. CLKOUT
Tjpe4 .
~r-o INIOUT
0-0
~
Type14.. WDTO
OUT
83CL.a1478
13
NEe
IlPD78352 Family
The three additional input/output ports in the
IlPD78352A/P352 are ports P4, P5, and P9. These ports
are available if external memory or memory-mapped
external circuitry is not being used. Port 4 is shared
with the low-order address/data bus (ADo to AD7) and is
byte-selectable for input or output. Port 5 is shared with
the high-order address bus (As to A15)' Depending on
the amount of external memory used, either 8, 6, 4, or
obits are available for bit-selectable I/O. Port 9 is a 4-bit,
bit-selectable I/O port. Two of its pins are shared with
the read and write strobes.
Timers
Figure 5. Timers Block Diagram
INTPO~
I----~
Capture
Interrupt
INTPO
INTOV
INTP1~
Capture
I----~ Interrupt
INTP1
The IlPD78352 family has three 16-bit timers. Two of
them count only the internal system clock; the third
counts either the internal system clock or external
events. Refer to the block diagram, figure 5.
Timer 0 is a16~bit, free-running counter that counts the
internal system clock (fcu
ASlB
~I
K--twSTH-----
WAIT
24
~,-
b
Address 0-7
\
/
HlghZ
' '"Y
tDAA-
~tDSTR~ +-tDRID-1
E
I
RD
-tFAA
D--<
Read Data
-
tWRL
~-tHRWRY~
tSRWRY
\
/
tHAWT
83CL-9150B (ItY93)
NEe
pPD78352 Family
Timing Waveforms (cont)
Write Operation
Clock
X
Address (High Ordal)
K
Address (Low Ordal)
Undefined
Wrtte Data
).
I+--ISAST- ~IHSTA~
ASlB
I
I-IDWOD-~ISODW"
--.l
!-ol---IWSTH- I+IDSTW~
~,oE
,
/
I
.-
>_IHRWRYISRWRY
1\
oE
r'-~
Address 0-7
!--IDWST-
IWWL
WR
K
I
II
!
ISAWT
IHAWT
B3CL-9151B (1!1'93)
25
NEe
pPD78352 Family
Timing Waveforms (cant)
PROM PROGRAMMING
Interrupt Input
The PROM in the JlPD78P352 is one-time programmable
(OTP) or ultraviolet erasable (UV EPROM). The 32,758 X
8-bit PROM has the programming characteristics of an
NEC JlPD27C1001A, including both page and byte programming modes. The MODEONpp, MODE1, P2 l , and
RESET pins are used to place the JlPD78P352 into the
PROM programmming mode. Table 3 shows the functions of the JlPD78P352 pins in normal operating mode
and PROM programming mode.
NMI
INTPn
Table 3. Pin Functions During PROM
Programming
n=0103
83CL.fJ162A
Normal Operating
Mode
Function
Reset Input
8SMLo6991A
Tllnput
n
p50. P20•
Programming Mode
Address input
POo - P0 7,
P51- P57
Data input
P40 - P47
00- 0 7
Program pulse
P12
PGM
Ao -A 16
Chip enable
Pl1
CE
Output enable
Plo
OE
Program voltage
MODEO/Vpp
MODEO/Vpp
Mode voltage
MODEl. P21.
RESET
MODEl. P21.
RESET
PROM Programming Mode
When + 6.5 V is applied to the VDD pin and + 12.5 V to
the MODEONpp pin, the JlPD78P352 enters the PROM
programming mode. Operation in this mode is determined by the setting of CE, OE, and PGM pins as
indicated in table 4.
Table 4. Operation Modes For Programming
MODE1
P21
RESET
CE
OE
PGM
MODEONpp
Voo
Page data latch
L
L
L
H
L
H
+12.5 V
+6.5 V
Data input
Page program
L
L
L
H
H
L
+12.5V
+6.5 V
High impedance
Byte program
L
L
L
L
H
L
+12.5V
+6.5 V
Data input
Program verify
L
L
L
L
L
H
+12.5 V
+6.5 V
Data output
Program inhibit
L
L
L
X
X
L
H
L
H
+12.5 V
+6.5 V
High impedance
Read
L
L
L
L
L
H
+5.0V
+5.0 V
Data output
Ouput disable
L
L
L
L
H
X
+5.0V
+5.0V
High impedance
Standby
L
L
L
H
X
X
+5.0V
+5.0V
High impedance
Mode
X can be either H or L.
26
00 - 07
NEe
pPD78352 Family
Figure 10. Pin Functions in pPD78P352 PROM Programming Mode
z
~~~&1;;~~i~~s
~ ~ ~
10
; g
m~
~
m~
~ ~ ~ ~ ~ ~
~
47
2
MODEl
3
~
VDD
4
L
5
45
44
MODEOIVpp
6
43
OPEN
7
G
8
vss
9
RESET
A9
~PD78P352G-22
41
A7
40
10
39
As
As
~PD78P352KK
11
38
A4
12
37
A3
13
38
Voo
14
35
A2
15
34
Al
18
33
Ao
~
!:l
y
~
L
G
OPEN
42
~PD78P352GC·3BE
J
I0W I0W I=-~ " - - - y
---l
~
Connect these pins separately to V SS through resistors.
Connect this pin to Vss.
Do not connect these pins.
PROM Byte Programming Procedure
(8) Increment address.
Data can be written to the PROM one byte at a time by
the following procedure.
(9) Repeat steps 4-8 until last address is programmed.
(1) Set the pins not used for programming as indicated
in figure 10. Set MODEONpp and Voo pins to +5 V
and MODE1, P2l, and RESET pins to 0 V. The CE,
OE, and PGM pins should be high.
(2) Supply + 6.5 V to Voo pin and + 12.5 V to MODEO/
Vpp pin. Set CE pin low and OE pin high.
(3) Provide initial address to pins
Ao . AlB'
PROM Page Programming Procedure
Data can be written to the PROM four bytes at a time
(page programming) by the following procedure.
(1) Set the pins not used for programming as indicated
in figure 10. Set MODEONpp and Voo pins to +~
and MODE1, P2l, and RESET pins to 0 V. The CE,
OE, and PGM pins should be high.
(4) Provide write data.
(2) Supply + 6.5 V to Voo pin and + 12.5 V to MODEO/
Vpp pin. Set CE pin low.
(5) Input a 0.1·ms program pulse (active low) to PGM
pin.
(3) Provide initial page address to pins Ao - AlB.
(6) Use verify mode (pulse OE low) to test data If data
has been written, proceed to step 8; if not, repeat
steps 4-6: If data cannot be written in 10 attempts,
go to step 7.
(7) Classify PROM as defective and cease write operation.
(4) Provide first byte of data and latch it into PROM by
pulsing OE low. Continue incrementing address
and latching in data until four bytes have been
loaded.
(5) Input a 0.1-ms program pulse (active low) to PGM
pin. Data bus Do - 07 is in a high-impedance state.
27
NEe
pPD78352 Family
(6) Use verify mode (pulse OE low four times) to test
four bytes of data. If all four bytes of data have been
written, proceed to step 8; if not, repeat steps 4-6.
If data cannot be written in 10 attempts, go to step
7.
(3) Input address of data to be read to pins Ao - A16.
(7) Classify PROM as defective and cease write operation.
Program Erasure
(8) Increment address.
(9) Repeat steps 4-8 until last address is programmed.
PROM Read Procedure
The contents of the PROM can be read out to the
external data bus (Do - 0 7) by the following procedure.
(1) Set the pins not used for programming as indicated
in figure 10. Set MODEONpp and VDD pins to +5 V
and MODE1, P21, and RESET pins to 0 V. The CE,
OE, and PGM pins should be high.
(2) Supply +5 V to VDD pin and MODEONpp pin.
(4) Put an active-low pulse on CE and OE pins.
(5) Data is output to pins Do - 07.
The UV EPROM can be erased by exposing the window
to light having a wavelength shorter than 400 nm,
including ultraviolet, direct sunlight, and fluoresecent
light. To prevent unintentional erasure, mask the window.
Typically, data is erased by 254-nm ultraviolet rays. A
minimum lighting level of 15 Ws/cm 2 (ultraviolet ray
intensity x exposure time) is required to completely
erase the written data. Erasure by an ultraviolet lamp
rated at 12,000 I1W/cm2 takes 15 to 20 minutes. Remove
any filter on the lamp and place the device within 2.5 cm
of the lamp tubes.
DC Programming Characteristics
= 25'C ±5'C; Vss = 0 v
TA
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIHl
2.2
VOO
V
VIH2
0.8 VOO
VOO
V
(Note 2)
Voop power supply voltage
VOOP
6.25
6.75
V
Memory program mode
4.5
5.0
5.5
V
Memory read mode
Vpp power supply voltage
Vpp
12.2
12.5
12.8
V
Memory program mode
V
Memory read mode
Typ
6.5
Vpp = Voop
Voop power supply current
Vpp power supply current
loOp
Ipp
Notes:
(1) All except pins in Note 2.
(2) Pins RESET, Xl, X2, P2n, INTPn, NMI, and TI.
28
Condition
(Note 1)
30
mA
100
mA
Memory program mode
Memory read mode
50
mA
Memory program mode
100
f1A
Memory read mode
NEe
,.,PD78352 Family
AC Programming Characteristics
= 25°C ±5°C; ¥oo = 6.5 ±0.25 ¥; Vpp = 12.5 ±0.3 V
TA
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
Byte Programming Mode
Address setup time to PGM l
tAS
2
Jis
CE setup time to PGM l
tCES
2
Jis
Input data setup time to PGM l
tos
2
JiS
tAH
2
Jis
Address hold time after OE
t
Input data hold time after PGM I
tOH
2
tOF
0
Vpp setup time before PGM l
tvps
2
Jis
¥OO setup time before PGM l
tvos
2
Jis
Program pulse width
tpw
0.095
tOES
2
Output data hold time after OE I
Data to OE • delay time
OE • to data output time
Jis
130
0.1
0.105
ns
ms
ps
150
tOE
ns
Page Programming Mode
Address setup time to OE •
tAS
2
ps
CE setup time to OE •
tCES
2
ps
Input data setup time to OE •
tos
2
ps
Address hold time from OE I
tAH
2
Jis
tAHL
2
Jis
Input data hold time after OE I
tAHV
0
ps
tOH
2
ps
Output data hold time after OE I
tOF
0
Vpp setup time to OE •
tvps
2
ps
VOO setup time to OE
tvos
2
ps
130
..
.,
ns
I
!
j
Program pulse width
tpw
0.095
Address to OE • delay time
tOES
2
OE l to data output time
tOE
OE pulse width during data latch
tLW
Data to PGM
tpGMS
2
Jis
tCEH
2
Jis
tOEH
2
Jis
j
delay time
CE hold time from PGM
t
CE hold time from OE I
0.1
0.105
ms
ps
150
ns
ps
Read Mode
Address to data output time
tACC
200
ns
CE I to data output time
tCE
200
ns
OE I to data output time
tOE
75
ns
Data hold time from OE t
tOF
0
60
ns
Data hold time from address
tOH
0
ns
= OE = VIL
= VIL
CE = V1L
CE = VIL
CE = OE = VIL
CE
OE
29
NEe
pPD78352 Family
PROM Timing Diagrams
Byte Programming Mode
t
Program
).
-tAS--j
I
Data Input
_tos-1
Vpp
Vpp
Voo
VOOP
VOO
VOO
{-~
rtOH.
I
~I
Program Ve~fy
K
tDFrOalaOutput
~tAH~
t-1
Notes:
[1] VOO must be appned befora Vpp and removed alter V pp.
[2] Vpp must not be graaterthan +13.5 V, including overshoot.
[3] Removing and relnsarUng the device while a voltage of +12.5 V
Is applied to pin Vpp may affect device reliabUIIy.
83CUI1668
30
NEe
IIPD78352 Family
PROM Timing Diagrams (cant)
Page Programming Mode; Page Data Latch ""* Page Program
~-------- Page Data Latch --------~»I- Page program-,
VPP
VPP
Voo
VOOP
Voo
Voo
~t
tvPs
~
tvos
-1
....
-I
"--..-tCEH
!
~tpw
I
'---'
~
I--tLW-+
~
Not..:
[1] VOO must be applied before Vpp and removed after V PI"
[2] Vpp must not be greater than +13.5 V. Including overshoot.
[3] Removing and relnserUng the device WhIle a voltage 01 +12.5 V
19 applied to pin Vpp may affect device reliability.
83Cl-9166B
31
NEe
pPD78352 Family
PROM Timing Diagrams (cont)
Page Programming Mode; Page Program -+ Program Verify
I_page program--Ii""...E-------------programverlfy------------)o~'
,---
-,
1r-
I I
tCEH
~lpw~
II
It
I
D
tOES
~
Notes:
[1] Veo must be applied before Vpp and removed after V PI'[2] Vpp must not be greater than +13.5 V, Including overshoot.
(3) Removing and relnserUng the device while a voltage 01+12.5 V
Is appBed to pin V pp may affect device reliability.
83CL-9167B
32
NEe
pPD78352 Family
PROM Timing Diagrams (cont)
Read Mode
)
EffecUve Address
l
L,~
OE
High Impedance
'~I
~toE-
~.tOF~
[Note 1]
. .tOH"+
J // / /
\
Data Output
\\
High Impedance
·f f
Note:
[1] 10F Is speclned from OE or CE, whichever goes high flrst.
B3Ct.......
..
I
33
NEe
IIPD78352 Family
INSTRUCTION SET
Instruction Set Symbols (cont)
The instruction set of the pPD78350/P352 is upward
compatible with the pPD78322 and pPD78312A fami lies.
Two instructions have been added to facilitate digital
signal processing. The convolution instruction, MACW,
calculates the sum of the products of un" pai rs of terms
stored in Main RAM. The value of un" is limited only by
the amount of Main RAM available. The MOVTBL instruction displaces a data table by one 16-bit word to
make room for a new data word.
Symbol
Definition
mem
Register indirect: [DE], [HL], [DE+], [HL+], [DE-] ,
[HL-] , [VP], [UP]
The instruction set features both 8- and 16-bit data
transfer, arithmetic, and logic instructions and singlebit manipulation instructions. String manipulation instructions are also included. Branch instructions exist
to test individual bits in the program status word, the
16-bit accumulator, the special function registers, and
the saddr portion of on-chip RAM. Instructions range in
length from 1 to 6 bytes depending on the instruction
and addressing mode.
Flag Column Indicators
Base Index Mode: [DE+ A], [HL+ A], [DE+ B],
[HL+ B], [VP+ DE], [VP+ HL]
Base Mode: [DE+ byte], [HL+ byte], [VP+ byte],
[UP+ byte], [SP+ byte]
Index Mode: word [A], word [B], word [DE], word
[HL]
saddr
FE20-FF1 FH: Immediate byte addresses one byte
in RAM, or label
saddrp
FE20-FF1 FH: Immediate byte (bit 0= 0) addresses
one word in RAM, or label
word
16 bits of immediate data, or label
byte
8 bits of immediate data, or label
jdisp8
8-bit two's complement displacement (immediate
data, displacement value -128 to +127)
bit
3 bits of immediate data (bit position in byte), or
label
n
3 bits of immediate data
!addr16
16-bit absolute address specified by an immediate
address or label
Symbol
Action
(blank)
No change
$addr16
Relative branch address or label
°
Set to
addr16
16-bit address
Set to 1
!addr11
11-bit immediate address or label
X
Set or cleared according to result
addr11
0800H-OFFFH: 0800H + (11-bit immediate
address), or label
addr5
0040H-007EH: 0040H + 2 X (5-bit immediate
address), or label
A
A register (8-bit accumulator)
X
X register·
B
B register
°
P
P/V indicates parity of result
V
P/V indicates arithmetic overflow
R
Restored from saved PSW
Instruction Set Symbols
Symbol
Definition
RO, R1, R2, R3, R4, AS, R6, R7, R8, RS, R10, R11,
R12, R13, R14, R15
r1
r2
rp
rp1
RO, R1, R2,R3, R4,AS,R6,R7
C,B
RPO,RP1,RP2, RP3,RP4,RP5,RP6,RP7*
RPO, RP1,RP2,RP3,RP4,RP5,RP6,RP7*
rp2
DE, HL, VP, UP
sfr
Special function register, 8 bits
sfrp
post
34
Special function register, 16 bits
RPO, RP1, RP2, RP3, RP4, RP5/PSW. RP6, RP7. Bits
set to 1 indicate register pairs to be pushed/
popped to/from stack; RP5 pushed/popped by
PUSH/POP, SP is stack pointer; PSW pushed/
popped by PUSHU/POPU, RP5 is stack pointer.
C
C register
D
D register
E
E register
H
H register
L
L register
RO-R15
Register
AX
Register pair AX (16-bit accumulator)
°to register 15
BC
Register pair BC
DE
Register pair DE
HL
Register pair HL
NEe
pPD78352 Family
Instruction Set Symbols (cont)
Symbol
Definition
RPO-RP7
Register pair 0 to register pair 7
PC
Program counter
SP
Stack pointer
UP
User stack pointer (RPS)
PSW
Program status word
PSWH
High-order 8 bits of PSW
PSWL
Low-order 8 bits of PSW
CY
Carry flag
AC
Auxiliary carry flag
Z
Zero flag
P/V
Parity/overflow flag
S
Sign flag
TPF
Table position flag
RBS
Register bank select flag
RSS
Regi ster set select flag
IE
Interrupt enable flag
STBC
Standby control register
WDM
Watchdog timer mode register
( )
Contents of the location whose address is within
parentheses; (+) and (-) indicate that the address
is incremented after or decremented after it is
used
(0)
Contents of the memory location defined by the
quantity within the sets of parentheses
xxH
Hexadecimal quantity
-I
I
High-order 8 bits and low-order 8 bits of X
/\
v
Logical product (AND)
Logical sum (OR)
Exclusive logical sum (exclusive OR)
Inverted data
• rp and rpl describe the same registers but generate different
machine code.
35
NEe
IIPD78352 Family
Instruction Set
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
.AC
PN
CY
X
X
X
X
X
X
X
X
X
X
8-BIt Data Transfer
MOV
XCH
r1, #byte
r1 - byte
saddr, #byte
(saddr) -
sfr, #byte (Note 1)
sfr - byte
3
r,r1
r-r1
2
A,r1
A-r1
A, saddr
A-
(saddr)
2
saddr, A
(saddr) - A
2
saddr, saddr
(saddr) -
A, sfr
A-sfr
2
2.
2
byte
(saddr)
sfr, A
sfr-A
A, mem (Note 2)
A- (mem)
A,mem
A- (mem)
mem, A (Note 2)
(mem) - A
3
3
2-4
2-4
mem,A
(mem) - A
A, [saddrp]
A-
«saddrp»
2
[saddrp], A
«saddrp» - A
2
A,laddr16
A-
4
!addr16, A
(addr16) - A
4
PSWL, #byte
PSWL- byte
3
PSWH, #byte
PSWH -
3
PSWL,A
PSWL- A
2
PSWH,A
PSWH- A
2
A, PSWL
A- PSWL
2
A, PSWH
A-PSWH
2
A,r1
A- r1
(addr16)
byte
r,r1
r-
r1
2
A,mem
A- (mem)
2-4
A, saddr
A-
A, sfr
A-sfr
A, [saddrp]
A-
saddr, saddr
(saddr) -
2
(saddr)
3
«saddrp»
(saddr)
2
3
ttS-BIt Data Transfer
MOVW
36
rp1, #Word
rp1 -word
3
saddrp, #Word
(saddrp)
4
sfrp, #Word
sfrp -word
4
rp, rp1
rp- rp1
2
AX, saddrp
AX +- (saddrp)
2
saddrp, AX
(saddrp) - AX
2
saddrp, saddrp
(saddrp) -
3
+-
word
(saddrp)
NEe
pPD78352 Family
Instruction Set (cant)
Flags
Mnemonic
Operand
Operation
Bytes
AX, sfrp
AX - sfrp
2
rp1, !addr16
rp1 -
!addr16, rp1
(addr16)
AX,mem
AX
5
z
AC
PN
CY
16-8it Data Transfer (cont)
MOVW
(con~
XCHW
--sf-rp-'-AX------------s-fr-p----AX~--------------------------~---2---------------------------
(addr16)
+-
rp1
4
4
(mem)
2-4
mem, AX
(mem) - AX
2-4
AX, saddrp
AX -
+-
(saddrp)
2
saddrp, saddrp
(saddrp) - (saddrp)
3
rp, rp1
rp- rp1
AX,mem
AX
AX, sfrp
++
2
(mem)
2-4
8-8it Arithmetic
ADD
AD DC
SUB
__
A_,_#_by~t_e__________A~,_C_Y__
-_A
__+__
by~t_e__________________________
2_____X
_____
X____X
______V_____X
__
saddr, #byte
(saddr), CY - (saddr) + byte
3
X
X
X
V
X
sfr, #byte
sfr, CY - sfr + byte
4
X
X
X
V
X
r, r1
r,CY-r+r1
2
X
X
X
V
X
A, saddr
A,CY-A+(saddr)
2
X
X
X
V
X
A, sfr
A, CY -
3
X
X
X
V
X
saddr, saddr
(saddr), CY - (saddr) + (saddr)
3
X
X
X
V
X
A,mem
A,CY- A+ (mem)
2-4
X
X
X
V
X
mem,A
(mem), CY - (mem) + A
2-4
X
X
X
V
X
A, #byte
A, CY - A + byte + CY
2
X
X
X
V
X
saddr, #byte
(saddr), CY +- (saddr) + byte + CY
3
X
X
X
V
X
sfr, #byte
sfr, CY - sfr + byte + CY
4
X
X
X
V
X
r, r1
r,CY-r+r1+CY
2
X
X
X
V
X
A, saddr
A, CY - A + (saddr) + CY
2
X
X
X
V
X
3
X
X
X
V
X
3
X
X
X
V
X
X
X
V
X
A + sfr
A, sfr
A, CY
sad dr, saddr
(saddr), CY - (saddr) + (saddr) + CY
A,mem
A, CY - A + (mem) + CY
2-4
X
<-
A + sfr + CY
mem, A
(mem), CY - (mem) + A + CY
2-4
X
X
X
V
X
A, #byte
A,CY-A-byte
2
X
X
X
V
X
saddr, #byte
(saddr), CY ..... (saddr) - byte
3
X
X
X
V
X
sfr, #byte
sfr, CY .... sfr - byte
4
X
X
X
V
X
r, r1
r,CY-r-r1
2
X
X
X
V
X
A, saddr
A,CY<-A-(saddr)
2
X
X
X
V
X
A, sfr
A, CY - A - sfr
3
X
X
X
V
X
saddr, saddr
(saddr), CY ..... (saddr) - (saddr)
3
X
X
X
V
X
A,mem
A, CY
2-4
X
X
X
V
X
mem,A
(mem), CY <- (mem) - A
2-4
X
X
X
V
X
+-
A - (mem)
37
NEe
IIPD78352 Family
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
AC
PN
CY
8-Bit Arithmetic (cont)
SUBC
A, #byte
A, CY .... A - byte - CY
2
X
X
X
V
X
sad dr, #byte
(saddr), CY - (saddr) - byte - CY
3
X
X
X
V
X
sfr, #byte
sfr, CY - sfr - byte - CY
4
X
X
X
V
X
r,rl
r,CY .... r-rl-CY
2
X
X
X
V
X
A, saddr
A, CY - A - (saddr) - CY
2
X
X
X
V
X
A, sfr
A,CY-A-sfr-CY
3
X
X
X
V
X
sad dr, saddr
(saddr), CY <- (saddr) - (saddr) - CY
3
X
X
X
V
X
A,mem
A, CY +- A - (mem) - CY
2·4
X
X
X
V
X
mem, A
(mem), CY <- (mem) - A - CY
2·4
X
X
X
V
X
A, #byte
A<-AA byte
2
X
X
P
saddr, #byte
(saddr) <- (saddr) A byte
3
X
X
P
sfr, #byte
sfr - sfr A byte
4
X
X
P
r,rl
r<- rA rl
2
X
X
P
A, saddr
A <- A A (saddr)
2
X
X
P
A, sfr
A<-AA sfr
3
X
X
P
sad dr, saddr
(saddr)<- (saddr) A (saddr)
3
X
X
P
A,mem
A_AA (mem)
2·4
X
X
P
8-BitLogic
AND
OR
XOR
38
mem, A
(mem) .... (mem) A A
2·4
X
X
P
A, #byte
A <-A V byte
2
X
X
P
saddr, #byte
(saddr) <- (saddr) V byte
3
X
X
P
sfr, #byte
sfr <- sfr V byte
4
X
X
P
r,rl
r - rV rl
2
X
X
P
A, saddr
A <- A V (saddr)
2
X
X
P
A, sfr
A <- A V sfr
3
X
X
P
saddr, saddr
(saddr)e- (saddr) V (saddr)
3
X
X
P
A,mem
Ae-AV (mem)
2·4
X
X
P
mem, A
(mem) e- (mem) V A
2·4
X
X
P
A, #byte
Ae-AVbyte
2
X
X
P
saddr, #byte
(saddr) e- (saddr) V byte
3
X
X
P
sfr, #byte
sfr - sfr V byte
4
X
X
P
r,rl
re-rVrl
2
X
X
P
A, saddr
A e- A V (saddr)
2
X
X
P
A, sfr
A-AVslr
3
X
X
P
sad dr, saddr
(saddr)<- (saddr) V (saddr)
3
X
X
P
A,mem
A-AV(mem)
2-4
X
X
P
mem, A
(mem) e- (mem) V A
2·4
X
X
P
NEe
JlPD78352 Famil y
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
5
z
AC
PN
CY
x
x
x
x
x
x
x
v
v
x
x
8-Bit Logic (cont)
CMP
A, #byte
A- byte
2
x
x
saddr, #byte
(saddr) - byte
3
x
5fr, #byte
sfr- byte
4
r,rl
r-r1
2
saddr, saddr
(saddr) - (saddr)
3
x
x
x
x
x
x
A,mem
A- (mem)
2-4
x
mem,A
(mem)- A
2-4
x
x
x
x
x
x
x
A, saddr
A - (saddr)
2
A, sfr
A-sfr
3
x
v
x
x
v
v
v
v
v
v
x
x
x
x
x
x
x
16-Bit Arithmetic
ADDW
SUBW
+
AX, #Word
AX, Cy .... AX
3
X
X
X
V
X
saddrp, #Word
(saddrp), CY -- (saddrp) + word
word
4
X
X
X
V
X
sfrp, #Word
sfrp, CY -- sfrp
+
word
5
X
X
X
V
X
rp, rp1
rp, CY -- rp
2
X
X
X
V
X
AX, saddrp
AX,
2
X
X
X
V
X
AX, sfrp
AX,
+ rp1
CY .... AX + (saddrp)
CY <-- AX + sfrp
3
X
X
X
V
X
saddrp, saddrp
(saddrp), CY <-- (saddrp)
3
X
X
X
V
X
AX, #Word
AX, CY <-- AX - word
3
X
X
X
V
X
+
(saddrp)
I
_sa_d_d..:rp...:.,_#W_o_rd_ _ _...:.(s_a_d_dr-'-p:.;.),_C_Y_<-----.:(_sa_d_d..:rp-'-}_-_w_o_rd
__________
4 ___X_ _X
___X_ _ _
V___X_ . "
CMPW
sfrp, #Word
sfrp, CY <-- sfrp - word
5
X
X
X
V
X
rp, rp1
rp, CY <-- rp - rp1
2
X
X
X
V
X
AX, saddrp
AX, CY <-- AX - (saddrp)
2
X
X
X
V
X
AX, sfrp
AX, CY <-- AX - sfrp
3
X
X
X
V
X
saddrp, saddrp
(saddrp), CY +- (saddrp) - (saddrp)
3
X
X
X
V
X
AX, #Word
AX - word
3
X
X
X
V
X
saddrp, #word
(saddrp) - word
4
X
X
X
V
X
sfrp, #Word
5frp - word
5
X
X
X
V
X
rp, rp1
rp - rpl
2
X
X
X
V
X
AX, saddrp
AX - (saddrp)
2
X
X
X
V
X
AX, sfrp
AX - sfrp
3
X
X
X
V
X
saddrp, saddrp
(saddrp) - (saddrp)
3
X
X
X
V
X
Multiplication/Division
MULU
r1
AX--AXxrl
2
DIVUW
rl
AX (quotient), r1 (remainder)<-- AX + r1
2
MULUW
rp1
AX (high-order 16 bits), rpl (low-order 16 bits) <-AX x rpl
2
DIVUX
rp1
AXDE (quotient), rpl (remainder) --AXDE + rp1
2
MULW
(Note 3)
rp1
AX (high-order 16 bits), rp1 (low-order 16
bits) -- AX x rpl
2
39
NEe
pPD78352 Family
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
AC
PN
CY
X
X
X
V
X
V
Sum-of-Products
MACW
n
AXDE +- (B) x (C) + AXDE, B +- B + 2, C +- C +
2, n +- n-l. End if n = 0 or P/V = 1
3
!addr 16, n
(Note 4)
(addr16 + 2) .... (addr16), n +- n-1, addr16 .... addr16
- 2. End if n = 0
4
Table Shift
MOVTBLW
Incrememt/Decrement
INC
DEC
INCW
r1
r1
saddr
(saddr) +- (saddr) + 1
r1
r1 +- r1 -1
<-
r1 + 1
saddr
(saddr) +- (saddr) - 1
rp2
rp2 .... rp2+1
2
2
X
X
X
X
X
X
V
X
X
X
V
X
X
X
V
saddrp
(saddrp) .... (saddrp) + 1
rp2
rp2 .... rp2-1
saddrp
(saddrp)
ROR
r1, n
(CY, r17+- r10, r1m-1 +- r1m) x n times
2
P
ROL
r1, n
(CY, r10 +- r17' r1m+ 1 <- r1m) x n times
2
P
X
RORC
r1, n
(CY .... r10, r17 +- CY, rl m-1
2
P
X
P
X
DECW
<-
3
(saddrp) - 1
3
Shift/Rotate
<-
r1m) x n times
X
ROLC
rl, n
(CY .... r17' r10 .... CY, r1m+ 1 .... r1m) x n times
2
SHR
r1, n
(CY+- r10, r17 .... 0, r1 m_1 .... r1m) x n times
2
X
X
0
P
X
SHL
r1, n
(CY+- r17' r10 .... 0, r1m+ 1 +- r1ml x n times
2
X
X
0
P
X
SHRW
rp1, n
(CY .... rp10, rp115 .... 0, rp1 m-1 +- rp1m) x n times
2
X
X
0
P
X
SHLW
rp1, n
(CY+- rp1 15, rp10 +- 0, rp1 m+ 1 .... rp1 m) x n times
2
X
X
0
P
X
ROR4
[rpl)
Aa-o +- (rp1)a-o, (rp1)7_4 +- Aa-o,
(rpl )a-o .... (rp1 )7-4
2
ROL4
[rp1)
Aa-o .... (rp1)7_4, (rp1)a-o +- Aa-o,
(rpl)7_4 .... (rp1)a-o
2
ADJBA
Decimal adjust accumulator after add
2
X
X
X
P
X
ADJBS
Decimal adjust accumulator after subtract
2
X
X
X
p
X
BCD Adjustment
Data Expansion
CVTBW
X +- A, As-o .... A7
Bit Manipulation
MOV1
40
CY, saddr. bit
CY +- (saddr.bit)
3
X
CY, sfr.bit
CY <- sfr. bi t
3
X
CY, A.blt
CY +- A.bit
2
X
CY, X.bit
CY .... X.bit
2
X
CY, PSWH.bit
CY +- PSWH.bit
2
X
NEe
JlPD78352 Family
Instruction Set (cant)
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
AC
PN
CY
Bit Manipulation (cont)
MOV1 (cont)
AND1
ORl
XORl
CY, PSW L. bi t
CY +- PSWL.bit
2
saddr.bit, CY
(saddr.bit) +- CY
3
3
slr.bit, CY
sIr. bit +- CY
A.bit, CY
A.bit+- CY
2
X.bit, CY
X.bit+-CY
2
X
PSWH.bit, CY
PSWH.blt +- CY
2
PSWL.bit, CY
PSWL.bit +- CY
2
CY, saddr.bit
CY +- CY f\ (saddr.bit)
3
X
CY, Isaddr. bit
CY +- CY f\ (saddr.bit)
3
X
CY, slr.bit
CY +- CY f\ slr.bit
3
X
CY,/slr.bit
CY +- CY f\ sIr. bit
3
X
CY, A.bit
CY +- CY f\ A.bit
2
X
CY, IA.bit
CY <- CY f\ A.bit
2
X
CY, X.bit
CY +- CY f\ X.blt
2
X
CY, /X.bit
CY +- CY f\ X.bit
2
X
CY, PSWH.bit
CY +- CY f\ PSWH.bit
2
X
CY, IPSWH.bit
CY +- CY f\ PSWH.bit
2
X
CY, PSWL.bit
CY +- CY f\ PSWL.bit
2
X
CY, IPSWL.bit
CY +- CY f\ PSWLbit
2
X
CY, saddr.bit
CY +- CY V (saddr.bit)
3
X
CY, Isaddr.bit
CY +- CY V (saddr.bit)
3
X
CY, sfr.bit
CY +- CY V slr.bit
3
X
X
X
X
X
CY, Islr.bit
CY +- CY V sfr.bit
3
X
CY,A.bit
CY +- CY V A.bit
2
X
CY, lA.bit
CY +- CY V A.bit
2
X
CY, X.bit
CY +- CY V X.bit
2
X
CY, /X.bit
CY +- CY V X.bit
2
X
CY, PSWH.bit
CY +- CY V PSWH.bit
2
X
CY, IPSWH.bit
CY +- CY V PSWH.bit
2
X
CY, PSWL.bit
CY +- CY V PSWLbit
2
X
CY, IPSWL.bit
CY +- CY V PSWL.bit
2
X
CY, saddr.bit
CY +- CY V (saddr.bit)
3
X
CY, slr.bit
CY +- CY V slr.bit
3
X
CY, A.bit
CY +- CY V A.bit
2
X
CY, X.bit
CY +- CYVX.blt
2
X
CY, PSWH.bit
CY +- CY V PSWH.bit
2
X
CY, PSWL.blt
CY +- CY V PSWL.bit
2
X
41
-
NEe
JlPD78352 Family
Instruction Set (cant)
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
AC
PN
CY
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit Manipulation (cont)
SET1
CLR1
NOn
saddr.bit
(saddr.bit) ... 1
2
slr.bit
slr.bit .... 1
3
A.bit
A.bit ... 1
2
X.bit
X.bit ... 1
2
PSWH.bit
PSWH.bit-1
2
PSWL.bit
PSWL.blt-1
2
saddr.bit
(saddr.bit) - 0
2
slr.bit
slr.bit .... 0
3
A.blt
A.bit .... O
2
X.bit
X.bit-O
2
PSWH.bit
PSWH.bit-O
2
PSWL.bit
PSWL.bit ... O
2
(saddr.bit) - (saddr.bit)
3
saddr.bit
slr.bit
slr.bit +- slr.bit
3
A.bit
A.bit +- A.bit
2
X.bit
X.bit .... X.bit
2
PSWH.bit
PSWH.bit - PSWH.bit
2
2
PSWL.bit
PSWL.blt- PSWL.bit
SEn
CY
CY .... 1
CLR1
Cy
Cy .... O
0
NOT1
CY
Cy- Cy
X
Subroutine Linkage
laddr16
(SP-1) - (PC + 3)H. (SP - 2) +- (PC
PC ... addr16. SP ... SP - 2
3)l.
3
rp1
(SP-1) +- (PC + 2)H. (SP - 2) - (PC + 2lL.
PCH - rp1H. PCl - rp1l. SP - SP - 2
2
[rp1]
(SP-1) - (PC + 2)H. (SP - 2) - (PC + 2)l.
PCH - (rp1 + 1). PCl - (rp1). SP - SP - 2
2
CALlF
!addr11
(SP-1) - (PC + 2)H. (SP - 2) - (PC + 2lL.
PC1!>-11 - 00001. PC1G-O - addr11. SP - SP - 2
2
CAllT
[addr5]
(SP-:-1) .... (PC + 1)H. (SP - 2) - (PC + 1)l.
PCH +- (TPFx6000H + 2 x addrS + 41 H).
PCl - (TPFx6000H + 2 x addr5 + 40H). SPSP-2
CALL
+
BRK
(SP-1) .... PSWH. (SP - 2) .... PSWl. (SP3) +- (PC + 1)H. (SP - 4) - (PC + 1)l.
PCl - (003EH). PCH - (003FH). SP - SP - 4.
IE-O
RET
PCl - (SP). PCH - (SP
RETB
PCl - (SP). PCH - (SP + 1). PSWl - (SP
PSWH- (SP + 3). SP-SP + 4
+
2).
R
R
R
R
R
RET!
PCl - (SP). PCH - (SP + 1). PSWl - (SP
PSWH - (SP + 3). SP - SP + 4
+
2).
R
R
R
R
R
42
+
1). SP +- SP
+
2
NEe
pPD78352 Family
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
S
Z
AC
PN
CY
R
R
R
R
R
3
X
X
P
3
X
X
P
Bytes
Stack Manipulation
PUSH
sfrp
(SP - 1) ..... sfrH, (SP - 2) <- sfrl, SP <- SP - 2
3
post
{(SP - 1) <- rpPH, (SP - 2) .... rpPl, SP <- SP - 2} x
n (Note 5)
2
PSW
(SP -1) .... PSWH, (SP - 2) ..... PSWL, SP .... SP - 2
PUSHU
post
{(UP - 1) +- rpPH, (UP - 2) ..... rpPl, UP
n (Note 5)
POP
sfrp
sfrl +- (SP), sfrH +- (SP
post
{rpPl <- (SP), rpPH +- (SP
(Note 5)
+
UP - 2} x
+
2
1), SP +- SP
+
1), SP +- SP
+
+-
+
3
2} x n
+
2
PSW
PSWL<- (SP) , PSWH<- (SP
POPU
post
{rpPl <- (UP), rpPH +- (UP
(Note 5)
MOVW
SP, #Word
SP <-word
4
SP, AA
SP <-AA
2
AX,SP
AA
+-
SP
INCW
SP
SP
+-
SP
DECW
SP
SP <-SP-1
+
1), SP+-SP
2
1), UP +- UP
+
2
2} x n
2
2
+
1
2
2
Pin Level Test
V
CHKL
sfr
(Pin level)
CHKLA
sfr
A .... (Pin level)
(internal signal level)
V
(internal signal level)
B,
Unconditional Branch
BR
!addr16
PC
+-
addr16
I
3
2
rp1
PC H +- rp1 H, PCl +- rp1 l
[rp1]
PCH <- (rp1
+
1), PCl .... (rp1)
2
$addr16
PC +- PC
+
2
+
jdisp8
2
=1
=0
jdisp8 if Z = 1
2
Conditional Branch
BC, BL
$addr16
BNC, BNL
$addr16
BZ,BE
$addr16
BNZ,BNE
$addr16
BV, BPE
$addr16
BNV,BPO
$addr16
BN
$addr16
BP
$addr16
BGT
$addr16
BGE
$addr16
BLT
$addr16
BLE
$addr16
BH
$addr16
BNH
$addr16
+
+
PC 00- PC +
PC +- PC +
PC +- PC +
PC +- PC +
PC ... PC +
PC .... PC +
PC 00- PC +
PC 00- PC +
PC +- PC +
PC - PC +
PC .... PC +
PC +- PC +
PC ... PC
PC
+-
PC
+
+
2 +
2+
2 +
2 +
2 +
2 +
3 +
3 +
3+
3 +
3+
3+
2
jdisp8 if CY
2
jdisp8 if CY
2
2
=0
=1
jdisp8 if P/V = 0
jdisp8 if S = 1
jdisp8 If S = 0
jdisp8 if Z
2
jdisp8 if P/V
2
2
2
2
V S)V Z = 0
jdisp8 if P/V V S = 0
jdisp8 if P/V V S = 1
jdisp8 if (P/V
jdisp8 If (P/V
V
S)
VZ=1
3
3
3
3
jdisp8 if Z
V CY = 0
3
jdisp8 if Z
V CY
=1
3
43
NEe
pPD78352 Family
Instruction Set (cant)
Flags
Mnemonic
Operand
Bytes
Operation
S
Z
AC
PN
CY
X
X
X
X
X
X
X
X
X
X
Conditional Branch
BT
saddr.bit, $addrl6
sfr.bit, $addrl6
A.bit, $addrl6
X.bit, $addrl6
PSWH.blt, $addrl6
PSWL.bit, $addrl6
BF
saddr.blt, $addrl6
sfr.bit, $addrl6
A.blt, $addrl6
X.blt, $addrl6
PSWH.bit, $addrl6
PSW L.bit, $addrl6
BTClR
saddr.bit, $addrl6
+
+
PC ... PC +
PC ... PC +
PC ... PC +
PC .... PC +
PC ... PC +
PC ... PC +
PC .... PC +
PC .... PC +
PC ... PC +
PC +- PC +
PC <- PC +
+
+
3+
3+
3+
3+
4+
4+
3+
3+
3+
3+
4+
PC ... PC
3
jdisp8 if (saddr.blt)
PC ... PC
4
jdlsp8 if sfr.bit
=1
3
=1
jdisp8 if A.bit = 1
jdisp8 if X.bit = 1
4
3
3
=1
jdisp8 if PSWL.bit = 1
jdisp8 if (saddr.bit) = 0
jdisp8 if sfr.bit = 0
jdisp8 if A.bit = 0
jdisp8 if X.bit = 0
jdlsp8 if PSWH.bit = 0
jdispB if PSWL.bit = 0
jdisp8 if (saddr.bit) = 1 then
3
jdisp8 if PSWH.bit
3
4
4
3
3
3
3
reset
4
(saddr.bit)
BFSET
sfr. bit, $addrl6
PC ... PC
sfr.bit
+
4
+
jdisp8 if sfr.bit = 1 then reset
4
+
+
+
3
+
+
+
jdlsp8 if A.bit
= 1 then reset A.bit
= 1 then reset X.bit
jdisp8 if PSWH.bit = 1 then reset
3
jdispB if X.bit
3
A.bit, $addrl6
PC ... PC
X. bit, $addrl6
PC ... PC
PSWH.bit, $addrl6
PC +- PC
PSWH.bit
PSWL.bit, $addrl6
PC +- PC + 3
PSWL.bit
+
jdisp8 if PSWL.bit
= 1 then reset
3
saddr.bit, $addrl6
PC ... PC + 4
(saddr.bit)
+
jdispB if (saddr.bit)
= 0 then set
4
sfr.bit, $addrl6
PC .... PC
+
+
PC <- PC +
PC +- PC +
4
4
PC .... PC
3
+
+
+
+
jdisp8 if sfr.bit
A.bit, $addrl6
jdisp8 if A.bit
3
+
jdisp8 if PSWL.bit
X.bit, $addrl6
PSWH.bit, $addrl6
3
3
3
3
= 0 then set sfr.bit
= 0 then set A.bit
jdisp8 if X.bit = 0 then set X.bit
jdisp8 if PSWH.bit = 0 then set
3
3
3
PSWH.bit
DBNZ
PSWL.bit, $addrl6
PC +- PC + 3
PSWL.bit
12, $addrl6
12 - 12 - 1, then PC - PC
saddr, $addrl6
(saddr) +- (saddr) - 1, then PC <- PC
if (saddr) = 0
+
2
+
= 0 then set
=0
2
jdlspB
3
jdispB if 12
+
3
+
3
Context Switching
BRKCS
RBn
RBS2'() +- n, PCH - RS, PCl ... R4, R7 +- PSWH,
R6 .... PSWl, RSS-O, IE-O
2
RETCS
!addrl6
PCH - R5, PC l +- R4. R5 +- addrl6H,
R4 .... addrl6l.
PSWH .... R7, PSWl ... R6
3
R
R
R
R
R
RETCSB
!addrl6
PCH +- RS, PCl +- R4, RS .... addrl6H,
R4 +- addrl6l.
PSWH .... R7, PSWl .... R6
4
R
R
R
R
R
44
NEe
pPD78352 Family
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
AC
PN
CY
X
String Manipulation
MOVM
[OE+],A
(OE+) <- A, C <- C-1 End if C = 0
[OE--], A
(OE-) <- A, C <- C-1 End if C = 0
2
MOVBK
[OE+], [HL+]
(OE+) <- (HL+), C <- C-1 End if C = 0
2
[OE-] , [HL-]
(OE-) <- (HL-) , C <- C-1 End if C = 0
2
XCHM
[OE+],A
(OE+) ... A, C <- C-1 End if C = 0
2
[OE-] , A
(OE-) -A, C<-C-1 End ifC = 0
2
[OE+], [HL+]
(OE+)
2
[OE-], [HL-]
(OE-) ... (HL-), C <- C-1 End if C = 0
2
[OE+],A
(OE+)-A, C<-C-1 End ifC = OorZ = 0
2
X
X
X
V
[OE-], A
(OE-) - A, C <- C-1 End if C = 0 or Z = 0
2
X
X
X
V
X
[OE+], [HL+]
(OE+)-(HL+),C<-C-1 EndifC= OorZ= 0
2
X
X
X
V
X
[OE-] , [HL-]
(OE-) - (HL-), C <- C-1 End if C = 0 or Z = 0
2
X
X
X
V
X
[OE+], A
(OE+)-A,C<-C-1 EndifC= OorZ= 1
2
X
X
X
V
X
[OE-], A
(OE-)-A,C<-C-1 EndifC= OorZ= 1
2
X
X
X
V
X
[OE+], [HL+]
(OE+)-(HL+),C<-C-1 EndifC= OorZ= 1
2
X
X
X
V
X
[OE-], [HL-]
(OE-) - (HL-), C <- C-1 End if C = 0 or Z = 1
2
X
X
X
V
X
[OE+],A
(OE+) - A, C <- C-1 End if C = 0 or CY = 0
2
X
X
X
V
X
[OE-], A
(OE-) - A, C <- C-1 End if C = 0 or CY = 0
2
X
X
X
V
X
[OE+], [HL+]
(OE+) - (HL+), C <- C-1 End if C = 0 or CY = 0
2
X
X
X
V
X
[OE-], [HL-]
(0&-) - (HL-), C <- C-1 End if C = 0 or CY = 0
2
X
X
X
V
X
[OE+],A
(OE+)-A,C<-C-1 EndlfC= OorCY= 1
2
X
X
X
V
X
[OE-],A
(OE-)-A,C<-C-1 EndifC= OorCY= 1
2
X
X
X
V
X
[OE+], [HL+]
(OE+) - (HL+), C <- C-1 End if C = 0 or CY = 1
2
X
X
X
V
X
[OE-], [HL-]
(OE-) - (HL-), C <- C-1 End if C = 0 or CY = 1
2
X
X
X
V
X
XCHBK
CMPME
CMPBKE
CMPMNE
CMPBKNE
CMPMC
CMPBKC
CMPMNC
CMPBKNC
<+
(HL+), C<-C-1 End ifC = 0
2
CPU Control
MOV
STBC, #byte
STBC <- byte (Note 6)
4
WOM, #byte
WOM <- byte (Note 6)
4
SWRS
SEL
RSS <- RSS
RBn
RBS2_0 <- n, RSS
0
2
RBn, ALT
RBS2_0 <- n, RSS <- 1
2
<-
NOP
No operation
EI
IE <- 1 (Enable interrupt)
01
IE <- 0 (Disable interrupt)
45
pPD78352 Family
Instruction Set (cant)
Notes:
(1) A special instruction is used to write to STBC and WDM.
(2) One byte move instruction when [DE], [HL], [DE+], [DE-] ,
[HL+], or [HL-] is specified for memo
(3) 16-blt signed multiply instruction
(4) Addressing range is OFEOOH to OFEFFH.
(5) rpp refers to register pairs specified in post byte. un" is the
number of register pairs specified in post byte.
(6) Trap if data bytes in operation code are not one's complement. If
trap, then:
(SP-1) .... PSWH, (SP-2) ..... PSWL, (SP-3) ..... (PC-4)H,
(SP-4) ..... (PC-4)l, PCl .... (003CH), PCH .... (OO3DH).
SP .... SP-4, IE .... o.
46
NEe
NEe
NEC Electronics Inc.
pPD78356 Family
(pPD78355/356/P356)
16-/8-Bit, K-Series Microcontrollers
With AID Converter and Convolution Capability
Preliminary
September 1993
Description
Features
The JlPD78355, JlPD78356, and JlPD78P356 are
K-Series® microcontroliers. These 16-/8-bit devices
-with a minimum instruction time of 125 ns at 32
MHz-are designed for high-speed, real-time process
control. They feature a 16-bit CPU, a 16-/8-bit external
data bus, eight banks of main registers, an advanced
interrupt handling facility, and a powerful set of
memory-mapped on-Chip peripherals. A 16-bit multiply
and accumulate instruction with or without a saturation word provides hardware convolution capability; a
16-bit subtract and accumulate absolute value instruction provides correlation capability.
o Complete single-chip microcontrolier
-16-bitALU
- 2048 bytes of RAM
- 48K bytes of ROM (uPD78356) or PROM
(uPD78P356)
o Powerful instruction set
-16-bit unsigned and signed multiply
-16-bit unsigned divide
-16-bit multiply and accumulate instruction with
or without saturation word
-16-bit subtraction and accumulate absolute
value instructions
-1-bit and 8-bit logic instructions
- String instructions
On-board memory includes 2048 bytes of RAM and 48K
bytes of mask ROM, UV EPROM, or one-time programmable (OTP) ROM. A ROMless version is also available.
The UV EPROM and OTP ROM versions feature a PROM
error correction function capable of correcting one
1-bit error per four bytes of code. This achieves a
significant improvement in reliability over devices without error correction and is suited for applications that
require high reliability under rigorous conditions.
The advanced interrupt handling facility has four levels
of programmable hardware-priority control and three
methods of servicing interrupt requests, including vectoring, hardware context switching, and macro service. The macro service facility reduces the CPU overhead involved in servicing peripheral interrupts by
transferring data between the memory-mapped special function registers (SFRs) and memory without the
use of time consuming interrupt service routines. In
addition, the macro service faci lity can perform certain
CPU functions, such as event counting and mathoriented data alterations.
The combination of high-speed hardware convolution
capability and context switching, eight register banks,
and the macro service facility makes these devices
ideal for applications in the hard-disk drive and tape
drive markets as well as the automotive, office automation, and industrial control/robotics markets.
K·Series is a registered trademark of NEe Electronics Inc.
50596
o Minimum instruction time: 125 ns at 32 MHz
o 5-byte instruction prefetch queue
o Memory expansion
-8- or 16-bit external data bus
- 64K-byte address space
o Large I/O capacity
- Up to 57 I/O port lines (uPD78355)
- Up to 76 I/O port Ii nes (uPD783561P356)
o Memory-mapped, on-Chip peripherals
(special function registers)
o Real-time pulse unit (RPU)
- Two 16-bit interval timers
- Two 16-bit timer/event counters
- One 10-bit interval timer
- One 16-bit up/down counter
- Ten 16-bit capture/compare registers
- Five external interrupt/capture lines
- Three external event counter inputs
- Three external timer clear inputs
- Ten timer outputs
o Two pulse-width modulated (PWM) output lines
with 8-, 10-, or 12-bit precision
DOne 8-bit real-time output port
o Eight-channel, high-speed 10-bit A/D converter;
conversion time: 2 Jls at 32 MHz
o Two-channel, 8-bit D/A converter
NEe
I'PD78356 Family
Features (cont)
o Three-channel serial communications interface
- Asynchronous seri al interface (UARl)
- Clock synchronous serial interface 0
Full-duplex, three-wire mode
NEC serial bus interface (SBI) mode
- Clock synchronous serial interface 1
Full-duplex three-wire mode
Pin switching function
o Programmable priority interrupt controller (four
levels)
o Three methods of interrupt service
- Vectored interrupts
- Context switching with hardware register bank
switch
- Macro service mode with choice of five different
functions
o Watchdog timer with dedicated output
o STOP and HALT standby functions
o Single 5-volt power supply
Ordering Information
Part Number
Package
ROM
pPD7B355GC-7EA
100-pin plastic QFP
(Dwg Pl00GC-50-7EA)
ROMless
pPD78356GC-xxx-7EA
100-pin plastic QFP
(Dwg Pl00GC-50-7EA)
48K mask
ROM
pPD78P356GC-7EA
100-pin plastic QFP
(Dwg Pl00GC-50-7EA)
48KOTP
ROM
pPD78P356KP-S
120-pin ceramic LCC
with window
(Dwg X120KW-BOA)
48K UV
EPROM
xxx indicates ROM code suffix.
2
NEe
pPD78356 Family
Pin Configurations
100-Pin Plastic QFP
P4atAD2
PilafADa
P44o'AD4
P4sfAD5
P4&,ADa
P471AD-,
P50fADs
P5l /AD9
P5afAD10
P5afADll
P54o'AD12
P5sfAD13
P5efAD 14
P57IAD15
MODEl
MODE2
Vss
VDD
WDTO
ASlB
WAIT
P9o'fiD
P9l1lWR
P9:zIHWR
P93
RESET
P27fT020
P2efTCLR2IT02l
P2sflNTP4
P24fINTP3
P2:i1NTP2
P2af1NTP11TOO5
P2lnNTPOITOO4
P2o'NMI
P37fT010
P3efT1lf1Oll
P3sfTCLRl
P34fSCKOO
P33SIOOISBl
P3afSOOO1SBO
P3l/RxD
P30fTxD
ANOl
ANOO
AVREF3
AVREF2
AVREFl
P77IANrT
P7&,ANI6
P7sfANI5
83fM.11427B
3
pPD78356 Family
NEe
Pin Configurations (cant)
120-Pin Ceramic LeC
POo IRTPo IAOTRGO
POl IRTP1/AOTRGl
P02 IRTP2/ADTRG2
Pea IRTP3/AOTRG3
P04 IRTP4
P05IRTP5
POa IRTP6
P07~
P8oITCLRO
P8llT101TOO3
P41/AOl
P4o/AOO
P17
Pla
NC
P15
P14
P13
P12
Pll
NC
Plo
P107fTCUO
Pl0afTIUO
Pl05/SCKll
Pl041S111
NC
Pl03/S011
P102/SCK10
Pl0l1S110
P100lS010
NC
VOO
Vss
Xl
X2
CLKOUT
3
4
5
a
9
NO
P82/TOOO
P831TOOl
P841TOO2
P8sITCLRUO
NO
Vss
VOO
NC
P86IPWMO
P87IPWMl
NC
AVss
AVOO
P7o/ANIO
P7l/ANI1
P72/AN12
NC
P73/AN13
P74/AN14
61
Vss
VOO
NC
Note:
NC: No connection
83YL·9484B (MJ3)
4
NEe
IIPD78356 Family
Pin Functions; Normal Operating Mode
Pin Name
Function
Alternate Pin Name
Alternate Function
POo
Port 0; 8-bit, bit-selectable VO port
RTPo
ADTRGO
Rea~time output port
External trigger input for AID converter
RTP,
ADTRGI
Rea~time output port
External trigger input for A/D converter
RTP2
ADTRG2
Real-time output port
External trigger input for AID converter
RTP3
ADTRG3
Real-time output port
External trigger input for AID converter
Rea~time
output port
Port 1 ; 8-bit, bit selectable VO port
Port 2; 8-bit, bit-selectable VO port
(P2o Is Input only)
P22
P26
P30
Port 3; B-blt, bit-selectable VO port
NMI
External nonmaskable interrupt
INTPO
T004
External maskable interrupt
Timer output from real-time pulse unit
INTP1
T005
External maskable interrupt
Timer output from real-time pulse unit
INTP2
External maskable interrupt
INTP3
External maskable interrupt
INTP4
External maskable interrupt
TCLR2
T021
Clear input to rea~time pulse unit
Timer output from rea~time pulse unit
T020
Timer output from
TxD
Asynchronous serial transmit data output
RxD
Asynchronous serial receive data input
SOOO
Serial data output; three-wire serial VO mode
VO bus for NEC serial bus interface mode
seo
pulse unit
Sel
Serial data input; three-wire serial VO mode
I/O bus for NEC serial bus interface mode
SIOO
P33
rea~time
SCKOO
Serial clock VO for synchronous serial interface
P3s
TCLRI
Clear input to real-time pulse unit
P36
Til
TOIl
External clock to timer 1
Timer output from rea~time pulse unit
T010
Timer output from real-time pulse unit
ADo-ADr
Low-order a bits of external multiplexed address/data
bus
Port 4; 8-bit, byte-selectable I/O port
(78356/P356)
High-order a bits of external multiplexed address/data
bus
Port 5; 8-blt, bit-selectable I/O port
(78358/P356)
Port 7; a-bit Input port
ANI0-ANI7
Analog inputs to AID converter
5
pPD78356 Family
Pin Functions; Normal Operating Mode (cont)
Pin Name
Function
Alternate Pin Name
Alternate Function
Plio
Port 8; B-bit, bit-selectable I/O port
TCLRO
Clear input to real-time pulse unit
TIO
T003
External count clock to timer 0
Timer output from rea~time pulse unit
P8s
P90
Port 9; 4-bit, bit-selectable I/O port
(P90 to P92 on 7B356/P356)
Timer output from real-time pulse unit
Timer output from real-time pulse unit
T002
Timer output from
TCLRUD
Clear input to real-time pulse unit
rea~time
pulse unit
PWMO
Pulse-width modulated output
PWMI
Pulse-width modulated output
RD
External memory read strobe output
LWR
External memory write strobe output to low-order 8bits in memory
HWR
External memory write strobe output to high-order
8-bits in memory
SOlO
Serial data output; three-wire serial I/O mode
SilO
Serial data input; three-wire serial I/O mode
Pl~
SCK10
Serial clock I/O for synchronous serial interface
P103
SOll
Serial data output; three-wire serial I/O mode
Sill
Serial data input; three-wire serial I/O mode
P105
SCK11
Serial clock I/O for synchronous serial Interface
P10s
TIUD
External clock for up/down counter
Plcq
TCUD
Up/down counter count direction control signal
PiCa
Port 10; B-bit, bit-selectable I/O port
TOOO
TOOl
ANOO, ANOI
Analog outputs from D/A converter
ASTB
Address strobe output; used to latch
address for external memory
CLKOUT
Output of the system clock
MODEO,
MODEl
Set MODEO and MODEl to Vss to
access internal program memory on
78356/P356. H all program memory is
external, set MODEO to VDD and
MODEl to to VSS for an B-bit data
bus. Or set both to VDD for a 16-bit
data bus.
To place 78P356 in programming
mode, set MODEO to VDD and MODEl
to Vss. The level of this pin cannot be
changed during normal operation.
NC
Pins labeled NC are not internally
connected and may be connected to
Vss
RESET
External system reset input
WAIT
A low-level Input adds walt states to
the external bus cycle
WDTO
Open-drain output from the watchdog
timer
6
NEe
IIPD78356 Family
Pin Functions; Normal Operating Mode (cont)
Pin Name
Function
XI
Crystal connection or
external clock input
X2
Crystal connection or
open for external clock
AVDD
AID converter power input
AVREFl
AID converter reference voltage high
AVREF2
D/A converter reference voltage high
AVREF3
D/A converter reference voltage low
AVSS
AID converter ground
VDD
+5 volt power input
VSS
Ground
Alternate Pin Name
Alternate Function
7
NEe
pPD78356 Family
Block Diagram; "PD78356 Family
Execution
Memory
Control
NMI(P2o)~
CLKOUT
InI8rna1
Program
Memory
48KBytes
INTPO·INTP4
(P21.p2s)
~PD7835B1
TlClTOO3 (P81) ~
TI11T011 (P3a) ~
Xl
X2
-----.
TIO
INTOVO
INTCMOO
Compare Register
CMOO
TOOO
Compare Register
CMOl
TOOl
INTCMOl
INTCOOO
IN1PO~
Oetector
CapturelCompare
Register CCOO
INlPl~
CapturefCompare
Register CC01
T005
INlP2
~
Oetector
CapturelCompare
Register CC02
INTCCOl
INTCC02
, - - - - - - INTCM02
Compare Register
CM02
TOO2
Compare Register
CM03
1----<> TOO3
' - - - - - - INTCM03
1I3Yl.-9486B·1 (9193)
30
NEe
pPD78356 Family
Figure 13. Real-Time Pulse Unit (Sheet 2 of 3)
Timer/COunter 1
TCLRl
Overflow
I----+---"--'-"'=---~
Til
OVFl Flag
r - - - - - INTCM10
Compare Register
CM10
Compare Register
CMll
1------0
'-----~~
TOll
INTCMll
nmer2
TCLR2
1-_ _+
__....::Ov:.:..:::Srfl.:.::O:.:w'--_ _
OVF2 Flag
, - - - - - INTCM20
Compare Register
CM20
Compare Register
CM2l
1-----0
T02l
' - - - - - _ INTCM2l
83YL·9486B-2
31
NEe
fJPD78356 Family
Figure 13. Real-Time Pulse Unit (Sheet 3 of 3)
TimerS
r---~
"CLK/4
OVF3 FBg
I -_ _-I--=.Ove=rflo;:;w"-~_-_ INTOV3
'CLKI8
'CLK/18
'CLKI32
INTP3
~
~
CaptureiCompare
RegBwrCCSO
~
CaptureiCompare
INTP4 ~
Reg~rCCS1
1 - - - - - - + 1NTCC31
nmer4
Compare Reglswr 1---0>---,.--+ INTCM40
CM40
Serial Interface
UplDown Counter
TCLRUD
'CLK/4
r~~-l-.2!!~---l-_ OVFUD FBg
'CLKI8
L...-,..-_,..........I
t--""'=='--..--t--~
UDFUD Flag
'CLK/18
nUD
Compare RegBwr
CMUOO
r-----~-~INTCMUDO
TCUD
CompareR~r
CMUD1
32
1-------~INTCMUD1
NEe
pPD78356 Family
The 16-bit up/down counter (UDC) can count the internal system clock (divided by 4, 8, or 16) or count
external events on the T1UD pin. When the counter
overflows, an overflow bit is set. If the counter underflows, an underflow bit is set. The UDC can be cleared
by an external clear input (TCLRUD) or by a coincidence signal from its compare register.
When counting external events, the UDC can be programmed to operate in four modes. See figure 14. In
mode 1, the UDC counts external events on the TIUD
pin. When direction control pin TCUD is high, the UDC
counts down. When TCUD is low, the UDC counts up.
Figure 14. Up/Down Counter; Modes 1, 2, 3, 4
Mode 1
Mode 2
nUD
TCUD
J
TCuD _ _ _ _~~~________
~Count Downl-~>rolo(o-----Count u p - - UDC 8
Count
~COUntUP~HOI~Down~Hold-UDC~~1!..__ _ _ __
8
il.
Start CounUng
* nUD set for rising edge.
Mode 3. Count Down
UDe
Mode 3. Count Up
FFFCH
* TIUD set for rising edge.
* nUD set for rising edge.
Mode 4
~-----;CounIUp-----~
~----CountDown,----~
TIUD
TCUD
UDe
33
pPD78356 Family
In mode 2, when the preset edge (rising, falling, or both)
is detected at the TIUD pin, the UDC counts up; when a
rising edge is detected at the TCUD pin, the UDC
counts down. If TIUD and TCUD are active simultaneously, they are not counted and the value in the UDC
is held.
Modes 3 and 4 are designed to count the output of a
two-phase shaft encoder on a servomotor. In mode 3,
two signals having a 90-degree phase shift are entered
into the TlUD and TCUD pins. When the preset edge
(rising, falling, or both) is detected on the TlUD pin, the
signal level on TCUD is sampled. If the level of TCUD is
low, the UDC counts down; if the level is high, the UDC
counts up.
When mode 4 is specified, quadrature counting is
enabled. The UDC is incremented or decremented at
positive and negative transitions of both input signals.
Whether it is incremented or decremented is dependent upon the relative phase of the two signals as
illustrated in figure 14.
The pPD78356 family has programmable noise detection on the external clock inputs and external clear
inputs to the RPU. The noise detection time can be set
for each input at 4 or 16 internal system clocks by the
noise protection control register (NPC).
Interrupts
The pPD78356 family has 24 maskable hardware interrupt sources: 5 software selectable as external or
internal and 19 internal. The four external maskable
interrupts share pins with port 2. Any of them, INTPO
and INTP4, can also be used to trigger capture events
in the real-time pulse unit. In addition, there are two
nonmaskable interrupts, three software interrupts, and
reset. The software interrupts, generated by the BRK or
BRKCS instruction and the operation code trap, are
not maskable. See table 3.
34
NEe·
NEe
pPD78356 Family
Table 3. Interrupt Sources
Type of
Request
Default"
Priority
Signal
Name
Software
Vector Address
TPF
= 0
TPF
=1
location
Operation code trap
CPU
003CH
003CH
BRK instruction
CPU
003EH
003EH
BRKCS instruction
(Initiates context switch)
CPU
NMI
NMI Input pin
External
0002H
S002H
INTWDT
Watchdog timer overflow
Internal
0004H
S004H
INTOVO
Timer 0 overflow
Internal
FE06H
0006H
8006H
INTOV3
Timer 3 overflow
Internal
FE06H
0006H
8006H
2
INTPO
INTCCOO
INTPO pin
coincidence
ceoo
External
Internal
FEOAH
OOOAH
800AH
3
INTPl
INTCCOl
INTPl pin
CCOl coincidence
External
Internal
FEOCH
OOOCH
800CH
4
INTP2
INTCC02
INTP2 pin
CC02 coincidence
External
Internal
FEOEH
OOOEH
800EH
5
INTP3
INTCC30
INTP3 pin
CC30 coincidence
External
Internal
FE10H
0010H
S010H
6
INTP4
INTCC31
INTP4 pin
CC31 coincidence
External
Internal
FE12H
0012H
8012H
Nonmaskable
Maskable
Macro Service
Control Word
Source
0
7
INTCMOO
CMOO coincidence
internal
FE14H
0014H
8014H
8
INTCMOl
CMOl coincidence
Internal
FE16H
0016H
8016H
9
iNTCM02
CM02 coincidence
Internal
FE18H
0018H
8018H
10
INTCM03
CM03 coincidence
Internal
FE1AH
001AH
801AH
11
INTCM10
CM10 coincidence
Internal
FElCH
001CH
801CH
12
iNTCMll
CMll coincidence
internal
FE1EH
001.EH
S01EH
13
INTCM20
CM20 coincidence
Internal
FE20H
0020H
8020H
14
INTCM21
CM21 coincidence
Internal
FE22H
0022H
8022H
15
INTCM40
CM40 coincidence
Internal
FE24H
0024H
8024H
16
INTCMUDO
CMUDO coincidence
Internal
FE26H
0026H
8026H
17
INTCMUD1
CMUD1 coincidence
Internal
FE2SH
0028H
S028H
18
INTSER
Asynchronous serial
interface reception error
Internal
FE2AH
002AH
802AH
19
INTSR
End of asynchronous serial
Interface reception
Internal
FE2CH
002CH
802CH
20
INTST
End of asynchronous serial
interface transmission
Internal
FE2EH
002EH
S02EH
21
INTCSIO
End of clocked serial interface CSIO
transmission/reception
Internal
FE30H
0030H
8030H
22
INTCSll
End of clocked serial interface
CSll transmission/reception
Internal
FE32H
0032H
8032H
23
INTAD
End of AID conversion
Internal
FE34H
0034H
8034H
RESET
RESET pin
Externai
OOOOH
OOOOH
Reset
• 0 is the highest priority.
35
..
NEe
JlPD78356 Family
Interrupt Servicing
Figure 15. Interrupt Control Register (xxICx)
The JlP078356 family provides four levels of programmable hardware priority control and three different
methods of handling maskable interrupt requests:
standard vectoring, context switching, and macro service. The programmer can choose the priority and
mode of servicing each maskable interrupt by using
the interrupt control registers.
Interrupt Control Registers
The JlP078356 family has 24 interrupt control registers.
Each maskable interrupt request has its own control
register, which includes bits to specify interrupt request, interrupt mask, macro service enable, context
switch enable, and priority. Priorities range from 0
(highest) to 3. See figure 15.
There are also three mask flag register, MKOL, MKOH,
and MK1L, with a bit for each maskable interrupt. Since
each interrupt has two mask bits, the masking of the
interrupt is the "or" function of those two bits.
Interrupt mode control register IMC can enable or
disable nesting of interrupts set to the lowest priority
level (level 3). Inservice priority register ISPR is used by
the hardware to hold the priority level of the interrupt
request currently being serviced. It is manipulated by
hardware only, but it can be read by software.
Finally, the IE bit of the program status word also is
used to control the interrupts. If the IE bit is 0, all
maskable interrupts, but not macro service, are disabled. The IE bit can be set or cleared by the EI or 01
instruction, respectively, or by direct writing to the
PSw. The IE bit is cleared each time an interrupt is
accepted.
7
6
5
4
xxlFxx
xxMKxx
xxlSMxx
xxCSExx
3
2
o
o
o
xxPRxl
xxPRxO
Interrupt Request Flag
xxlFxx
No interrupt request
Interrupt request received
0
1
Interrrupt Mask Flag
xxMKxx
Interrupt request enabled
Interrupt will be pending
0
1
xxlSMxx
Macro Service Enable
0
Software interrrupt
Macro service
xxCSExx
Context Switch Enable
Vector interrupt
Context switch
0
1
xxPRxl
xxPRxO
0
0
1
1
0
1
0
1
Priority Specification
Priority
Priority
Priority
Priority
0 (highest
1
2
3
Interrupt Priority
The two nonmaskable interrupts, NMI and INTWOT,
have priority over all others. Their priority relative to
each other is under program control.
Four hardware-controlled priority levels are available
for the maskable interrupts. Any one of the four levels
can be assigned by software to each of the maskable
interrupt lines. Interrupt requests of a priority higher
than the processor's current priority level are accepted; requests of the same or lower priority are held
pending until the processor's priority state is lowered
by a return instruction from the current service routine.
By setting the PRSL bit of the IMC register to zero, it is
possible to specify in software that level 3 interrupts
(the lowest level) can be accepted when the processor
is operating at level 3. This nesting within a level
applies to level 3 only.
Interrupt requests programmed to be handled by
macro service have priority over all software interrupt
service regardless of the assigned priority level, and
36
NEe
JlPD78356 Family
macro service requests are accepted even when the
interrupt enable bit in the PSW is set to the disable
state. See figure 16.
The default priorities listed in table 3 are fixed by
hardware; they are effective only when it is necessary
to choose between two interrupt requests of the same
software-assigned priority. For example, the default
priorities would be used after the completion of a
high-priority routine if two interrupts of the same lower
priority were pending.
Software interrupts, the BRK and BRKCS instructions,
and the operation code trap are executed regardless of
the processor's priority level and the state of the IE bit.
They do not alter the processor's priority level.
Figure 16. Interrupt Service Sequence
Interrupt Request
L
=
=
xxMK 1 (Intenrupt Masked) Intenrupt Pending.
xxMK 0 (Unmasked)
b. . .·,.........
XXlSM
=0 Software Service.
b· '""""'-EI
b"",,·,v-,ICXCSE
=1 Context SwItch.
83RD-7817A
Vectored Interrupt
When vectored interrupt is specified for a given interrupt request, (1) the program status word and the
program counter are saved on the stack, (2) the processor's priority is raised to that specified for the
interrupt, (3) the IE bit in the PSW is set to zero, and (4)
the routine whose address is in the interrupt vector
table is entered. At completion of the service routine,
the RETI instruction (or RETB instruction for software
interrupts) reverses the process, and the JiPD78356
family device resumes the interrupted routine. The
corresponding interrupt request flag is cleared before
executing the interrupt service routine.
Context Switch
When context switching (figure 17) is specified for a
given interrupt, the active register bank is changed to
the register bank specified by the three low-order bits
of the word in the interrupt vector table. The program
counter is loaded from RP2 of the new register bank,
the old program counter and program status word are
saved in RP2 and RP3 of the new register bank, and the
IE bit in the PSW is set to zero.
At completion of the service routine, the RETCS instruction for routines entered from hardware requests
or the RETCSB instruction for routines entered from
the BRKCS instruction reverses the process. The old
program counter and program status word are restored from RP2 and RP3 of the new register bank. The
entry address of the service routine, which must be
specified in the 16-bit immediate operand of these
return instructions, is stored again in RP2.
37
NEe
pPD78356 Family
Figure 17. Context Switching and Return
Context SwItch
Retum From Context SwItch
NewAc1lve
Register Bank
CUIT8fI!AcUva
Register Bank
AX
CUrrent Aclive
Register Bank
Former AcUve
Register Bank
AX
AX
BC
BC
llnvnedete
Data, 16BIIsJ
BC
BC
RP2
~
PC
Save Area
RP3
~
SaveAree
SaveAree
VP
VP
VP
VP
UP
UP
UP
UP
DE
DE
DE
DE
HL
HL
HL
HL
l
l
Program
Counter
I
PC
SaveAree
PEm
PSW
r----
RP2
r--
RP3
J;=-
l1
Y
Program
StetusWord
Program
Counter
J
Program
StetusWord
I
83RI>8738II
Macro Service
When macro service is specified for a given interrupt,
the macro service hardware temporarily stops the
executing program and transfers data between the
special function register area and the memory space.
Control is then returned to the executing program,
providing a completely transparent method of interrupt
service. Macro service significantly improves response
time and makes it unnecessary to save any registers.
For each request on the interrupt line, one operation is
performed, and an 8-bit counter is decremented. When
the counter reaches 0, a software service routine is
entered according to its specified priority. Either vectored interrupt or context switch can be specified for
entry to this routine, which is known as the macro
service completion routine.
Macro service is provided for all of the maskable interrupt requests, and each has a specific macro service
control word stored in on-Chip main RAM. The function
to be performed is specified in the control word.
38
The pPD78356 family provides five different macro
service functions.
Function
Description
EVrCNT
Event counter. Counts up to 256 events
by incrementing or decrementing the
macro service counter. When the counter
reaches OOH, the software service
routine is entered.
BLKTRS
Block transfer. Transfers a byte or word
of data in either direction between a
specified special function register and a
buffer in main RAM (FExx).
BLKTRS-P
Block transfer with memory pointer.
Transfers a byte or word of data in either
direction between a specified special
function register and a buffer anywhere
in the 64K-byte address space.
DTADIF
Data difference. Stores the difference
between the current value of a specified
16-bit special function register and its
previous value in a word buffer in main
RAM (FExx).
NEe
DTADIF-P
Data difference with memory pointer.
Stores the difference between the
current value of a specified 16-bit
special function register and its previous
value in a word buffer anywhere in the
64K-byte address space.
Standby Modes
The standby modes, HALT and STOP, reduce power
consumption when CPU action is not required. In HALT
mode, the CPU is stopped but the system clock continues to run. The HALT mode is released by any
unmasked interrupt, any nonmaskable interrupt, or an
external reset pulse. In STOP mode, both the CPU and
the system clock are stopped, further minimizing
power consumption. The STOP mode is released by
either an external reset pulse or an external NMI.
The HALT and STOP modes are entered by programming standby control register STBC. This register is a
protected location and can be written to only by a
special instruction. If the third and fourth bytes of the
instruction are not complements of each other, the
data is not written and an operation code trap interrupt
occurs.
pPD78356 Family
Once started, the timer can be stopped only by an
external reset. Watchdog timer mode register WDM is
used to select the time interval, to set the relative
priority ofthe watchdog timer interrupt and NM I, and to
clear the timer. This register is a protected location and
can be written to only by a special instruction. If the
third and fourth bytes of the instruction are not complements of each other, the data is not written and an
operation code trap interrupt occurs.
External Reset
The pPD78356 family is reset by taking the RESET pin
low. The reset circuit contains a noise filter to protect
against spurious system resets caused by noise. On
power-up, the RESET pin must remain low until the
power supply reaches its operating voltage and the
oscillator has stabilized. During reset, the program
counter is loaded with the address contained in the
reset vector table (addresses OOOOH, 0001H); program
execution starts at that address upon the RESET pin
going ~While RESET is low, all external lines
except WDTO, CLKOUT, Vss, Voo, AVss, AVoo, AVREF1,
AVREF2, AVREF3, X1, and X2 are in the high-impedance
state.
Watchdog Timer
.....
-\
The watchdog timer protects against inadvertent program loops. A nonmaskable interrupt occurs if the
timer is not reset by the program before it overflows. At
the same time, watchdog timer output pin WDTO goes
active low for a period of 32 system clocks. The WDTO
pin can be connected to the RESET pin or used to
control external circuitry. Three program-selectable
intervals are available: 8.2, 32.8, and 131.1 ms at 32
MHz.
,
39
NEe
pPD78356 Family
Preliminary
ELECTRICAL SPECIFICATIONS (Preliminary)
Operating Conditions
Absolute Maximum Ratings
Oscillator Frequency, fxx
TA = 25·C
8 to 32 MHz
Supply voltage, Voo
-0.5 to + 7.0 V
Supply voltage, Vpp
-0.5 to +13.5 V
Input voltage, VI
Except P20/NMI (A9) of 78P356
P20INMI (A9) of 78P356
-0.5 to Voo + 0.5 V
-0.5 to +13.5 V
Output voltage, Vo
-0.5 to Voo +.0.5 V
Output current, low; 10L
Each output pin
Total
4.0 rnA
140 rnA
Output current, high; 10H
Each output pin
Total
-1.0 rnA
30 rnA
-65 to
+1500C
Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent damage. The device should be operated within the limits
specified under DC and AC characteristics.
40
+5.0V ±10%
Capacitance
TA = 25·C;
voo
Parameter
=
vss
= 0V
Symbol
Max
Unit
Input pin
capacitance
CI
TBD
pF
Output pin
capacitance
Co
TBD
pF
I/O pin
capacitance
CIO
TBD
pF
AC Timing Test Points
Operating temperature, TOPT
Storage temperature, TSTG
-10 to +7OOC
Conditions
f = 1 MHz;
unmeasured pins
returned to 0 V
x
0.8 Voo
or 2.2
V
voo------~x_____
~~
______
oV _ _ _--'
0.8 V
_
.'--____
B3CL-914M
NEe
pPD78356 Family
Preliminary
DC Characteristics
TA = -10 to + 70·C; voo = +5.0 V ±10%; vss = 0 v
Symbol
Parameter
Min
Typ
o
Input voltage. low
Input voltage, high
Max
Unit
0.8
V
(Note 1)
2.2
V
0.8 VOO
V
(Note 2)
V
= 2.0 mA
= - 4OO IlA
VI = OtoVoo
Vo = 0 to Voo
Output voltage. low
0.45
Output voltage. high
Conditions
IOL
V
VOO -1.0
IOH
Input leakage current
±10
IlA
Output leakage current
±10
IlA
75
107
mA
Operating mode; 78355/356
86
125
mA
Operating mode; 78P356
HALT mode; 78355/356
VOO supply current
1001
1002
Data retention voltage
VOOOR
Data retention current
1000R
40
60
mA
40
60
mA
2.5
HALT mode; 78P356
V
STOP mode
2
10
IlA
STOP mode; VOOOR
10
50
IlA
STOP mode; VOOOR
= 2.5 V
= 5.0 V ±1D%
Notes:
(1) All except pins in Note 2.
(2) Pins RESET, Xl, POo - P03, P2, P32 - P36, P80 - P81. P85, P101,
P102, P104 - P107·
AC Characteristics
= -10 to +70·C; voo =
TA
+5.0 V ±1D%; vss
Parameter
= 0 V; !xx = 32 MHz
Symbol
Calculation Formula
Min
Max
Unit
62.5
250
..
Conditions
External Memory Read/Write Operation
System clock cycle time (Note 1)
tCYK
ns
CL
Address setup time to ASTB j
tSAST
(0.5 + a)T - 24
7
ns
CL
Address hold after ASTB j
tHSTA
0.5T-16
15
ns
= 50 pF
= 100 pF
CL = 100 pF
RD j to address floating
tFRA
Address to data input valid
tOAID
(2.5 +a + n)T-56
RD j to data input valid
tORIO
(1.5 + n)T - 44
ASTB j to RD j delay time
tosTR
0.5T-16
Data hold time from RD f
tHRIO
RD f to next address active
tORA
0
ns
CL = 100 pF
100
ns
CL
49
ns
CL
15
ns
0
ns
0.5T -14
17
ns
63
ns
14
tWRL
(1.5 + n)T - 30
ASTB width high
tWSTH
(0.5 + a)T -17
LWR or HWR to data output
toweD
0.5T-l0
ASTB j to LWR j or HWR j delay
tOSTW
0.5T-16
15
ns
tsoow
(1 + n)T-5
57
ns
8
ns
RDwldth low
Data setup time to LWR f or HWR
Data hold time after LWR
t
t or HWR t
tHWOO
LWR or HWR width. low
tWWL
(1.5 + n)T - 30
WAIT setup time from address
tSAWT
(a + n)T -15
WAIT hold time from address
tHAWT
(0.5 + a + n)T
ns
21
63
ns
110
156
ns
ns
ns
(Note 2)
= 100 pF (Note 2, 3)
= 100 pF (Note 3)
CL = 100 pF
CL = 100 pF
CL = 100 pF
CL = 100 pF (Note 3)
CL = 100 pF (Note 2)
CL = 100 pF
CL = 100 pF
CL = 100 pF (Note 3)
CL = 100 pF
CL = 100 pF (Note 2, 3)
CL = 100 pF (Notes 2, 4)
CL = 100 pF (Notes 2, 4)
41
NEe
pPD78356 Family
Preliminary
AC Characteristics (cont)
Parameter
Symbol
Calculation Formula
WAIT setup time from RD I or WR I
tsRWRY
(n -l)T - 25
WAIT hold time from RD I or WR I
tHRWRY
(n - 0.5)T - 14
tOWST
1.5T-15
ASTB
t delay time from
WR
t
Min
Max
Unit
37
Conditions
ns
CL = 100 pF (Note 4)
79
ns
CL = 100 pF (Note 4)
TBD
ns
CL = 100 pF
Serial Port Operation
aT
ns
SCK output
500
ns
SCK input
4T -40
ns
SCK output
210
ns
SCK input
4T -40
ns
SCK output
210
ns
SCK input
tSRXSK
80
ns
SI hold time after SCK
tHSKRX
80
SCK I to SO delay time
tOSKTX
SCK cycle time
tCYSK
SCK width, low
twSKL
SCK width, high
tWSKH
SI setup time to SCK t
Definitions:
(3)
=
address wait state: a
ns
Notes:
(1) T = tCYK (ns)
(2) a
ns
110
(t) tCYKequals twice the period of the crystal or external clock Input.
= a or 1
(2) No address wait state
~number
of wait states specified by the external wait pin
WAIT and the PWC register
(3) No wait states
(4) One external wait state and one internal wait state.
AID Converter Characteristics
TA = -10 to + 70'C; AVOO = VOO = +5 V ±10% or +3 V ±10%; VSS = AVss = 0 V
Parameter
Symbol
Min
Typ
Resolution
Total error·
Quantization error
Conversion time
tCONV
Bit
1.2
%
±1/2
LSB
Conditions
32
tCYK
AD trigger mode
tCYK
Timer/external trigger mode
Sampling time
tSAMP
7.5
AlAN
-0.3
Analog input impedance
RAN
Reference voltage
AVREF1
AVREF1 current
AIREF1
AVREF1 +0.3
TBD
Aloo
ful~scale
V
MO
VOO
V
3.0
9
mA
!xx =
TBD
TBD
mA
ADMO.7(CS) = 0
3.3
13
mA
Operational mode
TBD
• Does not include quantization error. Percentage of
42
Unit
10
37
Analog input voltage
AVOO supply current
Max
value is shown.
32 MHz
NEe
pPD78356 Family
Preliminary
D/A Converter Characteristics
= -10 to +70'C; AVREF2 = VDD = +5 V ±10%; AVREF3 = Vss = 0 v
TA
Parameter
Symbol
Min
Typ
Resolution
Max
Unit
8
Bit
Conditions
Overall error
TBD
%
Selt ling time
2
I1s
Load condition 2 MQ 30 pF
kQ
When DACSO and DACSl are set to 7FH
Output resistance
20
RO
Analog reference voltage
Reference supply input current
AIREF3
V
0.75 VDD
VDD
Vss
0.2 VDD
V
o
5
mA
-5
0
mA
Up/Down Counter Operation
= -10 to + 70"C; VDD = +5 V ±10% Vss = 0 V; T = tCYK (ns)
TA
Parameter
Symbol
TIUD high-, low-level width
twTIUH, tWTIUL
TCUD high-, low-level width
Min
tWTCUH, twTCUL
TCLRUD high-, low-level width
twCLUH, !wCLUL
TCUD setup time to TIUD
tSTCU
TCUD hold time from TIUD t
Unit
Max
Conditions
aT
ns
Except mode 4
bT
ns
Mode 4
aT
ns
Except mode 4
bT
ns
Mode 4
aT
ns
o
ns
Mode 3, rise
2T
ns
Mode 3, rise
TIUD setup time to TCUD
tS4TIU
4T
ns
Mode 4
TIUD hold time from TCUD
tH4TIU
4T
ns
Mode 4
TIUD, TCUD cycle time
tCYC4
I
= 1, then a = b = 16.
Other Operations
TA = -10 to +70'C; VDD =
= 0 V; T = tCYK (ns)
+5 V ±10%; Vss
..
MHz
Note: a, b are defined by NPC register.
NPC.bit = 0, then a = 4, b = 8; NPC.bit
Parameter
Symbol
NMI high-, low-level width
!wNIH, twNIL
Min
2
INTPO to INTP4 high-, low-level width
!wlnH, twlnL
4T
ns
RESET high-, low-level width
!wRSH, twRSL
2
I1S
Tin high-, low-level width
!wTlnH' !wTlnL
aT
ns
TCLRn high-, low-level width
!wCLnH, tWCLnL
aT
ns
ADTRGn high-, low-level width
twADnH' twADnL
4T
ns
ADC external trigger inputs ADTRGn to
ADTRGm (valid edge to valid edge)
tADCININ
37T
ns
Max
Unit
Conditions
I1S
Note: a is defined by NPC register (a = 4 or 16).
43
NEe
pPD78356 Family
Preliminary
Timing Waveforms
Read Operation (8-Bit Bus)
CLKOUT
2!
Address (High Order)
t'DAIO
HlghZ
H«~
Address (Low Order)
Read Data
l
---11
i
Address 0-7
\
I
HlghZ
'~"T
- t S A S T - +-tHSTA-
ASlB
>--<
~tFRA
+-tORA-
-tOSTR- +-tORIO-!
twSTH
tWRL
-
-tHRWRYtSRWRY
b
44
r-II
\
tHAWT
.
B3CL-9399B (9193)
NEe
I'PD78356 Family
Preliminary
Timing Waveforms (cont)
Read Operation (16-Bit Bus)
CLKOUT
~
tOAIO
HlghZ
M(<-
Address 0-15
-.II
l
Address 0·15
\
/
HlghZ
'"~f
- - t S A S T - -tHSTA-
ASlB
~
Read Oata
_IFRA
tORA-
i t W S T H - - -tOSTR- +-tORIO-1
tWRL
--
-tHRWRY-
tSRWRY
b
V
\
tHAWT
~
83Cl.g40OB (9/93)
45
•
NEe
JlPD78356 Family
Preliminary
Timing Waveforms (cont)
Write Operation (B-Bit Bus)
CLKOUT
X
Address (HIgh Order)
K
Address (Low Order)
~ISAST-
AS1B
----.II
i
Undefined
J
Write Data
~IHSTAl"
(
Address 0·7
\
/
...-IHWOD-l"
/
~IDSTW~
'WSTH
_IDWOD-~ISODW~
_IOWST-lO
tWWL
-
~ -
IHRWRY-
ISRWRY
b
46
\
V
IHAWT
83CL·9401B (9193)
NEe
pPD78356 Family
Preliminary
Timing Waveforms (cant)
Write Operation (16-Bit Bus)
CLKOUT
K
Address 0-15
Undefined
Write Oata
)
- t S A S T - - -<::tHSTA;>O
ASTB
K
Address 0-15
\
/
-tHWOO--;o..
~I
I
-towoo-~tSOOW~
H--tWSTH-- +tosrw-;>o
I
E
~
tOARW
tSRWRY
b
_toWST--)o
.-::----tWWL
tHRWRY-
~
\
II
•
.1
i
tHAWT
B3CL-9402B (9193)
!
47
NEe
pPD78356 Family
Preliminary
Timing Waveforms (cont)
Serial Port Operation, Clock Synchronous Mode
I+------CYsK-----~
IDSKTX
so
SI------------IS-RX-S-'r-I-I"""<~~~~~~=-IH-SK-R-X======:~.-------83FM-9333B
Up/Down Counter Input
tWTIUL
TlUD
:.~~~===-Iwn---UH-------------~--.:~tl~~:~~~~~~~__________
}
__J
---tWTCUL--~
}
TCUD
1...:----tWTCUH---~
tWCLUL
__________
~~~===-tW--CL-U-H======::~~~....:~~~~~~~
TCLRUD ________--')""<. .
48
}
__J
NEe
,.,PD78356 Family
Preliminary
Timing Waveforms (cant)
AID Converter Trigger Input
Interrupt Input
ADTRGn
n=0103
NMI
ADTRGn
INTPn
ADTRGm
n=0104
* Any valid edge 10 any valid edge
Reset Input
83YL-9406A
Timer Input
11n
n=O,l
TeLRn
n=0,1,2
83YL·9406A.
49
NEe
pPD78356 Family
Preliminary
PROM PROGRAMMING
The PROM in the jiPD78P356 is one-time programmable
(OTP) or ultraviolet erasable (UV EPROM). The 49,152 x
8-bit PROM has the programming characteristics of an
NEC jiPD27C1001A, including both page and byte programming modes. Table 4 shows the functions of the
jiPD78P356 pins in normal operating mode and PROM
programming mode.
PROM Programming Mode
Table 4. Pin Functions During PROM
Programming
When MODE1, P2l, and RESET pins are set low, the
pPD78P356 enters the PROM programming mode. Operation in this mode is determined by the setting of CE,
OE, PGM, MODEONpp, and VDD pins as indicated in
table 5.
Normal Operating
Mode
Programming
Mode
Address input
POo - P07, P50, P20,
P51- P57
Ao -A16
Data input
P40 - P47
00- 07
Program pulse
P1 2
PGM
Chip enable
P1a
CE
Output enable
Pl1
OE
Program voltage
MODEO/Vpp
MODEO/Vpp
Mode voltage
MODEl, P21, RESET
MODEl, P21, RESET
Function
to EFFFH). A four-byte ECC Control Word (ECW) is
located at addresses FOOOH to F003H and controls the
ECC circuitry. For additional protection, four bytes of
ECC data for the ECW are located at addresses F004H
to F007H. The error correction code and information to
be stored in the ECW are automatically generated and
added to your HEX file by the ECCGEN program supplied with the RA78K3 Relocatable Assembler Package.
The pPD78P356 also includes a PROM error correction
function capable of correcting one 1-bit error per four
bytes of code. Each device contains 49,152 bytes of
PROM for program storage (OOOOH to BFFFH) and
12,288 bytes of PROM for error correction code (COOOH
Table 5. Operation Modes for Programming
0 0 .07
MODEl
P21
RESET
CE
OE
PGM
MODEONpp
VDD
Page data latch
L
L
L
H
L
H
+12.5 V
+6.5V
Data input
Page program
L
L
L
H
H
L
+12.5 V
+6.5V
High impedance
Byte program
L
L
L
L
H
L
+12.5 V
+6.5V
Data input
Program verify
L
L
L
L
L
H
+12.5 V
+6.5V
Data output
Program inhibit
L
L
L
X
X
L
H
L
H
+12.5V
+6.5V
High impedance
Read
L
L
L
L
L
H
+5.0V
+5.0V
Data output
Ouput disable
L
L
L
L
H
X
+5.0V
+5.0V
High impedance
Standby
L
L
L
H
X
X
+5.0V
+5.0V
High impedance
Mode
X can be either H or L.
50
NEe
pPD78356 Family
Preliminary
Figure t8. Pin Functions in pPD78P356 PROM Programming Modej tOO-Pin Plastic QFP
D2
D3
D4
D5
4
D6
D7
AS
A10
A11
A12
A13
A14
A15
I-lPD78P356GC
A16
MODE1
MODEOIVpp
Vss
VDD
(Open) {
~{
o ~ '" ., ... '" co '" '----v-------"
««««
-
~
I/)
C
'Y 'Y
..
~
-- -
~f':::i"
G'
:::i"
Notes:
Recommended connections for pln. not used during
PROM progIBmmlng:
(L)
(G)
(Opan)
Connect each pin through a resistor to VSS'
Connect to VSS'
No connection.
83YL-9407B
51
NEe
pPD78356 Family
Preliminary
Figure 19. Pin Functions in pPD78P356 PROM Programming Mode; 120-Pin Ceramic LCC
01
DO
)(L)
NO
}(L)
PGM
OE
NC
BE
)~
IlPD78P356KP·S
NC
NO
Vss
Voo
NC
)~
(L){
NO
Voo
NC
(G) {
Vss
NC
(G)
(L){
} (Open)
NC
(L){
61
VSS
VOO
Nole8,
Recommended COMecUOns for pins not used durlng
PROM programming:
(L)
(G)
(Open)
NC
Connect each pin through a resistor to VSS'
Connect to VSS'
No connecHon.
Ccnnect to VSS to prevent noise.
83'fL09408B(I01l13)
52
NEe
pPD78356 Family
Preliminary
PROM Byte Programming Procedure
Data can be written to the PROM one byte at a time by
the following procedure.
(1) Set the pins not used for programming as indicated
in figures 18 and 19. Set MODEONpp and VDD pins to
+5 V and MODE 1, P21, and RESET pins to 0 V. The
CE, OE, and PGM pins should be high.
(2) Supply +6.5~to VD D pin an~+12.5 V to MODEO/
Vpp pin. Set CE pin low and OE pin high.
(3) Provide initial address to pins
Ao - A16.
(4) Provide write data.
(5) Input a 0.1-ms program pulse (active low) to PGM
pin.
(6) Use verify mode (pulse OE low) to test data. If data
has been written, proceed to step 8; if not, repeat
steps 4-6. If data cannot be written in 10 attempts,
go to step 7.
(7) Classify PROM as defective and cease write operation.
(5) Input a 0.1-ms program pulse (active low) to PGM
pin. Data bus Do - D7 is in a high-impedance state.
(6) Use verify mode (pulse OE low four times) to test
four bytes of data. If all four bytes of data have been
written, proceed to step 8; if not, repeat steps 4-6.
If data cannot be written in 10 attempts, go to step
7.
(7) Classify PROM as defective and cease write operation.
(8) Increment address.
(9) Repeat steps 4-8 until last address is programmed.
PROM Read Procedure
The contents of the PROM can be read out to the
external data bus (Do - D7) by the following procedure.
(1) Set the pins not used for programming as indicated
in figures 18 and 19. Set MODEONpp and VDD pins to
+5 V and MODE1, P21, and RESET pins to 0 V. The
CE, OE, and PGM pins should be high.
(2) Supply +5 V to VDD pin and MODEONpp pin.
(8) Increment address.
(3) Input address of data to be read to pins Ao - A16.
(9) Repeat steps 4-8 until last address is programmed.
(4) Put an active-low pulse on CE and OE pins.
PROM Page Programming Procedure
(5) Data is output to pins Do - D7.
Data can be written to the PROM four bytes at a time
(page programming) by the following procedure.
Program Erasure
(1) Set the pins not used for programming as indicated
in figures 18 and 19. Set MODEONpp andVDD pinsto
+5 V and MODE1, P21, and RESET pins to 0 V. The
CE, OE, and PGM pins should be high.
The UV EPROM can be erased by exposing the window ~
to light having a wavelength shorter than 400 nm, . . .~
including ultraviolet, direct sunlight, and fluorescent
.
light. To prevent unintentional erasure, mask the window.
(2) Supply + 6.5~to VD D pin and + 12.5 V to MODEO/
Vpp pin. Set CE pin low.
(3) Provide initial page address to pins Ao - A16.
(4) Provide first byte of data and latch it into PROM by
pulsing OE low. Continue incrementing address
and latching in data until four bytes have been
loaded.
Typically, data is erased by 254-nm ultraviolet rays. A
minimum lighting level of 15 Ws/cm 2 (ultraviolet ray
intensity x exposure time) is required to completely
erase the written data. Erasure by an ultraviolet lamp
rated at 12,000 pW/cm 2 takes 15 to 20 minutes. Remove
any filter on the lamp and place the device within 2.5 cm
of the lamp tubes.
53
NEe
pPD78356 Family
Preliminary
DC Programming Characteristics
= 25°0 ±5°0; Vss = 0 v
TA
Parameter
High-level input voltage
Symbol
Min
VIHl
2.2
Typ
Max
Unit
Voo
V
Condition
Voo
V
(Note 2)
6.75
V
Memory program mode
(Note 1)
VIH2
0.8V oo
VOOP power supply voltage
VOOP
6.25
4.5
5.0
5.5
V
Memory read mode
Vpp power supply voltage
Vpp
12.2
12.5
12.8
V
Memory program mode
V
Memory read mode
6.5
Vpp = VOOP
VOOP power supply current
Vpp power supply current
loop
Ipp
Notes:
(1) All except pins in Note 2.
(2) Pins RESET, XI. POo - P03. P2. P3:! - P36. PBo - P8l. P85.
P10l - P102. P104 - Pl0?
54
30
rnA
Memory program mode
100
rnA
Memory read mode
50
rnA
Memory program mode
100
jJA
Memory read mode
NEe
1'1'078356 Family
Preliminary
AC Programming Characteristics
= 25°C :!:5°C; Voo = 6.5 :!:0.25 V; Vpp = 12.5 ±0.3 V
TA
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
Byte Programming Mode
Address setup time to PGM I
tAS
2
CE setup time to PGM I
tCES
2
/is
tos
2
/is
tAH
2
/is
Input data setup time to PGM I
Address hold time after OE
t
Input data hold time after PGM t
tOH
2
Output data hold time after OE t
tOF
0
Vpp setup time before PGM I
tvps
2
VOO setup time before PGM I
tvos
2
Program pulse width
tpw
0.095
Data to OE I delay time
tOEs
2
OE I to data output time
/is
/is
130
ns
/is
/is
0.1
0.105
ms
/is
150
tOE
ns
Page Programming Mode
Address setup time to OE I
tAS
2
/is
CE setup time to OE I
tCES
2
/is
Input data setup time to OE I
tos
2
/is
tAH
2
/is
tAHL
2
/is
tAHV
0
/is
tOH
2
tOF
0
Vpp setup time to OE I
tvps
2
Voo setup time to OE I
tvos
2
Program pulse width
tpw
0.095
tOES
2
Address hold time from OE
t
Input data hold time after OE
t
Output data hold time after OE
t
Address to OE I delay time
/is
130
,
/is
/is
0.1
0.105
ms
/is
OE I to data output time
tOE
OE pulse width during data latch
tLW
Data to PGM I delay time
tpGMS
2
tCEH
2
/is
tOEH
2
/ls
CE hold time from PGM
CE hold time from OE
t
t
..
ns
150
ns
/l.
/ls
Read Mode
= OE = VIL
= VIL
CE = V1L
CE = VIL
CE = OE = VIL
Address to data output time
tACC
200
ns
CE
CE I to data output time
tCE
200
ns
OE
OE I to data output time
tOE
75
ns
Data hold time from OE t
tOF
0
60
ns
Data hold time from address
tOH
0
ns
55
NEe
JlPD78356 Family
PROM Timing Diagrams
Byte Programming Mode
t
Program
).
_ tAS
K
--!
tOFr--
I
Data Input
_tos-1
Vpp
Vpp
Voo
VOOP
Voo
Voo
-,
Program Ve~fy
{-~
r
IOH ....
I
Data Output
r-tAH~
{-1
Notes:
[1] VOO must be applied before Vpp and removed after V pp.
[2] Vpp must not be greater than +13.5 V,lncludlng overshoot
13]
Removing and reinserting the devloe while a vollaga of +12.5 V
Is applied to pin Vpp may affect device reliability.
83CL-9166B
56
NEe
pPD78356 Family
PROM Timing Diagrams (cont)
Page Programming Mode; Page Data Latch "'"* Page Program
~-------- Page Data Latch - - - - - - - - - - - . 1
.. ,.... Page program-,
Flrst8yte
Data Input
vpp
vPP
VDD
VDDP
VDD
VDD
~~
tvPs
~
tVDS
I\.-1
~tCEH
--tpw
i
~
/I
-tLW-
~
Notes:
[1) VDD must be appHed before VPP and removed after V PI'-
[2J VPP must not be greater than +13.5 V,lncludlng overshOot
[3J Removing and relnserUng the deVfos whHe a voltage of +12.5 V
Is applied to pin VPP may affect device rellabDIly.
83CW166B
57
NEe
pPD78356 Family
PROM Timing Diagrams (cant)
Page Programming Mode; Page Program -. Program Verify
r-Pageprogram'---+ll~
...----------programverlfy'----------~
..
I
I ~~ ____---'x'--_____
~x=:~~
FlrstByta
Data Output
~-l-tPGMS
tOE
I
I
I
vpP------+-------~~--------~+_--------------------------------~---------
Vpp
Voo
VODP
Voo
Voo
1y-
CE
tCEH
_Ipw
I
PGM
Notae:
(1) Voo must be applied before Vpp and removed after V PI"
(2) Vpp must not be greater \!Ian +13.5 V. Including overshoot.
(3) Removing and reinserUng the device WhIle a voItaga of +12.5 V
Is applied to pin Vpp may affect device rellablUty.
8301.-81678
58
NEe
IIPD78356 Family
PROM Timing Diagrams (cant)
Read Mode
)
EIIecIIv8 Address
I
~I
l-.=~~
Nota:
[1] IOF Is spadftad fnlm
~.IOF
[Nota 1]
1+10
HIgh Impedance
OE or CE. whichever goes high flrst.
_
I
I
59
NEe
pPD78356 Family
INSTRUCTION SET
Instruction Set Symbols
The instruction set of the pPD78356 family is upward
compatible with the pPD78322, and pPD78352 families.
Four new instructions (MACW, MACSW, SACW, and
MOVTBL) have been added to the pPD78322 and two
(MACSW and SACW) to the pPD78352 . These additional instructions facilitate digital signal processing.
Symbol
Convolution instruction MACW calculates the sum of
the products of un" pairs of terms stored in main RAM.
The value of un" is limited only by the amount of main
RAM available. The operation of the convolution instructionwith saturation word MACSW is identical to
instruction MACW except when the instuction terminates with the PN flag set. In this case, the AXDE
register will be set to 7FFFFFFFH by an overflow or
80000000H by an underflow.
Correlation instruction SACW subtracts corresponding factors of two tables and calculates the sum of the
absolute values of these subtractions. Instruction
MOVTBL displaces a data table by one 16-bit word to
make room for a new data word.
The instruction set features both 8- and 16-bit data
transfer, arithmetic, and logic instructions and singlebit manipulation instructions. String manipulation instructions are also included. Branch instructions exist
to test individual bits in the program status word, the
16-bit accumulator, the special function registers, and
the saddr portion of on-chip RAM. Instructions range in
length from 1 to 6 bytes depending on the instruction
and addressing mode.
Flag Column Indicators
Definition
RO, R1, R2, R3, R4, RS, R6, R7, R8, R9, R10, R11,
R12, R13, R14, R1S
r1
RO, R1, R2,R3, R4,RS, R6,R7
r2
C,B
rp
RPO,RP1, RP2,RP3,RP4,RP5,RP6,RP7*
rp1
RPO,RP1,RP2,RP3,RP4,RPS, RP6,RP7*
rp2
DE, HL, VP, UP
sfr
Special function register, 8 bits
sfrp
Special function register, 16 bits
post
RPO, RP1, RP2, RP3, RP4, RPS/PSW, RP6, RP7. Bits
set to 1 indicate register pairs to be pushed/
popped to/from stack; RPS pushed/popped by
PUSH/POP, SP is stack pointer; PSW pushed/
popped by PUSHU/POPU, RP5 is stack pointer.
mem
Register indirect: [DE], [HL], [DE+], [HL+], {DE-] ,
[HL-], [VP], [UP]
Base Index Mode: [DE+ A], [HL+ A], [DE+ B],
[HL+ B], [VP+ DE], [VP+ HL]
Base Mode: [DE+ byte], [HL+ byte], [VP+ byte],
[UP+ byte], [SP+ byte]
Index Mode: word [A], word [B], word [DE], word
[HL]
saddr
FE20-FF1 FH: Immediate byte addresses one byte
in RAM, or label
saddrp
FE20-FF1FH: Immediate byte (bit 0= 0) addresses
one word in RAM, or label
word
16 bits of immediate data, or label
byte
8 bits of immediate data, or label
jdisp8
8-bit two's complement displacement (immediate
data, displacement value -128 to +127)
bit
3 bits of immediate data (bit position in byte), or
label
Symbol
Action
(blank)
No change
0
Set to 0
n
3 bits of immediate data
Set to 1
laddr16
16-bit absolute address specified by an immediate
address or label
$addr16
Relative branch address or label
X
Set or cleared according to resul t
P
PIV indicates parity of result
V
PIV indicates arithmetic overflow
R
Restored from saved PSW
60
addr16
l6-blt address
!addrll
ll-bit immediate address or label
addrll
OSOOH-OFFFH: OSOOH + (ll-bit immediate
address), or label
addrS
0040H-007EH: 0040H + 2 X (S-bit immediate
address), or label
A
A register (S-blt accumulator)
X
X register
B
B register
C
C register
D
D register
NEe
pPD78356 Family
Instruction Set Symbols (cant)
Symbol
Definition
E
E register
H
H register
L
L register
RO-R15
Register 0 to register 15
BC
Register pair BC
Register pair AX (lS-bit accumulator)
DE
Register pair DE
HL
Register pair HL
RPO-
Register pair 0 to register pair 7
RP7
PC
Program counter
SP
Stack pointer
UP
User stack pointer (RP5)
PSW
Program status word
PSWH
High-order 8 bits of PSW
PSWL
Low-order 8 bits of PSW
CY
Carry flag
AC
Auxiliary carry flag
Z
Zero flag
P/V
Parity/overflow flag
S
Sign flag
TPF
Table position flag
RBS
Register bank select flag
RSS
Register set select flag
IE
Interrupt enable flag
STBC
Standby control register
WDM
Watchdog timer mode register
( )
Contents of the location whose address is within
parentheses; (+) and (-) indicate that the address
is incremented after or decremented after it is
used
«»
Contents of the memory location defined by the
quantity within the sets of parentheses
xxH
Hexadecimal quantity
•
High-order 8 bits and low-order 8 bits of X
/\
v
Logical product (AND)
Logical sum (OR)
Exclusive logical sum (exclusive OR)
Inverted data
• rp and rpl describe the same registers but generate different
machine code.
61
NEe
pPD78356 Family
Instruction Set
Flags
Mnemonic
.Operand
Operation
Bytes
S
Z
AC
PN
CY
X
X
X
X
X
X
X
X
X
X
8·Bit Data Transfer
MOV
XCH
rl, #byte
rl
8addr, #byte
(saddr)
byte
8fr, #byte (Note 1)
sfr
r,rl
r
A,rl
A--r1
A, saddr
A+- (saddr)
saddr, A
(saddr)
saddr, saddr
(saddr) +- (saddr)
A, sfr
A
sfr
2
sfr, A
sfr +- A
2
A, mem (Note 2)
A+- (mem)
A,mem
A- (mem)
mem, A (Note 2)
(mem) +- A
E-
2
byte
E-
byte
E-
3
rl
E-
E-
3
2
E-
2
A
2
3
2·4
mem, A
(mem) +- A
A, [saddrp]
A+- ((saddrp))
2
[saddrp], A
((saddrp»
2
A,laddr16
A+- (addr16)
4
!addr16, A
(addr16) -A
4
PSWL, #byte
PSWL-- byte
3
PSWH, #byte
PSWH +- byte
3
PSWL,A
PSWL
E-
A
2
PSWH, A
PSWH
E-
A
2
A, PSWL
A+- PSWL
2
A, PSWH
A
2
A, r1
A-rl
E-
E-
2·4
A
PSWH
r,r1
r-r1
A,mem
A- (mem)
2
A, saddr
A-
A, sfr
A- sfr
A, [saddrp]
A-
saddr, saddr
(saddr) -
(saddr)
2·4
2
3
((saddrp))
(saddr)
2
3
16-Bit Data Transfer
MOVW
62
rp1, #Word
rp1
saddrp, #Word
(saddrp) .... word
sfrp, #Word
sfrp .... word
4
rp, rp1
rp +- rp1
2
AX, saddrp
AX ... (saddrp)
2
saddrp, AX
(saddrp) +- AX
2
saddrp, saddrp
(saddrp) ... (saddrp)
3
E-
word
3
4
NEe
pPD78356 Family
Instruction Set (cant)
Flags
Mnemonic
Operand
Operation
Bytes
s
z
AC
PN
CY
x
x
x
x
v
v
v
x
v
x
X
X
X
v
v
16-Sit Data Transfer (cont)
MOVW
(cont)
XCHW
AX, sfrp
AX .... sfrp
2
sfrp,AX
sfrp .... P;x
2
rp1, !addr16
rp1 .... (addr16)
4
!addr16, rp1
(addr16) <-- rp1
4
AX,mem
P;x <-- (mem)
2-4
mem, AX
(mem) .... AX
2-4
AX, saddrp
AX
AX, sfrp
AX <+sfrp
3
saddrp, saddrp
(saddrp) - (saddrp)
3
rp, rp1
rp-rp1
AX,mem
AX- (mem)
<+
(saddrp)
2
2
2-4
8-Sit Arithmetic
ADD
ADDC
SUB
A, #byte
A, CY <-- A + byte
2
X
x
saddr, #byte
(saddr), CY <-- (saddr) + byte
3
x
sfr, #byte
sfr, CY <-- sfr + byte
4
x
x
x
X
x
r,r1
r, CY .... r + r1
2
X
A, saddr
A, CY <-- A + (saddr)
2
X
A, sfr
A,CY<-- A+ sfr
3
X
x
x
x
saddr, saddr
(saddr), CY <-- (saddr) + (saddr)
3
X
X
X
v
X
A,mem
A, CY <-- A + (mem)
2-4
X
x
X
X
mem,A
(mem), CY <-- (mem) + A
2-4
X
x
X
A, #byte
A, CY-A + byte + CY
2
X
X
X
sad dr, #byte
(saddr), CY <-- (saddr) + byte + CY
3
X
X
X
sfr, #byte
sfr, CY <-- sfr + byte + CY
4
X
X
r,r1
r,CY-r+ r1 + CY
2
X
x
x
X
v
v
v
v
v
v
X
A, saddr
A, CY <-- A + (saddr) + CY
2
X
X
X
v
X
A, sfr
A, CY-A + sfr + CY
3
X
X
X
v
saddr, saddr
(saddr), CY ... (saddr) + (saddr) + CY
3
x
X
v
A,mem
A, CY ... A + (mem) + CY
2-4
X
(mem), CY <-- (mem) + A + CY
2-4
x
x
x
x
x
x
x
x
x
x
x
x
x
x
A, #byte
A,CY<--A-byte
2
x
saddr, #byte
(saddr), CY ... (saddr) - byte
3
X
sfr, #byte
sfr, CY <-- sfr - byte
4
r,r1
r, CY<--r- r1
2
x
x
A, saddr
A, CY ... A - (saddr)
2
x
x
x
x
x
x
A, sfr
A, CY ... A-sfr
3
X
X
3
saddr, saddr
(saddr), CY ... (saddr) - (saddr)
A,mem
A, CY <--A - (mem)
2-4
x
x
mem,A
(mem), Cy ... (mem) - A
2-4
x
X
v
v
v
X
v
x
X
v
v
v
v
X
X
X
x
v
x
x
X
v
v
X
X
X
X
X
X
X
X
x
x
x
63
NEe
pPD78356 Family
Instruction Set (cant)
Flags
Mnemonic
Operand
Operation
Bytes
s
z
AC
PN
CY
8·Bit Arithmetic (cont)
SUBC
A, #byte
A, CY .... A- byte- CY
2
X
X
X
V
X
saddr, #byte
(saddr), CY <- (saddr) - byte - CY
3
X
X
X
V
X
sfr, #byte
sfr, CY - sfr - byte - CY
4
X
X
X
V
X
r, r1
r,CY<-r-r1-CY
2
X
X
X
V
X
A, saddr
A, CY <- A - (saddr) - CY
2
X
X
X
V
X
A,sfr
A, CY -A- sfr- CY
3
X
X
X
V
X
sad dr, saddr
(saddr), CY <- (saddr) - (saddr) - CY
3
X
X
X
V
X
A,mem
A, CY <-A- (mem) - CY
2·4
X
X
X
V
X
mem, A
(memJ, CY <- (mem) - A - CY
2-4
X
X
X
V
X
8·Bit Logic
AND
A, #byte
A - A /\ byte
2
X
X
P
saddr, #byte
(saddr) - (saddr) /\ byte
3
X
X
P
sfr, #byte
sfr <- sfr /\ byte
4
X
X
P
r, r1
r - r/\ r1
2
X
X
P
A, saddr
A+- A /\ (saddr)
2
X
X
P
A,sfr
A-A /\ sfr
3
X
X
P
saddr, saddr
(saddr) +- (saddr) /\ (saddr)
3
X
X
P
A,mem
A <- A /\ (mem)
2-4
X
X
P
(mem) +- (mem) /\ A
2-4
X
X
P
mem,
OR
XOR
64
A
A, #byte
A-A V byte
2
X
X
P
saddr, #byte
(saddr) ... (saddr) V byte
3
X
X
P
sfr, #byte
sfr +- sfr V byte
4
X
X
P
r,r1
r+-rVr1
2
X
X
P
A, saddr
A - A V (saddr)
2
X
X
P
A, sfr
A<-A V sfr
3
X
X
P
saddr, saddr
(saddr) ... (saddr) V (saddr)
3
X
X
P
A,mem
A .... AV (mem)
2-4
X
X
P
mem, A
(mem) .... (mem) V A
2·4
X
X
P
A, #byte
A+-AVbyte
2
X
X
P
sad dr, #byte
(saddr) +- (saddr) V byte
3
X
X
P
sfr, #byte
sfr .... sfr V byte
4
X
X
P
r,r1
r+-rVr1
2
X
X
P
A, saddr
A +- A V (saddr)
2
X
X
P
A, sfr
A+-AVsfr
3
X
X
P
saddr, saddr
(saddr) +- (saddr) V (saddr)
3
X
X
P
A,mem
A-AV(mem)
2·4
X
X
P
mem, A
(mem) ... (mem) V A
2·4
X
X
p
NEe
pPD78356 Family
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
s
z
AC
PN
x
x
x
x
x
x
x
x
x
x
x
x
x
x
v
v
v
v
v
v
v
v
v
CY
8-Bit Logic (cont)
CMP
A, #byte
A - byte
2
saddr, #byle
(saddr) - byte
3
sir, #byte
slr- byte
4
r,rl
r- rl
2
A, saddr
A - (saddr)
2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
A, sir
A-sir
3
saddr, saddr
(saddr) - (saddr)
3
A,mem
A- (mem)
2-4
mem,A
(mem)- A
2-4
x
x
x
3
X
X
X
X
X
X
v
v
X
4
x
x
x
16-Bit Arithmetic
ADDW
AX, #Word
AX, CY +- AX + word
saddrp, #Word
(saddrp), CY .... (saddrp)
slrp, #Word
slrp, CY .... slrp
word
5
X
X
x
v
X
rp, rpl
2
X
X
X
X
X
X
3
X
X
X
v
v
v
X
2
AX, slrp
+ rpl
AX, CY .... AX + (saddrp)
AX, CY .... AX + slrp
saddrp, saddrp
(saddrp), CY .... (saddrp)
3
X
X
X
v
X
AX, #Word
AX, CY .... AX - word
3
X
X
(saddrp), CY .... (saddrp) - word
4
slrp, #Word
slrp, CY +- slrp - word
5
x
x
x
x
x
x
X
saddrp, #Word
rp, rpl
rp, CY .... rp - rpl
2
x
x
X
AX, saddrp
AX, CY .... AX - (saddrp)
2
X
X
X
AX, slrp
AX, CY .... AX - slrp
3
X
X
X
X
AX, saddrp
SUBW
CMPW
+
+
word
rp, CY +- rp
+
(saddrp)
saddrp, saddrp
(saddrp), CY .... (saddrp) - (saddrp)
3
X
X
X
AX, #Word
AX -word
3
X
X
X
saddrp, #Word
(saddrp) - word
4
X
X
X
slrp, #Word
slrp -word
5
X
X
X
rp, rpl
rp- rpl
2
X
X
X
AX, saddrp
AX - (saddrp)
2
X
X
X
AX, slrp
AX - slrp
3
X
X
X
v
v
v
v
v
v
v
v
v
v
v
v
v
saddrp, saddrp
(saddrp) - (saddrp)
3
X
X
X
v
X
X
X
X
x
X
X
X
X
X
X
X
X
X
X
X
Multiplication/Division
MULU
rl
AX .... Ax rl
2
DIVUW
rl
AX (quotient), rl (remainder) ... AX .;- rl
2
MULUW
rpl
AX (high-order 16 bits), rpl (low-order 16 bits) ...
AXx rpl
2
DIVUX
rpl
AXDE (quotient), rpl (remainder) ... AXDE .;- rpl
2
MULW
(Note 3)
rpl
AX (high-order 16 bits), rpl (low-order 16
bits) .... AX x rpl
2
65
NEe
pPD78356 Family
Instruction Set (cont)
Flags
Mnemonic
Bytes
S
Z
AC
PN
CV
3
X
X
X
V
X
AXDE <- (8) x (C)
AXDE, 8 +- 8+2, C +- C + 2,
n <- n-l, if overflow (P/V = 1) then AXDE +7FFFFFFFH, if underflow (P/V = 1) then AXDE +-80000000H. End if n = 0 or P/V = 1
3
x
x
x
x
x
[DE+J, [HL+)
AX <- AX + I(DE)-(HL)I, DE +- DE+2, HL
2,C<-C-l.EndifC= OorCY= 1
4
x
x
x
V
x
!addr 16, n
(Note 4)
(addr16 + 2) <- (addr16), n +- n-l, addr16
<-addr16 - 2. End if n = 0
Operand
Operation
Sum-of-Products
MACW
n
AXDE +-- (8) x (C) + AXDE, 8 <- 8 + 2, C +- C +
2, n +- n-l. End if n = 0 or P/V = 1
Sum-of-Products With Saturation
MACSW
n
+
Correlation Operation
SACW
+-
HL +
Table Shift
MOVTBLW
4
Increment/Decrement
INC
DEC
INCW
rl
rl ..... rl + 1
saddr
(saddr)
rl
rl ..... rl-l
saddr
(saddr) ..... (saddr) - 1
rp2
rp2<-rp2+1
+-
(saddr) + 1
2
2
X
X
X
V
X
X
X
V
X
X
X
V
X
X
X
V
3
saddrp
(saddrp) ..... (saddrp) + 1
rp2
rp2 <- rp2-1
saddrp
(saddrp) +- (saddrp) - 1
3
ROR
rl, n
(CY, r17 ..... r10, r1m-l ..... r1m) x ntimes
2
P
X
ROL
rl, n
(CY, r10 +-- r17, rl m+ 1 <- rl ml x n times
2
P
X
RORC
r1, n
(CV
<-
r10, r17 ..... CY, rl m-l
2
P
X
ROLC
rl, n
(CY
+-
r17, r10 ..... CY, rl m+ 1 +- r1m) x n times
2
P
X
SHR
rl, n
(CV"- r10, r17 +- 0, r1m-l
X
SHL
r1, n
SHAW
rpl, n
SHLW
ROR4
ROL4
DECW
Shift/Rotate
<-
rl m) x n times
2
X
X
0
p
(CV+- r17, r10 <- 0, rlm+ 1 +- rlml x n times
2
X
X
0
p
X
(CV+- rp10, rpll5 - 0, rpl m_l ..... rpl m) x n times
2
X
X
0
p
X
rpl, n
(CV- rpl15, rp10 +- 0, rpl m+ 1 +- rpl ml x n times
2
X
X
0
P
X
[rpl)
Aa-o +- (rpl)a-o, (rpl)7-4 +- Aa-o,
(rpl)a-O +- (rplh_4
2
[rpl)
Aa-o - (rpl)7_4, (rpl)a-o <- Aa-o,
(rpl)7_4 <- (rpl)a-o
2
Decimal adjust accumulator after add
2
X
X
X
p
X
X
p
X
<-
r1m) x n times
BCD Adjustment
ADJ8A
ADJBS
Decimal adjust accumulator after subtract
Data Expansion
CVT8W
66
X <- A, As-o +- A7
2
X
X
NEe
pPD78356 Family
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
AC
PN
CY
Bit Manipulation
MOVI
AND1
ORI
CY, saddr.bit
CY ..... (saddr.bit)
3
X
CY, slr.bit
CY ..... slr.bit
3
X
CY, A.bit
CY-A.bit
2
X
CY, X.bit
CY ..... X.bit
2
X
CY, PSWH.bit
CY ..... PSWH.bit
2
X
CY, PSWL.bit
CY ..... PSWL.bit
2
X
saddr.bit, CY
(saddr.bit) - CY
3
str.bit, CY
slr.bit ..... CY
3
A.bit, CY
A.bit-CY
2
X.bit, CY
X.bit ..... CY
2
PSWH.bit, CY
PSWH.bit ..... CY
2
PSWL.bit, CY
PSW L.bit ..... CY
2
CY, saddr.bit
CY ..... CY A (saddr.bit)
3
X
CY, Isaddr.bit
CY ..... CY A (saddr.bit)
3
X
CY, slr.bit
CY ..... CY A str.bit
3
X
CY, Islr.bit
Cy ..... CY A str.bit
3
X
CY,A.bit
Cy ..... CY A A.bit
2
X
CY, IA.bit
CY - CY A A.bit
2
X
CY,X.bit
CY ..... CY A X.bit
2
X
CY, /X.bit
CY - CY A X.bit
2
X
CY, PSWH.bit
Cy ..... CY A PSWH.bit
2
X
CY, IPSWH.bit
CY ..... CY A PSWH.blt
2
X
CY, PSWL.bit
CY ..... CY A PSWL.bit
2
X
CY, IPSWL.bit
CY - CY A PSWL.bit
2
X
CY, saddr.bit
CY - CY V (saddr.bit)
3
X
CY, Isaddr.bit
Cy ..... CY V (saddr.bit)
3
X
CY, str.bit
CY +- CY V str.bit
3
X
CY, Islr.bit
CY ..... CY V str.bit
3
X
CY, A.bit
CY ..... CY V A.bit
2
X
CY,/A.blt
CY ..... CY V A.blt
2
X
CY, X.bit
CY ..... CY V X.bit
2
X
CY, /X.blt
Cy ..... CY V X.blt
2
X
CY, PSWH.bit
Cy ..... CY V PSWH.bit
2
X
CY, IPSWH.bit
CY ..... CY V PSWH.bit
2
X
CY, PSWL.blt
cy ..... CY V PSWL.bit
2
X
CY, IPSW L.bit
CY +- CY V PSWL.bit
2
X
X
X
X
X
67
..
I
NEe
IIPD78356 Family
Instruction Set (cont)
Flags
Mnemonic
Operand
Bytes
Operation
S
z
AC
PN
CY
Bit Manipulation (cont)
XORI
SET1
ClRl
NOTI
CY, saddr.bit
CY .... CY'if (saddr.blt)
3
CY. slr.bit
cy .... CY 'if slr.blt
3
X
CY, A.bit
CY .... CY 'if A.bit
2
X
CY, X.blt
CY .... CY 'if X.bit
2
X
CY. PSWH.blt
CY _ CY 'if PSWH.bit
2
X
CY. PSWL.bit
CY .... CY 'if PSWL.bit
2
X
saddr.bit
(saddr.blt) .... 1
2
sfr.blt
slr.bit- 1
3
A.bit
A.blt .... 1
2
X.blt
X.bit-l
2
PSWH.blt
PSWH.bit-1
2
PSWl.bit
PSWl.blt-l
2
saddr.bit
(saddr.bit) - 0
2
sfr.bit
slr.blt .... 0
3
A.bit
A.blt .... 0
2
X.blt
X.bit .... O
2
PSWH.bit
PSWH.blt .... 0
2
PSWl.bit
PSWl.bit .... O
2
saddr.bit
(saddr.bit) - (saddr.bit)
3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
sfr.bit
sfr.blt.... sfr.bit
3
A.bit
A.blt - A.blt
2
X.bit
X.bit .... X.blt
2
PSWH.blt
PSWH.blt .... PSWH.blt
2
PSWl.bit
PSWl.blt .... PSWl.blt
2
SETI
CY
CY-1
ClRl
CY
CY .... O
0
NOT1
CY
CY-CY
X
Subroutine Linkage
laddrlB
(SP-I) .... (PC + 3)H. (SP - 2) .... (PC
PC .... addrlB. SP - SP - 2
+ 3)l.
3
rpl
(SP-I) - (PC + 2)H. (SP - 2) .... (PC + 2)l.
PCH"" rplH. PCl"" rp1l. SP .... SP - 2
2
[rpl]
(SP-I) .... (PC + 2)H. (SP - 2) .... (PC + 2)l.
PCH"" (rpl + I). PCl"" (rpl). SP .... SP - 2
2
CAllF
laddrll
(SP-l) .... (PC + 2)H. (SP"7 2) .... (PC + 2)l.
PC1S-ll"" 00001. PC1G-O - addrll. SP - SP - 2
2
CAllT
[addr5]
(SP-l) .... (PC + l)H. (SP - 2) - (PC + l)l.
PCH .... (TPFxSOOOH + 2 x addr5 + 41 H).
PCl .... (TPFxBOOOH + 2 x addr5 + 40H). SP ....
SP-2
CAll
68
NEe
"PD78356 Family
Instruction Set (cont)
Flags
Mnemonic
Operand
S
Z
AC
PN
CY
2),
R
R
R
R
R
2),
R
R
R
R
R
R
R
R
R
R
Operation
Bytes
Subroutine Linkage (cont)
BRK
(SP-l)'" PSWH, (SP - 2) ... PSWL, (SP3) ... (PC + I)H, (SP - 4) ... (PC + l)l,
PCl +- (003EH), PCH'" (OO3FH), SP ... SP - 4,
IE ... 0
RET
+ 1), SP ... SP + 2
PCl'" (SP), PCH'" (SP + 1), PSWL - (SP +
PSWH - (SP + 3), SP - SP + 4
PCl - (SP), PCH - (SP + 1), PSWL - (SP +
PSWH ... (SP + 3), SP ... SP + 4
PCl +- (SP), PCH'" (SP
RETB
RETI
Stack Manipulation
PUSH
PUSHU
POP
POPU
MOVW
sfrp
(SP - 1) ... sfrH, (SP - 2) - sfrl, SP - SP - 2
3
post
{(SP - 1) ... rpPH, (SP - 2) ... rpPl, SP - SP - 2} x
n (Note 5)
2
PSW
(SP -1) - PSWH, (SP - 2) - PSWL, SP - SP - 2
post
{(UP -1) ... rpPH, (UP - 2) - rpPl, UP ... UP - 2} x
n (Note 5)
+
sfrp
sfrl - (SP), sfrH - (SP
post
{rPPl - (SP), rpPH - (SP
(Note 5)
PSW
PSWL - (SP), PSWH - (SP
post
{rpPl - (UP), rpPH - (UP
(Note 5)
+
2
1), SP - SP
+
1), SP - SP
+
+
+
1), SP - SP
1), UP - UP
+
2
3
2} x n
+
2
2
2} x n
2
SP, #Word
SP -word
4
Sp, AX
SP-AX
2
AX,SP
AX-SP
INCW
SP
SP - SP
DECW
SP
SP-SP-l
2
•
2
+
2
1
Pin Level Test
CHKL
sfr
(Pin level) 'if (internal signal level)
3
X
X
P
CHKLA
sfr
A ... (Pin level) 'if (Internal signal level)
3
X
X
P
Unconditional Branch
BR
laddr16
PC- addr16
3
rpl
PCH ... rpl H" PCl +- rp1l
2
[rpl]
PCH - (rpl
+
1), PCl - (rpl)
2
$addrl6
PC ... PC
+
2
+
jdlsp6
2
+
+
2
+
+
jdlsp8 if CY = 1
2
jdlsp6 If CY = 0
2
+
+
+
jdisp8 if Z = 1
2
jdisp8 If Z = 0
2
jdlsp8 If P/V = 1
2
Conditional Branch
BC, BL
$addrl6
PC - PC
BNC, BNL
$addrl6
PC ... PC
BZ,BE
$addrl6
PC - PC
BNZ,BNE
$addr16
PC - PC
BV,BPE
$addrl6
PC ... PC
+
+
+
2
2
2
2
69
I
I
N,EC
pPD78356. Family
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
AC
PN
CY
X
X
X
X
X
X
X
X
X
X
Conditional Branch (cont)
BNV,BPO
$addr16
BN
$addr16
BP
$addr16
BGT
$addr16
BGE
$addr16
BlT
$addr16
BlE
$addr16
BH
$addr16
BNH
$addr16
BT
saddr.blt, $addr16
sfr.blt, $addr16
A.blt, $addr16
X.blt, $addr16
PSWH.blt, $addr16
PSWl.bit, $addr16
BF
saddr.blt, $addrl6
sfr.bit, $addr16
A.bit, $addrl6
X.blt, $addrl6
PSWH.blt, $addr16
PSWl.blt, $addr16
BTClR
saddr.blt, $addr16
+
+
PC <- PC +
PC +- PC +
PC +- PC +
PC +- PC +
PC +- PC +
PC <- PC +
PC <- PC +
PC <- PC +
PC +- PC +
PC <- PC +
PC +- PC +
PC +- PC +
PC <- PC +
PC <- PC +
PC +- PC +
PC <- PC +
PC <- PC +
PC <- PC +
PC +- PC +
PC +- PC +
PC
+-
PC
PC +- PC
+
+
2 +
3 +
3+
3+
3+
3+
3+
3+
4+
3+
3+
3+
3+
4+
4+
3 +
3+
3 +
3 +
4 +
2
jdlspB If P/V = 0
2
2
jdlsp8 If S = 1
2
jdlspB If S = 0
2
jdlsp8 If (P/V V S ) V Z = 0
3
jdlsp8 If P/V V S = 0
3
jdlspB If P/V V S = 1
3
jdlsp8 If (P/V V S) V Z = 1
3
jdlspB If Z V CY = 0
3
jdlspB If Z V CY = 1
3
jdlspB If (saddr.blt) = 1
3
jdlsp8 If sfr.blt = 1
4
jdlspB If A.blt = 1
3
jdlsp8 If X.blt = 1
3
jdlspB if PSWH.bit = 1
3
jdispB If PSWL.blt = 1
3
jdlsp8 if (saddr.bit) = 0
4
jdispB If sfr.bit = 0
4
jdisp8 If A.blt = 0
3
jdlsp8 If X.blt = 0
3
jdlsp8 If PSWH.blt = 0
3
jdlspB If PSWL.blt = 0
3
jdlsp8 If (saddr.blt) = 1 then reset
4
jdlsp8 If sfr.blt = 1 then reset
4
3
(saddr.blt)
+
4
PC
+
+
PC +- PC +
3
jdlsp8 If A.blt = 1 then reset A.blt
PC +- PC
3
jdlspB If X.blt = 1 then reset X.bit
3
jdlspB If PSWH.blt = 1 then reset
3
sfr.blt, $addr16
PC +- PC
sfr.blt
A.blt, $addrl6
PC
X.blt, $addr16
PSWH.blt, $addrl6
+-
+
+
+
3+
PSWH.blt
BFSET
PSWl.blt, $addr16
PC +- PC + 3
PSWl.blt
+
jdlsp8 If PSWL.blt = 1 then reset
3
saddr.blt, $addr16
PC +- PC + 4
(saddr.bit)
+
jdlsp8 If (saddr.bit) = 0 then set
4
sfr.blt, $addrl6
PC +- PC
4
jdlspB If sfr.bit = 0 then set slr.blt
4
A.blt, $addr16
PC +- PC
3
jdisp8 if A.blt = 0 then set A.blt
3
X.bit, $addr16
PSWH.bit, $addr16
+
+
PC +- PC +
PC. +- PC +
+
+
3 +
3+
jdispB if X.bit = 0 then set X.blt
3
jdlspB if PSWH.blt = 0 then set
3
jdlsp8 If PSWl.blt = 0 then set
3
PSWH.bit
PSWL.bit, $addrl6
70
PC +- PC + 3
PSWL.bit
+
NEe
,.,PD78356 Family
Instruction Set (cant)
Flags
Mnemonic
Operand
Operation
Bytes
S
Z
AC
PN
Cy
Conditional Branch (cont)
DBNZ
12, $addrl6
12 <- 12 - 1, then PC <- PC + 2 + jdisp8 if 12 = 0
2
saddr, $addrl6
(saddr) .... (saddr) - 1, then PC .... PC + 3 + jdisp8
if (saddr) = 0
3
Context Switching
BRKCS
RBn
RBS:!-o <- n, PCH'" R5, PCL'" R4, R7 .... PSWH,
AS <-- PSWL, RSS <- 0, IE <-- 0
2
RETCS
!addrl6
PCH <-- AS, PCL .... R4, R5
R4 <- addrl6L'
PSWH <-- R7, PSWL <-- R6
3
R
R
R
R
R
RETCSB
!addrl6
PCH <- R5, PCL .... R4, R5 .... addrl6H'
R4 <-- addrI6L,PSWH <-- R7, PSWL .... R6
4
R
R
R
R
R
[DE+j,A
(DE+) .... A, C <- C-l End if C = 0
2
[DE-j, A
(DE-)
[DE+j, [HL+j
(DE+) <- (HL+), C .... C-l End if C = 0
2
[DE-] , [HL-]
(DE-) .... (HL-), C .... C-l End if C = 0
2
[DE+],A
(DE+) ... A, C <-- C-l End if C = 0
2
[DE-], A
(DE-) ... A, C .... C-l End if C = 0
2
[DE+], [HL+]
(DE+) ... (HL+), C .... C-l End if C = 0
2
[DE-] , [HL-]
(DE-) ... (HL-), C <-- C-l End if C = 0
2
[DE+I, A
(DE+)-A,C .... C-l EndifC= OorZ= 0
2
X
X
X
V
X
[DE-], A
(DE-)-A,C<-C-l EndifC= OorZ= 0
2
X
X
X
V
X
[DE+], [HL+]
(DE+)-(HL+), C<-C-l End ifC = OorZ = 0
2
X
X
X
V
X
[DE-I, [HL-I
(DE-) - (HL-), C <- C-l End if C = 0 or Z = 0
2
X
X
X
V
X
[DE+], A
(DE+) - A, C .... C-l End If C = 0 or Z = 1
2
X
X
X
V
X
[DE-I, A
(DE-) -A, C <- C-l End if C = 0 or Z = 1
2
X
X
X
V
X
[DE+], [HL+I
(DE+) - (HL+), C <- C-l End if C = 0 or Z = 1
2
X
X
X
V
X
[DE-] , [HL-I
(DE-) - (HL-), C .... C-l End if C = 0 or Z = 1
2
X
X
X
V
X
[DE+I, A
(DE+) - A, C <- C-l End if C = 0 or CY = 0
2
X
X
X
V
X
[DE-], A
(DE-) - A, C <- C-l End if C = 0 or CY = 0
2
X
X
X
V
X
[DE+ I, [HL+]
(DE+) - (HL+), C <-- C-l End if C = 0 or CY = 0
2
X
X
X
V
X
[DE-] , [HL-I
(DE-) - (HL-), C
2
X
X
X
V
X
[DE+I,A
(DE+) - A, C .... C-l End if C = 0 or CY = 1
2
X
X
X
V
X
[DE-], A
(DE-) - A, C +-- C-l End if C = 0 or CY = 1
2
X
X
X
V
X
[DE+], [HL+]
(DE+) - (HL+), C +-- C-l End if C = 0 or CY = 1
2
X
X
X
V
X
[DE-j, [HL-]
(DE-) - (HL-), C +-- C-l End if C = 0 or CY = 1
2
X
X
X
V
X
<--
addrl6H,
String Manipulation
MOVM
MOVBK
XCHM
XCHBK
CMPME
CMPBKE
CMPMNE
CMPBKNE
CMPMC
CMPBKC
CMPMNC
CMPBKNC
<--
A, C <-- C-l End if C = 0
<--
C-l End if C = 0 or CY = 0
2
71
..
I
NEe
pPD78356 Family
Instruction Set (cant)
Flags
Mnemonic
Operand
Operation
Bytes
CPUContro/
MOV
STBC, #byte
STBC - byte (Note 6)
4
WDM, #byte
WDM +- byte (Note 6)
4
SWAS
SEL
RSS-ASS
RBn
RBn, ALT
NOP
RBS:!.o +- n, RSS +- 0
2
RBS:!.o - n, RSS ... 1
2
No operation
EI
IE +- 1 (Enable interrupt)
01
IE ... 0 (Disable interrupt)
Notes:
(1) A special instruction is used to write to STBC and WDM.
(2) One byte move instruction when [DE], [HL], [DE+], [DE-] ,
[HL+], or [HL-] is specified for memo
(3) l6-bit signed multiply instruction
(4) Addressing range is OFEOOH to OFEFFH.
(5) rpp refers to register pairs specified in post byte. "n" is the
number of register pairs specified in post byte.
(6) Trap if data bytes in operation code are not one's complement. If
trap, then:
(SP-l) ... PSWH, (SP-2) ... PSWL, (SP-3)'" (PC-4)H'
(SP-4) .... (PC-4lL, PCl - (003CH), PCH - (003DH).
SP .... SP-4, IE .... o.
72
s
z
AC
PN
cv
NEe
Development Tools
NEe
Development Tools
Section 6
Development Tools
Development Tools Selection Guide
6-a
ROM Code Submission Guide
6-b
PG-1500 Series
PROM Programmer
6-c
pP078COO Product Line: 8-Bit Microcontrollers
DDB-78K2
Evaluation Board for the pPD78K2 Product
Line
6-m
EB-78230-PC
Evaluation Board for the pPD78238 Family
6-n
6-d
EB-78240-PC
Evaluation Board for the pPD78214/218A/244
Families
6-0
IE-78C11-M
In-Circuit Emulator for the pPD78COO Product
Line
6-e
CC78K2
C Compiler for the pPD78K2 Product Line
6-p
CC87
Micro-Series C Compiler Package for the
pPD78COO Product Line
6-q
RA87
Relocatable Assembler Package for the
pPD78COO Product line
6-f
RA78K2
Relocatable Assembler Package for the
pPD78K2 Product Line
pPD78K3 Product Line: 16-/8-Bit Microcontrol/ers
pPD78KO Product Line: 8-Bit Microcontrollers
IE-78000-R
In-Circuit Emulator for the pPD78KO Product
Line
6-g
CC78KO
C Compiler for the pPD78KO Product Line
6-h
RA78KO
Relocatable Assembler Package for the
pPD78KO Product Line
6-i
SD78KO
Screen Debugger for the pPD78KO Product
Line
6-j
pPD78K2 Product Line: 8-Bit Microcontrollers
IE-78230-R
In-Circuit Emulator for the pPD78224/238
Families
IE-78240-R
In-Circuit Emulator for the pPD78214/218A/244
Families
6-k
6-1
IE-78310A-R
In-Circuit Emulator for the pPD78312A Family
6-r
IE-78327-R
In-Circuit Emulator for the pPD78322 Family
6-s
IE-78350-R
In-Circuit Emulator for the pPD78352/356
Families
6-t
EB-78320-PC
Evaluation Board for the pPD78322 Family
6-u
EB-78350-PC
Evaluation Board for the pPD78352 Family
6-v
CC78K3
C Compiler for the pPD78K3 Product Line
6-w
RA78K3
Relocatable Assembler Package for the
pPD78K3 Product Line
6-x
Development Tools
Selection Gu ide
K-Series
NEe
NEC Electronics Inc.
NEC provides a variety of development support tools to
enable effective program development and hardware
development for various microcontroliers. The development tools are used for efficient software assembly!
compilation or debugging.
A debugger can be used alone in a debugging system.
However, development time and cost can be reduced
by using symbolic debugging, which is made available
by connecting the debugger to a host machine.
NEC currently supports development environments
that use an IBM-PC compatible personal computer.
Development Procedure
~
~
~
~
DevelOpment
Tools
r~
r~
I
121
:g
i
'0
0!
1
1.5
I
I
I
I
I
1.._
IW
1'0
!~
:.5
I
I
1.._
.,
HardWare
I
I
I ..
I'"
Iii!
Software
I rl-==--'
Assembler
CCompller
1'0
:!
10
1.5
I
I
1(1
I
I
I
I
I
_.J
Host Machine
Emulator
IBM PC
Compatible
Screen Debugger
IE Control Program
EVAKIT Control Program
L=:;::=::;:=J
83RD-a6648
50618
•
NEe
Development Tools
Typical Development Environment (pPD78COOj
~PD78C11AGQ.36
Development Envtronment
IBM PC CompaUble
Assembler
Package
CCornpDer
IE Control
Program
[Emulallon System)
[Emulator]
IE·78C11·M
I-
[Target System)
Host Machine
IBM PC Compallble
2
ao........B(1C18O)
NEe
Development Tools
I'PD78COO Product Line Development Tools
Target Device
Package
~
In-Circuit
Emulator
~
IE-78C11-M
Conversion
Socket
~
/lPD78C10ACW
/lPD78C11 ACW
/lPD78C12ACW
/lPD78C14CW
/lPD78C17CW
/lPD78C18CW
/lPD78CP14CW
/lPD78CP14DW
/lPD78CP18CW
/lPD78CP18DW
64-pin SDIP
EV-9001-64
/lPD78C10AGQ36
/lPD78C11AGQ
/lPD78C12AGQ
/lPD78C14G36
/lPD78C17GQ
/lPD78C18GQ
/lPD78CP14GQ
/lPD78CP14R
/lPD78CP18GQ
64-pin QUIP
/lPD78C10AGF
/lPD78C11AGF
/lPD78C12AGF
/lPD78C14GF
/lPD78C14G-1B
/lPD78C17GF
/lPD78C18GF
/lPD78CP14GF
/lPD78CP18GF
64-pin QFP
/lPD78CP18KB
64-pin ceramic
LCC with window
EV-9200G-64
/lPD78C10AL
/lPD78C11 AL
/lPD78C12AL
/lPD78C14L
/lPD78CP14L
68-pin PLCC
AS-QIP-PCC-D78C1X
Software
Packages
[U]
RA87-D52
(Relocatable
assembler)
and
CCMSD-15DD-87
(C compiler)
Supplied
with IE
-
•
Note: The 64-pin QFP package conversion adapter is manufactured
by San Hayato Co., Ltd. The QUIP to PLCC adapter
("AS-QIP-PCC-D78C1X") is manufactured by Emulation
Technology.
3
I
NEe
Development Tools
TypiCIII Development Environment {pPD78/CO}
"PD78014GC Development Environment
IBM PC CompaUbIe
Assembler
Package
Screen
[Emulation System)
CCompler
Debugger
Host Machine
IBM PC CompaUble
[pROM Programmerj
PG-l500
[PROM Programmerj
83,.,..,.33. (1M1G)
4
NEe
Development Tools
I'PD78KO Product Line Development Tools
Package
In-circuit
Emulator
~
IX]
/lPD78001 CW
/lPD78002CW
64-pin SDIP
IE-78000-R
/lPD78001 GC
/lPD78002GC
64-pin QFP
EP-78240GC-R*
(option)
/lPD78011 CW
/lPD78012CW
/lPD78013CW
/lPD78014CW
/lPD78P014CW
/lPD78P014DW
64-pin SDIP
EP-78240CW-R
(option)
/lPD78011 GC
/lPD78012GC
/lPD78013GC
/lPD78014GC
/lPD78P014GC
64-pin QFP
EP-78240GC-R*
(option)
EV-9200GC-64
/lPD78042GF
/lPD78043GF
/lPD78044GF
/lPD78P044GF
/lPD78P044KL-S
BO-pin QFP
IE-78044-R-EM
(option)
EP-78130GF-R*
(option)
EV-9200G-80
/lPD78052GC
/lPD78053GC
/lPD78054GC
/lPD78P054GC
80-pin QFP
(14x 14 mm)
IE-78064-R-EM
(option)
EP-78230GC-R*
(option)
EV-9200GC-80
/lPD78062GC
/lPD78063GC
/lPD78064GC
/lPD78P064GC
100-pin QFP
(14x 14 mm)
EP-78064GC-R*
(option)
EP-9500GC-l00
/lPD78062GF
/lPD78063GF
/lPD78064GF
/lPD78P064GF
/lPD78P064KL-T
100-pin QFP
(14x20 mm)
EP-78064GF-R*
(option)
EV-9200GF-l00
Target Device
Emulation
Board
cu
IE-78014-R-EM
(option)
Emulation
Probe
D==O
EP-78240CW-R
(option)
Conversion
Socket
~
EV-9200GC-64
-
Software
Packages
OJ
RA78KO-D52
(Relocatable
Assembler)
and
CC78KO-D52
(C compiler)
and
CL78KO-D52
(C compiler
library)
and
SD78KO-D52
(Screen debugger)
and
(GUBED due
late 1993)
* Includes one required socket adapter shown at right.
5
NEe
Development Tools
Typical Development Environment (pPD7BK2)
",PD78234GJ DevelOpment Environment
IBM PC Coll1l&tlble
Assembler
Package
C CompIler
[EmulaUon System]
IEConlIOI
Program
Debugger
Emulation Probe
(Sold Separately)
I
o
Host Machine
IBM PC CompaUble
[pROM Programmer]
PG-l500
[PROM Programmer]
83RP-9634B (10193)
6
NEe
Development Tools
I'PD78K2 Product Line Development Tools
Target Device
Package
~
IlPD78212CW
IlP078213CW
IlP078214CW
IlPD76P214CW
IlPD76P214DW
IlPD78217ACW
IlPD78218ACW
IlPD76P218ACW
IlP078P218AOW
64-Pin SDIP
Design
Development
Board
Low-End
Emulator
In-Circuit
Emulator
D L§!11 IXJ
DOB-78K2-21X
-
IE-76240-R
(Old device)
or
IE-78240-R-A
(New device)
Conversion
Socket
£F:===[J
~
EP-76240CW-R
(option)
RA78K2-052
(Relocatable
Assembler)
and
IlPD76213L
IlPD76214L
IlPD76P214L
66-pin PLCC
EP-78240LP-R
(option)
IlPD78212GJ
IlPD76213GJ
IlPD76214GJ
IlPD76P214GJ
74-pin QFP
EP-76240GJ-R*
or
EP-78210GJ
EP-78240LP-R
EV-9200G-74
IlPD76212GC
IlPD78213GC
IlPD76214GC
IlPD76P214GC
IlPD76217AGC
IlPD78218AGC
64-pin QFP
EP-76240GC-R*
(option)
EV-9200GC-64
64-pin PLCC
JJPD76220GJ
JJP 076224GJ
IlPD76P224GJ
94-pin QFP
JJPD78233GC
JJPD78234GC
JJPD78237GC
IlPD78236GC
IlPD76P236GC
60-pin QFP
IlPD78233GJ
IlPD76234GJ
JJPD76237GJ
JJPD78238GJ
IlPD76P236GJ
JJPD76P236KF
94-pin QFP
EB-78210-PC
or
EB-78240-PC
ODB-76K2-22X
EB-76220-PC
or
EB-78230-PC
ODB-78K2-23X
EB-76230-PC
EP-78240GQ-R
(option)
-
64-pin QUIP
-
[OJ
CL78K2-D52
(C library)
and
-
-
Software
Packages
CC78K2-052
(C compiler)
and
IlPD78213GQ
IlPD78214GQ
IlPD78P214GQ
IlPD78220L
IlPD76224L
IlPD76P224L
DOB-78K2-21X
EB-78210-PC
or
EB-78240-PC
Emulation
Probe
IE-76230-R
(Old devloe)
or
IE-78230-R-A
(New devioe)
EP-76230LO-R
(option)
Avocet Tool
chain from
Avocet Systems,
Inc.
(207) 236-9055
(800) 448-8500
Consists of:
~s~~~~il~:"
debugger,
simulator.
-
EP-76230GJ-R*
or EP-78220GJ
EP-76230LQ-R
EV-9200G-94
EP-76230GC-R*
(option)
EV -9200GC-60
EP-78230GJ-R*
(option)
EV-9200G-94
* Includes one required socket adapter shown at right.
7
NEe
Development Tools
"PD78K2 Product Line Development Tools (cont)
Target Device
Package
Design
Development
Board
Low-End
Emulator
~ D Ull
IlPD78233LQ
IlPD78234LQ
IlPD78237LQ
IlPD78238LQ
IlPD78P238LQ
84·pin PLCC
IlPD78243CW
IlPD78244CW
64-pin SDIP
IlPD78243GC
IlPD78244GC
64-pin QFP
DDB·78K2·23X
-
EB-78230·PC
EB-78240-PC
* Includes one required socket adapter shown at right.
8
In·Clrcuit
Emulator
Emulation
Probe
~
D==O
IE·78230·R
(Old device)
or
IE·78230·R·A
(New device)
Ep·78230LQ·R
(option)
IE-78240-R
(Old device)
or
IE-78240-R-A
(New device)
EP-78240CW-R
(option)
Conversion
Socket
~
-
Software
Packages
[OJ
CC78K2·D52
(C compiler)
and
CL78K2-D52
(C library)
and
EP-78240GC-R*
(option)
-
EV-9200GC-64
RA78K2-D52
(Relocatable
Assembler)
and
Avocet Tool
chain from
Avocet Systems,
Inc.
(207) 236-9055
(800) 448-8500
Consists of:
C compiler,
assembler,
debugger,
simulator.
NEe
Development Tools
Typical Development Environment (pPD78K3)
~PD78352GC Development EnvIronment
IBM PC CompaUble
Assembler
Package
[Emulation System]
IE Control
Program
CCompller
[Emulator]IE-78350-R
uuu
D
o
Host MachIne
IBM PC CompaUble
Emulation Probe
(Sold Separately)
I
[Programmer Adapter]
PA-78P352GC
PA-78P352KK _
[pROM Programmer]
PG-1500
[PROM Programmer]
83RD-9636B (10193)
9
NEe
Development Tools
"PD78K3 Product Line Development Tools
Target Device
Package
~
Evaluation
Board
In-Circuit
Emulator
cu IV
DDK-78310A
0===={]
~
-
64-pin SDiP
IlPD7B310AGQ
IlPD7B312AGQ
IlPD78P312AGQ
IlPD7BP312AR
64-pin QUIP
IlPD78310AGF
IlPD78312AGF
IlPD78P312AGF
64-pin QFP
EP-78310GF*
(option)
IlPD7B310AL
IlPD7B312AL
IlPD78P312AL
68-pin PLCC
EP-78310L
(option)
IlPD78320GJ
IlPD78322GJ
IlPD78P322GJ
IlPD78P322KD
74-pin QFP
IlPD7B320L
IlPD7B322L
IlPD78P322KC
IlPD78P322L
68-pin PLCC
EP-78320L-R
(option)
IlPD7B322GF
IlPD78P322GF
IlPD78P322K
SO-pin QFP
EP-78320GF-R*
(option)
EV-9200G-80
IlPD78327GF
IlPD78328GF
IlPD78P328GF
64-pin QFP
EP-78327GF-R*
(option)
EV-9200G-64
IlPD7B327CW
IlPD7B328CW
IlPD78P328DW
64-pin SDIP
IlPD78330LQ
IlPD78334LQ
IlPD78P334LQ
B4-pin PLCC
IlPD78330GJ
IlPD78334GJ
IlPD78P334GJ
IlPD78P334KE
94-pin QFP
EB-78327-PC
IE-78327-R
EP-7B320GJ-R*
(option)
EP-78327CW-R
(option)
EB-78330-PC
* Includes one required socket adapter shown at right.
10
IE-78327-R
EP-78310GQ
Supplied
with IE
Conversion
Socket
IlPD78310ACW
IlPD78312ACW
IlPD78P312ACW
IlPD78P312ADW
EB-78320-PC
IE-78310A-R
Emulation
Probe
IE-78330-R
EP-78330LQ-R
(option)
EP-7B330GJ-R*
(option)
EV-9200G-64
EV-9200G-74
-
EV-9200G-94
Software
Packages
[0]
CC78K3-D52
(C compiler)
and
RA78K3-D52
(Relocatable
Assembler)
and
GUBED
(New Graphical
Users binary
evaluation
display)
due end 1993
NEe
Development Tools
"PD78K3 Product Line Development Tools (cant)
Target Device
Package
~
JlPD78350GC
JlPD78352G-22
JlPD78P352G-22
JlPD78P352KK
64·pin OFP
JlPD78355GC
JlPD78356GC
JlPD78P356GC
100-pln OFP
JlPD78P356KP-S
l20-pin LCC
Evaluation
Board
In·Clrcult
Emulator
cu nJ
EB·78350·PC
Emulation
Probe
O===[J
Conversion
Socket
~
IE·78350·R
IE-78350 -R-EMl
Ep·78240GC-R*
(option)
EV-9200GC-64
IE-78350-R
IE-78355-R-EMl
EP-78355GC-R*
(option)
EV-9500GC-l00
-
EV-9500GC-l00
EV-9501 GC-100
Software
Packages
[OJ
CC78K3-D52
(C compiler)
and
RA78K3-D52
(Relocatable
Assembler)
and
GUBED
(New Graphical
Users binary
evaluation
display)
due end 1993
* Includes one required socket adapter shown at right.
11
NEe
Development Tools
PROM Programmers (K-Series)
Target PROM
~
Programmer Adapter
~
JlPD78P014CW
JlPD78P014DW
PA-78P014CW
JlPD78P014GC
PA-78P014GC
JlPD78P044GF
PA-78P044GF
JlPD78P044KL-S
PA-78P044KL-S
JlPD78P054GC
PA-78P054GC
JlPD78P054GK
JlPD78P054KK-S
JlPD78P064GC
JlPD78P064GF
PA-78P054GK
PA-78P054KK-S
PA-78P064GC
PA-78P064GF
JlPD78P064KL-T
PA-78P064KL-T
JlPD78P214CW/DW
JlPD78P218CW
JlPD78P218ADW
PA-78P214CW
JlPD78P214GC
PA-78P214GC
JlPD78P214GJ
PA-78P214GJ
JlPD78P214GQ
PA-78P214GQ
JlPD78P214L
PA-78P214L
JlPD78P224GJ
PA-78P224GJ
JlPD78P224L
PA-78P224L
JlPD78P238GC
PA-78P238GC
JlPD78P238GJ
PA-78P238GJ
JlPD78P238KF
PA-78P238KF
JlPD78P238LQ
PA-78P238LQ
JlPD78P312ACW
JlPD78P312ADW
PA-78P312CW
JlPD78P312AR
JlPD78P312AGQ
PA-78P312GQ
JlPD78P312AL
JlPD78P312AGF
JlPD78P322L
JlPD78P322GJ
PA-78P312L
PA-78P312GF
PA-78P322L
PA-78P322GJ
JlPD78P322GF
PA-78P322GF
JlPD78P322KC
PA-78P322KC
JlPD78P322KD
PA-78P322KD
JlPD78P324LP
PA-78P324LP
12
PROM Programmer
PG-1500
NEe
Development Tools
PROM Programmers (K-Series) (cant)
Target PROM
~
Programmer Adapter
~
IlPD78P324KC
PA·78P324KC
IlPD78P328GF
PA·78P328GF
IlPD78P334LQ
PA·78P334LQ
IlPD78P334GJ
PA·78P334GJ
IlPD78P334KE
PA·78P334KE
IlPD78P334KF
PA·78P334KF
IlPD78P352GC
PA·78P352GC
IlPD78P352KK
PA·78P352KG
IlPD78P356GC
PA·78P356GC
IlPD78P356KP·S
PA·78P356KP
PROM Programmer
•
PG·1500
PROM Programmers C#£PD78COO)
Target PROM
Programmer Adapter
PROM Programmer
IlPD78CP14CW
IlPD78CP14DW
IlPD78CP18CW
IlPD78CP18DW
PA·78CP14CW
PG·1500
IlPD78CP14R
IlPD78CP14GQ
IlPD78CP18GQ
PA·78CP14GQ
IlPD78CP14GF
IlPD78CP18GF
PA·78CP14GF
IlPD78CP14L
IlPD78CP18KB
..
PA·78CP14L
PA·78CP14KB
13
Development Tools
14
NEe
NEe
NEC Electronics Inc.
ROM Code Submission Guide
September 1993
Introduction
Minimum Requirements
This guide provides direction for submitting the data
files used by NEC to program semicustomized integrated circuits (a complete list of which appears in
table 3).
Anyone of the means described may be selected, but
NEC requires multiple copies of every file, as well as
device-specific information such as chip type, package
type, and package lead type.
Where to Send Files
D
A minimum of two copies of the chosen media
must be submitted. Three copies are preferred, as
this lessens the problems caused when one copy
is flawed. Please note that for modem transfers,
the file must be transmitted twice* to NEC and
transmitted once from NEC back to you.
D
Unless submitted by means of programmable ICs,
data files must be in Intel T• hexadecimal or
extended hexadecimal format.
D
Source code or the .executable binary of a data file
may be submitted but is not required.
D
Files taken from or read from previously built ICs,
even those produced for you by NEC, will not be
accepted.
Data files should be sent directly to Micro SBU, Customer Marketing, NEC Electronics, Mountain View, California, 94039.
Acceptable Media
NEC accepts data from the following:
D
D
In programmable ICs such as NEC's pPD27C2000
UV EPROM or pPD75P308 programmable 4-bit
microprocessor
On floppy diskette in MS-DOS® or PC DOST.
formats
- 5-1/4 inch disk (either 360K or 1.2 Mbyte)
- 3-1/2 inch disk (either 360K, 720K or 1.44 Mbyte)
D
Via modem over the telephone lines
- At 300 to 14,400 bps
- With 8 data bits, no parity, 1 stop bit
- Using XMODEM, YMODEM or KERMIT protocol
D
Via InterNet at shin @ asic.mtv.nec.com
D
When opting for modem transmittal, call Customer
Marketing for the appropriate engineering contact,
dial-up number, and hours of availability.
MS-DOS is a registered trademark of Microsoft.
PC DOS is a trademark of International Business Machines Corp.
Intel is a trademark of Intel.
*This will ensure that NEC has two copies for file compari son at the
NEC site, and that you will be able to perform a file comparison.
50628
Taking Precautions
NEC assumes no responsibility for data bits within a
target device's programmable area, and it is therefore
imperative that you define all bits within the possible
range of addresses. For example, if the programmable
area is 128K x 8 bits, and your data file defines only the
first 64K x 8 bits, there is no way for NEC to know how
to program the remaining 64K.
Furthermore, if your programming equipment was left
with random data in its memory from a previous operation, valid data would be built into the first half of the
programmable area and garbage data into the second
half-causing unforeseen and possibly very expensive
problems in the final design. Blank space must be
defined as either all Os or all 1s, or as binary NOP, in
which case the binary code for an NOP instruction
needs to be specified.
~.
~
'
NEe
ROM Code Submission Guide
What You Can Expect from NEC
Peculiar Addressing
After the media or devices have been received by NEC,
the copies will be compared to ensure they match
(customers whose files don't match will be contacted
by Customer Marketing). NEC will then duplicate the
media and return the following for verification:
Although addresses are usually contiguous, e.g., from
000016 to a maximum, these devices require special
consideration.
o One copy of the original media
o One copy of NEC's duplicate media
o A hard copy listing of the data files (for target.
devices with less than 5i2K, i.e., 64K x 8, of ROM)
ROMs with 16-Bit Data Buses. Data submitted for
these ROMs in devices with 8-bit data buses should be
organized this way.
Table ,_ Sequence for 8-Bit Data Bus Devices
Sequence
Addresses
Outputs
o Two floppy diskettes containing those data files
transmitted via modem, or InterNet
Device #1
00000 - OFFFF .
Device #2
10000 - 1 FFFF
Oo-~
o A ROM Code Verification Form, which must be
signed and returned before any devices can be
built
Device #3
00000 - OFFFF
0 8 -015
Device. #4
10000 -1FFFF
08- 0 15
upon receipt of the signed verification form, NEC will
produce ten engineering samples for testing and approval prior to building and shipping the entire order.
Data files are kept in archival storage for two years
(more than two years is not guaranteed) in one or more
of the following formats:
o In one originallC and one NEC duplicate IC, if
programmable ICs were initially submitted
o In a hard-copy listing of the hexadecimal file
o In electronic storage using either magnetic or
optical media (Write Once Read Many, i.e., WORM,
disk)
Please note that IC masks will be stored at NEC's
manufacturing facility for only one year after the last
order is received.
2
00- 0 7
Data submitted from a i6-bit data bus device would be
handled simiiarly.
Table 2. Sequence for 16-Bit Data Bus Del/ices
Sequence
Addresses
Device #1
00000 - OFFFF
Outputs
10000 - 1FFFF
In both cases, segments corresponding to the lower
data outputs are submitted first, a pattern that should
be followed for larger devices as well. Please be aware
that NEC has no way of identifying the sequential order
of individual segments if they're submitted in incorrect
order.
NEe
ROM Code Submission Guide
Using The Intel Hexadecimal Format
Table 3_ Applicable Device Types
Part Number(s)
Organization
Last Address
pPD78_C_11_A___________4_'0_96
__
X_8_b_it_s__________0_FF_F~1~6__
C12A
8,192 x 8 bits
1FFF16
C14
16,384 x 8 bits
3FFF16
C14A
16,384 x 8 bits
3FFF 16
C18
32,768 x 8 bits
7FFF16
pPD78_00_1____________8_,1_92__
x_8_b_it_s__________1_FF_F~1~6__
002
16,384 x 8 bits
16,384 x 8 bits
3FFF16
pPD78_01_1____________8_,1_92__
x_8_b_it_s__________1_FF_F~1_6__
012
16,384 x 8 bits
3FFF 16
013
24,576 x 8 bits
5FFF16
014
32,768 x 8 bits
7FFF16
pPD78_01_1_Y___________8~,1_92
__
X_8_b_it_s__________1_FF_F~1~6__
012Y
16,384 x 8 bits
24,576 x 8 bits
5FFF16
014Y
32,768 x 8 bits
7FFF16
pPD78042
16,384 x 8 bits
3FFF16
----------------------------~-043
24,576 x 8 bits
5FFF16
32,768 x 8 bits
o A colon to begin each line
o A two-character data word count for the line
o A four-character address of the first word of data
o A two-character record type identifier, e.g., 00, 01,
02 for data, end of file, segment address
o The data words
o A two-character line checksum at the end of each
line
3FFF16
013Y
044
Each byte of data must be expressed as a printable
ASCII character, and each line must contain these
elements:
3FFF16
pPD78_00_1_Y___________8_,1_92__
x_8_b_it_s__________1_FF_F~1~6__
002Y
Intel's hexadecimal format allows addressing of up to
512 kbits of data, or 64K x 8 bits (000016 through
FFFF16)' Data records larger than 64K x 8 must be
expressed in multiple segments, with each individually
addressed segment equal to or smaller than 64K x 8.
7FFF16
pPD78_05_2____________
16~,3_8_4_X_8_b_it_s__________3_FF_F~1~6__
053
24,576 x 8 bits
5FFF 16
054
32,768 x 8 bits
7FFF16
pPD78_06_2____________
16_,3_8_4_x_8_b_it_s__________3_F_FF~1~6__
For example, a line showing the "End of File" record
would be formatted as :00OOO001FF, while a typical
data line would be constructed this way:
:WWAAAATTDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDCC
Table 4_. Description of Elements
Code
Description
WW
Data word count
Beginning of line
AAAA
Address of the first data word
063
24,576 x 8 bits
5FFF16
TT
Record type
064
32,768 x 8 bits
7FFF16
0 ... 0
Data words
CC
Checksum
pPD78212
8,192 x 8 bits
1FFF16
----------------------------~-214
16,384 x 8 bits
3FFF16
pPD78218A
32,768 x 8 bits
7FFF16
pPD78224
16,384 x 8 bits
3FFF16
pPD78_23_4____________
16_,3_8_4_x_8_b_it_s__________3_F_FF~1~6__
_Ta_b_"_e_5.___D_'B_S_c_rl.:."_t_io_n_of_R_BCO_rtl_1i-'yp"'-e______ •
TT
Descr i ptlon
00
Data follows
32,768 x 8 bits
7FFF16
01
End of file
pPD78312A
8,192 x 8 bits
1FFF16
02
Begin new 64K x 8 data segment
pPD78322
16,384 x 8 bits
3FFF16
pPD78352A
32,768 x 8 bits
7FFF16
pPD78356
49,152 x 8 bits
BFFF16
238
Table 6 shows an address shift from one 32K x 8
segment to the next segment in hexadecimal format.
3
NEe
ROM Code Submission Guide
Table 6.
Sample Hexadecimal Addressing
Coded Segment
Instruction
:1oo000007F7F7F7F7F7F7E7D7B797878787 A 7 D2C
Begin first segment
:10FFFOooFFFFFFFFFFFFFFFFFFFFFFFFFFFFF11
End first segment
:020000021000EC
Second segment record
:100000007F7F7F7F7F7E7E7D7B7A797877797B7F2C
Begin second segment
:10FFFOOOFFFFFFFFFFFFFFFFFFFFFFFFFFFFF11
End second segment
:00000001 FF
End of file record
4
NEe
NEC Electronics Inc.
PG·1500
PROM Programmer
September 1993
Description
The PG-1500 series is a stand-alone PROM programmer
for programming 256-kilobit to 1-megabit PROMs and
PROM/OTP devices for NEC's 4/8/16-bit single-chip microcontroilers and digital signal processors. The system consists of the PG-1500 base programmer, two
interchangeable programmer adapter modules, and a
variety of programmer adapters to support the individual devices and package types. The PG-1500 can be
controiled directly from either a remote terminal or host
computer via an RS-232-C serial port or directly from
the on-board keypad in stand-alone mode.
Features
o Interchangeable modules for programming:
-256-kilobit to 1-megabit PROMs
- NEC pPD75xx and pPD75XXX 4-bit
microcontroilers
- NEC K-series® microcontroilers
- NEC V-series T" microcontroilers
- NEC pPD77xxX digital signal processors
o 512K-bytes data RAM
o Memory edit function to change/confirm PG-1500
buffer
o Address/data/message display LCD
o RS-232-C serial interface
o Centronics compatible parallel interface
o Power-on diagnostics
o Supports three data transfer formats
-Intel Extended Hex (Note 1)
- Extended Tektronix Hex (Note 2)
- Motorola S (Note 3)
o Two modes of operation
- Remote controlled
- Stand-alone
o Host Controller Program for IBM PC® Series
IBM PC is a registered trademark of International Business Machines
Corporation.
V-Series and V40 are trademarks of NEC Electronics, Inc.
K-series is a registered trademark of NEC Electronics, Inc.
Notes:
(1) Developed by Intel Corporation.
o Silicon signature read function
(2) Developed by Tektronix Corporation.
o PROM insertion error detection circuitry
(3) Developed by Motorola Incorporated
PG·1500 Series
50117-2
NEe
PG·1500 Series
Figure 1. PG-1500 System Block Diagram
Programmer Adapters
Programmer Adapter Modules
PG·1500
Base Programmer
L _______ _
-------'
83ML-693611 (9193)
Architecture
Operation
The PG-1500 base unit contains an NEC pPD70208
(V40"') microprocessor with 128K bytes of monitor
ROM, 32K bytes of working RAM, 512K bytes of data
memory, an RS-232-C serial port, a Centronics compatible parallel interface, an LCD display, and a 23-key
keypad. Figure 1 shows a block diagram of the PG-1500.
The PG-1500 operates in stand-alone mode from the
on-board keypad, or in remote-control mode from an
external terminal or a host computer via an RS-232-C
serial port.
The PG-1500 has two interchangeable programmer
adapter modules. These adapter modules plug directly
into the top of the PG-1500 and can accept a wide
variety of programmer socket adapters to support
NEC's devices. Refer to the Development Tool Selection
Guide for a list of all available adapters.
The PC-1500 can be controlled from an IBM PC series
host computer using the PG-1500 controller program.
The controller program has three modes of operation:
control mode, auto mode, and terminal mode.
2
Host Controller Program
NEe
PG·1500 Series
Silicon Signature
Equipment Supplied
A silicon signature is stored in all NEC devices and
contains information on the device type, start and stop
addresses, and programming voltages. The PG-1500
can read the silicon signature of the particular device
being programmed either manually or automatically,
or the device code can be entered manually.
The PG-1500 package includes the following:
Basic Specifications
• Power requirements:
- 90 to 250 VAC, 50 to 60 Hz
• Environment conditions:
- Operating temperature range: 10 to 35°C
- Operating humidity range: 20 to 80% relative
humidity
• RS-232-C serial port:
- Baud rates: 1200, 2400, 4800, 9600, 19200
- Parity: none, even, odd
-X-ON/X-OFF: on, off
- Bit configuration: 7, 8
-Stop bits: 1,2
• PG-1500 PROM programmer base unit
• 027A socket board for 27xxx PROMS and
pPD27C256A-like devices
• 04A interface board for NEC pPD75xx/pPD75xxx
microcontrollers
• PG-1500 controller program disk for IBM PC
• Power cord
• Power ground plug adapter
• Spare fuses (2)
Documentation
For further information on the operation of the PG1500, NEC provides the following documentation:
• PG-1500 PROM Programmer User's Manual
• PG-1500 Controller User's Manual
(IBM PC-based)
3
PG-1500 Series
4
NEe
IE·78C11·M
In·Circuit Emulator
for the pPD78COO Product Line
NEe
NEC Electronics Inc.
September 1993
Description
The IE-78C11-M is an in-circuit emulator providing both
hardware emulation and software debugging capabilities for the NEC pPD78COO product line of 8-bit, singlechip microcontrollers. Real-time and single-step emulation, coupled with sophisticated memory mapping
features, breakpoints, and trace capabilities, create a
powerful debugging environment. A line assembler
and disassembler, full register and memory control,
and complete upload/download capabilities simplify
the task of debugging hardware and software. The
IE-78C11-M is designed to operate as a stand-alone,
in-circuit emulator controlled from either a user terminal or a host computer system.
Features
D
Real-time and single-step emulation
D
User-specified breakpoints:
Logical OR of up to four sets of break conditions
Opcode fetch count
External sense clips condition
Emulation time
Logical AND of addresses, data values,
CPU controls, and number of loops
D
Sophisticated trace capabilities
-Instruction or machine cycle display
- 1,024 trace frames
- Address, control, data, and port trace
IE-78C11-M In-Circuit Emulator
50350
D
Powerful memory mapping: 64K bytes of RAM
mappable in 256-byte blocks
D
Line assembler/disassembler
D
Operating state LED indicators
D
CMOS latch-up warning and protection
D
Eight external sense probes
D
Self-diagnostic command
D
Stand-alone configuration
- User terminal controlled
- Host computer system controlled
D
IE78C11 controller program for IBM PC@, PC/XT@,
PC/AT@, or compatibles
- Symbolic debugging
- Autoexecution of commands
-On-line help facility
- Debug session logging
Ordering Information
Part Number
Description
IE-78C11-M
In-circuit emulator for !'PD78C1x/C1xA series
EP-7811 HGQ
Emulator probe for 64-pin QUIP package
(shipped with IE-78C11)
EV-9001-64
Optional emulator probe adapter for 64-pin
shrink DIP package (used with EP-7811 HGQ)
EV-9200G-64
64-pin lCC socket used with the
!,PD78CP18KB
A5-QIP-PCC-D781X
Optional QUIP to PlCC adapter (used with
EP-7811HGQ)
IBM PC, PCIXT, and PC/AT are registered trademarks of International
Business Machines Corporation.
..
IE-78C11-M
2
NEe
NEe
NEC Electronics Inc.
CC87
Micro-Series
C Compiler Package for the
IIPD78COO Product Line
September 1993
Description
C Library Functions
The CCB.7 Micro-Series"" C compiler package for the
NEC pPD7BCOO product line of microcontrollers consists of an ANSI C cross-compiler, relocatable macro
assembler, linker, and librarian. Developed by IAR systems in Sweden for NEC, the Micro-Series C compiler
package runs on an MS-DOS® system with a freestanding system as target (embedded system).
The CCB7 Micro-Series C compiler package includes
most of the important C library functions that apply to
PROM-based embedded systems. All library functions
reside in the supplied library files. Header files that
declare the set of library functions are also included.
Ordering Information
Part Number
System
Description
CCMSD-15DD-87
MS-DOS
5-1/4-inch double-density floppy
diskette
Features
o ANSI standard C
- Const, volatile, signed, void, enum keywords
- Function prototyping
- Hex string constants
- Structure and union assignments
o Optimization for code size or execution speed
o Extended functions for pPD78COO product line
code generation
- Saddr area usage for variables
- Non-initialized variable declaration
- Interrupt vector table generation
- Function execution with interrupts disabled
-Input byte/word from special register
- Output byte/word to special register
- Modify special register with a byte constant
- Disable/enable interrupts
-Halt CPU
- Check/reset interrupt flags
The following library functions are available:
CHARACTER HANDLING < ctype.h>
isalnum isalpha iscntrl isdigit islower
isprint ispunct
isspace isupper isxdigit to lower toupper
VARIABLE ARGUMENTS < stdarg.h>
va_arg va_end va_start
NON-LOGICAL JUMPS < setjmp.h>
longjmp setjmp
FORMATTED INPUT/OUTPUT < stdio.h>
getchar gets printf putchar scanf, sscanf, sprintf
GENERAL UTILITIES < stdlib.h>
atof atoi atol calloc exit free malloc ralloc
STRING HANDLING < string.h>
strcat strcmp strcpy strlen strncat strncmp strncpy
MATHEMATICS < math.h>
atan atan2 cos exp log log10 modf pow sin sqrt tan
LOW-LEVEL ROUTINES < icclbutl.h>
Jormatted_write
Memory Allocation
o ROMabie object file creation
The two memory allocation modes, static and reentrant, differ only in allocation of auto variables. In the
reentrant mode, all local auto variables are allocated
and deallocated dynamically; the auto variables reside
on the staCk, which is necessary if recursive or reentrant functions are needed. This option sometimes
generates more code and slower code than the static
mode. In the static mode, all function level variables are
put into static memory, with the exception of function
arguments, which are always placed on the stack.
o Generation of list and full cross-reference files
C Cross-Compiler (ICC7800)
o IEEE 32-bit floating-point data representation
o UNIX LINT functions (legal C code verification)
integrated into the compiler
o Interface checking between modules performed by
the linker XLiNK
o Built-in help facility
o Extensive error reporting
Micro-Series is a trademark of IAR Systems AB.
MS-DOS is a registered trademark of Microsoft Corporation.
50622
The C cross-compiler, which is the ICC7800 program,
converts standard C source code into relocatable object modules in the IAR systems' proprietary universal
binary relocatable object format (UBROF). This format
is used for all relocatable object files in the Micro-
•
NEe
CC87
Series development system, whether generated by an
assembler or compiler. During compilation, an optional
optimizer can be invoked to optimize the object code
for size or execution speed.
In addition, CC87 supports extended functions for
pPD78COO product line code generation. These extended functions allow the C compiler to take advantage of many of the powerful features in the pPD78COO
product line microcontrollers to decrease object code
size and improve program execution speed.
Relocatable Macro Assembler (A7800)
The relocatable macro asSembler (A7800) translates
symbolic source code for the NEC pPD78COO product
line of microcontrollers into relocatable object modules in the IAR systems proprietary UBROF format.
Features. The relocatable macro assembler features
are as follows:
• Absolute or relocatable address object code output
• Directives
- List formatting
- Conditional assembly, separate assembly
- Memory allocation
- Macro definition and value assignments to
symbol directives
• Generation of list files
• Generation of cross-reference and symbol tables
• Ability to include files in another source
Directives. Assembler directives give instructions to
the program but are not translated into machine code
during assembly. Basic directives include those for
storage definition and memory allocation (DB, DD, DW,
DS); symbol control and usability (PUBLIC, EXTERN,
LOCSYM); and value assignments to symbols (SET,
EQU, = , DEFINE).
Program control directives include those for module
definition (NAME, MODULE, ENDMOD); segment definition and control (ASEG, RSEG, STACK, COMMON,
ORG); conditional assembly (IF, ELSE, ENDIF); macro
processing (MACRO, ENDMAC); and listings control
(LSTOUT, LSTCND, LSTCOD, LSTEXP, LSTMAC,
LSTWID, LSTFOR, LSTPAG, PAGSIZ, PAGE, TITL, STITL,
PTITL, PSTlTL, LSTXRF).
2
Linker (XLiN K)
The universal linker, XLlNK, combines relocatable object modules and absolute load modules and produces
one absolute load module. The controls for XLiNK may
be specified either on the command line or in a parameter file. In addition to being able to generate several
types of absolute load module formats, it is also possible to generate cross-reference lists with an index list;
define segment allocation; force load and conditional
load of files; bank segments; and define a symbol on a
command line. The absolute load module can contain
symbol information as well as absolute object code.
Librarian (XLIB)
The XLiB librarian creates and maintains files containing relocatable object modules. With XLlB, the user can
merge object files from different assemblies/
compilations in order to create libraries; delete individual modules; change the order of modules and check
the CRC in a module; and rename modules, segments,
externals or entries. In addition, XLiB can change the
properties of a module to be conditionally or unconditionally loaded. Use of XLiB reduces the number of files
that need to be linked together by allowing several
modules to be kept in a single file, providing an easy
way to link frequently used modules into programs.
License Agreement
CC87 Micro-Series C Compiler package is sold under
terms of a license agreement included with the compiler. The accompanying card must be completed and
returned to NEC Electronics Inc. to register the license.
Documentation
For further information on source program format,
compiler operation, assembler operation, linker, librarian, and converter programs, and actual program examples, refer to the following manual supplied with the
CC87 package. Additional copies may be obtained
from NEC Electronics Inc.
• CC87 pPD7800 Series C Compiler, User's Manual
NEe
NEC Electronics Inc.
RA87
Relocatable Assembler Package
for the pPD78COO Product Line
September 1993
Description
Ordering Information
The RA87 relocatable assembler package converts
symbolic source code for the ~P078COO product line of
microcontrollers into executable absolute address object code. The RA87 package consists of six separate
programs: assembler (RA87), linker (LK87) , hexadecimal format object converter (OC87). librarian (LB87),
list converter (LCNV87), and macroprocessor (MP).
Part Number
System
Description
RA87-D52
MS-DOS
5-1/4-inch. double-density
floppy diskette
RA87 translates a symbolic source module into a relocatable object module. The assembler verifies that
each instruction assembled is valid for the target microcontroller specified at assembly time.
LK87 combines relocatable object modules and absolute load modules and converts them into an absolute
load module. OC87 converts an absolute object module or an absolute load module into an ASCII hexadecimal format object file.
LB87 allows commonly used relocatable object modules to be stored in one file and linked into multiple
programs, greatly increasing programming efficiency.
When a library file is included in the input to the linker,
the linker extracts only those modules required to
resolve external references from the file and relocates
and links them into the absolute load module.
LCNV87 allows relocatable list files to be converted
into absolute list files. MP expands macros contained
in a source program prior to assembling.
Features
o Absolute address object code output
o Generic jump capability
o User-selectable and directable output files
o Extensive error reporting
o Macro capabilities
o Runs under MS-OOS@ operating system
MS-DOS is a registered trademark of Microsoft Corporation.
50252·1
Program Syntax
An RA87 source module consists of a series of code,
byte-oriented data, or bit-oriented data segments.
Each segment consists of statements composed of up
to four fields: symbol, mnemonic, operand, comment.
The symbol field may contain a label whose value is the
instruction or data address or a name that represents
an instruction address, data address, or constant. The
mnemonic field may contain an instruction or an assembler directive. The operand field contains the data
or expression for the specified instruction or directive.
The comment field allows explanatory comments to be
added to a program.
Character constants are translated into 7-bit ASCII
codes. Numeric constants may be specified as binary,
octal, decimal, or hexadecimal. Arithmetic expressions
may include the operators +, -, *, /, NOT, AND, OR,
XOR, EO, NE, GT, GE, LT, LE, SHR, SHL, HIGH byte, LOW
byte, MOD, and the - sign.
Assembler Directives
Assembler directives give instructions to the assembler but are not translated into machine code during
assembly. Basic assembler directives include storage
definition (DB, Ow, OS, DBI1); symbol definition (EOU, . .
SET, CODE, DATA, BI1); and program boundary defini- . . . .
tion (ORG, END). Program linkage directives are provided to NAME the module and to declare symbols as
PUBLIC or external (EXTRN).
Segment definition directives define whether a segment is a code segment (CSEG), allocated to ROM; a
data segment (DSEG) or a bit segment (BSEG), allocated to RAM; or a working register segment (VREG).
The address boundary conditions for each segment
directive are specified in its operand. These include
UNIT, PAGE, INPAGE, FIXEDAREA, BYTE, CALLTABLE,
AT, BITADDRESSABLE. The combination types of PUBLIC, COMMON, and COMPLETE specified in the operand define how to link segments with the same name
and segment definition.
NEe
RA87
The pPD78COO product line instruction set contains
three jump instructions with varying legal address
ranges. To avoid calculating which jump instruction to
use, the programmer can substitute the generic jump
(GJMP) directive for any relative jump (JR) , any extended relative jump (JRE), or any long jump (JMP)
instruction in the source program. During assembly, a
suitable jump instruction is chosen for each GJMP
directive.
The object file contains the relocatable object module.
The format of this module is an NEC proprietary relocatable object module format. ThiS object file may also
contain local symbol information for the symbolic
debugger.
Assembler Controls
Linker
The RA87 assembler (figure 1) has two types of controls. The primary controls, which are specified in the
assembler command line, a parameter file, or at the
beginning of the source module, are as follows:
The LK87 linker (figure 2) combines several reloc~tabl.e
object modules or absolute load modules, resolving
PUBLIC/EXTRN references between modules, to create
an absolute load module. This load module contains
both absolute object code and symbol information.
The linker will also search library files for required
modules to resolve external references. The linker controls for LK87 can be specified in either the command
iine or in a parameter file. The programmer can specify
the date, module name, stack size and starting address, ROM/RAM segment allocation, starting address
and order for code/data/bit relocatable segments, and
the page address for the working register group. The
programmer may also specify that a list file containing
a link map, a: local symbol table, or a public symbol
table be created.
•
•
•
•
Target microcomputer specification
Output file selection and destination
Listing format controls
Date specification
Figure 1. Relocatable Assembler Functional
Diagram
Source
Module
File
I=~
InclUde
Rle
fined symbols in alphabetical order, their types, attributes, and the values initially assigned to them. The
cross-reference table contains all defined symbols and
the numbers of all statements that refer to them.
Figure
J
RA87
7800 Series
Relocatable
Assembler
2:
Linker Functional Diagram
Temporary
Wor1,
and PC/AT® under MS-DOS and is provided with the
in-circuit emulator at no extra charge.
4
IBM PC, PC/XT, and PC/AT are registered trademarks of International
Business Machines Corporation.
NEe
NEG Electronics Inc.
IE-78000-R
In-Circuit Emulator
for the IIPD78KO Product Line
September 1993
Description
The IE-7S000-R is an in-circuit emulator providing both
hardware emulation and software debugging capabilities for the NEC pPD7SKO product line of single-chip
microcontrollers. The IE-7S000-R, combined with a
SD7SKO screen debugger and IE-78000-R-BK break
board, create a powerful debug environment.
The SD7SKO is screen debugger software included in
an IE-7S000-R package that will allow the user to debug
a program through a host machine (IBM PC/lBM compatible) in a window-oriented environment. This screen
debugger software is used by connecting it to the
IE-7S000-R.
Different target devices can be emulated by connecting a separately purchased emulation board,
IE-78Oxx-R-EM to the IE-7S000-R . The product selection
guide shows the list of available emulation boards,
emulation probes, socket adapters, and corresponding
target devices.
Features
o 10-MHz maximum operating frequency
o Real-time and non-real-time emulation
o Sophisticated break events
- Logical OR of up to four sets of events
- Logical AND of addresses, data values, CPU
controls, and loop count
- Executed instruction count
- Parallel or sequential fetch addresses
- External sense clip condition
o Sophisticated trace capabilities
- Trace program fetch or data access
- 2K x 49-bit trace buffer
- Address, control, data, and external signal trace
-Instruction or frame display
- Trace search capability
-Specify trigger point at beginning, middle, or
end of trace buffer
50613
o Supports debug activities during real-time
emulation
- Displays trace buffer
- Modifies trace conditions
- Modifies trace event conditions
- Restarts trace
o Powerful memory mapping
- 64K bytes of RAM for off-chip RAM/ROM
emulation
-200K bytes DRAM memory for symbols (192K
byte) and programs (SK byte)
- 56K bytes ROM
-4K bytes of RAM for internal RAM emulation
-14K trace RAM
o Line assembler/disassembler
o Symbolic debugging, 700/900 symbols
o CMOS latch-up warning and protection
o Eight external sense clips on emulator probe
o Two serial and two parallel interface channels
o Memory bank selector to select ROM, DRAM or
trace RAM
o Host control program for IBM PC, PC/XT, PC/AT, or
compatible
Equipment Supplied
The IE-7S000-R package includes the following:
o IE-78000-R emulator chassis
o IE-78000-R-BK break board
o Control/trace board
o SD78KO-D52 screen debugger software
o RS-232-C interface cable
NEe
IE·78000·R
IE-78000-R In-Circuit Emulator
2
Ordering Information (Also, see selection guide.)
Part Number
Description
IE-7BOOO-R
In-circuit emulator for 7BKO product line
IE-7B014-R-EM
Emulation board for 7B014 family (optional)
IE-7B044-R-EM
Emulation board for 7B044 family (optional)
IE-7B064-R-EM
Emulation board for 7B064 family (optional)
EP-7B240GC-R
(64-pin plastic QFP) emulator probe
used with IE-7B014-R-EM board
EP-7B240CW-R
(64-pin shrink DIP) emulator probe
used with IE-7B014-R-EM board
EP-7B130GF-R
(BO-pin plastic QFP) emulator probe
used with IE-7B044-R-EM board (optional)
EP-7B064GF-R
(100-pin QFP (14x20)) emulator probe for
7B064GF family, used with IE-7B064-R-EM
board (optional)
EP-7B064GC-R
(100-pin QFP (14x14)) emulator probe for
7B064GC family used with IE-7B064-R-EM
board (optional)
EP-7B054GK-R
(BO-pin plastic TQFP (12x12)) emulator probe
for 7B054GK family, used with IE-7S064-R-EM
board (optional)
EP-7B230GC-R
(SO-pin QFP (14x14)) emulator probe for
7B054GC family, used with IE-7B064-R-EM
board (optional)
EV-9200G-BO
Five socket adapters; converts BO-pin LCC
probe tip to BO-pin QFP (14x20) device footprint
(optional)
EV-9200GC-64
Five socket adapters; converts 64.-pin LCC
probe tip to 64-pin QFP device footprint
(optional)
EV-9200GC-BO
Five socket adapters; converts BO-pin LCC
probe tip to BO -pin plastic QFP (14x14) device
footprint (optional)
EV-9200GF-l00
Five socket adapters; converts toO-pin LCC
probe tip to 100-pin QFP (14x20) device
footprint (optional).
EV-9500GC-l00
One socket adapter, 100-pin PGA to 100-pin
QFP (optional)
CC7BKO-D52
C compiler package for 7BKO product line
(optional)
RA7BKO-D52
Relocatable assembler for 7BKO product line
(optional)
SD7BKO-D52
Screen debugger software included in
IE-7BOOO-R package
NEe
IE·78000·R
IE-7BOOO -R Block Diagram
..
3
IE·78000·R
4
NEe
CC78KO
C Compiler for the
pPD78KO Product Line
NEe
NEC Electronics Inc.
September 1993
Description
The CC78KO C compiler is an ANSI standard C crosscompiler for the NEC J.lPD78KO product line of microcontrollers. The CC78KO (figure 1) converts ANSI standard C source code into NEC format object module or
assembly language source files. During compilation,
an optional optimizer can be invoked to optimize the
object code for size and/or execution speed.
In addition, CC78KO supports extended functions for
J.lPD78KO code generation. These extended functions
allow the C compiler to take advantage of many powerful features in the J.lPD78KO microcontrollers to decrease object code size and improve program execution speed.
The relocatable object file produced by the CC78KO
can be converted into an absolute object file by the
linker program and object converter program contained in the RA78KO relocatable assembler package.
The resulting ASCII hexadecimal format absolute object file then can be debugged using an NEC in-circuit
emulator or evaluation board.
Figure 1. CC78/CO Functional Diagram
CSource
Module
File
Parameter
FOe
1
L.",
8Assembler
Source
Module
FOe
f
CC78KO
CCompller
Rle
t
Include
Rle
./~
ObJect
Module
Rle
r-- Prepro06ss
UsIRle
1"
~
UsIRIe
~
Cross
Referenos
USlRle
a:m..-
Ordering Information
Part Number
System
Description
CC78KO-D52
MS-DOS
5-1/4-inch, double-density floppy
diskette
Features
o ANSI standard C compiler
o Extended functions for optimized J.lPD78KO code
generation
o Various optimization options for code size and/or
execution speed
o Legal C code verification
o Outputs NEC format object module or assembly
source file
o Run-time error checking
o Outputs debug information
o ROMabie object file creation
o User selectable and directable output files, list,
and full cross-reference files
o Extensive error reporting
o Built-in help facility
o Runs under MS-DOS® operating system
MS-DOS is a registered trademark of Microsoft Corporation
50619
CC78KO Extended Functions
• Register variables can be stored in the registers and
Saddr area
• Saddr area usage for variables
• Direct peripherals access with SFR names
• Saddr area usage for function arguments and automatic variables
• Functions can be called using the CALLT table
• Functions can be stored in the CALLF area
. '
• Bit data type
•
• In-line assembly language
• Interrupt functions
- Generate interrupt vector table
- Disable/enable interrupts
NEe
CC78KO
Compiler Options
The CC78KO C compiler supports the followi ng options
during compilation:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Target chip selection
Parameter file specification
Macro name definition
Include files search path specification
Symbol length extension
Symbol name conversion to uppercase
Outputs debug information
Generates
Object file
Assembler source file (with/without C source)
Cross-reference list file
Error list file (with/Without C source)
Preprocess list file
Listing format control
ROMable processing
Optimization option selection
Run-time error check selection
Temporary directory specification
Warning level selection
Outputs compilation status information
C Library Functions
The CC78KO C compiler library includes most of the
important C library functions that apply to PROMbased embedded systems. All library functions reside
in the library files supplied. Header files that declare
the set of library functions are also included.
The following library functions are available:
I/O Functions
sprintf
sscanf
Character Functions
isalpha
isupper
isalnum
isxdigit
isprint
isgraph
toupper
tolower
toascii
islower
isspace
iscntrl
_toupper
isdigit
ispunct
isascii
_to lower
String Functions
strlen
strcpy
strncat
strcmp
strrchr
strpbrk
strstr
strtok
atoi
atol
ultoa
strncpy
strncmp
strspn
strtol
itoa
strcat
strchr
strcspn
strtoul
Itoa
realloc
memcpy
memset
free
memmove
Memory Functions
malloc
calloc
brk
sbrk
memcmp
memchr
Program Control Functions
setjmp
longjmp
abort
exit
atexit
Mathematical Functions
abs
labs
div
Idiv
rand
srand
Special Functions
qsort
bsearch
va_arg
va_end
strerror
va_start
License Agreement
CC78KO is sold under terms of a license agreement
included with the compiler. The accompanying card
must be completed and returned to NEC Electronics
Inc. to register the license. Software updates are provided free to registered users for one year.
Documentation
For further information on source program formats, C
compiler, and actual program examples, refer to the
following manuals supplied with the compiler. Additional copies may be obtained from NEC Electronics
Inc.
• CC78K Series C Compiler for Language
• CC78K Series C Compiler for Operation
2
NEe
NEG Electronics Inc.
RA78KO
Relocatable Assembler Package
for the pPD78KO Product Line
September 1993
Description
Features
The RA78KO relocatable assembler package converts
symbolic source code for the pPD78KO product line of
8-bit. single-chip microcontrollers into executable absolute address object code. The RA78KO package consists of six separate programs: assembler (RA78KO).
linker (LK78KO). hexadecimal format object converter (OC78KO). librarian (LB78KO). list converter
(LCNV78KO). and structured assembler (ST78KO).
o Absolute address object code output
RA78KO translates a symbolic source module into a
relocatable object module. The assembler verifies that
each instruction assembled is valid for the target microcontroller specified at assembly time and produces
a listing file and a relocatable object module.
LK78KO combines multiple relocatable object modules
and library modules and converts them into a load
module. OC78KO converts a load module into an ASCII
hexadecimal format absolute object code file.
LB78KO allows commonly used relocatable object
modules to be stored in one file and linked into multiple
programs. greatly increasing programming efficiency.
When a library file is included in the input of the linker.
the linker extracts from the library file only those
modules required to resolve external references and
links them with the other modules.
LCNV78KO allows relocatable list files to be converted
into absolute list files.
The ST78KO structured assembler preprocessor is a
companion program to the RA78KO relocatable assembler for the NEC pPD78KO product line of microcontrollers. ST78KO converts a source code file containing
C-Iike structured assembly statements into a pure
assembly language source file. which then can be
assembled with RA78KO.
o User-selectable and directable output files
o Macro definitions
o Branch optimization
o Conditional assembly
o Extensive error reporting
o Powerful librarian
DC-like structured assembly statements
o Runs under MS-DOS® operating system
Ordering Information
Part Number
System
Description
RA78KO-D52
MS-DOS
5-1/4-inch, double-density
floppy diskette
Program Syntax
An RA78KO source module consists of a series of code.
data. or bit segments. Each segment consists of statements composed of up to four fields: symbol, mnemonic. operand, and comment.
The symbol field may contain a label, whose value is
the instruction or data address, or a name that represents an instruction address, data address. or constant. The mnemonic field may contain an instruction
or assembler directive. The operand field contains the
data or expression for the specified instruction or
directive. The comment field allows explanatory comments to be added to a program.
Character constants are translated into 7-bit ASCII
codes. Numeric constants may be specified as binary,
octal, decimal. or hexadecimal. Arithmetic expressions
may include the operators +, -, *, /, MOD, OR, AND.
NOT, XOR. EQ. NE. LT, LE. GT, GE. SHR, SHL, LOW,
HIGH •.• (). and character constants.
Macro Definition
MS-DOS is a registered trademark of Microsoft Corporation.
50611
RA78KO allows the definition of macro code sequences
with up to five parameters, LOCAL symbols, and special repeated code sequences. The macro code sequence differs from a subroutine call in that the invocation of a macro in the source code results in the
direct replacement of the macro call with the defined
code sequence.
NEe
RA78KO
Assembler Directives
Assembler directives give instructions to the assembler, but they are not translated into machine code
during assembly. Basic assembler directives include
storage definition and allocation directives (DB, OW
OS, OBI1); symbol directives (EQU, SE1); and location
counter control directive (ORG). Program control directives include segment directives (CSEG, OSEG, BSEG,
ENDS); linkage directives (NAME, PUBLIC, EXTRN,
EXTBI1); macro directives (MACRO, LOCAL, REPT, IRP,
EXITM, ENOM); automatic BR instruction directive
(BR); and assembly termination directive (END).
Assembler Controls
The RA78KO assembler (figure 1) has two types of
controls. Primary controls, specified in the assembler
command line or at the beginning of the source module, are as follows:
•
•
•
•
•
•
Processor selection
Output object creation selection
Output list file selection
Listing format controls
Optimization selection
Work file drive specification
General controls, specified in the source program, are
as follows:
•
•
•
•
•
Inclusion of other source files
Page eject
Generation/suppression of listing
Listing titles
Conditional assembly controls
~
~
~
FDe
--
RA78KO
The LK78KO linker (figure 2) combines several relocatable object modules, resolving PUBLIC/EXTRN references between modules, to create a load module. This
output module contains both absolute object code and
symbol information. The linker will also search library
files for required modules to resolve external references. The linker controls for LK78KO can be specified
in either the command line or in a parameter file.
The programmer can specify the starting address and
order for code/data/stack segments, and protectareas
of memory from being assigned.
Object
Module
File 1
Directive
FOe
~
t
obJect
Assembler
UstFRe
Error
list File
...
I
Object
Module
Fllen
I
LK78KO
Unker
--
Temporary
Work Ales
~
Temporary
Work FlIee
Load
Module
File
83CL-841tA
2
Linker
Parameter - - - +
File
~
Module
FRe
If the optimization option is chosen, the assembler will
generate the most efficient code by converting, where
possible, three-byte absolute branches into two-byte
relative branches.
Ubrary
File
[;J
Relocatable
Assembler
The cross-reference table contains all defined symbols
and the numbers 0.1 all statements referring to them.
The object file contains the relocatable object module.
This is an NEC proprietary relocatable object module
format.
Figure 2. Linker Functional Diagram
Figure 1. Relocatable Assembler Functional
Diagram
Source
Module
File
The listing file contains either the complete assembly
listing or only the lines with errors, and a symbol or
cross-reference table. The symbol table shows all defined symbols in alphabetical order with the types,
attributes, and the values initially assigned to them.
Unker
list File
Error
LIst File
B3Cl-9413A
NEe
RA78KO
Object Converter
List Converter
The OC78KO object converter (figure 3) outputs two
files: an absolute load file in ASCII hexadecimal format,
which can be downloaded to a PROM programmer, and
a symbol file for the symbolic debugger. The programmer can also specify an error list file for error logging.
The LC NV78KO list converter (figure 5) converts a
relocatable assembly list file into an absolute assembly list file, which contains absolute addresses and
symbol values.
Figure 5. Ust Converter Functional Diagram
Figure 3. Object Converter Functional Diagram
d
~
Module
Ale
B-Ale
y
Symbol
Table
Ale
/'
OC78KO
Hexadecimal Format
Object Converter
~
"-
Hexadecimal
y
Error
UstFne
Object
Code FUe
113C1.-9414A
Librarian
The LB78KO librarian (figure 4) creates and maintains
library files containing relocatable object modules.
This reduces the number of files to be linked together
by storing several modules in a single file. This provides an easy way to link frequently used modules into
programs. Modules can be added to, deleted from, or
replaced within a library file, or the contents of the
library file can be listed.
83CL
A< -> B
Contents of A and B are exchanged
Directive
+=
A += B
A+-A+B
Function
#define NAME value Defines the variable NAME, set to the
supplied value.
#ifdef ABC
< statements>
#else
< statements>
#endif
#include '1i1ename"
#defcallt @LABEL
CALL !label
#endcallt
~ ABC has been defined as above, or on the
command line with the -0 option, the first
set of statements is processed and the
second set ignored; if ABC has not been
defined, or defined as zero, the first set of
statements is ignored and the second set is
processed.
The named file is read from disk and
processed as if included in the source.
Whenever the instruction "CALL lIabel" is
encountered in the source program, it is
replaced by "CALLT [@LABEL]". The label
must be defined in the CALLT table.
Assignment, Increment, and Decrement
Statements
ST78KO provides the ability to represent an aSSignment,
or an assignment with an arithmetic operation, in C
language syntax:
destination < assign-op> source
A-= B
A ..... A- B
*=
AX*= B
AX ..... AX*B
/=
AX/= C
AX ..... AX/C
&=
A&= B
A ..... A & B (logical AND)
1=
AI= B
A +- A I B (logical OR)
A"= B
A +- A "B (logical XOR)
»=
A»=B
(CY.....AO.An.1+-An' ... .Amax+-O) x B times
«=
A«
++
A++
A ..... A+ l '
A--
A+- A-l
-
Control statements (table 3) allow conditions to be
tested. Based on the results of the test, blocks of code
are allowed to be executed or skipped. Reserved words
in the control statement define the start and end of
blocks of code and expressions to be evaluated.
Example:
if ( A = = [HL])
P5 = B (A)
A = [HL]
Examples:
else
=B
+ = [HL]
;Move contents of B register to A
;Add contents of memory at HL to A,
;store in A
Where an assignment requires an intermediate register
to hold the value being aSSigned, the register is designated by naming it in parentheses following the assignment operation.
(CY+-Amax.An+ 1+-An' ...Ao..... O) x B times
Control Statements
The assignment operators (table 2) allow either simple
assignment or the combination of an assignment with
an arithmetic operation on the source and destination.
A
A
=B
A + = [HL]
A- = B
;The condition is tested.
;If A equals the content of memory . - , ..
;at HL, this code is executed.
...,
;Otherwise, this code is executed.
P5 = A
endif
Examples:
DATA1 = B (A)
BC &
=
;Store contents of B into memory at
;DATA1, using A as temporary storage
HL (XA) ;and BC with HL, store in BC,
;use XA as temp
5
NEe
RA78KO
Table 3. Control Statement Directives
Table 6. Binary Operators
Control Statement
Function
Binary Operator
if - elseif - else - endif
Test variable expressions
if bit - elseltbit - else - end If
Test bit expressions
1=
Not equal
switch - case - default - ends
Select based on variable
>
Greater than
Meaning
Equal
for- next
Loop, test variable
>=
Greater than or equal to
while - endw
Loop, test variable
<
Less than
<=
Less than or equal to
repeat - until
Loop, test variable
while_bit - endw
Loop, test bit
repeat - until_bit
Loop, test bit
break
Exit control block
continue
Skip to top of block
goto LABEL
Branch to label
Bit expressions test individual bits of registers, ports,
or memory locations. Table 7 shows the acceptable
forms of bit expressions.
Table 7. Bit Expressions and Examples
Bit expression
Variable and Bit Expressions
Variable expressions for tests consist of a single value,
comparison between two variables, or a logical combination of comparisons. Bit expressions test individual
bits. Table 4 shows examples of comparisons. The
allowable expressions using variables are shown in
table 5.
Table 4. Examples of Variable Expression
Comparisons
Comparison
Meaning
if ( A )
True If A is non-zero
if (A < B)
True if A is less than B
if ((A < B) && (A > Cll
True if A is less than B and greater than C
itbit (P3.2)
True if bit 2 of P3 is 1
if_bit (!P3.2 )
True if bit 2 of P3 is 0
Table 5. Expressions and Examples
Expression
Example
Primary
(A)
Term
(A <= B)
Term &&Term
( (A< B) && (A> C) ) (logical AND)
Term II Term
( (A= = C) II (A= = B) ) (logical OR)
A primary value for a variable expression is a register
name or defined symbol. A term consists of two primary values compared with a binary operator. Table 6
lists the supported binary operators and their meanings.
6
Example
Bit primary
(P2.1 )
IBit primary
(ICY)
Bit primary && Bit primary
(A.O &&CY)
(P2.211 CY)
A Bit_primary can be either a reserved word bit identifier, such as a bit of a register or port (P2.1, Cy), or a bit
definition symbol (SBO EQU P2.2).
ST78KO Operation and Controls
ST78KO is invoked by specifying the name ofthe source
file, followed by optional controls.
Example:
C> ST78KO ABC.SRC -DXYZ= 3
ST78KO reads the specified source file and produces an
output assembly language file, which can be input to
RA78KO. The output file contains all lines provided in
the input source file, plus those generated by ST78KO.
Lines containing no statements for the structured
assembler are passed through unchanged. Lines with
structured assembly statements are placed in the
output preceded by a semicolon. RA78KO treats these
lines as comments. These commented lines are then
followed by the code generated by ST78KO.
The controls for ST78KO (table 8) are specified in the
preprocessor command line or in a parameter file
invoked in the command line.
NEe
RA78KO
Table B. 5178/(0 Preprocessor Controls
Control
Function
·Ofilename
Specify name of output assembly source file
-Ffilename
Specify name of parameter file to be read
-Elilename
Specify name of error listing file
-Dsymbol[ = value)
Define a symbol (Irke #define in code)
-I[d:) [directory)
Define path for include fi Ie
-WTnl,n2,n3
Define TAB settings for generated code
-SCcharacter
Defines word symbol last character
The -0 option allows the name of the output file to be
specified. If not specified, the output file name defaults
to the name of the input source file with the extension
.ASM.
The -F option allows a parameter file to be specified,
which will be read by ST78KO. This parameter file can
contain a list of controls to be given to ST78KO instead
of or in addition to those specified on the command
line.
The -E option specifies the name of the error listing file.
The error file contains the file name, error number,
description of error and the line containing the error. If
the -E option is not specified, the error file name
defaults to the name of the input source file with the
extension .EST.
The -D control allows a symbol to be defined on the
command line with an optional value provided. If a
symbol is defined but no value is specified, the value
defaults to 1. If the source file contains a #define
directive that specifies a variable with the same name
as the -D control, the value on the command line will
override the value in the #define directive.
The -I control specifies a drive or directory other than
the current drive and directory to search for include
files.
The -WT control specifies the number of TAB charactersto insert before labels, instruction mnemonics, and
instruction operands generated by ST78KO. This allows
clear separation of assembly language instructions
coded in the source file from those generated by
ST78KO.
The -SCcharacter control specifies the character used
as the last character in a word symbol. The character
must be a letter of the alphabet or the @, _ or ? This
allows ST78KO to distinguish between word and byte
operations. Symbols ending in this character are
treated as word symbols and will generate a word
operation (e.g. MOVW). If the -SC option is not specified, ST78KO assumes that a symbol ending with the
character "P" or "p" is a word symbol.
Emulator Controller Program
Absolute object files produced by the RA78KO relocatable assembler package can be debugged with the
appropriate NEC standalone in-circuit emulator. NEC
emulator controller programs allow communication
with the emulator through an RS-232C serial line. An
emulator controller program can run on the IBM PC®,
PCIXT®, or PC AT® under MS-DOS and is provided with
the in-circuit emulator at no extra charge.
These emulator controller programs provide the following features:
•
•
•
•
•
•
•
•
Uploading/downloading of object and symbol files
Symbolic debugging capability
Complete emulator control from host console
On-line help facilities
Macro command file capabilities
Host system directory and file display
Disk storage of debug session
Storage of last 20 commands for recall
License Agreement
RA78KO is sold under terms of a license agreement
included with the assembler. The accompanying card
must be completed and returned to NEC Electronics
Inc. to register the license. Software updates are provided free to registered users for one year.
Documentation
For further information on source program formats,
assembler operation, and actual program examples,
refer to the following manuals supplied with the RA78KO
package. Additional copies may be obtained from NEC
Electronics Inc.
• RA78KSeriesAssembier Package, Language Manual
• RA78K Series Assembler Package, Operation Manual
• RA78K Series Structured Assembler Preprocessor,
User's Manual
IBM PC, PC/XT, and PC AT are registered trademarks of International
Business Machines Corporation.
7
•
RA7SKO
8
NEe
SD78KO
Screen Debugger for the
pPD78KO Product Line
NEe
NEG Electronics Inc.
September 1993
Description
Development Tool Chain
The SD78KO screen debugger is a versatile software
tool for debugging C and assembly language programs
written for the ~PD78KO product line of microcontrollers. SD78KO has an easy-to-use, window-like user interface and can perform both source-level and symbolic debugging.
C source programs can be compiled with the CC78KO
C compiler to generate relocatable object code as
shown in figure 1. The RA78KO relocatable assembler
converts assembly language source programs into
relocatable object code. The debug option must be
specified during program compilation or assembly,
which will embed debug information into the object
code. The resulting object code can be linked using the
LK78KO linker, which is part of the RA78KO relocatable
assembler package, to generate a load module file. The
SD78KO screen debugger then takes this load module
file as input for program debugging on the in-circuit
emulator.
SD78KO performs software debugging by monitoring
and controlling program execution on an NEC incircuit emulator from a host computer. Program execution information is presented in an organized format on
several windows.
The SD78KO screen debugger is an integral component
ofthe software development tool chai n for the ~PD78KO
product line of microcontroliers. Its structured and
user-friendly debugging environment can significantly
improve software reliability as well as programmer
productivity.
Figure 1. Development Tool Chain
Features
o C and assembly language source-level debugging
o Extensive program debugging functions
o Window-like user interface
o Mouse support
o User-configurable windowing environment
o User-defined key macro
o Screen dump to a printer or a disk file
o On-line help facility
o Extensive error reporting
o Runs under MS-DOS® operating system
MS-DOS is a registered trademark of Microsoft Corporation
83Yl-9422A
Ordering Information
Part Number
System
Oescrlptlon
SD78KO-D52
MS-DOS
5-1/4-inch, double-density
floppy diskette
50616
SD78KO
Debugging Functions
• Program upload/download
• On-line program assembly/disassembly
• Separate display!working windows for:
• - Register banks
- Special function registers
-Memory
- Source code
-Symbols
-Variables
-Functions
-Stack
• Breakpoint/watchpoint setting
• Event conditions setting
• Program tracing
• Real-time step emulation
• Performance measurement
• PROM programmer control
• Command file execution
• Save debug session
License Agreement
SD78KO is sold under terms of a license agreement
included with purchased copies of the screen debugger. The accompanying card must be completed and
returned to NEC Electronics Inc. to register the license..
Software updates are provided free to registered users
for one year.
Documentation
For further information on features, operations, and
session examples, refer to the following manuals supplied with the SD78KO. Additional copies may be obtained from NEC Electronics Inc.
• SD78KjO Screen Debugger, SD Primer
• SD78KjO Screen Debugger, SD Reference
2
NEe
NEe
NEG Electronics Inc.
IE·78230·R
In·Circuit Emulator
for the pPD78224/238 Families
September 1993
Description
o Eight external sense clips on emulator probe
The IE-78230-R is an in-circuit emulator providing both
hardware emulation and software debugging capabilities for the NEC pPD78224/238 families of single-chip
microcontrollers. Real-time and single-step emulation,
combined with sophisticated memory mapping features, breakpoint, and trace capabilities, create a powerful debugging environment. A line assembler/
disassembler, full register and memory control,
symbolic debugging, and complete upload/download
capabilities simplify the task of debugging hardware
and software.
o Host control program for IBM PC®, PC/XT®,
PC/AT®, or compatible
o Centronics parallel interfaces for optional highspeed program download and printer
IBM PC, PC/XT, and PC/AT are registered trademarks of International
Business Machines Corporation.
Equipment Supplied
The IE-78230-R package includes the following:
o IE-78230-R emulator frame
Features
o Control/trace board
o 12-MHz maximum operating frequency
o Break board (IE-78200-R-EM)
o Real-time and non-real-time emulation
o Emulation board (IE-78230-R-EM)
o Sophisticated break events
- Logical OR of up to four sets of events
Executed instruction count
External sense clip condition
Parallel or sequential fetch addresses
Logical AND of addresses, data values, CPU
controls, and loop count
o Controller software program
o Sophisticated trace capabilities
- Traces program fetch or data access
-2K x 44 bit trace buffer
- Address, control, data, and external signal trace
-Instruction or frame display
- Trace search capability
-Specify trigger pOint at beginning, middle, or
end of trace buffer
o Supports debug activities during real-time
emulation
- Displays trace buffer
- Modifies trace conditions
- Modifies trace event conditions
- Restarts trace
o Powerful memory mapping
- 32K bytes RAM for pPD78224 or pPD78238 ROM
emulation
-3840 bytes of RAM for internal RAM emulation
- 64K bytes of RAM for off-chip RAM/ROM
emulation
o Line assembler/disassembler
o Symbolic debugging: 7000 symbols maximum
o CMOS latch-up warning and protection
50354
o RS-232-C interface cable
Ordering Information (Also, see selection guide.)
Part Number
Description
IE-78230-R
In-circuit emulator for pPD78224/238 families
IE-78230-R-EM
Emulation board included in IE-78230-R
package (separately purchased to upgrade 75X
or 78X product line emulators to have functions
equivalent to IE-78230-R)
EP-78230GC-R
Emulator probe for 80-pin QFP (optional)
(includes one EV-9200GC-80 socket adapter)
EP-78230GJ-R
Emulator probe for 94-pin QFP (optional)
(includes one EV-9200G-94 socket adapter)
EP-7S230LQ-R
Emulator probe for S4-pin PLCC package
(optional)
EV-9200GC-SO
Five socket adapters; converts 80-pin LCC
probe tip to SO-pin plastic QFP (14x14) device
footprint (optional)
EV-9200G-94
Five socket adapters; converts 94-pin LCC
probe tip to 94-pin QFP device package
(optional)
RA78K2-D52
Relocatable assembler for 78K2 product line
CC7SK2-D52
C compiler for 78K2 product line
SD7SK2-D52
Screen debugger for
*Under development
~8K2
product line*
IE·78230·R
IE-7823O-R In-Circuit Emulator
2
NEe
NEe
NEC Electronics Inc.
IE-78240-R
In-Circuit Emulator
for the JlPD78214/218A/244 Families
September 1993
Description
The IE-78240-R is an in-circuit emulator providing both
hardware emulation and software debugging capabilities for the NEC pPD78214/218A/244 families of singlechip microcontrollers. Real-time and single-step emulation capability, combined with sophisticated
memory-mapping features, breakpoints, and trace capabilities, create a powerful debugging environment. A
line assembler/disassembler, full register and memory
contrOl, symbolic debugging, and complete upload/
download capabilities simplify the task of debugging
hardware and software.
The IE-78240-R-EM is an optional emulation board
available to upgrade the 75X or 78K product lines of
in-circuit emulators to have functions equivalent to the
IE-78240-R.
Features
o 12-MHz max operating frequency
o Real-time and non-real-time emulation
o Sophisticated break events
- Logical OR of up to four sets of events
Executed instruction count
External sense clip condition
Parallel or sequential fetch addresses
Logical AND of addresses, data values, CPU
controls, and loop count
o Sophisticated trace capabilities
- Traces program fetch or data access
- 2K x 44-bit trace buffer
-Address, control, data, and external signal trace
-Instruction or frame display
- Trace se.arch capability
-Specify trigger point at beginning, middle, or
end of trace buffer
50355
o Supports debug activities during real-time
emulation
- Displays trace buffer
- Modifies trace conditions
- Modifies trace event conditions
- Restarts trace
o Powerful memory mapping
- 32K bytes RAM for pPD7821x or pPD7824X ROM
emulation
- 3840 bytes of RAM for internal RAM emulation
- 3840 bytes of EEPROM for pPD7824x EEPROM
emulation
- 64K bytes of RAM for off-chip RAMIROM
emulation
o Line assembler/disassembler
o Symbolic debugging: 7000 symbols maximum
o CMOS latch-up warning and protection
o Eight external sense clips on emulator probe
o Host control program for IBM PC@, PC/XT,
PC/AT@, or compatible
o Centronics parallel interfaces for optional highspeed program download and printer
IBM PC, pcnn; and PC/AT are registered trademarks of International
Business Machines Corporation.
Equipment Supplied
The IE-78240-R package includes the following:
o IE-78240-R emulator frame
o Control/trace board
o Break board (IE-78200-R-EM)
o Emulation board (IE-78230-R-EM)
o Controller software program
o RS-232-C interface cable
NEe
IE·78240·R
Ordering Information (Also, see selection guide.)
Part Number
Description
IE-76240-R
In-circuit emulator for /lP076214/216A/244
families
IE-76240-R-EM
Separately sold emulation board to upgrade
75X or 76X product lines of in-circuit emulators
to have functions equivalent to IE-76240-R
EP-76240CW-R
Emulator probe for 64-pin shrink OIP package
(optional)
EP-76240GC-R
Emulator probe for 64-pin QFP (optional)
(Includes one. EV-9200GC-64 socket adapter)
EP-76240GJ-R
Emulator probe for 74-pin QFP (optional)
(Includes one EV-9200G-74 socket adapter)
EP-76240GQ-R
Emulator probe for 64-pin QUIP (optional)
EP-76240LP-R
Emulator probe for 66-pin PLCC package
(optional)
EV-9200GC-64
Five socket adapters; converts 64-pin LCC
probe tip to 64-pin QFP device footprint.
(Optional)
EV-9200G-74
Five socket adapters; converts 74-pin probe tip
to 74-pin QFP device footprint. (Optional)
RA76K2-052
Relocatable assembler for 78K2 product line
CC78K2-052
C compiler for 76K2 product line
S078K2-052"
Screen debugger for 78K2 product line
"Under development
2
IE-78240-R In-Circuit Emulator
NEe
NEC Electronics Inc.
DDB-78K2
Evaluation Board
for the pPD78K2 Product Line
September 1993
Description
The DDB-78K2 are evaluation boards for the NEC
J.IPD78K2 product line of 8-bit, single-chip microcontrollers. The DDB-78K2 provides maximum flexibility
when evaluating and designing with the J.IPD78K2 product line. Every DDB-78K2 features a J.IPD78213,
J.IPD78220, J.IPD78233, or J.IPD78343 microcontrolier,
32K bytes of ROM, 32K bytes of RAM, J.IPD27C512
footprint for 64K bytes of optional extended data memory, RS-232-C communication port, and a powerful
monitor program. A playpen area is included for evaluating the J.IPD78K2 product line with application specific hardware.
Features
o J.IPD78213, J.IPD78220, J.IPD78233, or J.IPD78243
evaluation board
- Convertible by changing microcontroller
o On-board memory
-ROM: 32K bytes
-RAM: 32K bytes
o J.IPD27C512 footprint for 64K bytes of extended
data memory
o Powerful on-board debug monitor
- Real-time and single-step operation
- Display/change memory and internal registers
DDB·78K2 Evaluation Board
502tl7
- Multiple software breakpoints
- User program download capability
o RS-232-C serial interface for terminal or host
computer
o Playpen area for user circuitry
o Includes ACIDC converter
Equipment and Documentation Supplied
The DDB-78K2-2xx package includes the following:
o DDB-78K2-2XX evaluation board for 78K2 product
line
o RA78K2-D52 relocatable assembler for 78K2
product line
o AC/DC converter power supply
o Data book/user's manual
Ordering Information (Also, see selection guide.)
Part Number
Description
DDB-78K2-21x
Basic development board for JlPD78218N
214 families designs
DDB-78K2-22x
Basic development board for JlPD78224
fam ily designs
DDB-78K2-23x
Basic development board for JlPD78238
family designs
NEe
DDB·78K2
DDB-78K2 Block Diagram
rJAn
ADo-A07
RS-232-C
Connector I - -
RS·232·C
Interface
LF
SIO
Socket to Socket
ConnecUons
~PD78243
~PD78213
ea·PlnPLCC
Socket
I
I
Monitor
EPROM
o-7FFF
Address Latch
Ao-A7
Aa-A14
A1S-A19
27CS12
I
H
Control
Logic
I
I
I
I
t--RAM
8000·FFFF
~PD43256A
I
Header
'---
'--~PD78220
"PD78233
84·PlnPLCC
Sockst
Extended
Data Mamory
EPROM
Footp~nt
FOOOO·FFFFF
27C512
I
LfoAW
49NR·66tlB (9193)
2
EB-78230-PC
Evaluation Board
for the pPD78238 Family
NEe
NEG Electronics Inc.
September 1993
Description
The EB-78230-PC is an evaluation board for the NEC
IlPD78233 and IlPD78234. These devices are 8-bit,
single-chip microcontrollers. The EB-78230-PC provides a simple way to evaluate the capabilities of the
IlPD78233 and IlPD78234 in an application without
having to build a prototype. If it is necessary to connect
the EB-78230-PC directly to a target system, the IE78230 emulator probes can be purchased separately.
The EB-78230-PC features 32K bytes of static RAM for
evaluation programs, an RS-232-C communication
port, and a powerful on-board monitor. Evaluation
programs can be downloaded from a host computer or
created directly on the board using the line assembler.
Programs can be executed in real time with or without
breakpoints or one instruction at a time. Commands
are available to display or change memory, general
registers or special function registers, and to disassemble your code.
A controller program controls the EB-78230-PC directly
from the console of an IBM PC®, PC/XT®, PC/AT® or
compatible host computer using an RS-232-C serial
interface.
Equipment and Documentation Supplied
o EB-78230-PC evaluation board
o EB-78230-PC user's manual
o System disk for IBM PC
o AC/DC converter power supply
o Battery holder and mounting hardware
Ordering Information (Also, see selection guide.)
Part Number
Description
EB·78230-PC
pPD78233 Evaluation Board (IBM PC Based)
EP-78230GC·R
Emulator probe for aO·pin QFP (optional)
(Includes one EV·9200GC·80 socket adapter)
Ep·78230GJ·R
Emulator probe for 94'pin QFP (optional)
(Includes one EV·9200G·94 socket adapter)
Ep·78230LQ.R
Emulator probe for 84-pin PLCC package
(optional)
EV-9200GC·80
Five socket adapters; converts aO·pin LCC
probe tip to 80·pin plastic QFP (14x14) device
footprint (optional).
EV-9200G-94
Five socket adapters; converts 94-pin LCC
probe tip to 94-pin QFP device footprint
(optional).
Features
o 12-MHz max operating frequency
o IlPD78233 evaluation board
o 32K bytes static RAM
o Real-time and single-step execution
o Four parallel or sequential breakpoints
o Display/change memory and general registers
o Display/change special function registers
o User program upload/download capability
o Symbolic debugging support
o Line assembler and disassembler
o RS-232-C serial interface for host computer
o Host control software for IBM PC, PC/XT, PC/AT or
compatibles
o Connection to a target system using in-circuit
emulator probes
IBM PC, PC/XT, and PC/AT are registered trademarks of International
Business Machines Corporation.
50337
EB-78230-PC Evaluation Board
NEe
EB·78230·PC
EB·78230·PC Block Diagram
~PD78233
-
~PD71051
~
User
Inte rface
Using
Dedlcaled
P robe
I
>I
RS-2320
Interface
Buffer
Address Bus
-
-
-
r-=J~
I
:..
PAL
2
Buffer
AddresstData Bus
~
Latch
I
-
I
ROM
I I
RAM
I
=>-
User
Inlerface
Uslng
Dedicated
Probe
=>-
NEe
NEG Electronics Inc.
EB-78240-PC
Evaluation Board
for the pPD78214/218A/244 Families
September 1993
Description
The EB-78240-PC is an evaluation board for the NEC
J.lPD78214/218A/244 families of 8-bit, single-chip microcontrollers. The EB-78240-PC provides a simple way to
evaluate the capabilities of these devices in an application without having to build a prototype. If it is
necessary to connect the EB-78240-PC directly to a
target system, the IE-78240 emulator probes can be
purchased separately.
The EB-78240-PC features 32K bytes of static RAM for
evaluation programs, an RS-232-C communication
port, and a powerful on-board monitor. Evaluation
programs can be downloaded from a host computer or
created directly on the board using the line assembler.
Programs can be executed in real time with or without
breakpoints or one instruction at a time. Commands
are available to display or change memory, general
registers or special function registers, and to disassemble your code.
A controller program controls the EB-7B240-PC directly
from the console of an IBM PC®, PCIXT®, PC/AT® or
compatible host computer using an RS-232-C serial
interface.
Features
o 12-MHz max operating frequency
Equipment and Documentation Supplied
o EB-78240-PC evaluation board
o EB-78240-PC user's manual
o System disk for IBM PC
o AC/DC converter power supply
o Battery holder and mounting hardware
Ordering Information (Also, see selection guide.)
Part Number
Description
EB-78240-PC
JlPD78243 evaluation board (IBM
EP-78240CW-R
Emulator probe for 64-pin shrink DIP package
(optional)
EP-78240GC-R
Emulator probe for 64-pin QFP (optional)
(Includes one EV-9200GC-64 socket adapter)
EP-78240GJ-R
Emulator probe for 74-pin QFP (optional)
(includes one EV-9200G-74 socket adapter)
EP-78240GQ-R
Emulator probe for 64-pin QUIP package
(optional)
EP-78240LP-R
Emulator probe for 68-pin PLCC package
(optional)
EV-9200GC-64
Five socket adapters; converts 64-pin LCC
probe tip to 64-pin QFP device footprint
(optional).
EV-9200G-74
Five socket adapters; converts 74-pin probe tip
to 74-pin QFP device footprint (optional).
o J.lPD78243 evaluation board
o 32K bytes static RAM
o Real-time and single-step execution
o Four parallel or sequential breakpoints
o Display/change memory and general registers
o Display/change special function registers
o User program upload/download capability
o Symbolic debugging support
o Line assembler and disassembler
o RS-232-C serial interface for host computer
o Host control software for IBM PC, PCIXT, PC/AT, or
compatibles
o Connection to a target system using in-circuit
emulator probes
IBM pc, PC/XT, and PC/AT are registered trademarks of International
Business Machines Corporation.
50338
EB-78240-PC Evaluation Board
pc Based)
NEe
EB·78240·PC
EB·78240-PC Block Diagram
~PD78243
~PD71051
Target
System
~----------------~ R~~~
Port
~----------------,/ Interface
.--________:..:.Add::; leSS Bus
r-----'Add=Ie;s=is/D~at7aB~u:::s____-,-,--.,..,------l Buffer
Target
System
Target
System
BSYL·9423B (9193)
2
CC78K2
C Compiler for the
pPD78K2 Product Line
NEe
NEG Electronics Inc.
September 1993
Description
The CC78K2 C compiler is an ANSI standard C crosscompiler for the NEC J.lPD78K2 product line of microcontrollers. The CC78K2 (figure 1) convertsANSI standard C source code into NEC format object module or
assembly language source tiles. During compilation,
an optional optimizer can be invoked to optimize the
object code for size and/or execution speed.
In addition, CC78K2 supports extended functions for
J.lPD78K2 code generation. These extended functions
allow the C compiler to take advantage of many powerful features in the J.lPD78K2 microcontrollers to decrease object code size and improve program execution speed.
The relocatable object file produced by the CC78K2
can be converted into an absolute object file by the
linker program and object converter program contained in the RA78K2 relocatable assembler package.
The resulting ASCII hexadecimal format absolute object file then can be debugged using an NEC in-circuit
emulator or evaluation board.
Features
o ANSI standard C compiler
o Extended functions for optimized J.lPD78K2 code
generation
o Various optimization options for code size and/or
execution speed
o Legal C code verification
o Outputs NEC format object module or assembly
source file
o Run-time error checking
o Outputs debug information
o ROMabie object file creation
o User selectable and dlrectable output files, list,
and full cross-reference files
o Extensive error reporting
o Built-in help facility
o Runs under MS-DOS® operating system
MS·DOS is a registered trademark of Microsoft Corporation
50620
Figure 1. CC7BK2 Functional Diagram
CSourca
Module
FRe
Parameter
FIle
~
L...
&
Assembler
Source
Module
FIle
"..--J
CC78K2
CCompller
FIle
...
Include
FIle
~ "-
/~
Object
Module
Rle
r--- PrepRicess
Us! FIle
Error
Us! FIle
...
cross
Reference
Us! FIle
Ordering Information
Part Number
System
Description
CC78K2-D52
MS-DOS
5-1/4-inch, double-density floppy
diskette
CC78K2 Extended Functions
• Register variables can be stored in the registers and
Saddr area
• Saddr area usage for variables
• Direct peripherals access with SFR names
• Saddr area usage for function arguments and automatic variables
• Functions can be called using the CALLT table
• Functions can be stored in .the CALLF area
• Bit data type
• In-line assembly language
• Interrupt functions
- Generate interrupt vector table
- Disable/enable interrupts
• 1-megabyte extended data memory support
•
NEe
CC78K2
Compiler Options
The CC78K2 C compiler supports the following options
during compilation:
•
•
•
•
•
•
•
•
Target chip selection
Parameter file specification
Macro name definition
Include files search path specification
Symbol length extension
Symbol name conversion to uppercase
Outputs debug information
Generates
-Object file
- Assembler source file (with/without C source)
- Cross-reference list file
- Error list file (with/without C source)
- Preprocess list file
• Listing format control
• ROMabie processing
• Optimization option selection
• Run-time error check selection
• Temporary directory specification
• Warning level selection
• Outputs compilation status information
C Library Functions
The CC78K2 C compiler library includes most of the
important C library functions that apply to PROMbased embedded systems. All library functions reside
in the library files supplied. Header files that declare
the set of library functions are also included.
The following library functions are available:
1/0 Functions
sprintf
sscanf
Character Functions
isalpha
isupper
isalnum
isxdigit
isprint
isgraph
toupper
tolower
toascii
islower
isspace
iscntrl
_toupper
isdigit
ispunct
isascii
to lower
String Functions
strlen
strcpy
strncat
strcmp
strrchr
strpbrk
strstr
strtok
atoi
atol
ultoa
strncpy
strncmp
strspn
strtol
itoa
strcat
strchr
strcspn
strtoul
Itoa
realloc
memcpy
memset
free
memmove
Memory Functions
malloc
calloc
brk
sbrk
memcmp
memchr
Program Control Functions
setjmp
longjmp
abort
exit
atexit
Mathematical Functions
abs
labs
Idiv
div
rand
srand
Special Functions
qsort
bsearch
va_end
va_arg
strerror
License Agreement
CC78K2 is sold under terms of a license agreement
included with the compiler. The accompanying card
must be completed and returned to NEC Electronics
Inc. to register the license. Software updates are provided free to registered users for one year.
Documentation
For further information on source program formats, C
compiler, and actual program examples, refer to the
following manuals supplied with the compiler. Additional copies may be obtained from NEC Electronics
Inc.
• CC78K Series C Compiler for Language
• CC78K Series C Compiler for Operation
2
NEe
NEG Electronics Inc.
RA78K2
Relocatable Assembler Package
for the pPD78K2 Product Line
September 1993
Description
DC-like structured assembly statements
The RA78K2 relocatable assembler package converts
symbolic source code for the IlPD78K2 product line of
8-bit, single-chip microcontrollers into executable absolute address object code. The RA78K2 package consists of six separate programs: assembler (RA78K2),
linker (LK78K2), hexadecimal format object converter
(OC78K2),
librarian
(LB78K2),
list converter
(LC NV78K2) , and structured assembler (ST78K2).
o Runs under MS-DOS® operating system
RA78K2 translates a symbolic source module into a
relocatable object module. The assembler verifies that
each instruction assembled is valid for the target microcontroller specified at assembly time and produces
a listing file and a relocatable object module.
LK78K2 combines multiple relocatable object modules
and library modules and converts them into a load
module. OC78K2 converts a load module into an ASCII
hexadecimal format absolute object code file.
LB 78K2 allows commonly used relocatable object
modules to be stored in one file and linked into multiple
programs, greatly increasing programming efficiency.
When a library file is included in the input of the linker,
the linker extracts from the library file only those
modules required to resolve external references and
links them with the other modules.
LCNV78K2 allows relocatable list files to be converted
into absolute list files.
The ST78K2 structured assembler preprocessor is a
companion program to the RA78K2 relocatable assembler for the NEC IlPD78K2 product line of microcontrollers. ST78K2 converts a source code file containing
C-like structured assembly statements into a pure
assembly language source file, which then can be
assembled with RA78K2.
Features
o Absolute address object code output
o User selectable and directable output files
MS-DOS is a registered trademark of Microsoft Corporation.
Ordering Information
Part Number
System
Oeser i ptlon
RA78K2-D52
MS-DOS
5-1/4-inch, double-density floppy
diskette
Program Syntax
An RA78K2 source module consists of a series of code,
data, or bit segments. Each segment consists of statements composed of up to four fields: symbol, mnemonic, operand, and comment.
The symbol field may contain a label whose value is the
instruction or data address or a name that represents
an instruction address, data address, or constant. The
mnemonic field may contain an instruction or assembler directive. The operand field contains the data or
expression for the specified instruction or directive.
The comment field allows explanatory comments to be
added to a program.
Character constants are translated into 7-bit ASCII
codes. Numeric constants may be specified as binary,
octal, decimal, or hexadecimal. Arithmetic expressions
may include the operators + , -, *, /, MOD, OR, AND,
NOT, XOR, EO, NE, LT, LE, GT, GE, SHR, SHL, LOW, ~
••
HIGH, ., ( ), and character constants.
~
Macro Definition
RA78K2 allows the definition of macro code sequences
with up to five parameters, LOCAL symbols, and special repeated code sequences. The macro code sequence is different than a subroutine call in that the
invocation of a macro in the source code results in the
direct replacement of the macro call with the defined
code sequence.
o Macro definitions
o Branch optimization
Assembler Directives
o Conditional assembly
Assembler directives give instructions to the assembler, but they are not translated into machine code
during assembly. Basic assembler directives include
o Extensive error reporting
o Powerful librarian
50191-1
NEe
RA78K2
storage definition and allocation directives (DB, DVI(
OS, DBIl); symbol directives (EQU, SEl); and the location counter control directive ORG. Program control
directives include segment directives (CSEG, DSEG,
BSEG, ENDS); linkage directives (NAME, PUBLIC, EXTRN, EXTBIl); macro directives (MACRO, LOCAL,
REPT, IRP, EXITM, ENDM); automatic BR instruction
directive (BR); and assembly termination directive
(END).
Assembler Controls
The RA78K2 assembler (figure 1) has two types of
controls. The primary controls, which are specified in
the assembler command line or at the beginning of the
source module, are as follows:
•
•
•
•
•
•
Processor selection
Output object creation selection
Output list file selection
Listing format controls
Optimization selection
Work file drive specification
The general controls, specified in the source program,
are as follows:
• Inclusion of other source files
• Page eject
• Generation/suppression of listing·
• Listing titles
• Conditional assembly controls
The listing file may contain the complete assembly
listing or only lines with errors, and a symbol or
cross-reference table. The symbol table shows all defined symbols in alphabetical order, their types, attributes, and the values initially assigned to them.
Figure 1. RelocatableAssemblerFunctional
Diagram
Souroe
ModUle
Rle
~
1-·"1 · !
Ale
2
1
RA78K2
Relocatabla
Asaembler
Objacl
Module
FDe
!
--
Temporary
Work Alas
'f
Enor
UetAIe
Asaembler
UetAIe
Figure 2. Unker Functional Diagram
Ubrary
FHe
Object
Module
File 1
Directive
FDe
...
I
Object
Module
Alen
I
Perematar
~
Ala
LK78K2
Unker
I--
Temporary
Work Alas
1
The cross-reference table contains all defined symbols
and the numbers of all statements that refer to them.
The object file contains the relocatable object module.
The format of this module is an NEC proprietary relocatable object module format.
If the optimization option is chosen, the assembler will
generate the most efficient code by converting, where
pOSSible, three-byte absolute branches into tWO-byte
relative branches.
Include
FDe
Load
ModUle
Fila
Unker
UetAIe
B
LIstRie
..N.......
Linker
The LK78K2linker (figure 2) combines several relocatable object modules, resolving PUBLIC/EXTRN references between modules, to create a load module. This
output module contains both absolute Object code and
symbol information. The linker will also search library
files for required modules to resolve external references. The linker controls for LK78K2 can be specified
in either the command line or in a parameter file.
NEe
~~
The programmer can specify the starting address and
order for code/data/stack segments, and protect areas
of memory from being assigned.
Figure 4. Ubrarian Functional Diagram
Object Converter
The OC78K2 object converter (figure 3) outputs two
files: an absolute load file in ASCII hexadecimal format,
which can be downloaded to a PROM programmer, and
a symbol file for the symbolic debugger. The programmer can also specify an error list file for error logging.
_(Tam~~ J
'-r-----r'
Librarian
The LB78K2 librarian (figure 4) creates and maintains
library files containing relocatable object modules.
This reduces the number of files to be linked together
by storing several modules in a single file. This provides an easy way to link frequently used modules into
programs. Modules can be added to, deleted from, or
replaced within a library file, or the contents of the
library file can be listed.
83N'H'i27A
Figure 5. Ust Converter Functional Diagram
List Converter
The LCNV78K2 list converter (figure 5) converts a
relocatable assembly list file into an absolute assembly list file, which contains absolute addresses and
symbol values.
Figure 3_ Object Converter Functional Diagram
•
Load
Module
Ale
~
Parameter
Ale
~
OC78K2
Hexadecimal Format
Object Converter
t
~
Symbol
Table
Ale
Hexadecimal
Object
Code FOe
.......
t
Error
UsiAla
83NR-7628A
3
NEe
RA78K2
Structured Assembler
Summary of Structured Language
The ST78K2 (figure 6) converts a structured assembly
statement into one or more J.lPD78K2 assembly language instructions that perform the desired operation.
Since ST78K2 converts only structured assembly
statements and not J.lPD78K2 assembly language instructions, a structured source program can include a
combination of J.lPD78K2 structured assembly statements and assembly language.
A line of source code for ST78K2 contains either a
structured assembly statement or a J.lPD78K2 assembly language statement. J.lPD78K2 assembly language
statements (J.lPD78K2 instructions, RA78K2 directives,
or RA78K2 controls) pass through ST78K2 without
change.
ST78K2 enables the assembly language programmer
to use some of the structures and syntax of higher-level
languages such as the C language. This improves
program readability and reliability, and increases programmer productivity.
Features of the ST78K2
o Control structures for conditions, looping, and
switch-case
o Preprocessor directives for conditional code
generation
DC-like representation of comparison operations
DC-like representation of assignment/arithmetic
operations
o Increment and decrement operators
o Allows use of all J.lPD78K2 mnemonics, registers,
and features
Figure 6. Structured Assembler Preprocessor
Functional Diagram
RA78K2
"PD78K2
Relocatable
Assembler
49NR_
4
Structured assembly statements consist of preprocessor directives, assignment statements, and control
statements. These statements are entered one per Ii ne,
and are terminated by a line feed character. An optional
comment may follow a semicolon at the end of the
statement; all text following a semicolon is ignored by
ST78K2.
Preprocessor directives cause ST78K2 to include or
omit portions of code. Assignment statements cause
ST78K2 to generate one or more J.lPD78K2 assembly
language instructions to alter the contents of a register
or variable. Control statements cause ST78K2 to generate the necessary instructions to test conditions and
change control flow based on those conditions.
Preprocessor Directives
ST78K2 preprocessor directives set and test variables,
allowing conditional processing of code; include external files; and map instructions to J.lPD78K2 CALLT table
reference instructions. Table 1 lists the preprocessor
directives and their functions.
Table 1. Preprocessor Directives and Functions
Directive
Function
#define NAME value
Defines the variable NAME, set to the
supplied value.
#ildelABC
< statements>
#else
< statements>
#endif
If ABC has been defined as above, or on
the command line with the -0 option, the
first set of statements is processed and
the second set ignored; if ABC has not
been defined, or defined as zero, the Ii rst
set of statements is ignored and the
second set is processed.
#include "filename"
The named file Is read from disk and
processed as if included in the source.
#defcallt @LABEL
CALL !label
#endcallt
Whenever the instruction "CALL !label" is
encountered In the source program, it Is
replaced by "CALLT [@LABEL]". The
label must be defined in the CALLT table.
NEe
RA78K2
Assignment, Increment, and Decrement
Statements
ST78K2 provides the ability to represent an assignment.
or an assignment with an arithmetic operation. in C
language syntax:
destination < assign-op> source
The assignment operators (table 2) allow either simple
assignment or the combination of an assignment with
an arithmetic operation on the source and destination.
Examples:
A= B
A + = [HL]
;Move contents of B register to A
;Add contents of memory at HL to A.
;store in A
Where an assignment requires an intermediate register
to hold the value being assigned. the register is designated by nam i ng it in parentheses followi ng the assignment operation.
Examples:
DATA1
=
B (A)
;Store contents of B into memory at
;DATA1. using A as temporary
;storage
;and BC with HL. store in BC.
;use XA as temp
BC & = HL (XA)
Control Statements
Control statements (table 3) allow conditions to be
tested. Based on the results of the test. blocks of code
are allowed to be executed or skipped. Reserved words
in the control statement define the start and end of
blocks of code and expressions to be evaluated.
Example:
if (A = = [HL])
P5 = B (A)
A= [HL]
;The condition is tested
;If A equals the content of memory
;at HL. this code is executed
else
A + = [HL]
;Otherwise this code is executed
A- = B
P5 = A
endif
Table 3. Control Statement Directives
Control Statement
Function
if - elseif - else - end if
Test variable expressions
if bit - else if bit - else - end if
Test bit expressions
switch - case - default - ends
Select based on variable
for - next
Loop. test variable
while- endw
Loop. test variable
The increment and decrement operators (+ + and --)
operate on a single operand.
repeat - until
Table 2. Assignment Operators With Examples
and Functions
repeat - until bit
break
Exit control block
Operator
Example
Function
continue
Skip to top of block
A= B
A+-B
goto LABEL
Branch to label
< ->
A<->B
Contents of A and B are exchanged
+=
A+= B
A+-A+B
A-= B
A+-A-B
*=
AX *= B
AX+-AX*B
1=
AX
&=
A&= B
1=
A 1= B
A .... A I B (logical OR)
=
A"= B
A .... A "B (logical XOR)
»=
A> >=B
(CY+-Ao.An_1+-An.....Amax+-O) x B times
«=
A< < =B
(CY+-Amax.An+ 1+-An....Ao+-O) x B times
++
A++
A+-A+l
A-
A +- A-I
1=
C
AX+-AX/C
A .... A & B (logical AND)
Loop. test variable
Loop. test bit
Loop. test bit
Variable and Bit Expressions
Variable expressions for tests consist of a single value.
comparison between two variables. or a logical combination of comparisons. Bit expressions test individual
bits. Table 4 shows examples of comparisons. The
allowable expressions using variables are shown in
table 5.
5
NEe:
RA78K2
Table 4. Examples of Variable Expression
Comparisons
Comparison
Meaning
if ( A)
True if A is non-zero
if (A < B)
True if A is less than B
if «A < B) && (A > Cll
True if A is less than B and greater than C
if_bit ( P3.2 )
True if bit 2 of P3 is 1
if_bit (IP3.2 )
True if bit 2 of P3 is 0
Table 5. Expressions and Examples
Expression
Example
Primary
(A)
Term
(A <= B)
Term &&Term
( (A< B) && (A> C) ) (logical AND)
Term II Term
( (A= = C) II (A= = B) ) (logical OR)
A primary value for a variable expression is a register
name or defined symbol. A term consists of two primary values compared with a binary operator. Table 6
lists the supported binary operators and their meanings.
Table 6. Binary Operators
Binary Operator
Meaning
Equal
!=
>
Not equal
Greater than
> =
Greater than or equal to
<
Less than
< =
Less than or equal to
Bit expressions test individual bits of registers, ports,
or memory locations. Table 7 shows the acceptable
forms of bit expressions.
Table 7_ Bit Expressions and Examples
Bit Expression
Bit primary
Example
(P2.1 )
(!CY)
Bit primary && Bit primary
(AO &&CY)
(P2.211 CY)
A Bit_primary can be either a reserved word bit identifier, such as a bit of a register or port (P2.1, Cy), or a bit
definition symbol (SBO EQU P2.2).
6
ST78K2 Operation and Controls
ST78K2 is invoked by specifying the name of the source
file, followed by optional controls.
Example:
C> ST78K2 ABC.SRC -OXYZ = 3
ST78K2 reads the specified source file and produces an
output assembly language file, which can be input to
RA78K2. The output file contains all lines provided in
the input source file, plus those generated by ST78K2.
Lines containing no statements for the structured
assembler are passed through unchanged. Lines with
structured assembly statements are placed in the
output preceded by a semicolon. RA78K2 treats these
lines as comments. These commented lines are then
followed by the code generated by ST78K2.
The controls for ST78K2 are specified in the preprocessor command line or in a parameter file invoked in the
command line. Table 8 lists the ST78K2 preprocessor
controls and functions.
Table 8_ ST78K2 Preprocessor Controls
Control
Function
-Ofilename
Specify name of output assembly source file
-Ffilename
Specify name of parameter file to be read
-Efilename
Specify name of error listing file
-Dsymbol[= value]
Define a symbol (like #define in code)
-I[d:] [directory]
Define path for include file
-WTnl,n2,n3
Define TAB settings for generated code
-SCcharacter
Defines word symbol last character
The -0 option allows the name of the output file to be
specified. If not specified, the output file name defaults
to the name of the input source file with the extension
.ASM.
The -F option allows a parameter file to be specified,
which will be read by ST78K2. This parameter file can
contain a list of controls to be given to ST78K2, instead
of or in addition to those specified on the command
line.
The -E option specifies the name of the error listing file.
The error file contains the file name, error number,
description of error and the line containing the error. If
the -E option is not specified, the error file name
defaults to the name of the input source file with the
extension .EST.
The -0 control allows a symbol to be defined on the
command line, with an optional value provided. If a
symbol is defined but no value specified, the value
defaults to 1. If the source file contains a #define
NEe
directive which specifies a variable with the same name
as the -D control, the value on the command line will
override the value in the #define directive.
The -I control specifies a drive or directory other than
the current drive and directory to search for include
files.
The -WT control specifies the number of TAB charactersto insert before labels, instruction mnemonics, and
instruction operands generated by ST78K2. This allows
clear separation of assembly language instructions
coded in the source file from those generated by
ST78K2.
The -SCcharacter control specifies the character used
as the last character in a word symbol. The character
must be a letter of the alphabet or the @, _ or ? This
allows ST78K2 to distingush between word and byte
operations. Symbols ending in this character are
treated as word symbols and will generate a word
operation (e.g. MOVW). If the -SC option is not specified, ST78K2 assumes that a symbol ending with the
character ''P'' or "p" is a word symbol.
RA78K2
License Agreement
RA78K2 is sold under terms of a license agreement
included with the assembler. The accompanying card
must be completed and returned to NEC Electronics
Inc. to register the license. Software updates are provided free to registered users for one year.
Documentation
For further information on source program formats,
assembler operation, and actual program examples,
refer to the following manuals supplied with the RA78K2
package. Additional copies may be obtained from NEC
Electronics Inc.
• RA78K Series Assembler Package, Language Manual
• RA78K Series Assembler Package, Operation Manual
• RA78K Series Structured Assembler Preprocessor,
User's Manual
IBM PC, PC/XT. and PC AT are registered trademarks of International
Business Machines Corporation.
Emulator Controller Program
Absolute object files produced by the RA78K2 relocatable assembler package can be debugged by using the
appropriate NEC standalone in-circuit emulator. NEC
emulator controller programs allow communication
with the emulator through an RS-232C serial line. An
emulator controller program can run on the IBM PC®,
PCIXT®, or PC AT® under MS-DOS and is provided with
the in-circuit emulator at no extra charge.
..
These emulator controller programs provide the following features:
• Uploading and downloading of object and symbol
files
• Symbolic debugging capability
• Complete emulator control from host console
• On-line help facilities
• Macro command file capabilities
• Host system directory and file display
• Disk storage of debug session
• Storage of last 20 commands for recall
7
RA78K2
8
NEe
IE-78310A-R
In-Circuit Emulator
for the pPD78312A Family
NEe
NEG Electronics Inc.
September 1993
Description
o Line assembler/disassembler
The IE-78310A-R is an in-circuit emulator providing both
hardware emulation and software debugging capabilities for the pPD78312A family of single-chip microcontroller. Real-time and single-step emulation, combined
with sophisticated memory mapping features, breakpoints, and trace capabilities, create a powerful debugging environment. A line assembler/disassembler, full
register and memory control, symbolic debugging, and
complete upload/download capabilities simplify the
task of debugging hardware and software.
o Symbolic debugging
-2000 symbols available
-IEEE-796 bus memory expansion slot for 32K
additional symbols
o CMOS latch-up warning and protection
o Eight external sense clips
o Self-diagnostic command
o Stand-alone mode or system mode with host
control program
Features
Equipment Supplied
o 12-MHz operating frequency
The IE-78310A-R package includes the following:
o Real-time and single-step emulation capability
o IE-78310A-R emulator frame
o User-specified breakpoints
- Logical OR of up to four sets of break conditions
Opcode fetch count
External sense clips condition
Emulation time
Logical AND of addresses, data values, CPU
controls, and loop count
o Self-check board
o Sophisticated trace capabilities
-Instruction, frame, or macro service display
- 2K x 44-bit trace buffer
- Address, control, data, and port trace features
o Powerful memory mapping feature
-64K bytes of RAM mappable in 256-byte blocks
- Up to 16K bytes of high-speed internal RAM for
pPD78312A ROM emulation
o Emulation board
o Break board
o ControVinterface board
o Shrink DIP target probe
o VSP target probe
o external sense clip unit
o System diskette
Ordering Information (Also, see selection guide.)
Part Number
Description
IE-78310A-R
In-circuit emulator for pPD78312A family
EP-78310CW
Emulator probe for 64-pln shrink DIP
package(shipped with IE-78310A-R)
EP-78310GQ
Emulator probe for 64-pin QUIP
package(shipped with IE-78310A-R)
EP-78310L
Emulator probe for 68-pin PLCC package
(optional)
EP-78310GF
Emulator probe for 64-pin QFP package
(optional)
RA78K3-D52
Relocatable assembler package for 78K3
product line of microcontrollers (optional)
CC78K3-D52
C compiler package for 78K3 product line of
microcontrollers (optional)
IE-78310A-R with Emulator Probe
50250
--
IE·7831 OA·R
2
NEe
NEe
NEG Electronics Inc.
IE-78327-R
In-Circuit Emulator
for the pPD78322 Family
September 1993
Description
The IE-78327-R is an in-circuit emulator providing both
hardware emulation and software debugging capabilities for the pPD78322 family of single-chip microcontrollers. Real-time and single-step emulation, combined with sophisticated memory-mapping features,
breakpoints, and trace capabilities, create a powerful
debugging
environment.
A
line
assembler/
disassembler, full register and memory control, symbolic debugging, and complete upload/download capabilities simplify the task of debugging hardware and
software.
The IE-78327-R-EM is an optional emulation board
available to upgrade the 75X or 78K product lines of
in-circuit emulators to have functions equivalent to
IE-78327-R.
Features
o 16-MHz operating frequency
o Real-time and non-real-time emulation
o Sophisticated break events:
- Logical OR of up to six events with pass count
Logical AND of addresses, data values, CPU
status, and external sense clips five to eight
data (four bus cycle events)
External sense clips one to four data
Executed instruction address (four addresses)
- Sequential enable for bus cycle events
o Sophisticated trace capabilities
- Three trace modes: unconditional, qualified, and
sectional
- Traces main and internal CPU bus activity and
external sense clip activity or time between
trace frames
-Store specified memory/register/SFR contents in
trace buffer
- 8K x 88-bit trace buffer
-Instruction or frame display
- Trace search capability
-Specify trigger point at beginning, middle, or
end of trace buffer
50357
o Internal data RAM sampling
- Up to 2000 three-word samples
- Sample frequency: 0.4, 0.6, 0.8, or 1 to 10,000 ps
o Program Coverage
- Display map of memory space containing object
code
- Display map of object code that has been
executed
- Display percentage of executed instructions to
total instructions in an area
o Emulation timer and instruction counter
o Debug activities during real-time emulation
- Display trace buffer
- Display data sampled from internal RAM
- Modify trace conditions
- Modify trace event conditions
- Restart trace
o Powerful memory mapping:
56K bytes of RAM for internal ROM, turbo access
manager memory, or off-chip memory emulation
o Line assembler/disassembler
o Symbolic debugging: 2000 symbols maximum
o Save/restore in-circuit emulator settings to/from
disk
o CMOS latch-up warning and protection
o Eight external sense clips on emulator probe
o Host control program for IBM PC®, PCIXT®,
PC/AT®, or compatible
o Centronics parallel interfaces for optional highspeed program download and printer
IBM PC, PC/XT, and PC/AT are registered trademarks of International
Business Machines Corporation.
-
I
NEe
IE·78327·R
Equipment Supplied
The IE-78327-R package includes the following:
o IE-78327-R emulator frame
o IE-78327-R-EM emulation board
o IE-78327-R-BK break board
o Control/trace board
o Controller software program
Ordering Information (Also, see selection guide.)
Part Number
Description
IE-78327·R
In-circuit emulator for IlPD78322 family
IE-78327 -R-EM
Emulation board included in IE-78327 package
(separately purchased to upgrade 75x or 78K
product line emulators to have functions
equivalent to IE-78327-R)
IE-78330-R-BK
Break board (separately purchased to upgrade
75x or 78K product line emulators to have
functions equivalent to IE-78327-R)
EP-78320GF-R
Emulator probe for 80-pin LCC (optional)
EP-78320GJ-R
Emulator probe for 74-pin QFP (optional)
(includes one EV-9200G-74 socket adapter)
EP-78320L-R
Emulator probe for 58-pin PLCC package
(optional)
EP-78327CW-R
Emulator probe for 54-pin plastic shrink DIP
(optional)
EP-78327GF-R
Emulator probe for 54-pin plastic QFP
(optional)
EV-9200G-54
Five socket adapters; converts 54-pin LCC
probe tip to 54-pin QFP device footprint.
EV-9200G-74
Five socket adapters; converts 74-pin probe tip
to 74-pin OFP device footprint (optional).
EV-9200G-SO
Five socket adapters; converts SO-pin LCC
probe tip to 80-pin QFP (14x20) device footprint
(optional).
RA78K3-D52
Relocatable assembler for K3 product line of
microcontrollers (optional)
CC78K3-D52
C compiler for K3 product line of
microcontrollers (optional)
2
IE·78327·R In·Circuit Emulator
NEe
NEC Electronics Inc.
IE-78350-R
In-Circuit Emulator
for the I'PD78352/356 Families
September 1993
Description
The IE-78350-R is an in-circuit emulator providing both
emulation and software debugging capabilities for the
NEC J.lPD78352 and J.lPD78356 families of single-chip
microcontrollers. Real-time and single-step emulation,
combined with sophisticated memory-mapping features, break pOints, and trace capabilities, create a
powerful debugging environment.
The IE-78350-R-EM1 is a separately sold, I/O emulation
board used with the IE-78350-R development system
for J.lPD78350 or J.lPD78352 16/8-bit single-chip microcontrollers.
The IE78355-R-EM1 is a separately sold, I/O emulation
board used with the IE-78350-R development system
for J.lPD78355, J.lPD78P355, and J.lPD78356 16/8-bit
single-chip microconputers.
Features
o 25-MHz max operating frequency
o Real-time and non-real-time emulation
o Sophisticated break events:
- Logical OR of up to six events
Pass count
External sense clips (5-8) data (four bus cycle
events)
External sense clips (1-4) data
Executed instruction address (four addresses)
Logical AND of addresses, data values, and CPU
status
- Sequential enable for bus cycle events
o Sophisticated trace capabilities
- Three trace modes: unconditional, qualified, and
sectional
- Traces main and internal CPU bus activity and
external sense clip activity or time between
trace frames
- Store specified memory/register/SFR contents in
trace buffer
- 8K x 88-bit trace buffer
-Instruction or frame display
- Trace search capability
-Specify trigger point at beginning, middle, or
end of trace buffer
o Internal data RAM sampling
- Up to 2000 three-word samples
- Sample frequency: 0.4, 0.6, 0.8, or 1 to 10,000 J.ls
50612
o Program Coverage
- Display map of memory space containing object
code
- Display map of object code that has been
executed
- Display percentage of executed instructions to
total instructions in an area
o Emulation timer and instruction counter
o Debug activities during real-time emulation
- Display trace buffer
- Display data sampled from internal RAM
- Modify trace conditions
- Modify trace event conditions
- Restart trace
o Powerful memory mapping:
56K bytes of RAM for internal ROM, turbo access
manager memory, or off-chip memory emulation
o Line assembler/disassembler
o Symbolic debugging: 2000 symbols maximum
o Save/restore in-circuit emulator settings to/from
disk
o CMOS latch-up warning and protection
o Eight external sense clips on emulator probe
o Host control program for IBM PC®, PC/XT®,
PC/AT®, or compatible
o Centronics parallel interfaces for optional highspeed program download and printer
~
..
IBM PC, PC/XT, and PC/ATare registered trademarks of International
Business Machines Corporation.
NEe
IE-78350-R
Ordering Information (Also, see selection guide.)
Part Number
Description
IE-78350·R
In-circuit emulator for jJPD78352/356 families
IE-78350-R-EMl
I/O emulation board for IE-78350-R (optional)
combined with IE-78350-R to emulate jJPD78352
family
IE-78355-R-EMl
I/O emulation board for IE-78350-R (optional)
combined with IE-78350-R to emulate jJPD78356
family
IE-78350-R-EM
Emulation board for IE-78350-R (included with
IE-78350-R)
EP-78240GC-R
Emulator probe for 64-pin QFP (optional)
(includes one EV-9200GC-64 socket adapter)
EP-78355GC-R
Emulation probe for lOO-pin QFP (optional)
(includes one EV-9500GC-l00 socket adapter)
EV-9200GC-64
Five socket adapters; converts 64-pin LCC
probe tip to 64-pin QFP device loot print
(optional)
EV-9500GC-l00
One socket adapter; 100-pin PGA to lOO-pin
QFP (optional)
EV-950l GC-l00
One socket adapter; l20-pin LCC to lOO-pin
PGA receptacle (optional)
RA78K3-D52
Relocatable assembler for 78K3 product line
(optional)
CC78K3-D52
C compiler for 78K3 product line
Equipment Supplied
The IE-78350-R package includes the following:
o IE-78350-R emulator frame
D
IE-78350-R-EM emulation board
D
Break board
o Control/trace board (fixed in the IE-78350-R)
o System diskette
2
IE-78350-R In-Circuit Emulator
EB-78320-PC
Evaluation Board
for the JlPD78322 Family
NEe
NEG Electroni cs Inc.
September 1993
Description
o Line assembler and disassembler
The EB-78320-PC is an evaluation board for the NEC
J,lPD78322 family of 8-/16-bit, single-chip microcontrollers. The EB-78320-PC provides a simple way to evaluate the capabilities of the J,lPD78322 family in an application without having to build a prototype.
o RS-232C serial interface for host computer
The EB-78320 features 32K bytes of static RAM for
evaluation programs, an RS-232C communication
port, and a powerful on-board monitor. Evaluation
programs can be downloaded from a host computer or
created directly on the board using the line assembler.
Programs can be executed in real-time with or without
breakpoints or one instruction at a time. Commands
are available to display or change memory, general or
special function registers, and to disassemble code.
A controller program controls the EB-78320 directly
from the console of an IBM PC®, PCIXT®, PC AT®, or
compatible host computer using an RS-232C serial
interface.
o Host control software for IBM PC®, PCIXT®, PC
AT®, or compatibles
IBM PC, PC!XT and PC AT are registered trademarks of International
Business Machines Corporation.
Ordering Information (Also,
o J,lPD78320 evaluation board
guide.)
Description
EB-78320-PC
/lPD78320 evaluation board (IBM PC based)
EP-78320GF-R
Emulator probe for eO-pin OFP package
(optional)
EP-78320GJ-R
Emulator probe for 74-pin OFP package
(optional)
EP-78320L-R
Emulator probe for 68-pin PLCC package
(optional)
EV-9200G-74
Five socket adapters; converts 74-pin probe tip
to 74-pin OFP device footprint (optional).
EV-9200G-80
Five socket adapters; converts SO-pin to SO-pin
OFP (14x20)device footprint (optional).
Features
o 16-MHz maximum operating frequency
see selection
Part Number
Equipment Supplied
The EB-78320-PC package consists of the following:
o 32K bytes of static RAM
o Real-time and single-step execution
o Four parallel or sequential breakpoints
o Display/change memory and general registers
o Display/change special function registers
o User program upload/download capability
o Symbolic debugging support
EB-78320-PC Evaluation Board
50259
•
•
•
•
EB-78320-PC evaluation board
EB-78320-PC user's manual
System disk for IBM PC
AC/DC converter power supply
• Battery holder and mounting hardware
• Warranty policy and registration card
~...
. . . .~
NEe
EB·78320·PC
Block Diagram
PortsO,2,
3,7,S
AddrassBus
'>I
AS-A15
--"
",PD78320
ADo-A07
JE
I
f
OscIllator
"
I
PBO·PB7
~L
r-
f
.;:.
PAo.f'A7
)1PD71P301
Turbo Access
Manager
--y
"PD71055
Ff
"
,
'I
1
...
~r
CoMectors
Addres&'Data Bua
)I
Buffer
r---JL
AddrassBus
U
JJ
l"p~~~11 I'P:~ II
LJr lr 11' 11 11
PALs
II
Buffer
II
AO-A7
Lstdl
"i i"
II U
I'PD71051
RS·232·C
Driverf
Ra08lvar
RS·232·C
Connector
I
"i
II
49NR-666B(9I98)
2
EB· 78350·PC
Evaluation Board
for the pPD78352 Family
NEe
NEe Electronics Inc.
September 1993
Description
The EB-78350-PC is an evaluation board for the NEC
j.lPD78352 family of 8-/16-bit, single-chip microcontrollers. The EB-78350-PC provides a simple way to evaluate the capabilities of the j.lPD78352 family in an application without having to build a prototype.
The j.lPD78350/352 can be emulated by connecting a
separately purchased probe to the EB-78350-PC.
The EB-78350-PC features 32K bytes of static RAM for
evaluation programs, an RS-232C communication
port, and a powerful on-board monitor. Evaluation
programs can be downloaded from a host computer or
created directly on the board using an on-line assembler. Programs can be executed in real time with or
without breakpoints or one instruction at a time. Commands are available to display or change memory,
general or special function registers, and to disassemble code.
A controller program controls the EB-78350-PC directly
from the console of an IBM PCI!>, PCIXTI!>, PC/ATI!>, or
compatible host computer using an RS-232C serial
interface.
Equipment and Documentation Supplied
D
EB-78350-PC evaluation board
D
EB-78350-PC user's manual
D
System disk for IBM PC
D
AC/DC converter power supply
D
Battery holder and mounting hardware
D
Warranty policy and registration card
Ordering Information (Also, see selection guide.)
Part Number
Description
EB-78350-PC
IlPD78350/352 evaluation board
EP-78240GC-R
Emulator probe for 64-pin OFP (optional)
(includes one EV-9200GC-64 socket adapter)
EV-9200GC-64
Five socket adapters; converts 64-pln LCC probe
tip to 64-pin OFP device footprint (optional).
EB-78350-PC Evaluation Board
Features
D
25-MHz maximum operating frequency
D
j.lPD78350/352 evaluation board
D
32K bytes of static RAM
D
Real-time and single-step execution
D
Four parallel or sequential breakpoints
D
Display/change memory and general registers
D
Display/change special function registers
D
User program upload/download capability
D
Symbolic debugging support
D
Line assembler and disassembler
D
RS-232C serial interface for host computer
D
Host control software for IBM PC, PCIXT, PC/AT or
compatibles
IBM PC, PC/XT and PC/AT are registered trademarks of International
Business Machines Corporation.
50614
•
EB-78350-PC
2
NEe
CC78K3
C Compiler for the
pPD78K3 Product Line
NEe
NEe Electronics Inc.
September 1993
Description
Figure 1. CC78K3 Functional Diagram
The CC78K3 C compiler is an ANSI standard C crosscompiler for the NEC pPD78K3 product line of microcontrollers. The CC78K3 (figure 1) converts AN SI standard C source code into NEC format object module or
assembly language source files. During compilation,
an optional optimizer can be invoked to optimize the
object code for size and/or execution speed.
In addition, CC78K3 supports extended functions for
pPD78K3 code generation. These extended functions
allow the C compiler to take advantage of many powerful features in the pPD78K3 microcontro"ers to decrease object code size and improve program execution speed.
The relocatable object file produced by the CC78K3
can be converted into an absolute object file by the
linker program and object converter program contained in the RA78K3 relocatable assembler package.
The resulting ASC" hexadecimal format absolute object file then can be debugged using an NEC in-circuit
emulator or evaluation board.
Features
o ANSI standard C compiler
o Extended functions for optimized pPD78K3 code
generation
o Various optimization options for code size and/or
execution speed
o Legal C code verification
o Outputs NEC format object module or assembly
source file
o Run-time error checking
o Outputs debug information
o ROMable object file creation
o User selectable and directable output files, list,
and full cross-reference files
o Extensive error reporting
o Built-in help facility
o Runs under MS-DOS® operating system
MS-DOS is a registered trademark of Microsoft Corporation
50621
C Source
Module
File
Parameter
File
t
L",
Temporary
Ale
f
Assembler
Source
Module
Fae
Include
Ale
~
CC78K3
CCompller
~
/~
Object
Module
Ale
~
Preprocess
UsIAle
~
-.'t
Error
UsIAIe
Cross
Reference
LIsIAle
Ordering Information
Part Number
System
Description
CC78K3-D52
MS-DOS
5-1/4-inch, double-density floppy
diskette
CC78K3 Extended Functions
• Register variables can be stored in the registers and
Saddr area
• Saddr area usage for variables
• Direct peripherals access with SFR names
• Saddr area usage for function arguments and automatic variables
• Functions can be called using the CALLT table
• Functions can be stored in the CALLF area
• Bit data type
• In-line assembly language
• Interrupt functions
- Generate interrupt vector table
- Disable/enable interrupts
• Vector/CALLT table address change
_I,.
'i
NEe
CC78K3
Compiler Options
The CC78K3 C compiler supports the following options
during compilation:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Target chip selection
Parameter file specification
Macro name definition
Include files search path specification
Symbol length extension
Symbol name conversion to uppercase
Outputs debug information
Generates
Object fi Ie
Assembler source file (with/without C source)
Cross-reference list file
Error list file (with/without C source)
Preprocess list file
Listing format control
ROMabie processing
Optimization option selection
Run-time error check selection
Temporary directory specification
Warning level selection
Outputs compilation status information
C Library Functions
The CC78K3 C compiler library includes most of the
important C library functions that apply to PROMbased embedded systems. A" library functioris reside
in the library files supplied. Header files that declare
the set of library functions are also included.
The following library functions are available:
1/0 Functions
sprintf
sscanf
Character Functions
isalpha
isupper
isalnum
isxdigit
isprint
isgraph
toupper
tolower
toascii
islower
isspace
iscntrl
_toupper
isdigit
ispunct
isascii
_to lower
String Functions
strlen
strcpy
strncat
strcmp
strrchr
strpbrk
strstr
strtok
atol
atoi
ultoa
strncpy
strncmp
strspn
strtOI
itoa
strcat
strchr
strcspn
strtoul
Itoa
rea"oc
memcpy
memset
free
memmove
Memory Functions
malloc
ca"oc
brk
sbrk
memcmp
memchr
Program Control Functions
10ngjmp
setjmp
abort
exit
atexit
Mathematical Functions
labs
abs
div
Idiv
rand
srand
Special Functions
qsort
bsearch
va_arg
va_end
strerror
va_start
License Agreement
CC78K3 is sold under terms of a license agreement
included with the compiler. The accompanying card
must be completed and returned to NEC Electronics
Inc. to register the license. Software updates are provided free to registered users for one year.
Documentation
For further information on source program formats, C
compiler, and actual program examples, refer to the
following manuals supplied with the compiler. Additional copies may be obtained from NEC Electronics
Inc.
• CC78K Series C Compiler for Language
• CC78K Series C Compiler for Operation
2
NEe
NEG Electronics Inc.
RA78K3
Relocatable Assembler Package
for the pPD78K3 Product Line
September 1993
Description
The RA78K3 relocatable assembler package converts
symbolic source code for the pPD78K3 product line of
8/16-bit, single-chip microcontrollers into executable
absolute address object code. The RA78K3 package
consists of six separate programs: assembler
(RA78K3), linker (LK78K3), hexadecimal format object
converter (OC78K3), librarian (LB78K3), list converter
(LCNV78K3), and structured assembler (ST78K3).
RA78K3 translates a symbolic source module into a
relocatable object module. The assembler verifies that
each instruction assembled is valid for the target microcontroller specified at assembly time and produces
a listing file and a relocatable object module.
Features
o Absolute address object code output
o User-selectable and directable output files
o Macro definitions
o Branch optimization
o Conditional assembly
o Extensive error reporting
o Powerful librarian
DC-like structured assembly statements
o Runs under MS-DOS® operating system
Ordering Information
LK78K3 combines multiple relocatable Object and library modules and converts them to a load module.
OC78K3 converts a load module into an ASCII hexadecimal format absolute object code file.
Part Number
System
Description
RA78K3-D52
MS-DOS
5-1/4-inch, double-density
floppy diskette
LB 78K3 allows commonly used relocatable object
modules to be stored in one file and Ii nked into multiple
programs, greatly increasing programming efficiency.
When a library file is included in the input of the linker,
the linker extracts from the library file only those
modules required to resolve external references and
links them with the other modules.
Program Syntax
LCNV78K3 allows relocatable list files to be converted
into absolute list files.
The ST78K3 structured assembler preprocessor is a
companion program to the RA 78K3 relocatable assembler for the NEC pPD78K3 product line of microcontrollers. ST78K3 converts a source code file containing
C-like structured assembly statements into a pure
assembly language source file, which then can be
assembled with RA78K3.
The RA78K3 assembler package also includes an ECC
generator program (ECCGEN), which generates and
applies Error Correcting Code (ECC) to the hexadecimal object module file.
An RA78K3 source module consists of a series of code,
data, or bit segments. Each segment consists of statements composed of up to four fields: symbol, mnemonic, operand, and comment.
The symbol field may contain a label, whose value is
the instruction or data address, or a name that represents an instruction address, data address, or constant. The mnemonic field may contain an instruction
or assembler directive, The operand field contains the
data or expression for the specified instruction or
directive, The comment field allows explanatory comments to be added to a program,
Character constants are translated into 7-bit ASCII _
codes. Numeric constants may be specified as binary,
octal, decimal, or hexadecimal. Arithmetic expressions
may include the operators +, -, *, /, MOD, OR, AND,
NOT, XOR, EO, NE, LT, LE, GT, GE, SHR, SHL, LOW,
HIGH, " (), and character constants.
Macro Definition
MS-DOS is a registered trademark of Microsoft Corporation,
50251-1
RA78K3 allows the definition of macro code sequences
with up to five parameters, LOCAL symbols, and special repeated code sequences, The macro code sequence differs from a subrouti ne call: the invocation of
a macro in the source code results in the direct replacement of the macro call with the defined code sequence.
.'
'
NEe
RA78K3
Assembler Directives
Assembler directives give instructions to the assembler. They are not translated into machine code during
assembly. Basic assembler directives include storage
definition and allocation directives (DB, Ow, OS, DBI1);
symbol directives (EQU, SE1); and location counter
control directive (ORG). Program control directives
include segment directives (CSEG, DSEG, BSEG,
ENDS); linkage directives (NAME, PUBLIC, EXTRN,
EXTBI1); macro directives (MACRO, LOCAL, REPT, IRP,
EXITM, ENDM); automatic BR instruction directive
(BR); register assignment directive (RSS); and assembly termination directive (END).
Figure 1. Relocatable Assembler Functional
Diagram
• Processor selection
• Output object creation selection
• Output list file selection
• Listing format controls
• Optimization selection
• Work file drive specification
General controls are specified in the source program
as follows:
•
•
•
•
•
Inclusion of other source files
Page eject
Generation/suppression of listing
Listing titles
Conditional assembly controls
The listing file contains either the complete assembly
listing or only the lines with errors, and a symbol or
cross-reference table. The symbol table shows all defined symbols in alphabetical order with the types,
attributes, and the values initially assigned to them.
The cross-reference table contains all defined symbols
and the numbers of all statements referring to them.
The object file contains the relocatable object module.
This is an NEC proprietary relocatable object module
format.
If the optimization option is chosen, the assembler will
generate the most efficient code by converting, where
possible, three-byte absolute branches into two-byte
relative branches.
Linker
The LK78K3 linker (figure 2) combines several relocatable object modules, resolving PUBLIC/EXTRN refer-
2
File
~
I-~
RA78K3
Temporary
WorkRles
Relocatable
Assembler
Rle
Assembler Controls
The RA78K3 assembler (figure 1) has two types of
controls. Primary controls are specified in the assembler command line or at the beginning of the source
module as follows:
~
--
Source
Module
File
~
ObJect
Module
File
~
t
Assembler
UsIRIe
Error
UsIRle
ences between modules, to create a load module. This
output module contains both absolute object code and
symbol information. The linker will also search library
files for required modules to resolve external references. The linker controls for LK78K3 can be specified
in either the command line or in a parameter file.
Figure 2. Linker Functional Diagram
Ubrary
Module
FOe
r-:::l
~
ObJect
Module
Rle1
ObJect
Module
Rlen
~l
Parameter
Rle
1----+
LK78K3
Unkar
I---
Temporary
Work Rles
1
Load
Module
File
Unkar
UsIRle
G
UsIRIe
NEe
RA78K3
The programmer can specify the starting address and
order for code/data/stack segments and protect areas
of memory from being assigned.
Figure 4. Ubrarian Functiona' Diagram
Object Converter
The OC78K3 object converter (figure 3) outputs two
files: an absolute load file in ASCII hexadecimal format,
which can be downloaded to a PROM programmer, and
a symbol file for the symbolic debugger. The programmer can also specify an error list file for error logging.
~
________
~~( T.~~~
)
Figure 3. Object Converter Functiona' Diagram
Load
Module
FRe
B-
~
Figure 6. Ust Converter Functiona' Diagram
File
OC7BK3
Hexadecimal Fonnat
ObJec! Converter
..
~
,
Symbol
Table
FOe
Hexadecimal
Object
Code File
Error
list Rle
Librarian
The LB78K3librarian (figure 4) creates and maintains
library files containing relocatable object modules.
This reduces the number of files to be linked together
by storing several modules in a single file. This pro·
vides an easy way to link frequently used modules into
programs. Modules can be added to, deleted from, or
replaced within a library file; or the contents of the
library file can be listed.
-
List Converter
The LCNV78K3 list converter (figure 5) converts a
relocatableassembly list file into an absolute assembly list file, which contains absolute addresses and
symbol values.
B3NR-7&31A
3
NEe
RA78K3
Structured Assembler
Summary Of Structured Language
The ST78K3 (figure 6) will convert a structured assembly statement into one or more JlPD78K3 assembly
language instructions that perform the desired operation. Because ST78K3 converts only the structured
assembly statements and not JlPD78K3 assembly language instructions, a structured source program can
include a combination of JlPD78K3 structured assembly statements and assembly language.
A line of source code for ST78K3 contains either a
structured assembly statement or a pPD78K3 assembly language statement. pPD78K3 assembly language
statements (pPD78K3 instructions, RA78K3 directives,
or RA78K3 controls) pass through ST78K3 without
change.
ST78K3 enables the assembly language programmer
to use some of the structures and syntax of higher-level
languages such as the C language. This improves
program readability and reliability, and increases programmer productivity.
Features of the ST78K3
o Control structures for conditions, looping, and
switch-case
o Preprocessor directives for conditional code
generation
DC-like representation of comparison operations
DC-like representation of assignment/arithmetic
operations
o Increment and decrement operators
o Allows use of all pPD78K3 mnemonics, registers,
and features
Figure 6. Structured Assembler Preprocessor
Functional Diagram
RA78K3
~PD78K3
Relocatable
Aseembler
49NF>68M
4
Structured assembly statements consist of preprocessor directives, assignment statements, and control
statements. These statements are entered one per line,
and are terminated by a line feed character. An optional
comment may follow a semicolon at the end of the
statement; all text following a semicolon is ignored by
ST78K3.
Preprocessor directives cause ST78K3 to include or
omit portions of code. Assignment statements cause
ST78K3 to generate one or more pPD78K3 assembly
language instructions to alter the contents of a register
or variable. Control statements cause ST78K3 to generate the necessary instructions to test conditions and
change control flow based on those conditions.
NEe
RA78K3
I
Preprocessor Directives
ST78K3 preprocessor directives set and test variables,
allowing conditional processing of code; include external files; and map instructions to pPD78K3 CALLT table
reference instructions. Table 1 lists the preprocessor
directives and their functions.
The increment and decrement operators (+ + and --)
operate on a single operand.
Table 2. Assignment Operators with Examples
and Functions
Operator
Example
Function
A= B
A-B
Table 1. Preprocessor Directives and Functions
< ->
A< -> B
Contents of A and B are exchanged
DIrectIve
Function
+=
A += B
A-A+ B
#define NAME value
Defines the variable NAME, set to the
supplied value.
#ifdef ABC
< statements>
#else
< statements>
#endif
#include "filename"
#defcallt @LABEL
CALL IIabel
#endcallt
If ABC has been defined as above, or on the
command line with the -D option, the first
set of statements is processed and the
second set ignored; if ABC has not been
defined, or defined as zero, the first set of
statements is ignored and the second set is
processed.
The named file is read from disk and
processed as if included in the source.
Whenever the instruction "CALL !laber' is
encountered in the source program, it is
replaced by "CALLT [@LABELI". The label
must be defined in the CALLT table.
Assignment, Increment, and Decrement
Statements
ST78K3 provides the ability to represent an assignment,
or an assignment with an arithmetic operation, in
C language syntax:
destination < assign-op> source
A-= B
A-A- B
'=
AX'= B
AX-AX'B
1=
AX/= C
AX ..... AX/C
&=
A&= B
A - A & B (logical AND)
1=
AI= B
A ..... A I B (logical OR)
-
A A= B
A - A AB (logical XOR)
»=
A»=B
(CY-Ao,An_1 .... An, ... ,Amax-O) x B times
«=
A«=B
(CY ....Amax,An+ l<-An,... ,Ao<-O)
++
A++
A-A+1
A--
A+- A-1
Control statements (table 3) allow conditions to be
tested. Based on the results of the test, blocks of code
are allowed to be executed or skipped. Reserved words
in the control statement define the start and end of
blocks of code and expressions to be evaluated.
Example:
The assignment operators (table 2) allow either simple
assignment or the combination of an assignment with
an arithmetic operation on the source and destination.
Examples:
else
=B
;Move contents of B register to A
+ = [HL] ;Add contents of memory at HL to A,
;store in A
Where an assignment requires an intermediate register
to hold the value being assigned, the register is designated by naming it in parentheses following the assignment operation.
B times
Control Statements
if( A
A
A
X
==
[HL])
P5 = B (A)
A= [HL]
A + = [HL]
A- = B
;The condition is tested.
;If A equals the content of memory
;at HL, this code is executed.
;Otherwise, this code is executed.
P5 = A
endif
Examples:
DATA1
BC &
= B (A)
=
;Store contents of B into memory at
;DATA1, using A as temporary storage
HL (XA) ;and BC with HL, store in BC,
;use XA as temp
5
I
NEe
RA78K3
Table 3. Control Statements and Function
Table 6. Binary Operators
Control Statement
Function
Binary Operator
if - elseif - else - endif
Test variable expressions
Meaning
Equals
itbit - elseitblt - else - end if
Test bit expressions
1=
Not equal
switch - case - default - ends
Select based on variable
>
Greater than
for- next
Loop, test variable
>=
Greater than or equal
while - endw
Loop, test variable
<
Less than
repeat - until
Loop, test variable
<=
Less than or equal
while bit - endw
Loop, test bi t
repeat - until_bit
Loop, test bit
break
Exit control block
continue
Skip to top of block
goto LABEL
Branch to label
Bit expressions test individual bits of registers, ports,
or memory locations. Table 7 shows the acceptable
forms of bit expressions.
Table 7. Bit Expressions and Examples
Bit Expression
Example
IBit primary
( ICY)
Bit primary II Bit_primary
( PO.2 II CY)
(PO.l )
Variable and Bit Expressions
Variable expressions for tests consist of a single value,
comparison between two variables, or a logical combination of comparisons. Bit expressions test individual
bits. Table 4 shows examples of comparisons. The
allowable expressions using variables are shown in
table 5.
Table 4. Examples of Variable Expression
Comparisons
Comparison
Meaning
if (A)
True if A is non-zero
if (A < B)
True if A is less than B
if ((A < B) && (A > Cj)
True if A is less than B and greater than C
itbit ( P1.2 )
True if bit 2 of PI is 1
if_bit (IP1.2)
True if bit 2 of PI is 0
Table 5. Expressions and Examples
Expression
Example
Primary
(A)
Term
(A <= B)
Term && Term
( (A< B) && (A> C) ) (logical AND)
Term II Term
( (A= = C) II (A= = B) ) (logical OR)
A primary value for a variable expression is a register
name or defined symbol. A term consists of two primary values compared with a binary operator. Table 6
lists the supported binary operators and their meanings.
6
A Bit_primary can be either a reserved word bit identifier, such as a bit of a register or port (PO.1, Cy), or a bit
definition symbol (SBO EQU PO.2),
ST78K3 Operation and Controls
ST78K3 is invoked by specifyi ng the name of the source
file, followed by optional controls. For example:
C> ST78K3 ABC.SRC -DXYZ= 3
ST78K3 reads the specified source file and produces an
output assembly language file, which can be input to
RA78K3. The output file contains all lines provided in
the input source file, plus those generated by ST78K3.
Lines containing no statements for the structured
assembler are passed through unchanged. Lines with
structured assembly statements are placed in the
output preceded by a semicolon. RA78K3 treats these
lines as comments. These commented lines are then
followed by the code generated by ST78K3.
NEe
RA78K3
The controls for ST78K3 are specified in the preprocessor command line or in a parameter file invoked in the
command line. Table 8 lists the ST78K3 preprocessor
controls and functions.
Table B. ST7BK3 Preprocessor Controls
Control
Function
-Ofilename
Specify name of output assembly source file
-Ffilename
Specify name of parameter file to be read
-Efilename
Specify name of error listing file
-Dsymbol[ = value]
Define a symbol (like #define in code)
-I[d:] [directory]
Define path for include file
-WTnl,n2,n3
Define TAB settings for generated code
-SCcharacter
Defines word symbol last character
The -0 option allows the name of the output file to be
specified. If not specified, the output file name defaults
to the name of the input source file with the extension
.ASM.
The -F option allows a parameter file to be specified,
which will be read by ST78K3. This parameter file can
contain a list of controls to be given to ST78K3, instead
of or in addition to those specified on the command
line.
The -E option specifies the name of the error listing file.
The error file contains the file name, error number,
description of error and the line containing the error. If
the -E option is not specified, the error file name
defaults to the name of the input source file with the
extension .EST.
The -D control allows a symbol to be defined on the
command line, with an optional value provided. If a
symbol is defined but no value is specified, the value
defaults to 1. If the source file contains a #define
directive which specifies a variable with the same name
as the -D control, the value on the command line will
override the value in the #define directive.
The -I control specifies a drive or directory other than
the current drive and directory to search for include
files.
The -WT control specifies the number of TAB characters to insert before labels, instruction mnemonics, and
instruction operands generated by ST78K3. This allows
clear separation of assembly language instructions
coded in the source file from those generated by
ST78K3.
The -SCcharacter control specifies the character used
as the last character in a word symbol. The character
must be a letter of the alphabet or the @, _ or ? This
allows ST78K3 to distinguish between word and byte
operations. Symbols ending in this character are
treated as word symbols and will generate a word
operation (e.g. MOVW). If the -SC operation is not
specified, ST78K3 assumes that a symbol ending with
the character ''P'' or "p" is a word symbol.
Emulator Controller Program
Absolute object files produced by the RA78K3 relocatable assembler package can be debugged with the
appropriate NEC standalone in-circuit emulator. NEC
emulator controller programs allow communication
with the emulator through an RS-232C serial line. An
emulator controller program can run on the IBM PC®,
PC/XT®, or PC AT® under MS-DOS and is provided with
the in-circuit emulator at no extra charge.
These emulator controller programs provide the following features:
•
•
•
•
•
•
•
•
Uploading/downloading of object and symbol files
Symbolic debugging capability
Complete emulator control from host console
On-line help facilities
Macro command file capabilities
Host system directory and file display
Disk storage of debug session
Storage of last 20 commands for recall
License Agreement
RA78K3 is sold under terms of a license agreement
included with the assembler. The accompanying card
must be completed and returned to NEC Electronics
Inc. to register the license. Software updates are provided free to registered users for one year.
Documentation
__
For further information on source program formats,
assembler operation, and actual program examples,
refer to the following manuals supplied with the RA78K3
package. Additional copies may be obtained from NEC
Electronics Inc.
• RA78K Series Assembler Package, Language Manual
• RA78K Series Assembler Package, Operation Manual
• RA78K Series Structured Assembler Preprocessor,
User's Manual
• ECC Generator, User's Manual
IBM PC, PC/XT, and PC AT are registered trademarks of International
Business Machines Corporation.
7
RA78K3
8
NEe
NEe
Soldering
NEe
Soldering
Section 7
Soldering
"PD78COO Product Line;
Soldering and Packaging Information
7-1
"PD78KO Product Line;
Soldering and Packaging Information
7-3
"PD78K2 Product Line;
Soldering and Packaging Information
7-5
"PD78K3 Product Line;
Soldering and Packaging Information
7-7
Soldering Conditions
7-9
NEe
Soldering
I'PD78COO Product Line; Soldering and Packaging Information
Package
Package Drawing
Recommended
Soldering Code (Note 1)
78C10ACW
64-pin SDIP
P64C-70-750A,C
WS60-00-1
78C10AGF-3BE
64-pin QFP
P64GF-100-3B8,3BE-l
1R30-00-1, VP15-00-1
64-pin QUIP
P64GQ-l00-36
WS60-00-1
68-pln PLCC
P68L-50A 1-1
IR30-00-1, VP15-00-1
78C11ACW-xxx
64-pin SDIP
P64C-70-750A, C
WS60-00-1
78C11AGF-xxx-3BE
64-pin QFP
P64GF-100-3B8,3BE-1
1R30-00-1, VP15-00-1, WS60-00-1
64-pin QUIP
P64GQ-100-36
WS60-00-1
Part Number
PPD78C14 Family
78C10AGF(A)-3BE
78C10AGQ..36
78C10AGQ(A)-36
78Cl0AL
78C10AL(A)
78C11AGF(A)-xxx-3BE
78C11AGQ..xxx-36
1R30-00-1, VP15-00-1
78C11AGQ(A)-xxx-36
78C11 AGQ-xxx-37
64-pin QUIP (straight)
P64GQ-100-37
78C11AL-xxx
68-pin PLCC
P68L-50A 1-1
1R30-00-1, VP15-00-1
WS60-00-1
78C11 AL(A)-xxx
78C12ACW-xxx
64-pin SDIP
P64C-70-750A,C
78Cl2AG-xxx-37
64-pin QUIP (straight)
P64GQ..100-37
78Cl2AG-xxx-36
64-pin QUIP
P64GQ..100-36
WS60-00-1
78Cl2AG(A)-xxx-36
78C12AGF-xxx-3BE
64-pln QFP
P64GF-100-3B8,3BE-l
1R30-CO-l, VP15-00-1, WS60-00-1
78C12AL-xxx
68-pin PLCC
P68L-50A 1-1
IR30-CO-1, VP15-00-1
78C12AL(A)-xxx
78C14AG-xxx-AB8
64-pln QFP
P64GC-80-AB8-2
IR30-107-1, VP15-107-1
78C14CW-xxx
64-pin SDIP
P64C-70-750A,C
WS60-00-1
WS60-00-1
78C14G-xxx-36
64-pln QUIP
P64GQ-1CO-36
78C14G-xxx-37
64-pin QUIP (straight)
P64GQ-1CO-37
78C14G-xxx-l B
64-pin QFP
P64G-l00-12, 1B-1
IR30-107-1, VP15-107-1
78C14GF-xxx-3BE
64-pln QFP
P64GF-l00-3B8, 3BE-l
IR30-107-1, VP15-107-1,
WS60-107-1
78C14L-xxx
68-pin PLCC
P68L-50Al-l
IR30-00-l, VP15-00-l
7-1
NEe
Soldering
I'PD78COO Product Line; Soldering and Packaging Information (cont)
Part Number
Package
Package Drawing
Recommended
Soldering Code (NOle 1)
PP078C14 Family (cont)
7SCP14CW
64-pin SOIP
P64C-70-750A,C
WS60-00-1
7SCP14G-36
64-pin QUIP
P64GQ-100-36
WS60-00-1
7SCP14G-37
64-pin QUIP (straight)
P64GQ-100-37
WS60-00-1
7SCP14GF-3BE
64-pin QFP
P64GF-100-3B8,3BE-1
78CP14L
68-pin PLCC
P68L-50A 1-1
VP15-162-1
78CP140W
64-pin CER SOIP w/window
P640W-70-750A
WseO-OO-1
78CP14R
64-pin CER QUIP w/window
P64R0-100-A
WseO-OO-1
78CP14G(A)-36
64-pin QUIP
P64GQ-100-36
WS60-00-1
78C17CW
64-pin SOIP
P64C-70-750A, C
WS60-00-1
78C17GF-3BE
64-pin QFP
P64GF-100-3BS,3BE-1
1R30-107-1, VP15-107-1, WseO-OO-1
PP078C18 Family
7SC17GF(A)-3BE
7SC17GQ-36
1R30-207-1, VP15-207-1,
WS60-207-1
64-pin QUIP
P64GQ-100-36
WS60-00-1
7SC17GQ(A)-36
C
/lP07SC1SCW-xxx
64-pin SOIP
P64C-70-750A,
78C17GF-xxx-3BE
64-pin QFP
P64GF-100-3B8,3BE-1
1R30-107-1, VP15-107-1,
WS60-107-1
64-pin QUIP
P64GQ-100-36
WS60-00-1
78CP18CW
64-pin SOIP
P64C-70-750A, C
WS60-00-1
78CP18GF-3BE
64-pin QFP
P64GF-100-3B8,3BE-1
1R30-107-1, VP15-107-1
G4-pin QUiP
P64GQ-l00 -36
WS60-00-1
78C17GF(A)-xxx-3BE
7SC17GQ-xxx-36
WS60-00-1
78C17GQ(A)-xxx-36
78CP18GF(A)-3BE
78CP1SCC-36
78CP1SGQ(A)-36
78CP180W
64-pin SOIP w/window
P640W-70-750A
78CP1SKB (Note 2)
64-pin ceramic LCC w/window
X64KW-100A-1
Notes:
(1) See soldering conditions table at the end of this section for
further information on NEC's soldering codes.
(2) Not intended for soldering; if soldering code is not listed, contact
NEC.
7-2
NEe
Soldering
p.PD78KO Product line; Soldering and Packaging Information
Part Number
Package
Package Drawing
Recommended
Soldering Code (Note 1)
64-pin plastic shrink DIP
P64C-70-750A, C
WS60-00-1
64-pin plastic QFP
P64GC-80-AB8-2
IR30-107-1, VP15-107-1,
WS60-107-1
64-pin plastic shrink DIP
P64C-70-750A, C
WS60-00-1
64-pin plastic QFP
P64GC-80-AB8-2
IR30-107-1, VP15-107-1,
WS60-107-1
64-pin plastic shrink DIP
P64-70-750A, C
WS60-00-1
64-pin plastic QFP
P64GC-80-AB8-2
IR30-107-1, VP15-107-1,
WS60-107-1
P64GC-80-AB8-2
1R30-162-1, VP15-162-1
P64DW-70-750A
Pin partial heating
64-pin plastic shrink DIP
P64C-70-750A, C
WS60-00-1
64-pln plastic QFP
P64GC-80-AB8-2
IR30-107-1, VP15-107-1,
WS60-107-1
PPD78002 Family
78001 BCW-xxx
78002BCW.xxx
78001 BGC-xxx-AB8
78002BGC-xxx-AB8
ppD7BOO2Y Family
78001 BYCW-xxx
78002BYCW-xxx
78001 BYGC-xxx-AB8
78002BYGC-xxx-AB8
PPD78014 Family
78011 BCW-xxx
78012BCW.xxx
78013CW.xxx
78014CW.xxx
78P014CW
78011 BGC-xxx-AB8
78012BGC-xxx-AB8
78013GC-xxx-AB8
78014GC-xxx-AB8
78P014GC
64-pin plastic QFP
78P014DW
64-pin ceramic shrink DIP
window
wI
ppD78014Y Family
78011 F!NCW-xxx
78012BYCW.xxx
78013YCW-xxx
78014YCW-xxx
78P014YCW
78011 F!NGC-xxx-AB8
78012BYGC-xxx-AB8
7S013YGC-xxx-ABS
78014YGC-xxx-AB8
78P014YGC
64-pin plastic QFP
78P014YDW
64-pln ceramic shrink DIP
window
wI
P64GC-80-AB8-2
iR30-162-1, VP15-162-1
P64DW-70-750A
Pin partial heating
7-3
NEe
Soldering
I'PD78KO Product Line; Soldering and Packaging Information (cont)
Part Number
Package
Package Drawl ng
Recommended
Soldering Code (Note 1)
"PD78044 Family
_78_0_4_2G_F-_xxx_-3_B_9_ _ _ _ _ 80-pin plastic OFP
P80GF-80-3B9-1
78043GF-xxx-3B9
IR35-207-1, WSSO-207-1, VP15207-1
78044GF-xxx-3B9
78P044GF-3B9
80-pin plastic OFP
P80GF-80-3B9-1
(Note 2)
78P044KL-S
80-pin ceramic LCC w/window
X80KW-80A
Soldering not recommended
S80GC-65-SB9-1
Note 2
80-pin plastic TOFP
P80GK-50-BE9-1
Note 2
80-pin ceramic LCC w/window
X80KW-S5A
Note 2
Pl00GC-50-7EA
Note 2
P100GF-S5-3BA
Note 2
Note 3
Note 2
"PD78054 Family
_78_0_5_2_G_C_-xx_x_-_3B_9_ _ _ _ _ 80-pin plastic OFP
78053GC-xxx-3B9
78054GC-xxx-3B9
78P054GC-3B9
78052GK-xxx-BE9
---------------78053GK-xxx-BE9
78054GK-xxx-BE9
78P054GK-BE9
78P054KK-T
"PD78064 Family
780S2GC-xxx-7EA
100-pin plastic OFP (14 x 14
-78-0-S-3-G-C--x-XX---7E-A----- mm)
780S4GC-xxx-7EA
78POS4GC-7EA
780S2GF-xxx-3BA
100-pin plastic OFP (14 x 20
-78-0-S-3-G-F--xx-X--3-B-A----- mm)
78064GF-xxx-3BA
78P064GF-3BA
78P064KL-T
100-pin ceramic LCC
w/window (14 x 20 mm)
Notes:
(1) See soldering conditions table at the end of this section for
further information on NEC's soldering codes.
(2) Please contact NEC Electronics.
(3) Under development
7-4
NEe
Soldering
p.PD78K2 Product Line; Soldering and Packaging Information
Package Drawing
Recommended
Soldering Code (Note 1)
P64C-70-750A,C
WS60-00-1
P64GC-80-AB8-2
IR30-162-1, VP15-162-1
64-pin plastic QFP
P64GC-80-AB8-2
IR30-162-1, VP15-162-1 (Note 2)
_78_2_1_2G_J_-x_x_X_ _ _ _ _ _ _ 74-pin plastic QFP
S74GJ-100-5BJ-1
IR30-o0-1, VP15-00-1
Part Number
Package
pPD78214 Family
_78_2_1_2CW_-_XXX
_ _ _ _ _ _ _ 64-pin SDIP
78213CW
78214CW-xxx
78P214CW
_78_2_1_2G_C-_xxx
_ _ _ _ _ _ _ 64-pin plastic QFP
78213GC
78214GC-xxx
78P214GC
78213GJ
78214GJ-xxx
78P214GJ
74-pln plastic QFP
S74GJ-100-5BJ-1
IR30-107-1, VP15-107-1
P64GQ..100-36
WS60-o0-1
P68L-50A1-1
VP15-162-1
P68L-50A1-1
VP15-107-1
P64DW-70-750A1
Pin partial heating
64-pin plastic SDIP
P64C-70-750A,C
WS60-00-1
64-pin plastic QFP
P64C-80-AB8-2
IR30-162-1, VP15-162-1
64-pin ceramic SDIP wlwindow
P64DW-70-750A1
Pin partial heating
P84L-50A3-1
VP15-162-1
S94GJ-80-5BG-1
IR30-107-1, VP15-107-1
_78_2_1_3G_3_6_ _ _ _ _ _ _ _ 64-pin plastic QUIP
78214Gxxx36
782P14GQ
_78_2_1_3_L_ _ _ _ _ _ _ _ 6B-pin PLCC
78214L-xxx
7BP214L
68-pin PLCC
7BP214DW
64-pin ceramic shrink DIP
window
wi
pPD78218A Family
78217ACW
-----------------78218ACW
78P218ACW
78217AGC
-----------------78218AGC
78P218AGC
78P218ADW
pPD78224 Family
_78_22_0_L_ _ _ _ _ _ _ _ 84-pin PLCC
78224L-xxx
78P224L
_78_2_2_0G_J_-5_B_G
_ _ _ _ _ _ _ 94-pin plastic QFP
78224GJ-xxx-5BG
78P224GJ-5BG
Pin partial heating
7-5
NEe
$oldering
I'PD78K2 Product Line; Soldering and Packaging Information
Part Number
Package
Package Drawing
Recommended
Soldering Code (Note 1)
80-pin plastic QFP
S80GC-65-3B9-1
IR30-162-1, VPI5-162-1
94-pin plastic plastic QFP
S94GJ-80-5BG-1
1R30-107-1
84-pln PLCC
P84L-50A3-1
VPI5-107-1
94-pin ceramic LCC w/window
X94KW-8OA
Pin partial heating
64-pln plastic SDIP
P64C-70-750A, C
WS60.()O-1
64-pin plastic QFP
P64GC-80-AB8-2
IR30-162-1, VPI5-162-1
pPD78238 Family
78233GC
78234GC-xxx
78237GC
78238GC-xxx
78P236GC
78233GJ
78234GJ-xxx
78237GJ
78238GJ-xxx
78P238GJ
78233LQ
78234LQ-xxx
78237LQ
78238LQ-xxx
78P238LQ
78P236KF
PPD78244 Family
78243CW
78244CW-xxx
78243GC-AB8
78244GC-xxx
Notes:
(1) See soldering conditions table at the end of this section for
further Information on NEC's soldering codes.
(2) This soldering method is not applicable to the UK" speCification
product.
7-6
NEe
Soldering
",PD78K3 Product Line; Soldering and Packaging Information
Part Number
Recommended
Soldering Code (Note 1)
Package
Package Drawing
64-pin plastic shrink DIP
P64C-70-750A, C
64-pin plastic QFP
P64GF-100-3B8,3BE-1
IR30-162-1, VP1S-162-1
64-pin plastic QUIP
P64GQ-100-36
1R30-162-1, VP1S-162-1
68-pin plastic PLCC
P68L-SOA1-1
IR30-QQ-1, VP15-162-1
pPD78312A Family
78310ACW
78312ACW-xxx
78P312ACW
78310AGF-3BE
78312AGF-xxx-3BE
78P312AGF-3BE
78310AG0-36
78312AGQ-xxx-36
78P312AGQ-36
7B310AL
7B312AL-xxx
78P312AL
VP1S-00-1
wI
7BP312ADW
64-pin ceramic shrink DIP
window (350-mil)
P64DW-70-7S0A
78P312AR
64-pln ceramic QUIP w/Window P64RQ-100-A
pPD78322 Family
78320GF
80-pin plastic QFP
P80GF-80-3B9-1
1R30-162-1
68-pin PLCC
P68L-50A 1-1
IR30-QQ-l, VP1S-QQ-l
80-pin plastic QFP
P80GF-BO-3B9-l
IR30-l62-l
68-pin PLCC
P68L-SOA1-l
78320GF(A)
78320GF(A1)
78320GF(A2)
78320L
78320L(A)
78320L(Al)
78320L(A2)
78322GF-xxx
7B322GF(A)-xxx
78322GF(Al)-xxx
78322GF(A2)-xxx
7B322L-xxx
IR30-00-1, VP1S-QQ-1
78322L(A)-xxx
VP1S-00-l
78322L(A 1)-xxx
VP1S-00-l
7B322L(A2)-xxx
78P322GF
VP1S-00-l
80-pin plastic QFP
P80GF-80-3B9-l
78P322L
68-pin PLCC
P68L-50Al-l
7SP322KE
SO-pin ceramic LCC
with window
X80f
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.3
Linearized : No
XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date : 2017:07:25 16:57:30-08:00
Modify Date : 2017:07:25 17:33:36-07:00
Metadata Date : 2017:07:25 17:33:36-07:00
Producer : Adobe Acrobat 9.0 Paper Capture Plug-in
Format : application/pdf
Document ID : uuid:b8dfd8aa-7fe2-f848-97ab-c46c53f060f6
Instance ID : uuid:1d21f272-e566-2b42-bbde-f1e182a03566
Page Layout : SinglePage
Page Mode : UseNone
Page Count : 1004
EXIF Metadata provided by EXIF.tools