1994_National_COP8_Databook 1994 National COP8 Databook

User Manual: 1994_National_COP8_Databook

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t!lNational Semiconductor

COP8™
MICROCONTROLLER

DATABOOK
1994 Edition

COPS Family
COPS Applications
MICROWIRE/PLUSTM Peripherals

II
fa

COPS Development Support

Appendices/Physical Dimensions

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Product Status Definitions

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Definition of Terms
Data Sheet Identification

Product Status

Definition

Advance Information

Formative or
In Design

This data sheet contains the design specifications for product
development. Specifications may change in any manner without notice.

Preliminary

First
Production

This data sheet contains preliminary data, and supplementary data will
be published at a later date. National Semiconductor Corporation
reserves the right to make changes at any time without notice in order
to improve design and supply the best possible product.

No
Identification
Noted

Full
Production

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Corporation reserves the right to make changes at any time without
notice in order to improve design and supply the best possible product.

Obsolete

Not In Production

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discontinued by National Semiconductor Corporation. The data sheet
is printed for reference information only.

...

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National Semiconductor Corporation reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. National does not assume any liability arising out of the application or use of any product
or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

iii

Table of Contents
Alphanumeric Index............. .... ............... ...........................
Section 1 COP8 Family
COP8 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP912C/COP912CH Single-Chip microCMOS Microcontrollers. . . . . . . . . . . . . . . . . . .
COP620C/COP622C/COP640C/COP642C/COP820C/COP822C/COP840CI
COP842C/COP920C/COP922C/COP940C/COP942C Single-Chip microCMOS
Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP820CJ/COP822CJ/COP823CJ Single-Chip microCMOS Microcontrollers. . . . . . . .
COP8640C/COP8642C/COP8620C/COP8622C/COP86L20C/COP86L22CI
COP86L40C/COP86L42C Single-Chip microCMOS Microcontrollers . .............
COP680C/COP681 C/COP880C/COP881 C/COP980C/COP981 C Microcontrollers . . .
COP884BC/COP684BC Single-Chip microCMOS Microcontrollers ........ ;.........
COP688CLlCOP684CL/COP888CL/COP884CL/COP988CLlCOP984CL Single-Chip
microCMOS Microcontrollers .............. '.. ....... .........................
COP888CF ICOP884CFICOP988CFICOP984CF Single-Chip microCMOS
Microcontrollers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP688CS/COP684CS/COP888CS/COP884CS/COP988CS/COP984CS
Single-Chip microCMOS Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP888CG/COP884CG Single-Chip microCMOS Microcontrollers .................
COP888EK/COP884EK Single-Chip microCMOS Microcontrollers . . . . . . . . . . . . . . . . . .
COP688EG/COP684EG/COP888EG/COP884EG/COP988EG/COP984EG
Single-Chip microCMOS Microcontrollers . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP888GW Single-Chip microCMOS Microcontroller .............................
COP8780C/COP8781 C/COP8782C Single-Chip EPROM/OTP Microcontrollers . . . . . .
COP8640CMH/COP8642CMH Microcontroller Emulators. . . . . . . . . . . . . . . . . . . . . . . . . .
COP8788CLlCOP8784CL microCMOS One-Time Programmable (OTP)
Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP8788CF/COP8784CF microCMOS One-Time Programmable (OTP)
Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP8788EG/COP8784EG microCMOS One-Time Programmable (OTP)
Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 2 COP8 Applications
AN-521 Dual Tone Multiple Frequency (DTMF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-579 MICROWIRE/PLUS Serial Interface for COP800 Family. . . . . . . . . . . . . . . . . . . .
AN-596 COP800 MathPak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-607 Pulse Width Modulation AID Conversion Techniques with COP800 Family
Microcontrollers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-662 COP800 Based Automated Security/Monitoring System...... ......... .... .
AN-663 Sound Effects for the COP800 Family...... ..............................
AN-666 DTMF Generation with a 3.58 MHz Crystal....... ..... ................... .
AN-673 2-Way Multiplexed LCD Drive and Low Cost AID Converter Using VIF
Techniques with COP8 Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-681 PC MOUSE Implementation Using COP800... ....... ............... ......
AN-714 Using COP800 Devices to Control DC Stepper Motors .....................
AN-734 MF2 Compatible Keyboard with COP8 Microcontrollers ....................
AN-739 RS-232C Interface with COP800 ........................................
AN-952 Low Cost AID Conversion Using COP800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-953 LCD Triplex Drive with COP820CJ ..................... ..................
Section 3 MICROWIRE/PLUS Peripherals
MICROWIRE and MICROWIRE/PLUS: 3-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . .
COP472-3 Liquid Crystal Display Controller................. .................... .
iv

vi
1-3
1-10

1-28
1-50
1-76
1-98
1-121
1-166
1-201
1-235
1-275
1-311
1-342
1-383
1-423
1-440
1-449
1-477
1-509
2-3
2-12
2-24
2-60
2-67
2-75
2-98
2-126
2-145
2-170
2-180
2-200
2-212
2-221
3-3
3-7

Table of Contents (Continued)
Section 4 COP8 Development Support
Development Support ................ ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COPB Development System ...................................................
Section 5 Appendices/Physical Dimensions
Surface Mount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLCC Packaging .............................................................
Physical Dimensions ............................................' . . . . . . . . . . . . . .
Bookshelf
Distributors

4-3
4-6
5-3
5-23
5-27

Alpha-Numeric Index
AN-521 Dual Tone Multiple Frequency (DTMF) ................................................ 2-3
AN-579 MICROWIRE/PLUS Serial Interface for COP800 Family ...................... '........... 2-12
AN-596'COP800 MathPak ................................................................. 2-24
AN-607 Pulse Width Modulation A/D Conversion Techniques with COP800 Family
Microcontrollers ........................................................................ 2-60
AN-662 COP800 Based Automated Security/Monitoring System .................... ~ ........... 2-67
AN-663 Sound Effects for the COP800 Family ................................................ 2-75
AN-666 DTMF Generation with a 3.58 MHz Crystal ............................................ 2-98
AN-673 2-Way Multiplexed LCD Drive and Low Cost A/D Converter Using V /F Techniques,
with COP8 Microcontrollers ............................................................. 2-126
AN-681 PC MOUSE Implementation Using COP800 ......................................... 2-145
AN-714 Using COP800 Devices to Control DC Stepper Motors ................................ 2-170
AN-734 MF2 Compatible Keyboard with COP8 Microcontrollers ............................... 2-180
AN-739 RS-232C Interface with COP800 ................................................... 2-200
AN-952 Low Cost A/D Conversion Using COP800 ........................................... 2-212
AN-953 LCD Triplex Drive with COP820CJ .................................................. 2-221
COP8 Development System ................................................................ 4-6
COP8 Family .............................................................................. 1-3
COP86L20C Single-Chip microCMOS Microcontroller ......................................... 1-76
COP86L22C Single-Chip microCMOS Microcontroller ......................................... 1-76
COP86L40C Single-Chip microCMOS Microcontroller ......................................... 1-76
COP86L42C Single-Chip microCMOS Microcontroller ......................................... 1-76
COP472-3 Liquid Crystal Display Controller ................................................... 3-7
COP620C Single-Chip microCMOS Microcontroller ........................................... 1-28
COP622C Single-Chip microCMOS Microcontroller ........................................... 1-28
COP640C Single-Chip microCMOS Microcontroller ........................................... 1-28
COP642C Single-Chip microCMOS Microcontroller ........................................... 1-28
COP680C Microcontroller ................................................................. 1-98
COP681 C Microcontroller : ................................................................ 1-98
COP684BC Single-Chip microCMOS Microcontroller ......................................... 1-121
COP684CL Single-Chip microCMOS Microcontroller ......................................... 1-166
COP684CS Single-Chip microCMOS Microcontroller ......................................... 1-235
COP684EG Single-Chip microCMOS Microcontroller ......................................... 1-342
COP688CL Single-Chip microCMOS Microcontroller ......................................... 1-166
COP688CS Single-Chip microCMOS Microcontroller ......................................... 1-235
COP688EG Single-Chip microCMOS Microcontroller ......................................... 1-342
COP820C Single-Chip microCMOS Microcontroller ........................................... 1-28
COP820CJ Single-Chip microCMOS Microcontroller .......................................... 1-50
COP822C Single-Chip microCMOS Microcontroller ........................................... 1-28
COP822CJ Single-Chip microCMOS Microcontroller .......................................... 1-50
COP823CJ Single-Chip microCMOS Microcontroller .......................................... 1-50
COP840C Single-Chip microCMOS Microcontroller ........................................... 1-28
COP842C Single-Chip microCMOS Microcontroller ........................................... 1-28
COP880C Microcontroller ................................................................. 1-98
COP881 C Microcontroller ................................................................. 1-98
COP884BC Single-Chip microCMOS Microcontroller ......................................... 1-121
COP884CF Single-Chip microCMOS Microcontrolier ......................................... 1-201
COP884CG Single-Chip microCMOS Microcontrolier ......................................... 1-275
COP884CL Single-Chip microCMOS Microcontroller ......................................... 1-166
COP884CS Single-Chip microCMOS Microcontrolier ......................................... 1-235
COP884EG Single-Chip microCMOS Microcontroller ......................................... 1-342

Alpha-Numeric

Index(continued)

COP884EK Single-Chip microCMOS Microcontroller ......................................... 1-311
COP888CF Single-Chip microCMOS Microcontroller ......................................... 1-201
COP888CG Single-Chip microCMOS Microcontroller ......................................... 1-275
COP888CL Single-Chip microCMOS Microcontroller ......................................... 1-166
COP888CS Single-Chip microCMOS Microcontroller ......................................... 1-235
COP888EG Single-Chip microCMOS Microcontroller ......................................... 1-342
COP888EK Single-Chip microCMOS Microcontroller ......................................... 1-311
COP888GW Single-Chip microCMOS Microcontroller ........................................ 1-383
COP912C Single-Chip microCMOS Microcontroller ........................................... 1-10
COP912CH Single-Chip microCMOS Microcontroller .......................................... 1-10
COP920C Single-Chip microCMOS Microcontroller ........................................... 1-28
COP922C Single-Chip microCMOS Microcontroller ........................................... 1-28
COP940C Single-Chip microCMOS Microcontroller ........................................... 1-28
COP942C Single-Chip microCMOS Microcontroller ........................................... 1-28
COP980C Microcontroller ................................................................. 1-98
COP981C Microcontroller ................................................................. 1-98
COP984CF Single-Chip micro CMOS Microcontroller ......................................... 1-201
COP984CL Single-Chip microCMOS Microcontroller ......................................... 1-166
COP984CS Single-Chip microCMOS Microcontroller ......................................... 1-235
COP984EG Single-Chip microCMOS Microcontroller ......................................... 1-342
COP988CF Single-Chip microCMOS Microcontroller ......................................... 1-201
COP988CL Single-Chip microCMOS Microcontroller ......................................... 1-166
COP988CS Single-Chip microCMOS Microcontroller ......................................... 1-235
COP988EG Single-Chip microCMOS Microcontroller ......................................... 1-342
COP8620C Single-Chip microCMOS Microcontroller .......................................... 1-76
COP8622C Single-Chip microCMOS Microcontroller .......................................... 1-76
COP8640C Single-Chip microCMOS Microcontroller .......................................... 1-76
COP8640CMH Microcontroller Emulator .................................................... 1-440
COP8642C Single-Chip microCMOS Microcontroller .......................................... 1-76
COP86t!2CMH Micrccentrc!!er Emu!ater .................................................... 1-440
COP8780C Single-Chip EPROM/OTP Microcontroller ........................................ 1-423
COP8781C Single-Chip EPROM/OTP Microcontroller ........................................ 1-423
COP8782C Single-Chip EPROM/OTP Microcontroller ........................................ 1-423
COP8784CF microCMOS One-Time Programmable (OTP) Microcontroller ...................... 1-477
COP8784CL microCMOS One-Time Programmable (OTP) Microcontroller ...................... 1-449
COP8784EG microCMOS One-Time Programmable (OTP) Microcontroller ...................... 1-509
COP8788CF microCMOS One-Time Programmable (OTP) Microcontroller ...................... 1-477
COP8788CL microCMOS One-Time Programmable (OTP) Microcontroller ...................... 1-449
COP8788EG microCMOS One-Time Programmable (OTP) Microcontroller ...................... 1-509
Development Support ...................................................................... 4-3

vii

Section 1
COPS Family

Section 1 Contents
COP8 Family ......................................................................
COP912C/COP912CH Single-Chip microCMOS Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . .
COP620C/COP622C/COP640C/COP642C/COP820C/COP822C/COP840C/COP842CI
COP920C/COP922C/COP940C/COP942C Single-Chip microCMOS Microcontrollers ....
COP820CJ/COP822CJ/COP823CJ Single-Chip microCMOS Microcontrollers .............
COP8640C/COP8642C/COP8620C/COP8622C/COP86L20C/COP86L22C/COP86L40CI
COP86L42C Single-Chip microCMOS Microcontrollers ............ ............ . .......
COP680C/COP681 C/COP880C/COP881 C/COP980C/COP981 C Microcontrollers . . . . . . . . .
COP884BC/COP684BC Single-Chip microCMOS Microcontrollers........................
COP688CL/COP684CL/COP888CL/COP884CL/COP988CL/COP984CL Single-Chip
microCMOS Microcontrollers ......................................................
COP888CFICOP884CFICOP988CFICOP984CF Single-Chip microCMOS Microcontrollers ..
COP688CS/COP684CS/COP888CS/COP884CS/COP988CS/COP984CS Single-Chip
microCMOS Microcontrollers ......................................................
COP888CG/COP884CG Single-Chip microCMOS Microcontrollers .......................
COP888EK/COP884EK Single-Chip microCMOS Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . .
COP688EG/COP684EG/COP888EG/COP884EG/COP988EG/COP984EG Single-Chip
microCMOS Microcontrollers ......................................................
COP888GW Single-Chip microCMOS Microcontroller ...................................
COP8780C/COP8781 C/COP8782C Single-Chip EPROM/OTP Microcontrollers . . . . . . . . . . ..
COP8640CMH/COP8642CMH Microcontroller Emulators ...............................
COP8788CL/COP8784CL microCMOS One-Time Programmable (OTP) Microcontrollers . . ..
COP8788CF/COP8784CF microCMOS One-Time Programmable (OTP) Microcontrollers . . ..
COP8788EG/COP8784EG microCMOS One-Time Programmable (OTP) Microcontrollers ...

1-2

1-3
1-10
1-28
1-50
1-76
1-98
1-121
1-166
1-201
1-235
1-275
1-311
1-342
1-383
1-423
1-440
1-449
1-477
1-509

tJ1National Semiconductor

The 8-Bit COP8™ Family:
Optimized for Value
Key Features
The COP8 combines a powerful single-byte, multiple-function instruction set with a memory-mapped core architecture.

• High-performance 8-bit microcontroller
• Full 8-bit architecture and implementation
• 1 j.Ls instruction-cycle time
• High code efficiency with single-byte, multiple-function
instructions

Key Applications
• Automotive systems
• Process control
• Robotics
IS Telecommunications
II AC-motor control

• UART

• AID converter
• WATCHDOGTM/clock monitor
• Brown Out Detect
• On-chip ROM from 768 bytes to 16k bytes

• DC-motor control

• On-chip RAM to 256 bytes

1:1 Keyboard controllers

• EEPROM
• M2CMOSTM fabrication

I!I

1:1 Modems

RS232C controllers
Toys and games
1:1 Industrial control
1:1 Small appliances

• MICROWIRE/PLUSTM serial interface
• Wide operating voltage range:

+ 2.3V to + 6V

• Military temp range available: - 55'C to

+ 125'C

The COP8 family offers high performance in a low-cost,
easy-to-design-in package.

• MIL-STD-883C versions available
• 16- to 44-pin packages

An Example of COP888 Block Diagram (COP888CF)

II
CPU
REGISTERS
TL/XX/0073-3

1-3

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D..

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o

Embedded Control: Practical Solutions to Real Problems
Microcontrollers have played an important role in the semiconductor industry for quite some time. Unlike microprocessors, which typically address a range of more compute intensive, general purpose applications, microcontrollers are
based on a central processing unit, data memory and input/
output circuitry that are designed primarily for specific, single function applications.

circuitry and National's MICROWIRE/PLUSTM interface. In
addition, National's COP8 microcontrollers are available in a
wide variety of temperature range configurations from
- 55°C on up through + 125°C-optimizing them for rugged
industrial and military applications.

During the 1970s, microcontrollers were initially used in simple applications such as calculators and digital watches. Sut
the combination of decreasing costs and increasing integration and performance has created many new application opportunities over the years. Even as the bulk of application
growth occurs in the 8-bit arena, the same issues that system designers were concerned with in the 4-bit world continue in force today. These include cost/performance tradeoffs, low power and low voltage capabilities, time to market,
space/pin efficiency and ease of design.

The COP8 family provides designers with a number of features that result in substantial benefits. These include a
code-efficient instruction set, low power/voltage features,
efficient I/O, a flexible and configurable design methodology, robust design tools and electromagnetic interference
(EMI) control.

COPS Benefits

The COP8 family's compact, efficient and easy-to-program
instruction set enables designers to reduce time to market
for their products. Thanks to the instruction set, efficient
ROM utilization lowers costs while providing the opportunity
to integrate additional functionality on-chip. Low voltage operation, low current drain, multi-input wakeup and several
power saving modes reduce power consumption for today's
increasing range of handheld, battery-driven applications.
And an array of user-friendly development tools-including
hardware from MetaLink, and state of the industry assemblers, C compilers, and a "fuzzy logic" design environment
help design engineers save valuable development time.
National's Configurable Controller Methodology (CCM) for
the COP8 family creates "whole products" that are bugfree, fully tested and characterized, and supported by a
range of documentation and hardware/software tools. National developed CCM because the majority of customer requests for new products have typically called for reconfigurations of existing proven blocks-such as RAM, ROM, timers, comparators, UARTs, and I/O.

• Cost/Performance. A price difference of just a few pennies can be the gating factor in today's 8-bit design decisions. Manufacturers must offer a wide range of cost/
performance options in order to meet customer demands.
• Low Power and Low Voltage. The increasing range of
mobile and/or battery-powered applications is placing a
premium on low-power, low-voltage, CMOS and SiCMOS
embedded control solutions.
• Time to Market. All 8-bit microcontroller's architecture,
functionality and feature set have a major influence on
product design cycles in today's competitive market, with
its shrinking windows of opportunity.
• Space/Pin Efficiency. Real estate and board configuration considerations demand maximum space and I/O pin
efficiency, particularly given today's high integration and
small product form factors.

In addition, COP8 products incorporate circuitry that guards
against electromagnetic interference-an increasing problem in todays microcontroller board designs. Nationals patented EMI reduction technology offers low EMI clock circuitry, EM I-optimized pinouts gradual turn-on outputs (GTO) an
on-chip choke device and to help customers circumvent
many of the EMI issues influencing embedded control designs.

• Ease of Design. A familiar and easy to use application
design environment-including complete development
tool support-is one of the driving factors affecting today's 8-bit microcontroller design decisions.
All of these issues must be considered when searching for
the appropriate 8-bit microcontroller to meet specific application needs. And that's why National Semiconductor's
COP8 family of 8-bit microcontrollers is enjoying widespread
success in today's global embedded control marketplace.

A Growing Family
National's wide-ranging COP8 family is well-positioned to
meet the expanding variety of consumer 8- bit microcontroller applications. Available in. a wealth of different ROM (768
bytes to 16k bytes) and RAM (64 x 8,128 x 8, and 512 x 8)
configurations, COP8 microcontrollers provide designers
with cost-effective solutions at every price/performance
point in todays market. And the recent introduction of the
new COP912C-National's first 8 bit microcontroller priced
below 50¢ per unit when purchased in volume quantitiescontinues to drive prices down in the highly competitive 8-bit
market.

One of the leaders in the design, manufacture and sale of 8bit microcontrollers is National Semiconductor. Long a
prominent player in the worldwide microcontroller market,
National and its COP8 family of products spans today's
range of applications, providing customers with a wealth of
options at every price/performance point in the 8-bit microcontroller market.
National's 8-bit COP8 microcontrollers enable the company
to meet a wide range of embedded control application requirements. COP8 microcontrollers offer users cost-effective solutions at virtually every price/performance point in
today's market for 8 bit applications.

A code-efficient instruction set. Low power operation. I/O
pin efficiency. A "whole product" philosophy that includes
superior development tools, documentation and support.
These are the reasons that National's COP8 family is a key
player in the worldwide 8-bit microcontroller market. As that
market continues to expand. National continues its microcontroller technology research and development effortsan ongoing commitment that began during the infancy of
embedded control and continues in full force today.

Designers can select from a variety of building blocks centered around a common memory-mapped core and modified Harvard architecture. These building blocks include
ROM, RAM, user programmable memory, UART, comparator, AID and I/O functions.
The COP8 family incorporates 1 Ils instruction cycle times,
watchdog and clock monitors, multi-input wake up

1-4

COPS Features/Benefits Analysis
Key Features

Benefits

Instruction Set

• Efficient Instruction Set
(77% Single Byte/Single Cycle)
• Easy To Program
• Compact Instruction Set
• Multi Function Instructions
• Ten Addressing Modes

• Efficient ROM Utilization (compact code)
• Low Cost Microcontroller (small ROM size)
• Fast Time To Market

Low Power

•
•
•
•

• Lower Power Consumption for Hand Held
Battery Driven Applications

Efficient I/O

•
•
•
•

Software Programmable I/O
Efficient Pin Utilization
Breadth of Available Packages
Package Types Including Variety of Low Pin Count
Devices
• High Current Outputs
• Schmitt Trigger Inputs

• Multiple Use of I/O Pins
• Economical Use of External Components
(lower system cost)
• Cleaner Hardware Design
• Choice of Optimum Package Type (price/
outline/pinout)

Flexible/Powerful
On-Board Features

•
•
•
•
•
•
•

Smart 16-Bit Timers (processor independent PWM)
Comparators
UART
Multi-Input Wakeup
Multi-Source Hardware Interrupts
MICROWIRE/PLUS Serial Interface
Application Specific Features
(CAN, Motor Control Timers, etc.)

• Timers Allow Less Software/Process
Overhead for Frequency
• Measurement (capture) and PWM
• Cleaner Hardware (eliminating the need for
external components)
• Overall Cost Reduction

Safety/SoftwareRunaway Protection

•
•
•
•

WATCHDOG
Software Interrupt
Clock Monitor
Brown Out Detection

• No Need for External Protection Circuitry
• Brown Out Detection Allows the Use of Low
Cost Power Supply

Development Tools

Hardware:
• New, User Friendly, Development Tool Hardware
from MetaLink
• Low Cost Version of the Development Tool (Debug
Module)
• Various Third Party Programmers for Programming
OTPs

Low Voltage Operation
Lower Current Drain
Multi-Input Wakeup
Power Savings Modes (HALT/IDLE)

• Saves Engineering Development Time-Fast
Time to Market

Svft·II·I"~iC:

• New, User Friendly Assembler, a C Compiler and a
"Fuzzy" Logic Design Environment

1-5

COP8Family

COPS Features! Applications Matrix
Market Segment
Consumer

Applications

Applications
Features/Functions

Mlcrocontroller
Features Required

Appropriate
COPS Devices

Children Toys
and Games

Basketball/Baseball Games
Children Electronic Toys
Darts
Throws
Juke Box
Pinball
Laser Gun

Battery Driven
Replacing Discrete with Low Cost
Driving Piezo/Speaker/LEDs
Directly
Very Cost Sensitive

Very Low Price
Low Power Consumption
Wide Voltage Range
High Current Outputs
Small Packages

Electronic
Audio
Items

Audio Greeting Cards
Electronic Musical Equipment

Battery Driven
Tone Generation
Low Power

Wide Voltage Range
Low Power Consumption
Efficient Table Lookup
Flexible Timer

COP912C
COP820C/840C/880C

Electronic
Appliances/
Tools

Small Appliances:
Irons
Coffee Makers
Digital Scales
Microwave Ovens
Cookers
Food Processors
Blenders

Low Cost Power Supply
Temp Measurement
Safety Features
Noise Immunity
Driving LEOs/Relays/Heating
Elements

Brown Out Detection
On-Board Comparator
High Current Outputs
Watchdog/Software Interrupt
Schmtt Trigger Inputs
16-Bit PWM Timer

COP820/840
COP820CJ Family

Household Appliances:
Oven Control
Dishwasher
Washing Machine/Dryer
Vacuum Cleaner
Electronic Heater
Electronic Home Control
(Doorbell, Light Dimmer,
Climate)
Sewing Machine

Rely on Hard-Wire Relay Circuits,
Timers, Counters, Mechanical
Sequence Controllers
Temp Control
Noise Immunity
Safety Features
Timing Control
Main Driven

Brown Out Detection
On-Board Comparator
On-Board AID
Watchdog/Soft Interrupt
Schmitt Trigger Inputs
Flexible Timers
PWMOutputs
High Current Outputs
Safety Features

COP820CJ (on-board
comparator)
COP888CF (on-board AID)

Scales
Multimeters (portable)
Electronic Key
Laptop/Notebook Keyboard
Mouse
Garage Door Opener
TVIElectronic Remote Control
Portable PRP or Retail Pos Device
Jogging Monitor
Smart Cards

Battery Driven
Minimal Power Consumption
Low Voltage
Sensing
Measurement
Standby Mode
Flexible Package Offerings
Small Physical Size

Low Voltage Operation
Low Power Consumption
Wide Voltage Range
Power Saving Modes
Multi-Input Wakeup
On-Board Comparator
Small Packages

COP820CJ
COP840/COP880
COP888CL (Keyboards)
COP8646 (Smart Cards)

Cordless Phone (base/handset)
Phone Dialer
Answering Machine
Feature Phone
PBX Card
CB Radios/Digital Tuners
Cable Converter

Low Power
Timing
Serial Interfaces
Low Voltage
Tone Dialing
Battery Saving Functions
Small Physical Size

Low Current Drain
Low Voltage Operation
Standby Mode
UART
Seri.al Synchronous Interface
16-Bit Timers
Schmitt Trigger Inputs
LED Direct Drive
Sufficient I/O in Small Packages

Cordless Phone:
COP840/COP880
Feature Phone PBX Card:
COP888CG/COP888EG
Others:
Generic COP8 Devices

.....

Portable/
Handheld/
Battery
Powered

Personal Communications

COP912C
. COP920C/COP922C

COPS Featuresl Applications Matrix (Continued)
Market Segment
Medical

Industrial

Applications

Applications
Features/Functions

Mlcrocontroller
Features Required

Appropriate

COPS Devices

Monitors

Thermometer
Pressure Monitors
Various Portable Monitors

Battery Driven
Sensing/Measurement
Data Transmission
Low Power
Low Voltage

On-Board Comparator
(low cost AID)
16-Bit Timer
Low Power Consumption
Low Voltage Operation

COP820CJ (on-board)
comparator)
COP840/COP880
COP888CL

Medical
Equipment

Bed-Side Pump/Timers
Ultrasonic Imaging System
Analyzers (chemical, data)
Electronic Microscopes

Monitoring Data
Data Transmission
Timing

Serial Interface

AID

COP888CS
COP888CF
COP888CG/COP888EG

Motion Control

Motor Control
Power Tools

Motor Speed Control
Noisy Environment
Timing Control

Flexible PWM Timers
Schmitt Trigger Inputs
High Current Outputs

COP820/COP840
COP888CL

Security/
Monitoring
System

Security Systems
Burglar Alarms
Remote Data Monitoring Systems
Emergency Control Systems
Security Switches

Data Transmission
Monitoring (scan inputs from
sensors)
Keypad Scan
Timing
Diagnostic
Data Monitoring
Drive Alarm Sounders
Interface to Phone System
Standby Mode

UART
Flexible 16-Bit PWM Timers
Flexible I/O
Single Slop AID Capability
Power Saving Modes (HALT,
Multi-Input wakeup)
Serial Synchronous Interface

Basic Systems:
COP840/COP880, COP888CL
(Multi-Input wakeup)
More Involved Systems:
COP888CS/COP888CG
COP888EK (muxed analog
inputs, constant current
source)

Timing/Counting
Sensing
Measurement

Generic Microcontroller

Generic COP8 Microcontroller:
COP820/COP840/COP880

Timing
Motion Control
Display Control
Soft Runaway/Trap Recovery
(safety considerations)
EMI/Noise Immunity
Serial Interfaces
Standby Modes
Wide Temp Range

Flexible PWM Timers
Power Saving Modes
Multi-Input Wakeup
WATCHDOG Software Trap
UART
CAN Interface
Special Features for Dashboard
Control (counters, capture
modules, MUL/DIV)
Reduced EMI
Wide Temp Range

Radio/Climate Control:
COP888CG/888EG/888EK
SeatlMotional Control,
Slave Controller: COP884BC
Dashboard Control:
COP888GW
Mirror Control, etc.:
COP8 Basic Family
Climate Control: COP888CF

Switch Controls (elevator,
traffic, power switches)
Sensing Control Systems/Displays
Pressure Control (scales)
Metering (utility, monetary,
industrial)
Lawn Sprinkler/Lawn Mowers
Taxi Meter
Coin Controls
Industrial Timers
_Temperature Meters
Gas Pump
Gas/Smoke Detectors

Misc.

Automotive

Radio/Tape Deck Controls
Window/SeatlMirror/Door/
Controls
HeatlClimate/Controls
Headlightl Antenna
Power Steering
AntiTheft
Slave Controllers

16-Bit Timers

,{Ilwe:l 8dO~

iii

COP8Family

COPS Family Selection Guide
Common Features:

Comm

Ind

Mil

Temp
O·Cto

Temp
-40·Cto

Temp
-55·Cto

+70·C

+85·C

+ 125·C

• Multl·Source Interrupt

• MICROWIRE Serial Communication

• CMOS Process Technology

• Wide Temperature Range

• Pinout
• Instruction Set

• 1 /Ls Instruction Cycle Time

• Halt Mode
• Software Selectable I/O

• Development Tools

Memory

• Wide Power Supply-2.3V to 6.0V

1/0

Packages

Features

Single Chip Emulators

Timers

Multi·
if! of
WATCH
ROM RAM
Compar·
Idle
V Interrupt
NWM
Pins
UART
PWMI
Input
(Bytes) (Bytes)
Pins
ators
Sources
DOG
Timer
Capture
Wakeup

COP823CJ

1.0k

COP822CJ

1.0k

COP820CJ

1.0k

Additional
~

DIP

Features

Brown Out Detection
Modulator, Special PWM, COP8722CJN2
Timer, High Current Outputs COP8720CJN2

768

COP8782CJ

COP922C COP822C

COP622C

1.0k

COP8782CJ

COP920C COP820C

COP620C

1.0k

COP8781CJ

COP942C COP842C

COP642C

2.0k

128

COP8782CJ

COP912C

PLCC

COP940C COP840C

COP640C

2.0k

128

COP8781CJ

COP981C COP881C

COP681C

4.0k

128

COP8781CJ

4.0k

128

COP8722CJWM2
COP8720CJWM2

(Note 1)
COP980C COP880C

COP680C

40/44 x

COP8780CJ

COP8780EL

(Note 1)

COP8782C
COP8781C COP6781Cl

4.0k

128

UVWINDOWED

COP8782CJ

4.0k

128

COP8781CJ

COP8780C

4.0k

128

&
OTP

COP8622C COP6622C

1.0k

40/44 x
20

x
x

COP8780CJ

COP86L22C COP6622C

1.0k

COP8620C COP6620C

1.0k

64x8

COP86L20C COP6620C

1.0k

EEPROM

COP8642C COP6642C

2.0k

COP86L42C COP6642C

2.0k

RAM

COP8640C COP6640C

2.0k

COP86L40C COP6640C

2.0k

COP984CL COP884CL COP684CL

4.0k

128

Clock

COP8784CLN

COP988CL COP888CL COP688CL

4.0k

128

33/39 40/44 x

Monitor

COP8788CLN

COP984CF COP884CF

4.0k

128

8 Channel

COP8784CFN

4.0k

128

23
28 x
33/37 40/44 x

COP988CF COP888CF

(8-bit)AID

COP8788CFN

Note 1: MIL-STD-883 in J Pkg
Note~ 2: Contact sales office for availability.

x
x
x

COP8780EL

COP8642CMHD·X
I

COP8640CMHD·X
COP8642CMHD-X
COP8640CMHD-X

N = Plastic DIP

MHO = Ceramic DIP

V = Plastic Leaded Chip Carrier (PLCC)

MHEA = 28 Small-Outline Footprint

WM = Small Outline Package-Wide Body

EL = Lead Chip Carrier

- - - -

COP8784CLWM
COP8788CLV
COP8784CFWM
COP8788CFV

COPS Family Selection Guide
Common Features:

Comm

Ind

Mil

Temp

O·Cto

-40·Cto

Temp
-SS·C to

+70·C

+8S·C

+ 12S·C

(Continued)

• Multi-Source Interrupt

• MICROWIRE Serial Communication

• Pinout
• Instruction Set

• 1 Ils Instruction Cycle Time

Memory
ROM

RAM

(Bytes) (Bytes)

COP984CS COP884CS COP684CS

4.0k

192

COP988CS COP888CS COP688CS

4.0k

192

COP884CG

4.0k

192

COP888CG

4.0k

192

• CMOS Process Technology
• Halt Mode
• Software Selectable 1/0

• Wide Power SlIpply-2.3V to S.OV
I/O
Pins

Packages

COP884EK

8.0k

256

COP888EK

8.0k

256

COP984EG COP884EG COP684EG

8.0k

256

COP988EG COP888EG COP688EG

8.0k

256

COP884BC

2.0k

COP888GW

16.0k

512

Features

DIP

PLCC

COP8784EGWM

COP8784EGN

COP8788EGN COP8788EGV

14
12

COP8784EGN

COP8788EGN COP8788EGV

CAN Interface, Motor

Hardware Multiply/

35/39 40/44 x

Additional

35/39 40/44 x
23

Single Chip Emulators

Features

MultiInterrupt IT"Imers Compar# of
WATCHIdle
NWM
UART
Input
V Sources I PWMI
Pins
ators
DOG
Timer
Wakeup
Capture

35/39 40/44 x

• Wide Temperature Range
• Development Tools

Reduced EMI

COP8784EGN

Reduced EMI

COP8788EGN COP8788EGV

COP8784EGWM

6 Analog Inputs, Constant

Current Source,
Reduced EMI

35/39 40/44 x

x
x

COP884EGWM

Control Timer

cO
x

Divide Function,

4x Counter Block,
Reduced EMI
Note 1: MIL-STD-883 in J Pkg
Note 2: Contact sales office for availability.

N = Plastic DIP

MHD = Ceramic DIP

V = Plastic Leaded Chip Carrier (PLCC)

MHEA = 28 Small-Outline Footprint

WM = Small Outline Package-Wide Body

EL = Lead Chip Carrier

Al!we:l8dO~

iii

::I:

o
C\I
,....

D..

PRELIMINARY

t!lNational Semiconductor

......
o
C\I

,.... COP912C/COP912CH
en

D..

Single-Chip microCMOS Microcontrollers
General Description
The COP912C/COP912CH are members of the COPSTM
8-bit MicroControiler family. They are fully static Microcontrollers, fabricated using double-metal silicon gate microCMOS technology. These low cost MicroControilers are
complete microcomputers containing all system timing, interrupt logic, ROM, RAM, and I/O necessary to implement
dedicated control functions in a variety of applications. Features include an 8-bit memory mapped architecture,
MICROWIRETM serial I/O, a 16-bit timer/counter with capture register and a multi-sourced interrupt. Each I/O pin has
software selectable options to adapt the device to the specific application. The device operates over voltage ranges
from 2.3V to 4.0V (COP912C) and from 4.0V to 5.5V
(COP912CH). High throughput is achieved with an efficient,
regular instruction set operating at a minimum of 2 ,..,s per
instruction rate.

Features

• 16-bit read/write timer operates in a variety of modes
- Timer with 16-bit auto 'reload register
- 16-bit external event counter
- Tinier with 16-bit capture register (selectable edge)
• Multi-source interrupt
- External interrupt with selectable edge
- Timer interrupt or capture interrupt
- Software interrupt
• 8-bit stack pointer (stack in RAM)
• Powerful instruction set, most instructions single byte
• BCD arithmetic instructions
• 20-pin DIP/SO packages
• Software selectable I/O options (TRI-STATE®, pushpull, weak pull-up)
• Schmitt trigger inputs on Port G-Port
• Temperature range: COP912C/COP912CH from O°C to
70°C
• Form Factor Emulator

Applications

• Low cost 8-bit MicroController
• Fully static CMOS
• Instruction Time
- 2 ,..,s COP912CH
- 2.5,..,s COP912C
• Low current drain
Low current static HALT mode
• Single supply operation
• 768 x 8 on-chip ROM
• 64 Bytes on-chip RAM
• MICROWIRE/PLUSTM serial I/O

• Electronic keys and switches
• Remote Control
•
•
•
•
•
•
•

Timers
Alarms
Small industrial control units
Low cost slave controllers
Temperature meters
Small domestic appliances
Toys' and games

Block Diagram
GND

IT IT
PORT L

1-10 .

PORT G

TLlDD/12060':'1

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,

Total Current into Vee Pin (Source)

please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Total Current out of GND Pin (Sink)

Supply Voltage (Vee)
Voltage at Any Pin

80mA
80 rnA

Storage Temperature Range

6.0V

- 65°C to + 150°C

Note: Absolute maxImum ratings Indicate limits beyond which damage

to the device may occur. DC and AC electrIcal specificatIons are not
ensured when operatIng the devIce at absolute maxImum ratings.

-0.3V to Vee +0.3V

Conditions

Operating Voltage
912C
912CH
Power Supply Ripple 1 (Note 1)

Peak to Peak

Supply Current (Note 2)
CKI = 4MHz
CKI = 4MHz
HALT Current

Vee
Vee
Vee

Typ

Min
2.3
4.0

= 5.5V, tc = 2.5,.,.s
= 4.0V, tc = 2.5,.,.s
= 5.5V, CKI = 0 MHz

INPUT LEVELS (VIH, VIU
Reset, CKI:
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low

Units

4.0
5.5
0.1 Vee

V
V
V

6.0
2.5
8

rnA
rnA
,.,.A

0.1 Vee

V
V

0.2 Vee

V
V

0.9 Vee

0.7 Vee

Hi-Z Input Leakage/TRI-STATE Leakage

Vee

= 5.5V

Input Pullup Current

Vee

= 5.5V

-2

G-Port Hysteresis

0.05 Vee

Output Current Levels
Source (Push-Pull Mode)

Vee
Vee
Vee
Vee

Sink (Push-Pull Mode)

=
=
=
=

4.0V, VOH
2.3V, VOH
4.0V, VOL
2.3V, VOL

= 3.8V
= 1.8V
= 1.0V
= O.4V

,.,.A

250

,.,.A

0.35 Vee

0.4
0.2
4.0
0.7

o"C
(0

...a.
N

:I:

Max

o
......

DC Electrical Characteristics COP912C/COP91 ~CH; O°C ::s: TA ::s:. + 70°C unless other specified
Parameter

...a.
N

rnA
rnA
rnA
rnA

Allowable Sink/Source Current Per Pin

rnA

Input Capacitance (Note 3)

1000

Load Capacitance on D2 (Note 3)
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: Characterized, not tested.

--.r-LJ

~
~WH

~t~PD

FIGURE 1. MICROWIRE/PLUS Timing

1-11

TL/OO/12060-2

:I:

o
N

,..

AC Electrical Characteristics COP912C/COP912CH;0°C:$; TA:$;

a..
o
o
......
o
N
,..

a..

Parameter

Conditions

INSTRUCTION CYCLE TIME (tc)
Crystal I Resonator

RIC Oscillator

o
o

4.0V
2.3V
4.0V
2.3V

:$; Vee:$;
~ Vee <
:$; Vee:$;
~ Vee <

5.5V
4.0V
5.5V
4.0V

4.0V
2.3V
4.0V
2.3V

~ Vee ~ 5.5V

+70°C unless otherwise specified

Min

Typ

2
2.5

3
7.5

Max

Units

DC
DC
DC
DC

p,s
p,s
p,s
p,s

Inputs
tsetup

Output Propagation Delay
tp01, tpoo
SO,SK

~ Vee

< 4.0V

~ Vee ~ 5.5V
~

Vee

< 4.0V

200
500

ns
ns
ns
ns

60
150

RL = 2.2 k!l, C~ = 100 pF
4.0V ~ Vee ~ 5.5V
2.3V ~ Vee < 4.0V
4.0V ~ Vee ~ 5.5V
2.3V ~ Vee < 4.0V

All Others
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

0.7
1.75

p,s
p,s
p,s
p,s

220

ns
ns
ns

1 tc
1 tc
1 tc
1 tc

MICROWIRE Setup Time (t/LWS)
MICROWIRE Hold Time (t/LWH)
MICROWIRE Output
Propagation Delay (t/LPO)

Reset Pulse Width

1.0

COP912C/COP912CH Pinout
Top View
20 DIP

20S0Wlde

G4/S0- 1

20 -G3/TIO

G4/S0- 1

201-G3/TIO

G5/SK- 2

19 -G2

G5/SK- 2

191-G2

G6/SI- 3

18 -G1

G6/SI- 3

G7/CKO- 4

17 -GO/INT

G7/CKO- 4

~G1

17 ~GO/INT

CKI- 5

16 - RESET

CKI- 5

16 -RESET

Vcc -

15 -GND

Vcc -

15 -GND

LO- 7

14 -L7

LO- 7

14 -L7

L1-8

13 -L6

L1- 8

13 -L6

L2- 9

12 -L5

L2- 9

12 -L5

L3- 10

11 -L4

L3- 10

11 -L4

TL/00/12060-3

TLl00/12060-4

Order Number COP912C·XXXIN, COP912CH·XXX/N

Order Number COP912C·XXX/WM,
COP912CH·XXX/WM

FIGURE 2. COP912C/COP912CH Pinout

1-12

a-0

Pin Description

Vee and GND are the power supply pins.

The selection of alternate Port G functions are done through
registers PSW [OOEF] to enable external interrupt and
CNTRl [OOEE] to select TID and MICROWIRE operations.

CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunction with CKO). See Oscillator description.

Functional Description

RESET is the master reset input. See Reset description.

The internal architecture is shown in the block diagram.
Data paths are illustrated in simplified form to depict how
the various logic elements communicate with each other in
implementing the instruction set of the device.

PORT l is an 8-bit I/O port.
There are two registers associated to configure the l port: a
data register and a configuration register Therefore, each l
I/O bit can be individually configured under software control
as shown below:
Port l Config.

Port l Data

PORTl
Setup

Hi-Z Input (TRI-STATE)

is the 8-bit Accumulator register

Input with Weak Pull-Up

is the 15-bit Program Counter register

Push-Pull Zero Output

Push-Pull One Output

is the 8-bit address register and can be auto incremented or decremented

is the 8-bit alternate address register and can be auto
incremented or decremented.

PORT G is an 8-bit port with 6 I/O pins (GO-G5) and 2 input
pins (G6, G7).

is the 8-bit stack pointer which points to the subroutine
stack (in RAM).

All eight G-pins have Schmitt Triggers on the inputs.

8, X and SP registers are mapped into the on chip RAM.
The 8 and X registers are used to address the on chip RAM.
The SP register is used to address the stack in RAM during
subroutine calls and returns. The SP must be preset by software upon initialization.

There are two registers associated to configure the G port:
a data register and a configuration register. Therefore each
G port bit can be individually configured under software control as shown below:

Hi-Z Input (TRI-STATE)

Input with Weak Pull-Up

PUSh-Pull Lero Uutput

Push-Pull One Output

I\)

::J:

MEMORY

PORTG
Setup

PU is the upper 7 bits of the program counter (PC)
8

.....
o

Pl is the lower 8 bits of the program counter (PC)

Three data memory address locations are allocated for this
port, one each for data register [0000], configuration register [0001] and the input pins [0002].

a-0

AlU AND CPU REGISTERS

PortG
Data

I\)

The AlU can do an 8-bit addition, subtraction, logical or
shift operations in one cycle time. There are five CPU registers:

PortG
Config.

.....
o
........
o

The memory is separated into two memory spaces: program
and data.
PROGRAM MEMORY
Program memory consists of 768 x 8 ROM. These bytes of
ROivi may be instructions or consiant data. The memory is
addressed by the 15-bit program counter (PC). There are no
"pages" of ROM, the PC counts all 15 bits. ROM can be
indirectly read by the lAID instruction for table lookup.

Three data memory address locations are allocated for this
port, one for data register [0004], one for configuration register [0005] and one for the input pins [0006]. Since G6
and G7 are Hi-Z input only pins, any attempt by the user to
configure them as outputs by writing a one to the configuration register will be disregarded. Reading the G6 and G7
configuration bits will return zeroes. Note that the chip will
be placed in the Halt mode by writing a "1" to the G7 data
bit.

DATA MEMORY
The data memory address space includes on chip RAM, I/O
and registers. Data memory is addressed directly by the instruction or indirectly through 8, X and SP registers. The
device has 64 bytes of RAM. Sixteen bytes of RAM are
mapped as "registers", these can be loaded immediately,
decremented and tested. Three specific registers: X, 8, and
SP are mapped into this space, the other registers are available for general usage.

Six pins of Port G have alternate features:
GO INTR (an external interrupt)

Any bit of data memory can be directly set, reset or tested.
I/O and registers (except A and PC) are memory mapped;
therefore, I/O bits and register bits can be directly and individually set, reset and tested.

G3 TID (timer/counter input/output)
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock I/O)
G6 SI (MICROWIRE serial data input)

RESET

G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input/general purpose input (if clock option is R/C- or external clock)

The RESET input pin when pulled low initializes the microcontroller. Upon initialization, the ports land G are placed
in the TRI-STATE mode. The PC, PSW and CNTRl registers are cleared. The data and configuration registers for
ports land G are cleared. The external RC network shown
in Figure 3 should be used to ensure that the RESET pin is
held low until the power supply to the chip stabilizes.

Pins G1 and G2 currently do not have any alternate functions.

1-13

(.)
N
~

Functional Description

p
0

D-

o
(.)

......

E
R

(.)
N
~

D-

o(.)

P
P
L
Y

(Continued)
TABLE II. RC Oscillator Configuration
(Part-to-Part Variation, T A = 25°C)

vee

IfC

~~D

RESET

GND
TL/DD/12060-5

RC > 5 x POWER SUPPLY RISE TIME

R
(kn)

C
(pF)

CKI Freq.
(MHz)

Intr.
Cycle
(J,Ls)

3.3

2.2 to 2.7

3.7 to 4.6

5.6

100

1.1 to 1.3

7.4 to 9

6.8

100

0.9 to 1.1

8.8 to 10.8

Note: 3k

FIGURE 3. Recommended Reset Circuit

200 kO, 50 pF

OSCILLATOR CIRCUITS

The total current drain of the chip depends on:

The device can be driven by a clock input which can be
between DC and 5 MHz.

,1. Oscillator operating mode - 11
2. Internal switching current - 12

CRYSTAL OSCILLATOR

3. Internal leakage current - 13

By selecting CKO as a clock output, CKI and CKO can be
connected to create a crystal controlled oscillator. Table I
shows the component values required for various standard
crystal values.

4. Output source current - 14
5. DC current caused by external input not at Vee or GND.
Thus the total current drain is given as
It = 11

RIC OSCILLATOR

CKI

CKO

I I

CKI

CKO

::> R1
LA .

,. ~C2

-=-

yyy

IC1

+ 13 + 14 +

The following formula may be used to compute total current
drain when operating the controller in different modes.
12 = CxVxf

vee

when:l C = equivalent capacitance of' the chip

-L....c

I-

t;:::1

...R

To reduce the total current drain, each of the above components must be minimum. Operating with a crystal network
will draw more current than an external square-wave. The
R/C mode will draw the most. Switching current, governed
by the equation below, can be reduced by lowering voltage
and frequency. Leakage current can be reduced by lowering
voltage and temperature. The other two items' can be reduced by carefully designing the end-user's system.

By selecting CKI as a single pin oscillator, CKI can make an
RIC oscillator. CKO is available as a general purpose input
and/or HALT control. Table II shows variation in the oscillator frequencies as functions of the component (R and C)
value.

200 pF.

CURRENT DRAIN

,,=

operating voltage

f = CKI frequency.
HALT MODE

TLlDD/12060-6

FIGURE 4. Clock Oscillator Configurations
TABLE I. Crystal Oscillator Configuration
CKI
Freq.
(MHz)

R1
(kn)

R2
(mil)

C1
(pF)

C2
(pF)

30-36

5.6

200

100-150

0.455

The device supports two different ways of exiting the HALT
mode. The first method is with a low to high transition on the
CKO (G7) pin. This method precludes the use of the crystal
clock configuration (since CKO is a dedicated output), and
so may be used either with an RC clock configuration (or an
external clock configuration). The second method of exiting
the HALT mode is to pull the RESET low.
Note: To allow clock resynchronization, it is necessary to program two
NOP's immediately after the device comes out of the HALT mode.
The user must program two NOP's following the "enter HALT mode"
(set G7 data bit) instruction.

1-14

Functional Description

o
o

(Continued)

"1J

The following table details the different clock rates that may
be selected.

MICROWIRE/PLUS
MICAOWIAE/PlUS is a serial synchronous communications interface. The MICAOWIAE/PLUS capability enables
the device to interface with any of National Semiconductor's
MICAOWIAE peripherals (Le., AID converters, display drivers, EEPAOMS etc.) and with other microcontrollers which
support the MICAOWIAE interface. It consists of an 8-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK). Figure 5 shows
a block diagram of the MICAOWIAE logic.

o
o

........

SK Divide Clock Rates

SL1

SLO

2 xtc

4xtc

8xtc

CD
.....

"1J

CD
.....
~

::J:

Where tc is the instruction cycle clock.

The shift clock can be derived from either the internal
source or from an external source. Operating the
MICAOWIAE arrangement with the internal clock source is
called the Master mode of operation. Similarly, operating
the MICAOWIAE arrangement with an external shift clock is
called the Slave mode of operation.

MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MICAOWIAE/PlUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift.
The device may enter the MICAOWIAE/PlUS mode either
as a Master or as a Slave. Figure 5 shows how two microcontrollers and several peripherals may be interconnected
using the MICAOWIAE/PlUS arrangement.

The CNTAl register is used to configure and control the
MICAOWIAE mode. To use the MICAOWIAE, the MSEl bit
in the CNTAl register is set to one. The SK clock rate is
selected by the two bits, SlO and Sl1, in the CNTAl register.
.

CHIP SELECT LINES

I/o

LINES

COP
912C
(MASTER)

8 - BIT
AID CONvERTER
COP43X

EEPROM

vr/LCD
DISPLAY
DRIVER

LINES

COP
912C
(SLAVE)

~~'-----

::t-I'

....

TL/DD/12060-7

FIGURE 5. MICROWIRE/PLUS Application

1-15

::I:

T""

c..

.......

o
N

T""

c..

o
o

Functional Description

The user must set the BUSY flag immediately upon entering
the slave mode. This will ensure that all data bits sent by the
master will be shifted in properly. After eight clock pulses,
the BUSY flag will be cleared and the sequence may be
repeated .

(Continued)

WARNING: The SIO register should only be loaded when
the SK clock is low. loading the SID register while the SK
clock is high will result in undefined data in the SIO register.
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PlUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is
low.

Note: In the Slave mode the SIO register does not stop shifting even after
the busy flag goes low. Since SK is an external output, the SIO register stops shifting only when SK is turned off by the master.
Note: Setting the BUSY flag when the input SK clock is high in the MICROWIRE/PLUS slave mode may cause the current SK clock for the SIO
register to be narrow. When the BUSY flag is set, the MICROWIRE
logic becomes active with the internal SIO shift clock enabled. If SK is
high in slave mode, this will cause the internal shift clock to go from
low in standby mode to high in active mode. This generates a rising
edge, and causes one bit to be shifted into the SIO register from the
SI input. For safety, the BUSY flag should only be set when the input
SK clock is low.

Table III summarizes the settings required to enter the Master/Slave modes of operations.
The table assumes that the control flag MSEl is set.
TABLE III. MICROWIRE/PLUS G Port Configuration
G4
GS
(SO)
(SK)
Config. Config.
Bit
Bit

G4
Pin

GS
Pin

GG
Pin

Int.SK

MICROWIRE
Master

TRI-STATE Int.SK

MICROWIRE
Master

MICROWIRE
Slave

TRI-STATE Ext.SK SI

MICROWIRE
Slave

Note: The SIO register must be loaded only when the SK shift clock is low.
Loading the SIO register while the SK clock is high will result in undefined data in the SIO register.

Operation

Timer ICounter

Ext.SK

The device has an on board 16-bit timer/counter (organized
as two 8-bit registers) with an associated 16-bit autoreload/
capture register (also organized as two 8-bit registers). Both
are read/write registers.
The timer has three modes of operation:
PWM (PULSE WIDTH MODULATION) MODE
The timer counts down at the instruction cycle rate (2 ,.,.s
max). When the timer count underflows, the value in the
autoreload register is copied into the timer. Consequently,
the timer is programmable to divide by any value from 1 to
65536. Bit 5 of the timer CNTRl register selects the timer
underflow to toggle the G3 output. This allows the user to
generate a square wave output or a pulse-width-modulated
output. The timer underflow can also be enabled to interrupt
the processor. The timer PWM mode is shown in Figure 7.

MICROWIRE/PLUS MASTER MODE OPERATION
In MICROWIRE/PlUS Master mode operation, the SK shift
clock is generated internally. The MSEl bit in the CNTRl
register must be set to allow the SK and SO functions onto
the G5 and G4 pins. The G5 and G4 pins must also be
selected as outputs by setting the appropriate bits in the
Port G configuration register. The MICROWIRE Master
mode always initiates all data exchanges. The MSEl bit in
the CNTRl register is set to enable MICROWIRE/PlUS. G4
and G5 are selected as output.
~------------------~SO

1+------- SI

TIO
OUTPUT
TL/DD/12060-10

FIGURE 7. Timer in PWM Mode
SK

TL/DD/12060-8

FIGURE G. MICROWIRE/PLUS Block Diagram
MICROWIRE/PLUS SLAVE MODE
In MICROWIRE/PlUS Slave mode operation, the SK shift
clock is generated by an external source. Setting the MSEl
bit in the CNTRl register enables the SO and SK functions
onto the G port. The SK pin must be selected as an input
and the SO pin as an output by resetting and setting their
respective bits in the G port configuration register.

1-16

Functional Description

a"'C

(Continued)
the time of an external edge on the G3 pin is "captured". Bit
5 of the CNTRl register is used to select the polarity of the
external edge. This external edge capture can also be programmed to generate an interrupt. The duration of an input
signal can be computed by capturing the time of the leading
edge, saving this captured value, changing the capture
edge, capturing the time of the trailing edge, and then subtracting this trailing edge time from the earlier leading edge
time. The Input Capture mode is shown in Figure 9.

EXTERNAL EVENT COUNTER MODE
In this mode, the timer becomes a 16-bit external event
counter, clocked from an input signal applied to the G3 input. The maximum frequency for this G3 input clock is
250 kHz (half of the 0.5 MHz instruction cycle clock). When
the extern~1 event counter underflows, the value in the autoreload register is copied into the timer. This timer underflow may also be used to generate an interrupt. Bit 5 of the
CNTRl register is used to select whether the external event
counter clocks on positive or negative edges from the G3
input. Consequently, half cycles of an external input signal
could be counted. The External Event counter mode is
shown in Figure 8.

TIMER
UNDERFLOW
INTERRUPT

TID

16-BIT TIMER/COUNTER

EXT
ClK

a"'C
CD
.......

I\)

:::I:

/;:..

TlOiNPUT~ ,,~IBIT I
CAPTURE REG.

EDGE SELECTOR
LOGIC

16-BIT AUTO-RELOAD REGISTER

o
........

INTERNAL DATA BUS

INTERRUPT

INTERNAL DATA BUS

I
I

CD
.......

I\)

-.;

TI
16 - BIT TIMER

TL/DD/12060-12

FIGURE 9. Timer in Input Capture Mode
Table IV below details the TIMER modes of operation and
their associated interrupts. Bit 4 of CNTRl is used to start
and stop the timer/counter. Bits 5, 6 and 7 of the CNTRl
register select the timer modes. The ENTI (Enable Timer
Interrupt) and TPND (Timer Interrupt Pending) bits in the
PSW register are used to control the timer interrupts.

EDGE SELECTOR
lOGIC
TL/DD/12060-11

Care must be taken when reading from and writing to the
timer and its associated auto reload/capture register. The
timer and autoreload/ capture register are both 16-bit, but
they are read from and written to one byte at a time. It is
recommended that the timer be stopped before writing a
new value into it. The timer may be read "on the fly" without
stopping it if suitable precautions are taken. One method of
reading the timer "on the fly" is to read the upper byte of the
timer first, and then read the lower byte. If the most significant bit of the lower byte is then tested and found to be
high, then the upper byte of the timer should be read again
and this new value used.

FIGURE 8. Timer in External Event Mode
INPUT CAPTURE MODE
In this mode, the timer counts down at the instruction clock
rate. When an external edge occurs on pin G3, the value in
the timer is copied into the capture register. Consequently,

TABLE IV. Timer Modes and Control Bits
CNTRl Bits

Timer
Counts On

Timer
Interrupt

Operation Mode

External Event Counter with Autoreload Register

Timer Underflow

TID Positive Edge

External Event Counter with Autoreload Register

Timer Underflow

TID Negative Edge

Not Allowed

Timer with Autoreload Register

Timer Underflow

Timer with Autoreload Regiter and Toggle TID Out

Timer Underflow

Timer with Capture Register

TID Positive Edge

Timer with Capture Register

TID Negative Edge

1-17

::I:

o
N

,..

Functional Description

D-

TIMER APPLICATION EXAMPLE

o......

The timer has an autoreload register that allows any frequency to be programmed in the timer PWM mode. The
timer underflow can be programmed to toggle output bit G3,
and may also be programmed to generate a timer interrupt.
Consequently, a fully programmable PWM output may be
easily generated.

o
N
,..
en
D-

to interrupt the microcontroller when GIE is enabled. IEDG
selects the external interrupt edge (1 = rising edge, 0 =
falling edge). The user can get an interrupt on both rising
and falling edges by toggling the state of IEDG bit after each
interrupt.

(Continued)

IPND and TPND bits signal which interrupt is pending. After
interrupt is acknowledged, the user can check these two
bits to determine which interrupt is pending. The user can
prioritize the interrupt and clear the pending bit that corresponds to the interrupt being serviced. The user can also
enable GIE at this point for nesting interrupts. Two things
have to be kept in mind when using the software interrupt.
The first is that executing a simple RET instruction will take
the program control back to the software interrupt instruction itself. In other words, the program will be stuck in an
infinite loop. To avoid the infinite loop, the software interrupt
service routine should end with a RETSK instruction or with
a JMP instruction. The second thing to keep in mind is that
unlike the other interrupt sources, the software interrupt
does not reset the GIE bit. This means that the device can
be interrupted by other interrupt sources while servicing the
software interrupt.

The timer counts down and when it underflows, the value
from the autoreload register is copied into the timer. The
CNTRl register is programmed to both toggle the G3 output
and generate a timer interrupt when the timer underflows.
Following each timer interrupt, the user's program alternately loads the values of the "on" time and the "off" time into
the timer auto reload register. Consequently, a pulse-widthmodulated (PWM) output waveform is generated to a resolution of one instruction cycle time. This PWM application
example is shown in Figure 10.
_ _ _...~

/
o

TIO

Toff

t?~

Interrupts push the PC to the stack, reset the GIE bit to
disable further interrupts and branch to address OOFF. The
RETI instruction will pop the stack to PC and set the GIE bit
to enable further interrupts. The user should use the RETI or
the RET instruction when returning from a hardware (maskable) interrupt subroutine. The user should use the RETSK
instruction when returning from a software interrupt subroutine to avoid an infinite loop situation.

A SIMPLE 0 - A
CONVERTER USING
THE TIMER TO
GENERATE A PWM
OUTPUT.

P
9

1
2
C

The software interrupt is a special kind. of non-maskable
interrupt which occurs when the INTR instruction (opcode
00 used to acknowledge interrupts) is fetched from ROM
and placed inside the instruction register. This may happen
when the PC is pointing beyond the available ROM address
space or when the stack is over-popped. When the software
interrupt occurs, the user can re-initialize the stack pointer
and do a recovery procedure (similar to reset, but not necessarily containing all of the same initialization procedures)
before restarting.

TL/DD/12060-13

FIGURE 10. Timer Based PWM Application

Interrupts
There are three interrupt sources:
1. A maskable interrupt on external GO input positive or negative edge sensitive under software control
2. A maskable interrupt on timer underflow or timer capture

Hardware and Software interrupts are treated differently.
The software interrupt is not gated by the GIE bit. However,
it has the lowest arbitration ranking. Also the fact that all
interrupts vector to the same address OOFF Hex means that
a software interrupt happening at the same time as a hardware interrupt will be missed.

3. A non-maskable software/ error interrupt on opcode zero.
The GIE (global interrupt enable) bit enables the interrupt
function. This is used in conjunction with ENI and ENTI to
select one or both of the interrupt sources. This bit is
reset when interrupt is acknowledged.
ENI and ENTI bits select external and timer interrupt respectively. Thus the user can select either or both sources

EXTERNAL
INT. PIN

~O:~~~~~

________________________________

TO
INTERRUPT
LOGIC
~

TL/DD/12060-14

FIGURE 11. Interrupt Block Diagram

1-18

o
o
"0

Interrupts (Continued)

Control Registers

DETECTION OF IllEGAL CONDITIONS

CNTRl REGISTER (ADDRESS X'OOEE)

Reading of undefined ROM gets zeroes. The opcode for
software interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt,
thus signalling that an illegal condition has occurred.
Note: A software interrupt is acted upon only when a timer or external interrupt is not pending as hardware interrupts have priority over software
interrupt. In addition. the Global Interrupt bit is not set when a software interrupt is being serviced thereby opening the door for the hardware interrupts to occur. The subroutine stack grows down for each
call and grows up for each return. If the stack pointer is initialized to
2F Hex, then if there are more returns than calls. the stack painter will
point to addresses 30 and 31 (which are undefined RAM). Undefined
RAM is read as all 1's, thus, the program will return to address FFFF.
This is a undefined ROM location and the instruction fetched will generate a software interrupt signalling an illegal condition. The device
can detect the following illegal conditions:

The Timer and MICROWIRE control register contains the
following bits:
SL 1 and SLO Select the MICROWIRE clock divide-by
(00 = 2,01 = 4, 1x = 8)

External interrupt edge polarity select
Selects G5 and G4 as MICROWIRE signals
SK and SO respectively

TRUN

Used to start and stop the timer/counter
(1 = run, 0 = stop)

TC1

Timer Mode Control Bit
Timer Mode Control Bit

TC3

Timer Mode Control Bit
0

TCl

0046

i~GP

TC2

TC3

TRUN

MSEL

IEDG

SL1

SLO

The PSW register contains the following select bits:
GIE

Global interrupt enable (enables interrupts)

ENI

External interrupt enable

BUSY

MICROWIRE busy shifting flag

IPND

External interrupt pending

ENTI

Timer interrupt enable

TPND

Timer interrupt pending
(timer underflow or capture edge)

Carry Flip/flop

Half carry Flip/flop

I I
HC

CLRA
RC
JMP 04FF

:J:

PSW REGISTER (ADDRESS X'OOEF)

The detection of illegal conditions is illustrated with an example:
0043
0044
0045

I\)

MSEL

TC2

....&.

IEDG

Illegal conditions may occur from coding errors, "brown
out" voltage drops, statiC, supply noise, etc. When the software interrupt occurs, the user can re-initialize the stack
pointer and do a recovery procedure before restarting (this
recovery program is probably similar to RESET but might
not clear the RAM). Examination of the stack can help in
identifying the source of the error. For example, upon a software interrupt, if the SP = 30, 31 it implies that the stack
was over "POP"ed (with the SP = 2F hex initially). If the SP
contains a legal value (less than or equal to the initialized
SP value), then the value in the PC gives a clue as to where
in the user program an attempt to access an illegal (an address over 300 Hex) was made. The opcode returned in this
case is 00 which is a software interrupt.

....&.

I\)

o
........
o

1. Executing from undefined ROM
2. Over "POP"ing the stack by having more returns than calls.

TPND

ENTI

0
IPND

BUSY

ENI

GIE

The Half-Carry bit is also effected by all the instructions that
effect the Carry flag. The flag values depend upon the in-

stn.!ctlan. Far exe.mp!e, e.fter exec!.!tlng the ADC lnstr!.!ctla!1
the values of the Carry and the Half-Carry flag depend upon
the operands involved. However, instructions like SET C
and RESET C will set and clear both the carry flags. Table V
lists out the instructions that effect the HC and the C flags.

When the device is executing this program, it seemingly
"locks-up" having executed a software interrupt. To debug
this condition, the user takes a look at the SP and the contents of the stack. The SP has a legal value and the contents of the stack are 04FF. The perceptive user immediately realizes that an illegal ROM location (04FF) was accessed and the opcode returned (00) was a software interrupt. Another way to decode this is to run a trace and follow
the sequence of steps that ended in a software interrupt.
The damaging jump statement is changed.

TABLE V.lnstructlons Effecting HC and C Flags
Instr.

CFlag

HC Flag

ADC

Depends on Operands Depends on Operands

SUBC

Depends on Operands Depends on Operands

SETC

Set

RESETC Set

Set

RRC

Depends on Operands Depends on Operands

MEMORY MAP
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.

1-19

::I:

o
N
,...

Control Registers

Addressing Modes

(Continued)

o
......

Address

o
N
,...

00 to 2F

Contents

OPERAND ADDRESSING MODES

On-chip RAM Bytes (48 Bytes)

30 to 7F

Unused RAM Address Space (Reads as
all ones)

This is the "normal" addressing mode for the chip. The operand is the data memory addressed by the B or X pointer.

80 to BF

Expansion Space for On-Chip EERAM
(Reads Undefined Data)

COtoCF

Expansion Space for 1/0 and Registers

Port L Data Register

Port L Configuration Register

o
o

The device has ten addressing modes, six for operand addressing and four for transfer of control.

TABLE VI. Memory Map

Register Indirect With Auto Post Increment Or
Decrement
This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B
or X pointer. This is a register indirect mode that automatically post increments or post decrements the B or X pointer
after executing the instruction.

Port L Input Pins (read only)

Direct

Reserved for Port L

The instruction contains an 8-bit address field that directly
points to the data memory for the operand.

Port G Data Register

Port G Configuration Register

Port G Input Pins (read only)

Reserved

Immediate
The instruction contains an 8-bit immediate field as the operand.
Short Immediate
This addressing mode issued with the LD B, # instruction,
where the immediate # is less than 16. The instruction contains a 4-bit immediate field as the operand.

D8to DB

Reserved

DCto DF

Reserved

EO to EF

On-Chip Functions and Registers

EO to E7

Reserved for Future Parts

Reserved

This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.

MICROWIRE Shift Register

TRANSFER OF CONTROL ADDRESSING MODES

Timer Lower Byte

Timer Upper Byte

Timer Autoreload Register Lower Byte

Timer Auto reload Register Upper Byte

CNTRL Control Register

PSW Register

Absolute

On-Chip RAM Mapped as Registers
(16 Bytes)

This mode is used with the JMP and JSR instructions with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any location in the current 4k program memory segment.

FO to FF
FC

X Register

SP Register

B Register

Indirect

Relative
This mode is used for the JP instruction with the instruction
field being added to the program counter to produce the
next instruction address. JP has a range from -31 to +32
to allow a one byte relative jump (JP + 1 is implemented by
a Nap instruction). There are no "blocks" or "pages" when
using JP since all 15 bits of the PC are used. .

Absolute Long
This mode is used with the JMPL and JSRL instructions with
the instruction field of 15 bits replacing the entire 15 bits of
the program counter (PC). This allows jumping to any location in the entire 32k program memory space.

Reading other unused memory locations will return undefined data.

1-20

C')

o""C

Instruction Set

co
......

N
C')

Symbols

Registers
A
8-Bit Accumulator Register
B
8-Bit Address Register
X
8-Bit Address Register
SP
8-Bit Stack Pointer Register
S
8-Bit Data Segment Address Register
PC
15-Bit Program Counter Register
PU
Upper 7 Bits of PC
PL
Lower 8 Bits of PC
C
1-Bit of PSW Register for Carry
HC
1-Bit of PSW Register for Half Carry
GIE
1-Bit of PSW Register for Global Interrupt Enable

[B)
[X]

MD
Mem
Meml
Imm
Reg
Bit
~
~

Memory Indirectly Addressed by B Register
Memory Indirectly Addressed by X Register
Direct Addressed Memory
Direct Addressed Memory, or B
Direct Addressed Memory, B, or Immediate Data
8-Bit Immediate Data
Register Memory: Addresses FO to FF
(Includes B, X, and SP)
Bit Number (0 to 7)
Loaded with
Exchanged with

.....
C')
o""C
co
......
N
C')

::z:

1-21

::J:

('II
.,...

Instruction Set (Continued)

TABLE VII. Instruction Set

D-

o.....
o
('II

.,...

D-

Instr

Function

ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT

A,Meml
A,Meml,
A,Meml
A,Meml
A,Meml
A,Meml
A,Meml
A,Meml
#
Reg
#,Mem
#,Mem
#,Mem

X
LD
LD
LD

A,Mem
A,Meml
Mem,lmm
Reg,lmm

Exchange A with Memory
Load A with Memory
Load Direct Memory Immed.
Load Register Memory Immed.

X
X
LD
LD
LD

A, [B±]
A, [X±]
A, [B±]
A, [X±]
[B±],lmm

Exchange A with Memory [B)
Exchange A with Memory [X]
Load A with Memory [B)
Load A with Memory [X]
Load Memory Immediate

CLRA
INC
DEC
LAID
DCOR
RRC
SWAP
SC
RC
IFC
IFNC

A
A
A
A
A

JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

Addr.
Addr.
Disp.
Addr.
Addr.

Add
Add with Carry
Subtract with Carry
Logical AND
. Logical OR
Logical Exclusive-OR
IF Equal
IF Greater than
IF B not Equal
Decrement Reg, Skip if Zero
Set Bit
Reset Bit
If Bit

A~A

A
A

~
~

+ Meml
A + Meml + C, C ~ Carry
A - Meml + C, C ~ Carry

A~AandMeml
A~AorMeml

A ~ AxorMeml
Compare A and Meml, Do Next if A = Meml
Compare A and Meml, Do Next if A > Meml
Do Next If Lower 4 Bits of B not = Imm
Reg ~ Reg - 1, Skip if Reg Goes to Zero
1 to Mem.Bit (Bit = 0 to 7 Immediate)
o to Mem.Bit (Bit = 0 to 7 Immediate)
If Mem.Bit is True, Do Next Instruction
A~Mem

A~Meml
Mem~lmm

Reg~lmm

A ~ [B) (B ~ B ± 1)
[X] (X~X±1)
A ~ [B) (B ~ B ± 1)
A~ [X] (X~X±1)
[B) ~ Imm (B ~ B±1)
A~

Clear A
IncrementA
Decrement A
Load A Indirect from ROM
Decimal Correct A
Rotate Right Through Carry
Swap Nibbles of A
SetC
ResetC
IfC
IfNotC

A~O

Jump Absolute Long
Jump Absolute

PC ~ ii (ii = 15 Bits, Ok to 32k)
PC11 ... PCO ~ i (i = 12 Bits)
PC15 ... PC12 Remain Unchanged
PC ~ PC + r(ris -31 to +32, not 1)
[SP] ~ PL, [SP-1] ~ PU, SP-2, PC ~ ii
[SP] ~ PL, [SP-1] ~ PU, SP-2, PC11..PCO ~ ii
PL ~ ROM(PU, A)
SP+2, PL ~ [SP], PU ~ [SP-1]
SP+2, PL ~ [SP], PU ~ [SP-1],
Skip next Instr.
SP+2, PL ~ [SP], PU ~ [SP-1], GIE ~ 1
[SP] ~ PL, [SP-1] ~ PU, SP-2, PC ~ OFF
PC ~ PC+1

Jump Relative Short
Jump Subroutine Long
Jump Subroutine
Jump Indirect
Return from Subroutine
Return and Skip
Return from Interrupt
Generate an Interrupt
No Operation

1-22

A~A+

A~A-1

A ~ ROM(PU, A)
A ~ BCD Correction (follows ADC, SUBC)
C~A7~ ... ~AO~C
A7 ... A4 ~ A3 ... AO
C~1
C~O

If C is True, do Next Instruction
If C is not True, do Next Instruction

a"0

Instruction Set (Continued)
Instructions Using A and C (Bytes/Cycles)

• Most instructions are single byte (with immediate addressing mode instructions requiring two bytes).

Arithmetic and Logic
Instructions (Bytes/Cycles)
[B)

Direct

ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFNE
IFGT
IFBNE
DRSZ

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4

SBIT
RBIT
IFBIT

1/1
1/1
1/1

3/4
3/4
3/4

-&.

• Most single byte instructions take one cycle time to execute.
The following tables show the number of bytes and cycles
for each instruction in the format byte/cycle.

Instr

Immediate

2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2

Instr

Bytes/Cycles

CLRA
INCA
DECA
LAID
DCOR
RRCA
SWAPA
SC
RC
IFC
IFNC

1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1

o
.......
o

a"0
CD

-&.

::J:

Transfer of Control Instructions
(Bytes/Cycles)

1/3

Instr

Bytes/Cycles

JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

3/4
2/3
1/3
3/5
2/5

1/3
1/5
1/5
1/5
117

1/1

Memory Transfer Instructions (Bytes/Cycles)
Instr

LBj
XA,a
LDA,·
LDB,lmm
LDB,lmm
LDMem,lmm
LD Reg,lmm

1/1
1/1

2/2

Direct

Immed.

[xl

[B+,B-]
2/3
2/3

1/3
1/3
3/3
2/3

2/2
1/1 b
2/3 c

1/2
1/2

rx+,X-]

1/3
1/3

2/2

a. Memory location addressed by 8 or X directly
b. IF 8 < 16

c. IF 8 > 15

1-23

COP912C/COP912CH
UPPER NIBBLE BITS 7-4

JP-15

JP-31

LD OFO,#i

DRSZOFO

RRCA

JP-14

JP-30

LD OF1,#1

DRSZ,OF1

JP-13

JP-29

LD OF2,#i

DRSZOF2

XA(X+)

ADCA,
31

ADCA,
(B)

IFBIT
0, (B)

LD B, OF

IFBNE
0

JSR
OOOO-OOFF

JMP
OOOO-OOFF

JP+17

INTR

SUBCA,
#i

SUBC
A,(B)

IFBIT
1,(B)

LD B,OE

IFBNE
1

JSR
0100-01FF

JMP
0100-01FF

JP+1B

JP+2

XA,

IFEOA,
#i

IFEO,
#i

IFBIT
A,(B)

LD B, OD

IFBNE
2

JSR
0200-02FF

JMP
0200-02FF

JP+19

UJP+3

(X+)

A
RC.

JP-12

JP-2B

LD OF3#i

DRSZOF3

XA,(X-)

XA,
(B-)

IFGTA,
#i

IFGT
A,(B)

IFBIT
3, (B)

LDB,OC

IFBNE
3

JSR
0300-03FF

JMP
0300-03FF

JP+20

JP+4

JP-11

JP-27

LDOF4,#i

DRSZOF4

LAID

ADD A, #i

ADDA,
(B)

IFBIT
4, (B)

CLRA

LD B, OB

IFBNE
4

JSR
0400-04FF

JMP
0400-04FF

JP+21

JP+5

JP-10

JP-26

LD OF5,#i

DRSZOF5

JID

ANDA, #i

ANDA,
(B)

IFBIT
5,(B)

SWAPA

LD B, OA

IFBNE
5

JSR
0500-05FF

JMP
0500-05FF

JP+22

JP+6

1
2
3
I
I

JP-9

JP-25

LD OF6,#i

DRSZOF6

XA,(X)

XA,
(B)

XORA,
#i

XOR
A,(B)

IFBIT
6, (B)

DCORA

LDB,9

IFBNE
6

JSR
0600-06FF

JMP
0600-06FF

JP+23

JP+7

JP-B

JP-24

LDOF7,#i

DRSZOF7

ORA, #i

IFBIT
7,(B)

LDB,B

IFBNE
7

JSR
0700-07FF

JMP
0700-07FF

JP+24

JP+B

JP-7

JP-23

LD OFB,#i

DRSZOFB

NOP

ORA,
(B)

LDA, #i

IFC

SBIT
O,(B)

RBITO,
(B)

LDB,7

IFBNE
B

JSR
OBOO-OBFF

JMP
OBOO-OBFF

JP+25

SBIT
1,(B)

RBIT
1(B)

LDB,6

IFBNE
9

JSR
0900-09FF

JMP
0900-09FF

JP+26

SBIT
2,(B)

RBIT
2, (B)

LDB,5

IFBNE
OA

JSR
OAOO-OAFF

JMP
OAOO-OAFF

JP+27

4
5

I
I

:E
m
::D

r\:,
.j>..

JP-6
JP-5

JP-22
JP-21

LDOF9,#i
LDOFA,#i

DRSZOF9
DRSZOFA

IFNC

LDA,
X(+)

LDA,
(B+)

LD(B+), #i

INCA

JP+10
JP+11

DRSZOFB

LDA,
X(-)

LDA,
(B-)

LD(B-), #i

DECA

SBIT
3, (B)

RBIT
3, (B)

LDB,4

IFBNE
OB

JSR
OBOO-OBFF

JMP
OBOO-OBFF

JP+2B

JP+12

JP-3

JP-19

LDOFC,#i

DRSZOFC

LDMd,
#i

JMPL

XA,Md

SBIT
4,(B)

RBIT
4, (B)

LDB,3

IFBNE
OC

JSR
OCOO-OCFF

JMP
OCOO-OCFF

JP+29

JP+13

JP-2

JP-1B

LDOD,#i

DRSZOD

DIR

JSRL

LDA, Md

RETSK

SBIT
5,(B)

RBIT
5, (B)

LDB,2

IFBNE
OD

JSR
ODOO-ODFF

JMP
ODOO-ODFF

JP+30

JP+14

JP-1

JP-17

LOOFE,#i

DRSZOFE

LDA,(X)

LDA,
(B)

LOB, #i

RET

RBIT
6,(B)

LD B, 1

IFBNE
OE

JSR
OEOO-OEFF

JMP
OEOO-OEFF

JP+31

JP+15

SBIT
6,(B)

RETI

SBIT
7,(B)

RBIT
7, (B)

LDB,O

IFBNE
OF

JSR
OFOO-OFFF

JMP
OFOO-OFFF

JP+32

JP+16

DRSZOFF

- -

- - - - -

en
Co)

I
0

A
I

LD OFB,#i

LOOFF,#i

JP-20

JP-16

JP+9

JP-4

JP-O

B
C
D
E
F

o
of trace buffer memory. The user may define as many as
32k trace and break triggers which can be enabled, disabled, set or cleared. They can be simple triggers based on
code or address ranges or complex triggers based on code
address, direct address, opcode value, opcode class or immediate operand. Complex breakpoints can be ANDed and
ORed together. Trace information consists of address bus
values, opcodes and user selectable probe clips status (external event lines). The trace buffer can be viewed as raw
hex or as disassembled instructions. The probe clip bit values can be displayed in binary, hex or digital waveform formats.

Option List
The mask programmable options are listed out below. The
options are programmed at the same time as the ROM pattern to provide the user with hardware flexibility to use a
variety of oscillator configuration.
OPTION 1: CKIINPUT
= 1 Crystal (CKI/10) CKO for crystal configuration

2
= 3 R/C

NA
(CKI/10) CKO available as G7 input

OPTION 2: BONDING
= 2NA
= 3 20 pin DIP package
= 4 20 pin SO package

The following option information is to be sent to National
along with the EPROM.
Option Data
Option 1 Value_is: CKI Input
Option 2 Value_is: COP Bonding

To order a complete development package, select the section for the microcontroller to be developed and order the
parts listed. Contact the sales office for more details.

Development Support

co
.....
I\,)
o

::I:

IN-CIRCUIT EMULATOR
The MetaLink iceMASTERTM_COPB Model 400 In-Circuit
Emulator for the COPB family of microcontrollers features
high-performance operation, ease of use, and an extremely
flexible user-interface for maximum productivity. Interchangeable probe cards, which connect to the standard
ages of the COPB family.

The ice MASTER. connects easily to a PC via the standard
CO~.~~.1 pert ~r.:::! it: 115.2 ~B::t.!d ~~r::!! !:~~ ~cc;::: t}'~:c:.!
program download time to under 3 seconds.

The ice MASTER provides real time, full speed emulation up
to 10 MHz, 32 kBytes of emulation memory and 4k frames

The following tables list the emulator and probe cards ordering information:

........ _ _ .................................................... &.. ............. : .......... ___ 1:_ ............ : ............
L 101 IV

o"'C

How to Order

~\.oI..,t-'VI

I\,)

o
o

........

The iceMASTER's performance analyzer offers a resolution
of better than 6 I-'-s. The user can easily monitor the time
spent executing specific portions of code and find "hot
spots" or "dead code". Up to 15 independent memory areas based on code address or label ranges can be defined.
Analysis results can be viewed in bargraph format or as
actual frequency count.

5 NA

",""VIIIIIIVII t..IUo,.JVI

"'C

co
.....

= 1 NA

VU.IIVU~ '"'VIIlI~UIULIVII.;;)

_ .... ,..., __

,..I~

UIIU ..,U\"I''"'

Emulator Ordering Information
Part Number

Description

IM-COP8/400/1:j:

MetaLink base unit in-circuit emulator for all COPB devices, symbolic debugger
software and RS-232 serial interface cable, with 11 OV @ 60 Hz Power Supply.

IM-COPB/400/2:/:

MetaLink base unit in-circuit emulator for all COPB devices, symbolic debugger
software and RS-232 serial interface cable, with 220V @ 50 Hz Power Supply.

DM-COPB/BBO/:/:

MetaLink iceMASTER Debug Module. This is the low cost version of the MetaLink
iceMASTER.
Firmware: Ver. 6.07

Hhese parts include National's COPS Assembler/Linker/Librarian Package (COPS-DEV-IBMA)

1-25

Current Version

Host Software:
Ver. 3.3 Rev. 5,
Model File Rev 3.050

::c
o
,...
'"
en
a.

Development Support (Continued)

o.......
o

'",...en

Probe Card Ordering Information
Emulates

Part Number

Package

Voltage Range

MHW-880C20D5PC

20 DIP

4.5V-5.5V

COP912C, COP12CH

MHW-880C20DWPC

20 DIP

2.5V-6.0V

COP912C, COP912CH

MHW-SOIC20
(20-pin SO Adapter)

20S0

2.5V-6.0V

COP912C, COP912CH

MACRO CROSS ASSEMBLER

SINGLE CHIP EMULATOR DEVICE

National Semiconductor offers a COP8 macro cross assembier. It runs on industry standard compatible PCs and supports all of the full-symbolic debugging features of the
MetaLink ice MASTER emulators.

The COP8 family is fully supported by single chip form, fit,
and function emulators. For more detailed information refer
to the emulation device specific data sheets and the emu lator selection table below.

Assembler Ordering Information
Part Number

Description

COP8-DEV-IBMA COP8 Assembler/
Linker/Librarian for
IBM®, PC-XT®, AT®
or compatible

Manual
424410632-001

Single Chip Emulator Selection Table
Device Number

Package

Description

COP8782CN

20 DIP

OTP

COP912C,
COP912CH

COP8782CJ

20 DIP

UV Erasable

COP912C,
COP912CH·

COP8782CWM

20 SO

OTP

COP912C,
COP912CH

1-26

Emulates

Development Support (Continued)
PROGRAMMING SUPPORT

"co

Programming of the single chip emulator devices is supported by different sources. The following programmers are certified for
programming the One Time Programmable (OTP) devices:

EPROM Programmer Information

"co

Manufacturer
and Product

-a.

U.S. Phone
Number

MetaLink
-Debug Module

(602) 926-0797

Germany:
(49-81-41) 1030

Hong Kong:
(852) 737-1800

Xeltek
-Superpro

(408) 745-7974

Germany:
(49-20-41) 684758

Singapore:
(65) 276-6433

BP Microsystems
-EP-1140

(800) 225-2102

Germany:
(49-89-85) 76667

Hong Kong:
(852) 388-0629

Data I/O-Unisite;
-System 29,
-System 39

(800) 322-8246

Europe:
(31-20) 622866
Germany:
(49-89-85) 8020

Japan:
(33) 432-6991

System General
Turpro-1-FX;
-APRO

-a.

Asia Phone
Number

Europe Phone
Number

Abcom-COP8
Programmer

o
........

::t:

Europe:
(89-80) 8707
Taiwan, Taipei:
(2) 917-3005

Switzerland:
(31) 921-7844

(40B) 263-6667

INFORMATION SYSTEM

ORDER PIN: MOLE-DIAL-A-HLP

The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
:;o!t..;~ro ~i'id ut!:!t;~:; cCu:d bo ~vui,d. Tha "Ii •• ill.um ii;quiicment for accessing the Dial-A-Helper is a Hayes compatible
modem.

Information System Package contains:
Dial-A-Helper Users Manual
Public Domain Communications Software

FACTORY APPLICATIONS SUPPORT
Dial-A-Helper also provides immediate factory applications
:1 u Li:;~i hu5 quustiCii:;. h~ Caii :gg,'Va IIIo55Cigo5 vn
. our electronic bulletin board, which we will respond to.
:;up~Cit.

Voice:

If the user has a PC with a communications package then
files from the FILE SECTION can be down-loaded to disk for
later use.

(BOO) 272-9959

Modem: CANADA/U.S.: (800) NSC-MICRO
(BOO) 672-6427
Baud:

14.4k

Setup:

Length:

8-Bit

Parity:

None

Stop Bit: 1
Operation:

24 Hrs. 7 Days

1-27

oC\I
oo:::t'

......
o
o

t;tINational Semiconductor

oo:::t'

0)
......

oC\I COP620C/COP622C/COP640C/COP642CI
C\I

o
C\I

COP820C/COP822C/COP840C/COP842CI
COP920C/COP922C/COP940C/COP942C
Single-Chip microCMOS Microcontrollers

co
......

General Description

......

C\I

......
oo:::t'

oo:::t'
CO

......

oC\I
C\I

co
......
oo
C\I

CO
......

o
C\I
oo:::t'

CD
......
o
o

oo:::t'

The COP820C and COP840C are members of the COPSTM
microcontroller family. They are fully static parts, fabricated
using double-metal silicon gate microCMOS technology .
This low cost microcontroller is a complete microcomputer
containing all system timing, interrupt logic, ROM, RAM, and
I/O necessary to implement dedicated control functions in a
variety of applications. Features include an 8-bit memory
mapped architecture, MICROWIRE/PLUSTM serial I/O, a
16-bit timer/counter with capture register and a multisourced interrupt. Each I/O pin has software selectable options to adapt the device to the specific application. The
part operates over a voltage range of 2.5 to 6.0V. High
throughput is achieved with an efficient, regular instruction
set operating at a 1 microsecond per instruction rate.

CD
......

oC\I Features
C\I

CD
......

o
o

C\I

•
•
•
•

Low Cost 8-bit microcontroller
Fully static CMOS
1 JJ-s instruction time (10 MHz clock)
Low current drain (2.2 mA at 3 JJ-s instruction rate)
Low current static HALT mode (Typically <1 JJ-A)
• Single supply operation: 2.5 to 6.0V

• 1024 bytes ROM/64 Bytes RAM-COP820C family
• 2048 bytes ROM/128 Bytes RAM-COP840C family
• 16-bit read/write timer operates in a variety of modes
- Timer with 16-bit auto reload register
- 16-bit external event counter
- Timer with 16-bit capture register (selectable edge)
• Multi-source interrupt
- Reset master clear
- External interrupt with selectable edge
- Timer interrupt or capture interrupt
- Software interrupt
• 8-bit stack pointer (stack in RAM)
• Powerful instruction set, most instructions single byte
• BCD arithmetic instructions
• MICROWIRE/PLUS serial I/O
• 28 pin package (optionally 20 pin package)
• 24 input/output pins (28-pin package)
• Software selectable I/O options (TRI-STATE®, pushpull, weak pull-up)
• Schmitt trigger inputs on Port G
• Temperature ranges: O°C to + 70°C, - 40°C to + 85°C,
- 55°C to + 125°C
• Form Factor emulation devices
• Fully supported by MetaLink's development systems

Block Diagram
GND

II
nin
PORT L

PORT D

FIGURE 1

1-28

PORT G

PORT I

TL/DD/9103-1

a-0

COP920C/COP922C/COP940C/COP942C

Absolute Maximum Ratings

Total Current out of GNO Pin (Sink)
Storage Temperature Range

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
Voltage at any Pin
Total Current into Vee Pin (Source)

Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the de7
vice at absolute maximum ratings.

7V
-0.3V to Vee + 0.3V
50 rnA

DC Electrical Characteristics COP92XC, COP94XC; O°C :s: TA :s:
Parameter

Condition

Peak to Peak

Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz
CKI = 4 MHz
CKI = 1 MHz
HALT Current
(Note 3)

Vee
Vee
Vee
Vee
Vee
Vee

Typ

Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage

en
""
~

Max

Units

=
=
=
=
=
=

6V, tc = 1I-Ls
6V, tc = 2.51-Ls
4V, tc = 2.51-Ls
4V,tc = 1OI-Ls
6V, CKI = 0 MHz
4V, CKI = 0 MHz

<0.7
<0.4

4.0
6.0
0.1 Vee

V
V
V

6.0
4.0
2.0
1.2
8.0
5.0

rnA
rnA
rnA
rnA
I-LA
I-LA

""
(X)

""
N
(X)

""
(X)
~

""
N
CD

0.1 Vee

V
V

0.2 Vee

V
V

0.9 Vee

0.7 Vee
Vee
Vee

=
=

6.0V
6.0V, VIN

-1
-40

+1
-250

I-LA
I-LA

0.35 Vee

Output Current Levels
D Outputs

All Others
Source (Weak Pull-Up)

2.3
4.0

G Port Input Hysteresis

Sink

en
""
N

en
""
+ 70°C unless otherwise specified

Min

Input Levels
RESET,CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low

CC,UiCu

Operating Voltage
COP9XXC
COP9XXCH
Power Supply Ripple (Note 1)

Hi-Z Input Leakage
Input Pullup Current

60 rnA
- 65°C to + 140°C

"vee - ".')V,
",.." "VOH - "',.."
v.ov
Vee = 2.3V, VOH = 1.6V
Vee = 4.5V, VOL = 1.0V
Vee = 2.3V, VOL = O.4V
Vee
Vee
Vee
Vee
Vee
Vee
Vee

=
=
=
=
=
=
=

4.5V, VOH
2.3V, VOH
4.5V, VOH
2.3V, VOH
4.5V, VOL
2.3V, VOL
6.0V

= 3.2V
= 1.6V
= 3.8V
= 1.6V
= O.4V
= O.4V

-0.4

iliA

-0.2
10
2

rnA
rnA
rnA

-10
-2.5
-0.4
-0.2
1.6
0.7
-1.0

Allowable Sink/Source
Current Per Pin
o Outputs (Sink)
All Others
Maximum Input Current (Note 4)
Without Latchup (Room Temp)

Room Temp

RAM Retention Voltage, Vr

500 ns Rise and Fall Time (Min)

Input Capacitance
Load Capacitance on 02

1-29

-110
-33

""
N
CD

""
CD
~

I-LA
I-LA
rnA
rnA

+1.0

I-LA

15
3

rnA
rnA

±100

rnA

1000

2.0

oo::t

Q)
......

oo::t

......

o
N
N

......

oo
N

Q)
......

o
N

oo::t

co
......

oo::t

CO
......
o
N
N

co
......

N
CO

......
o
N
oo::t
CD

......

oo::t
CD

......
o
N
N

CD
......

o
o

N
CD

COP920C/COP922C/COP940C/COP942C
DC Electrical Characteristics (Continued)
Note 1: Rate of voltage change must be less than 0.5VI,rT)S.
Note 2: Supply current is measured after running 2000 .cycles with a squ~re wave CKI Input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee, Land Go-cG5 configured as
outputs and set high. The D port set to zero.',
" ."
"
Note 4: Except pin G7: + 100 mA, -25 mA (COP920C ~nIY). Sampled and not 100% tested. Pins G6 and I1ESET are designed with a high voltage input network
for factory testing. These pins allow Input voltages greate'r'than Vee and the pins will have sink current to Vee when biased at voltages greater than Vee (the pins
do not have source current when biased at a voltage below Vee). The effective resistance to Vee is 7500 (typical). These two pins will not latch up. The voltage at
the pins must be limited to less than 14V.
AC Electrical Characteristics o·c ~ TA':::: + 70·C unl~ss othe~ise specified
Parameter

Condition

Instruction Cycle Time (tc)
Ext., Crystal/Resonator
(Div-by 10)
R/C Oscillator Mode
(Div-by 10)

Vee ~ 4.0V
,2.3V ::::Vee:::: 4.0V
Vee ~ 4.0V
2.3V ::::Vee:::: 4.0V

CKI Clock Duty Cycle (Note 5)
Rise Time (Note 5)
Fall Time (Note 5)

fr
fr
fr

= Max
= 10 MHz Ext Clock '"
= 10 MHz Ext Clock

Typ

Max.

Units

1
2.5
3
7.5

DC
DC
DC
DC

60
12

%
' ns

,...5,
,...5
,...5
,...5

Inputs
Vee ~ ~.OV
2.3V :::: Vee:::: 4.0V
Vee ~ ~.OV
2.3V:::: Vee:::: 4.0V

tSETUP
tHOLO
Output Propagation Delay
t~01' tpoo
'
SO,SK

200
500
60
150

0.7
1.75
1
2.5

4.0V

2~,5V :::: Vee ::::.4.0V

Vee ~ 4.0V
2:5V:::: Vee:::: 4.0V

All Others
MICROWIRETM Setup Time (tuws)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output
Propagation Delay (tupo)
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

ns
ns
ns
ns

= 100 pF, RL = 2.2 kn

Vee

D-

Min

ns
ns

20
56
220

Reset Pulse Width

te'
te
te
te
1.0

Note 5: Parameter sampled (not 100% tested).

1·30

,...s
,...s
,...s
,...s

,...s

(')

a"'C

COP820C/COP822C/COP840C/COP842C
Absolute Maximum Ratings

Total Current out of GND Pin (Sink)
60mA
Storage Temperature Range
- 65°C to + 140°C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electri·
cal specifications are not ensured when operating the device at absolute maximum ratings.

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
7V
Voltage at any Pin
-0.3V to Vee + 0.3V
Total Current into Vee Pin (Source)
50mA

Condition

Operating Voltage
Power Supply Ripple (Note 1)

Peak to Peak

Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz
CKI = 4 MHz
CKI = 1 MHz
HALT Current (Note 3)

Vee
Vee
Vee
Vee
Vee

Min

6V, tc = 1 Ils
6V, tc = 2.51ls
4.0V, tc = 2.5 Ils
4.0V, tc = 10 Ils
6V, CKI = 0 MHz

Sink

Typ'

0l:Io

Max

Units

6.0
0.1 Vee

V
V

6.0
4.0
2.0
1.2
10

mA
mA
mA
mA
IlA

0.1 Vee

V
V

0.2 Vee

V
V

.+2
-250

IlA
IlA

0.35 Vee

0.9 Vee

0.7 Vee
Vee
Vee

= 6.0V
= 6.0V, VIN = OV

-2
-40

G Port Input Hysteresis
Output Current Levels
D Outputs
Source

N
(')

'"
00
N
o

(')

'"
00
N

N
(')

00
'"
0l:Io

(')

'"
00
0l:Io

Input Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current

(')

'"
0l:Io

+ 85°C unless otherwise specified

2.5

=
=
=
=
=

'"
N
0)

(')

DC Electrical Characteristics COP82XC, COP84XC: -40°C::;: TA ::;:
Parameter

(')

N
(')

CD
'"
N

(')

'"
CD
N

N
(')

'"
CD
0l:Io
o

(')

Vee
Vee
Vee
Vee

=
=
=
=

4.5V, VOH = 3.8V
2.5V, VOH = 1.8V
4.5V, VOL = 1.0V
2.5V, VOL = O.4V

-0.4
-0.2
10
2

Vee
Vee
Vee
Vee
Vee
Vee

=
=
=
=
=
=

4.5V, VOH = 3.2V
2.5V, VOH = 1.8V
4.5V, VOH = 3.8V
2.5V, VOH = 1.8V
4.5V, VOL = O.4V
2.5V, VOL = O.4V

-10
-2.5
-0.4
-0.2
1.6
0.7
-2.0

mA
mA
mA
mA

'"
CD
0l:Io
N
(')

AilOLIlt;"~

Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
Allowable Sink/Source
Current Per Pin
D Outputs (Sink)
All Others
Maximum Input Current (Note 4)
Without Latchup (Room Temp)
RAM Retention Voltage, Vr

Room Temp
500 ns Rise and
Fall Time (Min)

-110
-33

mA
+2.0

IlA

mA
mA

±100

2.0

Input Capacitance
Load Capacitance on D2

IlA
IlA
mA

V
7

1000

Note 1: Rate of voltage change must be less than O.SV/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave eKI input. CKO open. inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from OSCillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee. Land GO-GS configured as
outputs and set high. The D port set to zero.
Note 4: Except pin G7: + 100 rnA. - 25 rnA (COPB20C only). Sampled and not 100% tested. Pins G6 and 'Fii:m are designed with a high voltage input network
for factory testing. These pins allow input voltages greater than Vce and the pins will have sink current to Vee when biased at voltages greater than Vee (the pins
do not have source current when biased at a voltage below Vecl. The effective resistance to Vee is 7500 (typical). These two pins will not latch up. The voltage at
the pins must be limited to less than 14V.
1-31

o
N

"'I::t

COP820C/COP822C/COP840C/COP842C

o
o

AC Electrical Characteristics

en
.......
"'I::t

en
.......

oN
N

en
.......
o
o
N
en

.......

o
N

"'I::t

.......

"'I::t

CO
.......

Parameter

Vee ;;::4.5V
2.5V ~ Vee
Vee;;:: 4.5V
2.5V ~ Vee

CKI Clock Duty Cycle (Note 5)
Rise Time (Note 5)
Fall Time (Note 5)

fr = Max
fr = 10 MHz Ext Clock .
fr = 10 MHz Ext Clock

co
.......

tHOLD

N
CO

.......

Vee;;:: 4.5V
2.5V ~ Vee
Vee;;:: 4.5V
2.5V ~ Vee

Output Propagation Delay
tpD1, tpDO
SO,SK

Vee;;:: 4.5V
2.5V ~ Vee
Vee;;:: 4.5V
2.5V ~ Vee

o
o

All Others

"'I::t

CD
.......

o
N
N

CD
.......
oo
N

a..

o
o

1
2.5

< 4.5V

7.5
40

Max

Units

DC
DC
DC
DC

/-,-S

60
12
8

%
ns
ns

/-,-S
/-,-S

/-,-S

ns
ns
ns
ns

200
500
60
150

< 4.5V
< 4.5V

CL = 100 pF, RL = 2.2 kD.

"'I::t

.......

Typ

Inputs
tSETUP

Min

Condition

Instruction Cycle Time (tc)
Ext. or Crystal/Resonator
(Div-by 10)
R/C Oscillator Mode
(Div-by 10)

o
N
N

-40~C ~ T A ~ + 85°C unless otherwise specified

0.7
1.75
1
2.5

< 4.5V
< 4.5V

MICROWIRE Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output
Propagation Delay (tUPD)

220

te
te
te
te

Reset Pulse Width

1.0

Timing Diagram

fl=x=
!::::i
tuwh

. x=
t UPD

FIGURE 2~ MICROWIRE/PLUS Timing

1-32

/-,-S
/-,-S

/-,-S

Note 5: Parameter sampled (not 100% tested).

/-,-S

ns
ns

20
56

Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
. Timer Input High Time
Timer Input Low Time

/-,-S

TL/DD/9103-19

COP620C/COP622C/COP640C/COP642C

Absolute Maximum Ratings

Total Current out of GNO Pin (Sink)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
Voltage at any Pin
Total Current into Vee Pin (Source)

Storage Temperature Range

Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

6V
-0.3V to Vee + 0.3V
40mA

DC Electrical Characteristics COP62XC, COP64XC: Parameter

Condition

Operating Voltage
Power Supply Ripple (Note 1)

Peak to Peak

Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz
HALT Current (Note 3)

Vee = 5.5V, tc := 1 p,s
Vee = 5.5V, tc = 2.5 p,s
Vee = 5.5V, CKI = 0 MHz

55°C

:s: TA :s:
Min

RAM Retention Voltage, Vr

Max

Units

5.5
0.1 Vee

V
V

6.0
4
30

mA
mA
p,A

0.1 Vee

V
V

0.2 Vee

V
V

+5
-300

p,A
p,A

0.35 Vee

0.9 Vee

0.7 Vee
Vee = 5.5V
Vee = 4.5V, VIN = OV

-5
-35

Vee = 4.5V, VOH = 3.8V
Vee = 4.5V, VOL = 1.OV

-0.35
9

Vee = 4.5V, VOH = 3.2V
'.fCC == !r.C'J, 'v'OH - 3.o'y
Vee = 4.5V, VOL = O.4V

-0.35

-9
1.4
-5.0

Allowable Sink/Source
Current Per Pin
o Outputs (Sink)
All Others
Maximum Input Current (Room Temp)
Without Latchup (Note 5)

Typ

<10

G Port Input Hysteresis
Output Current Levels
o Outputs
Source
Sink
All Others
Source (Weak Pull-Up)
Source (Pu~h-P\.!!! ~.~cdc)
Sink (Push-Pull Mode)
TRI-STATE Leakage

+ 125°C unless otherwise specified

4.5

Input Levels
RESET,CKI
Logic High
Logic Low
All Other Inputs
Logie High
Logic Low
Hi-Z Input Leakage
Input Pullup Current

48mA
- 65°C to + 140°C

Room Temp
500 ns Rise and
Fall Time (Min)

mA
mA
-120

+5.0

p,A
mA
mA
p,A

12
2.5

mA
mA

±100

1000

2.5

Input Capacitance
Load Capacitance on 02

Note 1: Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee, Land GO-G5 configured as
outputs and set high. The 0 port set to zero.
Note 4: Except pin G7: + 100 mA, - 25 rnA (COP620C only). Sampled and not 100% tested. Pins G6 and f:fE:SE'f are designed with a high voltage input network
for factory testing. These pins allow input voltages greater than Vee and the pins will have sink current to Vee when biased at voltages greater than Vee (the pins
do not have source current when biased at a voltage below Vecl. The effective resistance to Vee is 7500 (typical). These two pins will not latch up. The voltage at
the pins must be limited to less than 14V.

1-33

en
......
o
o
~
en
......

oN
N

en
......

oo
N

en
......

o
N

......
oo
~

......

o
N
N

co
......
o

......

o
N

CD
......

o
N

N
CD

......

o
o
N

CD
D-

COP620C/COP622C/COP640C/COP642C
AC Electrical Characteristics

-55°C::;: TA ::;:

Parameter
Instruction Cycle Time (tc)
Ext. or Crystal/Resonant
(Div-by 10)
CKI Clock Duty Cycle
(Note 5)
Rise Time (Note 5)
Fall Time (Note 5)
Inputs
tSETUP
tHOLO
C?utput Propagation Delay
tPD1, tpoo
SO,SK
All Others

+ 125°C unless otherwise specified
Min

Condition
Vee

4.5V

fr = Max

Max

Units

p.s

12
8

ns
ns

fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
Vee ~ 4.5V
Vee ~ 4.5V

220
66

ns
ns

RL = 2.2k, CL = 100 pF
Vee ~ 4.5V
Vee ~ 4.5V

0.8
1.1
20
56

MICROWIRE Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Valid
Time (tupo)

te
te
te
te

Reset Pulse Width

p's

Parameter sampled (not 100% tested).

;

1-34

p's
p's
ns
ns

220

Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
.Timer Input High Time
Timer Input Low Time

Note 5:

Typ

Typical Performance Characteristics (-40°C:S; TA:S;

"'D

+85°C)

Dynamlc-IOO (Crystal Clock Option)

Halt-:-Ioo
0.35

0.3
':(

0.25

0.2

....

""::J:-<

,..'" '"

.85°e

0.15

0.1

10'

0.05

, ..

~~
/

,"1--"

3.5

...
.:; .-<4.5

5.5

Vee (V)

2.5

<4 101Hz

...~ .........(",-;;

o.......

' ,
',-,

en
oI:lo.

I\)

o
.......

1101Hz
3

3.5

TL/OO/9103-20

(X)
I\)

<4.5

5.5

6
TlIOO/91 03-21

Port L/G Push·Pull Source Current

Vee

.... 'L

::>

oI:lo.

I\)

o
.......

\
\

1--

o
0

o
.......

=<4.5V ~ -

I'
:--......vee =2.5V ,

(X)

I\)

<40

o
.......

.......

'60

0..

.......

VOH (V)

I\)
I\)

o.......
oI:lo.

':(

(X)
I\)
I\)

,I
I
Vee =6.0V -

100
80

o
.......
(X)

-...... ,
,

120

en
oI:lo.
o

~~'

Vee (V)

Port L/G Weak Pull·Up
Source Current

I\)

o.......

o
2.5

~ooe

0
2

10 101Hz

en
I\)
o
o.......
en
I\)

TL/OO/91 03-23

TlIOO/91 03-22

oI:lo.

o
.......
CD
oI:lo.

1<4

12
':(

"
,~
o li/

0.5

,,'" I
Vee
I

,,"

..-

Vee

=<4.5V

,=2.5V,

-...

I
I
',V ee =6.0V

'{
~ee=<4·5V \

- '1,\
--:::::

Vee = 2.5V

I I
2.5

Vee

.....

I I

1.5

.................

I
6.0V I

. . ~-t ..

J .. -1".

I\)

Port D Source Current

Port L/G Push·Pull Sink Current

VOL (V)

3.5

3
VOH (V)

TlIOO/9103-24

<40
35

,
I

'",.

o~
o

0.5

L'
~

.... =..Jo
Vee

6.0V

J1
I

Vee

=<4.5V

I- Vee

1 1.5

=2.5V

2 2.5 3 3.5 <4

VOL (V)

1-35

1'\

",
\

TL/OO/91 03-25

Port D Sink Current
<45

<4.5
TL/OO/9103-26

Connection Diagrams

DUAL-IN-LINE PACKAGE

.......
~

SURFACE MOUNT

.......

20 DIP

28 DIP

20 SO Wide

.......
oo
N

.......

o
N

co
.......
oo

G3jTlO

G.4/S0

G5/SK

G6/SI

GO/INT

G.4/S0

G7/CKO
CKI
VCC

CKI

RESET

vee

GNO

VCC

.......

L.4

co
.......

oo
N

CO
.......

o
N

.......

o
o

L6
L5

L.4

L7
17

Order Number COP622C-XXX/N,
COP642C-XXXIN, COP822C-XXXIN,
COP842C-XXXIN, COP922C-XXXIN
or COP942C-XXX/N
See NS Package Number N20A

1.4

L.4

GND
L7

mIT

CKI

.......

Gl
GO/INT

Top View

TL/DD/9103-3

G3jTlO
G2

G6/SI

GND

G7/CKO

mET
L7

o
N

G3jTlO

TL/DD/9103-5

Order Number COP620C-XXX/N,
COP640C-XXXIN, COP820C-XXX/N,
COP840C-XXX/D, COP920C-XXXIN
or COP940C-XXX/N
See NS Package Number N28B

TL/DD/91 03-3

Top View
Order Number COP822C-XXX/WM,
COP842C-XXX/WM,
COP922C-XXX/WM or
COP942C-XXX/WM
See NS Package Number M20B

o
N
N

.......

o
o

28-Lead SO

20DIP/SO

28 DIP/SO

D-

C4/S0
G5/SK

G7/CKO

C3/TIO

PORT 1 ,\",_ _;:.....1
1

VCC

GND

VCC

CKI

GND

GO/I NT

CKI

RESET

Vee

GNO

RESET

CKI
INTR
CKO
IAICROWIRE/PLUS
TLlDD/9103-6

01
13

L.4

RESET

INTR
CKO
MICROWIRE/PLUS
TL/DD/9103-B

, TL/DD/9103-1B

Order Number COP820C-XXX/WM,
COP840C-XXX/WM,
COP920C-XXX/WM or
COP940C-XXX/WM
See NS Package Number M28A
FIGURE 3. Connection Diagrams

1-36

PORT 0 is a four bit output port that is set high when
RESET goes low. Care must be exercised with the 02 pin
operation. At RESET, the external load on this pin must
ensure that the output voltage stays above 0.9 Vee to prevent the device from entering special modes. Also, keep the
external loading on the 02 pin to less than 1000 pf.

Pin Descriptions
Vee and GND are the power supply pins.
CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunction with CKO). See Oscillator description.
RESET is the master reset input. See Reset description.
PORT I is a four bit Hi-Z input port.
PORT L is an 8-bit I/O port.
There are two registers associated with each L I/O port: a
data register and a configuration register. Therefore, each L
I/O bit can be individually configured under software control
as shown below:
Port L
Config.

Port L
Data

Port L
Setup

0
0
1
1

0
1
0
1

Hi-Z Input (TRI-STATE)
Input With Weak Pull-Up
Push-Pull "0" Output
Push-Pull "1" Output

PortG
Config.

PortG
Data

PortG
Setup

0
0

0
1
0
1

Hi-Z Input (TRI-STATE)
Input With Weak Pull-Up
Push-Pujl "0" Output
Push-Pull "1" Output

i
1

<:)

""
N
0')

Functional Description

""
10

ALU AND CPU REGISTERS

co
""
N

There are five CPU registers:
A is the 8~bit Accumulator register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)

PORT G is an 8-bit port with 6 I/O pins (GO-GS) and 2 input
pins (G6, G7). All eight G-pins have Schmitt Triggers on the
inputs. The G7 pin functions as an input pin under normal
operation and as the continue pin to exit the HALT mode.
There are two registers with each I/O port: a data register
and a configuration register. Therefore, each I/O bit can be
individually configured under software control as shown below.

0')

Figure 1 shows the block diagram of the internal architecture. Data paths are illustrated in simplified form to depict
how the various logic elements communicate with each other in implementing the instruction set of the device.

The ALU can do an 8-bit addition, subtraction, logical or
shift operation in one cycle time.

Three data memory address locations are allocated for
these ports, one for data register, one for configuration register and one for the input pins.

a-a

0')
~

""
0')

<:)

co
""
N
N

co
""
~

<:)

S is the 8-bit address register, can be auto incremented or
decremented.

co
""

X is the 8-bit alternate address register, can be incremented
or decremented.

SP is the 8-bit stack pointer, points to subroutine stack (in
RAM).
S, X and SP registers are mapped into the on chip RAM.
The S and X registers are used to address the on chip RAM.
The SP register is used to address the stack in RAM dur!ng
subroutine calls and returns.
PROGRAM MEMORY
Program memory for the COP820C family consists of 1024
bytes of ROM (2048 bytes of ROM for the COP840C family).
These bytes may hold program instructions or constant
data. The program memory is addressed by the 1S-bit program counter (PC). ROM can be indirectly read by the LAID
instruction for table lookup.

CD
""
N
<:)

CD
""
N

CD
""
~

<:)

CD
""
~

DATA MEMORY
The data memory address space includes on chip RAM, I/O
and registers. Data memory is addressed directly by the instruction or indirectly by the S, X and SP registers.

The COP820C family has 64 bytes of RAM and the
COP840C family has 128 bytes of RAM. Sixteen bytes of
RAM are mapped as "registers" that can be loaded immediately, decremented or tested. Three specific registers: S, X
and SP are mapped into this space, the other bytes are
available for general usage.

Six bits of Port G have alternate features:

The instruction set permits any bit in memory to be set,
reset or tested. All I/O and registers (except the A & PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested.

GO INTR (an external interrupt)
G3 TIO (timer/counter input/output)
G4 SO (MICROWIRE serial data output)

Note: RAM contents are undefined upon power-up.

GS SK (MICROWIRE clock I/O)
G6 SI (MICROWIRE serial data input)

RESET

G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input (general purpose input)

The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the ports Land G are placed
in the TRI-STATE mode and the Port 0 is set high. The PC,
PSW and CNTRL registers are cleared_ The data and configuration registers for Ports L & G are cleared.

Pins G1 and G2 currently do not have any alternate functions.

The external RC network shown in Figure 4 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.
1-37

"'I:t

.......

Functional Description

o
o

"'I:t

.......

1pELP 1+

'"'"
.......
0)

:~ ~ ~

v:,

'"
"'I:t
'"

"'I:t

CX)

FIGURE 4. Recommended Reset Circuit

":-~

'"
'"
CX)

The device can be driven by a crystal clock. The crystal
network is connected between the pins CKI and CKO.

Table I shows the component values required for various
standard crystal values.

'"
.......
CX)

'"CD
.......
"'I:t

o
o

"'I:t

CD
.......

'"
CD
'"
.......

o
o

CKI

CKO

......
.1.......!'1''''

CC RESTART

~c
TLlDD/91 03-1 0

FIGURE 5. Crystal and R-C Connection Diagrams

B. EXTERNAL OSCIL.L.ATOR
CKI can be driven by an external clock signal. CKO is available as a general purpose input and lor HALT restart control.

OSCILL.ATOR MASK OPTIONS
The device can be driven by clock inputs between DC and
10 MHz.

C_ RIC OSCILL.ATOR
CKI is configured as a single pin RC controlled Schmitt trigger oscillator. CKO is available as a general purpose input
andl or HALT restart control.
Table II shows the variation in the oscillator frequencies as
functions of the component (R and C) values.

CD
'"

T ABL.E I. Crystal Oscillator Configuration, T A

o
o

"':"

Figure 5 shows the three clock oscillator configurations.
A. CRYSTAL OSCILL.ATOR

.......

=~C2

OSCILL.ATOR CIRCUITS

.......

CLOCK

~t:--tD~p Cl

5X Power Supply Rise Time

CX)

.......
o
o

REJART

...n.r
EXTERNAL

.~ Rl

TLlDD/9103-9
~

CKO

~ ..

CKI

'1'''''1'

.......

CKO
'" R2",

GND

A
CKI

o
o

(Continued)

= 25°C

R1
(kil)

R2
(Mn)

C1
(pF)

C2
(pF)

CKI Freq
(MHz)

Conditions

0
0
0

1
1
1

30
30
200

30-36
30-36
100-150

10
4
0.455

Vee = 5V
Vee = 5V
Vee = 5V

TABLE II. RC Oscillator Configuration, TA = 25°C
R
(kn)

C
(pF)

CKI Freq.
(MHz)

Instr. Cycle
(I-Ls)

3.3
5.6
6.8

82
100
100

2.2 to 2.7
1.1 to 1.3
0.9t01.1

3.7 to 4.6
7.4 to 9.0
8.8 to 10.8

Note: 3k

200k. 50 pF

200 pF

1-38

Conditions
Vee
Vee
Vee

= 5V
= 5V
= 5V

Functional Description

(Continued)

The device has three mask options for configuring the clock
input. The CKI and CKO pins are automatically configured
upon selecting a particular option.
-

Crystal (CKI/10) CKO for crystal configuration

External (CKI/10) CKO available as G7 input
RIC (CKI/10) CKO available as G7 input

OOOOH. A low to high transition on the eKO pin (only if the
external or the RIC clock option is selected) causes the
microcontroller to continue with no reinitialization from the
address following the HALT instruction. This also resets the
G7 data bit.
INTERRUPTS

There are three interrupt sources, as shown below.

G7 can be used either as a general purpose input or as a
control input to continue from the HALT mode.

A maskable interrupt on external GO input (positive or negative edge sensitive under software control)

CURRENT DRAIN

A maskable interrupt on timer underflow or timer capture

The total current drain of the chip depends on:

A non-maskable software I error interrupt on opcode zero

1) Oscillator operating mode-11
2) Internal switching current-12

INTERRUPT CONTROL

3) Internal leakage current-13

The GIE (global interrupt enable) bit enables the interrupt
function. This is used in conjunction with ENI and ENTI to
select one or both of the interrupt sources. This bit is reset
when interrupt is acknowledged.

4) Output source current-14
5) DC current caused by external input not at Vee or GND15
.

ENI and ENTI bits select external and timer interrupt respectively. Thus the user can select either or both sources
to interrupt the microcontroller when GIE is enabled:

Thus the total current drain, It is given as
It = 11 + 12 + 13 + 14 + 15
To reduce the total current drain, each of the above components must be minimum.

IEDG selects the external interrupt edge (0 = rising edge,
1 = falling edge). The user can get an interrupt on both
rising and falling edges by toggling the state of IEDG bit
after each interrupt.
IPND and TPND bits signal which interrupt is pending. After
interrupt is acknowledged, the user can check these two
bits to determine which interrupt is pending. This permits the
interrupts to be prioritized under software. The pending flags
have to be cleared by the user. Setting the GIE bit high
inside the interrupt subroutine allows nested interrupts.
The software interrupt does not reset the GIE bit. This
means that the controller can be interrupted by other interrupt sources while servicing the software interrupt.

Operating with a crystal network will draw more current than
an external square-wave. The RIC mode will draw the most.
Switching current, governed by the equation below, can be
reduced by lowering voltage and frequency. Leakage current can be reduced by lowering voltage and temperature.
The other two items can be reduced by carefully designing
the end-user's system.
12 = CxVxf
Where
C = equivalent capacitance of the chip.
V = operating voltage
f = CKI frequency

INTERRUPT PROCESSING

The device supports a power saving mode of operation:
HALT. The controller is placed in the HALT mode by setting
the G7 data bit, alternatively the user can stop the clock
input. In the HALT mode all internal processor activities including the clock oscillator are stopped. The fully static architecture freezes the state of the controller and retains all
information until continuing. In the HALT mode, power requirements are minimal as it draws only leakage currents
and output current. The applied voltage (Vee> may be decreased down to Vr (minimum RAM retention voltage) without altering the state of the machine.

The interrupt, once acknowledged, pushes the program
counter (PC) onto the stack and the stack pointer (SP) is
decremented twice. The Global Interrupt Enable (GIE) bit is
reset to disable further interrupts. The microcontroller then
vectors to the address OOFFH and resumes execution from
that address. This process takes 7 cycles to complete. At
the end of the interrupt subroutine, any of the following
three instructions return the processor back to the main program: RET, RETSK or RETI. Either one of the three instructions will pop the stack into the program counter (PC). The
stack pointer is then incremented twice.. The RETI instruction additionally sets the GIE bit to re-enable further interrupts.

There are two ways to exit the HALT mode: via the RESET
or by the CKO pin. A low on the RESET line reinitializes
the microcontroller and starts executing from the address

Any of the three instructions can be used to return from a
hardware interrupt subroutine. The RETSK instruction
should be used when returning from a software interrupt
subroutine to avoid entering an infinite loop.

1-39

o
N
V

en
.......

Functional Description

(Continued)

oo
v

en
.......

EXTERNAL
INT. PIN

o
N
N

en
.......

o
o

TO
INTERRUPT
LOGIC

TIt.4ER
UNDERFLOW----I

.......

SOFTWARE
INTERRUPT-----------------'

TL/DD/9103-11

.......
oo
v
CO

o'"
N
N

co
.......

oo
N

CO
.......

o
N
V

.......

o
o

v
(Q
.......

o
N
N

.......

o
o
N

o
o

FIGURE 6. Interrupt Block Diagram

TABLE III

DETECTION OF ILLEGAL CONDITIONS

The device contains a hardware mechanism that allows it to
detect illegal conditions which may occur from coding errors, noise and 'brown out' voltage drop situations. Specifically it detects cases of executing out of undefined ROM
area and unbalanced stack situations.

SL1

SLO

SK Cycle Time

0
0
1

0
1
x

2te
4te
Bte

Reading an undefined ROM location. returns 00 (hexadecimal) as its contents. The opcode for a software interrupt is
also '00'. Thus a program accessing undefined ROM will
cause a software interrupt.

te is the instruction cycle clock.

Reading an undefined RAM location returns an FF (hexadecimal). The subroutine stack grows down for each subroutine call. By initializing the stack pointer to the top of RAM,
the first unbalanced return instruction will cause the stack
pointer to address undefined RAM. As a result the program
will attempt to execute from FFFF (hexadecimal), which is
an undefined ROM location and will trigger a software interrupt.

Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS arrangement to start shifting the data. It
gets reset when eight data bits have been shifted. The user
may reset the BUSY bit by software to allow less than 8 bits
to shift. The device may enter the. MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 8 shows how
two microcontrollers and several peripherals may be interconnected using the MICROWIRE/PLUS arrangement.

MICROWIRE/PLUSTM

Master MICROWIRE/PLUS Operation

MICROWIRE/PLUS is a serial synchronous bidirectional
communications interface. The MICROWIRE/PLUS capabil~
ity enables the device to interface with any of National
Semiconductor's MICROWIRE peripherals (Le. AID converters, display drivers, EEPROMS, etc.) and with other microcontrollers which support the MICROWIRE/PLUS interface. It consists of an 8-bit serial shift register (SIO). with
serial data input (SI), serial data output (SO) and serial shift
clock (SK). Figure 7 shows the block diagram of the M ICROWIRE/PLUS interface.

In the MICROWIRE/PlUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE/
PLUS Master always initiates all data exchanges. (See Figure 8). The MSEL bit in the CNTRL register must be set to
enable the SO and SK functions onto the G Port. The SO
and SK pins must also be selected as outputs by setting
appropriate bits in the Port G configuration register. Table IV
summarizes the bit settings required for Master mode of
operation.

where,

MICROWIRE/PLUS OPERATION

SLAVE MICROWIRE/PLUS OPERATION

The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIRE/
PLUS interface with the internal clock source is called the
Master mode of operation. Similarly, operating the MICROWIRE/PLUS interface with an external shift clock is called
the Slave mode of operation.

In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRl register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by appropriately
setting up the Port G configuration register. Table IV summarizes the settings required to enter the Slave mode of
operation.

The CNTRl register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS ,
the MSEl bit in the CNTRL register is set to one. The SK
clock rate is selected by the two bits, SLO and Sl1, in the
CNTRl register. Table III details the different clock rates
that may be selected.

1-40

Functional Description

(Continued)

-C
0')

TABLE IV

Fun.

Int.SK

MICAOWIAE Master

TAl-STATE Int. SK

MICAOWIAE Master

Ext.SK

MICAOWIAE Slave

TAl-STATE Ext. SK

MICAOWIAE Slave

Conflg. Conflg.

Bit

MODE 1. TIMER WITH AUTO-LOAD REGISTER

In this mode of operation, the timer T1 counts down at the
instruction cycle rate. Upon underflow the value in the register R1 gets automatically reloaded into the timer which continues to count down. The timer underflow can be programmed to interrupt the microcontroller. A bit in the control
register CNTRl enables the TIO (G3) pin to toggle upon
timer underflows. This allow the generation of square-wave
outputs or pulse width modulated outputs under software
control. (See Figure 9)

Operation

TIMER/COUNTER
The device has a powerful 16-bit timer with an associated
16-bit register enabling them to perform extensive timer
functions. The timer T1 and its register R1 are each organized as two 8-bit read/write registers. Control bits in the
register CNTRl allow the timer to be started and stopped
under software control. The timer-register pair can be operated in one of three possible modes_ Table V details various
timer operating modes and their requisite control settings.

I+--------SI

TI/L._ _ _--'

A1 \ . , - - - - - - - '

B
U
S

0')

N
N

o
........
0')
~

MODE~EXTERNALCOUNTER

In this mode, the timer T1 becomes a 16-bit external event
counter. The counter counts down upon an edge on the TIO
pin. Control bits in the register CNTRl program the counter
to decrement either on a positive edge or on a negative
edge. Upon underflow the contents of the register R1 are
automatically copied into the counter. The underflow can
also be prograrnmed to generate an interrupt. (See Figure 9)

MODE 3. TIMER WITH CAPTURE REGISTER

o
o
........

........

Timer T1 can be used to precisely measure external frequencies or events in this mode of operation. The timer T1
counts down at the instruction cycle rate. Upon the occurrence of a specified edge on the TIO pin the contents of the
timer T1 are copied into the register R1. Bits in the control
register CNTRl allow the trigger edge to be specified either
as a positive edge or as a negative edge. In this mode the
user can elect to be interrupted on the specified trigger
edge. (See Figure 10.)

~-----------------'so

........
Q)

N
N

o
........
Q)
~

........
CO

o........
CO

N
N

o
........
CO
~

o........
CO
~

TL/DD/9103-12

FIGURE 7. MICROWIRE/PLUS Block Diagram

CHIP SELECT LINES

EEPROM

LCD
DISPLAY
DRIVER

!
CS

I/o
LINES

¢;

I/o
COP
B20C
(MASTER)

8 - 81T
A/O CONVERTER
COP43X

SI
so

01 ClK

coP
820C
(SLAVE)

SO
51
SK
TL/DD/9103-13

FIGURE 8. MICROWIRE/PLUS Application

1-41

(.)
C\I

-.::r

........

Functional Description

(.)

TABLE V. Timer Operating Modes

-.::r

........
(.)

CNTRl
Bits

C\I
C\I

765

........

000
001
010
01 1
100
101
110
111

(Continued)

Operation Mode

T Interrupt

External Counter W I Auto-Load Reg.
External Counter WI Auto-Load Reg.
Not Allowed
Not Allowed
Timer WI Auto-Load Reg.
Timer WI Auto-Load Reg'/Toggle TID Out
Timer W/Capture Register
Timer W ICapture Register

Timer Underflow
Timer Underflow
Not Allowed
Not Allowed
Timer Underflow
Timer Underflow
TID Pos. Edge
TID Neg. Edge

Timer
Counts·
On

(.)

C\I

........
(.)
C\I

-.::r

........
(.)

o
-.::r
CO

TID Pos. Edge
TID Neg. Edge
Not Allowed
Not Allowed
tc
tc
tc
tc

........
(.)

TIMER PWM APPLICATION
Figure 11 shows how a minimal component 01 A converter
can be built out of the Timer-Register pair in the Auto-Reload mode. The timer is placed in the "Timer with auto reload" mode and the TID pin is selected as the timer output.
At the outset the TID pin is set high, the timer T1 holds the
on time and the register R1 holds the signal off time. Setting
TRUN bit starts the timer which counts down at the instruction cycle rate. The underflow toggles the TID output and
copies the off time into the timer, which continues to run. By
alternately loading in the on time and the off time at each
successive interrupt a PWM frequency can be easily generated.

C\I
C\I
CO

........

(.)

C\I
CO

........

(.)
C\I

-.::r
CD

........

TIO
OUTPUT

(.)

o
-.::r

........

TLlDD/91D3-15

(.)

FIGURE 9. Timer/Counter Auto
Reload Mode Block Diagram

C\I
C\I

........

Ton

(.)

C\I

rl.

o
(.)
C

TID INPUT

o
P
8
2

/~
t?
R

TIO

A SIMPLE D- A
CONVERTER USING
THE TIMER TO
GENERATE A PWM
OUTPUT.
TL/DD/9103-16

TL/DD/9103-14

FIGURE 11. Timer Application

FIGURE 10. Timer Capture Mode Block Diagram

1-42

o
This mode is used for the JP instruction, the instruction field
is added to the program counter to get the new program
location. JP has a range of from -31 to +32 to allow a one
byte relative jump (JP + 1 is implemented by a NOP instruction). There are no 'pages' when using JP, all 15 bits of PC
are used.

CNTRl REGISTER (ADDRESS X'OOEE)
The Timer and MICROWIRE/PLUS control register contains
the following bits:
SL 1 & SLO Select the MICROWIRE/PLUS clock divide-by
IEDG

External interrupt edge polarity select

All RAM, ports and registers (except A and PC) are mapped
into data memory address space.

SK
Start/Stop the Timer/Counter (1 = run, 0 =
stop)

TC2

Selects the capture mode

TC1

Selects the timer mode

TC1

Contents

COP820C Family
00 to 2F On Chip RAM Bytes
30 to 7F Unused RAM Address Space (Reads as all Ones)

TC21 TC31 TRUN I MSEL IIEDG I SL 1 I SLO

BIT7

BITO

Carry Flag
Half carry Flag

I HC

I C I TPND I ENTI IIPND I BUSY I ENI I GIE

Bit7

BitO

Addressing Modes
REGISTER INDIRECT
This is the "normal" mode of addressing. The operand is
the memory addressed by the B register or X register.
DIRECT
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
IMMEDIATE
The instruction contains an 8-bit immediate field as the operand.
REGISTER INDIRECT
(AUTO INCREMENT AND DECREMENT)
This is a register indirect mode that automatically increments or decrements the B or X register after executing the
instruction.

DOto DF
DO
D1
D2
D3
D4
D5
D6
D7
D8-DB
DC
DD-DF

On Chip I/O and Registers
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Reserved for Port C
Port D Data Register
Reserved for Port D

EO to EF
EO-E7
E8
E9
EA
EB
EC
ED
EE
EF

On Chip Functions and Registers
Reserved for Future Parts
Reserved
MICROWIRE/PLUS Shift Register
Timer Lower Byte
Timer Upper Byte
Timer Autoload Register Lower Byte
Timer Autoload Register Upper Byte
CNTRL Control Register
PSW Register

FO to FF
FC
FD
FE

On Chip RAM Mapped as Registers
X Register
SP Register
B Register

Reading unused memory locations below 7FH will return all
ones. Reading other unused memory locations will return
undefined data.

1-43

en
N
N

en
~

o
.......
o
.......

COtoCF Expansion Space for I/O and Registers

o
.......

External interrupt enable

TPND Timer interrupt pending

COP820C and COP840C Families

ENI

BUSY MICROWIRE/PLUS busy shifting

o
.......

80 to BF Expansion Space for on Chip EERAM

External interrupt pending

0')

00 to 6F On Chip RAM Bytes
70 to 7F Unused RAM Address Space (Reads as all Ones)

Global interrupt enable

Timer interrupt enable

o
o
.......

o
.......

GIE

ENTI

N
N

o
.......

COP840C Family

PSW REGISTER (ADDRESS X'OOEF)
The PSW register contains the following select bits:

IPND

0')

Address

Timer input edge polarity select (0 = rising
edge, 1 = falling edge)

TC3

o
.......

Memory Map

Enable MICROWIRE/PLUS functions SO and

TRUN

0')

(0 = rising edge, 1 = falling edge)
MSEL

a"'tJ

RELATIVE

Control Registers

co
N

o
.......
co
N
N

o
.......
co
~
o
o.......
co
~

o
N

-.::t

Instruction Set

-.::t

en
.......

Registers

o
N

en
.......

o
o

Symbols
[B]
Memory indirectly addressed by B register

8-bit Accumulator register

[X]

Memory indirectly addressed by X register

8-bit Address register

Mem

Direct address memory or [B]

8-bit Address register

Meml Direct address memory or [B] or Immediate data

8-bit Stack pointer register

Imm

8-bit Immediate data

15-bit Program counter register

Reg

o
N

upper 7 bits of PC

lower 8 bits of PC

en
.......
-.::t

co
.......

-.::t
CO

.......

1-bit of PSW register for carry

Half Carry

GIE

1-bit of PSW register for global interrupt enable

oN
oo

N
CO

.......

-.::t

.......

-.::t

CD
.......

oN
N

Bit number (0 to 7)
Loaded with
Exchanged with

Instruction Set

co
.......

Bit
+-

ADD
ADC

add
add with carry

SUBC

subtract with carry

AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT

Logical AND
Logical OR
Logical Exclusive-OR
IF equal
IF greater than
IF B not equal
Decrement Reg. ,skip if zero
Set bit

A A + Meml
A A + Meml + C, C Carry
HC Half Carry
A A + Meml +C,C Carry
HC Half Carry
A AandMeml
A AorMeml
A AxorMeml
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B *- Imm
Reg - 1, skip if Reg goes to 0
Reg 1 tobit,
Mem (bit= 0 to 7 immediate)
Otobit,
Mem
If bit,
Mem is true, do next instr.

CD
.......

RBIT

Reset bit

IFBIT

If bit

X
LOA
LDmem
LDReg

Exchange A with memory
Load A with memory
Load Direct memory Immed.
Load Register memory Immed.

A ......... Mem

X
X
LOA
LOA
LDM

Exchange A with memory [BI
Exchange A with memory [XI
Load A with memory [BI
Load A with memory [xl
Load Memory Immediate

A ......... [BI
A ......... [XI

CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC

Clear A
IncrementA
Decrement A
Load A indirect from ROM
DECIMAL CORRECT A
ROTATE A RIGHT THRU C
Swap nibbles of A
SetC
ResetC
IfC
IfnotC

A-O

JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

Jump absolute long
Jump absolute
Jump relative short
Jump subroutine long
Jump subroutine
Jump indirect
Return from subroutirie
Return and Skip
Return from Interrupt
Generate an interrupt
No operation

PC ii (ii = 15 bits, 0 to 32k)
PC11 .. 0 i(i = 12 bits)
PC PC + r(ris -31 to +32,not1)
[SpI PL,[SP-11 PU,SP-2,PC ii
[SPI pL,[SP-11 PU,SP-2,PC11 .. 0 i
PL ROM(PU,A)
SP + 2,PL [SP),PU [SP-11
SP+2,PL [SPI,PU [SP-1I,Skip next instruction
SP+2,PL [SP),PU [SP-1),GIE 1
[SPI PL,[SP-11 PU,SP-2,PC OFF
PC-PC+1

o
o

D..

A Meml
Mem Imm
Reg Imm
(B B±1)
(X X±1)
(B B±1)
A [BI
(X X±1)
A [XI
[BI Imm (B B±1)
A
A
A
A

A+ 1
A-1
ROM(PU,A)
BCD correction (follows ADC, SUBC)

C A7 ... AO A7 ... A4 ......... A3 ... AO

C 1,HC 1
C O,HC 0
If C is true, do next instruction
If C is not true, do next instruction

1-44

o
"0
o
o

Bits 7-4

JP -15

JP -31

LDOFO,#i

DRSZOFO

RRCA

ADCA,
#i

ADCA,
[B]

IFBIT
O,[B]

JP -14

JP-30

LD OF1,#i

DRSZOF1

SUBCA,
#i

SUBC
A,[B]

IFBIT
1,[B]

JP -13

JP-29

LDOF2,#i

DRSZOF2

XA,
[X+]

XA,
[B+]

IFEOA,
#i

IFEO
A,[B]

IFBIT
2,[B]

XA,
[X-]

XA,
[B-]

IFGTA,
#i

IFGT
A,[B]

IFBIT
3,[B]

LAID

ADD A,
#i

ADD
A,[B]

IFBIT
4,[B]

JID

ANDA,
#i

AND
A,[B]

XA,
[X]

XA,
[B]

XORA,
#i

LD B, OF

IFBNEO

JSR
OOOO-OOFF

JMP
OOOO-OOFF

JP + 17

INTR

LDB,OE

IFBNE 1

JSR
0100-01FF

JMP
0100-01FF

JP + 1B

JP + 2

LDB,OD

IFBNE2

JSR
0200-02FF

JMP
0200-02FF

JP + 19

JP + 3

LD B,OC

IFBNE3

JSR
0300-03FF

JMP
0300-03FF

JP + 20

JP + 4

CLRA

LD B,OB

IFBNE4

JSR
0400-04FF

JMP
0400-04FF

JP + 21

JP + 5

IFBIT
5,[B]

SWAPA

LDB,OA

IFBNE5

JSR
0500-05FF

JMP
0500-05FF

JP + 22

JP + 6

XOR
A,[B]

IFBIT
6,[B]

DCORA

LDB,9

IFBNE6

JSR
0600-06FF

JMP
0600-06FF

JP + 23

JP + 7

ORA,
#i

OR
A,[B]

IFBIT
7,[B]

LDB,B

IFBNE7

JSR
0700-07FF

JMP
0700-07FF

JP + 24

JP + B

IFC

SBIT
O,[B]

RBIT
O,[B]

LDB,7

IFBNEB

JSR
OBOO-OBFF

JMP
OBOO-OBFF

JP + 25

JP + 9

B o

LDA,
#i

IFNC

JSR
0900-09FF

JMP
0900-09FF

JP + 26

JP + 10

RBIT
1,[B]

IFBNE9

SBIT
1,[B]

LDB,6

JP -12
JP -11

JP-2B
JP-27

LD OF3,#i
LDOF4,#i

DRSZOF3
DRSZOF4

*
JP -10

JP-26

LDOF5,#i

DRSZOF5

*
JP-9

JP-25

LDOF6,#i

DRSZOF6

JP-B

JP -24

LD OF7,#i

DRSZOF7

.J,.
U1

JP-7

JP-23

LDOFB,#i

DRSZOFB

JP-6

JP-22

LDOF9,#i

DRSZOF9

NOP

m
0 r-

c,.)

JP-5

JP -21

LDOFA,#i

DRSZOFA

LDA,
[X+]

LDA,
[B+]

LD
[B+l,#i

INCA

SBIT
2,[B]

RBIT
2,[B]

LDB,5

IFBNEOA

JSR
OAOO-OAFF

JMP
OAOO-OAFF

JP + 27

JP + 11

JP-4

JP-20

LDOFB,#i

DRSZOFB

LDA,
[X-]

LDA,
[B-]

LD
[B-l,#i

DECA

SBIT
3,[B]

RBIT
3,[B]

LDB,4

IFBNEOB

JSR
OBOO-OBFF

JMP
OBOO-OBFF

JP + 2B

JP + 12

JP-3

JP -19

LDOFC,#i

DRSZOFC

LDMd,
#i

JMPL

XA,Md

SBIT
4,[B]

RBIT
4,[B]

LDB,3

IFBNEOC

JSR
OCOO-OCFF

JMP
OCOO-OCFF

JP + 29

JP +13

DIR

JSRL

SBIT
5,[B]

RBIT
5,[B]

LDB,2

IFBNEOD

JSR
ODOO-ODFF

JMP
ODOO-ODFF

JP + 30

JP +14

JP-2

JP -1B

LDOFD,#i

DRSZOFD

JP -1

JP -17

LDOFE,#i

DRSZOFE

JP -0

JP -16

LD OFF,#1

DRSZOFF

LDA,
[X]

*
where,

is the immediate data

*
LDA,
[B]

LDA,
Md

RETSK

LD
[Bl, #i

RET

SBIT
6, [B]

RBIT
6, [B]

LD B,1

IFBNEOE

JSR
OEOO-OEFF

JMP
OEOO-OEFF

JP + 31

JP +15

RETI

SBIT
7,[B]

RBIT
7,[B]

LDB,O

IFBNEOF

JSR
OFOO-OFFF

JMP
OFOO-OFFF

JP + 32

JP + 16

Md is a directly addressed memory locatio.l

D
E

-'-----

• is an unused opcode (see following table)

O~"6/00"6/0~~6/00~6/0~"8/00"8/0~~8/00~8/0~"9100"9/0~~9/OO~9dOO

IiiI

o
N

(7)

Instruction Execution Time

o
o

Most instructions are single byte (with immediate addressing mode instruction taking two bytes).

(7)

Most single instructions take one cycle time to execute.
See the BYTES and CYCLES per INSTRUCTION table for
details.

""=t'

.......
""=t'

.......

oN
N

The following table shows the instructions assigned to unused opcodes. This table is for information only. The operations performed are subject to change without notice. Do
.
not use these opcode~.
Unused
Opcode

(7)

.......

(7)

BYTES and CYCLES per
INSTRUCTION

The following table shows the number of bytes and cycles
for each instruction in the format of byte/cycle.

.......
""=t'

60
61
62
63
67
BC
99
9F
. A7
AB

co
.......

Arithmetic and Logic Instructions

""=t'

[B]

Direct

Immed.

ADD
AOC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
ORSZ

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4

2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2

SBIT
RBIT
IFBIT

1/1
1/1
1/1

3/4
3/4
3/4

.......

o
N
N

co
.......

o
o
N

co
.......

o
N

""=t'
U)

.......

""=t'

.......

o
N
N

.......

Instruction

Unused
Opcode

Instruction

A9
AF
B1
B4
B5
B7
B9
BF

NOP
LOA, [B]
C ~ HC
NOP
NOP.
XA, [X]
NOP
LOA, [X]

NOP
NOP
NOP
NOP
NOP
RET
NOP
LO [B], #i
XA, [B]
NOP

1/3

Memory Transfer Instructions

Register
Register Indirect
Indirect Direct Immed.
Auto Incr & Decr
[B] [X]
[B+,B-]· [X+,X-]
XA,·
1/1 1/3
LOA,·
1/1 1/3
LOB,lmm
LO B,lmm
2/2
LOMem,lmm
LO Reg,lmm
• =

2/3
2/3

1/2
1/2

2/2
1/1
2/3

1/3
1/3
(If B < 16)
(If B > 15)

3/3

2/2
2/3

> Memory location addressed by B or X or directly.

Instructions Using A & C
CLRA
INCA
OECA
LAID
OCORA
RRCA
SWAPA
SC
RC
IFC
IFNC

Transfer of Control Instructions

1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1

JMPL
JMP
JP
JSRL
JSR
JIO
RET
RETSK
RETI
INTR
NOP

1-46

3/4
2/3
1/3
3/5
2/5.
1/3
1/5
1/5
1/5

117
1/1

32k trace and break triggers which can be enabled, disabled, set or cleared. They can be simple triggers based on
code or address ranges or complex triggers based on code
address, direct address, opcode value, opcode class or immediate operand. Complex breakpoints can be ANDed and
ORed together. Trace information consists of address bus
values, opcodes and user selectable probe CIiI1S status (external event lines). The trace buffer can be viewed as raw
'lex or as disassembled instructions. The probe clip bit valJes can be displayed in binary, hex or digital waveform formats.

OPTION 1: CKIINPUT
= 1 Crystal (CKI/10) CKO for crystal configuration
= 2 External (CKI/10) CKO available as G7 input
= 3 RIC
(CKI/10) CKO available as G7 input

OPTION 2: BONDING
= 1 28 pin package
= 2 N.A.
= 3 20 pin package
= 4 20 SO package

The iceMASTER's performance analyzer offers a resolution
of better than 6 I-ls. The user can easily monitor the time
spent executing specific portions of code and find "hot
spots" or "dead code". Up to 15 independent memory areas based on code address or label ranges can be defined.
Analysis results can be viewed in bargraph format or as
actual frequency count.

= 5 28 SO package
The following option information is to be sent to National
along with the EPROM.

Option Data
Option 1 Value_is: CKI Input
Option 2 Value_is: COP Bonding

How to Order
To order a complete development package, select the section for the microcontroller to be developed and order the
parts listed. Contact the sales office for more detail.

The iceMASTER. comes with an easy to use windowed interface. Each window can be sized, highlighted, color-controlled, added, or removed completely. Commands can be
accessed via pull-down-menus and/or redefineable hot
keys. A context sensitive hypertextlhyperlinked on-line help
system explains clearly the options the user has from within
any window.

Development Support
IN-CIRCUIT EMULATOR
The MetaLink iceMASTERTM-COP8 Model 400 In-Circuit
Emulator for the COP8 family of microcontrollers features
high-performance operation, ease of use, and an extremely
flexible user-interface for maximum productivity. Interchangeable probe cards, which connect to the standard
common base, support the' various configurations and packages of the COP8 family.

The ice MASTER connects easily to a PC via the standard
COMM port and its 115.2 kBaud serial link keeps typical
program download time to under 3 seconds.
The following tables list the emulator and probe cards ordering information:

The ice MASTER provides real time, full speed emulation up
to 10 MHz, 32 kBytes of emulation memory and 4k frames
of trace buffer memory. The user may define as many as

Emulator Ordering Information
Part Number

Description

IM-COP8/400/1 :j:

MetaLink base unit in-circuit emulator for all COP8 devices, symbolic debugger
software and RS-232 serial interface cable, with 11 OV @ 60 Hz Power Supply.

IM-COP8/400/2:j:

MetaLink base unit in-circuit emulator for all COP8 devices, symbolic debugger
software and RS-232 serial interface cable, with 220V @ 50 Hz Power Supply.

DM-COP8/880/:j:

MetaLink iceMASTER Debug Module. This is the low cost version of the MetaLink
iceMASTER. Firmware: Ver.6.07.

Hhese parts include National's COPS Assembler/linker/librarian Package (COPS·DEV·IBMA)

1-47

Current Version

HOST SOFTWARE:
VER. 3.3 REV.5,
Model File Rev 3.050.

o
o

"'C

0)
I'\)

o
o
.......

0)
I'\)
I'\)

.......
0)
~

o.......
0)
~

I'\)

o.......

co
I'\)
o
o
.......
co
I'\)
I'\)

o
.......
co
~

o
.......
co

~
I'\)

o
.......
(0
I'\)

o.......
(0
I'\)
I'\)

.......
(0
~

o
.......
(0
~

I'\)

o
N

0)
.....
oo

Development Support (Continued)

.....

Probe Card Ordering Information

o
N

Part Number

Package

Voltage Range

MHW-880C20D5PC

20DIP

4.5V-5.5V

COP822C, 842C, 8782C

MHW-880C20DWPC

20 DIP

2.5V-6.0V

COP822C, 842C, 8782C

.....
0)

Emulates

MHW-880C28D5PC

28 DIP

4.5V-5.5V

COP820C, 840C, 881C, 8781C

o
N

MHW-880C28DWPC

28 DIP

2.5V-6.0V

COP820C, 840C, 881C, 8781C

0)
.....
~

co
.....

MACRO CROSS ASSEMBLER

SINGLE CHIP EMULATOR DEVICE

CO
.....
oN

National Semiconductor offers a COP8 macro cross assembier. It runs on industry standard compatible PCs and supports all of the full-symbolic debugging features of the
MetaLink iceMASTER emulators.

co
.....

Assembler Ordering Information

o
o

oo
N

CO
.....

o
N

CD
.....

Part Number

Description

COP8-DEV-IBMA COP8 Assembler/
Linker/Librarian for'
IBM®, PC-XT®, AT®
or compatible

Manual

424410632-001

CD
.....
oN

Device Number

Clock Option

Package

Description

Emulates

CD
.....

o
o

COP8781CN

Programmable

28DIP

One Time Programmable (OTP)

N
CD
D..

COP840C,
COP820C

COP8781CJ

Programmable

28DIP

UV Erasable

COP840C,
COP820C

COP8781CWM

Programmable

28S0

OTP

COP840C,
COP820C

COP8782CN

Programmable

20DIP

OTP

COP842C,
COP822C

COP8782CJ

Programmable

20 DIP

UV Erasable

COP842C,
COP822C

COP8782CWM

Programmable

20S0

OTP

COP842C,
COP822C

Single Chip Emulator Selection Table

1-48

o
o
"0

Development Support (Continued)

PROGRAMMING SUPPORT

Programming of the single chip emulator devices is supported by different sources. The following programmers are certified for
programming the One Time Programmable (OTP) devices:

o
......
0)

o
......

EPROM Programmer Information
Manufacturer
and Product
MetaLink-Debug
Module

U.S. Phone
Number
(602) 926-0797

Europe Phone
Number
Germany: +49-81-41-1030

Asia Phone
Number
Hong Kong: + 852-737-1800

0)
~

+ 65 276 6433

Xeltek-Superpro

(408) 745-7974

Germany: +49-20-41 684758

Singapore:

BP MicrosystemsEP-1140

(800) 225-2102

Germany: + 49-89-857 66 67

Hong Kong: + 852 388 0629

Data 1/0- Unisite;
-System 29,
-System 39

(800) 322-8246

Europe: +31-20-622866
Germany: + 49-89-85-8020

Japan: + 33-432-6991

o
......
Q)
N

o
......
Q)

o
......
Q)
~

Abeom- COP8 Programmer
System General
Turpro-1-FX;
-APRO

o
......

Europe: + 89 80 8707

Q)
~

(408) 263-6667

Switzerland: + 31-921-7844

Taiwan Taipei: + 2-9173005

o
......
CD

o
......
INFORMATION SYSTEM

ORDER PIN: MOLE·DIAL·A·HLP

The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities could be found. The minimum requirement for accessing the Dial-A-Helper is a Hayes compatible
monAm.

Information System Package contains:

Dial-A-Helper Users Manual

Public Domain Communications Software
FACTORY APPLICATIONS SUPPORT
Dial-A-Helper also provides immediate factory applications
support. If a user has questions, he can leave messages on
our electronic bulletin board, which we will respond to.
'v'uic~:

If the user has a PC with a communications package then
files from the FILE SECTION can be down-loaded to disk for
later use.

o
......
~

o......
CD
~

(ovv) 272 .. S959

Modem: CANADA/U.S.: (800) NSC-MICRO
(800) 672-6427
Baud:
Setup:

14.4k
Length:

8-Bit

Parity:

None

Stop Bit: 1
Operation:

24 Hrs. 7 Days

1-49

oC")
N

PRELIMINARY

t!lNational Semiconductor

.......
~

o
N
N

COP820CJ/COP822CJ/COP823CJ
Single-Chip microCMOS Microcontroller

o....... General Description
COP820CJ is a member of the COPSTM 8-bit Microconoo The
troller family. It is a fully static Microcontrolier, fabricated
~

CO
D.

o
o

using double-metal silicon gate microCMOS technology.
This low cost Microcontroller is a complete microcomputer
containing all system timing, interrupt logic, ROM, RAM, and
liD necessary to implement dedicated control functions in a
variety of applications. Features include an 8-bit memory
mapped architecture, MICROWIRETM serial 1/0, a 16-bit
timerlcounter with capture register, a multi-sourced interrupt, Comparator, WATCHDOGTM Timer, ModulatorlTimer,
Brown out protection and Multi-Input Wakeup. Each 1/0 pin
has software selectable options to adapt the device to the
specific application. The device operates over a voltage
range of 2.5V to 6.0V. High throughput is achieved with an
efficient, regular instruction set operating at a 1 p's per instruction rate.

Features
•
•
•
•

Low cost 8-bit Microcontroller
Fully static CMOS
1 p's instruction time
Low current drain
- Low current static HALT mode
• Single supply operation: 2.5V to 6.0V
• 1024 x 8 on-chip ROM

•
•
•
•
•
•
•
•
•

64 bytes on-chip RAM
WATCHDOG Timer
Comparator
ModulatorlTimer (High speed PWM Timer for IR
Transmission)
Multi-Input Wakeup (on the 8-bit Port L)
Brown Out Protection
4 high current 1/0 pins with 15 mA sink capability
MICROWIRE/PLUSTM serial 1/0
16-bit readlwrite timer operates in a variety of modes
- Timer with 16-bit auto reload register
- 16-bit external event counter
- Timer with 16-bit capture register (selectable edge)

• Multi-source interrupt
- External interrupt with selectable edge
- Timer interrupt or capture interrupt
- Software interrupt
• 8-bit stack pointer (stack in RAM)
• Powerful instruction set, most instructions single byte
• BCD arithmetic instructions
• 28- and 20-pin DIPISO package or 16-pin SO package
• Software selectable 1/0 options (TRI-STATE®, pushpull, weak pull-up)
• Schmitt trigger inputs on Port G and Port L
• Fully supported by MetaLink's development systems
• One-Time Programmable (OTP) emulator devices

Block Diagram

I/o
COMPARATOR

ILLEGAL
COND
DETECT

TLIDD/11208-1

FIGURE 1. Block Diagram

1-50

o-a

COP820CJ/COP822CJ/COP823CJ

co
N

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
7.0V
Supply Voltage (Vee>
Voltage at any Pin
-0.3V to Vee + 0.3V
Total Current into Vee pin (Source)
80 rnA

DC Electrical Characteristics
Parameter
Operating Voltage
Power Supply Ripple 1 (Note 1)
Supply Current (Note 2)
CKI = 10 MHz
CKI = 4MHz
CKI = 4MHz
CKI = 1 MHz
HALT Current with Brown Out
Disbled (Note 3)
HALT Current with Brown Out
Enabled

-40°C

80 rnA
Total Current out of GND pin (sink)
- 65°C to + 150°C
Storage Temperature Range
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur.
DC and AC electrical specifications are not ensured when
operating the device at absolute maximum ratings.

Min

Brown Out Disabled
Peak to Peak
Vee
Vee
Vee
Vee

6V, tc =
6V, tc =
4.0V, tc
= 4.0V, tc

1 /-Ls
2.5 /-Ls
= 2.5 p.s
= 10 /-Ls

Vee

=
=

6V, CKI

Vee = 6V, CKI = 0 MHz

1.8

INPUT LEVELS (VIH, VIU
Reset, CKI:
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low

-2

'leG = 6.0'1, '1::~ = 0'1

L-.and G-Port Hysteresis (Note 5)

L4-L7 Output Sink
All Others
Source (Weak Pull-up Mode)
Source (Push-pull Mode)
Sink (Push-pull Mode)

V
V

6.0
3.5
2.0
1.5

rnA
rnA
rnA
rnA

/-LA

<50

110

3.1

4.2

0.2 Vee

V
V

Vee = 4.5V, VOH = 3.8V
Vee = 2.5V, VOH = 1.8V
Vee = 4.5V, VOL = 1.0V
Vee = 2.5V, VOH = O.4V
Vee = 4.5V, VOL = 2.5V

-0.4
-0.2
10
2
15

Vee
Vee
Vee
Vee
Vee
Vee

-10
-2.5
-0.4
-0.2
1.6
0.7
-2.0

= 4.5V, VOH = 3.2V
= 2.5V, VOH = 1.8V
= 4.5V, VOH = 3.8V

= 2.5V, VOH = 1.8V
= 4.5V, VOL = O.4V

2.5V, VOL

= O.4V

TRI-STATE Leakage
Allowable Sink/Source
Current Per Pin
DOutputs
L4-L7 (Sink)
All Others

1-51

oc..

......
co

oc..

V
0.2 Vee

Input Pu!lup Current

Sink

6.0
0.1 Vee

0.7 Vee
Vee = 6.0V

Output Current Levels
D Outputs:
Source

Units

0.8 Vee

Hi-Z Input Leakage

Max

2.5

0 MHz

Brown Out Trip Level
(Brown Out Enabled)

Typ

o-a

:s: TA :s: + 85°C unless otherwise specified

Conditions

oc..
......
o

+2
.. A

-250

r··

0.35 Vee

rnA
rnA
rnA
rnA
rnA

-110

+2.0

/-LA
/-LA
rnA
rnA
rnA
rnA
/-LA

15
20
3

rnA
rnA
rnA

-33

""')

o
('t)
N

DC Electrical Characteristics

Il.

Parameter

o
......
""')
o
N
N

Maximum Input Current
without Latchup (Note 4)

Room Temperature

RAM Retention Voltage, Vr

500 ns Rise and
Fall Time (Min)

Il.

......
""')

o
o
N

Il.

o
o

-40°C $; T A$;+ 85°C unless otherwise specified (Continued)

Conditions

Typ

Min

Max

Units

1:100

2.0

Input Capacitance
Load Capacitance on D2

1000

Note 1: Rate of voltage change must be less than 10 VlmS.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. HALT test conditions: L, and GO.. G5 ports configured as outputs and s~t
high. The D port set to zero. All inputs tied to Vee. The comparator and the Brown Out circuits are disabled.
Note 4: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than Vee and the pins will have sink: current to
Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vee!. The effective resistance to Vce Is 7500
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.

AC Electrical Characteristics

-40°C $; TA $; +85°C unless otherwise specified

Parameter

Instruction Cycle Time (tc)
Crystal/Resonator
R/C Oscillator

Conditions

4.5V
2.5V
4.5V
2.5V

$;
$;
$;
$;

Vee
Vee
Vee
Vee

$;
$;
$;
$;

6.0V
4.5V
6.0V
4.5V

Vee Rise Time when Using Brown Out
Frequency at Brown Out Reset
CKI Frequency For Modular Output

Vee = OVto6V

CKI Clock Duty Cycle (Note 5)
Rise Time (Note 5)
Fall Time (Note 5)

fr = Max
fr = 10 MHz ext. Clock
fr = 10 MHz ext. Clock

Min

1
2.5
3
7.5

Typ

Max

Units

DC
DC
DC
DC

p's
p.s
p.s
p's

4
4

~Hz

MHz

60
12
8

%
ns
ns

p.s

Inputs
tsetup
tHold
Output Propagation Delay
tp01, tpoo
SO,SK
All Others

4.5V
2.5V
4.5V
2.5V

$;
$;
$;
$;

Vee
Vee
Vee
Vee

$;
$;
$;
$;

6.0V
4.5V
6.0V
4.5V

200
500
60
150

ns
ns
ns

RL = 2.2k, CL = 100 pF
4.5V
2.5V
4.5V
2.5V

$;
$;
$;
$;

Vee
Vee
Vee
Vee

$;
$;
$;
$;

6.0V
4.5V
6.0V
4.5V

Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

0.7
1.75
1
5

p.s
p's
p's
p.s

1
1
1
1

tc
tc
tc
tc

MICROWIRE Setup Time (tIlWS)
MICROWIRE Hold Time (tIlWH)
MICROWIRE Output
Propagation Delay (tJ,tPO)

20
56

ns
ns

Reset Pulse Width

1.0

220

Note 5: Parameter characterized but not production tested.

1·52

ns
p.S

a""'C

AC Electrical Characteristics (Continued)

co
I\)
o

SK~

o
c..

"'o"
a""'C

fl=x=
!:=i
ws

~wh

ClO
I\)
I\)

x==

o
c..

'uPD

"'o"
a""'C

TL/DD/11208-2

co
I\)

FIGURE 2. MICROWIRE/PLUS Timing

(,.)

o
c..

Comparator DC and AC Characteristics 4V:S;: Vee:S;: 6V, -40°C:s;: TA:S;: + 85°C (Note 1)
Parameters

Conditions

Input Offset Voltage

O.4V

Min

< VIN < Vee - 1.5V

Input Common Mode Voltage Range

Type

Max

Units

±10

±25

0.4

Voltage Gain

Vee - 1.5
300k

DC Supply Current (when enabled)

Vee = 6.0V

Response Time

TBD mV Step,
TBD mV Overdrive, 100 pF Load

VIV
250

}iA

}is

Note 1: For comparator output current characteristics see L-Por! specs.

Connection Diagrams
C4/S0- 1

28 ,-C3/TiO

C5/SK- 2

27 r-G2

C6/SI- 3

26 -Cl

C4/S0- 1

25 -GO/INT

G5/SK- 2

19 -C2

H -RESET

G6/SI- 3

18 -Cl

C7/CKO- 4
CKI- 5

'\c-

'-'

"7/CV.O- ~

20 -C3/TiO

17 -C0/!~!T

G6/S1~'

C7/CKO

16~G5

G3/T10

CKI- 3

14 r-RESET

Vcc -

13 r-GND

10- 7

22 -03

CKI- 5

16 -RESET

11- 8

21 -02

Vcc -

15 -CND

LO/CMPOUT- 5

12 r- L7/MODOUT

12- 9

20 -01

LO/CMPOUT- 7

14 -L7/MODOUT

Ll/CMPIN-- 6

11 r-L6

L2/CMPIN+- 7

10 r-L5

L3- 8

9 r-L4

19 -DO

L1/CMPIN-- 8

13 -L6

LO/CMPOUT- 11

18 -L7/MODOUT

L2/CMPIN+- 9

121-L5

L1/CMPIN-- 12

17 -L6

13- 10

L2/CMPIN+- 13

16 -L5

L3- 14

15 -L4
TL/DD/11208-3

Top View

L3- 10

l11-Lo4
TL/DD/11208-5

TL/DD111208-4

Top View

Top View
Order Number COPCJ823-XXX/WM

Order Number COPCJ822-XXX/N or
COPCJ822-XXX/WM

Order Number COPCJ820-XXX/N or
COPCJ820-XXX/WM
FIGURE 3. Connection Diagrams

1-53

...,

o
C")
N

Typical Performance Characteristics

D..

Dynamlc-loO vs Vee
(Crystal Clock Option)

.......
...,

o
N

5.5

4.5

.......
...,

o
(;)

...
.§.
'"

2.5

D..

0.5

411Hz

3.0

~IIHz

3.5

,'/

.$>

, "

0.15

: ........"

0.10

0.05
4.5

5.0

5.5

6.0

a~.s.-'V

~·c

, ,
, ,

VCC (V)

Ports LtG Push-Pull
Sink Current

Ports LtG Push-Pull
Source Current

....

120 r---r-...------r--.--r---o

+70'C

15
4.0 4.2 U U 4.8 5.0 5.2 5." 5.6 5.8 6.0

VCc(V)

Ports LtG Weak
Pull-Up Source Current

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VCC(v)

1/ . . .

4.0

+85°';, l '

0.20

/1'

0.25

.y
,'V

2.0
1.5

...

3.0

1.0

3.5

0.35
0.30

1011Hz

4.0

D..

5.0

Halt-loO vs Vee
(Brown Out Enabled)

Halt-loO vs Vee
(Brown Out Disabled)

16
I ..

, ...

Vcc =6.0V

12
10

-- .. -

Vcc 2 4.5V

,- ~ Vcc·

.5V " -

o 1/

0.5

1.0

1.5

VaH (v)

vaH (v)

Ports L4-L7
Sink Current

2.0

2.5

Port D Source Current

I,'

10~~,+-+-;-~-r~-+~

o ~~.,.------r----rVcc=2.5V

Vcc ·2.5V

....

I ,
I

VOH (v)

Vcc =6.av

Vcc ·4.5V

I
I

1-", _~Vcc=2.5V

o
o

. VOL (v)

1'.

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

.§.

,Vcc =4.5V

~CC76.0V

. 4

3.5

Port D Sink Current
45

.§.

3.0

VOL (v)

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VOL (v)

Brown Out Voltage
vs Temperature

.:=.
'"
.!!!
~

.li

4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
-40

....

lIax

--...

..........
-20

......

Typ

......
~

Win

r-- ~
20

i"""o..
40

........
80

Temperature (Oc)
TL/DD/11208-28

1-54

I/O bit can be individually configured under software control
as shown below:

COP820CJ Pin Assignment

o
o
""D
co

Port
Pin

Typ

ALT
Funct.

I/O

MIWUlCMPOUT

i/O

MIWU/CMPIN-

I/O

MIWU/CMPIN +

i/O

MIWU

I/O

MIWU

i/O

MIWU

I/O

MIWU

I/O

MIWU/MOOOUT

I/O

INTR

I/O

TIO

i/O

I/O

Port L
Config.

Port L
Data

Port L
Setup

0
0
1
1

0
1
0
1

Hi-Z Input (TRI-STATE)
Input with Weak Pull-up
Push-pull Zero Output
Push-pull One Output

LO
L1
L2
L3
L4
L5
L6
L7

MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU

All eight L-pins have Schmitt Triggers on their inputs.

PORT G is an 8-bit port with 6 I/O pins (GO-G5) and 2 input
pins (G6, G7).

PortG
Config.

PortG
Data

PortG
Setup

0
1
1

0
1
0
1

H:·Z ~r.;:t.:t{TRI~STAT~J
Input with Weak Pull-up
Push-pull Zero Output
Push-pull One Output

RESET

(,.)

The selection of alternate Port L functions is done through
registers WKEN [00C9] to enable MIWU and CNTRL2
[OOCC] to enable comparator and modulator.

""D

(high sink current capability)
(high sink current capability)
(high sink current capability)
or MOOOUT (high sink current capability)

CKI

o
c...

or CMPOUT
or CMPINor CMPIN+

CKO

GNO

........

oc...

Port L has the following alternate features:

""D

oc...
........
o
o

Three data memory address locations are allocated for this
port, one each for data register [0000]. configuration register [0001] and the input pins [0002].

Vee

All eight G-pins have Schmitt Triggers on the inputs.
There are two registers associated with the G port: a data
register and a configuration register. Therefore each G port
bit can be individually configured under software control as
shown below:

Three data memory address locations are allocated for this
port, one for data register [0003], one for configuration register [0005] and one for the input pins [0006]. Since G6
and G7 are Hi-Z input only pins, any attempt by the user to
configure them as outputs by writing a one to the configuration register will be disregarded. Reading the G6 and G7
configuration bits will return zeros. Note that the device will
be placed in the Halt mode by writing a "1" to the G7 data
bit.

Pin Description
Vee and GND are the power supply pins.
CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunction with CKO). See Oscillator description.

Six pins of Port G have alternate features:
GO INTR (an external interrupt)

RESET is the master reset input. See Reset description.

G3 TIO (timer/counter input/output)

PORT I is a 4-bit Hi-Z input port.

G4 SO (MICROWIRE serial data output)

PORT L is an 8-bit i/O port.

G5 SK (MICROWIRE clock i/O)

There are two registers associated with the L port: a data
register and a configuration register. Therefore, each L

G6 SI (MICROWIRE serial data input)
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input/general purpose input (if clock
option is R/C or external clock)

1-55

...,

oM
N

Pin Description

"...,

The selection of alternate Port G functions are done through
registers PSW [OOEF) to enable external interrupt and
CNTRL 1 [OOEE) to select TID and MICROWIRE operations.

oo
o
N
N

o
o

"...,

N
CO

Any bit of data memory can be directly set, reset or tested.
All I/O and registers (except A and PC) are memory
mapped; therefore, I/O bits and register bits can be directly
and individually set, reset and tested, except the write once
only bit (WDREN, WATCHDOG Reset Enable), and the unused and read only bits in CNTRL2 and WDREG registers.

(Continued)

Pins G1 and G2 currently do not have any alternate functions.

Note: RAM contents are undefined upon power·up.

PORT D is a four bit output port that is preset when RESET
goes low. One data memory address location is allocated
for the data register [OODC).

Reset
EXTERNAL RESET

Note: Care must be exerCised with the 02 pin operation. At RESET, the
external loads on this pin must ensure that the output voltages stay above
0.8 Vcc to prevent the chip from entering special modes. Also keep the
external loading on D2 to less than 1000 pF.

The RESET input pin when pulled low initializes the microcontroller. The user must insure that the RESET pin is held
low until Vee is within the specified voltage range and the
clock is stabilized. An R/C circuit with a delay 5x greater
than the power supply rise time is recommended (Figure 4).
The device immediately goes into reset state when the
RESET input goes low. When the RESET pin goes high the
device comes out of reset state synchronously. The device
will be running within two instruction cycles of tile RESET
pin going high. The following actions occur upon reset:

o
o

Functional Description
The internal architecture is shown in the block diagram.
Data paths are illustrated in simplified form to depict how
the various logic elements communicate with each other in
implementing the instruction set of the device.

ALU and CPU Registers
The ALU can do an a-bit addition, subtraction, logical or
shift operations in one cycle time. There are five CPU registers:
A

is the a-bit Accumulator register

is the 15-bit Program Counter register

Port L

TRI-STATE

Port G

TRI-STATE

Port D

HIGH

CLEARED

RAM Contents

RANDOM with Power-OnReset
UNAFFECTED with external
Reset (power already applied)

PU is the upper 7 bits of the program counter (PC)
PL is the lower a bits of the program counter (PC)
S

is the S-bit address register and can be auto incremented or decremented.

is the a-bit alternate address register and can be auto
incremented or decremented.

S,X,SP

Same as RAM

is the a-bit stack pointer which points to the subroutine stack (in RAM).

PSW, CNTRL 1, CNTRL2
and WDREG Reg.

CLEARED

S, X and SP registers are mapped into the on chip RAM.
The S and X registers are used to address the on chip RAM.
The SP register is used to address the stack in RAM during
subroutine calls and returns. The SP must be preset by software upon initialization.

Multi-Input Wakeup Reg.
WKEDG, WKEN
WKPND

CLEARED
UNKNOWN

Data and Configuration
Registers for L & G

CLEARED

Memory

WATCHDOG Timer

The memory is separated into two memory spaces: program
and data.

Prescaler/Counter each
loaded with FF

The device comes out of the HALT mode when the RESET
pin is pulled low. In this case, the user has to ensure that the
RESET signal is low long enough to allow the oscillator to
restart. An internal 256 tc delay is normally used in conjunction with the two pin crystal oscillator. When the device
comes out of the HALT mode through Multi-Input Wakeup,
this delay allows the oscillator to stabilize.

PROGRAM MEMORY
Program memory consists of 1024 x a ROM. These bytes of
ROM may be instructions or constant data. The memory is
addressed by the 15-bit program counter (PC). ROM can be
indirectly read by the LAID instruction for table lookup.
DATA MEMORY
The data memory address space includes on chip RAM, I/O
and registers. Data memory is addressed directly by the instruction or indirectly through S, X and SP registers. The
device has 64 bytes of RAM. Sixteen bytes of RAM are
mapped as "registers", these can be loaded immediately,
decremented and tested. Three specific registers: X, S, and
SP are mapped into this space, the other registers are available for general usage.

The following additional actions occur after the device
comes out of the HALT mode through the RESET pin.
If a two pin crystal/resonator oscillator is being used:
RAM Contents

1-56

UNCHANGED

Timer T1 and A Contents

UNKNOWN

WATCHDOG Timer Prescaler/Counter

ALTERED

Functional Description

a"0

(Continued)

If the external or RC Clock option is being used:
RAM Contents

UNCHANGED

Timer T1 and A Contents

UNCHANGED

WATCHDOG Timer Prescaler/Counter

ALTERED

RESET as long as Vee is below the Brown Out Voltage. The
Device will resume execution if Vee rises above the Brown
Out Voltage. If a two pin crystal/resonator clock option is
selected, the Brown Out reset will trigger a 256tc delay. This
delay allows the oscillator to stabilize before the device exits the reset state. The delay is not used if the clock option is
either RIC or external clock. The contents of data registers
and RAM are unknown following a Brown Out reset. The
external reset takes priority over Brown Out Reset and will
deactivate the 256 tc cycles delay if in progress. The Brown
Out reset takes priority over the WATCHDOG reset.

The external RESET takes priority over the Brown Out Reset.
Note: If the RESET pin is pulled low while Brown Out occurs (Brown Out
circuit has detected Brown Out condition), the external reset will not
occur until the Brown Out condition is removed. External reset has
priority only if Vee is greater than the Brown Out voltage.

p +

.. > -

Vee
RESET

U
p
p
L

The following actions occur as a result of Brown Out reset:

:::~

GND

RC > 5 x Power Supply Rise Time

TL/DD/11208-6

FIGURE 4. Recommended Reset Circuit
WATCHDOG RESET
With WATCHDOG enabled, the WATCHDOG logic resets
the device if the user program does not service the WATCHDOG timer within the selected service window. The
WATCHDOG reset does not disable the WATCHDOG.
Upon WATCHDOG reset, the WATCHDOG Prescalerl
Counter are each initialized with FF Hex.
The following actions occur upon WATCHDOG reset that
are different from external reset.
WDREN
WDUDF

WATCHDOG Reset Enable bit
WATCHDOG Underflow bit

UNCHANGED
UNCHANGED

Port L

TRI-STATE

Port G

TRI-STATE

Port D

HIGH

CLEARED

RAM Contents

RANDOM

B,X,SP

UNKNOWN

PSW, CNTRL 1, CNTRL2
and WDREG Registers

CLEARED

Multi-Input Wakeup Registers
WKEDG,WKEN
WKPND

CLEARED
UNKNOWN

Data and Configuration
Registers for L & G

CLEARED

WATCHDOG Timer

Prescalar/Counter each
loaded with FF

Timer T1 and Accumulator

Unknown data after
coming out of the HALT
(through Brown Out
Reset) with any Clock
option

Additional initialization actions that occur as a result of
WATCHDOG reset are as follows:
Port L

TRI-STATE

PortG

TRI-STATE

Port D

HIGH

CLEARED

Ram Contents

UNCHANGED

B,X,SP

UNCHANGED

CLEARED
UNKNOWN

Data and Configuration
Registers for L & G

CLEARED

WATCHDOG Timer

c..
.......

a"0
co

I\.)
I\.)

o
c..

.......

a"0
co

I\.)
Co)

o
c..

Note: The development system will detect the BROWN OUT RESET externally and will force the RESET pin low. The Development System
does not emulate the 256tc delay.

Brown Out Protection
An on-board protection circuit monitors the operating voltage (Vee> and compares it with the minimum operating voltage specified. The Brown Out circuit is designed to reset the
device if the operating voltage is below the Brown Out voltage (between 1.8V to 4.2V at - 40°C to + 85°C). The Minimum operating voltage for the device is 2.5V with Brown
Out disabled, but with BROWN OUT enabled the device is
guaranteed to operate properly down to minimum Brown
Out voltage (Max frequency 4 MHz), For temperature range
of O°C to 70°C the Brown Out voltage is expected to be
between 1.9V to 3.9V. The circuit can be enabled or disabled by Brown Out mask option. If the device is intended to
operate at lower Vee (lower than Brown Out voltage VBO
max), the Brown Out circuit should be disabled by the mask
option.

PSW, CNTRL 1 and CNTRL2 (except
WDUDF Bit) Registers
CLEARED
Multi-Input Wakeup Registers
WKEDG, WKEN
WKPND

I\.)
<:)

Prescalar I Counter
each loaded with FF

BROWN OUT RESET
The on-board Brown Out protection circuit resets the device
when the operating voltage (Vee> is lower than the Brown
Out voltage. The device is held in reset when Vee stays
below the Brown Out Voltage. The device will remain in

The Brown Out circuit may be used as a power-up reset
provided the power supply rise time is slower than 50 P.s (OV
to 6.0V).
Note: Brown Out Circuit is active in HALT mode (with the Brown Out mask
option selected).

1-57

..,

(.)
C'\I

Functional Description

a..

Oscillator Circuits

Cot)

o(.)

..,.......
(.)
C'\I
C'\I

a..

o
(.)

..,.......
(.)

C'\I
CO

a..

o(.)

(Continued)

EXTERNAL OSCILLATOR
CKI can be driven by an external clock signal provided it
meets the specified duty cycle, rise and fall times, and input
levels.. CKO is available asa general purpose input G7
and/or Halt control.

CKO

CKI
R2

CRYSTAL OSCI~LATOR
By selecting CKO as a clock output, CKI and CKO can be
connected to create a crystal controlled oscillator. Table I
shows the component values required for various standard
crystal values.

J1.r

EXTERNAL

CLOCK

RIC OSCILLATOR
By selecting CKI as a single pin oscillator, CKI can make a
R/C oscillator. CKO is available as a general purpose input
and/or HALT control. Table II shows variation in the oscillator frequencies as functions of the component (R and C)
values.

TL/DD/1120B-7

FIGURE 5. Clock Oscillator Configurations

TABLE I. Crystal Oscillator Configuration
R1
(k!l)

R2
(Mn)

C1
(pF)

C2
(pF)

CKI Freq.
(MHz)

30-36

Vee

30-36

5.6

Vee

100

100-156

0.455

Vee

Conditions

=
=
=

5V
5V
5V

TABLE II. RC Oscillator Configuration (Part-To-Part Variation)
R
(kn)

C
(pF)

CK1 Freq.
(MHz)

Instr. Cycle
(ILS)

3.3,

2.2 to 2.7

3.7 to 4.6

Vee

5.6

100

1.1 to 1.3

7.4 to 9.0

Vee

6.8

100

0.9 to 1.1

8.8 to 10.8

1-58

Conditions

=
=
Vee =

(")

Functional Description

a"'D

(Continued)

Current Drain

If the two pin crystal/resonator oscillator is being used and
Multi-Input Wakeup or Brown Out causes the device to exit
the HALT mode, the WAKEUP signal does not allow the
chip to start running immediately since crystal oscillators
have a delayed start up time to reach full amplitude and
freuqency stability. The WATCHDOG timer (consisting of an
a-bit prescaler followed by an a-bit counter) is used to generate a fixed delay of 256tc to ensure that the oscillator has
indeed stabilized before allowing instruction execution. In
this case, upon detecting a valid WAKEUP signal only the
oscillator circuitry is enabled. The WATCHDOG Counter and
Prescaler are each loaded with a value of FF Hex. The
WATCHDOG prescaler is clocked with the tc instruction cycle. (The tc clock is derived by dividing the oscillator clock
down by a factor of 10). The Schmitt trigger following the
CKI inverter on the chip ensures that the WATCHDOG timer
is clocked only when the oscillator has a sufficiently large
amplitude to meet the Schmitt trigger specs. This Schmitt
trigger is not part of the oscillator closed loop. The start-up
timeout from the WATCHDOG timer enables the clock signals to be routed to the rest of the chip. The delay is not
activated when the device comes out of HALT mode
through RESET pin. Also, if the clock option is either RC or
External clock, the delay is not used, but the WATCHDOG
Prescaler/-Counter contents are changed. The Development System will not emulate the 256tc delay.

The total current drain of the chip depends on:
1. Oscillator operating mode - 11
2. Internal switching current - 12
3. Internal leakage current - 13
4. Output source current - 14
5. DC current caused by external input not at Vee or
GND-15
6. DC current caused by the comparator (if comparator is
enabled) - 16
7. DC current caused by the Brown Out - 17
Thus the total current drain is given as
It= 11

+ 13 +

+ 17

To reduce the total current drain, each of the above components must be minimum. Operating with a crystal network
will draw more current than an external square-wave. The
R/C-mode will draw the most. Switching current, governed
by the equation below, can be reduced by lowering voltage
and frequency. Leakage current can be reduced by lowering
voltage and temperature. The other two items can be reduced by carefully designing the end-user's system.
The following formula may be used to compute total current
drain when operating the controller in different modes.
12 = C x V x f

co
N
o

(")

c..
......
(")

a"'D
co

N
(")

c..

......
(")

"'D

co
N

(")

c..

The RESET pin or Brown Out will cause the device to reset
and start executing from address X'OOOO. A low to high transition on the G7 pin (if single pin oscillator is used) or MultiInput Wakeup will cause the device to start executing from
the address following the HALT instruction.
When RESET pin is used to exit the device from the HALT
mode and the two pin crystal/resonator (CKIICKO) clock
option is selected, the contents of the Accumulator and the
Timer T1 are undetermined following the reset. All other
information except the WATCHDOG Prescaler/Counter
contents is retained until continuing. If the device comes out
of the HALT mode through Brown Out reset, the contents of
data registers and RAM are unknown following the reset. All
information except the WATCHDOG Prescaler/Counter
contents is retained if the device exits the HALT mode
through G7 pin or Multi-Input Wakeup.

where: C = equivalent capacitance of the chip

V = operating voltage
f = CKI frequency
Halt Mode

The device is a fully static device. The device enters the
HALT mode by writing a one to the G7 bit of the G data
register. Once in the HALT mode, the internal circuitry does
not receive any clock signal and is therefore frozen in the
exact state it was in when halted. In this mode the chip will
only draw leakage current (output current and DC current
due to the Brown Out circuit if Brown Out is enabled).
The device supports four different methods of exiting the
HALT mode. The first method is with a low to high transition
on the CKO (G7) pin. This method precludes the use of the
crystal clock configuration (since CKO is a dedicated output). It may be used either with an RC clock configuration or
an external clock configuration. The second method of exiting the HALT mode is with the multi-Input Wakeup feature
on the L port. The third method of exiting the HALT mode is
by pulling the RESET input low. The fourth method is with
the operating voltage going below Brown Out voltage (if
Brown Out is enabled by mask option).

G7 is the HALT-restart pin, but it can still be used as an
input. If the device is not halted, G7 can be used as a general purpose input.
If the Brown Out Enable mask option is selected, the Brown
Out circuit remains active during the HALT mode causing
additional current to be drawn.
Note: To allow clock resynchronization, it is necessary to program two
NOP's immediately after the device comes out of the HALT mode.
The user must program two NOP's following the "enter HALT mode"
(set G7 data bit) instruction.

1-59

"")

('I)

D-

O
o
.......
"")

oN
N

D-

O
o
.......
"")

N
CO

Functional Description

(Continued)

MICROWIRE/PLUS
MICROWIRE/PlUS is a serial synchronous bidirectional
communications interface. The MICROWIRE/PlUS capability enables the device to interface with any of National
Semiconductor's MICROWIRE peripherals (i.e. AID converters, display drivers, EEPROMS, etc.) and with other microcontrollers which support the MICROWIRE/PlUS interface. It consists of an 8-bit serial shift register (SIO) with
serial data input (SI), serial data output (SO) and serial shift
clock (SK). Figure 6 shows the block diagram of the MICROWIRE/PLUS interface.

TABLE III
SK Cycle Time

2tc
4tc
8tc

1
x

tc is the instruction cycle time.
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MICROWIRE/PlUS arrangement to start shifting the data. It
gets reset when eight data bits have been shifted. The user
may reset the BUSY bit by software to allow less than 8 bits
to shift. The device may enter the MICROWIRE/PlUS
mode either as a Master or as a Slave. Figure 7 shows how
two device microcontrollers and several peripherals may be
interconnected using the MICROWIRE/PlUS arrangement.

SLO

0
0
where,

r-------------------~so

D-

SL1

I+-----SI

Master MICROWIRE/PLUS Operation
In the MICROWIRE/PlUS Master mode of operation the
shift clock (SK) is generated internally by the device. The
MICROWIRE/PlUS Master always initiates all data exchanges (Figure 7). The MSEl bit in the CNTRl register
must be set to enable the SO and SK functions on the G
Port. The SO and SK pins must also be selected as outputs
by setting appropriate bits in the Port G configuration register. Table IV summarizes the bit settings required for Master
mode of operation.

TLlDD/11208-8

FIGURE 6. MICROWIRE/PLUS Block Diagram
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIREI
PLUS interface with the internal clock source is called the
Master mode of operation. Operating the MICROWIREI
PLUS interface with an external shift clock is called the
Slave mode of operation.

SLAVE MICROWIRE/PLUS OPERATION
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEl
bit in the CNTRl register enables the SO and SK functions
on the G Port. The SK pin must be selected as an input and
the SO pin selected as an output pin by appropriately setting
up the Port G configuration register. Table IV summarizes
the settings required to enter the Slave mode of operation.

The CNTRl register is used to configure and control the
MICROWIRE/PlUS mode. To use the MICROWIRE/PlUS ,
the MSEl bit in the CNTRl register is set to one. The SK
clock rate is selected by the two bits, SlO and SL1, in the
CNTRl register. Table III details the different clock rates
that may be selected.

CHIP SELECT LINES
-""

EEPROM

DIGITAL
Pll

LCD
DISPLAY
DRIVER
COP472-3

I/o
LINES

¢:>

8 - BIT
A/D CONVERTER
COP43X

COP8
(MASTER)

DO
SI ....

01 ClK

I/O
LINES
COP8
(SLAVE)

01 ClK
SO

SK
TLlDD/11208-23

FIGURE 7. MICROWIRE/PLUS Application

1-60

Functional Description

MODE 1. TIMER WITH AUTO-LOAD REGISTER

(Continued)

In this mode of operation, the timer Tl counts down at the
instruction cycle rate. Upon underflow the value in the register Rl gets automatically reloaded into the timer which continues to count down. The timer underflow can be programmed to interrupt the microcontroller. A bit in the control
register CNTRl enables the TID (G3) pin to toggle upon
timer underflows. This allows the generation of square-wave
outputs or pulse width modulated outputs under software
control (Figure 8).

Conflg. Conflg.
Bit

Bit

Fun.

Operation

Int.SK

MICAOWIAE Master

TAl-STATE

Int.SK

MICAOWIAE Master

Ext. SK

MICAOWIAE Slave

TAl-STATE Ext. SK

MICAOWIAE Slave

co
N
o

o
o

c..
......

o-a
co
N
N

o
c..

......

MODE 2. EXTERNAL COUNTER

o-a

In this mode, the timer Tl becomes a 16-bit external event
counter. The counter counts down upon an edge on the TID
pin. Control bits in the register CNTRl program the counter
to decrement either on a positive edge or on a negative
edge. Upon underflow the contents of the register Rl are
automatically copied into the counter. The underflow can
also be programmed to generate an interrupt (Figure 9).

o."
co
N

Cot)

oc..

Timer/Counter
The device has a powerful 16-bit timer with an associated
16-bit register enabling it to perform extensive timer functions. The timer Tl and its register Rl are each organized
as two 8-bit read/write registers. Control bits in the register
CNTRl allow the timer to be started and stopped under
software control. The timer-register pair can be operated in
one of three possible modes. Table V details various timer
operating modes and their requisite control settings.

TlO
OUTPUT
TL/DD/1120B-24

FIGURE 8. Timer/Counter Auto
Reload Mode Block Diagram
TABLE V. Timer Operating Modes
CNTRL
Bits

Operation Mode

T Interrupt

Timer
Counts
On

t::xternal counter wi Auto-Load Reg.
External Counter wi Auto-load Reg.
Not Allowed
Not Allowed
Timer wi Auto-load Reg.
Timer wi Auto-load Reg.lToggle TID Out
Timer wlCapture Register
Timer wlCapture Register

Timer Underflow
Timer Underflow
Not Allowed
Not Allowed
Timer Underflow
Timer Underflow
TID Pos. Edge
TID Neg. Edge

TID Pos. Edge
TID Neg. Edge
Not Allowed
Not Allowed
tc
tc
tc
tc

765
000
001
010
01 1
100
1 01
1 10
111

INTERNAL DATA BUS

Rl
16-BIT AUTO-RELOAD REGISTER
TIMER
UNDERFLOW
INTERRUPT

Tl
16-BIT TIMER/COUNTER

EXT
ClK
EDGE SELECTOR
lOGIC

TL/DD/1120B-29

FIGURE 9. Timer In External Event Counter Mode
1-61

..,

o
('I)
N

co
D-

..,......o
o
N
N

D-

..,......o
oo

Timer I Counter (Conti~ued)
MODE 3.' TiMER WrrH CAPTURE REGISTER

Watchdog
The device has an on-board a-bit WATCHDOG timer. The
timer contains an a-bit READ/WRITE down counter clocked
by an a-bit prescaler. Under software control the timer can
be dedicated for the WATCHDOG or used as a general purpose counter. Figure 12 shows the WATCHDOG timer block
diagram.

Timer T1 can be used to precisely measure external .frequencies or events in this mode of operation; The timer T1
counts down at the instruction cycle rate. Upon the occurrence of a specified edge on the TIO pin the contents of the
timer T1 are copied into the register R1. Bits in the control
register CNTRl allow the trigger edge to be specified either
as a positive edge or as a negative edge. In this mode the
user can elect to be interrupted on the specified trigger
'<,.
'
edge (Figure 10).

MODE 1: WATCHDOG TIMER
The WATCHDOG is designed to detect user programs getting stuck in infinite loops resulting in loss of program control or "runaway" programs. The WATCHDOG can be enabled ,or disabled (only once) after the device is reset as a
resultof brown out reset o(external reset. On power-up the
WATCHDOG is disabled. The WATCHDOG is enabled by
writing a- "1" to WDREN bit (resides in WDREG' register).
Once enabled, the user program should write periodically
into the a-bit counter before the counter underflows. The
a-bit counter (WDCNT)is memory mapped at address aCE
Hex. The counter is loaded with n-1 to get n counts. The
counter underflow resets the device, but does not disable
the WATCHDOG. loading the a-bit counter initializes the
prescaler with FF Hex and starts the prescaler/counter.
Prescaler and counter are stopped upon counter underflow.
Prescaler and counter are each loaded with FF Hex when
the'device goes into the HALT mode. The prescaler is used
for crystal/resonator start-up when the device exits the
HAlT'mode through Multi-Input Wakeup. In this case, the
prescaler/counter contents are changed.

N
CO

D-

TIO INPUT

TL/DD/11208-25

FIGURE 10. Timer Capture Mode Block Diagram
TIMER PWM APPLICATION
Figure 11 shows how a minimal component D/ A converter
can be built out of the Timer-Register pair in the Auto-Reload mode. The timer is placed in the "Timer with auto reload" mode and the TIO pin is selected as the timer output.
At the outset the TIO pin is set high, the timer T1 holds the
on time and the register R1 holds the signal off time. Setting
TRUN bit starts the timer which counts down at the instruction cycle rate. The underflow toggles the TIO output and
copies the off time into the timer, which continues to run. By
alternately loading in the on time and the off time at each
successive interrupt a PWM frequency can be easily gener~~

MODE 2: TIMER
In this mode, the prescaler/counter is used as a timer by
keeping the WDREN (WATCHDOG reset enable) bit at a.
The counter underflow sets the WDUDF (underflow) bit and
the underflow does not reset the device. loading the a-bit
counter (load n-1 for n counts) sets the WDTEN bit
(WATCHDOG Timer Enable) to "1", loads the prescaler
with FF, and starts the timer. The counter underflow stops
the timer. The WDTEN bit serves as a start bit for the
WATCHDOG timer. This bit is set when the a-bit counter is
loaded by the user program. The load could be as a result of
WATCHDOG service (WATCHDOG timer dedicated for
WATCHDOG function) or write to the counter (WATCHDOG
timer used as a general purpose counter). The bit is cleared
upon Brown Out reset, WATCHDOG reset or external reset.
The 'bit is not memory mapped and is transparent to the
user program.

Ton

10,

~.A SIMPLE
"
,
0- A

CONVERTER USING
THE TIMER TO
GENERATE A PWM
OUTPUT.
TL/DD/11208-26

FIGURE 11. Timer Application
TABLE VI. WATCHDOG Control/Status
Parameter
a-Bit Prescaler
a-Bit WD Counter

HALT
Mode

WD
Reset

EXT/BOR
Reset
(Note 1)

Counter
Load

FF.

User Value
No Effect

WDREN Bit

Unchanged

' Unchanged

WDUDFBit

Unchanged

a
o

Unchanged

WDTEN Signal
Note 1: BOR is Brown Out Reset.

1-62

Functional Description

o"'D

(Continued)

co
N

CONTROL/STATUS BITS

WDREN: WD Reset Enable

WDUDF: WATCHDOG Timer Underflow Bit

WDREN bit resides in a separate register (bit 0 of WDREG).
This bit enables the WATCHDOG timer to generate a reset.
The bit is cleared upon Brown Out reset, or external reset.
The bit under software control can be written to only once
(once written to, the hardware does not allow the bit to be
changed during program execution).

This bit resides in the CNTRL2 Register. The bit is set when
the WATCHDOG timer underflows. The underflow resets
the device if the WATCHDOG reset enable bit is set
(WDREN = 1). Otherwise, WDUDF can be used as the timer underflow flag. The bit is cleared upon Brown-Out reset,
external reset, load to the a-bit counter, or going into the
HALT mode. It is a read only bit.

<:)

WDREN = 1 WATCHDOG reset is enabled.
WDREN = 0 WATCHDOG reset is disabled.
Table VI shows the impact of Brown Out Reset, WATCHDOG Reset, and External Reset on the Control/Status bits.

oc..

......
o

o"'D
co
N
N

oc..
......
o

o"'D
co
N
W

oc..

INTERNAL DATA BUS
HALT RESTART

HALT
BROWN OUT
RESET
PRESET

WAKE-UP

WD -COUNTER
(a-BIT)

LOAD
WD-COUNTER

UNDERfLOW

EXTERNAL RESET
BROWN OUT RESET

TL/DD/11208-1S

FIGURE 12. WATCHDOG Timer Block Diagram

1-63

o
C")

C\I

o
o

.......
-,

oC\I
C\I

Modulator/Timer
The Modulator/Timer contains an 8-bit counter and an 8-bit
autoreload register (MODRL address OCF Hex). The Modulator /Timer has two modes of operation, selected by the
control bit MC3. The Modulator/Timer Control bits MC1,
MC2 and MC3 reside in CNTRL2 Register.

control bit by software loads the counter with the value of
the autoreload register and starts the counter. The counter
underflow toggles the (L7) output pin. The 50% duty cycle
signal will be continuously generated until MC1 is reset by
the user program.

MODE 1: MODULATOR

b. Variable Duty Cycle:

The Modulator is used to generate high frequency pulses on
the modulator output pin (L7). The L7 pin should be configured as an output. The number of pulses is determined by
the 8-bit down counter. Under software control the modulator input clock can be either CKI or tC. The tC clock is derived by dividing down the oscillator clock by a factor of 10.
Three control bits (MC1, MC2, and MC3) are used for the
Modulator/Timer output control. When MC2 = 1 and MC3
= 1, CKI is used as the modulator input clock. When MC2
= 0, and MC3 = 1, tC is used as the modulator input clock.
The user loads the counter with the desired number of
counts (256 max) and sets MC1 to start the counter. The
modulator autoreload register is loaded with n-1 to get n
pulses. CKI or tc pulses are routed to the modulator output
(L7) until the counter underflows (Figure 13). Upon underflow the hardware resets MC1 and stops the counter. The
L7 pin goes low and stays low until the counter is restarted
by the user program. The user program has the responsibility to timeout the low time. Unless the number of counts is
changed, the user program does not have to load the counter each time the counter is started. The counter can simply
be started by setting the MC1 bit. Setting MC1 by software
will load the counter with the value of the autoreload register. The software can reset MC1 to stop the counter.

When MC3 = 0 and MC2 =" 1, a variable duty cycle PWM
signal is generated on the L7 output pin. The counter is
clocked by tC. In this mode the 16-bit timer T1 along with
the 8-bit down counter are used to generate a variable duty
cycle PWM signal. The timer T1 underflow sets MC1 which
starts the down counter and it also sets L7 high (L7 should
be configured as an output).When the counter underflows
the MC1 control bit is reset and the L7 output will go low
until the next timer T1 underflow. Therefore, the width of the
output pulse is controlled by the 8-bit counter and the pulse
duration is controlled by the 16-bit timer T1 (Figure 15). Timer T1 must be configured in "PWM Mode/Toggle TIO Out"
(CNTRL1 Bits 7,6,5 = 101).

.......
-,

o
o

C\I

CO
D.

o
o

Table VII shows the different operation modes for the Modulator/Timer.
TABLE VII. Modulator/Timer Modes
Control Bits In
CNTRL2(OOCC)

MODE 2: PWM TIMER
The counter can also be used as a PWM Timer. In this
mode, an 8-bit register is used to serve as an autoreload
register (MODRL).

a. 50% Duty Cycle:
When MC1 is 1 and MC2, MC3 are 0, a 50% duty cycle free
running signal is generated on the L7 output pin (Figure 14).
The L7 pin must be configured· as an output pin. In this
mode the 8-bit counter is clocked by tC. Setting the MC1

Operation Mode
L7 Function

MC3

MC2

MC1

Normal I/O

50% Duty Cycle Mode (Clocked
bytc)

Variable Duty Cycle Mode
(Clocked by tc) Using Timer 1
Underflow

Modulator Mode (Clocked by tc)

Modulator Mode (Clocked by
CKI)

Note: MC1. MC2 and MC3 control bits are cleared upon reset.

Internal Data Bus

.....--T"""Tr"'J~......

CNTRL2
REGISTER

.........- - - - - SOrTWARE

START /STOP

256 PULSES (MAX.)

CKI-""~~

JUlJL..IL-.....---1LIL.....fL
t
~ORIc

(5"0%

TRIGGERED BY
SOrTWARE

DUTY CYCLE)

TRIGGERED BY
SOrTWARE

TL/DD/1120B-16

FIGURE 13. Mode 1: Modulator Block Diagram/Output Waveform
1-64

(')

ModulatorITimer (Continued)

"tJ

co
I'\)
<:)

(')
C'...

(')
"'
o

INTERNAL DATA BUS

"tJ

co
I'\)

I.4Cl

~_-,-_...........
=_1-'-_......

I'\)

(')
C'...

CNTRL2

(')
"'
o

"tJ

co
I'\)
CAl

rlo._ _ _ _ _ _ _ ___''

(')

UNDERFLOW

C'...

START/STOP
TLlDD/11208-17

256

(I.4AX.)
TL/DD/11208-18

FIGURE 14. Mode 2a: 50% Duty Cycle Output

INTERNAL DATA BUS
o

~--'----''r''"r-'Z--......

CNTRL2
REGISTER

TIMER Tl
' - - - - - - - - UNDERfLOW

8-BIT

L7 PIN
START/STOP
TLlDD/11208-19

TIMER 11
UNDERFLOW

I 8-BIT COUNTER

256

I·

UNDERFLOW

(MAX.)
CONTROLLED BY T1

FIGURE 15. Mode 2b: Variable Duty Cycle Output

1-65

TL/DD/11208-20

..,o
C")

co
DO
o
......

..,
o
N
N

co
O

D-

The device has one differential comparator. Ports LO-L2
are used for the comparator. The output of the comparator
is brought out to a pin. Port L has the following aSSignments:

THE COMPARATOR STATUS/CONTROL BITS
These bits reside in the CNTRL2 Register (Address OCC)
CMPEN

Enables comparator ("1" = enable)

CMPRD

Reads comparator output internally
(CMPEN = 1, CMPOE=X)

N
CO

D-

An example may serve to clarify this procedure. Suppose
we wish to change the edge select from positive (low going
high) to negative (high going low) for L port bit 5, where bit 5
has previously been enabled for an input. The program
would be as follows:

LO Comparator output
L1 Comparator negative input
L2 Comparator positive input

o
......

..,o

the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.

Comparator

RBIT 5,WKEN
SBIT 5,WKEDG
RBIT 5,WKPND
SBIT 5,WKEN
If.· the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup, a safety procedure should also be followed to avoid inherited pseudo
wakeup conditions. After the selected L port bits have been
changed from output to input but before the associated
WKEN bits are enabled, the associated edge select bits in
WKEDG should be set or reset for the desired edge selects,
followed by the associated WKPND bits being cleared. This
same procedure should be used following RESET, since the
L port inputs are left floating as a result of RESET.

CMPOE

Enables comparator output to pin LO
("1" = enable), CMPEN bit must be set to enable this function. If CMPEN = 0, LO will be O.
The Comparator Select/Control bits are cleared on RESET
(the comparator is disabled). To save power the program
should also disable the comparator before the device enters
the HALT mode.
The user program must set up LO, L1 and L2 ports correctly
for comparator Inputs/Output: L 1 and L2 need to be configured as inputs and LO as output.

The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called
Reg:WKPND. The respective bits of the WKPND register
will be set on the occurrence of the selected trigger edge on
the corresponding Port L pin. The user has the responsibility
of clearing these pending flags. Since the Reg:WKPND is a
pending register for the occurrence of selected wakeup
conditions, the device will not enter the HALT mode if any
Wakeup bit is both enabled and pending. Setting the G7
data bit under this condition will not allow the device to enter the HALT mode. Consequently, the user has the responsibility of clearing the pending flags before attempting to
enter the HALT mode.

Multi-Input Wake Up
The Multi-Input Wakeup feature is used to return (wakeup)
the device from the HALT mode. Figure 16 shows the MultiInput Wakeup logic.
This feature utilizes the L Port. The user selects which particular L port bit or combination of L Port bits will cause the
device to exit the HALT mode. Three 8-bit memory mapped
registers, Reg:WKEN, Reg:WKEDG, and Reg:WKPND are
used in conjunction with the L port to implement the MultiInput Wakeup feature.

If a crystal oscillator is being used, the Wakeup signal will
not start the chip running immediately since crystal oscillators have a finite start up time. The WATCHDOG timer prescaler. generates a fixed delay to ensure that the oscillator
has indeed stabilized before allowing the device to execute
instructions. In this case, upon detecting a valid Wakeup
signal only the oscillator circuitry and the WATCHDOG timer
are enabled. The WATCHDOG timer prescaler is loaded
with a value of FF Hex (256 counts) and is clocked from the
tc instruction cycle clock. The tc clock is derived by dividing
down the oscillator clock by a factor of 10. A Schmitt trigger
following the CKI on chip inverter ensures that the WATCHDOG timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specs.
This Schmitt trigger is not part of the oscillator closed loop.
The startup timeout from the WATCHDOG timer enables
the clock signals to be routed to the rest of the chip.

All three registers Reg:WKEN, Reg:WKPND, and
Reg:WKEDG are read/write registers, and are cleared at
reset, except WKPND. WKPND is unknown on reset. .
The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg:WKEDG, which is an 8bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by

1-66

(')

Multi-Input Wakeup

(Continued)

"'C

IPND and TPND bits signal which interrupt is pending. After
an interrupt is acknowledged, the user can check these two
bits to determine which interrupt is pending. This permits the
interrupts to be prioritized under software. The pending flags
have to be cleared by the user. Setting the GIE bit high
inside the interrupt subroutine allows nested interrupts.

INTERNAL DATA BUS

[ill

The software interrupt does not· reset the GIE bit. This
means that the controller can be interrupted by other interrupt sources while servicing the software interrupt.

(X)
I\)

(')

c...

......
(')

"'C

(X)
I\)
I\)

(')

c...
......

(')

INTERRUPT PROCESSING
L7

[ill

The interrupt, once acknowledged, pushes the program
counter (PC) onto the stack and the stack pointer (SP) is
decremented twice. The Global Interrupt Enable (GIE) bit is
reset to disable further interrupts. The microcontroller then
vectors to the address OOFFH and resumes execution from
that address. ,This process takes 7 cycles to complete. At
the end of the interrupt subroutine, any of the following
three instructions return the processor back to the main program: RET, RETSK or RET!. Either one of the three instructions will pop the stack into the program counter (PC). The
stack pointer is then incremented twice. The RETI instruction additionally sets the GIE bit to re-enable further interrupts.

WKEDG

TL/DD/11208-21

FIGURE 16. Multi-Input Wakeup Logic
INTERRUPTS .

The device has a sophisticated interrupt structure to allow
easy interface to the real world. There are three possible
interrupt sources, as shown below.

(X)
I\)
(,.)

(')

c...

A maskable interrupt on external GO input (positive or negative edge sensitive under software control)
A maskable interrupt on timer carry or timer capture

DETECTION OF ILLEGAL CONDITIONS

A non-maskable software! error interrupt on opcode zero

The device incorporates a hardware mechanism that allows
it to detect illegal conditions which may occur from coding
errors, noise, and "brown out" voltage drop situations. Specifically, it detects cases of executing out of undefined ROM
area and unbalanced tack situations.

INTERRUPT CONTROL

Reading an undefined ROM location returns 00 (hexadecimal) as its contents. The opcode for a software interrupt is
~:~O "CC". Tf,u5 a jji09ialol CiCC8:,:,iIIY UlIUt:llilltjU ;:;Oivi wiii
cause a software interrupt.

ENI and ENTI bits select external and timer intArrnptc:: rpspectively. Thus the user can select either or both sources
to interrupt the microcontroller when GIE is enabled.

Reading an undefined RAM location returns an FF (hexadecimal). The subroutine stack on the device grows down for
each subroutine call. By initializing the stack pointer to the
top of RAM, the first unbalanced return instruction will cause
the stack pointer to address undefined RAM. As a result the
program will attempt to execute from FFFF (hexadecimal),
which is an undefined ROM location and will trigger a software in"terrupt.

IEDG selects the external interrupt edge (0 = riSing edge,
1 = falling edge). The user can get an interrupt on both
rising and falling edges by toggling the state of IEDG bit
after each interrupt.

EXTERNAL
INT. PIN

TO
INTERRUPT
LOGIC

TIMER
UNDERFLOW - - - - I
SOFTWARE
INTERRUPT

"'C

----------------....1
FIGURE 17. Interrupt Block Diagram

1-67

TL/DD/11208-27

..,

o
('t)

C\I

Control Registers

D-

CNTRl1 REGISTER (ADDRESS OOEE)

o
........

The Timer and MICROWIRE control register contains the
following bits:

o
C\I

SL1 and SLO Select the MICROWIRE clock divide-by
(00 = 2,01 = 4, 1x = 8)

co
O

..,
C\I

co
DO

..,o........
oo

C\I
CO

D-

IEDG

External interrupt edge polarity select

MSEL

Selects G5 and G4 as MICROWIRE signals
SK and SO respectively

TRUN

Used to start and stop the timer/counter
(1 = run, 0 = stop)

TC1

The Half-Carry bit is also effected by all the instructions that
effect the Carry flag. The flag values depend upon the instruction. For example, after executing the ADC instruction
the values of the Carry and the Half-Carry flag depend upon
the operands involved. However, instructions like SET C
and RESET C will set and clear both the carry flags. Table
XIII lists the instructions that effect the HC and the C flags.
TABLE XIII. Instructions Effecting HC and C Flags

ADC

Timer T1 Mode Control Bit

Depends on Operands Depends on Operands
Set

BltO

RESETC Set

Set

SLO

RRC

Timer T1 Mode Control Bit

TC3

Timer T1 Mode Control Bit

SETC

Bit 7

TC2 I TC3

I TRUN I MSEL IIEDG I

SL1

PSW REGISTER (ADDRESS OOEF)
Global interrupt enable (enables interrupts)

ENI

External interrupt enable

Depends on Operands Depends on Operands

CNTRl2 REGISTER (ADDRESS OOCC)

The PSW register contains the following select bits:
GIE

CFlag

Depends on Operands Depends on Operands

Set

TC2

SUBC

I TC1

. HC Flag

Instr.

BltO

Bit 7

BUSY MICROWIRE busy shifting flag
PND

External interrupt pending

MC3

Modulator/Timer Control Bit

ENTI

Timer T1 interrupt enable

MC2

Modulator/Timer Control Bit

MC1

ModulatorlTimer Control Bit

TPND Timer T1 interrupt pending
(timer Underflow or capture edge)
C

Carry Flip/Flop

Half-Carry Flip/Flop

Bit 7

CMPEN Comparator Enable Bit
CMPRD Comparator Read Bit
CMPOE Comparator Output Enable Bit
WDUDF WATCHDOG Timer Underflow Bit (Read Only)

BltO

I TPND I ENTI I IPND I BUSY I ENI

GIE

WDREG REGISTER (ADDRESS OOCD)
WDREN WATCHDOG Reset Enable Bit (Write Once Only)
BltO

Bit 7

UNUSED

1-68

WDREN

(')

Memory Map

Addressing Modes

All RAM, ports and registers (except A and PC) are mapped
into data memory address space.

There are ten addressing modes, six for operand addressing and four for transfer of control.

TABLE IX. Memory Map
Address

OPERAND ADDRESSING MODES
REGISTER INDIRECT

Contents

00 to 2F

On-chip RAM bytes (48 bytes)

This is the "normal" addressing mode for the chip. The operand is the data memory addressed by the B or X pointer.

30 to 7F

Unused RAM Address Space (Reads as All
Ones)

Expansion Space for On-Chip EERAM
(Reads Undefined Data)

This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B
or X pointer. This is a register indirect mode that automatically post increments or post decrements the B or X pointer
after executing the instruction.

80 to BF
CO to C7
C8
C9
CA
CB
CC
CD
CE
CF

Reserved
MIWU Edge Select Register (Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register (Reg:WKPND)
Reserved
Control2 Register (CNTRL2)
WATCHDOG Register (WDREG)
WATCHDOG Counter (WDCNT)
Modulator Reload (MODRL)

DO
01
02
03
04
05
06
07
08 to DB
DC
DDto OF

Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Reserved for Port C
Port 0 Data Register
Reserved for Port 0

EO to EF
EO to E7
E9
EA
EB
EC
ED
EE
EF

On-Chip Functions and Registers
Reserved for Future Parts
Re'3ef"'!ed
MICROWIRE Shift Register
Timer Lower Byte
Timer Upper Byte
Timer1 Autoreload Register Lower Byte
Timer1 Autoreload Register Upper Byte
CNTRL 1 Control Register
PSW Register

FO to FF
FC
FD
FE

On-Chip RAM Mapped as Registers
X Register
SP Register
B Register

(X)

(')

c..

(')
'"
o

(X)

N
N
(')

c..

'"
(')
o

(X)

N
W
(')

c..

DIRECT
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
IMMEDIATE
The instruction contains an 8-bit immediate field as the operand.
SHORT IMMEDIATE
This addressing mode issued with the LD B, # instruction,
where the immediate # is less than 16. The instruction contains a 4-bit immediate field as the operand.
INDIRECT
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
TRANSFER OF CONTROL ADDRESSING MODES
RELATIVE
This mode is used for the JP instruction with the instruction
field being added to the program counter to produce the
next instruction address. JP has a range from -31 to +32
to :'!!c':: :. C~: bi't: i'C~~t;\:o juii,P (Jr' : 1 i5 ~r"p:QiTlf;ntf;d by
a NOP instruction). There are no "blocks" or "pages" when
using JP since all 15 bits of the PC are used.
ABSOLUTE
This mode is used with the JMP and JSR instructions with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any location in the current 4k program memory segment.
ABSOLUTE LONG
This mode is used with the JMPL and JSRL instructions with
the instruction field of 15 bits replacing the entire 15 bits of
the program counter (PC). This allows jumping to any location in the entire 32k program memory space.
INDIRECT

Reading other unused memory locations will return undefined data.

This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits
of PC) for accessing a location in the program memory. The
contents of this program memory location serves as a partial address (lower 8 bits of PC) for the jump to the next
instruction.

1-69

...,
o
Cf')

'"coD-

o
......
...,

'"
'"

D-

o
......

...,
o
o

'"
CO

D-

Instruction Set
REGISTER AND SYMBOL DEFINITIONS

Symbols
[B)
Memory indirectly addressed by B register
[X]
Memory indirectly addressed by X register
Mem Direct address memory or [B)
Meml Direct address memory or [B) or Immediate data
Imm
a-bit Immediate data
Reg
Register memory: addresses FO to FF (Includes B, X
and SP)
Bit
Bit number (0 to 7)
~
Loaded with
~ Exchanged with

Registers
A
a-bit Accumulator register
B
a-bit Address register
X
a-bit Address register
SP
a-bit Stack pointer register
PC
15-bit Program counter register
PU
upper 7 bits of PC
PL
lower a bits of PC
C
1-bit of PSW register for carry
HC
Half Carry
GIE
1-bit of PSW register for global interrupt enable

Instruction Set
A ~ A + Meml
,A ~ A + Meml + C,C ~ Carry
HC ~ Half Carry
A ~ A + Meml +C,C ~ Carry
HC ~ Half Carry
A ~ AandMeml
A ~ AorMeml
A ~ AxorMeml
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B '1'= Imm
Reg ~ Reg - 1, skip if Reg goes to 0
1 to bit,
Mem (bit= 0 to 7 immediate)
to bit,
Mem
If bit,
Mem is true, do next instr.

ADD
ADC

add
add with carry

SUBC

subtract with carry

AND
OR
XOR
,IFEQ
IFGT
IFBNE
DRSZ
SBIT

Logical AND
Logical OR
Logical Exclusive-OR
IF equal
IF greater than
IF B not equal
Decrement Reg. ,skip if zero
Set bit

RBIT

Reset bit

IFBIT

If bit

Exchange A with memory
Load A with memory
Load Direct memory Immed.
Load Register memory Immed.

LDA
LDA
LDM

Exchange A with memory [B)
Exchange A with memory [X]
Load A with memory [B)
Load A with memory [X]
Load Memory Immediate

A ~ [B)
(B ~ B ± 1)
A ~ [X]
(X ~ X ± 1)
A ~ [B)
(B ~ B ± 1)
A ~ [X]
(X ~ X ± 1)
[B) ~ Imm (B ~ B±1)

CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC

Clear A
IncrementA
Decrement A
Load A indirect from ROM
DECIMAL CORRECT A
ROTATE A RIGHTTHRU C
Swap nibbles of A
SetC
ResetC
IfC
IfnotC

A ~ A+ 1
A ~ A-1
A ~ ROM(PU,A)
A ~ BCD correction (follows ADC, SUBC)
C ---. A 7 ---. ... ---. AO ---. C
A7 ... A4 ~ A3 ... AO
C ~ 1,HC ~ 1
C ~ O,HC ~ 0
If C is true, do next instruction
If C is not true, do next instruction

JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

Jump absolute long
Jump absolute
Jump relative short '
Jump subroutine long
Jump subroutine
Jump indirect
Return from subroutine
Return and Skip
Return from Interrupt
Generate an interrupt
No operation

PC ~ ii (ii = 15 bits, 0 to 32k)
PC11..0 ~ i (i = 12 bits)
PC ~ PC + r (r is -31 to +32, not 1)
[SP] ~ PL,[SP-1] ~ PU,SP-2,PC ~ ii
[SP] ~ PL,[SP-1] ~ PU,SP-2,PC11 .. 0 ~ i
PL ~ ROM(PU,A)
SP+2,PL ~ [SP],PU ~ [SP-1]
SP + 2,PL ~ [SPl.PU ~ [SP-1] ,Skip next instruction
SP+2,PL ~ [SPl,PU ~ [SP-11,GIE ~ 1
[SP] ~ PL,[SP-1] ~ PU,SP-2,PC ~ OFF
PC ~ PC + 1

LDA
LDmem
LDReg

X
X

Mem
A ~ Meml
Mem ~ Imm
Reg ~ Imm

A~O

1-70

Bits 7-4
F

JP -15

JP -31

LDOFO,#i

DRSZOFO

RRCA

ADCA,
#i

ADCA,
[B)

IFBIT
O,[B]

SUBCA,
#i

SUBC
A,[B]

IFBIT
l,[B]

JP -14

JP-30

LD OF1,#i

DRSZOFl

*
JP -13
JP -12
JP -11

JP-29
JP-28
JP-27

LDOF2,#i
LDOF3,#i
LDOF4,#i

DRSZOF2
DRSZOF3

JP-26

LDOF5,#i

LDOF6,#i

DRSZOF6

JP-8

JP-24

LDOF7,#i

DRSZOF7

JP-7
JP-6

JP-23
JP-22

LD OF8,#i
LDOF9,#i

DRSZOF8

LDB. OF

IFBNEO

JSR
OOOO-OOFF

JMP
OOOO-OOFF

JP + 17

INTR

LD B. OE

IFBNE 1

JSR
0100-01FF

JMP
0100-01FF

JP + 18

JP + 2

1 -t

LD B, OD

IFBNE2

JSR
0200-02FF

JMP
0200-02FF

JP + 19

JP + 3

LDB,OC

IFBNE3

JSR
0300-03FF

JMP
0300-03FF

JP + 20

JP + 4

LD B,OB

IFBNE4

JSR
0400-04FF

JMP
0400-04FF

JP + 21

JP + 5

LDB,OA

IFBNE5

JSR
0500-05FF

JMP
0500-05FF

JP + 22

JP + 6

LDB,9

IFBNE6

JSR
0600-06FF

JMP
0600-06FF

JP + 23

JP + 7

LDB,8

IFBNE7

JSR
0700-07FF

JMP
0700-07FF

JP + 24

JP + 8

JSR
0800-08FF

JMP
0800-08FF

JP + 25

IFBIT
2,[B]

XA,
. [X-]

XA,
[B-]

IFGTA,
#i

IFGT
A,[B]

IFBIT
3,[B]

LAID

ADDA,
#i

ADD
A,[B]

IFBIT
4,[B]

JID

ANDA,
#i

AND
A,[B]

IFBIT SWAPA
5,[B]

XA,
[X]

XA,
[B)

XORA,
#i

XOR
A,[B]

IFBIT
6,[B]

ORA,
#i

OR
A,[B]

IFBIT
7,[B]

IFC

SBIT
O,[B]

RBIT
O,[B]

LDB,7

LDA,
#i

IFNC

JSR
0900-09FF

JMP
0900-09FF

JP + 26

JP + 10

RBIT
l,[B]

IFBNE9

SBIT
l,[B]

LDB,6

NOP

DRSZOF9

CLRA

DCORA

IFBNE8

JP + 9

JP -21

LDOFA,#i

DRSZOFA

LDA,
[X+]

LDA,
[B+]

LD
[B+],#i

INCA

SBIT
2,[B]

RBIT
2,[B]

LDB,5

IFBNEOA

JSR
OAOO-OAFF

JMP
OAOO-OAFF

JP + 27

JP + 11

JP-4

JP-20

LDOFB,#i

DRSZOFB

LDA,
[X-]

LDA,
[B-]·

LD
[B- ],#i

DECA

SBIT
3,[B]

RBIT
3,[B]

LDB,4

IFBNEOB

JSR
OBOO-OBFF

JMP
OBOO-OBFF

JP + 28

JP + 12

JP-3

JP -19

LD OFC,#i

DRSZOFC

LDMd,
#i

JMPL

XA,Md

SBIT
4,[B]

RBIT
4,[B]

LDB,3

IFBNEOC

JSR
OCOO-OCFF

JMP
OCOO-OCFF

JP + 29

JP +13

JP-2

JP -18

LDOFD,#i

DRSZOFD

DIR

JSRL

LDA,
Md

RETSK

SBIT
5,[B]

RBIT
5,[B]

LDB,2

IFBNEOD

JSR
ODOO-ODFF

JMP
ODOO-ODFF

JP + 30

JP +14

JP -1

JP -17

LDOFE,#i

DRSZOFE

LDA,
[X]

LDA,
[B)

LD
[BJ. #i

RET

SBIT
6, [B)

RBIT
6, [B)

LD B,l

IFBNEOE

JSR
OEOO-OEFF

JMP
OEOO-OEFF

JP + 31

JP +15

JP-O

JP -16

LDOFF,#l

DRSZOFF

RETI

SBIT
7,[B]

RBIT

LDB,O

IFBNEOF

JSR
OFOO-OFFF

JMP
OFOO-OFFF

JP + 32

JP + 16

*
where.

is the immediate data

Md is a directly addressed memory locaticn

Co)

JP-5

m
r-

IFEQ
A,[B]

*
JP -25

IFEQA,
#i

DRSZOF5

JP-9

XA,
[B+]

*
JP -10

XA,
[X+]

DRSZOF4

o
"'C
o
o
c

• is an unused opcode (see following table)

rOE~8dOO/rO~~8dOO/rOO~8dOO

iii

..,

o
Cf)
N

CX)

..,......
o
N
N

CX)

BYTES and CYCLES per

Instruction Execution Time

Most instructions are single byte (with immediate addressINSTRUCTION
ing mode instruction taking two bytes).
The following table shows the number of bytes and cycles
Most single instructions take one cycle time to execute.
for each instruction in the format of byte/cycle .
See the BYTES and CYCLES per INSTRUCTION table for
details.
Arithmetic Instructions (Bytes/Cycles)

..,......
oo
N

CX)

o
o

[B]

Direct

Immed.

ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4

2/2
2/2
2/2
2/2 .
2/2
2/2
2/2
. 2/2

SBIT
RBIT
IFBIT

1/1
1/1
1/1

3/4
3/4
3/4

1/3

Memory Transfer Instructions (Bytes/Cycles)
Register
Register Indirect
Auto Incr & Decr
Indirect Direct Immed.
[B] [X]
[B+, B-] [X+,X-]
XA,·
1/1
LDA,·
1/1
LDB,lmm
LDB,lmm
LDMem,lmm
LDReg,lmm

1/3
1/3

2/3
2/3

2/2
1/1
2/3

3/3

1/2
1/2

1/3
1/3
(If B < 16)
(If B > 15)

2/2
2/3

• = > Memory location addressed by B or X or directly.

Instructions Using A & C
Instructions
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC

Transfer of Control Instructions
Instructions

Bytes/Cycles
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1

JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

1-72

Bytes/Cycles
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5

117
1/1

flexible user-interface for maximum productivity. Interchangeable probe cards, which connect to the standard
common base, support the various configurations and packages of the COPS family.

BYTES and CYCLES per
INSTRUCTION (Continued)
The following table shows the instructions assigned to unused opcodes. This table is for information only. The operations performed are subject to change without notice. Do
not use these opcodes.
Unused
Opcode
60
61
62
63
67
SC
99
9F
A7
AS

Instruction
NOP
NOP
NOP
NOP
NOP
RET
NOP
LD [B], #i
XA,[B]
NOP

Unused
Opcode
A9
AF
B1
B4
B5
B7
B9
BF

The iceMASTER provides real time, full speed emulation up
to 10 MHz, 32 kBytes of emulation memory and 4k frames
of trace buffer memory. The user may define as many as
32k trace and break triggers which can be enabled, disabled, set or cleared. They can be simple triggers based on
code or address ranges or complex triggers based on code
address, direct address, opcode value, opcode class or immediate operand. Complex breakpoints can be ANDed and
ORed together. Trace information consists of address bus
values, opcodes and user selectable probe clips status (external event lines). The trace buffer can be viewed as raw
hex or as disassembled instructions. The probe clip bit values can be displayed in binary, hex or digital waveform formats.

Instruction
NOP
LOA, [B]
C ~ HC
NOP
NOP
XA, [X]
NOP
LOA, [X]

Option List

The iceMASTER's performance analyzer offers a resolution
of better than 6 J-ts. The user can easily monitor the time
spent executing specific portions of code and find "hot
spots" or "dead code". Up to 15 independent memory areas based on code address or label ranges can be defined.
Analysis results can be viewed in bargraph format or as
actual frequency count.

The mask programmable options are listed below. The options are programmed at the same time as the ROM pattern
to provide the user with hardware flexibility to a variety of
oscillation and packaging configuration.
OPTION 1: CKIINPUT
= 1

Crystal (CKI/IO) CKO for crystal configuration

= 2

External (CKI/IO) CKO available as G7 input

= 3

RIC (CKI/IO) CKO available as G7 input

OPTION 2: BROWN OUT
= 1

Enable Brown Out Detection

= 2

Disable Brown Out Detection

The ice MASTER comes with an easy to use windowed interface. Each window can be sized, highlighted, color-contiO::",J, a.uuta.l, VI It:HIIUV~U cornpieieiy. Commands can be
accessed via pull-down-menus and/or redefinable hot keys.
A context sensitive hypertextlhyperlinked on-line help system explains clearly the options the user has from within
any window.

OPTION 3: BONDING
-

2a-f,lill DiP

20-pin DIP/SO

16-pin SO

2S-pin SO

The ice MASTER connects easily to a PC via the standard
COMM port and its 115.2 kBaud serial link keeps typical
program download time to under 3 seconds.

Development Support
IN·CIRCUIT EMULATOR

The following tables list the emulator and probe cards ordering information.

The MetaLink iceMASTERTM-COPS Model 400 In-Circuit
Emulator for the COPS family of microcontrollers features
high-performance operation, ease of use, and an extremely

1-73

Q)
I\)

oc..
........
o

a"0
Q)
I\)
I\)

o
c..

........

a"'tJ
Q)
I\)
(,.)

o
c..

o
C"')
N

Development Support (Continued)

D-

Emulator Ordering Information

o
......
~
o
N

Part Number

Current Version

Description

IM-COPS/400/1:j:

MetaLink base unit in-circuit emulator for all COPS devices, symbolic debugger
software and RS 232 serial interface cable, with 11 OV @ 60 Hz Power Supply.

D-

IM-COPS/400/2:j:

o
......
~
o
o

MetaLink base unit in-circuit emulator for all COPS devices, symbolic debugger
software and RS 232 serial interface cable, with 220V @ 50 Hz Power Supply.

DM-COPS/S20CJ:j:

MetaLink IceMaster Debug Module. This is the low cost version of MetaLinks
IceMaster. Firmware: Ver. 6.07.

co
O

HOST SOFTWARE:
VER. 3.3 REV.5,
Model File Rev 3.050 .

Hhese parts include National's COPS Assembler/Linker/Librarian Package (COPS-DEV·IBMA).

D-

Assembler Ordering Information

Probe Card Ordering Information
Part Number

Package

Voltage
Range

Emulates

MH-S20CJ20D5PC

20 DIP

4.5V-5.5V COPS22CJ

MHW-S20CJ20DWPC

20 DIP

2.3V-6.0V COPS22CJ

MHW-S20CJ2SD5PC

2S DIP

4.5V-5.5V COPS20CJ

MHW-S20CJ2SDWPC

2S DIP

2.3V-6.0V COPS20CJ

Part Number

Description

Manual

COPS-DEV-IBMA

COPS
Assemblerl
LinkerI Librarian
for IBM® PC-XT®,
AT® or
compatible

424410632-001

SINGLE CHIP EMULATOR

MACRO CROSS ASSEMBLER

The COPS20CJ family is supported by One~Time Programmable (OTP) emulators. For more detailed information refer
to the emulation device specific data sheets and the emulator selection table below.

National Semiconductor offers a COPS macro cross assembler. It runs on industry standard compatible PCs and supports all of the full-symbolic debugging features of the MetaLink iceMASTER emulators.

PROGRAMMING SUPPORT

Programming of the single chip emulator devices is supported by different sources.

1-74

(')

Development Support (Continued)

'"C

The following programmers are ceritfied for programming the One-Time Programmable (OTP) devices:
EPROM Programmer Information
Manufacturer
and Product

U.S. Phone
Number

(')

c:..
.......
Asia Phone
Number

Europe Phone
Number

(')

o'"C
CD

Germany:
+ 49-8141-1 030

Hong Kong:
+852-737-1800

(408) 745-7974

Germany:
+ 49-2041-684758

Singapore:
+ 65-276-6433

BP MicrosystemsEP-1140

(800) 225-2102

Germany:
+ 49-89-857-66-67

Hong Kong:
+ 852-388-0629

Data I/O-Unisite;
-System 29.
-System 39

(800) 322-8246

Europe:
+ 31-20-622866
Germany:
+ 49-89-858020

Japan:
+ 33-432-6991

c:..

MetaLink-Debug
Module

(602) 926-0797

XeltekSuperpro

Abcom-COP8
Programmer
System General
Turpro-1-FX;
-APRO

N
N

(')

c:..
.......
(')

'"C
N

CJ,)

(')

Europe:
+89-808707
(408) 263-6667

Switzerland:
+31-921-7844

Taiwan Taipei:
+2-9173005

One-Time Programmable (OTP) Selection Table
Device Number

Package

Emulates

COP8720CJN

28DIP

COP820CJ

COP8720CJWM

28S0

COP820CJ

COP8722CJWM

20 DIP

COP822CJ

DIAL-A-HELPER

If the user has a PC with a communications package then
files from the FILE SECTION can be down·loaded to disk for
later use.

Dial-A-Helper is a service provided by the Microcontroller
Applications Group. The Dial-A-Helper is an Electronic Rillletin Board information system.

FACTORY APPLICATIONS SUPPORT
Dial-A-Helper also provides immediate factory applications
support. If a user has questions. he can leave messages on
our electronic bulletin board.

INFORMATION SYSTEM
The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities could be found. The minimum requirement for accessing the Dial-A-Helper is a Hayes compatible
.
modem.

Voice:

(800) 272-9959

Modem: Canada/
U.S.:

(800) NSC-MICRO
(800) 672-6427

Baud:
Setup:

14.4k
Length:

8-Bit

Parity:

None

Stop Bit: 1
Operation: 24 Hrs. 7 Days

1-75

...I

CD
CO

f}1National Semiconductor

D..

......
o
o

COP8620C/COP8622C/COP8640C/COP8642CI

COP86L20C/COP86L22C/COP86L40C/COP86L42C
D..
Single-Chip microCMOS Microcontrollers
oo

...I

CD
CO

......
o
N
N

...I
CD
CO

D..

o
......
o
o
N

...I
CD
CO

D..

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CO

General Description

The COP8620C/COP8640C are members of the COPSTM
microcontroller family. They are fully static parts, fabricated
using double-metal silicon gate microCMOS technology.
These low cost microcontrollers are complete microcomputers containing all system timing, interrupt logic, ROM, RAM,
EEPROM, and I/O necessary to implement dedicated control functions in a variety of applications. Features include
an 8-bit memory mapped architecture, MICROWIRE/
PLUSTM serial I/O, a 16-bit timer/counter with capture register and a multi-sourced interrupt. Each I/O pin has software selectable options to adapt the device to the specific
application. The part operates over a voltage range of 4.5V
to 6.OV. High throughput is achieved with an efficient, regular instruction set operating at a 1 microsecond per instruction rate.

D..

o Features
o • Low Cost 8-bit microcontroller
......
oo • Fully static CMOS
~

CD
CO

D..

o
......
o
N
N

CD
CO

D..

• 1 }Ls instruction time
• Low current drain (2.2 mA at 3 }Ls instruction rate)
Low current static HALT mode (Typically < 1 }LA)
• Single supply operation: 4.5 to 6.OV
• 2048 Bytes ROM/64 Bytes· RAM/64 Bytes EEPROM
on COP8640C

• 1024 bytes ROM/64 bytes RAM/64 bytes EEPROM on
COP8620C
• 16-bit read/write timer operates in a variety of modes
- Timer with 16-bit auto reload register
- 16-bit external event counter
- Timer with 16-bit capture register (selectable edge)
• Multi-source interrupt
- Reset master clear
.:.... External interrupt with selectable edge
- Timer interrupt or capture interrupt
- Software interrupt
• 8-bit stack pOinter (stack in RAM)
• Powerful instruction set, most instructions single byte
• BCD arithmetic instructions
• MICROWIRE PLUSTM serial I/O
• 28 pin package (optional 20 pin package)
• 24 input/output pins (28-pin package)
• Software selectable I/O options (TRI-STATE®, pushpull, weak pull-up)
• Schmitt trigger inputs on Port G
• Temperature range: -40°C to + 85°C, -55°C to
+125°C
• Hybrid emulator devices
• Fully supported by MetaLink's Development Systems

Block Diagram

o
......
o
o

CKI

I'{ESEf VCC

GND

~ ~ ~

N
CD
CO

D..

o
o

PORT L

FIGURE 1

1-76

PORT D

PORT G

PORT I

TL/DD/10366-1

(')

COP86L20C/COP86L22C/COP86L40C/COP86L42C

"'C

0')

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
7V
Voltage at any Pin
-0.3V to Vee + 0.3V
Total Current into Vee Pin (Source)
50mA

Total Current out of GND Pin (Sink)
Storage Temperature Range

60 mA
-65°C to + 140°C

Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electri·
cal specifications are not ensured when operating the de·
vice at absolute maximum ratings.

(')

.......
(')

o"'C
GO

0')

N
N

(')

.......

DC Electrical Characteristics
Parameter
Operating Voltage
Power Supply Ripple (Note 1)

Condition

Max

Units

2.5

6.0
0.1 Vee

V
V

4.5

6.0

.......

= 6V, tc = 111-s

Sink
All Others
Source (Weak Pull· Up)
Source (Push·Pull Mode)
Sink (Push· Pull Mode)

0')
,I::io.

(')

"'C

0')
,I::io.

Vee
Vee

= 6.0V, tc = 1 I1-s
= 6V, CKI = 0 MHz

15
10

I1-A

N
(')

.......
(')

"'C

0.1 Vee

V
V

0.2 Vee

V
V

+2
-250

I1-A
I1-A

0.9 Vee
0.7 Vee
Vee
Vee

= 6.0V
= 6.0V, VIN = OV

-2
-40

G Port Input Hysteresis (Note 5)
Output Current Levels
DOutputs
Source

Typ

"'C

o
Vee

Input Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi·Z Input Leakage
Input Pullup Current

Min

Peak to Peak

Operating Voltage during EEPROM Write
Supply Current (Note 2)
CKI = 10 MHz
Supply Current during
Write Operation (Note 2)
CKI = 10 MHz
HALT Current (Note 3)

(')

-40°C :5: TA :5: +85°C unless otherwise specified

0.35 Vee

0')

o
(')
.......
(')

"'C
GO

0')

N
(")

.......

Vee
Vee
Vee
\Icc

=
=
=
=

4.5V, VOH = 3.8V
2.5V, VOH = 1.8V
4.5V, VOL = 1.0V
2.5'1, 'lui... = (!.~V

-0.4
-0.2
10
2

mA
mA
mA
fl1A

(')

"'C

0')

,I::io.

Vee
Vee
Vee
Vee
Vee
Vee

=
=
=
=
=
=

4.5V, VOH = 3.2V
2.5V, VOH = 1.8V
4.5V, VOH = 3.8V
2.5V, VOH = 1.8V
4.5V, VOL = O.4V
2.5V, VOL = O.4V

TRI·STATE Leakage

-10
-2.5
-0.4
-0.2
1.6
0.7
-2.0

-110
-33

I1-A
I1-A
mA
mA
mA
mA

+2.0

I1-A

o
(')
.......

(')

"'C

0')

r,I::io.
N

(')

Allowable Sink/Source
Current Per Pin
D Outputs (Sink)
All Others
Maximum Input Current (Note 4)
Without Latchup (Room Temp) (Note 5)

Room Temp

RAM Retention Voltage, Vr

500 ns Rise and Fall Time (Min)

mA
mA

±100

10
10,000

ms
Cycle
Years

2.0

Input Capacitance (Note 5)
EEPROM Characteristics
EEPROM Write Cycle Time
EEPROM Number of Write Cycles
EEPROM Data Retention

15
3

Note 1: Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input. CKO
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations.

open. inputs at rails and outputs open.
Test conditions: All inputs tied to Vee. Land

G ports are at
TRI·STATE and tied to ground. all outputs low and tied to ground.
Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than Vee and the pins will
have sink current to Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vecl. The effective
resistance to Vee is 7500 (typical). These two pins will not latch up. The voltage at G6 and RESET pins must be limited to less than 14V.

1·77

oC\I

oq-

...I
to

a..

o
o
.......

oq-

...I
to
CO

a..

.......

o
C\I
C\I

...I
to

a..

.......

o
o

C\I

...I
to
CO

a..

o.......
o
C\I
oq-

a..
oo
.......
o
o
oq-

COP86L20C/COP86L22C/COP86L40C/COP86L42C
AC Electrical Characteristics
Parameter
Instruction Cycle Time (tc)
Ext, Crystal/Resonator
(Div-by 10)
R/C Oscillator Mode
(Div-by 10)
CKI Clock Duty Cycle (Note 5)
Rise Time (Note 5)
Fall Time (Note 5)

-40°C

~ TA ~ +85°C unless otherwise specified
Max

Units

1
2.5
3
7.5

DC
DC
DC
DC

J-Ls
J-Ls
J-Ls
J-Ls

60
12
8

%
ns
ns

Condition

Min

Vee ~ 4.5V
2.5V ~ Vee ~ 6.0V
Vee ~ 4.5V
2.5V ~ Vee ~ 6.0V

Typ

fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock

Inputs
tSETUP
tHOLD
Output Propagation Delay
tpD1, tpDO
SO,SK
All Others

(Continued)

200
60

·ns
ns

CL == 100 pF, RL= 2.2 kn
0.7
1

ns'
ns

20
56

MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output
Propagation Delay Time (tUPD)

220

Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

te
te
te
te

Reset Pulse Width

1.0

Timing Diagram

o
C\I
C\I

a..

o.......
o
o

~
!:=i
.

t UPD

a..

o
o

~
tuwh

C\I

FIGURE 2. MICROWIRE/PLUS Timing

1-78

J-LS'

Note 5: Parameter sampled (not 100% tested).

a..
oo
.......

J-Ls
J-Ls

TL/DD/l0366-19

COP8620C/COP8622C/COP8640C/COP8642C

"'0

en
0)

Absolute Maximum Ratings

60 rnA
Total Current out of GND Pin (Sink)
Storage Temperature Range
- 65°C to + 140°C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electriI 'al specifications are not ensured when operating the de...ice at absolute maximum ratings.

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
7V
Voltage at any Pin
-0.3V to Vee + 0.3V
50 rnA
Total Current into Vee Pin (Source)

DC Electrical Characteristics

-40°C ~ TA ~ +B5°C unless otherwise specified

Parameter

Condition

Operating Voltage
Power Supply Ripple (Note 1)
Supply Current (Note 2)
CKI = 10 MHz
Supply Current during
Write Operation (Note 2)
CKI = 10 MHz
HALT Current (Note 3)

Min

Typ

4.5
Peak to Peak

o.......
o

"'0

en
0)
N
N

o.......
o
o

Max

Units

6.0
0.1 Vee

V
V

Vee

= 6V, tc = 1 IJ-s

rnA

Vee
Vee

= 6.0V, tc = 1 IJ-s
= 6V, CKI = 0 MHz

15
10

rnA
IJ-A

0.1 Vee

V
V

0.2 Vee

V
V

"'0

en
0)
~

o
.......

o"'0
en

Input Levels
RESET,CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current

0.9 Vee
0.7 Vee
Vee
Vee

= 6.0V
= 6.0V, VIN = OV

-2
-40

G Port Input Hysteresis (Note 5)
Output Current Levels
DOutputs
Source
Sink
All Others
Source (Weak Pull-Up)
Source (Push-Pull ModA)
Sink (Push-Pull Mode)
TRI-STATE Leakage

+2
-250
0.35 Vee

IJ-A
IJ-A
V

en
~

o
.......
o

o"'0
en
0)

o
o
.......

"'0

en
0)

N
N

= 4.5V, VOH = 3.BV
= 4.5V, VOL = 1.0V

-0.4
10

Vee = 4.5V, VOH = 3.2V
'Icc = 4.5'1, VCn = 3.8'/
Vee = 4.5V, VOL = O.4V

-10
-0.4
1.6
-2.0

Vee
Vee

Allowable Sink/Source
Current Per Pin
D Outputs (Sink)
All Others

rnA
rnA
-110

+2.0

IJ-A
rnA
rnA
IJ-A

15
3

rnA
rnA

±100

rnA

o.......
o

o"'0
~

o
.......

Maximum Input Current (Note 4)
Without Latchup (Room Temp) (Note 5)

Room Temp

RAM Retention Voltage, Vr

500 ns Rise and Fall Time (Min)

2.0

Input Capacitance (Note 5)
EEPROM Characteristics
EEPROM Write Cycle Time
EEPROM Number of Write Cycles
EEPROM Data Retention

10
10,000

ms
Cycle
Years

Note 1: Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vcc, Land G ports are at
TRI-STATE and tied to ground, all outputs low and tied to ground.
Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than Vee and the pins will
have sink current to Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vecl. The effective
resistance to Vee is 7500 (typical). These two pins will not latch up. The voltage at G6 and ~ pins must be limited to less than 14V.

1-79

o"'0
en
0)

r~
N

oC\I
~

-I

COP8620C/COP8622C/COP8640C/COP8642C (Continued)

a..
o
......
o
o

AC Electrical Characteristics
Parameter

a..

Instruction Cycle Time (tc)
Ext, Crystal/Resonator
(Div-by 10)
R/C Oscillator Mode
(Div-by 10)

......
o
C\I

CKI Clock Duty Cycle (Note 5)
Rise Time (Note 5)
Fall Time (Note 5)

-I

Inputs
tSETUP
tHOLD

-I
CD

C\I

a..
o
......

o
oo

C\I

-I
CD

a..
o
o
......
o
C\I

a..

......
o
o

Output Propagation Delay
tpD1, tPDO
SO,SK
All Others

-40°C

~ + 85°C unless otherwise specified

Condition

Min

Typ

Max

Units

/.Ls

60
12
8

%
ns
ns

fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
200
60

ns
ns

CL = 100 pF, RL = 2.2 kn
0.7
1

MICROWIRETM Setup Time. (tUW8)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output
Propagation Delay Time (tUPD)

20
56

ns
ns
220

Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

tc
tc
tc
tc

Reset Pulse Width

1.0

Note 5: Parameter sampled (not 100% tested).

a..
oo
......
o
C\I
C\I

D..

......

o
o

C\I

a..
o

1-80

/.Ls
/.Ls

/.LS

(')

a"1]

COP6620C/COP6622C/COP6640C/COP6642C

co
m
I\)

Absolute Maximum Ratings

o
48mA
Total Current out of GND Pin (Sink)
- 65°C to + 140°C
Storage Temperature Range
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
6V
Supply Voltage {Ved
Voltage at any Pin
-0.3V to Vee + 0.3V
40 rnA
Total Current into Vee Pin (Source)

DC Electrical Characteristics - 55°C ~ TA ~
Parameter
Operating Voltage
Power Supply Ripple (Note 1)
Supply Current (Note 2)
CKI = 10 MHz
Supply Current during
Write Operation (Note 2)
CKI = 10MHz
HALT Current (Note 3)

Peak to Peak

a"1]
co
m
I\)
I\)

(')

Max

Units

5.5
0.1 Vee

V
V

a"1]
co
m
~

(')

"(')
Vee = 5.5V, tc = 1 ,...s

rnA

Vee = 5.5V, tc = 1 Jlos
Vee = 5.5V, CKI = 0 MHz

21
40

rnA
,...A

<10

a"1]
co
m

I\)

(')

"(')
0.1 Vee

V
V

0.2 Vee

V
V

+5
-300

,...A
,...A

0.35 Vee

0.9 Vee
0.7 Vee
-5
-35

Vee = 5.5V
Vee = 4.5V

G Port Input Hysteresis (Note 5)
Output Current Levels
D Outputs
Source
Sink
All Others
Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sin;'; (ru::.il-ruii iviou~)
TRI-STATE Leakage

Typ

4.5

Input Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current

Min

(')

"(')

+ 125°C unless otherwise specified

Condition

(')

a"1]
co
r
I\)
o

(')

"(')

a"1]
co
m
rI\)
I\)

Vee = 4.5V, VOH = 3.8V
Vee = 4.5V, VOL = 1.0V

-0.35
9

Vee = 4.5V, VOH = 3.2V
Vee = 4.5V, VOH = 3.8V
Vee = 4.5V, VOL = U.4V

-9
-0.35
1.4
-5.0

rnA
rnA
-120

+5.0

,...A
rnA
rnA
,...A

(')

"(')

"1]

(')

"(')

Allowable Sink/Source
Current Per Pin
D Outputs (Sink)
All Others
Maximum Input Current (Note 4)
Without Latchup (Room Temp) (Note 5)

Room Temp

RAM Retention Voltage, Vr

500 ns Rise and Fall Time (Min)

rnA
rnA

± 100

rnA

10
10,000

ms
Cycle
Years

2.5

Input Capacitance (Note 5)
EEPROM Characteristics
EEPROM Write Cycle Time
EEPROM Number of Write Cycles
EEPROM Data Retention

12
2.5

Note 1: Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input. CKO open. inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from OSCillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vec. Land G ports are at
TRI-STATE and tied to ground. all outputs low and tied to ground.
Note 4: Pins G6 and RESET are deSigned with a high voltage input network for factory testing. These pins allow input voltages greater than Vce and the pins will
have sink current to Vee when biased at voltages greater than Vec (the pins do not have source current when biased at a voltage below Vecl. The effective
resistance to Vcc is 7500 (typical). These two pins will not latch up. The voltage at G6 and RESET pins must be limited to less than 14V.

1-81

"1]

co
r
m

~
I\)

(')

o
N

0I::t

...I

COP6620C/COP6622C/COP6640C/COP6642C (Continued)

D-

o.......
oo
0I::t

...I

AC Electrical Characteristics - 55°C ~ TA ~ + 125°C unless otherwise specified
Parameter

Condition

Instruction Cycle Time (tc)
Ext, Crystal/Resonator
(Div-by 10)

Min

Typ

Max

Units

,."s

60
12
8

D-

O
o
.......

oN
N

...I
CD

D-

O
o
.......
o
o
N
...J

D-

O
o.......

0I::t

D-

o.......
oo

CKI Clock Duty Cycle (Note 5)
Rise Time (Note 5)
Fall Time (Note 5)

fr
fr

=
=

9 MHz Ext Clock
9 MHz Ext Clock

Inputs
tSETUP
tHOLO
Output Propagation Delay
tp01, tpoo
SO,SK
All Others

220
66
CL

%
ns
ns
ns
ns

100 pF. RL = 2.2 kn'
0.8
1.1

MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output
Propagation Delay Time (tuPO)

ns
ns

20
56
220

Input Pulse Width
Interrupt Input High Time
Interrupt Input' Low Time
Timer Input High Time
Timer Input Low Time

tc
tc
tc
tc

Reset Pulse Width

1.0

Note 5: Parameter sampled (not 100% tested) .

0I::t

D-

o.......
o
N
N

D-

o.......
oo
N

D-

1-82

,."s
,."S

,."s

C')

Connection Diagrams

"'D

DUAL-IN-LINE PACKAGE

G4/S0

28 DIP

20 DIP
G3/T10

G5/SK
GI
G7/CKO

RmT

CKI

vee

GND

.......

(;4/S0

C3/T10

G5/SK

C6/SI

C7/CKO

GO/INT

C')
C')

o"'D
co

CO/INT

CKI

RESET

VCC

CNO

N
N
C')

.......

C')

o"'D

oI:ao

C')

TL/DD/l0366-3

.......

C')

Top VIew

"'D

Order Number
COP6622C-XXXIN, COP66L22C-XXXIN,
COP6642C-XXXIN, COP66L42C-XXXIN,
COP8622C-XXXIN, COP86L22C-XXXIN,
COP8642C-XXXIN, COP86L42C-XXXIN
See NS Package Number D20A or N20A
(0 Package for Prototypes Only)

TLlDD/l0366-5

Order Number
COP6620C-XXXIN, COP66L20C-XXXIN,
COP6640C-XXXIN, COP66L40C-XXXIN,
COP8620C-XXXIN, COP86L20C-XXXIN,
COP8640C-XXXIN, COP86L40C-XXXIN
See NS Package Number D28C or N28B
(0 Package for Prototypes Only)

G4/S0
G5/SK

28S0Wlde

C')

o"'D

GO/I NT

GO/INT

G3/T10

L.t.l~

'lFl5

N
C')

.......
C')

o"'D

L7
13

GNO

GND
LI

RESET

l31""_0_ _ _ _'...I'.

C')

o"'D

G3/T10

oI:ao
N
C')

.......

o
C')
.......

SURFACE MOUNT
20 SO WIde

en
.oI:ao

L6
DO

C')

.......

TLlDD/l0366-3

C')

Top VIew
l3

Order Number
COP6622C-XXX/WM, COP66L22C-XXX/WM,
COP6642C-XXX/WM, COP66L42C-XXX/WM,
COP8622C-XXX/WM, COP86L22C-XXX/WM,
COP8642C-XXX/WM, COP86L42C-XXX/WM
See NS Package Number M20B

o"'D

L4
TLlDD/l0366-5

Order Number
COP6620C-XXX/WM, COP66L20C-XXX/WM,
COP6640C-XXX/WM, COP66L40C-XXX/WM,
COP8620C-XXX/WM, COP86L20C-XXX/WM,
COP8640C-XXX/WM, COP86L40C-XXX/WM
See NS Package Number M28B

VCC
GND

VCC

CKI

CNO
CKI

RESET

INTR

eKO

t.lICROWIRE/PLUS

INTR

TLlDD/l0366-6

CKO

t.CICROWIRE/PLUS

FIGURE 3. ConnectIon DIagrams

1-83

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COP8620C/COP8640C

COP8622C/COP8642C

TL/DD/l0366-8

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Pin Descriptions

CD
00

Vee and GND are the power supply pins.

-I

D-

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......
o
o

"'=i"

-I
CD
00

D-

o......
o

N
N

-I
CD
00

D-

o
......

oo
N

-I

CD
00

D-

o......
o
N

"'=i"

CD
00

D-

o
......
oo
"'=i"

CD
00

D-

o
......
o
N
N
CD
00

D-

o
......
oo
N

CD
00

D-

how the various logic elements communicate with each other in implementing the instruction set of the device.
ALU AND CPU REGISTERS
The ALU can do an 8-bit addition, subtraction, logical or
shift operation in one cycle time.
There are five CPU registers:
A is the 8-bit Accumulator register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is the 8-bit address register, can be auto incremented or
decremented .
X is the 8-bit alternate address register, can be incremented
or decremented.
SP is the 8-bit stack pointer, points to subroutine stack (in
RAM).
B, X and SP registers are mapped into the on chip RAM.
The B and X registers are used to address the on chip RAM .
The SP register is used to address the stack in RAM during
subroutine calls and returns.

CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunction with CKO). See Oscillator description .
RESET is the master reset input. See Reset description.
PORT I is a four bit Hi-Z input port.
PORT L is an 8-bit I/O port.
There are two registers associated with each L I/O port: a
data register and a configuration register. Therefore, each L
I/O bit can be individually configured under software control
as shown below:
Port L
Conflg.

Port L
Data

Port L
Setup

0
0
1
1

0
1
0
1

Hi-Z Input (TRI-STATE)
Input With Weak Pull-Up
Push-Pull "0" Output
Push-Pull "1" Output

PROGRAM MEMORY
Program memory for theCOP8620C/COP8622C consists
of 1024 bytes of ROM and the COP8640C/COP8642C consists of 2048 bytes of ROM. These bytes may hold program
instructions or constant data. The program memory is addressed by the 15-bit program counter (PC). ROM can be
indirectly read by the LAID instruction for table lookup.

Three data memory address locations are allocated for
these ports, one for data register, one for configuration register and one for the input pins .
PORT G is an 8-bit port with 6 I/O pins (GO-G5) and 2 input
pins (G6, G7). All eight G-pins have Schmitt Triggers on the
inputs. The G7 pin functions as an input pin undor normal
operation and as the continue pin to exit the HALT mode.
There are two registers with each I/O port: a data register
and a configuration register. Therefore, each I/O bit can be
individually configured under software control as shown below.
PortG
Config.

PortG
Data

PortG
Setup

0
0
1
1

0
1
0
1

Hi-Z ,Input (TRI-STATE)
Input With Weak Pull-Up
Push-Pull "0" Output
Push-Pull "1" Output

DATA MEMORY
The data memory address space includes on chip RAM,
EEPROM, I/O and registers. Data memory is addressed directly by the instruction or indirectly through B, X and SP
registers.
The COP8620C/COP8640C has 64 bytes of RAM. Sixteen
bytes of RAM are mapped as "registers", these can be
loaded immediately and decremented and tested. Three
specific registers: X, B, and SP are mapped into this space,
the other registers are available for general usage.
Any bit of data memory can be directly set, reset or tested.
I/O and registers (except A and PC) are memory mapped;
therefore, I/O bits and register bits can be directly and individually set, reset and tested. RAM contents are undefined
upon power-up.
The COP8620C/COP8640C provides 64 bytes of EEPROM
for nonvolatile data memory. The data EEPROM can be
read and written in exactly the same way' as the RAM. All
instructions that perform read and write operations on the
RAM work similarly upon the data EEPROM. The data
EEPROM contains all OOs when shipped by the factory.
A data EEPROM programming cycle is initiated by an instruction such as X, LD, SBIT and RBIT. The EE memory
support circuitry sets the BsyERAM flag in the EECR register immediately upon beginning a data EEPROM write cycle.
It will be automatically reset by the hardware at the end of
the data EEPROM write cycle. The application program
should test the BsyERAM flag before attempting a write operation to the data EEPROM. A second EEPROM write operation while a write operation is in progress will be ignored
and the Werr flag in the EECR register will be set to indicate
the error status. Once the write operation starts, nothing will
stop the write operation, not by resetting the device, and not
even turning off the Vee will guarantee the write operation
to stop.

Three data memory address locations are allocated for
these ports, one for data register, one for configuration register and one for the input pins. Since G6 and G7 are input
only pins, any attempt by the user to set them up as outputs
by writing a one to the configuration register will be disregarded. Reading the G6 and G7 configuration bits will return
zeros. Note that the chip will be placed in the HALT mode
by setting the G7 data bit.
Six bits of Port G have alternate features:
GO INTR (an external interrupt)
G3 TIO (timer/counter input/output)
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock I/O)
G6 SI (MICROWIRE serial data input)
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input (general purpose input)
Pins G1 and G2 currently do not have any alternate functions.
PORT D is a four bit output port that is set high when
RESET goes low.

Warning: The data memory pointer should not point to
EEPROM unless the EEPROM is addressed. This will prevent inadvertent write to EEPROM.

Functional Description
Figure 1 shows the block diagram of the internal. architecture. Data paths are illustrated in simplified form to depict

1-84

o
Functional Description

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(Continued)

EECR AND EE SUPPORT CIRCUITRY

RESET

The EEPROM module contains EE support circuits to generate all necessary high voltage programming pulses. An
EEPROM cell in the erase state is read out as a a and the
written state as a 1. The EECR register provides control,
status and test mode functions for the EE module. The
EECR register bit assignments are shown below.

The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the ports land G are placed
in the TRI-STATE mode and the Port 0 is set high. The PC,
PSW and CNTRl registers are cleared. The data and configuration registers for Ports l & G are cleared. Except bit 3,
the EECR register is cleared.

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........
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Werr

Write Error. Writing to EEPROM while a previous
write cycle is still busy, that is BsyERAM is 1,
causes Werr to be set to 1 indicating error
status. Werr is a Read/Write bit and is cleared
by writing a a into it.

The external RC network shown in Figure 4 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.

Bit

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R/W

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R/W

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........
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5X Power Supply Rise Time

FIGURE 4. Recommended Reset Circuit

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Unused

4**
R/O

3
R/O

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........
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Unused

BsyERAM

5··

TLlDD/l0366-9

Test Mode Codes

6··

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........
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:::::

Test Mode Codes

7··

N
N

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........
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Bits 4 to 7 of the EECR register are used for encoding various EEPROM module test modes, most of which are for
factory manufacturing tests. Except BsyERAM (bit 3) the
EECR is cleared by reset. EECR is mapped into address
location EO. Bit 2 can be used as flag. Bits 1 and 4 are
always read as "0" and cannot be used as flags.

BsyERAM This bit is a read only bit and is set to 1 when
EEPROM is being written. It is automatically reset by the hardware upon completion of the
write operation. This bit is not cleared by reset. If
the bit is set upon power up or reset, the application program should test the BsyERAM flag and
wait for the flag to go low before attempting a
write operation to the data EEPROM.

Werr

2·

1· •

R/W

R/O

R/W

N
N

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........

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·Can be used as flag bit
• ·Cannot be used as flag bit

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1-85

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Functional Description

(Continued)

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......

CKI

CKO

....I

CD
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...f1J

EXTERNAL

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CLOCK

....I

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FIGURE 5. Crystal and R-C Connection Diagrams

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TL/DD/l0366-10

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OSCILLATOR CIRCUITS

C. RIC OSCILLATOR

Figure 5 shows the three clock oscillator configurations.

....I

A. CRYSTAL OSCILLATOR

CKI is configured as a single pin RC controlled Schmitt trigger oscillator. CKO is available as a general purpose input
andl or HALT restart control.

The device can be driven by a crystal clock. The crystal
network is connected between the pins CKI and CKO.

C'i

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......
o
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~

CD
CO

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......

Table \I shows the variation in the oscillator frequencies
(due to the part) as functions of the RIC component values
(RIC tolerances not included) .

Table I shows the component values required for various
standard crystal values.
B. EXTERNAL OSCILLATOR
CKI can be driven by an external clock signal. CKO is available as a general purpose input andlor HALT restart control.

CD
CO

......

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CD
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TABLE I. Crystal Oscillator Configuration, T A

25°C, Vee

5.0V

R1
(kn)

R2
(Mn)

C1
(pF)

C2
(pF)

CKI Freq
(MHz)

0
0
5.5

1
1
1

30
30
100

30-36
30-36
100

10
4

0.455

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......
o
o
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o
o

TABLE II. RC Oscillator Configuration, TA = 25°C, Vee = 5.0V
R
(kn)

C
(pF)

CKI Freq.
(MHz)

Instr. Cycle
(t-Ls)

3.3
5.6
6.8

82
100
100

2.2 to 2.7
1.1 to 1.3
0.9 to 1.1

3.7 to 4.6
7.4 to 9.0
8.8 to 10.8

Note: 3k oS: R oS: 200k
. 50 pF oS: C oS: 200 pF

1-86

Functional Description

a"'C

(Continued)
There are two ways to exit the HALT mode: via the RESET
or by the CKO pin. A low on the RESET line reinitializes the
microcontroller and starts executing from the address
OOOOH. A low to high transition on the eKO pin causes the
microcontroller to continue with no reinitialization from the
address following the HALT instruction. This also resets the
G7 data bit.

The device has three mask options for configuring the clock
input. The CKI and CKO pins are automatically configured
upon selecting a particular option.
-

Crystal/Resonator (CKI/10) CKO for crystal configuration

External (CKI/10) CKO available as G7 input

RIC (CKI/10) CKO available as G7 input

INTERRUPTS

G7 can be used either as a general purpose input or as a
control input to continue from the HALT mode.

There are three interrupt sources, as shown below.

CURRENT DRAIN

A maskable interrupt on external GO input (positive or negative edge sensitive under software control)

The total current drain of the chip depends on:

A maskable interrupt on timer underflow or timer capture

1) Oscillator operating mode-11

A non-maskable software/error interrupt on opcode zero

2) Internal switching current-12

INTERRUPT CONTROL

3) Internal leakage current-13

4) Output source current-14
5) DC current caused by external input not at Vee or GND15
6) EEPROM current during EE read operation. This current
is active during 20% of the instruction cycle time-16

ENI and ENTI bits select external and timer interrupt respectively. Thus the user can select either or both sources
to interrupt the microcontroller when GIE is enabled.

7) EEPROM current during write operation-17
Thus the total current drain, It is given as
It = 11

IEDG selects the external interrupt edge (0 = rising edge,
1 = falling edge). The user can get an interrupt on both
rising and falling edges by toggling the state of IEDG bit
after each interrupt.

To reduce the total current drain, each of the above components must be minimum.
Operating with a crystal network will draw more current than
an external square-wave. The RIC mode will draw the most.
Switching current, governed by the equation below, can be
reduced by lowering voltage and frequency. Leakage current can be reduced by lowering voltage and temperature.
The other two items can be reduced by carefully designing
the end-user's system.
12 = C

xVxf

Where

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INTERRUPT PROCESSING

1-87

o
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The software interrupt does not reset the GIE bit. This
means that the controller can be interrupted by other interrupt sources while servicing the software interrupt.

The interrupt, once acknowledged, pushes the program
counter (PC) onto the stack and the stack pointer (SP) is
decremented twice. The Global Interrupt Enable (GIE) bit is
reset to disable further interrupts. The microcontroller then
vectors to the address OOFFH and resumes execution from
that address. This process takes 7 cycles to complete. At
the end of the interrupt subroutine, any of the following
three instructions return the processor back to the main program: RET, RETSK or RET!. Either one of the three instructions will pop the stack into the program counter (PC). The
stack pointer is then incremented twice. The RETI instruction additionally sets the GIE bit to re-enable further interrupts.

HALT MODE

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C = equivalent capacitance of the chip.

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a

IPND and TPND bits signal which interrupt is pending. After
interrupt is acknowledged, the user can check these two
bits to determine which interrupt is pending. This permits the
interrupts to be prioritized under software. The pending flags
have to be cleared by the user. Setting the GIE bit high
inside the interrupt subroutine allows nested interrupts.

V = operating voltage
f = CKI frequency

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..
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~

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+:10

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-I

Functional Description

(Continued)

o
.......

EXTERNAL
INT. PIN

-I
CD

o
.......

SOFTWARE
INTERRUPT-----------------'

TL/DD/10366-11

N
-I
CD

FIGURE 6. Interrupt Block Diagram

DETECTION OF ILLEGAL CONDITIONS

The device incorporates a hardware mechanism that allows
it to detect illegal conditions which may occur from coding
errors, noise and 'brown out' voltage drop situations. Specif~
ically it detects cases of executing out of undefined ROM
area and unbalanced stack situations.

o
.......
o
o
N

-I
CD

TO
INTERRUPT
LOGIC

TIt.4ER
UNDERFLOW - - - t

TABLE III
SL1

SLO

SK Cycle Time

0
0
1

0
1
x

2tc
4tc
8tc

Reading an undefined ROM location returns 00 (hexadecimal) as its contents. The opcode for a software interrupt is
also '00'. Thus a program accessing undefined ROM will
cause a software interrupt.

tc is the instruction cycle clock.

Reading an undefined RAM location returns an FF (hexadecimal). The subroutine stack grows down for each subroutine call. By initializing the stack pOinter to the top of RAM
(02F), the first unbalanced return instruction will cause the
stack pointer to address undefined RAM. As a result the
program will attempt to execute from FFFF (hexadecimal),
which is an undefined ROM location and will trigger a software interrupt.

Setting the BUSY bit in the PSW register causes the MICROWIRE/PlUS arrangement to start shifting the data. It
gets reset when eight data bits have been shifted. The user
may reset the BUSY bit by software to allow less than 8 bits
to shift. The device may enter the MICROWIRE/PlUS
mode either as a Master or as a Slave. Figure 8 shows how
two microcontrollers and several peripherals may be interconnected using the MICROWIRE/PlUS arrangement.

MICROWIRE/PLUSTM

Master MICROWIRE/PLUS Operation

o
.......

MICROWIRE/PlUS is a serial synchronous bidirectional
communications interface. The MICROWIRE/PlUS capability enables the device to interface with any of National
Semiconductor's MICROWIRE peripherals (Le. AID converters, display drivers, EEPROMS, etc.) and with other microcontrollers which support the MICROWIRE/PlUS interface. It consists of an 8-bit serial shift register (SIO) with
serial data input (SI), serial data output (SO) and serial shift
clock (SK). Figure 7 shows the block diagram of the MICROWIRE/PLUS interface.

In the MICROWIRE/PlllS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIREI
PLUS Master always initiates all data exchanges. (See Figure 8). The MSEl bit in the CNTRl register must be set to
enable the SO and SK functions onto the G Port. The SO
and SK pins must also be selected as outputs by setting
appropriate bits in the Port G configuration register. Table IV
summarizes the bit settings required for Master mode of
operation.

.......

o
N

o.......
o
o

oN
N

o.......
o
o
N

o
o

where,

MICROWIRE/PLUS OPERATION

SLAVE MICROWIRE/PLUS OPERATION

The shift· clock can be selected from either an internal
source or an external source. Operating the MICROWIRE/
PLUS interface with the internal clock source is called the
Master mode of operation. Similarly, operating the MICROWIRE/PLUS interface with an external shift clock is called
the Slave mode of operation.

In the MICROWIRE/PlUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEl
bit in the CNTRl register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by appropriately
setting up the Port G configuration register. Table IV summarizes the settings required to enter the Slave mode of
operation.

The CNTRl register is used to configure and control the
MICROWIRE/PlUS mode. To use the MICROWIRE/PlUS ,
the MSEl bit in the CNTRl register is set to one. The SK
clock rate is selected by the two bits, SlO and Sl1, in the
eNTRl register. Table III details the different clock rates
that may be selected.

1-88

Functional Description

a"C

(Continued)

TABLE IV

MODE 1_ TIMER WITH AUTO-LOAD REGISTER

Fun.

Int.SK

MICROWIRE Master

TRI-STATE

Int.SK

MICROWIRE Master

Ext. SK

MICROWIRE Slave

TRI-STATE Ext. SK

MICROWIRE Slave

Conflg. Conflg.
Bit

Bit

Operation

TIMER/COUNTER

o
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MODE 2. EXTERNAL COUNTER

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Timer T1 can be used to precisely measure external frequencies or events in this mode of operation. The timer T1
counts down at the instruction cycle rate. Upon the occurrence of a specified edge on the TID pin the contents of the
timer T1 are copied into the register R1. Bits in the control
register CNTRl allow the trigger edge to be specified either
as a positive edge or as a negative edge. In this mode the
user can elect to be interrupted on the specified trigger
edge. (See Figure 10.)

14------SI

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MODE 3. TIMER WITH CAPTURE REGISTER

~-----------------+so

In this mode of operation, the timer T1 counts down at the
instruction cycle rate. Upon underflow the value in the register R1 gets automatically reloaded into the timer which continues to count down. The timer underflow can be programmed to interrupt the microcontroller. A bit in the control
register CNTRl enables the TID (G3) pin to toggle upon
timer underflows. This allow the generation of square-wave
outputs or pulse width modulated outputs under software
control. (See Figure 9)

In this mode, the timer T1 becomes a 16-bit external event
counter. The counter counts down upon an edge on the TID
pin. Control bits in the register CNTRl program the counter
to decrement either on a positive edge or on a negative
edge. Upon underflow the contents of the register R1 are
automatically copied into the counter. The underflow can
also be programmed to generate an interrupt. (See Figure 9)

The device has a powerful 16-bit timer with an associated
16-bit register enabling them to perform extensive timer
functions. The timer T1 and its register R1 are each organized as two 8-bit read/write registers. Control bits in the
register CNTRl allow the timer to be started and stopped
under software control. The timer-register pair can be operated in one of three possible modes. Table V details various
timer operating modes and their requisite control settings.

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TL/DD/l0366-12

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FIGURE 7. MICROWIRE/PLUS Block Diagram

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CHIP SELECT LINES

I
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a"C
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LINES

¢:)

COP8620C/
COP8640C
(MASTER)

8 - BIT
A/D CONVERTER
COP43X

01 ClK

VF
DISPLAY
DRIVER

EEPROM

LCD
DISPLAY
DRIVER
COP472-3

01 ClK

COP8620C/
COP8640C
(SLAVE)

TLlDD/l0366-13

1-89

so
SK

FIGURE 8. MICROWIRE/PLUS Application

...I

Functional Description

(Continued)

TABLE V. Timer Operating Modes

o
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......
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~

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......

o
N
N

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CNTRl
Bits

Timer
Counts
On

Operation Mode

T Interrupt

External Counter W / Auto:Load Reg.
External Counter W / Auto-Load Reg.
Not Allowed
Not Allowed
TimerW/Auto-Load Reg.
Timer W / Auto-Load Reg.lToggle TIO Out
Timer W /Capture Register
Timer W /Capture Register

Timer Underflow
. Timer Underflow
Not Allowed
Not Allowed
Timer Underflow
Timer Underflow
TIO Pos. Edge
TIO Neg. Edge

765
000
001
010
01 1
100
101
1 10
111

TIO Pos. Edge
TIO Neg. Edge
Not Allowed
Not Allowed
tc
tc
tc
. tc

o
......
o
o

Ton

.. /'~

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......

o
N

TIO
OUTPUT

tP ..

A SIt.lPLE 0 - A
CONVERTER USING
THE TltolER TO
'GENERATE A PWt.l
OUTPUT.

TL/DD/10366-15

o
......

TL/DD/10366-16

FIGURE 9. Timer/Counter Auto
Reload Mode Block Diagram

o
o

FIGURE 11. Timer Application

Control Registers

CNTRl REGISTER (ADDRESS X'OOEE)

The Timer and MICROWIRE/PLUS control register contains
the following bits:

o......
oN

SL1 &
SLO

TlO INPUT

IEOG

D-

o
......
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External interrupt edge polarity select
(0 = rising edge, 1

Select the MICROWIRE/P~US clock divide-by

Enable MICROWIRE/PLUS functions SO and SK

TRUN

Start/Stop the Timer/Counter (1 =
stop)

TC3

Timer input edge polarity select (0 = rising edge,
1 = falling edge)

TL/DD/10366-14

FIGURE 10. Timer Capture Mode.Block Diagram

=falling edge)

MSEL

TIMER PWM APPLICATION

Figure 11 shows how a minimal component 0/ A converter

TC2

Selects the capture mode

can be built out of the Timer-Register pair in the Auto-Reload mode. The timer is placed in the "Timer with auto reload" mode and the TIO pin is selected as the timer output.
At the outset the TIO pin is set high, the timer T1 holds the
on time and the register R1 holds the signal off time. Setting
TRUN bit starts the timer which counts down at the instruction cycle rate. The underflow toggles the TIO output and
copies the off time into the timer, which continues to run. By
alternately loading in the on time and the· off time· at each
successive interrupt a PWM frequency can be easily generated.

TC1

Selects the timer mode

I TC1

run, 0 =

I TC2 I TC3 I TRUN I MSEL IIEOG I SL 1 ISLa

BIT7

BIT 0

PSW REGISTER (ADDRESS X'OOEF)
The PSW register contains the following select bits:
GIE'

Global interrupt enable

ENI

External interrupt enable

BUSY MICROWIRE/PLUS busy shifting
IPNO

External interrupt pending

ENTI . Timer interrupt enable
TPNO Timer interrupt pending
C
HC

1-90

Carry Flag
Half carry Flag

I HC

I C I TPNO I ENTI IIPNO I BUSY I ENI I GIE

Bit7

BitO

o
DIRECT

Memory Map

The instruction contains an 8-bit address field that directly
points to the data memory for the operand.

All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Address

IMMEDIATE
The instruction contains an 8-bit immediate field as the operand.

Contents

COP8620C/COP8640C

00 to 2F On Chip RAM Bytes

30 to 7F Unused RAM Address Space (Reads as all Ones)

This is a register indirect mode that automatically increments or decrements the B or X register after executing the
instruction.

80 to BF On Chip EEPROM (64 bytes)
CO to CF Expansion Space for I/O and Registers
DOto DF
DO
D1
D2
D3
D4
D5
D6
D7
D8-DB
DC
DD-DF

On Chip I/O and Registers
Port l Data Register
Port l Configuration Register
Port l Input Pins (Read Only)
Reserved for Port l
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Reserved for Port C
Port D Data Register
Reserved for Port D

EO to EF
EO
E1-E8
E9
EA
EB
EC
ED
EE
EF

On Chip Functions and Registers
EECR
Reserved
MICROWIRE/PLUS Shift Register
Timer lower Byte
Timer Upper Byte
Timer Autoload Register lower Byte
Timer Autoload Register Upper Byte
CNTRl Control Register
PSW Register

RELATIVE

This mode is used for the JP instruction, the instruction field
is added to the program counter to get the new program
location. JP has a range of from -31 to + 32 to allow a one
byte relative jump (JP + 1 is implemented by a NOP instruction). There are no 'pages' when using JP, all 15 bits of PC
are used.

"'0

en
N
o
o
......

"'0
CD

en
N
N

o
......
o

o"'0
CD

o
......
o

"'0

en
~

Instruction Set
REGISTER AND SYMBOL DEFINITIONS
Registers
A
8-bit Accumulator register
B
8-bit Address register
X
8-bit Address register
SP
8-bit Stack pointer register
PC
15-bit Program counter register
PU
upper 7 bits of PC
Pl
lower 8 bits of PC
C
1-bit of PSW register for. carry
HC
Half Carry
GIE
1-bit of PSW register for global interrupt enable

FO to FF On Chip RAM Mapped as Registers
FC
X Register
t-=u tiP Hegister
FE
B Register

Symbols
[B]
Memory indirectly addressed by B register
[X]
Memory indirectly addressed by X register
Mem Direct address memory or [B]
Meml Direct address memory or [B] or Immediate data
Imm
8-bit Immediate data
Reg
Register memory: addresses FO to FF (Includes B, X
and SP)
Bit
Bit number (0 to 7)
~
loaded with
~ Exchanged with

Reading unused memory locations below 7FH will return all
ones. Reading other unused memory locations will return
undefined data.

Addressing Modes
REGISTER INDIRECT

This is the "normal" mode of addressing. The operand is
the memory addressed by the B register or X register.

o
......
o

"'0
CD

en
rN
o

o
......
o

"'0
CD

en
rN
N

o
......
o

o"'0
CD

en
.~

o
......

"'0

en
r~

1-91

oC\I
~

..J

Instruction Set (Continued)

Instruction Set

o.......
oo
~

..J

A ~ A + Meml
A ~ A + Meml + C, C ~ Carry
HC ~ Half Carry
A ~ A + Meml + C, C ~ Carry
HC ~ Half Carry
A ~ AandMeml
A ~ AorMeml
A ~ AxorMeml
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B #- Imm
Reg ~ Reg - 1, skip if Reg goes to 0
1 to bit,
Mem (bit= 0 to 7 immediate)
Otobit,
Mem
If bit,
Mem is true, do next instr.

ADD
ADC

add
add with carry

SUBC

subtract with carry

AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT

Logical AND
Logical OR
Logical Exclusive-OR
IF equal
IF greater than
IF B not equal
Decrement Reg. ,skip if zero
Set bit

RBIT

Reset bit

IFBIT

If bit

X
LDA
LDmem
LDReg

Exchange A with memory
Load A with memory
Load Direct memory Immed.
Load Register memory Immed.

A ~ Mem
A ~ Meml
Mem ~ Imm
Reg ~ Imm

X
X
LDA
LDA
LDM

Exchange A with memory [B]
Exchange A with memory [X]
Load A with memory [B]
Load A with memory [X]
Load Memory Immediate

A~[B]

(B ~ B±1)
(X ~ X±1)
A ~ [B]
(B ~ B±1)
A ~ [X]
(X ~ X±1)
[B] ~ Imm(B ~ B±1)

CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC

Clear A
IncrementA
Decrement A
Load A indirect from ROM
DECIMAL CORRECT A
ROTATE A RIGHT THRU C
Swap nibbles of A
SetC
ResetC
IfC
If notC

A~O

JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

Jump absolute long
Jump absolute
Jump relative short
Jump subroutine long
Jump subroutine
Jump indirect
Return from subroutine
Return and Skip
Return from Interrupt
Generate an interrupt
No operation

PC ~ ii (ii = 15 bits, 0 to 32k)
PC11..0 ~ i (i = 12 bits)
PC ~ PC + r (r is -31 to +32, not 1)
[SP] ~ PL,[SP-1] ~ PU,SP-2,PC ~ ii
[SP] ~ PL,[SP-1] ~ PU,SP-2,PC11.. 0 ~ i
PL ~ ROM(PU,A)
SP+2,PL ~ [SP],PU ~ [SP-1]
SP+2,PL ~ [SP],PU ~ [SP-1],Skip next instruction
SP+2,PL ~ [SP],PU ~ [SP-1],GIE ~ 1
[SP] ~ PL,[SP-1] ~ PU,SP-2,PC ~ OFF
PC ~ PC + 1

a.
o
.......
o
C\I

C\I

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CD

.......
oo
C\I

...J
CD

.......

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~

a.
o
.......
o
o

o.......
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C\I

D-

O
o
.......

o
o

C\I

D-

A~[X]

A ~ A+ 1
A ~ A-1
A ~ ROM(PU,A)
A ~ BCD correction (follows ADC, SUBC)
C ~ A7 ~ .. , ~ AO ~ C
A7 ... A4 ~ A3 ... AO
C ~ 1,HC ~ 1
C ~ O,HC ~ 0
If C is true, do next instruction
If C is not true, do next instruction

1-92

Bits 7-4
F

JP -15

JP -31

LDOFO,#i

DRSZOFO

RRCA

ADCA,
#i

ADCA,
[B]

IFBIT
O,[B]

JP-14

JP-30

LDOF1,#i

DRSZOF1

SUBCA,
#i

SUBC
A,[B]

IFBIT
1,[B]

*
JP -13
JP -12
JP -11

JP-29
JP-2B
JP-27

LDOF2,#i
LDOF3,#i
LDOF4,#i

DRSZOF2
DRSZOF3

JP-26

LDOF5,#i

DRSZOF6

JP-B

JP-24

LDOF7,#i

DRSZOF7

....

cO
Co)

JP-7
JP-6

JP-23
JP-22

LDOFB,#i
LDOF9,#i

DRSZOFB

LD B, OF

IFBNEO

JSR
OOOO-OOFF

JMP
OOOO-OOFF

JP + 17

INTR

LD B, OE

IFBNE 1

JSR
0100-01FF

JMP
0100-01FF

JP + 1B

JP + 2

LD B, OD

IFBNE2

JSR
0200-02FF

JMP
0200-02FF

JP + 19

JP + 3

LD B,OC

IFBNE3

JSR
0300-03FF

JMP
0300-03FF

JP + 20

JP + 4

0 C
m
r

IFEQ
A,[B]

IFBIT
2,[B]

XA,
[X-]

XA,
[B-]

IFGT A,
#i

IFGT
A,[B]

IFBIT
3,[B]

LAID

ADD A,
#i

ADD
A,[B]

IFBIT
4,[B]

CLRA

LD B, OB

IFBNE4

JSR
0400-04FF

JMP
0400-04FF

JP + 21

JP + 5

JID

ANDA,
#i

AND
A,[B]

IFBIT
5,[B]

SWAPA

LDB,OA

IFBNE5

JSR
0500-05FF

JMP
0500-05FF

JP + 22

JP + 6

XA,
[X]

XA,
[B]

XORA,
#i

XOR
A,[B]

IFBIT
6,[B]

DCORA

LDB,9

IFBNE6

JSR
0600-06FF

JMP
0600-06FF

JP + 23

JP + 7

OR
A,[B]

IFBIT
7,[B]

IFBNE7

JMP
0700-07FF

JP + B

JSR
0700-07FF

JP + 24

ORA,
#i

LDB,B

IFC

SBIT
O,[B]

RBIT
O,[B]

LDB,7

JSR
OBOO-OBFF

JMP
OBOO-OBFF

JP + 25

LDA,
#i

IFNC

JSR
0900-09FF

JMP
0900-09FF

JP + 26

JP + 10

RBIT
1,[B]

IFBNE9

SBIT
1,[B]

LDB,6

*
LDOF6,#i

IFEQA,
#i

DRSZOF5

JP-25

XA,
[B+]

DRSZOF4

JP-9

o"tI
o

XA,
[X+]

*
JP -10

NOP

DRSZOF9

IFBNEB

!!!

JP + 9

JP -21

LD OFA,#i

DRSZOFA

LDA,
[X+]

LDA,
[B+]

LD
[B+],#i

INCA

SBIT
2,[B]

RBIT
2,[B]

LDB,5

IFBNEOA

JSR
OAOO-OAFF

JMP
OAOO-OAFF

JP + 27

JP + 11

JP-4

JP-20

LDOFB,#i

DRSZOFB

LDA,
[X-]

LDA,
[B-]

LD
[B-],#i

DECA

SBIT
3,[B]

RBIT
3,[B]

LDB,4

IFBNEOB

JSR
OBOO-OBFF

JMP
OBOO-OBFF

JP + 2B

JP + 12

JP-3

JP -19

LDOFC,#i

DRSZOFC

LDMd,
#i

JMPL

XA,Md

SBIT
4,[B]

RBIT
4,[B]

LDB,3

IFBNEOC

JSR
OCOO-OCFF

JMP
OCOO-OCFF

JP + 29

JP +13

JP-2

JP -1B

LDOFD,#i

DRSZOFD

DIR

JSRL

LDA,
Md

RETSK

SBIT
5,[B]

RBIT
5,[B]

LDB,2

IFBNEOD

JSR
ODOO-ODFF

JMP
ODOO-ODFF

JP + 30

JP +14

JP -1

JP -17

LOOFE,#i

ORSZOFE

LOA,
[X]

LOA,
[B]

LO
[B], #i

RET

SBIT
6, [B]

RBIT
6, [B]

LOB,1

IFBNEOE

JSR
OEOO-OEFF

JMP
OEOO-OEFF

JP + 31

JP +15

JP-O

JP -16

LD OFF,#1

DRSZOFF

RETI

JSR
OFOO-OFFF

JMP
OFOO-OFFF

JP + 32

JP + 16

RBIT
7,[B]

IFBNEOF

SBIT
7,[B]

LDB,O

*
where,

is the immediate data

Md is a directly addressed memory locatic n

Co)

JP-5

• is an unused opcode (see following table)

:>~P'98dO:>/:>OP'198dO:>/:>~~'98dOO/:>O~'98dO:>/:>~P98dO:>/:>OP98dO:>/O~~98dO:>/:>O~98dO:>

o
N

-.::t
...I

CD
CO

D-

o
......
oo
-.::t
...I

BYTES and CYCLES per

Instruction Execution Time

Most instructions are single byte (with 'immediate addressINSTRUCTION
i
ing mode instruction taking two bytes).
The.following table shows the. number of bytes and cycles
Most single instructions take one cycle time to execute.
for each instruction in the forrTlat of byte/cycle.
See the BYTES and CYCLES per INSTRUCTION table for
details.'
Arithmetic and Logic instructions

CD
CO

[B]

D-

o
......
o
N
N

...I

CD
CO

D-

o
......
o
o
N

...I
CD
CO

SBIT
RBIT
IFBIT

D-

o
......
o
N

o
N

N
CD
CO

D-

3/4
3/4
3/4

XA,·
1/1 1/3
LOA,·
1/1 1/3
LDB,lmm
LDB,lmm
2/2
LDMem,lmm
LD Reg,lmm
• =

2/3
2/3

o
o

N
CD
CO

D-

1/2
1/2

2/2
1/1
2/3

1/3
1/3
tltB < 16)
(lfB> 15)

2/2

3/3
2/3

> Memory location addressed by 8 or X or-directly.

o
......

o......
oo
o......

Memory Transfer Instructions

CD
CO

2/2
2/2
2/2 '
2/2
2/2
2/2
2/2
2/2
"

1/1
1/1
1/1

CD
CO

D-

3/4.
3/4
3/4
3/4
3/4
3/4
3/4
3/4
1/3 -

-.::t

D-

-.::t

Immed.

Direct

' 1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

ADD
,ADC
SUBC
AND
OR
XOR
IFEQ
IFGT'
IFBNE
DRSZ

Transfer'of Controllnstructi~ns

Instructions Using A & C
: CLRA"
INCA
DECA
LAID
DCORA RRCA
SWAPA
SC
RC
IFC
IFNC

1/1
1/1
1/1
1/3
1/1
1/1
1/1

JMPL
:JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

I'll
1/1
1/1
1/1

1-94

3/4
2/3
1/3
3/5
2/5
1/3
.1/5
1/5
1/5
117
1/1

high-performance operation, ease of use, and an extremely
flexible user-interface for maximum productivity. Interchangeable probe cards, which connect to the standard
common base, support the various configurations and packages of the COP8 family.
The iceMASTER provides real time, full speed emulation up
to 10 MHz, 32k bytes of emulation memory and 4k frames
of trace buffer memory. The user may define as many as
32k trace and break triggers which can be enabled, disabled, set or cleared. They can be simple triggers based on
code or address ranges or complex triggers based on code
address, direct address, opcode value, opcode class or immediate operand. Complex breakpoints can be ANDed or
ORed together. Trace information consists of address bus
values, opcodes and user selectable probe clips status (external event lines). The trace buffer can be viewed as raw
hex or as disassembled instructions. The probe clip bit values can be displayed in binary, hex or digital waveform formats.
During single-step operation the dynamically annotated
code feature displays the contents of all accessed (read
and write) memory locations and registers, as well as flowof-control direction change markers next to each instruction
executed.
The ice MASTER's performance analyzer offers a resolution
of better than 6 ,...S. The user can easily monitor the time
spent executing specific portions of code and find "hot
spots" or "dead code". Up to 15 independent memory areas based on code address or label ranges can be defined.
Analysis results can be viewed in bargraph format or as
actual frequency count.
Emulator memory operations for program memory include
single line assembler, disassembler, view, change and write
to file. Data memory operations include fill, move, compare,
dump to file, examine and modify. The contents of any
memory space can be directly viewed and modified from the
corresponding window.
The ice MASTER comes with an easy to use windowed interface. Each window can be sized, highlighted, color-con-

Instruction

60
61
62
63
67
8C
99
9F
A7
A8

Nap
Nap
Nap
Nap
Nap
RET
Nap
LD [B], #i
XA, [B)
Nap

Unused
Opcode

Instruction

A9
AF
B1
B4
B5
B7
B9
BF

Nap
LOA, [B]
C ~ HC
Nap
Nap
XA,[X]
Nap
LOA, [X]

(CKI/10) CKO for crystal configuration

= 2 External

(CKI/10) CKO available as G7
input
(CKI/10) CKO available as G7
input

= 3 R/C

OPTION 2: BONDING
= 1 28 pin DIP
= 2 N/A
= 320 pin DIP
= 420 SO
= 528 SO

The following option information is to be sent to National
along with the EPROM.
Option Data
Option 1 Value is: _ CKI Input
Option 2 Value is: _ COP Bonding

o
o

-0
Q)
0')

o
.......
o

-0
Q)
0')

N
N

o
.......

-0
Q)
0')
~

o
.......

-0
Q)
0')
~

o.......
o

-0

Q)
0')

o
.......
o

-0
Q)
0')

N
N

o
.......
o

o-0
Q)
0')

trollAn, RnnAn, or rAmovAn comrlAtAly. CommRnn!': CRn hA

accessed via pull-down-menus and/or redefinable hot keys.
A context sensitive. hypertextlhyperlinked on-line help system explains clearly the options the user has from within
any window.
The ice MASTER connects easily to a PC via the standard
COM M port and its 115.2k baud serial link keeps typical
program download time to under 3 seconds.
The following tables list the emulator and probe cards ordering information.

o.......
o
o

-0
Q)
0')

Development Support
IN-CIRCUIT EMULATOR
The MetaLink iceMASTERTM-COP8 Model 400 In-Circuit
Emulator for the COP8 family of microcontrollers features

Emulator Ordering Information
Part Number

Description

IM-COP8/400/1:j:

MetaLink base unit in-circuit emulator for all COP8 devices, symbolic debugger software
and RS-232 serial interface cable, with 11 OV @ 60 Hz Power Supply.

IM-COP8/400/2:j:

MetaLink base unit in-circuit emulator for all COP8 devices, symbolic debugger software
and RS-232 serial interface cable, with 220V @ 50 Hz Power Supplv.

:j: These parts include National's COPB Assembler/Linker/Librarian Package (COPB-DEV-IBMA)

1-95

Current
Version
Host Software:
Ver. 3.3 Rev. 5,
Model File Rev
3.050.

o
N

...J
CD
CO

a..
o
"o
o

Development Support (Continued)
Probe Card Ordering Informaton

SINGLE CHIP EMULATOR DEVICE

MHW-8640C20D5PC 20 DIP 4.5-5.5V COP8642C, 8622C

The COP8 family is fully supported by single chip hybrid
emulators. For more detailed information refer to the emulation device specific data sheets and the emulator selection
table below.

...J

MHW-8640C20DWPC 20 DIP 2.5-6.0V COP8642C, 8622C

PROGRAMMING SUPPORT

a..

MHW-8640C28D5PC 28 DIP 4.5-5.5V COP8640C, 8620C

Programming of the single chip emulator devices is supported by different sources. The table below shows the programmers certified for programming the hybrid emulator
versions.

CD
CO

o
N
N

...J
CD
CO

a..
o
o
"o
o
N

...J
CD
CO

a..
o
"o
N

Part Number

Pkg.

Voltage
Range

Emulates

MHW-8640C28DWPC 28 DIP 2.5-6.0V COP8640C, 8620C
MACRO CROSS ASSEMBLER

DIAL-A-HELPER

National Semiconductor offers a COP8 macro cross assembler. It runs on industry standard compatible PCs and sup~
ports all of the full-symbolic debugging features of the
MetaLink iceMASTER emulators.

Dial-A-Helper is a service provided by the Microcontroller
Applications Group. The Dial-A·Helper is an Electronic Bulletin Board information system.
INFORMATION SYSTEM

Assembler Ordering Information
Part Number

Description

The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities could be found. The minimum requirement for accessing the Dial-A-Helper is a Hayes compatible
modem.

Manual

COP8·DEV-IBMA COP8 Assemblerl
LinkerlLibrarian for
IBM®, PC/XT®, AT®
or compatible.

424410632-001

CD
CO

a..

EPROM Programmer Information

CD
CO

Manufacturer
and Product

u.S. Phone
Number

Europe Phone
Number

Asia Phone
Number

MetaLink-Debug
Module

(602) 926-0797

Germany: + 498141-1030

Hong Kong:
737-1800

Xeltek-Superpro

(408) 745-7974

Germany: + 49
2041 684758

Singapore: + 65 276
6433

BP MicrosystemsEP-1140

(800) 224-2102

Germany + 49 89
8576667

Hong Kong: + 852
3880629

o"o

Data 1/0 - Unisite;
- System 29,
- System 39

(800) 322-8246

Europe: +31-20622866
Germany: .+ 49-8985-8020

Japan: + 33-4326991

a..
o
u

Abcom-COP8
Programmer

a..
o
"o
N

N
CD
CO

a..
o
o
N
CD
CO

System General
Turpro-1-FX;
-APRO

+ 852-

Europe: + 89 808707
(408) 263-6667

Switzerland: + 31921-7844

Taiwan: + 2-9173005

Single Chip Emulator Selection Table
Device Number

Clock Option

Package

COP8640CMHD-X

X = 1: Crystal
X = 2: External
X=3: RIC

28 DIP

Hybrid, UV
Erasable

COP8640C, 8620C

COP8640CMHEA-X

X = 1: Crystal
X = 2: External
X=3: RIC

28S0

Hybrid, UV
Erasable

COP8640C, 8620C

COP8642CMHD-X

X = 1: Crystal
X = 2: External
X=3: RIC

20 DIP

Hybrid, UV
Erasable

COP8642C, 8622C

1-96

Description

Emulates

o"lJ

Development Support (Continued)

If the user has a PC with a communications package then

FACTORY APPLICATIONS SUPPORT

files from the FILE SECTION can be down-loaded to disk for
later use.

Dial-A-Helper also provides immediate factory applications
support. If a user has questions, he can leave messages on
our electronic bulletin board, which we will respond to.

o.......
o

Voice:
(800) 272-9959
Modem: Canada/U.S.:
(800) NSC-MICRO
Baud:
14.4k
Length:
8-Bit
Setup:
Parity:
None
Stop Bit: 1
24 Hrs. 7 Days
Operation:

ORDER PIN: MOLE·DIAL·A·HLP

Information System Package contains:
Dial-A-Helper Users Manual
Public Domain Communications Software

o"tJ
CD

N
N

o
.......
o

o"lJ
CD

0)
~

o
.......
o

"lJ
CD

0)
~

o
.......
o

"lJ

o
o
.......

o"lJ
CD

o
.......

o"lJ
~

o
.......
o

o"lJ
CD

1-97

o......
co
en

a..
o
......
o

o
o

a..
o
o
......
o
......
co
co

a..
o
o
......
o
o
CO
CO

a..
o
o
......
o
......
co

a..
o
o
......

CO
CD

a..

o
o

tfI

National Semiconductor

COP680C/COP681C/COP880C/COP881CI

COP980C/COP981C Microcontrollers
General Description •
The COP680C/COP681 C/COP880C/COP881 C/COP980C,
and COP981C are members of the COPSTM microcontroller
family. They are fully static parts, fabricated using doublemetal silicon gate microCMOS technology. This low cost
microcontroller is a complete microcomputer containing all
system timing, interrupt logic, ROM, RAM, and I/O necessary to implement dedicated control functions in a variety of
applications. Features include an 8-bit memory mapped architecture, MICROWIRE/PLUSTM serial 1/0, a 16-bit timerl
counter with capture register and a multi-sourced interrupt.
Each I/O pin has software selectable options to adapt the
device to the specific application. The part operates over a
voltage range of 2.5 to 6.0V. High throughput is achieved
with an efficient, regular instruction set operating at a 1 microsecond per instruction rate.

Features
•
•
•
•

Low cost 8-bit microcontroller
Fully static CMOS
1 fLs instruction time
Low current drain
Low current static HALT mode (Typically < 1 fLA)
• Single supply operation: 2.5 to 6.0V
• 4096 bytes ROM/128 Bytes RAM

• 16-bit readlwrite timer operates in a variety of modes
- Timer with 16-bit auto reload register
- 16-bit external event counter
- Timer with 16-bit capture register (selectable edge)
• Multi-source interrupt
- Reset master clear
- External interrupt with selectable edge
- Timer interrupt or capture interrupt
- Software interrupt
• 8-bit stack pointer (stack in RAM)
• Powerful instruction set, most instructions single byte
• BCD arithmetic instructions
• MICROWIRE PLUSTM serial 1/0
• 44 PLCC, 36 1/0 pins
• 40 DIP, 36 I/O pins
• 28 DIP and SO, 24 1/0 pins
• Software selectable I/O options (TRI-STATE®, pushpull, weak pull-up)
• Schmitt trigger inputs on Port G
• Temperature ranges: COP98XC/COP98XCH O·C to
70·C, COP88XC -40·C to +85·C, COP68XC -55·C
to + 125·C.
• Form factor emulation devices
• Fully supported by Metalink's development systems

Block Diagram
RESET

vee

GND

! ! !

II
nlln
PORT L

PORT 0

FIGURE 1

1-98

PORT G

PORT I

PORT

e
TLlDD/10B02-1

COP980C/COP981 C

"C
0)

Total Current out of GND Pin (Sink)

7V
-0.3V to Vee + 0.3V ,

Total Current into Vee Pin (Source)

50mA

Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

DC Electrical Characteristics COP980XC; o·c : ;: TA ::;:
Parameter
Operating Voltage
98XC
98XCH
Power Supply Ripple (Note 1)
Supply Current
CKI = 10 MHz
CKI = 4 MHz
CKI = 4 MHz
CKI = 1 MHz
(Note 2)
HALT Current
(Note 3)

Condition

Typ

"C
0)

00
...A.

o........
o
o

"C
00
00

+ 70·C unless otherwise specified
Min

Max

Units

4.0
6.0
0.1 Vee

V
'V
V

6.0
4.4
2.2
1.4

rnA
rnA
rnA
rnA

8
5

J.LA
J.LA

o
........

2.3
4.0
Peak to Peak

o-a
00
CD

...A.

o
o

........
Vee
Vee
Vee
Vee

=
=
=
=

6V, tc = 1 J.Ls
6V, tc = 2.5 J.Ls
4.0V, tc = 2.5 J.Ls
4.0V, tc = 10 J.Ls

Vee = 6V, CKI = 0 MHz
Vee = 4.0V, CKI = 0 MHz

<0.7
<0.4

o'"U
co
00

o
........

o-a
co

Input Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current

60 rnA
- 65·C to + 140·C

Storage Temperature Range

o
........
o
o

...A.

0.1 Vee

V
V

0.2 Vee

V
V

+1.0
-250

J.LA

0.35 Vee

0.9 Vee

0.7 Vee
Vee
Vee

= 6.0V
= 6.0V, VIN

= OV

-1.0
-40

G Port Input Hysteresis

/LA

nlltnl
It ("
''' ... nnt I ,""".,,\1,...
_ _ .. ,.. .....
_ ..........................
ow

D Outputs'
Source
Sink
All Others
Source (Weak Pull-Up)
Source (push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage

3.8V
1.6V
1.0V
O.4V

-0.4
-0.2
10
2

VOH = 3.2V
VOH = 1.6V
VOH = 3.8V
VOH = 1.6V
VOL = O.4V
VOL = O.4V

-10
-2.5
-0.4
-0.2
1.6
0.7
-1.0

Vee
Vee
Vee
Vee

=
=
=
=

4.5V, VOH
2.3V, VOH
4.5V, VOL
2.3V, VOL

Vee
Vee
Vee
Vee
Vee
Vee
Vee

=
=
=
=
=

4.5V,
2.3V,
4.5V,
2.3V,
4.5V,
2.3V,
6.0V

=
=

=
=
=
=

Allowable Sink/Source
Current Per Pin
D Outputs (Sink)
All Others
Maximum Input Current (Note 4)
Without Latchup (Room Temp)

Room Temp

RAM Retention Voltage, Vr
(Note 5)

500 ns Rise and
Fall Time (Min)

rnA
rnA
rnA
rnA
-110
-33

rnA
+1.0

J.LA

15
3

rnA
rnA

±100

rnA

1000

2.0

Input Capacitance
Load Capacitance on D2

1-99

J.LA
J.LA
rnA

o
.....
co
C»

COP980C/COP981C

D..

o
o
......
o
c
co

C»

D..

o
......
o
.....
co
co

DC Electrical Characteristics (Continued)
Note 1: Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input. CKO open. inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee. L. C and G ports TRI-STATE
and tied to ground. all outputs low and tied to ground.
Note 4: Pins G6 and ~ are designed with a high voltage input network for factory testing. These pins allow input voltages greater than Vee and the pins will
have sink current to Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vecl. The effective
resistance to Vee is 7500 (typ). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: To maintain RAM integrity. the voltage must not be dropped or raised instantaneously.

D..

......
oc
co
co
D..

o
......
o
.....
co
CD

D..

o
......

co
CD

AC Electrical Characteristics O°C ~ TA ~ + 70°C unless otherwise specified

Vee ~ 4.0V
2.3V ~Vee ~ 4.0V
Vee ~ 4.0V
2.3V :S: Vee :S: 4.0V

CKI Clock Duty Cycle (Note 6)
Rise Time (Note 6)
Fall Time (Note 6)

fr
fr
fr

= Max
= 10 MHz Ext Clock
= 10 MHz Ext Clock

Max

Units

1
2.5
3
7.5

DC
DC
DC
DC

IJ-s
IJ-s
IJ-S
IJ-s

60
12

%
ns
ns

Min

Typ

Inputs

D..

tSETUP

tHOLO

Condition

Parameter
Instruction Cycle Time (tc)
Crystal/Resonator or External
(Div-by 10)
RIC Oscillator Mode
(Div-by 10)

Output Propagation Delay
tp01, tpoo
SO,SK
All Others

Vee ~ 4.0V
2.3V :S: Vee :S: 4.0V
Vee ~ 4.0V
2.3V :S: Vee :S: 4.0V
CL

ns
ns
ns
ns

200
500
60
150

= 100 pF, RL = 2.2 kn

Vee ~ 4.0V
2.3V:S: Vee :S: 4.0V
Vee ~ 4.0V
2.3V :S: Vee :S: 4.0V

0.7
1.75
1
2.5

ns
ns

20
56

MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output
Propagation Delay (tuPO)

220

Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

IJ-s
IJ-s
IJ-s
IJ-s

te
te

tc
te

Reset Pulse Width

1.0

Note 6: Parameter characterized but not production tested.

1-100

IJ-s

a"'tJ

COP880C/COP881 C

Q)
Q)

Total Current out of GNO Pin (Sink)
Storage Temperature Range

- 0.3V to Vee + 0.3V
50mA

DC Electrical Characteristics COP88XC; -40°C :5: TA :5:
Par.ameter
Operating Voltage
Power Supply Ripple (Note 1)
Supply Current
CKI = 10 MHz
CKI = 4 MHz
CKI = 4MHz
CKI = 1 MHz
(Note 2)
HALT Current
(Note 3)

Condition

+85°C unless otherwise specified
Min

Vee
Vee
Vee
Vee

=
=
=
=

Vee
Vee

= 6V, CKI = 0 MHz
= 3.5V, CKI = 0 MHz

Sink
All Others
Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage

Max
6.0
0.1 Vee

2.5

o
......
o

a"'tJ
Q)

Q)
.....

o
......
o

a"'tJ
Q)
Q)

Units
V
V·

o
......
o

a"'tJ
Q)
Q)

6V, tc = 1 P.s
6V, tc = 2.5 p.s
4.0V, tc = 2.5 p.s
4.0V, tc = 10 P.s

6.0
4.4
2.2
1.4

mA
mA
mA
mA

10
6

p.A
p.A

0.1 Vee

V
V

0.2 Vee

V
V

+2
-250

p.A
p.A

0.35 Vee

.....

o
......

a"'tJ
CD

<1
<0.5

0.9 Vee

0.7 Vee
Vee
Vee

= 6.0V
= 6.0V, VIN = OV

-2
-40

G Port Input Hysteresis
Output Current Levels
o Outputs
Source

Typ

Peak to Peak

Input Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current

- 65°C to + 140°C

Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

Total Current into Vee Pin (Source)

60mA

Vee =
Vee =
Vee =
Vee =

4.5V, VCH =
2.5V, VOH =
4.5V, VOL =
2.5V, VOL =

3.8V
1.8V
1.0V
O.4V

-0.'1

Vee = 4.5V, VOH = 3.2V
Vee = 2.5V, VOH = 1.8V
Vee = 4.5V, VOH = 3.8V
Vee = 2.5V, VOH = 1.8V
Vee = 4.5V, VOL = O.4V
Vee = 2.5V, VOL = O.4V
Vee = 6.0V

-10
-2.5
-0.4
-0.2
1.6
0.7·
-2.0

Maximum Input Current (Note 4)
Without Latchup (Room Temp)

Room Temp

RAM Retention Voltage, Vr
(Note 5)

500 ns Rise and
Fall Time (Min)

-110

-33

Load Capacitance on 02

1-101

p.A
p.A
mA
mA

+2.0

p.A

15
3

mA
mA

±100

1000

2.0

Input Capacitance

.....

m/\
mA
mA
mA

-0.2
10
2

Allowable Sink/Source
Current Per Pin
o Outputs (Sink)
All Others

o
......
o
a
"'tJ

o
,...

a..

o
......
o
o
CO

a..

o
......

o,...

co
co

a..

......
o
o

COP880C/COP881C
DC Electrical Characteristics (Continued)
Note 1: Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKllnput. CKO open. inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee. L. C and G ports TRI-STATE
and tied to ground. all outputs low and tied to ground.
Note 4: Pins G6 and m:m are designed with a high voltage input network for factory testing. These pins allow input voltages greater than Vee and the pins will
have sink current to Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vec>. The effective
resistance to Vee is 7500 (typ). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: To maintain RAM integrity. the voltage must not be dropped or raised Instantaneously.
AC Electrical

Characteristics-40°c ~ TA ~

Parameter

Vee ~ 4.5V
2.5V ~ Vee
Vee ~ 4.5V
2.5V ~ Vee

CKI Clock Duty Cycle (Note 6)
Rise Time (Note 6)
Fall Time (Note 6)

fr
fr
fr

Inputs

a..

o
......

o,...

co
CD

a..

o
......
CO
CD

tSETUP

a..

o
o

tHOLD·
Output Propagation Delay
tpD1,tpDO
·SO,SK
All Others

Min

Condition

Instruction Cycle Time (tc)
Crystal/Resonator or External
(Div-by 10)
R/C Oscillator Mode
(Div-by 10)

CO
CO

+ 85°C unless otherwise specified

=
=
=

1
2.5

< 4.5V

7.5
40

Max
10 MHz Ext Clock
10 MHz Ext Clock

Vee ~ 4.5V
2.5V ~ Vee
Vee ~ 4.5V
2.5V ~ Vee
CL

< 4.5V

Typ

< 4.5V
< 4.5V

Max

Units

DC
DC
DC
DC

!-,-S

60
12
8

%
ns
ns

ns
ns
ns
ns

200
500
60
150

0.7
1.75
1
2.5

< 4.5V
< 4.5V
20
56

MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output
Propagation Delay (tUPD)
Input Pulse Width
.. Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

te
te
te
te

Reset Pulse Width

1.0

Timing Diagram

~
!:=i·t
tuwh

UPD

)C
TL/DD/10B02-2

FIGURE 2. MICROWIRE/PLUS Timing
1-102

!-,-S
!-,-S
!-,-S

!-,-S

Note 6: Parameter characterized but not production tested.

!-,-S

ns
ns
220

!-,-S

100 pF, RL = 2.2 kO

Vee ~ 4.5V
2.5V ~ Vee
Vee ~ 4.5V
2.5V ~ Vee

!-,-S

a"'C

COP680C/COP681 C

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
6V
Supply Voltage (Vee>
Voltage at Any Pin
-0.3V to Vee + 0.3V
Total Current into Vee Pin (Source)
40 rnA

Total Current Out of GND Pin (Sink)

Storage Temperature Range
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

DC Electrical Characteristics COP68XC: -55°C
Parameter
Operating Voltage
Power Supply Ripple (Note 1)
Supply Current (Note 2)
CKI = 10 MHz
CKI = 4MHz
HALT Current (Note 3)

Condition

Min
4.5

Peak to Peak

o
'"
a
"'C
0)

......

o
'"
a
0)
0)

Max

Units

5.5
0.1 Vee

V
V

o
o
'"

a"'C
0)
0)

Vee
Vee
Vee

= 5.5V, tc = 1 ,..,s
= 5.5V, tc = 2.5,..,s
= 5.5V, CKI = 0 MHz

<10

B.O
4.4
30

rnA
rnA
,..,A

......

o
o
'"

a"'C
CD

0.1 Vee

V
V

0.2 Vee

V
V

+5
-300

,..,A
,..,A

0.35 Vee

0.9 Vee

0.7 Vee
Vee
Vee

= 5.5V
= 5.5V, VIN = OV

-5
-35

G Port Input Hysteresis
Output Current Levels
D Outputs
Source
Sink
All Uthers
Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage

Typ

"'C

~ TA ~ +125~Cunlessotherwisespecified

Input Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current

4BmA
- 65°C to + 140°C

= 4.5V, VOH = 3.BV
= 4.5V, VOL = 1.0V

-0.35
9

Vee = 4.5V, VOH = 3.2V
Vee = 4.5V, VOH = 3.2V
Vee = 4.5V, VOL = O.4V
Vee = 5.5V

-9
-0.35
1.4
-5.0

Vee
Vee

Allowable Sink/Source Current per Pin
D Outputs (Sink)
All Others
Maximum Input Current (Room Temp)
without Latchup (Note 4)

Room Temp

RAM Retention Voltage, Vr (Note 5)

500 ns Rise and Fall Time (Min)

Input Capacitance
Load Capacitance on D2

a"'C
CD

0)
......

rnA
rnA
-120

+5.0

,..,A
rnA
rnA
,..,A

12
2.5

rnA
rnA

±100

rnA

1000

2.5

Note 1: Rate of voltage change must be less than 0.5V1ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee. Land G ports TRI-STATE
and tied to ground, all outputs low and tied to ground.
Note 4: Pins G6 and RESET are designed with a high voltage input 'network for factory testing. These pins allow input voltages greater than Vee and the pins will
have sink current to Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vee). The effective
resistance to Vee is 7500 (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously.

1-103

o
o
'"

o
.....

co
en

COP680C/COP681C

AC Electrical Characteristics

o
......
oo

......

o
.....

co
co

......
oo
CO
CO
Q.

o
......

o.....
co

CD
Q.

o
......
o
o
CO

CD
Q.

Parameter
Instruction Cycle Time (tc)
Ext. or Crystal/Resonant
(Div-by 10)
CKI Clock Duty Cycle
(Note 6)
Rise Time (Note 6)
Fall Time (Note 6)

-55°C

+125°Cunlessotherwisespecified
Min'

Condition
Vee:;:;: 4.5V
fr = Max

Max

Units

,..,s

ns
ns

fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock

MICROWIRE Setup Tim~ (tuws)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Valid
Time (tUPD)

Typ

ns
ns

20
56
220

Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

te
tc
te
te

Reset Pulse Width

Note 6: Parameter characterized but not production tested.

o
o

1-104

,..,S

(')

Typical Performance Characteristics (-40·C ~ TA ~

a-a

+85·C)

Dynamlc-IOO (Crystal Clock Option)

Hall-IOO
0.35

0.3

..
.3
0

f'
....

0.25

0.2
0.15

...J

:z:

0.1

. ,.

,,"

,.~'

+85 0 C

..?:

()

........ ......... ~OOC

0.05

V ...

/ 4 t.4Hz , ":

~::.

.. ~:.:r/

....
,

Vee (V)

2.5

3.5

.....

Vee

'~,

Port L/C/G Push·Pull Sink Current

-:(

~ ..

,,
Il- "

,. '"

Vee

o Ij/
o

0.5

1.5

'20

VOL (V)

Vee

.......

-t-

-:(

= 4.5V

:I:

a-a

(0
C)

.....

(')

TLlDD/l0802-19

Port D Source Current

Vee = 6.0V

/11"
'/'
,~

(')

J .. -1".

(')

TLlDD/l0802-18

"(')

VOH (V)

.....

(')

3
VOH (V)

C)
C)

(0
C)

Vee =4.5V ~

.,....

o
o

O~~-~--~--~~-~

=6.0V

t---::: r---...vee =2.5VI' ,

a-a

I
Vee

I-

40
20 ~~ =2.5V -''''H---+--'\'ir'-l

NIN·I_ .... ~

6
TLlDD/l0802-17

,",

I '''~~~

5 5.5

.......

= 6.0V

=4.5 V '~"\r-+----I

I
WIN· .•••••'',!

(')

4.5

, : , Vee

I'- ..

C)
C)

(')

.~.,

WAX.

(')

a-a

' ,

100~-+-~~+--~-+-~

-:(

Port L/C/G Push·Pull Source Current

WAX- _ .....
'

Vee (V)

120 "'"""T--r---r--r---r--,

WIN. _....

(')

1 t.4Hz

TLlDD/l0802-16

Port L/C/G Weak Pull·Up
Source Current

.....

10 t.4Hz

",'

"(')

a-a

(')

I
I

2.5

r-::::

o
o

3.5

~ee

40
35

30
25

, "

~2-51

I I

ii"

10
1

.,.. ~ -

Vee

= 2.5V

o~
o

0.5

1 1.5

2 2.5 3 3.5 4 4.5
VOL (V)

1-105

,
TLlDD/l0802-21

~.
= 6.0V

Ve~ = 41.5V

Vee

'I" ,

Port D Sink Current
45

.~\
= 4.5V ,

VOH (V)

TL/DD/l0802-20

-:(

~', Vee = 6.0V

= 2.5V

.....

... .

TL/DD/l0802-22

o
.....
co

Connection Diagrams

D-

O
o
.......

Plastic Chip Carrier

o
o

(!)

ID
(!)

If)

(!)

"'"

(!)

..,
0

N
0

..,

(!)

(;

D-

o
.......

o.....

CKI

Vee

GO
RESET·

co
co
DO
o.......
oo
CO
CO

D-

O
o
.......

o.....
co

GNO

06
44 pin
PLCC

D-

o
.......
o
o
CO

:::i

..,

....I

o
Z

0
Z

"'"
....I

on
....I

ID
....I

"
....I

TLlDD/10B02-3

Top View
Order Number COP680C-XXX/V, COP880C-XXX/V, COP980C-XXX/V or COP980CH-XXX/V

D-

Dual-In-Llne Package (N)
and 28 Wide SO (WM)

Dual-In-Llne Package
C1

CKI

RESET

Vee

GNO

G4
G5

CKI

RESET

Vee

GNO

11
12

03
02
01

40 pin
,01P

28 pin
OIP/SO

L4
TL/DD/10B02-5

Top View
Order Number COP881C-XXXIN, COP981C-XXXIN,
COP881C-XXX/WM, COP981C-XXX/WM,
COP981CH-XXXIN or COP981CH-XXX/WM

TL/DD/10B02-4

Top View
Order Number COP680C-XXX/N, COP880C-XXX/N,
COP980C-XXXIN or COP980CH-XXXIN
FIGURE 3. Connection Diagrams

1-106

r---------------------------------------------------------------------------~

PORT 0 is an B-bit output port that is preset high when
RESET goes low. Care must be exercised with the 02 pin
operation. At RESET, the external loads on this pin must
ensure that the output voltages stay above 0.9 Vee to prevent the chip from entering special modes. Also, keep the
external loading on 02 to less than 1000 pF.

Functional Description

PORT I is an B-bit Hi-Z input port. The 2B-pin device does
not have a full complement of Port I pins. The unavailable
pins are not terminated i.e., they are floating. A read operation for these unterminated pins will return unpredictable
values. The user must ensure that the software takes this
into account by either masking or restricting the accesses to
bit operations. The unterminated Port I pins will draw power
only when addressed.

The ALU can do an B-bit addition, subtraction, logical or
shift operation in one cycle time.

PORT l is an B-bit I/O port.

There are five CPU registers:

PORT C is a 4-bit I/O port.

A is the B-bit Accumulator register

Three memory locations are allocated for the l, G and C
ports, one each for data register, configuration register and
the input pins. Reading bits 4-7 of the C-Configuration register, data register, and input pins returns undefined data.

PU is the upper 7 bits of the program counter (PC)
Pl is the lower B bits of the program counter (PC)
B is the B-bit address register, can be auto incremented or
decremented.

There are two registers associated with the land C ports: a
data register and a configuration register. Therefore, each l
and C I/O bit can be individually configured under software
control as shown below:
Data

Ports Land C Setup

0
0
1
1

0
1
0
1

Hi-Z Input (TRI-STATE Output)
Input with Pull-Up (Weak One Output)
Push-Pull Zero Output
Push-Pull One Output

"tJ

(X)
<:)

o
o
'"
o

"tJ

RESET is the master reset input. See Reset description.

Conflg.

X is the B-bit alternate address register, can be incremented
or decremented.
SP is the B-bit stack pointer, points to subroutine stack (in
RAM).
B, X and SP registers are mapped into the on chip RAM.
The B and X registers are used to address the on chip RAM.
The SP register is used to address the stack in RAM during
subroutine calls and returns.

...
o
m

(X)

o
'"
o
"tJ
(X)
(X)

<:)

o
'"
o
"tJ

...
o
(X)
(X)

o
'"
o

"tJ

co
(X)

<:)

o
'"
o

"tJ

...oco
(X)

PROGRAM MEMORY

On the 2B-pin part, it is recommended that all bits of Port C
be configured as outputs.

Program memory consists of 4096 bytes of ROM. These
bytes may hold program instructions or constant data. The
program memory is addressed by the 15-bit program counter (PC). ROM can be indirectly read by the LAID instruction
for table lookup.

PORT G is an B-bit port with 6 I/O pins (GO-G5) and 2 input
pins (G6, G7). All eight G-pins have Schmitt Triggers on the
inputs.
There fire two rA!:!i~tpr~ may be decreased down to Vr (minimum RAM retention voltage) without altering the state of the machine.
There are two ways to exit the HALT mode: via the RESET
or by the CKO pin. A low on the RESET line reinitializes the
microcontroller and starts executing from the address

1-109

o
.....

Functional Description

(Continued)

......

o
o

EXTERNAL
INT. PIN

o......
co
co

a.
o
o
......
o

SOFTWARE
INTERRUPT----------------'
TLlDD/l0B02-B'

FIGURE 6. Interrupt Block Diagram

DETECTION OF ILLEGAL CONDITIONS

a.
o
o
......

The device contains a hardware mechanism that allows it to
detect illegal conditions which may occur from coding er~
rers, noise and 'brown out' voltage drop situations. Specifically it detects cases of executing out of undefined ROM
area and unbalanced stack situations.

CO
CO

o.....
co
CD

a.
o
o
......
o
o
CO
CD

a.
o
o

TO
INTERRUPT
LOGIC

TIMER
UNDERFLOW - - - - - I

o
.....

TABLE III

Reading an undefined ROM location returns 00 (hexadeci~
mal) as its contents. The opcode for a software interrupt is
also '00'. Thus a program accessing undefined ROM will
cause a software interrupt.

SL1

SLO

SK Cycle Time

0
0
1

0
1

2te
4te
8te

where,
te is the instruction cycle clock.
MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the MICROWIRE/PlUS arrangement to start shifting the data. It
gets reset when eight data bits have been shifted. The user
may reset the BUSY bit by software to allow less than 8 bits
to shift. The devoce may. enter the MICROWIRE/PlUS
mode either as a Master or as a Slave. Figure 8 shows how
two COP880C microcontrollers and several peripherals may
be interconnected using the MICROWIRE/PlUS arrangement.

MICROWIRE/PLUSTM

Master MICROWIRE/PLUS Operation

MICROWIRE/PlUS is a serial synchronous bidirectional
communications interface. The MICROWIRE/PlUS capability enables the device to interface with any of National
Semiconductor's MICROWIRE peripherals (Le. AID converters, display drivers, EEPROMS, etc.) and with other microcontrollers which support the MICROWIRE/PlUS interface. It consists of an a-bit serial shift register (SIO) with
serial data input (SI), serial data output (SO) and serial shift
clock (SK). Figure 7 shows the block diagram of the MICRO.
WIRE/PLUS interface.

In the MICROWIRE/PlUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIREI
PLUS Master always initiates all data exchanges. (See Figure 8). The MSEl bit in the CNTRL register must be set to
enable the SO and SK functions 'onto the G Port. The SO
and SK pins must also be selected as outputs by setting
appropriate bits in the Port G configuration register. Table IV
summarizes the bit settings required. for Master mode of
operation.

The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIRE/
PLUS interface with the internal clock source is called the
Master mode of operation. Similarly, operating the MICROWIRE/pLus interface with an external shift clock is called
the Slave mode of operation.

SLAVE MICROWIRE/PLUS OPERATION
In the MICROWIRE/PlUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEl
bit in the CNTRl register enables the SO andSK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by appropriately
setting up the Port G configuration register. Table IV summarizes the settings required to enter' the Slave mode. of
operation.

The CNTRl register is used to configure and control the
MICROWIRE/PlUS mode. To use the MICROWIRE/PlUS ,
the MSEl bit in the CNTRl register is set to one. The SK
clock rate is selected by the two bits, SlO and Sl1, in the
CNTRl register. Table III details the different clock rates
that may be selected.

1-110

o
o

Functional Description (Continued)

"'C

TABLE IV
G4

Conflg. Conflg.

MODE 1. TIMER WITH AUTO-LOAD REGISTER

Fun.

In this mode of operation, the timer T1 counts down at the
instruction cycle rate. Upon underflow the value in the register R1 gets automatically reloaded into the timer which continues to count down. The timer underflow can be programmed to interrupt the microcontroller. A bit in the control
register CNTRl enables the TID (G3) pin to toggle upon
timer underflows. This allow the generation of square-wave
outputs or pulse width modulated outputs under software
control. (See Figure 9.)

Operation

Bit

In!. SK

MICROWIRE Master

TRI·STATE

In!.SK

MICROWIRE Master

Ext. SK

MICROWIRE Slave

TRI·STATE Ext. SK

MICROWIRE Slave

The device has a powerful 16·bit timer with an associated
16-bit register enabling them to perform extensive timer
functions. The timer T1 and its register R1 are each organized as two a-bit read/write registers. Control bits in the
register CNTRl allow the timer to be started and stopped
under software control. The timer-register pair can be operated in one of three possible modes. Table V details various
timer operating modes and their requisite control settings.

MODE 3. TIMER WITH CAPTURE REGISTER
Timer T1 can be used to precisely measure external frequencies or events in this mode of operation. The timer T1
counts down at the instruction cycle rate. Upon the occurrence of a specified edge on the TID pin the contents of the
timer T1 are copied into the register R1. Bits in the control
register CNTRl allow the trigger edge to be specified either
as a positive edge or as a negative edge. In this mode the
user can elect to be interrupted on the specified trigger
edge. (See Figure 10.)

r----.SO

4
1~/A,-o

8 - BIT 510 11+-----51

--,i I~SHIFT
CLOCK

___

'oj

-.f

~~~E~~

o
.......

o"'C
en

co
.....

o
.......
o
o
"'C

co
co
o

MODE 2. EXTERNAL COUNTER
TIMER/COUNTER

en
co

o
.......
o
o
"'C

co
.....

o
.......
o

o"'C
CD

co
o

o
o

.......

"'C
CD

co
.....

A
\ . , - - - . ,yJ>I,IL
'-

CNTRL

'oj

TLlDD/10802-9

FIGURE 7. MICROWIRE/PLUS Block Diagram

CHIP SELECT LINES

CS'

DIGITAL
Pll

LCD
DISPLAY
DRIVER
COP472-3

I/o
LINES

¢;

I/o
B - BIT
A/D CONVERTER
COP43X

COP

BBOC
(MASTER)

DO
SI ....

DI ClK

EEPROM

DI ClK

COP
B80C
(SLAVE)

DI ClK

SK
TL/DD/10802-10

FIGURE 8. MICROWIRE/PLUS Application

1-111

o
,...
co

Functional Description

o.......

TABLE V. Timer Operating Modes

o
o

CNTRl
Bits

765

.......

o
,...
co
co

o
.......
o
o

(Continued)

000
001
010
01 1
100
1 01
110
111

Operation Mode

T Interrupt

Timer
Counts
On

External Counter WI Auto-Load Reg.
External Counter WI Auto-Load Reg.
Not Allowed
Not Allowed
Timer WI Auto-Load Reg.
Timer WI Auto-Load Reg.lToggle TID Out
TimerW/Capture Register
Timer WICapture Register

Timer Underflow
Timer Underflow
Not Allowed
Not Allowed
Timer Underflow
Timer Underflow
TID Pos. Edge
TID Neg. Edge

TID Pos. Edge
TID Neg. Edge
Not Allowed
Not Allowed
tc
tc
tc
tc

CO
CO

TIMER PWM APPLICATION

o
.......

Figure 11 shows how a minimal component DI A converter
can be built out of the Timer-Register pair in the Auto-Reload mode. The timer is placed in the "Timer with auto reload" mode and the TID pin is selected as the timer output.
At the outset the TID pin is set high, the timer T1 holds the
on time and the register R1 holds the signal off time. Setting
TRUN bit starts the timer which counts down at the instruction cycle rate. The underflow toggles the TID output and
copies the off time into the timer, which continues to run. By
alternately loading in the on time and the off time at each
successive interrupt a PWM frequency can be easily generated.

o,...
co

o
.......
o
o

TIO
OUTPUT

TL/DD/10802-11

FIGURE 9. Timer/Counter Auto
Reload Mode Block Diagram

TID INPUT

TL/DD/10802-13
TL/DD/10802-12

FIGURE 11. Timer Application

FIGURE 10. Timer Capture Mode Block Diagram

1-112

(')

The Timer and MICROWIRE/PLUS control register contains
the following bits:
SL 1 & SLO Select the MICROWIRE/PLUS clock divide-by
External interrupt edge polarity select
(0 = rising edge, 1 = falling edge)
MSEL

Enable MICROWIRE/PLUS functions SO and
Start/Stop the Timer/Counter (1
stop)

run, 0

Address

TC3

Timer input edge polarity select (0 = rising
edge, 1 = falling edge)

TC2

Selects the capture mode

TC1

Selects the timer mode

I TC1 I TC21 TC31 TRUN I MSEL IIEDG I SL1 I
BIT7

80to BF Expansion Space for future use
CO to CF Expansion Space for I/O and Registers
BITO

PSW REGISTER (ADDRESS X'OOEF)

The PSW register contains the following select bits:
GIE

Global interrupt enable

EN I

External interrupt enable

BUSY MICROWIRE/PLUS busy shifting
IPND

External interrupt pending

ENTI

Timer interrupt enable

TPND Timer interrupt pending
C

Carry Flag

Half carry Flag

Contents

00 t06F On Chip RAM Bytes
70 to 7F Unused RAM Address Space (Reads as all Ones)

SLO

I HC

I C I TPND I ENTI IIPND I BUSY I ENI I GIE

Bit7

BitO

Addressing Modes
REGISTER INDIRECT

This is the "normal" mode of addressing. The operand is
the memory addressed by the B register or X register.
DIRECT

The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
IMMEDIATE

The instruction contains an 8-bit immediate field as the operand.
REGISTER INDIRECT
(AUTO INCREMENT AND DECREMENT)

DO to DF
DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD-DF

On Chip I/O and Registers
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port D Data Register
Reserved for Port D

EO to EF
EO-E7
E8
E9
EA
EB
EC
ED
EE
EF

On Chip Functions and Registers
Reserved for Future Parts
Reserved
MICROWIRF./PI.US Shift Ri'lQi'3ti'lr
Timer Lower Byte
Timer Upper Byte
Timer Autoload Register Lower Byte
Timer Autoload Register Upper Byte
CNTRL Control Register
PSW Register

FO to FF
FC
FD
FE

On Chip RAM Mapped as Registers
X Register
SP Register
B Register

Reading unused memory locations below 7FH will return all
ones. Reading other unused memory locations will return
undefined data.

This is a register indirect mode that automatically increments or decrements the B or X register after executing the
instruction.

1-113

(')

"(')

"'0
0)
C)

(')

All RAM, ports and registers (except A and PC) are mapped
into data memory address space.

0)
C)

....A.

Memory Map

SK
TRUN

"'0

This mode is used for the JP instruction, the instruction field
is added to the program counter to get the new program
location. J P has a range of from - 31 to + 32 to allow a one
byte relative jump (JP + 1 is implemented by a NOP instruction). There are no 'pages' when using JP, all 15 bits of PC
are used.

CNTRl REGISTER (ADDRESS X'OOEE)

IEDG

RELATIVE

Control Registers

(')

o"'0
C)
C)

(')

o"'0
C)
C)
....A.

(')

"(')

"'0

co
C)
o

(')

o"'0
co
C)
....A.

(')

co
0)
D-

o
.......

D-

o.......
o

co
co
DO

o.......
o
o

Instruction Set
REGISTER AND SYMBOL DEFINITIONS
Registers
A
a-bit Accumulator register
B
a-bit Address register
X
8-bit Address register
SP
a-bit Stack pointer register
PC
15-bit Program counter register
PU
upper 7 bits of PC
PL
lower 8 bits of PC
C
1-bit of PSW register for carry
HC
Half Carry
GIE
1-bit of PSW register for global interrupt enable

CO
CO

D-

O
o
.......

Symbols
[B)
Memory indirectly addressed by B register
[X]
Memory indkectly addressed by X register
Mem Direct address memory or [B)
Meml Direct address memory or [B) or Immediate data
8-bit Immediate data
Imm
Reg
Register memory: addresses FO to FF (Includes B, X
and SP)
Bit
Bit number (0 to 7)
~,
Loaded with
~
Exchanged with
Instruction Set

ADD
ADC

add
add with carry

SUBC

subtract with carry

AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT

Logical AND
Logical OR
Logical Exclusive-OR
IF equal
IF greater than
IF B not equal
Decrement Reg. ,skip if zero
Set bit

RBIT

Resetbit '

IFBIT

If bit

X
LOA
LDmem
LDReg

Exchange A with memory
Load A with memory
Load Direct memory Immed.
Load Register memory Immed.

X
X
LOA
LOA
LDM

Exchange A with memory [B)
Exchange A with memory [X)
Load A with memory [B)
Load A with memory [X)
Load Memory Immediate

(B B±1)
(X X±1)
(B B±1)
A [B)
(X X±1)
A [X]
[B) Imm(B B±1)

CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC'
IFNC

Clear A
IncrementA
Decrement A
Load A indirect from ROM
DECIMAL CORRECT A
ROTATE A RIGHT THRU C
Swap nibbles of A
SetC
ResetC
IfC
IfnotC

A-O
A A+1
A A-1
A ROM(PU,A)
A BCD correction (follows ADC, SUBC)

JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

Jump absolute long
Jump absolute
Jump relative short
Jump subroutine long
Jump subroutine
Jump indirect
Return from subroutine
Return and Skip
Return from InterruptGenerate an interrupt
No operation

PC ii (ii = 15 bits, 0 to 32k)
PC11 .. 0 i(i = 12 bits)
PC PC+r(ris-31to+32,not1)
[SP) PL,[SP-1) PU,SP-2,PC ii
[SP] PL,[SP-1) PU,SP-2,PC11.. 0 i
PL ROM(PU,A)
SP+2,PL [SP)'PU [SP-1]
SP + 2,PL [SP),PU [SP-1),Skip next instruction
SP+2,PL [SP),PU [SP-1),GIE 1
[SP) Pl,[SP-1) PU,SP-2,PC OFF
PC PC + 1

A A + Meml
A A + Meml ,+ C, C Carry
HC Half Carry
A A + Meml +C,C Carry
HC Half Carry
A AandMeml
A AorMeml
A AxorMeml
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B
Imm
Reg Reg - 1, skip if Reg goes to 0
1 tobit,
Mem (bit= 0 to 7 immediate)
Otobit,
Mem
If bit,
Mem is true, do next instr.

D-

O
o
.......

D-

A Mem
'A Meml
Mem Imm
Reg Imm
A-[B)
A-[X)

C A7 ... AO C
A7 ... A4 A3 ... AO
C 1,HC 1
C O,HC 0
If C is true, do next instruction
If C is not true, do next instruction

1-114

Bits 7-4
F

JP -15

JP -31

LD OFO,#i

DRSZOFO

RRCA

ADCA,
#i

ADCA,
[B]

IFBIT
O,[B]

JP -14

JP-30

LD OF1,#i

DRSZOF1

SUBCA,
#i

SUBC
A,[B]

IFBIT
1,[B]

*
JP -13
JP -12
JP -11

JP-29
JP-28
JP-27

LDOF2,#i
LDOF3,#i
LDOF4,#i

DRSZOF2
DRSZOF3

JP-26

LDOF5,#i

DRSZOF6

JP-B

JP-24

LDOF7,#i

DRSZOF7

JP-7
JP-6

JP-23
JP-22

LD OFB,#i
LD OF9,#i

DRSZOFB

LD B, OF

IFBNEO

JSR
OOOO-OOFF

JMP
OOOO-OOFF

JP + 17

INTR

0 C
m
r-

LD B, OE

IFBNE 1

JSR
01 00-01 FF

JMP
0100-01FF

JP + 1B

JP + 2

1 -I

LD B, OD

IFBNE2

JSR
0200-02FF

JMP
0200-02FF

JP + 19

JP + 3

LD B, OC

IFBNE3

JSR
0300-03FF

JMP
0300-03FF

JP + 20

JP + 4

IFEQ
A,[B]

IFBIT
2,[B]

XA,
[X-]

XA,
[B-]

IFGTA,
#i

IFGT
A,[B]

IFBIT
3,[B]

LAID

ADDA,
#i

ADD
A,[B]

IFBIT
4,[B]

CLRA

LD B,OB

IFBNE4

JSR
0400-04FF

JMP
0400-04FF

JP + 21

JP + 5

JID

ANDA,
#i

AND
A,[B]

IFBIT
5,[B]

SWAPA

LD B,OA

IFBNE5

JSR
0500-05FF

JMP
0500-05FF

JP + 22

JP + 6

XA,
[X]

XA,
[B]

XORA,
#i

XOR
A,[B]

IFBIT
6,[B]

DCORA

LDB,9

IFBNE6

JSR
0600-06FF

JMP
0600-06FF

JP + 23

JP + 7

OR
A,[B]

IFBIT
7,[B]

IFBNE7

JSR
0700-07FF

JMP
0700-07FF

JP + 24

JP + 8

ORA,
#i

LDB,B

*
LDOF6,#i

IFEQA,
#i

DRSZOF5

JP-25

XA,
[B+]

DRSZOF4

JP -9

XA,
[X+]

*
JP -10

NOP

LDA,
#i

DRSZOF9

IFC

SBIT
O,[B]

RBIT
O,[B]

LDB,7

IFNC

SBIT
1,[B]

RBIT
1,[B]

LDB,6

IFBNEB

en
JP + 9

JSR
OBOO-OBFF

JMP
OBOO-OBFF

JP + 25

IFBNE9

JSR
0900-09FF

JMP
0900-09FF

JP + 26

JP + 10

JP -21

LDOFA,#i

DRSZ OFA

LDA,
[X+]

LDA,
[B+]

LD
[B+ l,#i

INCA

SBIT
2,[B]

RBIT
2,[B]

LDB,5

IFBNEOA

JSR
OAOO-OAFF

JMP
OAOO-OAFF

JP + 27

JP + 11

JP-4

JP-20

LDOFB,#i

DRSZOFB

LDA,
[X-]

LDA,
[B-]

LD
[B-l,#i

DECA

SBIT
3,[B]

RBIT
3,[B]

LDB,4

IFBNEOB

JSR
OBOO-OBFF

JMP
OBOO-OBFF

JP + 2B

JP + 12

JP -3

JP -19

LDOFC,#i

DRSZOFC

LDMd,
#i

JMPL

XA,Md

SBIT
4,[B]

RBIT
4,[B]

LDB,3

IFBNEOC

JSR
OCOO-OCFF

JMP
OCOO-OCFF

JP + 29

JP +13

JP-2

JP -1B

LDOFD,#i

DRSZOFD

DIR

JSRL

LDA,
Md

nETSK

SBIT
5,[B]

RBIT
5,[B]

LDB,2

IFBNEOD

JSR
ODOO-ODFF

JMP
ODOO-ODFF

JP + 30

JP +14

JP -1

JP -17

LD OFE,#i

DRSZOFE

LDA,
[X]

LDA,
[B]

LD
[Bl, #i

RET

SBIT
6, [B]

RBIT
6, [B]

LD B,1

IFBNEOE

JSR
OEOO-OEFF

JMP
OEOO-OEFF

JP + 31

JP +15

JP-O

JP -16

LD OFF,#1

DRSZOFF

RETI

JSR
OFOO-OFFF

JMP
OFOO-OFFF

JP + 32

JP + 16

RBIT
7,[B]

IFBNEOF

SBIT
7,[B]

LDB,O

*
where,

is the immediate data

Md is a directly addressed memory location

JP-5

(,,)

• is an unused opcode (see following table)

~ ~ 86dO~/~086dO~/~ ~ 88dO~/~088dO~/~ ~ 89dO~/~089dO~

o
,....

Instruction Execution Time

D..

Most instructions are single byte (with immediate addressing mode instruction taking two bytes).
Most single instructions take one cycle time to execute.
See the BYTES and CYCLES per INSTRUCTION table for
details.

0')

oo
.....
o
o

0')

D..

oo
.....
D..

o
.....
o
o

CO
CO
D..

o
o
.....
o,....

co
to

D..

oo
.....
o
o

The following table shows the number of bytes and cycles
for each instruction in the format of byte/cycle.

Arithmetic and Logic Instructions

o
,....
co
co

BYTES and CYCLES per
INSTRUCTION

ADD·
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ

Direct

Immed.

1/1
1/1

3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4

2/2
2/2

1/1

1/1
1/1
1/1
1/1
1/1

2/2

2/2
2/2
2/2
2/2
2/2

1/1

1/3

SBIT
RBIT
IFBIT

CO
to
D..

[B)

1/1
1/1
1/1

3/4
3/4
3/4

Memory Transfer Instructions

Register
Register Indirect
Indirect Direct Immed.
Auto Incr & Decr
[B) [X]
[B+, B-] [X+,X-]
XA,·
1/1 1/3
LOA,·
1/1 1/3
LDB,lmm
LDB,lmm
LDMem,lmm
2/2
LD Reg,lmm

2/3

1/2

2/2
1/1
2/3

1/2

1/3
1/3
(If B < 16)
(If B > 15)

3/3

2/2
2/3

• = > Memory location addressed by B or X or directly.

Instructions Using A & C
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC

Transfer of Control Instructions

1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1

JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

1-116

3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/7
1/1

(')

BYTES and CYCLES per
INSTRUCTION (Continued)

Development Support
IN·CIRCUIT EMULATOR
The MetaLink iceMASTERTM-COP8 Model 400 In-Circuit
Emulator for the COP8 family of microcontrollers features
high-performance operation, ease of use, and an extremely
flexible user-interface for maximum productivity. Interchangeable probe cards, which connect to the standard
common base, support the various configurations and packages of the COP8 family.

The following table shows the instructions assigned to unused opcodes. This table is for information only. The operations performed are subject to change without notice. Do
not use these opcodes.
Unused
Opcode

Instruction

60
61
62
63
67
8C
99
9F
A7
A8

NOP
NOP
NOP
NOP
NOP
RET
NOP
LD [Bl. #i
XA, [B]
NOP

Unused
Opcode

Instruction

A9
AF
B1
B4
B5
B7
B9
BF

NOP
LOA, [B]
C ~ HC
NOP
NOP
XA, [X]
NOP
LOA, [X]

The ice MASTER provides real-time, full-speed emulation up
to 10 MHz, 32 kbytes of emulation memory and 4k frames of
trace buffer memory. The user may define as many as 32k
trace and break triggers which can be enabled, disabled, set
or cleared. They can be simple triggers based on code or
address ranges or complex triggers based on code address,
direct address, opcode value, opcode class or immediate
operand. Complex breakpoints can be ANDed and ORed
together. Trace information consists of address bus values,
opcodes and user selectable probe clips status (external
event lines). The trace buffer can be viewed as raw hex or
as disassembled instructions. The probe clip bit values can
be displayed in binary, hex or digital waveform formats.

Option List

The mask programmable options are listed out below. The
options are programmed at the same time as the ROM pattern to provide the user with hardware flexibility to use a
variety of oscillator configuration.

The iceMASTER's performance analyzer offers a resolution
of better than 6 JJ-s. The user can easily monitor the time
spent executing specific portions of code and find "hot
spots" or "dead code". Up to 15 independent memory areas based on code address or label ranges can be defined.
Analysis results can be viewed in bargraph format or as
actual frequency count.

OPTION 1: CKIINPUT
= 1 Crystal

(CK1/1 0) CKO for crystal configuration

= 2 External (CKI/10) CKO available as G7

input
= 3 RIC

(CKI/10) CKO available as G7
input

"'tJ

co
o

(')

......
(')

"'tJ
0)

co
.....

(')

......
(')

o"'tJ
co
co
o

(')

......
(')

"'tJ

co
co

.....

(')

......
(')

o"'tJ
(Q

co
o

(')

......
(')

"'tJ
(Q

co
.....

(')

OPTION 2: BONDING
= 1 44-Pin PLCC
= 2 40-Pin DIP
= 3 28-Pin SO
= 4 28-Pin DIP

The ice MASTER comes with an easy-to-use windowed interface. Each window can be sized, highlighted, color-controlled, added, or removed completely. Commands can be
accessed via pull-down menus and lor redefinable hot keys.
A context sensitive hypertextlhyperlinked on-line help system explains clearly the options the user has from within
any window.

The following option information is to be sent to National
along with the EPROM.
Option Data
Option 1 Value_is: CKI Input
Option 2 Value_is: COP Bonding

The iceMASTER connects easily to a PC via the standard
COMM port and its 115.2 kBaud serial link keeps typical
program download time to under 3 seconds.

1-117

The following tables list the emulator and probe cards ordering information.

Emulator Ordering Information

o
o

Part Number

.....
o
o

MetaLink base unit in-circuit emulator for all COP8 devices, symbolic
debugger software and RS232 serial interface cable, with 11 OV @ SO
Hz Power Supply

IM-COP8/400/2:j:

Metalink base unit in-current emulator for all COP8 devices, symbolic
debugger software and RS232 serial interface cable, with 220V @ 50
Hz Power Supply.

DM-COP8/880C:j:

Metalink IceMASTER Debug Module. This is the low cost version of
Metalink's IceMASTER. Firmware: Ver. S.07.

o
.....

Current Version

Description

IM-COP8/400/1:j:

HOST SOFTWARE: VER, 3.3 REV. 5,
Model File Rev 3.050 .

oo
.....
o
o

CO
CO

.....
o

:1=

These parts include National's COP8 Assembler/Linker/Librarian Package (COP8/DEV·IBMA)

Probe Card Ordering Information

MACRO CROSS ASSEMBLER
National Semiconductor offers a COP8 macro cross assembler. It runs on industry standard compatible PCs and supports all of the full-symbolic debugging features of the
MetaLink iceMASTER emulators.

Part
Number

Package

Voltage
Range

MHW·880C28DSPC

28 DIP

4.5V-5.5V

COP820C,
840C,
881C,
8781C

MHW·880C28DWPC

28 DIP

2.5V-S.OV

COP820C,
840C,
881C,
8781C

MHW-880C40D5PC

40 DIP

4,SV-5.5V

COP880C,
8780C

MHW·880C40DWPC

40DIP

2.5V-S.OV

COP880C,
8780C

MHW·880C44DSPC

44PLCC

4.5V-5.5V

COP880C,
8780C

MHW-880C44DWPC

44PLCC

2.5V-S.OV

COP880C,
8780C

CO
U)

o
.....
o
o
CO

Assembler Ordering Information
Part Number
COP8·DEV·IBMA

Description
COP8 Assembler/
Linker/Librarian for
IBM®, PC/XT®,
AT® or compatible.

Manual
42441 ~S32-001

1-118

Emulates

Development Support (Continued)
SINGLE-CHIP EMULATOR DEVICE

For more detailed information, refer to the emulation device
specific data sheets and the emulator selection table below.

The COP8 family is fully supported by single chip form, fit
and function emulators. The emulators are available as UV
erasable or one Time Programmable (OTP).

(

(
"1
C
C

Single-Chip Emulator Selection Table

.....

Device Number

Clock Option

Package

Description

Emulates

COP8780CV

Programmable

44 PLCC

One-Time Programmable (OTP)

COP880C

COP8780CEL

Programmable

44 LDCC

UV Erasable

COP880C

Q)
Q)
<:)

COP8780CN

Programmable

40 DIP

OTP

COP880C

(')

COP8780CJ

Programmable

40 DIP

UV Erasable

COP880C

COP8781CN

Programmable

28 DIP

OTP

COP881C

o
."

COP8781CJ

Programmable

28DIP

UV Erasable

COP881C

COP8781CWM

Programmable

28 SO

OTP

COP881C

PROGRAMMING SUPPORT

C':

o-0

.......
(')

Q)
Q)

..A.

(')

.......
(')

o."
co

Q)
<:)

Programming of the single-chip emulator devices is support·
ed by different sources. The following programmers are certified for programming the One Time Programmable (OTP)
devices:

(')

.......
(')

EPROM Programmer Information
Manufacturer
and Product

..A.

Asia Phono
Number

Europe Phone
Number

U.S. Phone
Number

Metalink-Debug Module

(602) 926-0797

Germany: +49-8141-1030

Hong Kong: I- 052·737-1000

Xeltek-Superpro

(408) 745·7974

Germany: +492041684758

Singaporo: I 652766433

BP Microsystems·EP·1140

(800) 225·2102

Germany: +49898576667

Hong Kong: I 0523000620

Data 1I0·Unisite;
-System 29,
·System 39

(800) 322·8246

Europe: + 31-20·622866
Germany: + 49-89-85-8020

Japan:

Abcom-COP8
Programmer
System General
Turpro·1·FX; -APRO

Europe:
(408) 263-6667

+33·432·60g 1

+ en 808707
Taiwan Taipei:

Switzerland: + 31-921-7844

\
1-119

+ 2-9173005

(')

Development Support (Continued)
If the user has a PC with a communications package then
files from the FILE SECTION can be down-loaded to disk for
later use.

DIAL-A-HELPER
Dial-A-Helper is a service provided by the Microcontroller
Applications Group. The Dial-A-Helper is an Electronic Bulletin Board information system.

)

3
:0

o
o
.....
o
o

co
co

o
o
.....

FACTORY APPLICATIONS SUPPORT
Dial-A-Helper also provides immediate factory applications
support. If a user has questions, he can leave messages on
our electronic bulletin board, which we will respond to.

INFORMATION SYSTEM
The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities can be found. The minimum requirement for accessing the Dial-A-Helper is a Hayes compatible
modem.

o,...
co

o
o
.....
o
o

co
CD

D-

\
1·120

Voice:

(800) 272-9959

Modem:

CANADA/U.S.:

(800) NSC-MICAO
(800) 672-6427

Baud:

14.4k

Setup:

Length: a-Bit
Parity:
None
Stop Bit: 1

Operation:

24 Hrs., 7 Days

a"'C
0)
Q)

/fJNational Semiconductor

COP684BC/COP884BC
Single-Chip microCMOS Microcontroller

a"'C

General Description

•

The COP684BC and COP884BC are members of the
COP888BC family of microcontrollers which uses an 8-bit
single chip core architecture fabricated with National Semiconductor's M2CMOSTM process technology. Each device
is a member of this expandable 8-bit core processor family
of microcontrollers.
(Continued)

Two 8-bit Register Indirect Data Memory Pointers
(B and X)

•
•
•
•

Versatile instruction set
True bit manipulation
Memory mapped I/O
BCD arithmetic instructions

Features
a
•
•
•
•
II

1:1
1:1

a
1:1
1:1

a
a
II

Low cost 8-bit microcontroller
Fully static CMOS, with low current drain
Two power saving modes: HALT and IDLE
1 }-ts instruction cycle time
2048 bytes on-board ROM
64 bytes on-board RAM
Single supply operation: 4.5V-5.5V
MICROWIRE/PLUSTM serial 1/0
Idle Timer
Multi-Input Wake Up (MIWU) with optional interrupts (7)
On chip reset
CAN Interface
2 comparators
High speed, constant resolution 8-bit PWM/frequency
monitor timer with 2 output pins
One 16-bit timer, with two 16-bit registers supporting:
- Processor Independent PWM mode
- External Event counter mode
- Input Capture mode
8-bit Stack Pointer SP (stack in RAM)

Q)
Q)
~

m
o

• Package:
- 28 SO with 18 general 1/0 pins
• Software selectableI/O options
- TRI-STATE® Output
- Push-Pull Output
- Weak Pull Up Input
- High Impedance Input
II Schmitt trigger inputs on ports G and L
• Temperature ranges:
- COP88xBC -40°C to +85°C,
- COP68xBC -55°C to + 125°C
II Single chip hybrid emulation device-COP884BCMH
g Real time emulation and full program debug offered by
MetaLink's Development Systems
a Eleven multi-source vectored interrupts servicing
- External Interrupt
- Idle Timer TO
- Timer T1 (with 2 Interrupts)
- MICROWIRE/PLUS
- Multi-Input Wake Up
- Software Trap
-PWM Timer
- CAN Interface (with 3 interrupts)

Block Diagram

II
CPU REGISTERS

TLIDD/12067-1

FIGURE 1

1-121

m
~

co
co
a..

.......

o
m
~

co
CD
a..

o
o

Dual-ln-L1ne Package

General Description (Continued)
It is a fully static part, fabricated using double-metal silicon
gate microCMOS technology. Features include an 8-bit
memory mapped architecture, MICROWIRE/PLUS serial
I/O, a 16-bit timer/counter supporting three modes (Processor Independent PWM generation, External Event counter,
and Input Capture mode capabilities), a CAN interface, two
comparators, 8-bit, high speed, constant resolution PWM/
frequency monitor timer, and two power savings modes
(HALT and IDLE), both with a multi-sourced wake up/ interrupt capability. This multi-sourced interrupt capability may
also be used independent of the HALT or IDLE modes.
Each I/O pin has software selectable configurations. The
device operates over a voltage range of 4.5V to 5.5V. High
throughput is achieved with an efficient, regular instruction
set operating at a maximum of 1 p.s per instruction rate. The
device has low EMI emissions. Low radiated emissions are
achieved by gradual turn-on output drivers and internal Icc
filters on the chip logic and crystal oscillator.

G4/S0- 1

28 f-G3/TIA

G5/SK- 2

27 ~G2/TIB

G6/SI- 3

23 f-GND

LO/CMP1IN+- 7
L I/CMP1IN- -

28 pin
SO

L2/CMP10UT- 9

Alt. Function

LO
L1
L2
L3
L4
L5
L6

I/O
I/O
I/O
I/O
I/O
I/O
I/O

DO
01
02
03

0
0
0
0

19
20
21
22

CAN VREF
CANTxO

18
15

CANTx1
CAN RxO
CAN Rx1

0
I
I

CMP11N + /MIWU
CMP11N -/MIWU
CMP1 OUT /MIWU
CMP21N -/MIWU
CMP21N + /MIWU
CMP2IN-/PWM1/MIWU
CMP20UT /PWMO/
CAPTIN/MIWU

25
26
27
28
1
2
3
4
7
8
9
10
11
12
13

17
16
6

Vcc
GNO

~Dl
~DO

L3/CMP2IN- -

L4/CMP2IN+ -

18 f-VREF

L5/CMP2IN- /PWM 1 -

17 f-RXO

L6"CMP20UT~_ 13
P MO/CAPTIN

~RXI

TX1- 14

~TXO

FIGURE 2

14
MIWU (Note A)
MIWU

21 f-D2
20

28-Lead (O.300 H Wide) Molded
Small Outline Package, JEDEC
Order Number COP884BC-xxx/WM or
COP684BC-xxx/WM
See NS Package Number M28B

28-Pln
SO

I/O
I/O
I/O
I/O
I/O
I/O
I
I

T1B
T1A
SO
SK
SI
CKO

22 f-D3

TLlDD/120B7-2

GO
G1
G2
G3
G4
G5
G6
G7

INTR

RESET

Top View

Pinouts for 28-Pln SO Package
Type

CKI- 5
Vcc -

Connection Diagram
Port
Pin

~Gl

25 ~GO/INT

G7/CKO- 4

CKI

RESET

Note A: The MIWU function for the CAN interface is internal (see CAN
interface block diagram)

1-122

Absolute Maximum Ratings

(Note)
If Military/Aerospace specified devices are required,
please contact the National .Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
Voltage at Any Pin
Total Current into Vee Pin (Source)

"'0

100mA
Total Current out of GND Pin (Sink)
-65°C to + 150°C
Storage Temperature Range
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

6V
- 0.3V to Vee + 0.3V
90mA

(X)

,flo,

m
o.......
o

o"'0
(X)
(X)

,flo,

DC Electrical Characteristics COP88xBC:
Parameter

Peak-to·Peak

Supply Current
CKI = 10 MHz (Note 2)

Vee

IDLE Current (Note 4)
CKI = 10 MHz

Vee

Typ

<300
<250

= 5.5V, to = 1 p's

Max

Units

5.5
0.1 Vee

V
V

480
380

p.A
p.A

5.5

0.2 Vee

V
V

0.2 Vee

V
V

±2
-250

p.A
p.A

O.S Vee

0.7 Vee

= 5.5V
= 5.5V, VIN = OV

G and L Port Input Hysteresis

(Note 6)
Vee

~.5\.J.

0.05 Vee

= 4.5V, VOH = 3.3V

'./cc ==

-40

'/UL

i .0'/

-0.4

lilA

Vee
Vee

= 4.5V, VOH = 3.3V
= 4.5V, VOL = 0.4V

1.6
-1.6

Vee
Vee
Vee
Vee

=
=
=
=

-10
-0.4
1.6

4.5V, VOH
4.5V, VOH
4.5V, VOL
5.5V

= 2.7V
= 3.3V
= O.4V

Allowable Sink/Source Current per Pin
D Outputs (Sink)
All Other
Maximum Input Current
without Latchup (Notes 5, 7)

m
o

+85°C

= 5.5V, te = 1 p.s

Vee
Vee

Comparator Output (L2, L6)
Source (Push·Pull)
Sink (Push· Pull)
All Others
Source (Weak Pull-Up)
Source (Push-Pull)
Sink (Push· Pull)
TRI·STATE Leakage

Vee = 5.5V, CKI = 0 MHz
Power·On Reset Enabled
Power-On Reset Disabled

Hi-Z Input Leakage
Input Pull·up Current

S:~~

4.5

Input Levels (VIH, VIU
Reset, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low

Output Current Levels D Outputs
Source

Min

Conditions

Operating Voltage
Power Supply Ripple (Note 1)

HALT Current (Notes 3, 4)

-40·C

' mA
mA
110

Room Temp

RAM Retention Voltage, Vr (Note 6)

500 ns Rise and Fall Time

Input Capacitance

(Note 7)

Load Capacitance on D2

±2.0

p.A
mA
mA
p.A

15
3

mA
rnA

±100

2.0

V
7

1000

Note 1: Maximum rate of voltage change must be less than 0.5 Vlms
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, Inputs at Vee or GND, and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the Crystal configurations. Halt test conditions: All inputs tied to Vee; L, and G port 1I0s configured as
outputs and programmed low; Doutputs programmed low. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. P,art will pull up CKI
during HALT in crystal clock mode.
Note 4: HALT and IDLE current specifications assume CAN block and comparators are disabled .

1·123

m
-.:t

co
co
O
o.......
D-

o
m
-.:t

D-

Absolute Maximum Ratings

(Note)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (Vee>
Voltage at Any Pin
Total Current into Vee Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range

Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

7V
-0.3V to Vee +0.3V
100mA
110 rnA
- 65°C to + 150°C

DC Electrical Characteristics COP68xBC:
Parameter

Conditions

Operating Voltage
Power Supply Ripple (Note 1)

Peak-to-Peak

Supply Current
CKI = 10 MHz (Note 2)

Vee = 5.5V, tc = 1 /Ls

HALT Current (Notes 3, 4)

IDLE Current (Note 4)
CKI = 10 MHz

-55°C ~ TA ~ +125°C
Typ

4.5

Vee = 5.5V, CKI = 0 MHz
Power-On Reset Enabled
Power-On Reset Disabled

<300
<250

Vee = 5.5V, tc = 1 /Ls

Input Levels (VIH' VIU
Reset, CKI
Logi'c High
Logic Low
All Other Inputs
Logic High
Logic Low

Max

Units

5.5
0.1 Vee

V
V

rnA

480
380

/LA
/LA

5.5

rnA

0.2 Vee

V
V

0.2Vcc

V
V

±5
-250

/LA
/LA

0.8 Vee

0.7 Vee

Hi-Z Input Leakage
Input Pull-up Current

Vee = 5.5V
Vee = 5.5V, VIN

G and L Port Input Hysteresis

(Note 6)

Output Current Levels D Outputs
Source
Sink
Comparator Output (L2, L6)
Source (Push-Pull)
Sink (Push-Pull)
All Others
Source (Weak Pull-Up)
Source (Push-Pull)
Sink (Push-Pull)
TRI-STATE Leakage

Min

= OV

-35

0.05 Vee

Vee
Vee

= 4.5V, VOH = 3.3V
= 4.5V, VOL = 1.0V

-0.4
9.0

rnA
rnA

Vee
Vee

= 4.5V, VOH = 3.3V
= 4.5V, VOL = O.4V

-1.6
1.6

mA
mA

Vee =
Vee =
Vee =
Vee =

4.5V, VOH
4.5V, VOH
4.5V, VOL
5.5V

= 2.7V
= 3.3V
= O.4V

-9.0
-0.4
1.4

Allowable Sink/Source Current per Pin
D Outputs (Sink)
All Other
Maximum Input Current
without Latchup (Notes 5, 7)

Room Temp

RAM Retention Voltage, Vr (Note 6)

500 ns Rise and Fall Time

Input Capacitance

(Note 7)

Load Capacitance on D2

-100

/LA

mA
mA
±5.0

/LA

12
2.5

mA
mA

±100

1000

2.0

Note 5: Pins G6 and ~ are designed with a high voltage input network. These pins allow input voltages greater than Vee and the pins will have sink current to
Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vee>. The effective resistance to Vee is 7500
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 6: Condition and parameter valid only for part in HALT mOde.
Note 7: Parameter characterized but not tested.
1-124

AC Electrical Characteristics: COP68xBCandCOP88xBC: -55°C::;; TA::;;
Parameter

Conditions

Instruction Cycle Time (te>
Crytal/Resonator

Min

Vee;:=: 4.5V

1.0

Vee;:=: 4.5V
Vee;:=: 4.5V

200
60

a"'0

+125°C

Typ

Max
DC

Units

IJ-s

Inputs
tSETUP
tHOLO
PWM Capture Input

ns
ns

m
o

o
......

a"'0
CD
CD

.a::.

o
Vee;:=: 4.5V
Vee;:=: 4.5V

tSETUP
tHOLO
Output Propagation Delay
(tp01, tpoo) (Note 8)
SK,SO
PWM Outputs
All Others

ns
ns

30
70

CL = 100 pF, RL
Vee;:=: 4.5V
Vee;:=: 4.5V
Vee;:=: 4.5V

2.2 kD.
0.7
75
1

MICROWIRE
Setup Time (tUWS) (Note 9)
Hold Time (tUWH) (Note 9)
Output Prop Delay (tuPO)

20
56
220

IJ-s
ns
IJ-s
ns
ns
ns

Input Pulse Width (Note 10)
Interrupt High Time
Interrupt Low Time
Timer 1,2 High Time
Timer 1,2 Low Time

1
1
1
1

te
te
te
te

Reset Pulse Width (Note 9)

1.0

IJ-s

Power Supply Rise Time for Proper
Operation of On-Chip RESET
Note: For device testing purposes of all

en
CD
.a::.

256*te

50 IJ-s

AC parameters, VOH will be tested at O.S·Vee.

Note 8: The output propagation is referenced to the end of the instruction cycle where the output change occurs.
Note 9: Parameter not tested.
Note 10:

= Instruction Cycle Time.

On-Chip Voltage Reference:
Parameter
Reference Voltage
VREF
Reference Supply Current,
100

-55°C::;; TA::;; +125°C

Min

Max

Units

0.5 Vee -0.12

0.5 Vee +0.12

120

IlA

Conditions
lOUT < 80 IJ-A,
Vee = 5V
lOUT = OA, (No Load)
Vee = 5V (Note A)

Note A: Reference supply 100 is supplied for information purposes only, it is not tested.

Comparator DCI AC Characteristics: 4.5V ::;; Vee::;; 5.5V, -55°C::;; T A ::;;
Parameter
Input Offset Voltage

Conditions
O.4V

Min

< VIN < Vee -1.5V

Input Common Mode Voltage Range

+ 125°C

Typ

Max

Units

±10

±25

Vee -1.5

0.4

Voltage Gain

·300k

Outputs Sink/Source

See I/O-Port DC Specifications

DC Supply Current (when enabled)

VCC

Response Time

TBD mV Step, TBD mV Overdrive,
100 pF Load

V/V

250

6.0V

1-125

Il A
Ils

~
CX)
CX)

AC Electrical Characteristics (Continued)
Port L has the following alternate features:
LO MIWU or CMP11N +
L1 MIWU or CMP1INL2 MIWU or CMP1 OUT
L3 MIWU or CMP2INL4 MIWU or CMP21N +
L5 MIWU or CMP2IN- or PWM1
L6 MIWU or CMP20UT or PWMO or CAPTIN

D..

~
CX)

D..

o
o

Port G is an 8~bit port with 5 1/0 pins (GO-G5), an input pin
(G6), and one dedicated output pin (G7). Pins GO-G6 all
have Schmitt Triggers on their inputs. G7 serves as the dedicated output pin for the CKO clock output. There are two
registers associated with the G Port, a data register and a
configuration register. Therefore, each of the 6 1/0 bits
(GO-G5) can be individually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin the associated bits in the data and configuration registers for G6 and G7 are used for special purpose
functions as outlined below. Reading the G6 and G7 data
bits will return zeroes.

TL/DD/12067-3

FIGURE 3. MICROWIRE/PLUS Timing Diagram

CKI~
tSETUP~ 1 +.. ~

_1---=:1 'HOLD

("PI~~"P"p"l) ~_____

, : =-=...EiX'

:IpDO,tPDl

PWMO& PWMI
(PWM outputs)

'-_ __

Vee and GND are the power supply pins.

Note that the chip will be placed in the HALT mode by writing a "1" to bit 7 of the Port G Data Register. Similarly the
chip will be placed in the IDLE mode by writing a "1" to bit 6
of the Port G Data Register.
Writing a "1" to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock.

CKI is the clock input. The clock can come from a crystal
oscillator (in conjunction with CKO). See Oscillator Description section.

TLlDD/12067-4

FIGURE 4. PWM/CAPTURE Timer
Input/Output Timing Diagram

Pin Descriptions

Config. Register

RESET is the master reset input. See Reset Description
section.

Data
Register

1
1

.. 0
1

HALT
Alternate SK

IDLE

CAN pins: For the on-chip CAN interface this device has five
dedicated pins with the following features:

The device contains one bidirectional 8-bit 1/0 port (G), and
one 7-bit bidirectional 1/0 port (L) where each individual bit
may be independently configured as an input (Schmitt trigger inputs on ports G and L), output or TRI-STATE under
program control.. Three data memory address locations are
allocated for each of these 1/0 ports. Each 1/0 port has two
associated 8-bit memory mapped registers, the CONFIGURATION register and the output DATA register. A memory
mapped address is also reserved for the input pins of each
110 port. (See the memory map for the various addresses
associated with the 110 ports.) Figure 5 shows the 1/0 port
configurations for the device. The DATA and CONFIGURATION registers allow for each port bit to be individually configured under software control as shown below:
Configuration
Register

Data Register

RxO

On-chip reference voltage with the value of Vee/2
CAN receive data input pin.

VREF

Rx1

CAN receive data input pin.

TxO

CAN transmit data output pin. This pin may be put in
the TRI-STATE mode with the TXENO bit in the
CAN Bus control register.

Tx1

CAN transmit data output pin. This pin may be put in
the TRI-STATE mode with the TXEN1 bit in the
CAN Bus control register.

Port G has the following alternate features:
GO INTR (External Interrupt Input)
, G2 T1 B (Timer T1 Capture Input)

Port Set-Up

G3 T1A (Timer T1 1/0)
G4 SO (MICROWIRE Serial Data Output)

Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Pu~h-Pull One Output

G5 SK (MICROWIRE Serial Clock)
G6 SI (MICROWIRE Serial Data Input)
Port G has the following dedicated function:
G7 CKO Oscillator dedicated output
Port D is a 4-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs (except D2) together in order to get a higher drive.

PORT L Is a 7-bit 110 port. All L-pins have Schmitt triggers
on the inputs.
Port L supports Multi-Input Wake Up (MIWU) on all seven
pins.

Note: Care must be exercised with the 02 pin operation. At RESET, the
external loads on this pin must ensure that the output voltages stay
above 0.8 vce to prevent the chip from entering special modes. Also
keep the external loading on 02 to less than 1000 pF.
1~126

Pin Descriptions

The device has 64 bytes of RAM. Sixteen bytes of RAM are
mapped as "registers" at addresses OFO to OFF Hex. These
registers can be loaded immediately, and also decremented
and tested with the DRSZ (decrement register and skip if
zero) instruction. The memory pointer registers X, SP, and B
are memory mapped into this space at address locations
OFC to OFE Hex respectively, with the other registers (other
than reserved register OFF) being available for general usage.

(Continued)

PORT LAND G

The instruction set permits. any bit in memory to be set,
reset or tested. All 1/0 and registers (except A and PC) are
memory mapped; therefore, 1/0 bits and register bits can be
directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.

"'CJ
0)

01::00

m
0
......
0

"'CJ

C)
C)

01::00

m
0

Note: RAM contents are undefined upon power-up.

PORT D

RESET

The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for Ports land G, are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Port 0 is
initialized high with RESET. The PC, PSW, CNTRl, and
ICNTRl control registers are cleared. The Multi-Input Wake
Up registers WKEN, WKEDG, and WKPND are cleared. The
Stack Pointer, SP, is initialized to 02F Hex.

TLlDD/12067-5

FIGURE 5. 1/0 Port Configurations

Functional Description
The architecture of the device utilizes a modified Harvard
architecture. With the Harvard architecture, the control store
program memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own separate addressing space with separate address buses. The
architecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.

The following initializations occur with RESET:
Port l: TRI-STATE
Port G: TRI-STATE

CPU REGISTERS

Port 0: HIGH

The CPU can do an a-bit addition, subtraction, logical or
shift operation in one instruction (tel cycle time.

PC: CLEARED
PSW, CNTRl and ICNTRl registers: CLEARED

There are five CPU registers:

Accumulator and Timer 1:

A is the 8-bit Accumulator Register

RANDOM after RESET with power already applied

PC is the 15-bit Program Counter Register

RANDOM after RESET at power-on

PU is the upper 7 bits of the program counter (PC)

SP (Stack Pointer): loaded with 2F Hex

Pl is the lower 8 bits of the program counter (PC)

CMPSl (Comparator control register): CLEARED

B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.

PWMCON (PWM control register): CLEARED
B and X Pointers:

X is an 8-bit alternate RAM address pOinter, which can be
optionally post auto incremented or decremented.

UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-up

SP is the 8-bit stack pointer, which points to the subroutinel
interrupt stack (in RAM). The SP is initialized to RAM address 02F with reset.

RAM:
UNAFFECTED after RESET with power already applied

All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).

RANDOM after RESET at power-up
CAN:

PROGRAM MEMORY

Program memory for the device consists of 2048 bytes of
ROM. These bytes may hold program instructions or constant data (data tables tor the LAID instruction, jump vectors
for the JID instruction, and interrupt vectors for the VIS instruction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the device vector to
program memory location OFF Hex.

The CAN Interface comes out of external reset in the
"error-active" state and waits until the user's software
sets either one or both of the TXENO, TXEN1 bits to
"1". After that, the device will not start transmission or
reception of a frame until eleven consecutive "recessive" (undriven) bits have been received. This is done to
ensure that the output drivers are not enabled during an
active message on the bus.

DATA MEMORY

CSCAl, CTIM, TCNTl, TEC, REC: CLEARED

The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data
and Pin), the control registers, the MICROWIRE/PlUS SIO
shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer).
Data memory is addressed directly by the instruction or indirectly by the B, X and SP pointers.

RTSTAT: CLEARED with the exception of the TBE bit
which is set to 1

RID, RIDl, TID, TDlC: RANDOM

•
1-127

m
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Functional Description

D..

ON-CHIP POWER-ON RESET

o
.....
o

The device is designed with an on-chip power-on reset circuit which will trigger a 256 te delay as Vcc rises above the
minimum RAM retention voltage (Vr). This delay allows the
oscillator to stabilize before the device exits the reset state.
The contents of data registers and RAM are unknown following an on-chip power-on reset. The external reset takes
priority over the on-chip reset and will deactivate the 256 te
delay if in progress.

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o
o

TABLE I. Crystal Oscillator Configuration, TA = 25°C

(Continued)

E
R
S
U

P
P
L

C1
(pF)

C2
(pF)

CKI Freq.
(MHz)

Conditions

30-36

VCC = 5V

30-36

VCC = 5V

200

100-150

0.455

VCC = 5V

Current Drain
The total current drain of the chip depends on:
1. Oscillator operation mode-11
2. Internal switching current-12
3. Internal leakage current-13
4. Output source current-14
5. DC current caused by external input not at Vcc or
GND-15
6. Comparator DC supply current when enabled-16

The on-Chip power-on reset circuit may reset the device if
the operating voltage (Vce) goes below Vr .

R2
(MO)

When using external reset, the external RC network shown
in Figure 6 should be used to ensure that the RESET pin is
held low until the power supply to the chip stabilizes.
Under no circumstances should the RESET pin be allowed
to float. If the on-chip power-on reset feature is being used,
RESET should be connected directly to Vcc. Be aware of
the Power Supply Rise Time requirements specified in the
DC Specifications Table. These requirements must be met
for the on-chip power-on reset to function properly.

p
0

R1
(kO)

7. VREF of CAN-17
8. Comparator of CAN block-18
9. On-chip Reset-19

..
fC

I
-

vee

Thus the total current drain, It, is given as

:~ R ~~D

It = 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19
To reduce the total current drain, each of the above components must be minimum.

RESET

The chip will draw more current as the CKI input frequency
increases up to the maximum 10 MHz value. Switching current, governed by the equation, can be reduced by lowering
voltage and frequency. Leakage current can be reduced by
lowering voltage and temperature. The other items can be
reduced by carefully designing the end-user's system.

GND
TLIDD/12067-6

RC > 5 x Power Supply Rise Time

FIGURE 6. Recommended Reset Circuit

12 = C * V * f
where C = equivalent capacitance of the chip
V = operating voltage
f = CKI frequency

Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7. The CKI input frequency is divided by 10
to produce the instruction cycle clock {1 ltd.

Control Registers
CNTRl Register (Address X'OOEE)

Figure 7 shows the Crystal diagram.

CKI

CKO

The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:

SL 1 & SLO Select the MICROWIRE/PLUS clock divide
by COO = 2, 01 = 4, 1x = 8)

TLIDD/12067-7

FIGURE 7. Crystal Oscillator Diagram
CRYSTAL OSCilLATOR
CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.

IEDG

External interrupt edge polarity select
(O = Rising edge, 1 = Falling edge)

MSEL

Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively

T1 CO

Timer T1 StartlStop control in timer
Timer T1 Underflow Interrupt Pending Flag in
timer mode 3

T1 C1

Timer T1 mode control bit

T1 C2

Timer T1 mode control bit

T1 C3

Timer T1 mode control bit

I T1C3 I T1C2 I T1C1
Bit7

Table I shows the component values required for various
standard crystal values.

1-128

I T1CO I MSEL IIEDG I SL1

I SLO
BitO

Control Registers

The Timer TO supports the following functions:

(Continued)

PSW Register (Address X'OOEF)
The PSW register contains the following select bits:
GIE

Global interrupt enable (enables interrupts)

EXEN

Enable external interrupt

BUSY

MICROWIRE/PLUS busy shifting flag

EXPND

External interrupt pending

T1 ENA

Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge

Carry Flag

Half Carry Flag

o
.......
o

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~

The device has a powerful timer/counter block, T1.

BitO

The control bits T1 C3, T1 C2, and T1 C1 allow selection of
the different modes of operation.
Mode 1. Processor Independent PWM Mode

ICNTRL Register (Address X'OOE8)

As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention.

The ICNTRL register contains the following bits:
Timer T1 Interrupt Enable for T1 B Input capture
edge

The user only has to define the parameters of the PWM
signal (ON time and OFF time). Once begun, the timer block
will continuously generate the PWM signal completely independent of the microcontroller. The user software services
the timer block only when the PWM parameters require updating.

T1 PNDB Timer T1 Interrupt Pending Flag for T1 B capture edge
WEN

The timer block consists of a 16-bit timer, T1, and two supporting 16-bit auto reload/ capture registers, R 1A and R 1B.
The timer block has two pins associated with it, T1 A and
T1 B. The pin T1 A supports I/O required by the timer block,
while the pin T1 B is an input to the timer block. The powerful
and flexible timer block allows the device to easily perform
all timer functions with minimal software overhead. The timer block has three operating modes: Processor Independent
PWM mode, External Event Counter mode, and Input Capture mode.

The Half-Carry bit is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and RC instructions, ADC,
SUBC, RRC and RLC instructions affect the carry and Half
Carry flags.

T1 ENB

TIMERT1

I HC IC IT1 PNDA IT1 ENA IEXPND IBUSY IEXEN I GIE I
Bit?

Exit out of the Idle Mode (See Idle Mode description)
Start up delay out of the HALT mode
The IDLE Timer TO can generate an interrupt when the thirteenth bit toggles. This toggle is latched into the TOPND
pending flag, and will occur every 4.096 ms at the maximum
clock frequency (te = 1 JLs). A control flag TOEN allows the
interrupt from the thirteenth bit of Timer TO to be enabled or
disabled. Setting TOEN will enable the interrupt, while resetting it will disable the interrupt.

T1 PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3)
C

a"tJ

Enable MICROWIRE/PLUS interrupt

WPND

MICROWIRE/PLUS interrupt pending

TOEN

Timer TO Interrupt Enable (Bit 12 toggle)

TOPND

Timer TO Interrupt pending

LPEN

L Port Interrupt Enable (Multi-Input Wake Up/
Interrupt)

In this mode the timer T1 counts down at a fixed rate of te.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, R1A and R1 B. The
very tlrst undertlow ot the timer causes the timer to reload
from the register R 1A. Subsequent underflows cause the
timer to be reloaded from the registers alternately beginning
with the register R1 B.

Bit? could be used as a flag

The T1 Timer control bits, T1 C3, T1 C2 and T1 C1 set up the
timer for PWM mode operation.
Bit7

BitO

Figure 9 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the T1 A output pin. The underflows can also be programmed to generate interrupts.

Timers
The device contains a very versatile set of timers (TO, T1,
and an 8-bit PWM timer). All timers and associated autoreload/capture registers power up containing random data.

Underflows from the timer are alternately latched into two
pending flags, T1 PNDA and T1 PNDB. The user must reset
these pending flags under software control. Two control enable flags, T1 ENA and T1 ENB, allow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag T1 ENA will cause an interrupt when a timer underflow causes the R 1A register to be reloaded into the
timer. Setting the timer enable flag T1 ENB will cause an
interrupt when a timer underflow causes the R1 B register to
be reloaded into the timer. Resetting the timer enable flags
will disable the associated interrupts.

Figure 8 shows a block diagram for timers T1 and TO on the
device.
TIMER TO (IDLE TIMER)
The device supports applications. that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer TO, which is a
16-bit timer. The Timer TO runs continuously at the fixed
rate of the instruction cycle clock, te' The user cannot read
or write to the IDLE Timer TO, which is a count down timer.

1-129

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Timers (Continued)

......

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N
A
14--------HI L

T1AI~~~----------~~

INSTRUCTION
CLOCK

--_1...---1

T1B IXI----i~

TLlDD/12067-8

FIGURE 8. Timers T1 and TO

TIMER
UNDERFLOW
INTERRUPT

+-----,

T1A

16 BIT AUTO RELOAD REGISTER
R1 B

141--....
TLlDD/12067 -9

FIGURE 9. Timer 1 In PWM MODE
Mode 2. External Event Counter Mode

Mode 3. Input Capture Mode

This mode is quite similar to the processor independent
PWM mode described above. The main difference is that
the timer, T1, is clocked by the input signal from the T1 A
pin. The T1 timer control bits, T1C3, T1C2 and T1C1 allow
the timer to be clocked either on a positive or negative edge
from the T1A pin. Underflows from the timer are latched into
the T1 PNDA pending flag. Setting the T1 ENA control flag
will cause an interrupt when the timer underflows.

The device can precisely measure external frequencies or
time external events by placing the timer block, T1, in the
input capture mode.

In this mode the input pin T1 B can be used as an independent positive edge sensitive interrupt input if the T1 ENB
control flag is set. The occurrence of a positive edge on the
T1 B input pin is latched into the T1 PNDB flag.

The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
T1 C3, T1 C2 and T1 C1 , allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently.

In this mode, the timer T1 is constantly running at the fixed
tc rate. The two registers, R1A and R 1B, act as capture
registers. Each register acts in conjunction with a pin. The
registerR1A acts in conjunction with the T1A pin and the
register R1 B acts in conjunction with the T1 B pin.

Figure 10 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the T1A pin is
being used as the counter input clock.

1-130

Timers

o"'C

(Continued)

The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the T1 A and T1 B pins will be respectively latched into
the pending flags, T1 PNDA and T1 PNDB. The control flag
T1 ENA allows the interrupt on T1 A to be either enabled or
disabled. Setting the T1 ENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
T1A pin. Similarly, the flag T1 ENB controls the interrupts
from the T1 B pin.

Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer T1 CO
pending flag (the T1 CO control bit serves as the timer underflow interrupt pending flag in the Input Capture mode). Consequently, the T1 CO control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is
enabled with the T1 ENA control flag. When a T1 A interrupt
occurs in the Input Capture mode, the user must check both
the T1 PNDA and T1 CO pending flags in order to determine
whether a T1A input capture or a timer underflow (or both)
caused the interrupt.

0)
Q)
~

o
......
o

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Q)
Q)
~

Figure 11 shows a block diagram of the timer in Input Capture mode.

TIMER
UNDERFLOW
INTERRUPT

+------.

T1AIXt--+I

16 81T AUTO RELOAD REGISTER ~--. .t
R18

TI8~TO

Interrupt Control
TL/00/12067-10

FIGURE 10. Timer 11n External Event Counter Mode

r-------ni"

16-81T TIMER

INSTRUCTION
CLOCK

T1A IXII-----1~

T18 IXlt---H

TL/DD/12067-11

FIGURE 11. Timer 11n Input Capture Mode

1-131

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D-

Timers

(Continued)
T1 ENA
T1 ENB

TIMER CONTROL FLAGS
The control bits and their functions are summarized below.
T1 CO

Timer Start/Stop control in Modes 1 and 2
(Processor Independent PWM and External
Event Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)
T1 PNDA Timer Interrupt Pending Flag
T1 PNDB Timer Interrupt Pending Flag

T1C3

T1C2

T1C1

T1 C3
T1 C2
T1 C1

Timer Interrupt Enable Flag
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
o = Timer Interrupt Disabled
Timer mode control
Timer mode control
Timer mode control

The timer mode control bits (T1C3, T1C2 and T1C1) are
detailed below:

Interrupt A
Source

Timer Mode

Interrupt B
Source

Timer
Counts On

MODE 2 (External
Event Counter)

Timer
Underflow

Positive T1 B
Edge

T1A
Positive Edge

MODE 2 (External
Event Counter)

Timer
Underflow

Positive T1 B
Edge

T1A
Negative Edge

MODE 1 (PWM)
T1A Toggle

Autoreload
RA

Autoreload
RB

MODE 1 (PWM)
No T1A Toggle

Autoreload
RA

Autoreload
RS

MODE 3 (Capture)
Captures:
T1 A Positive Edge
T1 B Positive Edge

Positive T1 A
Edge or
Timer
Underflow

Positive T1 B
Edge

MODE 3 (Capture)
Captures:
T1 A Positive Edge
T1 B Negative Edge

Positive T1 A
Edge or
Timer
Underflow

Negative T1 B
Edge

MODE 3 (Capture)
Captures:
T1 A Negative Edge
T1 B Positive Edge

Negative T1 B
Edge or
Timer
Underflow

Positive T1 B
Edge

MODE 3 (Capture)
Captures:
T1 A Negative Edge
T1 B Negative Edge

Negative T1 A
Edge or
Timer
Underflow

Negative T1 B
Edge

o
o

N = PSCAL + 1, so the maximum PWM clock frequency =
CKI and the minimum PWM clock frequency = CKJl256.
The processor is able to modify the PSCAL register regardless of whether the counter is running or not and the change
in frequency occurs with the next underflow of the prescaler
(CK-PWM).

HIGH SPEED, CONSTANT RESOLUTION
PWMTIMER
The device has one processor independent PWM timer. The
PWM timer operates in two modes: PWM mode and capture
mode. In PWM mode the timer outputs can be programmed
to two pins PWMO and PWM1. In capture mode, pin PWMO
functions as the capture input. Figure 12 shows a block diagram for this timer in capture mode and Figure 13 shows a
block diagram for the timer in PWM mode.

PWM On-time Register (RLON) (Address X'OOA1)
RLON is a read/write register. In PWM mode the timer output will be a "1" for RLON counts out of a total cycle of 255
PWM clocks. In capture mode it is used to program the
threshold frequency.

PWM TImer RegIsters
The PWM Timer has three registers: PWMCON, the PWM
control register, RLON, the PWM on-time register and
PSCAL, the prescaler register.

The PWM timer is specially designed to have a resolution of
255 PWM clocks. This allows the duty cycle of the PWM
output to be selected between 1/255 and 254/255. A value
of 0 in the RLON register will result in the PWM output being
continuously low and a value of 255 will result in the PWM
output being continuously high.

PWM Prescaler Register (PSCAL) (Address X'OOAO)
The prescaler is the clock source for the counter in both
PWM mode and in frequency monitor mode.
PSCAL is a read/write register that can be used to program
the prescaler. The clock source to the timer in both PWM
and capture modes can be programmed to CKJlN where

Note: The effect of changing the RLON register during active PWM mode
operation is delayed until the boundary of a PWM cycle. In capture
mode the effect takes place immediately.

1-132

Timers

o"'U

(Continued)

0')
(X)
~

o
......
o

o"'U
(X)
(X)

PWMI

ESEL

FMONIN

CKI------+I

memory mapped register
TL/DD/12067-12

FIGURE 12. PWM Timer Capture Mode Block Diagram

Standard

I/o

port function

PWENI

Standard I/O port function

1 - - - - -.... IlIl~rru!Jl
Overflow

PWENO

CKI----..

memory mapped register
TL/DD/12067-13

FIGURE 13. PWM Timer PWM Mode Block Diagram

1·133

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Timers

PWM Control Register (PWMCON) (Address X'0042)

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.......
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The PWMCON Register Bits are:

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PWEN1 Enable PWM1 output function on 1/0 port.
Note: The associated bits in the configuration and data register
of the IIO'port have to be setup as outputs and lor Inputs in
addition to setting the PWEN bits.
.

Once the timer is started, the timer output goes low after
RLON cycles and high after a total of 255 cycles. The procedure is continually repeated. In PWM mode the timer is
available at pins PWMO and lor PWM1, provided the port
configuration bits for those pins are defined as outputs and
the PWENO and lor PWEN1 bits in the PWMCON register
are set.

PWENO Enable PWMO output/input function on 1/0 port.

(Continued)

PWON

PWM start Bit, "1" to start timer, "0" to stop timer.

PWMD

PWM Mode bit, "1" for PWM mode, "0" frequency
monitor mode.

The PWM timer is started by the software setting the PWON
bit to "1 ". Starting the timer initializes the timer register.
From this point, the timer will continually generate the PWM
signal, independent of any processor activity, until the timer
is stopped by software setting the PWON bit to "0". The
processor is able to modify the RLON register regardless of
whether the timer is running. If RLON is changed while the
timer is running, the previous value of RLON is used for
comparison until the next. overflow occurs, when the new
value of RLON is latched into the comparator inputs.

PWIE
PWM interrupt enable bit.
PWPND PWM interrupt pending bit.
ESEL

Edge select bit, "1" for falling edge, "0" for rising
edge.

Sit7

When the timer overflows, the PWM pending flag (PWPND)
is set to "1". If the PWM interrupt enable bit (PWIE) is also
set to "1", timer overflow will generate an interrupt. The
PWPND bit remains set until the user's software writes a
"0" to it. If the software writes a "1" to the PWPND bit, this
has no effect. If the software writes a "0" to the PWPND bit
at the same time as the hardware writes to the bit, the hardware has precedence.

SitO'

PWMMode

The PWM timer can generate PWM signals at frequencies
up to 39 kHz (@ to = 1 JLs) with a resolution of 255 parts.
Lower PWM frequencies can be programmed via the pre'scaler.
If the PWM mode bit (PWMD) in the PWM configuration
register (PWMCON) is set to "1" the timer operates in PWM
mode. In this mode, the timer generates a PWM signal with
a fixed, non-programmable repetition rate of 255 PWM
clock cycles. The timer is clocked by the output of an 8-bit,
programmable prescaler, which is clocked with the chip's
CKI frequency. Thus the PWM signal frequency can be calculated with the formula:

Note: The software controlling the duty cycle is able to change the PWM
duty cycle with,out having to wait for the timer overflow.

Figure 14 shows how the PWM output is implemented. The
PWM Timer output is'set to "1" on an overflow of the timer
and set to "0" when the timer is greater than RLON. The
output can be multiplexed to two pins.

Capture Mode

If the PWM mode bit (PWMD) is set to "0" the PWM Timer
operates in capture mode. Capture mode allows the programmer to test whether the frequency of an external
source exceeds a certain threshold.

CKI

fpwm = - - - - - - - - - - (1 + (PSCAL-contents» x 255
Selecting the PWM mode by setting PWMD to "1", but not
yet starting the timer (PWON is "0"), will set the timer output
to "1".

If PWMD is "0" and PWON is "0", the timer output is set to
"0". In capture mode the timer output is available at pin
PWM1, provided the port configuration register bit for that
pin is set up as an output and the PWEN1 bit in the
PWMCON register is set. Setting PWON to "1" will initialize
the timer register and start the counter. A rising edge, or if
selected, a falling edge, on the FMONIN input pin will initialize the timer register and clear the timer output. The counter
continues .to count up after being initialized. The ESEL bit
determines whether the active edge is a rising or a falling
edge.

The contents of an 8-bit register, RLON, multiplied by the
clock cycle of the prescaler output defines the time between
overflow (or starting) and the falling edge of the PWM output.

1-134

~------------------------------------------------------------------------.

Timers

(Continued)

a"tJ
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ClO
~

255

o
o
'"

CONTENTS OF
FREE-RUNNING
UP-COUNTER

."
ClO
ClO
~

TIME

255

I
I

---~----t---~---7----i----~--~---~
TIMER OUTPUT
FOR DIFFERENT
VALUES OF RLON
(O,A,B and 255)

--~---~

---t-----

TIME

TL/OD/12067-14

FIGURE 14. PWM Mode Operation
If, in capture mode PWMO is configured incorrectly as an
output and is enabled via the PWENO bit, the timer output
will feedback into the PWM block as the timer input.

It should be noted that two other conditions could also set
the PWPND bit:

The contents of the counter are continually compared with
the RLON register. If the frequency of the input edges is
sufficiently high, the contents of the counter will always be
less than the value in RLON. However, if the frequency of
the input edges is too low, the free-running counter value
will count up beyond the value in RLON.

output will toggle. If frequency monitor mode is .entered
on the fly such that the timer output changes from 0 to 1,
PWPND will be set.

1. If the mode of operation is changed on the fly the timer

2. If the timer is operating in frequency monitor mode and
the RLON value is changed on the fly so that RLON
becomes less than the current timer value, PWPND will
be set.

When the counter is greater than RLON, the PWM timer
output is set to "1". It is set to "0" by a detected edge on
the timer input or when the counter overflows. When the
counter becomes greater than RLON, the PWPND bit in the
PWM centre! regi~ter !~ ~et to "1". If the PW!E bit is ~!so set
to "1", the PWPND bit is enabled to request an interrupt.

The PWPND bit remains set until the user's software writes
a "0" to it. If the software writes a "1" to the PWPND bit,
this has no effect: If the software writes a "0" to the
P'vVPi~D uit at iiltl l>allitl iilllt! a::; iilt! ildlUWdl'" Vvlii",::; to

iii'"

bit, the hardware has precedence. (See Figure 15 for Frequency Monitor Mode Operation.)

OVERFLOW

(255)

RLON

II
OUTPUT

INPUT (PROGRAMMED TO B~
ACTIVE ON POSITIVE EDGE)
TL/DD/12067-15

FIGURE 15. Frequency Monitor Mode Operation

1-135

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r-----------------------------------------------------------------~

Power Save Modes
The device offers the user two power save modes of operation: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscillator circuitry and timer TO are active but all other microcontroller activities are stopped. In either mode, all on-board
RAM, registers, I/O states, and timers (with the exception of
TO) are unaltered.

As with the HALT mode, the device can be returned to normal operation with a reset, or with a Multi-Input Wake Up
from the L Port or CAN Interface. Alternately, the microcontroller resumes normal operation from the IDLE mode when
the thirteenth bit (representing 4.096 ms at internal clock
frequency of 1 MHz, te = 1 fLS) of the IDLE Timer toggles.

HALT MODE

This toggle condition of the thirteenth bit of the IDLE Timer
TO is latched into the TOPND pending flag.

The contents of all PWM Timer registers are frozen during
HALT mode and are left unchanged when exiting HALT
mode. The PWM timer resumes its previous mode of operation when exiting HALT mode.

The device is placed in the HALT mode by writing a "1" to
the HALT flag (G7 data bit). All microcontroller activities,
including the clock, and timers, are stopped. In the HALT
mode, the power requirements of the device are minimal
and the applied voltage (Vee) may be decreased to Vr (Vr =
2.0V) without altering the state of the machine.

The user can enter the IDLE mode with the Timer TO interrupt enabled. In this case, when the TOPND bit gets set, the
device will first execute the Timer TO interrupt service routine and then return to the instruction following the "Enter
Idle Mode" instruction.
Alternatively, the user can enter the IDLE mode with the
IDLE Timer TO interrupt disabled. In this case, the device
will resume normal operation with the instruction immediately following the "Enter IDLE Mode" instruction.

The device supports two different ways of exiting the HALT
mode. The first method of exiting the HALT mode is with the
Multi-Input Wake Up feature on the L port. The second
method of exiting the HALT mode is by pulling the RESET
pin low.

Note: It is necessary to program two NOP instructions following both the set
HALT mode and set IDLE mode instructions. These NOP instructions
are necessary to allow clock resynchronization following the HALT or
IDLE modes.

Since a crystal or ceramic resonator may be selected as the
oscillator, the Wake Up signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wake Up signal, only the oscillator
circuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the te instruction cycle clock. The te
clock is derived by dividing the oscillator clock down by a
factor of 10. The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE timer is clocked only
when the oscillator has a sufficiently large amplitude. to
meet the Schmitt trigger specifications. This Schmitt trigger
is not part of the oscillator closed loop. The start-up time-out
from the IDLE timer enables the clock signals to be routed
to the rest of the chip.

Multi-Input Wake Up
The Multi-Input Wake Up feature is used to return (wake up)
the device from either the HALT or IDLE modes. Alternately,
the Multi-Input Wake Up/lnterrupt feature may also be used
to generate up to 7 edge selectable external interrupts.
Figure 16 shows the Multi-Input Wake Up logic for the microcontroller. The Multi-Input Wake Up feature utilizes the L
Port. The user selects which particular L port bit (or combination of L Port bits) will cause the device to exit the HALT
or IDLE modes. The selection is done through the Reg:
WKEN. The Reg: WKEN is an 8-bit read/write register,
which contains a control bit for every L port bit. Setting a
particular WKEN bit enables a Wake Up from the associated port pin.

The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an
8-bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wake Up condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.

The device has two mask options associated with the HALT
mode. The first mask option enables the HALT mode feature, while the second mask option disables the HALT
mode. With the HALT mode enable mask option, the device
will enter and exit the HALT mode as described above. With
the HALT disable mask option, the device cannot be placed
in the HALT mode (writing a "1" to the HALT flag will have
no effect).
IDLE MODE
The device is placed in the IDLE mode by writing a "1" to
the IDLE flag (G6 data bit). In this mode, all activities, except
the associated on-board oscillator circuitry, and the IDLE
Timer TO, are stopped. The power supply requirements of
the microcontroller in this mode of operation are typically
around 30% of normal power requirement of the microcontroller.

An example may serve to clarify this procedure. Suppose
we wish to change the edge select from positive (low going
high) to negative (high going low) for L Port bit 5, where bit 5
has previously been enabled for an input interrupt. The program would be as follows:

RBIT
SBIT
RBIT
SBIT
1-136

5,
5,
5,
5,

WKEN
WKEDG
WKPND
WKEN

Multi-Input Wake Up (Continued)

-a
0)

If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wake Up/Interrupt, a
safety procedure should also be followed to avoid inherited
pseudo wake up conditions. After the selected L port bits
have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired
edge selects, followed by the associated WKPND bits being
cleared.

Wake Up is latched into a pending register called WKPND.
The respective bits of the WKPND register will be set on the
occurrence of the selected trigger edge on the corresponding Port L pin. The user has the responsibility of clearing
these pending flags. Since WKPND is a pending register for
the occurrence of selected wake up conditions, the device
'",ill not enter the HALT mode if any Wake Up bit is both
... nabled and pending. Consequently, the user has the responsibility of clearing the pending flags before attempting
to enter the HALT mode.

This same procedure should be used following reset, since
the L port inputs are left floating as a result of reset. The
occurrence of the selected trigger condition for Multi-Input

(X)
~

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o

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(X)
(X)
~

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The WKEN, WKPND and WKEDG are all read/write registers, and are cleared at reset.

INTERNAL DATA BUS

~ LO
.!:.

::J
0

•
•
•

.!:.

•

.,
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a.
c

•
•
•

•

:::>

CAN
CaMP
OUT

TO INTERRUPT LOGIC

CHIP CLOCK
TL/DD/12067-16

FIGURE 16. Multi-Input Wake Up Logic

1-137

or-------------------------------------------------------------~

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Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software
interrupt are maskable. Each of the maskable interrupts
have an Enable bit and a Pending bit. A maskable interrupt
is active if its associated enable and pending bits are set. If
GIE = ·1 and an interrupt is active, then the processor will
be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described
in the Software Trap sub-section.

Multi-Input Wake Up (Continued)
CAN RECEIVE WAKE UP

The CAN Receive Wake Up source is always enabled and is
always active on a falling edge of the CAN comparator output. There is no specific enable bit for the CAN Wake Up
feature. Although the wake up feature on pins LO.. L6 can be
programmed to generate an interrupt (L-port interrupt), no
interrupt is generated upon a CAN receive wake up condition. The CAN block has its own, dedicated receiver interrupt upon receive buffer full.

The interruption process is accomplished with the INTR instruction (opcode 00), which is jammed inside the Instruction Register and replaces the opcode about to be executed. The following steps are performed for every interrupt:

PORT L INTERRUPTS

Port L provides the user with an additional seven fully selectable, edge sensitive interrupts which are all vectored
into the same service subroutine.

1. The GIE (Global Interrupt Enable) bit is reset.
2. The address of the instruction about to be executed is
pushed into the stack.
3. The PC (Program Counter) branches to address OOFF.
This procedure takes 7 tc cycles to execute.

The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to
be individually enabled or disabled. The register WKEDG
specifies the trigger condition to be either a positive or a
negative edge. Finally, the register WKPND latches in the
pending trigger conditions.
The GIE (global interrupt enable) bit enables the interrupt
function. A control flag, LPEN, functions as a global interrupt enable for Port L interrupts. Setting the LPEN flag will .
enable interrupts and vice versa. A separate global pending
flag is not needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If
he elects to disable the interrupt, then the device will restart
execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or
IDLE modes. In the other case, the device will first execute
the interrupt service routine and then revert to normal operation.
The Wake Up signal will not start the chip running immediately since crystal oscillators or ceramic resonators have a
finite start up time. The IDLE Timer (TO) generates a fixed
delay to ensure that the oscillator has indeed stabilized before allowing the device to execute instructions. In this case,
upon detecting a valid Wake Up signal, only the oscillator
circuitry and the IDLE Timer TO are enabled. The IDLE Timer is loaded with a value of 256 and is clocked from the tc
instruction cycle clock. The tc clock is derived by dividing
down the oscillator clock by a factor of 10. A Schmitt trigger
following the CKI on-chip inverter ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large
amplitude to meet the Schmitt trigger specifications. This
Schmitt trigger is not part of the oscillator closed loop. The
start-up time-out from the IDLE timer enables the clock signals to be routed to the rest of the chip.

At this time, since GIE = 0, other maskable interrupts are
disabled. The user is now free to do whatever context
switching is required by saving the context of the machine in
the stack with PUSH instructions. The user would then program a VIS (Vector Interrupt Select) instruction in order to
branch to the interrupt service routine of the highest priority
interrupt enabled and pending at the time of the VIS. Note
that this is not necessarily the interrupt that caused the
branch to address location OOFF Hex prior to the context
switching.
Thus, if an interrupt with a higher rank than the one which
caused the interruption becomes active before the decision
of which interrupt to service is made by the VIS, then the
interrupt with the higher rank will override any lower ones
and will be acknowledged. The lower priority interrupt(s) are
still pending, however, and will cause another interrupt immediately following the completion of the interrupt service
routine associated with the higher priority interrupt just serviced. This lower priority interrupt will occur immediately following the RETI (Return from Interrupt) instruction at the
end of the interrupt service routine just completed.
Inside the interrupt service routine, the associated pending
bit has to be cleared by software. The RETI (Return from
Interrupt) instruction at the end of the interrupt service routine will set the GIE (Global Interrupt Enable) bit, allowing
the processor to be interrupted again ff another interrupt is
active and pending.
The VIS instruction looks at all the active interrupts at the
time it is executed and performs an indirect jump to the
beginning of the service routine of the one with the highest
rank.
The addresses of the different interrupt service routines,
called vectors, are chosen by the user and stored in ROM in
a table starting at 01 EO (assuming that VIS is located between OOFF and 01DF). The vectors are 15-bit wide and
therefore occupy 2 ROM locations.

Interrupts
The device supports a vectored interrupt scheme. It supports a total of eleven interrupt sources. The following table
lists all the possible device interrupt sources, their arbitration ranking and the memory locations reserved for the interrupt vector for each source.

1-138

Interrupts (Continued)

"tJ

If, by accident, a VIS gets executed and no interrupt is active, then the PC (Program Counter) will branch to a vector
located at OyEO-OyE1. This vector can point to the Software
Trap (Sn interrupt service routine, or to another special
service routine as desired.
Figure 17 shows the Interrupt Block diagram.

The Software Trap has the highest rank and its vector is
located at OyFE and OyFF.

Arbitration
Ranking
1

Software Trap

OyFE-OyFF

Reserved

OyFC-OyFD

CAN Receive

OyFA-OyFB

CAN Error
(transmit/receive)

OyF9-0yF9

CAN Transmit

OyF6-0yF7

Pin GO Edge

OyF4-0yF5

IDLE Timer Underflow

OyF2-0yF3

Timer T1 AlUnderflow

OyFO-OyF1

TimerT1B

OyEE-OyEF

MICROWIRE/PLUS

OyEC-OyED

PWMtimer

OYEA-OyEB

CAN Block Description *

Reserved

OyE8-0yE9

This device contains a CAN serial bus interface as described in the CAN Specification Rev. 2.0 part B.

Reserved

OyE6-0yE7

Reserved

OyE4-0yE5

Port L/Wake Up

uf#l",uii VIS

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When an ST occurs, the user can re-initialize the stack
pointer and do a recovery procedure (similar to RESET, but
not necessarily containing all of the same initialization procedures) before restarting.
The occurrence of an ST is latched into the ST pending bit.
The GIE bit is not affected and the ST pending bit (not
accessible by the user) is used to inhibit other interrupts
and to direct the program to the ST service routine with the
VIS instruction. The RPND instruction is used to clear the
software interrupt pending bit. This bit is also cleared on
reset.
The ST has the highest rank among all interrupts.

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SOFTWARE TRAP
The Software Trap (Sn is a special kind of non-maskable
interrupt which occurs when the INTR instruction (used to
acknowledge interrupts) is fetched from ROM and placed
inside the instruction register. This may happen when the
PC is pointing beyond the available ROM address space or
when the stack is over-popped.

Vector
Address
HI-Low
Byte

Source

0)
0)

Nothing (except another ST) can Interrupt an ST being
serviced.

• Patents Pending.

OyE2-0yE3

IlIit:HIu~i

OycO-Oyci

Y is VIS page, y oF 0

SOFTWARE TRAP -------------~

TIt.lER Tl

EXTERNAL

t.lULTHNPUT WAKE UP

;lWIRE/PLUS
HIGH SPEED
CONSTANT RESOLUTION
PWM TIMER
CAN

IDLE TIt.lER

TlIDD/12067-17

FIGURE 17. Interrupt Block Diagram
1-139

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CAN Interface Block
This device supports applications which require a low speed
CAN interface. It is designed to be programmed with two
transmit and two receive registers. The user's program may
check the status bytes in order to get information of the bus
state and the received or transmitted messages. The device
has the capability to generate an interrupt as soon as one
byte has been transmitted or received. Care must be taken
if more than two bytes in a message frame are to be transmitted/received. In this case the user's program must poll
the transmit buffer empty (TBE)/receive buffer full (RBF)
bits or enable their respective interrupts and perform a data
exchange between the user data and the Tx/Rx registers.
TxO

Fully automatic retransmission is supported for messages
not longer than 2 bytes. Messages which are longer than
two byte have to be processed by software.
The interface is compatible with CAN Specification 2.0 part
B, without the capability to receive/transmit extended
frames. However, extended frames on the bus are checked
and acknowledged according to the CAN specification.
The maximum bus speed achievable with the CAN interface
is a function of crystal frequency, message length and software overhead. The device can support a bus speed of up
to 1 Mbitls with a 10 MHz oscillator and 2 byte messages.

Tx 1

RxREFO
TxENO

TxEN 1

CAN REGISTERS
TRANSCEIVER LOGIC
Rx/Tx SHIFT REGISTERS
CRC GENERATOR/CHECKER
BIT TIME LOGIC

BIT STREAM
PROCESSOR

ERROR
MANAGEMENT
LOGIC

INTERFACE MANAGEMENT LOGIC

INTERNAL BUS
TL/DD/12067-1B

FIGURE 18. CAN Interface Block Diagram

1-140

Functional Block Description Of The CAN Interface

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INTERFACE MANAGEMENT LOGIC (IML)

OUTPUT DRIVERS/INPUT COMPARATORS

The IML executes the CPU's transmission and reception
commands and controlling the data transfer between CPU,
Rx/Tx, and CAN registers. It provides the CAN Interface
with Rx/Tx data from the memory mapped Register Block. It
also sets and resets the CAN status information and generates interrupts to the CPU.

The output drivers/input comparators are the physical interface to the bus. Control bits are provided to TRI-STATE the
output drivers.

-1:10

TABLE II. Bus Level Definition
Bus Level

BIT STREAM PROCESSOR (BSP)
The BSP is a sequencer controlling the data stream between Interface Management Logic (parallel data) and the
bus line (serial data). It controls the transceive logic with
regard to reception, arbitration, and creates error signals
according to the bus specification.

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-1:10

Pin Tx1

PlnTxO

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"dominant"

drive low (GND)

drive high (Vce>

"recessive"

TRI-STATE

CKI

TRANSCEIVE LOGIC (TCL)
The TCL is a state machine which incorporates the bit stuff
logic and controls the output drivers, CRC logic, and the Rx/
Tx shift registers. It also controls the synchronization to the
bus with the CAN clock signal generated by the BTL.

TL/DD/12067-19

FIGURE 19. Bit Rate Generation
REGISTER BLOCK
The register block consists of fifteen 8·bit registers which
are described in more detail in the following paragraphs.

ERROR MANAGEMENT LOGIC (EML)
The EML is responsible for the fault confinement of the
CAN protocol. It is also responsible for changing the error
counters, setting the appropriate error flag bits and interrupts and changing the error status (passive, active and bus
off).

Note: The contents of the receiver related registers Rx01, RxD2, ROLC,
RIDH and RTSTAT are only changed if a received frame passes the
acceptance filter or the Receive Identifier Acceptance Filter bit (RIAF)
is set to accept all received messages.

TRANSMIT DATA REGISTER 1 (TXD1) (Address X'OOBO)

CYCLIC REDUNDANCY CHECK (CRC) GENERATOR
AND REGISTER

The Transmit Data Register 1 contains always the first data
byte to be transmitted within a frame and then the successive odd byte numbers (Le., bytes number 1,3,.. ,7).

The CRC Generator consists of a 15-bit shift register and
the logic required to generate the checksum of the destuffed bit-stream. It informs the EML about the result of a
receiver checksum.

TRANSMIT DATA REGISTER 2 (TXD2) (Address X'OOB1)
The Transmit Data Register 2 contains always the second
data byte to be transmitted within a frame and then the
successive even byte numbers (Le., bytes number 2,4, .. ,8).

The checksum is generated by the polynomial:
x 15

x14

x 10

+ x8 + x 7 + x4 +

+ 1

TRANSMIT DATA LENGTH CODE AND IDENTIFIER LOW
REGISTER (TDLC) (Address X'OOB2)

RECEIVE/TRANSMIT (RX/TX) REGISTERS
The Rx/Tx registers are 8-bit shift registers controlled by
the TCL and the BSR. They are loaded or read by the Interface Management Logic, which holds the data to be transmitted or the data that was received.

B~7

B~O

This register is read/write.

BIT TIME LOGIC (BTL)

TID3 .. TIDO

The bit time logic divider divides the CKI input clock by the
value defined in the CAN prescaler (CSCAL) and bus timing
register (CTIM). The resulting bus clock (tCAN) can be computed by the formula:

The transmit identifier is composed of eleven bits in total,
bits 3 to 0 of the TID are stored in bits 7 to 4 of this register.
DLC3 .. TDLCO

divider)

Transmit Data Length Code

These bits determine the number of data bytes to be transmitted within a frame.

CKI
teAN = (1

Transmit Identifier Bits 3 ... 0 (lower 4 bits)

x (1 + 2 x PS + PPS)

TRANSMIT IDENTIFIER HIGH (TID) (Address X'OOB3)

Where divider is the value of the clock prescaler, PS is the
programmable value of phase segment 1 and 2 (1 .. 8) and
PPS the programmed value of the propagation segment
(1 .. 8) (located in CTIM).

BitO

Bit7

This register is read/write.

Note: The synchronization jump width (SJ) (see CAN BUS TIMING REGISTER (CTIM)) should be less then the programmed value of PS1. If a
soft resynchronization is done during phase segment 1 or the propagation segment, then SJ will always be equal to the programmed
value. If soft resynchronization is done during phase segment 2 and
the programmed value of SJ is greater than or equal to the programmed PS 1 value, PS2 will never be smaller than 1.

TRTR

Transmit Remote Frame

This bit is set if the frame to be transmitted is a remote
frame.
TID10 .. TID4
Transmit Identifier Bits 10..4 (higher 7 bits)
Bits TID10 .. TID4 are the upper 7 bits of the 11-bit transmit
identifier.

1-141

ED
~

Functional Block Description Of The CAN Interface (Continued)

RECEIVE DATA REGISTER 1 (RXD1) (Address X'00B4)

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oo
o"'"
ED
~

RECEIVE DATA REGISTER 2 (RXD2) (Address X'OOB5)

The Receive Data Register 2 (RXD2) contains always the
second data byte received in a frame and then successive
even byte numbers (Le., bytes 2,4 .... 8). This register is readonly.

o
o

The PPS2 .. PPSO bits determine the length of the propagation delay in Prescaler clock cycles (PSC) per bit time. (For
a more detailed discussion of propagation delay and phase
segments. see SYNCHRONIZATION).

The Receive Data Register 1 (RXD1) contains always the
first data byte received in a frame and then successive odd
byte numbers (Le., bytes 1,3, .. ,7). This register is read-only.

PS2 .. PSO
Phase Segment 1. bits 2.. 0
The PS2 .. PSO bits fix the number of Prescaler clock cycles
per bit time for phase segment 2.
SJ1. SJO

Synchronization Jump Width 0 and 1

The Synchronization Jump Width defines the maximum
number of Prescaler clock cycles by which a bit may be
shortened. or lengthened. to achieve re-synchronization on
"recessive" to "dominant" data transitions on the bus.

RECEIVE DATA lENGTH CODE AND IDENTIFIER lOW
REGISTER (RIDl) (Address X'OOB6)

TABLE III. Synchronization Jump Width
~7

This register is read only.
RID3 .. RIDO

SJ1

SJO

Receive Identifier bits (lower four bits)

The RID3 .. RIDO bits are the lower four bits of the eleven bit
long Receive Identifier. Any received message that matches
the upper 7 bits of the Receive Identifier (RID10 .. RID4) is
accepted if the Receive Identifier Acceptance Filter (RIAF)
bit is set to zero (see also RECEIVE IDENTIFIER HIGH
(RID) (Address X·00B7).

Bij7

BijO

cKsel CKS5

4PSC

Bit 7

CKS41 CKS3

CKS21

CKS1

CKSO

PPSO

I I
PS2

PS1

I I
PSO

SJ1

Bit 0

RIAF

Receive identifier acceptance filter bit

If the RIAF bit is set to zero. bits 4 to 10 of the received
identifier are compared with the mask bits of RID4 .. RID10
and if the corresponding bits match. the message is accept~
ed. If the RIAF bit is set to a one. the filter function is disabled and all messages independent of the identifier will be
accepted.
TXENO.
TXEN1

TxD Output Driver Enable
TABLE IV. OutP~t Drivers

CAN BUS TIMING REGISTER (CTIM) (00B9)
SJO
'~o

This register is read/write.
PPS2 .. PPSO

3PSC

Reserved This bit is reserved and should be zero.

Bij7
BijO
This register is read/write.
CKS7 .. 0
Prescaler divider select.
The resulting clock value is the CAN Prescaler clock.

PPS1

CAN BUS CONTROL REGISTER (CBUS) (OOBA)

CAN PRESCAlER REGISTER (CSCAl) (Address
X'OOBB)

I I

1
1

Receive Identifier bits (upper bits)

The RID10 .. RID4 bits are the upper 7 bits of the eleven bit
long Receive Identifier. 'If the Receive Identifier Acceptance
Filter (RIAF) bit (see CBUS registers) is set to zero. bits 4 to
10 of the received identifier are compared with the mask
bits of RID4 .. RID1 0 and if the corresponding bits match. the
message is accepted. If the RIAF bit is set to a one. the filter
function is disabled and all messages independent of the
identifier will be accepted.

PPS2

2PSC

• Phase Segment 1 and Phase Segment 2 are programmable (PS) to be 1.2..... 8 PSC long

This register is read/write.

1 PSC

• The Propagation Segment can be programmed (PPS) to
be 1.2.: ... 8 PSC in length.

RECEIVE IDENTIFIER HIGH (RID) (Address X'OOB7)

CKS7

• The Synchronization Segment is 1 CAN Prescaler clock
(PSC)

The RDLC3 .. RDLCO bits determine the number of data
bytes within a rece,ived frame.

0
0

LENGTH OF TIME SEGMENTS

RDLC3 .. RDLCO Receive Data Length Code bits

RID10 .. RID4

Synchronization Jump
Width

Propagation Segment, bits 2 .. 0

1-142

TXEN1

TXENO

Output

TxO. Tx1 TRI-STATED. CAN,
input comparator disabled

TxO enabled

Tx1 enabled

TxO and Tx1 enabled

Functional Block Description Of The CAN Interface (Continued)
RERR

Bus synchronization of the device is done in the following
way:
If the output was disabled (TXEN1, TXENO = "0") and either TXEN1 or TXENO, or both are set to 1, the device will
not start transmission or reception of a frame until eleven
consecutive "recessive" bits have been received. Resetting
the TXEN1 and TXENO bits will disable the output drivers
and the CAN input comparator. All other CAN related registers and flags will be unaffected. It is recommended that the
user resets the TXEN1 and TXENO bits before switching the
device into the HALT mode (the CAN receive wake up will
still work) in order to reduce current consumption and to
assure a proper resynchronization to the bus after exiting
the HALT mode.

Reference voltage applied to Rx1 if bit is
set

RXREFO

Reference voltage applied to RxO if bit is
set

FMOD

Fault Confinement Mode select

Q)
Q)

CAN Error Interrupt Enable

TIE

TERR

I I
RERR

CEIE

I I
TIE

RIE

BH7

TXSS

BHO

NS1 .. NSO

Node Status, i.e., Error Status.
TABLE V. Node Status

NS1

NSO

error Aciiv~

Error Passive

Bus Off

Output

The Node Status bits are read only.
TERR

Transmit Interrupt Enable

Receive Interrupt Enable

TXSS

NSO

........

If set by the user's software, this bit enables the transmit
interrupt. (See TBE and TXPND.) Resetting this bit with a
pending transmit interrupt will inhibit the interrupt, but will
not clear the cause of the interrupt. If the bit is then set
without clearing the cause of the interrupt, the interrupt will
reoccur.

TRANSMIT CONTROL/STATUS (TCNTL) (OOBB)

I I

CEIE

If set by the user's software, this bit enables the receive
interrupt or a remote transmission request interrupt. (See
RBF, RFV and RRTR.) Resetting this bit with a pending receive interrupt will inhibit the interrupt, but will not clear the
cause of the interrupt. If the bit is then set without clearing
the cause of the interrupt, the interrupt will reoccur.

NS1

Setting the FMOD bit to "0" (default after power on reset)
will select the Standard Fault Confinement mode. In this
mode the device goes from "bus off" to "error active" after
monitoring 128 ·11 recessive bits (including bus idle) on the
bus.

"en

This bit is automatically set when an error occurred during
the reception of a frame. RERR can be programmed to generate an interrupt by setting the Can Error Interrupt Enable
bit (CEIE). This bit has to be cleared by the user's software.
If set by the user's software, this bit enables the transmit
and receive error interrupts. The interrupt pending flags are
TERR and RERR. Resetting this bit with a pending error
interrupt will inhibit the interrupt, but will not clear the cause
of the interrupt. If the bit is then set without clearing the
cause of the interrupt, the interrupt will reoccur.

Note: A "bus off" condition will also cause TxO and Txt to be at TRI·STATE
(independent of the values of the TXENt and TXENO bits).

RXREF1

Receive Error

Transmission Start/Stop

This bit is set by the user's software to initiate the transmission of a frame. Once this bit is set, a transmission is pending, as indicated by the TXPND flag being set. It can be
reset by software to cancel a pending transmission. Resetting the TXSS bit will only cancel a transmission, if the transmission of a frame hasn't been started yet (bus idle), if arbitration has been lost (receiving) or if an error occurs during
transmission. If the device has already started transmission
(won arbitration) the TXPND and TXSS flags will stay set
until the transmission is completed, even if the user's software has written zero to the TXSS bit. If one or more data
bytes are to be transmitted, care must be taken by the user,
that the Transmit Data Register(s) have been loaded before
the TXSS bit is set.
TXSS will be cleared on three conditions only: Successful
completion of a transmitted message; successful cancellation of a pending transmission; Transition of the CAN interface to the bus-off state.

Transmit Error

This bit is automatically set when an error occurred during
the transmission of a frame. TERR can be programmed to
generate an interrupt by setting the Can Error Interrupt Enable bit (CEIE). This bit has to be cleared by the user's
software.

Writing a zero to the TXSS bit will request cancellation of a
pending transmission but TXSS will not be cleared until
completion of the operation. If an error occurs during transmission of a frame, the logic will check for cancellation requests prior to restarting transmission. If zero has been written to TXSS, retransmission will be cancelled.

Note: This is used for messages of more than two bytes. If an error occurs
during the transmission of a frame with more than 2 data bytes, the
user's software has to handle the correct reloading of the data bytes
to the TxD registers for retransmission of the frame. For frames with 2
or less data bytes the interface logic of this chip does an automatic
retransmission. Nevertheless, regardless of the number of data bytes:
The user's software has to reset this bit if CEIE is enabled. Otherwise
a new interrupt will be generated immediately after return from the
interrupt service routine.

1-143

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a..

o"-

Functional Block Description Of The CAN Interface

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a..

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Bit?

BitO

This register is read only.
TBE

ROLD

Transmit Buffer Empty

RORN

Receiver Overrun

This bit is automatically set on an overrun of the receive
data register, i.e., if the user's program did not maintain the
RxDn registers when receiving a frame. It is automatically
reset through a read of the Receive/Transmit Status register. It is the responsibility of the user to clear this bit by
reading the Receive/Transmit Status register before the
next frame is received.
RFV

Received Frame Valid

This bit is set if the received frame is valid, i.e., after the
penultimate bit of the End of Frame was received. It is automatically reset through a read of the Receive/Transmit
Status register. It is the responsibility of the user to clear this
bit by reading the receive/transmit status register
(RTSTAT), before the next frame is received. RFV will
cause a Receive Interrupt if enabled by RIE. The user
should be careful to read the last data byte (RxD1) of odd
length messages (1, 3, 5 or ? data bytes) on receipt of RFV.
RFV is the only indication that the last byte of the message
has been received.

~EFRAME
SIGNAL

TLlDD/12067-20

FIGURE 20. Acceptance .Filter Block-Diagram

RCV

Transmission Pending

Receive Mode

This bit is set after the data length code of a message that
passes the device's acceptance filter has been received. It
is automatically reset after the eRC-delimiter of the same
frame has been received. It indicates to the user's software
that arbitration is lost and that data is coming in for that
node.

This bit is set as soon as the Transmit Start/Stop (TXSS) bit
is set by the user. It will stay set until the frame was successfully transmitted, until the transmission was successfully cancelled by writing zero to the Transmission Start/Stop
bit (TXSS), or the device enters the bus-off state. Resetting
the TXSS bit will only cancel a transmission, if the transmission of a frame hasn't been started yet (bus idle), or if arbitration has been lost (receiving). If the device has already
started transmission (won arbitration) the TXPND flag will
stay set until the transmission is completed, even if the user's software has requested cancellation of the message. If
an error occurs during transmission, a requested cancellation may occur prior to the beginning of retransmission.
RRTR

Received Overload Frame

This bit is automatically set when an Overload Frame was
received on the bus. It is automatically reset through a read
of the Receive/Transmit Status register. It is the responsibility of the user to clear this bit by reading the Receive/Transmit Status register, before the next frame is received.

This bit is set as soon as the TxD2 register is copied into the
Rx/Tx shift register, i.e., the 1st data byte of each pair has
been transmitted. The TBE bit is automatically reset if the
TxD2 register is written (the user should write a dummy byte
to the TxD2 register when transmitting an odd number of
bytes or zero bytes). TBE can be programmed to generate
an interrupt by setting the Transmit Interrupt Enable bit
(TIE). When servicing the interrupt the user has to make
sure that TBE gets cleared by executing a WRITE instruction on the TxD2 register, otherwise a new interrupt will be
generated immediately after return from the interrupt service routine. The TBE bit is read only. It is set to 1 upon reset.
TBE is also set upon completion of transmission of a valid
message.

TXPND

(Continued)

To detect RRTR the user can either poll this flag or enable
the receive interrupt (the reception of a remote transmission
request will also cause an interrupt if the receive interrupt is
enabled). If the receive interrupt is enabled, the user should
check the RRTR flag in the service routine in order to distinguish between a RRTR interrupt and a RBF interrupt. It is
the responsibility of the user to clear this bit by reading the
RXD1 register, before the next frame is received.

RECEIVE/TRANSMIT STATUS (RTSTAT) (Address
X'OOBC)

RBF

Receive Buffer Full

This bit is set if the second Rx data byte was received. It is
reset automatically, after the RxD1-Register has been read
by the software. RBF can be programmed to generate an
interrupt by setting the Receive Interrupt Enable bit (RIE).
When servicing the interrupt the user has to make sure that
RBF gets cleared by executing a LD instruction from the
RxD1 register, otherwise a new interrupt will be generated
immediately after return from the interrupt service routine.
The RBF bit is read only.

Received Remote Transmission Request

This bit is set when the remote transmission request (RTR)
bit in a received frame was set. It is automatically reset
through a read of the RXD1 register.

TRANSMIT ERROR COUNTER (TEC) (Address X'OOBD)

Bit?

BitO

This register is read/write.
For test purposes and to identify the node status, the transmit error counter, an 8-bit error counter, is mapped into the
data memory. If the lower seven bits of the counter overflow, i.e., TEC? is set, the device is error passive.

1-144

To prevent interference with the CAN fault confinement, the
user must not write to the REC/TEC registers. Both counters are automatically updated following the CAN specification.

REG1

0')

This device will process standard frame format only. Extended frame formats will be acknowledged, however the
data will be discarded. For this reason the description of
frame formats in the following chapters will cover only the
standard frame format.

RECEIVE ERROR COUNTER (REC) (OOBE)

Bit?

"'C

The following paragraphs provide a generic overview over
the basic concepts of the Controller Area Network (CAN) as
described in Chapter 4 of ISO/0IS11519-1. Implementation
related issues of the National Semiconductor device will be
discussed as well.

CAUTION:

I REG? IREGal REG5 IREG41 REG3 IREG21

Basic CAN Concepts

Functional Block Description Of
The CAN Interface (Continued)

I REGO I

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"'C

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The following section provides some more detail on how the
device will handle received extended frames:

BitO

This register is read/write.

If the device's remote identifier acceptance filter bit (RIAF)
is set to "1", extended frame messages will be acknowledged. However, the data will be discarded and the device
will not reply to a remote transmission request received in
extended frame format. If the device's RIAF bit is set to "0"
the upper 7 received 10 bits of an extended frame that
match the device's receive identifier (RID) acceptance filter
bits, are stored in the device's RID register. However, the
device does not reply to an RTR and any data is discarded.
The device will only acknowledge the message.

MESSAGE IDENTIFICATION

a) Transmitted Messages
The user can select ali 11 Transmit identifier Bits to transmit
any message which fulfills the CAN2.0, part B spec without
an extended identifier (see note below). Fully automatic retransmission is supported for messages no longer than 2
bytes.

b) Received Messages
The lower four bits of the Receive Identifier are don't care,
i.e., the controller will receive all messages that fit in that
window (16 messages). The upper 7 bits can be defined by
the user in the Receive Identifier High Register to mask out
groups of messages. If the RIAF bit is set, all messages will
be received.

MULTI-MASTER PRIORITY BASED BUS ACCESS
The CAN protocol is a message based protocol that allows
a total of 2032 (= 21 L 16) different messages in the standard format and 512 million (= 2 29-16) different messages
in the extended frame format.

Note: The CAN interface tolerates the extended CAN frame format of 29
identifier bits and gives an acknowledgment. If an error occurs the
receive error counter will be increased, and decreased if the frame is
valid.

MULTICAST FRAME TRANSFER BY ACCEPTANCE
FILTERING
Every CAN Frame is put on the common bus. Each module
receives every frame and filters out the frames which are
not required for the module's task.

BUS SYNCHRONIZATION DURING OPERATION
Resetting the TXEN1 and TXENO bits in Bus Control Register will disable the output drivers and do a resynchronization
to the bus. All other CAN related registers and flags will be
unaffected.

REMOTE DATA REQUEST
A CAN master module has the ability to set a specific bit
c2.Hed th~ Urcm~t~ tr~r.~m:~~:cn rc~'..!~~t t;!t" (RTR)
~
frame. This causes another module, either another master
or a slave, to transmit a data frame after the current frame
has been completed.

::1

Bus synchronization of the device in this case is done in the
following way:
If the output was disabled (TXEN1, TXENO = "0") and either TXEN1 or TXENO, or both are set to 1, the device will
not start transmission or reception of a frame until eleven
consecutive "recessive" bits have been received.

SYSTEM FLEXIBILITY
Additional modules can be added to an existing network
without a configuration change. These modules can either
perform completely new functions requiring new data or process existing data to perform a new function.

A "bus-off" condition will also cause the output drivers Tx1
and TxO to be tristated (independent of the status of TXEN1
and TXENO). The device will switch from "bus off" to "error
active" mode as described under the FMOO-bit description.
(See Can Bus Control register.) This will ensure that the
device is synchronized to the bus, before starting to transmit
or receive.

SYSTEM WIDE DATA CONSISTENCY
As the CAN network is message oriented, a message can
be used like a variable which is automatically updated by the
controlling processor. If any module cannot process information it can send an overload frame. This device is incapable of initiating an overload frame, but will join an overload
frame initiated by another device as required by CAN specifications.

For information on bus synchronization and status of the
CAN related registers after external reset refer to the
RESET section.
ON-CHIP VOLTAGE REFERENCE

NON-DESTRUCTIVE CONTENTION-BASED
ARBITRATION

The on-chip voltage reference is a ratiometric reference.
For electrical characteristics of the voltage reference refer
to the electrical specifications section.

The CAN protocol allows several transmitting modules to
start a transmission at the same time as soon as they monitor the bus to be idle. During the start of transmission every
node monitors the bus line to detect whether its message is
overwritten by a message with a higher priority. As soon as
a transmitting module detects another module with a higher
priority accessing the bus, it stops transmitting its own frame
and switches to receive mode. For illustration see Figure 21.

ANALOG SWITCHES
Analog switches are used for selecting between RxO and
VREF and between Rx1 and VREF.

1-145

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"'1:1'

Basic CAN Concepts (Continued)

11.

AUTOMATIC RETRANSMISSION OF FRAMES

INTRODUCTION

o
......
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If a data or remote frame was overwritten by either a higherprioritized data frame, remote frame, or an error frame, the
transmitting module will automatically retransmit it. This device will handle the automatic retransmission of up to two
data bytes automatically. Messages with more than 2 data
bytes require the user's software to update the transmit registers.

There are basically two different types of frames used in the
CAN protocol.
The data transmission frames are: data/remote frame
The control frames are: error/overload frame

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11.

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Frame Formats

Note: This device can not send an overload frame as a result of not being
able to process all information. However, the device is able to recognize an overload condition and join overload frames initiated by other
devices.

ERROR DETECTION AND ERROR SIGNALING

If no message is being transmitted, i.e., the bus is idle, the
bus is kept at the "recessive" level. Figure 22 and Figure 23
give an overview of the various CAN frame formats.

All messages on the bus are checked by each CAN node
and acknowledged if they are correct. If any node detects
an error it starts the transmission of an error frame.

DATA AND REMOTE FRAME

Switching Off Defective Nodes

Data frames consist of seven bit fields and remote frames
consist of six different bit fields:

There are two error counters, one for transmitted data and
one for received data, which are incremented, depending on
the error type, as soon as an error occurs. If either counter
goes beyond a specific value the node goes to an error
state. A valid frame causes the error counters to decrease.

1. Start of Frame (SO F)
2. Arbitration field
3. Control field (IDE bit, RO bit, and DLC field)

The device can be in one of three states with respect to
error handling:

4. Data field (not in remote frame)
5. CRC field

• Error active
An error active unit can participate in bus communication
and sends an active ("dominant") error flag.

6. ACK field
7. End of Frame (EOF)
A remote frame has no data field and is used for requesting
data from other (remote) CAN nodes. Figure 24 shows the
format of a CAN data frame.

• Error passive
An error passive unit can participate in bus communication. However, if the unit detects an error it is not allowed
to send an active error flag. The unit sends only a passive ("recessive") error flag.

FRAME CODING

• Bus off
A unit that is "bus off" has the output drivers disabled,
i.e., it does not participate in any bus activity.

Remote and Data Frames are NRZ coded with bit-stuffing in
every bit field which holds computable information for the
interface, i.e., Start of Frame arbitration field, control fiE1ld,
data field (if present) and CRC field.

(See ERROR MANAGEMENT AND DETECTION for more
detailed information.)

Error and overload frames are NRZ coded without bit stuffing.

TxPIN
MODULE A
RxPIN

TxPIN
MODULE B
RxPIN

BUS LINE

RECESSIVE DOMINANT MODULE A SUSPENDS TRANSMISSION

FIGURE 21. CAN Message Arbitration

1-146

TL/DD/12067-21

a"tJ

Frame Formats (Continued)

BIT STUFFING

Destuffed Bit Stream

100000x

011111x

After five consecutive bits of the same value, a stuff bit of
the inverted value is inserted by the transmitter and deleted
by the receiver.

Unstuffed Bit Stream

1000001x

0111110x

o.......

x = 10,11

DATA FRAME (number of bits = 44 + aN)

--------------.J

tIl

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tIl

STORED IN BUFFERS

STORED IN TRANSMIT/RECEIVE BUFFERS
BIT STUFFING
TLIDD/12067 -22

REMOTE FRAME (number of bits = 44)

TLIDD/12067·23
A remote frame is identical to a data frame, except that the RTR bit is "recessive", and there is no data field.
IDE

= Identifier Extension Bit

The IDE bit in the standard format is transmitted "dominant", whereas in the extended format the IDE bit is "recessive" and the id is expanded to 29 bits.
r = recessive
d

= dominant

FIGURE 22. CAN Data Transmission Frames

1-147

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Frame Formats (Continued)

D-

1 - - - - - ERROR FRAME

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DATA FRAME OR
REMOTE FRAME

m
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------'~

Iffi~Ort:E~H60ll~OR
FLAG

IERROR FLAG

DELIMITER

INTER-FRAME SPACE OR
OVERLOAD FRAME

IdH+H+1 ~~ H+I+H+I+H

D-

TL/DD/12067-24

An error frame can start anywhere in the middle of a frame.

I-

INTER-FRAME SPACE -

~3r8
INT
SUSPEND
ANY FRAME

':!:
~

.,A--~,::.:
BUS IDLE

TRANSMIT

DATA FRAME OR
REMOTE FRAME ..

14---------.

I+HrlrH+H+I+H+H+H ~~ H+I~I
TL/DD/12067-25

INT = Intermission
Suspend Transmission is only for error passive nodes.

OVERLOAD FRAME

E~~gRObE[f~I¥~ROSR ~R6L~
FLAG
II~R8L~
DELIMITER

OVERLOAD DELIMITER

INTEREt~t~hYJtE.. OR

Idl+H+ldlrlrlrlrlrlrlrlrl

TL/DD/12067-26

An overload frame can only start at the end of a frame.

FIGURE 23. CAN Control Frames

SOF

Arbitration Field
Identifier + RTR

Control
Field

1-Bit

12-Bit

6-Bit

Data Field
(If Present)
n

* Bit

(0,8)

FIGURE 24. CAN Frame Format

1-148

CRC
Field

ACK
Field

EOF

16-Bit

2-Bit

7-Bit

Frame Formats (Continued)

"'C

START OF FRAME (SOF)

INTERFRAME SPACE

The Start of Frame indicates the beginning of data and remote frames. It consists of a single "dominant" bit. A node
is only allowed to start transmission when the bus is idle. All
nodes have to synchronize to the leading edge (first edge
after the bus was idle) caused by SOF of the node which
starts transmission first.

Data and remote frames are separated from every preceding frame (data, remote, error and overload frames) by the
interframe space see Figure 25 and Figure 26 for details.
Error and overload frames are not preceded by an interframe space. They can be transmitted as soon as the condition occurs. The interframe space consists of a minimum of
three bit fields depending on the error state of the node.

ARBITRATION FIELD

These bit fields are coded as follows.

The arbitration field is composed of the identifier field and
the RTR (Remote Transmission Request) bit. The value of
the RTR bit is "dominant" in a data frame and "recessive"
in remote frame.
CONTROL FIELD

DATA FIELD

CRC FIELD

The CRC field consists of the CRC sequence followed by
the CRC delimiter. The CRC sequence is derived by the
transmitter from the modulo 2 division of the preceding bit
fields, starting with the SOF up to the end of the data field,
excluding stuff-bits, by the generator polynomial

x 10

+ x8 +

"'C

Q)
Q)

-'='-

ERROR FRAME.

The Data field consists of the data to be transferred within a
data frame. It can contain 0 to 8 bytes and each byte contains 8 bits. A remote frame has no data field.

x14

o
........

The Error Frame consists of two bit fields: the error flag and
the error delimiter. The error flag field is built up from the
various error flags of the different nodes. Therefore, its
length may vary from a minimum of six bits up to a maximum
of twelve bits depending on when a module is detecting the
error. Whenever a bit error, stuff error, form error, or acknowledgment error is detected by a node, this node starts
transmission of the error flag at the next bit. If a CRC error is
detected, transmission of the error flag starts at the bit following the acknowledge delimiter, unless an error flag for a
previous error condition has already been started. Figure 27
shows how a local fault at one module (module 2) leads to a
12-bit error frame on the bus.

The Data Length Code indicates the number of bytes in the
data field. This Data Length Code consists of four bits. The
data field can be of length zero. The admissible number of
data bytes for a data frame ranges from 0 to 8.

-'='-

The intermission has the fixed form of three "recessive"
bits. While this bit field is active, no node is allowed to start
a transmission of a data or a remote frame. The only action
to be taken is signalling an overload condition. This means
that also an error in this bit field would be interpreted as an
overload condition. Suspend transmission has to be inserted by error-passive nodes that were transmitter for the last
message. This bit field has the form of eight "recessive"
bits. However, it may be overwritten by a "dominant" startbit from another non error passive node which starts transmission. The bus idle field consists of "recessive" bits. Its
length is not specified and depends on the bus load.

The control field consists of six bits. It starts with two bits
reserved for future expansion followed by the four-bit Data
Length Code. Receivers must accept all possible combinations of the two reserved bits. Until the function of these
reserved bits is defined, the transmitter only sends "0" bits.
The first reserved bit (IDE) is actually defined to indicate an
extended frame with 29 Identifier bits if set to "1". CAN
chips must tolerate extended frames, even if they can only
understand standard frames, to prevent the destruction of
an extended frame on an existing network.

x 15

en
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ThA bus lelfel me.y either be "dam!r.2.nt" far ::'.n crrcr-::'.ct:':c
node or "recessive" for an error-passive node. An error active node detecting an error, starts transmitting an active
error flag consisting of six "dominant" bits. This causes the
destruction of the actual frame on the bus. The other nodes
detect the error flag as either the rule of bit-stuffing or the
value of a fixed bit field is destroyed. As a consequence all
other nodes start transmission of their own error flag. This
means, that the error sequence which can be monitored on
the bus has a maximum length of twelve bits. If an error
passive node detects an error it transmits six "recessive"
bits on the bus. This sequence does not destroy a message
sent by another node and is not detected by other nodes.
However, if the node detecting an error was the transmitter
of the frame the other modules will get an error condition by
a violation of the fixed bit or stuff rule. Figure 28 shows how
an error passive transmitter transmits a passive error frame
and when it is detected by the receivers.
After any module has transmitted its active or passive error
flag it waits for the error delimiter which consists of eight
"recessive" bits before continuing.

+ x4 + x3 + 1

The remainder of this division is the CRC sequence transmitted over the bus. On the receiver side the module divides
all bit fields up to the CRC delimiter, excluding stuff-bits, and
checks if the result is zero. This will then be interpreted as a
valid CRC. After the CRC sequence a single "recessive" bit
is transmitted as the CRC delimiter.
ACKFIELD

The ACK field is two bits long and contains the ACK slot and
the ACK delimiter. The ACK slot is filled with a "recessive"
bit by the transmitter. This bit is overwritten with a "dominant" bit by every receiver that has received a correct CRC
sequence. The second bit of the ACK field is a "recessive"
bit called the acknowledge delimiter. As a consequence the
acknowledge flag of a valid frame is surrounded by two "recessive" bits, the CRC-delimiter and the ACK delimiter.
EOF FIELD

The End of Frame field closes a data and a remote frame. It
consists of seven "recessive" bits.

1-149

m
"11:1'

co
co
DO
o
.......

"11:1'

Frame Formats (Continued)
overload frame can only be sent after the end of frame
(EOF) field and in this way destroys the fixed form of the
intermission field.

OVERLOAD FRAME
Like an error frame, an overload frame consists of two bit
fields: the overload flag and the overload delimiter. The bit
fields have the same length as the error frame field: six bits
for the overload flag and eight bits for the delimiter. The

ORDER OF BIT TRANSMISSION
A frame is transmitted starting with the Start of Frame, sequentially followed by the remaining bit fields. In every bit
field the MSB is transmitted first.

CD
D-

OLDFRA_M_E-+______IN_T_E_RF_R_A~ME--SP-A-C-E----_;

INTERMISSION
THREE BIT TIMES

/-4-----~1

NEW FRAME

BUS IDLE
t1
TLlDD/12067-27

t1 is the first possible start bit of a new frame

FIGURE 25. Interframe Space for Nodes Which Are Not Error Passive or Have Been Receiver for The Last Frame

OLD FRAME
INTERMISSION

INTERFRAME SPACE

NEW FRAME

SUSPEND TRANSMISSION

BUS IDLE

EIGHT BIT TIMES
I

TLlDD/12067·28

t1 - any module can start transmission except the error passive module which has transmitted the last frame.

FIGURE 26. Interframe Space for Nodes Which Are Error Passive and Have Been Transmitter for The Last Frame

BUS LINE

TxPIN

--1l

---.m

5 BIT

MODULE 1
RxPIN

TxPIN

RxPIN

MODULE 3
RxPIN

ERROR FLAG

IERROR DELIMITER

ERROR DELIMITER

BIT ERROR FLAG:

I
I

fTI
, i

TxPIN

Jil
I

MODULE 2

IERROR DELIMITER

12 BIT ERROR FLAG

~ISSING

PULSE

I
I

ERROR FLAG

IERROR DELIMITER

~--------

~~------~I--------~
I

module 1 = error active transmitter detects bit error at 12
module 2 = error active receiver with a local fault at t1
module 3 = error active receiver detects stuff error at 12

FIGURE 27. Error Frame-Error Active Transmitter

1-150

TLlDD/12067-29

C')

Frame Formats (Continued)

"C
0)

mat. Note that while the CAN specification allows valid standard identifiers only in the range OxOOO to Ox7EF the device
will allow identifiers to Ox7FF.

FRAME VALIDATION
Frames have a different validation point for transmitter and
receivers. A frame is valid for the transmitter of a message,
if there is no error until the end of the last bit of End of
Frame field. A frame is valid for a receiver, if there is no
error until and including the end of the penultimate bit of the
End of Frame.

There are three more items that should be taken into consideration to avoid unrecoverable collision on the bus:
• Within one system each message must be assigned to a
unique identifier. This is to prevent bit errors, as one
module may transmit a "dominant" data bit while the other is transmitting a "recessive" data bit. Which could
happen if two or more modules may start transmission of
a frame at the same time and all win arbitration.

FRAME ARBITRATION AND PRIORITY
Except for an error passive node which transmitted the last
frame, all nodes are allowed to start transmission of a frame
after the intermission, which can lead to two or more nodes
starting transmission at the same time. To prevent a node
from destroying another node's frame it monitors the bus
during transmission of the identifier field and the RTR-bit. As
soon as it detects a "dominant" bit while transmitting a "recessive" bit it releases the bus, immediately stops transmission and starts receiving the frame. This causes no data or
remote frame to be destroyed by another. Therefore the
highest priority message with the identifier OxOOO out of
Ox7EF (including the remote data request (RTR) bit) always
gets the bus. This is only valid for standard CAN frame forBUS LINE

TxPIN
MODULE 1
RxPIN

C')
........
C')

co
co
~
to

C')

• Data frames with a given identifier and a non-zero data
length code may be initiated by one node only. Otherwise, in worst case, two nodes would count up to the
bus-off state, due to bit errors, if they would always start
transmitting the same 10 with different data.
• Every remote frame should have a system-wide data
length code (OLC). Otherwise two modules starting
transmission of a remote frame at the same time will overwrite each other's OLC which results in bit errors.

--1

6 BIT ERROR FLAG

--1 :

6 BIT ERROR FLAG I

..1

co
to
~

IERROR DELIMITER

8 BIT ERROR DELIMITER

I
I

I
MliSING PULSE

TxPIN

ERROR FLAG

ERROR DELIMITER

MODULE 2
RxPIN

TxPIN
MODULE 3
RxPIN

ERROR FLAG

-.J:

ERROR DELIMITER

:11-..-----...1
I

, \2

,\1

TL/DD/12067-30

= error passive transmitter detects bit error at t2

module 1

module 2 = error active receiver with a local fault at t1

= error passive receiver detects stuff error at t2

module 3

FIGURE 28. Error Frame-Error Passive Transmitter

IDENTIFIER

CONTROL

DATA

CRC

I~o

lif~

g~~

~illl]]]]]]]]]]I]]

~ffi

n]]]]]]]] ~~ ]]]]]]] m]]]]]]]]]]]]]] n

FIRST BIT TRANSMITTED
TL/DD/12067-31

FIGURE 29. Order of Bit Transmission within a CAN Frame

1-151

m
"'I:t'

Frame Formats (Continued)

D..

ACCEPTANCE FILTERING·

o
......
o
m
"'I:t'

Every node performs acceptance filtering on the identifier of
a data or a remote frame to filter out the messages which
are not required by the node. In this way only the data of
frames which match the acceptance filter is stored in the
corresponding data buffers. However, every node which is
not in the bus-off state and has received a correct CRC-sequence acknowledges the frame.

co
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CD
D..

o
o

• Bus Off
A unit that is "bus off" has the output drivers disabled,
Le., it does not participate in any bus activity. A device is
bus off when the transmit error counter is greater than
255. A bus off device will become error active again in
one of two ways depending on which mode is selected
by the user through the Fault Confinement Mode select
bit (FMOD) in the CAN Bus Control Register (CBUS).
Setting the FMOD bit to "0" (default after power on reset) will select the Standard Fault Confinement mode. In
this mode the device goes from "bus off" to "error active" after monitoring 128*11 recessive bits (including
bus idle) on the bus. This mode has been implemented
for compatibility reasons with existing solutions. Setting
the FMOD bit to "1" will select the Enhanced Fault Confinement mode. In this mode the device goes from "bus
off" to "error active" after monitoring 128 "good" messages, as indicated by the reception of 11 consecutive
"recessive" bits including the End of Frame. The enhanced mode offers the advantage that a "bus off" device (Le., a device with a serious fault) is not allowed to
destroy any messages on the bus until other devices
could at least transmit 128 messages. This is not guaranteed in the standard mode, where a defective device
could seriously impact bus communication. When the device goes from "bus off" to "error active", both error
counters will have the value "0".

ERROR MANAGEMENT AND DETECTION
There are multiple mechanisms in the CAN protocol, to detect errors and to inhibit erroneous modules from disabling
all bus activities.
The following errors can be detected:
• Bit Error
A CAN device that is sending also monitors the bus. If
the monitored bit value is different from the bit value that
is sent, a bit error is detected. The reception of a "dominant" bit instead of a "recessive" bit during the transmission of a passive error flag, during the stuffed bit stream
of the arbitration field or during the acknowledge slot, is
not interpreted as a bit error.
• Stuff Error
A stuff error is detected, if the bit level after 6 consecutive bit times has not changed in a message field that has
to be coded according to the bit stuffing method.

In each CAN module there are two error counters to perform a sophisticated error management. The receive error
counter (REG) is 7-bit wide and switches the device to the
error passive state if it overflows. The transmit error counter
(TEG) is 8 bits wide. If it is greater than 127 the device is
also switched to the error passive state. As soon as the
TEC overflows the device is switched bus-off, Le., it does
not participate in any bus activity.

• Form Error
A form error is detected, if a fixed frame bit (e.g., CRC
delimiter, ACK delimiter) does not have the specified value. For a receiver a "dominant" bit during the last bit of
End of Frame does NOT constitute a frame error.
• Bit CRC Error
A CRC error is detected if the remainder of the CRC
calculation of a received CRC polynomial is non-zero.

The counters are modified by the device's hardware according to the following rules:

• Acknowledgment Error
An acknowledgment error is detected whenever a transmitting node does not get an acknowledgment from any
other node (Le., when the transmitter does not receive a
"'dominant" bit during the ACK frame).

TABLE VI. Receive Error Counter Handling
Condition

The device can be in one of three states with respect to
error handling:
• Error active
An error active unit can participate in bus communication
and sends an active ("dominant") error flag.
• Error passive
An error passive unit can participate in bus communication. However, if the unit detects an error it is not allowed
to send an active error flag. The unit sends only a passive ("recessive") error flag. A device is error passive
when the transmit error counter is greater than 127 or
when the receive error counter is greater than 127. A
device becoming error passive sends an active error flag.
An error passive device becomes error active again
when both transmit and receive error counter are less
than 128.

1-152

Receive
Error Counter

A receiver detects a Bit Error
during sending an active error
flag.

Increment by 8

A receiver detects a "dominant"
bit as the first bit after sending an
error flag.

Increment by 8

After detecting the 14th
consecutive "dominant" bit
following an active error flag or
overload flag or after detecting
the 8th consecutive "dominant"
bit following a passive error flag.
After each sequence of additional
8 consecutive "dominant" bits.

Increment by 8

Any other error condition (stuff,
frame, CRC, ACK).

Increment by 1

A valid reception or transmission.

Decrement by 1 if
Counter is not 0

(')

Frame Formats (Continued)
Transmit Error
Counter

Condition
A transmitter detects a Bit Error
during sending an active error
flag.

(')
""

(TEC OR REC) > 127 .......
ERROR ACTIVE

(TEC AND REC)

< 128

ERROR PASSIVE

Any other error condition (stuff,
frame, CRC, ACK)

Increment by 8

A valid reception or transmission.

Decrement by 1 if
Counter is not 0

TEC> 255

128 occurrences of
11 'recessive' bits

BUS Ofr

TL/DD/12067 -32

FIGURE 30. CAN Bus States
SYNCHRONIZATION
Every receiver starts with a "hard synchronization" on the
falling edge of the SOF bit. One bit time consists of four bit
segments: Synchronization segment, propagation segment,
phase segment 1 and phase segment 2.

• An ACK-error occurs in an error passive device and no
"dominant" bits are detected while sending the passive
error flag. This does not lead to an incrementation of the
TEC.

A falling edge of the data signal should be in the synchronization segment. This segment has the fixed length of one
time quanta. To compensate the various delays within a network the propagation segment is used. Its length is programmable from 1 to 8 time quanta. Phase segment 1 and
phase segment 2 are used to resynchronize during an active frame. The length of these segments is from 1 to 8 time
quanta long.

• If only one device is on the bus and this device transmits

Two types of synchronization are supported:

• A stuff error occurs during arbitration, when a transmitted
"recessive" stuff bit is received as a "dominant" bit. This
does not lead to an incrementation of the TEC.

a message, it will get no acknowledgment. This will be
detected as an error and the message will be repeated.
When the device goes "error passive" and detects an
acknowledge error, the TEC counter is not incremented.
Therefore the device will not go from "error passive" to
th~ "bt::; CHII :;t~tv duo to 5uch a condiUon.

Hard synchronization is done with the falling edge on the
bus while the bus is idle, which is then interpreted as the
SOF. It restarts the internal logic.
Soft synchronization is used to lengthen or shorten the bit
time while a data or rflmotfl fr::lml'l i'3 rlO'cIO'ived. Whenever a
falling edge is detected in the propagation segment or in
phase segment 1, the segment is lengthened by a specific
value, the resynchronization jump width (see Figure 31).

PRESCALER
CLOCK (PSC)

ONE TIME QUANTA

"coco

(')

Special error handling for the TEC counter is performed in
the following situations:

0l:Io

Increment by 8

0l:Io

(')

Increment by 8

11 tq

"co

Figure 30 shows the connection of different bus states according to the error counters.

TABLE VII. Transmit Error Counter Handling

B)
1 to Btq

PHASE SEGMENT 1

PHASE SEGMENT 2

1 to B tq

SAMPLE POINT

TRANSMISSION POINT
A) synchronization segment
B) propagation segment

FIGURE 31. Bit Timing

1-153

TL/DD/12067-33

o
m
oo:t

Frame Formats (Continued)

a..
o
.......

BUS SIGNAL

co
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o
m
oo:t

''''_ _..;..._ _ _ _ _ _ _ _

~---------.........-

co
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a..
o
o

PREVIOUS
BIT

NEXT BIT '
... NORMAL-BIT TIME

PREVIOUS
BIT

NEXT BIT

BIT TIME LENGTHENED WITH RESYNC .
TLlDDf12067 -34

FIGURE 32. Resynchronlzatlon 1

,'------

BUS SIGNAL

PREVIOUS
BIT

PHASE SEG 2

PHASE SEG 1

NEXT BIT

... NORMAL-BIT TIME

PREVIOUS
BIT

B) ,

PHASE SEC 1

PHASE SEC 2

BIT TIME SHORTENED BY RESYNC

NEXT BIT

.1
TLlDDf12067-35

FIGURE 33. Resynchronlzatlon 2
Additionally the comparator output can be connected internally to the L-Port pin of the respective positive input and
thereby generate an interrupt using the L-Port interrupt
structure (neg/pos. edge, enable/disable).

A falling edge lies in the phase segment 2 (as sho"Vn in
Figure 33) it is shortened by the resynchronization jump
width. Only one resynchronization is allowed during one bit
time. The sample point lies between the two phase segments and is the point where the received data is supposed
to be valid. The transmission point lies at the end of phase
segment 2 to start a new bit time with the synchronization
segment.

Note that in Figure 34, pin L6 has a second alternate function of supporting the PWMO output. The comparator 2 output MUST be dis~bled in order to use PWMO output on L6.
Figure 34 shows the Comparator Block Diagram.

Comparators

COMPARATOR CONTROL REGISTER (CMPLS) (0003)

The device has two differential comparators. Port L is used
for the comparators. The output of the comparators is multiplexed out to two pins. The following are the Port L assignments:

These bits reside in the Comparator Register

LO Comparator 1 positive input

The register contains the following bits:

L1 Comparator 1 negative input

CMP1 EN Enables comparator 1 ("1" = enable). If comparator 1 is disabled the associated L-pins can be
used as standard I/O.

L2 Comparator 1 output
L3 Comparator 2 negative input
L4 Comparator 2 positive input

,CMP1 RD Reads
comparator
1
output
internally
(CMP1 EN = 1) Read-only, reads as a "0" if comparator not enabled.

L5 Comparator 2 negative input
L6 Comparator 2 output

1-154

a"0

Comparators (Continued)
CMPlOE Enables comparator 1 output ("1" = enable),
CMP1 EN bit must be set to enable this function.

CMP2SEL Selects which L port pin to use for comparator2
negative input. (CMP2SEL = 0 selects L5;
CMP2SEL = 1 selects pin L3).

CMP2EN Enables comparator 2 ("1" = enable). If comparator 2 is disabled the associated L-pins can be
used as standard 1/0.

The Comparator Select/Control bits are cleared on RESET
(the comparator is disabled). To save power, the program
should also disable the comparator before the device enters
the HALT mode.

CMP2RD Reads
comparator
2
output
internally
(CMP2EN = 1) Read-only, reads as a "0" if comparator not enabled.

The Comparator rise and fall times are symmetrical. The
user program must set up the Configuration and Data registers of the L port correctly for comparator Inputs/Output.

CMP20E Enables comparator 2. output ("1" = enable),
CMP2EN bit must be set to enable this function.
L1DO------------~

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.......

a"0
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oI:loo

~--~--------------.ICMPIRDI

LODO---------4~----+-----~~

L2D04-------------~

en
co

1----------. LO Input function

1+--------1------ L2

Output function

~--_.--------------_.ICMP2RDI

L4~~----+__4~----+-----_r~

1---------. L4 Input function
L6

Output function

L6DO.-----r-----~

from PWMO
output

TLlDD/12067-36

Note: the SHADED area shows logic from PWM Timer. Comparator 2 output (CMP20E) must be disabled in order to use PWMO output.

FIGURE 34. Comparator Block

1-155

til
~

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.......

til
~

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CD

PLUS arrangement with the internal clock source is called
the. Master mode of operation. Similarly, operating the
MICROWIRE arrangement with an external shift clock is
called the Slave mode of operation.

Detection of Illegal Conditions
The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.

The CNTRl register is used to configure and control the
MICROWIRE/PlUS mode. To use the MICROWIRE/PlUS,
the MSEl bit in the CNTRl register is set to one. In the
master mode the SK clock rate is selected by the two bits,
SlO and Sl1, in the CNTRl register. Table VIII details the
different clock rates that may be selected.

Reading of undefined ROM gets zeroes. The opcode for
software interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt,
thus signaling that an illegal condition has occurred.
The subroutine stack grows down for each call Oump to
subroutine), interrupt, or PUSH, and grows up for each return or POP. The stack pointer is initialized to RAM location
02F Hex during reset. Consequently, if there are more returns than calls, the stack pointer will point to addresses
030 and 031 Hex (which are undefined RAM). Undefined
RAM from addresses 030 to 03F Hex is read as all 1's,
which in turn will cause the program to return to address
7FFF Hex. This is an undefined ROM location and the instruction fetched (all O's) from this location will generate a
software interrupt signaling an illegal condition.

MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the
MICROWIRE/PlUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PlUS
mode either as a Master or as a Slave. Figure 35 shows
how two COP888 family microcontrollers and several peripherals may be interconnected using the MICROWIREI
PLUS arrangements.

Thus, the chip can detect the following illegal conditions:
1. Executing from undefined ROM.

Warning:

2. Over "POP"ing the stack by having more returns than
calls.

The SIO register should only be loaded when the SK clock
is low. loading the SIO register while the SK clock is high
will result in undefined data in the SIO register. SK clock is
normally low when not shifting.
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PlUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is
low.

When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that
following reset, but might not contain the same program
initialization procedures).

MICROWIRE/PLUS
MICROWIRE/PlUS is a serial synchronous communications interface. The MICROWIRE/PlUS capability enables
the device to interface with any of National Semiconductor's
MICROWIRE peripherals (Le., AID converters, display drivers, E2PROMs etc.) and with other microcontrollers which
support the MICROWIRE interface. It consists of an 8-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK). Figure 34
shows a block diagram of the MICROWIRE/PlUS logic.

The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIREI

1-156

(')

MICROWIRE/PLUS (Continued)

"'0
0)

t------.....

(')

"(')

INTERRUPT

a"'0

~~==~=_------+SO

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~

H-----SI

(')

++SK

TLIOOI 12067 -37

FIGURE 35. MICROWIRE/PLUS Block Diagram

8 - BIT
A/D CONVERTER

I/O
LINES

LCD
DIGITAL
DRIVER
COP472

EEPROM

COPS
(MASTER)

VF
DISPLAY
DRIVER

I/o
LINES
COPS
(SLAVE)

DI SK
SII+.....;L--t'-+---'--+-+----+-+---~I___1

SK
TLl00/12067-38

FIGURE 36. MICROWIRE/PLUS Application

1-157

-.:t"

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co
DO

Memory Map

MICROWIRE/PLUS (Continued)

All RAM, ports and registers (except A and PC) are mapped
into data memory address space.

TABLE VIII. MICROWIRE/PLUS
Master Mode Clock Selection

o........
o

SL1

-.:t"

co
(Q

D-

SLO

Address

x tc

00 to 2F

4 X tc

30 to 7F

8 X tc

80 t09F

Where tc is the instruction cycle clock
AO
A1
A2
BO
B1
B2

MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bit in the Port G configuration reg,
ister. Table V summarizes the settings required to enter the
Slave mode of operation.

B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
COtoC7
C8
C9
CA
CB
CC
CDtoCF

The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and. the. sequence may be
repeated.
Alternate SK Phase Operation
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register.
In both the modes the SK is normally low. In the normal
mode data is shifted in on the rising edge of the SK clock
and the data is shifted out on the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK clock in the normal mode. In the alternate SK phase
mode the SIO register is shifted on the rising edge of the SK
clock.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alternate SK clock. The SKSEL is mapped into the G6 configuration bit. The SKSEL flag will power up in the reset condition,
.
selecting the normal SK signal.
TABLE IX. MICROWIRE/PLUS Mode Selection
G4 (SO)
Config.
Bit

G5 (SK)
Conflg.
Bit

G4
Fun.

G5
Fun.

Operation

Int.
SK

MICROWIRE/PLUS
Master

TRISTATE

Int.
SK

MICROWIRE/PLUS
Master

Ext.
SK

MICROWIRE/PLUS
Slave

TRISTATE

Ext.
SK

MICROWIRE/PLUS
Slave

This table assumes that the control flag MSEL is set.

1-158

Contents
On-Chip RAM bytes (48 bytes)
Unused RAM Address Space (Reads As All
Ones)
Unused RAM Address Space (Reads
Undefined Data)
PSCAL, PWM timer Prescaler Register
RLON, PWM timer On-Time Register
PWMCON, PWM Control Register
TXD1, Transmit Data
TXD2, Transmit 2 Data
TDLC, Transmit Data Length Code and
Identifier Low
TID, Transmit Identifier High
RXD1, Receive Data 1
RXD2, Receive Data 2
RIDL, Receive Data Length Code
RID, Receive Identify High
CSCAL, CAN Prescaler
CTIM, Bus Timing Register
CBUS, Bus Control Register
TCNTL, Transmit/Receive Control Register
RTSTA T Receive/Transmit Status Register
TEC, Transmit Error Count Register
REC, Receive Error Count Register
Reserved
Reserved
WKEDG, MIWU Edge Select Register
WKEN, MIWU Enable Register
WKPND, MIWU Pending Register
Reserved
Reserved
Reserved

~------------------------------------------------------------------------'O

Memory Map
Address

Contents

DO
01
02
03
04
05
06
07to DB
DC
OOtoOF

PORTLO, Port L Data Register
PORTLC, Port L Configuration Register
PORTLP, Port L Input Pins (Read Only)
CMPSL, Comparator control register
PORTGO, Port G Data Register
PORTGC, Port G Configuration Register
PORTGP, Port G Input Pins (Read Only)
Reserved
PORTO, Port 0 output register
Reserved for Port 0

EO-E5
E6

EE
EF

Reserved
T1 RBLO, Timer T1 Autoload Register Lower
Byte
T1 RBHI, Timer T1 Autoload Register Upper
Byte
ICNTRL, Interrupt Control Register
SIOR, MICROWIRE/PLUS Shift Register
TMR1 LO, Timer T1 Lower Byte
TMR1 HI, Timer T1 Upper Byte
T1 RALO, Timer T1 Autoload Register Lower
Byte
T1 RAHI, Timer T1 Autoload Register T1 RA
Upper Byte
CNTRL, Control Register
PSW, Processor Status Word Register

Fa to FB
FC
FO
FE
FF

On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
Reserved (Note A)

E7
E8
E9
EA
EB
EC
ED

Immediate

(Continued)

a""C

The instruction contains an 8-bit immediate field as the operand.

Short Immediate

o
.......
o

This addressing mode is used with the, Load B Immediate
instruction. The instruction contains a 4·bit immediate field
as the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumuiator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.

CD
~

""C
CD
CD
~

'TRANSFER OF CONTROL ADDRESSING MODES
Relative
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
program location. JP has a range from -31 to + 32 to allow
a 1-byte relative jump (JP + 1 is implemented by a NOP
instruction). There are no "pages" when using JP, since all
15 bits of PC are used.
Absolute
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any location in the current 4k program memory segment.
Absolute Long
This mode is used with the JMPL and JSRL instructions,
with the instruction field of 15 bits replacing the entire 15
bits of the program counter (PC). This allows jumping to any
location in the current 4k program memory space.
Indirect
This mode is used with the JIO instruction. The contents of
the accumulator are used as a partial address (lower 8 bits
of PC) for accessing a location in the program memory. The
(;O(lttmlS oilhis lJ'UYl<1'II IIII:HIIU'Y IO(;i:1lioll ::i1j/VIj i:1::i i:11Ji:1rlii:11
address (lower 8 bits of PC) for the jump to the next instruction.

Note: Reading memory locations 30-7F Hex will return all ones. Reading
other unused memory locations will return undefined data.
Note A: In devices with more than 128 bytes of RAM, location OFF is used
as the Segment register to switch between different Segments of RAM
memory. In this device location OFF can be used as a general purpose, on·
chip RAM mapped register. However, the user is advised that caution should
be taken in porting software utilizing this memory location to a chip with
more than 128 bytes of RAM.

Note: The VIS is a speCial case of the Indirect Transfer of Control addressing mode, where the double byte vector associated with the interrupt
is transferred from adjacent addresses in the program memory into
the program counter (PC) in order to jump to the associated interrupt
service routine.

Addressing Modes
There are ten addressing modes, six for operand addressing and four for transfer of control.
OPERAND ADDRESSING MODES

Register Indirect
This is the "normal" addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.
Register Indirect (with auto post Increment or decrement of pointer)
This addressing mode is used with the LO and X instructions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that
automatically post increments or decrements the B or X register after executing the instruction.
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.

1-159

~
co
~

o.......
o

Instruction Set
Symbols

[B]

Memory Indirectly Addressed by B
Register

[X]

Memory Indirectly Addressed by X
Register

8-Bit Accumulator Register

8-Bit Address Register

Direct Addressed Memory

8-Bit Stack Pointer Register

Mem

Direct Addressed Memory or [B)

Meml

Direct Addressed Memory or [B) or
Immediate Data

'01::1'

CD
D.

. 15-Bit Program Counter Register

Upper 7 Bits of PC

Lower 8 Bits of PC

Imm

8-Bit Immediate Data

1-Bit of PSW Register for Carry

Reg

1-Bit of PSW Register for Half Carry

GIE

1-Bit of PSW Register for Global·
Interrupt Enable

Interrupt Vector Upper Byte

Interrupt Vector Lower Byte

Bit

1-160

Bit Number (0 to 7)

Meml
Do next if lower 4 bits of B '=1= Imm
Reg ~ Reg - 1, Skip if Reg =0
1 to bit, Mem (bit = 0 to 7 immediate)
Otobit, Mem
If bit in A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
A~Mem

A~[X]
A~Meml

A~[X]
B~lmm

Mem~lmm
Reg~lmm

A~ [B],(B~B ± 1)
A~[X],(X~ ±1)

A ~ [B], (B ~ B ± 1)
A~ [X],(X~X ± 1)
[B] ~ Imm,(B~B ± 1)
A~O

A~A+

A~A-1

A ..;...- ROivi (PU,A)
A ~ BCD correction of A (follows ADC, SUBC)
C-+ A7 -+ ... -+ AO-+ C
C~A7~ ... ~AO~C
A7 ... A4~A3 ... AO
C~1,HC~1
C~O,HC~O

IF C is true, do next instruction
If C is not true, do next instruction
SP~SP + 1,A~ [SP]
[SP] ~A,SP~SP-1

Vector to Interrupt Service Routine
Jump absolute Long
Jump absolute
Jump relative short
Jump SubRoutine Long
Jump SubRoutine
Jump InDirect
RETurn from subroutine
RETurn and SKip
RETurn from Interrupt
Generate an Interrupt
No OPeration

1-161

PU ~ [VU], PL ~ [VL]
PC ~ ii (ii = 15 bits, Ok to 32k)
PCg ... 0 ~ i (i = 12 bits)
PC ~ PC + r (r is -31 to +32, except 1)
[SP] ~ PL, [SP-1] ~ PU,SP-2, PC ~ ii
[SP] ~ PL, [SP-1] ~ PU,SP-2, PCg ... 0 ~ i
PL ~ ROM (PU,A)
SP + 2, PL ~ [SP], PU ~ [SP-1]
SP + 2, PL ~ [SP],PU ~ [SP-1]
SP + 2, PL ~ [SP],PU ~ [SP-1),GIE ~ 1
[SP] ~ PL, [SP-1] ~ PU, SP-2,PC ~ OFF
PC~PC + 1

(.)

en
~

Instruction Execution Time

D-

Most instructions are single byte (with immediate addressing mode instructions taking two bytes).

co
co

o
(.)
.....
(.)

Most single byte instructions take one cycle time to execute.
See the BYTES and CYCLES per INSTRUCTION table for details.

Bytes and Cycles per Instruction

The following table shows the number of ~ytes and cycles for each instruction in the format of byte/cycle.

D-

Instructions Using A and C

Arithmetic and Logic Instructions

(.)

[B)

Direct

Immed.

ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4

2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2

SBIT
RBIT
IFBIT

1/1
1/1
1/1

3/4
3/4
3/4

RPNO

1/1

CLRA
INCA
DECA
LAID
DCORA
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ

1/3

Transfer of Control
Instructions

1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2

JMPL
JMP
JP
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP

Memory Transfer Instructions
Register
Indirect

Direct Immed.

[B)

[X]

XA,·

1/1

1/3

2/3

LDA,·

1/1

1/3

2/3

2/2

[B+,B-]

[X+,X-]

1/2

1/3

. 1/2

1/3

LDB,lmm

1/1

(IFB

< 16)

LOB,lmm

2/3

(IF B

LDMem,lmm

2/2

3/3

LDReg,lmm

2/3

IFEQMO,lmm

3/3

• = > Memory location addressed by B or X or directly.

1-162

15)

3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5

117
1/1

COP888 Family Opcode Table
UPPER NIBBLE

JP -15 JP -31

LD OFO, #i

DRSZOFO

RRCA

ADCI-.,
#i

ADCA,[B]

IFBIT ANDSZ
O,[B]
A, #i

LD B,#OF

IFBNEO

JSR
xOOO-xOFF

JMP
xOOO-xOFF

JP JP - 15 0
17

JP -14 JP -30

LDOF1, #i

DRSZOF1

SUBCA,
#i

SUBA,[B]

IFBIT
1,[B]

LDB,#OE

IFBNE 1

JSR
x100-x1FF

JMP
x100-x1FF

JP
18

JP -13 JP -29

LDOF2, #i

DRSZOF2

XA,
[X

XA,
[B

IFEQ/I,
#i

IFEQA,[B]

IFBIT
2,[B]

LD B,#OD

IFBNE2

JMP
x200-x2FF

JP JP
19

JP -12 JP -28

LDOF3, #i

DRSZOF3

XJA,
[X-]

XJA,
[B-]

IFGTI-.,
#i

IFGTA,[B]

IFBIT
3,[B]

JSR
x200-x2FF

LD B,#OC

IFBNE3

JSR
x300-x3FF

JMP
x300-x3FF

JP
20

JP - 12 3

JP -11

JP -27

LDOF4, #i

DRSZOF4

VIS

LAID

ADDA,
#i

ADDA,[B]

IFBIT
4,[B]

CLRA

LD B,#OB

IFBNE4

JSR
x400-x4FF

JMP
x400-x4FF

JP
21

JP - 11

JP -10 JP -26

LD OF5, #i

DRSZOF5

RPND

JID

ANDA,
#i

ANDA,[B]

IFBIT SWAPA LD B,#OA
5,[B]

IFBNE5

JSR
x500-x5FF

JMP
x500-x5FF

JP
22

JP - 10 5

JP -9

JP -25

LDOF6, #i

DRSZOF6

XA,[X]

XORA,
#i

XORA,[B]

IFBIT DCORA LD B,#09
6,[B]

IFBNE6

JSR
x600-x6FF

JMP
x600-x6FF

JP
23

JP - 9

JP -8

JP -24

LDOF7, #i

DRSZOF7

XA,[B]

ORA,;!i

ORA,[B]

IFBIT PUSHA
7,[B]

LD B,#08

IFBNE7

JSR
x700-x7FF

JMP
x700-x7FF

JP
24

JP - 8

JP -7

JP -23

LDOF8, #i

DRSZOF8

NOP

RLCA

LDA,#i

IFC

SBIT
O,[B]

RBIT
O,[B]

LD B,#07

IFBNE8

JSR
x800-x8FF

JMP
x800-x8FF

JP
25

JP - 7

JP -6

JP -22

LDOF9, iFi

DRSZOF9

IFNE
A,[B]

IFEQ
Md,#i

IFNE
A,#i

IFNC

SBIT
1,[B]

RBIT
1,[B]

LDB,#06 . IFBNE 9

JSR
x900-x9FF

JMP
x900-x9FF

JP
26

JP - 6

JP -5

JP -21

LDOFA, #i

DRSZOFA

LDA,
[X

LDA,
[B

LD[B
ti

INCA

SBIT
2,[B]

RBIT
-2,[B]

LD B,#05

IFBNEOA

JMP
JP
JSR
xAOO-xAFF xAOO-xAFF 27

JP - 5

JP -4

JP -20

LDOFB, #i

DRSZOFB

LdA,
[X-]

LdA;
[B-]

LD [B-1.
#i

- DECA

SBIT
3,[B]

RBIT
3,[B]

LD B,#04

IFBNEOB

JSR
xBOO-xBFF

JMP
JP
xBOO-xBFF 28

JP - 4

JP -3

JP -19

LDqFC, #i

DRSZOFC LD Md,#i

JMPL-

. XA,Mc

. POPA

SBIT
4,[B]

RBIT
4,[B]

LD B,#03

IFBNEOC

JMP
JP
JSR
xCOO-xCFF xCOO-xCFF 29

JP -3

JP -2

JP -18

LDOFD, #i

DRSZOFD

JP -1

JP -17

LDOFE, #i

DRSZOFE

JP -0

JP -16

LDOFF, #;

DRSZOFF

CJ.)

JP - 14

=- 13

:E
m
::c

m
m
rm

JSRL

LDA,Md

RETSK

SBIT
5,[B]

RBIT
5,[B]

LD B,#02

IFBNEOD

JMP
JP
JSR
xDOO-xDFF xDOO-xDFF 30

JP - 2

LDA,[X]

LDA,[B]

LD[B],i'i

RET

SBIT
6,[B]

RBIT
6,[B]

LD B,#01

IFBNEOE

JSR
xEOO-xEFF

JMP
JP
xEOO-xEFF 31

JP - 1

LDB,#i

RETI -

SBIT
7,[B]

RBIT
7,[B]

LD B,#OO

IFBNEOF

JSR
xFOO-xFFF

JMP
JP
xFOO-xFFF 32

JP - 0

DIR·

where,

i is the immediate data
Md is a directly addressed memorY location
* is an unused opcode

- I

Note: The opcode 60 Hex is also the opcode for IFBIT #i,A
-

- - -

OSP88dOO/OSP89dOO

m
-.::t'
co
co

a..
o
........
o

-.::t'

co
CD

a..

Mask Options
Emulator memory operations for program memory include
single line assembler, disassembler, view, change and write
to file. Data memory operations include fill, move, compare,
dump to file, examine and modify. The contents of any
memory space can be directly viewed and modified from the
corresponding window.
The iceMASTER comes with an easy to use window interface. Each window can be sized, highlighted, color-controlled, added, or removed completely. Commands can be
accessed via pull-down-menus and I or redefinable hot keys.
A context sensitive hypertext/hyperlinked on-line help system explains clearly the options the user has from within
any window.
The ice MASTER connects easily to a personal computer via
the standard COMM port and its 115.2 kBaud serial link
keeps typical program download time shorter.

The COP684BC and COP884BC mask programmable options are shown below. The options are programmed at the
same time as the ROM pattern submission.
OPTION 1: CLOCK CONFIGURATION
= 1 Crystal Oscillator (CKI/10)
G7 (CKO) is clock generator output to
crystal/ resonator
CKI is the clock input
OPTION 2: HALT
= 1 Enable HALT mode
= 2 Disable HALT mode
OPTION 3: BOND OUT
=1 28-Pin SO
OPTION 4: ON-CHIP RESET
= 1 Enable ON-CHIP RESET

The following tables list the emulator and probe cards ordering information.

= 2 Disable ON-CHIP RESET
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7. The CKI input frequency is divided down
by 10 to produce the instruction cycle clock (1 ltd.

Emulator Ordering Information
Part
Number
IM-COP8

Development Support

1400/1:1:

IN-CIRCUIT EMULATOR ,
The MetaLink iceMASTERTM-COP8 Model 400 In-Circuit
Emulator for the COP8 family of microcontrollers features
high-performance operation, ease of use, and an extremely
flexible user-interface or maximum productivity. Interchangeable probe cards, which connect to the standard
common base, support the various configurations and packages of the COP8 family.

IM-COP81

400/2:1:

The iceMASTER provides real time, full speed emulation up
to 10 MHz, 32 kbytes of emulation memory and 4k frames of
trace buffer memory. The user may define as many as 32k
trace and break triggers which can be enabled, disabled, set
or cleared. They can be simple triggers based on code address, direct address, opcode value, opcode class or immediate operand. Complex breakpoints can be ANDed and
ORed together. Trace information consists of address bus
values, opcodes and user selectable probe clips status (external event lines). The trace buffer can be viewed as raw
hex or as disassembled instructions. The probe clip bit values can be displayed in binary, hex or digital waveform formats.

Current
Version

Description
MetaLink base unit incircuit emulator for all
COP8 devices, symbolic
debugger software and
RS232 serial interface
cable, with 11 OV @ 60 Hz
Power Supply.
MetaLink base unit incircuit emulator for all
COP8 devices, symbolic
debugger software and
RS232 serial interface
cable, with 220V @ 50 Hz
Power Supply.

Host Software:
Ver. 3.3 Rev. 5,
Model File
Rev 3.050.

:!:These parts include National's COPS Assembler/Linker/Librarian Package
(COPS-DEV-IBMA).

Probe Card Ordering Information

Voltage
Range

Emulates

Part Number

Package

MHW-884BC28D5PC

28 DIP

4.5V-5.5V COP884BC

MHW-SOIC28

28 SO

28-PinSOIC Adaptor Kit

MACRO CROSS ASSEMBLER
National Semiconductor offers a relocatable COP8 macro
cross assembler. It runs on industry standard compatible
PCs and supports all of the full-symbolic debugging features
of the MetaLink ice MASTER emulators.

The iceMASTER's performance analyzer offers a resolution
of better than 6 JLs. The user can easily monitor the time
spent executing specific portions of code and find "hot
spots" or "dead code". Up to 15 independent memory areas based on code address or label ranges can be defined.
Analysis results can be viewed in bar graph format or as
actual frequency count.

Assembler Ordering Information
Part Number
COP8-DEV-IBMA

1-164

Description
COP8
Assemblerl
LinkerI Librarian
for IBM®
PC/XT®, AT® or
compatible.

Manual
424410632-001

o
o

Development Support (Continued)

"tJ
0)

SINGLE CHIP EMULATOR DEVICE

INFORMATION SYSTEM .

The COP8 family is fully supported by single chip form. fit
and function emulators. For more detailed information refer
to the emulation deviced specific datasheets and the form.
fit. function emulator selection table below.

The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities could be found. The minimum requirement for accessing the Dial-A-Helper is a Hayes compatible
modem.

COP684BC/COP884BC Ordering Information
Device Number

Clock
Option

Package

Emulates

COP884BCMHEA-X·

Crystal

28LCC

COP884BC

RIC

o.......
o

o"tJ
co
co
~

If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.

'Check with the local sales office about the availability.

DIAL·A·HELPER
ORDER PIN: MOLE·DIAL·A·HLP

Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Bulletin Board Information system.

Information System Package contains:
Dial-A-Helper Users Manual
Public Domain Communications Software

PROGRAMMING SUPPORT
Programming of the single chip emulator devices is supported by different sources.

FACTORY APPLICATIONS SUPPORT

The following programmers are certified for programming
EPROM versions of COP8:

Dial-A-Helper also provides immediate factor applications
support. If a user has questions. he can leave messages on
our electronic bulletin board. which we will respond to.
Voice:

(800) 272-9959

Modem: CANADA/U.S.: (800) NSC-MICRO
(800) 672-6427
Baud:
Set-Up:

14.4k
Length: 8-Bit
Parity: None
Stop Bit: 1

Operation:

24 Hrs .• 7 Days

EPROM Programmable Information
Manufacturer
and Product

U.S. Phone
Number

Europe Phone
Number

MetaLinkDebug Module

(602) 926-0797

Germany:
+ 49-8141-1 030

Hong Kng:
+852-737·
1800

XeltekSuperpro

(408) 745-7974

Germany: + 49
2041-684758

Singapore:
+ 65-276-6433

BP MicrosystemsTurpro

(800) 225-2102

Germany: + 49
2041·684758

Hong Kong:
+852-3880629

Data I/O-Unisite
-System 29
-System 39

(800) 322-8246

Europe:
+ 31-20-622866
Germany:
+ 49-89-858020

Japan:
+ 81-33-4326991

Abcom-COP8
Programmer
System GeneralTurpro-1-FX
-APRO

Asia Phone
Number

Europe: + 49-89
808707
(408) 263-6667

Switzerland:
+41-31
.921-7844

1-165

Taiwan:
+ 886-2-9173005

;..J

o
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co

c..
o
.......

IfI

National Semiconductor

..J

oco COP688CL/COP684CL, COP888CL/COP884CL,
co

COP988CL/COP984CL Single-Chip
o microCMOS Microcontroller
o
0)

c..

.......

..J

o
"'1:1'

co
co

c..
oo
.......
..J

oco

General Description
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconductor's M2CMOSTM process technology. The COP888CL is a
member of this expandable 8-bit core processor family of
microcontrollers.
(Continued)

co
co

Features

•
•
•
•
•
•
•
•
•

c..

.......

..J

o"'1:1'

co
CD

c..

o.......
oco

..J

co
CD

c..

Low cost 8-bit microcontroller
Fully static CMOS, with low current drain
Two power saving modes: HALT and IDLE
1 tJ-s instruction cycle time
4096 bytes on-board ROM
128 bytes on-bo.ard RAM
Single supply operation: 2.SV-6V
MICROWIRE/PLUSTM serial 1/0
WATCHDOGTM and Clock Monitor logic

• Idle Timer
• Multi-Input Wakeup (MIWU) with optional interrupts (8)
• Ten multi-source vectored interrupts servicing
- External Interrupt
- Idle Timer TO
- Timers TA, TB (Each with 2 Interrupts)
- MICROWIRE/PLUS
- Multi-Input Wake Up
- Software Trap
- Default VIS

• Two 16-bit timers, each with two 16-bit registers sup~
porting:
- Processor Independent PWM mode
- External Event counter mode
- Input Capture mode
• 8-bit Stack Pointer SP (stack in RAM)
• Two 8-bit Register Indirect Data Memory Pointers
(B and X)
• Versatile instruction set
• True bit manipulation
• Memory mapped 1/0
• BCD arithmetic instructions
• Package:
- 44 PLCC with 39 1/0 pins
- 40 N with 33 1/0 pins
- 28 SO or 28 N, each with 23 1/0 pins
• Software selectable 1/0 options
- TRI-STATE® Output
- Push-Pull Output
- Weak Pull Up Input
- High Impedance Input
• Schmitt trigger inputs on ports G and L
• Temperature ranges: O°C to + 70°C,
-40°C to + 85°C,
- 55°C to + 125°C
• One-Time Programmable (OTP) emulation device
• Fully supported by Metalink's Development Systems

Block Diagram
r-~--------------~-----~

CPU
REGISTERS
TLlDD/9766-1

FIGURE 1. Bloc Diagram

1-166

(')

General Description

(Continued)

"coco

It is a fully static part, fabricated using double-metal silicon
gate microCMOS technology. Features include an a-bit
memory mapped architecture, MICROWIRE/PLUS serial
I/O, two 16-bit timer/counters supporting three modes
(Processor Independent PWM generation, Exteirnal Event
counter, and Input Capture mode capabilities), and two power savings modes (HALT and IDLE), both with a multi-

(')

"'(')

co
~

(')

Connection Diagrams

"'(')

"coco

(')

RESET

"'(')

-40
3

-40

Dual-ln-L1ne Package

Plastic Chip Carrier

CKI

vee
10

GNO

RESET

GND

-4-4 pin

1-4

0-4

1-4

PLCC

co
co
~

(')

"'(')

"co

co
co

(')

"'(')

UNUSED

::::; ~ :3 ~ ~ l3

::!i

'" ,....
..........
TL/OO/9766-2

Top View
Order Number COP688CL-XXX/V, COP888CL-XXX/V or
COP988CL-XXX/V
See NS Plastic Chip Package Number V44A

UNUSED

Ll
L2

L6
L5

"co
co
~

(')

TLIDD/9766-4

Top View
Order Number COP688CL-XXX/N, COP888CL-XXX/N or
COP988CL-XXX/N

Dual-In-Llne Package
G4

Order Number COP688CL-XXXIN, COP884CL-XXX/N or
COP984CL-XXX/N
See NS Molded Package Number N288

G2
Gl

Order Number COP684CL-XXX/WM,
COP884CL-XXX/WM or COP984CL-XXX/WM
See NS Surface Mount Package Number M288

RESET

GNO
03

28 pin..
DIP/SO

01
DO
L7

TLIOO/9766-5

Top View
FIGURE 2. Connection Diagrams

1-167

...J

o
:

Connection Diagrams (Continued)

o.......
...J
oco

Port

Type

1/0

a..

L2
L3
L4
L5
L6 .
L7
GO
G1
G2
G3
G4
G5
G6
G7

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WOOUT
I/O
I/O
I/O
I/O
I
I/CKO

o.......

...J

o
"II:t'

co
co

a..
oo
.......
...J

oco

co
co

a..
o

o.......
o"II:t'

...J

a..
o
o
.......
...J

oco
co

a..
oo

DO
01
02
03
10
11
12
13
14
15
16
17
04
05
06
07
CO
C1
C2
C3
C4
C5
C6
C7
Unused·
Unused·

0
0
0
0

I
I
I
I
I
I
I

Pinouts for 28·, 40· and 44·Pln Packages
28·Pln
Alt. Fun
Alt. Fun
Pack.
MIWU
11
MIWU
12
MIWU'
13
MIWU
14
MIWU
T2A
15
MIWU
T2B
16
MIWU
17
MIWU
18
INT
25
26
T1B
27
T1A
28
SO
1
SK
2
SI
3
HALT
4
RESTART
19
20
21
22
7
8

9
10

40·Pln
Pack.
17
18
19
20
21
22
23
24
35
36
37
38
3
4
5
6

44·Pln
Pack;
17
18
19
20
25
26
27
28
39
40
41
42
3
4
5
6

25
26
27
28
9
10
11
12
13
14

29
30
31
32
9
10
11
12
13
14
15
16
33
34
35
36
43
44
1
2
21
22
23
24

29
30
31
32
39
40
1
2

0
0
0
0

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Vee

6
23
5
24

GNO
CKI
RESET

• = On the 40-pin package Pins 15 and 16 must be connected to GND.

1-168

16
15
8
33
7
34

8
37
7
38

(')

o"'C

Absolute Maximum Ratings
110 rnA
Total Current out of GNO Pin (Sink)
Storage Temperature Range
- 65°C to + 140°C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

If Military/Aerospace. specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
7V
Supply Voltage {Ved
Voltage at Any Pin
-0.3V to Vee + 0.3V
Total Current into Vee Pin (Source)
100 rnA

0)
Q)
Q)

(')

r.......

(')

o"'C
0)
Q)

(')

DC Electrical Characteristics COP98XCL: O°C :5: TA :5: + 70°C unless otherwise specified
Parameter

Conditions

2.5
4.0

Power Supply Ripple (Note 1)

Peak-to-Peak

Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz

Vee
Vee

= 6V, tc = 1 p's
= 4V, tc = 2.5,..,s

Vee
Vee

= 6V, CKI = 0 MHz
= 4V, CKI = 0 MHz

Vee

= 6V, tc = 1 ,..,s

IDLE Current
CKI = 10 MHz

Input Pullup Current

<0.7
<0.4

Sink
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)

Units

(')

Q)
Q)
Q)

4.0
6.0

V
V

(')

0.1 Vee

(')

12.5
2.5

rnA
rnA

Q)
Q)

8
5

,..,A
,..,A

3.5

rnA

r.......

o"'C
~

(')

r.......

(')

o"'C
(0
Q)
Q)

r.......

(')

0.2 Vee

V
V

0.2 Vee

V
V

0.2 Vee

V
V

0.8 Vee

o"'C
(0
Q)
~

0.7 Vee

0.7 Vee
Vee

= 6V

-1

ILA.

Vee

= 6V, VIN = OV

-40

-250

,..,A

0.35 Vee

G and L Port Input Hysteresis
Output Current Levels
o Outputs
Source

Max

(')

Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage

Typ

"'C

Operating Voltage
COP98XCL
COP98XCLH

HALT Current (Note 3)

Min

r.......

Vee
Vee
Vee
Vee

=
=
=
=

4V, VOH = 3.3V
2.SV, VOH = 1.8V
4V, VOL = 1V
2.5V, VOL = O.4V

-0.4
-0.2
10
2.0

Vee
Vee
Vee
Vee
Vee
Vee

=
=
=
=
=
=

4V, VOH = 2.7V
2.5V, VOH = 1.8V
4V, VOH = 3.3V
2.5V, VOH = 1.8V
4V, VOL = O.4V
2.5V, VOL = 0.4V

-10
-2.5
-0.4
-0.2
1.6
0.7

rnA
rnA
rnA
rnA
-100
-33

p.A
p.A
rnA
rnA
rnA
rnA

Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee, Land GO-G5 configured as
outputs and set high. The D port set to zero. The clock monitor is disabled.

1-169

(')

..J

o
~

co
Q)

DC Electrical Characteristics O°C s: TA s: + 70°C unless otherwise specified (Continued)

c..

Parameter

.......

TRI-STATE Leakage

o
co

Allowable Sink/Source
Current per Pin
o Outputs (Sink)
All others

..J

co
Q)

c..
o
.......

Conditions

Maximum Input Current
without Latchup (Note 4)

TA = 25°C

co
co

RAM Retention Voltage, Vr

500 ns Rise
and Fall Time (Min)

c..
o
o
.......
..J

oco
co
co

c..

o
~

c..
o

'"
..J
o
co
co

o
o

JJ-A

15 .
3

rnA
rnA

±100

rnA

1000

AC Electrical Characteristics DoC s: TA s: + 70 e unless otherwise specified
0

Parameter
Instruction Cycle Time (to>
Crystal or Resonator
R/C Oscillator

Conditions

Min

4V s: VeeS: 6V
2.5V s: Vee < 4V
4V s: Vee s: 6V
2.5V s: Vee < 4V

1
2.5
3
7.5

4V s: Vee s: 6V
2.5V s: Vee < 4V
4V s: Vee s: 6V
2.5V s: Vee < 4V

200
500
60
150

Typ

Max

Units

DC
DC
DC
DC

JJ-s
JJ-s
JJ-s
JJ-s

Inputs
tSETUP

c..

Units

Load Capacitance on 02

Max

Input Capacitance

o.......
..J

Typ

-1

..J

o
~

'-"in

Vee =.6.0V

tHOLO
Output Propagation Delay (Note 5)
tpD1, tpoo
SO,SK
All Others

ns
ns
ns
ns

RL = 2.2k, CL = 100 pF
4V s: Vee s: 6V
2.5V s: Vee < 4V
4V s: Vee s: 6V
2.5V s: Vee < 4V

0.7
1.75
1
2.5

. JJ-s
JJ-s,
JJ-s
JJ-s

220

ns
ns
ns

20
56

MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tupo)
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

1
1
1
1

tc
tc

Reset Pulse Width

JJ-S

Pins G6 and RESET are designed with a high voltage inpu't network for factory testing. These pins allow input voltages greater than Vcc and the pins will
have sink current to Vcc when biased at voltages greater than Vce (the pins do not have source current when biased at a voltage below Vee>. The effective
resistance to Vee is 7500 (typical). These two pins will not latch up. The voltage at tM pins must be limited to less than 14V.
Note 5: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 4:

1-170

(')

a"tJ

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
7V
Voltage at Any Pin
-0.3V to Vee + 0.3V
Total Current into Vee Pin (Source)
100mA

110 rnA
Total Current out of GND Pin (Sink)
- 65°C to + 140°C
Storage Temperature Range
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

DC Electrical Characteristics COP88XCL: Parameter
Operating Voltage

Min
2.5

Power Supply Ripple (Note 1)

Peak-to-Peak
Vee = 6V, tc = 1 p,s
Vee = 4V, tc = 2.5 p,s

HALT Current (Note 3)

Vee = 6V, CKI = 0 MHz

IDLE Current
CKI = 10 MHz

Vee = 6V, tc = 1 p,s

0.1 Vee

12.5
2.5

rnA
rnA

p,A

3.5

rnA

0.2 Vee

Q)
Q)
Q)

(')

a"tJ
Q)
Q)

0l:Io
(')

........

(')

V
V

Q)
Q)

(')

........

(')

0.7 Vee
0.2 Vee

V
V

a"tJ
<0

0l:Io

0.2 Vee

V
V

p,A

-250

p,A

0.35 Vee

0.7 Vee

Vee = 6V, Y,N = OV

-40

TRI-STATE Leakage

(')

a"tJ

Input Pullup Current

Sink (Push-Pull Mode)

Units

0.8 Vee

-1

Source (Push-Pull Mode)

........

Max

a"tJ

Vee = 6V

All Others
Source (Weak Pull-Up Mode)

Hi-Z Input Leakage

Sink

........

Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low

Output Current Levels
o Outputs
Source

a"tJ

Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz

G and L Port Input Hysteresis

Typ

........

(')

0l:Io
(')

40°C ~ TA ~ + 85°C unless otherwise specified

Conditions

Q)
Q)

(')

.---

Vee
Vee
Vee
Vee

=
=
=
=

4V, VOH = 3.3V
2.5V, VOH = 1.8V
4V, VOL = 1V
2.5V, VOL = O.4V

-0.4
-0.2
10
2.0

Vee
Vee
Vee
Vee
Vee
Vee

=
=
=
=
=
=

4V, VOH = 2.7V
2.5V, VOH = 1.8V
4V, VOH = 3.3V
2.5V, VOH = 1.8V
4V, VOL = O.4V
2.5V, VOL = O.4V

-10
-2.5
-0.4
-0.2
1.6
0.7

-100
-33

p,A
p,A
rnA
rnA
rnA
rnA

-2

p,A

Vee = 6.OV

rnA
rnA
rnA
rnA

Note 1: Rate of voltage change must be less then O.S V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee. Land GO-GS configured as
outputs and set high. The 0 port set to zero. The clock monitor is disabled.

1-171

(')

...J

o
~

co
en

DC Electrical Characteristics

o
......

...J

oco

co
en

o
......
...J
o
~
co
co

Parameter

+ 85°C unless otherwise specified (Continued)

Conditions

Min

Max

Units

15
3

mA
mA

,±100

Typ

Allowable Sink/Source
Current per Pin
D Outputs (Sink)
All others
Maximum Input Current
without Latchup (Note 4)

TA = 25°C

RAM Retention Voltage, Vr

500 ns Rise
and Fall Time (Min)

Input Capacitance

......
o

Load Capacitance on 02

-40°C::;; TA ::;;

2
7

1000

...J

co
co
co

AC Electrical Characteristics
Parameter

o
......
...J
o
~
co

Instruction Cycle Time (tc)
Crystal or Resonator
R/C Oscillator

o
o
......

tSETUP

tHOLD

+ 85°C unless otherwise specified

Conditions

Min

4V::;; Vee::;; 6V
2.5V ::;; Vee < 4V
4V::;; Vee::;; 6V
2.5V ::;; Vee < 4V

1
2.5
3
7.5

4V::;; Vee::;; 6V
2.5V ::;; Vee < 4V
4V::;; Vee::;; 6V
2.5V ::;; Vee < 4V

200
500
60
150

Typ

Max

Units

DC
DC
DC
DC

p,s
p,s
p,s
p,s

Inputs

...J

oco

-40°C::;; TA ::;;

Output Propagation Delay (Note 5)
tpD1, tpDo
SO,SK
All Others

ns
ns
ns
ns

RL = 2.2k, CL = 100 pF
4V::;; Vee::;; 6V
2.5V ::;; Vee < 4V
4V::;; Vee::;; 6V
2.5V ::;; Vee < 4V

0.7
1.75
1
2.5

p,s
p,s
p,s
p,s

220

ns
ns
ns

20
56

MICROWIRE Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tUPD)
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

1
1
1
1

tc
tc
tc
tc

Reset Pulse Width

p,s

Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than Vee and the pins will
have sink current to Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vecl. The effective
resistance to Vee is 7500 (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: The output propagation delay is 'referenced to the end of the instruction cycle where the output change occurs.

1-172

o
o

Electrical Specifications

Note: Absolute maximum ratings indicate limds beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

DC ELECTRICAL SPECIFICATIONS
COP688CL Absolute Specifications
Supply Voltage (Vee)
7V
Voltage at Any Pin
-0.3V to Vee + 0.3V
Total Current into Vee Pin (Source)
90 rnA
Total Current out of GND Pin (Sink)
100mA
Storage Temperature Range

o
'"

o"C
en

DC Electrical Characteristics COP68XCL: -55°C ~ TA ~
Conditions

Operating Voltage
Power Supply Ripple (Note 1)

Peak-to-Peak
Vee
Vee

= 5.5V. tc = 1 J-Ls
= 5.5V. tc = 2.5 J-Ls

HALT Current (Note 3)

Vee

= 5.5V. CKI = 0 MHz

IDLE Current
CKI = 10 MHz
CKI = 4MHz

Vee
Vee

= 5.5V. tc = 1 J-Ls
= 5.5V. tc = 2.5 J-Ls

o
'"
o

+ 125°C unless otherwise specified
Min

Typ

4.5

Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz

Max

Units

5.5

0.1 Vee

12.5
5.5

rnA
rnA

J-LA

3.5
2.5

rnA
rnA

Q)
Q)
Q)

o
r-

o
'"
o
"C

Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low

<10

Q)
Q)
~

oro
'"

o"C
CD

Q)
Q)

0.2 Vee

V
V

0.2 Vee

V
V

0.2 Vee

V
V

-5

J-LA

-35

-400

J-LA

0.35 Vee

0.8 Vee

o
'"
o
"C
CD

0.7 Vee

Hi-Z Input Leakage

Vcc = 5.5'1

Input Pullup Current

Vee

= 5.5V. VIN = OV

G and L Port Input Hysteresis
Output Current Levels
o Outputs
Source
Sink
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage

o
r-

Q)
~

- 65°C to + 150°C

Parameter

Q)
Q)

Vee
Vee

= 4.5V. VOH = 3.8V
= 4.5V. VOL = 1.0V

-0.4
9

Vee
Vee
Vee
Vee

=
=
=
=

-9.0
-0.4
1.4
-5.0

4.5V. VOH
4.5V. VOH
4.5V. VOL
5.5V

= 3.8V
= 3.8V
= O.4V

Note 1: Rate

rnA
rnA
-140

+5.0

J-LA
rnA
rnA
J-LA

of voltage change must be less then 0.5 Vlms.
Supply current is measured after running 2000 cycles with a square wave eKI input. CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee. Land GO-G5 configured as
outputs and set high. The D port set to zero. The clock monitor is disabled.
Note 2:

1-173

o
r-

.;.J

o"'1::1'

DC Electrical Characteristics

-55°C:>; TA :>;

+ 25°C unless otherwise specified (Continued)

D-

Parameter

';.J

o
co
co

D-

...I

o
"'1::1'

co
co
DO

...I

o
co
co
co
O

D-

Conditions

RAM Retention Voltage,,vr

500 ns Rise
and Fall Time (Min)

Max

Units

12
2.5

rnA
mA

150

rnA

2.0

Input Capacitance
Load Capacitance on D2

1000

Note 1: Rate of voltage change must be less then 0.5 Vlms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input. CKO open. inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied.to VCC. Land G ports in the TRI·
STATE mode and tied to ground. all outputs low and tied to ground. The Clock Monitor and the comparators are disabled.

AC Specifications for COP688CL

o
"'1::1'

AC Electrical Characteristics

Typ

Maximum Input Current
without Latchup (Note 4)

...I

Min

Allowable Sink/Source
Current per Pin
D Outputs (Sink)
All others

-55°C

~ TA ~ + 125°C unless otherwise specified

D-

Parameter

Instruction Cycle Time (tc)
Crystal, Resonator, or
External Oscillator
RIC Oscillator (div-by 10)

Inputs

'...I

o
co
co

D-

tSETUP
tHOLD
Output Propagation Delay (Note 5)
tpD1, tpDO
SO,SK
All Others

Conditions

Vee ~ 4.5V

Min

Typ

Max

Units

p's

Vee ~ 4.5V

p's

Vee ~ 4.5V
Vee ~ 4.5V

200
60

ns
ns

RL = 2.2k, CL = 100 pF
Vee ~4.5V
Vee ~ 4.5V

MICROWIRE Setup Time (tUWS)
MICROWIRE Hold Time(tUWH)
MICROWIRE Output Propagation Delay (tUPD)

0.7
1

p.s
p.s

220

ns
ns
ns

20
56

Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer,lnput High Time
Timer Input Low Time

1
1
1
1

tc
tc
tc
tc

Reset Pulse Width

p.S

Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than Vcc and the pins will
have sink current to Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vecl. The effective
resistance to Vee is 7500 (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

1-174

Typical Performance Characteristics (-40°C ~ TA ~

+85°C)

Halt-Ioo

"'0

Idle-IOO (Crystal Clock Option)

"<
-3
0
_0

1."

1.2

0.6
V'
0... JI'
2.5

bZf'

10MHz

?t, ... 4 ~Hz
I

5.5

o"'0

o ~~

3.5

4.5

5.5

2.5

3.5

Vee (V)

".5

Vee (V)
TLIDD/9766-27

TLIDD/9766-2B

6
~
~

10 MHz

......

...

2.5

V
,/

''i

"<
-3

100

r.......

f--+--+-~+-~f--+---I

"'0

o"'0

5.5

VOH (V)

TLIDD/9766-29

Port L/C/G Push-Pull Source Current
I

......

"......

\
\

.'}.

,'I
\

2.5

45
.. 0

Vee = 6.0V
'

"<
-5

}3 10 1--+__"+-"",
...V_ee-t-_4_.5_V+---":..n_-f

..J

..s>

'I, '\. '\ \

r---:::::~=2.5JV \~ \

_ "~,

10
'/

o P'

.. ..

3.5

o 0.5

, ... ...
...

.. J.
Vee = S.OV

I J
I

O~~... ~
_f'_~_~~_~'
VOH (V)

TL/DD/9766-32

20f--+-~~",-+--1--1-+1---I

1.5

0.5

I I

Port D Sink Current

...............

- . ....

TL/DD/9766-31

25r--__,.--r-~-r--__,.--,

Vee = 2.SV -

VOL (V)

Port D Source Current

..:

Vee =4.5V

'I',

. . ~-r-

... ...

I I

','

VOH (V)

T-

--:: ~Vee=2.5VI' ,

I
Vee = 6.0V I
I

," I

"~,

J .. 'i"-

Vee = .. ·5V

or-

Port L/C/G Push-Pull Sink Current

Vee = 6.0V -

TL/DD/9766-30

.a::.

Vee (V)

.....

o
o

r.......
20

4.5

o~~-~-~~~~-~

CO
CO

60 1---+-.3,.......'

c..

3.5

CO
CO

.a::.

~ ~MHz

o
o

120 r--__,.--r-,.--r-----.---,

::>

"MHz ... '

1-- ......

.......

,
".

CO
CO

or-

"'0

Port L/C/G Weak Pull-Up
Source Current

Dynamlc-IOO vs Vee
(Crystal Clock Option)

o
r.......

/" r'.... '

0.2
2

en
.a::.

V .;'.

f""""

....., < .. ooC

0.8

o"'0

1 MHZ}

+85 0 C /

o
o

r.......

1.8
1.6

CO
CO

Vee =4.5V

f- Vee = 2.5V

1 1.5 2 2.5 3 3.5 4 4.5
VOL (V)

TLIDD/9766-33

TLIDD/9766-34

1-175

~ r-----------------------------------------------------------------------------~

o
-.::r

AC Electrical Characteristics

SK~

co
en
c..

o
......

tuws

oco

It-,

(Continued)

Port L supports Multi-Input Wakeup (MIWU) on all eight
pins. L4 and L5 are used for the timer input functions T2A
and T2B.

tUWH

Port L has the following alternate features:

Sl~

co
en
c..

!:::::i

o
......

SO -------------

t UPD

o-.::r

co
co
c..

o
......
oco
~

co
co
c..

o
......
~

o-.::r

co
CD
c..

......
~

oco

co
CD
c..

TLlDD/9766-26

FIGURE 2. MICROWIRE/PLUS Timing

Pin Descriptions
Vee and GND are the power supply pins.

The device contains three bidirectional8-bit I/O ports (C, G
and L), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports G and L),
output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these 1/
o ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also
reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O
ports.) Figure 3 shows the I/O port configurations. The
DATA and CONFIGURATION registers allow for each port
bit to be individually configured under software control as
shown below:
DATA
Register

0
1
1

1
0
1

MIWU
MIWU

MIWU

MIWU or T2A

L5
L6

MIWU orT2B

MIWU

CONFIGURATION
Register

PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.

Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin or general purpose input (R/C clock configuration), the associated bits in the data and configuration
registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits
will return zeros.

Port Set-Up

Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output

Writing a "1" to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set
high, enables the clock start up delay after HALT when the
R/C clock configuration is used.
Config Reg.

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

Port G has the following alternate features:
GO
INTR (External Interrupt Input)

TL/DD/9766-6

FIGURE 3. 110 Port Configurations

1-176

T1 B (Timer T1 Capture Input)

G3
G4

T1A (Timer T1 I/O)
SO (MICROWIRETM Serial Data Output)

SK (MICROWIRE Serial Clock)

SI (MICROWIRE Serial Data Input)

tables for the lAID instruction, jump vectors for the JID instruction, and interrupt vectors for the VIS instruction). The
program memory is addressed by the 15-bit program counter (PC). All interrupts vector to program memory location
OFF Hex.

Pin Descriptions (Continued)
Port G has the following dedicated functions:
G1

WDOUT WATCHDOG and/or Clock Monitor
dedicated output

CKO Oscillator dedicated output or general
purpose input

DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data
and Pin), the control registers, the MICROWIRE/PLUS SID
shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer).
Data memory is addressed directly by the instruction or indirectly by the B, X and SP pointers.

Port C is an 8-bit I/O port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated
pins will return unpredictable values.
Port I is an 8-bit Hi-Z input port. The 40-pin device does not
have a full complement of Port I pins. Pins 15 and 16 on this
package must be connected to GND.

The device has 128 bytes of RAM. Sixteen bytes of RAM
are mapped as "registers" at addresses OFO to OFF Hex.
These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and
skip if zero) instruction. The memory pointer registers X, SP,
and B are memory mapped into this space at address locations OFC to OFE Hex respectively, with the other registers
(other than reserved register OFF) being available for general usage.

The 28-pin device has four I pins (10, 11, 14, 15). The user
should pay attention when reading port I to the fact that 14
and 15 are in bit positions 4 and 5 rather than 2 and 3.
The unavailable pins (14-17) are not terminated i.e., they are
floating. A read operation for these unterminated pins will
return unpredictable values. The user must ensure that the
software takes into account by either masking or restricting
the accesses to bit operations. The unterminated port I pins
will draw power only when addressed.

The instruction set permits any bit in memory to be set,
reset or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, //0 bits and register bits can be
directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.

Port 0 is an 8-bit output port that is preset high when RESET goes low. The user can tie two or more 0 port outputs
(except 02) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the
external loads on this pin must ensure that the output voltages stay
above 0.8 VcC to prevent the chip from entering speCial modes. Also
keep the external loading on D2 to less than 1000 pF.

Note: RAM contents are undefined upon power-up.

Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for Ports l, G, and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WATCHDOG and/or Clock Monitor error
output pin. Port 0 is initiAlizerJ hiah with RESET. The PC,
PSW, CNTRl. ICNTRl, and T2CNTRl control registers are
cleared. The Multi-Input Wakeup registers WKEN, WKEDG,
and WKPND are cleared. The Stack Pointer, SP, is initialized to 06F Hex.

Functional Description
The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store memory (RAM). Both ROM and RAM have their own separate
addressing space with separate address buses. The architecture, though based on Harvard architecture, permits
CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or
shift operation in one instruction (td cycle time.

The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, and with both
the WATCHDOG service window bits set and the Clock
Monitor bit set. The WATCHDOG and Clock Monitor detector circuits are inhibited during reset. The WATCHDOG service window bits are initialized to the maximum WATCHDOG
service window of 64k te clock cycles. The Clock Monitor bit
is initialized high, and will cause a Clock Monitor error following reset if the clock has not reached the minimum specified frequency at the termination of reset. A Clock Monitor
error will cause an active low error output on pin G 1. This
error output will continue until 16-32 te clock cycles following the clock frequency reaching the minimum specified value, at which time the G1 output will enter the TRI-STATE
mode.

There are five CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
Pl is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.
All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).

The external RC network shown in Figure 4 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.

PROGRAM MEMORY

Program memory consists of 4096 bytes of ROM. These
bytes may hold program instructions or constant data (data

1-177

o
o""0
m

0)
0)

or
.......
o
o

""0

r
.......

o""0
0)
0)
0)

or
.......
o
o

""0
0)
0)

o
o

r
.......

o""0
(0
0)
0)

o
o

r.......

o""0
(0
0)

...I

o
..::t
co

Reset (Continued)

TABLE B. RC Oscillator Configuration, TA = 25°C

D-

P
0

o
......

w
E
R

...I

o
co

S
U
P
P
L
Y

D-

o
......

...I

o
..::t
co
co

Vee

~~D

• R

COPBaa
RESET

::: ~C

o
......
...I
o
co
co
co
DO

o
......
...I

o
..::t

co
CD

D-

o
......
...I
o
co
co
CD

D-

CKI Freq
(MHz)

Instr. Cycle
(/-Ls)

Conditions

3.3
5.6
6.8

82
100
100

2.2 to 2.7
1.1 to 1.3
0.9 to 1.1

3.7 to 4.6
7.4 to 9.0
8.8 to 10.8

Vee = 5V
Vee = 5V
Vee = 5V

GND

Current Drain

Power Supply Rise Time

The total current drain of the chip depends on:

FIGURE 4. Recommended Reset Circuit

1. Oscillator operation mode-11
2. Internal switching current-12

D-

C
(pF)

Note: 3k :<:: R :<:: 200k, 50 pF :<:: C :<:: 200 pF

TL/DD/9766-7

RC > 5

R
(kn)

Oscillator Circuits

3. Internal leakage current-13

The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input frequency is divided down by 10 to produce the instruction
cycle clock (1 ltd.

5. DC current caused by external input
not at Vee or GND-15
6. Clock Monitor current when enabled-16

Figure 5 shows the Crystal and RIC diagrams.

Thus the total current drain, It, is given as

4. Output source current-14

It = 11 + 12 + 13 + 14 + 15 + 16
To reduce the total current drain, each of the above components must be minimum.

CRYSTAL OSCillATOR
CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.
Table A shows the component values required for various
standard crystal values .

The chip will draw more current as the CKI input frequency
increases up to the maximum 10 MHz value. Operating with
a crystal network will draw more current than an external
square-wave. Switching current, governed by the equation
below, can be reduced by lowering voltage and frequency.
Leakage current can be reduced by lowering voltage and
temperature. The other two items can be reduced by carefully designing the end-user's system.
12 = C x V x f

RIC OSCillATOR
By selecting CKI as a single pin oscillator input, a single pin
RIC oscillator circuit can be connected to it. CKO is available as a general purpose input, andl or HALT restart pin.
Table B shows the variation in the oscillator frequencies as
functions of the component (R and C) values.

CKI

CKO

where C = equivalent capacitance of the chip
V = operating voltage
f = CKI frequency

t~~--"""t'"I

CKI

R2
....

CKO

Control Registers

• Rl

CNTRl Register (Address X'OOEE)
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
SL1 & SLO Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
External interrupt edge polarity select
IEDG
(0 = Rising edge, 1 = Falling edge)
Selects G5 and G4 as MICROWIRE/PLUS
MSEL
Signals SK and SO respectively

-~C

TLIDD/9766-9

TLIDD/9766-B

FIGURE 5. Crystal and RIC Oscillator Diagrams
TABLE A. Crystal Oscillator Configuration, TA = 25°C
R1
(kil)

o
o

R2
(Mil)

C1
(pF)

C2
(pF)

CKI Freq
(MHz)

Conditions

30
30
200

30-36
30-36
100-150

10
4
0.455

Vee = 5V
Vee = 5.0V
Vee = 5V

1-178

(")

Control Registers
T1 CO

(Continued)

"tJ

Timer T1 Start/Stop control in timer
modes 1 and 2

JLWEN

Enable MICAOWIAE/PLUS interrupt

Timer T1 Underflow Interrupt Pending Flag in
timer mode 3

TOEN

Timer TO Interrupt Enable (Bit 12 toggle)

TOPND

Timer TO Interrupt pending

lPEN

Q)
Q)

(")

JLWPND MICAOWIAE/PLUS interrupt pending

r.......

(")

T1 C1

Timer T1 mode control bit

T1 C2

Timer T1 mode control bit

l Port Interrupt Enable (Multi-Input Wakeup/lnterrupt)

T1 C3

Timer T1 mode control bit

Bit 7 could be used as a flag

I T1C31 T1C21 T1C1 I T1CO I MSEl IIEDG I Sl1
Bit7

I Unused I LPEN I TOPND TOEN I p.WPND I p.WEN I T1 PNDB I T1 ENB I

BitO

PSW Register (Address X'OOEF)

T2CNTRl Register (Address X'OOC6)

The PSW register contains the following select bits:
Global interrupt enable (enables interrupts)

EXEN

Enable external interrupt

BUSY

MICAOWIAE/PlUS busy shifting flag

EXPND

External interrupt pending

T1 ENA

Timer T1 Interrupt Enable for Timer Underflow
or T1 A Input capture edge

Carry Flag

Half Carry Flag

Bit7

BitO

The Half-Carry bit is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and AC (Aeset
Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and AC instructions, ADC,
SUBC, AAC and AlC instructions affect the 'carry and Half
Carry flags.

"tJ
Q)
Q)
Q)

r.......

(")

T2PNDB Timer T2 Interrupt Pending Flag for T2B capture edge

Q)
Q)

T2ENA

I HC I C I T1 PNDA I T1 ENA I EXPND I BUSY I EXEN I GIE I

Timer T2 Interrupt Enable for T2B Input capture
edge

T2ENB

T1 PNDA Timer T1 Interrupt Pending Flag (Autoreload AA
in mode 1, T1 Underflow in Mode 2, T1 A capture edge in mode 3)

(")

The T2CNTAl register contains the following bits:

GIE

BitO

Bit?

01::0.
(")

r.......

SlO

"tJ

Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge

"tJ

01::0.
(")

r.......

(")

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload AA
in mode 1, T2 Underflow in mode 2, T2A capture edge in mode 3)
T2CO
Timer T2 Start/Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3

T2C1

Timer T2 mode control bit

"tJ

T2C2

Timer T2 mode control bit

co
Q)

T2C3

Timer T2 mode control bit

01::0.
(")

"tJ

Q)
Q)

(")

r.......

(")

IT2c3IT2c2IT2c11T2coIT2PNDAIT2ENAIT2PNDBIT2ENBI
Bit7

BitO

Timers
The device contains a very versatile set of timers (TO, T1,
T2). All timers and associated autoreload/capture registers
power up containing random data.

ICNTRl Register (Address X'OOE8)
The ICNTAl register contains the following bits:
T1 ENB . Timer T1 Interrupt Enable for T1 B Input capture
edge

Figure 6 shows a block diagram for the timers.

T1 PNDB Timer T1 Interrupt Pending Flag for T1 B capture edge

1-179

-J

o
oo::t'

co
0)

r-------------------------------------~--------------------------------------------------__,

Timers (Continued)

a..

-J
""
o

co
co

a..
o

I
N

o""

-J

IX~~~----~,~~~.J+-----~~

oo::t'

co
co

N
A
L

-J
""
o

D
A

a..
o
o

co
co
co

1+------.. TA

....--r-~

a..

T2A

-J
""
o

TIt.lER T2

1+---+1

B
U
S

oo::t'

a..
o
o

-J
""
o

TL/DD/9766-11

co
co
CD

a..

FIGURE 6. Timers

block, while the pin TxB is an input to the timer block. The
powerful and flexible timer block allows the device to easily
perform all timer functions with minimal software overhead.
The timer block has three operating modes: Processor'lnde·
pendent PWM mode, External Event Counter mode, and
Input Capture mode.

TIMER TO (IDLE TIMER)

The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer TO, which is a
16-bit timer. The Timer TO runs continuously at the fixed
rate of the instruction cycle clock, te. The user cannot read
or write to the IDLE Timer TO, which is a count down timer.

The control bits TxC3, TxC2, and TxC1 allow selection of
the different modes of operation.

The Timer TO supports the following functions:
Exit out of the Idle Mode (See Idle Mode description)
WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode

Mode 1. Processor Independent PWM Mode

As the name suggests, this mode allows the device to gen·
erate a PWM signal with very minimal user intervention.

The IDLE Timer TO can generate an interrupt when the thir·
teenth bit toggles. This toggle is latched into the TOPND
pending flag, and will occur every 4 ms at the maximum
clock frequency (te = 1 fLS). A control flag TOEN allows the
interrupt from the thirteenth bit of Timer TO to be enabled or
disabled. Setting TOEN will enable the interrupt, while reset·
ting it will disable the interrupt.

The user only has to define the parameters of the PWM
signal (ON time and OFF time). Once begun, the timer block
will continuously generate the PWM signal completely inde·
pendent of the microcontroller. The user software services
the timer block only when the PWM parameters require up·
dating.
In this mode the timer Tx counts down at a fixed rate of te.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.

TIMER T1 AND TIMER T2

The device has a set of two powerful timer/counter blocks,
T1 and T2. The associated features and functioning of a
timer block are described by referring to the timer block Tx.
Since the two timer blocks, T1 and T2, are identical, all com·
ments are equally applicable to either timer block.

The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.

Figure 7 shows a block diagram of the timer in PWM mode.

1-180

Timers

a"'C

(Continued)

(X)
(X)

TIMER
UNDERFLOW
INTERRUPT

or
........
o

a"'C
m

+----..,

(X)
~

TxA

........

a"'C

t C - - - - - -....

(X)
(X)
(X)

o
r
........
o

a"'C

TLlDD/9766-13

FIGURE 7. Timer In PWM Mode

This mode is quite similar to the processor independent
PWM mode described above. The main difference is that
the timer, Tx, is clocked by the input signal from the TxA pin.
The Tx timer control bits, TxC3, TxC2 and TxC1 allow the
timer to be clocked either on a positive or negative edge
from the TxA pin. Underflows from the timer are latched into
the TxPNDA pending flag. Setting the TxENA control flag
will cause an interrupt when the timer underflows.

Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control enable flags, TxENA and TxENB, allow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be
reloaded into the timer. Resetting the timer enable flags will
.
disable the associated interrupts.

o
o

r........

a"'C
co

(X)
(X)

r
o

........

a"'C
co
(X)
~

Figure 8 shows a block diagram of the timer in External
Event Counter mode.

TIMER
UNDERFLOW
INTERRUPT

Mode 2. External Event Counter Mode

The underflows can be programmed to toggle the TxA output pin. The underflows can also be programmed to generate interrupts.

(X)
(X)

Note: The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock.

+------,

TxAIXt--+I

II
TXB~TO Interrupt Control
TLlDD/9766-14

FIGURE 8. Timer in External Event Counter Mode

1-181

~ r-------------------------------------------------------------------~

co
en
D-

o
......

..;J

oco

Timers

(Continued)

Mode 3. Input Capture Mode

en
DO

In this mode, the timer Tx is constantly running at the fixed
tc rate. The two registers, RxA and RxB, act as capture
registers. Each register acts in conjunction with a pin. The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin.

co
co
D-

o
......
~
o
~
O

o
......
~

oco

co
co
D-

o
......
~

o
~

co
(D
D-

o
......
~

flow interrupt pending flag in the Input Capture mode). Consequently, the TxCO control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxCO pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.

The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode.

Figure 9 shows a block diagram of the timer in Input Capture
mode.

TIMER CONTROL FLAGS
The timers T1 and T2 have indentical control. structures.
The control bits and their functions are summarized below.
TxCO

The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag TxENA allows the interrupt on TxA to be either enabled or disabled. Setting the TxENA flag enables interrupts to be generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.

Timer Start/Stop control in Modes 1 and 2
(Processor Independent PWM and External
Event Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)

TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag

Underflows·from the timer can also be programmed to generate interrupts. Underflows are latched into the timer TxCO
pending flag (the TxCO control bit serves as the timer under-

o
co
co
(D
D-

TxENA
TxENB

Timer Interrupt Enable Flag
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
o = Timer Interrupt Disabled

TxC3
TxC2
TxC1

Timer mode control
Timer mode control
Timer mode control

I
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T
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R
N
A
L

Tx AIXI-----IW

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A

T
A

Tx BIXI----~

B
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TL/DD/9766-15

FIGURE 9. Timer In Input Capture Mode

1-182

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Timers

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(Continued)

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The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
Interrupt A
Source

Interrupt B
Source

Timer
Counts On

MODE 2 (External
Event Counter)

Timer
Underflow

Pos. TxB
Edge

TxA
Pos.Edge

MODE 2 (External
Event Counter)

Timer
Underflow

Pos. TxB
Edge

TxA
Neg.Edge

TxC3

TxC2

TxC1

Timer Mode

MODE 1 (PWM)
TxA Toggle

Autoreload
RA

Autoreload
RB

MODE 1 (PWM)
No TxA Toggle

Autoreload
RA

Autoreload
RB

MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Pos. Edge

Pos. TxA'
Edge or
Timer
Underflow

Pos. TxB
Edge

MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Neg. Edge

Pos.TxA
Edge or
Timer
Underflow

Neg.TxB
Edge

MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Pos. Edge

Neg. TxB .
Edge or
Timer
Underflow

Pos. TxB
Edge

MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Neg. Edge

Neg. TxA
Edge or
Timer
Underflow

Neg. TxB
Edge

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Power Save Modes
The device offers the user two power save modes of operat~~n: H/\LT :.r.d !DLE. In th~ ~-1ALT iiiCGu, Cia iT,~Ciuco .. truiif;i
activities are stopped. In the IDLE mode, the on-board oscillator circuitry and timer TO are active but all other microcontroller activities are stopped. In either mode, all on-board
RAM, registers, 1/0 states, and timers (with the exception of
TO) are unaltered.

with the Multi-Input Wakeup feature on the L port. The second IIII:lU,OU i~ witil a low to high transition on the CKO (G/)
pin. This method precludes the use of the crystal clock configuration (since CKO becomes a dedicated output), and so
may be used with an RC clock configuration. The third
method of exiting the HALT mode is by pulling the RESET
pin low.

HALT MODE

Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the tc instruction cycle clock. The tc
clock is derived by dividing the oscillator clock down by a
factor of 10. The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE timer is clocked only
when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger specifications. This Schmitt trigger
is not part of the oscillator closed loop. The startup timeout
from the IDLE timer enables the clock signals to be routed
to the rest of the chip.

The device is placed in the HALT mode by writing a "1" to
the HALT flag (G7 data bit). All microcontroller activities,
including the clock, timers, are stopped. The WATCHDOG
logic is disabled during the HALT mode. However, the clock
monitor circuitry, if enabled, remains active and will cause
the WATCHDOG output pin (WDOUT) to go low. If the
HALT mode is used and the user does not want to activate
the WDOUT pin, the Clock Monitor should be disabled after
the device comes out of reset (resetting the Clock Monitor
control bit with the first write to the WDSVR register). In the
HALT mode, the power requirements of the device are minimal and the applied voltage (Ved may be decreased to Vr
(Vr = 2.0V) without altering the state of the machine.
The device supports three different ways of exiting the
HALT mode. The first method of exiting the HALT mode is

1-183

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Power Save Modes (Continued)
If an RC clock option is being used, the fixed delay is introduced optionally. A control bit, CLKDLV, mapped as configuration bit G7, controls whether the delay is to be introduced or not. The delay is included if CLKDLV is set, and
excluded if CLKDLV is reset. The CLKDLV bit is cleared on
reset.

As with the HALT mode, the device can be returned to normal operation with a reset, or with a Multi-Input Wake-up
from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the thirteenth
bit (representing 4.096 ms at internal clock frequency of
1 MHz, tc = 1 ,....s) of the IDLE Timer toggles.

The device has two mask options associated with the HALT
mode. The first mask option enables the HALT mode feature, while the second mask option disables 'the HALT
mode. With the HALT mode enable mask option, the device
will enter and exit the HALT mode as described above. With
the HALT disable mask option, the device cannot be placed
in the HALT mode (writing a "1" to the HALT flag will have
no effect).

This toggle condition of the thirteenth bit of the IDLE Timer
TO is latched into the TOPND pending flag.
The user has the option of being interrupted with a transition
on the thirteenth bit of the IDLE Timer TO. The interrupt can
be enabled or disabled via the TOEN control bit. Setting the
TOEN flag enables the interrupt and vice versa.
The user can enter the IDLE mode with the Timer TO interruptenabled. In this case, when the TOPND bit gets set, the
device will first execute the Timer TO interrupt service routine and then return to the instruction following the "Enter
Idle Mode" instruction.

The WATCHDOG detector circuit is inhibited during the
HALT mode. However, the clock monitor circuit, if enabled,
remains active during HALT mode in order to ensure a clock
monitor error if the device inadvertently enters the HALT
mode as a result of a runaway program or power glitch.

IDLE MODE

The device is placed in the IDLE mode by writing a "1" to
the IDLE flag (G6 data bit). In this mode, all activity, except
the associated on-board oscillator circuitry, the WATCHDOG logic, the clock monitor and the IDLE Timer TO, is
stopped.

Note: It is necessary to program two NOP instructions following both the
set HALT mode and set IDLE mode instructions. These NOP instruc·
tions are necessary to allow clock resynchronization following the
HALT or IDLE modes.

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1-184

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Multi-Input Wakeup
RBIT
SBIT
RBIT
SBIT

The Multi-Input Wakeup feature is used to return (wakeup)
the device from either the HALT or IDLE modes. Alternately
Multi-Input Wakeup/Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts.

5,
5,
5,
5,

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WKEN
WKEDG
WKPND
WKEN

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If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup/Interrupt, a safety procedure should also be followed to avoid inherited
pseudo wakeup conditions. After the selected L port bits
have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired
edge selects, followed by the associated WKPND bits being
cleared.
This same procedure should be used following reset, since
the L port inputs are left floating as a result of reset.
The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since WKPND is a pending
register for the occurrence of selected wakeup conditions,
the device will not enter the HALT mode if any Wakeup bit is
both enabled and pending. Consequently, the user has the
responsibility of clearing the pending flags before attempting to enter the HALT mode.
The WKEN, WKPND and WKEDG are all read/write registers, and are cleared at reset.

Figure 10 shows the Multi-Input Wakeup logic.

The Multi-Input Wakeup feature utilizes the L Port. The user
selects which particular L port bit (or combination of L Port
bits) will cause the device to exit the HALT or IDLE modes.
The selection is done through the Reg: WKEN. The Reg:
WKEN is an 8-bit read/write register, which contains a control bit for every L port bit. Setting a particular WKEN bit
enables a Wakeup from the associated L port pin.
The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an 8bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.
An example may serve to clarify this procedure. Suppose
we wish to change the edge select from positive (low going
high) to negative (high going low) for L Port bit 5, where bit 5
has previously been enabled for an input interrupt. The program would be as follows:

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PORT L INTERRUPTS

Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into
the same service subroutine.

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The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to

DATA BUS

•

•
•
•
•
•

m
•
•
•
•
•
•

L7
WKEDG

CKI

WKPND

CKO

CHIP CLOCK

TL/DD/9766-16

FIGURE 10. Multi-Input Wake Up Logic

1-185

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(Continued)

be individually enabled or disabled. The register WKEDG
specifies the trigger condition to be either a positive or a
negative edge. Finally, the register WKPND latches in the
pending trigger conditions.
The GIE (Global Interrupt, Enable) bit enables the interrupt
function.

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A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag is' not
needed since the register ""KPND is adequate~

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Since Port L is also used for waking the, device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If
he elects to disable the interrupt, then the device will restart
execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or
IDLE modes. In the other case, the device will first execute
the interrupt service routine and then revert to normal operation.

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case, upon detecting a valid Wakeup signal, only the oscillator circuitry and the IDLE Timer TO are enabled. The IDLE
Timer is loaded with a value of 256 and is clocked from the
tc instruction cycle clock. The tc clock is derived by dividing
down the oscillator clock by a factor of 10. A Schmitt trigger
following the CKI on-chip inverter ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large
amplitude to meet the Schmitt trigger specifications. This
Schmitt trigger is not part of the oscillator closed loop. The
startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip.
If the RC clock option is used, the fixed d~lay is under software control. A control flag, CLKDLY, in the G7 configuration bit allows the clock start up delay to be optionally inserted. Setting CLKDLY flag high will cause clock start up delay
to be inserted and resetting it will exclude the clock start up
delay. The CLKDLY flag is cleared during reset, so the clock
start up delay is not, present following reset with, the RC
clqck options.
"
"

Interrupts
The device supports a vectored interrupt scheme. It supports a total of ten interrupt sources. The following table ,
lists all the possible interrupt sources, their arbitration rank·
ing and the memory locations reserved for the interrupt vec.
tor for each source.

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Arbitration
Ranking

(1) Highest

Description

Source

Software
; Reserved

' Vector
Address
HI·Low Byte

INTR Instruction

OyFE-OyFF

for Future Use

OyFC-OyFD

(2)

External

Pin GO Edge

OyFA-OyFB

(3)

Timer TO

Underflow

OyF8-0yF9

(4)

TimerT1

T1A1Underflciw

OyF6-0yF7

(5)

TimerT1

T1B

OyF4-0yF5

(6)

MICROWIRE/PLUS

BUSY Goes Low

OyF2-0yF3

Reserved

for Future Use

OyFO-OyF1

Reserved

for UART

OyEE-OyEF

Reserved

for UART'

OyEC-OyED

T2A1Underflow

OyEA-OyEB

TimerT2

T2B

OyE8-0yE9

Reserved

for Future Use

OyE6-0yE7

(7)

'TimerT2

(8)

Reserved

for Future Use

OyE4-0yE5

(9)

Port LlWakeup

Port LEdge

OyE2-0yE3

(10) Lowest

Default

VIS Instr. Execution
without Any Interrupts

OyEO-OyE1

Y IS VIS page.

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1~186

Interrupts (Continued)

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Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software
interrupt are maskable. Each of the maskable interrupts
have an Enable bit and a Pending bit. A maskable interrupt
is active if its associated enable and pending bits are set. If
GIE = 1 and an interrupt is active, then the processor will
be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described
'
in the Software Trap sub-section.

Inside the interrupt service routine, the associated pending
bit has to be cleared by software. The RETI (Return from
Interrupt) instruction at the end of the interrupt service routine will set the GIE (Global Interrupt Enable) bit, allowing
the processor to be interrupted again if another interrupt is
active and pending.
.

The VIS instruction looks at all the active interrupts at the
time it is executed and performs an -indirect jump to the
beginning of the service routine of the one with the highest
rank.

1. The GIE (Global Interrupt Enable) bit is reset.

routine associated with the higher priority interrupt just serviced. This lower priority interrupt will occur immediately following the RETI (Return from Interrupt) instruction at the
end of the interrupt service routine just completed.

2. The address of the instruction about to be executed is
pushed into the stack.
3. The PC (Program Counter) branches to address OOFF.
This procedure takes 7 tc cycles to execute.

At this time, since GIE = 0; other maskable interrupts are
disabled. The user is' now free to do whatever context
switching is required by saving the context of the machine in
the stack with PUSH instructions. The user would then program a VIS (Vector Interrupt Select) instruction in order to
branch to the interrupt service routine of the highest priority
interrupt enabled and pending at the time of the VIS. Note
that this is not necessarily the interrupt that caused the
branch to address location OOFF Hex prior to the context
switching.

The Software Trap has the highest rank and its vector is
located at OyFE and OYFF.

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If, by accident, a VIS gets executed and no interrupt is active, then the PC (Program Counter) will branch to a vector
located at OyEO-OyE1. This vector can point to the Software Trap (ST) interrupt service routine, or to another special service routine as desired.
Figure 11 shows the Interrupt block diagram.

SOnwARE--------------------------~

TIMER Tl AND T2

EXTERNAL

MULTI-INPUT WAKE UP
INTERRUPT
}lWIRE/PLUS

rUTURE PERIPHERALS

IDLE TIMER

TLlDD/9766-1 B

FIGURE 11. Interrupt Block Diagram

1-187

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TABLE II. WATCHDOG Service Window Select

I nterru pts

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SOFTWARE TRAP

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The Software Trap (Sn is a special kind of non-maskable
interrupt which occurs when the INTR instruction (used to
acknowledge interrupts) is fetched from ROM and placed
inside the instruction register. This may happen when the
PC is pOinting beyond the available ROM address space or
when the stack is over-popped.

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When an ST occurs, the user can re-initialize the stack
pointer and do a recovery procedure (similar to reset, but
not necessarily containing all of the same initialization procedures) before restarting.
The occurrence of an ST is latched into the ST pending bit.
The GIE bit is not affected and the ST pending bit (not
accessible by the user) is used to inhibit other interrupts
and to direct the program to the ST service routine with the
VIS'instruction. The RPND instruction is used to clear the
software interrupt pending bit. This pending bit is also
cleared on reset.
The ST has the highest rank among all interrupts.

WATCHDOG
The device contains a WATCHDOG and clock monitor. The
WATCHDOG is designed to detect the user program getting
stuck in infinite loops resulting in loss of program control or
"runaway" programs. The Clock Monitor is used to detect
the absence of a clock or a very slow clock below a specified rate on the CKI pin.

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TABLE I. WATCHDOG Service Register (WDSVR)

Clock
Monitor

I1 I1 Ia Ia
4

a
1

2k-8k tc Cycles
2k-16k tc Cycles
2k-32k tc Cycles
2k-64k tc Cycles

The WATCHDOG has an output pin associated with it. This
is the WDOUT pin, on pin 1 of the port G. WDOUT is active
low. The WDOUT pin is in the high impedance state in the
inactive state. Upon triggering the WATCHDOG, the logic
will pull the WDOUT (G1) pin low for an additional
16 tc-32 tc cycles after the signal level on WDOUT pin goes
below the lower Schmitt trigger threshold. After this delay,
the device will stop forcing the WDOUT output low.

Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the
5-bit Key Data field. The key data is fixed at 01100. Bit a of
the WDSVR Register is the Clock Monitor Select bit.

1
1

WATCHDOG Operation

The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 and 6 of the WDSVR register allow
the user to pick an upper limit of the service window.
Table II shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flexibility in choosing the WATCHDOG service window prevents
any undue burden on the user software.

The WATCHDOG and Clock Monitor are disabled during
reset. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG Window Select bits (bits 6,7 of the
WDSVR Register) set, and the Clock Monitor bit (bit a of the
WDSVR Register) enabled. Thus, a Clock Monitor error will
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, including the case where the oscillator fails to start.
The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the WATCHDOG service window and match the WATCHDOG key data. Subsequent writes to the WDSVR register
will compare the value being written by the user to the
WATCHDOG service window value and the key data (bits 7
through 1) in the WDSVR Register. Table III shows the sequence of events that can occur.
The user must service the WATCHDOG at least once before the upper limit of the serivce window expires. The
WATCHDOG may not be serviced more than once in every
lower limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period
between the lower and upper limits of the service window.
The first write to the WDSVR Register is also counted as a
WATCHDOG service.

Key Data

a
a

Service Window
(Lower-Upper Limits)

Clock Monitor

The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.

Window
Select

WDSVR
BitS

The Clock Monitor aboard the device can be selected or
deselected under program control. The Clock Monitor is
guaranteed not to reject the clock if the instruction cycle
clock (1 ltd is greater or equal to 10kHz. This equates to a
clock input rate on CKI of greater or equal to 100 kHz.

Nothing (except another ST) can Interrupt an ST being
serviced.

WDSVR
Blt7

The WATCHDOG service window will restart when the
WDOUT pin goes high It is recommended that the user tie
the WDOUT pin back to Vee through a resistor in order to
pull WDOUT high.

A WATCHDOG service while the WDOUT signal is active
will be ignored. The state of the WDOUT pin is not guaranteed on reset, but if it powers up low then the WATCHDOG
will time out and WDOUT will enter high impedance state.

1-188

WATCHDOG Operation

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(Continued)

(X)
(X)

TABLE III. WATCHDOG Service Actions

Key
Data

Window
Data

Clock
Monitor

Action

r......

Match

Valid Service: Restart Service Window

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Mismatch

Don't Care

Error: Generate WATCHDOG Output

Mismatch

Don't Care

Error: Generate WATCHDOG Output

r......

Don't Care

Mismatch

Error: Generate WATCHDOG Output

a"tJ

TABLE IV. MICROWIRE/PLUS
Master Mode Clock Select
SL1

SLO

0
0
1

0
1

SK
2
4
8

x
x
x

te
te
te

Where te is the instruction cycle clock
The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum specified value, after which the G1 output will enter the high impedance TRI-STATE mode following 16 te-32 te clock cycles. The Clock Monitor generates a continual Clock Monitor error if the oscillator fails to start, or fails to reach the
minimum specified frequency. The specification for the
Clock Monitor is as follows:

1/te > 10kHz-No clock rejection.
1 Ite < 10Hz-Guaranteed clock rejection.
WATCHDOG AND CLOCK MONITOR SUMMARY

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• With the single-pin RIC oscillator mask option selected
and the CLKDLY bit reset, the WATCHDOG service window will resume following HALT mode from where it left
off before entering the HALT mode.

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• With the crystal oscillator mask option selected, or with
the single-pin RIC oscillator mask option selected and
the CLKDLY bit set, the WATCHDOG service window will
be set to its selected value from WDSVR following HALT.
Consequently, the WATCHDOG should not be serviced
for at least 2048 instruction cycles following HALT, but
must be serviced within the selected window to avoid a
WATCHDOG error.

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• The IDLE timer TO is not initialized with reset.
• The user can sync in to the IDLE counter cycle with an
IDLE counter (TO) interrupt or by monitoring the TOPND
!~~g. Tho TCr~~D !:ug i:; 3~t '''fh~iig'vci th~ thirteenth bit of
the IDLE counter toggles (every 4096 instruction cycles).
The user is responsible for resetting the TOPND flag.

The following salient points regarding the WATCHDOG and
Clock Monitor should be noted:
• Both WATCHDOG and Clock Monitor detector circuitR
are inhibited during reset.
• Following reset, the WATCHDOG and Clock Monitor are
both enabled, with the WATCHDOG having the maximum service window selected.

• A hardware WATCHDOG service occurs just as the device exits the IDLE mode. Consequently, the Watchdog
should not be serviced for at least 2048 instruction cycles following IDLE, but must be serviced within the selected window to avoid a WATCHDOG error.
• Following reset, the initial WATCHDOG service (where
the service window and the Clock Monitor enable/disable must be selected) may be programmed anywhere
within the maximum service window (65,536 instruction
cycles) initialized by RESET. Note that this initial
WATCHDOG service may be programmed within the initial 2048 instruction cycles without causing a WATCHDOG error.

• The WATCHDOG service window and Clock Monitor enablel disable option can only be changed once, during
the initial WATCHDOG service following reset.
• The initial WATCHDOG service must match the key data
value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error.
• Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG errors.
• The correct key data value cannot be read from the
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all O's.

Detection of Illegal Conditions
The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.

• The WATCHDOG detector circuit is inhibited during both
the HALT and IDLE modes.
• The Clock Monitor detector circuit is active during both
the HALT and IDLE modes. Consequently, the device
inadvertently entering the HALT mode will be detected
as a Clock Monitor error (provided that the Clock Monitor
enable option has been selected by the program).

1-189

~ ~--------------------------------~----------------------------~

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o
......

o-.::I'

co
CD

master mode, the SK clock rate is selected by the two bits,
SlO and Sl1, in the CNTRl register. Table IV details the
different clock rates that may be selected.

Detection of Illegal
Conditions (Continued)
The subroutine stack grows down for each call Gump to
subroutine), interrupt, or PUSH, and grows up for each re- .
turn or POP. The stack pointer is initialized to RAM location
06F Hex during reset. .Consequently, if there are more returns than calls,. the stack pointer will pOint to addresses
070 and 071 Hex (which are undefined RAM). Undefined
RAM from addresses 070 to. 07F Hex is read as all .1's,
which in turn will cause the program to return to address
7FFF Hex. This is an undefined ROM location and theinstruction fetched (all O's) from this location wiil generate a
software interrupt signaling an illegal condition.
Thus, the chip can detect the following illegal conditions:

MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the MICROWIRE/PlUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less tha'n 8 bits to shift. If
enabled; an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PlUS
mode either as a Master or as a Slave. Figure 13 shows
how two COP888Cl microcontrollers and several peripherals may be interconnected using the MICROWIRE/PlUS
arrangements.
.. Warnlng:

a. Executing from undefined ROM

The SIO register should only be loaded when the SK clock
is low. loading the SIO register while the SK clock is high
will result in undefined data in the SIO register. The SK
clock is normally low when not shifting.
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PlUS slave mode may cause the current SK
clock for the $10 shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is
low.
.

b. Over "POP"ing the stack by having more returns than
calls.
When the software interrupt occurs, the user can re-initialize
the stack pOinter and do a recovery procedure before restarting (this recovery program is probably similar to that
following reset, but might not contain the same· program
initialization procedures). The recovery program should reset the software interrupt pending. bit using. the RPND instruction ..

o
......
~

o
co
co
CD

MICROWIRE/PLUS Master Mode Operation

MICROWIRE/PLUS

In the MICROWIRE/PlUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE
Master always initiates all data exchanges. The MSEL bit in
the CNTRl register must be set to enable the SO and SK
functions onto the G Port. The SO and SK pins must also be
selected as outputs by setting appropriate bits in the Port G
configuration register. Table V summarizes the bit settings
required for Master mode of operation.

MICROWIRE/PlUS is a serial synchronous communications interface. The MICROWIRE/PlUS capability enables
the device to interface with any of National Semiconductor's
MICROWIRE peripherals (Le. AID converters, display drivers, E2PROMs etc.) and with other microcontrollers which
support the MICROWIRE interface. It consists of an 8-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK). Figure 12
shows a block diagram of the MICROWIRE logic.

MICROWIRE/PLUS Slave Mode Operation

In the MICROWIRE/PlUS Slave mode' of operation the SK
clock is generated by an external source. Setting the MSEl
bit in the CNTRl register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bit in the Port G configuration register. Table V summarizes the settings required to enter the
Slave mode of operation.

The shift. clock can be selected from either an internal
source or an. external source. Operating the MICROWIREI
PLUS arrangement with the internal clock source is called
the Master mode of operation. Similarly, operating the MICROWIRE arrangement with an external shift clock is called
the Slave mode of operation.

I---"';"'--~

The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure' that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated.

INTERRUPT

~~----~----------~SO

I+---------SI ,

Alternate SK Phase Operation

The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register.
In both the modes the SK is normally low. In the normal
mode data is shifted in on the rising· edge of the SK clock
and the data is shifted out on the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK clock. In the alternate SK phase operation, data is shifted in on the falling edge of the SK clock and shifted out on
the rising edge of the SKclock.

TL/DD/9766-20

FIGURE 12. MICROWIRE/PLUS Block Diagram

The CNTRl register is used to configure and control the
MICROWIRE/PlUS mode. To use the MICROWIRE/PlUS,
the MSEl bit in the CNTRl register is set to one. In the

1-190

a"'C

MICROWIRE/PLUS (Continued)
/5
/

CHIP SELECT LINES
CS

CD
CD

a"'C
0)

I/o

AID

LINES

+-+

LCD
DISPLAY
DRIVER
COP472

8 - BIT
EEPROM

COP43X
COP8
(MASTER)

CD
LINES

COP8
(SLAVE)

00 SK 01

SK 01

! f

0l:Io

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I/o

PLL

+-+

a"'C
CD
CD
CD

a"'C

SK
TLlDD/9766-21

FIGURE 13. MICROWIRE/PLUS Application

A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alternate SK clock. The SKSEL is mapped into the G6 configuration bit. The SKSEL flag will power up in the reset condition,
selecting the normal SK signal.

TABLE V
This table assumes that the control flag MSEL is set.
G4
(SO)
Conflg.

G5
(SK)
Conflg.

Bit

CD
CD
0l:Io

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a"'C
<0
CD
CD

G4
Fun.

G5
Fun.

Operation

Int.
SK

M ICROWIRE/PLUS
Master

TRI·
STATE

Int.
SK

MICROWIRE/PLUS
Master

Ext.
SK

MICROWIRE/PLUS
Slave

Tf1ISTATE

::::At.
SK

Slave

a"'C
<0
CD

0l:Io

o
r-

~.~:cnow:nE/rLUS

1-191

o
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en
D..

o.......
~

r-------------------------------------------------------------------------,
Memory Map

Addressing Modes

All RAM, ports and registers (except A and PC) are mapped
into data memory address space

The device has ten addressing modes, six for operand addressing and four for transfer of control.

Address
00 to 6F

70 to BF

Unused RAM Address Space

CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CDtoCF

Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA Lower Byte
Timer T2 Autoload Register T2RA Upper Byte
Timer T2 Autoload Register T2RB Lower Byte
Timer T2 Autoload Register T2RB Upper Byte
Timer T2 Control Register
WATCHDOG Service Register (Reg:WDSVR)
MIWU Edge Select Register (Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register (Reg:WKPND)
Reserved
Reserved
Reserved

D..

o
.......
~

o
~

co
co

D..

o
.......
~

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co
co
D..

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~
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CD

D..

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.......
~

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CD

D..

o
o

OPERAND ADDRESSING MODES

Contents

o
co

On-Chip RAM bytes

DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DDto DF

Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port D Data Register
Reserved for Port D

EO to E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF

Reserved
Timer T1 Autoload Register T1 RB Lower Byte
Timer T1 Autoload Register T1 RB Upper Byte
ICNTRL Register
MICROWIRE Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1 RA Lower Byte
Timer T1 Autoload Register T1 RA Upper Byte
CNTRL Control Register
PSW Register

FO to FB
FC
FD
FE
FF

On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
Reserved

This is the "normal" addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.
Register Indirect (with auto post Increment or
decrement of pointer)
This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that
automatically post increments or decrements the B or X register after executing the instruction.
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
Immediate
The instruction contains an 8-bit immediate field as the operand.
Short Immediate
This addressing mode is used with the Load B Immediate
instruction. The instruction contains a 4-bit immediate field
as the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
TRANSFER OF CONTROL ADDRESSING MODES
Relative
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
program location. JP has a range from -31 to +32 to allow
a 1-byte relative jump (JP + 1 is implemented by a NOP
instruction). There are no "pages" when using JP, since all
15 bits of PC are used.
Absolute
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any location in the current 4k program memory segment.
Absolute Long
This mode is used with the JMPL and JSRL instructions,
with the instruction field of 15 bits replacing the entire 15
bits of the program counter (PC). This allows jumping to any
location in the current 4k program memory space.
Indirect
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits
of PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruction.

Reading memory locations 70-7F Hex will return all ones. Reading other
unused memory locations will return undefined data.

Note: The VIS is a special case of the Indirect Transfer of Control address·
ing mode, where the double byte vector associated with the interrupt
is transferred from adjacent addresses in the program memory into
the program counter (PC) in order to jump to the associated interrupt
service routine.

1-192

o
o

Instruction Set

"'D

CD
CD

X
SP
PC
PU
PL
C
HC
GIE
VU
VL

Symbols
[B)

8-Bit Accumulator Register
8-Bit Address Register
8-Bit Address Register
8-Bit Stack Pointer Register
15-Bit Program Counter Register
Upper 7 Bits of PC
Lower 8 Bits of PC
1 Bit of PSW Register for Carry
1 Bit of PSW Register for Half Carry
1 Bit of PSW Register for Global
Interrupt Enable
Interrupt Vector Upper Byte
Interrupt Vector Lower Byte

[X]
MD
Mem
Meml
Imm
Reg
Bit
~

Memory Indirectly Addressed by B
Register
Memory Indirectly Addressed by X
Register
Direct Addressed Memory
Direct Addressed Memory or [B)
Direct Addressed Memory or [B) or
Immediate Data
8-Bit Immediate Data
Register Memory: Addresses FO to FF
(Includes B, X and SP)
Bit Number (0 to 7)
Loaded with
Exchanged with

o
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......
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CD
~

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......

o"'D
CD
CD
CD

o
r
......
o

o"'D
CD
CD
~

o
r
......
o

"'D

CD
CD

o
r
......

o"'D
co

CD
~

1·193

..J

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:;

Instruction Set (Continued)

INSTRUCTION SET

o
......
..J

ADD
ADC

A,Meml
A,Meml

ADD
ADD with Carry

ClO

SUBC

A,Meml

Subtract with Carry

AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND

A,Meml
A,lmm
A,Meml
A,Meml
MD,Imm
A,Meml·
A,Meml
A,Meml
#
Reg
#,Mem
#,Mem
#,Mem

Logical AND
Logical AND Immed., Skip if Zero
Logical OR
Logical EXclusive OR
IF EQual
IF EQual
IF Not Equal
IF Greater Than
If B Not Equal
Decrement Reg., Skip if Zero
Set BIT
Reset BIT
IFBIT
Reset PeNDing Flag

X
X
LD
LD
LD
LD
LD

A,Mem
A,[X]
A,Meml
A,[X]
B,lmm
Mem,lmm
Reg,lmm

EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD B with Immed.
LoaD Memory Immed
LoaD Register Memory Immed.

A~Mem

X
X
LD
LD
LD

A, [B ±]
A, [X ±]
A, [B±]
A, [X±]
[B±l,Imm

EXchange A with Memory [B]
EXchange A with Memory [X]
LoaD A with Memory [B]
LoaD A with Memory [X]
LoaD Memory [B] Immed.

A~ [B],(B+-B±1)

CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH

A
A
A

CLeaR A
INCrementA
DECrementA
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
SetC
ResetC
IFC
IF Note
POP the stack into A
PUSH A onto the stack

A+-O
A+-A+1
A+-A-1
A +- ROM (PU,A)
A +- BCD correction of A (follows ADC, SUBC)
C ~ A7 ~ ... ~ AO ~ C
C +- A7 +- .,. +- AO +- C
A7 ... A4 ~ A3 ... AO
C+-1,HC+-1
C +- 0, HC +- 0
IF C is true, do next instruction
If C is not true, do next instruction
SP +- SP + 1, A +- [SP]
[SP] +- A, SP +- SP - 1

PU +- [VU], PL +- [VL]
PC +- ii (ii = 15 bits, 0 to 32k)
PC9 ... 0 +- i (i = 12 bits)
PC +- PC + r (ris -31 to +32, except 1)
[SP] +- PL, [SP-1] +- PU,SP-2, PC +- ii
[SP] +- PL, [SP-1] +- PU,SP-2, PC9 ... 0 +- i
PL +- ROM (PU,A)
SP+2, PL +- [SPl, PU +- [SP-1]
SP+2, PL +- [SPl,PU +- [SP-1]
SP+2, PL +- [SP],PU +- [SP-1l,GIE +-1
[SP] +- PL, [SP-1] +- PU, SP-2, PC +- OFF
PC+- PC+1

oClO

D-

o
......
..J
o
"'I:t'
ClO
ClO

D-

o
......
..J

o
ClO
ClO
ClO

D-

o......
..J
o"'I:t'
ClO

D-

o
......
o

..J

ClO
ClO

D-

VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

A
A
A
A

A
A
Addr.
Addr.
Disp.
Addr.
Addr

1-194

A+-A + Meml
A +- A +·Meml + C, C +- Carry
HC +- Half Carry
A +- A - Meml + C, C +- Carry
HC +- Half Carry
A +- A and Meml
Skip next if (A and Imm) = 0
A+- Aor Meml
A +- A xor Meml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A =1= Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B =1= Imm
Reg +- Reg- 1, Skip if Reg =0
1 to bit, Mem (bit = 0 to 7 immediate)
Oto bit, Mem
If bit in A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
A~[X]

A+- Meml
A+- [X]
B+-Imm
Mem +-Imm
Reg+-Imm
A~ [X], (X+- ±1)
A+- [Bl, (B +- B± 1)
A +- [X], (X +- X ± 1)
[B] +-Imm, (B +- ±1)

Instruction Execution Time
Most instructions are single byte (with immediate addressing mode instructions taking two bytes).

Instructions Using A & C

CLRA
INCA
DECA
LAID
DCOR
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ

Most single byte instructions take one cycle time to execute.
See the BYTES and CYCLES per INSTRUCTION table for
details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles
for each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
[B)

Direct

ADD
ADC
SUBC
AND
OR
XOR
·IFEQ
IFNE
IFGT
IFBNE
DRSZ

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4

SBIT
RBIT
IFBIT

1/1
1/1
1/1

Immed.

2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2

1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2

Transfer of Control
Instructions

JMPL
JMP
JP
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP

3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5

117
1/1

0
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en

co
co

........

0
"'D
en
co
.r::.
0

........

"'D

co
co
co

........

"'D

co
co
.r::.

........

"'D
<0

co
co

1/3

3/4
3/4
3/4

........

"'D
<0

RPND

co
.r::.

1/1

Memory Transfer Instructions
Register
Indirect

XA,·
LOA,·
LDB,lmm
LDB,lmm
LDMem,lmm
LD Reg,lmm
IFEQMD,lmm

[~]

1/1
1/1

1/3
1/3

2/2

Direct

2/3
2/3

Immed.

2/2
1/1
2/2

3/3
2/3
3/3

[a+,a-]

[~+,A-J

1/2
1/2

1/3
1/3
(IFB < 16)
(IFB>15)

2/2

• = > Memory location addressed by 8 or X or directly.

1-195

..J

o
"'I:t'

Opcode Table

Upper Nibble Along X-Axis
Lower Nibble Along Y-Axis

co
en
c..

o
......
..J
o
co
co
en
c..

JP -15

JP -31

LDOFO, # i

DRSZOFO

JP -14

JP -30

LD OF1, # i

DRSZOF1

ADCA,#i

ADCA,[B]

SUBCA, #i

SUBA,[B]

RRCA

o
......

JP -13

JP -29

LDOF2, # i

DRSZOF2

XA, [X+]

XA,[B+]

IFEQA,#i

IFEQA,[B]

..J

o"'I:t'

JP -12

JP -28

LDOF3, # i

DRSZOF3

XA,[X-]

XA,[B-]

IFGTA,#i

IFGTA,[B]

co
co
c..

JP -11

JP -27

LDOF4, # i

DRSZOF4

VIS

LAID

ADDA,#i

ADDA,[B]

JP -10

JP -26

LDOF5, # i

DRSZOF5

RPND

JID

ANDA,#i

ANDA,[B]

......

JP -9

JP -25

LD OF6, # i

DRSZOF6

XA,[X]

XORA,[B]

JP -8

JP -24

LDOF7, # i

DRSZOF7

XORA,#i

oco

ORA,#i

ORA,[B]

JP -7

JP -23

LDOF8, # i

DRSZOF8

JP -6

JP -22

LDOF9, # i

DRSZOF9

..J

co
co
c..

o
......

..J

o
"'I:t'

XA,[B]

NOP

RLCA

LDA,#i

IFC

IFNE
A,[B]

IFEQ
Md,#i

IFNE
A,#i

IFNC

9
A

JP -5

JP -21

LDOFA, # i

DRSZOFA

LDA,[X+]

LDA,[B+]

LD [B+ ]'#i

INCA

JP -4

JP -20

LDOFB, # i

LDA,[X-]

LD A,[B-]

LD [B-]'#i

DRSZOFB

DECA

JP -3

JP -19

LDOFC, # i

DRSZOFC

LD Md,#i

JMPL

XA,Md

POPA

..J

o
co

JP -2

JP -18

LDOFD, # i

DRSZOFD

DIR

JSRL

LDA,Md

RETSK

co
CD
c..

JP -1

JP -17

LDOFE, # i

DRSZOFE

LDA,[X]

RET

JP -16

LDOFF, # i

DRSZOFF

LD[B],#i

JP -0

LDB,#i

RETI

co
CD
c..

o
......

1-196

LDA,[B]

Opcode Table

o
o

(Continued)

"'C
0')
Q)
Q)

Upper Nibblo Along X-Axis

Lower Nibble Along V-Axis
7

IFBIT
O,[B]

ANOSZ
A, #i

LO B,#OF

·
·

4
IFBNEO

JSR
xOOO-xOFF

JMP
xOOO-xOFF

JP +17

r.......

0
INTR

o
o

"'C

Q)
~

LO B,#OE

IFBNE 1

JSR
x100-x1FF

JMP
x100-x1FF

JP +18

JP + 2

LO B,#OO

IFBNE2

JMP
x200-x2FF

JP +19

JP + 3

JSR
x200-x2FF

LO B,#OC

IFBNE 3

JSR
x300-x3FF

JMP
x300-x3FF

JP +20

JP + 4

IFBIT
4,[B]

CLRA

LO B,#OB

IFBNE4

JSR
x400-x4FF

JMP
x400-x4FF

JP +21

JP + 5

IFBIT
5,[B]

SWAPA

LO B,#OA

IFBNE 5

JSR
x500-x5FF

JMP
x500-x5FF

JP +22

JP + 6

Q)
Q)

IFBIT
6,[B]

OCORA

LO B,#09

IFBNE6

JSR
x600-x6FF

JMP
x600-x6FF

JP +23

JP + 7

o
r.......

IFBIT
7,[B]

PUSHA

LO B,#08

IFBNE 7

JSR
x700-x7FF

JMP
x700-x7FF

JP +24

JP + 8

SBIT
O,[B]

RBIT
O,[B]

LO B,#07

IFBNE 8

JSR
x800-x8FF

JMP
x800-x8FF

JP +25

JP + 9

SBIT
1,[B]

RBIT
1,[B]

LO B,#06

IFBNE 9

JSR
x900-x9FF

JMP
x900-x9FF

JP +26

JP + 10

SBIT
2,[B]

RBIT
2,[B]

LO B,#05

IFBNEOA

JSR
xAOO-xAFF

JMP
xAOO-xAFF

JP +27

SBIT
3,[B]

RBIT
3,[B]

LO B,#04

IFBNEOB

JSR
xBOO-xBFF

JMP
xBOO-xBFF

JP +28

JP + 12

SBIT
4,rB]

RBIT
4,rB]

LO B,#03

IFBNEOC

JSR
xCOO-xCFF

JMP
xCOO-xCFF

JP +29

JP + 13

SBIT
5,[B]

RBIT
5,[B]

LO B,#02

IFBNEOO

JSR
xOOO-xOFF

JMP
xOOO-xOFF

JP +30

SBIT
6,[B]

RBIT
6,[B]

LO B,#01

IFBNEOE

JSR
xEOO-xEFF

JMP
xEOO-xEFF

JP +31

JP + 15

SBIT
7,[B]

RBIT
7,[B]

LO B,#OO

IFBNEOF

JSR
xFOO-xFFF

JMP
xFOO-xFFF

JP +32

IFBIT
1,[B]
IFBIT
2,[B]
IFBIT
3,[B]

o
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o

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r.......

o"'C
~

"'C
CD

Q)
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r.......

"'C
CD

or-

Where,
i is the immediate data
Md is a directly addressed memory location
• is an unused opcode
Note: The opcode 60 Hex is also the opcode for IFBIT #i,A

1-197

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oco
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.......

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o"'1:1"

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D.

o
.......
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oco

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D.

o
.......

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o
"'1:1"

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(S)
D.

.......

OPTION 1: CLOCK CONFIGURATION
1
Crystal Oscillator (CKI/10)
G7 (CKO) is clock generator
output to crystal/resonator
CKI is the clock input
2
Single-pin HC controlled
oscillator (CKI/10)
G7 is available as a HALT
restart and/or general purpose
input

=
=

The ice MASTER's performance analyzer offers a resolution
of better than 6 p.s. The user can easily monitor the time
spent executing specific portions of code and find "hot
spots" or "dead code". Up to 15 independent memory areas based on code address or label ranges can be defined.
Analysis results can be viewed in bar graph format or as
actual frequency count.

=
=

OPTION 3: BONDING
1
44-Pin PCC
2
40-Pin DIP
3
N.A.
4
2S-Pin DIP
5
2S-Pin SO

=
=
=
=
=

Development Support

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IN·CIRCUIT EMULATOR

'OPTION 2: HALT
1
Enable H~LT mode
2
Disable HALT mode

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many as 32k trace and break triggers which can be enabled,
disabled, set or cleared. They can be simple triggers based
on code or address ranges or complex triggers based on
code address, direct address, opcode value, opcode class
or immediate operand. Complex breakpoints can be ANDed
and ORed together. Trace information consists of address
bus values, opcodes and user-selectable probe clips status
(external event lines). The trace buffer can be viewed as
raw hex or as disassembled instructions. The probe clip bit
values can be displayed in binary, hex or digital waveform
formats.
'

Mask Options
The mask programmable options are shown below. The options are programmed at the same time as the ROM pattern
submission.

The MetaLink iceMASTERTM-COPS Model 400 In~Circuit
Emulator for the COPS family of microcontrollers features
high-performance operation, ease of use, and an extremely
flexible user-interface for maximum productivity. Interchangeable probe cards, which connect to the standard
common base, support the various configurations and packages of the COPS family.
The ice MASTER provides real-time,. full-speed. emulation,
up to 10 MHz,. 32 kBytes of emulation memory and 4k
frames of trace buffer memory. The user may define as

The ice MASTER comes with an easy to use windowed interface. Each window can be sized, highlighted, color-controlled, added, or removed completely. Commands can be
accessed via pull-down-menus and/or redefinable hot keys.
A context sensitive hypertextlhyperlinked on-line help system explains clearly the options the user has from within
any window.
The iceMASTER connects easily to a PC® via the standard
, COMM port and its 115.2 kBaud serial link keeps typical
program download time to under 3 seconds.
The following tables list the emulator and probe cards ordering information.

Emulator Ordering Information
Part Number

Description

IM-COPS/ 400/1:1:

MetaLink base unit in-circuit emulator for all COPS devices, symbolic debugger
software and RS-232 serial interface cable, with 11 OV @ 60 Hz Power Supply.

IM-COPS/400/2:j:

MetaLink base unit in-circuit emulator for all COPS devices, symbolic debugger
software and RS-232 serial interface cable, with 220V @ 50 Hz Power Supply.

DM-COPS/SSSCF:j:

MetaLink iceMASTER Debug Module. This is the low cost version of the MetaLink's
iceMASTER. Firmware: Ver. 6.07.

+These parts include National's COP8 Assembler/Linker/Librarian Package (COP8-DEV-IBMA).

1-19S

Current
Version

HOST SOFTWARE:
VER. 3.3 REV.5,
Model File Rev 3.050.

o
Probe Card Ordering Information
Part Number

Package

MHW-884CL28D5PC

Voltage
Range

Emulates

28DIP

4.5V-5.5V COP884CL

MHW-884CL28DWPC 28 DIP

2.3V-6.0V COP884CL

40 DIP

4.5V-5.5V COP888CL

MHW-888CL40DWPC 40 DIP

2.3V-6.0V COP888CL

MHW-888CL40D5PC
MHW-888CL44D5PC

44 PLCC 4.5V-5.5V COP888CL

r
.......

EMULATOR DEVICE

The COP8 family is fully supported by One-Time Programmabie (OTP) emulators. For more detailed information refer
to the emulation device specific data sheets and the emulator selection table below.

en
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OTP Ordering Information

National Semiconductor offers a COP8 macro cross assembler. It runs on industry standard compatible PCs and supports all of the full-symbolic debugging features of the MetaLink iceMASTER emulators.
Assembler Ordering Information

COP8-DEV-IBMA

COP8
Assemblerl
Linker I Librarian
for IBM®
PC/XT®, AT® or
compatible

Manual
424410632-001

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.......
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Clock
Option

Package

Emulates

COP8788CLV-X
COP8788CLV-R*

Crystal

44 PLCC

COP888CL

COP8788CLN-X
COP8788CLN-R*

Crystal

40 DIP

COP888CL

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COP8784CLN-X
COP8784CLN-R*

Crystal

28DIP

COP884CL

COP8784CLWM-X*
COP8784CLWM-R*

Crystal

28S0

COP884CL

Device Number

MACRO CROSS ASSEMBLER

Description

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Programming of the single-chip emulator devices is supported by different sources. The table below shows the programmers certified for programming the One-Time Programmabie (OTP) devices.

MHW-888CL44DWPC 44 PLCC 2.5V-6.0V CPP888CL

Part Number

PROGRAM SUPPORT

Development Support (Continued)

RIC
RIC

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.......
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RIC

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.......

RIC

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·Check with the local sales office about the availability.

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or
.......
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EPROM Programmer Information

co
Manufacturer
and Product

U.S. Phone
Number

Europe Phone
Number

Asia Phone
Number

MetaLinkDebug Module

(602) 926-0797

Germany:
+ 49-8141-1 030

Hong Kong:
+ 852-737-1800

XeltekSuperpro

(408) 745-7974

Germany:
+ 49-2041-684758

Singapore:
+ 65-276-6433

BP MicrosystemsEP-1140

(800) 225-2102

Germany:
+ 49-89-857-66-67

Hong Kong:
+ 852-388-0629

Data I/O-Unisite;
-System 29,
-System 39

(800) 322-8246

Europe:
+ 31-20-622866
Germany:
+ 49-89-85-8020

Japan:
+ 33-432-6991

Abcom-COP8
Programmer
System General
Turpro-1-FX;
-APRO

o
r

Europe:
+89-808707
(408) 263-6667

Switzerland:
+ 31-921-7844

Taiwan Taipei:
+2-9173005

1-199

..J

Development Support (Continued)

en
D..

DIAL-A-HELPER

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.......

Dial-A-Helper· is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Bulletin Board Information System.

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.......

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.......

Order PIN: MOLE-DIAL-A-HLP

Information System Package Contents
Dial-A-Helper User Manual PIN
Public Domain Communications Software

Information System
The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities could be found. The minimum requirement for accessing the Dial-A-Helper is a Hayes compatible
modem.

Factory Applications Support

Dial-A-Helper also provides immediate factor applications
support. If a user has questions, he can leave messages on
our electronic bulletin board, which we will respond to.
Voice: (800) 272-9959
Modem: CANADA/U.S.: (800) NSC-MICRO
(800) 672-6427

If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.

Baud:

14.4k

Set-up:

Length: 8-Bit
Parity:
None
Stop Bit: 1

Operation:

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1-200

24 Hrs.,' 7 Days

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tJ1National Semiconductor

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COP988CF I COP984CF I COP888CF I COP884CF
Single-Chip microCMOS Microcontroller
General Description
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconductor's M2CMOSTM process technology. The COP888CF is a
member of this expandable 8-bit core processor family of
microcontrollers.
(Continued)

Features
•
•
•
•
II
II

a
Ell

•
•
•

Low cost 8-bit microcontroller
Fully static CMOS, with low current drain
Two power saving modes: HALT and IDLE
1 !-,-S instruction cycle time
4096 bytes on-board ROM
128 bytes on-board RAM
Single supply operation: 2.5V-6V
8-channel AID converter with prescaler and both differential and single ended modes
MICROWIRE/PLUSTM serial I/O
WATCHDOGTM and Clock Monitor logic
Ten mUlti-source vectored interrupts servicing
- External Interrupt
- Idle Timer TO
- Two Timers (Each with 2 Interrupts)
- MICROWIRE/PLUS
- Multi-Input Wake Up
- Software Trap
- Default VIS
Idle Timer

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II Multi-Input Wakeup (MIWU) with optional interrupts (8)

-n
......

• Two 16-bit timers, each with two 16-bit registers
supporting:
- Processor Independent PWM mode
- External Event counter mode
- Input Capture mode
• 8-bit Stack Pointer SP (stack in RAM)
a Two 8-bit Register Indirect Data Memory Pointers
(B and X)
• Versatile instruction set
• True bit manipulation
• Memory mapped I/O
II BCD arithmetic instructions
II Package:
- 44 PLCC with 37 I/O pins
- 40 N with 33 I/O pins
- 28 SO or 28 N, each with 23 I/O pins
1:1 Software selectable I/O options
- TRI-STATE® Output
- Push-Pull Output
- Weak Pull Up Input
- High Impedance Input
.. Schmitt trigger inputs on ports G and L
I!I Temperature ranges:
O°C to + 70°C
- 40°C to + 85°C
• One-Time Programmable (OTP) emulation devices
II Real time emulation and full program debug offered by
Metalink's Development Systems

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Block Diagram

r----------------------,

II
CPU
REGISTERS

~----------------------~

FIGURE 1. Block Diagram

1-201

TL/DD/9425-1

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General Description

(Continued)

It is a fully static part, fabricated using double-metal silicon
gate microCMOS technology. Features include an 8-bit
memory mapped architecture, MICROWIRE/PLUS serial
I/O, two 16-bit timer/counters supporting three modes
(Processor Independent PWM generation, External Event
counter, and Input Capture mode capabilities), an 8-channel, 8-bit AID converter with both differential and single
ended modes, and two power savings modes (HALT and

IDLE), both with a multi-sourced wakeup/interrupt capability. This multi-sourced interrupt capability may also be used
independent of the HALT or IDLE modes. Each I/O pin has
software selectable. configurations. The device operates
over a voltage range of 2.5V to 6V. High throughput is
achieved with an efficient, regular instruction set operating
at a maximum of 1 /-Ls per instruction rate.

Connection Diagrams

co
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D..

Plastic Chip Carrier

Dual-In-Line Package

......

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D..

o
o

41 40
CKI

Vee
IO/ACHO
11/ACHI
12/ACH2

44 pin
PLCC

RESET

GNO

G1
GO

RESET

GNO

13/ACH3

CKI

14/ACH4

VCC

15/ACH5

10/ACHO

16/ACH6

11/ACH1

17/ACH7

12/ACH2

AGNO

13/ACH3

04·

14/ACH4

15/ACH5

40 pin
DIP

AGNO
TL/DD/9425-2

Top View
Order Number COP888CF-XXX/V
See NS Plastic Chip Package Number V44A
Dual-In-Llne Package
G4

G7
24

28 pin
DIP/SO

RESET

D3
21

AGND

D2
Dl

VREF

Order Number COP888F-XXX/N
See NS Molded Package Number N40A

GND

Vee

TL/DD/9425-4

CKI

Top View

VREF

TL/DD/9425-37

Top View
Order Number COP884CF-XXX/N
or COP884CF-XXX/WM
See NS Package Number D28G or M28B
FIGURE 2. Connection Diagrams
1-202

a"1J

Connection Diagrams (Continued)

(0
Q)

("0

Pinouts for 28-, 40- and 44-Pln Packages
Port
LO
L1
L2
L3
L4
L5
L6
L7
GO
G1
G2
G3
G4
G5
G6
G7
00
01
02
03
10
11
12
13
14
15
16
17
04
05
06

Type
I/O
liD
liD
liD
liD

I/O
I/O
liD
liD

WOOUT
I/O
liD
liD
liD

I
I/CKO

I
I
I
I
I
I
I
I

CO
C1
C2
C3
C4
C5
C6
C7

liD
liD
liD
liD
liD
liD
liD
liD

AGNO

MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
INT

AIt.Fun

T2A
T28

T18
T1A
SO
SK
SI
HALT Restart

0
0
0
0

VREF

AIt.Fun

ACHO
ACH1
ACH2
ACH3
ACH4
ACH5
ACH6
ACH7

28-Pin
Pack.
11
12
13
14
15
16
17
18
25
26
27
28
1
2
3
4
19
20
21
22
7
8

(')

40-Pin
Pack.
17
18
19
20
21
22
23
24
35
36
37
38
3
4
5
6
25
26
27
28
9
10
11
12
13
14

29
30
31
32
39
40
1
2

44-Pln
Pack.

19
20
25
26
27
28
39
40
41
42
3
4
5
6
29
30
31
32
9
10
11
12
13
14
15
16
33
34
35
36
43
44
1
2
21
22

.......

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(0
Q)

oI:lo

o
.......
o

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Q)
Q)
Q)

.......

a""C
Q)
Q)

oI:lo

10
9
6
23
5
24

+VREF
AGNO

Vee
GNO
CKI
RESET

1-203

16
15
8
33
7
34

24
18
17
8
37
7
38

Absolute Maximum Ratings

a..

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

co
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o
o

.......
LL

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a..

o
o.......

Supply Voltage (Vee>
Voltage at Any Pin
Total Current into Vee Pin (Source)

o
~

a..

.......

7V
-0.3V to Vee + 0.3V
100 mA

Parameter

Conditions

Operating Voltage
988CF
998CFH
Power Supply Ripple (Note 1)

Peak-to-Peak

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Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz
CKI = 4 MHz
CKI = 1 MHz

Vee
Vee
Vee
Vee

a..

o
o

HALT Current (Note 3)
IDLE Current
CKI = 10 MHz
CKI = 4 MHz
CKI = 1 MHz

+70°C unless otherwise specified
Min

Typ

2.5
4.0

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co

110 mA
- 65°C to + 140°C
Storage Temperature Range
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

DC Electrical Characteristics 988CF: O°C ~ TA ~

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Total Current out of GND Pin (Sink)

6V. tc
6V. tc
= 4V. tc
= 4V.tc

1 ,...s
2.5 ,...s
= 2.5,...s
= 10,...s

Vee = 6V. CKI = 0 MHz
Vee = 4.0V. CKI = 0 MHz

<0.7
<0.3

Vee = 6V. tc = 1 ,...s
Vee = 6V. tc = 2.5 ,...s
Vee = 4.0V. tc = 10,...s

Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low

Max

Units

4.0
6.0

V
V

0.1 Vee

12.5
5.5
2.5
1.4

mA
mA
mA
mA

8
4

,...A
,...A

3.5
2.5
0.7

mA
mA
mA

0.2 Vee

V
V

0.2 Vee

V
V

0.2 Vee

V
V

0.8 Vee

0.7 Vee

Hi-Z Input Leakage

Vee = 6V

-1

,...A

Input Pullup Current

Vee = 6V. VIN = OV

-40

-250

,...A

0.35 Vee

G and L Port Input Hysteresis
Output Current Levels
o Outputs
Source
Sink
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)

4V. VOH = 3.3V
2.5V, VOH = 1.8V
= 4V, VOL = 1V
= 2.5V, VOL = 0.4V

-0.4
-0.2
10
2.0

4V. VOH = 2.7V
2.5V, VOH = 1.8V
4V, VOH = 3.3V
2.5V, VOH = 1.8V
4V, VOL = O.4V
2.5V, VOL = O.4V

-10
-2.5
-0.4
-0.2
1.6
0.7

Vee
Vee
Vee
Vee

Vee
Vee
Vee
Vee
Vee
Vee

=
=
=
=
=

mA
rnA
mA
mA
-100
-33

,...A
,...A
mA
mA
mA
mA

Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, eKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from OSCillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee, Land GO-G5 configured as
outputs and set high. The D port set to zero. The AID is disabled. VREF is tied to AGND (effectively shorting the Reference resistor). The clock monitor is disabled.
1-204

DC Electrical Characteristics O°C ::;; TA ::;;
Parameter
TRI-STATE Leakage

+ 70°C unless otherwise specified (Continued)

Conditions

Typ

Min
-1

Vee = 6.0V

Allowable Sink/Source
Current per Pin
o Outputs (Sink)
All others

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(0

CO
CO

Max

Units

p.A

mA
mA

± 100

......
o
o

CO
CO
CO

1000

"T1
......
o

"T1
......
o
o

"tJ

Maximum Input Current
without Latchup (Note 6)

TA = 25°C

RAM Retention Voltage, Vr

500 ns Rise
and Fall Time (Min)

Load Capacitance on 02

Parameter

Conditions

Min

Typ

Units

Bits

Reference Voltage Input

AGND = OV

Vee

VREF = Vee

±1

LSB

Non-Linearity

VREF = Vee
Deviation from the
Best Straight Line

±%

LSB

VREF = Vee

±%

LSB

1.6

4.8

AGND

VREF

±%

LSB

Input Reference Resistance
Common Mode Input Range (Note 7)
DC Common Mode Error
Off Channel Leakage Current
On Che.nnel Lee.ke.ge Current

0.1

Conversion Time (Note 4)

"T1

JJ.A
1.67

p.A

AID Clock Frequency (Note 5)

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Max

Absolute Accuracy

CO
CO

5V ±10% (Vss - O.050V)::;; Any Input::;; (Vee + 0.050V)

Resolution

Differential Non-Linearity

o"T1

"tJ

Input Capacitance

AID Converter Specifications Vee =

MHz
A/D Clock
Cycles

Note 4: Conversion Time includes sample and hold time.
Note 5: See Prescaler description.
Note 6: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than Vee and the pins will
have sink current to Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vee!. The effective
resistance to Vee is 7500 (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 7: For VIN( -):?: VIN( +) the digital output code will be 0000 0000. Two on·chip diodes are tied to each analog input. The diodes will forward conduct for analog
input voltages below ground or above the Vee supply. Be careful, during testing at low Vee levels (4.5V), as high level analog inputs (5V) can cause this input diode
to conduct-especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This
means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 Voe to
5 Voe input voltage range will therefore require a minimum supply voltage of 4.950 Voe over temperature variations, initial tolerance and loading. The voltage at
any analog Input should be - 0.3V to Vee + 0.3V.

1-205

o
v

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co

AC Electrical Characteristics o·c : ; T A ::;; + 70·C unless otherwise specified

D-

Parameter

o
......
LL
o
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Instruction Cycle Time (td
Crystal, Resonator
RIC Oscillator

D-

o
......

tSETUP

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en

tHOLO

D-

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......
LL

Output Propagation Delay (Note 8)

oco

tpD1, tpoo
SO,SK

D-

All Others

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en

Min

4V::;; Vee::;; 6V
2.5V ::;; Vee < 4V
4V::;; Vee::;; 6V
2.5V ::;; Vee < 4V

1
2.5
7.5

4V::;; Vee::;; 6V
2.5V ::;; Vee < 4V
4V::;; Vee::;; 6V
2.5V ::;; Vee < 4V

200
500
60
150

Typ

Max

Units

DC
DC
DC
DC

,..,s
,..,s
,..,s
,..,s

Inputs

Conditions

ns
ns
ns
ns

RL = 2.2k, CL = 100 pF
4V::;; Vee::;; 6V
2.5V ::;; Vee < 4V
4V::;; Vee::;; 6V
2.5V ::;; Vee < 4V

MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tupo)

0.7
1.75
1
2.5

,..,s
,..,s
,..,s
,..,s

220

ns
ns
ns

20
56

Input Pulse Width
Interrupt Input High Time
Interrupt input Low Time
Timer Input High Time
Timer Input Low Time

1
1
1
1

tc
tc
tc
tc

Reset Pulse Width

,..,S

Note 8: The output propagation delay is referenced to the end of the insiruction cycle where the output change occurs.

~
,

tUWH

~tUPD

FIGURE 3. MICROWIRE/PLUS Timing

1·206

TL/DD/9425-26

o
o

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
Voltage at Any Pin

Total Current out of GNO Pin (Sink)
Storage Temperature Range

- 65°C to + 140°C

Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

7V
-0.3V to Vee + 0.3V

Total Current into Vee Pin (Source)

110 rnA

100mA

CD
(X)
(X)

o
"T1
o
""

o"C
CD

(X)
~

DC Electrical Characteristics 888CF:
Parameter

-40°C::;; TA ::;; + 85°C unless otherwise specified

Conditions

Operating Voltage
Peak-to-Peak

Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz

Vee = 6V, te = 1 /-Ls
Vee = 4V, te = 2.5 J-Ls

HALT Current (Note 3)

Vee = 6V, CKI = 0 MHz

Vee = 6V

TRI-STATE Leakage

0.1 Vee

12.5
2.5

rnA
rnA

J-LA
rnA
rnA

0.2 Vee

V
V

0.2 Vee

V
V

0.2 Vee

V
V

-2

J-LA

-40

-250

/-LA

0.35 Vee

G and L Port Input Hysteresis

Sink (Push-Pull Mode)

0.7 Vee

Vee = 6V, VIN = OV

Source (Push-Pull Mode)

0.7 Vee

Hi-Z Input Leakage

All Others
Source (Weak Pull-Up Mode)

Units

0.8 Vee

Input Pullup Current

Sink

Max

3.5
0.7

Vee = 6V, te = 1 /-Ls
Vee = 4V, te = 10 /-Ls

Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low

Output Current Levels
o Outputs
Source

Typ

2.5

Power Supply Ripple (Note 1)

IDLE Current
CKI = 10 MHz
CKI = 1 MHz

Min

Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee

= 4V, VOH = 3.3V
= 2.5V, VOH = 1.8V
= 4V, VOL = 1V
= 2.5V, VOL = O.4V
= 4V, VOH = 2.7V
= 2.5V, VOH = 1.8V
= 4V, VOH = 3.3V
= 2.5V, VOH = 1.8V
= 4V, VOL = O.4V
= 2.5V, VOL = O.4V

Vee = 6.0V

o"C
(X)
(X)
(X)

o"T1
o
""

o"C
(X)
(X)
~

o"T1

-,,-- --- . -- .. - .....- ..- -

-0.4
-0.2
10
2.0

rnA
rnA
rnA
rnA

-10
-2.5
-0.4
-0.2
1.6
0.7

-100
-33

-2

J-LA
/-LA
rnA
rnA
rnA
rnA
J-LA

1-207

o"T1
o
""

o
"11:2'

co
co

DC Electrical Characteristics 888CF:

Parameter

o
......
LL
o
co
co
co
D.

o
......
LL
o
"11:2'
co
en

Typ

Min

Maximum Input Current
without Latchup (Note 6)

TA = 25°C

RAM Retention Voltage, Vr

500 ns Rise
and Fall Time (Min)

Input Capacitance

o
......
LL
o
co

Load Capacitance on 02

co
en

Conditions

+ 85°C unless otherwise specified (Continued)

Allowable Sink/Source
Current per Pin
Outputs (Sink)
All others

-40°C::;; TA ::;;

Max

Units

mA
mA

±100

V
7

1000

AID Converter Specifications 888CF:
Vee = 5V ±10% (Vss -:- 0.050V) ::;; Any Input::;; (Vee

Parameter

O.050V)

Conditions

Min

Typ

Resolution

Max

Units

Bits

Vee

Reference Voltage Input

AGND = OV

Absolute Accuracy

VREF = Vee

±1

LSB

Non-Linearity

VREF = Vee
Deviation from the
Best Straight Line

±%

LSB

Differential Non-Linearity

±%

LSB

1.6

4.8

k!1

AGND

VREF

±%

LSB

VREF = Vee

Input Reference Resistance
Common Mode Input Range (Note 7)
DC Common Mode Error
Off Channel Leakage Current

On Channel Leakage Current

AID Clock Frequency (Note 5)

0.1

Conversion Time (Note 4)

p.A
p.A
1.67

MHz
AID Clock
Cycles

Note 4: Conversion Time includes sample and hold time.
Note 5: See Prescaler description.
Note 6: Pins G6 and ~ are designed with a high voltage input network for factory testing. These pins allow input voltages greater than Vee and the pins will
have sink current to Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vee). The effective
resistance to Vee is 7500 (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 7: ForVIN( -) 5

Power Supply Rise Time

FIGURE 5. Recommended Reset Circuit

1-212

(")

7. Clock Monitor current when enabled-17

The chip will draw more current as the CKI input frequency
increases up to the maximum 10 MHz value. Operating with
a crystal network will draw more current than an external
square-wave. Switching current, governed by the equation,
can be reduced by lowering voltage and frequency. Leakage current can be reduced by lowering voltage and temperature. The other two items can be reduced by carefully
designing the end-user's system.
12 = C x V x f

RIC OSCillATOR
By selecting CKI as a single pin oscillator input, a single pin
A/C oscillator circuit can be connected to it. CKO is available as a general purpose input, andlor HALT restart pin.

IL.,;C~KI;. . . _. .,;,;CKp,; O. . .1

TLlDD/9425-8

External interrupt edge polarity select
(0 = Aising edge, 1 = Falling edge)

MSEL

Selects G5 and G4 as MICAOWIAE/PLUS
signals SK and SO respectively
Timer T1 StartlStop control in timer
modes 1 and 2

T1 CO

R2
(MO)

C1
(!IF)

C2
(!"IF)

CKI Freq
(MH7)

Conditions

0
0
0

1
1
1

30
30
200

30-36
30-36
100-150

10
4
0.455

Vee = 5V
Vee = 5V
Vee = 5V

C
(pF)

CKI Freq
(MHz)

Instr. Cycle

3.3
5.6
6.8

82
100
100

2.2 to 2.7
1.1 to 1.3
0.9 to 1.1

3.7 to 4.6
7.4 to 9.0
8.8 to 10.8

(fL S )

T1 C1

Timer T1 mode control bit

T1C2
T1 C3

Tirm:lr T I mode control bit
Timer T1 mode control bit

IT1C31 T1C21 T1C1 I T1CO IMSEL IIEDG I SL1 I SLO
Bit7

TABLE B. RIC Oscillator Configuration, T A = 25°C
R
(kO)

"'1J

co
co
co

(")

........
(")

Timer T1 Underflow Interrupt Pending Flag in
timer mode 3

TABLE A. Crystal Oscillator Configuration, TA = 25°C
R1
(kO)

.1::10
(")

IEDG

FIGURE 6. Crystal and RIC Oscillator Diagrams

........

(")

"'1J

Control Registers

TL/DD/9425-9

.1::10
(")

co
co

CNTRl Register (Address X'OOEE)
The Timer1 (T1) and MICAOWIAE/PLUS control register
contains the following bits:
SL 1 & SLO Select the MICAOWIAE/PLUS clock divide
by (00 = 2,01 = 4, 1x = 8)

o"'1J

where C = equivalent capacitance of the chip
V = operating voltage
f = CKI frequency

Table B shows the variation in the oscillator frequencies as
functions of the component (A and C) values.

(")

To reduce the total current drain, each of the above components must be minimum.

Table A shows the component values required for various
standard crystal values.

(")

........

It = 11 + 12 + 13 + 14 + 15 + 16 + 17

CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.

"'1J

co
co

Thus the total current drain, It, is given as

CRYSTAL OSCillATOR

6. DC reference current contribution
from the AID converter-16

Oscillator Circuits

BitO

PSW Register (Address X'OOEF)
The PSW register contains the following select bits:
GIE
Global interrupt enable (enables interrupts)

Conditions

EXEN

Vee = 5V
Vee = 5V
Vee = 5V

Note: 3k ,;; R ,;; 200k
50 pF ,;; C ,;; 200 pF

Enable external interrupt

BUSY

MICAOWIAE/PLUS busy shifting flag

EXPND

External interrupt pending

T1 ENA

Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge

T1 PNDA Timer T1 Interrupt Pending Flag (Autoreload AA
in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3)

Current Drain
The total current drain of the chip depends on:
1. Oscillator operation mode-11
2. Internal switching current-12

Carry Flag

Half Carry Flag

I HC I C I T1 PNDA IT1 ENA I EXPND I BUSY IEXEN I GIE I

3. Internal leakage current-13

Bit7

4. Output source current-14
5. DC current caused by external input
not at Vee or GND-15

1-213

BitO

u.
o
~

Q)
Q)

D-

o
"u.
o
Q)
Q)
Q)

ICNTRL Register (Address X'OOES)

o
"u.
o
~

The ICNTRL register contains the following bits:

Q)
0)

D-

o
"u.
o
Q)
Q)
0)

D-

Exit out of the Idle Mode (See Idle Mode description)
WatchDog logic (See WatchDog description)
Start up delay out of the HALT mode

D-

The Timer TO supports the following functions:

Control Registers (Continued)

T1 ENB

The IDLE Timer TO can generate an interrupt when the thirteenth bit toggles. This toggle is latched into the TOPND
pending flag, and will occur every 4 ms at the maximum
clock frequency (te = 1 /Ls). A control flag TOEN allows the
interrupt from the thirteenth bit of Timer TO to be enabled or
disabled. Setting TOEN will enable the interrupt, while resetting it will disable the interrupt.

Timer T1 Interrupt Enable for T1 B Input capture
edge

TIMER T1 AND TIMER T2

T1 PNDB Timer T1 Interrupt Pending Flag for T1 B capture edge
/LWEN

The device has a set of two powerful timer/counter blocks,
T1 and T2. The associated features and functioning of a
timer block are described by referring to the timer block Tx.
Since the two timer blocks, T1 and T2, are identical, all comments are equally applicable to either timer block.

Enable MICROWIRE/PLUS interrupt

/LWPND MICROWIRE/PLUS interrupt pending
TOEN

Timer TO Interrupt Enable (Bit 12 toggle)

TOPND

Timer TO Interrupt pending

LPEN

L Port Interrupt Enable (Multi-Input Wakeup/Interrupt)

Bit 7 could be used as a flag
I Unused I LPEN I TOPNO I TOEN I /J,WPND IIJ.WEN I T1 PNDS I T1 ENS I
~7

T2CNTRL Register (Address X'OOCS)
The T2CNTRL register contains the following bits:
T2ENB

Timer T2 Interrupt Enable for T2B Input capture
edge
I
N

T2PNDB Timer T2 Interrupt Pending Flag for T2B capture edge
T2ENA

~~-t---------+I:~~~::~~------.Ji

Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge

N
A
l

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA
in mode 1, T2 Underflow in mode 2, T2A capture edge in mode 3)
T2CO

D
A

Timer T2 Start/Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3

T2C1

Timer T2 mode control bit

T2C2

Timer T2 mode control bit

T2C3

Timer T2 mode control bit

'--_-z~-.rt-------f.. A
B
U

M--------+..

/T2C3IT2C2IT2C1IT2coIT2PNDAIT2ENAIT2PNDBIT2ENBI
Bit 7

BitO

Timers

TLlDD/9425-11

FIGURE 7. Timers

The device contains a very versatile set of timers (TO, T1,
T2). All timers and associated autoreload/capture registers
power up containing random data.

easily perform all timer functions with minimal software
overhead. The timer block has three operating modes: Processor Independent PWM mode, Ex1ernal Event Counter
mode, and Input Capture mode.

Figure 7 shows a block diagram for the timers.

TIMER TO (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer TO, which is a
16-bit timer. The Timer TO runs continuously at the fixed
rate of the instruction cycle clock, te. The user cannot read
or write to the IDLE Timer TO, which is a count down timer.

The control bits TxC3, TxC2, and TxC1 allow selection of
the different modes of operation.

1-214

o
Timers

(Continued)

"'tJ

timer to be clocked either on a positive or negative edge
from the TxA pin. Underflows from the timer are latched into
the TxPNDA pending flag. Setting the TxENA control flag
will cause an interrupt when the timer underflows.

Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the COP888CF to
generate a PWM signal with very minimal user intervention.
The user only has to define the parameters of the PWM
signal (ON time and OFF time). Once begun, the timer block
will continuously generate the PWM signal completely independent of the microcontroller. The user software services
the timer block only when the PWM parameters require updating.

In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
Figure 9 shows a block diagram of the timer in External
Event Counter mode.

In this mode the timer Tx counts down at a fixed rate of tc.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
.
register RxB.

Note: The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock.

o"T1
o

"'tJ

U)
(X)
~

o
o

"'tJ

(X)
(X)
(X)

o"T1
o

nMER
UNDERflOW
INTERRUPT . - - - - . . . ,

The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.
Figure 8 shows a block diagram of the timer in PWM mode.

"'tJ

(X)
(X)
~

TxA

The underflows can be programmed to toggle the TxA output pin. The underflows can also be programmed to generate interrupts.

"T1

D
A
T

The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode.

Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once
per PWM period on either thA ri~ina or feJlina ed~e of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.

In this mode, the timer Tx is constantly running at the fixed
tc rate. The two registers, RxA and RxB, act as capture
rcg:~t~r~. =~:h rcg::.tcr ~ct:; ;ii CCi,JUiictivil 'w'w"ith a pin. Tha
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin.

TIMER
UNDERfLOW
INTERRUPT

U)
(X)
(X)

TXB~TO Interrupt Control
TL/DD/942S-14

FIGURE 9. Timer In External Event Counter Mode
Mode 3. Input Capture Mode

+------.

TxA
tC-------1

Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer TxCO
pending flag (the TxCO control bit serves as the timer underflow interrupt pending flag in the Input Capture mode). Consequently, the TxCO control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both

TL/DD/942S-13

FIGURE 8. Timer In PWM Mode
Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that
the timer, Tx, is clocked by the input signal from the TxA pin.
The Tx timer control bits, TxC3, TxC2 and TxC1 allow the

1-215

(.)
~

CX)
CX)

Timers (Continued)

£l.

whether a TxA input capture or a timer underflow (or both)
caused the interrupt.

......

Figure 10 shows a block diagram of the timer in Input Cap·
ture mode.

o(.)
LL

(.)

£l.

o(.)

......

(.)
~
CX)

£l.

TxA:2:

......

TxCO

TxB~

I
N
T
E
R
N
A
L

16 BIT TIMER

FINTA
INPUT CAPT1JRE
REG RA

EDGE SELECTOR
LOGIC

(.)

EDGE SELECTOR
LOGIC

CX)
CX)

The timers T1 and T2 have indentical control structures.
The control bits and their functions are summarized below.

,..

CX)
CX)
CX)

o(.)

TIMER CONTROL FLAGS

r
I
I

B
U
S

...

£l.

o(.)

TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag

0
A
T
A

FINTB
INPUT CAPT1JRE
REG RB

Timer Start/Stop control in Modes 1 and 2
(Processor Independent PWM and External
Event Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)

TxENA
TxENB

Timer Interrupt Enable Flag
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
o = Timer Interrupt Disabled

TxC3
TxC2
TxC1

Timer mode control
Timer mode control
Timer mode control

TL/DD/9425-15

FIGURE 10. Timer In Input Capture Mode
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below;
TxC3

TxC2

TxC1

Timer Mode

Interrupt A
Source

Interrupt B
Source

Timer
Counts On

MODE 2 (External
Event Counter)

Timer
Underflow

Pos.TxB
Edge

TxA
Pos.Edge

MODE 2 (External
Event Counter)

Timer
Underflow

Pos.TxB
Edge

TxA
Neg. Edge

MODE 1 (PWM)
TxA Toggle

Autoreload
RA

Autoreload
RB

MODE 1 (PWM)
No TxA Toggle

Autoreload
RA

Autoreload
RB

MODE 3 (Capture)
Captures;
TxA Pos. Edge
TxB Pos. Edge

Pos.TxA
Edge or
Timer
Underflow

Pos. TxB
Edge

MODE 3 (Capture)
Captures;
TxA Pos. Edge
TxB Neg. Edge

Pos. TxA
Edge or
Timer
Underflow

Neg. TxB
Edge

MODE 3 (Capture)
Captures;
TxA Neg. Edge
TxB Pos. Edge

Neg. TxB
Edge or
Timer
Underflow

Pos. TxB
Edge

MODE 3 (Capture)
Captures;
TxA Neg. Edge
TxB Neg. Edge

Neg. TxA
Edge or
Timer
Underflow

Neg. TxB
Edge

1·216

a"C

Power Save Modes
The device offers the user two power save modes of operation: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscillator circuitry and timer TO are active but all other microcontroller activities are stopped. In either mode, all on-board
RAM, registers, 1/0 states, and timers (with the exception of
TO) are unaltered.

If an RC clock option is being used, the fixed delay is introduced optionally. A control bit, CLKDLY, mapped as configuration bit G7, controls whether the delay is to be introduced or not. The delay is included if CLKDLY is set, and
excluded if CLKDL Y is reset. The CLKDLY bit is cleared on
reset.
The device has two mask options associated with the HALT
mode. The first mask option enables the HALT mode feature, while the second mask option disables the HALT
mode. With the HALT mode enable mask option, the device
will enter and exit the HALT mode as described above. With
the HALT disable mask option, the device cannot be placed
in the HALT mode (writing a "1" to the HALT flag will have
no effect).

HALT MODE
The device is placed in the HALT mode by writing a "1" to
the HALT flag (G7 data bit). All microcontroller activities,
including the clock, timers, and AID converter, are stopped.
The WatchDog logic is disabled during the HALT mode.
However, the clock monitor circuitry if enabled remains active and will cause the WatchDog output pin (WDOUT) to go
low. If the HALT mode is used and the user does not want
to activate the WDOUT pin, the Clock Monitor should be
disabled after the device comes out of reset (resetting the
Clock Monitor control bit with the first write to the WDSVR
register). In the HALT mode, the power requirements of the
device are minimal and the applied voltage (Vee> may be
decreased to Vr (Vr = 2.0V) without altering the state of the
machine.

"T1

"ao

(X)
~

"T1

"ao

"C
(X)
(X)
(X)

o"T1

The WatchDog detector circuit is inhibited during the HALT
mode. However, the clock monitor circuit if enabled remains
active during HALT mode in order to ensure a clock monitor
error if the device inadvertently enters the HALT mode as a
result of a runaway program or power glitch.

"ao

IDLE MODE

"T1

(X)
(X)
~

As with the HALT mode, the device can be returned to normal operation with a reset, or with a Multi-Input Wakeup
from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the thirteenth
bit (representing 4.096 ms at internal clock frequency of
1 MHz, tc = 1 ,...s) of the IDLE Timer toggles.
This toggle condition of the thirteenth bit of the IDLE Timer
TO is latched into the TOPND pending flag.

The device is placed in the IDLE mode by writing a "1" to
the IDLE flag (G6 data bit). In this mode, all activity, except
the associated on-board oscillator circuitry, the WatchDog
logic, the clock monitor and the IDLE Timer TO, is stopped.

The device supports three different ways of exiting the
HALT mode. The first method of exiting the HALT mode is
with the Multi-Input Wakeup feature on the L port. The second method is with a low to high transition on the CKO (G7)
pin. This method precludes the use of the crystal clock configuration (since CKO becomes a dedicated output), and so
may be used with an RC clock configuration. The third
method of exiting the HALT mode is by pulling the RESET
pin low.

t;icitt::; ci iiJlt;J ut::;lciY to t::;i"I::.ulti tilcit lilt! u::.cilldlOr

(X)
(X)

inutltlJ

stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the tc instruction cycle clock. The tc
clock is derived by dividing the oscillator clock down by a
factor of 10. The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE timer is clocked only
when the oscillator has a' sufficiently large amplitude to
meet the Schmitt trigger specifications. This Schmitt trigger
is not part of the oscillator closed loop. The startup timeout
from the IDLE timer enables the clock signals to be routed
to the rest of the chip.

Alternatively, the user can enter the IDLE mode with the
IDLE Timer TO interrupt disabled. In this case, the device
will resume normal operation with the instruction immediately following the "Enter IDLE Mode" instruction.
Note: It is necessary to program two NOP instructions following both the set
HALT mode and set IDLE mode instructions. These NOP instructions
are necessary to allow clock resynchronization following the HALT or
IDLE modes.

1-217

co
co
D-

o
......
~

oco
co
co
D-

o......
~

o
~

en
D-

o
......
~
o
co
co

D-

r-----------------------------------------------------------------------~

Multi-Input Wakeup
If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup/Interrupt, a safety procedure should also be followed to avoid inherited
pseudo wakeup conditions. After the selected L port bits
have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired
edge selects, followed by the associated WKPND bits being
cleared.

FIgure 11 shows the Multi-Input Wakeup logic.
The Multi-Input Wakeup feature utilizes the L Port. The user
selects which particular L port bit (or combination of L Port
bits) will cause the device to exit the HALT or IDLE modes.
The selection is done through the Reg: WKEN. The Reg:
WKEN is an 8-bit read/write register, which contains a control bit for every L port bit. Setting a particular WKEN bit
enables a Wakeup from the associated L port pin.

This same procedure should be used following reset, since
the L port inputs are left floating as a result of reset.
The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since WKPND is a pending
register for the occurrence of selected wakeup conditions,
the device will not enter the HALT mode if any Wakeup bit is
both enabled and pending. Consequently, the user has the
responsibility of clearing the pending flags before attempting to enter the HALT mode.

The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an 8bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.

The WKEN, WKPND and WKEDG are all read/write registers, and are cleared at reset.
PORT L INTERRUPTS

Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into
the same service subroutine.

RBIT
SBIT
RBIT
SBIT

5,
5,
5,
5,

WKEN
WKEDG
WKPND
WKEN

L7
WKEDG

WKPND
CHIP CLOCK

TLlDD/9425-16

FIGURE 11. Multi-Input Wake Up Logic

1-218

o
Multi-Input Wakeup

Allow any differential channel pair to be scanned continuously. In other words, the user will specify the differential
channel pair and the AID converter will keep on scanning
it continuously. The user can come in at any arbitrary time
and immediately read the result of the last differential
conversion. The user does not have to wait for the current conversion to be completed.

(Continued)

The GIE (global interrupt enable) bit enables the interrupt
function. A control flag, LPEN, functions as a global interrupt enable for Port L interrupts. Setting the LPEN flag will
enable interrupts and vice versa. A separate global pending
flag is not needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If
he elects to disable the interrupt, then the device will restart
execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or
IDLE modes. In the other case, the device will first execute
the interrupt service routine and then revert to normal operation.

The AID converter is supported by two memory mapped
registers, the result register and the mode control register.
When the device is reset, the control register is cleared and
the AID is powered down. The AID result register has unknown data following reset.

AID Control Register
A control register, Reg: ENAD, contains 3 bits for channel
selection, 3 bits for prescaler selection, and 2 bits for mode
selection. An AID conversion is initiated by writing to the
ENAD control register. The result of the conversion is available to the user from the AID result register, Reg: ADRSLT.

Reg: ENAD
ICHANNEL SELECTI MODE SELECTI PRESCALER
Bits 7,6,5

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Bits 2,1,0

CHANNEL SELECT
This 3-bit field selects one of eight channels to be the VIN +.
The mode selection determines the VIN- input.
Single Ended mode:
Bit 7
Bit 6

If the RC clock option is used, the fixed delay is under software control. A control flag, CLKDLY, in the G7 configuration bit allows the clock start up delay to be optionally inserted. Setting CLKDLY flag high will cause clock start up delay
to be inserted and resetting it will exclude the clock start up
delay. The CLKDLY flag is cleared during reset, so the clock

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Bits 4,3

SELEC~

Bit 5

Channel No.

0
0
0
1

1
0
1
0

1
0
0

2
3
4
5
6
7

re'3et '.'!ith the RC

Differential mode:

clock options.

AID Converter
The device contains an a-channel, multiplexed input, successive approximation, AID converter. Two dedicated pins,
VREF and AGND are provided for voltage reference.

Bit 7
0
0
0
0

Bit6
0
0

1
0
0

OPERATING MODES
The AID converter supports ratiometric measurements. It
supports both Single Ended and Differential modes of operation.

Bit5
0
0
1
0
1
0

Channel Pairs (+. -)
0,1
1,0
2,3
3,2
4,5
5,4
6, 7
7,6

MODE SELECT

Four specific analog channel selection modes are supported. These are as follows:

This 2-bit field is used to select the mode of operation (single conversion, continuous conversions, differential, single
ended) as shown in the following table.

Allow any specific channel to be selected at one time.
The AID converter performs the specific conversion requested and stops.
Allow any specific channel to be scanned continuously. In
other words, the user will specify the channel and the
AID converter will keep on scanning it continuously. The
user can come in at any arbitrary time and immediately
read the result of the last conversion. The user does not
have to wait for the current conversion to be completed.

Bit 4

Bit 3

Mode
Single Ended mode, single conversion
Single Ended mode, continuous scan
of a single channel into the result
register

Differential mode, single conversion
Differential mode, continuous scan of
a channel pair into the result register

Allow any differential channel pair to be selected at one
time. The AID converter performs the specific differential
conversion requested and stops.

1-219

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AID Converter (Continued)

PRESCALER SELECT

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This 3·bit field is used to select one of the seven prescaler
clocks for the AID converter. The prescaler also allows the
AID clock inhibit power saving mode to be selected. The
following table shows the various prescaler options.

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0
0
0
0

Bit 1
0
0

0
0

......

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0
1
0
0
1
0

Clock Select
Inhibit AID clock
Divide by 1
Divide by 2
Divide by4
Divide by6
Divide by 12
Divide by8
Divide by 16

ADC Operation

The AID converter interface works as follows. Writing to the
AID control register ENAD initiates an AID conversion unless the prescaler value is set to 0, in which case the ADC
clock is stopped and the ADC is powered down. The conversion sequence starts at the beginning of the write to
ENAD operation powering up the ADC. At the first falling
edge of the converter clock following the write operation
(not counting the falling edge if it occurs at the same time as
the write operation ends), the sample signal turns on for two
clock cycles. The ADC is selected in the middle of the sample period. If the ADC is in single conversion mode, the
conversion complete signal from the ADC will generate a
power down for the AID converter. If the ADC is in continuous mode, the conversion complete signal will restart the
conversion sequence by deselecting the ADC for one converter clock cycle before starting the next sample. The ADC
8-bit result is loaded into the AID result register (ADRSLT)
except during LOAD clock high, which prevents transient
data (resulting from the ADC writing a new result over an old
one) being read from ADRSLT.
PRESCALER

The AID converter takes 12 ADC clock cycles to complete
a conversion. Thus the minimum ADC conversion time for
the device is 7.2 f-Ls when a prescaler of 6 has been selected. These 12 ADC clock cycles necessary for a conversion
consist of 1 cycle at the beginning for reset, 2 cycles for
sampling, 8 cycles for converting, and 1 cycle for loading
the result into the AID result register (ADRSLT). This AID
result register is a read-only register. The device cannot
write into ADRSLT.
The prescaler also allows an AID clock inhibit option, which
saves power by powering down the AID when it is not in
use.
Note: The AID converter is also powered down when the device is in either
the HALT or IDLE modes. If the ADC is running when the device
enters the HALT or IDLE modes, the ADC will power down during the
HALT or IDLE, and then will reinitialize the conversion when the device comes out of the HALT or IDLE modes.

Analog Input and Source Resistance Considerations
Figure 12 shows the AID pin model in single ended mode.
The differential mode has similiar AID pin model. The leads
to the analog inputs should be kept as short as possible.
Both noise and digital clock coupling to an AID input can
cause conversion errors. The clock lead should be kept
away from the analog input line to reduce coupling. The AID
channel input pins do not have any internal output driver
circuitry connected to them because this circuitry would
load the analog input signals due to output buffer leakage
current.
Source impedances greater than 1 kn on the analog input
lines will adversely affect internal RC charging time during
input sampling. As shown in Figure 12, the analog switch to
the DAC array is closed only during the 2 AID cycle sample
time. Large source impedances on the analog inputs may
result in the DAC array not being charged to the correct
voltage levels, causing scale errors.
If large source resistance is necessary, the recommended
solution is to slow down the AID clock speed in proportion
to the source resistance. The AID converter may be operated at the maximum speed for Rs less than 1 kn. For Rs
greater than 1 kn, AID clock speed needs to be reduced.
For example, with Rs = 2 kn, the AID converter may be
operated at half the maximum speed. AID converter clock
speed may be slowed down by either increasing the AID
prescaler divide-by or decreasing the CKI clock frequency.
The AID clock speed may be reduced to its minimum frequency of 100 kHz.

The AID Converter (ADC) contains a prescaler option which
allows seven different clock selections. The AID clock frequency is equal to CKI divided by the prescaler value. Note
that the prescaler value must be chosen such that the AID
clock falls within the specified range. The maximum AID
frequency is 1.67 MHz. This equates to a 600 ns ADC clock
cycle.

Vee
<2 )J.A
JUNCTION

DIFFUSION/POLY

LEAKAGE

COUPLER
4.5k

<2 )J.A
JUNCTION

LEAKAGE

~ <25 pF

DAC

ARRAY

AGND

TLlDD/9425-28

'The analog switch is closed only during the sample time.

FIGURE 12. AID Pin Model (Single Ended Mode)

1-220

a-a

Interrupts
The device supports a vectored interrupt scheme. It supports a total of ten interrupt sources. The following table
lists all the possible interrupt sources, their arbitration ranking and the memory locations reserved for the interrupt vector for each source.

Thus, if an interrupt with a higher rank than the one which
caused the interruption becomes active before the decision
of which interrupt to service is made by the VIS, then the
interrupt with the higher rank will override any lower ones
and will be acknowledged. The lower priority interrupt(s) are
still pending, however, and will cause another interrupt immediately following the completion of the interrupt service
routine associated with the higher priority interrupt just serviced. This lower priority interrupt will occur immediately following the RETI (Return from Interrupt) instruction at the
end of the interrupt service routine just completed.

Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software
interrupt are maskable. Each of the maskable interrupts
have an Enable bit and a Pending bit. A maskable interrupt
is active if its associated enable and pending bits are set. If
GIE = 1 and an interrupt is active, then the processor will
be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described
in the Software Trap sub-section.

The VIS instruction looks at all the active interrupts at the
time it is executed and performs an indirect jump to the
beginning of the service routine of the one with the highest
rank.

1. The GIE (Global Interrupt Enable) bit is reset.
2. The address of the instruction about to be executed is
pushed into the stack.

(1) Highest

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00
~

o"T1

.........

-a

00
00
00

o"T1

.........

a-a
00
00
~

o"T1

VIS and the vector table must be located in the same 256byte block (OyOO to OyFF) except if VIS is located at the last
address of a block. In this case, the table must be in the
next block. The vector table cannot be inserted in the first
256-byte block.
The vector of the maskable interrupt with the lowest rank is
located at OyEO (Hi-Order byte) and OyE1 (Lo-Order byte)
and so forth in increasing rank number. The vector of the

Description

Source

Ranking

00
00

o"T1
.........
o

3. The PC (Program Counter) branches to address OOFF.
This procedure takes 7 tc cycles to execute.

Arbitr!'!t!l)n

Vector
Address
HI-Low Byte

Software

INTR Instruction

OyFE-OyFF

Reserved

for Future Use

OyFC-OyFD

(2)

External

Pin GO Edge

OyFA-OyFB

(3)

Timer TO

Underflow

OyFB-OyF9

(4)

TimerT1

T1 A/Underflow

OyF6-0yF7

(5)

TimerT1

T1B

OyF4-0yF5

(6)

MICROWIRE/PLUS

BUSY Goes Low

OyF2-0yF3

Reserved

for Future Use

OyFO-OyF1

Reserved

for UART

OyEE-OyEF

Reserved

for UART

OyEC-OyED

(7)

TimerT2

T2A1Underflow

OyEA-OyEB

(B)

TimerT2

T2B

OyEB-OyE9

Reserved

for Future Use

OyE6-0yE7

Reserved

for Future Use

OyE4-0yE5

(9)

Port LlWakeup

Port LEdge

OyE2-0yE3

(10) Lowest

Default

VIS Instr. Execution
without Any Interrupts

OyEO-OyE1

y is VIS page, y =1= 0

1-221

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Interrupts (Continued)

D-

0
.......

. SOnwARE

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TIMER Tl AND T2

D-

EXTERNAL

0
.......
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MULTI-INPUT WAKE UP

INTERRUPT

D-

}.'WIRE/PLUS

0
.......
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FUTURE PERIPHERALS

D-

IDLE TIMER

0
0

TLlDD/9425-18

FIGURE 13. Interrupt Block Diagram
maskable interrupt with the highest rank is located at OyFA
(Hi-Order byte) and OyFB (Lo-Order byte).

the absence of a clock or a very slow clock below a specified rate on the, CKI pin.

The Software Trap has the highest rank and its vector is
located at OyFE and OyFF.

The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper. limit on the service window and WD LOWER defines
the lower limit of the service window.

If, by accident, a VIS gets executed and no interrupt is active, then the PC (Program Counter) will branch t6 a vector
located at OyEO-OyE1. This vector can point to the Software Trap (Sn interrupt service routine, or to another special service routine as desired.

Figure 13 shows the Interrupt block diagram.

Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5bit Key Data field. The key data is fixed at 01100. Bit 0 of the
WDSVR Register is the Clock Monitor Select bit.

The occurrence of an ST is latched into the ST pending bit.
The GIE bit is not affected and the ST pending bit (not
accessible by the user) is used to inhibit other interrupts
and to direct the program to the ST service routine with the
VIS instruction. The RPND instruction is used to clear the
software interrupt pending bit. This bit is also cleared on
reset.

TABLE I. WATCHDOG Service Register
Window
Select

The ST has the highest rank among all interrupts.

Clock
Monitor

Key Data

I1 I

TABLE II. WATCHDOG Service Window Select

Nothing (except another ST) can interrupt an ST being
serviced.

WDSVR
Bit7

WDSVR
Bit6

0
0
1
1

0
1
0
~

Service Window
(Lower-Upper limits)
2k-8k te Cycles
2k-16k te Cycles
2k-32k te Cycles
. 2k-64k te Cycles

~-------------------------------------------------------------------'O

Clock Monitor
The Clock Monitor aboard the device can be selected or
deselected under program control. The Clock Monitor is
guaranteed not to reject the clock if the instruction cycle
clock (1 ltd is greater or equal to 10kHz. This equates to a
clock input rate on CKI of greater or equal to 100 kHz.

The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum specified value, after which the G1 output will enter the high impedance TRI-STATE mode following 16 te-32 te clock cycles. The Clock Monitor generates a continual Clock Monitor error if the oscillator fails to start, or fails to reach the
minimum specified frequency. The specification for the
Clock Monitor is as follows:

WATCHDOG Operation
The WATCHDOG and Clock Monitor are disabled during
reset. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG Window Select (bits 6, 7 of the
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
WDSVR Register) enabled. Thus, a Clock Monitor error will
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, including the case where the oscillator fails to start.
The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the WATCHDOG service window and match the WATCHDOG key data. Subsequent writes to the WDSVR register
will compare the value being written by the user to the
WATCHDOG service window value and the key data (bits 7
through 1) in the WDSVR Register. Table III shows the sequence of events that can occur.
The user must service the WATCHDOG at least once before the upper limit of the service window expires. The
WATCHDOG may not be serviced more than once in every
lower limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period
between the lower and upper limits of the service window.
The first write to the WDSVR Register is also counted as a
WATCHDOG service.
The WATCHDOG h9.S e.n output p!n 9.ssod9.ted '.Afith it. Th!s
is the WDOUT pin, on pin 1 of the port G. WDOUT is active
low. The WDOUT pin is in the high impedance state in the
inactive state. Upon triggering the WATCHDOG, the logic
will pull the WDOUT (G1) pin low for an additional
16 te-32 te cycles after the signal level on WDOUT pin goes
below the lower Schmitt trigger threshold. After this delay,
the device will stop forcing the WDOUT output low.

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WATCHDOG AND CLOCK MONITOR SUMMARY

The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted:

•

Both the WATCHDOG and Clock Monitor detector circuits are inhibited during RESET.

•

Following RESET, the WATCHDOG and CLOCK MONITOR are both enabled, with the WATCHDOG having the
maximum service window selected.

•

The WATCHDOG service window and Clock Monitor enable/disable option can only be changed once, during
the initial WATCHDOG service following RESET.

•

The initial WATCHDOG service must match the key data
value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error.

•

Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG errors.

•

The correct key data value cannot be read from the
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all O's.

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the HALT and IDLE modes.

The WATCHDOG service window will restart when the
WDOUT pin goes high. It is recommended that the user tie
the WDOUT pin back to Vee through a resistor in order to
pull WDOUT high.

•

The Clock Monitor detector circuit is active during both
the HALT and IDLE modes. Consequently, the device
inadvertently entering the HALT mode will be detected
as a Clock Monitor error (provided that the Clock Monitor
enable option has been selected by the program).

•

With the single-pin R/C oscillator mask option selected
and the CLKDLY bit reset, the WATCHDOG service window will resume following HALT mode from where it left
off before entering the HALT mode.

TABLE III WATCHDOG Service Actions
Key
Data

Window
Data

Clock
Monitor

Action

Match

Valid Service: Restart Service Window

Don't Care

Mismatch

Don't Care

Error: Generate WATCHDOG Output

Mismatch

Don't Care

Error: Generate WATCHDOG Output

Don't Care

Mismatch

Error: Generate WATCHDOG Output

1-223

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WATCHDOG Operation

• The IDLE timer TO is not initialized with RESET.

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• The user can sync in to the IDLE counter cycle with an
IDLE counter (TO) interrupt or by monitoring the TOPND
flag. The TOPND flag is set whenever the thirteenth bit of
the IDLE counter toggles (every 4096 instruction cycles).
The user is responsible for resetting the TOPND flag.

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Detection of Illegal Conditions

(Continued)

The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.

• With the crystal oscillator mask option selected, or with
the single-pin RIC oscillator mask option selected and
the CLKDLY bit set, the WATCHDOG service window will
be set to its selected value from WDSVR following
HALT. Consequently, the WATCHDOG should not be
serviced for at least 2048. instruction cycles following
HALT, but must be serviced within the selected window
to avoid a WATCHDOG error.

• A hardware WATCHDOG service occurs just as the device exits the IDLE mode. Consequently, the WATCHDOG should not be serviced for at least 2048. instruction
cycles following IDLE, but must be serviced within the
selected window to avoid a WATCHDOG error.
•

Thus, the chip can detect the following illegal conditions:

Following RESET, the initial WATCHDOG service (where
the service window and the CLOCK MONITOR enablel
disable must be selected) may be programmed anywhere within the maximum service window (65,536 instruction cycles) initialized by RESET. Note that this initial WATCHDOG service may be programmed within the
initial 2048. instruction cycles without causing a WATCH~
DOG error.

a. Executing from undefined ROM
b. Over "POP"ing the stack by having more returns than
calls.
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that
following reset, but might not contain the same program
initialization procedures).

1-224

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MICROWIRE/PLUS

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The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIREI
PLUS arrangement with the internal clock source is called
the Master mode of operation. Similarly, operating the MICROWIRE/PLUS arrangement with an external shift clock
is called the Slave mode of operation.

.oOIIIIl-. .....

2 x tc

1
x

4 X tc
8 X tc

."
.......

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(Q
Q)
~

MICROWIRE/PLUS OPERATION

.......

Setting the BUSY bit in the PSW register causes the MICROWIRE/PlUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PlUS
mode either as a Master or as a Slave. Figure 15 shows
how two COP888CF microcontrollers and several peripherals may be interconnected using the MICROWIRE/PlUS
arrangements.

o"'0

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Q)
Q)

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.......

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~

CHIP SELECT LINES

:...±= ..:..L
cs
Cs
8 - BIT
A/D
COP·OX

EEPROM

DO SK 01

! t

Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PlUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is
low.

The CNTRl register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PlUS,
the MSEl bit in the CNTRl register is set to one. In the
master mode the SK clock rate is selected by the two bits,
SlO and Sl1, in the CNTRl register. TABLE IV details the
different clock rates that may be selected.

, ..,.

0
0

Warning:

TL/DD/9425-20

COP8
(MASTER)

FIGURE 14. MICROWIRE/PLUS Block Diagram

I/O
LINES

SLO

Where tc is the instruction cycle clock

~~--~~------------~SO

,,5

SL1

J------+ INTERRUPT

(Q
Q)
Q)

TABLE IV. MICROWIRE/PLUS
Master Mode Clock Selection

MICROWIRE/PlUS is a serial synchronous communications interface. The MICROWIRE/PlUS capability enables
the device to interface with any of National Semiconductor's
MICROWIRE peripherals (Le. AID converters, display drivers, E2PROMs etc.) and with other microcontrollers which
support tho MICROWIRE interfaco. It consists of an 8-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK). Figure 14
shows a block diagram of the MICROWIRE/PlUS logic.

.---

-.:-

LCD
DISPLAY
DRIVER
COP472

VF
DISPLAY
DRIVER

SK 01

I/O
COP8
(SLAVE)

SO
--,.
~

51
SK
L.....-.-

FIGURE 15. MICROWIRE/PLUS Application

1-225

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,......LINES....
...,..

TLlDD/9425-21

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MICROWIRE/PLUS (Continued)

Memory Map

MICROWIRE/PLUS Slave Mode Operation

All RAM, ports and registers (except A and PC) are mapped
into data memory address space

In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bit in the Port G configuration register. Table V summarizes the settings required to enter the
Slave mode of operation.
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated.

Alternate SK Phase Operation

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0)
D..

The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register.
In both the modes the SK is normally low. In the normal
mode data is shifted in on the rising edge of the SK clock
and the data is shifted out on the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK clock in the normal mode. In the alternate SK phase
mode the SIO register is shifted on the rising edge of the SK
clock.

oco

Address
00 to 6F

G4
Fun.
SO

G5
Fun.

Operation

Int. MICROWIRE/PLUS
SK Master

TRIInt. MICROWIRE/PLUS
STATE SK Master
SO

Ext. MICROWIRE/PLUS
SK Slave

TRI- Ext. MICROWIRE/PLUS
STATE SK Slave

Contents
On-Chip RAM bytes

70 to BF

Unused RAM Address Space

CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CDto CF

DO
01
02
03
04
05
06
07
08
09
DA
DB
DC
DDto OF

Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port 0 Data Register
Reserved for Port 0

EO to E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF

FO to FB
FC
FD
FE
FF

On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
Reserved

Reading memory locations 70-7F Hex will return all ones. Reading other
unused memory locations will return undefined data.

1-226

o
o

Addressing Modes

"'C
<0

The device has ten addressing modes, six for operand ad·
dressing and four for transfer of control.

co
co

OPERAND ADDRESSING MODES
Register Indirect
This is the "normal" addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.
Register Indirect (with auto post Increment or
decrement of pointer)
This addressing mode is used with the LD and X instruc·
tions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that
~utomatically post increments or decrements the B or X reg·
Ister after executing the instruction.
Direct
'

o
"T1
......

A
B
X
SP
PC
PU
PL
C
HC
GIE

This addressing mode is used with the Load B Immediate
instruction. The instruction contains a 4-bit immediate field
as the operand.
Indirect
This addressing mode is used with the LAID instruction. The
~ontents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.

VU
VL

TRANSFER OF CONTROL ADDRESSING MODES

Instruction Set
Registers

Short Immediate

"'C
<0

"T1
......
o

The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
The instruction contains an 8-bit immediate field as the op·
erand.

Immediate

"T1
......

Relative

"'C

co
co
co

"'C

co
co
~

"T1

Symbols

This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
program location. JP has a range from .-31 to + 32 to allow
it l-uyLti rdalivtI jump (JP + 1 is implemented by a NOP
instruction). There are no "pages" when using JP, since all
15 bits of PC are used ..

[B)

[X}
MD
Mem
Meml

Absolute
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any loca·
tion in the current 4k program memory segment.

Imm
Reg

Absolute Long

Bit

This mode is used with the JMPL and JSRL instructions
with the instruction field of 15 bits replacing the entire 15
bits of the program counter (PC). This allows jumping to any
location in the current 4k program memory space.

Memory Indirectly Addressed by B
Register
Memory Inoirectly Addressed by X
Register
Direct Addressed Memory
Direct Addressed Memory or [B)
Direct Addressed Memory or [B) or
Immediate Data
8-Bit Immediate Data
Register Memory: Addresses FO to FF
(Includes B, X and SP)
Bit Number (0 to 7)
Loaded with
Exchanged with

1-227

u.
o

Instruction Set (Continued)

INSTRUCTION SET

.......

oco

co
co
O
o
.......
D-

u.
o
~

co
en
O
o
.......
D-

u.
o
co
co
en
O

D-

A ~ A + Meml
A ~ A + Meml + C, C ~ Carry
HC ~ Half Carry
A ~ A Meml + C, C ~ Carry
HC ~ Half Carry
A ~ AandMeml
Skip next if (A and Imm) = 0
A ~ AorMeml
A ~ AxorMeml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do riext if A
Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B
Imm
Reg ~ Reg- 1, Skip if Reg = 0
1 to bit, Mem (bit = 0 to 7 immediate)
Oto bit, Mem
If bit in A or Mem is true do next instruction
Reset Software Interrupt Pending Flag

ADD
ADC

A,Meml
A,Meml

ADD
ADD with Carry

SUBC

A,Meml

Subtract with Carry

AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND

A,Meml
A,lmm
A,Meml
A,Meml
MD,Imm
A,Meml
A,Meml
A,Meml
#
Reg
#,Mem
#,Mem
#,Mem

X
X
LD
LD
LD
LD
LD

A,Mem
A,[X]
A,Meml
A,[X]
B,lmm
Mem,lmm
Reg,lmm

EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD B with Immed.
LoaD Memory Immed
LoaD Register Memory Immed.

X
X
LD
LD
LD

A, [B ±]
A, [X ±]
A, [B±]
A, [Xi]
[B±],lmm

EXchange A with Memory [B)
EXchange A with Memory [X]
LoaD A with Memory [B)
LoaD A with Memory [X]
LoaD Memory [B) Immed.

A ~ [B],(B ~ B ±1)
A ~ [X], (X ~ ±1)
A ~[B],(B ~B±1)
A ~ [X], (X ~ X±1)
[B) ~ Imm, (B ~ B±1)

CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH

A
A
A

CLeaR A
INCrementA
DECrementA
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
SetC
ResetC
IFC
IF NotC
POP the stack into A
PUSH A onto the stack

A~O

A~ A+ 1
A ~ A-1
A ~ ROM (PU,A)
A ~ BCD correction of A (fOllows ADC, SUBC)
C ---+ A 7 ---+ '" ---+ AO ---+ C
C ~ A7 ~ '" ~ AO ~ C
A7 ... A4 ~ A3 ... AO
C ~ 1,HC ~ 1
C ~ O,HC ~ 0
IF C is true, do next instruction
If C is not true, do next instruction
SP ~ SP + 1, A ~ [SP]
[SP] ~ A, SP ~ SP - 1

PU ~ [VU], PL ~ [VL]
PC ~ ii (ii = 15 bits, 0 to 32k)
PCg ... 0 ~ i (i = 12 bits)
PC ~ PC + r (r is -31 to + 32, except 1)
[SP] ~ PL, [SP-1] ~ PU,SP-2, PC ~ ii
[SP] ~ PL, [SP-1] ~ PU,SP-2, PCg ... 0 ~ i
PL ~ ROM (PU,A)
SP + 2, PL ~ [SP], PU ~ [SP-1]
SP + 2, PL ~ [SP],PU ~ [SP-1]
SP + 2, PL ~ [SP],PU ~ [SP-1],GIE ~ 1
[SP] ~ PL, [SP-1] ~ PU, SP-2, PC ~ OFF
PC ~ PC + 1

VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
Nap

A
A
A
A

A
A
Addr.
Addr.
Disp.
Addr.
Addr

1-228

Mem

A~[X]

Meml
[X]
B ~ Imm
Mem ~ Imm
Reg ~ Imm

(')

Instruction Execution Time
Most instructions are single byte (with immediate addressing mode instructions taking two bytes).

Instructions Using A & C
CLRA
INCA
DECA
LAID
DCOR
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ

Direct

ADD
ADC
SUBC
AND
OR
XOR
IFEO
IFNE
IFGT
IFBNE
DRSZ

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4

SBIT
RBIT
IFBIT

1/1
1/1
1/1

3/4
3/4
3/4

RPND

1/1

Immed.
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2

1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2

Transfer of Control
Instructions
JMPL
JMP
JP
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP

3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
1/7
1/1

0
"'C
co
co
co

(')

"T1

"'(')
0
"'C
co
co

(')

"T1

"'(')
0
"'C

co
co
co

(')

"T1

"'(')

"'C

co
co
~

(')

"T1

1/3

Memory Transfer Instructions
Register
Indirect

XA,·
LOA,·
LDB,lmm
LDB,lmm
LD Mem, Imm
LD Reg, Imm
IFEOMD,lmm
• =

h~]

[X]

1/1
1/1

1/3
1/3

2/2

Direct Immed.

2/3
2/3

2/2
1/1
2/2

3/3
2/3
3/3

[X+,X-]

1/2
1/2

1/3
1/3
(IFB < 16)
(IFB> 15)

2/2

> Memory location addressed by B or X or directly.

1-229

o
-.::to

co
co

o
o

'"
~

.------------------------------------------------------------------------------,
Opcode Table
Upper Nibble Along X-Axis
Lower Nibble Along Y-Axis

o
co

JP -15

JP -31

LDOFO, # i

DRSZOFO

RRCA

ADCA,#i

ADCA,[S]

JP -14

JP -30

LD OF1, # i

DRSZOF1

SUSCA, #i

SUS A,[S]

co
en

JP -13

JP -29

LDOF2, #,i

DRSZOF2

XA,[X+]

XA,[S+]

IFEQ A,#i

IFEQA,[S]

JP -12

JP -28

LDOF3, # i

DRSZOF3

XA, [X-]

XA,[S-]

IFGTA,#i

IFGT A,[S]

'"
oco

JP -11

JP -27

LD OF4, # i

DRSZOF4

VIS

LAID

ADDA,#i

ADDA,[S]

JP -10

JP -26

LDOF5, # i

DRSZOF5

RPND

JID

ANDA,#i

ANDA,[S]

JP -9

JP -25

LDOF6, # i

DRSZOF6

XA,[X]

XA,[S]

XORA,[S]

JP -8

JP -24

LDOF7, # i

DRSZOF7

XORA,#i
ORA,#i

ORA,[S]

JP -7

JP -23

LD OF8, # i

DRSZOF8

NOP

RLCA

LDA,#i

IFC

JP -6

JP -22

LDOF9, # i

DRSZOF9

IFNC

co
co

o
o

o
-.::to

co
en
Q.

IFNE

IFEQ

IFNE

A,[S]

Md,#i

A,#i

JP -5

JP -21

LDOFA, # i

DRSZOFA

LDA,[X+]

LDA,[S+]

LD [S+ ],#i

INCA

JP -4

JP -20

LDOFS, #i

DRSZOFS

LDA,[X-]

LDA,[S-]

LD [S-],#i

DECA

JP -3

JP -19

LDOFC, # i

DRSZOFC

LD Md,#i

JMPL

XA,Md

POPA

JP -2

JP -18

LDOFD, # i

DRSZOFD

DIR

JSRL

LDA,Md

RETSK

JP -1

JP -17

LDOFE, # i

DRSZOFE

LDA,[X]

LDA,[S]

LD[S],#i

RET

JP -0

JP -16

LDOFF, # i

DRSZOFF

LDS,#i

RETI

1-230

Opcode Table

o"C

(Continued)

(0
0)
0)

Upper Nibble Along X-Axis

Lower Nibble Along Y-Axis

IF81T
0,[8]

ANDSZ
A, #i

LD 8,#OF
LD 8,#OE

IF81T
1,[8]
IF81T
2,[8]

·
·

LD 8,#OD

"T1
......

IF8NEO

JSR
xOOO-xOFF

JMP
xOOO-xOFF

JP +17

INTR

IF8NE 1

JSR
x100-x1FF

JMP
x100-x1FF

JP +18

JP + 2

JSR
x200-x2FF

JMP
x200-x2FF

JP +19

IF8NE2

(0
0)

JP +'3

IF8NE 3

JSR
x300-x3FF

JMP
x300-x3FF

JP +20

JP + 4

IF81T
4,[8]

CLRA

LD 8,#08

IF8NE4

JSR
x400-x4FF

JMP
x400-x4FF

JP +21

JP + 5

IF81T
5,[8]

SWAPA

JSR
x500-x5FF

JMP
x500-x5FF

JP +22

IF81T
6,[8]

DCORA

LD 8,#09

IF8NE 6

JSR
x600-x6FF

JMP
x600-x6FF

JP +23

JP + 7

IF81T
7,[8]

PUSHA

LD 8,#08

IF8NE 7

JSR
x700-x7FF

JMP
x700-x7FF

JP +24

JP + 8

S81T
0,[8]

R81T
0,[8]

LD 8,#07

IF8NE8

JSR
x800-x8FF

JMP
x800-x8FF

JP +25

JP + 9

S81T
1,[8]

R81T
1,[8]

LD 8,#06

IF8NE 9

JSR
x900-x9FF

JMP
x900-x9FF

JP +26

JP + 10

S81T
2,[8]

R81T
2,[8]

LD 8,#05

IF8NEOA

JSR
xAOO-xAFF

JMP
xAOO-xAFF

JP +27

JP + 11

S81T
3,[8]

R81T
3,[8]

LD 8,#04

IF8NE08

JSR
x800-x8FF

JMP
x800-x8FF

JP +28

JP + 12

S81T
4,[8]

RBIT
4,[8]

LD 8,#03

IF8NEOC

JMP
xCOO-xCFF

JP +29

JP + 13

S81T
5,[8]

R81T
5,[8]

LD 8,#02

IF8NEOD

JSR
xCOO-xCFF
--_._JSR
xDOO-xDFF

JMP
xDOO-xDFF

JP +30

JP + 14

S81T
6,[8]

R81T
6,[8]

LD 8,#01

IF8NEOE

JSR
xEOO-xEFF

JMP
xEOO-xEFF

JP +31

JP + 15

S81T
7,[8]

R81T
7,[8]

LD 8,#00

IF8NE OF

JSR
xFOO-xFFF

JMP
xFOO-xFFF

JP +32

JP + 16

IF8NE 5

.........

......
o
o

LD 8,#OC

LD 8,#OA

0l:Io

"T1

IF81T
3,[8]

o"C

0)
0)
0)

o
o

"T1
......

"C
JP + 6

0)
0)

0l:Io

"T1

Where,
i is the immediate data
Md is a directly addressed memory location
• is an unused opcode

Note: The opcode 60 Hex is also the opcode for IFBIT #i,A

1-231

u..

o
"'I:J'

co
co

D..

o
o

.......

u..
o
co
co
co
D..

o
.......
u..

o
"'I:J'

co
en

D..

o
.......
u..
o
co
co
en
D..

o
o

32k trace and break triggers which can be enabled, disabled, set or cleared. They can be simple triggers based on
code address, direct address, opcode value, opcode class
or immediate operand. Complex breakpoints can be ANDed
and ORed together. Trace information consists of address
bus values, opcodes and user selectable probe clips status
(external event lines). The trace buffer can be viewed as
raw hex or as disassembled instructions. The probe clip bit
values can be displayed in binary, hex or digital waveform
formats.
During single-step operation the dynamically annotated
code feature displays the contents of all accessed (read
and write) memory locations and registers, as well as flowof-control direction change markers next to each instruction
executed.

Mask Options
The mask programmable options are shown below. The options are programmed at the same time as the ROM pattern
submission.

OPTION 1: CLOCK CONFIGURATION
1
Crystal Oscillator (CKI/10)
G7 (CKO) is clock generator
output to crystal/resonator
CKI is the clock input
2
Single-pin RC controlled
oscillator (CKI/10)
G7 is available as a HALT
restart and/or general purpose
input

=
=

The iceMASTER's performance analyzer offers a resolution
of better than 6 !-'-S. The user can easily monitor the time
spent executing specific portions of code and find "hot
spots" or "dead code". Up to 15 independent memory areas based on code address or label ranges can be defined.
Analysis results can be viewed in bar graph format or as
actual frequency count.

OPTION 2: HALT
Enable HALT mode
=1
Disable HALT mode
=2
OPTION 3: BONDING
44-Pin PLCC
=1
40-Pin DIP
=2
N/A
=3
28-Pin DIP
=4
28-Pin SO
=5

Development Support

The iceMASTER connects easily to a PC® via the standard
COMM port and· its 115.2 kBaud serial link keeps typical
program download time to under 3 seconds.
The following tables list the emulator and probe cards ordering information.

. Emulator Ordering Information
Part Number

Description

IM-COP8/400/1:f:

MetaLink base unit in-circuit emulator for all COP8 devices, symbolic debugger
software and RS-232 serial interface cable, with 11 OV @ 60 Hz Power Supply.

IM-COP8/400/2:j:

MetaLink base unit in-circuit emulator for all COP8 devices, symbolic debugger
software and RS-232 serial interface cable, with 220V @ 50 Hz Power Supply.

DM-COP8/888CF:j:

MetaLink ice MASTER Debug Module. This is the low cost version of MetaLink's
iceMASTER. Firmware: Ver. 6.07.

:j: These parts include National's COPS Assembler/Linker/Librarian Package (COP8/0EV-I8MA).

1-232

Current Version

HOST SOFTWARE:
VER. 3.3 REV.5,
Model File Rev 3.050.

(")

a""C

Development Support (Continued)

Probe Card Ordering Information

co
co

Assembler Ordering Information

(")

Part Number
MHW-884CF28D5PC

Package

Voltage
Range

Emulates

28 DIP

4.5V-5.5V COP884CF

MHW-884CF28DWPC 28 DIP

2.5V-6.0V COP884CF

40 DIP

4.5V-5.5V COP888CF

MHW-888CF40DWPC 40DlP

MHW-888CF40D5PC

2.5V-6.0V COP888CF

MWH-888CF44D5PC

Part Number

Description

Manual

."
......

COP8·DEV·IBMA

COP8 Assemblerl
LinkerlLibrarian for
IBM®, PC/XT®,
AT® or compatible.

424410632-001

a""C

(")

."
......

SINGLE CHIP EMULATOR DEVICE

(")

The COP8 family is fully supported by One-Time Programmable (OTP) emulators. For more detailed information refer
to the emulation device specific datasheets and the emulator selection table below.

44 PLCC 4.5V-5.5V COP888CF

MHW-888CF44DWPC 44 PLCC 2.5V-6.0V COP888CF
MACRO CROSS ASSEMBLER

a""C
co
co
co

(")

......

PROGRAMMING SUPPORT

National Semiconductor offers a COP8 macro cross assembier. It runs on industry standard compatible PCs and supports all of the full-symbolic debugging features of the
MetaLink iceMASTER emulators.

(")

Programming of the single chip emulator devices is supported by different sources. The following programmers are certified for programming the One-Time Programmable (OTP)
devices.

a""C
co
co
~

(")

EPROM Programmer Information
Manufacturer
and Product

U.S. Phone
Number

Europe Phone
Number

Asia Phone
Number

MetaLink-Debug Module

(602) 926-0797

Germany: + 49-8141-1 030

Hong Kong: +852-737-1800

Zeltek-Superpro

(408) 745-7974

Germany: + 49-20-41 684758

Singapore: + 65 276 6433

BP Microsystems-EP-1140

(800) 225-2102

Germany: + 49-89 857 66 67

Hong Kong: + 852 388 0629

Data 1/0-Unisite;
-System 29,
-System 39

(800) 322-8246

Europe: +31-20-622866
Germany: + 49-89-85-8020

Japan: + 33-432-6991

Abcom-COP8
Programmer
System General
Turpro-1-FX; -APRO

Europe: + 89-80 8707
(408) 263-6667

TeiwO'm Te.ipe!: -+- 2-9173QQ5

Switzerland: +31-921-7844

OTP Emulator Ordering Information
Device Number

Clock Option

Package

Emulates

COP8788CFV-X
COP8788CFV-R*

Crystal

44 LDCC

COP888CF

COP8788CFN-X
COP8788CFN-R *

Crystal

40DlP

COP888CF

COP8784CFN-X
COP8784CFN-R*

Crystal

28DlP

COP884CF

COP8784CFWM-X·
COP8784CFWM-R*

Crystal

28S0

COP884CF

RIC
RIC
RIC
RIC

'Check with the local sales office about the availability.

1-233

(.)
"'1::1'
CX)
CX)

r-------------------------------------------------------------------------------~

Development Support (Continued)

Il.

DIAL-A-HELPER

ORDER PIN: MOLE-DIAL-A-HLP

......

Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Bulletin Board Information system.

Information System Package Contents:
Dial-A-Helper Users Manual
Public Domain Communications Software

o
(.)
~

(.)
CX)
CX)
CX)

Il.

o(.)

......
~

(.)
"'1::1'
CX)

0')

Il.

o(.)

......
~

(.)
CX)
CX)

0')

Il.

o(.)

INFORMATION SYSTEM

FACTORY APPLICATIONS SUPPORT

The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities could be found. The minimum requirement for accessing the Dial-A-Helper is a Hayes compatible
modem.

Dial-A-Helper also provides immediate factor applications
support. If a user has questions, he can leave messages on
our electronic bulletin board, which we will respond to.
Voice:

(800) 272-9959

Modem: Canadal
U.S.:

(800) NSC-MICRO
(800) 672-6427

If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.

Baud:

14.4k

Set-Up:

Length: 8-Bit
Parity:
None
Stop Bit: 1

Operation: 24 Hours, 7 Days

1-234

a"'C
0')

t#lNational Semiconductor

co
co

oen
........

COP688CS/COP684CS/COP888CS/COP884CS/
COP988CS/COP984CS Single-Chip
microCMOS Microcontroller
General Description
The COP888 family of micro controllers uses an 8-bit single
chip core architecture fabricated with National Semiconductor's M2CMOSTM process technology. The COP888CS is a
member of this expandable 8-bit core processor family of
microcontrollers.
(Continued)

Features
• Low cost 8-bit microcontroller
.. Fully static CMOS, with low current drain
• Two power saving modes: HALT and IDLE
a 1 JLs instruction cycle time
II 4096 bytes on-board ROM
.. 192 bytes on-board RAM
a Single supply operation: 2.5V-6V
• Full duplex UART
One analog comparator
• MICROWIRE/PLUSTM serial liD
a WATCHDOGTM and Clock Monitor logic
II Idle Timer
• Multi-Input Wakeup (MIWU) with optional interrupts (8)
II One 16-bit timer, with two 16-bit registers supporting:
- Processor Independent PWM mode
- External Event counter mode
- Input Capture mode
• 8-bit Stack Pointer SP (stack in RAM)
;; T'Vvo o-bii Rt:yi::;lt:r Im.iirect Data Memory t'ointers
(B and X)
II

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~

• Ten multi-source vectored interrupts servicing
- External Interrupt
- Idle Timer TO
-Timer (2)
- MICROWIRE/PLUS
- Multi-Input Wake Up
- Software Trap
-UART (2)
- Default VIS
a Versatile instruction set
II True bit manipulation
• Memory mapped liD
a BCD arithmetic instructions
a Package:
- 44 PLCC with 39 I/O pins
- 40 N with 35 I/O pins
- 28 SO or 28 N, each with 23 I/O pins
a Software selectable liD options
- TRI-STATE® Output
- Push-Pull Output
- Weak Pull Up Input
- High Impedance Input
a Schmitt trigger inputs on ports G and L
II One-Time Programmable (OTP) emulation devices
a Real time emulation and full program debug offered by
MetaLink's Development Systems

Block Diagram

.------~~~~~~~---------------!

TLIDD/10830-1

FIGURE 1. Block Diagram

1-235

o
en
........
o

a"'C
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co
co

........

a"'C
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~

o
en
........
o

a"'C
CD
(X)

o
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........
o

a"'C
CD

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~

o
en

C/)

o
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en

General Description

(Continued)

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It is a fully static part, fabricated using double-metal silicon
gate microCMOS technology. Features include an 8-bit
memory mapped architecture, MICROWIRE/PLUS serial
lID, one 16-bit timer/counter supporting three modes (Processor Independent PWM generation, External Event counter, and Input Capture mode capabilities), full duplex UART,
one comparator, and two power savings modes (HALT and

C/)

Connection Diagrams

......
C/)

oco

a.
o
o
......

o
oo:t'

co
co

Plastic Chip Carrier

o
......
C/)
o
co
co
co

a.
o
o
......

8 <1 0

Dual-In-Line Package

~ ~ 0

CKI

vee

RESET

10
12
13

37
10

44 pin
PLCC

a.
o
o
......

Voltage at Any Pin
Total Current into Vee Pin (Source)

DC Electrical Characteristics 98XCS: O°C ~ TA ~
Parameter

CJ)

o
oo:::t

co
co
DO

o......
CJ)

o
co
co
co
DO

o......
CJ)
ooo:::t
co

D-

o
......
CJ)

o
co
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CD

D-

7V
-0.3V to Vee + 0.3V
100mA

110 mA
Total Current out of GND Pin (Sink)
- 65°C to + 140°C
Storage Temperature Range
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrt~
cal specifications are not ensured when operating the device at absolute maximum ratings.
+ 70°C unless otherwise specified

Conditions

Power Supply Ripple (Note 1)

Peak-to-Peak

Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz
CKI = 4 MHz
CKI = 1 MHz

Vee
Vee
Vee
Vee

HALT Current (Note 3)
IDLE Current
CKI = 10 MHz
CKI = 4MHz
CKI = 1 MHz

Input Pullup Current

Vee = 6V, CKI = 0 MHz
Vee = 4V, CKI = 0 MHz

<0.7
<0.3

Vee = 6V, tc = 1 ,..,S
Vee = 6V, tc = 2.5,..,s
Vee = 4V, tc = 10,..,s

Sink
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage

Max

Units

4.0
6.0

V
V

0.1 Vee

12.5
5.5
2.5
1.4

mA
rnA
mA
mA

8
4

,..,A
,..,A

3.5
2.5
0.7

mA
mA
mA

0.2 Vee

V
V

0.2 Vee

V
V

0.2 Vee

V
V

0.8 Vee

0.7 Vee

0.7 Vee
Vee = 6V

-1

,..,A

Vee = 6V, VIN = OV

-40

-250

,..,A

0.35 Vee

G and L Port Input Hysteresis
Output Current Levels
o Outputs
Source

Typ

= 6V, tc = 1 ,..,S
= 6V, tc = 2.5,..,s
== 4V, tc = 2.5,..,s
= 4V,tc = 10,..,s

Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage

Min
2.5
4.0

Operating Voltage COP98XCS
COP98XCSH

4V, VOH = 3.3V
= 2.5V, VOH = 1.8V
= 4V, VOL = 1V
= 2.5V, VOL = O.4V

-0.4
-0.2
10
2.0

4V, VOH = 2.7V
2.5V, VOH = .1.8V
4V, VOH = 3.3V
2.5V, VOH = 1.8V
4V, VOL = OAV
2.5V, VOL = O.4V

-10
-2.5
-0.4
-0.2
1.6
0.7

-100.
-33

,..,A
,..,A
mA
mA
mA
mA

-1

,..,A

Vee
Vee
Vee
Vee

Vee
Vee
. Vee
Vee
Vee
Vee

=
=
=
=
=

Vee = 6.0V

mA
mA
mA
mA

Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured aiter running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vce, L, C and GO-G5 configured
as outputs and set high. The D port set to zero. The clock monitor and the comparators are disabled.
Note 1:

DC Electrical Characteristics
Parameter

98XCS: O°C

Conditions

s: + 70·C unless otherwise specified (Continued)
Min

Typ

""C

Units

Max

en
(X)
(X)

o
o

en
........

Allowable Sink/Source
Current per Pin
o Outputs (Sink)
All others

15
3

mA
mA

±100

TA = 25°C

RAM Retention Voltage, Vr

500 ns Rise
and Fall Time (Min)

Load Capacitance on 02

1000

Min

4V s: Vee s: 6V
2.5V s: Vee < 4V
4V s: Vee s: 6V
2.5V s: Vee < 4V

1
2.5
3
7.5

4V s: Vee s: 6V
2.5V s: Vee < 4V
4V s: Vee s: 6V
2.5V s: Vee < 4V

200
500
60
150

Typ

tHOLD
Output Propagation Delay (Note 6)
tpD1, tPDO
SO,SK
All Others

o
en
........
o
(X)
(X)

Max

DC
DC
DC
DC

Units

,..,s
,..,s
,..,s
,..,s

en
........

o
o

""C
<0

(X)
(X)

Inputs
tSETUP

(X)
(X)
(X)

o""C

AC Electrical Characteristics 98XCS: O°C s: TA s: + 70°C unless otherwise specified
Conditions

oen
........
o

o""C

Input Capacitance

Instruction Cycle Time (te)
Crystal, Resonator,
R/C Oscillator

(X)
~

Maximum Input Current
without Latchup (Note 5)

Parameter

o""C

ns
ns
ns
ns

""C
<0

(X)
~

4V s: Vee s: 6V
2.5V s: Vee < 4V
4V s: Vee s: 6V
2.5V s: Vee < 4V

0.7
1.75
1
2.5
20
56
220

,..,s
,..,s
,..,s
IL!'>

ns
ns
ns

Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

1
1
1
1

te
te
te
te

Reset Pulse Width

,..,s

Note 5: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than Vee and the pins will
have sink current to Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vee>. The effective
resistance to Vee is 7500 (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Notye 6: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

1-239

o
o

RL = 2.2k, CL = 100 pF

MICROWIRETM Setup Time (tuWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tUPD)

en
........

CJ)

(.)
~

co
en

o(.)

.......

CJ)

(.)

co
co
en

Absolute Maximum Ratings
Total Current out of GND Pin (Sink)
110 mA
- 65°C to + 140°C
Storage Temperature Range
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (Vee>
Voltage at Any Pin
Total Current into Vee Pin (Source)

7V
-0.3V to Vee + 0.3V
100mA

(.)

.......

CJ)

DC Electrical Characteristics BBXCS: -40°C ~ TA ~

+B5°Cunlessotherwisespecified

(.)

Parameter

co
co

o
(.)

.......

CJ)

(.)

co
co
co

o
(.)

.......
CJ)

(.)
~

co
CD

o(.)

.......

CJ)
(.)

co
co
CD

o(.)

Conditions

Operating Voltage

Min

Typ

2.5

Power Supply Ripple (Note 1)

Peak-to-Peak

Supply Current (Note 2)
CKI = 10 MHz
CKI = 4MHz

Vee = 6V, tc = 1 p.s
Vee = 6V, tc = 2.5 p.s

HALT Current (Note 3)

Vee = 6V, CKI = 0 MHz

IDLE Current
CKI = 10 MHz
CKI = 4 MHz

Vee = 6V, tc = 1 p.s
Vee = 6V, tc = 2.5 p's

Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low

Max

Units

0.1 Vee

12.5
5.5

mA
mA

p.A

3.5
2.5

mA
mA

0.2 Vee

V
V

0.2 Vee

V
V

0.2 Vee

V
V

O.BVee

0.7 Vee

Hi-Z Input Leakage

Vee = 6V

-2

p.A

Input Pullup Current

Vee = 6V, VIN ~ OV

-40

-250

p.A

0.35 Vee

G and L Port Input Hysteresis
Output Current Levels
D Outputs
Source
Sink
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)

Vee
Vee
Vee
Vee

=
=
=
=

4V, VOH = 3.3V
2.5V, VOH = 1.BV
4V, VOL = 1V
2.5V, VOL = O.4V

-0.4
-0.2
10
2.0

Vee
Vee
Vee
Vee
Vee
Vee

=
=
=
=
=
=

4V, VOH = 2.7V
2.5V, VOH = 1.BV
4V, VOH = 3.3V
2.5V, VOH = 1.BV
4V, VOL = 0.4V
2.5V, VOL = O.4V

-10
-2.5
-0.4
. -0.2
1.6
0.7
-2

TRI-STATE Leakage

mA
mA
mA
mA
-100
-33

p.A
p.A
mA
mA
mA
mA

p.A

Note 2:

1-240

DC Electrical Characteristics 88XCS:
Parameter

-40·C s; TA s;

Min

Conditions

o
o

+ 85·C unless otherwise specified (Continued)
Typ.

Allowable Sink/Source
Current per Pin
o Outputs (Sink)
All others

"tJ

Max

Units

mA
mA

±100

RAM Retention Voltage, Vr

500 ns Rise
and Fall Time (Min)

Parameter

Conditions

Min

4V S; Vee S; 6V
2.5V S; Vee < 4V
4V::;: Vee s; 6V
2.5V ::;: Vee < 4V

1
2.5

(X)
(X)
(X)

1000

"tJ

4V::;: Vee::;: 6V
2.5V ::;: Vee < 4V
4V::;: Vee::;: 6V
2.5V ::;: Vee < 4V

200
500
60
150

3
7.5

Typ

All Others
..-.-

--_.

= 2.2k, CL =

(X)
(X)

Max

Units

DC
DC
DC
DC

J.Ls
J.Ls
J.Ls
J.Ls
ns
ns
ns
ns

oen

.......

"tJ
CO

(X)
(X)

o
en
.......
o

"tJ
CO

(X)
~

o
en

100 pF
0.7
1.75
1
2.5

4V::;: Vee::;: 6V
2.5V ::;: Vee < 4V
4V::;: Vee::;: 6V
2.5V ::;: Vee < 4V
20
56

MICROWIRE Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tUPD)

o
o

en
.......
"tJ

Inputs

en
.......
o

AC Electrical Characteristics 88XCS: -40·C s; TA s; + 85·C unless otherwise specified

Output Propagation Delay (Note 6)
tPD1, tpDD
SO,SK

Q)
(X)

Load Capacitance on 02

tHOLD

o"tJ

Input Capacitance

tSETUP

o
en
.......
o
~

= 25·C

Maximum Input Current
without Latchup (Note 5)

Instruction Cycle Time (td
Crystal, Resonator,
RIC Oscillator

Q)
(X)
(X)

220

J.Ls
J.Ls
J.Ls
It!;

ns
ns
ns

Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

1
1
1
1

tc
tc
tc
tc

Reset Pulse Width

J.LS

Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than Vee and the pins will
have sink current to Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vee>. The effective
resistance to Vec is 750n (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 6: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 5:

1-241

(J)

o
"II:J'

......
(J)

oco

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
7V
Voltage at Any Pin
-0.3V to Vee + 0.3V
100mA
Total Current into Vee Pin (Source)

Total Current out of GNO Pin (Sink)
110mA
Storage Temperature Range
- 65°C to + 140°C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

o
......
(J)

o
"II:J'

co
co
D.

DC Electrical Characteristics 68XCS: Parameter

55°C ~ TA ~ + 125°C unless otherwise specified

Conditions

Operating Voltage
Peak-to-Peak

co
co

Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz

Vee = 5.5V, tc = 1 fJ-s
Vee = 5.5V, tc = 2.5fJ-s

HALT Current (Note 3)

Vee = 5.5V, CKI = 0 MHz

IDLE Current
CKI = 10 MHz
CKI = 4 MHz

Vee = 5.5V, tc = 1 fJ-s
Vee = 5.5V, tc = 2.5 fJ-s

......

oco

o
......
(J)

o
"II:J'

co
CD

o
......
(J)

o
co
co
CD

o
o

Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current

Max

Units

5.5

0.1 Vee

12.5
5.5

mA
mA

fJ-A

3.5
2.5

mA
mA

0.2 Vee

V
V

0.2 Vee

V
V

0.2 Vee

V
V

-5

fJ-A

-35

-400

fJ-A

0.35 Vee

<10

0.8 Vee

0.7 Vee

0.7 Vee
Vee = 5.5V, VIN
Vee = 5.5V, VIN

= OV
= OV

G and L Port Input Hysteresis
Output Current Levels
o Outputs
Source
Sink
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage

Typ

4.5

Power Supply Ripple (Note 1)

(J)

Min

Vee = 4.5V, VOH = 3.8V
Vee = 4.5V, VOL = 1V
Vee = 4.5V, VOH = 3.2V
Vee = 4.5V, VOH = 3.8V
Vee = 4.5V, VOL = O.4V

-0.4

-9

140

fJ-A
mA
mA

fJ-A

-0.4
1.4
-5

Vee = 5.5V

mA
mA

Rate of voltage change must be less then O.S V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee. L, C and GO-GS configured
as outputs and set high. The 0 port set to zero. The clock monitor and the comparators are disabled.
Note 1:

1-242

DC Electrical Characteristics
Parameter

o
o

68XCS: - Ssoc :;: TA :;: + 125°C unless otherwise specified (Continued)

Conditions

Min

Typ

Max

"'C

0')

Units

en
en

en
.......

Allowable Sink/Source
Current per Pin
o Outputs (Sink)
All others

12
2.5

mA
mA

±100

'1J
0')

Maximum Input Current
without Latchup (Note S)

TA = 2SoC

RAM Retention Voltage, Vr

500 ns Rise
and Fall Time (Min)

input Capacitance
Load Capacitance on 02

o
en
.......
o
"'C

1000

en
en
en

en
.......

AC Electrical Characteristics 68XCS: -Ssoc:;: TA:;:
Parameter

Instruction Cycle Time (tel
Crystal, Resonator,
R/C Oscillator

"'C

+125°C uniessotherwise specified

Conditions

4.5V :;: Vee:;: 5.5V
4.5V :;: Vee:;: 5.SV

Min

1
3

Typ

en
en

Max

DC
DC

Units

JLs
JLs

en
.......

o"'C
(0

Inputs
tSETuP
tHOLD
Output Propagation Delay (Note 6)
tpD1, tpDD
SO,SK
All Others

4.SV :;: Vee:;: S.SV
4.5V :;: Vee:;: 5.5V

200
60

ns
ns

en
en

en
.......

o"'C

RL = 2.2k, CL = 100 pF

4.5V :;: Vee ~ 5.5V
4.5V :;: Vee:;: 5.5V

0.7
1

JLs
JLs

220

ns
ns
ns

20
56

MICROWIRE Setup Time (tUWS)
MICROWiRE Hold Time (tUWH)
MiCROWIRE Output Propagation Delay (tUPD)
Input Pulse Width
interrupt input High I ime
interrupt input Low Time
Timer Input High Time
Timer input Low Time

1
1
1
1

tc
tc
tc
tc

Reset Pulse Width

JLs

Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than Vee and the pins will
have sink current to Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vee>. The effective
resistance to Vee is 7500 (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 6: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 5:

1-243

en
o'1::1'
co
0')

Comparator AC and DC Characteristics Vee =
Parameter

Conditions

5V, T A

Min

25°C
Typ

Max

Units

±25

oo
'"
en

Input Offset Voltage

co
0')

Low Level Output Current

VOL

OAV

1.6

High Level Output Current

VOH

4.6V

1.6

oco

en
'"
o'1::1'
co
co

0.4V ~ VIN ~ Vee - 1.5V

Input Common Mode Voltage Range

±10

004

Vee - 1.5

DC Supply Current
(When Enabled)
Response Time

250
TBD mV Step, TBD mV
Overdrive, 100 pF Load

o
o

en
o'"
co

co
co

'"
en

~
tUWH

o
o

o
'1::1'

~tUPD

CD
Q.

o
o

'"
en

FIGURE 3. MICROWIRE/PLUS Timing

o
co
co

CD
Q.

o
o

1-244

TL/DD/l0630-6

JJ-A
JJ-s

o
Typical Performance Characteristics

(-40°C to + 85°C)

"'C

m
Idle-IOO (Crystal Clock Option)

Halt-Ioo
3.5

2
1.8
/

""
-3

-r
CI

+85 C "

1.2

:x:

0.6

0.4
0.2
2

" r--:o40 o C

....
-'

1.5

V,.. 1-'"'. '
'" 4 MHz
:t
.
10MHz , ..

3.5

4.5

5.5

~IN -

, "
4 MHz ~,..

"<
-3

"''''
~" V

"-"-

3.5

4.5

5.5

~IN

•

. : ...

TLlDD/10830-25

..s"<

=4.5V ~ \

,,'

.,,-

o 1/
0.5

I I
I

=2.5V

Vee

=6.0V

..s

I I

2
TLlDD/10830-29

10
'/

\
\

3
VOH (V)

, ,

I I

0.5

, ,..

...

1·245

Vee = 4.5V

1 1.5

Vee = 2.5V

2 2.5 3 3.5 4 4.5
VOL (V)

TL/DD/10830-30

.. ~ .
Vee = 6.0V
II

15
\

\
\

=4.5V",

-'I"
r-:::: -~2.51
o

~ee

Port D Sink Current

............... ,

...

Vee =4.5V

=6.0V

VOL (V)

Port D Source Current

o"'C

. . ~-t .

1.5

TLlDD/10830-28

.\
TLlDD/l0830-27

,.' I
Vee
I

" , ,;

',vee

~"1"·

en
........

r-~

,'I

25
20

Q)
Q)

VOH (V)

"'C

'. '.

o
o

I ••~~~,
~2.51

,/'
\

en
........

Q)
Q)

'.
' '. "

I' ..
f-::: r-.....vee =2.5V

o
o
o

Vee

"'C

v~e,=,rv" ,'.

O.riY -

:I:

Port L/C/G/ Push-Pull Sink Current

VOH (v)

'Vee~

5.5

........

......

..9

TLlDD/10830-26

o
o

~AX

Port L/C/G Push·Puli Source Current

.....

4.5

o
o

Vee (V)

Vee = 6.0V

20 ~
~IN ..

1 MHz

3.5

... .....
- ...... ~ ..

100

............ .%
,........

..s

"'C
Q)
Q)
Q)

~AX-

.... f-" V

120

o
o

Port L/C/G Weak Pull-Up
Source Current

10 MHz

2.5

TL/DD/10830-24

en
........

Vee (V)

Dynamlc-Ioo (Crystal Clock Option)

2.5

;::.pr
o~

~'
/

0.5

Vee (V)

"'C

2.5

1 MHzj

CI
_0

",';'

vV"

0.8

2.5

..s

I-

1.4

1.6

Q)
Q)

o
en
........
o

TL/DD/10830-31

co
en

D..

o
o

.......

o
co
co
en
D..

o
.......

co
co
D..

o
.......

o
co
co
co
D..

.......

Pin Descriptions
Vee and GND are the power supply pins.

MIWU

CKI is the clock input. This can come from an R/C generated oscillator, or a crystal oscillator (in conjunction with
CKO). See Oscillator Description section.

MIWU

RESET is the master reset input. See Reset Description
section.

Port G is an 8-bit port with 5 I/O pins (GO, G2-G5), an input
pin (G6), and two dedicated output pins (G1 and G7). Pins
GO and G2-G6 all have Schmitt Triggers on their inputs. Pin
G1 serves as the dedicated WDOUT WATCHDOG output,
while pin G7 is either input or output depending on the oscillator mask option selected. With the crystal oscillator option
selected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin but is
also used to bring the device out of HALT mode with a low
to high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (GO, G2-G5) can be individually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose
input (R/C clock option), the associated bits in the data and
configuration registers for G6 and G7 are used for special
purpose functions as outlined below. Reading the G6 and
G7 data bits will return zeros.
Note that the chip will be placed in the HALT mode by writing a "1" to bit 7 of the Port G Data Register. Similarly the
chip will be placed in the IDLE mode by writing a "1" to bit 6
of the Port G Data Register.

The device contains three bidirectional 8-bit I/O ports (C, G
and L), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L and G),
output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these II
o ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also
reserved for the input pins of each 1/0 port. (See the memory map for the various addresses associated with the I/O
ports.) Figure 4 shows the I/O port configurations. The
DATA and CONFIGURATION registers allow for each port
bit to be individually configured under software control as
shown below:

CONFIGURATION
Register

DATA
Register

D..

0
1
1

1
0
1

o
.......

oco
co
CD

Port Set-Up
Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output

D..

PORT L, C, AND G

Config Reg.

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

Port G has the following alternate features:

TL/DD/10830-7

FIGURE 4. 1/0 Port Configurations

The Port L supports Multi-Input Wake Up on all eight pins.
L 1 is used for the UART external clock. L2 and L3 are used
for the UART transmit and receive.

MIWU or CKX

MIWU or TDX

MIWU or RDX

T1A (Timer T1 I/O)

SO (MICROWIRE Serial Data Output)

SK (MICROWIRE Serial Clock)

SI (MICROWIRE Serial Data Input)

WDOUT WATCHDOG and/or Clock Monitor dedicated output

CKO Oscillator dedicated output or general purpose input

The Port L has the following alternate features:
MIWU

INTR (External Interrupt Input)
T1 B (Timer T1 Capture Input)

Port G has the following dedicated functions:

Port L is an 8·bit 1/0 port. All L-pins have Schmitt triggers on
the inputs.

GO
G2

Port I is an eight-bit Hi-Z input port. The 28-pin device does
not have a full complement of Port I pins. The unavailable

1-246

and Pin), the control registers, the MICROWIRE/PLUS SID
shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer).
Data memory is addressed directly by the instruction or indirectly by the 8, X, SP pointers and S register.

Pin Descriptions (Continued)
pins are not terminated i.e., they are floating. A read operation for these unterminated pins will return unpredictable
values. The user must ensure that the software takes this
into account by either masking or restricting the accesses to
bit operations. The unterminated Port I pins will draw power
only when addressed.

The device has 192 bytes of RAM. Sixteen bytes of RAM
are mapped as "registers" at addresses OFO to OFF Hex.
These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and
skip if zero) instruction. The memory pointer registers X, SP,
8 and S are memory mapped into this space at address
locations OFC to OFF Hex respectively, with the other registers being available for general usage.

Ports 11-13 are used for Comparator 1.
Ports 11-13 have the following alternate features.
11

COMP1 -IN (Comparator 1 Negative Input)

COMP1

COMP10UT (Comparator 1 Output)

+ IN (Comparator 1 Positive Input)

The instruction set permits any bit in memory to be set,
reset or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.

Port 0 is an 8-bit output port that is preset high when
RESET goes low. The user can tie two or more 0 port outputs (except 02) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the
external loads on this pin must ensure that the output voltages stay
above O.B Vee to prevent the chip from entering special modes. Also
keep the external loading on D2 to less than 1000 pF.

Functional Description
The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store memory (RAM). 80th ROM and RAM have their own separate
addressing space with separate address buses. The architecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or
shift operation in one instruction (td cycle time.
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lowAr A hits of the program c0'..!nter (PC)
8 is an S-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an S-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the S-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.
S is the 8-bit Data Segment Address Register used to extend the lower half of the address range (00 to 7F) into 256
data segments of 128 bytes each.

PROGRAM MEMORY

Program memory consists of 4096 bytes of ROM. These
bytes may hold program instructions or constant data (data
tables for the LAID instruction, jump vectors for the JID instruction, and interrupt vectors for the VIS instruction). The
program memory is addressed by the 15-bit program counter (PC). All interrupts vector to program memory location
OFF Hex.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data

1-247

0)
Q)
Q)

o
en
.........
o

o"0
0)
Q)
~

o
en
.........
o

o"0
Q)
Q)
Q)

o
en
o

.........

Note: RAM contents are undefined upon power-up.

Data Memory Segment
RAM Extension

o
en
.........

Data memory address OFF is used as a memory mapped
location for the Data Segment Address Register (S).

o"0

The data store memory is either addressed directly by a
single byte address within the instruction, or indirectly relative to the reference of the 8, X, or SP pointers (each contains a single-byte address). This single-byte address allows
an addressing range of 256 locations from 00 to FF hex.
The upper bit of this single-byte address divides the data
store memory into two separate sections as outlined previously. With the exception of the RAM register memory from
address locations OOFO to OOFF, all RAM memory is memory mapped with the upper bit of the single-byte address being equal to zero. This allows the upper bit of the single-byte
address to determine whether or not the base address
range (from 0000 to OOFF) is extended. If this upper bit
eq'...!~!s cr.~ (rcprc:cr.t:r.g :..ddrc:;:; ruiigG ceca to COFF).
then address extension does not take place. Alternatively, if
this upper bit equals zero, then the data segment extension
register S is used to extend the base address range (from
0000 to 007F) from XXOO to XX7F, where XX represents the
8 bits from the S register. Thus the 128-byte data segment
extensions are located from addresses 0100 to 017F for
data segment 1, 0200 to 027F for data segment 2, etc., up
to FFOO to FF7F for data segment 255. The base address
range from 0000 to 007F represents data segment O.

Q)
Q)

Figure 5 illustrates how the S register data memory extension is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XXOO
to XX7F. This organization allows a total of 256 data segments of 128 bytes each with an additional upper base segment of 128 bytes. Furthermore, all addressing modes are
available for all data segments. The S register must be
changed under program control to move from one data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory registers, I/O registers,
control registers, etc.) is always available regardless of the

All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).

Q)
Q)
~

.........

o
o

Q)
~

o
en

o
v

r-----------------------------------------------------------------------~

WKEDG and WKPND are cleared. The stack pointer, SP, is
initialized to 6F Hex.

co
D.

Data Memory Segment
RAM' Extension (Continued)

o
......

contents of the S register, since the upper base segment
(address range 0080 to OOFF) is independent of data segment extension.

o
o

oco

o
......
o

co
co
D.

o......
o

o
co
co
co

D-

o
......
o
o
v
co
CD
D.

o
o
......
o

oco

The instructions that utilize the stack pOinter (SP) always
reference the stack as part of the base segment (Segment
0), regardless of the contents of the S register. The S register is not changed by these instructions. Consequently, the
stack (used with subroutine linkage and interrupts) is always
located in the base segment. The stack pointer will be intitialized to point at data memory location 006F as a result of
reset.
The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
112 bytes of RAM are resident from address 0000 to 006F
in the lower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at addresses OOFO to OOFF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.

The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k tc clock cycles. The Clock Monitor bit
being initialized high will cause a Clock Monitor error following reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 tc-32 tc clock cycles following
the clock frequency reaching the minimum specified value,
at which time the G1 output will enter the TRI-STATE mode.
The external RC network shown in Figure 6 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.
p
0

XXFO
XXEF

S
E
G
II

UNUSED •

ON CHIP RAil

E
N
T

(112 BYTES)

-.L

S
E
G
II
E
N
T

I-

GND
TL/DD/l0830-9

> 5 x Power Supply Rise Time
FIGURE 6. Recommended Reset Circuit

Figure 7 shows the Crystal and RIC diagrams.

017F

CRYSTAL OSCILLATOR
UNUSED •

013F
ON CHIP RAil
(64 BYTES)

0000

p
P
L

UNUSED
(READS UNDEFINED
DATA) ,
XX80
007F
0070
006F

S
U

RESET

Oscillator Circuits

TlIIERS,I/O,IIW,
CNTRL, PSW, A/D,
ICNTRL, WD, IIIWU,
COIIPARATOR
AND UART
REGISTERS

XXBO
XXAF

COP888CS

RAil REGISTERS
(16 BYTES)
INClUDES B, X, SP, S

vee

Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XXOO to XX7F) of
the lower base segment. The additional 64 bytes of RAM
(beyond the initial 128 bytes) are memory mapped at address locations 0100 to 013F hex .

xxrr

0100

TL/DD/l0830-8

"Reads as all ones:

FIGURE 5. RAM Organization

Reset

CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.
Table A shows the component values required for various
standard crystal values.

RIC OSCILLATOR
By selecting CKI as a single pin oscillator input, a single pin
RIC oscillator circuit can be connected to it. CKO is available as a general purpose input, andl or HALT restart input.
Table B shows the variation in the oscillator frequencies as
functions of the component (R and C) values.

The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports l, G and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pinG1 is
dedicated as the WATCHDOG and/or Clock Monitor error
output pin. Port D is set high. The PC, PSW, ICNTRl,
CNTRl, are cleared. The UART registers PSR, ENU (except
that TBMT bit is set), ENUR and ENUI are cleared. The
Comparator Select Register is cleared. The S register is initialized to zero. The Multi-Input Wakeup registers WKEN,

Vee

TL/DD/l0830-11

TL/DD/l0830-10

FIGURE 7. Crystal and RIC Oscillator Diagrams

1-248

o
Oscillator Circuits (Continued)
R1
(k!1)

R2
(M!1)

C1
(pF)

C2
(pF)

CKI Freq
(MHz)

Conditions

0
0
0

1
1
1

30
30
200

30-36
30-36
100-150

10
4
0.455

Vee = 5V
Vee = 5.0V
Vee = 2.5V

The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
SL1 & SLO Select the MICROWIRE/PLUS clock divide
by (00 = 2,01 = 4, 1x = 8)
IEDG

TABLE B. RC Oscillator Configuration, T A = 25°C
R
(k!1)

C
(pF)

CKI Freq
(MHz)

Instr. Cycle
(J.Ls)

Conditions

3.3
5.6
6.8

82
100
100

2.2 to 2.7
1.1 to 1.3
0.9t01.1

3.7 to 4.6
7.4 to 9.0
8.8 to 10.8

Vee = 5V
Vee = 5V
Vee = 5V

0)
Q)
Q)

CNTRL Register (Address X'OOEE)

TABLE A. Crystal Oscillator Configuration, T A = 25°C

External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)

MSEL

Selects G5 and G4 as MICROWIRE/PLUS
Signals SK and SO respectively

T1CO

Timer T1 StartlStop control in timer
modes 1 and 2

T1C1

Timer T1 mode control bit

T1 C2

Timer T1 mode control bit

T1 C3

Timer T1 mode control bit

o
o

en
.......

o"0
0)
Q)
~

Timer T1 Underflow Interrupt Pending Flag in
timer mode 3
\

Note: 3k ,,;; R ,,;; 200k
50 pF ,,;;

Control Registers

o
o

en
.......

o"0
Q)
Q)
Q)

en
.......

o
o

Q)
Q)
~

e , ; 200 pF

I T1C31 T1C21 T1C1 I T1CO I MSEL IIEDG I SL1

Current Drain

Bit7

SLO
BitO

The total current drain of the chip depends on:

PSW Register (Address X'OOEF)

1. Oscillator operation mode-11
2. Internal switching current-12

The PSW register contains the following select bits:
GIE
Global interrupt enable (enables interrupts)

3. Internal leakage current-13

EXEN

Enable external interrupt

4. Output source current-14

BUSY

MICROWIRE/PLUS busy shifting flag

5. DC current caused by external input
not at Vee or GND-15
6. Comparator DC supply current when enabled-16

EXPND

External interrupt pending

T1 ENA

Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
T1 PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1 A capture edge in mode 3)

7. Clock Monitor current when enabled-17
Thus the total current drain, It, is given as
It = 11 + 12 + 13 + 14 + 15 + 16 + 17
To reduce the total current drain, each of the above components must be minimum.
The chip will draw more current as the CKI input frequency
increases up to the maximum 10 MHz value. Operating with
a crystal network will draw more current than an external
square-wave. Switching current, governed by the equation
below, can be reduced by lowering voltage and frequency.
Leakage current can be reduced by lowering voltage and
temperature. The other two items can be reduced by carefully designing the end-user's system.
12 = C

Carry Flag

Half Carry Flaq

en
.......

o"0
<0

Q)
Q)

en
.......

o"0
<0

Q)
~

I HC I C I T1 PNDA I T1 ENA I EXPND I BUSY I EXEN I GIE I
Bit7
BitO
The Half-Carry bit is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and RC instructions, ADC,
SUBC, RRC and RLC instructions affect the carry and Half
Carry flags.

xVxf

where C = equivalent capacitance of the chip
V = operating voltage
f = CKI frequency

1-249

o
-.::r

D..

.......

en
oco
co

D..

ICNTRL Register (Address X'OOE8)

interrupt from the thirteenth bit of Timer TO to be enabled or
disabled. Setting TOEN will enable the interrupt, while resetting it will disable the interrupt.

The ICNTRL register contains the following bits:

TIMERT1

Control Registers (Continued)

T1 ENB

Timer T1 Interrupt Enable for T1 B Input capture
edge
T1 PNDB Timer T1 Interrupt Pending Flag for T1 B capture edge
jJ.WEN

jJ.WPND MICROWIRE/PLUS interrupt pending

o
-.::r

TOEN

Timer TO Interrupt Enable (Bit 12 toggle)

TOPND

Timer TO Interrupt pending

D..

LPEN

L Port Interrupt Enable (Multi-Input Wakeup/Interrupt)
,

co
co

.......

The timer block consists of a 16-bit timer, T1, and two supporting 16-bit auto reload/ capture registers, R1A and R 1B. It
has two pins associated with it, T1A and T1B. The pin T1A
supports I/O required by the timer block, while the pin T1 B
is an input to the timer block. The powerful and flexible timer
block allows the device to easily perform all timer functions
with minimal software overhead. The timer block has three
operating modes: Processor Independent PWM mode, External Event Counter mode, and Input Capture mode.
The control bits T1 C3, T1 C2, and T1 C1 allow selection of
the different modes of operation .

Enable MICROWIRE/PLUS interrupt

.......

The device has a powerful timer/counter block.

Bit 7 could be used as a flag

o
co
co
co
D..

.......

en
o-.::r

10kHz-No clock rejection.

1/tc

< 10Hz-Guaranteed clock rejection.

WATCHDOG AND CLOCK MONITOR SUMMARY

The following salient points regarding the device WATCHDOG and CLOCK MONITOR should be noted:
• Both the WATCHDOG and Clock Monitor detector circuits are inhibited during RESET.

a""C
en
Q)
Q)

en
.......

a""C
en

Q)
~

o
en
.......
o

a""C
Q)
Q)
Q)

o
en
.......
o

a""C
Q)
Q)
~

en
.......

a""C
(0
Q)
Q)

en
.......

a""C
(0
Q)
~

• Following RESET, the WATCHDOG and CLOCK MONITOR are both enabled, with the WATCHDOG having the
maximum service window selected.

WATCHDOG Operation
The WATCHDOG and Clock Monitor are disabled during
reset. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG WindowSelect bits (bits 6, 7 of the
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
WDSVR Register) enabled. Thus, a Clock Monitor error will
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, including the case where the oscillator fails to start.

• The WATCHDOG service window and Clock Monitor
enablel disable option can only be changed once, during
i.:',t; iniLiCiI 'v'JATCi-iDGG ~~Ivi<':t;j fuiiuwillY ncScT.
• The initial WATCHDOG service must match the key data
value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error.
• Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG errors.

The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the WATCHDOG service window and match the WATCHDOG key data. Subsequent writes to the WDSVR register
will compare the value being written by the user to the
WATCHDOG service window value and the key data (bits 7
through 1) in the WDSVR Register_ Table V shows the sequence of events that can occur.

• The correct key data value cannot be read from the
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all O's.
• The WATCHDOG detector circuit is inhibited during both
the HALT and IDLE modes.
• The Clock Monitor detector circuit is active during both
the HALT and IDLE modes. Consequently, the device
inadvertently entering the HALT mode wil be detected as
a Clock Monitor error (provided that the Clock Monitor
enable option has been selected by the program).

The user must service the WATCHDOG at least once before the upper limit of the service window expires. The
WATCHDOG may not be serviced more than once in every
lower limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period
between the lower and upper limits of the service window.
The first write to the WDSVR Register is also counted as a
WATCHDOG service.

1-263

C/)

o
~

WATCHDOG Operation

a..

o
o

C/)
'"

o
co
co
Q)

a..

•
•

'"
o
C/)
~

co
co

•

a..
oo

C/)
'"

oco
co
co

a..
o

C/)
'"

o
~

a..

o
o

C/)

o
co
co

a..
o
o

•

Thus, the chip can detect the following illegal conditions:
a. Executing from undefined ROM

(Continued)

be set to its selected value from WDSVR following HALT.
Consequently, the WATCHDOG should not be serviced
for at least 2048 instruction cycles following HALT, but
must be serviced within the selected window to avoid a
WATCHDOG error.
The IDLE timer TO is not initialized with RESET.
The user can sync in to the IDLE counter cycle with an
IDLE counter (TO) interrupt or by monitoring the TOPND
flag. The TOPND flag is set whenever the thirteenth bit of
the IDLE counter toggles (every 4096 instruction cycles).
The user is responsible for resetting the TOPND flag.
A hardware WATCHDOG service occurs just as the device exits the IDLE mode. Consequently, the WATCHDOG should not be serviced for at least 2048 instruction
cycles following IDLE, but must be serviced within the
selected window to avoid a WATCHDOG error.
Following RESET, the initial WATCHDOG service (where
the service window and the CLOCK MONITOR enable/disable must be selected) may be programmed anywhere within the maximum service window (65,536 instruction cycles) initialized by RESET. Note that this initial WATCHDOG service may be programmed within the
initial 2048 instruction cycles without causing a WATCHDOG error.

b. Over "POP"ing the stack by having more returns than
calls.
When the software interrupt occurs, the user can re-initialize
the stack pointer and doa recovery procedure before restarting (this recovery program is probably similar to that
following reset, but might not contain the same program
initialization procedures). The recovery program should reset the software interrupt pending bit using the RPND instruction.

MICROWIRE/PLUS
MICROWIRE/PLUS is a serial synchronous communications interface. The MICROWIRE/PLUS capability enables
the device to interface with any of National Semiconductor's
MICROWIRE peripherals (Le. A/D converters, display drivers, E2PROMs etc.) and with other microcontrollers which
support the MICROWIRE interface. It consists of an 8-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK). Figure 17
shows a block diagram of the MICROWIRE/PLUS logic.

t------+INTERRUPT
~~--~------.SO

Detection of Illegal Conditions
The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.
Reading of undefined ROM gets zeros. The opcode for software interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt,
thus signaling that an illegal condition has occurred.
The subroutine stack grows down for each call Oump to
subroutine), interrupt, or PUSH, and grows up for each return or POP. The stack pointer is initialized to RAM location
06F Hex during reset. Consequently, if there are more returns than calls, the stack pointer will point to addresses
070 and 071 Hex (which are undefined RAM). Undefined
RAM from addresses 070 to 07F (Segment 0), 140 to 17F
(Segment 1), and all other segments (Le., Segments 3 ...
etc.) is read as all 1's, which in turn will cause the program
to return to address 7FFF Hex. This is an undefined ROM
location and the instruction fetched (all O's) from this location will generate a software interrupt signaling an illegal
condition.

I+------SI

Tl/DD/l0830-21

FIGURE 17. MICROWIRE/PlUS Block Diagram
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIRE/
PLUS arrangement with the internal clock source is called
the Master mode of operation. Similarly, operating the
MICROWIRE/PlUS arrangement with an external shift
clock is called the Slave mode of operation.
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PlUS,
the MSEL bit in the CNTRl register is set to one. In the
master mode, the SK clock rate is selected by the two bits,
SLO and SL 1, in the CNTRl register. Table VI details the
different clock rates that may be selected.

TABLE V. WATCHDOG Service Actions
Key
Data
Match
Don't Care
Mismatch
Don't Care

Window
Data
Match
Mismatch
Don't Care
Don't Care

Clock
Monitor
Match
Don't Care
Don't Care
Mismatch

Action
Valid Service: Restart Service Window
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output

TABLE VI. MICROWIRE/PlUS
Master Mode Clock Select
SL1

SlO

0
0
1

0
1
x

2 x tc
4 x tc
8 x tc

1-264

Where tc is the
instruction cycle clock

(')

MICROWIRE/PLUS (Continued)
MICROWIRE/PLUS OPERATION

The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
;the BUSY flag will be cleared and the sequence may be
repeated.

Setting the BUSY bit in the PSW register causes the MICROWl REI PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 14 shows
how two COP888CS microcontrollers and several peripherals may be interconnected using the MICROWIRE/PLUS
arrangements.

Alternate 5K Phase Operation

MICROWIRE/PLUS Slave Mode Operation

I/O
LINES

G4
Fun.

B - BIT
A/D
COP43X

EEPROM

LCD
DISPLAY
DRIVER

VF
DISPLAY
DRIVER

COPB
(MASTER)

G5
Fun.

en
........

(')

o"'D
Q)
Q)
Q)

(')

........

(')

"'D
Q)
Q)

(')

en
........

(')

o"'D
(')

(')

Q)
~

(')

Ext. MICROWIRE/PLUS
SK Slave

TRI- Ext. ~.1ICRQI."!lRE/PLUS
STATE SK Slave

I/o
LINES

SIH--f....jH--.....z.-+-+----I-I----+-+---I SO
SO

SK
TL/DD/l0830-22

1-265

(')

"'D

Int. MICROWIRE/PLUS
SK Master

COPB
(SLAVE)

FIGURE 18. MICROWIRE/PLUS Application

"en

........

Operation

TRIInt. MICROWIRE/PLUS
STATE SK Master
SO

(')

Q)
Q)

This table assumes that the control flag MSEL is set.
G4 (SO)
G5 (SK)
Config. Bit Con fig. Bit

........

TABLE VII

In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE
Master always initiates all data exchanges. The MSEL bit in
the CNTRL register must be set to enable the SO
and SK functions onto the G Port. The SO and SK pins must
also be selected as outputs by setting appropriate bits in the
Port G configuration register. Table VII summarizes the bit
settings required for Master mode of operation.

Q)
Q)

(')

The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register.
In both the modes the SK is normally low. In the normal
mode data is shifted in on the rising edge of the SK clock
and the data is shifted out o~ the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK clock in the normal mode. In the alternate SK phase
operation, data is shifted in on the falling edge of the SK
clock and shifted out on the rising edge of the SK clock.

Warning:

"en

0r---------------------------------------------------------------~

o
:;

Memory Map

All RAM, ports and registers (except A and PC) are mapped into data memory address space.

o......
o
oco

0000 to 006F

On-Chip RAM bytes (112 bytes)

0070 to 007F

Unused RAM Address Space (Reads
As All Ones)
Unused RAM Address Space (Reads
Undefined Data)

D-

o
......

Address
S/ADDREG

xx80toxxAF

o-.::t
O

xxBOtoxxB6
xxB7
xxB8
xxB9
xxBA

co
co

xxBB

xxBC

o-.::t

xxBD
xxBE
xxBF

co
co

D-

o......
o
oco
D-

o
......
o
co

D-

o......
o
oco
co

xxCOto xxC6
xxC7
xxC8

D-

xxC9
xxCA
xxCB
xxCC
xxCDtoxxCF

Address
S/ADDREG

Contents

Reserved
Comparator Select Register (CMPSL)
UART Transmit Buffer (TBUF)
UART Receive Buffer (RBUF)
UART Control and Status Register
(ENU) .
UART Receive Control and Status
Register (ENUR)
UART Interrupt and Clock Source
Register (ENUI)
UART Baud Register (BAUD)
UART Prescale Select Register (PSR)
Reserved for UART

xxDO
xxD1
xxD2
xxD3
xxD4
xxD5
xxD6
xxD7
xxD8
xxD9
xxDA
xxDB
xxDC
xxDDto OF

Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Regist,er
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
PortO
Reserved for Port 0

xxEOto xxE5
xxE6

xxEE
xxEF

Reserved for EE Control Registers
Timer T1 Autoload Register T1 RB
Lower Byte
Timer T1 Autoload Register T1 RB
Upper Byte
ICNTRL Register
MICROWIRE/PLUS Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1 RA
Lower Byte
Timer T1 Autolo~d Register T1 RA
Upper Byte
CNTRL Control Register
PSW Register

xxFOto FB'
xxFC
xxFD
xxFE
xxFF

On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
S Register

0100-013F

On-Chip RAM Bytes (64 bytes)

xxE7

Reserved
WATCHDOG Service Register
(Reg:WDSVR)
MIWU Edge Select Register
(Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register
(Reg:WKPND)
Reserved
Reserved
Reserved

Contents

xxE8
xxE9
xxEA
xxEB
xxEC
xxED

Reading memory locations 0070H-007FH (Segment 0) will return all ones.
Reading unused memory locations 0080H-00AFH (Segment 0) will return
undefined data. Reading unused memory locations 0140-017F (Segment 1)
will return all ones. Reading memory locations from other Segments (Le.,
Segment 2, Segment 3, ... etc.) will return all ones.
All reserved location reads undefined data.

1-266

a-a

Addressing Modes
The device has ten addressing modes, six for operand addressing and four for transfer of control.

0)
(X)
(X)

OPERAND ADDRESSING MODES
Register Indirect
This is the "normal" addressing mode. The operand is the
data memory addressed by the 8 pointer or X pointer.
Register Indirect (with auto post Increment or
decrement of pointer)

Note: The VIS is a special case of the Indirect Transfer of Control addressing mode, where the double byte vector associated with the interrupt
is transferred from adjacent addresses in the program memory into
the program counter (PC) in order to jump to the associated interrupt
service routine.

This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the 8
pointer or X pointer. This is a register indirect mode that
automatically post increments or decrements the B or X register after executing the instruction.

Instruction Set

The instruction contains an 8-bit address field that directly
points to the data memory for the operand.

Registers
A
B
X
SP
PC
PU
PL
C
HC
GIE

Immediate
The instruction contains an 8-bit immediate field as the operand.
Short Immediate
This addressing mode is used with the Load B Immediate
instruction. The instruction contains a 4-bit immediate field
as the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.

VU
VL

a-a
0)
(X)
~

o
en
......

a-a
(X)
(X)
(X)

Direct

en
......

TRANSFER OF CONTROL ADDRESSING MODES

o
en
......
o

a-a
(X)
(X)
~

en
......
o

a-a
co

(X)
(X)

o
en
......
o

a-a
co

(X)
~

oen

Relative
Symbols

This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
program location. JP has a range from -31 to + 32 to allow
~ 1-bi't~ rc!~t:\:~ l~~tJ (JP -1- 1 l:; iiiip!viii61ltod by it i~O?
instruction). There are no "pages" when using JP, since all
15 bits of PC are used.

[B]

lXJ
MD
Mem
Meml

Imm
Reg

Absolute Long

Bit

This mode is used with the JMPL and JSRL instructions,
with the instruction field of 15 bits replacing the entire 15
bits of the program counter (PC). This allows jumping to any
location in the current 4k program memory space.

~
~

Memory Indirectly Addressed by B
Register
Memory Indirectly Addressed by X
Register
Direct Addressed Memory
Direct Addressed Memory or [B]
Direct Addressed Memory or [B] or
Immediate Data
8-Bit Immediate Data
Register Memory: Addresses FO to FF
(Includes B, X and SP)
Bit Number (0 to 7)
Loaded with
Exchanged with

1-267

Instruction Set

INSTRUCTION SET

en
"

o
co
co
0)
Q.

"en
o
-.::t'

co
co

"en
o
co
co
co

en
"

o
-.::t'

co
(D

"en
o

co
co
(D
Q.

(Continued)

A~A + Meml
A ~ A + Meml + C, C ~ Carry
HC ~ Half Carry
A~A - Meml + C,C~Carry
HC ~ Half Carry

ADD
ADC

A,Meml
A,Meml

ADD
ADD with Carry

SUBC

A,Meml

Subtract with Carry

AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND

A,Meml
A,lmm
A,Meml
A,Meml
MD,lmm
A,Meml
A,Meml
A,Meml
#
Reg
#,Mem
#,Mem
#,Mem

X
LD
LD
LD
LD

A,Mem
A,Meml
B,lmm
Mem,lmm
Reg,lmm

EXchange A with Memory
LoaD A with Memory
LoaD B with Immed.
. LoaD Memory Immed
LoaD Register Memory Immed.

X
X
LD
LD
LD

A, [B ±]
A,[X ±]
A, [B±]
A, [X±]
[B±],lmm

EXchange A with Memory [B]
EXchange A with Memory [X]
LoaD A with Memory [B]
LoaD A with Memory [X]
LoaD Memory [B] Immed.

A ~ [B], (B ~ B ± 1)

CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH

A
A
A

CLeaR A
INCrementA
DECrementA
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
SetC
ResetC
IFC
IFNotC
POP the stack into A
PUSH A onto the stack

A~O

PU ~ [VU], PL ~ [VL]
PC ~ ii (ii = 15 bits, 0 to 32k)
PCg ... 0 ~ i (i = 12 bits)
PC ~ PC + r (r is -31 to +32, except 1)
[SP] ~ PL, [SP-1] ~ PU,SP-2, PC ~ ii
[SP] ~ PL, [SP-1] ~ PU,SP-2, PCg ... 0 ~ i
PL ~ ROM (PU,A)
SP + 2, PL ~ [SP], PU ~ [SP-1]
SP + 2, PL ~ [SP],PU ~ [SP-1]
SP + 2, PL ~ [SP],PU ~ [SP-1],GIE ~ 1
[SP] ~ PL, [SP-1] ~ PU, SP-2, PC ~ OFF
PC~ PC + 1

VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

A
A
A
A

A
A
Addr.
Addr.
Disp.
Addr.
Addr

A~AandMeml

Skip next if (A and Imm)

A~AorMeml

A ~ AxorMeml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A =1= Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B =1= Imm
Reg ~ Reg - 1, Skip if Reg = 0
1 to bit, Mem (bit = 0 to 7 immediate)
o to bit, Mem
If bit in A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
A~Mem

A~Meml
B~lmm

Mem~lmm
Reg~lmm

A~[X],(X~±1)

[B], (B ~ B ± 1)
[X], (X~X±1)
[B] ~ Imm, (B ~ B±1)

A~A+

A~A-1

A
A

ROM (PU,A)
BCD correction of A (follows ADC, SUBC)
C~A7~ ... ~AO~C
C~A7~ ... ~AO~C
A7 ... A4 ~ A3 ... AO
~

C~1,HC~1
C~O,HC~O

IF C is true, do next instruction
If C is not true, do next instruction
SP ~ SP + 1, A ~ [SP]
[SP] .~ A, SP ~ SP - 1

1-268

Instruction Execution Time

""C

0)
(X)
(X)

Most instructions are single byte (with immediate addressing mode instructions taking two bytes).

o
en
........
o

Most single byte instructions take one cycle time to execute.
See the BYTES and CYCLES per INSTRUCTION table for details.
Bytes and Cycles per Instruction

The fol/owing table shows the number of bytes and cycles for each instruction in the format of byte/cycle.

0)
(X)

Arithmetic and Logic Instructions
[B]

Direct

ADD
ADC
SUBC
AND
OR
XOR
iFEQ
IFNE
iFGT
IFBNE
DRSZ

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4

SBIT
RBIT
iFBIT

1/1
1/1
1/1

RPND

1/1

Instructions Using A & C
CLRA
INCA
DECA
LAID
DCOR
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ

Immed.
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2

1/3
3/4
3/4
3/4

1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2

""C

Transfer of Control
Instructions
JMPL
JMP
JP
JSRL
JSR
JID
ViS
RET
RETSK
RETI
INTR
NOP

3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5

117
1/1

01::00

o
en
........
o
o

""C
(X)
(X)
(X)

o
en
o
........

""C
(X)
(X)

01::00

o
en
........
o
o

""C

(0
(X)
(X)

o
en
........
o

o""C
(0
(X)

Memory Transfer Instructions
Register
Indirect

XA,·

1.1) A,·
LDB,lmm
LDB,lmm
LDMem,lmm
LD Reg, Imm
iFEQMD,lmm

[B)

[X]

1/1
1/1

1/3
1/3

Direct Immed.

2/3

2/2

3/3
2/3
3/3

1/3

1/2

1/3
(IF B < 16)
(iF B > 15)

2/2

• = > Memory location addressed by B or X or directly.

1-269

[X+,X-]

1/2
1/1
2/2

2/2

o
en

2/3

01::00

(.)
~

Opcode Table

Upper Nibble Along X-Axis

D-

o(.)

.......

en
(.)

Lower Nibble Along Y-Axis

co
co

JP -15

JP -31

LDOFO, # i

DRSZOFO

D-

JP -14

JP -30

LD OF1, # i

DRSZOF1

.......

JP -13

JP -29

LD OF2, # i

DRSZOF2

JP -12

JP -28

LDOF3, # i

co
co

JP -11

JP -27

o(.)

JP -10

RRCA

ADCA,#i

ADCA,[B]
SUBA,[B]

SUBCA, #i

XA,[X+]

XA,[B+]

IFEO A,#i

IFEOA,[B]

DRSZOF3

XA,[X-]

XA,[B-]

IFGT A,#i

IFGTA,[B]

LDOF4, # i

DRSZOF4

VIS

LAID

ADDA,#i

ADDA,[B]

JP -26

LDOF5, # i

DRSZOF5

RPND

JID

ANDA,#i

ANDA,[B]

JP -9

JP -25

LDOF6, # i

DRSZOF6

XA,[X]

XORA,[B]

co
co
co

JP -24

LDOF7, # i

DRSZOF7

XORA,#i

JP -8

ORA,#i

ORA,[B]

JP -7

JP -23

LDOF8, # i

DRSZOF8

NOP

RLCA

LDA,#i

IFC

o
(.)

JP -6

JP -22

LDOF9, # i

DRSZOF9

IFNE
A;[B]

IFEO
Md,#i

IFNE
A,#i

IFNC

JP -5

JP -21

LDOFA, # i

DRSZOFA

LDA,[X+]

LDA,[B+]

LD [B+ ],#i

INCA

D-

JP -4

JP -20

LDOFB, # i

DRSZOFB

LDA,[X-]

LDA,[B-]

LD [B-'- ],#i

DECA

(.)

JP -3

JP -19

LDOFC, # i

DRSZOFC

LD Md,#i

JMPL

XA,Md

POPA

en
(.)

JP -2

JP -18

LDOFD, # i

DRSZOFD

DIR

JSRL

LDA,Md

RETSK

CO
CO
CD

JP -1

JP -17

LDOFE, # i

DRSZOFE

LDA,[X]

LD [B],#i

RET

LDB,#i

RETI

o(.)
en
(.)
~

D-

.......

(.)

D-

.......

(.)
~

co
CD

.......

D-

(.)

JP -0

JP -16

LDOFF, # i

DRSZOFF

XA,[B]

1-270

LDA,[B]

o
o
"'D

Opcode Table (Continued)

(J)

Upper Nibble Along X-Axis

CO
CO

o
en
......
o

Lower Nibble Along Y-Axis
7

IFBIT
O,[B]

ANDSZ
A, #i

LD B,#OF

IFBIT
1,[B]
IFBIT
2,[B]

·
·

4
IFBNEO

JSR
xOOO-xOFF

JMP
xOOO-xOFF

JP +17

0
INTR

o"'D
(J)

LD B,#OE

IFBNE 1

JSR
x100-x1FF

JMP
x100-x1FF

JP +1B

JP + 2

LD B,#OD

IFBNE2

JSR
x200-x2FF

JMP
x200-x2FF

JP +19

JP + 3

JSR
x300-x3FF

JMP
x300-x3FF

JP +20

CO
0l:Io

en
......

"'D

LD B,#OC

IFBIT
4,[B]

CLRA

LD8,#OB

IFBNE4

JSR
x400-x4FF

JMP
x400-x4FF

JP +21

JP + 5

IFBIT
5,[B]

SWAPA

LD 8,#OA

IFBNE5

JSR
x500-x5FF

JMP
x500-x5FF

JP +22

JP + 6

IF81T
6,[B]

DCORA

LD B,#09

IF8NE6

JSR
x600-x6FF

JMP
x600-x6FF

JP +23

JP + 7

en
......

IFBIT
7,[B]

PUSHA

LD 8,#OB

IFBNE7

JSR
x700-x7FF

JMP
x700-x7FF

JP +24

JP + B

o"'D

SBIT
O,[B]

R81T
O,[B]

LD B,#07

IFBNEB

JSR
xBOO-xBFF

JMP
xBOO-xBFF

JP +25

JP + 9

SBIT
1,[B]

RBIT
1,[B]

LD B,#06

IF8NE9

JSR
x900-x9FF

JMP
x900-x9FF

JP +26

JP + 10

SBIT
2,[B]

R81T
2,[B]

LD 8,#05

JSR
xAOO-xAFF

JMP
xAOO-xAFF

JP +27

SBIT
3,[B]

RBIT
3,[8]

LD B,#04

IFBNE08

JSR
xBOO-xBFF

JMP
xBOO-x8FF

JP +2B

JP + 12

SBIT
4,rBj

RBIT
4,[8J

LD B,#03

IFBNEOC

JSR

JMP

JP +29

JP + 13

~COO-~CFF

~CCO-~CFF

SBIT
5,[B]

RBIT
5,[8]

LD B,#02

IFBNEOD

JSR
xDOO-xDFF

JMP
xDOO-xDFF

JP +30

JP + 14

SBIT
6,[B]

RBIT
6,[8]

LDB,#01

IFBNEOE

JSR
xEOO-xEFF

JMP
xEOO-xEFF

JP +31

JP + 15

SBIT
7,[8]

RBIT
7,[8]

LD B,#OO

IFBNEOF

JSR
xFOO-xFFF

JMP
xFOO-xFFF

JP +32

JP + 16

IFBIT
3,[B]

IF8NE3

JP + 4

CO
CO
CO

o
o
o

en
......
"'D

IFBNEOA

CO
CO
0l:Io

JP + 11

CO
CO
CO

o
o
o

en
......
"'D

CO
CO
0l:Io

Where,
i is the immediate data
Md is a directly addressed memory location
• is an unused opcode
Note: The opcode 60 Hex is also the opcode for IFBIT #i,A

1-271

(.)
~

CIO

(7)

D-

(.)

.....
en
(.)
CIO
CIO

(7)

D-

o(.)

.....
en

(.)
~

CIO
CIO

D-

o(.)
.....
en
(.)
CIO
CIO
CIO

D-

o(.)
.....
en

(.)
~

CIO

D-

(.)

.....
en

OPTION 1: CLOCK CONFIGURATION
1
Crystal Oscillator (CKI/IO)
G7 (CKO) is clock generator
output to crystal/resonator
CKI is the clock input
2
Single-pin RC controlled
oscillator' (CKI/lO)
G7 is available as a HALT
restart and/or general purpose
input

OPTION 3: BONDING OPTIONS
1
44-Pin PLCC
2
40-Pin DIP
NA
3
4
28-Pin DIP
5
28-Pin SO

=
=
=
=
=

Development Support
IN-CIRCUIT EMULATOR

D-

(.)

The iceMASTER's performance analyzer offers a resolution
of better than 6 p.s. The user can easily monitor the time
spent executing specific portions of code and find "hot
spots" or "dead code". Up to 15 indeperident memory areas based on code address or label ranges can be defined.
Analysis results can be viewed in bar graph format or as
actual frequency count.

=
=

CIO
CIO

During Single-step operation the dynamically annotated
code feature displays the contents of all accessed (read
and write) memory locations and registers, as well as flowof-control direction change markers next to each instruction
executed.

OPTION 2: HALT
Enable HALT mode
1
Disable HALT mode
2

(.)

of trace buffer memory. The user may define as many as
32k trace and break triggers which can be enabled, disabled, set or cleared. They can be simple triggers based on
code or address ranges or complex triggers based on code
address, direct address, opcode value, opcode class or immediate operand. Complex breakpoints can be ANDed and
ORed together. Trace information consists of address bus
values, opcodes and user selectable probe clips status (external event lines). The trace buffer can be viewed as raw
hex or as diassembled instructions. The probe clip bit values
can be displayed in binary, hex ordigital waveform formats .

Mask Options
The device mask programmable options are shown below.
The options are programmed at the same time as the ROM
pattern submission.

Emulator memory operations for program memory include
single line assembler, disassembler, view, change and write
to file. Data memory operations include fill, move, compare,
dump to file, examine and modify. The contents of any
memory space can be directly viewed and modified from the
corresponding window.
The iceMASTER comes with an 'easy to use windowed interface. Each window can be sized, highlighted, color-controlled, added, or removed completely. Commands can be
accessed via pull-down-menus and/or redefineable hot
keys. A context sensitive hypertext/hyperlinked on-line help
system explains clearly the options the user has from within
any window.

The ice MASTER connects easily to a PC® via the standard
COMM port and its 115.2 kBaud serial link keeps typical
program download time to under 3 seconds.

The iceMASTER provides real time, full speed emulation up
to 10 MHz, 32 kBytes of emulation memory and 4k frames

The following tables list the emulator and probe cards ordering information.

Emulator Ordering Information
Part Number

Description

IM-COP8/400/1:j:

MetaLink base unit in-circuit emulator for all COP8 devices, symbolic debugger
software and RS-232 serial interface cable, with 11 OV @ 60 Hz Power Supply.

IM-COP8/400/2:j:

MetaLink base unit in-circuit emulator for all COP8 devices, symbolic debugger
software and RS-232 serial interface cable, with 220V @ 50 Hz Power Supply.

DM-COP8/888EG:j:

MetaLink iceMASTER Debug Module. This is the low cost version of MetaLink's
iceMASTER. Firmware: Ver. 6.07.

Hhese parts include National's COP8 Assembler/Linker/Librarian Package (COP8·DEV·IBMA).

1-272

Current Version

Host Software:
Ver. 3.3 Rev. 5,
Model File
Rev. 3.050.

o
o

Development Support (Continued)

"'tJ

0)
Q)
Q)

MACRO CROSS ASSEMBLER

SINGLE CHIP EMULATOR DEVICE

National Semiconductor offers a COP8 macro cross assembier. It runs on industry standard compatible PCs and supports all of the full-symbolic debugging features of the
MetaLink iceMASTER emulators.

The COP8 family is fully supported by One-Time Programmabie (OTP) emulators. For more detailed information refer
to the emulation device specific data sheets and emulator
selection table below. (The COP8788EG/COP8784EG can
be used to emulate the COP888CS/COP884CS.)

"'tJ

0)
Q)
~

Programming of the single chip emulator devices is supported by different sources.
Probe Card Ordering Information
Package

.......

o
o

PROGRAMMING SUPPORT

Part
Number

oen

en
.......

o"'tJ
Q)
Q)
Q)

Voltage
Range

Emulates

.......

MHW-884CG28D5PC

28 DIP

4.5V-5.5V

COP884CS

MHW-884CG28DWPC

28DIP

2.5V-6.0V

COP884CS

MHW-888CG40D5PC

40 DIP

4.5V-5.5V

COP888CS

MHW-888CG40DWPC

40 DIP

2.5V-6.0V

COP888CS

MHW-888CG44D5PC

44 PLCC

4.5V-5.5V

COP888CS

MHW-888CG44DWPC

44 PLCC

2.5V-6.0V

COP888CS

"'tJ

Q)
Q)
~

en
.......

o
o

"'tJ
CD

Q)
Q)

EPROM Programmer Information
U.S. Phone
Number

Manufacturer
and Product

Asia Phone
Number

Europe Phone
Number

MetaLink-Debug Module

(602) 926-0797

Germany: +49-8141-1030

Hong Kong: +852-737-1800

Xeltek-Superpro

(408) 745-7974

Germany: + 49-2041 684758

Singapore:

BP Microsystems-EP-1140

(800) 225-2102

Germany: + 49 89 857 66 67

Hong Kong: + 852 388 0629

Data I/O-Unisite;
-System 29,
-System 39

(800) 322-8246

Europe: +31-20-622866
Germany: + 49-89-85-8020

Japan: + 33-432-6991

-----

"'tJ
CD
Q)
~

----_•.. _-------

Abcom-COP8 Programmer
System General Turpro-1-FX;
-APRO

+ 65 276 6433

o
o
o

en
.......

Europe: + 89 808707
(408) 263-6667

Switzerland: + 31-921-7844

Taiwan Taipei: + 2-9173005

Assembler Ordering Information
Part Number

Description

Manual

COP8-DEV-IBMA

COP8 Assembler/Linker/Librarian for
IBM® PC/XT®, AT® or compatible

424410632-001

Single Chip Emulator Selection Table

Clock Option

Package

Emulates

COP87898EGV-X
COP8788EGV-R*

Crystal

44 PLCC

COP888CS

COP8788EGN-X
COP8788EGN-R*

Crystal

40DIP

COP888CS

COP8784EGN-X
COP8784EGN-R*

Crystal
R/C

28DIP

COP884CS

COP8784EGWM-X*
COP8784EGWM-R*

Crystal

28S0

COP884CS

Device Number

RIC
RIC

RIC

'Check with the local sales office about the availability.

1-273

ooqo
co

c..
oo
......
~

oco

r-----------------------------------------------------------------------~

Development Support (Continued)
DIAL-A-HELPER

ORDER PIN: MOLE-DIAL-A-HLP

Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Bulletin Board Information system.

Information System Package contains:
Dial-A-Helper Users Manual
Public Domain Communications Software

INFORMATION SYSTEM

c..

The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone, lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities could be found. The minimum requirement for accessing the Dial-A-Helper is a Hayes compatible
modem.

......
~

ooqo

co
co

c..
oo
......
~

oco

co
co

c..
oo
......

FACTORY APPLICATIONS SUPPORT

Dial-A-Helper also provides immediate factor applications
support. If a user has questions, he can leave messages on
our electronic bulletin board, which we will respond to.
Voice:

(800) 272-9959

Modem: Canada/U.S.
(800) NSC-Micro:
(800) 672-6427

If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.

Baud:

14.4k

Set-up:

Length:

8-Bit

Parity:

None

Stop Bit: 1
Operation: 24 Hrs., 7 Days

ooqo

co
CD

c..
o

o
......

oco
co
CD

c..

1-274

a"'tJ

CD
CD

/fJNational Semiconductor

o
G)
......

COP884CG/COP888CG
Single-Chip microCMOS Microcontrollers

a"'tJ

General Description

oG)

The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconductor's M2CMOSTM process technology. The COP888CG is a
member of this expandable 8-bit core processor family of
microcontrollers.
(Continued)

Features
•
•
•
•
•
•
•
•
•
•
•

Low cost 8-bit microcontroller
Fully static CMOS, with low current drain
Two power saving modes: HALT and IDLE
1 p's instruction cycle time
4096 bytes on-board ROM
192 bytes on-board RAM
Single supply operation: 2.5V-6V
Full duplex UART
Two analog comparators
MICROWIRE/PLUSTM serial lID
WATCHDOGTM and Clock Monitor logic

• Idle Timer
• Multi-Input Wakeup (MIWU) with optional interrupts (8)
• Three 16-bit timers, each with two 16-bit registers supporting:
- Processor Independent PWM mode
- External Event counter mode
- Input Capture mode
• 8-bit Stack Pointer SP (stack in RAM)
a Two A-hit Rp.!:!i~tl?r Indir",ct D:>.t~ Mem0!''j Pc!nters
(B and X)

CD
CD
CD

• Fourteen mUlti-source vectored interrupts servicing
- External Interrupt
- Idle Timer TO
- Three Timers (Each with 2 Interrupts)
- MICROWIRE/PLUS
- Multi-Input Wake Up
- Software Trap
-UART (2)
- Default VIS
• Versatile instruction set
• True bit manipulation
• Memo~ mapped I/O
• BCD arithmetic instructions
a Package:
- 44 PLCC with 39 lID pins
- 40 N with 35 lID pins
- 28 N with 23 lID pins
- 28 SO with 23 lID pins
• Software selectable lID options
- TRI-STATE® Output
- Push-Pull Output
- Weak Pull Up Input
- High Impedance Input
• Schmitt trigger inputs on ports G and L
• Temperature ranges: -40·C to +85°C
• One-Time Programmable emulation devices
• Real time emulation and full program debug offered by
~.~otQLin:-'s Covolopm60nt Sy~l60ln:s

Block Diagram

II
CPU REGISTERS

TL/OO/9765-1

FIGURE 1. Block Diagram

1-275

oCIO
CIO
CIO

o
......
~

ooo::t

CIO
CIO

o
o

General Description

(Continued)
also be used, independent of the HALT or. IDLE modes.
Each I/O pin has software selectable configurations. The
device operates over a voltage range of 2.5V to 6V. High
throughput is achieved with an efficient, regular instruction
set operating at a maximum of 1 /Ls per instruction rate.

They are fully static parts, fabricated using double-metal silicon gate microCMOS technology. Features include an a-bit
memory mapped architecture, MICROWIRE/PLUS serial
110, three 16-bit timer/counters supporting three modes
(Processor Independent PWM generation, External Event
counter, and Input Capture mode capabilities), full duplex
UART, two comparators, and two power savings modes
(HALT and IDLE), both with a multi-sourced wakeup/interrupt capability. This multi-sourced interrupt capability may

The device has reduced EMI emissions. Low radiated emissions are achieved by gradual turn-on output drivers and
internal Icc filters on the chip logic and crystal oscillator.

Connection Diagrams
Dual-In-Llne Package

Plastic Chip Carrier

CKI

vee

RESET

GNO

07
12
13

44 pin
PLCC

RESET

GNO

01
29

07
40 pin
DIP

05
29

TL/DD/9765-2

Top View
Order Number COP888CG-XXX/V
See NS Plastic Chip Package Number V44A

02·

L2
L3

L4
TL/DD/9765-4

Top View
Order Number COP888CG-XXX/N
See NS Molded Package Number N40A
Dual-In-Llne Package
G3
G2
Gl
GO
RESET
GNO
03
02
01
00
LO

TL/DD/9765-5

Top View
Order Number COP884CG-XXX/N or COP884CG-XXX/WM
See NS Molded Package Number N28A OR M28B
FIGURE 2a. Connection Diagrams

1-276

(")

Connection Diagrams (Continued)

-a
(X)
(X)

Pinouts for 28-, 40- and 44-Pln Packages
Port
LO
L1
L2
L3
L4
L5
L6
L7
GO
G1
G2
G3
G4
G5
G6
G7

Type

liD
liD
liD
liD
liD

AIt.Fun

liD
liD

MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU

liD

INT

I/O

AIt.Fun

CKX
TDX
RDX
T2A
T2B
T3A
T3B

WDOUT

liD
liD
liD
I/O
I
I/CKO

T1B
T1A
SO
SK
SI
HALT Restart

0l:Io
(")

28-Pln
Pack.

40-Pin
Pack.

44-Pln
Pack.

11
12
13
14
15
16
17
18

17
18
19
20
21
22
23
24

17
18
19
20
25
26
27
28

25
26
27
28
1
2
3
4

35
36
37
38
3
4
5
6

39
40
41
42
3
4

19
20
21
22

25
26
27
28

29
30
31
32

7
8
9
10

9
10
11
12

13
14
15
16

10
11
12
13

I
I
I
I

14
15
16
17

I
I
I
I

D4
D5
D6
D7

0
0
0
0

29
30
31
32

33
34
35
36

CO
C1
C2
C3
C4
C5
C6
C7

liD
liD

39
40
1
2

43
44
1
2
21
22
23
24

8
33
7
34

8
37
7
38

I/O

liD
liD
I/O

liD
liD

Vee

6
23
5
24

GND
CKI
RESET

1-277

-a

(X)
(X)
(X)

(")

0
0
0
0

COMP2INCOMP2IN+
COMP20UT

DO
D1
D2
D3

COMP1INCOMP1IN+
COMP10UT

.......

(")

oco
co
co

Absolute Maximum Ratings

co
co

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
7V
Voltage at Any Pin
-0.3V to Vee + 0.3V
Total Current into Vee Pin (Source)
100mA

DC Electrical Characteristics

.......
e"

o
"'1:1'

110 mA
Total Current out of GND Pin (Sink)
- 65°C to + 140°C
Storage Temperature Range
,Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

-40°C S:TA

Parameter

+85°C unless otherwise speeified

Conditions

Power Supply Ripple (Note 1)

Peak-to-Peak

Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz
CKI = 4 MHz
CKI = 1 MHz

Vee
Vee
Vee
Vee

HALT Current (Note 3)
IDLE Current
CKI = 10 MHz
CKI = 4MHz
CKI = 1 MHz

Min

Typ

2.5

Operating Voltage

=
=
=
=

6V, tc = 1 ,...s
6V, tc = 2.5,...s
4.0V, tc = 2.5,...s
4.0V, tc = 10,...s

Vee = 6V, CKI = 0 MHz
Vee = 4.0V, CKI = 0 MHz

<1
<0.5

Vee = 6V, tc = 1 ,...s
Vee = 6V, tc = 2.5,...5
Vee = 4.0V, tc = 10,...s

Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logie High
Logic Low

Max

Units

0.1 Vee

8.0
4.5
2.5
1.4

mA
rnA
rnA
rnA

10
6

,...A
,...A

3.5
2.5
0.7

rnA
rnA
rnA

0.2 Vee

V
V

0.2 Vee

V
V

0.2 Vee

V
V

0.8 Vee

0.7 Vee

Hi-Z Input Leakage

Vee = 6V

-2

,...A

Input Pullup Current

Vee = 6V, VIN = OV

-40

-250

,...A

0.35 Vee

G and L Port Input Hysteresis
Output Current Levels
DOutputs
Source
Sink
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage

Vee
Vee
Vee
Vee

=
=
=
=

4V, VOH = 3.3V
2.5V, VOH = 1.8V
4V, VOL = 1V
2.5V, VOL = O.4V

-0.4
-0.2
10
2.0

Vee
Vee
Vee
Vee
Vee
Vee

=
=
=
=
=
=

4V, VOH = 2.7V
2.5V, VOH = 1.8V
4V, VOH = 3.3V
2.5V, VOH = 1.8V
4V, VOL = O.4V
2.5V, VOL = O.4V

-10
-2.5
-0.4
-0.2
1.6
0.7

-100
-33

,...A
,...A
rnA
rnA
rnA
rnA

-2

,...A

Vee = 6.OV

rnA
rnA
rnA
rnA

Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a crystal/resonator OSCillator, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee, L, C, and GO-G5 configured
as outputs and set high. The 0 port set to zero. The clock monitor and the comparators are disabled.

1-278

DC Electrical Characteristics
Parameter

-40°C::::: TA :::::

o
o

+ 85°C unless otherwise specified (Continued)

Conditions

Min

Units

Max

Typ

"'C

CO
CO
A

G>
.......

Allowable Sink/Source
Current per Pin
o Outputs (Sink)
All others

mA
mA

±100

rnA

Maximum Input Current
without Latchup

TA = 25°C

RAM Retention Voltage, Vr

500 ns Rise
and Fall Time (Min)

Load Capacitance on 02

Parameter
Instruction Cycle Time (td
Crystal, Resonator,
R/C Oscillator

-40°C::::: TA:::::

Input Capacitance

AC Electrical Characteristics

"'C

CO
CO
CO

1000

+ 85°C unless otherwise specified

Conditions

Min

4V::::: Vee::::: 6V
2.5V ::::: Vee < 4V
4V::::: Vee::::: 6V
2.5V ::::: Vee < 4V

1
2.5

4V::::: Vee::::: 6V
2.5V ::::: Vee < 4V
4V::::: Vee::::: 6V
2.5V ::::: Vee < 4V

200
500
60
150

3
7.5

Typ

Max

Units

DC
DC
DC
DC

Jls
Jls
Jls
Jls

Inputs
tSETUP
tHOLD
Output Propagation Delay (Note 4)
tpD1, tPDO
SO,SK
All Others

ns
ns
ns
ns

RL = 2.2k, CL = 100 pF
4V::::: Vee::::: 6V
2.5V ::::: Vee < 4V
4V::::: Vee::::: 6V
2.5V::::: Vee < 4V

MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tUPD)

0.7
1.75
1
2.5

Jls
Jls
Jls
Jls

220

ns
ns
ns

20
56

Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

1
1
1
1

Reset Pulse Width
1
Note 4: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

tc
tc
tc
tc

JlS

1-279

C!J

oco
co
co

Comparators AC and DC Characteristics Vee =
Parameter

D..

Conditions

5V, TA = 25°C

Typ

Min

Max

Units

±25

Input Offset Voltage

C!J

Input Common Mcde Voltage Range

Low Level Output Current

VOL = O.4V

1.6

D..

High Level Output Current

VOH = 4.6V

1.6

""
o
co
co

O.4V

:0;:

VIN

:0;:

±10

Vee - 1.5V
0.4

Vee - 1.5

DC Supply Current Per Comparator
(When Enabled)

250

Response Time

TBD mV Step, TBD mV
Overdrive, 100 pF Load

I
N
T
E
R
N
A
L

~tUPD

TL/DD/9765-7

Pin Descriptions

.......

Vee and GND are the power supply pins.

0
1
1

1
0
1

.~~

.1 CONFIGURATION
'I

DATA
REGISTER

PORT D

PORT I

PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.
The Port L supports Multi-Input Wake Up on all eight pins.
L 1 is used for the UART external clock. L2 and L3 are used
for the UART transmit and receive. L4 and L5 are used for
the timer input functions T2A and T2B. L6 and L7 are used
for the timer input functions T3A and T3B.

The device contains three bidirectional 8-bit I/O ports (C, G
and L), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L and G),
output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also
reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O
ports.) Figure 3 shows the I/O port configurations. The
DATA and CONFIGURATION registers allow for each port
bit to be individually configured under software control as
shown below:

FIGURE 3. I/O Port Configurations

RESET is the master reset input. See Reset Description
section.

TLlDD/9765-B

CKI is the clock input. This can come from an RIC generated oscillator, or a crystal oscillator (in conjunction with
CKO). See Oscillator Description section.

DATA
Register

DATA
REGISTER

B
U
S

FIGURE 2. MICROWIRE/PLUS Timing

CONFIGURATION
Register

/LA
/Ls

PORT L, C, AND G

.....--

~
tUWH

The Port L has the following alternate features:
LO

MIWU

MIWU or CKX

MIWU or TDX

MIWU or RDX

MIWU orT2A

MIWU or T2B

MIWU or T3A

MIWU orT3B

Port Set-Up
Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output

1-280

Pin Descriptions (Continued)

Functional Description

The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store memory (RAM). 80th ROM and RAM have their own separate
addressing space with separate address buses. The architecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.

.......

CPU REGISTERS

oG)

The CPU can do an 8-bit addition, subtraction, logical or
shift operation in one instruction (td cycle time.

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
8 is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.

Port G has the following alternate features:

SP is the 8-bit stack pointer, which points to the subroutinel
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.

GO INTR (External Interrupt Input)
G2 T18 (Timer T1 Capture Input)
G3 T1A (Timer T1 1/0)

S is the 8-bit Data Segment Address Register used to extend the lower half of the address range (00 to 7F) into 256
data segments of 128 bytes each.

G4 SO (MICROWIRETM Serial Data Output)
G5 SK (MICROWIRE Serial Clock)

All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).

G6 SI (MICROWIRE Serial Data Input)
Port G has the following dedicated functions:

PROGRAM MEMORY

G1 WDOUT WATCHDOG andlor Clock Monitor dedicated output

The program memory consists· of 4096 bytes of ROM.
These bytes may hold program instructions or constant data
(data tables for the LAID instruction, jump vectors for the
JID instruction, and interrupt vectors for the VIS instruction).
The program memory is addressed by the 15-bit program
counter (PC). All interruptg in the devices vector to progmm
memory location OFF Hex.

G7 CKO Oscillator dedicated output or general purpose
input
Port C is an 8-bit 1/0 port. The 40-pin device does not have
a full complement of Port C ping. ThA IJOAVAiiAhiA ping ArA
not terminated. A read operation for these unterminated
pins will return unpredicatable values.

DATA MEMORY

PORT I is an eight-bit Hi-Z input port. The 28-pin device
does not have a full complement of Port I pins. The unavailable pins are not terminated Le., they are floating. A read
operation for these unterminated pins will return unpredictable values. The user must ensure that the software takes
this into account by either masking or restricting the accesses to bit operations. The unterminated Port I pins will draw
power only when addressed.

The data memory address space includes the on-chip RAM
and data registers, the 1/0 registers (Configuration, Data
and Pin), the control registers, the MICROWIRE/PLUS SIO
shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer).
Data memory is addressed directly by the instruction or indirectly by the 8, X, SP pointers and S register.
The device has 192 bytes of RAM. Sixteen bytes of RAM
are mapped as "registers" at addresses OFO to OFF Hex.
These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and
skip if zero) instruction. The memory pointer registers X, SP,
8 and S are memory mapped into this space at address
locations OFC to OFF Hex respectively, with the other registers being available for general usage.

Port 11-13 are used for Comparator 1. Port 14-16 are used
for Comparator 2.
The Port I has the following alternate features.
11

COMP1-IN (Comparator 1 Negative Input)

COMP1 + IN (Comparator 1 Positive Input)

COMP10UT (Comparator 1 Output)

COMP2-IN (Comparator 2 Negative Input)

COMP2+IN (Comparator 2 Positive Input)

COMP20UT (Comparator 2 Output)

The instruction set permits any bit in memory to be set,
reset or tested. All 1/0 and registers (except A and PC) are
memory mapped; therefore, 1/0 bits and register bits can be
directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.

Port 0 is an 8-bit output port that is preset high when
RESET goes low. The user can tie two or more 0 port outputs together in order to get a higher drive.

Note: RAM contents are undefined upon power-up.

1-281

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C»
C»
~

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C»
C»
C»

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D..

o
......
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~
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D..

Data Memory Segment RAM Extension
Data memory address OFF is used as a memory mapped
location for the Data Segment Address Register (S).

(beyond the initial 128 bytes) are memory mapped at address locations 0100 to 013F hex.

The data store memory is either addressed directly by a
single byte address within the instruction, or indirectly relative to the reference of the B, X, or SP pOinters (each contains a single-byte address). This single-byte address allows
an addressing range of 256 locations from 00 to FF hex.
The upper bit of this single-byte address divides the data
store memory into two separate sections as outlined previously. With the exception of the RAM register memory from
address locations OOFO to OOFF, all RAM memory is memory mapped with the upper bit of the single-byte address being equal to zero. This allows the upper bit of the single-byte
address to determine whether or not the base address
range (from 0000 to OOFF) is extended. If this upper bit
equals one (representing address range 0080 to OOFF),
then address extension does not take place. Alternatively, if
this upper bit equals zero, then the data segment extension
register S is used to extend the base address range (from
0000 to 007F) from XXOO to XX7F, where XX represents the
8 bits from the S register. Thus the 128-byte data segment
extensions are located from addresses 0100 to 017F for
data segment 1, 0200 to 027F for data' segment 2, etc., up
to FFOO to FF7F for data segment 255. The base address
range from 0000 to 007F represents data segment O.

XXff

RAM REGISTERS
(16 BYTES)
INCLUDES B, X, SP, S

XXfO
XXEF

TIMERS, I/o, MW.
CNTRL, PSW, A/D,
ICNTRL, WD. MIWU,
COfolPARATOR
AND UART
REGISTERS

XXBO

XXAF

T
S
E

UNUSED
(READS UNDEfINED
DATA)

XX8 0
007 f
007 0
006 f

UNUSED'

o1 7 f _ - - - - - - .
, UNUSED

G
foI
E
N
T

ON CHIP RAfol

o13f 1 - - - - - - - 4

(112 BYTES)

-L

ON CHIP RAM
(64 BYTES)

-.L

000 0

01 ooL-----.II

TLlDD/9765-9

'Reads as all ones.

FIGURE 4. RAM Organization

Figure 4 illustrates how the S register data memory extension is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XXOO
to XX7F. This organization allows a total of 256 data segments of 128 bytes each with an additional upper base segment of 128 bytes. Furthermore, all addressing modes are
available for all data segments. The S register must be
changed under program control to move from one data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory registers, 1/0 registers,
control registers, etc.) is always available regardless of the
contents of the S register, since the upper base segment
(address range 0080 to OOFF) is independent of data segment extension.

Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports l. G and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WATCHDOG andlor Clock Monitor error
output pin. Port D is set high. The PC, PSW, ICNTRl,
CNTRl, T2CNTRl and T3CNTRl control registers are
cleared. The UART registers PSR, ENU (except that TBMT
bit is set), ENUR and ENUI are cleared. The Comparator
Select Register is cleared. The S register is initialized to
zero. The Multi-Input Wakeup registers WKEN, WKEDG and
WKPND are cleared. The stack pOinter, SP, is initialized to
6F Hex.

The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
116 bytes of RAM are resident from address 0000 to 006F
in the lower base segment, while the rerTlaining 16 bytes of
RAM represent the 16 data memory registers located at addresses OOFO to OOFF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.

The external RC network shown in Figure 5 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.

1-282

Reset

w
S
P
P

L
Y

vee
D

3. Internal leakage current-13

o"'0

4. Output source current-14

Q:)
Q:)
Q:)

5. DC current caused by external input
not at Vee or GND-15

GND

oC)

6. Comparator DC supply current when enabled-16
7. Clock Monitor current when enabled-17

FIGURE 5. Recommended Reset Circuit

Thus the total current drain, It, is given as
It = 11

Oscillator Circuits

+ 12 +

+ 14 + 15 + 16 + 17

To reduce the total current drain, each of the above components must be minimum.

The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input frequency· is divided down by 10 to produce the instruction
cycle clock (1 ltd.

Figure 6 shows the Crystal and RIC diagrams.
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.

12 = C

Table A shows the component values required for various
standard crystal values.

xVxf

where C = equivalent capacitance of the chip
V = operating voltage
f = CKI frequency

RIC OSCILLATOR
By selecting CKI as a single pin oscillator input, a single pin
RIC oscillator circuit can be connected to it. CKO is available as a general purpose input, and lor HALT restart input.

Control Registers
CNTRL Register (Address X'OOEE)

Table B shows the variation in the oscillator frequencies as
functions of the component (R and C) values.

CKO

oC)
.......
o

2. Internal switching current-12

COPBOO
RESET

RC > 5 x Power Supply Rise Time

CKI

Q:)
Q:)

1. Oscillator operation mode-11

TL/DD/9765-10

"'0

The total current drain of the chip depends on:

E
R
U

Current Drain

(Continued)

The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:

SL 1 & SLO Select the MICROWIRE/PLUS clock divide
by (00 = 2,01 = 4, 1x = 8)

LJRI
i~~ 1"
-- --

IEDG

External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)

MSEL

Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively

T1CO

Timer T1 StartlStop control in timer
modes 1 and 2

TL/DD/9765-12

Timer T1 Underflow Interrupt Pending Flag in
timer mode 3

TL/DD/9765-11

FIGURE 6. Crystal and RIC Oscillator Diagrams
TABLE A. Crystal Oscillator Configuration, T A

= 25°C

R1
(kn)

R2
(Mn)

C1
(pF)

C2
(pF)

CKI Freq
(MHz)

Conditions

0
0
0

1
1
1

30
30
200

30-36
30-36
100-150

10
4
0.455

Vee = 5V
Vee = 5.0V
Vee = 5V

C
(pF)

CKI Freq
(MHz)

Instr. Cycle
(Il-s)

3.3
5.6
6.8

82
100
100

2.2 to 2.7
1.1 to 1.3
0.9 to 1.1

3.7 to 4.6
7.4 to 9.0
8.8 to 10.8

Conditions
Vee
Vee
Vee

Timer T1 mode control bit

T1 C2

Timer T1 mode control bit

T1 C3

Timer T1 mode control bit

Bit7

TABLE B. RC Oscillator Configuration, T A = 25°C
R
(kn)

T1 C1

= 5V
= 5V
= 5V

Note: 3k ;<;; R ;<;; 200k
50 pF ;<;; C ;<;; 200 pF

1-283

BitO

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Control Registers

(Continued)

PSW Register (Address X/OOEF)

T2C1

Timer T2 mode control bit

The PSW register contains the following select bits:

T2C2

Timer T2 mode control bit

T2C3

Timer T2 mode control bit

GIE

Global interrupt enable (enables interrupts)

EXEN

Enable external interrupt

BUSY

MICROWIRE/PLUS busy shifting flag

EXPND

External interrupt pending

T1 ENA

Timer T1 Interrupt Enable for Timer Uilderflow
or T1A Input capture edge

The T3CNTRL register contains the following bits:

T1 PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1 A capture edge in mode 3)
C

Carry Flag

Half Carry Flag

T3ENB

T3ENA

T3CO

The ICNTRL register contains the following bits:

Timer T3 mode control bit

T3C3

Timer T3 mode control bit

The device contains a very versatile set of timers (TO, T1,
T2, T3). All timers and associated autoreload/capture registers power up containing random data.

Timer TO Interrupt Enable (Bit 12 toggle)

TOPND

Timer TO Interrupt pending

LPEN

L Port Interrupt Enable (Multi-Input Wakeup/Interrupt)

TIMER TO (IDLE TIMER)

The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timerTO, which is a
16-bit timer. The Timer TO runs continuously at the fixed
rate of the instruction cycle clock, tc. The user cannot read
or write to the IDLE Timer TO, which is a count down timer.
The Timer TO supports the following functions:

Bit 7 could be used as a flag

Bit7

BitO

Timers

Enable MICROWIRE/PLUS interrupt

TOEN

BitO

T2CNTRl Register (Address X/OOC6)

Exit out of the Idle Mode (See Idle Mode description)
WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode
The IDLE Timer TO can generate an interrupt when the thirteenth bit toggles. This toggle is latched into the TOPND
pending flag, and will occur every 4 ms at the maximum
clock frequency (tc = 1 /Ls). A control flag TOEN allows the
interrupt from the thirteenth bit of Timer TO to be enabled or
disabled. Setting TOEN will enable the interrupt, while resetting it will disable the Interrupt.

The T2CNTRL register contains the following bits:
Timer T2 Interrupt Enable for T2B Input capture
edge

T2PNDB Timer T2 Interrupt Pending Flag for T2Bcapture edge
Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA
in mode 1, T2 Underflow in mode 2, T2A capture edge in mode 3)
T2CO

Timer T3 mode control bit

T3C2

Bit7

/LWPND MICROWIRE/PLUS interrupt pending

T2ENA

T3C1

Timer T1 Interrupt Enable for T1 B Input capture
edge

T1 PNDB Timer T1 Interrupt Pending Flag for T1 B capture edge

T2ENB

Timer T3 Start/Stop control in timer modes 1
and 2
Timer T3 Underflow Interrupt Pending Flag ,in
timer mode 3

ICNTRl Register (Address X/OOE8)

/LWEN

Timer T3 Interrupt Enable for Timer Underflow
or T3A pin

T3PNDA Timer T3 Interrupt Pending Flag (Autoload RA
in mode 1, T3 Underflow in mode 2, T3a capture edge in mode 3)

BitO

The Half-Carry bit is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the carry'flags. In addition to the SC and RC instructions, ADC,
SUBC, RRC and RLC instructions affect the carry and Half
Carry flags.

T1 ENB

Timer T3 Interrupt Enable for T3B

T3PNDB Timer T3 Interrupt Pending Flag for T3B pin
(T3B capture edge)

I HC IC IT1 PNDA IT1 ENA IEXPND IBUSY IEXEN I GIE I
Bit7

BitO

Bit7

T3CNTRl Register (Address X/OOB6)

Timer T2 Start/Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3

1-284

Timers

a""D

(Continued)

(X)
(X)

TIMER T1, TIMER T2 AND TIMER T3

,1::0.

oG')

The device has a set of three powerful timer/counter
blocks, T1, T2 and T3. The associated features and functioning of a timer block are described by referring to the
timer block Tx. Since the three timer blocks, T1, T2 and T3
are identical, all comments are equally applicable to any of
the three timer blocks.

TIt.lER
UNDERflOW
INTERRUPT

........

a""D

+-----,

(X)
(X)
(X)

TxA

oG')

Each timer block consists of a 16-bit timer, Tx, and two
supporting 16-bit autoreload/capture registers, RxA and
RxB .. Each timer block has two pins associated with it, TxA
and TxB. The pin TxA supports I/O required by the timer
block, while the pin TxB is an input to the timer block. The
powerful and flexible timer block allows the device to easily
perform all timer functions with minimal software overhead.
The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and
Input Capture mode.
The control bits TxC3, TxC2, and TxC1 allow selection of
the different modes of operation.

tC-----...J

TL/DD/9765-14

FIGURE 7. Timer in PWM Mode
Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that
the timer, Tx, is clocked by the input signal from the TxA pin.
The Tx timer control bits, TxC3, TxC2 and TxC1 allow the
timer to be clocked either on a positive or negative edge
from the TxA pin. Underflows from the timer are latched into
the TxPNDA pending flag. Setting the TxENA control flag
will cause an interrupt when the timer underflows.

Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention. The
user only has to define the parameters of the PWM signal
(ON time and OFF time). Once begun, the timer block will
continuously generate the PWM signal completely independent of the microcontroller. The user software services the
timer block only when the PWM parameters require updating.
In this mode the timer Tx counts down at a fixed rate of te.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.
The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
ti,ilai fOi P\v'JiY~ riooda opara.tion.

In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
Figure 8 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock.

TIt.lER
UNDERFLOW
INTERRUPT

Figure 1 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the TxA output pin. The underflows can also be programmed to generate interrupts.
Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control enable flags, TxENA and TxENB, allow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be
reloaded into the timer. Resetting the timer enable flags will
disable the associated interrupts.
Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.

+----...,

TxA

Ix B~ To Interrupt Control
TL/DD/9765-15

FIGURE 8. Timer in External Event Counter Mode
Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode.
In this mode, the timer Tx is constantly running at the fixed
te rate. The two registers, RxA and RxB, act as capture
registers. Each register acts in conjunction with a pin. The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin.

1-285

(!J

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.......

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o
o

Timers

(Continued)

The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently.
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.

TLlDD/9765-16

FIGURE 9. Timer In Input Capture Mode
TIMER CONTROL FLAGS
The timers T1, T2 and T3 have indentical control structures.
The control bits and their functions are summarized below.
TxCO

Timer Start/Stop control in Modes 1 and 2
(Processor Independent PWM and External
Event Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)

TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag

Figure 9 shows a block diagram of the timer in Input Capture
mode.

TxENA Timer Interrupt Enable Flag
TxENB ' Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
o = Timer Interrupt Disabled
TxC3
Timer mode control
TxC2
Timer mode control
TxC1
Timer mode control

1-286

Timers

0
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(Continued)

The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:

0I::loo

Interrupt A
Source

Interrupt B
Source

Timer
Counts On

TxC3

TxC2

TxC1

Timer Mode

MODE 2 (External
Event Counter)

Timer
Underflow

Pos. TxB
Edge

TxA
Pos.Edge

MODE 2 (External
Event Counter)

Timer
Underflow

Pos. TxB
Edge

TxA
Neg. Edge

MODE 1 (PWM)
TxA Toggle

Autoreload
RA

Autoreload
RB

MODE 1 (PWM)
No TxA Toggle

Autoreload
RA

Autoreload
RB

MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Pos. Edge

Pos. TxA
Edge or
Timer
Underflow

Pos. TxB
Edge

MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Neg. Edge

Pos. TxA
Edge or
Timer
Underflow

Neg. TxB
Edge

MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Pos. Edge

Neg. TxB
Edge or
Timer
Underflow

Pos. TxB
Edge

MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Neg. Edge

Neg. TxA
Edge or
Timer
Underflow

Neg. TxB
Edge

0
'"
0

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0

Power Save Modes
The device offers the user two power save modes of operation: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscillator circuitry the WATCHDOG logic, the Clock Monitor and
timer TO are active but all other microcontroller activities are
stopped. In either mode, all on-board RAM, registers, 1/0
states, and timers (with the exception of TO) are unaltered.

fioumtion (since CKO hflcomfls a nflrlicatAn output), anrl !':o
~ay be used with an RC clock configuration. The third
method of exiting the HALT mode is by pulling the RESET
pin low.

Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the te instruction cycle clock. The te
clock is derived by dividing the oscillator clock down by a
factor of 10. The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE timer is clocked only
when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger specifications. This Schmitt trigger
is not part of the oscillator closed loop. The startup timeout
from the IDLE timer enables the clock signals to be routed
to the rest of the chip.

HALT MODE
The device can be placed in the HALT mode by writing a
"1" to the HALT flag (G7 data bit). All microcontroller activities, including the clock and timers, are stopped. The
WATCHDOG logic is disabled during the HALT mode. However, the clock monitor circuitry if enabled remains active
and will cause the WATCHDOG output pin (WDOUT) to go
low. If the HALT mode is used and the user does not want
to activate the WDOUT pin, the Clock Monitor should be
disabled after the device comes out of reset (resetting the
Clock Monitor control bit with the first write to the WDSVR
register). In the HALT mode, the power requirements of the
device are minimal and the applied voltage (Vee> may be
decreased to Vr (Vr = 2.0V) without altering the state of the
machine.

1-287

"ococo
co

a..

......

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~

a..

Power Save Modes (Continued)
The device has two mask options associated with the HALT
mode. The first mask option enables the HALT mode feature, while the second mask option disables the HALT
mode. With the HALT mode enable mask option, the device
will enter and exit the HALT mode as described above. With
the HALT disable mask option, the device cannot be placed
in the HALT mode (writing a "1" to the HALT flag will have
no effect).

This toggle condition of the thirteenth bit of the IDLE Timer
TO is latched into the TOPND pending flag.
The user has the option of being interrupted with a transition
on the thirteenth bit of the IDLE Timer TO. The interrupt can
be enabled or disabled via the TOEN control bit. Setting the
TOEN. flag enables the interrupt and vice versa.
The user can enter the IDLE mode with the Timer TO interrupt enabled. In this case, when the TOPND bit gets set, the
device will first execute the Timer TO interrupt service routine and then return to the instruction following the "Enter
Idle Mode" instruction.

IDLE MODE
The device is placed in the IDLE mode by writing a "1" to
the IDLE flag (G6 data bit). In this mode, all activities, except
the associated on-board oscillator circuitry, the WATCHDOG logic, the clock monitor and the IDLE Timer TO, are
stopped.

Multi-Input Wakeup

As with the HALT mode, the device can be returned to normal operation with a reset,or with a Multi-Input Wakeup
from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the thirteenth
bit (representing 4.096 ms at internal clock frequency of
1 MHz, te = 1 /Ls) of the IDLE Timer toggles.

The Multi-Input Wakeup feature is ued to return (wakeup)
the device from either the HALT or IDLE modes. Alternately
Multi-Input Wakeup/Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts.

Figure 10 shows the Multi-Input Wakeup logic.

TLlDD/9765-17

·FIGURE 10. Multi-Input Wake Up Logic

1-288

Multi-Input Wakeup

o
o

(Continued)

WKEN, WKPND and WKEDG are all read/write registers,
and are cleared at reset.

The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an 8bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, fOllowed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.

PORT L INTERRUPTS
Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into
the same service subroutine.

5,
5,
5,
5,

0l::Io

.......

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en
en
en

RBIT
SBIT
RBIT
SBIT

en
en

WKEN
WKEDG
WKPND
WKEN

The Wakeup signal will not start the chip running immediately since crystal oscillators or ceramic resonators have a finite start up time. The IDLE Timer (TO) generates a fixed
delay to ensure that the oscillator has indeed stabilized before allowing the device to execute instructions. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry and the IDLE Timer TO are enabled. The IDLE Timer is loaded with a value of 256 and is clocked from the te
in~tr"Gtion cycle clock. The tc c!0~k is d~ri\!ed by cH'!ldlr.g
down the oscillator clock by a factor of 10. A Schmitt trigger
following the CKI on-chip inverter ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large
amplitude to meet the Schmitt trigger specifications. This
Schmitt trigger is not part of the oscillator closed loop. The
startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip.
If the RC clock option is used, the fixed delay is under software control. A control flag, CLKDLY, in the G7 configuration bit allows the clock start up delay to be optionally inserted. Setting CLKDLY flag high will cause clock start up delay
to be inserted and resetting it will exclude the clock start up
delay. The CLKDLY flag is cleared during reset, so the clock
start up delay is not present following reset with the RC
clock options.

If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup/lnterrupt, a safety procedure should also be followed to avoid inherited
pseudo wakeup conditions. After the selected L port bits
have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired
edge selects, followed by the associated WKPND bits being
cleared.
This same procedure should be used following reset, since
the L port inputs are left floating as a result of reset.
The occurrence of the selected trigger condition for MUlti-Input Wakeup is latched into a pending register called
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since WKPND is a pending
register for the occurrence of selected wakeup conditions,
the device will not enter the HALT mode if any Wakeup bit is
both enabled and pending. Consequently, the user has the
responsibility of clearing the pending flags before attempting to enter the HALT mode.

1-289

oco
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.......
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UART
The COP888CG contains a full-duplex software programmable UART. The UART (Figure 11) consists of a transmit
shift register, a receiver shift register and seven addressable registers, as follows: a transmit buffer register (TBUF),
a receiver buffer register (RBUF), a UART control and
status register (ENU), a UART receive control and status
register (ENUR), a UART interrupt and clock source register
(ENUI), a prescaler select register (PSR) and baud (BAUD)
register. The ENU register contains flags for transmit and
receive functions; this register also determines the length of
the data frame (7, 8 or 9 bits), the value of the ninth bit in
transmission, and parity selection bits. The ENUR register
flags framming, data overrun and parity errors while the
UART is receiving.

Other functions of the ENUR register include saving the
ninth bit received in the data frame, enabling or disabling the
UART's attention mode of operation and providing additional receiver/transmitter status information via RCVG and
XMTG bits. The determination of an internal or external
clock source is done by the ENUI register, as well as selecting the number of stop bits and enabling or disabling transmit and receive interrupts. A control flag in this register can
also select the UART mode of operation: asynchronous or
synchronous.

WAKE-UP LOGIC
RDX

W
E
DOE
FE

I
N
T

1--------. INTERRUPT

E
R
N
A
L

1--------. INTERRUPT
TDX

D
A
T
A

XMIT RECV
CLOCK CLOCK

CKX

CKI
TL/DD/9765-18

FIGURE 11. UART Block Diagram

1-290

o
o

UART (Continued)

"'C

PSEL1 = 1, PSELO = a
PSEL 1 = 1, PSELO = 1

UART CONTROL AND STATUS REGISTERS
The operation of the UART is programmed through three
registers: ENU, ENUR and ENUI. The function of the individual bits in these registers is as follows:
ENU-UART Control and Status Register (Address at OBA)
PEN
ORW

PSEL1 XBIT91 CHL1
PSELO
ORW ORW ORW

CHLO

ERR

RBFL TBMT

ORW

Bit7

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......

PEN: This bit enables/disables Parity (7- and 8-bit modes
only).
PEN = a Parity disabled.
PEN = 1 Parity enabled.

ENUR-UART RECEIVE CONTROL AND
STATUS REGISTER

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RCVG: This bit is set high whenever a framing error occurs
and goes low when RDX goes high.

BitO

ENUR-UART Receive Control and Status Register
(Address at OBB)

Mark(1) (if Parity enabled)
Space(O) (if Parity enabled)

XMTG: This bit is set to indicate that the UART is transmitting. It gets reset at the end of the last frame (end of last
Stop bit).
ATTN: ATIENTION Mode is enabled while this bit is set.
This bit is cleared automatically on receiving a character
with data bit nine set.

BOO

RBIT9: Contains the ninth data bit received when the UART
is operating with nine data bits per frame.

ENUI-UART Interrupt and Clock Source Register
(Address at aBC)

SPARE: Reserved for future use.

PE: Flags a Parity Error.
PE = a Indicates no Parity Error has been detected since
the last time the ENUR register was read.
PE = 1 Indicates the occurrence of a Parity Error.

BOO

OBit is not used.

Bit is cleared on reset.

Bit is set to one on reset.

Bit is read-only; it cannot be written by software.

FE: Flags a Framing Error.
FE = a Indicates no Framing Error has been detected
since the last time the ENUR register was read.
FE = 1 Indicates the occurrence of a Framing Error.

RW Bit is read/write.
D

DOE: Flags a Data Overrun Error.
DOE = a Indicates no Data Overrun Error has been detected since the last time the ENUR register
was read.
DOE = 1 Indicates the occurrence of a Data Overrun Error.

Bit is cleared on read; when read by software as a one, it is cleared
automatically. Writing to the bit does not affect its state.

DESCRIPTION OF UART REGISTER BITS
ENU-UART CONTROL AND STATUS REGISTER
TBMT: This bit is set when the UART transfers a byte of
data from the TBUF register into the TSFT register for transmission. It is automatically reset wh'en software writes into
the TBUF register.

ENUI-UART INTERRUPT AND
CLOCK SOUHCt: Ht:GISTER
ETI: This bit enables/disables interrupt from the transmitter
section.
ETI = a Interrupt from the transmitter is disabled.
ETI = 1 Interrupt from the transmitter is enabled.

RBFL: This bit is set when the UART has received a complete character and has copied it into the RBUF register. It
is automatically reset when software reads the character
from RBUF.

ERI: This bit enables/disables interrupt from the receiver
section.
ERI = a Interrupt from the receiver is disabled.
ERI = 1 Interrupt from the receiver is enabled.

ERR: This bit is a global UART error flag which gets set if
any or a combination of the errors (DOE, FE, PEl occur.
CHL 1, CHLO: These bits select the character frame format.
Parity is not included and is generated/verified by hardware.
CHL 1 = a, CHLO = a The frame contains eight data bits.
CHL 1 = a, CHLO = 1 The frame contains seven data
bits.
CHL 1 = 1, CHLO = a The frame contains nine data bits.
CHL 1 = 1, CHLO = 1 Loopback Mode selected. Transmitter output internally looped
back to receiver input. Nine bit
framing format is used.

XTCLK: This bit selects the clock source for the transmittersection.
XTCLK = a The clock source is selected through the
PSR and BAUD registers.
XTCLK = 1 Signal on CKX (L 1) pin is used as the clock.
XRCLK: This bit selects the clock source for the receiver
section.
XRCLK = a The clock source is selected through. the
PSR and BAUD registers. ,
XRCLK = 1 Signal on CKX (L 1) pin is used as the clock.

XBIT9/PSELO: Programs the ninth bit for transmission
when the UART is operating with nine data bits per frame.
For seven or eight data bits per frame, this bit in conjunction
with PSEL 1 selects parity_

SSEL: UART mode select.
SSEL = a Asynchronous Mode.
SSEL = 1 Synchronous Mode.

PSEL 1, PSELO: Parity select bits.
PSEL 1 = 0, PSELO = a Odd Parity (if Parity enabled)
PSEL 1 = a, PSELO = 1 Even Parity (if Parity enabled)

1-291

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STP78: This bit is set to program the last Stop bit to be
7/8th of a bit in length.

C-

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C-

when a framing error occurs and goes low once RDX goes
high. TBMT, XMTG, RBFL and RCVG are read only bits.

UART (Continued)
ETDX: TDX (UART Transmit Pin) is the alternate function
assigned to Port L pin L2; it is selected by setting ETDX bit.
To simulate line break generation, software should reset
ETDX bit and output logic zero to TDX pin through Port L
data and configuration registers.

SYNCHRONOUS MODE

In this mode data is transferred synchronously with the
clock. Data is transmitted on the rising edge and received
on the falling edge of the synchronous clock.
This mode is selected by setting SSEL bit in the ENUI register. The input frequency· to the UART is the same as the
baud rate.

STP2: This bit programs the number of Stop bits to be transmitted.
STP2 = 0 One Stop bit transmitted.
STP2 = 1 Two Stop bits transmitted.

When an external clock input is selected at the CKX pin,
data transmit and receive are performed synchronously with
this clock through TDX/RDX pins.
If data transmit and receive are selected with the CKX pin
as clock output, the device generates the synchronous
clock output at the CKX pin. The internal baud rate generator is used to produce the synchronous clock. Data transmit
and receive are performed synchronously with this clock.

Associated I/O Pins
Data is transmitted on the TDX pin and received on the RDX
pin. TDX is the alternate function assigned to Port L pin L2;
it is selected by setting ETDX (in the ENUI register) to one.
RDX is an inherent function of Port L pin L3, requiring no
setup.

FRAMING FORMATS
The UART supports several serial framing formats (Figure
12). The format is selected using control bits in the ENU,
ENUR and ENUI registers.

The baud rate clock for the UART can be generated on~
chip, or can be taken from an external source. Port L pin L1
(CKX) is the external clock 110 pin. The CKX pin can be
either an input or an output, as determined by Port L Configuration and Data registers (Bit 1). As an input, it accepts a
clock signal which may be selected to drive the transmitter
andlor receiver. As an output, it presents the internal Baud
Rate Generator output.

The first format (1, 1a, 1b, 1c) for data transmission (CHLO
= 1, CHL 1 = 0) consists of Start bit, seven Data bits (excluding parity) and 7/8, one or two Stop bits. In applications
using parity, the parity bit is generated and verified by hardware.
The second format (CHLO = 0, CHL 1 = 0) consists of one
Start bit, eight Data bits (excluding parity) and 7/8, one or
two Stop bits. Parity bit is generated and verified by hardware.

UART Operation
The UART has two modes of operation: asynchronous
mode and synchronous mode.

The third format for transmission (CHLO = 0, CHL 1 = 1)
consists of one Start bit, nine Data bits and 7/8, one or two
Stop bits. This format also supports the UART "ADENTION" feature. When operating in this format, all eight bits
of TBUF and RBUF are used for data. The ninth data bit is
transmitted and received using two bits in the ENU and
ENUR registers, called XBIT9 and RBIT9. RBIT9 is a read
only bit. Parity is not generated or verified in this mode.

ASYNCHRONOUS MODE
This mode is selected by resetting the SSEL (in the ENUI
register) bit to zero. The input frequency to the UART is 16
times the baud rate.
The TSFT and TBUF registers double-buffer data for transmission. While TSFT is shifting out the current character on
the TDX pin, the TBUF register may be loaded by software
with the next byte to be transmitted. When TSFT finishes
transmitting the current character the contents of TBUF are
transferred to the TSFT register and the Transmit Buffer
Empty Flag (TBMT in the ENU register) is set. The TBMT
flag is automatically reset by the UART when software loads
a new character into the TBUF register. There is also the
XMTG bit which is set to indicate that the UART is transmitting. This bit gets reset at the end of the last frame (end of
last Stop bit). TBUF is a readlwrite register.

For any of the above framing formats, the last Stop bit can
be programmed to be 7/8th of a bit in length. If two Stop
bits are selected and the· 7/8th bit is set (selected), the
second Stop bit will be 7/8th of a bit in length.
The parity is enabledldisabled by PEN bit located in the
ENU register. Parity is selected for 7- and 8-bit modes only.
If parity is enabled (PEN = 1), the parity selection is then
performed by PSELO and PSEL1 bits located in the ENU
register.

The RSFT and RBUF registers double-buffer data being received. The UART receiver continually monitors the signal
on the RDX pin for a low level to detect the beginning of a
Start bit. Upon sensing this low level, it waits for half a bit
time and samples again. If the RDX pin is still low, the receiver considers this to be a valid Start bit, and the remaining bits in the character frame are each sampled a single
time, at the mid-bit position. Serial data input on the RDX pin
is shifted into the RSFT register. Upon receiving the complete character, the contents of the RSFT register are copied into the RBUF register and the Received Buffer Full Flag
(RBFL) is set. RBFL is automatically reset when software
reads the character from the RBUF register. RBUF is a read
only register. There is also the RCVG bit which is set high

Note that the XBIT9/PSELO bit located in the ENU register
serves two mutually exclusive functions. This bit programs
the ninth bit for transmission when the UART is operating
with nine data bits per frame. There is no parity selection in
this framing format. For other framing formats XBIT9 is not
needed and the bit is PSELO used in conjunction with
PSEL1 to select parity.
The frame formats for the receiver differ from the transmitter in the number of Stop bits required. The receiver only
requires one Stop bit in a frame, regardless of the setting of
the Stop bit selection bits in the control register. Note that
an implicit assumption is made for full duplex UART operation that the framing formats are the same for the transmitter and receiver.

1-292

UART Operation
11

16
1
lb

l
I

26
1
2b

l
I

3
1

36~

(Continued)

START
BIT

"'0

7 BIT DATA

CO
CO

START
BIT

7 BIT DATA

START
BIT

7 BIT DATA

START
BIT

7 BIT DATA

START
BIT

8 BIT DATA

START
BIT

8 BIT DATA

START
BIT

8 BIT DATA

START
BIT

8 BIT DATA

START
BIT

9 BIT DATA

START
BIT

9 BIT DATA

oI:lo

.......

L
L
2S

"'0

CO
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CO

L
2S

L
L
2S

L
2S

TL/DD/9765-19

FIGURE 12. Framing Formats
UART INTERRUPTS

source selected in the PSR and BAUD registers. Interna"y,
the basic baud clock is created from the oscillator freouencv
through a two-stage divider chain consisting of a 1-16 (in'crements of 0.5) prescaler and an 11-bit binary counter.
(Figure 13) The divide factors are specified through two
read/write registers shown in Figure 14. Note that the 11-bit
Baud Rate Divisor spills over into the Prescaler Select Register (PSR). PSR is cleared upon reset.

The UART is cl'Ipl'Ible of gflnArAting int A rrupt'3, IntlO'rrvpts e.r~
generated on Receive Buffer Full and Transmit Buffer Empty. Both interrupts have individual interrupt vectors. Two
bytes of program memory space are reserved for each interrupt vector. The two vectors are located at addresses OxEC
to OxEF Hex in the program memory space. The interrupts
can be individually enabled or disabled using Enable Transmit Interrupt (ETI) and Enable Receive Interrupt (ERI) bits in
the ENUI register.

As shown in Table I, a Prescaler Factor of 0 corresponds to
NO CLOCK. NO CLOCK condition is the UART power down
mode where the UART clock is turned off for power saving
purpose. The user must also turn the UART clock off when
a different baud rate is chosen.

The interrupt from the Transmitter is set pending, and remains pending, as long as both the TBMT and ETI bits are
set. To remove this interrupt, software must either clear the
ETI bit or write to the TBUF register (thus clearing the TBMT
bit).

The correspondences between the 5-bit Prescaler Select
and Prescaler factors are shown in Table I. Therer are many
ways to calculate the two divisor factors, but one particularly
effective method would be to achieve a 1.8432 MHz frequency coming out of the first stage. The 1.8432 MHz prescaler output is then used to drive the software programmable baud rate counter to create a x16 clock for the following
baud rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400,
3600, 4800, 7200, 9600, 19200 and 38400 (Table II). Other
baud rates may be created by using appropriate divisors.
The x16 clock is then divided by 16 to provide the rate for
the serial shift registers of the transmitter and receiver.

The interrupt from the receiver is set pending, and remains
pending, as long as both the RBFL and 'ERI bits are set. To
remove this interrupt, software must either clear the ERI bit
or read from the RBUF register (thus clearing the RBFL bit).

Baud Clock Generation
The clock inputs to the transmitter and receiver sections of
the UART can be individually selected to come either from
an external source at the CKX pin (port L, pin L 1) or from a

1-293

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r-------------------------------------------------------------------------Baud Clock Generation
UART TRANSMIT
CLOCK
MUX

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(Continued)

+16

BAUD RATE SELECT
11 BITS

PRESCALER
5 BITS
+1 TO +16

CRYSTAL

UART RECEIVE
CLOCK
TL/DD/9765-20

FIGURE 13. UART BAUD Clock Generation

~RESCALER SELECT REGISTER (PSR)

·1.

BAUD REGISTER

•

1,1,1,110,,", lsi 1,1 1,1,1,1 101
5

~PRESCALER
~ SELECT

·1.

·1

BAUD RATE DIVISOR

TL/DD/9765-21

FIGURE 14. UART BAUD Clock Divisor Registers
TABLE I. Prescaler Factors
Prescaler
Select

Prescaler
Factor

00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

NO CLOCK
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
16

TABLE II. Baud Rate Divisors
(1.8432 MHz Prescaler Output)
Baud
Rate

Baud Rate
Divisor - 1 (N-1)

110 (110.03)
134.5 (134.58)
150
300
600
1200
1800
2400
3600
4800
7200
9600
19200
38400

1046
855
767
383
191
95
63
47
31
23
15
11
5
2

The entries in Table II assume a prescaler output
of 1.B432 MHz. In the asynchronous mode the
baud rate could be as high as 625k.

As an example, considering the Asynchronous Mode .and a
CKI clock of 4.608 MHz, the prescaler factor selected is:
4.608/1.8432

2.5

The 2.5 entrY is available in Table J. The 1.8432 MHz pre·
scaler output is then used with proper Baud Rate Divisor
(Table II) to obtain different baud rates. For a baud rate of
19200 e.g., the entry in Table II is 5.
N - 1 = 5 (N -1 is the value from Table II)
N = 6 (N is the Baud Rate Divisor)
Baud Rate

1.8432 MHz/(16

19200

The divide by 16 is performed because in the asynchronous
mode, the input frequency to the UART is 16 times the baud
rate. The equation to calculate baud rates is given below.
The actual Baud Rate may be found from:
BR = Fc/(16

1-294

~--------------------------------------------------------------------------,

Baud Clock Generation

Note that the framing format for this mode is the nin~ bit
format; one Start bit, nine data bits, and 7/8, one or two
Stop bits. Parity is not generated or verified in this mode.

(Continued)

Where:
BR is the Baud Rate
Fc is the CKI frequency

Attention Mode

N is the Baud Rate Divisor (Table II).

The UART Receiver section supports an alternate mode of
operation, referred to as ATTENTION Mode. This mode of
operation is selected by the ATTN bit in the ENUR register.
The data format for transmission must also be selected as
having nine Data bits and either 7/8, one or two Stop bits.

P is the Prescaler Divide Factor selected by the value in the
Prescaler Select Register (Table I)
Note: In the Synchronous Mode, the divisor 16 is replaced by two.

Example:
Crystal Frequency = 5 MHz
Desired baud rate = 9600
Using the above equation N x P can be calculated first.

P = (5

10 6 )/(16

9600) = 32.552

Now 32.552 is divided by each Prescaler Factor (Table II) to
obtain a value closest to an integer. This factor happens to
be 6.5 (P = 6.5).
N

= 32.552/6.5 = 5.008 (N = 5)

Using the above values calculated for Nand P:

10 6 )/(16

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.......

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While in ATTENTION mode, the UART monitors the communication flow, but ignores all characters until an address
character is received. Upon receiving an address character,
the UART signals that the character is ready by setting the
RBFL flag, which in turn interrupts the processor if UART
Receiver interrupts are enabled. The ATTN bit is also
cleared automatically at this point, so that data characters
as well as address characters are recognized. Software examines the contents of the RBUF and responds by deciding
either to accept the subsequent data stream (by leaving the
ATTN bit reset) or to wait until the next address character is
seen (by setting the ATTN bit again).

The programmed value (from Table II) should be 4 (N - 1).
BR = (5

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The ATTENTION mode of operation is intended for use in
networking the device with other processors. Typically in
such environments the messages consists of device addresses, indicating which of several destinations should receive them, and the actual data. This Mode supports a
scheme in which addresses are flagged by having the ninth
bit of the data field set to a 1. If the ninth bit is reset to a
zero the byte is a Data byte.

Asynchronous Mode:

6.5) = 9615.384

% error = (9615.385 - 9600)/9600 = 0.16

Effect of HALT /IDLE
The UART logic is reinitialized when either the HALT or
IDLE modes are entered. This reinitialization sets the TBMT
flag and resets all read only bits in the UART control and
status registers. Read/Write bits remain unchanged. The
Transmit Buffer (TBUF) is not affected, but the Transmit
Shift register (TSFT) bits are set to one. The receiver registers RBUF and RSFT are not affected.

Operation of the UART Transmitter is not affected by selection of this Mode. The value of the ninth bit to be transmitted
is programmed by setting XBIT9 appropriately. The value of
the ninth bit received is obtained by reading RBIT9. Since
this bit is located in ENUR register where the error flags
reside; a bit operation on it will reset the error flags.

The device will exit from the HALTIIDLE modes when the
Start bit of a character is detected at the RDX (L3) pin. This
feature is obtained by using the Multi-Input Wakeup scheme
provided on the device.

Comparators
Tho GO'v'ic;; cv"t"i,, 10kHz-No clock rejection.
1 ftc < 10Hz-Guaranteed clock rejection.
1-298

Watchdog and Clock Monitor Summary
The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted:

""C

• With the single-pin R/C oscillator mask option selected
and the CLKDLY bit reset, the WATCHDOG service window will resume following HALT mode from where it left
off before entering the HALT mode.

• Both the WATCHDOG and CLOCK MONITOR detector
circuits are inhibited during RESET.

• With the crystal oscillator mask option selected, or with
the single-pin R/C oscillator mask option selected and
the CLKDLY bit set, the WATCHDOG service window will
be set to its selected value from WDSVR following HALT.
Consequently, the WATCHDOG should not be serviced
for at least 2048 instruction cycles following HALT, but
must be serviced within the selected window to avoid a
WATCHDOG error.

• Following RESET, the WATCHDOG and CLOCK MONITOR are both enabled, with the WATCHDOG having he
maximum service window selected.
• The WATCHDOG service window and CLOCK MONITOR enable/disable option can only be changed once,
during the initial WATCHDOG service following RESET.
• The initial WATCHDOG service must match the key data
value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error.

Q:)
Q:)
~

oG)

......

o""C
Q:)
Q:)
Q:)

oG)

• The IDLE timer TO is not initialized with RESET.
• The user can sync in to the IDLE counter cycle with an
IDLE counter (TO) interrupt or by monitoring the TOPND
flag. The TOPND flag is set whenever the thirteenth bit of
the IDLE counter toggles (every 4096 instruction cycles).
The user is responsible for resetting the TOPND flag.

• Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG errors.
• The correct key data value cannot be read from the
WATCHDOG Service register WDSVR.Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all O's.

• A hardware WATCHDOG service occurs just as the de~
vice exits the IDLE mode. Consequently, the WATCHDOG should not be serviced for at least 2048 instruction
cycles following IDLE, but must be serviced within the
selected window to avoid a WATCHDOG error.

• The WATCHDOG detector circuit is inhibited during both
the HALT and IDLE modes.
• The CLOCK MONITOR detector circuit is active during
both the HALT and IDLE modes. Consequently, the device inadvertently entering the HALT mode will be detected as a CLOCK MONITOR error (provided that the
CLOCK MONITOR enable option has been selected by
the program).

• Following RESET, the initial WATCHDOG service (where
the service window and the CLOCK MONITOR enable/
disable must be selected) may be programmed anywhere within the maximum service window (65,536 instruction cycles) initialized by RESET. Note that this initial WATCHDOG service may be programmed within the
initial 2048 instruction cycles without causing a WATCHDOG error.

1-299

"ococo
co

......

"oco
"I::t'

Detection of Illegal Conditions

MICROWIRE/PLUS

MICROWIRE/PlUS is a serial synchronous communications interface. The MICROWIRE/PlUS capability enables
the device to interface with any of National Semiconductor's
MICROWIRE peripherals (Le. AID converters, display drivers, E2PROMs etc.) and with other microcontrollers which
support the MICROWIRE interface. It consists of an a-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK). Figure' 12
shows a block diagram of the MICROWIRE/PlUS logic.

The subroutine stack grows down for each call Gump to
subroutine), interrupt, or PUSH, and grows up for each return or POP. The stack pointer is initialized to RAM location
06F Hex during reset. Consequently, if there are more returns than calls, the stack pointer will point to addresses
070 and 071 Hex (which are undefined RAM). Undefined
RAM from addresses 070 to 07F (Segment 0), 140 to 17F
(Segment 1), and all other segments (Le., Segments 3 ...
etc.) is read as all 1's, which in turn will cause the program
to return to address 7FFF Hex. This is an undefined ROM
location and the instruction fetched (all O's) from this location will generate a software interrupt Signaling an illegal
condition.
Thus, the chip can detect the following illegal conditions:

t------.INTERRUPT

~~--~~--------~SO

~-~~~~~----SI

a. Executing from undefined ROM
b. Over "POP"ing the stack by having more returns than
calls. '
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that
following reset, but might not contain the same program
initialization procedures). The recovery program should reset the software interrupt pending bit using the RPND instruction.

TLlDD/9765-23

, FIGURE 16. MICROWIRE/PLUS Block Diagram
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIREI
PLUS arrangement with the internal clock source is called
the Master mode of operation. Similarly, operating the
MICROWIRE/PlUS arrangement with an external shift
clock is called the Slave mode of operation.
The CNTRl register is used to configure and control the
MICROWIRE/PlUS mode. To use the MICROWIRE/PlUS,
the MSEl bit in the CNTRl register is set to one. In the
master mode, the SK clock rate is selected by the two bits,
SlO and Sl1, in the CNTRl register. Table VI details the
different clock rates that may be selected.

TABLE V. WATCHDOG Service Actions
Key
Data

Window
Data

Clock
Monitor

Action
Valid Service: Restart Service Window

Match

Don't Care

Mismatch

Don't Care

Mismatch

Don't Care

Error: Generate WATCHDOG Output

Don't Care

Mismatch

Error: Generate WATCHDOG Output

TABLE VI. MICROWIRE/PLUS
Master Mode Clock Select
SL1

SLO

0
0
1

0
1

x te
4 X te
a x te

1-300

Where te is the
instruction cycle clock

MICROWIRE/PLUS (Continued)

"'C

MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the MICROWl REI PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 13 shows
how two devices, microcontrollers and several peripherals
may be interconnected using the MICROWIRE/PLUS arrangements.

Alternate SK Phase Operation
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register.
In both the modes the SK is normally low. In the normal
mode data is shifted in on the rising edge of the SK clock
and the data is shifted out on the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK clock. In the alternate SK phase operation, data is shifted in on the falling edge of the SK clock and shifted out on
the rising edge of the SK clock.

Warning:
The SIO register should only be loaded when the SK clock
is low. Loading the SIO register while the SK clock is high
will result in undefined data in the SIO register. SK clock is
normally low when not shifting.

co
co
A

oG)
.......

"'C

co
co
co

TABLE VII

In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE
Master always initiates all data exchanges. The MSEL bit in
the CNTRL register must be set to enable the SO and SK
functions onto the G Port. The SO and SK pins must also be
selected as outputs by setting appropriate bits in the Port G
configuration register. Table VII summarizes the bit settings
required for Master mode of operation.

This table assumes that the control flag MSEL is set.
G4(SO)
G5 (SK)
Config. Bit Con fig. Bit

MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin mll'~t OA 81'O'II'O'ctl'O'd e.'3 e.n in~'.!t
and the SO pin is selected as an output pin by setting and
resetting the appropriate bit in the Port G configuration register. Table VII summarizes the settings required to enter
the Slave mode of operation.

~......,.

AID

EEPROM

LCD
DISPLAY
DRIVER
COP472

VF
DISPLAY
DRIVER

COP43X

DO SK DI

SK DI

! i

! t

Operation

Int. MICROWIRE/PLUS
SK Master

Int. MICROWIRE/PLUS
TRISTATE SK Master
SO

Ext. MICROWIRE/PLUS
SK Slave

TRI- Ext. MICROWIRE/PLUS
STATE SK Slave

I/o
LINES

COPS
(SLAVE)

DO SK DI

G5
Fun.

...--

COPS
(MASTER)

...

8 - BIT

..-

::E

I/o

CHIP SELECT LINES

/5
/

LINES
-'0..
A

G4
Fun.

+-+

SO
SI
SK
TL/DD/9765-24

FIGURE 17. MICROWIRE/PLUS Application

1-301

Memory Map

All RAM, ports and registers (except A and PC) are mapped into data memory address space.

o.......
o00::1'

"
co
co
DO

Address
S/ADDREG
0000 to 006F

On-Chip RAM bytes (112 bytes)

0070 to007F

Unused RAM Address Space (Reads
As All Ones)
Unused RAM Address Space (Reads
Undefined Data)

xx80toxxAF
xxBO
XXB1
xxB2
xxB3
xxB4
xxB5
xxB6
xxB7
xxB8
xxB9
xxBA
xxBB
xxBC
xxBD
xxBE
xxBF
xxCO
xxC1
xxC2
xxC3
xxC4
xxC5
xxC6
xxC7
xxC8
xxC9
xxCA
xxCB
xxCC
xxCDtoxxCF

Address
S/ADD REG

Contents

Timer T3 Lower Byte
Timer T3 Upper Byte
Timer T3 Autoload Register T3RA
Lower Byte
Timer T3 Autoload Register T3RA
Upper Byte
Timer T3 Autoload Register T3RB
Lower Byte
Timer T3 Autoload Register T3RB
Upper Byte
Timer T3 Control Register
Comparator Select Register (CMPSL)
UART Transmit Buffer (TBUF)
UART Receive Buffer (RBUF)
UART Control and Status Register
(ENU)
UART Receive Control and Status
Register (ENUR)
UART Interrupt and Clock Source
Register (ENUI)
UART Baud Register (BAUD)
UART Prescale Select Register (PSR)
Reserved for UART

xxDO
xxD1
xxD2
xxD3
xxD4
xxD5
xxD6
xxD7
xxD8
xxD9
xxDA
xxDB
xxDC
xxDDto DF

Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port D
Reserved for Port D

xxEO to xxE5
xxE6

xxEE
xxEF

Reserved for EE Control Registers
Timer T1 Autoload Register T1 RB
Lower Byte
Timer T1 Autoload Register T1 RB
Upper Byte
ICNTRL Register
MICROWIRE/PLUS Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1 RA
Lower Byte
Timer T1 Autoload Register T1 RA
Upper Byte
CNTRL Control Register
PSW Register

xxFOto FB
xxFC
xxFD
xxFE
xxFF

On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
S Register

0100-013F

On-Chip 64 RAM Bytes

xxE7
xxE8
xxE9
xxEA
xxEB
xxEC
xxED

Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA
Lower Byte
Timer T2 Autoload Register T2RA
Upper Byte
Timer T2 Autoload Register T2RB
Lower Byte
Timer T2 Autoload Register T2RB
Upper Byte
Timer T2 Control Register
WATCHDOG Service Register
(Reg:WDSVR)
MIWU Edge Select Register
(Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register
(Reg:WKPND)
Reserved
Reserved
Reserved

Contents

Reading memory locations 0070H-007FH (Segment 0) will return all ones.
Reading unused memory locations 0080H-00AFH (Segment 0) will return
undefined data. Reading unused memory locations 0140-017F (Segment 1)
will return all ones. Reading memory locations from other Segments (i.e.,
Segment 2, Segment 3, ... etc.) will return all ones.

1-302

(')

o."

Addressing Modes
There are ten addressing modes, six for operand addressing and four for transfer of control.

CD
CD

Indirect

This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits
of PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruction.

(')
G')

......
(')

o."
CD
CD
CD

(')
G')

Instruction Set
Register and Symbol Definition

Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.·

Registers
A
B

Immediate
The instruction contains an 8-bit immediate field as the operand.
.

X
SP
PC
PU
PL
C
HC
GIE

Short Immediate
This addressing mode is used with the Load B Immediate
instruction. The instruction contains a 4-bit immediate field
as the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.

VU
VL

8-Bit Accumulator Register
8-Bit Address Register
. 8-Bit Address Register
8-Bit Stack Pointer Register
15-Bit Program Counter Register
Upper 7 Bits of PC
Lower 8 Bits of PC
1 Bit of PSW Register for. Carry
·1 Bit of PSW Register for Half Carry
1 Bit of PSW Register for Global
Interrupt Enable
Interrupt Vector Upper Byte
Interrupt Vector Lower Byte

TRANSFER OF CONTROL ADDRESSING MODES
Relative
Symbols

This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
program location. JP has a range from -31 to +32 to allow
Cl i -byte relative jump (JP + 1 is implemented by a NOP
instruction). There are no "pages" when using JP, since all
15 bits of PC are used.

[B)

[X]
MD
Mem
Meml

Imm
Reg

Absolute Long

Bit

~
~

Memory Indirectly Addressed by B
ReQister
Memory Indirectly Addressed by X
Register
o'irect Addressed Memory
Direct Addressed Memory or [B)
Direct Addressed Memory or [B) or
Immediate Data
8-Bit Immediate Data
Register Memory: Addresses FO to FF
(Includes B, X and SP)
Bit Number (0 to 7) .
Loaded with
Exchanged with

1-303

C!J

~
co
~

Instruction Set (Continued)
INSTRUCTION SET

o........

ADD
ADC

A,Meml
A,Meml

o
~

SUBC

A,Meml

Subtract with Carry

AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND

A,Meml
A,lmm
A,Meml·
A,Meml
MD,lmm
A,Meml
A,Meml
A,Meml
#
Reg
#,Mem
#,Mem
#,Mem

X
X
LD
LD
LD
LD
LD

A,Mem
A,[X]
A,Meml
A,[X]
B,lmm
Mem,lmm
Reg,lmm

EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with MemorY [X]
LoaD B with Immed.
: LoaD Memory Immed
LoaD Register Memory Immed.

X
X
LD
LD
LD

A, [B ±]
A, [X ±]
A, [B±]
A, [X±]
[B±],lmm

EXchange A with Memory [B]
EXchange A with Memory [X]
LoaD A with Memory [B]
LoaD A with Memory [X]
LoaD Memory [B]lmmed.

A~ [B],(B~B

CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH

A
A
A

CLeaR A
INCrementA
DECrementA
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
Sete
ResetC
IFC
IFNotC
POP the stack into A
PUSH A onto the stack

A~O

PU ~ [VU], PL ~ [VL]
PC ~ ii (ii = 15 bits, 0 to 32k)
PC9 ... 0~i(i = 12 bits)
PC ~ PC + r (r is -31 to +32, except 1)
[SP] ~ PL, [SP-1] ~ PU,SP-2, PC ~ ii
[SP] ~ PL, [SP-1] ~ PU,SP-2, PCg ... 0 ~ i
PL ~ ROM (PU,A)
SP + 2, PL ~ [SP], PU ~ [SP-1]
SP + 2, PL ~ [SP)'PU ~ [SP-1]
SP + 2, PL ~ [SP],PU ~ [SP-1],GIE ~ 1
[SP] ~ PL, [SP-1] ~ PU, SP-2, PC ~ OFF
PC~PC + 1

C!J

co
co
c..

VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

A
A
A
A

A
A
Addr.
Addr.
Disp.
Addr.
Addr

A~A

+ Meml
+ Meml +
HC ~ Half Carry
A~A - Meml +
HC ~ Half Carry

ADD
. ADD with Carry

A~A

e,C~Carry
e,C~Carry

A~AandMeml

Skip next if (A and Imm)

A~AorMeml

A ~ A xorMeml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A =1= Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B =1= Imm
Reg ~ Reg - 1, Skip if Reg = 0
1 to bit, Mem (bit = 0 to 7 immediate)
o to bit, Mem
If bit in A or Mem is true do next instruction
Reset SoftWare Interrupt Pending Flag
A~Mem

A~[X]
A~Meml
A~[X]
B~lmm

Mem~lmm
Reg~lmm

±1)

A~[X],(X~±1)
A~ [B],(B~B ±1)
A ~ [X], (X ~ X±1)

[B] ~ Imm, (B ~ B±1)
A~A+

A~A-1

A ~ ROM (PU,A)
A ~ BCD correction of A (follows ADC, SUBC)
C~A7~ ... ~AO~e
C~A7~ ... ~AO~e
A7 ... A4~A3 ... AO
C~1,HC~1
C~O,HC~O

IF e is true, do next instruction
If e is not true, do next instruction
SP~SP + 1,A~ [SP]
[SP] ~A,SP~SP-1

1·304

Instruction Execution Time

-a

CO
CO

Most instructions are single byte (with immediate addressing mode instructions taking two bytes).

.a::.

oG')

Most single byte instructions take one cycle time to execute.

......
o

See the BYTES and CYCLES per INSTRUCTION table for details.

Bytes and Cycles per Instruction

-a

The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle.

Arithmetic and Logic Instructions
[B]

Direct

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4

SBIT
RBIT
IFBIT

1/1
1/1
1/1

3/4
3/4
3/4

RPND

1/1

ADD
ADCSUBC
AND
OR
XOR IFEQ
IFNE
IFGT
IFBNE
DRSZ

Instructions Using A & C

Immed.

CLRA
INCA
DECA
LAID
DCOR
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ

2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2,
'2/2

1/3

1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2

CO
CO
CO

Transfer of Control
Instructions
JMPL
JMP
JP
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP

oG')

3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
1/7
1/1

Memory Transfer Instructions
Register
Indirect

Direct Immed.

[B]

[X]

''110/',

V" •

1 /1

1/3

2/3

LDA,·
LDB,lmm
LDB,lmm
LDMem,lmm
LD Reg, Imm
IFEQMD,lmm

1/1

1/3

2/3

• =

2/2

2/2
1/1
2/2

3/3
2/3
3/3

[X+,X-]

1/2

1/3

1/2

1/3
(lFB < 16)
(IFB> 15)

2/2

> Memory location addressed by B or X or directly.

1·305

oco

co
co
DO

o
.......
CJ

co
co
DO

Opcode Table
Upper Nibble Along X-Axis
Lower Nibble Along Y-Axis

JP -15

JP -31

LD OFO, # i

DRSZOFO "

RRCA

ADCA,#i

ADCA,[B]

JP -14

JP -30

LDOF1, # i

DRSZOF1

SUBCA, #i

SUBA,[B]

JP -13

JP -29

' LDOF2, # i

DRSZOF2

XA,[X+]

XA,[B+]

IFEQA,#i

IFEQA,[B]

JP -12

JP -28

LDOF3, # i

DRSZOF3

XA, [X-]

XA,[B-]

IFGTA,#i

IFGTA,[B]

JP -11

JP -27

LDOF4, # i

DRSZOF4

VIS

LAID

ADDA,#i

ADDA,[B]

JP -10

JP -26

LDOF5, # i

DRSZOF5

RPND

JID

ANDA,#i

ANDA,[B]

5
6

JP -9

JP -25,

LDOF6, # i

DRSZOF6

XA,[X]

XA,[B]

XORA,#i

XORA,[B]

JP -8

JP -24

LDOF7, # i

DRSZOF7

ORA,#i

ORA,[B]

JP -7

:JP -23

LD OF8, # i,

DRSZOF8

NOP

RLCA

LDA,#i

IFC

JP -6

JP -22

LD'OF9, # i

DRSZOF9

IFNE
A,[B]

,IFEQ
Md,#i

IFNE
A,#i

IFNC

JP -5

JP -21

LDOFA, # i

DRSZOFA

LDA,[X+]

LDA,[B+]

LD [B+ ],#i'

INCA

JP -4

JP -20

LDOFB, # i

DRSZOFB

LDA,[X-]

LDA,[B-]

LD [B-],#i

DECA

JP -3

JP -19

LDOFC, # i

DRSZOFC

LD Md,#i

JMPL

XA,Md

POPA

JP -2

JP -18

LDOFD, # i

DRSZOFD

DIR

JSRL

LDA,Md

RETSK

JP -1

JP -17

LDOFE, # i

DRSZOFE

LDA,[X]

LDA,[B]

LD [B]'#i

RET

JP -0

JP -16

LDOFF, # i

DRSZOFF

LDB,#i

RETI

1-306

(')

Opcode Table

(Continued)

"'C
CO
CO

Upper Nibble Along X-Axis

0I::loo

(')
C)

Lower Nibble Along V-Axis

"(')

IFBIT
O,[B]

ANOSZ
A, #i

LO B,#OF

IFBNEO

JSR
xOOO-xOFF

JMP
xOOO-xOFF

JP +17

INTR

LO B,#OE

IFBNE 1

JSR
x100-x1FF

JMP
x100-x1FF

JP +18

JP + 2

LO B,#OO

IFBNE2

JMP
x200-x2FF

JP +19

JP + 3

JSR
x200-x2FF

LOB,#OC

IFBNE3

JSR
x300-x3FF

JMP
x300-x3FF

JP +20

JP + 4

IFBIT
4,[B]

CLRA

LOB,#OB

IFBNE4

JSR
x400-x4FF

JMP
x400-x4FF

JP +21

JP + 5

IFBIT
5,[B]

SWAPA

LD B,#OA

IFBNE 5

JSR
x500-x5FF

JMP
x500-x5FF

JP +22

JP + 6

IFBIT
6,[B]

OCORA

LOB,#09

IFBNE6

JSR
x600-x6FF

JMP
x600-x6FF

JP +23

JP + 7

IFBIT
7,[B]

PUSHA

LO B,#08

IFBNE7

JSR
x700-x7FF

JMP
x700-x7FF

JP +24

JP + 8

SBIT
O,[B]

RBIT
O,[B]

LOB,#07

IFBNE 8

JSR
x800-x8FF

JMP
x800-x8FF

JP +25

JP + 9

SBIT
1,[B]

RBIT
1,[B]

LOB,#06

IFBNE9

JSR
x900-x9FF

JMP
x900-x9FF

JP +26

JP + 10

SBIT
2,[B]

RBIT
2,[B]

LO B,#05

IFBNEOA

JSR
xAOO-xAFF

JMP
xAOO-xAFF

JP +27

JP + 11

SBIT
3,[B]

RBIT
3,[B]

LOB,#04

IFBNEOB

JSR
xBOO-xBFF

JMP
xBOO-xBFF

JP +28

JP + 12

SBIT
4,[B]

RBIT
4,[B]

LOB,#03

IFBNEOC

JSR
xCOO-xCFF

JMP
xCOO-xCFF

JP +29

JP + 13

SBIT
5,[B]

RBIT
5,[B]

LO B,#02

IFBNEOO

JSR
xOOO-xOFF

JMP
xOOO-xOFF

JP +30

JP + 14

SBIT
5,[9]

RBIT
6,[9]

LO B,#01

IFBNEOE

JSR

JMP
xEOO-xEFF

JP +31

JP + 15

xEOO-xErr

SBIT
7,[B]

RBIT
7,[B]

LO B,#OO

JSR
xFOO-xFFF

JMP
xFOO-xFFF

JP +32

JP + 16

·
·

IFBIT
1,[B]
IFBIT
2,[B]
IFBIT
3,[B]

IFBNEOF

o"'C
CO
CO
CO
(')
C)

Where.
i is the immediate data
Md is a directly addressed memory location
• is an unused opcode
Note: The opcode 60 Hex is also the opcode for IFBIT #i,A

Mask Options
The mask programmable options are shown below. The options are programmed at the same time as the ROM pattern
submission.

OPTION 2: HALT

=1
=2
OPTION
=1
=2
=3
=4
=5

OPTION 1: CLOCK CONFIGURATION

Crystal Oscillator (CKI/10)
G7 (CKO) is clock generator
output to crystal/resonator
CKI is the clock input

Single-pin HC controlled
oscillator (CKI/1O)
G7 is available as a HALT
restart and/or general purpose
input

1-307

Enable HALT mode
Disable HALT mode
3: BONDING OPTIONS
44-Pin PLCC
40-Pin DIP
N/A
28-Pin DIP
28-Pin SO

u
CX)
CX)
CX)

a..
o
u
.......
~

u
~

CX)
CX)

a..
ou

Development Support
The iceMASTER comes with an easy to use window interface. Each window can be sized, highlighted, color-controlled, added, or removed completely. Commands can be
accessed via pull-down-menus and lor redefinable hot keys.
A context sensitive hypertextlhyperlinked on-line help system explains clearly the options the user has from within
any window.

IN-CIRCUIT EMULATOR
The MetaLink iceMASTERTM-COP8 Model 400 In-Circuit
Emulator for the COP8 family of microcontrollers features
high-performance operation, ease of use, and an extremely
flexible user-interface or maximum productivity. Interchangeable probe cards, which connect to the standard
common base, support the various configurations and packages of the COP8 family.
The iceMASTER provides real time, full speed emulation up
to 10 MHz, 32 kBytes of emulation memory and 4k frames
of trace buffer memory. The user· may define as many as
32k trace and break triggers which can be enabled, disabled, set or cleared. They can be simple triggers based on
code or address ranges or complex triggers based on code
address, direct address, opcode value, opcode class or immediate operand. Complex breakpoints can be ANDed and
ORed together. Trace information consists of address bus
values, opcodes and user selectable probe clips status (external event lines). The trace buffer can be viewed as raw
hex or as disassembled instructions. The probe clip bit values can be displayed in binary, hex or digital waveform formats.
During single-step operation the dynamically annotated
code feature displays the contents of all accessed (read
and write) memory locations and registers, as well as flowof-control direction change markers next to each instruction
executed.
The iceMASTER's performance analyzer offers a resolution
of better than 6 IJ-s. The user can easily monitor the time
spent executing specific portions of code and find "hot
spots" or "dead code". Up to 15 independent memory areas based on code address or label ranges can be defined.
Analysis results can be viewed in bar graph format or as
actual frequency count.
Emulator memory operations for program memory include
single line assembler, disassembler, view, change and write
to file. Data memory operations include fill, move, compare,
dump to file, examine and modify. The contents of any
memory space can be directly viewed and modified from the
corresponding window.

The ice MASTER connects easily to a PC® via the standard
COMM port and its 115.2 kBaud serial link keeps typical
program download time to under 3 seconds.
The following tables list the emulator and probe cards order~
ing information.

Probe Card Ordering Information
Part Number
MHW-884CG28D5PC

Package

Voltage
Range

Emulates

28 DIP

4.5V-5.5V COP884CG

MHW-884CG28DWPC 28 DIP

2.5V-6.0V COP884CG

MHW-888CG40D5PC

40 DIP

4.5V-5.5V COP888CG

MHW-888CG40DWPC 40 DIP

2.5V-6.0V COP888CG

MWH-888CG44D5PC

44 PLCC 4.5V-5.5V COP888CG

MHW-888CG44DWPC 44 PLCC 2.5V-6.0V COP888CG

Description

Manual

COP8-DEV-IBMA COP8 Assemblerl
424410632-001
LinkerlLibrarian for
IBM®, PC-/XT®, AT®
or compatible.

Emulator Ordering Information
Part Number

Description

IM-COP8/400/1:j:

MetaLink base unit in-circuit emulator for all COP8 devices, symbolic debugger
software and RS232 serial interface cable, with 11 OV @ 60 Hz Power Supply.

IM-COP8/400/2:j:

MetaLink base unit in-circuit emulator for all COP8 devices, symbolic debugger
software and RS32 serial interface cable, with 220V @ 50 Hz Power Supply.

DM-COP8/888EG:j:

MetaLink ice MASTER Debug Module. This is the low cost version of the MetaLink
ice MASTER. Firmware Ver. 6.07.

:!:These parts include National's COP8 Assembler/Linker/Librarian Package (COP8-DEV-IBMA).

1-308

Current Version

HOST SOFTWARE:
VER. 3.3 REV.5,
Model File Rev 3.050.

o
o

Development Support (Continued)

"'D

SINGLE CHIP EMULATOR DEVICE

PROGRAMMING SUPPORT

The COP8 family is fully supported by One-Time Programmable (OTP) emulators. For more detailed information refer
to the emulation device specific datasheets and the single
chip emulator selection table below.

Programming of the single chip emulator devices is supported by different sources. The following programmers are certified for programming the One-Time Programmable (OTP)
devices:

U.S. Phone
Number

Europe Phone.
Number

MetaLink- .
Debug Module

(602) 926-0797

Germany:
+49-8141-1030

Hong Kong:
+852-7371800

XeltekSuperpro

(408) 745-7974

Germany: + 49
2041-684758

Singapore:
+ 65-276-6433

BP MicrosystemsTurpro

(800) 225-2102

Germany: + 49
2041-684758

Hong Kong:
+852-3880629

Data I/O-Unisite
-System 29
-System 39

(800) 322-8246

Europe:
+ 31-20-622866
Germany:
+ 49-89-858020

Japan:
+ 81-33-4326991

Abcom-COP8
Programmer
System GeneralTurpro-1-FX
-APRO

oG)

......
o

"'D

CO
CO
CO

EPROM Programmer Information
Manufacturer
and Product

CO
CO

Asia Phone
Number

oG)

Europe: + 49-89
808707
(408) 263-6667

Switzerland:
+41-31
921-7844

Taiwan:
+ 886-2-9173005

The COP8788EG/COP8784EG can be used to emulate the COP8788CG/COP8784CG.
Single Chip Emulator Ordering Information
Clock Option

P;tck;t!!p.

F.mul~t~s

COP8788EGV-X
COP8788EGV-R*

Crystal

44 PLCC

COP888EG

COP8788EGN-X
COP8788EGN-R*

Crystal

40DIP

COP888EG

COP8784EGN-X
COP8784EGN-R*

Crystal

28DIP

COP884EG

COP8784EGWM-X*
COP8784EGWM-R*

Crystal

28S0

COP884EG

Device Number

RIC
RIC
RIC
RIC

·Check with the local sales office about the availability.

1-309

CJ
oco
co
co
D.

o
......
CJ

o
~

co
co

o
o

Development Support (Continued)
DIAL-A-HELPER

If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.

Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Bulletin Board Information system.

ORDER PIN: MOLE-DIAL-A-HLP

INFORMATION SYSTEM

Information System Package contains:
Dial-A-Helper Users Manual
Public Domain Communications Software

The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities could be found. The minimum requirement for accessing the Dial-A-Helper is a Hayes compatible
modem.
Voice:

FACTORY APPLICATIONS SUPPORT
Dial-A-Helper also provides immediate factor applications
support. If a user has questions, he can leave messages on
our electronic bulletin board, which we will respond to.

(800) 272-9959

Modem: Canada/U.S.: (800) NSC-MICRO
(800) 672-6427
Baud:

14.4 k

Set-up:

Length:

8-Bit

Parity:

None

Stop Bit: 1
Operation: 24 Hrs., 7 Days

1-310

IfI

o-a
co
co
co

National Semiconductor

"......o

COP888EK/COP884EK
Single-Chip microCMOS Microcontrollers

o-a
co
co
~

General Description
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconductor's M2CMOSTM process technology. The COP888EKI
COP884EK is a member of this expandable 8-bit core processor family of micro controllers.
(Continued)

II Two 8-bit Register Indirect Data Memory Pointers
II

Features
£II Low cost 8-bit microcontroller

.. Fully static CMOS, with low current drain
a Two power saving modes: HALT and IDLE
a 1 /-Ls instruction cycle time
tI 8k bytes on-board ROM
tI 256 bytes on-board RAM
tI Single supply operation: 2.5V-6V
tI Analog function block with
- Analog comparator with seven input multiplexor
- Constant current source and VCC/2 reference
tI MICROWIRE/PLUSTM serial I/O
EI WATCHDOGTM and Clock Monitor logic
III Idle Timer
tI Multi-Input Wakeup (MIWU) with optional interrupts (8)
tI Three 16-bit timers, each with two 16-bit registers supporting:
- Processor Independent PWM mode
- External Event counter mode
- Input Capture mode
a 8-bit Stack Pointer SP (stack in RAM)

II
II

a
II

II
II

..
•

(B and X)
Twelve mUlti-source vectored interrupts servicing
- External Interrupt
- Idle Timer TO
- Three Timers (Each with 2 Interrupts)
- MICROWIRE/PLUS
- Multi-Input Wake Up
- Software Trap
- Default VIS
Versatile instruction set
True bit manipulation
Memory mapped 1/0
BCD arithmetic instructions
Package:
- 44 PLCC with 39 1/0 pins
- 40 N with 35 1/0 pins
- 28 SO or 28 N, each with 23 lID pins
Software selectable I/O options
- TRI-STATE® Output
- Push-Pull Output
- Weak Pull Up Input
- High Impedance Input
Schmitt trigger inputs on ports G and L
Quiet design (low radiated emissions)
Temperature range: -40°C to +85°C
Single chip emulation devices
Real time emulation and full program debug offered by
MetaLink's Development Systems

Block Diagram

II
CPU REGISTERS

TL/DD/12094-1

FIGURE 1. Block Diagram

1-311

"'I::J'

co
co

co
co
co

General Description

(Continued)

They are fully static parts, fabricated using double-metal silicon gate microCMOS technology. Features include an 8-bit
memory mapped architecture, MICROWIRE/PLUS serial
I/O, three 16-bit timer/counters supporting three modes
(Processor Independent PWM generation, External Event
counter, and Input Capture mode capabilities), one analog
comparator with seven input multiplexor, and two power
saving modes (HALT and IDLE), both with a multi-sourced
wakeup/interrupt capability. This multi-sourced interrupt ca-

pability may also be used independent of the HALT or IDLE
modes. Each I/O pin has software selectable configurations. The devices operate over a voltage range of 2.5V to
6V. High throughput is achieved with an efficient, regular
instruction set operating at a maximum of 1 J-Ls per instruction rate.
Low radiated emissions are achieved by gradual turn-on
output drivers and internal Icc filters on the chip logic and
crystal oscillator.

Connectio ll Diagrams
Plastic Chip Carrier

Dual-In-Llne Package
C2

1 44 43 42 41 40

CKI

Vee

RESET

GNO

44 pin
PLCC

18 19 20 21 22 23 24 25 26 27 28

TLlDD/12094-2

Top View
Order Number COP888EK-XXX/V
See NS Plastic Chip Package Number V44A

CKI

RESET

Vee

GNO

40 pin
DIP

TL/DD/12094-3

Top View
Order Number COP888EK-XXX/N
See NS Molded Package Number N40A
Dual-In-Line Package
G4

GO
RESET
GNO
03

28 pin
0IP/SO

02
01

TL/DD/12094-4

Top View
Order Number COP884EK-XXX/WM or COP884EK-XXX/N
See NS Molded Package Number M28B or N28A
FIGURE 2. Connection Diagrams

1-312

Connection Diagrams (Continued)

'lJ

Q)
Q)
Q)

Pinouts for 28-, 40- and 44-Pln Packages
Type

Port

LO
L1

L2
L3
L4
L5
L6
L7
GO
G1
G2
G3
G4
G5
G6
G7

Alt. Fun

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU

1/0

INT

AIt.Fun

T2A
T2B
T3A
T3B

WOOUT
1/0
1/0
1/0
1/0

I
I/CKO

T1B
T1A
SO
SK
SI
HALT Restart

28-Pln
Pack.

40-Pln
Pack.

44·Pln
Pack.

11
12
13
14
15
16
18

17
18
19
20
21
22
23
24

17
18
19
20
25
26
27
28

25
26
27
28
1
2
3
4

35
36
37
38
3
4
5
6

39
40
41
42
3
4
5
6

19
20
21
22

25
26
27
28

29
30
31
32

7
8

9
10

11
12

13
14
16

13
14
15
16

DO
01
02
03

0
0
0
0

10
11

I
I

12
13

I
I

COMPIN1 +
COMPIN-/Current
Source Out
COMPINO+
COMPOUT/COMPIN2+

14
IS
16
17

I
I
I
I

COMPIN3+
COMPIN4+
COMPINS+
COM POUT

04
05
06
07

0
0
0
0

29
30
31
32

33
34
35
36

CO
C1
C2
C3
C4
CS
C6
C7

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

39
40
1
2

43
44
1
2
21
22
23
24

8
33
7
34

Vee

6
23
5
24

GNO
CKI
RESET

1·313

37
7

'lJ

Q)
Q)

0I:loo

w
~

co
co

D..

.......
~

w
co
co
co

Absolute Maximum Ratings
Total Current out of GNO Pin (Sink)
110mA
- 65°C to + 140·C
Storage Temperature Range
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
7V
Voltage at Any Pin
-0.3V to Vee +0.3V
100mA
Total Current into Vee Pin (Source)

D..

o
o

DC Electrical Characteristics 888EK: -40·C ~ TA ~
Parameter

Conditions

Min

Typ

2.5

Operating Voltage
Power Supply Ripple (Note 1)

Peak-to-Peak

Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz
CKI = 4MHz
CKI = 1 MHz

Vee
Vee
Vee
Vee

HALT Current (Note 3)

+ 85·C unless otherwise specified

IDLE Current
CKI = 10 MHz
CKI = 4 MHz
CKI = 1 MHz

6V, tc =
6V, tc =
= 4.0V, tc
= 4.0V, tc

1 J.Ls
2.5 J.Ls
= 2.5 J.Ls
= 10 J.Ls
<5
<3

Vee = 6V, CKI = 0 MHz
Vee = 4.0V, CKI = 0 MHz
Vee = 6V, tc = 1 J.Ls
Vee = 6V, tc = 2.5 J.Ls
Vee = 4.0V, tc = 10 J.Ls

Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low

Max

Units

0.1 Vee

12.5
5.5
2.5
1.4

mA
mA
mA
mA

10
6

J.LA
J.LA

3.5
2.5
0.7

mA
mA
mA

0.2 Vee

V
V

0.2 Vee

V
V

0.2 Vee

V
V

0.8 Vee

0.7 Vee

Hi-Z Input Leakage

Vee = 6V

-2

J.LA

Input Pullup Current

Vee = 6V, VIN = OV

-40

-250

J.LA

0.35 Vee

G and L Port Input Hysteresis
Output Current Levels
o Outputs
Source
Sink
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage

4V, VOH = 3.3V
2.5V, VOH = 1.8V
= 4V, VOL = 1V
= 2.5V, VOL = O.4V

-0.4
-0.2
10
2.0

4V, VOH = 2.7V
2.5V, VOH = 1.8V
4V, VOH = 3.3V
2.5V, VOH = 1.8V
4V, VOL = O.4V
2.5V, VOL = O.4V

-10
-2.5
-0.4
-0.2
1.6
0.7

-100
-33

J.LA
J.LA
mA
mA
rnA
mA

-2

J.LA

Vee
Vee
Vee
Vee

Vee
Vee
Vee
Vee
Vee
Vee

=
=
=
=
=

Vee = 6.0V

Note 1: Rate

mA
mA
mA
mA

of voltage change must be less then 0.5 Vlms.
Note 2: Supply current is measured after running 2000 cycles with a square wave OSCillator, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of 100 HALT is done with device neither sourcing or
sinking current; with L, C, and GO-G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to Vee;
clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in
crystal clock mode.
1-314

DC Electrical Characteristics 888EK:
Parameter

-40°C

s::

Conditions

TA s::

o"0

+ 85°C unless otherwise specified (Continued)

Min

Typ

Allowable Sink/Source
Current per Pin
D Outputs (Sink)
All others

Max

Units

15
3

mA
mA

± 100

C)
C)
C)

o"
""
o
"0
C)
C)

-Iloo

Maximum Input Current
without Latchup (Note 4)

TA = 25°C

RAM Retention Voltage, Vr

500 ns Rise
and Fall Time (Min)

Input Capacitance
Load Capacitance on D2

1000

AC Electrical Characteristics 888EK: -40°C s:: TA s:: + 85°C unless otherwise specified
Parameter
Instruction Cycle Time (td
Crystal, Resonator,
R/C Oscillator

Conditions

Min

4V s:: Vee s:: 6V
2.5V s:: Vee < 4V
4V s:: Vee s:: 6V
2.5V s:: Vee < 4V

1
2.5
3
7.5

4V s:: Vee s:: 6V
2.5V s:: Vee < 4V
4V s:: Vee s:: 6V
2.5V s:: Vee < 4V

200
500
60
150

Typ

Max

Units

DC
DC
DC
DC

,."s
,."s
,."s
,."s

Inputs
tSETUP
tHOLD
Output Propagation Delay (Note 5)
tp01, tpDO
SO,SK
All Others

ns
ns
ns
ns

RL = 2.2k, CL = 100 pF
4V s:: Vee s:: 6V
2.5V s:: Vee < 4V
4V s:: Vee s:: 6V
2.5V ~ Vee < 4V

MICROWIRETM Setup Time (tUWS) (Note 5)
MICROWIRE Hold Time (tUWH) (Note 5)
MICROWIRE Output Propagation Delay (tuPO)

0.7
1.75
1
2.5
20
56
220

,."s
,."s
,."s
,.,,~

ns
ns
ns

Input Pulse Width (Note 6)
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

1
1
1
1

tc
tc
tc
tc

Reset Pulse Width

,."s

= Instruction cycle time
Note 4: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than Vee and the pins will have sink current to
Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vecl. The effective resistance to Vee is 7500
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltages In excess of 14V will cause damage to
the pins. This warning excludes ESO transients.
Note 5: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 6: Parameter characterized but not tested.

1-315

W
"'I:t
co
co

Comparator AC and DC Characteristics Vee =

a..

......
~
w
co
co
co

a..

o
o

Conditions

Parameter
Input Offset Voltage

O.4V

< VIN < Vee

5V, -40·C:5: TA:5: +85·C
"

Min

- 1.5V

Input Common Mode Voltage Range (Note 7)

Units

Vee- 1.5
300k

4.0V

< Vee < 6.0V

DC Supply Current for
Comparator (When Enabled)

Vee

= 6.0V

DC Supply Current for
Vee/2 Reference (When Enabled)

Vee

= 6.0V

DC Supply Current for
Constant Current Source (When Enabled)

Vee

= 6.0V

< Vee < 6.0V

Constant Current Source

4.0V

Current Source Variation

4.0V < Vee < 6.0V
Temp = Constant

0.5 Vee - 0.04

0.5 Vee

100 mV Overdrive,
100 pF Load

0.5 Vee + 0.04

80
200

V
V/v

250

1.5

Current Source Enable Time
Comparator Response Time

Max

10
0.4

Voitage Gain

Vee/2 Reference

Typ

Il A
Il A
Il A

Il A

Il s

Note 7: The device is capable of operating, over a common mode voltage range of 0 to vec - 1.5V. however increased offset voltage will be observed between OV
and O.4V.

1·316

(")

Pin Descriptions

"'C

Vee and GND are the power supply pins. All Vee and GND
pins must be connected.

T28. L6 and L7 are used for the timer input functions T3A
and T38.

CKI is the clock input. This can come from an RIC generated oscillator, or a crystal oscillator (in conjunction with
CKO). See Oscillator Description section.
RESET is the master reset input. See Reset Description
section.

The Port L has the following alternate features:

The device contains three bidirectional 8-bit I/O ports (C, G
and L), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L and G),
output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also
reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O
ports.) Figure 3 shows the I/O port configurations. The
DATA and CONFIGURATION registers allow for each port
bit to be individually configured under software control as
shown below:
CONFIGURATION
Register

DATA
Register

0
1
1

1
0
1

LO
L1

MIWU
MIWU

MIWU

MIWU orT2A

MIWU orT28

Q)
Q)
Q)

'"
(")
"'C
Q)
Q)
~

MIWU orT3A
L6
L7
MIWU orT38
Port G is an 8-bit port with 5 I/O pins (GO, G2-G5), an input
pin (G6), and two dedicated output pins (G1 and G7). Pins
GO and G2-G6 all have Schmitt Triggers on their inputs. Pin
G1 serves as the dedicated WDOUT WATCHDOG output,
while pin G7 is either input or output depending on the oscillator mask option selected. With the crystal oscillator option
selected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin RIC oscillator mask option
selected, G7 serves as a general purpose input pin but is
also used to bring the device out of HALT mode with a low
to high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (GO, G2-G5) can be individually configured under software control.

Port Set-Up
Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output

PORTL is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.
The Port L supports Multi-Input Wake Up on all eight pins.
L4 and L5 are used for the timer input functions T2A and
PC!"!T L, c~ ~~:D

I
N

T
E
R
N
A

PORT 0

B
U

S
PORT I
TLlDD/12094-5

FIGURE 3. I/O Port Configurations

1-317

""=I"

co
co

o......
~

co
co
co

Pin Descriptions (Continued)

Functional Description

I
I

Config Reg.

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

CPU REGISTERS

Port G has the following alternate features:

PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)

GO INTR (External Interrupt Input)

8 is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.

G2 T18 (Timer T1 Capture Input)
G3 T1A (Timer T1 1/0)

X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.

G4 SO (MICROWIRETM Serial Data Output)
G5 SK (MICROWIRE Serial Clock)

SP is the 8-bit stack pointer, which points to the subroutinel
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.

G6 SI (MICROWIRE Serial Data Input)
Port G has the following dedicated functions:
G1 WDOUT WATCHDOG andlor Clock Monitor dedicated output

S is the 8-bit Data Segment Address Register used to extend the lower half of the address range (00 to 7F) into 256
data segments of 128 bytes each.

G7 CKO Oscillator dedicated output or general purpose
input

All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).

Port C is an 8-bit 1/0 port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated
pins will return unpredicatable values.

PROGRAM MEMORY
The program memory consists of 8192 bytes of ROM.
These bytes may hold program instructions or constant data
(data tables for the LAID instruction, jump vectors for the
JID instruction, and interrupt vectors for the VIS instruction).
The program memory is addressed by the 15-bit program
counter (PC). All interrupts in the devices vector to program
memory location OFF Hex.

DATA MEMORY

Port I is an eight-bit Hi-Z input port.
Port 10-17 are used for the analog function block.
The Port I has the following alternate features:
10

COMPIN1 + (Comparator Positive Input 1)

COMPIN- (Comparator Negative Input!Current
Source Out)
.

COMPINO+ (Comparator Positive Input 0)

COMPOUT/COMPIN2+ (Comparator
Comparator Positive Input 2»

COMPIN3 + (Comparator Positive Input 3)

COMPIN4+ (Comparator Positive Input 4)

COMPIN5+ (Comparator Positive Input 5)

COM POUT (Comparator Output)

The data memory consists of 256 bytes of RAM. Sixteen
bytes of RAM are mapped as "registers" at addresses OFO
to OFF Hex. These registers can be loaded immediately,
and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction. The memory
pointer registers X, SP, 8 and S are memory mapped into
this space at address locations OFC to OFF Hex respectively, with the other registers being available for general usage.

Output!

Port 0 is an 8-bit output port that is preset high when
RESET goes low. The user can tie two or more 0 port outputs (except 02) together in order to get a higher drive.
Note: Care must be exercised with the 02 pin operation. At RESET, the
external loads on this pin must ensure that the output voltages stay
above O.B Vee to prevent the chip from entering special modes. Also
keep the external loading on 02 to less than 1000 pF.

Note: RAM contents are undefined upon power·up.

1-318

Data Memory Segment RAM Extension
Data memory address OFF is used as a memory mapped
location for the Data Segment Address Register (S).

"'C

xxrr

The data store memory is either addressed directly by a
single byte address within the instruction, or indirectly relative to the reference of the 8, X, or SP pointers (each contains a single-byte address). This single-byte address allows
an addressing range of 256 locations from 00 to FF hex.
The upper bit of this single-byte address divides the data
store memory into two separate sections as outlined previously. With the exception of the RAM register memory from
address locations OOFO to OOFF, all RAM memory is memory mapped with the upper bit of the single-byte address being equal to zero. This allows the upper bit of the single-byte
address to determine whether or not the base address
range (from 0000 to DOFF) is extended. If this upper bit
equals one (representing address range 0080 to OOFF),
then address extension does not take place. Alternatively, if
this upper bit equals zero, then the data segment extension
register S is used to extend the base address range (from
0000 to 007F) from XXOO to XX7F, where XX represents the
8 bits from the S register. Thus the 128-byte data segment
extensions are located from addresses 0100 to 017F for
data segment 1, 0200 to 027F for data segment 2, etc., up
to FFOO to FF7F for data segment 255. The base address
range from 0000 to 007F represents data segment O.

CD
CD
CD

RAt.! REGISTERS
(16 BYTES)
INCLUDES B. X. SP, S

xxro
XXEr

m
......

o
o

TIt.!ERS, I/O, t.!W,
CNTRL, PSW,
ICNTRL, t.4IWU,
AND Ct.4PSL

"'C
CD
CD
0I:loo

XXBO
XXAr

(READS UNDEFINED
DATA)

XX80

OOU

UNUSED'

0070
006 r

01U
ON CHIP RAt.4
(128 BYTES)

ON CHIP RAt.4

01~r

(112 BYTES)

---L

...L

000 0

0100

TL/DD/12094-6

'Reads as all ones.

FIGURE 4. RAM Organization

Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports L, G and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WATCHDOG and/or Clock Monitor error
output pin. Port 0 is set high. The PC, PSW, ICNTRL,
CNTRL, T2CNTRL and T3CNTRL control registers are
cleared. The Comparator Select Register is cleared. The S
register is initialized to zero. The Multi-Input Wakeup registers WKEN and WKEDG are cleared. Wakeup register
WKPND is unknown. The !;tflck pointp-r, SP, i!; initiAli7flO to
6F Hex.

Figure 4 illustrates how the S register data memory extension is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XXOO
to XX7F. This organization allows a total of 256 data segments of 128 bytes each with an additional upper base segment of 128 bytes. Furthermore, all addressing modes are
available for all data segments. The S register must be
changed under program control to move from one data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory registers, I/O registers,
control registers, etc.) is always available regardless of the
contents of the S register, since tne upper base segment
(address range 0080 to DOFF) is independent of data segment extension.

The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k tc clock cycles. The Clock Monitor bit
being initialized high will cause a Clock Monitor error following reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G 1. This error
output will continue until 16 tc-32 tc clock cycles following
the clock frequency reaching the minimum specified value,
at which time the G 1 output will enter the TRI-STATE mode.

The instructions that utilize the stack pointer (SP) always
reference the stack as part of the base segment (Segment
D), regardless of the contents of the S register. The S register is not changed by these instructions. Consequently, the
stack (used with subroutine linkage and interrupts) is always
located in the base segment. The stack pointer will be intitialized to point at data memory location 006F as a result of
reset.
The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
112 bytes of RAM are resident from address 0000 to 006F
in the lower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at addresses OOFO to DOFF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.

The external RC network shown in Figure 5 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.

Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XXOO to XX7F) of
the lower base segment. The additional 128 bytes of RAM
are memory mapped at address locations 0100 to 017F
hex.

1-319

w
oor::r
co
co

Reset

p
0

D-

E
R

S
U

co
co
co

P
P
L
Y

D-

vee

......

TABLE B. RC Oscillator Configuration, T A = 25°C

(Continued)

:.R

COP800
RESET

:::::C

R
(kil)

C
(pF)

CKI Freq
(MHz)

Instr. Cycle
(/-I-s)

Conditions

3.3
5.6
6.8

82
100
100

2.2to 2.7
1.1 to 1.3
0.9 to 1.1

3.7 to 4.6
7.4 to 9.0
8.8 to 10.8

Vee = 5V
Vee = 5V
Vee = 5V

Note: 3k

GND

:$;

50 pF

R
:$;

:$;

200k
:$;

200 pF

TL/DD/12094-7

RC > 5

Power Supply Rise Time

Current Drain

FIGURE 5. Recommended Reset Circuit

The total current drain of the chip depends on:

Oscillator Circuits

1. Oscillator operation mode-11

2. Internal switching current-12
3. Internal leakage current-13
4. Output source current-14
5. DC current caused by external input
not at Vcc or GND-15

Figure 6 shows the Crystal and RIC oscillator diagrams.

6. Comparator DC supply current when enabled-16

CRYSTAL OSCILLATOR

7. Clock Monitor current when enabled-17

CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.

Thus the total current drain, It, is given as
It = 11

Table A shows the component values required for various
standard crystal values.
RIC OSCILLATOR

Note: Use of the RIC oscillator option will result in higher electromagnetic
emissions.

Table B shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
CKI

CKO

CKI

CKO

By selecting CKI as a single pin oscillator input, a single pin
RIC oscillator circuit can be connected to it. CKO is available as a general purpose input, and/or HALT restart input.

+ 12 + 13 + 14 +

To reduce the total current drain, each of the above components must be minimum.

12 = C

xVxf

where C = equivalent capacitance of the chip
V = operating voltage
f = CKI frequency

Control Registers
CNTRL Register (Address X'OOEE)
TL/DD/12094-9

SL1 & SLO Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)

TL/DD/12094-8

FIGURE 6. Crystal and RIC Oscillator Diagrams
TABLE A. Crystal Oscillator Configuration, TA = 25°C
R1
(kil)

R2
(Mil)

C1
(pF)

C2
(pF)

CKI Freq
(MHz)

Conditions

0
0
0

1
1
1

30
30
200

30-36
30-36
100-150

10
4
0.455

Vee = 5V
Vee = 5V
Vee = 5V

The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:

IEDG

External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)

MSEL

Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively

T1CO

Timer T1 StartlStop control in timer
modes 1 and 2
Timer T1 Underflow Interrupt Pending Flag in
timer mode 3

T1 C1

Timer T1 mode control bit

T1 C2

Timer T1 mode control bit

T1 C3

Timer T1 mode control bit

I T1C31 T1C21 T1C1 I T1CO I MSEL IIEDG I SL1 I SLO
Bit7

1-320

BitO

Control Registers

o
o

(Continued)

"'D

PSW Register (Address X/OOEF)

T2C1

Timer T2 mode control bit

The PSW register contains the following select bits:

T2C2

Timer T2 mode control bit

T2C3

Timer T2 mode control bit

GIE

Global interrupt enable (enables interrupts)

EXEN

Enable external interrupt

BUSY
EXPND

MICROWIRE/PLUS busy shifting flag
External interrupt pending

T1 ENA

Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge

Carry Flag

Half Carry Flag

I II
HC

T3ENB

I I
GIE

Timer T3 Interrupt Enable for Timer Underflow
or T3A pin

Timer T3 Start/Stop control in timer modes 1
and 2

T3C1

Timer T3 mode control bit

T3C2

Timer T3 mode control bit

T3C3

Timer T3 mode control bit

Timer T1 Interrupt Enable for T1 B Input capture
edge
Bit?

T1 PNDB Timer T1 Interrupt Pending Flag for T1 B capture edge

The device contains a very versatile set of timers (TO, T1,
T2, T3). All timers and associated autoreload/capture registers power up containing random data.

TOEN

Timer TO Interrupt Enable (Bit 12 toggle)

TOPND

Timer TO Interrupt pending

LPEN

L Port Interrupt Enable (Multi-Input W8kel plln'
terrupt)

Bit 7 could be used as a flag

Bit?

BitO

Timers

Enable MICROWIRE/PLUS interrupt

J.LWPND MICROWIRE/PLUS interrupt pending

BitO

T2CNTRL Register (Address X/~OCS)

Exit out of the Idle Mode (See Idle Mode description)
WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode
The IDLE Timer TO can generate an interrupt when the thirteenth bit toggles. This toggle is latched into the TOPND
pending flag, and will occur every 4 ms at the maximum
clock frequency (te = 1 J-ts). A control flag TOEN allows the
interrupt from the thirteenth bit of Timer TO to be enabled or
disabled. Setting TOEN will enable the interrupt, while resetting it will disable the interrupt.

The T2CNTRL register contains the following bits:
Timer T2 Interrupt Enable for T2B Input capture
edge

T2PNDB Timer T2 Interrupt Pending Flag for T2B capture edge
Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA
in mode 1, T2 Underflow in mode 2, T2A capture edge in mode 3)
T2CO

Timer T3 Interrupt Enable for T3B

Timer T3 Underflow Interrupt Pending Flag in
timer mode 3

ICNTRL Register (Address X/ODES)

T2ENA

T3PNDA Timer T3 Interrupt Pending Flag (Autoload RA
in mode 1, T3 Underflow in mode 2, T3a capture edge in mode 3)
T3CO

The ICNTRL register contains the following bits:

T2ENB

Q)
Q)

T3PNDB Timer T3 Interrupt Pending Flag for T3B pin
(T3B capture edge)

BitO
The Half-Carry bit is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and RC instructions, ADC,
SUBC, RRC and RLC instructions affect the carry and Half
Carry flags.

J.LWEN

BitO

The T3CNTRL register contains the following bits:

Bit7

T1 ENB

"oo

T3CNTRL Register (Address X/OOBS)

T3ENA

C T1 PNDA T1 ENA EXPND BUSY EXEN

.......
"'D

Bit?

T1 PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1 A capture edge in mode 3)
C

Q)
Q)
Q)

Timer T2 Start/Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3

1-321

ILl

"1:1'
CO
CO

D-

o.......
~

ILl
CO
CO
CO

D-

Timers

(Continued)

TIMER T1, TIMER T2 AND TIMER T3
The device has a set of three powerful timer/counter
blocks, T1, T2 and T3. The associated features and functioning of a timer block are described by referring to the
timer block Tx. Since the three timer blocks, T1, T2 and T3
are identical, all comments are equally applicable to any of
the three timer blocks.

TI~ER

UNDERFLOW
INTERRUPT

<4-----,

TxA

Each timer block consists of a 16-bit timer, Tx, and two
supporting 16-bit autoreload/capture registers, RxA and
RxB. Each timer block has two pins associated with it, TxA
and TxB. The pin TxA supports I/O required by the timer
block, while the pin TxB is an input to the timer block. The
powerful and flexible timer block allows the device to easily
perform all timer functions with minimal software overhead.
The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and
Input Capture mode.
The control bits TxC3, TxC2, and TxC1 allow selection of
the different modes of operation.

IC------'

TL/DD/12094-10

In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
Figure 8 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock.

TIMER
UNDERFLOW
INTERRUPT

Figure 7 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the TxA output pin. The underflows can also be programmed to generate interrupts.
Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control enable flags, TxENA and TxENB, allow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be
reloaded into the timer. Resetting the timer enable flags will
disable the associated interrupts.
Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.

<4-----.

Tx A

TL/DD/12094-11

FIGURE 8. Timer in External Event Counter Mode
Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode.
In this mode, the timer Tx is constantly running at the fixed
tc rate. The two registers, RxA and RxB, act as capture
registers. Each register acts in conjunction with a pin. The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin.

1-322

Timers

(Continued)

Q)
Q)
Q)

The timer value gets copied over into the register when. a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently.

~
.....
o
a

The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.

Q)
Q)
~

TL/DD/12094-12

FIGURE 9. Timer in Input Capture Mode
TIMER CONTROL FLAGS

The timers T1. T2 and T3 have indentical control structures.
The control bits and their functions are summarized below.
TxCO

Timer Start/Stop control in Modes 1 and 2
(Processor Independent PWM and External
Event Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)

TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag

Figure 9 shows a block diagram of the timer in Input Capture
mode.

TxENA
TxENB

Timer Interrupt Enable Flag
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
o = Timer Interrupt Disabled

TxC3
TxC2
TxC1

Timer mode control
Timer mode control
Timer mode control

1-323

UJ
~

ClO
ClO

Timers

(Continued)

The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:

a
0

Interrupt A
Source .

,Interrupt B
Source

Timer
Counts On

MODE 2 (External
Event Counter)

Timer
Underflow

Pos. TxB
Edge'

TxA
Pos.Edge

MODE 2 (External
Event Counter)

Timer
Underflow

Pos. TxB
Edge

TxA
Neg. Edge

MODE 1 (PWM)
TxA Toggle

Autoreload
RA

Autoreload
RB

MODE 1 (PWM)
No TxA Toggle

Autoreload
RA

Autoreload
RB

MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Pos.Edge

Pos. TxA
Edge or
Timer
Underflow

Pos. TxB
Edge

MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Neg. Edge

Pos. TxA
Edge or
Timer
Underflow

Neg. TxB
Edge

MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Pos. Edge

Neg.TxA
Edge or
Timer
Underflow

Pos. TxB
Edge

MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Neg. Edge

Neg.TxA
Edge or
Timer
Underflow

Neg.TxB
Edge

.......

TxC3

TxC2

TxC1

Timer Mode

ClO
ClO
ClO

Power Save Modes
The device offers the user two power save modes of operation: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscillator circuitry the WATCHDOG logic, the Clock Monitor and
timer TO are active but all other microcontroller activities are
stopped. in either mode, all on-board RAM, registers, I/O
states, and timers (with the exception of TO) are unaltered.

figuration (since CKO becomes a dedicated output), and so
may be used with an RC clock configuration. The third
method of exiting the HALT mode is by pulling the RESET
pin low.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the tc instruction cycle clock. The tc
clock is derived by dividing the oscillator clock down by a
factor of 10. The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE timer is clocked only
when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger specifications. This Schmitt trigger
is not part of the oscillator closed loop. The startup timeout
from the IDLE timer enables the clock signals to be routed
to the rest of the chip.

HALT MODE
The device can be placed in the HALT mode by writing a
"1" to the HALT flag (G7 data bit). All microcontroller activities, including the clock and timers, are stopped. The
WATCHDOG logic is disabled during the HALT mode. However, the clock monitor circuitry if enabled remains active
and will cause the WATCHDOG output pin (WDOUn to go
low. If the HALT mode is used and the user does not want
to activate the WDOUT pin, the Clock Monitor should be
disabled after the device comes out of reset (resetting the
Clock Monitor control bit with the first write to the WDSVR
register). In the HALT mode, the power requirements of the
device are minimal and the applied voltage (Ved may be
decreased to Vr (Vr = 2.0V) without altering the state of the
machine.

1-324

a""C

Power Save Modes (Continued)
This toggle condition of the thirteenth bit of the IDLE Timer
TO is latched into the TOPND pending flag.

The device is placed in the IDLE mode by writing a "1" to
the IDLE flag (G6 data bit). In this mode, all activities, except
the associated on-board oscillator circuitry, the WATCHDOG logic, the clock monitor and the IDLE Timer TO, are
stopped.
As with the HALT mode, the device can be returned to nor- .
mal operation with a reset, or with a Multi-Input Wakeup
from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the thirteenth
bit (representing 4.096 ms at internal clock frequency of
1 MHz, tc = 1 !-'-s) of the IDLE Timer toggles.

The user can enter the IDLE mode with the Timer TO interrupt enabled. In this case, when the TOPND bit gets set, the
device will first execute the Timer TO interrupt service routine and then return to the instruction following the "Enter
Idle Mode" instruction.
Alternatively, the user can enter the IDLE mode with the
IDLE Timer TO interrupt disabled. In this case,. the device
will resume normal operation with the instruction immediately following the "Enter IDLE Mode" instruction.

co
co
co

......

a""C
co
co
0l:Io

Multi-Input Wakeup
The Multi-Input Wakeup feature is ued to return (wakeup)
the device from either the HALT or IDLE modes. Alternately
Multi-Input Wakeup/Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts..
Figure 10 shows the Multi-Input Wakeup logic.

INTERNAL DATA BUS

lc~~1

1"':7'1

L!.!.J

•
•
•
•
•
•

•
•
•
•

WKEDG

WKPND

•

CKO

CHIP CLOCK

TL/00/12094-13

FIGURE 10. Multi-Input Wake Up Logic

1-325

w
~

co
co

a..

.......
~

co
co
co

a..

Multi-Input Wakeup

(Continued)
WKEN, WKPND and WKEDG are all read/write registers,
and are cleared at reset.

PORT L INTERRUPTS
Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into
the same service subroutine.
The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to
be individually enabled or disabled. The register WKEDG
specifies the trigger condition to be either a positive or a
negative edge. Finally, the register WKPND latches in the
pending trigger conditions.
The GIE (Global Interrupt Enable) bit enables the interrupt
function.
A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag is not
needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If
he elects to disable the interrupt, then the device will restart
execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or
IDLE modes. In the other case, the device will first execute
the interrupt service routine and then revert to normal oper.
ation.

The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an 8bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.
An example may serve to clarify this procedure. Suppose
we wish to change the edge select from positive (low going
high) to negative (high going low) for L Port bit 5, where bit 5
has previously been enabled for an input interrupt. The program would be as follows:

RBIT
SBIT
RBIT
SBIT

5,
5,
5,
5,

WKEN
WKEDG
WKPND
WKEN

If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeupllnterrupt, a safety procedure should also be followed to avoid inherited
pseudo wakeup conditions. After the selected L port bits
have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired
edge selects, followed by the associated WKPND bits being
cleared.
This same procedure should be used following reset, since
the L port inputs are left floating as a result of reset.
The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since WKPND is a pending
register for the occurrence of selected wakeup conditions,
the device will not enter the HALT mode if any Wakeup bit is
both enabled and pending. Consequently, the user has the
responsibility of clearing the pending flags before attempting to enter the HALT mode.

1-326

~---------------------------------------------------------------------.o

o"tJ

Analog Function Block

(X)
(X)
(X)

Vee

~ r~' :~Np: :) ~

CMPNEG

o""tJ
o

(X)
(X)

0l:Io

TO TIMER T28

12
13

14
15
16

17 or 13
TLlDD/12094-14

FIGURE 11. COP888EK Analog Function Block
This device contains an analog function block with the intent to provide a function which allows for single slope, low
cost, AID conversion of up to 6 channels.

CMPT28

CMPSL REGISTER (ADDRESS X'OOB7)

Selects the timer T2B input to be driven
directly by the comparator output. If the
comparator is disabled (CMPEN = 0), this
function is disabled, i.e., the T2B input is
connected to Port L5.

The CMPSL register contains the following bits:
CMPNEG

Will drive 11 to a low level. This bit can be
used to discharge an external capacitor.
This bit is disabled if the comparator is not
~~::.:!~d (C~.~PEN - O).

CMPEN

Enable the comparator ("1" = enable).

CSEN

Enables the internal constant current
source. This current source provides a
nominal 20 J1-A constant current at the 11
pin. This current can be used to ensure a
linear charging rate on an external capacitor. This bit has no affect and the current
source is disabled if the comparator is not
enabled (CMPEN = 0);

CMPOE

The Comoarator Select Reni!;ter i!; r-leMP(j on RESET (the
comparator is disabled). To -save power the program should
also disable the comparator before the J-LC enters the
HALT/IDLE modes. Disabling the comparator will turn off
the constant current source and the Vcc/2 reference, disconnect the comparator output from the T2B input and pin
13 or 17 and remove the low on 11 caused by CMPNEG.
It is often useful for the user's program to read the result of
a comparator operation. Since 11 is always selected to be
COMPIN- when the comparator is enabled (CMPEN = 1),
the comparator output can be read internally by reading bit
1 (CMPRD) of register PORTI (RAM address 0 x 07).

Enables the comparator output to either
pin 13 or pin 17 ("1" = enable) depending
on the value of CMPISELO/1 /2.

The following table lists the comparator inputs and outputs
vs. tlie value of the CMPISELO/1 /2 bits. The output will only
be driven if the CMPOE bit is set to 1.

CMPISELO/1/2 Will select one of seven possible sources
(IO/l2/13/14/15/16/internal reference) as a
positive input to the comparator (see Table I for more information.)

1-327

Analog Function Block (Continued)

TABLE I. Comparator Input Selection

Control Bit

o
.......
~

CMPISEL2

co
co
co

D-

Comparator Input Source

Comparator
Output

CMPISEL1

CMPISELO

VCC/2 Ref.

Neg. Input

Reset

ranking and the memory locations reserved for the interrupt
vector for each source.

The state of the Comparator Block immediately after
RESET is as follows:

Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software
interrupt are maskable. Each of the maskable interrupts
have an Enable bit and a Pending bit. A maskable interrupt
is active if its associated enable and pending bits are set. If
GIE = 1 and an interrupt is active, then the processor will
be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described
in the Software Trap sub-section.

1. The CMPSL Register is set to all zeros
2. The Comparator is disabled
3. The Constant Current Source is disabled
4. CMPNEG is turned off
S. The Port I inputs are electrically isolated from the comparator
6. The T2B input is as normally selected by the T2CNTRL
Register

7. CMPISELO-CMPISEL2 are set to zero
8. All Port I inputs are selected to the default digital input
mode
The comparator outputs have the same specification as
Ports Land G except that the rise and fall times are symmetrical.

2. The address of the instruction about to be executed is
pushed into the stack.
3. The PC (Program Counter) branches to address OOFF.
This procedure takes 7 tc cycles to execute.

Interrupts
The device supports a vectored interrupt scheme. It supports a total of fourteen interrupt sources. The following table lists all the possible interrupt sources, their arbitration

SOFTWARE

Pos.lnput

--------------1

Tlt.lER Tl, T2. AND T3

EXTERNAL

t.lULTI-INPUT WAKE UP
INTERRUPT

~WIRE/pLUS

rUTURE PERIPHERAL

IDLE TIt.lER

TL/DD/12094-l5

FIGURE 12. Interrupt Block Diagram

1-328

~------------------------------------------------------------------------,

Interrupts (Continued)
Arbitration
Ranking
(1) Highest

Source

Description

Vector
Address
Hi-Low Byte

a"'C
Q)
Q)
Q)

.......

a"'C

Software

INTR Instruction

OyFE-OyFF

Reserved

for Future Use

OyFC-OyFD

Q)
Q)

External

Pin GO Edge

OyFA-OyFB

(2)
(3)

Timer TO

Underflow

OyF8-0yF9

(4)

TimerT1

T1 AlUnderflow

OyF6-0yF7

(5)

TimerT1

T1B

OyF4-0yF5

(6)

MICROWIRE/PLUS

BUSY Goes Low

OyF2-0yF3

Reserved

for Future Use

OyFO-OyF1

(7)

Reserved

OyEE-OyEF

(8)

Reserved

(9)

TimerT2

T2A1Underflow

OyEA-OyEB

(10)

TimerT2

T2B

OyE8-0yE9

(11 )

TimerT3

T3A1Underflow

OyE6-0yE7

(12)

TimerT3

T3B

OyE4-0yE5

(13)

Port LlWakeup

Port LEdge

OyE2-0yE3

(14) Lowest

Default

VIS Instr. Execution
without Any Interrupts

OyEO-OyE1

Y is VIS page,

OyEC-OyED

y #- o.

The addresses of the different interrupt service routines,
called vectors, are chosen by the user and stored in ROM in
a table starting at 01 EO (assuming that VIS is located between OOFF and 01 DF). The vectors are 15-bit wide and
therefore occupy 2 ROM locations.
VIS and the vector table must be located in the same 256bita bloc;'; (uyuu lu uyrr) tlxcept if VIS is located at the last
address of a block. In this case, the table must be in the
next block. The vector table cannot be inserted in the first
256-byte block (y =1= 0).

The vector of the maskable interrupt with the lowest rank is
located at OyEO (Hi-Order byte) and OyE1 (Lo-Order byte)
and so forth in increasing rank number. The vector of the
maskable interrupt with the highest rank is located at OyFA
(Hi-Order byte) and OyFB (Lo-Order byte).
The Software Trap has the highest rank and its vector is
located at OyFE and OyFF.
If, by accident, a VIS gets executed and no interrupt is active, then the PC (Program Counter) will branch to a vector
located at OyEO-OyE1. This vector can point to the Software Trap (ST) interrupt service routine, or to another special service routine as desired.

Figure 12 shows the Interrupt block diagram.
SOFTWARE TRAP
The Software Trap (ST) is a special kind of non-maskable
interrupt which occurs when the INTR instruction (used to
acknowledge interrupts) is fetched from ROM and placed
inside the instruction register. This may happen when the
PC is pointing beyond the available ROM address space or
when the stack is over-popped.

The VIS instruction looks at all the active interrupts at the
time it is executed and performs an indirect jump to the
beginning of the service routine of the one with the highest
rank.

1-329

::.::
w

oo::t'

co
co
D-

o
::.::
"
w

co
co
co
D-

Interrupts (Continued)

Clock Monitor

When an ST occurs, the user can re-initialize the stack
pOinter and do a recovery procedure (similar to reset, but
not necessarily containing all of the same initialization procedures) before restarting.

WATCHDOG Operation
The WATCHDOG and Clock Monitor are disabled during
reset. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG Window Select bits (bits 6,7 of the
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
WDSVR Register) enabled. Thus, a Clock Monitor error will
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, including the case where the oscillator fails to start.

The ST has the highest rank among all interrupts.
Nothing (except another ST) can Interrupt an ST being
serviced.

WATCHDOG

The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match .to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the WATCHDOG service window and match the WATCHDOG key data. Subsequent writes to the WDSVR register
will compare the value being written by the user to the
WATCHDOG service window value and the key data (bits 7
through 1) in the WDSVR Register. Table IV shows the sequence of events that can occur.

The device contains a WATCHDOG and clock monitor. The
WATCHDOG is designed to detect the user program getting
stuck in infinite loops resulting in loss of program control or
"runaway" programs. The Clock Monitor is used to detect
the absence of a clock or a very slow clock below a specified rate on the CKI pin.
The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.
ServiCing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table II shows the WDSVR register.

The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 and 6 of the WDSVR register allow
the user to pick an upper limit of the service window.
Table III shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flexibility in choosing the WATCHDOG service window prevents
any undue burden on the user software.

Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5bit Key Data field. The key data is fixed at 01100. Bit 0 of the
WDSVR Register is the Clock Monitor Select bit.
TABLE II. WATCHDOG Service Register (WDSVR)
Window
Select

Key Data

I1 I

1 101 0

The WATCHDOG service window will restart when the
WDOUT pin goes high. It is recommended that the user tie
the WDOUT pin back to Vee through a resistor in order to
pull WDOUT high.

Clock
Monitor

TABLE III. WATCHDOG Service Window Select
WDSVR
Blt7

WDSVR
BitS

0
0
1
1

0
1
0
1

The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock .frequency has reached the minimum specified value, after which the G1 output will enter the high impedance TRI-STATE mode following 16 tc-32 tcclock cycles. The Clock Monitor generates a continual Clock Monitor error if the oscillator fails to start, or fails to reach the
minimum specified frequency. The specification for the
Clock Monitor is as follows:

Service Window
(Lower-Upper Limits)
2k-Bk tc Cycles
2k-16k tc Cycles
2k-32k tc Cycles
2k-64k tc Cycles

1-330

1/tc

> 10kHz-No clock rejection.

1/tc

< 10Hz-Guaranteed clock rejection.

(")

WATCHDOG Operation

(Continued)

"'tJ

WATCHDOG AND CLOCK MONITOR SUMMARY

• With the single-pin R/C oscillator mask option selected
and the CLKDLY bit reset, the WATCHDOG service window will resume following HALT mode from where it left
off before entering the HALT mode.

The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted:
• Both the WATCHDOG and CLOCK MONITOR detector
circuits are inhibited during RESET.

• With the crystal oscillator mask option selected, or with
the Single-pin R/C oscillator mask option selected and
the CLKDLY bit set, the WATCHDOG service window will
be set to its selected value from WDSVR following HALT.
Consequently, the WATCHDOG should not be serviced
for at least 2048 instruction cycles following HALT, but
must be serviced within the selected window to avoid a
WATCHDOG error.

Ol
Ol
Ol

........

(')

o"'tJ
Ol
Ol
~

• Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG errors.
• The correct key data value cannot be read from the
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all O's.

• A hardware WATCHDOG service occurs just as the device exits the IDLE mode. Consequently, the WATCHDOG should not be serviced for at least 2048 instruction
cycles following IDLE, but must be serviced within the
selected window to avoid a WATCHDOG error.

• The WATCHDOG detector circuit is inhibited during both
the HALT and IDLE modes.

• The CLOCK MONITOR detector circuit is active during
both the HALT and IDLE modes. Consequently, the device inadvertently entering the HALT mode will be detected as a CLOCK MONITOR error (provided that the
CLOCK MONITOR enable option has been selected by
the program).

1-331

UJ
~

co
co

o
o......
~

co
co
co

o
o

Detection of Illegal Conditions

MICROWIRE/PLUS

The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc .
Reading of undefined ROM gets zeros. The opcode for software interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt,
thus signaling that an illegal condition has occurred.
The subroutine stack grows down for each call Qump to
subroutine), interrupt, or PUSH, and grows up for each return or POP. The stack pointer is initialized to RAM location
06F Hex during reset. Consequently, if there are more returns than calls, the stack pointer will point to addresses
070 and 071 Hex (which are undefined RAM). Undefined
RAM from addresses 070 to 07F (Segment 0), 140 to 17F
(Segment 1), and all other segments (Le., Segments 2 ...
etc.) is read as all1's, which in turn will cause the program
to return to address 7FFF Hex. This is an undefined ROM
location and the instruction fetched (all O's) from this location will generate a software interrupt signaling an illegal
condition.

MICROWIRE/PlUS is .a serial synchronous communications interface. The MICROWIRE/PlUS capability enables
the device to interface with any of National Semiconductor's
MICROWIRE peripherals (Le. AID converters, display drivers, E2PROMs etc.) and with other microcontrollers which
support the MICROWIRE interface. It consists of an 8-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK). Figure 13
shows a block diagram of the MICROWIRE/PlUS logic.

1 - - - - - - + INTERRUPT
~~--~~------'SO

~-t1.~~~j-----SI

Thus, the chip can detect the following illegal conditions:
a. Executing from undefined ROM
b. Over "POP"ing the stack by having more returns than
calls.
When the software interrupt occurs, the user can re-initialize
the stack pointer' and do a recovery procedure before restarting (this recovery program is probably similar to that
following reset, but might not contain the same program
initialization procedures). The recovery program should reset the software interrupt pending bit using the RPND instruction.

TL/DD/12094-16

FIGURE 13. MICROWIRE/PLUS Block Diagram

The shift clock can be selected from either an internal
source or an externai source. Operating the MICROWIREI
PLUS arrangement with the internal clock source is called
the Master mode of operation. Similarly, operating the
MICROWIRE/PlUS arrangement with an external shift
clock is called the Slave mode of operation.
.
The CNTRl register is used to configure and control the
MICROWIRE/PlUS mode. To use the MICROWIRE/PlUS,
the MSEl bit in the CNTRl register is set to one. In the
master mode, the SK clock rate is selected by the two bits,
SlO and Sl1, in the CNTRl register. Table V details the
different clock rates that may be selected.

TABLE IV. WATCHDOG Service Actions
Key
Data

Window
Data

Clock
Monitor

Action

Valid Service: Restart Service Window

Match

Don't Care

Mismatch

Don't Care

Error: Generate WATCHDOG Output

Mismatch

Don't Care

Error: Generate WATCHDOG Output

Don't Care

Mismatch

Error: Generate WATCHDOG Output

TABLE V. MICROWIRE/PLUS
Master Mode Clock Select
SL1

SLO

0
0
1

0
1
x

2 x tc

1-332

4 X tc
8 X tc

Where tc is the
instruction cycle clock

MICROWIRE/PLUS (Continued)

-a

MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MICAOWIAE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICAOWIAE/PLUS
mode either as a Master or as a Slave. Figure 14 shows
how two devices, microcontrollers and several peripherals
may be interconnected using the MICAOWIAE/PLUS arrangements.

......

Alternate SK Phase Operation

Q)
Q)

The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register.
In both the modes the SK is normally low. In the normal
mode data is shifted in on the rising edge of the SK clock
and the data is shifted out on the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK clock. In the alternate SK phase operation, data is shifted in on the falling edge of the SK clock and shifted out on
the rising edge of the SK clock.

A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICAOWIAE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alternate SK clock. The SKSEL is mapped into the G6 configuration bit. The SKSEL flag will power up in the reset condition,
selecting the normal SK signal.

Setting the BUSY flag when the input SK clock is high in the
MICAOWIAE/PLUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is
low.
MICROWIRE/PLUS Master Mode Operation

TABLE VI
This table assumes that the control flag MSEL is set.

In the MICAOWIAE/PLUS Master mode of operation the
shift clock (SK) is generated internally by the device. The
MICAOWIAE Master always initiates all data exchanges.
The MSEL bit in the eNTAL register must be set to
enable the SO and SK functions onto the G Port. The SO
and SK pins must also be selected as outputs by setting
appropriate bits in the Port G configuration register. Table VI
summarizes the bit settings required for Master mode of
operation.

G4(SO)
G5 (SK)
Config. Bit Config. Bit
1

MICROWIRE/PLUS Slave Mode Operation
In the MICAOWIAE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTAL reqister enables the SO and SK flJnr.tinn~
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bits in the Port G configuration register. Table VI summarizes the settings required to enter the
Slave mode of operation.

, /5

CHIP SELECT LINES

...

...-:LCS

8 - 81T
A/D
COP43X

I/O
LINES

..IlL

......
..,..

EEPROM

COP8
(MASTER)
DO SK 01

SI
SO

! t
I

DO SK 01

G4
Fun.
SO

G5
Fun.

Operation

Int. MICAOWIAE/PLUS
SK Master

TAIInt. MICAOWIAE/PLUS
STATE SK Master
SO

Ext. MICAOWIAE/PLUS
SK Slave

TAI- Ext. MICAOWIAE/PLUS
STATE SK Slave

r----

...

LCD
DISPLAY
DRIVER
COP472

VF
DISPLAY
DRIVER

SK 01

r lI

I/O
LINES
COP8
(SLAVE)

SK 01

l.d
I'

.....

.".

SO
SI
SK
TL/OO/12094-17

FIGURE 14. MICROWIRE/PLUS Application

1-333

Q)
Q)
Q)

o-a
~

Memory Map

All RAM, ports and registers (except A and PC) are mapped into data memory address space.

........

Address
S/ADDREG

w
co
co
co

0000 to 006F

On-Chip RAM bytes (112 bytes)

0070 to 007F

Unused RAM Address Space (Reads
As All Ones)
Unused RAM Address Space (Reads
Undefined Data)

D..

xx80to xxAF
xxBO
XXB1
xxB2
xxB3
xxB4
xxB5
xxB6
xxB7
xxB8-xxBF
xxCO
xxC1
xxC2
xxC3
xxC4
xxC5
xxC6
xxC7
xxC8
xxC9
xxCA
xxCB
xxCC
xxCDto xxCF

Address

Contents

S/ADD REG

xxDO
xxD1
xxD2
xxD3
xxD4
xxD5
xxD6
xxD7
xxD8
xxD9
xxDA
xxDB
xxDC
xxDDto OF

Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port 0
Reserved

xxEO to xxE5
xxE6

xxEE
xxEF

Reserved
Timer T1 Autoload Register T1 RB
Lower Byte
Timer T1 Autoload Register T1 RB
Upper Byte
ICNTRL Register
MICROWIRE/PLUS Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1 RA
Lower Byte
Timer T1 Autoload Register T1 RA
Upper Byte
CNTRL Control Register
PSW Register

xxFO to FB
xxFC
xxFD
xxFE
xxFF

On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
S Register

0100-017F

On-Chip 128 RAM Bytes

xxE7

Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA
Lower Byte
Timer T2 Autoload Register T2RA
Upper Byte
Timer T2 Autoload Register T2RB
Lower Byte
Timer T2 Autoload Register T2RB
Upper Byte
Timer T2 Control Register
WATCHDOG Service Register
(Reg:WDSVR)
MIWU Edge Select Register
(Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register
(Reg:WKPND)
Reserved
Reserved
Reserved

Contents

xxE8
xxE9
xxEA
xxEB
xxEC
xxED

Reading memory locations 0070H-007FH (Segment 0) will return all ones.
Reading unused memory locations 0080H-00AFH (Segment 0) will return
undefined data. Reading memory locations from other unused Segments
(i.e., Segment 2, Segment 3, ... etc.) will return all ones.

1-334

Addressing Modes

-a

There are ten addressing modes, six for operand addressing and four for transfer of control.
OPERAND ADDRESSING MODES
Register Indirect
This is the "normal" addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.
Register Indirect (with auto post Increment or
decrement of pointer)
This addressing mode is used with the LD and X instructions. The operand is the data memory addressed,by the B
pointer or X pointer. This is a register indirect mode that
automatically post increments or decre'ments the B or X register after executing the instruction.

0)
0)
0)

"oo

Note: The VIS is a special case of the Indirect Transfer of Control addressIng mode, where the double byte vector associated with the interrupt
Is transferred from adjacent addresses in the program memory into
the program counter (PC) in order to jump to the associated interrupt
service routine.

.....
-a

0)
0)
~

Instruction Set
Register and Symbol Definition

Direct
The instruction contains an a-bit address field that directly
points to the data memory for the operand.

Registers
A
B

Immediate
The instruction contains an a-bit immediate field as the operand.

X
SP
PC
PU
PL
C
HC
GIE

Short Immediate
This addressing mode is used with the Load B Immediate
instruction. The instruction contains a 4-bit immediate field
as the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower a bits of PC) for accessing a data operand from the
program memory.

VU
VL

a-Bit Accumulator Register
a-Bit Address Register
a-Bit Address Register
a-Bit Stack Pointer Register
15-Bit Program Counter Register
Upper 7 Bits of PC
Lower a Bits of PC
1 Bit of PSW Register for Carry
1 Bit of PSW Register for Half Carry
1 Bit of PSW Register for Global
Interrupt Enable
Interrupt Vector Upper Byte
Interrupt Vector Lower Byte

TRANSFER OF CONTROL ADDRESSING MODES
Relative
Symbols

This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
program location. JP has a range from -31 to +32 to allow
a 1-byte relative jump (JP + 1 is implemented by a NOP
instruction). There are no "pages" when using JP, since all
15 bits of PC are used.

[B)
[X]
MD
Mem
Meml

Imm
Reg

Absolute Long

Bit
-+-

This mode is used with the JMPL and JSRL, instructions,
with the instruction field of 15 bits replacing the entire 15
bits of the program counter (PC). This allows jumping to any
location in the current 4k program memory space.

Memory Indirectly Addressed by B
Register
Memory Indirectly Addressed by X
Register
Direct Addressed Memory
Direct Addressed Memory or [B)
Direct Addressed Memory or [B) or
Immediate Data
a-Bit Immediate Data
Register Memory: Addresses FO to FF
(Includes B, X and SP)
Bit Number (0 to 7)
Loaded with
Exchanged with

1-335

LIJ

Instruction Set (Continued)

INSTRUCTION SET

A -E- A + Meml
A -E- A + Meml + C, C -E- Carry
HC -E- Half Carry
A -E- A - Meml + C, C -E- Carry
HC -E- Half Carry
A -E- A and Meml
Skip next if (A and Imm) = 0
A -E- A or Meml
A -E- A xor Meml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A =1= Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of 8 =1= Imm
Reg -E- Reg - 1, Skip if Reg = 0
1 to bit, Mem (bit = 0 to 7 immediate)
Oto bit, Mem
If bit in A or Mem is true do next instruction
Reset Software Interrupt Pending Flag

ADD
ADC

A,Meml
A,Meml

ADD
ADD with Carry

co
co
co

SU8C

A,Meml

Subtract with Carry

AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IF8NE
DRSZ
S81T
R81T
IF81T
RPND

A,Meml
A,lmm
A,Meml
A,Meml
MD,Imm
A,Meml
A,Meml
A,Meml
#
Reg
#,Mem
#,Mem
#,Mem

Logical AND
Logical AND Immed., Skip if Zero
Logical OR
Logical EXclusive OR
IF EQual
IF EQual
IF Not Equal
IF Greater Than
If 8 Not Equal
Decrement Reg., Skip if Zero
Set 81T
Reset 81T
IF81T
Reset PeNDing Flag

X
X
LD
LD
LD
LD
LD

A,Mem
A,[X]
A,Meml
A,[X]
8,Imm
Mem,lmm
Reg,lmm

EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD 8 with Immed.
LoaD Memory Immed
LoaD Register Memory Immed.

A~Mem

X
X
LD
LD
LD

A, [8 ±]
A, [X ±]
A, [8±]
A, [X±]
[8±],lmm

EXchange A with Memory [8]
EXchange A with Memory [X]
LoaD A with Memory [8]
LoaD A with Memory [X]
LoaD Memory [8] Immed.

A ~ [8], (8 -E- 8 ± 1)
A~ [X],(X-E- ±1)
A -E- [8], (8 -E- 8 ± 1)
A -E- [X], (X -E- X ± 1)
[8] -E- Imm, (8 -E- 8 ± 1)

CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH

A
A
A

CLeaR A
INCrementA
DECrement A
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
SetC
ResetC
IFC
IF NotC
POP the stack into A
PUSH A onto the stack

A-E-O
A-E-A+1
A-E-A-1
A -E- ROM (PU,A)
A -E- 8CD correction of A (follows ADC, SU8C)
C~A7~ ... ~AO~C
C -E- A7 -E- ... -E- AO -E- C
A7 ... A4~A3 ... AO
C -E- 1, HC -E- 1
C -E- 0, HC -E- 0
IF C is true, do next instruction
If C is not true, do next instruction
SP -E- SP + 1, A -E- [SP]
[SP] -E- A, SP -E- SP - 1

PU -E- [VU], PL -E- [VL]
PC -E- ii (ii = 15 bits, 0 to 32k)
PCg ... 0 -E- i (i = 12 bits)
PC -E- PC + r (r is -31 to +32, except 1)
[SP] -E- PL, [SP-1] -E- PU,SP-2, PC -E- ii
[SP] -E- PL, [SP-1] -E- PU,SP-2, PCg ... 0 -E- i
PL -E- ROM (PU,A)
SP + 2, PL -E- [SP], PU -E- [SP-1]
SP + 2, PL -E- [SP],PU -E- [SP-1]
SP + 2, PL -E- [SP],PU -E- [SP-1],GIE-E-1
[SP] -E- PL, [SP-1] -E- PU, SP-2, PC -E- OFF
PC -E- PC + 1

.......
~

LIJ

D-

VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

A
A
A
A

A
A
Addr.
Addr.
Disp.
Addr.
Addr

1-336

A~[X]

A -E- Meml
A -E- [X]
8 -E-Imm
Mem -E-Imm
Reg -E-Imm

o
o

Instruction Execution Time

-C

Q)
Q)
Q)

Most instructions are single byte (with immediate addressing mode instructions taking two bytes).

Most single byte instructions take one cycle time to execute.
See the BYTES and CYCLES per INSTRUCTION table for details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
[B]

Direct

ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFNE
IFGT
IFBNE
DRSZ

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4

SBIT
RBIT
IFBIT

1/1
1/1
1/1

RPND

1/1

Instructions Using A & C
CLRA
INCA
DECA
LAID
DCOR
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ

Immed.

2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2

1/3
3/4
3/4
3/4

1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2

"'"oo
-C

Transfer of Control
Instructions
JMPL
JMP
JP
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP

3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5

Q)
Q)
~

117

1/1

Memory Transfer Instructions
Register
Indirect

XA,·
LD A,·
LDB,lmm
LDB,lmm
LDMem,lmm
LD Reg, Imm
IFEQMD,lmm

Direct Immed.

[B]

[X]

1/1

1/3

2/3

1/1

1/3

2/3

2/2

[X+,X-]

1/2

1/3

1/2

1/3
(IFB < 16)
(IFB> 15)

1/1
2/2
2/2

3/3
2/3
3/3

2/2

• = > Memory location addressed by B or X or directly.

1-337

w
~
co
co

Upper Nibble Along X-Axis

Lower Nibble Along Y-Axis

D-

o......

Opcode Table

co
co
co
DO

JP -15

JP -31

LDOFO, #. i

ORSZOFO

JP -14

JP -30

LOOF1, # i

ORSZOF1

JP -13

. JP -29

LOOF2, # i .

ORSZOF2

XA,[X+]

XA,[B+]

.IFEQA,#i

IFEQA,[B]

JP -12

JP -28

LO OF3, # i

ORSZOF3

XA,[X-]

XA,[B-]

IFGTA,#i

IFGTA,[B]

JP -11

JP -27

LOOF4, # i

DRSZOF4

VIS

LAID

AOOA,#i

AODA,[B]

JP -10

JP -26

LOOF5, # i

ORSZOF5

RPNO

JIO

ANDA,#i

ANOA,[B]

JP -9

JP -25

LO OF6, # i

ORSZOF6

XA,[X]

XORA,[B]

JP -24

LOOF7, # i

DRSZOF7.·'

ORA,#i

ORA,[B]

JP -7

JP -23

LOOF8, # i

ORSZOF8

XORA,#i

JP -8

NOP

RLCA

LOA,#i

IFC

JP -6

JP -22

LDOF9, # i

ORSZOF9

IFNE
A,[B]

IFEQ
Md,#i

IFNE
A,#i

IFNC

LOA,[B+]

LO [B+ ],#i

INCA

B
RRCA

AOCA,#i

ADCA,[B]

SUBCA, #i

SUBA,[B]

XA,[B]

JP -5

JP -21

LDOFA, # i

ORSZ OFA

LOA,[X+]

JP -4

JP -20

LOOFB, # i

DRSZOFB

LOA,[X-]

LOA,[B-]

LO [B--'-l,#i

OECA

JP -3

JP -19

LOOFC,# i

ORSZOFC

LOMd,#i

JMPL

XA,Md

POPA

JP -2

JP -18

LOOFO, # i

ORSZOFO

OIR

JSRL

LOA,Md

RETSK

JP -1

JP -17

LDOFE, # i

DRSZOFE

LOA,[X]

RET

JP -0

JP -16

LOOFF, # i

ORSZOFF

LO [Bl,#i
LOB,#i

RETI

1-338

LOA,[B]

Opcode Table

o
o

(Continued)

"tJ

(X)
(X)
(X)

Upper Nibble Along X-Axis

m
......

Lower Nibble Along Y-Axis

IFBIT
O,[B]

ANDSZ
A, #i

LD B,#OF

IFBIT
1,[B]
IFBIT
2,[B]
IFBIT
3,[B]

·
·
·

IFBNEO

JSR
xOOO-xOFF

JMP
xOOO-xOFF

JP +17

INTR

LD B,#OE

IFBNE 1

JSR
x100-x1FF

JMP
x100-x1FF

JP +18

JP + 2

LDB,#OD

IFBNE2

JSR
x200-x2FF

JMP
x200-x2FF

JP +19

JP + 3

LDB,#OC

IFBNE 3

JSR
x300-x3FF

JMP
x300-x3FF

JP +20

JP + 4

IFBIT
4,[B]

CLRA

LDB,#OB

IFBNE4

JSR
x400-x4FF

JMP
x400-x4FF

JP +21

JP + 5

IFBIT
5,[B]

SWAPA

LDB,#OA

IFBNE 5

JSR
x500-x5FF

JMP
x500-x5FF

JP +22

JP + 6

IFBIT
6,[B]

DCORA

LD B,#09

IFBNE6

JSR
x600-x6FF

JMP
x600-x6FF

JP +23

JP + 7

IFBIT
7,[B]

PUSHA

LD B,#08

IFBNE7

JSR
x700-x7FF

JMP
x700-x7FF

JP +24

JP + 8

SBIT
O,[B]

RBIT
O,[B]

LDB,#07

IFBNE8

JSR
x800-x8FF

JMP
x800-x8FF

JP +25

JP + 9

SBIT
1,[B]

RBIT
1,[B]

LD B,#06

IFBNE9

JSR
x900-x9FF

JMP
x900-x9FF

JP +26

JP + 10

SBIT
2,[B]

RBIT
2,[B]

LD B,#05

IFBNEOA

JSR
xAOO-xAFF

JMP
xAOO-xAFF

JP +27

JP + 11

SBIT
3,[B]

RBIT
3,[B]

LD B,#04

IFBNEOB

JSR
xBOO-xBFF

JMP
xBOO-xBFF

JP +28

JP + 12

SBIT
4,[B]

RBIT
4,[B]

LD B,#03

IFBNEOC

JSR
xCOO-xCFF

JMP
xCOO-xCFF

JP +29

JP + 13

SBIT
5,[B]

RBIT
5,[B]

LD B,#02

IFBNEOD

JSR
xDOO-xDFF

JMP
xDOO-xDFF

JP +30

JP + 14

SBIT

RBIT
G,[8]

LD B,#01

IFBNEOE

JSR
xEOO-xEFF

JMP
xEOO-xEFt=

JP +31

JP + 15

0,[[3]
SBIT
7,[B]

RBIT
7,[B]

LD B,#OO

IFBNEOF

JSR
xFOO-xFFF

JMP
xFOO-xFFF

JP +32

JP + 16

o
o

"tJ

(X)
(X)

0l::Io

Where,
i is the immediate data
Md is a directly addressed memory location
• is an unused opcode
Note: The opcode 60 Hex is also the opcode for IFBIT #i,A

Mask Options
OPTION 2: HALT
Enable HALT mode
1
Disable HALT mode
2
OPTION 3: BONDING OPTIONS
44-Pin PLCC
1
40-Pin DIP
2
N/A
3
28-Pin DIP
4
28-Pin SO
5

The mask programmable options are shown below. The options are programmed at the same time as the ROM pattern
submission.

=
=

OPTION 1: CLOCK CONFIGURATION
1
Crystal Oscillator (CKI/IO)
G7 (CKO) is clock generator
output to crystal/resonator
CKI is the clock input
2
Single-pin HC controlled
oscillator (CKI/IO)
G7 is available as a HALT
restart and/or general purpose
input

=
=
=
=
=

1-339

UJ
~

co
co

D-

o
.......
~

co
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DO

Development Support
The iceMASTER's performance analyzer offers a resolution
of better than 6 fLs. The user can easily monitor the time
spent executing specific portions of code and find "hot
spots" or "dead code". Up to 15 independent memory areas based on code address or label ranges can be defined.
Analysis results can be viewed in bar graph format or as
actual frequency count.

IN·CIRCUIT EMULATOR
The MetaLink iceMASTERTM-COP8 Model 400 In-Circuit
Emulator for the COP8 family of microcontrollers features
high-performance operation, ease of use, and an extremely
flexible user-interface for maximum productivity. Interchangeable probe cards, which connect to the standard
common base, support the various configurations and packages of the COP8 family.

The iceMASTER provides real time, full speed emulation up
to 10 MHz, 32 kBytes of emulation memory and 4k frames
of trace buffer memory. The user may define as many as
32k trace and break triggers which can be enabled, disabled, set or cleared. They can be simple triggers based on
code or address ranges or complex triggers based on code
address, direct address, opcode value, opcode class or immediate operand. Complex breakpoints can be ANDed and
ORed together. Trace information consists of address bus
values, opcodes and user selectable probe clips status (external event lines). The trace buffer can be viewed as raw
hex or as diassembled instructions. The probe Clip bit values
can be displayed in binary, hex or digital waveform formats.

The iceMASTER comes with an easy to use windowed interface. Each window can be sized, highlighted, color-controlled, added, or removed completely. Commands can be
accessed via pull-down-menus and/or redefineable hot
keys. A context sensitive hypertextlhyperlinked on-line help
system explains clearly the options the user has from within
any window.
The iceMASTER connects easily to a PC® via the standard
COMM port and its 115.2 kBaud serial link keeps typical
program download time shorter.

The following tables list the emulator and probe cards ordering information.

Emulator Ordering Information
Part Number

Description

Current Version

IM-COP8/400/1:1: MetaLink base unit in-circuit emulator for all COP8 devices, symbolic debugger software
Host Software:
_ _ _ _ _ _ _t-a_nd_R_S_2_3_2_s_e_ri_a_1i_nt_e_rf_a_ce_ca_b_le_,_w_it_h_1_1_0_V_@_6_0_H_z_P_o_w_e_r_S_u-'-p.:....p.:.,ly_._ _ _ _ _ _ _- j Ver. 3.3 Rev. 5,
IM-COP8/400/2:1:

MetaLink base unit in-circuit emulator for all COP8 devices, symbolic debugger software
and RS 232 serial interface cable, with 220V @ 50 Hz Power Supply.

Model File
Rev 3.050.

:j:These parts include National's COP8 Assembler/Linker/Librarian Package (COP8-DEV-IBMA).

Probe Card Ordering Information
Part Number

Package

Voltage
Range

Assembler Ordering Information
Part Number

Emulates

COP8-DEV-IBMA

MHW-888EK44DWPC 44 PLCC 2.5V-5.5V COP888EK
MHW-888EK40DWPC

40 DIP

2.5V-5.5V COP888EK

MHW-884EK28DWPC

28 DIP

2.5V-5.5V COP884EK

MHW-SOIC28

28 SO

28-pin SOIC
Adaptor Kit

Description
COP8
Assembler/
Linker/Librarian
for IBM®,
PC/XT®, AT® or
compatible.

Manual
424410632-001

SINGLE CHIP EMULATOR DEVICE
The COP8 family is fully supported by single chip form, fit
and function emulators. For more detailed information refer
to the emulation device specific datasheets.

1~340

(')

Development Support (Continued)

"'C

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.......

PROGRAMMING SUPPORT
Programming of the single chip emulator devices is supported by different sources.

The following programmers are certified for programming EPROM versions of COP8.

(')

"'C

EPROM Programmer Information
Manufacturer
and Product

U.S. Phone
Number

Europe Phone
Number

Asia Phone
Number

MetaLinkDebug Module

(602) 926-0797

Germany:
(49-81-41) 1030

Hong Kong:
852-737-1800

XeltekSuperpro

(408) 745-7974

Germany:
(49-20-41) 684758

Singapore:
(65) 276-6433

BP MicrosystemsEP-1140

(800) 225-2102

Germany:
(49-89-85) 76667

Hong Kong:
(852) 388-0629

Data I/O-Unisite;
-System 29
-System 39

(800) 322-8246

Europe:
(31-20) 622866
Germany:
(49-89-85) 8020

Japan:
(33) 432-6991

Europe:
(89-80) 8707

Abcom-COP8
Programmer
System GeneralTurpro-1-FX;
-APRO

co
co
~
m

(408) 263-6667

Switzerland:
(31) 921-7844

Taiwan:
(2) 917-3005

If the user has a PC with a communications package then
files from the FILE SECTION can be. down loaded to disk for
later use.

DIAL-A-HELPER
Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Bulletin Board Information system.

ORDER PIN: MOLE-DIAL-A-HLP

INFORMATION SYSTEM

Information System Package contains:
Dial-A-Helper Users Manual
Pl!~!:~ D:rn~::l C\:liiiil,Liiiicatiuii5 SoiT~v'itr~

The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be acCfI::'5f1U UVtH ::;landard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities could be found. The minimum requirement for accessing the Dial-A-Helper is a Hayes compatible
modem.
Voice:

(800) 272-9959

Modem: CANADA/U.S.: (800) NSC-MICRO
Baud:

14.4k

Set-up:

Length:

8-Bit

Parity:

None

Stop Bit: 1
Operation:

1-341

24 Hrs., 7 Days

LLI

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National Semiconductor

o
......

COP688EG/COP684EG/COP888EG/COP884EGI
COP988EG/COP984EG
o Single-Chip microCMOS Microcontrollers
......

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General Description

co
co
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The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconductor's M2CMOSTM process technology. The COP888EGI
COP884EG is a member of this expandable 8-bit core processor family of microcontrollers.
(Continued)

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o......

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LLI

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......

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D-

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......
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D-

Features
•
•
•
•
•
•
•
•
•
•
•

Low cost 8-bit microcontroller
Fully static CMOS, with low current drain
Two power saving modes: HALT and IDLE
1 p's instruction cycle time
8k bytes on-board ROM
256 bytes on-board RAM
Single supply operation: 2.5V -6V
Full duplex UART
Two analog comparators
MICROWIRE/PLUSTM serial 1/0
WATCHDOGTM and Clock Monitor logic

• Idle Timer
• Multi-Input Wakeup (MIWU) with optional interrupts (8)
• Three 16-bit timers, each with two 16-bit registers supporting:
- Processor Independent PWM mode
- External Event counter mode
- Input Capture mode
a 8-bit Stack Pointer SP (stack in RAM)
• Two 8-bit Register Indirect Data Memory Pointers
(B and X)

• Fourteen multi-source vectored interrupts servicing
- External Interrupt
- Idle Timer TO
- Three Timers (Each with 2 Interrupts)
- MICROWIRE/PLUS
- Multi-Input Wake Up
- Software Trap
-UART (2)
- Default VIS
• Versatile instruction set
• True bit manipulation
• Memory mapped 1/0
• BCD arithmetic instructions
• Package:
- 44 PLCC with 39 1/0 pins
- 40 N with 35 1/0 pins
- 28 SO or 28 N, each with 23 1/0 pins
• Software selectable 1/0 options
- TRI-STATE® Output
- Push-Pull Output
- Weak Pull Up Input
- High Impedance Input
• Schmitt trigger inputs on ports G and L
• Temperature ranges: O°C to + 70°C,
-40°C to +85°C
- 55°C to + 125°C
• One-Time Programmable emulation devices
• Real time emulation and full program debug offered by
MetaLink's Development Systems

Block Diagram

CPU REGISTERS

TLlDD/11214-1

FIGURE 1. Block Diagram

1-342

General Description

o
o

(Continued)

They are fully static parts, fabricated using double-metal silicon gate microCMOS technology. Features include an 8-bit
memory mapped architecture, MICROWIRE/PLUS serial
liD, three 16-bit timer/counters supporting three modes
(Processor Independent PWM generation, External Event
counter, and Input Capture mode capabilities), full duplex
UART, two comparators, and two power savings modes

(HALT and IDLE), both with a multi-sourced wakeup/interrupt capability. This multi-sourced interrupt capability may
also be used independent of the HALT or IDLE modes.
Each I/O pin has software selectable configurations. The
device operates over a voltage range of 2.5V to 6V. High
throughput is achieved with an efficient, regular instruction
set operating at a maximum of 1 I-'-s per instruction rate.

1 H

CKI

RESET

44 pin
PLCC

.......

Vee
11

0)
Q)

o"0

Dual-In-Line Package

43 42 41 40

o"0
G)

Plastic Chip Carrier

.......

Connection Diagrams

0)
Q)
Q)

GND

RESET

GNO

CKI
VCC

TLlDD/11214-2

Top View
Order Number COP888EG-XXX/V
See NS Plastic Chip Package Number V44A

40 pin
DIP

Q)
Q)
Q)

.......

o"0
Q)
Q)
~

.......

o
o

oI:lo

.......

o"0
CD

Q)
Q)

TLlDD/11214-3

Top View
Order Number COP888EG-XXX/N
See NS Molded Package Number N40A
Dual-In-Line Package
G4

GO
RESET

Vee
10

28 pin
DIP/SO

GND

II
TL/DD/11214-4

Top View
Order Number COP884EG-XXX/WM or COP884EG-XX·X/N
See NS Molded Package Number M288 or N28A
FIGURE 2a. Connection Diagrams

1-343

e"
UJ

Connection Diagrams (Continued)

c..

oo
.....
e"

Pinouts for 28-, 40- and 44-Pin Packages
Port

Type

Alt. Fun

-.:t'

co
c..

.....
e"
UJ

-.:t'

co
co
c..

LO
L1
L2
L3
L4
L5
L6
L7

I/O
' I/O
I/O
I/O
I/O
I/O
I/O
I/O

MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU

CKX
TOX
ROX
T2A
T2B
T3A
T3B

28-Pin
Pack.

40-Pln
Pack.

44-Pln
Pack.

11
12
13
14
15
16
17
18

17
18
19
20
21
22
23
24

17
18
19
20
25
26
27
28

25
26
27
28
1
2
3
4

35
36
37
38
3
4
5
6

39
40
41
42
3
4
5
6

19
20
21
22

25
26
27
28

29
30
31
32

7
8
9
10

9
10
11
12

13
14
15
16

GO
G1
G2
G3
G4
G5
G6
G7

I/O
WOOUT
I/O
I/O
I/O
I/O
I
I/CKO

o.....

DO
01
02
03

0
0
0
0

10
11
12
13

I
I
I
I

14
15
16
17

I
I
I
I

04
05
06
07

0
0
0
0

29
30
31
32

33
34
35
36

CO
C1
C2
C3
C4
C5
C6
C7

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

39
40
1
2

43
44
1
2
21
22
23
24

8
33
7
34

8
37
7
38

.....

e"
UJ
co
co
co
c..

o
.....
e"
UJ

INT
T1B
T1A
SO
SK
SI
HALT Restart

-.:t'

co
c..
CD

e"
UJ
co
co
CD
c..

COMP1INCOMP1IN+
COMP10UT
COMP2INCOMP2IN+
COMP20UT

Vee

6
23
5
24

GNO
CKI
RESET

1-344

o
o

Absolute Maximum Ratings

-a

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Storage Temperature Range

- 65°C to + 140°C

which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

-0.3V to Vee + 0.3V

Total Current into Vee Pin (Source)

110mA

Note: Absolute maximum ratings indicate limits beyond

Supply Voltage (Ved
Voltage at Any Pin

Total Current out of GND Pin (Sink)

100mA

en
Q)
Q)

o
'"
o
-a

en
Q)
~

DC Electrical Characteristics 98XEG: O°C :s; T A :s;
Parameter
Operating Voltage

Conditions

COP98XCS
COP98XCSH
Peak-to-Peak .

Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz
CKI = 4 MHz
CKI = 1 MHz

Vee
Vee
Vee
Vee

HALT Current (Note 3)

IDLE Current
CKI = 10 MHz
CKI = 4MHz
CKI = 1 MHz

Min

= 6V.
= 6V.
= 4V.
=4V.

tc
tc
tc
tc

= 1 /-Ls
= 2.5/-Ls
= 2.5/-Ls
= 10 /-Ls
<0.7
<0.3

Vee = 6V. CKI = 0 MHz
Vee = 4V. CKI = 0 MHz

0.1 Vee

12.5
5.5
2.5
1.4

mA
mA
mA
mA

8
4

/-LA
/-LA

3.5
2.5
0.7

mA
mA
mA

0.2 Vee

V
V

0.2 Vee

V
V

0.2 Vee

V
V

-1

/-LA

-40

-250

/-LA

0.35 Vee

0.7 Vee

G and L Port Input Hysteresis

TRI-STATE Leakage

V
V

0.8 Vee

Vee = 6V. VIN = OV

Sink (Push-Pull Mode)

4.0
6.0

o
'"
o
-a
Q)
Q)
Q)

'"
o
o-a
Q)
Q)
~

o
'"
o
-a
~

o
'"
o
-a

Input Pullup Current

Source (Push-Pull Mode)

Units

Vee = 6V

All Others
Source (Weak Pull-Up Mode)

Max

Hi-Z Input Leakage

Sink

Vee = 6V. tc = 1 /-Ls
Vee = 6V. tc = 2.5/-Ls
Vee = 4V. tc = 10 /-Ls

Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low

Output Current Levels
o Outputs
Source

Typ

2.5
4.0

Power Supply Ripple (Note 1)

+ 70°C unless otherwise specified

Vee
Vee
Vee
Vee

= 4V. VOH = 3.3V
= 2.5V. VOH = 1.8V
= 4V. VOL = 1V
= 2.5V. VOL = O.4V

-0.4
-0.2
10
2.0

Vee
Vee
Vee
Vee
Vee
Vee

= 4V. VOH = 2.7V

=
=
=
=
=

-10
-2.5
-0.4
-0.2
1.6
0.7

-100
-33

/-LA
/-LA
mA
mA
mA
mA

-1

/-LA

2.5V. VOH = 1.8V
4V. VOH = 3.3V
2.5V. VOH = 1.8V
4V. VOL = 0.4V
2.5V. VOL = 0.4V

Vee = 6.0V

mA
mA
mA
mA

Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input. CKO open. inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee. Land Go-Gs configured as
outputs and set high. The 0 port set to zero. The clock monitor and the comparators are disabled.
1-345

Q)
Q)

"
LLI

co
co

DC Electrical Characteristics 98XEG: o·c : : T A :::: + 70·C unless otherwise specified (Continued)

D-

......

"
LLI

"'I:t'

D-

Parameter

Min

Conditions

Allowable Sink/Source
Current per Pin
D Outputs (Sink)
All others

Maximum Input Current
without Latchup (Note 5)

RAM Retention Voltage, Vr

co
co

500 ns Rise
and Fall Time (Min)

D-

Input Capacitance

o
......

Load Capacitance on D2

o
......
LLI

"'I:t'

"
LLI

co
co
co
D-

"
LLI

"'I:t'

o......

"
LLI

co
co

D-

15
3

mA
mA

±100

mA
V

1000

Conditions

Min
1
2.5
3
7.5

4V:::: Vee:::: 6V
2.5V :::: Vee < 4V
4V:::: Vee:::: 6V
2.5V :::: Vee < 4V

200
500
60
150

Typ

Max

Units

DC
DC
DC
DC

,."s
,."s
,."s
,."s

Inputs
tSETUP
tHOLO

Units

4V:::: Vee:::: 6V
2.5V :::: Vee < 4V
4V:::: Vee:::: 6V
2.5V :::: Vee < 4V

Parameter
Instruction Cycle Time (td
Crystal, Resonator,
R/C Oscillator

D-

25·C

Max

AC Electrical Characteristics 98XEG: o·c : : T A :::: + 70·C unless otherwise specified

o......

Typ

Output Propagation Delay (Note 6)
tp01, tpoo
SO,SK
All Others

2.2k, CL

ns
ns
ns
ns

100 pF

4V:::: Vee:::: 6V
2.5V :::: Vee < 4V
4V:::: Vee:::: 6V
2.5V :::: Vee < 4V

0.7
1.75
1
2.5

,."s
,."s
,."s
,."s

220

ns
ns
ns

20
56

MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tuPO)
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

1
1
1
1

tc
tc
tc
tc

Reset Pulse Width

,."s

Note 5: Pins G6 and RESET are designed with a high voltage input network for factorY testing. These pins allow input voltages greater than Vee and the pins will
have sink current to Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vee>. The effective
resistance to Vee is 7500 (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 6: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

1-346

o
o

Absolute Maximum Ratings

"'C

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
7V
Voltage at Any Pin
- 0.3V to Vee + 0.3V
Total Current into Vee Pin (Source)
100mA

Total Current out of GND Pin (Sink)
110 mA
Storage Temperature Range
-65°C to + 140°C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

en
CO
CO

o
""
o
"'C

en
CO
~

DC Electrical Characteristics 888EG:
Parameter

-40°C:::; TA :::; + 85°C unless otherwise specified

Conditions

Operating Voltage
Power Supply Ripple (Note 1)
Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz
CKI = 4 MHz
CKI = 1 MHz
HALT Current (Note 3)
IDLE Current
CKI = 10 MHz
CKI = 4 MHz
CKI = 1 MHz

Min

Typ

2.5
Peak-to-Peak

Max

Units

0.1 Vee

Vee
Vee
Vee
Vee

6V, tc =
6V, tc =
= 4.0V, tc
= 4.0V, tc
=

12.5
5.5
2.5
1.4

1 /-Ls
2.5/-Ls
= 2.5/-Ls
= 10/-Ls

Vee = 6V, CKI = 0 MHz
Vee = 4.0V, CKI = 0 MHz

<1
<0.5

Vee = 6V, tc = 1 /-Ls
Vee = 6V, tc = 2.5 /-Ls
Vee = 4.0V, tc = 10 /-Ls

mA
mA
mA
mA

10
6

/-LA
/-LA

3.5
2.5
0.7

mA
mA
mA

0.2 Vee

V
V

0.8 Vee

0.2 Vee

V
V

0.2 Vee

V
V

0.7 Vee

Hi-Z Input Leakage

Vee = 6V

-2

/-LA

Vee = 6V, VIN = OV

-40

-250

/-LA

0.35 Vee

G and L Port Input Hysteresis

All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage

o
""
o
"'C
CO
CO
~

o
""
o
"'C
<0

CO
~

o
""
o
"'C
<0
CO
CO

Input Pullup Current

Sink

"'C

CO
CO
CO

Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low

Output Current Levels
D Outputs
Source

o
""
o

4V, VOH = 3.3V
2.5V, VOH = 1.8V
= 4V, VOL = 1V
= 2.5V, VOL = O.4V

-0.4
-0.2
10
2.0

4V, VOH = 2.7V
2.5V, VOH = 1.8V
4V, VOH = 3.3V
2.5V, VOH = 1.8V
4V, VOL = O.4V
2.5V, VOL = O.4V

-10
-2.5
-0.4
-0.2
1.6
0.7

-100
-33

/-LA
/-LA
mA
mA
mA
mA

-2

/-LA

Vee
Vee
Vee
Vee

Vee
Vee
Vee
Vee
Vee
Vee

=
=
=
=
=

Vee = 6.0V

mA
mA
mA
mA

Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a crystal/resonator oscillator, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee, L, C, and GO·G5 configured
as outputs and set high. The D port set to zero. The clock monitor and the comparators are disabled.

1-347

C!J
UJ
co
co
en

DC Electrical Characteristics 888EG: -40·C:5: TA:5:

D-

oo
.....
C!J
UJ

"I::t

co
en
DO

o
.....
C!J
UJ

Parameter

o
.....

C!J
UJ
co
co
co
DO

o
.....

C!J
UJ

Maximum Input Current
without Latchup

RAM Retention Voltage, Vr

500 ns Rise
and Fall Time (Min)

Parameter
Instruction Cycle Time (td
Crystal, Resonator,
R/C Oscillator

DtSETUP
tHOLD

Units

15
3

mA
mA

±100

V
7

1000

+ 85·C unless otherwise specified

Conditions

Min

4V:5: Vee:5: 6V
2.5V :5: Vee < 4V
4V:5: Vee:5: 6V
2.5V:5: Vee < 4V

1
2.5
3
7.5

4V:5: Vee::::: 6V
2.5V :5: Vee < 4V
4V:5: Vee:5: 6V
2.5V :5: Vee < 4V

200
500
60
150

Typ

Max

Units

DC
DC
DC
DC

P.s
p.s

p.s

P.s

Inputs

D-

Max

AC Electrical Characteristics 888EG: -40·C :5: TA :5:

o
.....

25·C

Load Capacitance on 02

"I::t

C!J
UJ
co
co

Typ

Input Capacitance

co
O

Min

Allowable Sink/Source
Current per Pin
o Outputs (Sink)
All others

"I::t

co
co
DO

Conditions

+85·C unless otherwise specified (Continued)

Output Propagation Delay (Note 4)
tpD1, tpDO
SO,SK
All Others

2.2k, CL

100 pF

4V:5: Vee:5: 6V
2.5V :5: Vee < 4V
4V:5: Vee:5: 6V
2.5V :5: Vee < 4V

MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tUPD)

ns
ns
ns
ns

0.7
1.75
1
2.5

P.s
p.s

220

ns
ns
ns

20
56

p.s
p.s

Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

1
1
1
1

tc
tc
tc
tc

Reset Pulse Width

P.s

te = Instruction cycle time.
Note 4: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

1·348

a"'0

Total Current out of GND Pin (Sink)
Storage Temperature Range

7V
100mA

DC Electrical Characteristics 688EG: -55°C ~ TA ~
Parameter

Conditions

Operating Voltage
Peak-to-Peak

Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz

Vee = 5.5V, tc = 1 J.Ls
Vee = 5.5V, tc = 2.5 J.Ls

HALT Current (Note 3)

Vee = 5.5V, CKI = 0 MHz

Input Pullup Current

Typ

<10

TRI-STATE Leakage

o
""
a
"'0

(X)
~

Max

Units

5.5

0.1 Vee

12.5
5.5

mA
mA

J.LA

o
""
a
"'0

(X)
(X)
(X)

o
""
a
"'0

(X)

CD
~

m
3.5
2.5

Vee = 5.5V, tc = 1 J.Ls
Vee = 5.5V, tc = 2.5 J.Ls

mA
mA

o
""

"'0

(X)
~

0.2 Vee

V
V

0.2 Vee

V
V

0.2 Vee

V
V

0.8 Vee

0.7 Vee

0.7 Vee
Vee = 5.5V
Vee = 5.5V, VIN = OV

-5

J.LA

-35

-400

J.LA

0.35 Vee

G and L Port Input Hysteresis
Output Current Levels
D Outputs
Source
Sink
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)

Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage

Min

(X)
(X)

+ 125°C unless otherwise specified

4.5

Power Supply Ripple (Note 1)

IDLE Current
CKI = 10 MHz
CKI = 4 MHz

- 65°C to + 140°C

Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

-0.3V to Vee + 0.3V

Total Current into Vee Pin (Source)

110 mA

Vee = 4.5V, VOH = 3.3V
Vee = 4.5V, VOL = 1V

-0.4
9

Vee = 4.5V, VOH = 2.7V
Vee = 4.5V, VOH = 3.3V
Vee = 4.5V, VOL = O.4V

-0.4
1.4

-9

-140

J.LA
mA
mA

J.LA

Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a crystal/resonator oscillator, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from OSCillating in the RC and the Crystal configurations. Test conditions: All inputs tied to
as outputs and set high. The D port set to zero. The clock monitor and the comparators are disabled.

1-349

o
""
a
"'0

(X)
(X)

mA
mA

-5

Vee = 5.5V

Vec,

L, C, and Go-Gs configured

LLI

co
co
en

DC Electrical Characteristics 688EG: -

o.......
~

LLI

-.::r
co
en

o.......

Parameter

Maximum Input Current
without Latchup

TA = 25°C

Input Capacitance

o.......

Load Capacitance on D2

co
co
co

.......
~

LLI

-.::r
co
(D

o
o
.......
~

LLI

co
co
(D

o
o

500 ns Rise
and Fall Time (Min)

AC Electrical Characteristics 688EG: Parameter

Typ

RAM Retention Voltage, Vr

LLI

Min

Conditions

-.::r
co
co

~ TA ~ + 125°C unless otherwise specified (Continued)

Allowable SinklSource
Current per Pin
D Outputs (Sink)
All others

LLI

55°C

Instruction Cycle Time (to)
Crystal, Resonator,
RIC Oscillator

Max

Units

12
2.5

rnA
rnA

±100

rnA
V

55°C

1000

~ TA ~ + 125°C unless otherwise specified

Conditions

Min

Vee ~ 4.5V
Vee ~ 4.5V

1
3

Vee ~ 4.5V
Vee ~ 4.5V

200
60

Typ

Max

Units

DC
DC

I-Ls
I-Ls

Inputs
tSETUP
tHOLO
Output Propagation Delay (Note 4)
tp01, tpoo
SO,SK
All Others

ns
ns

RL = 2.2k, CL = 100 pF
Vee ~ 4.5V
Vee ~ 4.5V

0.7
1

I-Ls
I-Ls

220

ns
ns
ns

20
56

MICROWIRE Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tuPO)
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

1
1
1
1

te
te
te
te

Reset Pulse Width

I-LS

Note 4: The output propagation delay is referenced to the end of instruction cycle where the output change occurs.

1·350

(')

Comparators AC and DC Characteristics Vee =
Parameter
Input Offset Voltage

Conditions

Min

"'C
Ol

Typ
±10

O.4V :::;: VIN :::;: Vee - 1.5V

Input Common Mode Voltage Range

5V, TA = 25°C

0.4

Max

Units

±25

Vee - 1.5

Low Level Output Current

VOL = O.4V

1.6

High Level Output Current

VOH = 4.6V

1.6

(X)
(X)

......
(')
o
"'C
Ol
(X)

DC Supply Current Per Comparator
(When Enabled)
Response Time

250
1

FIGURE 2. MICROWIRE/PLUS Timing

"'C

(X)
(X)
(X)

"'C

(X)
(X)
~

m
......

~tuPD

J.Ls

(')

m
G)
......

tuWH

......

TBD mV Step, TBD mV
Overdrive, 100 pF Load

J.LA

(')

"'C

CD
TLlDD/11214-5

(X)
~

......
(')

"'C

CD
(X)
(X)

1-351

"coco
LLI

Typical Performance Characteristics (-40°C ~ TA ~

o
.....

"
'OI::t

co
en

D..

o
o
.....

"co

Idle-IOO (Crystal Clock Option)

Halt-Ioo

D..

LLI

+85°C)
3.5

1.8
/

1.6

..3
0
_0

1.4
1.2

!:;
~

0.6

LLI

'OI::t

0.4

0.2

D..

-'
2

o
o
.....

/
1.5

10 t.lHz.... ~

".;

l(..

-J

2.5

1 t.lHzj

0
_0

...

" ........ ~40oC
k? . . .

0.8

2.5

..5.
./

+85 0 C

?!, .. 4 t.lHz
I

5.5

0.5

::,;;;.ff
o

3.5

4.5

5.5

2.5

3.5

Vee (V)

4.5

Vee (V)
TL/DD/11214-7

"coco

TLlDD/11214-8

LLI

Port L/C/G Weak Pull-Up
Source Current

Dynamlc-IOO vs Vee
(Crystal Clock Option)

D..

o
o
.....

10 t.lHz ~.

"co

120 r-----r--r--..,.----,.------r--,

I--t-+~-t--I--j.--l

100

LLI

'OI::t

D..

o
o.....

,I.-'

i"
, ....

4 t.lHz ...

... ....

"
LLI

co
co

o ~ -~

D..

2.5

60 f---+----"'....:

.,g.

V
20

......1 t.lHz

3.5

~/
~v

OL-~

4.5

5.5

_L_~_L-~_~

VOH (V)

Vee (V)

TL/DD/11214-9

Port L/C/G Push-Pull Source Current
~"

.......

Vee =6.0V "
I

..5.

,Vee =4.5V ~ -

\
\

VOH (V)

I' ,
~ee=2.5V

,"
!/

..--

0.5

Vee = 4.5V

1.5

I I
I

Vee = 2.5V 1

I I
2.5

-. ...

..5.

.. .

TL/DD/11214-12

..5.

~ee = 4.5V',

~ I

, ~'

It"

-J.
Vee = 6.0V

I I
I

Vee = 4.5V

, .,. ~

Vee = 2.5V

o J?

3
VOH (V)

15
\

'~.

I
I
',vee = 6.0V

'I"
r-::::: r- Vee = 2.5V

3.5

Port D Sink Current
45

...................

::I:

I,'

. . ~-t-

...

TLlDD/11214-11

,- ,,"

Vee = S.OV I
I

VOL (V)

Port D Source Current

.. ' I

'~,

f-:;: '-

J,"i--

o
o

Port L/C/G Push-Pull Sink Current
18

... ...

TL/DD/11214-10

0.5

1 1.5 2 2.5 3 3.5 4 4.5
VOL (V)
TL/DD/11214-14

TL/DD/11214-13

1-352

o
o

Pin Descriptions

""'C

Vee and GND are the power supply pins.

PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.

CKI is the clock input. This can come from an R/C generated oscillator, or a crystal oscillator (in conjunction with
CKO). See Oscillator Description section.

The Port L supports Multi-Input Wake Up on all eight pins.
L 1 is used for the UART external clock. L2 and L3 are used
for the UART transmit and receive. L4 and L5 are used for
the timer input functions T2A and T28. L6 and L7 are used
for the timer input functions T3A and T38.

RESET is the master reset input. See Reset Description
section.
The device contains three bidirectional 8-bit I/O ports (C, G
and L), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L and G),
output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also
reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O
ports.) Figure 3 shows the I/O port configurations. The
DATA and CONFIGURATION registers allow for each port
bit to be individually configured under software control as
shown below:
CONFIGURATION
Register

DATA
Register

0
1
1

1
0
1

The Port L has the following alternate features:
MIWU

MIWU or CKX

MIWU or TDX

MIWU or RDX

MIWU or T2A

MIWU orT28

MIWU or T3A

Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output

I
N
T

""'C
0)
Q)

......
""'C

Q)
Q)
Q)

m
C)
......

AND
~
I .?f12SJ
n~ ~~~IP~~~~DA~T~A~~~:~~__~~~
PORT L, C,

m
C)
......
o

o
o

MIWU orT38
L7
Port G is an 8-bit port with 5 I/O pins (GO, G2-G5), an input
pin (G6), and two dedicated output pins (G1 and G7). Pins
GO and G2-G6 all have Schmitt Triggers on their inputs. Pin
G1 serves as the dedicated WDOUT WATCHDOG output,
while pin G7 is either input or output depending on the oscillator mask option selected. With the crystal oscillator option
selected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin but is
also used to bring the device out of HALT mode with a low
to high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (GO, G2-G5) can be individually configured under software control.

Port Set-Up

__ .

0)
Q)
Q)

o""'C
Q)
Q)
~

......

""'C

Q)
~

m
C)

......

""'C

co
Q)
Q)

......

E
R
N
A

PORT D

B
U

PORT I
TL/DD/11214-6

FIGURE 3. 110 Port Configurations

1-353

co
co

D-

o.......
~

w
~

co
0)
D-

O
o.......
~

w
~

co
co

D-

O
o.......

Pin Descriptions (Continued)

Functional Description

CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or
shift operation in one instruction (te) cycle time.

co
co
co

D-

O
o
.......
~

w
~

co
CD

D-

O
o
.......

Conflg Reg.

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

Port G has the following alternate features:
G2 T18 (TimerT1 Capture Input)
G3 T1A (Timer T1 1/0)
G5 SK (MICROWIRE Serial Clock)
G6 SI (MICROWIRE Serial Data Input)

D-

S is the 8-bit Data Segment Address Register used to extend the lower half of the address range (00 to 7F) into 256
data segments of 128 bytes ea~h .

G4 SO (MICROWIRETM Serial Data Output)

co
co
O

SP is the 8-bit stack pointer, which points to the subroutinel
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.

GO INTR (External Interrupt Input)

8 is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented .

All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).

Port G has the following dedicated functions:

G1 WDOUT WATCHDOG and lor Clock Monitor dedicated output
G7 CKO Oscillator dedicated output or general purpose
input
Port C is an 8-bit 1/0 port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated
pins will return unpredicatable values.

DATA MEMORY

PORT I is an eight-bit Hi-Z input port. The 28-pin device
does not have a full complement of Port I pins. The unavailable pins are not terminated i.e., they are floating. A read
operation for these unterminated pins will return unpredictable values. The user must ensure that the software takes
this into account by either masking or restricting the accesses to bit operations. The unterminated Port I pins will draw
power only when addressed.

The data memory address space includes the on-chip RAM
and data registers, the 1/0 registers (Configuration, Data
and Pin), the control registers, the MICROWIRE/PLUS SIO
shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer).
Data memory is addressed directly by the instruction or indirectly by the 8, X, SP pointers and S register.
The data memory consists of 256 bytes of RAM. Sixteen
bytes of RAM are mapped as "registers" at addresses OFO
to OFF Hex. These registers can be loaded immediately,
and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction. The memory
pointer registers X, SP, 8 and S are memory mapped into
this space at address locations OFC to OFF Hex respectively, with the other registers being available for general usage.

Port 11-13 are used for Comparator 1. Port 14-16 are used
for Comparator 2.
The Port I has the following alternate features.
11

COMP1 -IN (Comparator 1 Negative Input)

COMP1 + IN (Comparator 1 Positive Input)

COMP10UT (Comparator 1 Output)

COMP2 -IN (Comparator 2 Negative Input)

15
16

COMP2+ IN (Comparator 2 Positive Input)
COMP20UT (Comparator 2 Output)

Port D is an 8-bit output port that is preset high when
RESET goes low. The user can tie two or more D port outputs (except D2) together in order to get a higher drive.

Note: RAM contents are undefined upon power-up.

Note: Care must be exercised with the 02 pin operation. At RESET, the
external loads on this pin must ensure that the output voltages stay
above 0.8 Vee to prevent the chip from entering special modes. Also
keep the external loading on 02 to less than 1000 pF.

1-354

o
o

Data Memory Segment RAM Extension
Data memory address OFF is used as a memory mapped
location for the Data Segment Address Register (S).

XXFF

The data store memory is either addressed directly by a
single byte address within the instruction, or indirectly relative to the reference of the B, X, or SP pointers (each contains a single-byte address). This single-byte address allows
an addressing range of 256 locations from 00 to FF hex.
The upper bit of this single-byte address divides the data
store memory into two separate sections as outlined previously. With the exception of the RAM register memory from
address locations OOFO to OOFF, all RAM memory is memory mapped with the upper bit of the single-byte address being equal to zero. This allows the upper bit of the single-byte
address to determine whether or not the base address
range (from 0000 to OOFF) is extended. If this upper bit
equals one (representing address range 0080 to OOFF),
then address extension does not take place. Alternatively, if
this upper bit equals zero, then the data segment extension
register S is used to extend the base address range (from
0000 to 007F) from XXOO to XX7F, where XX represents the
8 bits from the S register. Thus the 128-byte data segment
extensions are located from addresses 0100 to 017F for
data segment 1, 0200 to 027F for data segment 2, etc., up
to FFOO to FF7F for data segment 255. The base address
range from 0000 to 007F represents data segment O.

"enen
en

RAM REGISTERS
(16 BYTES)
INCLUDES B, X, SP, S

XXFO

XXEF

Q
........

TIIoIERS,I/O, MW,
CNTRL, PSW, A/D,
ICNTRL, WD, MIWU,
COlA PARA TOR
AND UART
REGISTERS

o
o

en
en
~

XXBO
XXAF

UNUSED
(READS UNDEFINED
DATA)

T
S

XX80
007F
0070
006F

UNUSED'

Q
........

T
S

ON CHIP RAIoI
(128 BYTES)

E
G

E
G
M
E
N
T

ON CHIP RAIoI

M
E

(112 BYTES)

o
o

017F

013F

000 0

0100 .....- - - -..
TL/00/11214-15

'Reads as all ones.

FIGURE 4. RAM Organization

Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports l, G and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WATCHDOG and lor Clock Monitor error
output pin. Port 0 is set high. The PC, PSW, ICNTRl,
CNTRl, T2CNTRl and T3CNTRl control registers are
cleared. The UART registers PSR, ENU (except that TBMT
bit is set), ENUR and ENUI are cleared. The Comparator
Select Register is cleared. The S register is initialized to
zero. The Multi-lnout Wakeup re~iRtpr~ WKEN, WKEDG e.r.d
WKPND are clea~ed. The stack pointer, SP, is initialized to
6F Hex.

Figure 4 illustrates how the S register data memory extension is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XXOO
to XX7F. This organization allows a total of 256 data segments of 128 bytes each with an additional upper base segment of .128 bytes. Furthermore, all addressing modes are
available for all data segments. The S register must be
changed under program control to move from one data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory registers, 1/0 registers,
control registers, etc.) is always available regardless of the
ccnt~:1t~ c! th~ S i~g;:;t~i, 5;'lca Hid upp..:,,. ud.:,e ~~yrnent
(address range 0080 to OOFF) is independent of data segment extension.

The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k tc clock cycles. The Clock Monitor bit
being initialized high will cause a Clock Monitor error following reset if the clock has not reached the minimum specified
frequency at the termination of reset. .A Clock Monitor error
will cause an active low error output on pin G 1. This error
output will continue until 16 tc-32 tc clock cycles following
the clock frequency reaching the minimum specified value,
at which time the G1 output will enter the TRI-STATE mode.

The instructions that utilize the stack pointer (SP) always
reference the stack as part of the base segment (Segment
0), regardless of the contents of the S register. The S register is not changed by these instructions. Consequently, the
stack (used with subroutine linkage and interrupts) is always
located in the base segment. The stack pointer will be intitialized to point at data memory location 006F as a result of
reset.
The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
112 bytes of RAM are resident from address 0000 to 006F
in the lower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at addresses OOFO to OOFF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.

The external RC network shown in Figure 5 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.

Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XXOO to XX7F) of
the lower base segment. The additional 128 bytes of RAM
are memory mapped at address locations 0100 to 017F
hex.

1-355

m
Q

........

-L

"enen
"enen
~

m
Q

........

"enco
~

Q
........

"enco
en

~ r-------------------------------------------------------------------~

co
co
en

Reset (Continued)
P
0

D-

co
en

P
L
Y

o
......

co
co
co
DO

3. Internal leakage current-13
4. Output source current-14

:::r:;:c

5. DC current caused by external input
not at Vee or GND-15

GND

7. Clock Monitor current when enabled-17

FIGURE 5. Recommended Reset Circuit

Thus the total current drain, It, is given as
It = 11

Oscillator Circuits

CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.

"'1:1'

co
CD

D-

o
......

co
co
CD

D-

RIC OSCILLATOR

CKO

R2
-"

CKI

: Rl

-'.I.

~C2

_L- C1

+ 16 +

SL 1 & SLO Select the MICROWIRE/PLUS clock divide
by (00 = 2,01 = 4, 1x = 8)

IEDG

External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)

MSEL

Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively

T1CO

Timer T1 StartlStop control in timer
modes 1 and 2

•

TLlDD/11214-18

Timer T1 Underflow Interrupt Pending Flag in
timer mode 3

TL/DD/I1214-17

FIGURE 6. Crystal and RIC Oscillator Diagrams

T1 C1

Timer T1 mode control bit

TABLE A. Crystal Oscillator Configuration, T A = 25°C

T1 C2

Timer T1 mode control bit

R1
(kn)

R2
(MO)

C1
(pF)

C2
(pF)

CKI Freq
(MHz)

T1 C3

Timer T1 mode control bit

Conditions

0
0
0

1
1
1

30
30
200

30-36
30-36
100-150

10
4
0.455

Vee = 5V
Vee = 5V
Vee = 5V

IT1C31 T1C21 T1C1 I T1CO I MSEL IIEDG I SL1 I SLO I
Bit7

TABLE B. RC Oscillator Configuration, T A = 25°C
R
(kO)

C
(pF)

CKI Freq
(MHz)

Instr. Cycle
(p.s)

Conditions

3.3
5.6
6.8

82
100
100

2.2 to 2.7
1.1 to 1.3
0.9t01.1

3.7 to 4.6
7.4 to 9.0
8.8 to 10.8

Vee = 5V
Vee = 5V
Vee = 5V

Note: 3k

50 pF

R
~

200k
~

CNTRL Register (Address X'OOEE)

..A

The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:

"'~~-~f~

..L

CKO

+ 14 +

Control Registers

Table B shows the variation in the oscillator frequencies as
functions of the component (R and C) values.

where C = equivalent capacitance of the chip
V = operating voltage
f = CKI frequency

By selecting CKI as a single pin oscillator input, a single pin
RIC oscillator circuit can be connected to it. CKO is available as a general purpose input, and lor HALT restart input.

CKI

12 = C

Table A shows the component values required for various
standard crystal values.

Figure 6 shows the Crystal and RIC oscillator diagrams.

CRYSTAL OSCILLATOR

To reduce the total current drain, each of the above components must be minimum.

o
......

6. Comparator DC supply current when enabled-16

> 5 x Power Supply Rise Time

o
......

2. Internal switching current-12

TL/DD/11214-16

"'1:1'

COP800
RESET

D-

1. Oscillator operation mode-11

.~R

S
U

"'1:1'

co
co
DO

vee
~

E
R

o
......

Current Drain
The total current drain of the chip depends on:

200 pF

1-356

Bit 0

Control Registers

(Continued)

"tJ

PSW Register (Address X/OOEF)

T2C1

Timer T2 mode control bit

The PSW register contains the following select bits:

T2C2

Timer T2 mode control bit

T2C3

Timer T2 mode control bit

GIE

Global interrupt enable (enables interrupts)

EXEN

Enable external interrupt
MICROWIRE/PLUS busy shifting flag

EXPND

External interrupt pending

T1 ENA

Timer T1 Interrupt Enable for Timer Underflow
or T1 A Input capture edge

Half Carry Flag

I II

C T1 PNDA T1 ENA EXPND BUSY EXEN GIE

Bit7

BitO

T3C1

Timer T3 mode contro"l bit

T3C2

Timer T3 mode control bit

T3C3

.Timer T3 mode control bit

.......

o"tJ
Q)
Q)
~

.......

o
"tJ
CD

Q)
~

.......

BitO

Timers

Q)
Q)

The device contains a very versatile set of timers (TO, T1,
T2, T3). All timers and associated autoreloacl/capture registers power up containing random data.

Timer TO Interrupt Enable (Bit 12 toggle)

TOPND

Timer TO Interrupt pending

LPEN

L Port Interrupt Enable (Mlllti-lnput W8kl?l'pllnterrupt)

Bit 7 could be used as a flag

Bit?

Q)
Q)
Q)

"tJ

Bit?

JA-WPND MICROWIRE/PLUS interrupt pending

BitO

T2CNTRl Register (Address

o"tJ

o
o

Enable MICROWIRE/PLUS interrupt

TOEN

X/~OCS)

Exit out of the Idle Mode (See Idle Mode description)
WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode
The IDLE Timer TO can generate an interrupt when the thirteenth bit toggles. This toggle is latched into the TOPND
pending flag, and will occur every 4 ms at the maximum
clock frequency (te = 1 JA-s). A control flag TOEN allows the
interrupt from the thirteenth bit of Timer TO to be enabled or
disabled. Setting TOEN will enable the interrupt, while resetting it will disable the interrupt.

The T2CNTRL register contains the following bits:
Timer T2 Interrupt Enable for T2B Input capture
edge

T2PNDB Timer T2 Interrupt Pending Flag for T2B capture edge
'
Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA
in mode 1, T2 Underflow in mode 2, T2A capture edge in mode 3)
T2CO

Timer T3 Start/Stop control in timer modes 1
and 2

Timer T1 Interrupt Enable for T1 B Input capture
edge

T1 PNDB Timer T1 Interrupt Pending Flag for T1 B capture edge

T2ENA

Timer T3 Interrupt Enable for Timer Underflow
or T3A pin

Timer T3 Underflow Interrupt Pending Flag in
timer mode 3

The ICNTRL register contains the following bits:

T2ENB

Timer T3 Interrupt Enable for T3B

T3PNDA Timer T3 Interrupt Pending Flag (Autoload RA
in mode 1, T3 Underflow in mode 2, T3a capture edge in mode 3)
T3CO

ICNTRl Register (Address X/ODES)

JA-WEN

.......

T3PNDB Timer T3 Interrupt Pending Flag for T3B pin
(T3B capture edge)

The T3CNTRL register contains the following bits:
T3ENB

T3CNTRl Register (Address X/OOBS)

I I

T1 ENB

o
o

T3ENA

.......

BitO

Bit?

T1 PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3)
Carry Flag

"tJ

BUSY

en
Q)

Timer T2 Start/Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3

1-357

LIJ
co
co

o
o
.......
CJ
LIJ
~
co
0)

o.......
CJ

LIJ
~
co
co

o.......
CJ

LIJ
co
co
co

.......

CJ
LIJ
~
co

o
.......
CJ
LIJ
co
co

o
o

Timers (Continued)
TIMER T1, TIMER T2 AND TIMER T3
The device has a set of three powerful timer/counter
blocks, T1, T2 and T3. The associated features and functioning of a timer block are described by referring to the
timer block Tx. Since the three timer blocks, T1, T2 and T3
are identical, all comments are equally applicable to any of
the three timer blocks.

TIMER
UNDERFLOW
INTERRUPT . - - - - - .

TxA

Each timer block consists of a 16-bit timer, Tx, and two
supporting 16-bit autoreload/ capture registers, RxA and
RxB. Each timer block has two pins associated with it, TxA
and TxB. The pin TxA supports 110 required by the timer
block, while the pin TxB is an input to the timer block. The
powerful and flexible timer block allows the device to easily
perform all timer functions with minimal software overhead.
The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and
Input Capture mode.
The control bits TxC3, TxC2, and TxC1 allow selection of
the different modes of operation.

t C - - - - -......

TL/DD/11214-19

In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
Figure 8 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock.

TIMER
UNDERFLOW
INTERRUPT . - - - - - .

TxA

TL/DD/11214-20

FIGURE 8. Timer In External Event Counter Mode
Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode.
In this mode, the timer Tx is constantly running at the fixed
te rate. The two registers, RxA and RxB, act as capture
registers. Each register acts in conjunction with a pin. The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin.

1-358

Timers

a'1J

(Continued)

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.......

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The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.

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.......

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TL/DD/11214-21

FIGURE 9. Timer In Input Capture Modo

a'U

TIMER CONTROL FLAGS
The timers T1, T2 and T3 have indentical control structures.
The control bits and their functions are summarized below.
TxCO

Figure 9 shows a block diagram of the timer in Input Capture
mode.

Timer Start/Stop control in Modes
(Processor Independent PWM and
Event Counter), where 1 = Start, 0 =
Timer Underflow Interrupt Pending
Mode 3 (Input Capture)

.......

1 and 2
External
Stop
Flag in

Q)
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0l:Io.

.......

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0l:Io.

TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag

.......

TxENA
TxENB

Timer Interrupt Enable Flag
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
o = Timer Interrupt Disabled

a'U

Timer mode control
Timer mode control
Timer mode control

TxC3
TxC2
TxC1

U)
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1-359

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a..

Timers (Continued)
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:

0
0

Interrupt B
Source

Counts On

Timer
Underflow

Pos. TxB
Edge

TxA
Pos.Edge

MODE 2 (External
Event Counter)

Timer
Underflow

Pos.TxB
Edge

TxA
Neg. Edge

......

TxC3

TxC2

TxC1

Timer Mode

MODE 2 (External
Event Counter)

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0
0

......
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Interrupt A

Source

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0

MODE 1 (PWM)
TxA Toggle

Autoreload
RA

Autoreload
RB

MODE 1 (PWM)
No TxA Toggle

Autoreload
RA

Autoreload
RB

......

MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Pos. Edge

Pos. TxA
Edge or
Timer
Underflow

Pos. TxB
Edge

0
......

MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Neg. Edge

Pos. TxA
Edge or
Timer
Underflow

Neg. TxB
Edge

MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Pos. Edge

Neg. TxA
Edge or
Timer
Underflow

Pos. TxB
Edge

MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Neg. Edge

Neg. TxA
Edge or
Timer
Underflow

Neg. TxB
Edge

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Timer

a..

0
0

......

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0
0

Power Save Modes
The device offers the user two power save modes of operation: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscillator circuitry the WATCHDOG logic, the Clock Monitor and
timer TO are active but all other microcontroller activities are
stopped. In either mode, all on-board RAM, registers, 1/0
states, and timers (with the exception of TO) are unaltered.

1-360

o
o
-a

Power Save Modes (Continued)

This toggle condition of the thirteenth bit of the IDLE Timer
TO is latched into the TOPND pending flag.

The user has the option of being interrupted with a transition
on the thirteenth bit of the IDLE Timer TO. The interrupt can
be enabled or disabled via the TOEN control bit. Setting the
TOEN flag enables the interrupt and vice versa.
The user can enter the IDLE mode with the Timer TO interrupt enabled. In this case, when the TOPND bit gets set, the
device wi" first execute the Timer TO interrupt service routine and then return to the instruction following the "Enter
Idle Mode" instruction.
Alternatively, the user can enter the IDLE mode with the
IDLE Timer TO interrupt disabled. In this case, the device
will resume normal operation with the instruction immediately following the "Enter IDLE Mode" instruction.

The WATCHDOG detector circuit is inhibited during the
HALT mode. However, the clock monitor circuit if enabled
remains active during HALT mode in order to ensure a clock
monitor error if the device inadvertently enters the HALT
mode as a result of a runaway program or power glitch.
IDLE MODE
The device is placed in the IDLE mode by writing a "1" to
the IDLE flag (G6 data bit). In this mode, a" activities, except
the associated on-board oscillator circuitry, the WATCHDOG logic, the clock monitor and the IDLE Timer TO, are
stopped.
As with the HALT mode, the device can be returned to normal operation with a reset, or with a Multi-Input Wakeup
from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the thirteenth
bit (representing 4.096 ms at internal clock frequency of
1 MHz, tc = 1 JLs) of the IDLE Timer toggles.

en
en

m
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.......

o-a
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en
~

.......

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.......

o-a

Multi-Input Wakeup

co
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.......

The Multi-Input Wakeup feature is ued to return (wakeup)
the device from either the HALT or IDLE modes. Alternately
Multi-Input Wakeup/lnterrupt feature may also be used to
generate up to 8 edge selectable external interrupts.
Figure 10 shows the Multi-Input Wakeup logic.

-a
co

<0
~

.......

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INTERNAL DATA BUS

TO
INTERRUPT
LOGIC

ro1
L.....I

•
•
•
•
•
•

WKEDG

WKPND

••
•••

~~~W-A-K-EU-P--~-+--~

•

CHIP CLOCK

TL/DD/11214-22

FIGURE 10. Multi-Input Wake Up Logic

1-361

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Multi-Input Wakeup

(Continued)

WKEN, WKPND and WKEDG are all read/write registers,
and are cleared at reset.

The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an 8bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.

PORT L INTERRUPTS
Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into
the same service subroutine.

RBIT
SBIT
RBIT
SBIT

5,
5,
5,
5,

WKEN
WKEDG
WKPND
WKEN

1-362

a"tJ

UART
Other functions of the ENUR register include saving the
ninth bit received in the data frame, enabling or disabling the
UART's attention mode of operation and providing additional receiver/transmitter status information via RCVG and
XMTG bits. The determination of an internal or external
clock source is done by the ENUI register, as well as selecting the number of stop bits and enabling or disabling transmit and receive interrupts. A control flag in this register can
also select the UART mode of operation: asynchronous or
synchronous.

The device contains a full-duplex software programmable
UART. The UART (Figure 11) consists of a transmit shift
register, a receiver shift register and seven addressable registers, as follows: a transmit buffer register (TBUF), a receiver buffer register (RBUF), a UART control and status register (ENU), a UART receive control and status register
(ENUR), a UART interrupt and clock source register (ENUI),
a prescaler select register (PSR) and baud (BAUD) register.
The ENU register contains flags for transmit and receive
functions; this register also determines the length of the
data frame (7, 8 or 9 bits), the value of the ninth bit in transmission, and parity selection bits. The ENUR register flags
framming, data overrun and parity errors while the UART is
receiving.

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.......

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.......

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.......

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WAKE-UP LOGIC

RDX

G')

.......

DOE
FE

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INTERRUPT

G')

.......

INTERRUPT

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A
L

Q)
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TDX
D
A
T
A

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ENU

XMIT RECV
CLOCK CLOCK

ENUR

CKX

CKI
TlIOO/11214-23

FIGURE 11. UART Block Diagram

1-363

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UART (Continued)

D..

UART CONTROL AND STATUS REGISTERS

The operation of the UART is programmed through three
registers: ENU, ENUR and ENUI. The function of the individual bits in these registers is as follows:

oo::r

ENU-UART Control and Status Register (Address at OBA)

o
o
......
w

PSEL 1 = 1, PSELO = 0
PSEL1 = 1, PSELO = 1

PEN: This bit enables/disables Parity (7- and a-bit modes
only).
PEN = 0 Parity disabled.
PEN = 1 Parity enabled.

0')

D..

PEN

o......

ORW

Bit7

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ENUR-UART Receive Control and Status Register
(Address at OBB)

oo::r

D..

......
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PSEL1 XBIT9/ CHL1
PSELO
ORW ORW ORW

CHLO

ERR

RBFL TBMT

ORW

ENUR-UART RECEIVE CONTROL AND
STATUS REGISTER

RCVG: This bit is set high whenever a framing error occurs
and goes low when RDX goes high.

BitO

XMTG: This bit is set to indicate that the UART is transmitting. It gets reset at the end of the last frame (end of last
Stop bit).
ATTN: ATTENTION Mode is enabled while this bit is set.
This bit is cleared automatically on receiving a character
with data bit nine set.

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RBIT9: Contains the ninth data bit received when the UART
is operating with nine data bits per frame.

ENUI-UART Interrupt and Clock Source Register
(Address at OBC)

SPARE: Reserved for future use .

......
w

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D..

·Bit is not used.

o
o
......

Bit is cleared on reset.
Bit is set to one on reset.

Bit is read-only; it cannot be written by software.

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o
o

PE: Flags a Parity Error.
PE = 0 Indicates no Parity Error has been detected since
the last time the ENUR register was read.
PE = 1 Indicates the occurrence of a Parity Error.

Mark(1) (if Parity enabled)
Space(O) (if Parity enabled)

FE: Flags a Framing Error.
FE = 0 Indicates no Framing Error has been detected
since the last time the ENUR register was read.
FE = 1 Indicates the occurrence of a Framing Error.

RW Bit is read/write.

DOE: Flags a Data Overrun Error.
DOE = 0 Indicates no Data Overrun Error has been detected since the last time the ENUR register
was read.
DOE = 1 Indicates the occurrence of a Data Overrun Error.

Bit is cleared on read; when read by software as a one, it is cleared
automatically. Writing to the bit does not affect its state.

ENUI-UART INTERRUPT AND
CLOCK SOURCE REGISTER
ETI: This bit enables/disables interrupt from the transmitter
section.
ETI = 0 Interrupt from the transmitter is disabled.
ETI = 1 Interrupt from the transmitter is enabled.

RBFL: This bit is set when the UART has received a complete character and has copied it into the RBUF register. It
is automatically reset when software reads the character
from RBUF.

ERI: This bit enables/disables interrupt from the receiver
section.
ERI = 0 Interrupt from the receiver is disabled.
ERI = 1 Interrupt from the receiver is enabled.

ERR: This bit is a global UART error flag which gets set if
any or a combination of the errors (DOE, FE, PE) occur.
CHL 1, CHLO: These bits select the character frame format.
Parity is not included and is generated/verified by hardware.
CHL 1 = 0, CHLO = 0 The frame contains eight data bits.
CHL 1 = 0, CHLO = 1 The frame contains seven data
bits.
CHL 1 = 1, CHLO = 0 The frame contains nine data bits.
CHL1 = 1, CHLO = 1 Loopback Mode selected. Transmitter output internally looped
back to receiver input. Nine bit
framing format is used.

XTCLK: This bit selects the clock source for the transmittersection.
XTCLK = 0 The clock source is selected through the
PSR and BAUD registers.
XTCLK = 1 Signal on CKX (L 1) pin is used as the clock.
XRCLK: This bit selects the clock source for the receiver
section.
XRCLK = 0 The clock source is selected through the
PSR and BAUD registers.
XRCLK = 1 Signal on CKX (L 1) pin is used as the clock.

SSEL: UART mode select.
SSEL = 0 Asynchronous Mode.
SSEL = 1 Synchronous Mode.

PSEL 1, PSELO: Parity select bits.
PSEL 1 = 0, PSELO = 0 Odd Parity (if Parity enabled)
PSEL 1 = 0, PSELO = 1 Even Parity (if Parity enabled)

1-364

C')

when a framing error occurs and goes low once RDX goes
high. TBMT, XMTG, RBFL and RCVG are read only bits.

UART (Continued)
ETDX: TDX (UART Transmit Pin) is the alternate function
assigned to Port L pin L2; it is selected by setting ETDX bit.
To simUlate line break generation, software should reset
ETDX bit and output logic zero to TDX pin through Port L
data and configuration registers.

SYNCHRONOUS MODE

In this mode data is transferred synchronously with the
clock. Data is transmitted on the rising edge and received
on the falling edge of the synchronous clock.

STP78: This bit is set to program the last Stop bit to be
7/8th of a bit in length.

This mode is selected by setting SSEL bit in the ENUI register. The input frequency to the UART is the same as the
baud rate.

STP2: This bit programs the number of Stop bits to be transmitted.
STP2 = 0 One Stop bit transmitted.
STP2 = 1 Two Stop bits transmitted.

FRAMING FORMATS

The UART supports several serial framing formats (Figure
12). The format is selected using control bits in the ENU,
ENUR and ENUI registers.

The baud rate clock for the UART can be generated onchip, or can be taken from an external source. Port L pin L1
(CKX) is the external clock liD pin. The CKX pin can be
either an input or an output, as determined by Port L Configuration and Data registers (Bit 1). As an input, it accepts a
clock signal which may be selected to drive the transmitter
andlor receiver. As an output, it presents the internal Baud
Rate Generator output.

UART Operation
The UART has two modes of operation: asynchronous
mode and synchronous mode.

The third format for transmission (CHLO = 0, CHL 1 = 1)
consists of one Start bit, nine Data bits and 7/8, one or two
Stop bits. This format also supports the UART "ATTENTION" feature. When operating in this format, all eight bits
of TBUF and RBUF are used for data. The ninth data bit is
transmitted and received using two bits in the ENU and
ENUR r~g;;;t6is, ca.ll6U )(61.9 ctlili n61T8. RBIT9 is a read
only bit. Parity is not generated or verified in this mode.

ASYNCHRONOUS MODE
This mode is selected by resetting the SSEL (in the ENUI
register) bit to zero. The input frequency to the UART is 16
times the baud rate.
The TSFT and TBUF registers double-buffer data for transm!ss!cn. Wh:!~ TSFT:~ ~h;ft;ng out th", CUfft':nl l;ilctli:tcltlr on
the TDX pin, the TBUF register may be loaded by software
with the next byte to be transmitted. When TSFT finishes
transmitting the current character the contents of TBUF are
transferred to the TSFT register and the Transmit Buffer
Empty Flag (TBMT in the ENU register) is set. The TBMT
flag is automatically reset by the UART when software loads
a new character into the TBUF register. There is also the
XMTG bit which is set to indicate that the UART is transmitting. This bit gets reset at the end of the last frame (end of
last Stop bit). TBUF is a readlwrite register.

For any of the above framing formats, the last Stop bit can
be programmed to be 7/8th of a bit in length. If two Stop
bits are selected and the 7/8th bit is set (selected), the
second Stop bit will be 7/8th of a bit in length.
The parity is enabledldisabled by PEN bit located in the
ENU register. Parity is selected for 7- and 8-bit modes only.
If parity is enabled (PEN = 1), the parity selection is then
performed by PSELO and PSEL 1 bits located in the ENU
register.

Note that the XBIT9/PSELO bit located in the ENU register
serves two mutually exclusive functions. This bit programs
the ninth bit for transmission when the UART is operating
with nine data bits per frame. There is no parity selection in
this framing format. For other framing formats XBIT9 is not
needed and the bit is PSELO used in conjunction with
PSEL 1 to select parity.
The frame formats for the receiver differ from the transmitter in the number of Stop bits required. The receiver only
requires one Stop bit in a frame, regardless of the setting of
the Stop bit selection bits in the control register. Note that
an implicit assumption is made for full duplex UART operation that the framing formats are the same for the transmitter and receiver.

1-365

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UART Operation

(Continued)

START
BIT

7 BIT DATA

l a - , START
BIT

7 BIT DATA

l b - , START
BIT

7 BIT DATA

l e - , START
BIT

7 BIT DATA

START
BIT

8 BIT DATA

2 a - , START
BIT

8 BIT DATA

2 b - , START
BIT

8 BIT DATA

2 e - , START
BIT

8 BIT DATA

START
BIT

9 BIT DATA

3 a - , START
BIT

9 BIT DATA

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L

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TL/DD/11214-24

FIGURE 12. Framing Formats
source selected in the PSR and BAUD registers. Internally,
the basic baud clock is created from the oscillator frequency
through a two-stage divider chain consisting of a 1-16 (increments of 0.5) prescaler and an 11-bit binary counter.
(Figure 13) The divide factors are specified through two
read/write registers shown in Figure 14. Note that the 11-bit
Baud Rate Divisor spills over into the Prescaler Select Register (PSR). PSR is cleared upon reset.

UARTINTERRUPTS
The UART is capable of generating interrupts. Interrupts are
generated on Receive Buffer Full and Transmit Buffer Empty. Both interrupts have individual interrupt vectors. Two
bytes of program memory space are reserved for each interrupt vector. The two vectors are located at addresses OxEC
to OxEF Hex in the program memory space. The interrupts
can be individually enabled or disabled using Enable Transmit Interrupt (ETI) and Enable Receive Interrupt (ERI) bits in
the ENUI register.

The interrupt from the receiver is set pending, and remains
pending, as long as both the RBFL and ERI bits are set. To
remove this interrupt, software must either clear the ERI bit
or read from the RBUF register (thus clearing the RBFL bit).

1-366

Baud Clock Generation

o
o

(Continued)

""C

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UART TRANSMIT
CLOCK
~

MUX
+16

PRESCALER
5 BITS
+1 TO +16

BAUD RATE SELECT
11 BITS

CRYSTAL

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UART RECEIVE
CLOCK

TLlDD/11214-25

FIGURE 13. UART BAUD Clock Generation
I--PRESCALER SELECT REGISTER (PSR)

-I-

-I

BAUD REGISTER

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BAUD RATE DIVISOR

SELECT

TL/DD/11214-26

TABLE I. Prescaler Factors
Prescaler
Factor

00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100

NO CLOCK
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5

01101

01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

7.5
8
8.5
9
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
16

""C

FIGURE 14. UART BAUD Clock Divisor Registers

Prescaler
Select

I I I I I -I-I" I I I I I I I I I I -II
I~ PRESCALER

TABLE II. Baud Rate Divisors
(1.8432 MHz Prescaler Output)
Baud
Rate

Baud Rate
Divisor - 1 (N-1)

110 (110.03)
134.5 (134.58)
150
300
600
1200
1800
2400
3600
4800
7200
9600
19200
38400

1046
855
767
383
191
95
63
47
31
23
15
11
5
2

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The entries in Table II assume a prescaler output
of 1.8432 MHz. In the asynchronous mode the
baud rate could be as high as 625k.

As an example, considering the Asynchronous Mode and a
CKI clock of 4.608 MHz, the prescaler factor selected is:
4.608/1.8432 = 2.5
The 2.5 entry is available in Table I. The 1.8432 MHz prescaler output is then used with proper Baud Rate Divisor
(Table II) to obtain different baud rates. For a baud rate of
19200 e.g., the entry in Table II is 5.
N - 1 = 5 (N - 1 is the value from Table II)
N = 6 (N is the Baud Rate Divisor)
Baud Rate = 1.8432 MHz/(16 x 6) = 19200
The divide by 16 is performed because in the asynchronous
mode, the input frequency to the UART is 16 times the baud
rate. The equation to calculate baud rates is given below.
The actual Baud Rate may be found from:
BR = Fc/(16 x N x P)

1-367

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D-

Baud Clock Generation

Note that the framing format for this mode is the nine bit
format; one Start bit, nine data bits, and 7/8, one or two
Stop bits. Parity is not generated or verified in this mode.

(Continued)

Where:

SR is the Baud Rate

.......

Fc is the CKI frequency

Attention Mode

N is the Baud Rate Divisor (Table II).

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P is the Prescaler Divide Factor selected by the value in the
Prescaler Select Register (Table I)

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Note: In the Synchronous Mode, the divisor 16 is replaced by two.

Example:
Crystal Frequency = 5 MHz

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Desired baud rate = 9600
Using the above equation N

x P can be calculated first.

N X P = (5 X 106)/(16 X 9600) = 32.552
Now 32.552 is divided by each Prescaler Factor (Table II) to
obtain a value closest to an integer. This factor happens to
be 6.5 (P = 6.5).

D-

N = 32.552/6.5 = 5.008 (N = 5)

o.......

The programmed value (from Table II) should be 4 (N - 1).

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Asynchronous Mode:

Using the above values calculated for Nand P:
BR

= (5

X 106)/(16 X 5 X 6.5)

= 9615.384

% error = (9615.385 - 9600)/9600 = 0.16

D-

Effect of HALT /IDLE

The UART logic is reinitialized when either the HALT or
IDLE modes are entered. This reinitialization sets the TBMT
flag and resets all read only bits in the UART control and
status registers. Read/Write bits remain unchanged. The
Transmit Buffer (TBUF) is not affected, but the Transmit
Shift register (TSFT) bits are set to one. The receiver registers RBUF and RSFT are not affected.

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D-

Operation of the UART Transmitter is not affected by selection of this Mode. The value of the ninth bit to be transmitted
is programmed by setting XBIT9 appropriately. The value of
the ninth bit received is obtained by reading RBIT9. Since
this bit is located in ENUR register where the error flags
reside, a bit operation on it will reset the error flags.

The device will exit from the HALT/IDLE modes when the
Start bit of a character is detected at the RDX (L3) pin. This
feature is obtained by using the Multi-Input Wakeup scheme
provided on the device.

Comparators
The device contains two differential comparators, each with
a pair of inputs (positive and negative) and an output. Ports
11-13 and 14-16 are used for the comparators. The following
is the Port I assignment:

Before entering the HALT or IDLE modes the user program
must select the Wakeup source to be on the RDX pin. This
selection is done by setting bit 3 of WKEN (Wakeup Enable)
register. The Wakeup trigger condition is then selected to
be high to low transition. This is done via the WKEDG register (Bit 3 is zero.)

11
12
13
14
15
16

If the device is halted and crystal oscillator is used, the
Wakeup signal will not start the chip running immediately
because of the finite start up time requirement of the crystal
oscillator. The idle timer (TO) generates a fixed delay to ensure that the oscillator has indeed stabilized before allowing
the device to execute code. The user has to consider this
delay when data transfer is expected immediately after exiting the HALT mode.

Comparator1
Comparator1
Comparator1
Comparator2
Comparator2
Comparator2

negative input
positive input
output
negative input
positive input
output

A Comparator Select Register (CMPSL) is used to enable
the comparators, read the outputs of the comparators internally, and enable the outputs of the comparators to the pins.
Two control bits (enable and output enable) and one result
bit are associated with each comparator. The comparator
result bits (CMP1 RD and CMP2RD) are read only bits which
will read as zero if the associated comparator is not enabled. The Comparator Select Register is cleared with
reset, resulting in the comparators being disabled. The comparators should also be disabled before entering either the
HALT or IDLE modes in order to save power. The configuration of the CMPSL register is as follows:

Diagnostic
Bits CHARLO and CHARL 1 in the ENU register provide a
loopback feature for diagnostic testing of the UART. When
these bits are set to one, the following occur: The receiver
input pin (RDX) is internally connected to the transmitter
output pin (TDX); the output of the Transmitter Shift Register is "looped back" into the Receive Shift Register input. In
this mode, data that is transmitted is immediately received.
This feature allows the processor to verify the transmit and
receive data paths of the UART.

1-368

~--------------------------------------------------------------------------'O

Comparators

C')

BitO

Note that the two unused bits of CMPSL may be used as
software flags.

1. The GIE (Global Interrupt Enable) bit is reset.
2. The address of the instruction about to be executed is
pushed into the stack.

Comparator outputs have the same spec as Ports Land G
except that the rise and fall times are symmetrical.

SOFTWARE

"'tJ

The device supports a vectored interrupt scheme. It supports a total of fourteen interrupt sources. The following table lists all the possible interrupt sources, their arbitration
ranking and the memory locations reserved for the interrupt
vector for each source.
Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software
interrupt are maskable. Each of the maskable interrupts
have an Enable bit and a Pending bit. A maskable interrupt
is active if its associated enable and pending bits are set. If
GIE = 1 and an interrupt is active, then the processor will
be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described
in the Software Trap sub-section.

CMPSL REGISTER (ADDRESS X'OOB7)
The CMPSL register contains the following bits:
CMP1 EN Enable comparator 1
CMP1 RD Comparator 1 result (this is a read only bit,
which will read as 0 if the comparator is not
enabled)
CMP1 DE
Selects pin 13 as comparator 1 output provided
that CMPIEN is set to enable the comparator
CMP2EN
Enable comparator 2
CMP2RD
Comparator 2 result (this is a read only bit,
which will read as 0 if the comparator is not
enabled)
CMP20E
Selects pin 16 as comparator 2 output provided
that CMP2EN is set to enable the comparator

Bit7

Interrupts

(Continued)

3. The PC (Program Counter) branches to address DOFF.
This procedure takes 7 te cycles to execute.

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en

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TIMER Tl, T2, AND T3

en
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EXTERNAL

MULTI-INPUT WAKE UP
INTERRUPT

j4WIRE/PLUS

FUTURE PERIPHERAL

UART

IDLE TIMER

TLlDD/11214-27

FIGURE 15. Interrupt Block Diagram

1-369

"wcoco

Interrupts (Continued)

0')

a..
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.....

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~

Arbitration
Ranking

(1) Highest

a..

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~

Vector
Address
HI·Low Byte

Software

INTR Instruction

Reserved

for Future Use

OyFC-OyFD

(2)

External

Pin GO Edge

OyFA-OyFB

(3)

Timer TO

Underflow

OyFS-OyF9

(4)

TimerT1

T1A1Underflow

OyF6-0yF7

0')

o
o
.....

Description

Source

OyFE-OyFF

(5)

TimerT1

T1B

OyF4-0yF5

(6)

MICROWIRE/PLUS

BUSY Goes Low

OyF2-0yF3

"cocow

Reserved

for Future Use

OyFO-OyF1

(7)

UART

Receive

OyEE-OyEF
OyEC-OyED

a..
o
.....
co

(S)

UART

Transmit

oo
.....

(9)

TimerT2

T2A1Underflow

OyEA-OyEB

(10)

TimerT2

T2B

OyEB-OyE9

a..

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~

(11)

TimerT3

T3A1Underflow

OyE6-0yE7

(12)

TimerT3

T3B

OyE4-0yE5

o
o

(13)

Port LlWakeup

Port LEdge

OyE2-0yE3

(14) Lowest

Default

VIS Instr. Execution
without Any Interrupts

OyEO-OyE1

a..

.....

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CD

a..
o

Y is VIS page,

y "'" o.

At this time, since GIE = 0, other maskable interrupts are.
disabled. The user is now free to do whatever context
switching is required by saving the context of the machine in
the stack with PUSH instructions. The user would then program a VIS (Vector Interrupt Select) instruction in order to
branch to the interrupt service routine of the highest priority
interrupt enabled and pending at the time of the VIS. Note
that this is not necessarily the interrupt that caused the
branch to address location OOFF Hex prior to the context
switching.

The Software Trap has the highest rank and its vector is
located at OyFE and OyFF.
If, by accident, a VIS gets executed and no interrupt is active, then the PC (Program Counter) will branch to a vector
located at OyEO-OyE1. This vector can point to the Software Trap (Sn interrupt service routine, or to another special service routine as desired.

Figure 15 shows the Interrupt block diagram.
SOFTWARE TRAP

The Software Trap (Sn is a special kind of non-maskable
interrupt which occurs when the INTR instruction (used to
acknowledge interrupts) is fetched from ROM and placed
inside the instruction register. This may happen when the
PC is pointing beyond the available ROM address space or
when the stack is over-popped.

The VIS instruction looks at all the active interrupts at the
time it is executed and performs an indirect jump to the
beginning of the service routine of the one with the highest
rank.

1-370

Interrupts (Continued)

Clock Monitor

o
o

WATCHDOG Operation

WATCHDOG

The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the WATCHDOG service window and match the WATCHDOG key data. Subsequent writes to the WDSVR register
will compare the value being written by the user to the
WATCHDOG service window value and the key data (bits 7
through 1) in the WDSVR Register. Table V shows the sequence of events that can occur.

The device contains a WATCHDOG and clock monitor. The
WATCHDOG is designed to detect the user program getting
stuck in infinite loops resulting in loss of program control or
"runaway" programs. The Clock Monitor is used to detect
the absence of a clock or a very slow clock below a specified rate on the CKI pin.
The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table 11/ shows the WDSVR register.

The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 and 6 of the WDSVR register allow
the user to pick an upper limit of the service window.

Th8 WATCHDOG h=.s =.n ct.!t;Jt.!t ;:::n :.::::~:::.t~d ';:lth It. Thl:.
is the WDOUT pin, on pin 1 of the port G. WDOUT is active
low. The WDOUT pin is in the high impedance state in the
inactive state. Upon triggering the WATCHDOG, the logic
will pull the WDOUT (G1) pin low for an additional 16 te32 te cycles after the signal level on WDOUT pin goes below the lower Schmitt trigger threshold. After this delay, the
device will stop forcing the WDOUT output low.

Table IV shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flexibility in choosing the WATCHDOG service window prevents
any undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5bit Key Data field. The key data is fixed at 01100. Bit a of the
WDSVR Register is the Clock Monitor Select bit.
TABLE III. WATCHDOG Service Register (WDSVR)

I1 I1 IaIa
4

The WATCHDOG service window will restart when the
WDOUT pin goes high. It is recommended that the user tie
the WDOUT pin back to Vee through a resistor in order to
pull WDOUT high.

Clock
Monitor

Key Data

TABLE IV. WATCHDOG Service Window Select
WDSVR
Bit 7

WDSVR
BitS

a
a

1
1

a
1

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G)
........
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The ST has the highest rank among all interrupts.

Window
Select

"'C

The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum specified value, after which the G1 output will enter the high impedance TRI-STATE mode following 16 tc-32 te clock cycles. The Clock Monitor generates a continual Clock Monitor error if the oscillator fails to start, or fails to reach the
minimum specified frequency. The specification for the
Clock Monitor is as follows:

Service Window
(Lower-Upper limits)
2k-8k te Cycles
2k-16k te Cycles
2k-32k te Cycles
2k-64k te Cycles

1/te
1/te
1-371

> 10kHz-No clock rejection.
< 10Hz-Guaranteed clock rejection.

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........

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WATCHDOG Operation

WATCHDOG AND CLOCK MONITOR SUMMARY

The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted: .

• Both the WATCHDOG and CLOCK MONITOR detector
circuits are inhibited during RESET.

00
00

D-

o
.......
UJ
~

(Continued)

• Following RESET, the WATCHDOG and CLOCK MONITOR are both enabled, with the WATCHDOG having he
maximum service window selected.

• The WATCHDOG service window and CLOCK MONITOR enableldisable option can only be changed once,
during the initial WATCHDOG service following RESET.

D-

o
.......

UJ
~

00
00

• The initial WATCHDOG service must match the key data
value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error.

• Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG errors.

D-

• The correct key data value cannot be read from the
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all O's.

D-

o
.......

00
00
00

o
.......

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~

D-

.......

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00
00

D-

• With the single-pin RIC oscillator mask option selected
and the CLKDLY bit reset, the WATCHDOG service window will resume following HALT mode from where it left
off before entering the HALT mode .
• With the crystal oscillator mask option selected, or with
the single-pin RIC oscillator mask option selected and
the CLKDLY bit set, the WATCHDOG service window will
be set to its selected value from WDSVR following HALT.
Consequently, the WATCHDOG should not be serviced
for at least 2048 instruction cycles following HALT, but
must be serviced within the selected window to avoid a
WATCHDOG error.
• The IDLE timer TO is not initialized with RESET.
• The user can sync in to the IDLE counter cycle with an
IDLE counter (TO) interrupt or by monitoring the TOPND
flag. The TOPND flag is set whenever the thirteenth bit of
the IDLE counter 'toggles (every 4096 instruction cycles).
The user is responsible for resetting the TOPND flag.
• A hardware WATCHDOG service occurs just as the device exits the IDLE mode. Consequently, the WATCHDOG should not be serviced for at least 2048 instruction
cycles following IDLE, but must be serviced within the
selected window to avoid a WATCHDOG error.

• The WATCHDOG detector circuit is inhibited during both
the HALT and IDLE modes.

• Following RESET, the initial WATCHDOG service (where
the service window and the CLOCK MONITOR enablel
disable must be selected) may be programmed anywhere within the maximum service window (65,536 instruction cycles) initialized by RESET. Note that this initial WATCHDOG service may be programmed within the
initial 2048 instruction cycles without causing a WATCHDOG error.

1-372

Detection of Illegal Conditions

MICROWIRE/PLUS

The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.

MICROWIRE/PlUS is a serial synchronous communications interface. The MICROWIRE/PlUS capability enables
the device to interface with any of National Semiconductor's
MICROWIRE peripherals (Le. AID converters, display drivers, E2PROMs etc.) and with other microcontrollers which
support the MICROWIRE interface. It consists of an a-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK). Figure 12
shows a block diagram of tile MICROWIRE/PlUS logic.

Reading of undefined ROM gets zeros. The opcode for software interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt,
thus signaling that an illegal condition has occurred.
The SUbroutine stack grows down for each call Uump to
subroutine), interrupt, or PUSH, and grows up for each return or POP. The stack pointer is initialized to RAM location
06F Hex during reset. Consequently, if there are more returns than calls, the stack pointer will point to addresses
070 and 071 Hex (which are undefined RAM). Undefined
RAM from addresses 070 to 07F (Segment 0), 140 to 17F
(Segment 1), and all other segments (Le., Segments 2 ...
etc.) is read as all 1's, which in turn will cause the program
to return to address 7FFF Hex. This is an undefined ROM
location and the instruction fetched (all O's) from this location will generate a software interrupt signaling an illegal
condition.
Thus, the chip can detect the following illegal conditions:
a. Executing from undefined ROM
b. Over "POP"ing the stack by having more returns than
calls.
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that
following reset, but might not contain the same program
initialization procedures). The recovery program should reset the software interrupt pending bit using the RPND instruction.

""C
0)

1-------.

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......
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m

......

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INTERRUPT

~~--~~------.SO

~-~~~~H-----SI

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Q)

m
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......

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Q)
Q)

TL/DD/11214-28

FIGURE 16. MICROWIRE/PlUS Block Diagram
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIREI
PLUS arrangement with the internal clock source is called
the Master mode of operation. Similarly, operating the
MICROWIRE/PLUS arrangement with an external shift
clock is called the Slave mode of operation.
The CNTRl register is used to configure and control the
MICROWIRE/PlUS mode. To use the MICROWIRE/PlUS,
the MSEl bit in the CNTRl register is set to one. In the
master mode, the SK clock rate is selected by the two bits,
SlO and SL1, in the CNTRl register. Table VI details the
different clock rates that may be selected.

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m

TABLE V. WATCHDOG Service Actions
Key

Data

Window
Data

Clock
Monitor

Action
Valid Service: Restart Service Window

Match

Don't Care

Mismatch

Don't Care

Error: Generate WATCHDOG Output

Mismatch

Don't Care

Error: Generate WATCHDOG Output

Don't Care

Mismatch

Error: Generate WATCHDOG Output

TABLE VI. MICROWIRE/PlUS
Master Mode Clock Select
Sl1

SlO

0
0
1

0
1
x

2 X tc
4 X tc

1-373

a x tc

Where tc is the
instruction cycle clock

~r---------------------------------------------------------------~

co
co

MICROWIRE/PLUS (Continued)

MICROWIRE/PLUS OPERATION

.......

w
~

a.
oo
.......
~

w
~

co
co

.......

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co
co

Warning:

~
~

MICROWIRE/PLUS Master Mode Operation

In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally by the device. The
MICROWIRE Master always initiates all data exchanges .
The MSEL bit in the CNTRL register must be set to
enable the SO and SK functions onto the G Port. The SO
and SK pins must also be selected as outputs by setting
appropriate bits in the Port G configuration register. Table
VII summarizes the bit settings required for Master mode of
operation.

.......

co
(D

.......

co
co
(D

o
o

The SIO register should only be loaded when the SK clock
is low. Loading the SIO register while the SK clock is high
will result in undefined data in the SIO register. SK clock is
normally low when not shifting.
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is
low.

Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. A'gure 13 shows
how two devices, microcontrollers and several peripherals
may be interconnected using the MICROWIRE/PLUS arrangements.

MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bits in the Port G configuration register. Table VII summarizes the settings required to enter
the Slave mode of operation.

,/5

I/O
LINES

......
..... ...,.

""IIIIf

CHIP SELECT LINES

•

8 - BIT
A/D
COP43X

EEPROM

DO SK 01
SI
SO

! t
I

-r I

G5
Fun.

Operation

Int. MICROWIRE/PLUS
SK Master

TRIInt. MICROWIRE/PLUS
STATE SK Master
SO

Ext. MICROWIRE/PLUS
SK Slave

TRI- Ext. MICROWIRE/PLUS
STATE SK Slave

•

x
CS

COP8
(MASTER)

G4
Fun.

LCD
DISPLAY.
DRIVER
COP472

VF
DISPLAY
DRIVER

I/O
LINES
COP8
(SLAVE)

DO SK DI

SK 01

SK DI

' -f

SO
SI
SK
TL/DD/11214-29

FIGURE 17. MICROWIRE/PLUS Application

1-374

o
o

Memory Map

"'C

Ol
00
00

All RAM, ports and registers (except A and PC) are mapped into data memory address space.
Address
SIADD REG
0000 to 006F

On-Chip RAM bytes (112 bytes)

0070 to 007F

Unused RAM Address Space (Reads
As All Ones)
Unused RAM Address Space (Reads
Undefined Data)

xx80 to xxAF
xxBO
XXB1
xxB2
xxB3
xxB4
xxB5
xxB6
xxB7
xxB8
xxB9
xxBA
xxBB
xxBC
xxBD
xxBE
xxBF
xxCO
xxC1
xxC2
xxC3
xxC4
xxC5
xxC6
xxC7
xxC8
xxC9
xxCA
xxCB
xxCC
xxCDtoxxCF

Address
SIADD REG

Contents

xxDO
xxD1
xxD2
xxD3
xxD4
xxD5
xxD6
xxD7
xxD8
xxD9
xxDA
xxDB
xxDC
xxDDto OF

Port L Data Register
Port LConfiguration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port 0
Reserved for Port 0

xxEO toxxE5
xxE6

Reserved for EE Control Registers
Timer T1 Autoload Register T1 RB
Lower Byte
Timer T1 Autoload Register T1 RB
Upper Byte
ICNTRL Register
MICROWIRE/PLUS Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1 RA
Lower Byte
Timer T1 Autoload Register T1 RA
Upper Byte
CNTRL Control Register
PSW Register

xxE7
xxE8
xxE9
xxEA
xxEB
xxEC
xxED
xxEE
xxEF

Timer T2 Lower Byte
Timer T2 LJppAr AytA
Timer T2 Autoload Register T2RA
Lower Byte
Timer T2 Autoload Register T2RA
Upper Byte
Timer T2 Autoload Register T2RB
Lower Byte
Timer T2 Autoload Register T2RB
Upper Byte
Timer T2 Control Register
WATCHDOG Service Register
(Reg:WDSVR)
MIWU Edge Select Register
(Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register
(Reg:WKPND)
Reserved
Reserved
Reserved

m
Contents

xxFO io Fa
xxFC
xxFD
xxFE
xxFF

Oil-Chip RAivi iviapped as Registers
X Register
SP Register
B Register
S Register

0100-017F

On-Chip 128 RAM Bytes

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00
0l:Io

o
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00
00
00

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o

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00
00
0l:Io

o
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o
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00
0l:Io

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o
o"'C
<0

00
00

Reading memory locations 0070H-007FH (Segment 0) will return all ones.
Reading unused memory locations 0080H-00AFH (Segment 0) will return
undefined data. Reading memory locations from other unused Segments
(Le., Segment 2, Segment 3, ... etc.) will return all ones.

1-375

w
CX)
CX)

0')

D..

......
CJ
w
~
CX)

0')

D..

This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B
pOinter or X pointer. This is a register indirect mode that
automatically post increments or decrements the B or X register after executing the instruction.

......

~
CX)
CX)

D..

o
......

w
CX)
CX)
CX)

D..

o
......
CJ
w
~
CX)

D..

o
......
CJ
w
CX)
CX)

D..

o
o

Indirect
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower a bits
of PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower a bits of PC) for the jump to the next instruction.
Note: The VIS is a special case of the Indirect Transfer of Control addressing mode, where the double byte vector associated with the interrupt
is transferred from adjacent addresses in the program memory into
the program counter (PC) in order to jump to the associated interrupt
service routine.

Instruction Set
Register and Symbol Definition

Direct
The instruction contains an a-bit address field that directly
pOints to the data memory for the operand.

Registers
A
B

Immediate
The instruction contains an a-bit immediate field as the operand.

X
SP
PC
PU
PL
C
HC
GIE

Short Immediate
This addressing mode is used with the Load B Immediate
instruction. The instruction contains a 4-bit immediate field
as the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower a bits of PC) for accessing a data operand from the
program memory.

VU
VL

TRANSFER OF CONTROL ADDRESSING MODES
Relative
Symbols

This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
program location. JP has a range from -31 to + 32 to allow
a 1-byte relative jump (JP + 1 is implemented by a NOP
instruction). There are no "pages" when using JP, since all
15 bits of PC are used.

[B)

[X]
MD
Mem
Meml

Imm
Reg

Absolute Long

Bit

1-376

Memory Indirectly Addressed by B
Register
Memory Indirectly Addressed by X
Register
Direct Addressed Memory
Direct Addressed Memory or [B)
Direct Addressed Memory or [B) or
Immediate Data
a-Bit Immediate Data
Register Memory: Addresses FO to FF
(Includes B, X and SP)
Bit Number (0 to 7)
Loaded with
Exchanged with

o
o

Instruction Set (Continued)

"'0

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co

INSTRUCTION SET
ADD
ADC

A,Meml
A,Meml

ADD
ADD with Carry

SU8C

A,Meml

Subtract with Carry

AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IF8NE
DRSZ
S81T
R81T
IF81T
RPND

A,Meml
A,lmm
A,Meml
A,Meml
MD,lmm
A,Meml
A,Meml
A,Meml
#
Reg
#,Mem
#,Mem
#,Mem

X
X
LD
LD
LD
LD
LD

A,Mem
A,[X]
A,Meml
A,[X]
8,lmm
Mem,lmm
Reg,lmm

EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD 8 with Immed.
LoaD Memory Immed
LoaD Register Memory Immed.

A~Mem

X
X
LD
LD
LD

A, [8 ±]
A, [X ±]
A, [B±]
A, [X±]
[B±],lmm

EXchange A with Memory [8]
EXchange A with Memory [X]
LoaD A with Memory [8]
LoaD A with Memory [X]
LoaD Memory [B]lmmed.

A ~ [8], (8 +- 8 ± 1)
A ~ [X], (X +- ± 1)
A +- [B], (B +- B ± 1)
A +- [X], (X +- X± 1)
[8] +-Imm, (B +- 8±1)

CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH

A
A
A

CLeaR A
INCrementA
DECrementA
Luau A IIIDi,~t.:i
ROivi
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
SetC
ResetC
IFC
IF NotC
POP the stack into A
PUSH A onto the stack

A+-O
A+-A+1
A+-A-1

PU +- [VU], PL +- [VL]
PC +- ii (ii = 15 bits, 0 to 32k)
PCg ... 0 +- i (i = 12 bits)
PC+-PC + r(ris -31 to +32,except1)
[SP] +- PL, [SP-1] +- PU,SP-2, PC +- ii
[SP] +- PL, [SP-1] +- PU,SP-2, PCg ... 0 +- i
PL +- ROM (PU,A)
SP + 2, PL +- [SP], PU +- [SP-1]
SP + 2, PL +- [SP],PU +- [SP-1]
SP + 2, PL +- [SP]'PU +- [SP-1].GIE +-1
[SP] +- PL, [SP -1] +- PU, SP- 2, PC +- OFF
PC +- PC + 1

VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

['U'"

A
A
A
A

A
A
Addr.
Addr.
Disp.
Addr.
Addr

A+-A + Meml
A +- A + Meml + C, C +- Carry
HC +- Half Carry
A +- A - Meml + C, C +- Carry
HC +- Half Carry
A +- A and Meml
Skip next if (A and Imm) = 0
A +-AorMeml
A +- A xor Meml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A =F Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of 8 =F Imm
Reg +- Reg - 1, Skip if Reg = 0
1 to bit, Mem (bit = 0 to 7 immediate)
Oto bit, Mem
If bit in A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
A~[X]

A+- Meml
A+- [X]
8 +-Imm
Mem+-Imm
Reg +-Imm

'"
o
o

"'0

co
~

'"
o
o"'0
co
co
co

o
'"
o

"'0

co
co
~

'"
o
o

"'0
CD

co
~

o
'"

o"'0
CD

co
co

A ~ ROivi (PU,A)
A +- BCD correction of A (follows ADC, SU8C)
C --. A7 --. ... --. AO --. C
C +- A7 +- ... +- AO +- C
A7 ... A4~A3 ... AO
C +-1, HC +-1
C+-O, HC +- 0
IF C is true, do next instruction
If C is not true, do next instruction
SP +- SP + 1, A +- [SP]
[SP] +- A, SP +- SP - 1

1-377

co
co
CJ)

c..
oo
.......
CJ

-.::r

co
CJ)

Instruction Execution Time
Most instructions are single byte (with immediate addressing mode instructions taking two bytes).
Most single byte instructions take one cycle time to execute.
See the BYTES and CYCLES per INSTRUCTION table for details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle.

c..
.......
CJ
UJ

-.::r

co
co

c..
oo
.......
CJ

co
co
co

c..

.......

-.::r

co
CD

c..
o
.......

Instructions Using A & C

Arithmetic and Logic Instructions

[B)
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFNE
IFGT
IFBNE
DRSZ

1/1
1/1
1/1
1/1

1/1
1/1
1/1
1/1
1/1
1/1

Direct

CLRA
INCA
DECA
LAID
DCOR
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ

Immed.

3/4
3/4
3/4
. 3/4
3/4
3/4
3/4
3/4
3/4

2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2

1/3

SBIT
RBIT
IFBIT

1/1
1/1
1/1

RPND

1/1

3/4
3/4
3/4

1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2

Transfer of Control
Instructions
JMPL
JMP
JP
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP

co
co
CD

, Memory Transfer Instructions

c..
o

1/1
1/1

2/2

Direct Immed.

DC]

[B+,B-]

[X+,X-]

1/3
1/3

1/2
1/2

1/3
1/3

2/3
2/3

2/2
1/1
2/2

3/3
2/3
3/3

(IF B < 16)

(IF B > 15)
2/2

• = > Memory location addressed by B or X or directly.

1-378

3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
117

1/1

Opcode Table

-a

co
co

Upper Nibble Along X-Axis
Lower Nibble Along Y-Axis

JP -15

JP -31

LDOFO, # i

DRSZOFO

JP -14

JP -30

LDOF1, # i

DRSZOF1

JP -13

JP -29

LDOF2, # i

DRSZOF2

JP -12

JP -28

LDOF3, # i

JP -11

JP -27

JP -10

JP -26

JP -9

.......

o-a

ADCA,#i

ADCA,[B]

SUBCA, #i

SUB A,[B]

m
co

XA, [X+]

XA,[B+]

IFEQA,#i

IFEQA,[B]

DRSZOF3

XA, [X-]

XA,[B-]

IFGTA,#i

IFGTA,[B]

LDOF4, # i

DRSZOF4

VIS

LAID

ADDA,#i

ADDA,[B]

LDOF5, # i

DRSZOF5

RPND

JID

ANDA,#i

ANDA,[B]

JP -25

LDOF6, # i

DRSZOF6

XA,[X]

XORA,[B]

JP -8

JP -24

LDOF7, # i

DRSZOF7

XORA,#i
ORA,#i

ORA,[B]

JP -7

JP -23

LDOF8, # i

DRSZOF8

NOP

RLCA

LDA,#i

IFC

JP -6

JP -22

LDOF9, # i

DRSZOF9

IFNE
A,[B]

IFEQ
Md,#i

IFNE
A,#i

IFNC

RRCA

·
·

XA,[B]

.......

o-a
co
co
co
m

.......

o-a
co
co
~
m

.......

JP -5

JP -21

LDOFA, # i

DRSZOFA

LDA,[X+]

LDA,[B+]

LD [B+ ],#i

INCA

o
o

JP -4

JP -20

LDOFB, # i

DRSZOFB

LDA,[X-]

LDA,[B-]

LD [B-],#i

DECA

JP -3

JP -19

LDOFC, # i

DRSZOFC

LD Md,#i

JMPL

XA,Md

POPA

JP -2

JP -18

LDOFD, # i

DRSZOFD

DIR

JSRL

LDA,Md

RETSK

JP -1

JP -17

LDOFE, # i

DRSZOFE

LDA,[X]

RET

o-a

JP -0

JP -16

LDOFF, # i

DRSZOFF

LD [B],#i
LDB,#i

RETI

co
co

LDA,[B]

-a
CD
~

.......

1-379

co
co
m

D..

Opcode Table

(Continued)

Upper Nibble Along X-Axis

o
(.)

Lower Nibble Along Y-Axis

IF81T
O,[B]

ANDSZ
A, #i

LDB,#OF

IF8NEO

JSR
xOOO-xOFF

JMP
xOOO-xOFF

JP +17

INTR

D..

IF81T
1,[B]

LD8,#OE

IF8NE 1

JSR
x100-x1FF

JMP
x100-x1FF

JP +1B

JP + 2

......
~
w

IF81T
2,[8]

LD 8,#OD

IF8NE 2

JSR
x200-x2FF

JMP
x200-x2FF

JP +19

JP + 3

co
co

IF81T
3,[B]

LD8,#OC

IF8NE3

JSR
x300-x3FF

JMP
x300-x3FF

JP +20

JP + 4

o(.)

IF81T
4,[B]

CLRA

. LD 8,#OB

IF8NE4

JSR
x400-x4FF

JMP
x400-x4FF

JP +21

JP + 5

IFBIT
5,[8]

SWAPA

LD 8,#OA

IF8NE 5

JSR
x500-x5FF

JMP
x500-x5FF

JP +22

JP + 6

IF81T
6,[B]

DCORA

LD 8,#09

IF8NE 6

JSR
x600-x6FF

JMP
x600-x6FF

JP +23

JP + 7

IF81T
7,[8]

PUSHA

LD 8,#OB

IFBNE 7

JSR
x700-x7FF

JMP
x700-x7FF

JP +24

JP + B

SBIT
0,[8]

RBIT
0,(8)

LD 8,#07

IFBNEB

JSR
xBOO-xBFF

JMP
xBOO-xBFF

JP +25

JP + 9

o
(.)

SBIT
l,[B]

RBIT
1,[8]

LD 8,#06

IF8NE 9

JSR
x900-x9FF

JMP
x900-x9FF

JP +26

JP + 10

SBIT
2,[B)

RBIT
2,[8]

LD 8,#05

IF8NEOA

JSR
xAOO-xAFF

JMP
xAOO-xAFF

JP +27

JP + 11

SBIT
3,[B]

RBIT
3,[8]

LD 8,#04

IF8NEOB

JSR
x800-x8FF

JMP
x800-xBFF

JP +2B

JP + 12

SBIT
4,[B]

RBIT
4,[8]

LD 8,#03

IFBNEOC

JSR
xCOO-xCFF

JMP
xCOO-xCFF

JP +29

JP + 13

S81T
5,[8]

R81T
5,[B]

LD 8,#02

IFBNEOD

JSR
xDOO-xDFF

JMP
xDOO-xDFF

JP +30

JP + 14

SBIT
6,[8]

R81T
6,[B]

LD 8,#01

IFBNE OE

JSR
xEOO-xEFF

JMP
xEOO-xEFF

JP +31

JP + 15

SBIT
7,[8]

RBIT
7,[8]

LD B,#OO

IFBNE OF

JSR
xFOO-xFFF

JMP
xFOO-xFFF

JP +32

JP + 16

......
~
w
co
m

o(.)
~

D..

......
~
w
co
co
co

D..

o
(.)

......
w
~

D..

......

co
co

D..

o
(.)

Where,
i is the immediate data
Md is a directly addressed memory location
• is an unused opcode
Note: The opcode 60 Hex is also the opcode for IFBIT #i,A

Mask Options
The mask programmable options are shown below. The options are programmed at the same time as the ROM pattern
submission.

OPTION 2: HALT

=1
=2

OPTION 1: CLOCK CONFIGURATION

Disable HALT mode

OPTION 3: BONDING OPTIONS

Crystal Oscillator (CKI/IO)

=1
=2
=3
=4
=5

G7 (CKO) is clock generator
output to crystal/resonator
CKI is the clock input

Enable HALT mode

Single-pin RC controlled
oscillator (CKI/IO)
G7 is available as a HALT
restart and/or general purpose
input

1-3BO

44-Pin PLCC
40-Pin DIP
N/A
2B-Pin DIP
2B-Pin SO

a""D

Development Support
IN-CIRCUIT EMULATOR

The ice MASTER's performance analyzer offers a resolution
of better than 6 J1.s. The user can easily monitor the time
spent executing specific portions of code and find "hot
spots" or "dead code". Up to 15 independent memory areas based on code address or label ranges can be defined.
Analysis results can be viewed in bar graph format or as
actual frequency count.

The ice MASTER provides real time, full speed emulation up
to 10 MHz, 32 kBytes of emulation memory and 4k frames
of trace buffer memory. The user may define as many as
32k trace and break triggers which can be enabled, disabled, set or cleared. They can be simple triggers based on
code or address ranges or complex triggers based on code
address, direct address, opcode value, opcode class or immediate operand. Complex breakpoints can be ANDed and
ORed together. Trace information consists of address bus
values, opcodes and user selectable probe clips status (external event lines). The trace buffer can be viewed as raw
hex or as diassembled instructions. The probe clip bit values
can be displayed in binary, hex or digital waveform formats.

The iceMASTER comes with an easy to use windowed interface. Each window can be sized, highlighted, color-controlled, added, or removed completely. Commands can be
accessed via pull-down-menus and I or redefineable hot
keys. A context sensitive hypertextlhyperlinked on-line help
system explains clearly the options the user has from within
any window.
The ice MASTER connects easily to a PC® via the standard
COMM port and its 115.2 kBaud serial link keeps typical
program download time to under 3 seconds.

The following tables list the emulator and probe cards ordering information.

en
(X)
(X)

G)
........

a""D
en
(X)
~

G)
........

a""D
(X)
(X)
(X)

G)
........

a""D
(X)
(X)
~

G)
........

a""D
CD

(X)
~

........

Emulator Ordering Information
Part Number

IM-COP8/400/1:j:

Current Version

Description
MetaLink base unit in-circuit emulator for all COP8 devices, symbolic debugger software
and RS 232 serial interface cable, with 11 OV @ 60 Hz Power Supply.

IM-COP8/400/2:j:

MetaLink base unit in-circuit emulator for all COP8 devices, symbolic debugger software
and RS 232 serial interface cable, with 220V @ 50 Hz Power Supply.

DM-COP8/888EG:j:

MetaLink iceMASTER Debug Module. This is the low cost version of the MetaLink
iceMASTER. Firmware: Ver, 6.07.

a""D
CD

(X)
(X)

Host Software:
Ver, 3.3 Rev. 5,
Model File
Rev 3.050.

:j:These parts include National's COP6 Assembler/Linker/Librarian Package (COP6-DEV-IBMA).
Probe Card Ordering Information
Part Number

Package

Voltage
Range

SINGLE CHIP EMULATOR DEVICE
The COP8 family is fully supported by One-Time Programmabie (OTP) emulators. For more detailed information refer
to the emulation device specific datasheets and the emu lator selection table below.

Emulates

MHW-888EG44DWPC 44 PLCC 2.5V-5.5V COP888EG
MHW-888EG40DWPC

40 DIP

2.5V-5.5V COP888EG

MHW-884EG28DWPC

28 DIP

2.5V-5.5V COP884EG

MHW-SOIC28

28S0

28-Pin SOIC Adaptor
Kit

Single Chip Emulator Ordering Information

Assembler Ordering Information
Part Number
COP8-DEV-IBMA

Description
COP8
Assemblerl
LinkerlLibrarian
for IBM®
PC/XT®, AT® or
compatible.

Clock
Option

Package

Emulates

COP8788EGV-X
COP8788EGV-R*

Crystal

44 PLCC

COP888EG

COP8788EGN-X
COP8788EGN-R*

Crystal

40 DIP

COP888EG

COP8784EGN-X
COP8784EGN-R*

Crystal

28 DIP

COP884EG

COP8784EGWM-X
COP8784EGWM-R*

Crystal

28S0

COP884EG

Device Number

Manual
424410632-001

RIC
RIC
RIC
RIC

·Check with the local sales office about the availability.

1-381

UI
Q)
Q)
0')

Development Support (Continued)

PROGRAMMING SUPPORT

Programming of the single chip emulator devices is supported by different sources. The following programmers are certified for
programming these One-Time Programmable emulator devices:
EPROM Programmer Information

o
......

UI
'l1l:I'

Q)
0')

Manufacturer
and Product

U.S. Phone
Number

Europe Phone
Number

Asia Phone
Number

MetaLinkDebug Module

(602) 926-0797

Germany:
+49-8141-1030

Hong Kong:
852-737-1800

XeltekSuperpro

(408) 745-7974

Germany:
+49-2041684758

Singapore:
+ 65 276-6433

o
......

BP MicrosystemsTurpro

(800) 225-2102

Germany:
+49898576667

Hong Kong:
+ 852 388-0629

Data I/O-Unisite
-System 29
-System 39

(800) 322-8246

Europe:
+ 31-20-622866
Germany:
+ 49-89-85-8020

Japan:
+ 33-432-6991

......
Cl

UI
'l1l:I'

Q)
Q)

Cl
Q)
Q)
Q)

o
......

Cl
UI
'l1l:I'

o......

Abcom-COP8
Programmer
System GeneralTurpro-1-FX
-APRO

Europe:
+89808707
(408) 263-6667

Switzerland:
+31-921-7844

Taiwan:
+ 2-917 -3005

UI
Q)
Q)

o
o

DIAL-A-HELPER

If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.

Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Bulle-tin Board Information system.

, ORDER PIN: MOLE·DIAL-A·HLP

INFORMATION SYSTEM

Information System Package contains:
Dial-A-Helper Users Manual
Public Domain Communications Software

The Dial-A-Helper system provides access to an au'tomated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system 'capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities could be found. The minimum requirement for accessing the Dial-A-Helper is a Hayes compatible
modem.
Voice:

(800) 272-9959

Modem: CANADA/U.S.: (800) NSC-MICRO
Baud:

14.4k

Set-up:

Length:

8-Bit

Parity:

None

Stop Bit: 1
Operation:

1-382

24 Hrs., 7 Days

tfJ

National Semiconductor

PRELIMINARY

COP888GW
Single-Chip microCMOS Microcontroller
General Description
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconductor's M2CMOSTM process technology. The COP888GW is a
member of this expandable 8-bit core processor family of
microcontrollers.
(Continued)

Features
•
•
•
•
..
•

a
III

•
III

a
iii

Low cost 8-bit microcontroller
Fully static CMOS, with low current drain
Two power saving modes: HALT and IDLE
1 ,...s instruction cycle time
16 kbytes on-board ROM
512 bytes on-board RAM
Single supply operation: 2.5V-6V
Full duplex UART
MICROWIRE/PLUSTM serial I/O
Idle Timer
Two 16-bit timers, each with two 16-bit registers
supporting:
- Processor independent PWM mode
- External event counter mode
- Input capture mode
Four pulse train generators with 16-bit prescalers
Two 16-bit input capture modules with 8-bit prescalers
Multi-Input Wake Up (MIWU) with optional interrupts (8)

• 8-bit Stack Pointer SP (stack in RAM)
• Two 8-bit register indirect data memory pointers
(B and X)
• Fourteen multi-source vectored interrupts servicing
- External Interrupt
- Idle Timer TO
- Two Timers (Each with 2 Interrupts)
- MICROWIRE/PLUS
- Multi-Input Wake Up
- Software Trap
-UART (2)
- Default VIS
- Capture Timers
- Counters (one vector for all four counters)
• Versatile instruction set
.. True bit manipulation
II Memory mapped I/O
III BCD arithmetic instructions
a Multiply/Divide Functions
• Software selectable I/O options
- TRI-STATE@ Output
- Push-Pull Output
- Weak Pull-Up Input
- High Impedance Input
.. Schmitt trigger inputs' on ports G and L
• Temperature range: -40°C to +85°C
II Real time emulation and full program debug offered by
MetaLink Development System

Block Diagram
CLOCK
HALT
IDLE
WAKE UP
RESET

jJC 8-BIT CORE
MODIfIED HARVARD
ARCHITECTURE

II
CPU REGISTERS

~----------------------~
FIGURE 1. COP888GW Block Diagram

1-383

Tl/DD12065-1

co
co
co

General Description

(Continued)

It is a fully static part, fabricated using double-metal silicon
gate microCMOS technology. Features include an 8-bit
memory mapped architecture, MICROWIRE/PLUS serial
I/O, two 16-bit timer/counters supporting three modes
(Processor Independent PWM generation, External Event
counter and Input Capture mode capabilities), four independent 16-bit pulse train generators with 16-bit prescalers, two
independent 16-bit input capture modules with 8-bit prescalers, multiply and divide functions, full duplex UART, and two
power savings modes (HALT and IDLE), both with a multi-

sourced wake up/interrupt capability. This multi-sourced interrupt capability may also be used independent of the
HALT or IDLE modes. Each I/O pin has software selectable
configurations. The devices operate over a voltage range of
2.5V-6V. High throughput is achieved with an efficient, regular instruction set operating at a maximum of 1 J.Ls per instruction rate. The device has low EMI emissions. Low radiated emissions are achieved by gradual turn-on output drivers and internal Icc filters on the chip logic and crystal oscillator. The device is available in 68-pin PLCC package.

Connection Diagram

COP888GW

Vss

Tl/DD12065-2

Top View

1-384

Absolute Maximum Ratings

(Note)
7V

Note: Absolute maximum ratings indicate limits beyond

- 0.3V to Vee + 0.3V

which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

Supply Voltage (Vee)
Voltage at Any Pin
Total Current into Vee Pin (Source)

100mA

Total Current out of GNO Pin (Sink)
Storage Temperature Range

110 rnA
- 65°C to + 150°C

DC Electrical Characteristics COP888GW: -40°C :s: T A :s:
Parameter
Operating Voltage
Power Supply Ripple (Note 1)
Supply Current (Note 2)
CKI = 10 MHz
CKI = 4 MHz
HALT Current (Note 3)
IDLE Current
CKI = 10 MHz
CKI = 4 MHz

Conditions

+ 85°C unless otherwise specified
Min

Typ

2.5
Peak-to-Peak

Vee = 6V, tc = 1 }-Ls
Vee = 2.5V, tc = 2.5}-Ls
Vee = 6V, CKI = 0 MHz

Vee = 6V
Vee = 2.5V

Input Levels (VIH' VIU
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low

Max

Units

6.0
0.1 Vee

V
V

10
1.7
10

rnA
rnA
}-LA

1.7
0.4

rnA
rnA

0.2 Vee

V
V

0.2 Vee

V
V

0.8 Vee

0.7 Vee

Hi-Z Input Leakage

Vee = 6V

-2

}-LA

Input Pullup Current

Vee = 6V, VIN = OV

-40

-250

}-LA

G Port Input Hysteresis

(Note 6)

0.35 Vee

Output Current Levels
Outputs
Source

0.05 Vee

Sink
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage

-0.4

rnA

'Icc - '2..5'/, '!OH - 1.S'J

-0.2

iii';

Vee = 4V, VOL = 1V
Vee = 2.5V, VOL = O.4V

10
2.0

rnA
rnA

Vee = 4V, VOH = 3.3V

Vee
Vee
Vee
Vee
Vee
Vee

= 4V, VOH = 2.7V
= 2.5V, VOH = 1.8V
= 4V, VOH = 3.3V
= 2.5V, VOH = 1.8V
= 4V, VOL = O.4V
= 2.5V, VOL = O.4V

Vee = 6.0V

-10
-2.5
-0.4
-0.2
1.6
0.7

-100
-33

}-LA
}-LA
rnA
rnA
rnA
rnA

-2

}-LA

15
3

rnA
rnA

±200

rnA

Allowable Sink/Source
Current per Pin
Outputs (Sink)
All others

Maximum Input Current
without Latchup (Note 4, 6)

Room Temp

RAM Retention Voltage, VA (Note 5)

500 ns Rise and Fall Time (min)

Input Capacitance

(Note 6)

Load Capacitance on 02

(Note 6)

1000

1-385

3:
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AC Electrical Characteristics COP888GW: -40·C :0;; T A :0;; + 85·C unless otherwise specified
Parameter

D-

o
o

Conditions

Min

Typ

< 4V

2.5

,..,s

1.0

,..,s

Instruction Cycle Time (tC>

Units

Crystal, Resonator

2.5V:O;; Vee

Ceramic

Vee ~ 4V

f
f
f

CKI Clock Duty Cycle (Note 5)
Rise Time (Note 5) Fall Time (Note 5)
Inputs

Max

= Max
= 10 MHz Ext Clock
= 10 MHz Ext Clock

..
Vee ~ 4V

tSETUP

2.5V :0;; Vee

200

< 4V

500

Vee ~ 4V

tHOLO

2.5V !S: Vee
Output Propagation Delay (Note 8)

< 4V

150

= 2.2k, CL = 100 pF

tp01, tpOD
Vee ~ 4V

SO,SK

2.5V !S: Vee

0.7

< 4V

1.8

< 4V

2.5

Vee ~ 4V

All Others

2.5V !S: Vee

MICROWIRETM Setup Time (tuWS) (Note 6)

Vee ~ 4V

MICROWIRE Hold Time (tUWH) (Note 6)

Vee ~ 4V

MICROWIRE Output Propagation Delay (tUPD)

Vee ~ 4V

,..,s

ns
220

Input Pulse Width (Note 7)
Interrupt Input High Time

Interrupt Input Low Time

Timer 1, 2 Input High Time

Timer 1, 2 Input Low Time

Capture Timer High Time

CKI

Capture Timer Low Time

CKI

Reset Pause Width
Note 1: Maximum rate of voltage change to be defined.

Note 2: Supply current is measured after running 2000 cydes with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillatng. Test conditions: All inputs tied to Vee, L, C, E, F, and G port 110's configured as outputs and programmed
low and not driving a load; D outputs programmed low and not driving a load. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.
Part will pull up CKI during HALT in crystal clock mode.
Note 4: Pins G6 and ~ are designed with a high voltage input network. These pins allow Input voltages greater than Vee and the pins will have sink current to
Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vee.) The effective resistance to Vee is 7500
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14 volts. WARNING: Voltages in excess of 14 volts will cause damage
to the pins: This warning excludes ESD transients.
.
Note 5: Condition and parameter valid only for part in HALT mode.
Note 6: Parameter characterized but not tested.
Note 7: Ie = Instruction Cycle Time
Note 8: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

frr:
bl
;

luWH

luPD

FIGURE 2. MICROWIRE/PLUS Timing

1-386

TLlDD12065-3

o
o

Pin Descriptions

Vee and GND are the power supply pins. All Vee and GND
pins must be connected.

PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.

CKI is the clock input. This comes from a crystal oscillator
(in conjunction with CKO). See Oscillator Description section.
RESET is the master reset input. See Reset description
section.

The Port L supports Multi-Input Wake Up on all eight pins.
L1 is used for the UART external clock. L2 and L3 are used
for the UART transmit and receive. L4 and L5 are used for
the timer input functions T2A and T28. L6 and L7 are used
for the capture timer input functions CAP1 and CAP2.

The device contains five bidirectional 8-bit I/O ports (C, E,
F, G and L), where each individual bit may be independently
configured as an input (Schmitt trigger inputs on ports Land
G), output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also
reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O
ports.) Figure 3 shows the I/O port configurations. The
DATA and CONFIGURATION registers allow for each port
bit to be individually configured under software control as
shown below:

The Port L has the following alternate features:

Configuration
Data
Register
Register

Hi-Z Input (TRI-STATE Output)

Input with Weak Pull-Up

Push-Pull Zero Output

Push-Pull One Output

PORT L, G, C, E AND

rl
:!

MIWU

MIWU orCKX

L2
L3

MIWU orTDX

MIWU orT2A

MIWU or T28

MIWU or CAP1

::E

MIWU or RDX

L7 MIWU or CAP2
Port G is an 8-bit port with 6 I/O pins (GO-G5), an input pin
(G6), and a dedicated output pin (G7). Pins GO-G6 all have
Schmitt Triggers on their inputs. Pin G7 serves as the dedicated output pin for the CKO clock output. There are two
registers associated with the G Port, a data register and a
configuration register. Therefore, each of the 6 I/O bits
(GO-G5) can be individually configured under software control.

Port Set-Up

CD
CD
CD

---~·~I. __

.~PIN

DATA
RE_G_IS_TE_R_':----+

+-4- - - - - - '

T
E
R

A
L

~---------------~
PORT D

PORT I
Tl/DD12065-4

FIGURE 3. I/O Port Configurations

1-387

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D-

o
o

X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.

Pin Descriptions (Continued)
Since G6 is an input only pin and G7 is dedicated CKO clock
output pin, the associated bits in the data and configuration
registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits
will return zeros.

SP is the 8-bit stack pOinter, which points to the subroutinel
interrupt stack (in RAM). The SP is initialized to RAM ad.
dress 06F with reset.
S is the 8-bit Data Segment Address Register used to extend the lower half of the address range (00 to 7F) into 256
data segments of 128 bytes each.

All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Progr~m Counter (PC).

Writing a "1" to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock.

G7
G6

Config Reg.

Data Reg.

Not Used
Alternate SK

HALT
IDLE

PROGRAM MEMORY

The program memory consists of' 16384 bytes of ROM.
These bytes may hold program instructions or constant data
(data tables for the LAID instruction, jump vectors for the
JID instruction, and interrupt vectors for the VIS instruction).
The program memory is addressed by the 15-bit program
counter (PC). All interrupts in the devices Vector to program
memory location OFF Hex.

Port G has the following alternate features:
GO

DATA MEMORY

INTR (External Interrupt Input)

T1 B (Timer T1 Capture Input)

T1A (Timer T1 1/0)

SO (MICROWIRE Serial Data Output)

SK (MICROWIRE Serial Clock)

SI (MICROWIRE Serial Data Input)

The data memory address space includes the on~chip RAM
and data registers, the 1/0 registers (Configuration, Data
and Pin), the control registers, the MICROWIRE/PLUS SIO
shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer).
Data memory is addressed directly by the instruction or indirectly by the B, X, SP pointers and S register.

Port G has the following dedicated functions:
G7

The data memory consists of 512 bytes of RAM. Sixteen
bytes of RAM are mapped as "registers" at addresses OFO
to OFF Hex. These registers can be loaded immediately,
and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction. The memory
pointer registers X, SP, Band S are memory mapped into
this space at address locations OFC to OFF Hex respectively, with the other registers being available for general usage.

CKO Oscillator dedicated output

Ports C and Fare 8-bit 1/0 ports.
Port E is an 8-bit 1/0 port. It has the following alternate
features:
EO

CT1 (Output for counter1, Pulse Train Generator)

CT2 (Output for counter2, Pulse Train Generator)

CT3 (Output for counter3, Pulse Train Generator)

CT4 (Output for counter4, Pulse Train Generator)

Port I is an eight-bit Hi-Z input port.
Port 0 is an 8-bit output port that is preset high when
RESET goes low. The user can tie two or more 0 port outputs (except 02) together in order to get a higher drive.

Note: RAM contents are undefined upon power-up.

Data Memory Segment RAM
Extension

Data memory address OFF is used as a memory mapped
location for the Data Segment Address Register (S).
The data store memory is either addressed directly by a
single-byte address within the instruction, or indirectly relative to the reference of the B, X, or SP pointers (each contains a single-byte address). This single-byte address allows
an addressing range of 256 locations from 00 to FF hex.
The upper bit of this single-byte address divides the data
store memory into two separate sections as outlined previously. With the exception of the RAM register memory from
address locations OOFO to OOFF, all RAM memory is memory mapped with the upper bit of the single-byte address being equal to zero. This allows the upper bit of the single-byte
address to determine whether or not the base address
range (from 0000 to OOFF) is extended. If this upper bit
equals one (representing address range 0080 to OOFF),
then address extension does not take place. Alternatively, if
this upper bit equals zero, then the data segment extension

CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or
shift operation in one instruction (tel cycle time.
There are six CPU registers:
A is the 8-bit Aocumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.

1-388

Data Memory Segment RAM Extension

(Continued)

register S is used to extend the base address range (from
0000 to 007F) from XXOO to XX7F, where XX represents the
8 bits from the S register. Thus the 128-byte data segment
extensions are located from addresses 0100 to 017F for
data segment 1, 0200 to 027F for data segment 2, etc., up
to FFOO to FF7F for data segment 255. The base address
range from 0000 to 007F represents data segment O.
.

Figure 4 illustrates how the S register data memory extension is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XXOO
to XX7F. This organization allows a total of 256 data segments of 128-bytes each with an additional upper base segment of 128 bytes. Furthermore, all addressing modes are
available for all data segments. The S register must be
changed under program control to move from one data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory registers, 110 registers,
control registers, etc.) is always available regardless of the
contents of the S register, since the upper base segment
(address range 0080 to OOFF) is independent of data segment extension.

XXFF
XXFO
XXEF

~
~

I/o,

MW,

CNTRL, PSW, A/D,
ICNTRL, MIMU,
AND
UART REGISTERS

...

Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XXOO to XX7F) of
the lower base segment. The additional 384 bytes of RAM
in this device are memory mapped at address locations
0100 to 017P 0200 to 027F, and 0300 to 037F hex.

RAM REGISTERS
(16 BYTES)
INCLUDES B, X, SP, S

TIMERS,

~
...~

The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
112 bytes of RAM are resident from address 0000 to 006F
in the lower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at addresses OOFO to OOFF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.

XX90
XX8F

(Rf' Ar)S IINflEFINED
DATA)

xxao
007F

a
I-

0070
006F

017F
UNUSED'

0000

037F
SEGMENT 2

SEGMENT 3

ON-CHIP RAM
(128 BYTES)

SP INITIALIZED TO 6F

:::l:

027F
SEGMENT 1

ON-CHIP RAM
(112 BYTES)
0100

0200

0300 ' -_ _ _.......
TL/DD/12065-5

"Reads as all ones.

FIGURE 4. RAM Organization

1-389

3:
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D-

Reset
UNAFFECTED after RESET with RC clock option (power
already applied)

This device enters a reset state immediately upon detecting
a logic low on the RESET pin. The RESET pin must be held
low for a minimum of one instruction cycle to guarantee a
valid reset. During power-up initialization, the user must insure that the RESET pin is held low until this device is within
the specified Vee voltage. An RIC circuit on the RESET pin
with a delay 5 times (5x) greater than the power supply rise
time is recommended.

RANDOM after RESET at power-on
MDCR: CLEARED
MDR1, MDR2, MDR3, MDR4, MDR5: RANDOM
WKEN, WKEDG: CLEARED
WKPND: RANDOM

When the RESET input goes low, the 1/0 ports are initialized immediately, with any observed delay being only propagation delay. When the RESET pin goes high, this device
comes out of the reset state synchronously. This device will
be running within two instruction cycles of the RESET pin
going high.

S Register: CLEARED
SP (Stack Pointer): Loaded with 6F Hex
B and X Pointers:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on

RESET may also be used to exit this device from the HALT
mode.

RAM:
UNAFFECTED after RESET with power already applied

Some registers are reset to a known state, whereas other
registers and RAM are "unchanged"· by reset. When the
controller goes into reset state while it is performing a write
operation to one of these registers or RAM that are "unchanged" by reset, the register or RAM value wi!: become
unknown (Le. not unchanged). This is because the write operation is terminated prematurely by reset and the results
become uncertain. These registers and RAM locations are
unchanged by reset only if they are not written to when the
controller resets.

RANDOM after RESET at power-on
The external RC network shown in Figure 5 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.
p

a
w
E
R
S
U
P

The following initializations occur with RESET:
Port L: TRI-STATE

P
L
Y

Port C: TRI-STATE
Port G: TRI-STATE

vee

I
-

COPS

RESET

GND
TL/DD12065-6

Port E: TRI-STATE

RC > 5

Port F: TRI-STATE

POWER SUPPLY RISE TIME

FIGURE 5. Recommended Reset Circuit

Port D: HIGH

Oscillator Circuits

PC: CLEARED

RANDOM after RESET at power-on

The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration), The CKI input frequency is divided down by 10 to produce the instruction
cycle clock (te).

T1 CNTRl: CLEARED

Figure 6 shows the Crystal diagram

PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
UNAFFECTED after RESET with power already applied

T2CNTRL:ClEARED

TxRA, TxRB: RANDOM

CKI

CCMR1, CCMR2: CLEARED

CKO

CM1PSC, CM1CRL, CM1CRH, CM2PSC, CM2CRL, and
CM2CRH:

&&&

UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
CCR1 and CCR2: CLEARED
CxPRH, CxPRL, CxCTH, and CxCTl:
RANDOM after RESET at power-on

TLlDD12065-7

PSR, ENUR and ENUI: CLEARED

FIGURE 6. Crystal Diagram

ENU: CLEARED except Bit 1 (TBMD = 1

CRYSTAL OSCILLATOR

Accumulator, Timer 1 and Timer 2:

CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.

RANDOM after RESET with crystal clock option (power already applied)

1-390

PSW Register (Address X'OOEF)

Oscillator Circuits (Continued)

The PSW register contains the following select bits:

Table I shows the component values required for various
standard crystal values.
TABLE I. Crystal Oscillator Configuration, TA = 25°C
R1
(kil)

R2
(Mil)

C1
(pF)

C2
(pF)

CKI Freq
(MHz)

Conditions

30-36

VCC = 5V

30-36

VCC = 5V

200

100-150

0.455

VCC = 5V

GIE

Global interrupt enable (enables interrupts)

EXEN

Enable external interrupt

BUSY

MICROWIRE/PLUS busy shifting flag

EXPND

External interrupt pending

T1 ENA

Timer T1 Interrupt Enable for Timer Underflow or
T1A Input capture edge

T1 PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1 A capture
edge in mode 3)

Current Drain

Carry Flag

Half Carry Flag

The total current drain of the chip depends on:
1. Oscillator operation mode-11
2. Internal switching current-12
4. Output source current-14
5. DC current caused by external input not at VCC or
GND-15
Thus the total current drain, It, is given as

+ 12 +

T1 PNOA

T1 ENA

EXPNO

BUSY

EXEN

GIE

BitO

ICNTRl Register (Address X'OOE8)

The ICNTRL register contains the following bits:

To reduce the total current drain, each of the above components must be minimum.

T1 EN8

The chip will draw more current as the CKI input frequency
increases up to the maximum 10 MHz value. Operating with
a crystal network will draw more current than an external
Square·wave. Switching current, governed by the equation
below, can be reduced by lowering voltage and frequency.
Leakage current can be reduced by lowering voltage and
temperature. The other two items can be reduced by carefully designing the end-user's system.
12 = C

I I

The Half-Carry flag is also affected by all the instructions
that affect the Carry flag. The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and RC instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
.

3. Internal leakage current-13

It = 11

HC
Bit7

Timer T1 Interrupt Enable for T18 Input capture
edge

T1 PNDB Timer T1 Interrupt Pending Flag for T1 B capture
edge
p.WEN

Enable MICROWIRE/PLUS interrupt

p.WPND MICROWIRE/PLUS interrupt pending

xVxf

where C = equivalent capacitance of the chip

TOEN

Timer TO Interrupt Enable (Bit 12 toggle)

TOPND

Timer TO Interrupt pending

LPEN

L Port Interrupt Enable (Multi-Input Wake up/Interrupt)

Bit 7 could be used as a flag

V - opt:;raUng IiOltagt:l

Unused LPEN TOPNO TOEN WPNO WEN T1 PNOB T1 ENB

f = CKI frequency

Bit7

Control Registers

BitO

T2CNTRl Register (Address X'OOC6)

CNTRl Register (Address X'OOEE)

The T2CNTRL register contains the following bits:

The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:

T2ENB

SL 1 & Select the MICROWIRE/PLUS clock divide by (00 =
SLO
2,01 = 4, 1x = 8)

T2PNDB Timer T2 Interrupt Pending Flag for T2B capture
edge

IEDG External interrupt edge polarity select (0 = Rising
edge, 1 = Falling edge)

T2ENA

MSEL Selects G5 and G4 as MICROWIRE/PLUS signals
SK and SO respectively

T2PNDA Timer T2 Interrupt Pending Flag (Auto reload RA
in mode 1, T2 Underflow in mode 2, T2A capture
edge in mode 3)

T1 CO Timer T1 Start/Stop control in timer modes 1 and 2
T1 Underflow Interrupt Pending Flag in timer mode 3
T1 C1

T1 C3 Timer T1 mode control bit

T1C3
Bit7

T1C2

T1C1

T1CO

MSEL IIEOG

SL1

SLO

Timer T2 Start/Stop control in timer modes 1 and
2 Timer T2 Underflow Interrupt Pending Flag in
timer mode 3

T2C1

Timer T2 mode control bit

T2C2

Timer T2 mode control bit

T2C3

Timer T2 mode control bit

BitO

Timer T2 Interrupt Enable for Timer Underflow or
T2A Input capture edge

T2CO

Timer T1 mode control bit

T1 C2 Timer T1 mode control bit

Timer T2 Interrupt Enable for T2B Input capture
edge

T2C31 T2C21 T2C1
Bit7

1-391

T2CO T2PNOA T2ENA T2PNOB T2ENB
BitO

:;:
CJ

Timers

D-

The device contains a very versatile set of timers (TO, T1,
T2). All timers and associated autoreload/capture registers
power up containing random data.

co
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o
o

user only has to define the parameters of the PWM signal
(ON time and OFF time). Once begun, the timer block will
continuously generate the PWM signal completely independent of the microcontroller. The user software services the
timer block only when the PWM parameters require updating.

The Timer TO supports the following functions:
• Exit out of the Idle Mode (See Idle Mode description)

The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.

• Start up delay out of the HALT mode
The IDLE Timer TO can generate an interrupt when the thirteenth bit toggles. This toggle is latched into the TOPND
pending flag, and will occur every 4 ms at the maximum
clock frequency (te = 1 ,...s). A control flag TOEN allows the
interrupt from the thirteenth bit of Timer TO to be enabled or
disabled. Setting TOEN will enable the interrupt, while resetting it will disable the interrupt.

A"gure 7 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the TxA output pin. The underflows can also be programmed to generate interrupts.
Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control enable flags, TxENA and TxENB, allow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be
reloaded into the timer. Resetting the timer enable flags will
disable the associated interrupts.

TIMER T1 AND TIMER T2
The device has a set of two powerful timer/counter blocks,
T1 and T2. The associated· features and functioning of a
timer block are described by referring to the timer block Tx.
Since the two timer blocks, T1 and T2 are identical, all comments are equally applicable to either of the two timer
blocks.
Each timer block consists of a 16-bit timer, Tx, and two
supporting 16-bit autoreload/ capture registers, RxA and
RxB. Each timer block has two pins associated with it, TxA
and TxB. The pin TxA supports I/O required by the timer
block, while the pin TxB is an input to the timer block. The
powerful and flexible timer block allows the device to easily
perform all timer functions with minimal software overhead.
The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and
Input Capture mode.

Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.
Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that
the timer, Tx, is clocked by the input signal from the TxA pin.
The Tx timer control bits, TxC3, TxC2 and TxC1 allow the
timer to be clocked either on a positive or negative edge
from the TxA pin. Underflows from the timer are latched into
the TxPNDA pending flag. Setting the TxENA control flag
will cause an interrupt when the timer underflows .

The control bits TxC3, TxC2, and TxC1 allow selection of
the different modes of operation.
Mode 1. Processor Independent pWM Mode
As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention. The

.TIMER
UNDERFLOW
INTERRUPT

1-----.

TxA

\C-------'

TL/DD12065-8

FIGURE 7. Timer In PWM Mode

1-392

(')

Timers

a"1J

(Continued)

Q)
Q)
Q)

=E
TIMER
UNDERFLOW
INTERRUPT . .- - - - . . . . ,

TxAIXJ---H

TX8~TO

Interrupt Control
TLlDD12065-9

FIGURE 8. Timer In External Event Counter Mode
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag TxENA allows the interrupt on TxA to be either enabled or disabled. Setting the TxENA flag enables interrupts to be generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.

In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
Figure 8 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock.

Mode 3. Input Capture Mode

The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode.
In this mode, the timer Tx is constantly running at the fixed
tc rate. The two registers, RxA and RxB, act as capture
registers. Each register acts in conjun"ction with a pin. The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin.
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently.

Figure 9 shows a block diagram of the timer in Input Capture
mode.

A
T
A

TLlDD12065-10

FIGURE 9. Timer in Input Capture Mode

1-393

Meml
Do next if lower 4 bits of B =1= Imm
Reg ~ Reg - 1, Skip if Reg = 0
1 to bit, Mem (bit = 0 to 7 immediate)
Oto bit, Mem
If bit #, A or Mem is true do next instruction
Reset Software Interrupt Pending Flag

X
X
LD
LD
LD
LD
LD

A,Mem
A,[X]
A,Meml
A,[X]
B,lmm
Mem,lmm
Reg,lmm

EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD B with Immed.
LoaD Memory Immed.
LoaD Register Memory Immed.

A~Mem

X
X
LD
LD
LD

A, [B±]

EXchange A with Memory [B)
EXchange A with Memory [X]
LoaD A with Memory [B)
LoaD A with Memory [X]
LoaD Memory [B] Immed.

A~ [8],(B~8

CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH

A
A
A

CLeaR A
INCrementA
DECrement A
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
SetC
ResetC
IFC
IF NotC
POP the stack into A
PUSH A onto the stack

A~O

PU ~ [VU], PL ~ [VL]
PC ~ ii (ii = 15 bits, 0 to 32k)
PCg ... 0 ~ i (i = 12 bits)
PC ~ PC + r (r is -31 to +32, except 1)
[SP] ~ PL, [SP - 1] ~ PU, SP - 2, PC ~ ii
[SP] ~ PL, [SP - 1] ~ PU, SP - 2, PCg ... 0 ~ i
PL ~ ROM (PU, A)
SP + 2, PL ~ [SP], PU ~ [SP - 1]
SP + 2, PL ~ [SP], PU ~ [SP - 1], skip next instruction
SP + 2, PL ~ [SP], PU ~ [SP - 1], GIE ~ 1
[SP] ~ PL, [SP - 1] ~ PU, SP - 2, PC ~ OFF
PC~ PC + 1

VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

A, [X±]
A, [B±]
A, [X±]
[B±],lmm

A
A
A
A

A
A
Addr.
Addr.
Disp.
Addr.
Addr

A~[X]
A~Meml

A~[X]
B~lmm
Mem~lmm
Reg~lmm

± 1)
1)
A~ [B],(B~B ± 1)
A~ [X],(X~X ± 1)
[B) ~ Imm,·(B ~ 8 ± 1)
A~[X],(X~X±

A~A+

A~A-1

A ~ ROM (PU, A)
A ~ BCD correction of A (follows ADC, SUBC)
C ---+ A 7 ---+ ... ---+ AO ---+ C
C~A7~ ... ~ AO~C
A7 ... A4 ~ A3 ... AO
C~1,HC~1
C~O,HC~O

If C is true, do next instruction
If C is not true, do next instruction
SP~SP + 1,A~ [SP]
[SP] ~ A, SP ~ SP - 1

1-418

a"0

Instruction Execution Time
Most instructions are single byte (with immediate addressing mode instructions taking two bytes).

(X)
(X)
(X)

Most single byte instructions take one cycle time to execute.

See the BYTES and CYCLES per INSTRUCTION table for details.

Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
[B)

Direct

Immed.

ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4

2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2

SBIT
RBIT
IFBIT

1/1
1/1
1/1

3/4
3/4
3/4

RPND

1/1

Instructions Using A & C

1/3

Transfer of Control Instructions

1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
. 1/1
1/3
1/3
2/2

CLRA
INCA
DECA
LAID
DCORA
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ

JMPL
JMP
JP
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP

3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
117
1/1

Memory Transfer Instructions
Register
Indirect

XA, •
LOA, •
LD!3, Iiii iii
LDB,lmm
LDMem,lmm
LD Reg, Imm
IFEQMD,lmm
Note: •

[B)

[X]

1/1
1/1

1/3
1/3

212

Direct

2/3
2/3

Immed.

212

[X+,X-]

1/2
1/2

1/3
1/3

iii

(IF B < 16)

212

(IF B

3/3
2/3
3/3

> 15)

212

= > Memory location addressed by B or X or directly.

1-419

COP888GW

Opcode List
Bits 7·4
D

LD OFO, #i

DRSZOFO

RRCA

ADCA,
#i

ADCA,[B]

IFBIT ANDSZ
O,[B]
A, #i

JP -14 JP -30 LDOF1, #i

DRSZOF1

SUBCA,
#i

SUB A,[B]

IFBIT
1,[B]

JP -13 JP -29 LD OF2, #i

DRSZOF2

XA,
[X+]

XA,
[B+]

IFEQA,
#i

JP -12 JP -28 LD OF3, #i

DRSZOF3

XA,
[X-]

XA,
[B-]

JP -11

JP -27 LDOF4, #i

DRSZOF4

VIS

JP -10 JP -26 LD OF5, #i

DRSZOF5

RPND

JP -15 JP -31

.....
.;,.

XA,[X]

JP -9

JP -25 LDOF6, #i

DRSZOF6

JP -8

JP -24 LDOF7, #i

DRSZOF7

JP -7

JP -23 LDOF8, #i

DRSZOF8

NOP

IFBNEO

JSR
xOOO-xOFF

JMP
xOOO-xOFF

JP +17

INTR

LD B, OE IFBNE 1

JSR
x100-x1FF

JMP
x100-x1FF

JP +18

JP + 2

IFEQA,[B] IFBIT
2,[B]

LD B,OD IFBNE2

JSR
x200-x2FF

JMP
JP +19
x200-x2FF

JP + 3

IFGTA,
#i

IFGTA,[B] IFBIT
3,[B]

LD B, OC IFBNE3

JSR
x300-x3FF

JMP
JP +20
x300-x3FF

JP + 4

LAID

ADDA,
#i

ADDA,[B]

IFBIT
4,[B]

CLRA

LD B, OB IFBNE4

JSR
x400-x4FF

JMP
JP +21
x400-x4FF

JP + 5

JID

ANDA,
#i

AND A, [B)

IFBIT SWAPA LD B,OA IFBNE 5
5,[B]

JSR
x500-x5FF

JMP
JP +22
x500-x5FF

JP + 6

XA,[B]

XORA,
#i

XORA,[B]

IFBIT DCORA LDB,9
6,[B]

IFBNE6

JSR
x600-x6FF

JMP
JP +23
x600-x6FF

JP + 7 - 6

ORA,#i

ORA,[B]

IFBIT PUSHA LDB,8
7,[B]

IFBNE7

JSR
x700-x7FF

JMP
x700-x7FF

JP +24

JP + 8

RLCA

LDA,#i

IFC

SBIT
O,[B]

RBIT
O,[B]

LDB,7

IFBNE8

JSR
x800-x8FF

JMP
x800-x8FF

JP +25

JP + 9

JMP
x900-x9FF

JP +26 JP + 10 9

LD B, OF

I\)

JP -22 LDOF9, #i

DRSZOF9

IFNE
A,[B]

IFEQ
Md,#i

IFNE
A,#i

IFNC

SBIT
1,[B]

RBIT
1,[B]

LDB,6

IFBNE9

JSR
x900-x9FF

JP -5

JP -21

LDOFA, #i

DRSZOFA

LDA,
[X+]

LDA,
[B+]

LD [B+],
#i

INCA

SBIT
2,[B]

RBIT
2,[B]

LDB,5

IFBNEOA

JMP
JSR
JP+27 JP + 11
xAOO-xAFF xAOO-xAFF

JP -4

JP -20 LDOFB, #i

DRSZOFB

LDA,
[X-]

LDA,
[B-]

LD [B-]'
#i

DECA

SBIT
3,[B]

RBIT
3,[B]

LDB,4

IFBNEOB

JSR
JMP
JP +28 JP + 12 B
xBOO-xBFF xBOO-xBFF

JP -3

JP -19 LDOFC, #i

DRSZOFC LD Md,#i

JMPL

XA,Md

POPA

SBIT
4,[B]

RBIT
4,[B]

LDB,3

IFBNEOC

JSR
JMP
JP +29 JP + 13 C
xCOO-xCFF xCOO-xCFF

JP -2

JP -18 LDOFD, #i

DRSZOFD

DIR

JSRL

LDA,Md

RETSK

SBIT
5,[B]

RBIT
5,[B]

LDB,2

IFBNEOD

JSR
JMP
JP +30 JP + 14 D
xDOO-xDFF xDOO-xDFF

JP -1

JP -17 LDOFE, #i

DRSZOFE

LDA,[X]

RET

SBIT
6,[B]

RBIT
6,[B]

LD B,1

IFBNEOE

JSR
JMP
JP +31
xEOO-xEFF xEOO-xEFF

JP -0

JP -16 LDOFF, #i

DRSZOFF

RETI

SBIT
7,[B]

RBIT
7,[B]

LDB,O

IFBNEOF

JSR
xFOO-xFFF

Where,

LDA,[B] LD [B],#i

LDB,#i

m
ijf
(0)

JP -6

JP + 15 E
I

JMP
JP +32 JP + 16 F
xFOO-xFFF
I

# i is the immediate data
Md is a directly addressed memory location
• is an unused opcode

Note: The opcode 60 Hex is also the opcode for IFBIT #i,A.
-

Mask Options
The mask programmable options are shown below. The options are programmed at the same time as the ROM pattern
submission.
OPTION 1: CLOCK CONFIGURATION
= 1

Crystal Oscillator (CKI/10)

G7 (CKO) is clock generator output to crystal/resonator with CKI being the clock input
OPTION 2: HALT
= 1

Enable HALT mode

= 2

Disable HALT mode

OPTION 3: BONDING OPTIONS
= 1

The iceMASTER connects easily to a PCRM via the standard COMM port and its 115.2 kBaud serial link keeps typi·
cal program download time to under 3 seconds.

6S Pins PLCC

Development Support

The following tables list the emulator and probe cards ordering information.

IN·CIRCUIT EMULATOR

Emulator Ordering Information

The MetaLink iceMASTERTM-COPS Model 400 In-Circuit
Emulator for the COPS family of microcontrollers features
high-performance operation, ease of use, and an extremely
flexible user-interface for maximum productivity. Interchangeable probe cards, which connect to the standard
common base, support the various configurations and packages of the COPS family.
The iceMASTER provides real-time, full-speed emulation up
to 10 MHz, 32 kBytes of emulation memory and 4k frames
of trace buffer memory. The user may define as many as
32k trace and break triggers which can be enabled, disabled, set or cleared. They can be simple triggers based on
code or address ranges or complex triggers based on code
address, direct address, opcode value, opcode class or immediate operand. Complex breakpoints can be ANDed and
ORed together. Trace information consists of address bus
values, opcodes and user-selectable probe clips status (external event lines). The trace buffer can be viewed as raw
hex or as disassembled instructions. The probe clip bit values can be displayed in binary, hex or digital waveform formats.

Part Number

Description

IM-COPS/400/1:j:

MetaLink base unit incircuit emulator forall
COPS devices,
symbolic debugger
software and RS232
serial interface cable,
with 110V @ 60 Hz
Power Supply.

IM-COPS/400/2:j:

MetaLink base unit incircuit emulator for all
COPS devices,
symbolic debugger
software and RS232
serial interface cable,
with 220V @ 50 Hz
rC';;~j"

Current
Version

Host
Software:
Ver3.3
Rev. 5,
Model File
Rev 3.050.

Supp!y.

:t:These parts include National's COPS Assembler/Linker/Librarian Package
(COPS-DEV-IBMA).

Probe Card Ordering Information
Part Number

The ice MASTER's performance analyzer offers a resolution
of better than 6 J.l-s. The user can easily monitor the time
spent executing specific portions of code and find "hot
spots" or "dead code". Up to 15 independent memory areas based on code address or label ranges can be defined.
Analysis results can be viewed in bar graph format or as
actual frequency count.

Package

Voltage
Range

Emulates

MHW-SSSGW6SPWPC 6S PLCC 2.5V-6.0V COPSSSGW
MACRO CROSS ASSEMBLER

National Semiconductor offers a COPS macro cross assembler. It runs on industry standard compatible PCs and supports all of the full-symbolic debugging features of the
MetaLink ice MASTER emulators.

1-421

3:
C!J

co
co
co
D-

Development Support (Continued)
If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.

Assembler Ordering Information
Part Number
COP8-DEV-IBMA

Description
COP8
Assembler/
Linker/Librarian
for IBM®
PC/XT®, A T® or
compatible.

Manual
424410632-001

Order PIN: MDS-DIAL-A-HLP
Information System Package Contains
Dial-A-Helper User's Manual
Public Domain Communications Software

Factory Applications Support

DIAL-A-HELPER

Dial-A-Helper also provides immediate factor applications
support. If a user has questions, he can leave messages on
our electronic bulletin board, which we will respond to.

Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Bulletin Board Information System.

1-422

Voice:

(800) 272-9959

Modem:

CANADA/US.:

(800) NSC-MICRO
(800) 672-6427

Baud:

14.4k

Set-Up:

Length: 8-Bit
Parity:
None
Stop Bit 1

Operation:

24 Hours, 7 Days

(")

a'"0
CD

tflNational Semiconductor

........

(")

.......

COP8780C/COP8781 C/COP8782C
Single-Chip EPROM/OTP Microcontrollers
General Description
The COP8780C, COP8781C and COP8782C are members
of the COPSTM 8-bit microcontroller family. They are fully
static microcontrollers, fabricated using double-metal, double poly silicon gate microCMOS EPROM technology.
These devices are available as UV erasable or One Time
Programmable (OTP). These low cost microcontrollers are
complete microcomputers containing all system timing, interrupt logic, EPROM, RAM, and I/O necessary to implement dedicated control functions in a variety of applications.
Features include an 8-bit memory mapped architecture, MICROWIRE/PLUSTM serial I/O, a 16-bit timer/counter with
associated 16-bit autoreload/capture register, and a multisourced interrupt. Each I/O pin has software selectable options to adapt the device to the specific application. These
devices operate over a voltage range ot 4.5V to 6.0V. An
efficient, regular instruction set operating at a 1 ,..,S instruction cycle rate provides optimal throughput.
The COP8780C, COP8781C and COP8782C can be configured to EMULATE the COP880C, COP840C and COP820C
microcontrollers.

Features
1:1 Low cost 8-bit microcontroller
1:1 Fully static CMOS
1:1 4096 x 8 on-chip UV erasable or OTP EPROM
1:1 EPROM security
1:1 128 or 64 bytes of on-chip RAM, user configurable
1:1 Crystal, RC or External Oscillator, user configurable
n 1 I'~ instruction tim~ (10 MH~ dock)
Ell Low current drain
II Extra-low current static HALT mode

Block Diagram

(")

a'"0
CD

• Single supply operation: 4.5V to 6.0V
• 8-bit stack pointer (stack in RAM)
• 16-bit read/write timer operates in a variety of modes
- PWM (Pulse Width Modulation) mode with 16-bit autoreload register
'-- External Event Counter mode, with selectable edge
- Input Capture mode (selectable edge) with 16-bit
capture register
• Multi-source interrupt
- External interrupt with selectable edge
- Timer interrupt or capture interrupt
- Software interrupt
II Powerful instruction set, with most instructions single
byte
a Many single byte, single cycle instructions
1:1 BCD arithmetic instructions
Ell MICROWIRE/PLUS serial I/O
1:1 Software selectable I/O options (TRI-STATE, push-pull,
weak pull-up)
13 Temperature ranges: -40°C to +85°C
Ell Schmitt trigger inputs on G port
1:1 COP8780C EPROM Programming fully supported by different sources
a Packages:
- 44 PLCC, OTP, Emulates COP880C, 36 I/O pins
- 40 DIP, OTP, Emulates COP880C, 36 I/O pins
- 28 DIP, OTP, Emulates COP820C/840C/881C,
24 I/O pins
- 20 DIP, OTP, Emulates COP822C/842C, 16 I/O pins
- 28 SO, 20 SO, OTP
- 44 LDCC, UV Erasable
- 40 CERDIP, 28 CERDIP, 20 CERDIP, UV Erasable

........
CD
......

(")

.......
(")

a'"0
CD

........
CD

(")

r----,

II
TLlDD/11299-1

FIGURE 1

1-423

oC'I

co
r-..
co

D-

COP8780C/COP8781 C/COP8782C

Absolute Maximum Ratings

o..-

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications •

D-

Supply Voltage (Vee>
Programming Voltage Vpp (RESET pin)
and ME (pin G6)

o
.......

co
r-..
co

O
o
.......
oo
CO

r-..

Voltage at any Pin

50mA
60mA
- 65·C to + 150·C

7V
13.4V

-0.3V to Vee + 0.3V

DC Electrical Characteristics COP87XXC; -40·C ~ TA ~

D-

. Parameter

Total Current into Vee Pin (Source)
Total Current out of GND Pin (Sink)

Condition

Operating Voltage
Power Supply Ripple (Note 1)

Peak to Peak

Supply Current
CKI = 10 MHz (Note 2)
HALT Current (Note 3)

Vee
Vee

= 6V, tc = 1 ).Ls
= 6V, CKI = 0 MHz

Max

Units

6.0
0.1 Vee

V
V

21
10

mA
).LA

0.1 Vee

V
V

0.2 Vee

V
V

+2
-250

).LA
).LA

0.9 Vee

0.7 Vee

= 6.0V
= 6.0V, VIN = OV

Hi-Z Input Leakage
Input Pullup Current

Vee
Vee

G Port Input Hysteresis

(Note 6)

-2
-40

0.05 Vee

Vee
Vee

= 4.5V, VOH = 3.8V
= 4.5V, VOL = 1.0V

-0.4
10

Vee
Vee
Vee

= 4.5V, VOH = 3.2V
= 4.5V, VOH = 3.8V
= 4.5V, VOL = O.4V

-10
-0.4
1.6
-2.0

Allowable Sink/Source
Current per Pin
D Outputs (Sink)
All Others
Maximum Input Current (Notes 4,6)
without Latchup (Room Temp)

Typ

4.5

Input Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low

Output Current Levels
D Outputs
Source
Sink
All Others
Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage

+ 85·C unless otherwise specified
Min

Room Temp

RAM Retention Voltage, Vr
(Note 5)

mA
mA
-110

+2.0

).LA
mA
mA
).LA

15
3

mA
mA

±200

2.0

Input Capacitance

(Note 6)

Load Capacitance on D2

(Note 6)

1000

Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the crystal configurations. Halt test conditions: All Inputs tied to VCC. L, C, and G port 110's
configured as outputs and programmed low; D outputs programmed low; the window for UV erasable packages is completely covered with an opaque cover to
prevent light from falling onto the die during HALT mode test. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.
Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than Vee and the pins will
have sink current to Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vecl. The effective
resistance to Vec is 750n (typ). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously.
Note 6: Parameter characterized but not tested.
Note 1:

1-424

a-a

COP8780C/COP8781 C/COP8782C
AC Electrical Characteristics

-40°C

Parameter

......
Q)

< T A < + 85°C unless otherwise specified
Condition

Instruction Cycle Time (tel
Crystal/Resonator or External Clock
R/C Oscillator Mode

Vee ~ 4.5V
Vee ~ 4.5V

CKI Clock Duty Cycle (Note 7)
Rise Time (Note 7)
Fall Time (Note 7)

fr = Max
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock

Min

Typ

3
45

Max

Units

DC
DC

p.s
p's

55
12
8

%
ns
ns

0
0

a-a
Q)

......
Q)
.......

0
0

a-a
Q)

Inputs
Vee ~ 4.5V
Vee ~ 4.5V

tSETUP
tHOLD
Output Propagation Delay
tpD1, tpDO
SO,SK
All Others

200
60

ns
ns

......
Q)
N

CL = 100 pF, RL = 2.2 k!1
Vee ~ 4.5V
Vee ~ 4.5V

0.7
1

MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output
Propagation Delay (tUPD)

ns
ns

20
56
220

Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
Reset Pulse Width

p's
p's

1
1
1
1

tc
tc
tc
tc

1.0

p.s

Note 7: Parameter guaranteed by design, but not tested.

Ie = Instruction Cycle Time.

Timing Diagram

5K~LJ

£I=x=
!=:i
WS

*uWh

x=:
\uPD

TLlDD/l0802-2

FIGURE 2. MICROWIRE/PLUS Timing

1-425

co
I"co
c..

0
0
"0

.....

co
I"co
c..

0
0
"0
0

co
I"co
c..

0
0

Connection Diagrams

:.::
u

G4/S0

G3/T10

G5/SK

G6/SI

.......

'"
(.!)

CKI

GNO

(.!)

>=
.......
",
(.!)

N
(.!)

(;

43 42 41
GO/INT
RESET

Vee

RESET

Vee

:.::

.......
.......
..,.
If)

CKI

GO/INT

G7/CKO

~
(.!)

GNO

05
04

01
00

15
16

03
31

18 19 20

::::; ~ ~ uz

u
Z

..,.
...J

~
TLlDD/11299-4

Top View
COP8780CV, COP8780CEL

L4
TLlDD/11299-3

Top View
COP8780CN, COP8780CJ

G4/S0

G3/T10

G4/S0

G5/SK

G3/T10
G2

G6/SI

Gl
GO/INT

G5/SK

G7/CKO

G6/SI

CKI

RESET

G7/CKO

GO/INT

Vee

GNO

CKI

RESET

GNO

00
L7

Vee

L2
L3

TL/DD/11299-5

Top View
COP8782CN, COP8782CWM,
COP8782CJ

TLlDD/11299-6

Top View
COP8781CN, COP8781 CWM
COP8781CJ
FIGURE 3. Connection Diagrams

1-426

a"'D

Pin Descriptions

Q:)

Pins G1 and G2 currently do not have any alternate functions.

Vee and GND are the power supply pins.
CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunction with CKO). See Oscillator description.

PORT 0 is an B-bit output port that is preset high when
RESET goes low. Care must be exercised with the 02 pin
operation. At reset, the external load on this pin must ensure that the output voltage stay above 0.7 Vee to prevent
the chip from entering special modes. Also, keep the external loading on 02 to less than 1000 pF.

RESET is the master reset input. See Reset description.
PORT I is an B-bit Hi-Z input port. The 2B-pin device does
not have a full complement of PORT I pins. The unavailable
pins are not terminated i.e., they are floating. A read operation for these unterminated pins will return unpredictable
values. The user must ensure that the software takes this
into account by either masking or restricting the accesses to
bit operations. The unterminated PORT I pins will draw power only when addressed.
PORT L is an B-bit I/O port.
PORT C is a 4-bit I/O port.

ALU AND CPU REGISTERS

Three memory locations are allocated for the L, G and C
ports, one each for data register, configuration register and
the input pins. Reading bits 4-7 of the C-Configuration register, data register, and input pins returns undefined data.

The ALU can do an B-bit addition, subtraction, logical or
shift operation in one cycle time.

Ports Land C Setup

0
0
1
1

0
1
0
1

Hi-Z Input (TRI-STATE Output)
Input with Pull-Up (Weak One Output)
Push-Pull Zero Output
Push-Pull One Output

Port G Setup

0
1
0
1

Hi-Z Input (TRI-STATE Output)
Input with Pull-Up (Weak One Output)
Push-Pull Zero Output
Push-Pull One Output

a"'D
Q:)

.......

Q:)

PU is the upper 7 bits of the program counter (PC)
B is the B-bit address register, can be auto incremented or
decremented.
X is the B-bit alternate address register, can be incremented
or decremented.
SP is the B-bit stack pointer, which points to the subroutine/
interrupt stack in RAM. The SP must be initialized with software (usually to RAM address 06F Hex with 12B bytes of
on-chip RAM selected, or to RAM address 02F Hex with 64
bytes of on-chip RAM selected). The SP is used with the
subroutine call and return instructions, and with the interrupts.
B, X and SP registers are mapped into the on-chip RAM.
The B and X registers are used to address the on-chip RAM.

There are two registers associated with the G port: 8. rigtg
register and a configuration register. Therefore, each G port
bit can be individually configured under software control as
shown below:

Data

o
.......

PL is the lower B bits of the program counter (PC)

PORT G is an B-bit port with 6 I/O pins (GO-G5) and 2 input
pins (G6, G7). All eight G-pins have Schmitt Triggers on the
inputs.

0
0
1
1

Q:)

.......
Q:)
.......

A is the B-bit Accumulator register

On the 20- and 2B-pin parts, it is recommended that all bits
of Port C be configured as outputs to minimize current.

Config.

a"'D

There are five CPU registers:

There are two registers associated with the Land C ports: a
data register and a configuration register. Therefore, each L
and C I/O bit can be individually configured under software
control as shown below:

Data

Q:)

o
.......
o

Functional Description
Figure 1 shows the block diagram of the internal architecture. Data paths are illustrated in simplified form to depict
how the various logic elements communicate with each other in implementing the instruction set of the device.

Con fig.

.......

Th: SP

r~~!:;t:i'

::; u::d to u.ddi\::;::; tho

5tQC~

r:A~v~

dUiing

subroutine calls and returns.

PROGRAM MEMORY
The device contains 4096 bytes of UV erasable or OTP
EPROM memory. This memory is mapped in the program
memory address space from 0000 to OFFF Hex. The program memory may contain either instructions or data constants, and is addressed by the 15-bit program counter (PC).
The program memory can be indirectly read by the LAID
(Load Accumulator Indirect) instruction for table lookup of
constant data.

Since G6 and G7 are input only pins, any attempt by the
user to configure them as outputs by writing a one to the
configuration register will be disregarded. Reading the G6
and G7 configuration bits will return zeros. The device will
be placed in the HALT mode by writing a one to the G7 bit in
the G-port data register.

All locations in the EPROM program memory will contain
OFF Hex (all 1's) after the device is erased. OTP parts are
shipped with all locations already erased to OFF Hex. Unused EPROM locations should always be programmed to 00
Hex so that the software trap can be used to halt runaway
program operation.

Six pins of Port G have alternate features:

The device can be configured to inhibit external reads of the
program memory. This is done by programming the security
bit in the ECON (EPROM configuration) register to zero. See
the ECON REGISTER section for more details.

GO INTR (an external interrupt)
G3 TIO (timer/counter input/output)
G4 SO (MICROWIRE/PLUS serial data output)
G5 SK (MICROWIRE/PLUS clock I/O)

DATA MEMORY

G6 SI (MICROWIRE/PLUS serial data input)

The data memory address space includes on-chip RAM,
I/O, and registers. Data memory is addressed directly by
instructions, or indirectly by means of the B, X, or SP point-

G7 CKO crystal oscillator output (selected by programming
the ECON register) or HALT Restart/general purpose
input

1-427

o
N
co
......

co
c..

......

o,....
co
......
co
c..

......
o
o
CO
......
CO

c..

Functional Description

(Continued)

ers. The device can be configured to have either 64 or 128
bytes of RAM, depending on the value of the "RAM SIZE"
bit in the ECON (EPROM CONFIGURATION) register. The
sixteen bytes of RAM located at data memory address OFOOFF are designated as "registers". These sixteen registers
can be decremented and tested with the DRSZ (Decrement
Register and Skip if Zero) instruction.

RESET
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the Ports L, G and Care
placed in the TRI-STATE mode and the Port 0 is set high.
The PC, PSW and CNTRL registers are cleared. The data
and configuration registers for Ports L, G and C are cleared.

The three pointers X, B, and SP are memory mapped into
this register address space at addresses OFC, OFE, and
OFD respectively. The remaining registers are available for
general usage.

The external RC network shown in Figure 4 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.
p +

Any bit of data memory can be directly set, reset or tested.
All of the I/O registers and control registers (except A and
PC) are memory mapped. Consequently, any of the 1/0 bits
or control register bits can be directly and individually set,
reset, or tested.

VCC

R
S
U

RESET

P
P
L
V

Note: RAM contents are undefined upon power·up.

ECON (EPROM CONFIGURATION) REGISTER
The ECON register is used to configure the user selectable
clock, security, and RAM size options. The register can be
programmed and read only in EPROM programming mode.
Therefore, the register should be programmed at the same
time as the program memory locations 0000 through OFFF
Hex. UV erasable parts are shipped with OFF Hex in this
register while the OTP parts are shipped with 07F Hex in
this register. Erasing the EPROM program memory also
erases the ECON register.

GNO
TL/DD/11299-7

RC ;;, 5X Power Supply Rise Time

FIGURE 4. Recommended Reset Circuit
OSCILLATOR CIRCUITS
Figure 5 shows the three clock oscillator configurations
available for the device. The CKI 1 and CKI 2 bits in the
ECON register are used to select the clock option. See the
ECON REGISTER section for more details.

The device has a security feature which, when enabled, prevents reading of the EPROM program memory. The security
bit in the ECON register determines whether security is enabled or disabled. If the security option is enabled, then any
attempt to externally read the contents of the EPROM will
result in the value EO Hex being read from all program memory locations. If the security option is disabled, the contents
of the internal EPROM may be read. The ECON register is
readable regardless of the state of the security bit.

CKI

Jl.I"

EXTERNAL

CLOCK

The format of the ECON register is as follows:

:!Cl

TABLE I

CKO

Bit 7 = X
Bit6 = X
Bit5 = 1

'V\jl\rt~

Don't care.
Don't care.

.......

Security disabled. EPROM read and write are
allowed.
Security enabled. EPROM read and write are
not allowed.

TL/DD/11299-B

A. Crystal Oscillator
The device can be driven by a crystal clock. The crystal
network is connected between the pins CKI and CKO.

= 1,1 External CKI option selected.
Not allowed.

= 1,0

RC oscillator option selected.

= 0,0

Crystal oscillator option selected.

Bit 2 = X
Bit 1 = 1

Don't care.
Selects 128 byte RAM option. This emulates
COP840 and COP880.

= 0

Selects 64 byte RAM option. This emulates
COP820.

Bit 0 = X

RESTART

FIGURE 5. Crystal, External and
R-C Connection Diagrams

Bits 4,3
= 0,1

Vcc

Table II shows the component values required for various
standard crystal frequencies.
B. External Oscillator
CKI can be driven by an exter~al clock signal provid~d it
meets the specified duty cycle, rise and fall times, and input
levels. In External oscillator mode, G7 is available as a general purpose input andlor HALT restart control.

Don't care.

1-428

Functional Description

o
o

(Continued)

""'D

co
.......
co

TABLE II. Crystal Oscillator Configuration, T A = 25°C
R1
(kil)

R2
(Mil)

o
o

CKI Freq

~H~

30
30

30-36
30-36

10
4

Conditions
Vee = 5V
Vee = 5V

o
......
o

o""'D
co
co
.....
.......

o
......

TABLE III. RC Oscillator Configuration, TA = 25°C

""'D

R
(kil)

C
(pF)

CKI Freq.
(MHz)

Instr. Cycle
(J-Ls)

Conditions

.......

3.3
5.6
6.8

82
100
100

2.2 to 2.7
1.1 to 1.3
0.9 to 1.1

3.7 to 4.6
7.4 to 9.0
8.8 to 10.8

Vee = 5V
Vee = 5V
Vee = 5V

co
co
N

Note: (RIC Oscillator Configuration): 3k ,,; R ,,; 200k, 50 pF ,,; C ,,; 200 pF.

C. RIC Oscillator

INTERRUPT CONTROL

CKi can be configured as a single pin RC controlled oscillator. In RC oscillator mode, G7 is available as a general purpose input and/ or HALT restart control.

Table ill shows the variation in the oscillator frequencies as
functions of the component (R and C) values.

ENI and ENTI bits select external and timer interrupts respectively. Thus the user can select either or both sources
to interrupt the microcontroller when GIE is enabled.

HALT MODE
The device supports a power saving mode of operation:
HALT. The controller is placed in the HALT mode by setting
the G7 data bit, alternatively the user can stop the clock
input. (Stopping the clock input will draw more current than
setting the G7 data bit.) in the HALT mode all internal processor activities including the clock oscillator are stopped.
The fully static architecture freezes the state of the controller and retains all information until continuing. In the HALT
mode, power requirements are minimal as it draws only
leakage currents and output current. The applied voltage
(Vee) mAy hA (jPGr88'3lO'd down to \lr (m1n1mum RAM retention voltage) without altering the state of the machine.

IEDG selects the external interrupt edge (0 = rising edge,
1 = falling edge). The user can get an interrupt on both
rising and falling edges by toggling the state of IEDG bit
after each interrupt.
IPND and TPND bits signal which interrupt is pending. After
an interrupt is acknowledged, the user can check these two
bits to determine which interrupt is pending. This permits the
interrupts to be prioritized under software. The pending flags
have to be cleared by the user. Setting the GIE bit high
inside the interrupt subroutine allows nested interrupts.
The software interrupt does not reset the GIE bit. This
means that the controller can be interrupted by other interrupt sources while servicing the software interrupt.

There are two ways to exit the HALT mode: via the RESET
or by the G7 pin. A low on the RESET line reinitializes the
microcontroller and starts execution from address OOOOH. In
external and RC oscillator modes, a low to high transition on
the G7 pin also causes the microcontroller to come out of
the HALT mode. Execution resumes at the address following the HALT instruction. Except for the G7 data bit, which
gets reset, all RAM locations retain the values they had prior
to execution of the "HALT" instruction. It is required that the
first instruction following the "HALT" instruction be a
"NOP" in order to synchronize the clock.

INTERRUPT PROCESSING
The interrupt, once acknowledged, pushes the program
counter (PC) onto the stack and the stack pointer (SP) is
decremented twice. The Global Interrupt Enable (GIE) bit is
reset to disable further interrupts. The microcontroller then
vectors to the address OOFFH and resumes execution from
that address. This process takes 7 cycles to complete. At
the end of the interrupt subroutine, any of the following
three instructions return the processor back to the main program: RET, RETSK or RETI. Either one of the three instructions will pop the stack into the program counter (PC). The
stack pointer is then incremented twice. The RETI instruction additionally sets the GIE bit to re-enable further interrupts.

INTERRUPTS
The device has a sophisticated interrupt structure to allow
easy interface to the real world. There are three possible
interrupt sources, as shown below.
A maskable interrupt on external GO input (positive or negative edge sensitive under software control)

A maskable interrupt on timer underflow or timer capture
A non-maskable software/error interrupt on opcode zero

1-429

o
C\I

co
r-co

Functional Description

(Continued)

o......

EXTERNAL
INT. PIN

o
,....
co
r-co
Q.

o
......

SOFTWARE
INTERRUPT

co
r-co

Tl/DD/11299-9

FIGURE 6. Interrupt Block Diagram

TO
INTERRUPT
LOGIC

TIMER
UNDERFLOW - - - - I

DETECTION OF ILLEGAL CONDITIONS

The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIREI
PLUS interface with the internal clock source is called the
Master mode of operation. Operating the MICROWIREI
PLUS interface with an external shift clock is called the
Slave mode of operation.

The device incorporates a hardware mechanism that allows
it to detect illegal conditions which may occur from coding
errors, noise and "brown out" voltage drop situations. Specifically, it detects cases of executing out of undefined EPROM area and unbalanced stack situations.

The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PlUS ,
the MSEl bit in the CNTRl register is set to one. The SK
clock rate is selected by the two bits, SlO and Sl1, in the
CNTRl register. Table IV details the different clock rates
that may be selected.

Reading an undefined EPROM location returns 00 (hexadecimal), as its contents. The opcode for a software interrupt is
also "00". Thus a program accessing undefined EPROM
will cause a software interrupt.
Reading an undefined RAM location returns an FF (hexadecimal). The subroutine stack on the device grows down for
each subroutine call. By initializing the stack pointer to the
top of RAM, the first unbalanced return instruction will cause
the stack pOinter to address undefined RAM. As a result the
program will attempt to execute from FFFF (hexadecimal),
which is an undefined EPROM location' and will trigger a
software interrupt.

TABLE IV

MICROWIRE/PLUS

SL1

SLO

SK Cycle Time

0
0
1

0
1
x

2te
4te
ate

where,

MICROWIRE/PlUS is a serial synchronous bidirectional
communications interface. The MICROWIRE/PlUS capability enables the device to interface with any of National
Semiconductor's MICROWIRE peripherals (Le. AID converters, display drivers, EEPROMS, etc.) and with other microcontrollers which support the MICROWIRE/PlUS interface. It consists of an a-bit serial shift register (SIO) with
serial data input (SI), serial data output (SO) and serial shift
clock (SK). Figure 7 shows the block diagram of the MICROWIRE/PlUS interface.

te is the instruction cycle time.
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MICROWIRE/PlUS arrangement to start shifting the data. It
gets reset when eight data bits have been shifted. The user
may reset the BUSY bit by software to allow less than a bits
to shift. The device may enter the MICROWIRE/PlUS
mode either as a Master or as a Slave. Figure 8 shows how
two device microcontrollers and several peripherals may be
interconnected using the MICROWIRE/PlUS arrangement.

~---------~SO

Master MICROWIRE/PLUS Operation

1+-----51

In the MICROWIRE/PlUS Master mode of operation the
shift clock (SK) is generated internally by the device. The
MICROWIRE/PlUS Master always initiates all data exchanges (Figure 8). The MSEl bit in the CNTRl register
must be set to enable the SO and SK functions on the G
Port. The SO and SK pins must also be selected as outputs
by setting appropriate bits in the Port G configuration register. Table V summarizes the bit settings required for Master
mode of operation.
SLAVE MICROWIRE/PLUS OPERATION

Tl/DD/11299-10

In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL

FIGURE 7. MICROWIRE/PLUS Block Diagram

1-430

Functional Description

(Continued)

"'C
(X)

......

(X)

CHIP SELECT LINES

1
cs

J
cs

0
......
0

I/o
LINES

¢:l

8 - BIT
A/D CONVERTER
COP43X

COP8
(MASTER)

DIGITAL
Pll

EEPROM

"'C

I/O
LINES

LCD
DISPLAY
DRIVER
COP472-3

COP8
(SLAVE)

(X)

......
(X)

.....
0
......

¢:l

0
DO
SI

01 ClK

~_J

01 ClK

"'C

01 ClK

(X)

......
(X)
so

I\)

SI
SK
TlIDD/11299-11

FIGURE 8. MICROWIRE/PLUS Application
bit in the CNTRl register enables the SO and SK functions
on the G Port. The SK pin must be selected as an input and
the SO pin selected as an output pin by appropriately setting
up the Port G configuration register. Table V summarizes
the settings required to enter the Slave mode of operation.
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated (Figure 8).

MODE 1. TIMER WITH AUTO· LOAD REGISTER
In this mode of operation, the timer T1 counts down at the
instruction cycle rate. Upon underflow the value in the register R1 gets automatically reloaded into the timer which continues to count down. The timer underflow can be programmed to interrupt the microcontroller. A bit in the control
register CNTRl enables the TIO (G3) pin to toggle upon
timer underflows. This allows the generation of square-wave
outputs or pulse width modulated outputs under software
control (Figure 9).
MODE 2. EXTERNAL COUNTER
In this mode, the timer T1 becomes a 16-bit external event
counter. The counter counts down upon an edge on the TIO
pin. Control bits in the register CNTRl program the counter
to decrement either on a positive edge or on a negative
edge. Upon underflow the contents of the register R 1 are
automatically copied into the counter. The underflow r.An
also be programmed to generate an interrupt (Figure 9).

TABLE V

Fun.

Int. SK

MICAOWIAE Master

o
1
TAl-STATE Int. SK
!-----+---+-----l-· .....

MICAOWIAE Master

Ext. SK

MICAOWIAE Slave

TAl-STATE Ext. SK

MICAOWIAE Slave

Conflg. Conflg.
Bit
Bit
1

Operation

MODE 3. TIMER WITH CAPTURE REGISTER
Timer T1 can be used to precisely measure external frequencies or events in this mode of operation. The timer T1
counts down at the instruction cycle rate. Upon the occurrence of a specified edge on the TIO pin the contents of the
timer T1 are copied into the register R1. Bits in the control
register CNTRl allow the trigger edge to be specified either
as a positive edge or as a negative edge. In this mode the
user can elect to be interrupted on the specified trigger
edge (Figure 10).

TIMER/COUNTER
The device has a powerful 16-bit timer with an associated
16-bit register enabling it to perform extensive timer functions. The timer T1 and its register R1 are each organized
as two a-bit read/write registers. Control bits in the register
eNTRl allow the timer to be started and stopped under
software control. The timer-register pair can be operated in
one of three possible modes. Table VI details various timer
operating modes and their requisite control settings. I

TABLE VI. Timer Operating Modes
CNTRL
Bits

Operation Mode

T Interrupt

Timer
Counts
On

External Counter w/ Auto-load Reg.
External Counter w/ Auto-load Reg.
Not Allowed
Not Allowed
Timer w/ Auto-load Reg.
Timer wI Auto-load Reg.lToggle TIO Out
Timer wI Capture Register
Timer wlCapture Register

Timer Underflow
Timer Underflow
Not Allowed
Not Allowed
Timer Underflow
Timer Underflow
TID Pos. Edge
TIO Neg. Edge

TID Pos. Edge
TIO Neg. Edge
Not Allowed
Not Allowed
tc
tc
tc
tc

765
000
001
010
01 1
100
101
1 10
111

1·431

o
N

co
.....
co

Functional Description

Control Registers

(Continued)

D..

CNTRl REGISTER (ADDRESS X'OOEE)

o
......

The Timer and MICROWIRE/PLUS control register contains
the following bits:

o,....
co
.....
co

SL 1 & SLO Select the MICROWIRE/PLUS clock divide-by
IEOG

External interrupt edge polarity select

MSEL

Enable MICROWIRE/PLUS functions SO and

D..

......

TIO
OUTPUT

oo
CO
.....
CO

falling edge)

FIGURE 9. Timer/Counter Auto
Reload Mode Block Diagram

D..

riSing edge, 1

Start/Stop the Timer/Counter (1
stop)

TC3

Timer input edge polarity select (0 = rising
edge, 1 = falling edge)

TC2

Selects the capture mode

TC1

Selects the timer mode

run, 0

TC1 I TC21 TC31 TRUN I MSEL IIEOG I S1 I SO
Bit 7

TIO INPUT

TRUN

TL/DD/11299-12

BitO

PSW REGISTER (ADDRESS X'OOEF)
The PSW register contains the following select bits:
GIE

Global interrupt enable

ENI

External interrupt enable

BUSY MICROWIRE/PLUS busy shifting
TL/DD/11299-13

FIGURE 10. Timer Capture Mode Block Diagram
TIMER PWM APPLICATION

IPNO

External interrupt pending

ENTI

Timer interrupt enable

TPNO Timer interrupt pending

Figure 11 shows how a minimal component 0/ A converter

Carry Flag

can be built out of the Timer-Register pair in the Auto-Reload mode. The timer is placed in the "Timer with auto reload" mode and the TIO pin is selected as the timer output.
At the outset the TIO pin is set high, the timer T1 holds the
on time and the register R1 holds the signal off time. Setting
TRUN bit starts the timer which counts down at the instruction cycle rate. The underflow toggles the TIO output and
copies the off time into the timer, which continues to run. By
alternately loading in the on time and the off time at each
successive interrupt a PWM frequency can be easily generated.

Half carry Flag

1 HC I C I TPNO I ENTI IIPNO 1 BUSY I ENI I GIE
Bit7

BitO .

Addressing Modes
REGISTER INDIRECT
This is the "normal" mode of addressing for the device. The
operand is the memory location addressed by the B register
or X register.
DIRECT
The instruction contains an 8-bit address field that directly
points to the data memory location for the operand.
IMMEDIATE
The instruction contains an 8-bit immediate field as the operand.
REGISTER INDIRECT
(AUTO INCREMENT AND DECREMENT)
This is a register indirect mode that automatically increments or decrements the B or X register after executing the
instruction.

TLlDD/11299-14

FIGURE 11. Timer Application

RELATIVE
This mode is used for the JP instruction, the instruction field
is added to the program· counter to get the new program
location. JP has a range of -31 to + 32 to allow a one byte
relative jump (JP + 1 is implemented by a NOP instruction).
There are no "pages" when using JP, all 15 bits of PC are
used.

1-432

o
o

Memory Map

'"C

All RAM, ports and registers (except A and PC) are mapped into data memory address space.

co
.......
co
o

o
"o

Address

Contents

64 On-Chip RAM Bytes
Selected by ECON reg.

00-2F
30-7F

48 On-Chip RAM Bytes
Unused RAM Address Space (Reads as all1's)

128 On-Chip RAM Bytes
Selected by ECON reg.

00-6F
70-7F

112 On-Chip RAM Bytes
Unused RAM Address Space (Reads as all1's)

co
.......
co
.....

Expansion Space for On-Chip EERAM

CO to CF

Expansion Space for I/O and Registers

DOto OF
DO
01
02
03
04
05
06
07

On-Chip I/O and Registers
Port l Data Register
Port l Configuration Register
Port l Input Pins (Read Only)
Reserved for Port l
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)

o'"C

08
09
DA
DB
DC
DO-OF

Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port 0 Data Register
Reserved for Port 0

EO to EF
EO-E7
E8
E9
EA
EB
EC
ED
EE
EF

On-Chip Functions and Registers
Reserved for Future Parts
Reserved
MICROWIRE/PlUS Shift Register
Timer lower Byte
Timer Upper Byte
Timer Autoload Register lower Byte
Timer Autoload Register Upper Byte
CNTRl Control Register
PSW Register

FOto FF
FC
FD
FE

On-Chip RAM Mapped as Registers
X Register
SP Register
B Register

RAM Select

80 to BF

'"C

co
co
I\)

.......

Reading unused memory locations below 7FH will return all ones. Reading other unused memory locations will return undefined
data.

1-433

o
N

co
r-co

D..

.......

o
,...
co
r-co

D..

.......

co
r-co

D..

Instruction Set
REGISTER AND SYMBOL DEFINITIONS
Registers
A
a-bit Accumulator register
a-bit Address register
B
X
a-bit Address register
SP
a-bit Stack pointer register
PC
15-bit Program counter register
upper 7 bits of PC
PU
PL
lower a bits of PC
C
1-bit of PSW register for carry
Half Carry
HC
GIE
1-bit of PSW register for global interrupt enable

Instruction Set

A ~ A + Meml
A ~ A + Meml + C, C ~ Carry
HC ~. Half Carry
A ~ A + Meml +C,C ~ Carry
HC ~ Half Carry
A ~ AandMeml
A ~ AorMeml
A ~ AxorMeml
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B =1= Imm
Reg ~ Reg - 1, skip if Reg goes to 0
1 to bit,
MelT) (bit= 0 to 7 immediate)
o to bit,
Mem
If bit,
Mem is true, do next instr.

ADD
ADC

add
add with carry

SUBC

subtract with carry

AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT

Logical AND
Logical OR
Logical Exclusive-OR
IF equal
IF greater than
IF B not equal
Decrement Reg. ,skip if zero
Set bit

RBIT

Reset bit

IFBIT

If bit

X
LDA
LDmem
LDReg

Exchange A with memory
Load A with memory
Load Direct memory Immed.
Load Register memory Immed.

A +--+ Mem
A ~ Meml
Mem ~ Imm
Reg ~ Imm

X
X
LDA
LDA
LDM

Exchange A with memory [B)
Exchange A with memory [X]
Load A with memory [B)
Load A with memory [X]
Load Memory Immediate

A +--+ [B)
(B ~ B±1)
A +--+ [X]
(X ~ X±1)
A ~ [B)
(B ~ B±1)
A~ [X]
(X ~ X±1)
[B) ~ Imm(B ~ B±1)

CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC

Clear A
IncrementA
Decrement A
Load A indirect from ROM
DECIMAL CORRECT A
ROTATE A RIGHTTHRU C
Swap nibbles of A
SetC
ResetC
IfC
IfnotC

A ~.A + 1
A ~ A-1
A ~ ROM(PU,A)
A ~ BCD correction (follows ADC, SUBC)
C ~ A7 ~ ... ~ AO ~ C
A 7 ... A4 +--+ A3 ... AO
C ~ 1,HC ~ 1
C ~ O,HC ~ 0
If C is true, do next instruction
If C is not true, do next instruction

JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

Jump absolute long
Jump absolute
Jump relative short
Jump subroutine long
Jump subroutine
Jump indirect
Return from subroutine
Return and Skip
Return from Interrupt
Generate an interrupt
No operation

PC ~ ii (ii = 15 bits, 0 to 32k)
PC11 .. 0 ~ i (i = 12 bits)
PC ~ PC + r (r is -31 to +32, not 1)
[SP] ~ PL,[SP-1] ~ PU,SP-2,PC ~ ii
[SP] ~ PL,[SP-1] ~ PU,SP-2,PC11 .. 0 ~ i
PL ~ ROM(PU,A)
SP+2,PL ~ [SP],PU ~ [SP-1]
SP+2,PL ~ [SP],PU ~ [SP-1],Skipnextinstruction
SP+2,PL ~ [SP],PU ~ [SP-1],GIE ~ 1
[SP] ~ PL,[SP-1] ~ PU,SP-2,PC ~ OFF
PC ~ PC + 1

A~O

1-434

Bits 7-4
F

JP -15

JP -31

LD OFO,#i

DRSZOFO

RRCA

ADCA,
#i

j\DCA,
[B)

IFBIT
O,[B]

SUBCA,
#i

SUBC
A,[B]

IFBIT
1,[B]

JP -14

JP-30

LD OF1,#i

DRSZ OF1

*
JP -13
JP -12
JP -11

JP-29
JP-28
JP-27

LDOF2,#i
LD OF3,#i
LDOF4,#i

DRSZOF2
DRSZOF3

JP-26

LDOF5,#i

.....

DRSZOF6

JP-8

JP-24

LD OF7,#i

DRSZOF7

0'1

JP-7

JP-23

LD OF8,#i

DRSZOF8

JP-6

JP-22

LD OF9,#i

DRSZOF9

LD B, OF

IFBNEO

JSR
OOOO-OOFF

JMP
OOOO-OOFF

JP + 17

INTR

o
c

LD B, OE

IFBNE 1

JSR
0100-01FF

JMP
0100-01FF

JP + 18

JP + 2

LD B, OD

IFBNE2

JSR
0200-02FF

JMP
0200-02FF

JP + 19

JP + 3

LD B, DC

IFBNE3

JSR
0300-03FF

JMP
0300-03FF

JP + 20

JP + 4

(')

IFBIT
2,[B]

XA,
[X-]

XA,
[B-]

IFGTA,
#i

IFGT
A,[B]

IFBIT
3,[B]

LAID

ADDA,
#i

ADD
A,[B]

IFBIT
4,[B]

CLRA

LD B, DB

IFBNE4

JSR
0400-04FF

JMP
0400-04FF

JP + 21

JP + 5

JID

ANDA,
#i

AND
A,[B]

IFBIT
5,[B]

SWAPA

LDB,OA

IFBNE5

JSR
OSOO-OSFF

JMP
OSOO-OSFF

JP + 22

JP + 6

XA,
[X]

XA,
[B)

XORA,
#i

XOR
A,[B]

IFBIT
6,[B]

DCORA

LDB,9

IFBNE6

JSR
0600-06FF

JMP
0600-06FF

JP + 23

JP + 7

OR
A,[B]

IFBIT
7,[B]

IFBNE7

JMP
0700-07FF

JP + 8

JSR
0700-07FF

JP + 24

ORA,
#i

. LDB,8

IFC

SBIT
O,[B]

RBIT
O,[B]

LDB,7

IFBNE8

JSR
0800-08FF

JMP
0800-08FF

JP + 2S

JP + 9

8 o

LDA,
#i

!FNC

JSR
0900-09FF

JMP
0900-09FF

JP + 26

JP + 10

RBIT
1,[B]

IFBNE9

SBIT
1,[B]

LDB,6

NOP

(,,)

JP-21

LDOFA,#i

DRSZOFA

LOA,
[X+]

LDA,
[B+]

LD
[B+],#i

INCA

SBIT
2,[B]

RBIT
2,[B]

LDB,S

IFBNEOA

JSR
OAOO-OAFF

JMP
OAOO-OAFF

JP + 27

JP + 11

JP-4

JP-20

LDOFB,#i

DRSZOFB

LDA,
[X-]

LDA,
[B-]

LD
[B-],#i

DECA

SBIT
3,[B]

RBIT
3,[B]

LDB,4

IFBNEOB

JSR
OBOO-OBFF

JMP
OBOO-OBFF

JP + 28

JP + 12

JP-3

JP -19

LDOFC,#i

DRSZOFC

LDMd,
#i

JMPL

XA,Md

SBIT
4,[B]

RBIT
4,[B]

LDB,3

IFBNEOC

JSR
OCOO-OCFF

JMP
OCOO-OCFF

JP + 29

JP +13

JP-2

JP -18

LDOFD,#i

DRSZOFD

DIR

JSRL

LOA,
Md

RETSK

SBIT
5,[B]

RBIT
S,[B]

LDB,2

IFBNEOD

JSR
ODOO-ODFF

JMP
ODOO-ODFF

JP + 30

JP +14

JP -1

JP -17

LDOFE,#i

DRSZOFE

LDA,
[X]

LDA,
[B)

LD
[B], #i

RET

SBIT
6, [B)

RBIT
6, [B)

LDB,1

IFBNEOE

JSR
OEOO-OEFF

JMP
OEOO-OEFF

JP + 31

JP +15

JP-O

JP -16

LDOFF,#1

DRSZOFF

I~ETI

JSR
OFOO-OFFF

JMP
OFOO-OFFF

JP + 32

JP + 16

RBIT
7,[B]

IFBNEOF

SBIT
7,[B]

LD B,O

*
is the immediate data

Md is a directly addressed memory location

JP-5

where.

m
r

IFEQ
A,[B]

*
LDOF6,#i

IFEQA,
#i

DRSZOF5

JP -25

XA,
[B+]

DRSZOF4

JP-9

XA,
[X+]

*
JP -10

• is an unused opcode (see following table)

O~8l8dOO/O ~ 8l8dOO/008l8dOO

iii

oN
co
.....
co

I nstruction Execution Time

BYTES and CYCLES per
INSTRUCTION

Most instructions are single byte (with immediate address·
ing mode instruction taking two bytes).
Most single instructions take one cycle time to execute.

co
.....
co

See the BYTES and CYCLES per INSTRUCTION table for
details.
Arithmetic Instructions (Bytes/Cycles)

c..

o
,...
c..

[B]

Direct

Immed.

ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4

2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2

SBIT
RBIT
IFBIT

1/1
1/1
1/1

3/4
3/4
3/4

oo
CO
.....
CO
c..

o
o

The following table shows the number of bytes and cycles
for each instruction in the format of byte/cycle.

1/3

Memory Transfer Instructions (Bytes/Cycles)
Register
Register Indirect
Indirect Direct Immed.
Auto Incr & Decr
[B] [X]
[B+,B-] [X+,X-]
XA,·
1/1
LOA,·
1/1
LDB,Imm
LDB,lmm
LDMem,lmm
LD Reg,lmm

1/3
1/3

2/3
2/3

2/2
1/1
2/3

3/3

1/2
1/2

1/3
1/3
(lfB < 16)
(lf8> 15)

2/2
2/3

• = > Memory location addressed by B or X or directly.

Instructions Using A & C
Instructions
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC

Transfer of Control Instructions

Bytes/Cycles

Instructions

1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1

JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

1·436

Bytes/Cycles
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
117
1/1

Instruction

, 60
61
62
63
67
8C
99
9F
A7
A8

NOP
NOP
NOP
NOP
NOP
RET
NOP
LD [Bl, #i
XA,[Bl
NOP

EPROM Security Disabled

Unused
Opcode

External
CKI

RC
Oscillator

Crystal
Oscillator

64 Bytes

o
.......

128 Bytes

NOP
LOA, [Bl
C ~ HC
NOP
NOP
XA, [Xl
NOP
LOA, [Xl

"'tJ

.....

RAM
Memory

External
CKI

RC
Oscillator

Crystal
Oscillator

64 Bytes

128 Bytes

EPROM programmer manufacturers may not all calculate a
"checksum" the same way. Before implementing an inhouse verification by comparing checksums, need to ensure
how each programming system utilized calculates a checksum. It is strongly recommended not to include the ECON
register in the checksum for not all programmers include
this byte in their calculated checksum.

Programming Support

ERASING THE COP8780C EPROM

Programming of the single-chip emulator devices is supported by different sources. The following programmers are certified for programming the One-Time Programmable (OTP)
and UV-erasable devices:

The EPROM program memory is erased by exposing the
transparent window on the UV erasable packages to an ultraviolet light source. Erasure begins to occur when exposed to light with wavelengths shorter than approximately
4000 Angstroms (A). It should be noted that sunlight and
certain types of fluorescent lamps have wavelengths in the
3000A to 4000A range.

In addition to the application program, the ECON register
needs to be programmed as well. The following tables provide examples of some ECON register values. For more detailed information refer to the ECON REGISTER section.

co
.......
co

EPROM Security Enabled

Instruction

A9
AF
B1
B4
B5
B7
B9
BF

"'tJ

co
.......
co

RAM
Memory

o
.......

"'tJ

co
.......
co
N

After programming, "truly opaque" labels should be placed
over the window of the device to prevent functional failure
due to the generation of photo currents, erasure and excessive HALT current. The term "truly opaque" needs additional clarification when used in the context of covering quartz

EPROM Programmer Information
;,~Qr.uiQ~iUii:I'

dm.i r:ruuuci

U.S.

~none

Number

a:urope pnone Number

Asia Phone Number

MetaLinkDebug Module

(602) 926-0797

Germany:
+ 49-8141-1 030

Hong Kong:
852-737 -1800

XeltekSuperpro

(408) 745-7974

Germany:
+ 49-2041-684758

Singapore:
+ 65-276-6433

BP MicrosystemsEP-1140

(800) 225-2102

Germany:
+ 49-89-857 -6667

Hong Kong:
+ 852-388-0629

Data I/O-Unisite;
-System 29,
-System 39

(800) 322-8246

Europe:
+ 31-20-622866
Germany:
+ 49-89-85-8020

Japan:
+ 33-4326991

Abcam-COP8
Programmer
System General
Turpra-1-FX;
-APRO

Europe:
+89-808707
(408) 263-6667

Switzerland:
+31-921-7844

1-437

Taiwan Taipei:
+2-9173005

or-------------------------------------------------------------~

co
co

I"-

D..

o
o

.......

o
,....

co
I"co
D..

.......

o
o

CO
I"CO

D..

values, opcodes, and user selectable probe clips status (external event lines). The trace buffer can be viewed as raw
hex or as disassembled instructions. The probe clip bit values can be displayed in binary, hex or digital waveform formats .

Programming Support (Continued)
windows on these devices. The typical white colored stickers or labels are normally used for they are easy to write on.
These stickers are not opaque but translucent, they do let a
certain percentage of UV-light through. The black write-protect labels supplied with 5.25" floppy disks work extremely
well. If problems are encountered during programming (fails
blank check) or during normal operation (intermittent functional or logical failures), need to determine first if an appropriate opaque label is being used to cover the quartz window at all times. Note that the device will also draw more
current than normal (especially in HALT mode) when the
window of the device is not covered with an opaque label.

During single-step operation the dynamically annotated
code feature displays the contents of all accessed (read
and write) memory locations and registers, as well as flowof-control direction change markers next to each instruction
executed.
The iceMASTER's performance analyzer offers a resolution
of better than 6 !-,-s. The user can easily monitor the time
spent executing specific portions of code and find "hot
spots" or "dead code". Up to 15 independent memory areas based on code address or label ranges can be defined.
Analysis results can be viewed in bar graph format or as
actual frequency count.

The recommended erasure procedure for the device is exposure to short wave ultraviolet light which has a wavelength of 2537 A. The integrated dose (UV intensity x exposure time) for erasure should be a minimum of 30W-secl
cm 2 .

Emulator memory o:Jerations for program memory include
single line assembler, disassembler, view, change and write
to file. Data memory operations include fill, move, compare,
dump to file, examine and modify. The contents of any
memory space can be directly viewed and modified from the
corresponding window.

The device should be placed within one inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. The following table shows the minimum erasure time for various light
intensities.

The iceMASTER comes with an easy-to-use' windowed interface. Each window can be sized, highlighted. color-controlled, added, or removed completely. Commands can be
accessed via pull-down-menus and lor redefinable hot keys.
A context, sensitive hypertext/hyperlinked on-line help system explains clearly the options the user has from within
any window.

Minimum Erasure Time
Light Intensity
(Mlcro-Watts/cm 2)

Erasure Time·
(Minutes)

15,000
10,000
8,500

36
50
60

The iceMASTER connects easily to a PC via the standard
COMM port and its 115.2 kBaud serial link keeps typical
program download to under 3 seconds.

'Does not include light intensity ramp up time.

An erasure system should be calibrated periodically. The
distance from lamp to device should be maintained at one
inch. The erasure time increases as the square of the distance. Lamps lose intensity as they age. When a lamp has
aged, the system should be checked to make certain that
adequate UV dosages are being applied for full erasure.
Common symptoms of insufficient erasure are:

The following tables list the emulator and probe cards ordering information.
Emulator Ordering Information

• Inability to be programmed.

Part Number

Description

IM-COP8/400/1:j:

MetaLink base unit incircuit emulator for all
COP8 devices,
symbolic debugger
software and RS232
serial interface cable,
with 110V @ 60 Hz
Power Supply.

IM-COP8/400/2:j:

MetaLink base unit incircuit emulator for all
COP8 devices,
symbolic debugger
software and RS232
serial interface cable,
with 220V @ 50Hz
Power Supply.

DM-COP8/880C:j:

MetaLink ice MASTER
Debug Module. This is
the low cost version of
the MetaLink's
iceMASTER.
Firmware: Ver. 6.07

• Operational malfunctions associated with Vcc, temperature, or clock frequency.
• Loss of data in program memory.
• A change in configuration values in the ECON register.

Development Support
IN-CIRCUIT EMULATOR

Current
Version

Host
Software:
Ver3.3
Rev. 5,
Model File
Rev 3.050.

:j:These parts include National's COPS Assembler/Linker/Librarian Package
(COPS·DEV·IBMA).

1-438

Development Support (Continued)

"'CJ
CD

Single-Chip Emulator Selection Table

Probe Card Ordering Information

......

«:)

Part Number

MHW-880C28D5PC

MHW-880C28DWPC

Package

28DIP

28 DIP

Voltage
Range

Emulator

4.5V-5.5V

COP820C,
840C,
881C,
8781C

2.5V-6.0V

COP820C,
840C,
881C,
8781C

MHW-880C40D5PC

40 DIP

4.5V-5.5V

COP880C,
8780C

MHW-880C40DWPC

40DIP

2.5V-6.0V

COP880C,
8780C

MHW-880C44D5PC

44 PLCC

4.5V-5.5V

COP880C,
8780C

MHW-880C44DWPC

44 PLCC

2.5V-6.0V

COP880C,
8780C

MACRO CROSS ASSEMBLER

National Semiconductor offers a COP8 macro cross assembler. It runs on industry standard compatible PCs and supports all of the full symbolic debugging features of the MetaLink ice MASTER emulators.

Device
Number

Package

Description

Emulates

o
......

COP8780CV

44PLCC

OneTime
Programmable
(OTP)

COP880C

o"'CJ

Part Number

COP8-DEV-IBMA

Description

COP8
Assembler/
Linker/Librarian
forlBM®
PC/XT(ii), AT(ii) cr
compatible.

......

CD
-.

COP8780CEL

44 LDCC

UVErasable

COP880C

COP8780CN

40 DIP

OTP

COP880C

COP8780CJ

40DIP

UV Erasable

COP880C

COP8781CN

28 DIP

OTP

COP881C,
COP840C,
COP820C.

COP8781CJ

28DIP

UV Erasable

COP881C,
COP840C,
COP820C

COP8781CWM

28S0

OTP

COP881C,
COP840C,
COP820C

COP8782CN

20 DIP

OTP

COP842C,
COP822C

COP8782CJ

20DIP

UV Erasable

COP842C,
COP822C

COP8782CWM

20S0

OTP

COP842C,
COP822C

Assembler Ordering Information

o......
o

o"'CJ
CD

......

CD
N

DIAL-A-HELPER

Manual

Dial-A-Helper is a service provided by the Microcontroller
Applications Group. The Dial-A-Helper is an Electronic Bulletin Board information system.

424410632-001

INFORMATION SYSTEM
T11f1 Dial-A-Hdpt:H ::;y::;l~fll jJroviu~~ Ciccess to an automated

information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities could be found. The minimum requirement for accessing the Dial-A-Helper is a Hayes compatible
modem.

CROSS REFERENCE TABLE

The following cross reference table lists the COP800 devices which can be emulated with the COP87XXC single-chip,
form fit and function emulators.

If the user has a PC with a communications package then
files from the FILE SECTION can be down-loaded to disk for
later use.
FACTORY APPLICATIONS SUPPORT

Dial-A-Helper also provides immediate factory applications
support. If a user has questions, he can leave messages on
our electronic bulletin board.

1-439

Voice:

(800) 272-9959

Modem:

CANADA/U.S.:

(800) NSC-MICRO
(800) 672-6427

Baud:

14.4k

Setup:

Length: 8-Bit
Parity:
None
Stop Bit: 1

Operation:

24 Hrs. 7 Days

r---------------------------------------------------------------------.

o
C'i
-.::J'

/fJNational Semiconductor

a..
o
......

COP8640CMH/COP8642CMH
oo Microcontroller Emulator

-.::J'

a..

General Description

Features

The COP8640CMH/COP8642CMH hybrid emulators are
members of the COPSTM microcontroller family. The devices (offered in 28-pin DIP LCC and 20-pin DIP) contain transparent windows which allow the EPROM to be erased and
reprogrammed. They are fully static parts, fabricated using
double-metal silicon gate microCMOS technology. These
microcontrollers are complete microcomputers containing
all system timing, interrupt logic, EPROM, RAM, EEPROM,
and I/O necessary to implement dedicated control functions
in a variety of applications. Features include an 8-bit memory mapped architecture, MICROWIRE/PLUSTM serial I/O, a
16-bit timer/counter with capture register and a multisourced interrupt. Each I/O pin has software selectable options to adapt the COP8640CMH/COP8642CMH to the
specific application. The part operates over a voltage range
of 4.5V to 6.0V. High throughput is achieved with an efficient, regular instruction set operating at a 1 microsecond
per instruction rate.

• Form fit and function emulation devices for COP8640C/
COP8642C/COP8620C/COP8622C

COP8640CMH and COP8642CMH are intended primarily as a prototyping design tool. The Electrical Performance Characteristics are not tested but are included for
reference only.

•
•
•
•
•

•

•
•
•
•
•
•
•
•
•

Fully static CMOS
1 p.s instruction time
Single supply operation: 4.5V to 6.0V
8k bytes EPROM/64 bytes RAM/64 bytes EEPROM
16-Bit read/write timer operates in a variety of modes
- Timer with 16-bit auto reload register
- 16-bit external event counter
- Timer with 16-bit capture register (selectable edge)
Multi-source interrupt
- Reset master clear
- External interrupt with selectable edge
- Timer interrupt or capture interrupt
- Software interrupt
8-bit stack pointer (stack in RAM)
Powerful instruction set, most instructions single byte
BCD arithmetic instructions
MICROWIRE/PLUS serial I/O
28-pin and 20-pin DIP packages
24 input/output pins (28-pin package)
Software selectable I/O options (TRI-STATE®, pushpull, weal pull-up)
Schmitt trigger inputs on Port G
Fully supported by National's Development Systems

Ordering Information

Hybrid
Emulator

Package
Type

Part
Emulated

COP8640CMHD-x

28-DIP

COP8640C-XXX/N
COP8620C-XXX/N

COP8642CMHD-x

20-DIP

COP8642C-XXX/N
COP8622C-XXX/N

= 1. 2. 3 corresponds to oscillator option.

1-440

(')

Connection Diagrams
DUAL-IN-L1NE PACKAGES

Port

20-Pln DIP
G4/S0- 1

\.J

LO
L1
L2
L3
L4
L5
L6
L7

201-G3/T10
19

G5/SK- 2

~G2

18~Gl

G6/SI- 3
G7/CKO- 4

17I-GO/INT

CKI- 5

16 I- RESET

VCC- 6

~GNO

LO- 7

~L7

Ll- 8

131-L6

L2- 9

12t-L5

L3- 10

llt-L4
TLlDD/11207-1

Top View

28-Pin DIP
G4/S0- 1

\.J

G5/SK- 2

COP8640CMH/COP8642CMH
Pinouts

281-G3/TiO
27 -G2

Type

Alternate
Function

lID
lID

28-Pln
DIP/LCC

11
12
13
14
15
16
17
18

9
10
11
12
13
14

lID
lID
I/O

lID

en
0l::Io
o

20-Pln
DIP

I/O
I/O

"'C

GO
G1
G2
G3
G4
G5
G6
G7

I
I/CKO

10
11
12
13

I
I
I
I

7
8
9
10

0
0
0
0

19
20
21
22

lID
lID
lID
lID
lID
lID

Interrupt

TID
SO
SK
SI
Halt Restart

17
18
19
20
1
2
3

CKI- 5

24 -RESET

VCC- 6

23 -GNO

10- 7

22 -03

Vee

11- 8

21 -02

GNO

12- 9

20 1-01

CKI

I~~

i~~Cv

LO- II

18 f- L7

RESET

L1- 12

17 f- L6

26 -Gl

G7/CKO- 4

25 -GO/INT

L2- 13

16 f-L5

L3- 14

151-L4

o"'C
co

0l::Io
N
(')

::I:

25
26
27
28
1
2
3
4

DO
01
02
03

G6/SI- 3

(')

::I:
"(')

TL/DD/11207-2

Top View
FIGURE 1. COP8640CMH/COP8642CMH
Connection Diagrams

1·441

:::I:

:!:

COP8640CMH/COP8642CMH

Absolute Maximum Ratings

D..

.......

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability· and specifications.

:!:

Supply Voltage (Vee>

-.::I"

:::I:

-.::I"

D..

o
o

Voltage at Any Pin

(Note)

7V
50mA

Total Current out of GND Pin (Sink)

60mA

DC Electrical Characteristics O°C ~ TA ~
Parameter

Supply Current
CKI = 10 MHz
Supply Current during
Write Operation (Note 2)
CKI = 10 MHz
HALT Current (Note 3)

The following AC and DC Electrical Characteristics
are not tested but are for reference only.

Min

Condition

Typ

4.5
Peak to Peak
Vee = 6V, tc = 1 ,.,.s

Vee = 6V, tc = 1 ,.,.s
Vee = 6V, CKI = 0 MHz

Max

Units

6.0
0.1 Vee

V
V

mA
,.,.A

500

0.1 Vee

V
V

0.2 Vee

V
V

+2
250

,.,.A
,.,.A

0.9 Vee

0.7 Vee
-2
40

Vee = 6.0V
Vee = 6.0V

G Port Input Hysteresis
Outut Current Levels
D Outputs
Source
Sink
All Others
Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage

+ 70°C unless otherwise specified

Input Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Curent

- 65°C to + 140°C

Note: Absolute maximum ratings indicate limits beyond which damage to the
device may occur. DC and AC electrical specifications are not ensured when
operating the device at absolute maximum ratings.

-0.3V to Vee + 0.3V

Total Current into Vee Pin (Source)

Operating Voltage
Power Supply Ripple (Note 1)

Storage Temperature Range

0.05 Vee

Vee = 4.5V, VOH = 3.8V
Vee = 4.5V, VOL = 1.OV

0.4
10

Vee = 4.5V, VOH = 3.2V
Vee = 4.5V, VOH = 3.8V
Vee = 4.5V, VOL = 0.4V

10
0.4
1.6
-2.0

Allowable Sink/Source
Current per Pin
D Outputs (Sink)
All Others
Maximum Input Current (Note 4)
without Latchup (Room Temp)

Room Temp

RAM Retention Voltage, Vr

500 ns Rise and Fall Time (Min)

Input Capacitance

1-442

mA
mA
110

+2.0

,.,.A
mA
mA
,.,.A

15
3

mA
mA

±100

2.0

COP8640CMH/COP8642CMH

(Continued)

DC Electrical Characteristics ODC ~ TA ~ + 70DC unless otherwise specified (Continued)
Parameter

Condition

Typ

Min

Max

Units

::I:
......

EEPROM Characteristics
EEPROM Write Cycle Time
EEPROM Number of Write Cycles
EEPROM Data Retention

10
10,000
10

ms
Cycle
Years

Note 1: Aate of voltage change must be less than 0.5V1ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the AC and the Crystal configurations. Test conditions: All inputs tied to Vce, Land Gports at TAl-STATE
and tied to ground, all outputs low and tied to ground.
Note 4: Pins G6 and ~ are designed with a high voltage input network for factory testing. These pins allow input voltages greater than Vee and the pins will
have sink current to Vec when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vee>. The effective
resistance to Vee is 750n (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.

::I:

AC Electrical Characteristics ODC ~ TA ~ + 70DC unless otherwise specified
Parameter

Condition

Instruction Cycle Time (tel
Ext, Crystal/Resonator
(Div-by 10)
R/C Oscillator Mode
(Div-by 10)
CKI Clock Duty Cycle (Note 4)
Rise Time (Note 4)
Fall Time (Note 4)

fr
fr

Typ

Max

Units

p.s

60
12
8

%
ns
ns

Min

= 10 MHz Ext Clock
= 10 MHz Ext Clock

Inputs

200
60

tSETUP
tHOLD
Output Propagation Delay
tpD1, tpDo
SO,SK
All OthArs

ns
ns

= 100 pF, RL = 2.2 kO

MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (TUWH)
MICROWIRE Output
Propagation Delay Time (tUPD)

0.7

P.s

!'_9

20
56

ns
ns

220

Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
Reset Pulse Width

1
1
1
1

te
te
te
te

1.0

p.S

Note 4: Parameter sampled but not 100% tested.

1-443

:I:

:e
u

Six bits of Port G have alternate features:

Timing Diagram

GOINTR (an external interrupt)

SK~

D-

flI=
!:::=i
ws

'"
:e

:I:

o
o

G3 TIO (timer/counter input/output)
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock I/O)

~wh

G6 SI (MICROWIRE serial data input)
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input (general purpose input)

x::

Pins G 1 and G2 currently do not have any alternate functions.

\JPD

D-

O
U

PORT D is a four bit output port that is set high when
RESET goes low.

TL/DD/11207-3

FIGURE 2. MICROWIRE/PLUS Timing

Functional Description

Pin Descriptions

OSCILLATOR CIRCUITS

Vee and GND are the power supply pins.

Figure 3 shows the three clock oscillator configurations. Table III shows the clock options per package.

CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunction with CKO). See Oscillator description.

A. CRYSTAL OSCILLATOR
The COP8640CMH/COP8642CMH can be driven by a crystal clock. The crystal network is cnonected between the
pins CKI and CKO.

RESET is the master reset inupt. See Reset description.
PORT I is a four bit Hi-Z input port.
PORT L is an 8-bit I/O port.

Table I shows the component values required for various
standard crystal values.

There are two registers associated with each L I/O port: a
data register and a configuration register. Therefore, each L
I/O bit can be individually configured under software control
as shown below:
Port L
Conflg.

Port L
Data

Port L
Setup

0
0
1
1

0
1
0
1

Hi-Z Inupt (TRI-STATE)
Input with Weak Pull-Up
Push-Pull "0" Output
Push-Pull "1" Output

B. EXTERNAL OSCILLATOR
CKI can be driven by an external clock signal. CKI is available as a general purpose input and/or HALT restart control.
C. R/C OSCILLATOR
CKI is configured as a single pin RC controlled Schmitt trigger oscillator. CKO is available as a general purpose input
and/or HALT restart control.
Table II shows the variation in the oscillator frequencies
(due to the part) as functions of the R/C component values
(R/C tolerances not included).

Three data memory address locations are allocated for
these ports,one for data register, one for configuration register and one for the input pins.

TABLE I. Crystal Oscillator Configuration
TA = 25°C, Vee = 5.0V

PORT G is an 8-bit port with 6 I/O pins (GO:-G5) and 2 input
pins (G6, G7). All eight G-pins have Schmitt Triggers on the
inputs. The G7 pin functions as an input pin under normal
operation and as the continue pin to exit the HALT mode.
There are two registers with each I/O port: a data register
and a configuration register. Therefore, each I/O bit can be
individually configured under software control as shown below:
PortG
Config.

PortG
Data

PortG
Setup

0
0
1
1

0
1
0
1

Hi-Z Input (TRI-STATE)
Input with Weak Pull-Up
Push-Pull "0" Output
Push-Pull "1" Output

R1
(kO)

R2
(MO)

C1
(pF)

C2
(pF)

CKI Freq
(MHz)

0
0
5.5

1
1
1

30
30
100

30-36
30-36
100

10
4
0.455

TABLE II. RC Oscillator Configuration
TA = 25°C, Vee = 5.0V

R
(kO)

C
(pF)

CKI Freq.
(MHz)

Instr. Cycle
(/Ls)

3.3
5.6
6.8

82
100
100

2.2 to 2.7
1.1 to 1.3
0.9 to 1.1

3.7 to 4.6
7.4 to 9.0
8.B to 10.8

Note: 3k :-;; R :-;; 200k
50 pF :-;; C :-;; 200 pF

1-444

Functional Description

a"'0

(Continued)

en
~
o

o
B

CKI

CKO

.. R2"

"""

CKO

CKI

REstART

...J1..J""

FO~ICl
-

CKI

::t:
......

CKO

I-A ! ..

.J..,C

:r.

EXTERNAL
CLOCK

~~ Rl
~~

Y'YY

_ Vcc

a"'0

RES ART

::t:

":"

TL/DD/11207-4

FIGURE 3. Crystal and R-C Connection Diagrams
TABLE III. Clock Option per Package
Order
Part Number

Package

Clock Option

COP8640CMHD-1
COP8642CMHD-1

28 DIP
20DIP

Crystal Oscillator -:- 10 .

COP8640CMHD-2
COP8642CMHD-2

28DIP
20 DIP

External Oscillator -:- 10

COP8640CMHD-3
COP8642CMHD-3

28 DIP
20 DIP

RIC Oscillator -:- 10

The erasure characteristics of the device are such that erasure begins' to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000A to 4000A range.
After programming, opaque labels should be placed over
the window of the device to prevent temporary functional
failure due to the generation of photo currents, erasure, and
excessive HALT current. Note that the device will also draw
more current than normal (especially in HALT mode) when
the window of the device is not covered with an opaque
label.
The recommended· erasure procedure for the devices is
exposure to short wave ultraviolet light which has a
wavelength of 2537 A. The integrated dose (UV intensity
x exposure time) for erasure should be a minimum
of 15 W-sec/cm 2 .
An erasure system should be calibrated periodically. The
distance from lamp to device should be maintained at one
inch. The erasure time increases as the square of the distance. Lamps lose intensity as they age. When a lamp has
aged, the system should be checked to make certain that
adequate UV dosages are being applied for full erasure.

Programming the
COP8640CMH/COP8642CMH
Programming the hybrid emulators is accomplished through
the duplicator board which is a stand alone programmer capable of supporting different package types. It works in conjunction with a pre-programmed EPROM (either via the NSC
development system or a standard programmer) holdinQ the
application program. The duplicator board essentially copies
the information in the EPROM into the hybrid emulator.
The last byte of program memory (EPROM location 01 FFF
Hex) must contain the proper value specified in the following table:

TABLE IV
Device

Package
Type

Contents of
Last Byte
(Address 01FFF)

COP8640CMHD

28 DIP

Package
Type

Light Intensity
(Micro-Watts! cm 2 )

Erasure Time
(Minutes)

COP8642CMHD

20 DIP

28 DIP

15,000
10,000
5,000

20
25
50

20 DIP

15,000
10,000
5,000

40
50
100

TABLE V. Minimum Erasure Time

ERASING THE PROGRAM MEMORY
Erasure of the EPROM program memory is achieved by removing the device from its socket and exposing the transparent window to an ultra-violet light source.

1-445

::I:

o==
C'I
~

CD
CO

D-

o.......

::I:

o==
o
~

CD
CO

D-

Development Support
IN-CIRCUIT EMULATOR

The MetaLink iceMASTERTM-COP8 Model 400 In-Circuit
Emulator for the COP8 family of microcontrollers features
high-performance operation, ease of use, and an extremely
flexible user-interface for maximum. productivity: Interchangeable probe cards, which connect to the standard
common base, support the various configurations and packages of the COP8 family.
The ice MASTER provides real time, full speed emulation up
to 10 MHz, 32 kbytes of emulation memory and 4k frames of
trace buffer memory. The user may define as many as 32k
trace and break triggers which can be enabled, disabled, set
or cleared. They can be simple triggers based on code or
address ranges or complex triggers based on code address,
direct address, opcode value, opcode class or. immediate
operand. Complex breakpoints can be AN Oed and ORed .
together. Trace information consists of address bus values,
opcodes and user selectable probe clips status (external
event lines). The trace buffer can be viewed as raw hex or
as disassembled instructions. The probe clip bit values can
be displayed in binary, hex or digital waveform formats.
During single-step operation the dynamically annotated
code feature displays the contents of all accessed (read
and write) memory locations and registers, as well. as flowof-control direction change markers next to each instruction
executed.

The iceMASTER connects easily to a PC® via the standard
COMM port and its 115.2 kBaud serial link keeps typical
program download time to under 3 seconds.
The following tables list the emulator and probe cards ordering information.

Emulator Ordering Information
Part Number

Description

IM-COP8/400

MetaLink base unit in-circuit emulator
forall COP8·devices, symbolic
debugger software and RS 232 serial
interface cable

MHW-PS3

Power Supply 11 OV160 Hz

MHW-PS4

Power Supply 220V150 Hz

Probe Card Ordering Information
Part
Number

The iceMASTER's performance analyzer offers a resolution
of better than 6 fLs. The user can easily monitor the time
spent executing specific portions of code and find "hot
spots" or "dead code". Up to 15 independent memory areasbased on code address or label ranges can be defined.
Analysis results can be viewed in bar graph format or as
actual frequency count.
Emulator memory operations for program memory include
single line assembler, disassembler, view, change and write
to file. Data memory operations include fill, move, compare,
dump to file, examine and modify. The contents of any
memory space can be directly viewed and modified from the
corresponding window.

1-446

Package

Voltage
Range

Emulates

MHW-8640C20D5PC

20 DIP

4.5V-5.5V COP8642C,
8622C

MHW-8640C20DWPC

20DIP

2.5V-6.0V COP8642C,
8622C

MHW-8640CG28D5PC

28 DIP 4.5V-5.5V COP8640C,
8620C

MHW-8640CG28DWPC

28 DIP

2.5V-6.0V COP8640C,
8620C

Development Support (Continued)
MACRO CROSS ASSEMBLER

SINGLE CHIP EMULATOR DEVICE

National Semiconductor offers a COP8 macro cross assem·
bier. It runs on industry standard compatible PCs and sup·
ports all of the full·symbolic debugging features of the
MetaLink ice MASTER emulators.

The COP8 family is fully supported by single chip form, fit
and function emulators. For more detailed information refer
to the emulation device specific data sheets and the form,
fit, function emulator selection table below.

SIMULATOR

PROGRAMMING SUPPORT

The COP8 Designers' Toolkit is available for evaluating Na·
tional Semiconductor's COP8 microcontroller family. The kit
contains programmer's manuals, device datasheets, pocket
reference guides, assembler and simulator which allow the
user to write, test, debug and run code on an industry stan·
dard compatible PC. The simulator has a windowed user
interface and can handle script files that simulate hardware
inputs, interrupts and automatic command processing. The
capture file feature enables the user to record to a file cur·
rent cycle count and output port changes which are caused
by the program under test.

Programming of the single chip emulator devices is support·
ed by different sources~ National Semiconductor offers a
duplicator board which allows the transfer of program code
from a standard programmed EPROM to the single chip em·
ulator and vice versa. Data I/O supports COP8 emulator
device programming with its uniSite 48 and System 2900
programmers. Further information on Data I/O program·
mers can be obtained from any Data I/O sales office or the
following USA numbers;
.
Telephone: (206) 881·6444

FAX: (206) 882·1043

Assembler Ordering Information
Part Number

Description

Manual

MOLE·COP8·IBM

COP8 Macro Cross Assembler for
IBM® PC·XT®, PC·AT® or Compatible

424410527·001

Simulator Ordering Information
Part Number

Description

Manual

COP8·TOOL·KIT

COP8 Designer's Tool Kit
Assembler and Simulator

420420270·001
424420269·001

Single Chip Emulator Selection Table
Device
Number

Clock
Option

Package

Description

Emulates

COP8640CMHD·X

X = 1 : Crystal
X = 2 : External
X = 3: R/C

28 DIP

Multi·Chip Module (MCM),
UV Erasable

COP8640C,
8620C

COP8640CMHEA·X

X = 1 : Crystal
X = 2 : External
X = 3: R/C

28LCC

MCM (Same Footprint as 28 SO),
UV Erasable

COP8640C,
8620C

COP8642CMHD·X

X = 1 : Crystal
X = 2 : External
X = 3: R/C

20DIP

MCM, UV Erasable

COP8642C,
8622C

Duplicator Board Ordering Information
Part
Number

Description

Devices
Supported

Duplicator Board for 28 DIP and for
use with Scrambler Boards

COP8640CMHD

COP8·SCRM·DIP

Scrambler Board for 20 DIP Socket

COP8642CMHD

COP8·SCRM·SBX

Scrambler Board for 28 LCC Socket

COP8640CMHEA

Duplicator Board with COP8·SCRM·DIP
Scrambler Board

COP8642CMHD,
COP8640CMHD

COP8·PRGM·28D

COP8·PRGM·DIP

1·447

:i!:

"I:t
CD
CO

c..

o
......
~

:i!:

o
o

"I:t
CD
CO

c..

r-----------------------------------------------------------------------------~

Development Support (Continued)
DIAL-A-HELPER

ORDER PIN: MOLE-DiAL-A-HLP

Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Bulletin Board Information system.
.

Information System Package contains:
Dial-A-Helper Users Manual
Public Domain Communications Software

INFORMATION SYSTEM

FACTORY APPLICATIONS SUPPORT

The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities could be found. The minimum requirement for accessing the Dial-A-Helper is a Hayes compatible
modem.

If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.

Baud:

300 or 1200 Baud

Set-up:

Length:

8-Bit

Parity:

None

Stop Bit: 1
Operation: 24 Hrs., 7 Days

1-448

IfINational Semiconductor

PRELIMINARY

COP8788CL/COP8784CL microCMOS
One-Time Programmable (OTP) Microcontrollers
General Description
The COP8788CL/COP8784CL programmable microcontrollers are members of the COPSTM microcontroller family.
Each device is a two chip system in a plastic package. Within the package is the COP888CL and a 8k EPROM with port
recreation logic. The code executes out of the EPROM.
These devices are offered in four packages: 44-pin PLCC,
40-pin DIP, 28-pin DIP and 28-pin SO.
The COP8788CLlCOP8784CL are fully static parts, fabricated using double-metal silicon gate microCMOS technology. Features include an 8-bit memory mapped architecture,
MICROWIRE/PLUSTM serial 1/0, two 16-bit timerlcounters
supporting three modes (Processor Independent PWM generation, External Event counter, and Input Capture mode
capabilities). Each 1/0 pin has software selectable configurations. The devices operates over a voltage range of 4.5V
to 5.5V. High throughput is achieved with an efficient, regular instruction set operating at a maximum of 1 JLs per instruction rate.

Features
a
•
•
•
..
•
•
•
•
•

Low cost 8-bit microcontroller
Fully static CMOS, with low current drain
1 JLs instruction cycle time
8192 bytes on-board EPROM
128 bytes on-board RAM
Single supply operation: 4.5V-5.5V
MICROWIRE/PLUS serial I/O
WATCHDOGTM and Clock Monitor logic
Idle timer
Multi-Input Wakeup (MIWU) with optional interrupts (8)
II Ten mUlti-source vectored interrupts servicing
- External interrupt
- Idle timer TO
- Two timers each with 2 Interrupts
- MICROWIRE/PLUS
- Multi-Input wake up
- Software trap
- Default VIS

• Two 16-bit timers, each with two 16-bit registers
supporting:
- Processor independent PWM mode
- External event counter mode
- I nput capture mode
• 8-bit Stack Pointer SP (stack in RAM)
• Two 8-bit register indirect data memory pointers
(B and X)
• Versatile instruction set with True bit manipulation
• Memory mapped 1/0
• BCD arithmetic instructions

o
o

"tJ
Q)

-.....

Q)
Q)

....o

........

"tJ
Q)

-.....

0l:Io

....

• Package:
- 44 PLCC with 39 1/0 pins
- 40 DIP with 33 1/0 pins
- 28 DIP with 23 I/O pins
- 28 SO with 23 1/0 pins (contact local sales office for
availability)
a Software selectable 1/0 options
- TRI-STATE® output
- Push-Pull output
- Weak pull-up input
- High impedance input
• Schmitt trigger inputs on ports G and L
• Form fit and function emulation device for the
COP888CLlCOP884CL
• Real time emulation and full program debug offered by
Metalink's Development Systems

1-449

....I

0
"I:t
co
~
co

. Connection Diagrams

D..

Plastic Chip Carrier

.... '"

"'....I"

0
co
co
~
co

D..

0
0

... '"
C)

N
(J

0
(J

'"
C)

N
C)

Dual-ln-L1ne Package

;:;
C2

CKI

Vec

RESET

GNO

CKI

vee

44 pin
PLCC

N
...J

,..,
...J

...

an
U

,....
U

.....

on
...J

'"
...J

....
...J

TL/DD12063-1

Top View

RESET

40 pin
DIP

GND

UNUSED

Order Number COP8788CLV-X, COP8788CLFV-R
See NS Package Number V44A .

L5
21

L4
TL/DD12063-2

Top View
Order Number COP8788CLN-X, COP8788CLN-R
See NS Package Number N40A

Dual-In-Llne Package
G4

CKI

RESET
GNO
03

14
15

01
10

L5
15

L4
TL/DD12063-3

Top View
Order Number COP8784CLN-X, COP8784CLN-R,
COP8784CLWM-X and COP8784CLWM-R
See NS Package Number M28B or N28B
FIGURE 1. COP8788CL/COP8784CL Connection Diagrams

1-450

Connection Diagrams

o
o

-a
......

(Continued)

Pinouts for 28-, 40- and 44-Pln Packages
Type

Port

LO
L1

L2
L3
L4
L5
L6
L7
GO
G1
G2
G3
G4
G5
G6
G7
DO
01
02
03
10
11
12
13
14
15
16
17
04
05
06
07
CO
C1
C2
C3
C4
C5
C6
C7
Unused·
Unused·

lID
lID
lID

I/O
lID
lID
lID
lID
lID

AIt.Fun

MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
INT

AIt.Fun

T2A
T28

ALE

WDOUT
lID
lID
lID
lID

I
I/CKO
0
0
0
0

T18
T1A
SO
SK
SI
Halt Restart

WR
RD
ME
ADO
AD1
AD2
AD3

I
I
I
I
I
I
I
I
0
0
0
0

0)
0)

40-Pin
Pkg.

11
12
13
14
15
16
17
18
25
26
27
28
1
2
3
4

17
18
19
20
21
22
23
24
35
36
37
38
3
4
5
6

17
18
19
20
25
26
27
28
39
40
41
42
3
4
5
6

19
20
21
22
7
8

25
26
27
28
9
10
11
12

9
10

13
14

29
30
31
32
9
10
11
12
13
14
15
16
33
34
35
36
43
44
.1
2
21
22
23
24

AD4
AD5
AD6
AD7

29
30
31
32
39
40
1
2

lID
lID
lID

I/O
lID
lID
lID
lID

Vee

GND
CKI
RESET

Vpp

• = On the 40-pin package, Pins 15 and 16 must be connected to GND.

1-451

. 44-Pln
Pkg.

28-Pln
Pkg.

6
23
5
24

16
15
8
33
7
34

·8
37
7
38

ro
o

.......

-a
0)

......

0)
~

o
r-

..J

o
"'1::1'

co
r-co

c..

oo
.....
..J
o
co

co
r-co
c..

Absolute Maximum Ratings (Note)
Total Current out of GND Pin (Sink)
110 mA
- 65°C to + 140°C
Storage Temperature Range
Note: Absolute maximum ratings indicate limits beyond which damage to the

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
7V
Voltage at Any Pin
-:-0.3V to Vee + 0.3V
100mA
Total Current into Vee Pin (Source)

DC Electrical Characteristics

device may occur. DC and AC electrical specifications are not ensured when
operating the device at absolute maximum ratings.

-40°C ~ TA ~ + 85°C unless otherwise specified

Parameter

Conditions

Operating Voltage

Typ

4.5

Power Supply Ripple (Note 1)

Peak-to-Peak

Supply Current (Note 2)
CKI = 10 MHz

Vee

HALT Current (Note 3)
IDLE Current, CKI

Min

= 10 MHz

= 5.5V, tc = 1 JLs
Vee = 5.5V, CKI = 0 MHz
Vee = 5.5V, tc = 1 JLs

Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current

TRI-STATE Leakage

Units

5.5

0.1 Vee

250

JLA

0.8 Vee
0.2 Vee
V

0.7 Vee
0.2 Vee
0.7 Vee
0.2 Vee

= 5.5V
Vee = 5.5V
Vee

-2

JLA

250

p.A

0.35 Vee

G and L Port Input Hysteresis
Output Current Levels
D Outputs
Source
Sink
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)

Max

0.05 Vee

Vee
Vee

= 4.5V, VOH = 3.3V
= 4.5V, VOL = 1V

=
=
=
Vee =

Vee
Vee
Vee

4.5V, VOH
4.5V, VOH
4.5V, VOL

= 2.7V
= 3.3V
= OAV

004

100

JLA
mA
mA

JLA

004
1.6
-2

5.5V

mA
mA

Allowable Sink/Source
Current per Pin
D Outputs (Sink)
All others

15
3

= 25°C

Maximum Input Current
without Latchup (Note 4)

RAM Retention Voltage, Vr

500 ns Rise
and Fall Time (Min)

±100

Input Capacitance
Load Capacitance on D2

mA
V

1000

Rate of voltage change must be less then 0.5 V/ms.
Supply current is measured after running 2000 cycles with a square wave CKI input. CKO open. inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee. Land G ports in the
TRI-STATE mode and tied to ground. all outputs low and tied to ground. The clock monitor is disabled.
Note 4: Pins G5 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than Vee and the pins will
have sink current to Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vecl. The effective
resistance to Vee is 7500 (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 1:
Note 2:

1-452

o
AC Electrical Characteristics
Parameter

-40°C

Conditions

Min

Instruction Cycle Time (td
Crystal or Resonator
RIC Oscillator
CKI Clock Duty Cycle (Note 5)
Rise Time (Note 5)
Fall Time (Note 5)

~ TA ~ + 85°C unless otherwise specified

fr = Max
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock

Typ

-a

Max

Units

1
3

DC
DC

J1-s

60
5
5

200
60

Output Propagation Delay

ns
ns

-a
Q)

.....

Q)
~

o
.-

RL = 2.2k, CL = 100 pF

tpD1, tpDO
SO,SK
All Others

4V ~ Vee ~ 6V
4V ~ Vee ~ 6V

0.7

J1-s

MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tUPD)

20
56

ns
220

Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time

1
1
1
1

Reset Pulse Width

Note 5:

Q)
Q)

Inputs
tSETUP
tHOLD

.....
o
.......
o

J1-s

Parameter sampled (not 100% tested).

~
\UWH

~\UPD

TLlDD12063-4

FIGURE 2. MICROWIRE/PLUS Timing

1-453

..J

o
~

co
.....
co
D..

......

..J

oco
co
.....
co
D..

o
o

Pin Descriptions
Vee and GND are the power supply pins .

Port L has the following alternate features:

CKI is the clock input. This can come from an R/C generated oscillator, or a crystal oscillator (in conjunction with
CKO). See Oscillator Description section.
RESET is the master reset input. See Reset Description
section.
The device contains three bidirectional a-bit I/O ports (C, G
and L), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports G and L),
output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these 1/
ports. Each I/O port has two associated a-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also
reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O
ports.) Figure 3 shows the I/O port configurations. The
DATA and CONFIGURATION registers allow for each port
bit to be individually configured under software control as
shown below:
DATA
Register

Hi-Z Input

Input with Weak Pull-Up

Push-Pull Zero Output

Push-Pull One Output

MIWU

L3
L4

MIWU
MIWU or T2A

MIWU or T28

MIWU

Port G is an a-bit port with 5 I/O pins (GO, G2-G5), an input
pin (G6), and two dedicated output pins (G1 and G7). Pins
GO and G2-G6 all have Schmitt Triggers on their inputs: Pin
G1 serves as the dedicated WDOUT WATCHDOG output,
while pin G7 is either input or output depending on the oscillator mask option selected. With the crystal oscillator option
selected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin, but is
also used to bring .the.device out of HALTmode with a low
to high transition. There are two registers associated with
the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (GO, G2-G5) can be individually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin or general purpose input (R/C clock configuration), the associated bits in the data and configuration·
registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits
will return zeros.

CONFIGURATION
Register

Port Set-Up

(TRI-STATE Output)

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

Port G has the following alternate features:
TL/DD12063- 5

FIGURE 3. 1/0 Port Configurations
PORT L is an a-bit I/O port. All L-pins have Schmitt triggers
on the inputs.
Port L supports Multi-Input Wakeup (MIWU) on all eight
pins. L4 and L5 are used for the timer input functions T2A
and T28.

1-454

INTR (External Interrupt Input)

T18 (Timer T1 Capture Input)

T1 A (Timer T1 I/O)

SO (MICROWIRE Serial Data Output)

SK (MICROWIRE Serial Clock)

SI (MICROWIRE Serial Data Input)

Pin Descriptions (Continued)
Port G has the following dedicated functions:
G1

WDOUT WATCHDOG andlor Clock Monitor
dedicated output

CKO Oscillator dedicated output or general
purpose input

Port I is an 8-bit Hi-Z input port. The 28-pin device does not
have a full complement of Port I pins. The unavailable pins
are not terminated (Le. they are floating). A read operation
from these unterminated pins will return unpredictable values. The user should ensure that the software takes this
into account by either masking out these inputs, or else restricting the accesses to bit operations only. If unterminated,
Port I pins will draw power only when addressed. The I port
leakage current may be higher in 28-pin devices.

DATA MEMORY

r.......

ClO

........
ClO
ClO

ClO
........
ClO
~

The device has 128 bytes of RAM. Sixteen bytes of RAM
are mapped as "registers" at addresses OFO to OFF Hex.
These registers C~ln be loaded immediately, and also decremented and tested with the DRSZ (decrement register and
skip if zero) instruction. The memory pointer registers X, SP,
and B are memory mapped into this space at address locations OFC to OFE Hex respectively, with the other registers
(other than reserved register OFF) being available for general usage.

Port 0 is a recreated 8-bit output port that is preset high
when RESET goes low. 0 port recreation is one clock cycle
behind the normal port timing. The user can tie two or more
o port outputs (except D2 pin) together in order to get a
higher drive.

The instruction set permits any bit in memory to be set,
reset or tested. All 1/0 and registers on the device (except A
and PC) are memory mapped; therefore, 1/0 bits and register bits can be directly and individually set, reset and tested.
The accumulator (A) bits can also be directly and individually tested.

Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for Ports l, G, and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WATCHDOG and lor Clock Monitor error
output pin. Port 0 is initialized high with RESET. The PC,
PSW, CNTRl, ICNTRl, and T2CNTRl control registers are
cleared. The Multi-Input Wakeup registers WKEN, WKEDG,
and WKPND are cleared. The Stack Pointer, SP, is initialized to 06F Hex.

CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or
shift operation in one instruction (td cycle time.
Th~iu

The data memory address space includes the on-chip RAM
and data registers, the 1/0 registers (Configuration, Data
and Pin), the control registers, the MICROWIRE/PlUS SIO
shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer).
Data memory is addressed directly by the instruction or indirectly by the B, X and SP pointers.

Port C is an 8-bit 1/0 port. The 28-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated
pins will return unpredictable values.

o
o

instruction, and interrupt vectors for the VIS instruction).
The program memory is addressed by the 15-bit program
counter (PC). All interrupts vector to program memory location OFF Hex.

(iiG fi;;a CPU rogistci5:

A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register

The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, and with both
the WATCHDOG service window bits set and the Clock
Monitor bit set. The WATCHDOG and Clock Monitor detector circuits are inhibited during reset. The WATCHDOG service window bits are initialized to the maximum WATCHDOG
service window of 64k tc clock cycles. The Clock Monitor bit
is initialized high, and will cause a Clock Monitor error following reset if the clock has not reached the minimum specified frequency at the termination of reset. A Clock Monitor
error will cause an active low error output on pin G1. This
error output will continue until 16-32 tc clock cycles following the clock frequency reaching the minimum specified value, at which time the G1 output will enter the TRI-STATE
mode.

PU is the upper 7 bits of the program counter (PC)
Pl is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutinel
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.
All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY

Program memory consists of 8192 bytes of ROM. These
bytes may hold program instructions or constant data (data
tables for the LAID instruction, jump vectors for the JID

The external RC network shown in Figure 4 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.
Note: In continual state of reset. the device will draw excessive current.

1-455

..J

co
co

Reset (Continued)

TABLE II. RIC Oscillator Configuration, TA = 25°C

1'0

P
0

.......

..J

E
R

o
co

co
1'0
co

S
U

P
P

R
(kO)

vee

+
-,R

.n.D

CKI Freq
(MHz)

3.3

5.6

100

6.8

100

COP800

-RESET

Note: 3k

C
(pF)

GND

:s:

Instr. Cycle
(J.Ls)

Conditions

2.2-2.7

3.7-4.6

Vee = 5V

1.1-1.3

7.4-9.0

Vee = 5V

0.9-1.1

8.8-10.8

Vee = 5V

200k. 50 pF

:s:

200 pF

Current Drain

TLlDD12063-6

The total current drain of the chip depends on:
1. Oscillator operation mode-11

RC > 5 x Power Supply Rise Time

FIGURE 4. Recommended Reset Circuit

2. Internal switching current-12

Oscillator Circuits

3. Internal leakage current-13

4. Output source current-14
5. DC current caused by external input
not at Vee or GND-15
6. Clock Monitor current when enabled-16
Thus the total current drain, It, is given as

Figure 5 shows the Crystal and RIC diagrams.

CKI

CKO

CKI

It = 11

CKO

......

R
....:......

vee

-'-c

CRYSTAL OSCilLATOR
CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.

Control Registers
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:

TABLE I. Crystal Oscillator Configuration, T A = 25°C
C1
(pF)

CNTRl Register (Address X'OOEE)

Table I shows the component values required for various
standard crystal values.

R2
(MO)

where C = equivalent capacitance of the chip
V = operating voltage
f = CKI frequency

TL/DD12063-7

FIGURE 5. Crystal and RIC Oscillator Diagrams

R1
(kO)

To reduce the total current drain, each of the above components must be minimum.
The chip will draw more current as the CKI input frequency
increases up to the maximum 10 MHz value. Operating with
a crystal network will draw more current than an external
square-wave. Switching current, governed by the equation,
can be reduced by lowering voltage and frequency. Leakage current can be reduced by lowering voltage and temperature. The other two items can be reduced by carefully
designing the end-user's system.
12 = C x V x f

SL1 & SLO Select the MICROWIRE/PLUS clock divide
by (00 = 2,01 = 4, 1x = 8)

C2
(pF)

CKI Freq
(MHz)

Conditions

IEDG

External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)

MSEL

Selects G5 and G4 as MICROWIRE/PLUS
signals
SK and SO respectively

30-36

Vee = 5V

30-36

Vee = 5V

200

100-150

0.455

Vee = 5V

RIC OSCilLATOR
By selecting CKI as a single pin oscillator input, a single pin
RIC oscillator circuit can be connected to it. CKO is available as a general purpose input, and/or HALT restart pin.
Table" shows the variation in the oscillator frequencies as
functions of the component (R and C) values.

1-456

Control Registers
T1 CO

a'"D

(Continued)

Timer T1 Start/Stop control in timer

leNTRl Register (Address X'OOES)

Timer T1 Underflow Interrupt Pending Flag in
timer mode 3

The ICNTRL register contains the following bits:

T1 C1

Timer T1 mode control bit

Timer T1 Interrupt Enable for T1 B Input capture
edge

T1 C2
T1 C3

Timer T1 mode control bit
Timer T1 mode control bit

T1PNDB Timer T1 Interrupt Pending Flag for T1B capture edge

! T1C3! T1C2! T1C1 ! T1CO ! MSEL !IEDG! SL 1
Bit7

T1 ENB

"'"

CQ
CQ

WEN

Enable MICROWIRE/PLUS interrupt

SLO

WPND

MICROWIRE/PLUS interrupt pending

BitO

TOEN

Timer TO Interrupt Enable (Bit 12 toggle)

TOPND
LPENL

Timer TO Interrupt pending
Port Interrupt Enable (Multi-Input
eup/ Interrupt)

PSW Register (Address X'OOEF)
The PSW register contains the following select bits:
GIE

Global interrupt enable (enables interrupts)

EXEN

Enable external interrupt

BUSY

MICROWIRE/PLUS busy shifting flag
External interrupt pending

T1 ENA

Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge

CQ
~

r
Wak-

Bit?

BitO

The T2CNTRL register contains the following bits:
T2ENB

Timer T2 Interrupt Enable for T2B Input capture
edge

T2PNDB Timer T2 Interrupt Pending Flag for T2B capture edge

Carry Flag
Half Carry Flag

T2ENA
! HC ! C! T1 PNDA ! T1 ENA ! EXPND ! BUSY! EXEN! GIE I
Bit7

"'"

! Unused! LPEN ! TOPND ! TOEN ! WPND ! WEN! T1 PNDB ! T1 ENB I

T1 PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1 A capture edge in mode 3)
C
HC

a'"D

Bit 7 could be used as a flag
T2CNTRL

EXPND

o
o

r
.......

Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA
in mode 1, T2 Underflow in mode 2, T2A capture edge in mode 3)
T2CO
Timer T2 Start/Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3

BitO

T2C1

Timer T2 mode control bit

T2C2

Timer T2 mode control bit

!T2C3IT2C2!T2C1!T2CO!T2PNDA!T2ENAIT2PNDBIT2ENBI
Bit 7

BitO

1-457

...I

o
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D-

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.....
...I

Timers
TIMER T1 AND TIMER T2

The device contains a very versatile set of timers (TO, T1,
T2). All timers and associated auto reload/capture registers
power up containing random data.

The device has a set of two powerful timer/counter blocks,
T1 and T2. The associated features and functioning of a
timer block are described by referring to the timer block Tx.
Since the two timer blocks, T1 and T2, are identical, all comments are equally applicable to either timer block.

Figure 6 shows a block diagram for the timers .

oco

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DO

The control bits TxC3, TxC2, and TxC1 allow selection of
the different modes of operation.
Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention.
The user only has to define the parameters of the PWM
signal (ON time and OFF time). Once begun, the timer block
will continuously generate the PWM signal completely independent of the microcontroller. The user software services
the timer block only when the PWM parameters require updating.
In this mode the timer Tx counts down at a fixed rate of tc.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.

TL/DD12063-8

FIGURE 6. Timers
TIMER TO (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer TO, which is a
16-bit timer. The Timer TO runs continuously at the fixed
rate of the instruction cycle clock, tc. The user cannot read
or write to the IDLE Timer TO, which is a count down timer.

The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.
Figure 7 shows a block diagram of the timer in PWM mode.

The Timer TO supports the following functions:
Exit out of the Idle Mode (See Idle Mode description)
WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode

TIMER
UNDERFLOW
INTERRUPT

The IDLE Timer TO can generate an interrupt when the thirteenth bit toggles. This toggle is latched into the TOPND
pending flag, and will occur every 4 ms at the maximum
clock frequency (tc = 1 fLS). A control flag TOEN allows the
interrupt from the thirteenth bit of Timer TO to be enabled or
disabled. Setting TOEN will enable the interrupt, while resetting it will disable the interrupt.

+------,

TxA
tC------'

TL/DD12063-9

FIGURE 7. Timer in PWM Mode

1-458

,---------------------------------------------------------------------------, 0

a"'C

Timers

(Continued)
The underflows can be programmed to toggle the TxA out~
put pin. The underflows can also be programmed to generate interrupts.

Mode 2. External Event Counter Mode
This mode is. quite similar to the processor independent
PWM mode described above. The main difference is that
the timer, Tx, is clocked by the input signal from the TxA pin.
The Tx timer control bits, TxC3, TxC2 and TxC1 allow the
timer to be clocked either on a positive or negative edge
from the TxA pin. Underflows from the timer are latched into
the TxPNDA pending flag. Setting the TxENA control flag
will cause an interrupt when the timer underflows.

o
o

r
.......

a"'C
co
co

.......
0l::Io

o
r

Figure 8 shows a block diagram of the timer in External
Event Counter mode.

Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once
per PWM period on either the riSing or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.

TIMER
UNDERFLOW
INTERRUPT

co
.......
co
co

Note: The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock.

+-------.

TxAIXI--~

16 BIT AUTO RELOAD REGISTER
OFF TIME

14--....

T x B~ To Interrupt Control

FIGURE 8. Timer In External Event Counter Mode

1-459

o"I:t'
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D-

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~

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DO

r-------------------------------------------------------------------~

Timers

(Continued)

Mode 3. Input Capture Mode

flow interrupt pending flag in the Input Capture mode). Consequently, the TxCO control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs "in the Input Capture mode, the user must check both
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.

Figure 9 shows a block diagram of the timer in Input Capture
mode.

TIMER CONTROL FLAGS
The timers T1 and T2 have indentical control structures.
The control bits and their functions are summarized below.
TxCO

The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.

Timer Start/Stop control in Modes
(Processor Independent PWM and
Event Counter), where 1 = Start, 0 =
Timer Underflow "Interrupt Pending
Mode 3 (Input Capture)

TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag

Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer TxCO
pending flag (the TxCO control bit serves as the timer under-

TxENA
TxENB

Timer Interrupt Enable Flag
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
o = Timer Interrupt Disabled

TxC3
TxC2
TxC1

Timer mode control
Timer mode control
Timer mode control

I
N

T
tC

E
R
N
A

D
A
T
A

Tx B 1Xi1----I~

TL/DD12063-11

FIGURE 9. Timer In Input Capture Mode

1·460

1 and 2
External
Stop
Flag in

Timers

(Continued)

""C
(X)

.......

The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
TxC3

TxC2

TxC1

Timer Mode

MODE 2 (External
Event Counter)

(X)
(X)

Interrupt A
Source

Interrupt 8
Source

Timer
Counts On

Timer
Underflow

Pos. TxB
Edge

TxA
Pos.Edge

Timer
Underflow

Pos. TxB
Edge

TxA
Neg. Edge

MODE 1 (PWM)
TxA Toggle

Autoreload
RA

Autoreload
RB

MODE 1 (PWM)
No TxA Toggle

Autoreload
RA

Autoreload
RB

MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Pos. Edge

Pos. TxA
Edge or
Timer
Underflow

Pos. TxB
Edge

MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Neg. Edge

Pos. TxA
Edge or
Timer
Underflow

Neg. TxB
Edge

MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Pos. Edge

Neg. TxB
Edge or
Timer
Underflow

Pos. TxB
Edge

MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Neg. Edge

Neg. TxA
Edge or
Timer
Underflow

Neg. TxB
Edge

Power Save Modes
The device offers the user two power save modes of operation: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscillator circuitry and timer TO are active but all other microcontroller activities are stopped. In either mode, all on-board
RAM, registers, 1/0 states, and timers (with the exception of
TO) are unaltered.

with the Multi-Input Wflkeup feflture on thp. I. port. ThA SAr.ond method is with a low to high transition on the CKO (G7)
pin. This method precludes the use of the crystal clock configuration (since CKO becomes a dedicated output), and so
may be used with an RC clock configuration. The third
method of exiting the HALT mode is by pulling the RESET
pin low.

HALT MODE

The device is placed in the HALT mode by writing a "1" to
the HALT flag (G7 data bit). All microcontroller activities,
including the clock, timers, are stopped. The WATCHDOG
logic is disabled during the HALT mode. However, the clock
monitor circuitry, if enabled, remains active and will cause
the WATCHDOG output pin (WDOUT) to go low. If the
HALT mode is used and the user does not want to activate
the WDOUT pin, the Clock Monitor should be disabled after
the device comes out of reset (resetting the Clock Monitor
control bit with the first write to the WDSVR register). In the
HALT mode, the power requirements are minimal and the
applied voltage {Ved may be decreased to Vr (Vr = 2.0V)
without altering the state of the machine.
The device supports three different ways of exiting the
HALT mode. The first method of exiting the HALT mode is

1-461

r
.......
0

""C

(X)

.......

(X)

.I:a.

...J

o
oo::J'

co
r-co
c..

......
...J
o
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co
r-co
c..

o
o

Power Save Modes (Continued)
The user has the option- of being interrupted with a transition
on the thirteenth bit of the IDLE Timer TO. The interrupt can
be enabled or disabled via the TOEN control bit Setting the
TOEN flag enables the interrupt and vice versa.

IDLE MODE

Note: It Is necessary to program two NOP instructions following both the
set HALT mode and set IDLE mode instructions. These NOP instructions are necessary to allow clock resynchronization following the
HALTor IDLE modes. Due to the on-board 8k EPROM with port
recreation logic, the HALT/IDLE current is much higher compared to
the equivalent masked device (COP888CL/COP884CL).

Multi-Input Wakeup
The Multi-Input Wakeup feature is used to return (wakeup)
the device from either the HALT or IDLE modes. Alternately
Multi-Input Wakeup/Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts.
Figure 10 shows the Multi-Input Wakeup logic.

This toggle condition of the thirteenth bit of the IDLE Timer
TO is latched into the TOPND pending flag.

•
•
•

G
•
•

•
•

-.••

WKEDG

WKPND

CKO

CHIP CLOCK

TLlDD12063-12

FIGURE 10. Multi-Input Wake UpLogic

1-462

~------------------------------------------------------------~o

Multi-Input Wakeup

(Continued)

""D

5,
5,
5,
5,

Port L provides the user with an additional eight fully selectable, edge sensitive i.nterrupts which are all vectored into
the same service subroutine.

o
r

o
""
o
""D

co
......
co
~

The GIE (Global Interrupt Enable) bit enables the interrupt
function. A control flag, LPEN, functions as a global interrupt enable for Port L interrupts. Setting the LPEN flag will
enable interrupts and vice versa. A separate global pending
flag is not needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If
he elects to disable the interrupt, then the device will restart
execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or
IDLE modes. In the other case, the device will first execute
the interrupt service routine and then revert to normal operation.
The Wakeup signal will not start the chip running immediately since crystal oscillators or ceramic resonators have a finite start up time. The IDLE Timer (TO) generates a fixed
delay to ensure that the oscillator has indeed stabilized before allowing the execution of instructions. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry and the IDLE Timer TO are enabled. The IDLE Timer is loaded with a value of 256 and is clocked from the te
instruction cycle clock. The te clock is derived by dividing
down the oscillator clock by a factor of 10. A Schmitt trigger
following the CKI on-chip inverter ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large
cunpiituue to meet the Schmitt trigger specifications. 'I his
Schmitt trigger is not part of the oscillator closed loop. The
startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip.

RMRBIT
RMSBIT
RMRBIT
RMSBIT

......

The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an
8-bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.

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PORT L INTERRUPTS

WKEN
WKEDG
WKPND
WKEN

If the RC clock option is used, the fixed delay is under software control. A control flag, CLKDL Y, in the G7 configuration bit allows the clock start up delay to be optionally inserted. Setting CLKDLY flag high will cause clock start up delay
to be inserted and resetting it will exclude the clock start up
delay. The CLKDL Y flag is cleared ,during reset, so, the clock
start up delay is not present following reset with the RC
clock options.
'

The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since WKPND is a pending
register for the occurrence of selected wakeup conditions,
the device will not enter the HALT mode if any Wakeup bit is
both enabled and pending. Consequently, the user has the
responsibility of clearing the pending flags before attempting to enter the HALT mode.,

The WKEN, WKPND and WKEDG are all read/write registers, and are cleared at reset.

1-463

-I

Interrupts (Continued)

a..
o
.......

Arbitration
Ranking

(1) Highest

Description

Source

-I
CX)

co
~
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Vector
Address
HI·Low Byte

Software

INTR Instruction

Reserved

for Future Use

OyFC-OyFD

OyFE-OyFF

a..

(2)

External

Pin GO Edge

OyFA-OyFB

(3)

Timer TO

Underflow

OyF8-0yF9
OyF6-0yF7

(4)

TimerT1

T1 AlUnderflow

(5)

TimerT1

T1B

OyF4-0yF5

(6)

MICROWIRE/PLUS

BUSY Goes Low

OyF2-OyF3

Reserved

for Future Use

OyFO-OyF1

Reserved

forUART

OyEE-OyEF

Reserved

forUART

OyEC-OyED

(7)

TimerT2

T2A1Underflow

OyEA-OyEB

(8)

TimerT2

T2B

OyE8-0yE9
OyE6-0yE7

Reserved

for Future Use

Reserved

for Future Use

OyE4-0yE5

(9)

Port LlWakeup

Port LEdge

OyE2-OyE3

(10) Lowest

Default

VIS Instr. Execution
without Any Interrupts

OyEO-OyE1

Y is VIS page,

y of. o.

Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software
interrupt are maskable. Each of the maskable interrupts
have an Enable bit and a Pending bit. A maskable interrupt
is active if its associated enable and pending bits are set. If
GIE = 1 and an interrupt is active, then the processor will
be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described
in the Software Trap sub-section.

1-464

(')

a-a

Interrupts (Continued)
Inside the interrupt service routine, the associated pending
bit has to be cleared by software. The RETI (Return from
Interrupt) instruction at the end of the interrupt service routine will set the GIE (Global Interrupt Enable) bit, allowing
the processor to be interrupted again if another interrupt is
active and pending.

last address of a block. In this case, the table must be in the
next block. The vector table cannot be inserted in the first
256-byte block.
The vector of the maskable interrupt with the lowest rank is
located at OyEO (Hi-Order byte) and OyE1 (Lo-Order byte)
and so forth in increasing rank number. The vector of the
maskable interrupt with the highest rank is located at OyFA
(Hi-Order byte) and OyFB (Lo-Order byte).

The VIS instruction looks at all the active interrupts at the
time it is executed and performs an indirect jump to the
beginning of the service routine of the one with the highest
rank.

The Software Trap has the highest rank and its vector is
located at OyFE and OyFF.

If, by accident, a VIS gets executed and no interrupt is active, then the PC (Program Counter) will branch to a vector
located at OyEO-OyE1. This vector can point to the Software Trap (ST) interrupt service routine, or to another special service routine as desired.

VIS and the vector table must be located in the same
256-byte block (OyOO to OyFF) except if VIS is located at the

Figure 11 shows the Interrupt block diagram.

SOFTWARE

ClO
......

ClO
ClO

(')

r......

(')

-a

ClO
......
ClO

0I:loo
(')

----------------1

TIMER T1 AND T2

EXTERNAL

MULTI-INPUT WAKE UP
INTERRUPT
pWIRE/PLUS

FUTURE PERIPHERALS

F
L
A 1---4-+-~I----I~'____'______',_____.....
G

IDLE TIMER

TLlDD12063-13

FIGURE 11. COP888CL Interrupt Block Diagram

1-465

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(,)
oq-

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.......
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D-

o
(,)
"..J

(,)

co
co
co

.......
D-

o(,)

TABLE IV. WATCHDOG Service Window Select

Interrupts (Continued)

. WDSVR
Blt7

0
0
1
1.

WATCHDOG Operation

The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the WATCHDOG service window and match the
WATCHDOG key data. Subsequent writes to the WDSVR
register will compare the value being written by the user to
the WATCHDOG service window value and the key data
(bits 7 through 1) in the WDSVR Register. Table V shows
the sequence of events that can occur.

The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table III shows the WDSVR register.

The user must service the WATCHDOG at least once before the upper limit of the serivce window expires. The
WATCHDOG may not be serviced more than once in every
lower limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period
between the lower and upper limits of the service window.
The first write to the WDSVR Register is also counted as a
WATCHDOG service.

TABLE III. WATCHDOG Service Register (WDSVR)

1
3

Clock
Monitor
0

2k-8k tc Cycles
2k-16k tc Cycles
2k-32k tc Cycles
2k-64k tc Cycles

The WATCHDOG and Clock Monitor are disabled during
reset. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG Window Select (bits 6, 7 of the
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
WDSVR Register) enabled. Thus, a Clock Monitor error will
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, including the case where the oscillator fails to start.

Nothing (except another ST) can interrupt an ST being
serviced.

0
1
0
1

Clock Monitor

The ST has the highest rank among all interrupts.

Key Data

Service Window
(Lower-Upper Limits)

Window
Select

WDSVR
BitS

The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 and 6 of the WDSVR register allow
the user to pick an upper limit of the service window.
Table IV shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flexibility in choosing the WATCHDOG service window prevents
any undue burden on the user software.

The WATCHDOG service window will restart when the
WDOUT pin goes high It is recommended that the user tie
the WDOUT pin back to Vee through a resistor in order to
pull WDOUT high.

Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the
5-bit Key Data field. The key data is fixed at 01100. Bit 0 of
the WDSVR Register is the Clock Monitor Select bit.

1-466

(')

WATCHDOG Operation

(Continued)

"'C

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TABLE V. WATCHDOG Service Actions
Key
Data

Window
Data

(')

Clock
Monitor

r
.......

Action

(')

Match

Valid Service: Restart Service Window

Don't Care

Mismatch

Don't Care

Error: Generate WATCHDOG Output

"-I

Mismatch

Don't Care

Error: Generate WATCHDOG Output

(')

Don't Care

Mismatch

Error: Generate WATCHDOG Output

"'C

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..a::.

TABLE VI. MICROWIRE/PLUS
Master Mode Clock Select
SL1

SLO

0
0
1

0
1
x

2 x te
4 X te
8 X te

Where te is the instruction cycle clock
• With the single-pin RIC oscillator mask option selected
and the CLKDLY bit reset, the WATCHDOG service window will resume following HALT mode from where it left
off before entering the HALT mode.

The CLOCK MONITOR forces the G1 pin low upon detecting a clock frequency error. The CLOCK MONITOR error
will continue until the clock frequency has reached the minimum specified value, after which the G 1 output will enter
the high impedance TRI-STATE mode following 16 te-32 te
clock cycles. The CLOCK MONITOR generates a continual
CLOCK MONITOR error if the oscillator fails to start, or fails
to reach the minimum specified frequency. The specification
for the CLOCK MONITOR is as follows:
1/te

> 10kHz-No clock rejection.

1/te

< 10Hz-Guaranteed clock rejection.

• With the crystal oscillator mask option selected, or with
the single-pin RIC oscillator mask option seloctod and
the CLKDL Y bit set, the WATCHDOG sorvico window will
be set to its selected value from WDSVR following HALT.
Consequently, the WATCHDOG should not be servicod
for at least 2048 instruction cycles following HALT, but
must be serviced within the selected window to avoid a
WATCHDOG error.

WATCHDOG AND CLOCK MONITOR SUMMARY

• The IDLE timer TO is not initialized with RESET.

The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted:

• The user can sync in to the IDLE counter cycle with an
IDLE coulli8( (TO) inh:H1lJfJL UI
II10llilulillY lilt:! TO;::i~D
flag. The TOPND flag is set whenever the thirteenth bit of
the IDLE counter toggles (every 4096 instruction cycles).
The user is responsible for resetting the TOPND flag.

• Both WATCHDOG and CLOCK MONITOR detector circuits are inhibited during RESET.
• Following RESET, the WATCHDOG and CLOCK MONITOR are both enabled, with the WATCHDOG having the
maximum service window selected.

• A hardware WATCHDOG service occurs just as the device exits the IDLE. mode. Consequently, the
WATCHDOG should not be serviced for at least 2048
instruction cycles following IDLE, but must be serviced
within the selected window to avoid a WATCHDOG error.

• The WATCHDOG service window and CLOCK MONITOR enableldisable option can only be changed once,
during the initial WATCHDOG service following RESET.

• Following RESET, the initial WATCHDOG service (where
the service window and the Clock Monitor enablel disable must be selected) may be programmed anywhere
within the maximum service window (65,536 instruction
cycles) initialized by RESET. Note that this initial
WATCHDOG service may be programmed within the initial 2048 instruction cycles without causing a
WATCHDOG error.

• The initial WATCHDOG service must match the key data
value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error.
• . Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG errors.
• The correct key data value cannot be read from the
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all O's.

Detection of Illegal Conditions
The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.

1-467

...J

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a..

.......

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oco

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a..
o

MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master. or as a Slave. Figure 13 shows
how two COP888 microcontrollers and several peripherals
may be interconnected using the MICROWIRE/PLUS arrangements.

Detection of Illegal
Conditions (Continued)
The subroutine stack grows down for each call Oump to
subroutine), interrupt, or PUSH, and grows up for each return or POP. The stack pointer is initialized to RAM location
06F Hex during reset. Consequently, if there are more returns than calls, the stack pointer will pOint to addresses
070 and 071 Hex (which are undefined RAM). Undefined
RAM from addresses 070 to 07F Hex is read as all 1's,
which in turn will cause the program to return to address
7FFF Hex. This is an undefined ROM location and the instruction fetched (all O's) from this location will generate a
software interrupt signaling an illegal condition.

Warning
The SIO register should only be loaded when the SK clock
is low. Loading the SIO register while the SK clock is high
will result in undefined data in the SIO register. SK clock is
normally low when not shifting.

Thus, the chip can detect the following illegal conditions:

1. Executing from undefined ROM
2. Over "POP"ing the stack by having more returns than
calls.
When the software interrupt occurs, the user can re-initialize
the stack pOinter and do a recovery procedure before restarting (this recovery program is probably similar to that
following reset, but might not contain the same program
initialization procedures).

Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is
low.
MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE
Master always initiates all data exchanges. The MSEL bit in
the CNTRL register must be set to enable the SO and SK
functions onto the G Port. The SO and SK pins must also be
selected as outputs by setting appropriate bits in the Port G
configuration register. Table VII summarizes the bit settings
required for Master mode of operation.

MICROWIRE/PLUS
MICROWIRE/PLUS is a serial synchronous communications interface. The MICROWIRE/PLUS capability enables
the device to interface with any of National Semiconductor's
MICROWIRE peripherals (Le. AID converters, display drivers, E2PROMs etc.) and with other microcontrollers which
support the MICROWIRE interface. It consists of an 8-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK). Figure 12
shows a block diagram of the MICROWIRE logic.

MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bit in the Port G configuration register. Table V summarizes the settings required to enter the
Slave mode of operation.

The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIREI
PLUS arrangement with the internal clock source is called
the Master mode of operation. Similarly, operating the
MICROWIRE/PLUS arrangement with an external shift
clock is called the Slave mode of operation.

1-------+ INTERRUPT

~=-====~---------+so

Alternate SK Phase Operation
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register.
In both the modes the SK is normally low. In the normal
mode data is shifted in on the rising edge of the SK clock
and the data is shifted out on the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK clock in the normal mode. In the alternate SK phase
mode the SIO register is shifted on the rising edge of the SK
clock.

TL/DD12063-14

FIGURE 12. MICROWIRE/PLUS Block Diagram

The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. In the
master mode, the SK clock rate is selected by the two bits,
SLO and SL 1, in the CNTRL register. Table VI details the
different clock rates that may be selected.

1-468

o-C
co
.....
co

MICROWIRE/PLUS (Continued)
TABLE VII
G5
(5K)
Config.
Bit

G4
(50)
Con fig.
Bit

G4
Fun.

or-

G5
Fun.

.......

o
o

Operation

-C

Int. SK

MICROWIRE/PLUS Master

co
.....
co

TRI-STATE

Int. SK

MICROWIRE/PLUS Master

Ext.SK

MICROWIRE/PLUS Slave

TRI-STATE

Ext.SK

MICROWIRE/PLUS Slave

This table assumes that the control flag MSEL is set.

,/5

CHIP SELECT LINES

...

8 - BIT

I/o

AID

LINES

.... ....

COP8
~ (MASTER)

EEPROM

CONVERTER

...

LCD
DISPLAY
DRIVER

VF
DISPLAY
DRIVER
COP8
(SLAVE)

DO ClK 01

ClK 01

! i

I/o
LINES

SK
..

TLlDD1206315

FIGURE 13. MICROWIRE/PLU5 Application

1·469

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v

Memory Map

Addressing Modes

c..

All RAM, ports and registers (except A and PC) are mapped
into data memory address space

There are ten addressing modes, six for operand addressing and four for transfer of control.

co
......
co

.......

....I

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co
co
......
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c..
oo

Address

OPERAND ADDRESSING MODES

Contents

00 to 6F

On-Chip RAM bytes

70 to BF

Unused RAM Address Space

CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CBtoCF

DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DDto DF

Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port D Data Register
Reserved for Port D

EO to E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF

FO to FB
FC
FD
FE
FF

On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
Reserved

Register Indirect
This is the "normal" addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.
Register Indirect (with auto post Increment or
decrement
pointer)

This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that
automatically post increments or decrements the B or X register after executing the instruction.
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
Immediate
The instruction contains an 8-bit immediate field as the operand.
Short Immediate
This addressing mode is used with the Load B Immediate
instruction. The instruction contains a 4-bit immediate field
as the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
TRANSFER OF CONTROL ADDRESSING MODES
Relative
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
program location. JP has a range from -31 to +32 to allow
a 1-byte relative jump (JP + 1 is implemented by a NOP
instruction). There are no "pages" when using JP, since all
15 bits of PC are used.
Absolute
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any location in the current 4k program memory segment.
Absolute Long
This mode is used with the JMPL and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any location in the current 4k program memory space.
Indirect
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits
of PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruction.

Note: Reading memory locations 70-7F Hex will return all ones. Reading
other unused memory locations will return undefined data.

Note: The VIS is a special case of the Indirect Transfer of Control addressing mode. where the double byte vector associated with the interrupt
is transferred from adjacent addresses in the program memory into
the program counter (PC) in order to jump to the associated interrupt
service routine.

1-470

C')

Instruction Set

""C

co
......
co
co

X
SP
PC
PU
PL
C
HC
GIE
VU
VL

Symbols
[B]

[X]
MD
Mem
Meml
Imm
Reg
Bit
~
~

C')

r......
C')

""C

co
......
co
~

C')

1-471

..J

Instruction Set (Continued)

INSTRUCTION SET

o
......
..J
o
co
co

""co

o
o

A~A

ADD
ADC

A,Meml
A,Meml

ADD
ADD with Carry

SUBC

A,Meml

Subtract with Carry

AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND

A,Meml
A,lmm
A,Meml
A,Meml
MD,Imm
A,Meml
A,Meml
A,Meml
#
Reg
#,Mem
#,Mem
#,Mem

X
X
LD
LD
LD
LD
LD

A,Mem
A,[X]
A,Meml
A,[X]
B,lmm
Mem,lmm
Reg,lmm

EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD B with Immed.
LoaD Memory Immed.
LoaD Register Memory Immed.

X
X
LD
LD
LD

A, [B ±]
A, [X ±]
A, [B±]
A, [X±]
[B±],Imm

EXchange A with Memory [B)
EXchange A with Memory [X]
LoaD A with Memory [B)
LoaD A with Memory [X]
LoaD Memory [B) Immed.

CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH

A
A
A

CLeaR A
INCrementA
DECrementA
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
SetC
Reset C
IFC
IFNotC
POP the stack into A
PUSH A onto the stack

A~O

PU ~ [VU], PL ~ [VL]
PC ~ ii (ii = 15 bits, 0 to 32k)
PCg ... 0 ~ i (i = 12 bits)
PC ~ PC + r (r is -31 to +32, except 1)
[SP] ~ PL, [SP-1] ~ PU,SP-2, PC ~ ii
[SP] ~ PL, [SP-1] ~ PU,SP-2, PCg ... 0 ~ i
PL ~ ROM (PU,A)
SP+2, PL ~ [SP], PU ~ [SP-1]
SP+2, PL ~ [SP],PU ~ [SP-1]
SP+2, PL ~ [SP],PU ~ [SP-1],GIE ~ 1
[SP] ~ PL, [SP-1] ~ PU, SP-2, PC ~ OFF
PC~ PC+1

VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

A
A
A
A

A
A
Addr.
Addr.
Disp.
Addr.
Addr.

+ Meml
A ~ A + Meml + C, C ~ Carry,
HC ~ Half Carry
A ~ A - Meml + C, C ~ Carry,
HC ~ Half Carry

A~AandMeml

Skip next if (A and Imm) = 0
A~AorMeml

A ~ AxorMeml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A =1= Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B =1= Imm
Reg ~ Reg- 1, Skip if Reg = 0
1 to bit, Mem (bit = 0 to 7 immediate)
Oto bit, Mem
If bit in A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
A~Mem
A~[X]
A~Meml

A~[X]
B~lmm

Mem~lmm
Reg~lmm

[B], (B

B ± 1)

A~[X],(X~±1)

A ~ [B], (B ~ B ± 1)
A ~ [X], (X ~ X±1)
[B) ~ Imm, (B ~ ±1)
A~A+

A~A-1

A ~ ROM (PU,A)
A ~ BCD correction of A (follows ADC, SUBC)
C ~ A7 ~ ... ~ AO ~ C
C~A7 ~ ... ~ AO~C
A7 ... A4 ~ A3 ... AO
C~ 1,HC~ 1
C~O,HC~O

IF C is true, do next instruction
If C is not true, do next instruction
SP ~ SP + 1, A ~ [SP]
[SP] ~A,SP~ SP-1

1-472

Instruction Execution Time

"'C

Most instructions are single byte (with immediate addressing mode instructions taking two bytes).
Most single byte instructions take one cycle time to execute.
See the BYTES and CYCLES per INSTRUCTION table for
details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles
for each instruction in the format of byte/cycle.

Instructions Using A and C
CLRA
INCA
DECA
LAID
DCORA
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ

Logic and Arithmetic Instructions
[B)

Direct

ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4

SBIT
RBIT
IFBIT

1/1
1/1
1/1

3/4
3/4
3/4

RPND

1/1

Immed.
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2

1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2

Transfer of Control
Instructions

co
.......
CO
co

JMPL
JMP
JP
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP

3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
117
1/1

r......
0

"'C
CO

.......

CO
~

1/3

Memory Transfer Instructions
Register
Indirect
[B)

Direct Immed.

[X]

XA,~

1/1

1/3

2/3

LDA,·

1/1

1/3

2/3

2/2

[X+,X-]

1/2

1/3

1/2

1/3

< 16)

LDB,lmm

1/1

(IF B

LDB,lmm

2/3

(IFB> 15)

LDMem,imm

2/2

3/3

LD Reg, imm

2/3

IFEQMD,lmm

3/3

2/2

• = > Memory location addressed by B or X or directly.

1-473

COP8788CL/COP8784CL

COP8788CL/COP8784CL Opcode Table
UPPER NIBBLE

.l:>.

-..J
.1'>0

JP -15 JP -31 LDOFO, #i

DRSZOFO

RRCA

ADCA,
#i

ADCA,[B]

JP -14 JP -30 LD OF1, #i

DRSZOF1

SUBCA,
#i

SUBCA,[B] IFBIT
1,[B]

JP -13 JP -29 LD OF2, #i

DRSZOF2

XA,
[X+]

XA,
[B+]

IFEQA,
#i

IFEQA,[B]

IFBIT
2,[B]

JP -12 JP -2B LD OF3, #i

DRSZOF3

XA,
[X-]

XA,
[B-]

IFGTA,
#i

IFGTA,[B]

JP -11 JP -27 LD OF4, #i

DRSZOF4

VIS

LAID

ADD A,
#i

JP -10 JP -26 LDOF5, #i

DRSZOF5

RPND

JID

JP -9

JP -25 LDOF6, #i

DRSZOF6

XA,[X]

JP -B

JP -24 LDOF7, #i

DRSZOF7

JP -7

JP -23 LDOFB, #i

DRSZOFB

JSR
xOOO-xOFF

JMP
JP +17 JP - 15 0
xOOO-xOFF

LD B,#OE IFBNE 1

JSR
x100-x1FF

JMP
JP +1B JP - 14 1
x100-x1FF

LD B,#OD IFBNE2

JSR
x200-x2FF

'JMP
JP +19 JP - 13 2
x200-x2FF

IFBIT
3,[B]

LD B,#OC IFBNE3

JSR
x300-x3FF

JMP
JP +20 JP - 12 3
x300-x3FF

ADDA,[B]

IFBIT
4,[B]

CLRA

LD B,#OB IFBNE4 .

JSR
x400-x4FF

JMP
JP +21 JP- 11 4
x400-x4FF

ANDA,
#i

ANDA,[B]

IFBIT
5,[B]

SWAPA LD B,#OA IFBNE 5

JSR
x500-x5FF

JMP
JP +22 JP - 10 5
x500-x5FF

XA,[B]

XORA,
#i

XORA,[B]

IFBIT
6,[B]

DCORA LDB,#09 IFBNE6

JSR
x600-x6FF

JMP
JP +23
x600-x6FF

JP - 9

ORA,#i

ORA,[B]

IFBIT
7,[B]

PUSHA LD B,#OB IFBNE7

JSR
x700-x7FF

JMp·
JP +24
x700-x7FF

JP - B

NOP

RLCA

IFC

SBIT
O,[B]

RBIT
O,[B]

LD B,#07 IFBNEB

JSR
xBOO-xBFF

JMP
JP +25
xBOO-xBFF

JP -7

LDA,#i I;

IFBITL ANDSZ LD B,#OF IFBNEO
O,[B]
A, #i

==
m

JP -22 LD OF9, #i

DRSZOF9

IFNE
A,[B]

IFEQ
Md,#i

IFNE
A,#i

IFNC

SBIT
1,[B]

RBIT
1,[B]

LD B,#06 IFBNE9

JSR
JMP
JP +26
x900-x9FF 'x900-x9FF

JP - 6

JP -5

JP -21 LDOFA, #i

DRSZOFA

LDA,
[X+]

LDA,
[B+]

LD [B+],
#i

INCA

SBIT
2,[B]

RBIT
2,[B]

LD B,#05 IFBNEOA

JSR
JMP
JP +27
xAOO-xAFF xAOO-xAFF

JP - 5

JP -4

JP -20 LDOFB, #i

DRSZOFB

LDA,
[X-]

LDA,
[B-]

LD [B-];
#i

DECA

SBIT
3,[B]

RBIT
3,[B]

LD B,#04 IFBNEOB

JSR
JMP
JP +2B
xBOO-xBFF xBOO-xBFF

JP - 4

JP -3

JP -19 LDOFC, #i

DRSZOFC LD Md,#i

JMPL

XA,Md

POPA

SBIT
4,[B]

RBIT
4,[BJ

LD B,#03 IFBNEOC

JSR
JMP
JP +29
xCOO-xCFF xCOO-xCFF

JP - 3

JP -2

JP -1B LDOFD, #i

DRSZOFD

JSRL

LDA,Md

RETSK

SBIT
5,[B]

RBIT
5,[B]

LD B,#02 IFBNEOD

JSR
JMP
JP +30
xDOO-xDFF xDOO-xDFF

JP -2

JP -1

JP -17 LDOFE, #i

DRSZOFE LDA,[X]

RET

SBIT
6,[B]

RBIT
6,[B]

LD B,#01

IFBNEOE

JSR
JMP
JP +31
xEOO-xEFF xEOO-xEFF

JP - 1

JP -0

JP -16 LDOFF, #i

DRSZOFF

RETI

SBIT
7,[B]

RBIT
7,[B]

LD B,#OO IFBNEOF

JSR
JMP
JP +32
xFOO-xFFF xFOO-xFFF

JP - 0

Where,
i is the immediate data
Md is a directly addressed memory location
* is an unused opcode
Note: The opcode 60 Hex is also the opcode for IFBIT #i,A.
-

LDA,[B] LD [B],#i

LDB,#i

::0

JP -6

DIR

r
0

m
r
m

Ordering Information and Development Support
COP8788CL/CIP8784CL Ordering Information
Clock
Option

Package

Emulates

COP8788CLV-X
COP8788CLV-R*

Crystal

44 PLCC

COP888CL

COP8788CLN-X
COP8788CLN-R *

Crystal

COP8784CLN-X
COP8784CLN-R *

Crystal

COP8784CLWM-X*
COP8784CLWM-R*

Crystal

Device Number

IN-CIRCUIT EMULATOR
The MetaLink iceMASTERTM-COP8 Model 400 In-Circuit
Emulator for the COP8 family of microcontrollers features
high·performance operation, ease of use, and an extremely
flexible user-interface for maximum productivity. Interchangeable probe cards, which connect to the standard
common base, support the various configurations and packages of the COP8 family.

RIC
40 DIP

COP888CL

RIC
28 DIP

COP884CL

28S0

COP884CL

The iceMASTER provides real-time, full-speed emulation up
to 10 MHz, 32 kBytes of emulation memory and 4k frames
of trace buffer memory. The user may define as many as
32k trace and break triggers which can be enabled, disabled, set or cleared. They can be simple triggers based on
code address, direct address, opcode value, opcode class
or immediate operand. Complex breakpoints can be ANDed
and ORed together. Trace information consists of address
bus values, opcodes and user-selectable probe clips status
(external event lines). The trace buffer can be viewed as
raw hex or as disassembled instructions. The probe clip bit
values can be displayed in binary, hex or digital waveform
formats.

RIC
RIC

'Check with the local sales office about the availability.

PROGRAMMING SUPPORT
Programming of these emulator devices is supported by different sources. The following programmers are certified for
programming these One-Time Programmable emulator devices:
EPROM Programmer Information
Manufacturer
and Product

U.S. Phone
Number

Europe Phone
Number

(602)926-0797 Germany:
+49·8141·1030

p 5 x Power Supply Rise Time

FIGURE 4. Recommended Reset Circuit

6.8

Oscillator Circuits

CKI

CKO

I I

200k
~

200 pF

1. Oscillator operation mode-11
2. Internal switching current-12

CKI

3. Internal leakage current-13

CKol

~-~i-r-l

4. Output source current-14
S. DC current caused by external input not at Vee or
GND-IS

F"'I

Current Drain

~C2

= SV
= sv

The total current drain of the chip depends on:

......
\

50 pF

Figure 5 shows the Crystal and A/C diagrams.

100

Note: 3k

.. ,,"

Vee

6. DC reference current contribution from the AID
converter-16
7. Clock Monitor current when enabled-I?

Thus the total current drain, It, is given as

It = 11 + 12 + 13 + 14 + IS + 16 + 17
To reduce the total current drain, each of the above components must be minimum.

TLIDD/12062-7

FIGURE 5. Crystal and RIC Oscillator Diagrams

The chip will draw more current as the CKI input frequency
increases up to the maximum 10 MHz value. Operating with
a crystal network will draw more current than an external
square-wave. Switching current, governed by the equation,
can be reduced by lowering voltage and frequency. Leakage current can be reduced by lowering voltage and temperature. The other two items can be reduced by carefully
designing the end-user's system.

CRYSTAL OSCILLATOR
CKI and CKO CAn hf! ~nnnl?ctt:'d to m~ke
crystal (or resonator) controlled oscillator.

~ c!c~cd

!ccp

Table I shows the component values required for various
standard crystal values.
TABLE I. Crystal Oscillator Configuration, T A = 25°C
R1
(k!l)

R2
(M!l)

C1
(pF)

200

12 = C

C2
(pF)

CKI Freq
(MHz)

30-36

Vee = 5V

30-36

Vee = 5V

100-1S0

0.455

Vee = 5V

Conditions

xVxf

where C = equivalent capacitance of the chip
V = operating voltage
f = CKI frequency

1-485

o
o"

Table II shows the variation in the oscillator frequencies as
functions of the component (A and C) values.

R
(k!l)

GND

"'C

u.
o
-.::r
co
.....
co
DO
o
.......
u.
oco
co
.....
co
DO

Control Registers
CNTRL REGISTER (ADDRESS X'OOEE)

ICNTRL REGISTER (ADDRESS X'OOES)

The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:

The ICNTRL register contains the following bits:

SL 1 & SLO Select the MICROWIRE/PLUS clock divide by
(00 = 2, 01 = 4, 1x = 8)
IEDG

External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)

MSEL

Selects G5 and G4 as MICROWIRE/PLUS signals SK and SO respectively

T1CO

Timer T1 Start/Stop control in timer
Timer T1 Underflow Interrupt Pending Flag .in
timer mode 3

T1C1

Timer T1 mode control bit

T1C2

Timer T1 mode control bit

T1C3

Timer T1 mode control bit

I T1C3 I T1C2 I T1C1 I T1CO I MSEL I IEDG I SL1
Bit 7

Enable external interrupt

BUSY

MICROWIRE/PLUS busy shifting flag

EXPND

External interrupt pending

T1 ENA

Timer T1 Interrupt Enable for Timer Underflow or
T1A Input capture edge

IT1PNDAI T1ENA I EXPND I BUSY I EXEN I

Timer TO Interrupt Enable (Bit 12 toggle)

TOPND

Timer TO Interrupt pending
Port Interrupt Enable (Multi-Input Wakeup/

WEN In PNDBI n ENB I

Bit7

T1 PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1 A capture
edge in mode 3)

MICROWIRE/PLUS interrupt pending

TOEN

BitO

The T2CNTRL register contains the following bits:

Global interrupt enable (enables interrupts)

Bit7

Enable MICROWIRE/PLUS interrupt

IUnused I LPEN I TOPND I TOEN I WPND I

SLO

EXEN

WEN
WPND

Bit 7 could be used as a flag

GIE

Half Carry Flag

Timer T1 Interrupt Pending Flag for T1 B capture
edge

T2CNTRL Register (Address X'00C6)

PSW REGISTER (ADDRESS X'OOEF)

Carry Flag

T1 PNDB

Interrupt)

The PSW register contains the following select bits:

Timer T1 Interrupt Enable for T1 B Input capture
edge

LPENL

BitO

T1 ENB

GIE
Bit 0

T2ENB

Timer T2 Interrupt Enable for T2B Input capture
edge

T2PNDB

Timer T2 Interrupt Pending Flag for T2B capture
edge

T2ENA

Timer T2 Interrupt Enable for Timer Underflow or
T2A Input capture edge

T2PNDA

Timer T2 Interrupt Pending Flag (Autoreload RA
in mode 1, T2 Underflow in mode 2, T2A capture
edge in mode 3)

T2CO

Timer T2 Start/Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3

T2C1

Timer T2 mode control bit

T2C2

Timer T2 mode control bit

T2C3

Timer T2 mode control bit

I T2C3 I T2C2 I T2C1

Bit7

1-486

I T2CO IT2PNDAI T2ENA IT2PNDBI T2ENB I
BitO

(')

Timers

"tJ
Q)

The device contains a very versatile set of timers (TO, T1,
T2). All timers and associated auto reload/ capture registers
power up containing random data.

Figure 6 shows a block diagram for the timers.
TIMER TO (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer TO, which is a
16-bit timer. The Timer TO runs continuously at the fixed
rate of the instruction cycle clock, te. The user cannot read
or write to the IDLE Timer TO, which is a count down timer.

.......
Q)
Q)

(')

-n
......
(')

"tJ

.......

Q)
~

(')

-n

The control bits TxC3, TxC2, and TxC1 allow selection of
the different modes of operation.

The Timer TO supports the following functions:

Mode 1. Processor Independent PWM Mode

Exit out of the Idle Mode (See Idle Mode description)

As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention.

WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode

The IDLE Timer TO can generate an interrupt when the thirteenth bit toggles. This toggle is latched into the TOPND
pending flag, and will occur every 4 ms at the maximum
clock frequency (te = 1s). A control flag TOEN allows the
interrupt from the thirteenth bit of Timer TO to be enabled or
disabled. Setting TOEN will enable the interrupt, while resetting it will disable the interrupt.

In this mode the timer Tx counts down at a fixed rate of te.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.

TIMER T1 AND TIMER T2
The device has a set of two powerful timer/counter blocks,
T1 and T2. The associated features and functioning of a
timer block are described by referring to the timer block Tx.
Since the two timer blocks, T1 and T2, are identical, all comments are equally applicable to either timer block.

The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.

n
I
N

T
U+----+U E

~~~....

~:::rn]--.......J

R
A

_-..--......

H-----+II

......

8
U

1+-----.....

TLIDD/12062-8

FIGURE 6. Timers

1-487

"="
co
......
co
DO
o
.......

Timers

(Continued)
Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.

Figure 7 shows a block diagram of the timer in PWM mode.

o
co
co
......

Mode 2. External Event Counter Mode

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TIO
OUTPUT
TL/DD/12062-9

FIGURE 7. Timer InPWM Mode
The underflows can be programmed to toggle the TxA output pin. The underflows can also be programmed to generate interrupts.
Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control enable flags, TxENA and TxENB, allow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the
timer. Setting the timer enable flag TxENB will cause an
interrupt when a timer underflow causes the RxB register to
be reloaded into the timer. Resetting the timer enable flags
will disable the associated interrupts.

In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
Figure 8 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock.

Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode.

INTERNAL DATA BUS

16-BIT AUTO-RELOAD REGISTER
TIMER
UNDERFLOW
INTERRUPT

16-BIT TIMER/COUNTER
EXT
ClK
EDGE SELECTOR
lOGIC

TL/DD/12062-10

FIGURE 8. Timer In External Event Counter Mode

1-488

(")

Timers (Continued)

sequently, the TxCO control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.

Rgure 9 shows a block diagram of the timer in Input Capture
mode.

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(")

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(")

TIMER CONTROL FLAGS
The timers T1 and T2 have indentical control structures.
The control bits and their functions are summarized below.

The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.

TxCO

'TI

Timer Start/Stop control in Modes 1 and 2 (Processor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in Mode 3
(Input Capture)

TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag

TxENA

Timer Interrupt Enable Flag

TxENB

Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled

o=
TxC3

Timer Interrupt Disabled

Timer mode control

TxC2

Timer mode control

TxC1

Timer mode control

INTERRUPT

TIO INPUT

~"'-

___

...

EDGE SELECTOR
LOGIC

TLIDD/12062-11

FIGURE 9. Timer in Input Capture Mode

1-489

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r-----------------------------------------------------------------------~

Timers

(Continued)

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The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:

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......

TxC3

TxC2

TxC1

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MODE 2 (External Event Counter)

D..

Interrupt B
Source

Timer
Counts On

Timer Underflow

Pos. TxB Edge

TxA Pos. Edge

Timer Underflow

Pos. TxB Edge

TxA Neg. Edge

MODE 1 (PWM) TxA Toggle

Autoreload RA

Autoreload RB

MODE 1 (PWM) No TxA Toggle

Autoreload RA

Autoreload RB

Pos. TxA Edge or·
Timer Underflow

Pos. TxB Edge

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Interrupt A
Source

Timer Mode

MODE 3 (Capture) Captures:
TxA Pos. Edge
TxB Pos. Edge

MODE 3 (Capture) Captures:
TxA Pos. Edge
TxB Neg. Edge

Pos. TxA Edge or
Timer Underflow

Neg. TxB Edge

MODE 3 (Capture) Captures:
TxA Neg. Edge
TxB Pos. Edge

Neg. TxB Edge or
Timer Underflow

Pos. TxB Edge

MODE 3 (Capture) Captures:
TxA Neg. Edge
TxB Neg. Edge

Neg. TxA Edge or
Timer Underflow

Neg. TxB Edge

Since a crystal or ceramic resonator may be selected as the
OSCillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the to instruction cycle clock. The tc
clock is derived by dividing the oscillator clock down by a
factor of 10. The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE timer is clocked only
when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger speCifications. This Schmitt trigger
is not part of the oscillator closed loop. The startup timeout
from the IDLE timer enables the clock signals to be routed
to the rest of the chip.

Power Save Modes
The, device offers the user two power save modes of operation: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscillator circuitry and timer TO are active but all other microcontroller activities are stopped. In either mode, all on-board
RAM, registers, 1/0 states, and timers (with the exception of
TO) are unaltered.
HALT MODE
The device is placed in the HALT mode by writing a "1" to
the HALT flag (G7 data bit). All microcontroller activities,
including the clock, timers, and AID converter, are stopped.
The WATCHDOG logic is disabled during the HALT mode.
However, the clock monitor circuitry if enabled remains active and will cause the WATCHDOG output pin (WDOUT) to
go low. If the HALT mode is used and the user does not
want to activate the WDOUT pin, the Clock Monitor should
be disabled after the device comes out of reset (resetting
the Clock Monitor control bit with the first write to the
WDSVR register). In the HALT mode, the power requirements of the device are minimal and the applied voltage
(Vee> may be decreased to Vr (Vr = 2.0V) without altering
the state of the machine.

If an RC clock option is being used, the fixed delay is introduced optionally. A control bit, CLKDLY, mapped as configuration bit G7, controls whether the delay is to be introduced or not. The delay is included if CLKDLY is set, and
excluded if CLKDLY is reset. The CLKDLY bit is cleared on
reset.
The WATCHDOG detector circuit is inhibited during the
HALT mode. However, the clock monitor circuit if enabled
remains active during HALT mode in order to ensure a clock
monitor error if the device inadvertently enters the HALT
mode as a result of a runaway program or power glitch.

IDLE MODE
The device is placed in the IDLE mode by writing a "1" to
the IDLE flag (G6 data bit). In this mode, all activity, except

1-490

Power Save Modes (Continued)

""C

Due to the onboard 8k EPROM with port recreation logic,
the HALT/IDLE current is much higher compared to the
equivalent masked device.

the associated on-board oscillator circuitry,
the
WATCHDOG logic, the clock monitor and the IDLE Timer
TO, is stopped.

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........

As with the HALT mode, the device can be returned to normal operation with a reset, or with a Multi-Input Wake Up
from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the thirteenth
bit (representing 4.096 ms at internal clock frequency of
1 MHz, tc = 1 JLs) of the IDLE Timer toggles.
This toggle condition of the thirteenth bit of the IDLE Timer
TO is latched into the TOPND pending flag.

o
o

Multi-Input Wake Up
The Multi-Input Wake Up feature is used to return (Wake
Up) the device from either the HALT or IDLE modes. Alternately Multi-Input Wake Up/Interrupt feature may also be
used to generate up to 8 edge selectable external interrupts.
Figure 10 shows the Multi-Input Wake Up logic.

The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an
8-bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positiv~ odge. Changing
an edge select entails several steps in ordor to avoid a
pseudo Wake Up condition as a result of tho odgo chango.
First, the associated WKEN bit should be rosot, followod by
the edge select change in WKEDG. Next, the associatod
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.

Alternatively, the user can enter the IDLE mode with the
IDLE Timer TO interrupt disabled. In this case, the device
will resume normal operation with the instruction immediately following the "Enter IDLE Mode" instruction.
Note: It is necessary to program two NOP instructions following both the
set HALT mode and set IDLE mode instructions. These NOP instructions are necessary to allow clock resynchronization following the
HALT or IDLE modes.

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.......
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INTERNAL DATA BUS

TO INTERRUPT LOGIC

CHIP CLOCK
TLlDD/12062-12

FIGURE 10. Multi-Input Wake Up Logic

1-491

""C

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Multi-Input Wake Up

(Continued)
An example may serve to clarify this procedure. Suppose
we wish to change the edge select from positive (low going
high) to negative (high gOing low) for L Port bit 5, where bit 5
has previously been enabled for an input interrupt. The program would be as follows:

RMRBIT
RMSBIT
RMRBIT
RMSBIT

5,
5,
5,
5,

The Wake Up signal will not start the chip running immediately since crystal oscillators or ceramic resonators have a
finite start up time. The IDLE Timer (TO) generates a fixed
delay to ensure that the oscillator has indeed stabilized before allowing the device 40 execute instructions. In this
case, upon detecting a valid Wake Up signal, only the oscillator circuitry and the IDLE Timer TO are enabled. The IDLE
Timer is loaded with a value of 256 and is clocked from the
tc instruction cycle clock. The tc clock is derived by dividing
down the oscillator clock by a factor of 10. A Schmitt trigger
following the CKI on-chip inverter ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large
amplitude to meet the Schmitt trigger specifications. This
Schmitt trigger is not part of the oscillator closed loop. The
startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip.

WKEN
WKEDG
WKPND
WKEN

If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wake Up/Interrupt, a
safety procedure should also be followed to avoid inherited
pseudo Wake Up conditions. After the selected L port bits
have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired
edge selects, followed by the associated WKPND bits being
cleared.

If the RC clock option is used, the fixed delay is under software control. A control flag, CLKDLY, in the G7 configuration bit allows the clock start up delay to be optionally inserted. Setting CLKDL Y flag high will cause clock start up delay
to be inserted and resetting it will exclude the clock start up
delay. The CLKDLY flag is cleared during reset, so the clock
start up delay is not present following reset with the RC
clock options.

This same procedure should be used following reset, since
the L port inputs are left floating as a result of reset.
The occurrence of the selected trigger condition for MultiInput Wake Up is latched into a pending register called
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since WKPND is a pending
register for the occurrence of selected wakeup conditions,
tho device will not enter the HALT mode if any Wake Up bit
is both enabled and pending. Consequently, the user has
the responsibility of clearing the pending flags before attempting to enter the HALT mode.

AID Converter
The device contains an 8-channel, multiplexed input, successive approximation, AID converter. Two dedicated pins,
VREF and AGND are provided for voltage reference.

OPERATING MODES
The AID converter supports ratiometric measurements. It
supports both Single Ended and Differential modes of operation.

The WKEN, WKPND and WKEDG are all read/write registers, and are cleared at reset.

PORT L INTERRUPTS

Four specific analog channel selection modes are supported. These are as follows:

Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into
the same service subroutine.

Allow any specific channel to be selected at one time. The
AID converter performs the specific conversion requested
and stops.

The interrupt from Port L shares logic with the Wake Up
circuitry. The register WKEN allows interrupts from Port L to
be individually enabled or disabled. The register WKEDG
specifies the trigger condition to be either a positive or a
negative edge. Finally, the register WKPND latches in the
pending trigger conditions.

Allow any specific channel to be scanned continuously. In
other words, the user will specify the channel and the AID
converter will keep on scanning it continuously. The user
can come in at any arbitrary time and immediately read the
result of the last conversion. The user does not have to wait
for the current conversion to be completed.

Allow any differential channel pair to be selected at one
time. The A/D converter performs the specific differential
conversion requested and stops.
Allow any differential channel pair to be scanned continuously. In other words, the user will specify the differential
channel pair and the AID converter will keep on scanning it
continuously. The user can come in at any arbitrary time and
immediately read the result of the last differential conversion. The user does not have to wait for the current conversion to be completed.

Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If
he elects to disable the interrupt, then the device will restart
execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or
IDLE modes. In the other case, the device will first execute
the interrupt service routine and then revert to normal operation.

The A/D converter is supported by
registers, the result register and the
When the device is reset, the control
the AID is powered down. The AID
known data following reset.

1-492

two memory mapped
mode control register.
register is cleared and
result register has un-

AID Converter (Continued)
PRESCALER SELECT

Mode Select

Prescaler Select

Bits 7, 6, 5

Bits4,3

Bits 2,1,0

This 3-bit field is used to select one of the seven prescaler
clocks for the AID converter. The prescaler also allows the
AID clock inhibit power saving mode to be selected. The
following table shows the various prescaler options.

Bit 2

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CHANNEL SELECT

Single Ended mode:

Blt6
0
0

BitS
0
1
0

1
0
0
1

0
1
0

Bit6
0
0

Bit 5
0
1
0

0
0

0
1
0

2
3
4
5
6
7

Channel
Pairs (+, -)
0,1
1,0
2,3
3,2
4,5
5,4
6, 7
7,6

Bit 3
0
1

PRESCALER

MODE SELECT

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o

0
1

This 2-bit field is used to select the mode of operation (single conversion, continuous conversions, differential, single
ended) as shown in the following table.

Bit 4

Clock Select
Inhibit AID clock
Divide by 1
Divide by 2
Divide by4
Divide by 6
Divide by 12
Divide by8
Divide by 16

ACC Operation
The AID converter interface works as follows. Writing to the
AID control register ENAD initiates an AID conversion unless the prescaler value is set to 0, in which case the ADC
clock is stopped and the ADC is powered down. The conversion sequence starts at the beginning of the write to
ENAD operation powering up the ADC. At the first falling
edge of the converter clock following the write operation
(not counting the falling edge if it occurs at the same time
as the write operation ends), the sample signal turns on for
two clock cycles. The ADC is selected in the middle of the
sample period. If the ADC is in single conversion mode, the
conversion complete signal from the ADC will generate a
power down for the AID converter. If the ADC is in continuous mode, the conversion complete signal will restart the
conversion sequence by deselecting the ADC for one converter clock cycle before starting the next sample. The ADC
8-bit result is loaded into the AID result register (ADRSLT)
except during LOAD clock high, which prevents transient
data (resulting from the ADC writing a new result over an old
one) heing rA::Id from ADRSLT.

Channel
No.
0

Differential mode:

Bit?
0
0
0
0

Bit 0
0
1
0

This 3-bit field selects one of eight channels to be the VIN +.
The mode selection determines the VIN- input.

Bit?
0
0
0
0

Bit 1
0
0

Mode
Single Ended mode, single conversion

The AID converter takes 12 ADC clock cycles to complete
a conversion. Thus the minimum ADC conversion time is
7.2 p.s when a prescaler of 6 has been selected. These 12
ADC clock cycles necessary for a conversion consist of 1
cycle at the beginning for reset, 2 cycles for sampling, 8
cycles for converting, and 1 cycle for loading the result into
the AID result register (ADRSLT). This AID result register is
a read-only register. The user cannot write into ADRSLT.

Single Ended mode, continuous scan of a
single channel into the result register
Differential mode, single conversion
Differential mode, continuous scan of a
channel pair into the result register

1-493

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o

AID Converter (Continued)
The prescaler also allows an AID clock inhibit option, which
saves power by powering down the AID when it is not in
use.

Source impedances greater than 1 kn on the analog input
lines will adversely affect internal RC charging time during
input sampling. As shown in A'gure 11, the analog switch to
the DAC array is closed only during the 2 AID cycle sample
time. Large source impedances on the analog inputs. may
result in the DAC array not being charged to the correct
voltage levels, causing scale errors.

Note: The AID converter is also powered down when the device is in either
the HALT or IDLE modes. If the ADC is running when the device
enters the HALT or IDLE modes, the ADC will power down during the
HALT or IDLE, and then will reinitialize the conversion when the device comes out of the HALT or IDLE modes.

If large source resistance is necessary, the recommended
solution is to slow down the AID clock speed in proportion
to the source resistance. The AID converter may be operated at the maximum speed for Rs less than 1. kn. For Rs
greater than 1 kn, AID clock speed needs to be reduced.
For example, with Rs = 2 kn, the AID converter may be
operated at half the maximum speed. AID cOl")verter clock
speed may be slowed down by either increasing the AID
prescaler divide-by or decreasing the CKI clock frequency,
The AID clock speed may be reduced to its minimum frequency of 100 kHz.

Analog Input and Source Resistance Considerations

Figure 11 shows the AID pin model in single-ended mode.
The differential mode has a similiar AID pin model. The
leads to the analog inputs should be kept as short as possible. Both noise and digital clock coupling to an AID input
can cause conversion errors. The clock lead should be kept
away from the analog input line to reduce coupling. The
AID channel input pins do not have any internal output driver circuitry connected to them because this circuitry would
load the analog input signals due to output buffer leakage
current.

<2 J.LA
JUNCTION DIFFUSION/POLY
LEAKAGE COUPLER

4.5k

<2 J.LA
JUNCTION
LEAKAGE

cr:t..

<25 pF
DAC
ARRAY

AGND

GND

TLlDD/12062-13

·The analog switch is closed only during the sample time.

FIGURE 11. AID Pin Model (Single Ended Mode)

1-494

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Interrupts

""C

The device supports a vectored interrupt scheme. It supports a total of ten interrupt sources. The following table
lists all the possible interrupt sources, their arbitration ranking and the memory locations reserved for the interrupt vector for each source.

branch to the interrupt service routine of the highest priority
interrupt enabled and pending at the time of the VIS. Note
that this is not necessarily the interrupt that caused the
branch to address location OOFF Hex prior to the context
switching.

Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software
interrupt are maskable. Each of the maskable interrupts
have an Enable bit and a Pending bit. A maskable interrupt
is active if its associated enable and pending bits are set. If
GIE = 1 and an interrupt is active, then the processor 'will
be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described
in the Software Trap SUb-section.

Source

Description

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Software

INTR Instruction

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Vector Address
Hi·Low Byte
OyFE-OyFF
Cyi-C-Cyi-D

(2)

External

Pin GO Edge

OyFA-OyFB

(3)

Timer TO

Underflow

OyF8-0yF9

(4)

TimerT1

T1 AlUnderflow

OyF6-0yF7

(5)

TimerT1

T1B

OyF4-0yF5

MICROWIRE/PLUS

BUSY Goes Low

OyF2-0yF3

Reserved

for Future Use

OyFO-OyF1

Reserved

for UART

OyEE-OyEF

Reserved

for UART

OyEC-OyEO

(7)

TimerT2

T2A1Underflow

OyEA-OyEB

(8)

TimerT2

T2B

OyE8-0yE9

Reserved

for Future Use

OyE6-0yE7

(6)

The VIS instruction looks at all the active interrupts at the
time it is executed and performs an indirect jump to the beginning of the service routine of the one with the highest
rank. The addresses of the different interrupt service routines, called vectors, are chosen by the user and stored in
ROM in a table starting at 01 EO (assuming that VIS is located between OOFF and 010F). The vectors are 15-bit wide
and therefore occupy 2 ROM locations.

3. The PC (Program Counter) branches to address OOFF.
This procedure takes 7 tc cycles to execute.

(1) Highest

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2. The address of the instruction about to be executed is
pushed into the stack.

Arbitration
Ranking

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.......
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ex»

Reserved

for Future Use

OyE4-0yE5

(9)

Port LlWakeup

Port LEdge

OyE2-0yE3

(10) Lowest

Default

VIS Instr. Execution

OyEO-OyE1

without Any Interrupts
Y is VIS page, y =1= 0

1-495

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Interrupts

(Continued)

VIS and the vector table must be located in the same
256-byte block (OyOO to OyFF) except if VIS is located at the
last address of a block. In this case, the table must be in the
next block. The vector table cannot be inserted in the first
256-byte block.
The vector of the maskable interrupt with the lowest rank is
located at OyEO (Hi-Order byte) and OyE1 (Lo-Order byte)
and so forth in increasing rank number. The vector of the
maskable interrupt with the highest rank is located at OyFA
(Hi-Order byte) and OyFB (Lo-Order byte).

SOFTWARE TRAP
The Software Trap (ST) is a special kind of non-maskable
interrupt which occurs when the INTRinstruction (used to
acknowledge interrupts) is fetched from ROM and placed
inside the instruction register. This may happen when the
PC is pointing beyond the available ROM address space or
when the stack is over-popped.
When an ST occurs, the user can re-initialize the stack
pointer and do a recovery procedure (similar to RESET, but
not necessarily containing all of the same initialization procedures) before restarting.
The occurrence of an ST is latched into the ST pending bit.
The GIE bit is not affected and the ST pending bit (not
accessible by the user) is used to inhibit other interrupts
and to direct the program to the ST service routine with the
VIS instruction. The RPND instruction is used to clear the
software interrupt pending bit. This bit is also cleared on
reset.
The ST has the highest rank among all interrupts.

The Software Trap has the highest rank and its vector is
located at OyFE and OyFF.
If, by accident, a VIS gets executed and no interrupt is active, then the PC (Program Counter) will branch to a vector
located at OyEO-OyE1. This vector can point to the Software Trap (ST) interrupt service routine, or to another special service routine as desired.
Figure 12 shows the device Interrupt block diagram.

Nothing (except another ST) can Interrupt an ST being
serviced.

SOFTWARE TRAP

-------------f-----,

N M I - - - - - - - - - - - " " L_ _ _ _...J

INTERRUPT

INTERRUPT ENABLE
TL/DD/12062-14

FIGURE 12. Interrupt Block Diagram

1-496

~--------------------------------------------------------------------------~

WATCHDOG

"'C

Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the
5-bit Key Data field. The key data is fixed at 01100. Bit 0 of
the WDSVR Register is the Clock Monitor Select bit.

The device contains a WATCHDOG and clock monitor. The
WATCHDOG is designed to detect the user program getting
stuck in infinite loops resulting in loss of program control or
"runaway" programs. The Clock Monitor is used to detect
the absence of a clock or a very slow clock below a specified rate on the CKI pin.
The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named WDSVR
which Is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table III shows the WDSVR register.

Window
Select

WDSVR
Blt6

Service Window
(Lower-Upper Limits)

2k-8k te Cycles

2k-16k te Cycles

2k-32k te Cycles

2k-64k te Cycles

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The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, soloct
the WATCHDOG service window and match tho
WATCHDOG key data. Subsequent writes to tho WDSVR
register will compare the value being written by tho usor to
the WATCHDOG service window value and the key data
(bits 7 through 1) in the WDSVR Register. Table V shows
the sequence of events that can occur.

Clock Monitor .
The Clock Monitor aboard the device can be selected or
deselected under program control. The Clock Monitor is
guaranteed not to reject the clock if the instruction cycle
clock (1 ltd is greater or equal to 10kHz. This equates to a
clock input rate on CKI of greater or equal to 100 kHz.

WATCHDOG Operation

Clock
Monitor

Key Data

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.......
co
co
o
-n
.......

TABLE III. WATCHDOG Service Register (WDSVR)

TABLE V. WATCHDOG Service Actions
Key
Data
Match

Window
Data
Match

Clock
Monitor

Action
Valid Service: Restart Service Window

Match

Don't Care

Mismatch

Don't Care

Error: Generate WATCHDOG Output

Mismatch

Don't Care

Error: Generate WATCHDOG Output

Don't Care

Mismatch

Error: Generate WATCHDOG Output

1-497

co
co

r--

o
.......
u.
o
co
co
co

r--

o
o

WATCHDOG Operation

(Continued)
• The Clock Monitor detector circuit is active during both
the HALT and IDLE modes. Consequently, the device
inadvertently entering the HALT mode will be detected
as a Clock Monitor error (provided that the Clock Monitor
enable option has been selected by the program).

The user must service the WATCHDOG at least once before the upper limit of the service window expires. The
WATCHDOG may not be serviced more than once in every
lower limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period
between the lower and upper limits of the service window~
The first write to the WDSVR Register is also counted as a
WATCHDOG service.

• With the single-pin R/C oscillator mask option selected
and the CLKDLY bit reset, the WATCHDOG service window will resume following HALT mode from where it left
.off before entering the HALT mode.

The WATCHDOG service window will restart. when the
WDOUT pin goes high. It is recommended that the user tie
the WDOUT pin back to Vee through a resistor in order to
pull WDOUT high.

• The IDLE timer TO is not initialized with RESET.
• The user can sync in to.the IDLE counter cycle with an
IDLE counter (TO) interrupt or by monitoring the TOPND
flag. The TOPND flag is set whenever the thirteenth bit of
the IDLE counter toggles (every 4096 instruction cycles).
The user is responsible for resetting the TOPND flag.

A WATCHDOG service while.the WDOUT signal is active
will be· ignored. The state of the WDOUT pin is not guaranteed on reset, but if it powers up low then the WATCHDOG
will time out and WDOUTwill enter high impedance state.

• A hardware WATCHDOG service occurs just as the device exits the IDLE mode. Consequently, the
WATCHDOG should not be serviced for at least 2048
instruction cycles following IDLE, but must be serviced
within the selected window to avoid a WATCHDOG error.

The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum specified value, after which the G1 output will enter the high impedance TRI-STATE mode following 16 tc-32 tc clock cycles. The Clock Monitor generates a continual Clock Monitor error if the oscillator fails to start, or fails to reach the
minimum specified frequency. The specification for the
Clock Monitor is as follows:

1/tc > 10kHz-No clock rejection.
1/tc < 10Hz-Guaranteed clock rejection.
WATCHDOG AND CLOCK MONITOR SUMMARY

The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted:

Detection of Illegal Conditions
The device can detect various illegal conditions resulting·
from coding errors, transient noise, power supply voltage
drops,runaway programs, etc.

• Both the WATCHDOG and Clock Monitor detector circuits are inhibited during RESET.
• Following RESET, the WATCHDOG and CLOCK MONITOR are both enabled, with the WATCHDOG having the
maximum service window selected.

• The WATCHDOG service window and Clock Monitor enable/disable option can only be changed once, during
the initial WATCHDOG service following RESET.

The subroutine stack grows down for each call Oump to
subroutine), interrupt, or PUSH, and grows up for each return or POP, the stack pOinter is initialized to RAM location
06F Hex during reset. Consequently, if there are more returns than calls, the stack pointer will point to addresses
070 and 07i Hex (which are undefined RAM). Undefined
RAM from addresses 070 to 07F Hex is read as all 1's,
which in turn will cause the program to return to address
7FFF Hex. This is an undefined ROM location and the instruction fetched (all O's) from this location will generate a
software interrupt signaling an illegal condition.

• The initial WATCHDOG service must match the key data·
value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error.
• Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG errors.
• The correct key data value cannot be read from the
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all O's.

Thus, the chip can detect the following illegal conditions:
1. Executing from undefined ROM.

• The WATCHDOG detector circuit is inhibited during both
the HALT and IDLE modes.

2. Over "POP"ing the stack by having more returns than
calls.

1-498

MICROWIRE/PLUS OPERATION

Detection of Illegal Conditions

Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PlUS
mode either as a Master or as a Slave. Figure 14 shows
how two COP888 microcontrollers and several peripherals
may be interconnected using the MICROWIRE/PLUS arrangements.

(Continued)
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that
following reset, but might not contain the same program
initialization procedures).

MICROWIRE/PLUS
MICROWIRE/PlUS is a serial synchronous communications interface. The MICROWIRE/PlUS capability enables
the device to interface with any of National Semiconductor's
MICROWIRE peripherals (Le. AID converters, display drivers, E2PROMs etc.) and with other microcontrollers which
support the MICROWIRE interface. It consists of an 8-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK). Figure 13
shows a block diagram of the MICROWIRE/PlUS logic.

co
........
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0l:Io

-n

MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PlUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE
Master always initiates all data exchanges. The MSEl bit in
the CNTRl register must be set to enable the SO and SK
functions onto the G Port. The SO and SK pins must also be
selected as outputs by setting appropriate bits in the Port G
configuration register. Table VI summarizes the bit settings
required for Master mode of operation.
MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PlUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEl
bit in the CNTRl register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the FlppropriAtfl bit in thlO' Port G conf!g'..!raHcn register. Table VII summarizes the settings required to enter
the Slave mode of operation.

TL/DD/12062-15

FIGURE 13. MICROWIRE/PLUS Block Diagram
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIREI
PLUS arrangement with the internal clock source is called
the Master mode of operation. Similarly, operating the
tlXlt:Hlli:l.l

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r--------------------------+SO

~.~!CROWIRE/rlUS

o
o

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:;i1iit

clock is called the Slave mode of operation.
The CNTRl register is used to configure and control the
MICROWIRE/PlUS mode. To use the MICROWIRE/PLUS,
the MSEl bit in the CNTRl register is set to one. In the
master mode the SK clock rate is selected by the two bits,
SlO and Sl1, in the CNTRl register. Table VI details the
differe~t clock rates that may be selected.
TABLE VI. MICROWIRE/PLUS
Master Mode Clock Selection
SL1

SLO

x tc
4 x tc
8 x tc

Where 1c is the instruction cycle clock

1-499

co
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MICROWIRE/PLUS (Continued)

D-

o
.....
LL

oco

co
r-co
DO

I/O
LINES

COP8
(MASTER)

8 - BIT
A/D
CONVERTER

LCD
DISPLAY
DRIVER

EEPROM

VF
DISPLAY
DRIVER
COP472-3

I/o
COP8

LINES

(SLAVE)

SI H---''-f-+--.....+-i----+-t----t-t~_ISO
SO

SK
TL/DD/12062-16

FIGURE 14. MICROWIRE/PLUS Application

TABLE VII. MICROWIRE/PLUS Mode Selection
. G4{SO)
Config. Bit

G5 (SK)
Config. Bit

G4
Fun.

G5
Fun.

Operation

Int.SK

MICROWIRE/PLUS Master

TRI-STATE

Int.SK

MICROWIRE/PLUS Master

Ext. SK

MICROWIRE/PLUS Slave

TRI-STATE

Ext. Sk

MICROWIRE/PLUS Slave

This table assumes that the control flag MSEL is set.

clock. The SIO register is shifted on each falling edge of the
SK clock in the normal mode. In the alternate SK phase
mode the SIO register is shifted on the rising edge of the SK
clock.

Alternate SK Phase Operation

1-500

(')

Memory Map

""C
QO

All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Address
OOto 6F

On-Chip RAM bytes
Unused RAM Address Space

C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CDtoCF
DO
01
02
03
04
05

05
07
08
09
DA
DB
DC
DDto OF
EO to E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF

Contents

FO to FB
FC
FD
FE
FF

Contents

70 to BF
CO
C1
C2

Address

......
QO

Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA
Lower Byte
Timer T2 Autoload Register T2RA
Upper Byte
Timer T2 Autoload Register T2RB
Lower Byte
Timer T2 Autoload Register T2RB
Upper Byte
Timer T2 Control Register
WATCHDOG Service Register
(Reg:WDSVR)
MIWU Edge Select Register
(Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register (Reg:WKPND)
AID Converter Control Register
(Reg:ENAD)
AID Converter Result Register
(Reg:ADRSLT)
Reserved

On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
Reserved

Note: Reading memory locations 70-7F Hex will return all ones. Reading
other unused memory locations will return undefined data.

(')

'T1

........
(')

""C

......
QO
~

(')
'T1

Addressing Modes
There are ten addressing modes, six for operand addressing and four for transfer of control.
OPERAND ADDRESSING MODES
Register Indirect
This is the "normal" addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.
Register Indirect (with auto post increment or decrement
of pointer)
This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that
automatically post increments or decrements the B or X register after executing the instruction.
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.

Port L Data Register
Port l Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Pert G !~;:t!t P;~:i (~cz"d Gil:;)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port 0 Data Register
Reserved for Port 0

Immediate
The instruction contains an 8-bit immediate field as the operand.
Short Immediate
This addressing mode is used with the Load B Immediate
i',5tiuCtioil. Tht:: insilucliull l,;ullldim; CI. 4-bil immediate fieid
as the operand.
Indirect
This addressing mode is used with the lAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
TRANSFER OF CONTROL ADDRESSING MODES

Reserved
Timer T1 Autoload Register T1 RB
Lower Byte
Timer T1 Autoload Register T1 RB
Upper Byte
ICNTRl Register
MICROWIRE Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1 RA
Lower Byte
Timer T1 Autoload Register T1 RA
Upper Byte
CNTRL Control Register
PSW Register

Relative
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
program location. JP has a range from -31 to +32 to allow
a 1-byte relative jump (JP + 1 is implemented by a NOP instruction). There are no "pages" when using JP, since all 15
bits of PC are used.
Absolute
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any location in the current 4k program memory segment.

Note: Reading memory locations 70-7F Hex will return all ones. Reading
other unused memory locations will return undefined data.

1-501

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o
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Addressing Modes (Continued)

Instruction Set

Absolute Long
This mode is used with the JMPL and JSRL instructions,
with the instruction field of 15 bits replacing the entire 15
bits of the program counter (PC). This allows jumping to any
location in the current 4k program memory space.

REGISTER AND SYMBOL DEFINITION
Registers
A
8-Bit Accumulator Register
B
8-Bit Address Register
X
a-Bit Address Register
SP
a-Bit Stack Pointer Register
PC
15-Bit Program Counter Register
PU
Upper 7 Bits of PC
PL
Lower a Bits of PC
C
1 Bit of PSW Register for Carry
HC
1 Bit of PSW Register for Half Carry
GIE
1 Bit of PSW Register for Global Interrupt Enable
VU
Interrupt Vector Upper Byte
VL
Interrupt Vector Lower Byte

Indirect
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits
of PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruction.
Note: The VIS is a special case of the Indirect Transfer of Control addressing mode, where the double byte vector associated with the interrupt
is transferred from adjacent addresses in the program memory into
the program counter (PC) in order to jump to the associated interrupt
service routine.

Symbols
[B]
Memory Indirectly Addressed by B Register
[X]
Memory Indirectly Addressed by X Register
MD
Direct Addressed Memory
Mem Direct Addressed Memory or [B]
Meml Direct Addressed Memory or [B] or Immediate Data
Imm
a-Bit Immediate Data
Reg
Register Memory: Addresses FO to FF (Includes B,
X and SP)
Bit
Bit Number (0 to 7)
~
Loaded with
~
Exchanged with

1-502

o
Instruction Set

(Continued)

"tJ

en
.......
en
en

INSTRUCTION SET
A~A

ADD
ADC
SUBC
AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND

A,Meml
A,Meml
A,Meml
A,Meml
A,lmm
A,Meml
A,Meml
MD,Imm
A,Meml
A,Meml
A,Meml
#
Reg
#,Mem
#,Mem
#,Mem

ADD
ADD with Carry
Subtract with Carry
Logical AND
Logical AND Immed., Skip if Zero
Logical OR
Logical EXclusive OR
IF EQual
IF EQual
IF Not Equal
IF Greater Than
IF B Not Equal
Decrement Reg., Skip if Zero
Set BIT
Reset BIT
IFBIT
Reset PeNDing Flag

X
X
LD
LD

EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD B with Immed.
LoaD Memory Immed.
LoaD Register Memory Immed.

A~Mem

LD
LD

A,Mem
A,[X]
A,Meml
A,[X]
B,lmm
Mem,lmm
Reg,lmm

X
X
LD
LD
LD

A,[B]
A,[X]
A,[B]
A,[X]
[Bl.Imm

EXchange A with Memory [B]
EXchange A with Memory [X]
LoaD A with Memory [B]
LoaD A with Memory [X]
LoaD Memory [B] Immed

A~ [Bl.(B~B1)

CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH

A
A
A

CLeaR A
INCrementA
DECrement A

A
A
A
A

Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
SetC
Reset C
IFC
IFNotC
POP the stack into A
PUSH A onto the stack

Vector to Interrupt Service Routine
Jump absolute Long
Jump absolute
Jump relative short
Jump SubRoutne Long
Jump SubRoutine
Jump InDirect
RETurn from subroutine
RETurn and SKip
RETurn from Interrupt
Generate an Interrupt
No OPeration

PU ~ [VUl. PL ~ [VL]
PC ~ ii (ii = 15 bits, 0 to 32k)
PCg ... 0 ~ i (i = 12 bits)
PC ~ PC + r (r is -31 to +32, except 1)
[SP] ~ PL, [SP-1] ~ PU,SP-2, PC ~ ii
[SP] ~ PL, [SP-1] ~ PU,SP-2, PCg ... 0 ~ i
PL ~ ROM (PU,A)
SP + 2, PL ~ [SPl. PU ~ [SP-1]
SP + 2, PL ~ [SPl. PU ~ [SP-1]
SP + 2, PL ~ [SPl. PU ~ [SP-1], GIE ~ 1
[SP] ~ PL, [SP-1] ~ PU, SP-2, PC ~ OFF
PC~PC + 1

VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

Lc=.d .!'t.. !nD:rc:t frc:m

A
A
Addr.
Addr.
Disp.
Addr.
Addr

+ Meml
A ~ A + Meml + C, C ~ Carry, HC ~ Half Carry
A ~ A - Meml + C, C ~ Carry, HC ~ Half Carry
A~AandMeml

Skip next if (A and Imm)

A~AorMeml

A ~AxorMeml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A oF Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B =1= Imm
Reg ~ Reg - 1, Skip if Reg = 0
1 to bit, Mem (bit = 0 to 7 immediate)
Otobit, Mem
IF bit in A or Mem is two do next instruction
Reset Software Interrupt Pending Flag
A~[X]
A~Meml

A~[X]
B~lmm

Mem~lmm
Reg~lmm

A~[Xl.(X~1)
A~ [Bl. (B ~ B 1)
A ~ [Xl. (X ~ X 1)
[B] ~lmm,(B~B1)
A~O

A~A+

A~A-1

RC~.~

RC:vi (PU,A)

BCD correction of A (follows ADC, SUBC)
C~A7~ ... ~AO~C
C~A7~ ... ~AO~C
A7 ... A4 ~ A3 ... AO
C~1,HC~1
C~O,HC~O

IF C is true, do next instruction
IF C is not true, do next instruction
SP~SP t 1,A~ [SP]
[SP] ~ A, SP ~ SP - 1

1-503

o"T1
........
o

o"tJ
en
.......
en
-'='o"T1

r-----------------------------------------------------------------------------------~

;:;

Instruction Execution Time

U:
o
co
~

Bytes and Cycles per Instruction

The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.

Instructions Using A and C

. Logic and Arithmetic Instructions
Instr.

[B]

Direct

Immed.

ADD
ADC
SUBC
AND
OR
XOR
IFEQ
iFGT
IFBNE
DRSZ

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4

2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2

SBIT
RBiT
IFBIT

1/1
1/1
1/1

3/4
3/4
3/4

RPND

1/1

CLRA
INCA
DECA
LAID
DCORA
RRCA
RLCA
SWAPA
SC
RC
iFC
IFNC
PUSHA
POPA
ANDSZ

1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2

Transfer of Control
Instructions
JMPL
JMP
JP
JSRL
JSR
JID
ViS
RET
RETSK
RETI
INTR
NOP

1/3

Memory Transfer Instructions
Register
Indirect

Direct

[B]

[X]

XA,·

1/1

1/3

2/3

LOA,·

1/1

1/3

2/3

Immed.

[B+,B-]

[X+,X-]

1/2

1/3

1/2

1/3
(If B < 16)

1/1

LD B,lmm

(If B > 15)

2/3

LDB,lmm
LDMem,lmm

2/2

3/3

LD Reg,lmm

2/3

IFEQMD,lmm

3/3

2/2

• ;;" Memory location addressed by B or X or directly

1-504

3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
117
1/1

COP8788CF /COP8784CF Opcode Table
Upper Nibble

JP-15 JP-31 LDOFO,#i DRSZOFO

RRCA

ADCA,;!i

JP-14 JP-30 LD OF1,#i DRSZOF1

ADCA,[8] IF81T
0,[8]

SU8C
A,#i

SU8CA,[8] IF81T
1,[8]

JP-13 JP-29 LD OF2,#i DRSZOF2

XA,[X+]

XA,[8+]

IFEQ A,;!i

IFEQA,[8] IF81T
2,[8]

JP-12 JP-28 LD OF3,#i DRSZOF3

XA,[X-]

XA,[8-]

IFGTA,;!i

IFGTA,[8] IF81T
3,[8]

JP-11 JP-27 LD OF4,#i DRSZOF4

VIS

LAID

ADDA,#i

ADDA,[8] IF81T
4,[8]

LD OF5,#i DRSZOF5

RPND

JID

ANDA,#i

JP-9 JP-25 LD OF6,#i DRSZOF6

XA,[X]

XA,[8]

XORA,#i

JP-8 JP-24 LD OF7,#i DRSZOF7

JP-7 JP-23 LD OF8,#i DRSZOF8

NOP

JP-10 JR-26

ena

JP-6 JP-22 LDOF9,#i DRSZOF9

IFNE
A,[8]

.
RLCA

ANDSZ
A,#i

LD 8,#OF

IF8NEO

JMP
JP+17 JP-15 0
JSR
xOOO-xOFF xOOO-xOFF

LD 8,#OE

IF8NE 1

JSR
JMP
JP+18 JP-14 1
x100-x1FF x100-x1FF

LD 8,#OD

IF8NE2

JSR
JMP
JP+19 JP-13 2
x200-x2FF x200-x2FF

LD 8,#OC

IF8NE 3

JSR
JMP
JP+20 JP-12 3
x300-x3FF x300-x3FF

CLRA

LD8,#08

IF8NE4

JSR
JMP
JP+21 JP-11 4
x400-x4FF x400-x4FF

ANDA,[8] IF81T
5,[8]

SWAPA

LD 8,#OA

IF8NE5

XORA,[8] IF81T
6,[8]

DCORA

LD 8,#09

IF8NE6

JSR
JMR
JR+22 JP-10 5
x500-x5FF x500-x5FF
L
JSR
JMP
JP+23 JP-9 6 0
w
x600-x6FF x600-x6FF

PUSHA

LD 8,#08

IF8NE7

JSR
JMR
JR+24 JP-8
x700-x7FF x700-x7FF

S81T R8ITO,[8] LD 8,#07
0,[8]

IF8NE8

JSR
JMP
JP+25 JP-7
x800-x8FF x800-x8FF

8 N

ORA,#i

ORA,[8]

LDA,#i

IFC

IF81T
7,[8]

·
·
·

I
b
R81T 1,[8] LD 8,#06 IF8NE9
JSR
JMP
JP+26 JP-6 9 b
x900-x9FF x900-x9FF
I
R8IT2,[8] LD 8,#05 IF8NEOA
JMP
JP+27 JP-5 A e
JSR
xAOO-xAFF xAOO-xAFF

IFEQ
Md,#i

IFNE
A,#i

IFNC

S81T
1,[8]

LD
8,[8+]

LD [8+ ]"q

INCA

S81T
2,[8]

JP-4 JP-20 LDOF8,#i DRSZOF8 LDA,[X-] LDA[8-] LD [8-],1.Q

DECA

S81T R8IT3,[8] LD 8,#04 IF8NE08
JSR
JMP
JP+28 JP-4 B
3,[8]
x800-x8FF x800-x8FF

JP-3 JP-19 LDOFC,#i DRSZOFC

LD Md,#i

JMPL

XA,Md

POPA

S81T R81T 4,[8] LD 8,#03 IF8NEOC
JMP
JP+29 JP-3 C
JSR
4,[8]
xCOO-xCFF xCOO-xCFF

JP-2 JP-18 LDOFD,#i DRSZOFD

DIR

JSRL

LDA,Md

RETSK

S81T R8IT5,[8] LD 8,#02 IF8NEOD
JMP
JP+30 JP-2 0
JSR
5,[8]
xDOO-xDFF xDOO-xDFF

LDA,[X]

LDA,[8]

LD[8],#i

RET

JMP
JP+31
S81T R81T 6,[8] LD 8,#01 IF8NEOE
JSR
6,[8]
xEOO-xEFF xEOO-xEFF

LD8,#i

RETI

S81T R8IT7,[8] LD 8,#00 IF8NEOF
JSR
7,[8]
xFOO-xFFF

JP-5 JP-21 LDOFA,#i DRSZOFA LDA,[X+]

JP-1

JP-17 LDOFE,#i DRSZOFE

JP-O JP-16 LD OFF,#i DRSZOFF
where, i is the immediate data
Md is a directly addressed memory location
• is an unused opcode
The opcode 60 Hex is also the opcode for IFBIT #i,A

JP-1

JMP
JP+32 JP-O
xFOO-xFFF

:I:lP8l8dO:l1:I:l88l8dO:l

1;1

o
~
,....

Ordering and Development Support

o
o

......

o
ex)

,....

ex)

COP8788CF1COP8784CF Ordering Information
Clock
Option

Package

Emulates

COP8788CFV·X
COP8788CFV·R*

Crystal

44 PLCC

COP888CF

. COP8788CFN·X
COP8788CFN·R *

Crystal

40 DIP

COP888CF

COP8784CFN·X
COP8784CFN·R*

Crystal

28 DIP

COP884CF

COP8784CFWM·X*
COP8784CFWM·R*

Crystal

28S0

COP884CF

Device Number

RIC

ex)

D-

RIC
RIC
RIC

'Check with the local sales office about the availability.

PROGRAMMING SUPPORT

Programming of these emulator devices is supported by different sources. The following programmers are certified for program·
ming these One·Time Programmable emulator devices:
EPROM Programmer Information
Manufacturer
and Product

Europe
Phone No.

U.S.
Phone No.

Asia
Phone No.

MetaLinkDebug Module

(602) 926·0797

Germany:
+ 49·8141·1 030

Hong Kong:
852·737·1800

XeltekSuperpro

(408) 745·7974

Germany:
(49·20·41) 684758

Singapore:
(65) 276·6433

BP MicrosystemsTurpro

(800) 225·2102

Germany:
(49·89·85) 76667

Hong Kong:
(852) 388·0629

Data I/O-Unisite
-System 29
-System 39

(800) 322·8246

Europe:
+ 31·20·622866
Germany:
+ 49·89·85·8020

Japan:
+ 33·432·6991

Abcom-COP8
programmer
System GeneralTurpro·1-FX
-APRO

Europe:
+89808707
(408) 263·6667

Switzerland:
+31·921·7844

1·506

Taiwan:
+2·917·3005

~---------------------------------------------------------------------'O

Development System Support

"1J

IN·CIRCUIT EMULATOR

The following tables list the emulator and probe cards ordering information.

Emulator Ordering Information
Part
Number

IM-COP81

MetaLink base unit incircuit emulator for all
COP8 devices, symbolic
debugger software and
RS-232 serial interface
cable, with 220V @
50 Hz Power Supply.

400/2t

DM-COP81
888CF

The iceMASTER's performance analyzer offers a resolution
of better than 6s. The user can easily monitor the time spent
executing specific portions of code and find "hot spots" or
"dead code". Up to 15 independent memory areas based
on code address or label ranges can be defined. Analysis
results can be viewed in bar graph format or as actual frequency count.

o."

"oo

"1J

CD
......
CD

MetaLink base unit incircuit emulator for all
COP8 devices, symbolic
debugger software and
RS-232 serial interface
cable, with 11 OV @
60 Hz Power Supply.

400/1t

Current
Version

Description

......

CD
CD

o
."

Host Software:
Ver. 3.3 Rev. 5,
Model File
Rev 3.050.

MetaLink ice MASTER
Debug Module. This is
the low cost version of
the MetaLink
ice MASTER. Firmware:
Ver.6.07.

tThese parts include National's COPS Assembler/Linker/Librarian Package
(COPS-DEV-IBMA).

Probe Card Ordering Information
Part Number

Emulator memory operations for program memory include
single line assembler, disassembler, view, change and write
to file. Data memory operations include fill, move, compare,
dUmp to filu, cAaliilna and moJiry. TiI~ cOllttlnts or any
memory space can be directly viewed and modified from the
corresponding window.
The iceMASTER comes with an easy to use window interface. Each window can be sized, highlighted, colorcontrolled, added, or removed completely. Commands can
be accessed via pull-down menus and/or redefinable hot
keys. A context sensitive hypertextlhyperlinked on-line help
system explains clearly the options the user has from within
any window.

Package

Voltage
Range

Emulates

MHW-884CF28D5PC

28DIP

4.5V-5.5V COP884CF

MHW-884CF28DWPC

28 DIP

2.5V-6.0V COP884CF

MHW-888CF40D5PC

40DIP

4.5V-5.5V COP888CF

MHW-888CF40DWPC

40DIP

2.5V-6.0V COP888CF

MWH-888CF44D5PC

44 PLCC 4.5V-5.5V COP888CF

MHW-888CF44DWPC 44 PLCC 2.5V-6.0V COP888CF
MACRO CROSS ASSEMBLER

National Semiconductor offers a relocatable COP8 macro
cross assembler. It runs on industry standard compatible
PCs and supports all of the full-symbolic debugging features
of the MetaLink iceMASTER emulators.

The iceMASTER connects easily to a PCRM via the standard COMM port and its 115.2 kBaud serial link keeps typical program download time to under 3 seconds.

Assembler Ordering Information

Part Number

Description

Manual

COP8-DEV-IBMA

COP8AssembierI
Linker/Librarian
for IBM®

424410632-001

PC/XT®,
AT@or
compatible.

1-507

~ r-------------------------------------------------------------------~

o
~

co
r-co

D..

o
......
~
o
co
co
r-co

D..

Development System Support
(Continued)

ORDER PIN: MOLE-DIAL-A-HLP
Information System Package Contents:

D1AL-A-HELPER

Dial-A-Helper Users Manual

Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Bulletin Board Information system.

Public Domain Communications Software

FACTORY APPLICATIONS SUPPORT

INFORMATION SYSTEM

Dial-A~Helper also provides immediate factor applications
support. If a user has questions, he can leave messages on
our electronic bulletin board, which we will respond to.

The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities could be found. The minimum requirement for accessing the Dial-A-Helper is a Hayes compatible
modem.

Voice:

(800) 272-9959

Modem: CANADA/U.S.: (800) NSC-MICRO
(800) 672-6427

If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.

1-508

Baud:

14.4k

Set-Up:

Length:
Parity:
Stop Bit:

Operation:

24 Hours, 7 Days

8-Bit
None
1

(')

t!JNational Semiconductor

PRELIMINARY

COP8788EG/COP8784EG microCMOS
One-Time Programmable (OTP) Microcontrollers
General Description

Features

The COP8788EG/COP8784EG programmable microcontrollers are members of the COPSTM microcontroller family.
Each device is a two chip system in a plastic package. Within the package is the COP888EG and an 8k EPROM with
port recreation logic. The code executes out of the
EPROM. The device is offered in four packages: 44-pin
PLCC, 40-pin DIP, 28-pin DIP and 28-pin SO.

•
•
•
•
•
•
•
•
•
•

The COP8788EG/COP8784EG are fully static, fabricated
using double-metal silicon gate microCMOS technology.
Features include an 8-bit memory mapped architecture,
MICROWIRE/PLUSTM serial 1/0, three 16-bit timer/counters supporting three modes (Processor Independent PWM
generation, External Event counter, and Input Capture
mode capabilities), full duplex UART and two comparators.
Each I/O pin has software selectable configurations. The
devices operates over a voltage range of 4.5V to 5.5V. High
throughput is achieved with an efficient, regular instruction
set operating at a maximum of 1 JLs per instruction rate.
The COP8788EG/COP8784EG devices can be used to provide form fit and function emulation for the COP888EGI
COP884EG, COP888CG/COP884CG and COP888CSI
COP884CS family of mask programmable devices. The user
must pay special attention, since the COP8788EGI
COP8784EG devices contain additional features and are
supersets of COP888CG/COP884CG and COP888CSI
COP884CS. The following table shows the differences between the various devices.

,.,,""
.IV.I.

nAi.i
(Bytes) (Bytes)

Timers

# of
Camparators

COP8788EGI
COP8784EG

256

TO, T1, T2, T3

COP888EGI
COP884EG

256

TO,T1,T2,T3

COP888CGI
COP884CG

192

TO, T1, T2, T3

COP888CSI
COP884CS

192

TO, T1

Low cost 8-bit microcontroller
Fully static CMOS, with low current drain
1 JLs instruction cycle time
8192 bytes on-board EPROM
256 bytes on-board RAM
Single supply operation: 4.5V-5.5V
Full duplex UART
Two analog comparators
MICROWIRE/PLUSTM serial I/O
WATCHDOGTM and Clock monitor logic

"'D

en
en
en
m
C>
.......
.......

(')

"'D

en
.......
en
m
,Jlo.

• Idle Timer
&:I Multi-Input Wake Up (MIWU) with optional interrupts (8)
• Fourteen multi-source vectored interrupts servicing
- External interrupt
- Idle Timer TO
- Two Timers (each with 2 interrupts)
- MICROWIRE/PLUS
- Multi-Input Wake up
- Software Trap
-UART (2)
- Default VIS
a Three 16-bit timers, each with two 16-bit registers
supporting:
- Processor Independent PWM mode
- External Event counter mode
- Input Capture mode
• 8-bit Stack Pointer SP (stack in RAM)
iii Two a-bit Register Indirect Data Memory Pointers
(B and X)
• Versatile instruction set with true bit manipulation
• Memory mapped 1/0
• BCD arithmetic instructions
• Package:
- 44 PLCC with 39 1/0 pins
- 40 DIP with 35 I/O pins
- 28 DIP with 23 1/0 pins
- 28 SO with 23 I/O pins (contact local sales office for
availability)
• Software selectable 1/0 options
- TRI-STATE® Output
- Push-Pull Output
- Weak Pull Up Input
- High Impedance Input
• Schmitt trigger inputs on ports G and L
• Form fit and function emulation device for the
COP888EG/COP884EG, COP888CG/COP884CG and
COP888CS/COP884CS
• Real time emulation and full program debug offered by
MetaLink's Development Systems

1-509

LLI
~

co
co

Connection Diagrams

1'0

D-

Dual-In-Llne Package

Plastic Chip Carrier

o.......
~

co
co
1'0
co
DO

LLI

CKI

vee

RESET
GNO

10
11

07
35

44 pin
PlCC

Cl
CO

CKI

RESET

GNO

Vee
10

40 pin
DIP

05
04
03

18 19 20 21 22 23 24 25 26 27 28

02
01
25

Tl/DD12064-1

Top View
Order Number COP8788EGV-X, COP8788EGFV-R
See NS Package Number V44A

Tl/DD12064-2

Top View
Order Number COP8788EGN-X, COP8788EGN-R
See NS Package Number N40A

Dual-In-Llne Package
G4

REffi
GNO
03
02
01
DO
l7
l6
l5
l4

Tl/DD12064-3

Top View
Order Number COP8784EGN-X, COP8784EGN-R,
COP8784EGWM-X or COP8784EGWM-R
See NS Package Number M28B or N28A
FIGURE 1. COP8788EG/COP8784EG Connection Diagrams

1-510

a"'tJ

Connection Diagrams (Continued)
Pinouts for 28-,40- and 44-Pin Package,s
Port

Type

I/O

lID

L2
L3
L4
L5
L6
L7

I/O
I/O
I/O

GO
Gl
G2
G3
G4
G5
G6
G7

AIt.Fun

I/O

MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU

CKX
TDX
RDX
T2A
T28
T3A
T38

lID

INT

ALE

T18
T1A
SO
SK
SI
HALT Restart

WR
RD

lID
lID

WDOUT

lID
lID
lID
lID
I
I/CKO

DO
01
02
03

0
0
0
0

10
11
12
13

I
I
I
I

14
15
16
17

I
I
I
I

04
05
06
07

0
0
0
0

CO
C1
C2
C3
C4
C5
C6
C7

I/O

ME
ADO
ADl
AD2
AD3

COMP1INCOMPlIN+
COMP10UT

28-Pln
Pkg.

40·Pln
Pkg.

44-Pin
Pkg.

11
12
13
14
15
16
17
18

17
18
19
20
21
22
23
24

17
18
19
20
25
26
27
28

25
26
27
28
1
2
3
4

35
36
37
38
3
4
5
6

39
40
41
42

19
20
21
22

25
26
27
28

29
30
31
32

7
8
9
10

9
10
11
12

10
11
12

13
14
15
16

29
30
31
32

39
40
1
2

43
44
1
2
21
22
23
24

8
33
7
34

8
37
7
38

COMP2INCOMP2IN+
COMP20UT
~-

AD4
AD5
AD6
AD7

lID
lID
lID
lID
lID
lID
lID

Vee
GND
CKI
RESET

Vpp

1-511

6
23
5
24

co
.......
co
co
m
Q

........

a"'tJ
co
co

.......

3
4
5
6

34
35
36

C!J

Absolute Maximum Ratings

D-

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

co
r-co

o
.......
C!J
w
co
co
r-co
D-

(Note)

Voltage at Any Pin

Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.

- 0.3V to Vee + 0.3V

Total Current into Vee Pin (Source)

100 mA

DC Electrical Characteristics

- 65°C to + 140°C

Storage Temperature Range

Supply Voltage (Vee>

110 mA

Total Current out of GND Pin (Sink)

-40°C ~ T A ~ + 85°C unless otherwise specified

Parameter

Conditions

Operating Voltage

Min

Max

Units

5.5

0.1 Vee

Typ

4.5

Power Supply Ripple (Note 1)

Peak-to-Peak

Supply Current (Note 2)
CKI = 10 MHz

Vee

HALT Current (Note 3)

Vee

=
=

5.5V, CKI

IDLE Current
CKI = 10 MHz

Vee

5.5V, tc

1 ,..,s

250

0 MHz

,..,A
15

0.2 Vee

V
V

0.2 Vee

V
V

0.2 Vee

V
V

1,..,s

Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc. Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low

0.8 Vee

0.7 Vee

Hi-Z Input Leakage

Vee

Input Pullup Current

Vee

=
=

5.5V

-2

,..,A

5.5V

250

,..,A

0.35 Vee

G and L Port Input Hysteresis

0.05 Vee

Output Current Levels
o Outputs
Source
Sink
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)

Vee
Vee

=
=

4.5V, VOH
4.5V, VOL

= 3.3V
= 1V

0.4
10

Vee
Vee
Vee

4.5V, VOH
4.5V, VOH
4.5V, VOL

= 2.7V
= 3.3V
= O.4V

10
0.4
1.6

100

,..,A
mA
mA

TR I-STATE Leakage

Vee

=
=
=
=

-2

,..,A

15
3

mA
mA

±100

1000

5.5V

Allowable Sink/Source
Current per Pin
D Outputs (Sink)
All others

Maximum Input Current
without Latchup (Note 4)

RAM Retention Voltage, Vr

500 ns Rise and Fall Time (Min)

25°C

mA
mA

Input Capacitance
Load Capacitance on D2
Note 1: Rate of voltage change must be less then 0.5 Vlms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input. CKO open. inputs at rails and outputs open.

Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to Vee. Land G ports in the
TRI-STATE mode and tied to ground. all outputs low and tied to ground. The clock monitor is disabled.
Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than Vee and the pins will
have sink current to Vee when biased at voltages greater than Vee (the pins do not have source current when biased at a voltage below Vee!. The effective
resistance to Vee is 7500 (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.

1-512

o
AC Electrical Characteristics

- 40°C::;; TA ::;;

Parameter

+ 85°C unless otherwise specified
Typ

Min

Conditions

co
co
co

.......

Max

Units

1
3

DC
DC

p.s
p's

o
'"
o

60
5
5

%
ns
ns

co
co

Instruction Cycle Time (tel
Crystal, Resonator,
RIC Oscillator
CKI Clock Duty Cycle (Note 5)
Rise Time (Note 5)
Fall Time (Note 5)

fr
fr
fr

=
=
=

Max
10 MHz Ext Clock
10 MHz Ext Clock

.......
~

Inputs
ns
ns

200
60

tSETUP
tHOLO
Output Propagation Delay

2.2k, CL

100 pF

tpOl, tpoo
SO,SK
All Others

0.7
1

p's
p's

220

ns
ns
ns

20
56

MICROWIRETM Setup Time (tuws)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tupo)
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timei' Input High Time
Timer Input Low Time

1
1
1
1

tc
tc
tc
tc

Reset Pulse Width

p's

Note 5: Parameter sample (not 100% tested).

Comparators AC and DC Characteristics Vee =
Parameter
Input Offset Voltage

5V, TA
Min

Conditions
O.4V ::;; VIN ::;; Vee - 1.5V

25°C
Typ

Max

Units

±10

±25

Vee - 1.6

o.~

Input Common Mode Voltage Rfln!]A
Low Level Output Current

VOL

O.4V

1.6

High Level Output Current

VOH

4.6V

1.6

DC Supply Current Per Comparator
(When Enabled)
Response Time

250
TBD mV Step, TBD mV
Overdrive, 100 pF Load

--.lLS
~tUPD

FIGURE 2. MICROWIRE/PLUS Timing

1-513

p's

rl=c
tUWH

p.A

TLlDD12064-4

e"
LLI
-.::r
co
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D-

o
.......

e"
LLI
co
co
I"'co
D-

Pin Descriptions
PORT L is an a-bit I/O port. All L-pins have Schmitt triggers
on the inputs.

Vee and GND are the power supply pins.
CKI is the clock input This can come from an R/C generated OSCillator, or a crystal oscillator (in conjunction with
CKO). See Oscillator Descriptionsection.

Port L supports Multi-Input Wake Up (MIWU) on all eight
pins. L 1 is used for the UART external clock. L2 and L3 are
used for the UART transmit and receive. L4 and L5 are used
for the timer input functions T2A and T2B. L6 and L7 are
used for the timer input functions T3A and T3B.

RESET is the master reset. input. See Reset Description
section.
The device contains three bidirectional a-bit I/O ports (C, G
and L), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L and G),
output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated a-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also
reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O
ports.) Figure 3 shows the I/O port configurations. The
DATA and CONFIGURATION registers allow for each port
bit to be individually configured under software control as
shown below:
CONFIGURATION
Register

DATA
Register

Hi-Z Input
(TRI-STATE Output)

Input with Weak Pull-Up

Push-Pull Zero Output

Push-Pull One Output

Port L has the following alternate features:
LO

MIWU

MIWU or CKX

MIWU orTDX
MIWU or RDX

L3
L4

MIWU or T2A

MIWU or T2B

MIWU orT3A

MIWU orT3B
L7
Port G is an a-bit port with 5 I/O pins (GO, G2-G5), an input
pin (G6), 'and two dedicated output pins (G1 and G7). Pins
GO and G2-G6 all have Schmitt Triggers on their inputs. Pin
G1 serves as the dedicated WDOUT WATCHDOG output,
while pin G7 is either input or output depending on the oscillator mask option selected. With the crystal oscillator option
selected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin but is
also used to bring the device out of HALT mode with a low
to high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (GO, G2-G5) can be individually configured under software control.

Por~Set-Up

PORT L, C, AND G

TLlDD12064-5

FIGURE 3. I/O Port Configurations

1-514

Pin Descriptions (Continued)

Functional Description

Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose
input (RIC clock option), the associated bits in the data and
configuration registers for G6 and G7 are used for special
purpose functions as outlined below. Reading the G6 and
G7 data bits will return zeros.
Note that the chip will be placed in the HALT mode by writing a "1" to bit 7 of the Port G Data Register. Similarly the
chip will be placed in the IDLE mode by writing a "1" to bit 6
of the Port G Data Register.

The CPU can do an 8-bit addition, subtraction, logical or
shift operation in one instruction (te> cycle time.

I
I

Data Reg.

8 is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.

Alternate SK

IDLE

X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.

Port G has the following alternate features:
G2 T18 (Timer T1 Capture Input)
G3 T1A (Timer T1 1/0)
G5 SK (MICROWIRE Serial Clock)
Port G has the following dedicated functions:

PROGRAM MEMORY
The program memory consists of 8092 bytes of ROM.
These bytes may hold program instructions or constant data
(data tables for the LAID instruction, jump vectors for the
JID instruction, and interrupt vectors for the VIS instruction).
The program memory is addressed by the 15-bit program
counter (PC). All interrupts in the devices vector to program
memory location OFF Hex.

G1 WDOUT WATCHDOG and lor Clock Monitor dedicated output
G7 CKO Oscillator dedicated output or general purpose
. input
Port C is an 8-bit 110 port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
lIul itmninaled. A read operation for these unterminated
pins will return unpredictable values.

DATA MEMORY

The data memory address space includes the on-chip RAM
and data registers, the 1/0 registers (Configuration, Data
and Pin), the control registers, the MICROWIRE/PLUS SIO
shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer).
Data memory is addressed directly by the instruction or indirectly by the 8, X, SP pointers and Sregister.
The data memory consists of 256 bytes of RAM. Sixteen
bytes of RAM are mapped as "registers" at addresses OFO
to OFF Hex. These registers can be loaded immediately,
and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction. The memory
pointer registers X, SP, 8 and S are memory mapped into
this space at address locations OFC to OFF Hex respectively, with the other registers being available for general usage.

Port 11-13 are used for Comparator 1. Port 14-16 are used
for Comparator 2.
The Port I has the following alternate features.
11
COMP1 -IN (Comparator 1 Negative Input)

+ IN (Comparator 1 Positive Input)

COMP2 -IN (Comparator 2 Negative Input)

All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).

G6 SI (MICROWIRE Serial Data Input)

COMP2 + IN (Comparator 2 Positive Input)
COMP20UT (Comparator 2 Output)

ClO

S is the 8-bit Data Segment Address Register used to extend the lower half of the address range (00 to 7F) into 256
data segments of 128 bytes each.

G4 SO (MICROWIRE Serial Data Output)

15
16

ClO
....,

SP is the 8-bit stack pointer, which points to the subroutinel
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.

GO INTR (External Interrupt Input)

COMP10UT (Comparator 1 Output)

o
'"
o

PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)

HALT

PC is the 15-bit Program Counter Register

Conflg Reg.

ClO
ClO

There are six CPU registers:

CLKDLY

COMP1

....,

ClO

A is the 8-bit Accumulator Register

o
o

The instruction set permits any bit in memory to be set,
reset or tested. All 110 and registers (except A and PC) are
memory mapped; therefore, 1/0 bits and register bits can be
directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.

Port 0 is a recreated 8-bit output port that is preset high
when RESET goes low. 0 port recreation is one clock cycle
behind normal port timing. The user can tie two or more 0
port outputs (except 02) together in order to get a higher
drive.
1-515

oo::J'

Data Memory Segment RAM Extension

l"-

Data memory address OFF is used as a memory mapped
location for the Data Segment Address Register (S).

CC)

o(.)

w
CC)
CC)

l"-

CC)

o(.)

XXFF

RAM REGISTERS
(16 BYTES)
INCLUDES B, X, SP, S

XXFO
XXEF

TIMERS, I/O, MW,
CNTRL, PSW, A/D,
ICNTRL, WD, MIWU,
COMPARATOR
AND UART
REGISTERS

XXBO
XXAF
UNUSED
(READS UNDEFINED
DATA)

T
S
E
G
M
E
N

XX80
007F
0070
006 F

ON CHIP RAM
(112 BYTES)

T
S
E
G
M

017F
ON CHIP RAM
(128 BYTES)

a13F

-.L

UNUSED'

1
000 a

01001.0..------'

TL/DD12064-6

'Reads as all ones.

FIGURE 4. RAM Organization

Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports l, G and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WATCHDOG and/or Clock Monitor error
output pin. Port D is set high. The PC, PSW, ICNTRl,
CNTRl, T2CNTRl and T3CNTRl control registers are
cleared. The UART registers PSR, ENU (except that TBMT
bit is set), ENUR and ENUI are cleared. The Comparator
Select Register is cleared. The S register is initialized to
zero. The Multi-Input Wake Up registers WKEN, WKEDG
and WKPND are cleared. The stack pointer, SP, is initialized
to 6F Hex.

Figure 4 illustrates how the S register data memory extension is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a 'total addressing range of 32 kbytes from XXOO
to XX7F. This organization allows a total of 256 data segments of 128 bytes each with an additional upper base segment of 128 bytes. Furthermore, all addressing modes are
available for all data segments. The S register must be
changed under program control to move from one data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory registers, I/O registers,
control registers, etc.) is always available regardless of the
contents of the S register, since the upper base segment
(address range 0080 to OOFF) is independent of data segment extension.

The instructions that utilize the stack pointer (SP) always
reference the stack as part of the base segment (Segment
0), regardless of the contents of the S register. The S register is not changed by these instructions. Consequently, the
stack (used with subroutine linkage and interrupts) is always
located in the base segment. The stack pointer will be intitialized to point at data memory location 006F as a result of
reset.
The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
116 bytes of RAM are resident from address 0000 to 006F
in the lower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at addresses OOFO to OOFF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.

The external RC network shown in Figure 5 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.

Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XXOO to XX7F) of
the lower base segment. The additional 128 bytes of RAM
are memory mapped at address locations 0100 to 017F
hex.

Note: Continual state of reset will cause the device to draw excessive cur·
rent.

1-516

Table" shows the variation in the oscillator frequencies as
functions of the component (R and C) values.

Reset (Continued)
p
0

vee

E
R
S
U
P

:= R

]~D

TABLE II. RIC Oscillator Configuration, T A = 25°C
COP800

RESET

GND

RC > 5 x Power Supply Rise Time

Conditions

.......

3.3
5.6
6.8

82
100
100

2.2-2.7
1.1-1.3
0.9-1.1

3.7-4.6
7.4-9.0
8.8-10.8

Vee = 5V
Vee = 5V
Vee = 5V

"en......en

R
~

200k
~

200 pF

1. Oscillator operation mode-11
2. Internal switching current-12
3. Internal leakage current-13
4. Output source current-14
5. DC current caused by external input not at Vee or GND15

Figure 6 shows the Crystal and RIC diagrams.

I I

CKO

Instr. Cycle
(p,s)

The total current drain of the chip depends on:

CKI

CKI Freq
(MHz)

Current Drain

Oscillator Circuits

en
m

C
(pF)

50 pF

FIGURE 5. Recommended Reset Circuit

"......enen

R
(k!l)

Note: 3k

TLIDD/12064-7

CKI

CKO

6. Clock Monitor current when enabled-16
7. Clock Monitor current when enabled-17
Thus the total current drain, It, is given as
It = 11

+ 12 + 13 + 14 + 15 + 16 +

-"'C

TLlDD12064-B

FIGURE 6. Crystal and RIC Oscillator Diagrams

12 = C x V x f

CRYSTAL OSCilLATOR

where C = equivalent capacitance of the chip

CKI and CKO can be connected to make a closed loop
cr,!ste.f (or re~cr.:!tcr) c:ntrc!!~d c:;c!:~utvi.

f = CKI frequency

Table I shows the component values required for various
standard crystal values.

Control Registers

TABLE I. Crystal Oscillator Configuration, T A = 25°C

CNTRl Register (Address X'OOEE)

R1
(k!l)

R2
(M!l)

C1
(pF)

C2
(pF)

CKI Freq
(MHz)

Conditions

The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:

30-36

Vee = 5V

SL 1 & SLO Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)

30-36

Vee = 5V

IEDG

200

100-150

0.455

Vee = 5V

External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)

MSEL

Selects G5 and G4 as MICROWIRE/PLUS
signals
SK and SO respectively

T1CO

Timer T1 Start/Stop control in timer
modes 1 and 2

RIC OSCillATOR
By selecting CKI as a single pin oscil/ator input, a single pin
R/C oscillator circuit can be connected to it. CKO is available as a general purpose input, and/or HALT restart pin.

Timer T1 Underflow Interrupt Pending Flag in
timer mode 3
T1 C1

Timer T1 mode control bit

T1 C3

Timer T1 mode control bit

Bit7

1-517

Timer T1 mode control bit

T1 C2

BitO

"cow
~

roco
a..

Control Registers (Continued)
PSW Register (Address X'OOEF)

T2C1

The PSW register contains the following select bits:

T2C2

Timer T2 mode control bit

T2C3

Timer T2 mode control bit

o
......
w
co

GIE

Global interrupt enable (enables interrupts)

EXEN

Enable external interrupt

BUSY

MICROWIRE/PLUS busy shifting flag

roco
a..

EXPND

External interrupt pending

T1 ENA

Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge

"co
o
o

Sit 7

Carry Flag

Half Carry Flag

I II
HC

The T3CNTRL register contains the following bits:

T3ENB

I I
GIE

Bit7
BitO
The Half-Carry bit is also affected by all the instructions that
affect the Carry flag. The SC· (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and RC instructions, ADC,
SUBC, RRC and RLC instructions affect the carry and Half
Carry flags.

WEN

Enable MICROWIRE/PLUS interrupt

WPND

MICROWI~E/PLUS

Timer T3 mode control bit
Timer T3 mode control bit

T3C3

Timer T3 mode control bit

Sit7

The device contains a very versatile set of timers (TO, T1,
T2, T3). All timers and associated autoreload/capture registers power up containing random data.

TOEN

Timer TO Interrupt Enable (Bit 12 toggle)
Timer TO Interrupt pending

LPEN

L Port Interrupt Enable (Multi-Input Wake Up/
Interrupt)

TIMER TO (IDLE TIMER)
The devices support applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer TO, which is a
16-bit timer. The Timer TO runs continuously at the fixed
rate of the instruction cycle clock, te. The user cannot read
or write to the IDLE Timer TO, which is a count down timer.
The Timer TO. supports the following functions:

Bit 7 could be used as a flag

Sit7

SitO

Timers

interrupt pending

TOPND

SitO

T2CNTRl Register (Address X'OOC6)

Exit out of the Idle Mode (See Idle Mode description)
WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode.
The IDLE Timer TO can generate an interrupt when the thirteenth bit toggles. This toggle is latched into the TOPND
pending flag, and will occur every 4 ms at the maximum
clock frequency (te = 1 ,..,s). A control flag TOEN allows the
interrupt from the thirteenth bit of Timer TO to be enabled or
disabled. Setting TOEN will enable the interrupt, while resettirJg it will disable the interrupt.

The T2CNTRL register contains the following bits:
Timer T2 Interrupt Enable for T2B Input capture
edge

T2PNDB Timer T2 Interrupt Pending Flag for T2B capture edge
Timer T2 Interrupt Enable for Timer Underflow
or ~2A Input capture edge

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA
in mode 1, T2 Underflow in mode 2, T2A capture edge in mode 3)
T2CO

T3C1
T3C2

Timer T1 Interrupt Enable for T1 B Input capture
edge

T1 PNDB Timer T1 Interrupt Pending Flag for T1 B capture edge

T2ENA

Timer T3 Start/Stop control in timer modes 1
and 2
Timer T3 Underflow Interrupt Pending Flag in
timer mode 3

ICNTRl Register (Address X'OOE8)

T2ENB

Timer T3 Interrupt Enable for Timer .Underflow
or T3A pin

T3PNDA Timer T3 Interrupt Pending Flag (Autoload RA
in mode 1, T3 Underflow in mode 2, T3a capture edge in mode 3)
T3CO

The ICNTRL register contains the following bits:
T1 ENB

Timer T3 Interrupt Enable for T3B

T3PNDB Timer T3 Interrupt Pending Flag for T3B pin
(T3B capture edge)
T3ENA

C T1 PNDA T1 ENA EXPND BUSY EXEN

SitO

T3CNTRl Register (Address X'0086)

T1 PNDA Timer T1 Interrupt Pending Flag (Auto reload RA
in mode 1, T1 Underflow in Mode 2, T1 A capture edge in mode 3)
C

Timer T2 mode control bit

Timer T2 Start/Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3

1-518

Timers

(Continued)
TIMER 11, TIMER T2 AND TIMER T3

co
-.....
co
co
m

The devices have a set of three powerful timer/counter
blocks, T1, T2 and T3. The associated features and functioning of a timer block are described by referring to the
timer block Tx. Since the three timer blocks, T1, T2 and T3
are identical, all comments are equally applicable to any of
the three timer blocks.

TIMER
UNDERFLOW
INTERRUPT

o""-

+-----,

o"0
co
-.....
co
~
m

TxA

I C - - - - -......

TL/DD12064-9

FIGURE 7. Timer In PWM Mode
Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that
the timer, Tx, is clocked by the input signal from the TxA pin.
The Tx timer control bits, TxC3, TxC2 and TxC1 allow the
timer to be clocked either on a positive or negative edge
from the TxA pin. Underflows from the timer are latched into
the TxPNDA pending flag. Setting the TxENA control flag
will cause an interrupt when the timer underflows.
In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on tho
TxB input pin is latched into the TxPNDB flag.

Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention. The
user only has to define the parameters of the PWM signal
(ON time and OFF time). Once begun, the timer block will
continuously generate the PWM signal completely independent of the microcontroller. The user software services the
timer block only when the PWM parameters require updating.
In this mode the timer Tx counts down at a fixed rate of tc.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.
The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.

Figure 8 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock.

TLlDD12064-10

FIGURE 8. Timer In External Event Counter Mode
Mode 3.lnput Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode.
In this mode, the timer Tx is constantly running at the fixed
tc rate. The two registers, RxA and RxB, act as capture
registers. Each register acts in conjunction with a pin. The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin.

1-519

~ r---------------------------------------------------------------~

UJ
"1:1"

co
I"co
D-

o........
~

co
co
I"co

D-

Timers

(Continued)

The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.

T x B1Xlf---+I

TLlDD12064-11

Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer TxCO
pending flag (the TxCO control bit serves as the timer underflow interrupt pending flag in the Input Capture mode). Consequently, the TxCO centrol bit should be reset when entering the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxCO pending flags .in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.

FIGURE 9. Timer In Input Capture Mode
TIMER CONTROL FLAGS
The timers T1, T2 and T3 have indentical control structures.
The control bits and their functions are summarized below.
TxCO

Timer Start/Stop control in Modes 1 and 2
(Processor Independent PWM and External
Event Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)

TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag

Figure 9 shows a block diagram of the timer in Input Capture
mode.

1-520

TxENA
TxENB

Timer Interrupt Enable Flag
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
o = Timer Interrupt Disabled

TxC3
TxC2
TxC1

Timer mode control
Timer mode control
Timer mode control

(')

Timers

a"tJ

(Continued)

The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
TxC3

TxC2

TxC1

Timer Mode

Interrupt A
Source

Interrupt B
Source

Timer
Counts On

""enenm

.......

(')

MODE 2 (External
Event Counter)

Timer
Underflow

Pos.TxB
Edge

TxA
Pos.Edge

a"tJ

MODE 2 (External
Event Counter)

Timer
Underflow

Pos. TxB
Edge

TxA
Neg. Edge

MODE 1 (PWM)
TxA Toggle

Autoreload
RA

Autoreload
RB

MODE 1 (PWM)
No TxA Toggle

Autoreload
RA

Autoreload
RB

MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Pos. Edge

Pos. TxA
Edge or
Timer
Underflow

Pos.TxB
Edge

MODE 3 (Capture)
Captures:
TxA Pos. Edge
TxB Neg. Edge

Pos. TxA
Edge or
Timer
Underflow

Neg. TxB
Edge

MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Pos. Edge

Neg. TxB
Edge or
Timer
Underflow

Pos. TxB
Edge

MODE 3 (Capture)
Captures:
TxA Neg. Edge
TxB Neg. Edge

Neg. TxA
Edge or
Timer
Underflow

Neg. TxB
Edge

Power Save Modes
so may be used with an RC clock configuration. The thir~
111~lIluu ui tlxiling ine HALT mode is by pulling the RESET
pin low.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wake Up signal is not allowed to start the ch~p
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wake Up signal, only the oscillator
circuitry is enabled. The IDLE timer is loaded with a value of
256' and is clocked with the te instruction cycle clock. The te
clock is derived by dividing the oscillator clock down by a
factor of 10. The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE timer is clocked only
when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger specifications. This Schmitt trigger
is not part of the oscillator closed loop. The startup timeout
from the IDLE timer enables the clock signals to be routed
to the rest of the chip.

HALT MODE
The devices can be placed in the HALT mode by writing a
"1" to the HALT flag (G7 data bit). All microcontroller activities, including the clock and timers, are stopped. The
WATCHDOG logic on the device is disabled during the
HALT mode. However, the clock monitor circuitry if enabled
remains active and will cause the WATCHDOG output pin
(WDOUT) to go low. If the HALT mode is used and the user
does not want to activate the WDOUT pin, the Clock Monitor should be disabled after the device comes out of reset
(resetting the Clock Monitor control bit with the first write to
the WDSVR register). In the HALT mode, the power requirements of the device are minimal and the applied voltage
(Vee) may be decreased to Vr (Vr = 2.0V) without altering
the state of the machine.

The devices support three different ways of exiting the
HALT mode. The first method of exiting the HALT mode is
with the Multi-Input Wake Up feature on the L port. The
second method is with a low to high transition on the CKO
(G7) pin. This method precludes the use of the crystal clock
configuration (since CKO becomes a dedicated output), and
1-521

""
oI:ao

The devices offer the user two power save modes of operation: HALT and IDU::. In th~ H:\LT rr:;::~;::, c::.!l rr:;Ci0C0I,tiU::",i
activities are stopped. In the IDLE mode, the on-board oscillator circuitry the WATCHDOG logic, the Clock Monitor and
timer TO are active but all other microcontroller activities are
stopped. In either mode, all on-board RAM, registers, I/O
states, and timers (with the exception of TO) are unaltered.

en
en

C!J
LLJ
~

Power Save Modes (Continued)

a..
oo
.......

IDLE MODE

co
.....
co

C!J
co
co
.....
co

LLJ

a..

The device is placed in the IDLE mode by writing a "1" to
the IDLE flag (G6 data bit). In this mode, all activities, except
the associated on-board oscillator circuitry,
the
WATCHDOG logic, the clock monitor and the IDLE Timer
TO, are stopped. The power supply requirements of the micro-controller in this mode of operation are typically around
30% of normal power requirement of the microcontroller.

Due to the on-board 8k EPROM with port recreation logic,
the HALT/IDLE current is much higher compared to the
equivalent masked port.

Multi-Input Wake Up
The Multi-Input Wake Up feature is ued to return (Wake Up)
the device from either the HALT or IDLE modes. Alternately
Multi-Input Wake Up/Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts.

Figure 10 shows the Multi-Input Wake Up logic. The MultiInput Wake Up feature utilizes the L Port. The user selects
which particular L port bit (or combination of L Port bits) will
cause the device to exit the HALT or IDLE modes. The selection is done through the Reg: WKEN. The Reg: WKEN

•

•
•
•
•
•
L7

WKEDG

WKPND
CHIP CLOCK

TL/DD12064-12

FIGURE 10. Multi-Input Wake Up Logic

1-522

Multi-Input Wake Up

a""tJ

(Continued)

WKEN, WKPND and WKEDG are all read/write registers,
and are cleared at reset.

is an a-bit read/write register, which contains a control bit
for every L port bit. Setting a particular WKEN bit enables a
Wake Up from the associated L port pin.

PORT L INTERRUPTS

The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an
a-bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wake Up condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.

Port L provides the user. with an additional eight fully selectable, edge sensitive interrupts which are all vectored into
the same service subroutine.
The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to
be individually enabled or disabled. The register WKEDG
specifies the trigger condition to be either a positive or a
negative edge. Finally, the register WKPND latches in the
pending trigger conditions.

5,
5,
5,
5,

......

a""tJ
Q)

-....
Q)
0l:Io

RMRBIT
RMSBIT
RMRBIT
RMSBIT

-....
Q)

WKEN
WKEDG
WKPND
WKEN

If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wake Upllnterrupt, a
safety procedure should also be followed to avoid inherited
pseudo wakeup conditions. After the selected L port bits
have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired
edge selects, followed by the associated WKPND bits being
cleared.

The Wake Up signal will not start the chip running immediately since crystal oscillators or ceramic resonators have a
finite start up time. The IDLE Timer (TO) generates a fixed
delay to ensure that the oscillator has indeed stabilized before allowing the device to execute instructions. In this case,
upon detecting a valid Wake Up signal, only the oscillator
circuitry and the IDLE Timer TO are enabled. The IDLE Timer is loaded with a value of 256 and is clocked from the te
instruction cycle clock. The te clock is derived by dividinq
down the oscil/ator clock by a factor of 10. A Schmitt trigger
fol/owing the CKI on-chip inverter ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large
amplitude to meet the Schmitt trigger specifications. This
Schmitt trigger is not part of the oscillator closed loop. The
startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip.

This same procedure should be used following reset, since
the L port inputs are left floating as a result of reset.
The occurrence of the selected trigger condition for Multi-Input Wake Up is latched into a pending register called
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since WKPND is a pending
register for the occurrence of selected Wake Up conditions,
the device will not enter the HALT mode if any Wake Up bit
is both enabled and pending. Consequently, the user has
the responsibility of clearing the pending flags before attempting to enter the HALT mode.

If the RC clock option is used, the fixed delay is under software control. A control flag, CLKDL Y, in the G7 configuration bit allows the clock start up delay to be optionally inserted. Setting CLKDL Y flag high will cause clock start up delay
to be inserted and resetting it will exclude the clock start up
delay. The CLKDLY flag is cleared during reset, so the clock
start up delay is not present following reset with the RC
clock options.

1-523

oo::t'

UART

The device contains a full-duplex software programmable
UART. The UART (Figure 11) consists of a transmit shift
register, a receiver shift register and seven addressable registers, as follows: a transmit buffer register (TBUF), a receiver buffer register (RBUF), a UART control and status register (ENU), a UART receive control and status register
(ENUR), a UART interrupt and clock source register (ENUI),
a prescaler select register (PSR) and baud (BAUD) register.
The ENU register contains flags for transmit and receive
functions; this register also determines the length of the
data frame (7, 8 or 9 bits), the value of the ninth bit in transmission, and parity selection bits. The ENUR register flags
framing, data overrun and parity errors while the UART is
receiving.

co
......

Il.

w
co
co
......
co

Il.

WAKE-UP LOGIC
RDX

[IJ
DOE
FE

INTERRUPT
R
N
A
L

INTERRUPT

lOX
D
A
T
A

ENU

XMIT RECV
CLOCK CLOCK

CKX

CKI
TLlDD12064-13

FIGURE 11. UART Block Diagram

1-524

(")

UART (Continued)

""C

UART CONTROL AND STATUS REGISTERS

PSEL1 = 1, PSELO = 0
PSEL1 = 1, PSEL1 = 1

The operation of the UART is programmed through three
registers: ENU, ENUR and ENUI. The function of the individual bits in these registers is as follows:

PEN: This bit enables/disables Parity (7- and a-bit modes
only).
PEN = 0 Parity disabled.
PEN = 1 Parity enabled.

ENU-UART Control and Status Register (Address at OBA)
PSEL1 XBIT91 CHL1
PSELO
ORW ORW ORW ORW
PEN

CHLO

ERR

ORW

RBFL TBMT
OR

Bit?

ENUR-UART RECEIVE CONTROL AND
STATUS REGISTER

RCVG: This bit is set high whenever a framing error occurs
and goes low when RDX goes high.

BitO

Bit is read-only; it cannot be written by software.

PE: Flags a Parity Error.
PE = 0 Indicates no Parity Error has been detected since
the last time the ENUR register was read.
PE = 1 Indicates the occurrence of a Parity Error.

BitO

FE: Flags a Framing Error.
FE = 0 Indicates no Framing Error has been detected
since the last time the ENUR register was read.
FE = 1 Indicates the occurrence of a Framing Error.

RW Bit is read/write.
D

""C

co
......
co

SPARE: Reserved for future use.

Bit is cleared on reset.
Bit is set to one on reset.

RBIT9: Contains the ninth data bit received when the UART
is operating with nine data bits per frame.

'Bit is not used.
1

(")

AnN: ATIENTION Mode is enabled while this bit is set.
This bit is cleared automatically on receiving a character
with data bit nine set.

ENUI-UART Interrupt and Clock Source Register
(Address at OBC)

Bit?

.......

XMTG: This bit is set to indicate that the UART is transmitting. It gets reset at the end of the last frame (end of last
Stop bit).

ENUR-UART Receive Control and Status Register
(Address at OBB)

Bit?

Mark(1) (if Parity enabled)
Space(O) (if Parity enabled)

co
......
co
co

DOE: Flags a Data Overrun Error.
DOE = 0 Indicates no Data Overrun Error has been detected since the last time the ENUR register
was read.
DOE = 1 Indicates the occurrence of a Data Overrun Error.

Bit is cleared on read; when read by software as a one, it is cleared
automatically. Writing to the bit does not affect its state.

DESCRIPTION OF UART REGISTER BITS
ENU-UART CONTROL AND STATUS REGISTER
TBMT: This bit is set when the UART transfers a byte of
data from the TBUF register into the TSFT register for transmission. It iR flutomRticeJly reset '.'!hen scfr:::::.rc '::r:t:;~ i:lto
the TBUF register.

ENUI-UART INTERRUPT AND
CLCCi~ SOURC~

Ri:GiSTcn

ETI: This bit enables/disables interrupt from the transmitter
section.
ETI = 0 Interrupt from the transmitter is disabled.
ETI = 1 Interrupt from the transmitter is enabled.

RBFL: This bit is set when the UART has received a complete character and has copied it into the RBUF register. It
is automatically reset when software reads the character
from RBUF.

ERI: This bit enables/disables interrupt from the receiver
section.
ERI = 0 Interrupt from the receiver is disabled.
ERI = 1 Interrupt from the receiver is enabled.

XTCLK: This bit selects the clock source for the transmitter
section.
XTCLK = 0 The clock source is selected through the
PSR and BAUD registers.
XTCLK = 1 Signal on CKX (L 1) pin is used as the clock.
XRCLK: This bit selects the clock source for the receiver
section.
XRCLK = 0 The clock source is selected through the
PSR and BAUD registers.
XRCLK = 1 Signal on CKX (L 1) pin is used as the clock.

SSEL: UART mode select.
SSEL = 0 Asynchronous Mode.
SSEL = 1 Synchronous Mode.

PSEL 1, PSELO: Parity select bits.
PSEL 1 = 0, PSELO = 0 Odd Parity (if Parity enabled)
PSEL 1 = 0, PSELO = 1 Odd Parity (if Parity enabled)

1-525

CJ
W

"'1::1'

eo
I"eo

D-

CJ
W

eo
eo
I"eo

D-

when a framing error occurs and goes low once ROX goes
high. TBMT, XMTG, RBFL and RCVG are read only bits.

UART (Continued)
ETDX: TDX (UART Transmit Pin) is the alternate function
aSSigned to Port L pin L2; it is selected by setting ETDX bit.
To simulate line break generation, software should reset
ETDX bit and output logic zero to TDX pin through Port L
data and configuration registers.
STP78: This bit is set to program the last Stop bit to be
7/8th of a bit in length.

SYNCHRONOUS MODE

STP2: This bit programs the number of Stop bits to be transmitted.
STP2 = 0 One Stop bit transmitted.
STP2 = 1 Two Stop bits transmitted.

When an external clock input is selected at the CKX pin,
data transmit and receive are performed synchronously with
this clock through TDX/RDX pins.
If data transmit and receive are selected with the CKX· pin
as clock output, the device generates the synchronous
clock output at the CKX pin. The internal baud rate generator is used to produce the synchronous clock. Data transmit
and receive are performed synchronously with this clock.

Associated 1/0 Pins
Data is transmitted on the TOX pin and received on the RDX
pin. TOX is the alternate function aSSigned to Port L pin L2;
it is selected by setting ETDX (in the ENUI register) to one.
RDX is an inherent function of Port L pin L3, requiring no
setup.

FRAMING FORMATS
The UART supports several serial framing formats (Figure
12). The format is selected using control bits in the ENU,
ENUR and ENUI registers.

The baud rate clock for the UART can be generated onchip, or can be taken from an external source. Port L pin L1
(CKX) is the external clock I/O pin. The CKX pin can be
either an input or an output, as determined by Port L Configuration and Data registers (Bit 1). As an input, it accepts a
clock Signal which may be selected to drive the transmitter
and/or receiver. As an output, it presents the internal Baud
Rate Generator output.

The first format (1, 1a, 1b, 1c) for data transmission (CHLO
= 1, CHL 1 = 0) consists of Start bit, seven Data bits (excluding parity) and 7/8, one or two Stop bits. In applications
using parity, the parity bit is generated and verified by hardware.
The second format (CHLO = 0, CHL1 = 0) consists of one
Start bit, eight Data bits (excluding parity) and 7/8, one or
two Stop bits. Parity bit is generated and verified by hardware.

UART Operation
The UART has two modes of operation: asynchronous
mode and synchronous mode.

The third format for transmission (CHLO = 0, CHL1 = 1)
consists of one Start bit, nine Data bits and 7/8, one or two
Stop bits. This format also supports the UART "ATTENTION" feature. When operating in this format, all eight bits
of TBUF and RBUF are used for data. The ninth data bit is
transmitted and received using two bits in the ENU and
ENUR registers, called XBIT9 and RBIT9. RBIT9 is a read
only bit. Parity is not generated or verified in this mode.

ASYNCHRONOUS MODE

This mode is selected by resetting the SSEL (in the ENUI
register) bit to zero. The input frequency to the UART is 16
times the baud rate.
The TSFT and TBUF registers double-buffer data for transmission. While TSFT is shifting out the current character on
the TDX pin, the TBUF register may be loaded by software
with the next byte to be transmitted. When TSFT finishes
transmitting the current character the contents of TBUF are
transferred to the TSFT register and the Transmit Buffer
Empty Flag (TBMT in the ENU register) is set. The TBMT
flag is automatically reset by the UART when software loads
a new character into the TBUF register. There is also the
XMTG bit which is set to indicate that the UART is transmitting. This bit gets reset at the end of the last frame (end of
last Stop bit). TBUF is a read/write register.

For any of the above framing formats, the last Stop bit can
be programmed to be 7/8th of a bit in length. If two Stop
bits are selected and the 7/8th bit is set (selected), the
second Stop bit will be 7/8th of a bit in length.
The parity is enabled/disabled by PEN bit located in the
ENU register. Parity is selected for 7- and 8-bit modes only.
If parity is enabled (PEN = 1), the parity selection is then
performed by PSELO and PSEL1 bits located in the ENU
register.

1-526

(')

UART Operation
"

(Continued)

START
BIT

""C

-...
CO

CO
CO

7 BIT DATA

"(')
0

L
L

l a , START
BIT

7 BIT DATA

l b , START
BIT

7 BIT DATA

lC,

START
BIT

7 BIT DATA

START
BIT

B BIT DATA

2a,

START
BIT

B BIT DATA

2b,

START
BIT

B BIT DATA

2C,

START
BIT

B BIT DATA

START
BIT

9 BIT DATA

3a,

START
BIT

9 BIT DATA

CO
-...
CO
~

""C

L
2S

L
L
2S

L
2S

TLlDD12064-14

FIGURE 12. Framing Formats
UART INTERRUPTS

source selected in the PSR and BAUD registers. Internally,

The UART is capable of apnlO'ratina intern.!pts. lnt-::rn:;:t: :.r;:;
generated on Receive Buffer Full and Transmit Buffer Empty. Both interrupts have individual interrupt vectors. Two
bytes of program memory space are reserved for each interrupt vector. The two vectors are located at addresses OxEC
to OxEF Hex in the program memory space. The interrupts
can be individually enabled or disabled using Enable Transmit Interrupt (ETI) and Enable Receive Interrupt (ERI) bits in
the ENUI register.

the ba~!c b2.ud c!~c!":.:: crc~tcd frcm tr,e o5cU:ator rf..;;qlJt:"cy
through a two-stage divider chain consisting of a 1-16 (increments of 0.5) prescaler and an 11-bit binary counter.
(Figure 13) The divide factors are specified through two
read/write registers shown in Figure 14. Note that the 11-bit
Baud Rate Divisor spills over into the Prescaler Select Register (PSR). PSR is cleared upon reset.
As shown in Table III, a Prescaler Factor of 0 corresponds
to NO CLOCK. NO CLOCK condition is the UART power
down mode where the UART clock is turned off for power
saving purpose. The user must also turn the UART clock off
when a different baud rate is chosen.

The interrupt from the transmitter is set pending, and remains pending, as long as both the TBMT and ETI bits are
set. To remove this interrupt, software must either clear the
ETI bit or write to the TBUF register (thus clearing the TBMT
bit).

The correspondences between the 5-bit Prescaler Select
and Prescaler factors are shown in Table III. There are
many ways to calculate the two divisor factors, but one particularly effective method would be to achieve a 1.8432 MHz
frequency coming out of the first stage. The 1.8432 MHz
prescaler output is then used to drive the software programmable baud rate counter to create a x16 clock for the following baud rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400,
3600,4800, 7200, 9600, 19200 and 38400 (Table IV). Other
baud rates may be created by using appropriate divisors.
The x16 clock is then divided by 16 to provide the rate for
the serial shift registers of the transmitter and receiver.

1-527

C!J

LLI
~

co
co
D-

Baud Clock Generation

(Continued)

I"'-

o
......

UART TRANSMIT
CLOCK

C!J

co
co
I"'co
D-

PRESCALER
5 BITS
+ 1 TO + 16

BAUD RATE SELECT
11 BITS

MUX

LLI

+16

CRYSTAL

UART RECEIVE
CLOCK
TL/DD12064-15

FIGURE 13. UART BAUD Clock Generation

;...I-I----

I-PRESCALER SELECT REGISTER (PSR)}-...

I, 1,1,1, 1 1,,1
0

~PRESCALER

SELECT

BAUD REGISTER

1,1,1,1,1, 1,1,1, 1 1
0

.1.

BAUD RATE DIVISOR

TLlDD12064-16

FIGURE 14. UART BAUD Clock Divisor Registers
TABLE IV. Baud Rate Divisors
(1.8432 MHz Prescaler Output)

TABLE III. Prescaler Factors
Prescaler
Select

Prescaler
Factor

Prescaler
Select

Prescaler
Factor

00000

NO CLOCK

10000

8.5

00001

10001

00010

1.5

10010

9.5

00011

10011

00100

2.5

10100

10.5

00101

10101

00110

3.5

10110

11.5

00111

10111

01000

4.5

11000

12.5

01001

11001

01010

5.5

11010

13.5

01011

11011

01100

6.5

11100

14.5

01101

11101

01110

7.5

11110

15.5

01111

11111

Baud
Rate

Baud Rate
Divisor - 1 (N-1)

110 (110.03)
134.5 (134.58)
150
300
600
1200
1800
2400
3600
4800
7200
9600
19200
38400

1046
855
767
383
191
95
63
47
31
23
15
11
5
2

Note: The entries in Table IV assume a prescaler
output of 1.8432 MHz. In the asynchronous mode
the baud rate could be as high as 625k.

As an example, considering the Asynchronous Mode and a
CKI clock of 4.608 MHz, the prescaler factor selected is:
4.608/1.8432 = 2.5
The 2.5 entry is available in Table III. The 1.8432 MHz prescaler output is then used with proper Baud Rate Divisor
(Table II) to obtain different baud rates. For a baud rate of
19200 e.g., the entry in Table IV is V.
N - 1 = 5 (N - 1 is the value from Table IV)
N = 6 (N is the Baud Rate Divisor)
Baud Rate = 1.8432 MHz/(16 X 6) = 19200
The divide by 16 is performed because in the asynchronous
mode, the input frequency to the UART is 16 times the baud
rate. The equation to calculate baud rates is given below.
The actual Baud Rate may be found from:
BR = Fc/(16

1-528

x N x P)

Baud Clock Generation

Note that the framing format for this mode is the nine bit
format; one Start bit, nine data bits, and 7/8, one or two
Stop bits. Parity is not generated or verified in this mode.

(Continued)

Where:
BR is the Baud Rate
Fc is the CKI frequency

Attention Mode

N is the Baud Rate Divisor (Table IV).

P is the Prescaler Divide Factor selected by the value in the
Prescaler Select Register (Table III)
Note: In the Synchronous Mode, the divisor 16 is replaced by two.

Example:

Asynchronous Mode:
Crystal Frequency

= 5 MHz

Desired baud rate

= 9600

Using the above equation N x P can be calculated first.
N x P = (5 x 106)/(16 x 9600) = 32.552
Now 32.552 is divided by each Prescaler Factor (Table III)
to obtain a value closest to an integer. This factor happens
to be 6.5 (P = 6.5).
N

32.552/6.5

5.008 (N

o
o

-a
co
.......
co
co
m

.......

-a
co
.......
co
0l:Io

The programmed value (from Table IV) should be 4 (N - 1).
Using the above values calculated for Nand P:
BR = (5 x 106)/(16 x 5 x 6.5) = 9615.384
% error = (9615.385 - 9600)/9600 = 0.16

Effect of HALT/IDLE
The UART logic is reinitialized when either the HALT or
IDLE modes are entered. This reinitialization sets the TBMT
flag and resets all read only bits in the UART control and
status registers. Read/Write bits remain unchanged. The
Transmit Buffer (TBUF) is not affected, but the Transmit
Shift register (TSFT) bits are set to one. The receiver registers RBUF and RSFT are not affected.

Operation of the UART Transmitter is not affected by selection of this Mode. The value of the ninth bit to be transmitted
is programmed by setting XBIT9 appropriately. The value of
the ninth bit received is obtained by reading RBIT9. Since
this bit is located in ENUR register where the error flags
reside, a bit operation on it will reset the error flags.

The device will exit from the HALT/IDLE modes when the
Start bit of a character is detected at the RDX (L3) pin. This
feature is obtained by using the Multi-Input Wake Up
sc::hflmA rrovid,=d en the de\!:c~.

Comparators
The devices contain two differential comparators, each with
a pair of inputs (positive and negative) and an output. Ports
11-13 and 14-16 are used for the comparators. The following
is the Port I assignment:

Before entering the HALT or IDLE modes the user program
must select the Wake Up source to be on the RDX pin. This
selection is done by setting bit 3 of WKEN (Wake Up Enable) register. The Wake Up trigger condition is then selected to be high to low transition. This is done via the WKEDG
register (Bit 3 is zero.)

11
12
13
14
15
16

If the device is halted and crystal oscillator is used, the
Wake Up signal will not start the chip running immediately
because of the finite start up time requirement of the crystal
oscillator. The idle timer (TO) generates a fixed delay to ensure that the oscillator has indeed stabilized before allowing
the device to execute code. The user has to consider this
delay when data transfer is expected immediately after exiting the HALT mode.

Comparator1
Comparator1
Comparator1
Comparator2
Comparator2
Comparator2

negative input
positive input
output
negative input
positive input
output

1-529

u.I

-.:r
co
r-co

Comparators (Continued)

Interrupts

CMPSL REGISTER (ADDRESS X'OOB7)

The CMPSL register contains the following bits:

The devices support a vectored interrupt scheme. It supports a total of fourteen interrupt sources. The following table lists all the possible device interrupt sources, their arbitration ranking and the memory locations reserved for the
interrupt vector for each source.

......

CMP1 EN Enable comparator l'

u.I

CMP1 RD Comparator 1 result (this is a read only bit,
which will read as 0 if the comparator is not
enabled)

co
co
r-co

CMP10E

o
o

Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software
interrupt are maskable. Each of the maskable interrupts
have an Enable bit and a Pending bit. A maskable interrupt
is active if its associated enable and pending bits are set. If
GIE = 1 and an interrupt is active, then the processor will
be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described
in the Software Trap sub-section.

Selects pin 13 as comparator 1 output provided
that CMPIEN is set to enable the comparator

CMP2EN

Enable comparator 2

CMP2RD

Comparator 2 result (this is a read only bit,
which will read as 0 if the comparator is not
enabled)

CMP20E

Selects pin 16 as comparator 2 output provided
that CMP2EN is set to enable the comparator

Note that the two unused bits of CMPSL may be used as
software flags.
'

1. The GIE (Global Interrupt Enable) bit is reset.
2. The address of the instruction about to be executed is
pus~ed into the stack.

Comparator outputs have the same spec as Ports Land G
except that the rise and fall times are symmetrical.

Arbitration
Ranking

3. The PC (Program Counter) branches to address OOFF.
This procedure takes 7 tc cycles to execute.

Description

Source

(1) Highest

Vector
Address
Hi·Low Byte

Software

INTR Instruction

OyFE-OyFF

Reserved

for Future Use

OyFC-OyFD

(2)

External

Pin GO Edge

OyFA-OyFB

(3)

Timer TO

Underflow

OyFB-OyF9

(4)

TimerT1

T1 AlUnderflow

OyF6~OyF7

(5)

TimerT1

T1B

OyF4-0yF5

(6)

MICROWIRE/PLUS

BUSY Goes Low

OyF2-0yF3

Reserved

for Future Use

OyFO-OyF1

(7)

UART

Receive

OyEE-OyEF

(B)

UART

Transmit

OyEC-OyED

(9)

TimerT2

T2A1Underflow

OyEA-OyEB

(10)

TimerT2

T2B

OyEB-OyE9

(11 )

TimerT3

T3A1Underflow

OyE6-0yE7

(12)

TimerT3

T3B

OyE4-0yE5

(13)

Port LlWake Up

Port LEdge

OyE2-0yE3

(14) Lowest

Default

VIS Instr. Execution
without Any Interrupts

OyEO-OyE1

Y is VIS page, y 0'= O.

1-530

C')

Interrupts (Continued)

-a
():)

The addresses of the different interrupt service routines,
called vectors, are chosen by the user and stored in ROM in
a table starting at 01 EO (assuming that VIS is located between OOFF and 01 DF). The vectors are 15-bit wide and
therefore occupy 2 ROM locations.
VIS and the vector table must be located in the same
256-byte block (OyOO to OyFF) except if VIS is located at the
last address of a block. In this case, the table must be in the
next block. The vector table cannot be inserted in the first
256-byte block (y =1= 0).

......
C')
o
-a
():)

.......
():)
~

The Software Trap has the highest rank and its vector is
located at OyFE and OyFF.
If, by accident, a VIS gets executed and no interrupt is active, then the PC (Program Counter) will branch to a vector
located at OyEO-OyE1. This vector can point to the Software Trap (ST) interrupt service routine, or to another special service routine as desired.

Figure 15 shows the Interrupt block diagram.
SOFTWARE TRAP

The Software Trap (ST) is a special kind of non-maskable
interrupt which occurs when the INTR instruction (used to
acknowledge interrupts) is fetched from ROM and placed
inside the instruction register. This may happen when the
PC is pointing beyond the available ROM address space or
when the stack is over-popped.

The VIS instruction looks at all the active interrupts at the
time it is executed and performs an indirect jump to the
beginning of the service routine of the one with the highest
rank.

SOFTWARE

.......

():)
():)

---------------------------------------------~
~
I

TIMER TI, T2. AND T3

EXTERNAL

MULTI-INPUT WAKE UP
INTERRUPT
}.IWIRE/PLUS

FUTURE PERIPHERAL

UART

IDLE TIMER

TLlDD12064-17

FIGURE 15. Interrupt Block Diagram

1-531

is greater or equal to 10kHz. This equates to a
clock input rate on CKI of greater or equal to 100 kHz.

The ST has the highest rank among all interrupts.
Nothing (except another ST) can interrupt an ST being
serviced.

WATCHDOG

WATCHDOG Operation

The devices contain a WATCHDOG and clock monitor. The
WATCHDOG is designed to detect the user program getting
stuck in infinite loops resulting in loss of program control or
"runaway" programs. The Clock Monitor is used to detect
the absence of a clock or a very slow clock below a specified rate on the CKI pin.

The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.

The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the WATCHDOG service window and match the
WATCHDOG key data. Subsequent writes to the WDSVR
register will compare the value being written by the user to
the WATCHDOG service window value and the key data
(bits 7 through 1) in the WDSVR Register. Table VII shows
the sequence of events that can occur.

Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table V shows the WDSVR register.
The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 and 6 of the WDSVR register allow
the user to pick an upper limit of the service window.
Table VI shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flexibility in choosing the WATCHDOG service window prevents
any undue burden on the user software.

. The user must service 'the WATCHDOG at least once before the upper limit of the service window expires. The
WATCHDOG may not be serviced more than once in every
lower limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period
between the lower and upper limits of the service window.
The first write to the WDSVR Register is also counted as a
WATCHDOG service.

Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5bit Key Data field. The key data is fixed at 01100. Bit 0 of the
WDSVR Register is the Clock Monitor Select bit.
TABLE V. WATCHDOG Service Register (WDSVR)
Window
Select

X
7

Clock
Monitor

Key Data

I1 I1 I0 I0
4

TABLE VII. WATCHDOG Service Actions
Key Data

Window Data

Clock Monitor

Action

Match

Valid Service: Restart Service Window

Don't Care

Mismatch

Don't Care

Error: Generate WATCHDOG Output

Mismatch

Don't Care

Error: Generate WATCHDOG Output

Don't Care

Mismatch

Error: Generate WATCHDOG Output

1-532

WATCHDOG Operation

o
o

(Continued)

The WATCHDOG service window will restart when the
WDOUT pin goes high. It is recommended that the user tie
the WDOUT pin back to Vee through a resistor in order to
pull WDOUT high.

• The WATCHDOG detector circuit is inhibited during both
the HALT and IDLE modes.
• The CLOCK MONITOR detector circuit is active during
both the HALT and IDLE modes. Consequently, the
COP888 inadvertently entering the HALT mode will be
detected as a CLOCK MONITOR error (provided that the
CLOCK MONITOR enable option has been selected by
the program).

• With the single-pin RIC oscillator mask option selected
and the CLKDLY bit reset, the WATCHDOG service window will resume following HALT mode from where it left
off before entering the HALT mode.

The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum specified value, after which the G1 output will enter the high impedance TRI-STATE mode following 16 tc-32 tc clock cycles. The Clock Monitor generates a continual Clock Monitor error if the oscillator fails to start, or fails to reach the
minimum specified frequency. The specification for the
Clock Monitor is as follows:
1/tc
1/tc

>
<

co
.....
co

........

o
o

co
.....
co
0l:Io

• With the crystal oscillator mask option selected, or with
the single-pin RIC oscillator mask option selected and
the CLKDL Y bit set, the WATCHDOG service window will
be set to its selected value from WDSVR following HALT.
Consequently, the WATCHDOG should not be serviced
for at least 2048 instruction cycles following HALT, but
must be serviced within the selected window to avoid a
WATCHDOG error.

10kHz-No clock rejection.
10Hz-Guaranteed clock rejection.

WATCHDOG AND CLOCK MONITOR SUMMARY

• The IDLE timer TO is not initialized with RESET.

The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted:

• Both the WATCHDOG and CLOCK MONITOR detector
circuits are inhibited during RESET.
• Following RESET, the WATCHDOG and CLOCK MONITOR are both enabled, with the WATCHDOG having the
maximum service window selected.

• A hardware WATCHDOG service occurs just as the device exits the IDLE mode. Consequently, the
WATCHDOG should not be serviced for at least 2048
instruction cycles following IDLE, but must be serviced
within the selected window to avoid a WATCHDOG error.

• The WATCHDOG service window and CLOCK MONITOR enableldisable option can only be changed once,
during the initial WATCHDOG service following RESET.

• Following RESET, the initial WATCHDOG service (where
the service window and the CLOCK MONITOR enablel
disable must be selected) may be programmed anywhere within the maximum service window (65,536 instruction cycles) initialized by RESET. Note thAt thiR initial WATCHDOG service may be programmed within the
initial 2048 instruction cycles without causing a
WATCHDOG error.

• The initial WATCHDOG service must match the key data
value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error.
• Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG errors.
• The correct key data value cannot be read from the
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all O's.

1-533

"I:t'

Detection of Illegal Conditions

MICROWIRE/PLUS

D-

The device can detect various illegal conditions resulting
from coding errors, transient nOise, power supply voltage
drops, runaway programs, etc.

MICROWIRE/PLUS is a serial synchronous communications interface. The MICROWIRE/PLUS capability enables
the device to interface with any of National Semiconductor's
MICROWIRE peripherals (Le. AID converters, display drivers, E2PROMs etc.) and with other microcontrollers which
support the MICROWIRE interface. It consists of. an a-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK). Figure 16
shows a block diagram of the MICROWIRE/PLUS logic.

co
.....
co

......
e"
w

co
co
.....
co
DO

1 - - - - - - + INTERRUPT
~~--~~------.SO

~-'l..~~~......- - - - S I

Thus, the chip can detect the following illegal conditions:
1. Executing from undefined ROM

2. Over "POP"ing the stack by having more returns than
calls.
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that
following reset, but might not contain the same program
initialization procedures). The recovery program should reset the software interrupt pending bit using the RPND instruction.

TLlDD12064-18

FIGURE 16. MICROWIRE/PLUS Block Diagram
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIREI
PLUS arrangement with the internal clock source is called
the Master mode of operation. Similarly, operating the
MICROWIRE/PLUS arrangement with an external shift
clock is called the Slave mode of operation.
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. In· the
master mode, the SK clock rate is selected by the two bits,
SLO and SL1, in the CNTRLregister. Table VIII details the
different clock rates that may be selected.
TABLE VIII. MICROWIRE/PLUS
Master Mode Clock Select
SL1

SLO

x tc

4 X tc

x tc

Where tc is the instruction cycle clock

1-534

MICROWIRE/PLUS (Continued)
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated.

MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 17 shows
how two devices, microcontrollers and several peripherals
may be interconnected using the MICROWIRE/PLUS arrangements.

Alternate SK Phase Operation

The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register.
In both the modes the SK is normally low. In the normal
mode data is shifted in on the rising edge of the SK clock
and the data is shifted out on the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK clock. In the alternate SK phase operation, data is shifted in on the falling edge of the SK clock and shifted out on
the rising edge of the SK clock.

Warning

TABLE IX. MICROWIRE/PLUS Mode Selection

In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally by the device. The
MICROWIRE Master always initiates all data exchanges.
The MSEL bit in the CNTRL register must be set to
enable the SO and SK functions onto the G Port. The SO
and SK pins must also be selected as outputs by setting
appropriate bits in the Port G configuration register. Table IX
summarizes the bit settings required for Master mode of
operation.

G4(SO)
G5(SK)
Conf/g. Bit Con fig. Bit

MICROWIRE/PLUS Slave Mode Operation

,/5

I/o
A
~

--..

...".

•

8 - BIT

1 KBYTE
EEPROM
COP495

LCD
DISPLAY
DRIVER
COP472

VF
DISPLAY
DRIVER

Int. MICROWIRE/PLUS
SK Master

TRIInt. MICROWIRE/PLUS
STATE SK Master
SO

Ext. MICROWIRE/PLUS
SK Slave

TRI- Ext. MICROWIRE/PLUS
SIAl J:::: t;K t;lave

DO SK DI

SK DI

! i

I/o
LINES
COPS I.....
(SLAVE) I....

DO SK DI

Operation

COPS
(MASTER)

COP43X

AID

LINES

G5
Fun.

Note: This table assumes that the control flag MSEL is set.

CHIP SELECT LINES

.i.

G4
Fun.

.....
-,..

so
51
5K
TLlDD12064-19

FIGURE 17. MICROWIRE/PLUS Application

1-535

*
Cl
~

D..

Memory Map
All RAM, ports and registers (except A and PC) are mapped into data memory address space.

o
........

Address
S/ADDREG

0000 to 006F

On-Chip RAM bytes (112 bytes)

co
co
r-co

0070 to 007F

xx80 toxxAF

Unused RAM Address Space (Reads
As All Ones)
Unused RAM Address Space (Reads
Undefined Data)

D..

xxBO
xxB1
xxB2
xxB3
xxB4
xxB5
xxB6
xxB7
xxB8
xxB9
xxBA
xxBB
xxBC
xxBD
xxBE
xxBF
xxCO
xxC1
xxC2
xxC3
xxC4
xxC5
xxC6
xxC7
xxC8
xxC9
xxCA
xxCB
xxCC
xxCDto xxCF

Address
S/ADD REG

Contents

xxDO
xxD1
xxD2
xxD3
xxD4
xxD5
xxD6
xxD7
xxD8
xxD9
xxDA
xxDB
xxDC
xxDDto DF

Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port D
Reserved for Port D

xxEO to xxE5
xxE6

xxEE
xxEF

Reserved for EE Control Registers
Timer T1 Autoload Register T1 RB
Lower Byte
Timer T1 Autoload Register T1 RB
Upper Byte
ICNTRL Register
MICROWIRE/PLUS Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1 RA
Lower Byte
Timer T1 Autoload Register T1 RA
Upper Byte
CNTRL Control Register
PSW Register

xxFO to FB
xxFC
xxFD
xxFE
xxFF

On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
S Register

0100-017F

On-Chip 128 RAM Bytes

xxE7
xxE8
xxE9
xxEA
xxEB
xxEC
xxED

Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA
Lower Byte
Timer T2 Autoload Register T2RA
Upper Byte
Timer T2 Autoload Register T2RB
Lower Byte
Timer T2 Autoload Register T2RB
Upper Byte
Timer T2 Control Register
WATCHDOG Service Register
(Reg:WDSVR)
MIWU Edge Select Register
(Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register
(Reg:WKPND) .
Reserved
Reserved
Reserved

Contents

Note: Reading memory locations 0070H-007FH (Segment 0) will return all
ones. Reading unused memory locations OOBOH-OOAFH (Segment 0) will
return undefined data. Reading memory locations from other Segments (i.e.,
Segment 2, Segment 3, ... etc.) will return all ones.

1-536

a"'C

Addressing Modes
Indirect

There are ten addressing modes, six for operand addressing and four for transfer of control.

This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits
of PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruction.

co
co
co

"'m"

.......

o
a"'C
co
co

"'m"
0l:Io

Instruction Set
Register and Symbol Definition

Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.

Registers
A
B
X
SP
PC
PU
PL
C
HC
GIE

VU
VL

TRANSFER OF CONTROL ADDRESSING MODES
Relative
Symbols

This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
program location. JP has a range from -31 to +32 to allow
d 1-iJylt:1 1t:11C1.livl:l jump (JP i- 1 is implemented by a NOP
instruction). There are no "pages" when using JP, since all
15 bits of PC are used.

[B]
[X]
MD
Mem
Meml

Imm
Reg

Absolute Long

Bit

fE
I

1-537

Instruction Set (Continued)

tc;

INSTRUCTION SET

.......
CJ
w
co
co
......
co
Q.

o
o

A~A

ADD
ADC

A,Meml
A,Meml

ADD
ADD with Carry

SUBC

A,Meml

Subtract )Nith Carry

AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND

A,Meml
A,lmm
A,Meml
A,Meml
MD,Imm
A,Meml
A,Meml
A,Meml
#
Reg
#,Mem
#,Mem
#,Mem

Logical AND
Logical AND Immed., Skip if Zero
Logical OR
Logical EXclusive OR
IF EQual
IF EQual
IF Not Equal
IF Greater Than
If BNot Equal
Decrement Reg., Skip if Zero
Set BIT
Reset BIT
IFBIT
Reset PeNDing Flag

X
X
LD
LD
LD
LD
LD

A,Mem
A,[X]
A,Meml
A,[X]
B,lmm
Mem,lmm
Reg,lmm

EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD B with Immed.
LoaD Memory Immed.
LoaD Register Memory Immed.

A~Mem

X
X
LD
LD
LD

A, [B ±]
A,[X ±]
A, [B±]
A, [X±]
[B±],lmm

EXchange A with Memory [B]
EXchange A with Memory [X]
LoaD A with Memory [B]
LoaD A with Memory [X]
LoaD Memory [B] Immed.

A~ [B],(B~B

CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH

A
A
A

CLeaR A
INCrementA
DECrementA
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
SetC
ResetC
IFC
IFNotC
POP the stack into A
PUSH A onto the stack

VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP

A
A
A
A

A
A
Addr.
Addr.
Disp.
Addr.
Add.

+ Meml
A ~ A + Meml + C, C ~ Carry,
HC ~ Half Carry
A~A - Meml + C,C~Carry,
HC ~ Half Carry
A~AandMeml

Skip next if (A and Imm) = 0
A~AorMeml

A .~ A xor Meml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A =1= Meml
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B =1= Imm
Reg ~ Reg - 1, Skip if Reg = 0
1 to bit, Mem (bit = 0 to 7 immediate)
o to bit, Mem
If bit in A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
A~[X]
A~Meml

A~[X]
B~lmm

Mem~lmm
Reg~lmm

±1)
±1)
A~ [B], (B~B ±1)
A ~ [X], (X ~ X±1)
[B] ~ Imm, (B ~ B±1)

A~ [X],(X~

A~O
A~A+

A~A-1

A
A

ROM (PU,A)
BCD correction of A (follows ADC, SUBC)
C~A7~ ... ~AO~C
C~A7~ ... ~AO~C
A7 ... A4~A3 ... AO
~

C~1,HC~1
C~O,HC~O

IF C is true, do next instruction
If C is not true, do next instruction
SP~SP + 1,A~ [SP]
[SP] ~ A, SP ~ SP - 1

1·538

PU ~ [VU], PL ~ [VL]
PC ~ ii (ii = 15 bits, Ok to 32k)
PCg ... O~i(i = 12 bits)
PC ~ PC + r (r is -31 to + 32, except 1)
[SP] ~ PL, [SP-1] ~ PU,SP-2, PC ~ ii
[SP] ~ PL, [SP-1] ~ PU,SP-2, PCg ... 0 ~ i
PL ~ ROM (PU,A)
SP + 2, PL ~ [SP], PU ~ [SP-1]
SP + 2, PL ~ [SP],PU ~ [SP-1]
SP + 2, PL ~ [SP],PU ~ [SP-1],GIE ~ 1
[SP] ~ PL, [SP-1] ~ PU, SP-2, PC ~ OFF
PC~ PC + 1

o
o

Instruction Execution Time

."
CO
~

Most instructions are single byte (with immediate addressing mode instructions taking two bytes).

CO
CO

Most single byte instructions take one cycle time to execute.
See the BYTES and CYCLES per INSTRUCTION table for details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle.

........

o
o

."
CO

Logic and Arithmetic Instructions

Instructions Using A and C

[BJ

Direct

Immed.

ADD
ADC
SUBC
AND
OR
XOR
IFEO
IFGT
IFBNE
DRSZ

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4

2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2

SBIT
RBIT
IFBIT

1/1
1/1
1/1

3/4
3/4
3/4

RPND

1/1

CLRA
INCA
DECA
LAID
DCORA
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ

1/3

1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2

Transfer of Control
Instructions
JMPL
JMP
JP
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP

3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
117
1/1

CO
~

Memory Transfer Instructions
Register
Indirect

XA,·
LDA,·
LDD,:iiiiil
LDB,lmm
LDMem,lmm
LDReg,lmm
IFEOMD,lmm
• =

[BJ

[XJ

1/1
1/1

1/3
1/3

Direct Immed.

2/3
2/3

2/2

[X+,X-J

1/2
1/2

1/3
1/3
(IF B < 16)
(IFB> 15)

1/1

2/3
2/2

2/2

3/3
2/3
3/3

Memory location addressed by B or X or directly.

1·539

COP8788EG/COP8784EG

COP8788EG/COP8784EG Opcode Table
UPPER NIBBLE
I

JSR
xOOO-xOFF

JMP
xOOO-xOFF

JP + 17 JP - 15 0

0
I

JP -15 JP -31

u,
.j:>.

LD OFO, #i

DRSZOFO RRCA

ADCA,
#i

ADCA,[B]

SUBCA,
#i

SUB A,[B]

IFBIT ANDSZ
O,[B] A, #i

LD B,#OF IFBNEO

IFBIT *
1,[B]

LD B,#OE IFBNE1

JSR
x100-x1FF

JMP
x100-x1FF

JP + 18 JP - 14 1

JP -14 JP -30 LDOF1, #i

DRSZOF1

JP -13 JP -29 LD OF2, #i

DRSZOF2 XA,
[X+]

XA,
[B+]

IFEOA,
#i

IFEOA,[B] IFBIT *
2,[B]

LD B,#OD IFBNE2

JSR
x200-x2FF

JMP
x200-x2FF

JP + 19 JP - 13 2

JP -12 JP -28 LD OF3, #i

DRSZOF3 XA,
[X-]

XA,
[B-]

IFGTA,
#i

IFGT A,[B] IFBIT *
3,[B]

LD B,#OC IFBNE 3

JSR
x300-x3FF

JMP
x300-x3FF

JP + 20 JP - 12 3

JP -11 JP -27 LDOF4, #i

DRSZOF4 VIS

LAID

ADD A,
#i

ADDA,[B]

IFBIT CLRA
4,[B]

LD B,#OB IFBNE4

JSR
x400-x4FF

JMP
x400-x4FF

JP + 21 JP - 11

JP -10 JP -26 LD OF5, #i

DRSZOF5 RPND

JID

ANDA,
#i

ANDA,[B]

IFBIT SWAPA LD B,#OA IFBNE 5
5,[B]

JSR
x500-x5FF

JMP
x500-x5FF

JP + 22 JP - 10 5

JP -9

JP -25 LD OF6, #i

DRSZOF6 X A, [X]

XA,[B]

XORA,
#i

XORA,[B]

IFBIT DCORA LD B,#09
6,[B]

IFBNE 6

JSR
x600-x6FF

JMP
x600-x6FF

JP + 23 JP - 9

JP -8

JP -24 LD OF7, #i

DRSZOF7

ORA,#i

ORA;[B]

IFBIT PUSHA
7,[B]

LD B,#08

IFBNE 7

JSR
x700-x7FF

JMP
x700-x7FF

JP + 24 JP - 8

I"'"

JP -7

JP -23 LD OF8, #i

DRSZOF8

NOP

RLCA

LDA,#i

IFC

SBIT
O,[B]

RBIT
O,[B]

LD B,#07

IFBNE8

JSR
x800-x8FF

JMP
x800-x8FF

JP + 25 JP - 7

::E
m
::D
8 z
iii

JP -6

JP -22 LDOF9, #i

DRSZOF9

IFNE
A,[B]

IFEO,
Md,#i

IFNE
A,#i

IFNC

SBIT
1,[B]

RBIT
1,[B]

LD B,#06 IFBNE9

JSR
x900-x9FF

JMP
x900-x9FF

JP + 26 JP - 6

JP -5

JP -21

LDOFA, #i

DRSZOFA LDA,
[X+]

LDA,
[B+]

LD [B+], INCA
#i

SBIT
2,[B]

RBIT
2,[B]

LD B,#05

IFBNEOA JSR
JMP
JP + 27 JP - 5
xAOO-xAFF xAOO-xAFF

JP -4

JP -20 LDOFB, #i

DRSZOFB LDA,
[X-]

LDA,
[B-]

LD [B-]' DECA
#i

- SBIT
3,[B]

RBIT
3,[B]

LD B,#04

IFBNEOB JSR
JMP
JP + 28 JP - 4
xBOO-xBFF xBOO-xBFF

JP -3

JP -19 LDOFC, #i

DRSZOFC LD Md,#i JMPL

XA,Md

POPA

SBIT
4,[B]

RBIT
4,[B]

LD B,#03

IFBNEOC JSR
JMP
JP + 29 JP - 3
xCOO-xCFF xCOO-xCFF

JP -2

JP -18 LDOFD, #i

DRSZOFD DIR

JSRL

LDA,Md

RETSK

SBIT
5,[B]

RBIT
5,[B]

LD B,#02 IFBNEOD JSR
JMP
JP + 30 JP --:- 2
xDOO-xDFF xDOO-xDFF

JP -1

JP -17 LDOFE, #i

DRSZOFE LDA,[X]

LD A,[B] LD [B],#i RET

SBIT
6,[B]

RBIT
6,[B]

LD B,#01

IFBNEOE JSR
JMP
JP + 31 JP - 1
xEOO-xEFF xEOO-xEFF

JP -0

JP -16 LD OFF, #i

DRSZ OFF

SBIT
7,[B]

RBIT
7,[B]

LD B,#OO

IFBNEOF JSR
JMP
JP + 32 JP - 0
xFOO-xFFF xFOO-xFFF

where,
i is the immediate data
Md is a directly addressed memory location
* is an unused opcode
Note: The opcode 60 Hex is also the opcode for IFBIT #i,A
-

LDB,#i

RETI

I"'"

Ordering Information and Development Support
COP8788EG/COP8784EG Ordering Informat/on
Clock
Opt/on

Package

COP8788EGV-X
COP8788EGV-W

Crystal

44 PLCC

COP8788EGN·X
COP8788EGN·W

Crystal

Device Number

"'C
0)

PROGRAMMING SUPPORT

Programming of these emulator devices is supported by different sources. The following programmers are certified for
programming these One·Time Programmable emulator devices:

Emulates

COP888EG

COP8784EGWM·X·
COP8784EGWM·W

Crystal

.......

o
o

40DIP

"'"

COP888EG

0I:loo

RIC
Crystal

0)
0)

"'C

RIC

COP8784EGN-X
COP8784EGN·R •

"'"

28 DIP

COP884EG

28S0

COP884EG

RIC
RIC

'Check with the local sales office about the availability.

EPROM Programmer Informat/on
Manufacturer and Product

U.S. Phone Number

Europe Phone Number

Asia Phone Number

MetaLink·Debug Module

(602) 926-0797

Germany:
+49-8141-1030

Hong Kong:
852-737-1800

Xeltek-Superpro

(408) 745-7974

Germany:
+ 49·20·41·684758

Singapore:
65-276·6433

BP Microsystems·Turpro

(800) 225-2102

Germany:
+ 49-89-85-76667

Hong Kong:
852-388-0629

Data 1I0·Unisite
-System 29
-System 39

(800) 322-8246

Europe:
+ 31-20·622866
Germany:
+ 49-89-85-8020

Japan:
+ 33-432·6991

Abcom-COP8
Programmer
System G eneral-Turpro-1·FX
-APRO

Europe:
+ 49·89-808707
(408) 263·6667

Switzerland:
+ 41-31-921·781\1\

Taiwan:
+2·917·3CC5

1-541

w
~

co
co

I"-

D-

o.......
e"

w
co

co
co
DO
I"-

Development Support
The iceMASTER's performance analyzer offers a resolution
of better than 6 I-'-s. The user can easily monitor the time
spent executing specific portions of code and find "hot
spots" or "dead code". Up to 15 independent memory areas b'ased on code address or label ranges can be defined.
Analysis results can be viewed in bar graph format or as
actual frequency count.

IN·CIRCUIT EMULATOR

The MetaUnk iceMASTERTM-COP8 Model 400 In-Circuit
Emulator for the COP8 family of microcontrollersfeatures
high-performance operation, ease of use, and an extremely
flexible user-interface or maximum productivity. Interchangeable probe cards, which connect to the standard
common base, support the various configurations and packages of the COP8 family.

Emulator memory operations for program memory include
single line assembler, disassembler, view, change and write
.to file. Data memory operations include fill, move, compare,
dump to file, examine and modify. The contents of any
memory space can be directly viewed and modified from the
corresponding window.

The ice MASTER comes with an easy to use window interface. Each window can be sized, highlighted, color-controlled, added, or removed completely. Commands can be
accessed via pull-down-menus and/or redefinable hot keys.
A context sensitive hypertextlhyperlinked on-line help system .explains clearly the options the user has from within
any window.
The ice MASTER connects easily to a PC® via the standard
COMM port and its 115.2 kBaud serial link keeps typical
program download time to under 3 seconds.

During single-step operation the dynamically annotated
code feature displays the contents of all accessed (read
and write) memory locations and registers, as well as. flowof-control direction change markers next to each instruction
executed.

The following tables list the emulator and probe cards ordering information.

Emulator Ordering Information
Part Number

Description

IM-COP8/400/1:j:

MetaUnk base unit in-circuit emulator for all COP8
devices, symbolic debugger software and RS 232
serial interface cable, with 11 OV @ 60 Hz Power
Supply.

IM-COP8/400/2:j:

MetaUnk base unit in-circuit emulator for all COP8
devices, symbolic debugger software and RS 232
serial interface cable, with 220V @ 50 Hz Power
Supply.

DM-COP8/888EG:j:

MetaUnk Ice Master Debug Modul. This is the low cost
version of the MetaUnk IceMaster. Firmware: Ver. 6.07

+These parts include National's COPS Assembler/Linker/Librarian Package (COPS-DEV-IBMA).

1-542

Current Version

Host Software:
Ver. 3.3 Rev. 5,
Model File Rev 3.050.

C')

Development Support (Continued)

"tJ

Probe Card Ordering Information
Package

Part Number

Voltage
Range

4.5V-5.5V COP884EG

MHW-884EG28DWPC 28 DIP

2.5V-6.0V COP884EG

MHW-888EG40D5PC

40 DIP

4.5V-5.5V COP888EG

MHW-888EG40DWPC 40 DIP

2.5V-6.0V COP888EG

MWH-888EG44D5PC

The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be accessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Microcontroller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities could be found. The minimum requirement for accessing the Dial-A-Helper is a Hayes compatible
modem.
If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.

Emulates

28 DIP

MHW-884EG28D5PC

44 PLCC 4.5V-5.5V COP888EG

MHW-888EG44DWPC 44 PLCC 2.5V-6.0V COP888EG
MACRO CROSS ASSEMBLER
National Semiconductor offers a relocatable COP8 macro
cross assembler. It runs on industry standard compatible
PCs and supports all of the full-symbolic debugging features
of the MetaLink iceMASTER emulators.

COP8-DEV-IBMA

Description
COP8
Assembler/
Linker/ Librarian
forlBM®
PC/XT®, AT® or
compatible.

m
C')
......
C')

"tJ

Ol
.....
Ol
~

C')

ORDER PIN: MOLE-DIAL-A-HLP
Information System Package contains:
Dial-A-Helper Users Manual
Public Domain Communications Software

Assembler Ordering Information
Part Number

Ol
.....
Ol

INFORMATION SYSTEM

FACTORY APPLICATIONS SUPPORT

Manual

Dial-A-Helper also provides immediate factor applications
support. If a user has questions, he can leave messages on
our electronic bulletin board, which we will respond to.

424410632-001

Voice:

(800) 272-9959

Modem: CANADA/U.S.: (800) NSC-MICRO
(800) 672-6427

DlAL-A-HELPER

Baud:

14.4k

Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Bulletin Board Information system.

Set-Up:

Length: 8-Bit
Parity: None
Stop Bit: 1

Operation:

24 Hrs., 7 Days

1-543

Section 2
COPS Applications

Section 2 Contents
AN-521 Dual Tone Multiple Frequency (DTMF) .........................................
AN-579 MICROWIRE/PLUS Serial Interface for COP800 Family..........................
AN-596 COP800 MathPak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-607 Pulse Width Modulation A/D Conversion Techniques with COP800 Family
Microcontrollers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-662 COP800 Based Automated Security/Monitoring System.............. ............
AN-663 Sound Effects for the COP800 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-666 DTMF Generation with a 3.58 MHz Crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-673 2-Way Multiplexed LCD Drive and Low Cost A/D Converter Using V /F Techniques
with COP8 Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-681 PC MOUSE Implementation Using COP800.....................................
AN-714 Using COP800 Devices to Control DC Stepper Motors...................... .....
AN-734 MF2 Compatible Keyboard with COP8 Microcontrollers ..........................
AN-739 RS-232C Interface with COP800 ..............................................
AN-952 Low Cost A/D Conversion Using COP800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-953 LCD Triplex Drive with COP820CJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-2

2-3
2-12
2-24
2-60
2-67
2-75
2-98
2-126
2-145
2-170
2-180
2-200
2-212
2-221

Dual Tone
Multiple Frequency (DTMF)

National Semiconductor
Application Note 521
Verne H. Wilson

The DTMF (Dual Tone Multiple Frequency) application is
associated with digital telephony, and provides two selected
output frequencies (one high band, one low band) for a duration of 100 ms: A benchmark subroutine has been written
for the COP820C/840C microcontrollers, and is outlined in
detail in this application note. This DTMF subroutine takes
110 bytes of COP820C/840C code, consisting of 78 bytes
of program code and 32 bytes of ROM table. The timings
in this DTMF subroutine are based on a 20 MHz
COP820C/840C clock, giving an instruction cycle time of
1 J-Ls.
The matrix for selecting the high and low band frequencies
associated with each key is shown in A"gure 1. Each key is
uniquely referenced by selecting one of the four low band
frequencies associated with the matrix rows, coupled with
selecting one of the four high band frequencies associated
with the matrix columns. The low band frequencies are 697,
770, 852, and 941 Hz, while the high band frequencies are
1209, 1336, 1477, and 1633 Hz. The DTMF subroutine assumes that the key decoding is supplied as a low order hex
digit in the accumulator. The COP820C/840C DTMF subroutine will then generate the selected high band and low
band frequencies on port G output pins G3 and G2 respectively for a duration of 100 ms.

The solution then is to use the program to produce the selected low band frequency as well as keep track of the
100 ms duration. This is achieved by using three programmed register counters RO, R2, and R3, with a backup
register R1 to reload the counter RO. These three counters
represent the half period, the 100 ms quotient, and the
100 ms remainder associated with each of the four low
band frequencies.

The DTMF subroutine makes use of two 16 b~1fe ROM t::lbles. The first ROM table contains the translation table for
the input hex digit into the core vector. The encoding of the
hex digit along with the hex digit ROM translation table is
shown in Table II. The row and column bits (RR, CC) representing the low band and high band frequencies respective, Iy of the keyboard matrix shown in Figure 1, are encoded in
TABLE I. Frequency Half Periods,
Quotients, and Remainders
Half
Freq.
Period
Hz
0.5P

1633
0
ZVl
<,

1477

:t:a::
e> ....
:E

1336

....

CDC/

1209
697
0
ZVl

770

CDS
~a::

0 ....

852

...J

941

o
R

2 W

•

.....

The theory of operation in producing the selected low band
frequency starts with loading the three counters with values
obtained from a ROM table. The half period for the selected
frequency is counted out, after which the G2 output bit is
toggled. During this half period countout, the quotient counter is decremented. This procedure is repeated until the
quotient counter counts out, after which the program
branches to the remainder loop. During the remainder loop,
the remainder counter counts out to terminate the 100 ms.
Following the remainder countout, the G2 and G3 bits are
both reset, after which the DTMF subroutine is exited. Great
care must be taken in time balancing the half period loop for
the selected low band frequency. Furthermore, the toggling
of the G2 output bit (achieved with either a set or reset bit
instruction) must also be exactly time balanced to maintain
the half period time integrity. Local stall loops (consisting of
a DRSZ instruction followed by a JP jump back to the DRSZ
for a two byte, six instruction cycle loop) are embedded in
both the half period and remainder loops. Consequently, the
ROM table parameters for the half period and remainder
counters are approximately only one sixth of what otherwise
might be expected. The program for the half period loop, •
along with the detailed time balancing of the loop for each
of the low band frequencies, is shown in Figure 2.

The COP820C/840C each contain only one timer. The
problem is that three different times must be generated to
satisfy the DTMF application. These three times are the periods of the two selected frequencies and the 100 ms duration period. Obviously the single timer can be used to generate anyone (or possibly two) of the required times, with the
program having to generate the other two (or one) times.
The solution to the DTMF problem lies in dividing the 100
ms time duration by the half periods (rounded to the nearest
micro second) tor each of the eight frequencies, and then
examining the respective high band and low band quotients
and remainders. The results of these divisions are detailed
in Table I. The low band frequency quotients range from 139
to 188, while the high band quotients range from 241 to 326.
The observation that only the low band quotients will each
fit in a single byte dictates that the high band frequency be
produced by the 16 bit (2 byte) COP820C/840C timer running in PWM (Pulse Width Modulation) Mode.

en
N

023
COLUMNS

2-3

Quotient Remainder

717

139

649

154

587

170

210

941

531

188

172

414
(256 + 158)

241

226

1336 374.25
374
High
(256 + 118)
Band
339
Freq.'s 1477 338.52
(256 + 83)

267

142

294

334

326

244

531.35

1633 306.18

TlIDD/9662-1

FIGURE 1. DTMF Keyboard Matrix

100 ms/0.5P

697 717.36
Low
770
649.35
Band
Freq.'s
852 586.85

1209 413.56

Half
Period
in J-Ls

306
(256 + 50)

337

~
('II

Z
<

r---------------------------------------------------------------------------------------~

the two upper and two lower bits of the hex digit respectively. Consequently, the format for the hex digit bits is RRCC,
so that the input byte in the accumulator will consist of
OOOORRCC. The program changes this value into
1101 RRCC before using it in setting up the address for the
hex digit ROM translation table.

ter vectors for R1, R2, and R3. The formats for the three
counter vectors are 1100XX11 (F), 11 00XX1 a (a), and
1100XX01 (R) for R1, R2, and R3 respectively. These four
vectors produced from the core vector are then used as
inputs to the second ROM table. One of these four vectors
(the T vector) is a function of the T bits from the core vector,
while the other three vectors (F, 0, R) are a function of the
X bits. This correlates to only one parameter being needed
for the timer (representing the selected high band frequency), while three parameters are needed for the three counters (half period, 100 ms quotient, 100 ms remainder) associated with the low band frequency and 100 ms duration.
The frequency parameter ROM translation table, accessed
by the T, F, 0, and R vectors, is shown in Table IV.

The core vectors from the hex digit ROM translation table
consist of a format of xxoonoo, where the two T (Timer)
bits select one of four high band frequencies, while the two
X bits select one of four low band frequencies. The core
vector is transformed into four different inputs for the second ROM table. This transformation of the core vector is
shown in Table III. The core vector transformation produces
and three programmed couna timer vector 11 oonoo

Program

LUP1:

BYP1:

BYP2:

LUP2:

BACK:

Table IV
Frequency
((114 - 1)
((104 - 1)
((93 - 1)
((83 - 1)

Bytes/Cycle

LD
LD

B,#PORTGD
X,#R1

2/3
2/3

LD
IFBIT
JP
X
SBIT
JP
NOP
RBIT
X
DRSZ
JP
JP

A,[X-]
2,[B]
BYP1
A,[X+]
2,[B]
BYP2

1/3
1/1
1/3
1/3

2,[B]
A,[X+]
R2
LUP2
FINI

1/3 DECREMENT

DRSZ
JP

RO
LUP2

1/3 DECREMENT
1/3 FCOUNT

NOP
LD
IFEo
JP

A,[X]
A,#104
LUP1

NOP
IFEo
JP
JP

Stall
+
Loop
x6)
x6)
x6)
x6)

Conditional
Cycles

1/3
1/1
1/1
1/3

1
3
1
3

1
1
3
3
3

a COUNT
1/3
3
3

3
1

2/2
1/3

,1
3
2
3

A,#93
LUP1

1/1
2/2
1/3

1
2
3

BACK

1/3

Total
=
Cycles
+ 39
+ 31
+ 35
+ 39

Total Cycles

3
1

1/1

1/3

Cycles

1/1
1/3

1
3
3

Half
Period
=717
= 649
= 587
= 531
FIGURE 2. Time Balancing for Half Period Loop

2-4

TABLE II. Hex Digit ROM Translation Table

ROW
COLUMN
ADDRESS

0
697 Hz
1209 Hz

1
770 Hz
1336 Hz

2
852 Hz
1477 Hz

DATA (HEX)

KEYBOARD

000
004
008
OOC
040
044
048
04C
080
084
088
08C
OCO
OC4
OC8
OCC

1
2
3
A
4
5
6
B
7
8
9
C

OxDO
OxDl
OxD2
OxD3
OxD4
OxD5
OxD6
OxD7
OxD8
OxD9
OxDA
OxDB
OxDC
OxDD
OxDE
OxDF

3
941 Hz
1633 Hz

• HEX DIGIT IS RRCC,
WHERE R ROW #
AND C COLUMN #
EXAMPLE: KEY 3 IS ROW #0,
COLUMN #2, SO HEX DIGIT
2
IS 0010
RRCC

=
=
=

0
#
D

TABLE III. Core Vector Translation

CORE VECTOR

XXOOTTOO

TIMER VECTOR
HALF PERIOD VECTOR
QUOTIENT VECTOR
REMAINDER VECTOR

- - - - - - - -

. TIMER
Rl
R2
R3

T
F
Q
R

1l00TTOO
1100::::11

1l00XXlO
1l00XXOl

2-5

.....
~

TABLE IV. Frequency Parameter ROM Translation Table

T - TIMER
ADDRESS

F - FREQUENCY
DATA (DEC)

OxCO
OxCl
OxC2
OxC3
OxC4
OxC5
OxC6
OxC7
OxC8
OxC9
OxCA
OxCB
OxCC
OxCD
OxCE
OxCF

Q - QUOTIENT

R - REMAINDER

VECTOR
T
R
Q
F
T
R

158
53
140
114
118
6
155
104
83
32
171
93
50
25
189
83

F
T
R
Q

In summary, the input hex digit selects one of 16 core vectors from the first ROM table. This core vector is then transformed into four other vectors (T, F, Q, R), which in turn are
used to select four parameters from the second ROM table.
These four parameters are used to load the timer, and the
respective half period, quotient, and remainder counters.
The first ROM table (representing the hex digit matrix table)
is arbitrarily placed starting at ROM location 01 DO, and has
a reference setup with the ADD A,#ODO instruction. The
second ROM table (representing the frequency parameter
table) must be placed starting at ROM location 01CO (or
OxCO) in order to minimize program size, and has reference
setups with the OR A, #OC3 instruction for the F vector and
with the OR A, # oeo instruction for the T vector.
The three parameters associated with the two X bits of the
core vector require a multi-level table lookup capability with
the LAID instruction. This is achieved with the following section of code in the DTMF subroutine:

LUP:

LD
LD

B,#Rl
X,#R4

A, [XJ

LD
LAID

A,[X]

A, [B+]

DRSZ
IFBNE
JP

R4
#4
LUP

This program code loads the F frequency vector into R4,
and then decrements the vector each time around the loop.
This successive loop decrementation of the R4 vector
changes the F vector into the Q vector, and then changes
the Q vector into the R vector. This R4 vector is used to
access the ROM table with the LAID instruction. The X
pointer references the R4 vector, while the 8 pointer is incremented each time around the loop after it has been used
to store away the three selected ROM table parameters
(one per loop). These three parameters are stored in sequential RAM locations R1, R2, and R3. The IF8NE test
instruction is used to skip out of the loop once the three
selected ROM table parameters have been accessed and
stored away.
The timer is initialized to a count of 15 so that the first timer
underflow and toggling of the G3 output bit (with timer PWM
mode and G3 toggle output selected) will occur at the same
time as the first toggling of the G2 output bit. The half period
counts for the high band frequencies range from 306 to 414,
so these values minus 256 are stored in the timer section of
the second ROM table. The selected value from this frequency ROM table is then stored in the lower half of the
timer autoreload register, while a 1 is stored in the upper
half. The timer is selected for PWM output mode and started
with the instruction lD [8],#080 where the 8 pointer is selecting the CNTRl register at memory location OEE.
The DTMF subroutine for the COP820C/840C uses 110
bytes of code, consisting of 78 bytes of program code and
32 bytes of ROM table. A program routine to sequentially
call the DTMF subroutine for each of the 16 hex digit inputs
is supplied with the listing for the DTMF subroutine.

2-6

NATIONAL SEMICONDUCTOR CORPORATION
COP800 CROSS ASSEMBLER,REV:B,20 JAN 87
DTMF

PAGE:

VERNE H. WILSON

DTMF PROGRAM FOR COP820C/840C

2
3
4

DTMF - DUAL TONE MULTIPLE FREQUENCY

5
6
7
8
9

10
11

12
13
14
15

16
17
18
19

20
21

5/1/89

PROGRAM NAME: DTMF.MAC
.TITLE DTMF
• CHIP 840
~~~~~~~ THE DTMF SUBROUTINE CONTAINS 110 BYTES ~~~~~~~
~*~~* THE DTMF SUBROUTINE TIMES OUT IN 100MSEC ~~~**
~~ FROM THE FIRST TOGGLE OF THE G2/G3 OUTPUTS **
~~~ BASED ON A 20 MHZ COP820C/840C CLOCK *~*
G PORT IS USED FOR THE TWO OUTPUTS
HIGH BAND (HB) FREQUENCY OUTPUT ON G3
LOW BAND (LB) FREQUENCY OUTPUT ON G2
TIMER COUNTS OUT
HB FREQUENCIES

23
24

PROGRAM COUNTS OUT
LB FREQUENCIES
100 MSEC DIVIDED BY LB HALF PERIOD QUOTIENT
100 MSEC DIVIDED BYLB HALF PERIOD REMAINDER

26
27
28

FORMAT FOR THE 16 HEX DIGIT MATRIX VECTOR IS 1101RRCC,
WHERE - RR IS ROW SELECT (LB FREQUENCIES)
CC IS COLUMN SELECT (HB FREQUENCIES)

30
31
32

FORMAT FOR THE 16 CORE VECTORS FROM THE MATRIX SELECT
TABLE IS XXOOTTOO, WHERE - TT IS HB SELECT
XX IS LB SELECT

FREQUENCY VECTORS (HB 8 LB) FOR FREQ PARAMETER TABLE
MADE FROM CORE VECTORS

36
37
38
39

40
41
42
43
44
45

46
47
48

50
51

HB FREQUENCY VECTORS(4) END WITH 00 FOR TIMER COUNTS,
WHERE VECTOR FORMAT IS 1100TTOO
LB FREQUENCY VECTORS(12) END WITH:
11 FOR HALF PERIOD LOOP COUNTS,
WHERE VECTOR FORMAT IS 1100XXII
10 FOR 100 MSEC DIVIDED BY HALF PERIOD QUOTIENTS,
WHERE VECTOR FORMAT IS 1100XXI0
01 FOR 100 MSEC DIVIDED BY HALF PERIOD REMAINDERS,
WHERE VECTOR FORMAT IS 1100XXOI
HEX DIGIT MATRIX TABLE AT HEX OlD~ (OPTIONAL LOCATION,
DEPENDING ON 'ADD A,IODO' INST. IMMEDIATE VALUE)
FREQ PARAMETER TABLE AT HEX

OlC~

(REQUIRED LOCATION)
TL/DD/9662-2

2·7

~ r-------------------------------------------------------------------~

C\I

lI)

NATIONAL SEMICONDUCTOR CORPORATION
COP800 CROSS ASSEMBlER,REVIB,20 JAN 87
DTMF
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
96

;MAGICI

0000
OODI
00D4
00D5
OODC
OOEA
OOEE
OOEF
OOFO
00F1
00F2
00F3
00F4
0000
0002
0005
0008
OOOA
OOOC
0000
OOOF
0011
0012
0014
0015
0016
0018
0019
OOIA
001C

DD2F
BCD1FF
BCD080
DEDC
9EOO
AE
3160
DEDC
AE
9405
A6
6C
9000
Al
BO
9CDO
EF

CORE VECTOR
XXOOTTOO
T
TTOO
F
XXII
Q
XX10
R
XXOI

TIMER
R1
R2
R3

; DECLARATIONS s
PORTlD = ODO
PORTlC = OD1
PORTGD = OD4
PORTGC = OD5
PORTO = ODC
TIMERlO = OEA
CNTRl = OEE
PSW = OEF
RO = OFO
R1 = OF1
R2 = OF2
R3 = OF3
R4 = OF4
;

STARTs

lOOP I

. FORM

;

;
;
;
;
;
;

PAGEl

lO
lD
lO
lD
lO
lD
JSR
lD
lD
ADO
X

RBIT
lD
SC
RRC

PORTl DATA REG
PORTl CON FIG REG
PORTG DATA REG
PORTG CONFIG REG
PORTO REG
TIMER lOW COUNTER
CONTROL REG
PROC STATUS WORD
lB FREQ lOOP COUNTER
lB FREQ LOOP COUNT
LB FREQ Q COUNT
LB FREQ R COUNT
LB FREQ TABLE VECTOR
SP,102F
PORTlC,IOFF
PORTlD,1080
B,IPORTD
[B],IO
A,[B]
OTMF
B,IPORTD
A,[B]
A,15
A, [B] .
4,[B]
A,PORTlD
A

A,PORTlD
lOOP

HEX DIGIT MATRIX
1

A
B

3E 0 I D
DTMF TEST lOOP
HEX MATRIX DIGIT
TO SUBROUTINE IS
OUTPUT TO PORTD
DO WIll TOGGLE
FOR EACH CALL OF
DTMF SUBROUTINE
PORTL OUTPUTS
PROVIDE SYNC
OUTPUT ORDER IS
1,5,9,D,4,8,I,A,
7,0,3,B,3E,2,6,C
TLlDD/9662-3

2-8

97
98
99
100
101
102
103
104
105
106
107
108
109
110
III
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170

0160

.=0160
;

0160
0162
0164
0165

DED5
9B3F
6B
6A

DTMFr

LD
LD
RBIT
RBIT

B,l1PORTGC
[B-],tJ03F
3,[B]
2,[B]

ADD
LAID

A,IODO

LD
X
LD
SWAP
OR
LD
LD
X
LD
LAID
X
DRSZ
IFBNE
JP

B,OO
A,[B]
A,[B]
A
A,IOC3
B,IRI
X,tJR4
A, [X]
A,[X]

LD
LD
OR
LAID
LD
LD
LD
X
lD
LD

B,OO
A, [B)
A,OOCO
B, fHIMERLO
[8+],015
[8+],00
A,[B+]
[B+], U
[B],OOBO

LD
LD

B,f1PORTGD
X,fJRl

LD
IFBIT
JP
X
SB!T
JP
NOP
RBIT
X
DRSZ
JP
JP

A,[X-]
2,[B]
BYPI
A,[X+]

OPTIONAL
OPTIONAL

;

DIGIT MATRIX TABLE

;
;

LB FREQ TADLES
(3 PARAMETERS)

;
;

HB FREQ TABLE
(1 PARAMETER)

;

START TIMER PWM

;

TEST LB OUTPUT

2,~2!

;

rl":"'"

2,[B]
A, [X+]
R2
LUP2
FINI

;

RESET LB OUTPUT

;

DECR. QUOT. COUNT

;

Q COUNT FINISHED

DRSZ
JP

RO
LUP2

;
;

DECR. F COUNT
LB (HALF PERIOD)

NOP
LD
IFEQ
JP

A, [X]
A,0}04
LUPI

NOP
IFEQ
JP
JP

A,fJ93
LUPI
BACK

;
;
;
;
;
;
;
;
;

)( 3un0E3unE * 3000E
BALANCE
LB FREQUENCY
HALF PERIOD
RESIDUE
DELAY FOR
EACH OF 4
LB FREQ'S
*****)(****3ElE*

DRSZ
JP

R3
FINI

;

DECR. REM. COUNT
R CNT NOT FINISHED

RBIT
RBIT
RBIT

4,CNTRL
3,[B]
2,[B]

;

0166 94DO
0168 A4
;

0169
016A
016B
017B
016C
016E
0170
0172
0173
0174
0175
0176
0177
0178

SF
A6
AE
65
97C3
DEFI
DCF4
B6
BE
A4
A2
C4
44
FA

0179
017A
Ol7C
017E
017F
0181
0183
0185
0186
0188

SF
AE
97CO
A4
DEEA
9AOF
9AOO
A2
9AOl
9EBO

LUP:

;

018A DED4
018C DCFI
;

018E
018F
0190
0191
0192
0193
0194
0195
0196
0197
0198
0199

BB
72
03
B2
7A
03
B8
6A
B2
C2
01
OC

019A CO
019B FE
019C
019D
019E
OIAO

B8
BE
9268
ED

DIAl
0lA2
01A4
0lA5

B8
925D
E9
FE

LUPlr

BYPI:
BYP2r
;

LUP2r

;

BACK:

0lA8 BDEE6C
01AB 6B
OIAC 6A

FINII
;

-, ... ,

"" •• - _ •• -

UUlrUI

BYP2

;

01A6 C3
01A7 FE

A,[B+]
R4
tJ4
LUP

;

STOP TIMER
CLR HB OUTPUT
CLR LB OUTPUT

;

01AD 8E

RET
;
TLIDD/9662-4

2-9

T""

U')

REPEAT:

X
WAIT:

LOOP:

SBIT
IF81T
JP
IF8NE
JP
SBIT
JP

;SEGMENT DATA TO A
;LOAD THE SIO REGISTER
;SET BUSY BIT IN PSW
;WAIT TILL SHIFTING IS
;COMPLETE
;CHECK FOR END OF FOUR
;DIGITS AND REPEAT
;DESELECT COP472
;DONE DISPLAYING

A,IB-J
A,SIO
I2,PSW
'2,PSW
WAIT

.04
REPEAT
1,PORTGD
LOOP

(Jl

......
CD

: STORE THE LOOKUP TABLE FOR SEGMENT DATA IN ROM LOCATION OFO

.•OFO

.BYTE
.BYTE
.BYTE

.BYTE

:DATA FOR 0,1,2,3
;DATA FOR 4,5,6,7
;DATA FOR B,9.A,B
;DATA FOR C,D,E,F

03F,006,05B,04F
O66,06D.07D,07
07F,067,077,07C
039,OSE,079,071

.END
TL/DD/10252-11

The code listed in this App Note is available on Dial-A-Helper.
Dial-A-Helper is a service provided by the Microcontroller Applications Group. The Dial-A-Helper system provides access to an automated information storage and retrieval system that may be accessed over standard dial-up telephone
lines 24 hours a day. The system capabilities include a MESSAGE SECTION (electronic mail) for communicating to and
from the Microcontroller Applications Group and a FILE SECTION mode that can be used to search out and retrieve
application data about NSC Microcontrollers. The minimum system requirement is a dumb terminal, 300 or 1200 baud
modem, and a telephone.
With a communications package and a PC, the code detailed in this App Note can be downloaded from the FILE
SECT!Or"! to c!~~ fer !:!tcr t!~~. Th~ D::'!-l\-H~~~Gj" t~~\:.p~vi,a ~iilo5 art;:
Modem (408) 739-1162
Voice (408) 721-5582

For Additional Information, Please Contact Factory

2-23

National Semiconductor
Application Note 596
Verne H. Wilson

COP800 MathPak

OVERVIEW

Clear Accumulator (ACC) , Set Carry (SC), and Reset Carry
(RC). The shift and rotate instructions, which include the
Rotate Right through Carry (RRC) and the Swap Accumulator Nibbles (SWAP), may also be considered as arithmetic
instruction variations. The RRC instruction is instrumental in
writing a fast multiply routine.

This application note discusses the various arithmetic operations for National Semiconductor's COP800 family of 8-bit
microcontrollers. These arithmetic operations include both
binary and BCD (Binary Coded DeCimal) operation. The four
basic arithmetic operations (add, subtract, multiply, divide)
are outlined in detail, with several examples shown for both
binary and BCD addition and subtraction. Multiplication, division, and BCD conversion algorithms are also provided.
Both BCD to binary and binary to BCD conversion subroutines are included, as well as the various multiplication and
division subroutines.

1.0 BINARY AND BCD ADDITION AND SUBTRACTION

In subtraction, a borrow is represented by the absence of a
carry and vice versa. Consequently, the carry flag needs to
be set (no borrow) before a subtraction, just as the carry
flag is reset before an addition. The ADD instruction does
not use the carry flag as an input, nor does it change the
carry flag. It should also be noted that both the carry and
half carry flags (bits 6 and 7, respectively, of the PSW control register) are cleared with reset, and remain unchanged
with the ADD, INC, DEC, DCOR, CLR and SWAP instructions. The DCOR instruction uses both the carry and half
carry flags. The SC instruction sets both the carry and half
carry flags, while the RC instruction resets both these flags.

Four sets of optimal subroutines are provided for
1. Multiplication
2. Division
3. Decimal (Packed BCD) to binary conversion
4. Binary to decimal (Packed BCD) conversion
One class of subroutines is optimized for minimal COP800
program code, while the second class is optimized for minimal execution time in order to optimize throughput time.

The following program examples illustrate additions and
subtractions of 4-byte data fields in both binary and BCD
(Binary Coded Decimal). The four bytes from data memory
locations 24 through 27 are added to or subtracted from the
four bytes in data memory locations 16 through 19. The
results replace the data in memory locations 24 through 27.

This application note is organized in four different sections.
The first section outlines various addition and subtraction
routines, including both binary and BCD (Binary Coded Decimal). The second section outlines the multiplication algorithm and provides several optimal multiply subroutines for
1, 2, 3, and 4 byte operation. The third section outlines the
division algorithm and provides several optimal division subroutines for 1, 2, 3, and 4 byte operation. The fourth section
outlines both the decimal (Packed BCD) to binary and binary
to decimal (Packed BCD) conversion algorithms. This section provides several optimal subroutines for these BCD
conversions.
The COP800 arithmetic instructions include the Add (ADD),
Add with Carry (ADC) , Subtract with Carry (SUBC), Increment (I NCR), Decrement (DECR), Decimal Correct (DCOR),

These operations are performed both in Binary and BCD. It
should be noted that the BCD pre-conditioning of Adding
(ADD) the hex 66 is only necessary with the BCD addition,
not with the BCD subtraction. The (Binary Coded Decimal)
DCOR (Decimal Correct) instruction uses both the carry and
half carry flags as inputs, but does not change the carry and
half carry flags. Also note that the # 12 with the IFBNE instruction represents 28 - 16, since the IFBNE operand is
modulo 16 (remainder when divided by 16).

2-24

»
z

BINARY ADDITION:

LOOP:

LD
LD
RC
LD
ADC
X
IFBNE
JP
IFC
JP

X,#16
B,#24
A, [X+]
A, [B]
A, [B+]
#12
LOOP
OVFLOW

NO LEADING ZERO
INDICATES DECIMAL
RESET CARRY TO START
[X] TO ACC
ADD [B] TO ACC
RESULT TO [B]
IF STILL IN DATA FIELD
JUMP BACK TO REPEAT LOOP
IF TERMINAL CARRY,
JUMP TO OVERFLOW

BINARY SUBTRACTION:

LOOP:

LD
LD
SC
LD
SUBC
X
IFBNE
JP
IFNC
JP

X,#010
B,#018
A, [X+]
A, [B]
A, [B+]
#12
LOOP
NEGRSLT

LEADING ZERO
INDICATES HEX
RESET BORROW TO START
[X] TO ACC
SUBTRACT [B] FROM ACC
RESULT TO [B]
IF STILL IN DATA FIELD
JUMP BACK TO REPEAT LOOP
IF TERMINAL BORROW,
JUMP TO NEGATIVE RESULT

BCD ADDITION:

LOOP:

LD
LD
RC
LD
ADD
ADC
DCOR
X
IFBNE
JP
IFC
JP

X,#010
B.#018
A. [X+]
A,#066
A, [B]
A
A, [B+]
#12
LOOP
OVFLOW

LEADING ZERO
INDICATES HEX
RESET CARRY TO START
[X] TO ACC
ADD HEX 66 TO ACC
ADD [B] TO ACC
DECIMAL CORRECT RESULT
RESULT TO [B]
IF STILL IN DATA FIELD
JUMP BACK TO REPEAT LOOP
IF TERMINAL CARRY
JUMP TO OVERFLOW

BCD SUBTRACTION:

LOOP:

LlJ
LD
C
LD
SUBC
DCOR
X
IFBNE
JP
IFNC
JP

X,#lS

B,#24
A. [X+]
A. [B]
A
A, [B+]
#12
LOOP
NEGRSLT

NO LEADING ZERO
INDICATES DECIMAL
[X] TO ACC
SUBTRACT [B] FROM ACC
DECIMAL CORRECT RESULT
RESULT TO [B]
IF STILL IN DATA FIELD
JUMP BACK TO REPEAT LOOP
IF TERMINAL BORROW
JUMP TO NEGATIVE RESULT

2-25

U,
CD
en

The astute observer will notice that these previous additions
and subtractions are not "adding machine" type arithmetic
operations in that the result replaces the second operand
rather than the first. The following program examples iUus- ;

trate "adding machine" type operation where the result replaces the first operand. With subtraction, this entails the
result replacing the minuend rather than the" subtrahend.
Note that the B and X pOinters are now reversed.

BINARY ADDITION:

LOOP:

LD
LD
RC
LD
ADC
X
IFBNE
JP
IFC
JP

B POINTER AT FIRST OPERAND
X POINTER AT SECOND OPERAND
RESET CARRY TO START
[X]" TO ACC"
ADD [B] TO ACC
RESULT TO [B]
IF STILL IN DATA FIELD
JUMP BACK TO REPEAT LOOP
IF'TERMINAL CARRY
JUMP TO OVERFLOW

B,#16
X,#24
A, [X+l .
A, [B]
A, [B+]
#4
LOOP
OVFLOW

BINARY SUBTRACTION:

LOOP:

LD
LD
SC
LD
X
SUBC
X
IFBNE
JP
IFNC
JP

, B POINTER AT FIRST OPERAND

B,#OlO
X,OlB
A, [X+] "
A, [B]
A, [B]
A, [B+]
#4
LOOP
NEGRSLT

X POINTER AT SECOND OPERAND
RESET BORROW TO START
.. ; [X] 'TO ACC
EXCHANGE [B] AND ACC
SUBTRACT [B] FROM ACC
RESULT TO [B]
IF STILL IN DATA FIELD
JUMP BACK TO REPEAT LOOP
;
'. ' 'IF TERMINAL BORROW
JUMP TO NEGATIVE RESULT

BCD ADDITION:

LOOP:

LD
LD
RC
LD
ADD
ADC
DCOR
X
IFBNE
JP
IFC
JP

B,#OlO
X,#OlB
A, [X+]
A,#066 '
A, [B]
A
A, [B+]
#4
LOOP

OVFLOW

B POINTER AT FIRST OPERAND
X POINTER AT SECOND OPERAND
RESET CARRY TO START
[X] TO ACC
ADD'HEX66 TO ACC
ADD [B] TO ACC
DECIMAL CORRECT RESULT
RESULT TO [B]
IF STILL IN DATA FIELD
JUMP BACK TO REPEAT LOOP
IF TERMINAL CARRY
JUMP,TO OVERFLOW

BCD SUBTRACTION:

LOOP:

LD
LD
SC
LD
X
SUBC
DCOR
X
IFBNE
JP
IFNC
JP

B,#16
X,#24
A, [X+]
A, [B]
A, [B]
A
A, [B+]
#4
LOOP
NEGRSLT

B POINTER AT FIRST OPERAND
X POINTER AT SECOND OPERAND
RESET BORROW TO START
, [X] TO ACC
; EXCHANGE [B] AND ACC
SUBTRACT [B] FROM ACC
DECIMAL CORRECT RESULT
RESULT TO [B]
IF STILL IN DATA FIELD
JUMP BACK TO REPEAT LOOP
IF TERMINAL BORROW
JUMP TO NEGATIVE RESULT

2-26

that the ROM table is located starting at program memory
address 0401, while SUM and TOT are at RAM data memory locations [1, 0] and [3, 2] respectively, and that we wish
to encode the program as a subroutine.

Let us now consider a hybrid arithmetic example, where we
wish to add five successive bytes of a data table in ROM
program memory to a two byte sum, and then subtract the
SUM result from a two byte total TOT. Let us further assume
ROM Table:
· = 0401

· Byte 102
· Byte 41
· Byte 31
· Byte 26
· Byte 5
ROM Table Accessed Top Down
SUMLO = 0
SUMHI = 1
TOTLO = 2
TOTHI = 3

ARITH1:
LOOP:

LUP:

LD
LD
RC
LD
LAID
ADC
X
CLR
ADC
X
DRSZ
JP
SC
LD
LD
X
SUBC
X
IFBNE
JP
RET

Xt #5
Bt#O
AtX
At [B]
At [B+]
A
At [B]
At [B-]
X
LOOP
Bt #2
At [X+]
At [B]
At [B]
At [B+]
#4
LUP

SET UP ROM TABLE POINTER
SET UP SUM POINTER
RESET CARRY TO START ADDITION
ROM POINTER TO ACC
TABLE VALUE FROM ROM TO ACC
ADD SUMLO TO ACC
RESULT TO SUMLO
CLEAR ACC
ADD SUMHI TO ACC
RESULT TO SUMHI
DECR AND TEST. ROM PTR FOR ZERO
JUMP BACK TO REPEAT LOOP
IF X PTR NOT ZERO
RESET BORROW TO START SUBTRACTION
SET UP TOT POINTER
SUBTRAHEND (SUM) TO ACC
REVERSE OPERANDS
FOR SUBTRACTION
RESULT TO TOT
IF STILL IN TOT FIELD
JUMP BACK TO REPEAT LUP
RETURN FROM SUBROUTINE

2-27

»
z
en
CD
0)

en
Ln

Z
<

r---------------------------------------------------------------------------------------,
2.0 MULTIPLICATION
The COP800· multiplications are all based on starting the
multiplier in the low order end of the double length product
space. The high end of the double length product space is
initially cleared, and then the double length product is shifted right one bit. The bit shifted out from the low order end
represents the low order bit of the multiplier. If this bit is a
"1", the multiplicand is added to the high end of the double
length product space. The entire shifting process and the
conditional addition of the multiplicand to the upper end of
the double length product is then repeated. The number of
shift cycles is equal to the number of bit positions in the
multiplier plus one extra shift cycle. This extra terminal shift
cycle is necessary to correctly align the resultant product.
Note that an M byte multiplicand multiplied by an N byte
multiplier will result in an M + N byte double length product.
However, these multiplication subroutines will only use 2M
+ N + 1 bytes of RAM memory space, since the multiplier
initially occupies the low order end of the double length
product. The one extra byte is necessary for the shift coun~
ter CNTR.

MPY816 (or MPY824, MPY832)
- 8 by16 (or 24,32) Multiply Subroutine
- 22 Bytes
- 589 (or 1065, 1669) Instruction Cycles Average
- 597 (or 1077, 1685) Instruction Cycles
Maximum
- Minimum Code, Minimum RAM
- Extendable Routine for MPY8XX by
Changing Parameters, with Number of
Bytes (22) Remaining a Constant

The minimal code (28 byte) general multiplication subroutine is shown with two different· examples, MY2448 and
MY4824. Both examples multiply 24 bits by 48 bits. The
MY2448 subroutine uses the 48-bit operand as the multiplier, and consequently uses minimal RAM as well as minimal
program code. The MY4824 subroutine uses the 24-bit operand as the multiplier, and consequently executes considerably faster than the minimal RAM MY2448 subroutine.
MPY88

- 8 by 8 Multiplication Subroutine
-19 Bytes
- 180 Instruction Cycles
- Minimum Code

MLT88

Fast 8 by 8 Multiplication Subroutine
42 Bytes
145 Instruction Cycles

VFM88

Very Fast 8 by 8 Multiply Subroutine
96 Bytes
116 Instruction Cycles

MPY168

Fast 16 by 8 Multiplication Subroutine
36 Bytes
230 Instruction Cycles Average
254 Instruction Cycles Maximum

MPY248

Fast 24 by 8 Multiplication Subroutine
47 Bytes
289 Instruction Cycles Average
333 Instruction Cycles Maximum.. .
Fast 16 by 16 Multiplication Subroutine
39 Bytes
498 Instruction Cycles Average
546 Instruction Cycles Maximum

MP1616

16 by 16 Multiplicand Subroutine
29 Bytes
759 Instruction Cycles Average
807 Instruction Cycles Maximum
Almost Minimum Code

MY1616

(or MY1624, MY1632)
- 28 Bytes
- 16 by 16 (or 24, 32) Multiply Subroutine
- 861 (or 1473, 2213) Inst. Cycles Average
- 1029 (or 1725, 2549) Inst. Cycles Maximum
- Minimum Code, Minimum RAM
- Extendable Routne for MY16XX by
Changing Parameters, with N·umber of
Bytes (28) Remaining a Constant

MX1616

Minimal general multiplication subroutine for any number of
bytes in multiplicand and multiplier
- 28 Bytes
- Minimum Code
- MY2448 Used as First Example,
with Minimum RAM and
4713 Instruction Cycles Average
5457 Instruction Cycles Maximum
- MY4824 Used as Second Example,
with Non Minimal RAM and
2751 Instruction Cycles Average
3483 Instruction Cycles Maximum

2-28

>
z

MPY88-8 BY 8 MULTIPLICATION SUBROUTINE

MPY88 :

M88LUP :

MINIMUM CODE
19 BYTES
180 INSTRUCTION CYCLES
MULTIPLICAND IN [0]
MULTIPLIER IN [1]
PRODUCT IN [2,1]
LD
CNTR, #9
RC
LD
B,#2
CLR
A
RRC
A
X

A, [B-]

LD
RRC

A,[B]
A

A, [B-]

CLR
IFC
LD
RC
LD
ADC
DRSZ
JP
RET

A
A, [B]

B,#2
A, [B]
CNTR
M88LUP

(ICAND)
(IER)
(PROD)
LD CNTR WITH LENGTH OF
MULTIPLIER FIELD + 1
CLEAR UPPER PRODUCT
RIGHT SHIFT
UPPER PRODUCT
RIGHT SHIFT LOWER
PRODUCT/MULTIPLIER
CLR ACC AND TEST LOW
ORDER MULTIPLER BIT
MULTIPLICAND TO ACC IF
LOW ORDER BIT
1
ADD MULTIPLICAND TO
UPPER PRODUCT
DECREMENT AND TEST
CNTR FOR ZERO
RETURN FROM SUBROUTINE

2·29

MLT88-FAST 8 BY 8 MULTIPLICATION SUBROUTINE

MLT88:

ML88LP:

42 BYTES
145 INSTRUCTION CYCLES
MULTIPLICAND IN [0]
MULTIPLIER IN [1]
PRODUCT IN [2.1]
LD
CNTR.#3
RC
LD
B.#2
CLR
A
RRC
X

LD
RRC
X

CLR
IFC
LD
RC
LD
ADC
RRC
X

LD
RRC
X

CLR
IFC
LD
RC
LD
ADC
RRC
X

LD
RRC
X

CLR
IFC
LD
RC
LD
ADC
DRSZ
JMP
RET

(ICAND)
(IER)
(PROD)
LOAD CNTR WITH
1/3 OF LENGTH OF
(MULTIPLIER FIELD + 1)
CLEAR UPPER PRODUCT

A
A. [B-]
A. [B]
A
A. [B-]
A

RIGHT SHIFT
***
, UPPER, PRODUCT

A. [B]
B.#2
A, [B]
A
A, [B-]
A, [B]
A
A. [B-]
A

'RIGHT SHIFT LOWER
PRODUCT /MULT IPLIER
CLR ACC AND TEST ,LOW
ORDER MULTIPLIER BIT
MULTIPLICAND TO ACC IF
'LOW ORDER BIT
1
, ADD MULTIPLICAND TO
UPPER· PRODUCT ***

A. [B]

REPEAT THE ABOVE
'. 11 BYTE '.
13 INSTRUCTION
CYCLE PROGRAM
SECTION (WITH
THE *** DELIMITERS)
TWICE MORE FOR A
TOTAL OF THREE TIMES

B.#2
A, [B]

END OF SECOND REPEAT

A
A, [B-]
A. [B]
A
A, [B-]
A

START OF THIRD REPEAT

A. [B]
B,#2
A, [B]
CNTR
ML88LP

END OF THIRD REPEAT
DECREMENT AND TEST
CNTR FOR ZERO
RETURN FROM SUBROUTINE

2-30

VFM88-VERY FAST 8 BY 8 MULTIPLY SUBROUTINE

96 BYTES
116 INSTRUCTION CYCLES

VFM88:

MULTIPLICAND IN [OJ
MULTIPLIER IN [lJ
PRODUCT IN [2,lJ
RC
LD
B,#2
LD
[B-J,#O
LD
A, [BJ
RRC
A
X
A, [B-J
CLR
A
IFC
LD
A, [BJ
RC
LD
B,#2
ADC
A, [BJ
RRC

A, [B-J
A, [BJ

LD
RRC
X

CLR
IFC
LD
RC
LD
ADC

A, [B-J
A
A, [BJ

B,#2
A, [BJ

(ICAND)
(IER)
(PROD)
CLEAR UPPER PRODUCT
RIGHT SHIFT LOWER
PRODUCT/MULTIPLIER
CLR ACC AND TEST LOW
ORDER MULTIPLIER BIT
MULTIPLICAND TO ACC IF
LOW ORDER BIT
1
ADD MULTIPLICAND TO
UPPER PRODUCT

RIGHT SHIFT
***
UPPER PRODUCT

RIGHT SHIFT LOWER
PRODUCT/MULTIPLIER
CLR ACC AND TEST LOW
ORDER MULTIPLIER BIT
MULTIPLICAND TO ACC IF
LOW ORDER BIT
1
, ADD MULTIPLICAND TO
UPPER PRODUCT ***

THE ABOVE 11 BYTE, 13 INSTRUCTION CYCLE SECTION WITH THE ***
DELIMITERS REPRESENTS THE PROCESSING FOR ONE MULTIPLIER BIT.
REPEAT THE
ABOVE SECTION
SIX MORE TIMES,
FOR A TOTAL
OF SEVEN TIMES
RRC

A, [B-J
A, [BJ

LD
RRC
X

RET

A
A, [BJ

RIGHT SHIFT
UPPER PRODUCT
RIGHT SHIFT LOWER
PRODUCT/MULTIPLIER
RETURN FROM SUBROUTINE

2·31

MPY168-FAST 16 BY 8 MULTIPLICATION SUBROUTINE

36 BYTES
230 INSTRUCTION CYCLES AVERAGE
254 INSTRUCTION CYCLES MAXIMUM

MPYl68:

M168LP:

MP168S:

MP168T:

MULTIPLICAND IN [1.0]
MULTIPLIER IN [2]
PRODUCT IN [4.3.2]
LD
CNTR.#9
RC
LD
B.#4
LD
[B-].#O
LD
[B-].#O
JP
MP168S
RRC
A
X
A. [B-]
LD
A. [B]
RRC
A
X
A. [B-]
LD
A. [B]
RRC
A
X
A. [B]
IFNC
JP
MP168T
RC
LD
B.#O
LD
A. [B]
LD
B.#3
ADC
A. [B]
X
A. [B]
LD
B.#l
LD
A. [B]
LD
B.#4
ADC
A. [B]
DRSZ
CNTR
JP
M168LP
LD
LD
DRSZ
JP
RET

B.#4
A. [B]
CNTR
M168LP

(ICAND)
(IER)
(PROD)
LD CNTR WITH LENGTH OF
MULTIPLIER FIELD + 1
CLEAR
UPPER PRODUCT
RIGHT SHIFT UPPER
BYTE OF PRODUCT
RIGHT SHIFT MIDDLE
BYTE OF PRODUCT
RIGHT' SHIFT LOWER
PRODUCT/MULTIPLIER
TEST LOWER BIT
OF MULTIPLIER
' CLEAR, CARRY
LOWER BYTE OF
MULTIPLICAND TO ACC
ADD LOWER BYTE OF
MULTIPLICAND TO
MIDDLE BYTE OF PROD
UPPER BYTE OF
MULTIPLICAND TO ACC
ADD UPPER BYTE OF ICAND
TO UPPER BYTE OF PROD
DECREMENT CNTR AND JUMP
BACK TO LOOP; CNTR
CANNOT EQUAL ZERO
HIGH ORDER PRODUCT
BYTE TO ACC
DECREMENT AND TEST IF
CNTR EQUAL TO ZERO
RETURN FROM SUBROUTINE

2-32

»
z

MPY816-(OR MPY824, MPY832) 8 BY 16 (OR 24, 32) MULTIPLY SUBROUTINE

MINIMUM CODE, MINIMUM RAM
22 BYTES
589 (OR 1065, 1669) INSTR. CYCLES AVERAGE
597 (OR 1077, 1685) INSTR. CYCLES MAXIMUM
EXTENDABLE ROUTINE FOR MPY8XX BY CHANGING
PARAMETERS, WITH NUMBER OF BYTES (22)
REMAINING A CONSTANT.

MULTIPLICAND IN [0]
(ICAND)
MULTIPLIER IN [2,1] FOR 16 BIT (IER)
OR [3,2,1] for 24 BIT
OR [4,3,2,1] for 32 BIT
PRODUCT IN [3,2,1] FOR 16 BIT
(PROD)
OR [4,3,2,1] FOR 24 BIT
OR [5,4,3,2,1] FOR 32 BIT
MPY816:

M8XXLP:
M8XXL:

!!'8~~T:

CNTR,#17

LD CNTR WITH LENGTH OF
MULTIPLIER FIELD + 1
#17 FOR MPY816 16 BIT
(#25 FOR MPY824 24 BIT)
(#33 FOR MPY832 32 BIT)

RC
LD

B,#3

#3 FOR MPY816
(#4 FOR MPY824)
(#5 FOR MPY832)
CLEAR UPPER PRODUCT
FIVE INSTRUCTION
PROGRAM LOOP TO
RIGHT SHIFT
PRODUCT/MULTIPLIER
LOOP JUMP BACK
CLR ACC AND TEST LOW
ORDER MULTIPLIER BIT
JP IF LOW ORDER BIT
0

LD
LD
RRC
X
IFBNE
JP
CLR
IFNC
JP
RC
LD
LD
LD

B,#O
A, [B]
n,#3

ADC

A, [B]

DRSZ
JP
RET

CNTR
M8XXL

[B-] ,#0
A, [B]
A
A, [B-]
#0
M8XXLP
A
M8XXT

MULTIPLICAND TO ACC
#3 :FOR MPY816
(#4 FOR MPY824)
(#5 FOR MPY832)
ADD MULTIPLICAND TO
UPPER BYTE OF PRODUCT
DECREMENT AND TEST
CNTR FOR ZERO
RETURN FROM SUBROUTINE

2·33

U)
Q)

MPY248-FAST 24 BY 8 MULTIPLICATION SUBROUTINE

47 BYTES
289 INSTRUCTION CYCLES AVERAGE
333 INSTRUCTION CYCLES MAXIMUM
MULTIPLICAND IN [2,1,0]
(ICAND)
MULTIPLIER IN [3]
(IER)
PRODUCT IN [6,5,4,3]
(PROD)

cs:

MPY248:

M248LP:

MP248S:

MP248T:

LD
RC
LD
LD
LD
LD
JP
RRC
X
LD
RRC
X
LD
RRC
X
LD
RRC
X
IFNC
JP
RC
LD
LD
LD
ADC
X
LD
LD
LD
ADC
X
LD
LD
LD
ADC
DRSZ
JP
LD
LD
DRSZ
JMP
RET

CNTR,#9
B.#6
[B-] ,#0
[B-] ,#0
[B-] ,#0
MP248S
A
A, [B-]
A, [B]
A
A, [B-]
A, [B]
A
A, [B-]
A, [B]
A
A, [B]
MP248T
B,#O
A, [B]
B,#4
A, [B]
A, [B]
B,#l
A, [B]
B,#5
A, [B]'
A, [B]
B,#2
A, [B]
B,#6
A, [B]
CNTR
M248LP
B,#6
A, [B]
CNTR
M248LP

LD CNTR WITH LENGTH OF
MULTIPLIER FIELD + 1
CLEAR THREE
UPPER BYTES
OF PRODUCT
JUMP TO START
RIGHT SHIFT HIGH
ORDER PRODUCT BYTE
RIGHT SHIFT NEXT LOWER
ORDER PRODUCT BYTE
RIGHT SHIFT NEXT LOWER
ORDER PRODUCT BYTE
RIGHT SHIFT LOW ORDER
PRODUCT/MULTIPLIER
TEST LOW ORDER
MULTIPLIER BIT
LOAD ACC WITH LOW ORDER
MULTIPLICAND BYTE
ADD LOW ORDER ICAND
BYTE TO NEXT TO LOW
ORDER PRODUCT BYTE
LOAD ACC WTIH MIDDLE
MULTIPLICAND BYTE
ADD MIDDLE ICAND BYTE
TO NEXT TO HIGH ORDER
MULTIPLICAND BYTE
LOAD ACC WITH HIGH ORDER
MULTIPLICAND BYTE
ADD HIGH ORDER ICAND BYTE
TO HIGH ORDER PROD BYTE
DECREMENT CNTR AND JUMP
BACK TO LOOP; CNTR
CANNOT EQUAL ZERO
HIGH ORDER PRODUCT
BYTE TO ACC
DECREMENT AND TEST
CNTR FOR ZERO
RETURN FROM SUBROUTINE

2-34

MX1616-FAST 16 BY 16 MULTIPLICATION SUBROUTINE

en
CO

39 BYTES
498 INSTRUCTION CYCLES AVERAGE
546 INSTRUCTION CYCLES AVERAGE
MULTIPLICAND IN [1.0]
MULTIPLIER IN [3.2]
PRODUCT IN [5.4.3.2]
MX1616:

MX1616L:

MXSTRT:

MX1616T:

LD
RC
LD
LD
LD
JP
RRC
X
LD
RRC
X
LD
RRC
X
LD
RRC
X
IFNC
JP
RC
LD
LD
LD
ADC
X
LD
LD
LD
ADC
DRSZ
JP
LD
LD
DRSZ
JP
RET

(ICAND)
(IER)
(PROD)

CNTR.#17

LD.CNTR WITH LENGTH OF
MULTIPLIER FIELD + 1

B.#5
[B-].#O
[B-].#O
MXSTRT
A
A. [B-]
A. [B]
A
A. [B-]
A. [BJ
A
A. [B-J
A. [BJ
A
A. [BJ

CLEAR UPPER TWO
PRODUCT BYTES
JUMP TO STARTRIGHT SHIfT
UPPER:PROPUCT BYTE
;

RIGHT SHIFT NEXT LOWER
PRODUCT BYTE
RIGHT SHIFT PRODUCT
UPPER MULTIPLIER BYTE
RIGHT SHIFT PRODUCT
LOWER MULTIPLIER BYTE
TEST LOW, ORDER
MULTIPLIER BIT

MX1616T
B.#O
A. [BJ
B.#4
A. [B]
A. [BJ
B.#l
A. [B]
B.#5
A. [BJ
CNTR
MX1616L
B.#5
A. [BJ
CNTR
MX1616L

.
;

LOAD ACC WITH LOWER
MULTIPLICAND BYTE
ADD LOWER ICAND BYTE
TO NEXT. TO. HIGH·
ORDER PRODUCT BYTE
LOAD ACC WITH UPPER
MULTIPLICAND BYTE
ADD UPPER ICAND BYTE TO
HIGH ORDER PRODUCT
D~CHEMENT CNTR AND JUMP
BACK TO LOOP; CNTR
CANNOT EQUAL ZERO
HIGH ORDER PRODUCT
BYTE TO ACC
DECREMENT AND TEST
CNTR FOR ZERO
RETURN FROM SUBROUTINE

2·35

en
Lt)

MP1616-16 BY 16 MULTIPLICATION SUBROUTINE

MINIMUM CODE
29 BYTES
759 INSTRUCTION CYCLES AVERAGE
807 INSTRUCTION CYCLES MAXIMUM]
MULTIPLICAND IN [1.0]
(ICAND)
MULTIPLIER IN [3.2]
(IER)
(PROD)
PRODUCT IN [5.4.3.2]

MP1S1S:

M1S1SX:
M1S1SL:

M1S1ST:

LD
RC
LD
LD
LD
LD
RRC
X
IFBNE
JP
CLR
IFNC
JP
RC
LD
LD
LD
ADC
X
LD
LD
LD
ADC
DRSZ
JP
RET

LD CNTR WITH LENGTH OF
MULTIPLIER FIELD + 1

CNTR.#17
B.#5
[B-].#O
[B-].#O
A. [B)
A
A. [B-]
#1
M1S1SX
A

CLEAR UPPER TWO
PRODUCT BYTES
FIVE INSTRUCTION
PROGRAM LOOP TO
RIGHT· SHIFT
PRODUCT/MULTIPLIER.
' LOOP JUMP BACK
CLEAR ACC
TEST LOW ORDER
'MULTIPLIER BIT

M1S1ST
B.#O
A. [B)
B.#4
A. [B)
A. [B)
B.#l
A. [B)
B.#5
A. [B)
CNTR
M1S1SL

..
,

LOAD ACC WITH LOWER
MULTIPLICAND BYTE
ADD LOWER ICAND BYTE
TO NEXT TO LOW
ORDER PRODUCT BYTE
LOAD ACC WITH UPPER
MULTIPLICAND BYTE
ADD UPPER ICAND BYTE TO
HIGH ORDER PRODUCT
DECREMENT AND TEST
CNTR EQUAL TO ZERO
RETURN FROM SUBROUTINE

2-36

l>
MY1616 (OR MY1624, MY1632)-16 BY 16 (OR 24, 32) MULTIPLY SUBROUTINE

MINIMUM CODE, MINIMUM RAM
28 BYTES
861 (OR 1473, 2213) INST. CYCLES AVERAGE
1029 (OR 1725,1473) INST. CYCLES MAXIMUM
EXTENDABLE ROUTINE FOR MY16XX BY CHANGING
PARAMETERS, WITH NUMBER OF BYTES (28)
REMAINING A CONSTANT
MULTIPLICAND IN [1,0]
(ICAND)
MULTIPLIER IN [3,2] FOR 16 BIT
(IER)
OR [4,3,2] FOR 24 BIT
OR [5,4,3,2] FOR 32 BIT
PRODUCT IN [5,4,3,2] FOR 16 BIT
(PROD)
OR [6,5,4,3,2] FOR 24 BIT
OR [7,6,5,4,3,2] FOR 32 BIT
MYl616:

MYl6XS:

CNTR,#17

B,#5

LD
LD
RC
LD
RRC

[B-] ,#0
[B-],#O

IFBNE
JP
IFNC
JP
RC
LD

MYl6XL:

MYl6XT:

LD
LD
ADC

A, [B]
A
A, [B-]

#1
M16XS
MYl6XT
B,#4

X,1t-U
A, [X+]
A, [B]
A, [B+]

IFBNE
JP
LD

#2
MYl6XL
B,#5

DRSZ
JP
RET

CNTR
MYl6XS

LD CNTR WITH LENGTH OF
MULTIPLIER FIELD + 1
#17 FOR MYl616
(#25 FOR MYl624)
(#33 FOR MYl632)
#5 FOR MYl616
(#6 FOR MYl624)
(#7 FOR MYl632)
CLEAR UPPER TWO
PRODUCT BYTES
FIVE INSTRUCTION
PROGRAM LOOP TO
RIGHT SHIFT
PRODUCT/MULTIPLIER
LOOP JUMP BACK
TEST LOW ORDER
MULTIPLIER BIT
#4 FOR MYl616
(#5 FOR MYl624)
(#6 FOR MYl632)
LOAD ACC WITH
MULTIPLICAND BYTES
; ADD MULTIPLICAND TO
HI TWO PROD. BYTES
; LOOP BACK FOR SECOND
MULTIPLICAND BYTE
; #5 FOR MYl616
(#6 FOR MYl624)
(#7 FOR MYl632)
DECREMENT AND TEST
CNTR EQUAL TO ZERO
RETURN FROM INTERRUPT

2·37

en
CO

~ ~--------------------------------------------------------------------------------,

•

DX1616-FAST 16 BY 16 DIVISION SUBROUTINE

53 BYTES
638 INSTRUCTION CYCLES AVERAGE
678 INSTRUCTION CYCLES MAXIMUM
DIVIDEND IN [1,0]
(DD)
(DR)
DIVISOR IN [5,4]
(QUOT)
QUOTIENT IN [1,0]
(TEST FIELD)
REMAINDER IN [3,2]
DX1616:

DX616S:
DX616L:

DX616T:

LD
LD
LD
XOR
X
LD
XOR
X
LD
LD
LD
RC
LD
ADC
X
LD
ADC
X
LD
ADC
X
LD
ADC
X
SC
LD
LD
ADC
LD
LD
LD
ADC
IFNC
JP
X
LD
LD
ADC
X
LD
SBIT
DRSZ
JP
RET
DRSZ
JMP
RET

LOAD CNTR WITH LENGTH
OF DIVIDEND FIELD
REPLACE DIVISOR WITH
lIS COMPLEMENT OF
DIVISOR TO ALLOW
OPTIONAL ADDITION OF
DIVISOR'S COMPLEMENT
IN MAIN PROG. LOOP
CLEAR
TEST FIELD

CNTR,#16
B,#5
A, [B]

A,#OFF
A, [B-]
A, [B]
A,#OFF
A, [B-]
[B-],#O
[B] ,#0

B,#O
A, [B]
A, [B]
A, [B+]
A, [B]
A, [B]
A, [B+]
A, [B]
A, [B]
A, [B+]
A, [B]
A, [B]
A. [B+]

LEFT SHIFT DIVIDEND LO
LEFT SHIFT DIVIDEND HI
LEFT SHIFT TEST FIELD LO
LEFT SHIFT TEST FIELD HI

DIVISORX (DRX) LO TO ACC
(l'S COMPLEMENT)
ADD REM LO TO DRX LO

[B]
B,#2
A, [B]
B,#5
:.., [TI]
B,#3
A, [B]

DIVISORA (DRA) HI IO Ace
(l'S COMPLEMENT)
ADD REM HI TO DRX HI
TEST IF NO 'CARRY FROM
lIS COMPL.ADDITION
RESULT TO REM HI
DRX LO TO ACCUMULATOR

DX616T
A, [B+]
A, [B]
B,#2
[B]
[B]
B,#O
0, [B]

A,
A,

CNTR
DX616L
CNTR
DX616S

..,

ADD REM LO TO DRX LO
RESULT TO REM LO
SET QUOTIENT BIT
DECREMENT AND TEST
CNTR FOR ZERO
RETURN FROM SUBROUTINE
DECREMENT AND TEST
CNTR FOR ZERO
RETURN FROM SUBROUTINE

C11
CO
Q)

0')
Lt)
I

r-----------------------------------------------------------------------------------~

DV2815-FAST 28 BY 15 DIVISION SUBROUTINE

WHERE THE DIVIDEND IS LESS THAN 2**28
AND THE DIVISOR IS GREATER THAN 2**12 (4096) AND LESS THAN 2**15 (32768)
43 BYTES
640 INSTRUCTION CYCLES AVERAGE
696 INSTRUCTION CYCLES MAXIMUM
DIVIDEND IN [3.2.1.0]
(DD)
DIVISOR IN [5.4]
(DR)
QUOTIENT IN [1.0]
(QUOT)
REMAINDER IN [3.2]
(TEST FIELD)

BINDEC-Blnary to Decimal (Packed BCD)

c.n
U)
<»

This 25 byte subroutine represents very minimal code for
translating a binary number of any length to packed BCD
decimal.
ALGORITHM:
The packed BCD decimal result is resident just above the
binary number. A sufficient number of bytes must be allowed for the BCD result. During each cycle of the algorithm
the binary number is shifted left one bit position. The packed
BCD decimal result is also shifted left one bit position, with
the high order bit of the binary field being shifted up into the
low order bit position of the BCD field. The shifted result in
the BCD field is decimal corrected by using the DCOR instruction. Note that for addition an "ADD A, #066" instruction must be used in conjunction with the DCOR (Decimal
Correct) instruction. The entire cycle is then repeated, with
the total number of cycles being equal to the number of bit
positions in the binary field.
16 Bit:

Binary in [1,0]
Packed BCD in [4, 3, 2]

24 Bit:

Binary in [2, 1, 0]
Packed BCD in [6, 5, 4, 3]

32 Bit:

Binary in [3, 2, 1, 0]
Packed BCD in [8, 7, 6, 5, 4]

25 Bytes
856 Instructions Cycles (16 Bit)

BINDEC:

CNTR,#1S

LOAD CNTR WITH NUMBER OF BIT POSITIONS
IN BINARY FIELD
#1S FOR 1S BIT (2 BYTE)
#'S 24/32 FOR 24/32 BIT

BD1:

RC
LD
LD
IFBNE
JP

B,#2
[B+],#O
#5
BD1

#'S 3/4 FOR 24/32 BIT
CLEAR BCD FIELD
#'S 7/9 FOR 24/32 BIT
JUMP BACK FOR CLR LOOP

BD2:
BD3:

!:D

B,f,lO

LD
ADC

A, [BJ
A, [B]
A, [B+]
#2
BD3
A, [BJ
A,#OSS
A, [BJ
A
A, [B+]
#5
BD4
CNTR
BD2

BD4:

IFBNE
JP
LD
ADD
ADC
DCOR
X

IFBNE
JP
DRSZ
JP
RET

PROGRAM LOOP TO
LEFT SHIFT
BINARY FIELD
#'S 3/4 FOR 24/32 BIT
JUMP BACK FOR SHIFT LOOP1
PROGRAM LOOP TO
LEFT SHIFT AND
DECIMAL CORRECT
RESULT OF SHIFT
IN BCD FIELD
#'S 7/9 FOR 24/32 BIT
JUMP BACK FOR SHIFT LOOP2
DECREMENT AND TEST IF
CNTR EQUAL TO ZERO
RETURN FROM SUBROUTINE

2-55

(£)

en
ll)

FBTOD-FAST BINARY TO DECIMAL (PACKED BCD)
Algorithm:

This algorithm is based on the BINDEC
algorithm, except that it is optimized for
speed of execution.

Binary in [1, OJ
Packed BCD in [4, 3, 2J
59 Bytes
334 Instruction Cycles

FBTOD:

FBD1:

FBD2:

RC
LD
LD
SWAP
X
LD
AND
IFGT
ADD
X
LD
LD
LD

B,#l
A, [B]
A
A, [B]
A, [B+]
A,#OF
A,#9
A,#06
A, [B+]
[B+],#O
[B],#O
CNTR,#4

LD
LD
ADC
X
LD
ADD
ADC
DCOR
X
LD
ADC
X

B,#l
A, [B]
A, [B]
A, [B+]
A, [B]
A,#066
A, [B]
A
A, [B+]
A, [B]
A, [B]
A, [B]

DRSZ
JP
LD
LD
LD
ADC
X
LD
LD
ADD
ADC
DCOR
X
LD
ADD
ADC
DCOR
X
LD
ADC
X

CNTR
FBDl
CNTR,#8
B,#O
A, [B]
A, [B]
A, [B]
B,#2
A, [B]
A,#066
A, [B]
A
A, [B+]
A, [B]
A,#066
A, [B]
A
A, [B+]
A, [B]
A, [B]
A, [B]

DRSZ
JP
RET

CNTR
FBD2

REVERSE NIBBLES IN
UPPER BINARY BYTE
EXTRACT ORIGINAL UPPER
NIBBLE OF HI BYTE
IF NIBBLE GREATER THAN
NINE, THEN ADD SIX TO CORRECT BCD NIBBLE
NIBBLE TO LOWER BCD BYTE
CLEAR UPPER BCD BYTES
INITIALIZE CNTR TO COVER
REMAINING HI NIBBLE (ORIGINALLY LO NIBBLE)
IN UPPER BINARY BYTE
PROGRAM LOOP TO
LEFT SHIFT A BIT
OUT OF UPPER BINARY
BYTE INTO LOW ORDER
BIT POSITION OF BCD
FIELD, AS LOWER TWO
BYTES OF BCD FIELD
ARE LEFT SHIFTED WITH
THE LOWER BYTE BEING
DECIMAL CORRECTED
MIDDLE BYTE OF BCD FIELD
NEED NOT BE DECIMAL CORRECTED, SINCE
MAX VALUE IS 2 (256)
DECREMENT AND TEST IF
CNTR EQUAL TO ZERO
INITIALIZE CNTR TO COVER
LOWER BINARY BYTE
PROGRAM LOOP TO
LEFT SHIFT A BIT
OUT OF LOWER BINARY
BYTE INTO LOW ORDER
BIT POSITION OF BCD
FIELD, AS BCD FIELD
IS LEFT SHIFTED WITH
THE LOWER TWO BYTES
OF THE FIELD BEING
DECIMAL CORRECTED
ADD (NOT ADC) HEX 66
TO SET UP "ADD" DCOR
DECIMAL CORRECT MIDDLE
BYTE OF BCD FIELD
UPPER BYTE OF BCD FIELD
NEED NOT BE DECIMAL
CORRECTED, SINCE MAX
VALUE IS 6 (65535)
DECREMENT AND TEST IF
CNTR EQUAL TO ZERO
RETURN FROM SUBROUTINE

2-56

VFBTOD-VERY FAST BINARY TO DECIMAL (PACKED
BCD)
Algorithm:

Decimal (Packed BCD) result is equal to
summation in BCD of powers of two
corresponding to 1's bits present in binary number.
Note that binary field (2 bytes) is initially
one's complemented by program, in order to facilitate bypass branching when
a tested bit in the binary field is found
equal to zero.

Binary in [1, 0]
BCD in [4, 3, 2]
189 Bytes
144 Instruction Cycles Average
208 Instruction Cycles Maximum

VFBTOD:

VFB1:

VFB2:

RC
LD
LD
AND
IFGT
ADD
LD
X
LD
LD
LD
LD
XOR
X
LD
XOR
X
IFBIT
JP
LD
LD
ADC
DCOR
X
LD
IFBIT
JP
LD
LD
ADC
DCOR
X
LD
!FBIT
JP
LD
LD
ADC
DCOR
X
CLR
ADC
X
LD

B.#O
A. [B]
A.#OF
A.#9
A.#6
B.#2
A. [B+]
[B+],#O
[B].#O
B.#l
A. [B]
A.#OFF
A. [B-]
A. [B]
A.#OFF
A. [B]
4. [B]
VFB1
B.#2
A.#07C
A. [Bj
A
A. [B]
B.#O
5. [B]
VFB2
B.#2
A.#098
A. [B]
A
A. [B]
B.#O
6. [B]
VFB3
B.#2
A.#OCA
A. [B]
A
A. [B+]
A
A. [B]
A. [B]
B.#O

EXTRACT LO NIBBLE
TEST NIBBLE 9
ADD 6 FOR CORRECTION
STORE IN LO BCD NIBBLE
CLEAR UPPER
BCD NIBBLES
COMPLEMENT HI BYTE
FOR REVERSE TESTING
OF BINARY NUMBER
COMPLEMENT LO BYTE
FOR REVERSE TESTING
TEST BINARY BIT 4
TO CONDITIONALLY
ADD BCD 16
16 + 66
ADD BCD 16

TEST BINARY BIT 5
TO CONDITIONALLY
ADD BCD 32
32 + 66
ADD BCD 32

TEST BINARY BIT 6
TO CONDITIONALLY
ADD BCD 64
64 + 66
ADD BCD 64

ADD CARRY

2-57

en
U')

VFB3:

c:t

IFBIT
JP
LD
LD
ADC
DCOR
X

LD
ADC
X

VFB4:

LD
IFBIT
JP
LD
LD
ADC
DCOR
X

LD
ADC
X

VFB5:

LD
IFBIT
JP
LD
LD
ADC
DCOR
X

LD
ADC
DCOR
X

VFB6:

LD
IFBIT
JP
LD
LD
ADC
DCOR
X

LD
ADC
DCOR
X

VFB7:

LD
IFBIT
JP
LD
LD
ADC
DCOR
X

LD
ADC
DCOR
X

7, [BJ
VFB4
B,#2
A,#08E
A, [BJ
A
A, [B+J
A,#l
A, [BJ
A, [BJ
B,#l
0, [BJ
VFB5
B,#2
A,#OBC
A, [BJ
A
A, [B+ J
A,#2
A, [BJ
A, [BJ
B,#l
1, [BJ
VFB6
B,#2
A,#078
A, [BJ
A
A, [B+ J
A,#06B
A, [BJ
A
A, [BJ
B,#l
2, [BJ
VFB7
B,#2
A,#08A
A, [BJ
A
A, [B+J
A,#076
A, [BJ
A
A, [BJ
B,#l
3, [BJ
VFB8
B,#2
A,#OAE
A, [BJ
A
A, [B+ J
A,#086
A, [BJ
A
A, [BJ
B,#l

TEST BINARY BIT 7
TO CONDITIONALLY
ADD BCD 128
28 + 66
ADD BCD 28

ADD BCD 1
HI BINARY BYTE
TEST BINARY BIT 8
TO CONDITIONALLY
ADD BCD 256
56 + 66
ADD BCD 56

ADD BCD 2
TEST BINARY BIT 9
TO CONDITIONALLY
ADD BCD 512
12 + 66
ADD BCD 12
5 + 66
ADD BCD 5

TEST BINARY BIT 10
TO CONDITIONALLY
ADD BCD 1024
24 + 66
ADD BCD 24
10 + 66
ADD BCD 10

TEST BINARY BIT 11
TO CONDITIONALLY
ADD BCD 2048
48 + 66
ADD BCD 48
20 + 66
ADD BCD 20

2-58

VFB8:

IFBIT
JP

LD
LD
ADC
DCOR
X

LD
ADC
DCOR
X

VFB9:

LD
IFBIT
JP

LD
LD
ADC
DCOR
X

LD
ADC
DCOR
X

CLR
ADC
X

VFB10:

LD
IFBIT
JP

LD
LD
ADC
DCOR
X

LD
ADC
DCOR
X

LD
ADC
X

VFBll :

LD
IFBIT
RET
LD
LD
ADC
DCOR
X

LD
ADC
DCOR
X

LD
ADC
X

4. [BJ
VFB9
B.#2
A.#OFC
A. [BJ
A
A. [B+J
A.#OA6
A. [BJ
A
A. [BJ
B.#l
5. [BJ
VFB10
B.#2
A.#OF8
A. [BJ
A
A. [B+J
A.#OE7
A. [BJ
A
A. [BJ
A
A. [BJ
A. [BJ
B.#l
6. [BJ
VFBll
B.#2
A.#OEA
A. [BJ
A
A. [B+J
A.#OC9
A. [BJ
A
A. [B+ J
A.#l
A. (is]
A. [BJ
B.#l
7. [BJ
B.#2
A.#OCE
A. [BJ
A
A. [B+ J
A.#08D
A. [BJ
A
A. [B+J
A.#3
A. [BJ
A. [BJ

TEST BINARY BIT 12
TO CONDITIONALLY
ADD BCD 4096
96 + 66
ADD BCD 96
40 + 66
ADD BCD 40

TEST BINARY BIT 13
TO CONDITIONALLY
ADD BCD 8192
92 + 66
ADD BCD 92
81 + 66
ADD BCD 81

ADD CARRY
TEST BINARY BIT 14
TO CONDITIONALLY
ADD BCD 16384
84 + 66
ADD BCD 84
63 + 66
ADD BCD 63

ADD .tWD

.I.

TEST BINARY BIT 15
TO CONDITIONALLY
ADD BCD 32768
68 + 66
ADD BCD 68
27 + 66
ADD BCD 27

ADD BCD 3

RET

2-59

»
Z

0,
CD

r---------------------------------------------------------------------~

Pulse Width Modulation
AID Conversion
Techniques with COP800
Family Microcontrollers

National Semiconductor
Application Note 607
Kevin Daugherty

1.0 BASIC TECHNIQUE

To minimize error, a tradeoff must be made when selecting
the resistor. The microcontroller output (L 1) should have a
large resistor to minimize the output switching offset (Vas)'
and the comparator should have a small resistor due to error caused by Ibos (input bias offset current).

This application note describes a technique for creating an
analog to digital converter using a microcontroller with other
low cost components. Many applications do not require the
speed associated with a dedicated hardware AID converter
and it is worth evaluating a more cost effective approach.
With a high speed CMOS microcontroller an eight bit AID
can be implemented that converts in approximately 10 ms.
This method is based on the fact that if a repetitive waveform is applied to an RC network, the capacitor will charge
to the average voltage, provided that the RC time constant
is much larger than the pulse widths. The basic equation for
computing the analog to digital result is:
Vin = Vref[Ton/(Ton + Toff)]
(1)
With this equation it is necessary to precisely measure several time periods within both the Ton and Toff in order to
achieve the desired resolution. Additionally, the waveform
would have to be gradually adjusted to allow for the large
RC time constant to settle out. This results in a relatively
long conversion cycle. Modifying the equation and technique slightly, significantly speeds up the process. This
technique works by averaging several pulses over a fixed
period of time and is based on the following equation:
Vin = Vref[Sum of Tani (Sum of (Ton

T off»]

(2)

Once the resistor is' determined, the capacitor should be
chosen so that the RC time constant is large enough to
provide a small incremental voltage ramp. This design has a
sample time of 20 fLs and has a 4.7 ms time constant with a
0.047 mfd film type capacitor which has low leakage current
to prevent errors. Since a 100k resistor is used in the RC
network for one comparator input, another 100k resistor is
required for the Vin input to balance the offset voltage
caused by the comparator Ib (input bias current).
Figure 2 illustrates the relationship between the microcontroller squarewave output and the capacitor charge and discharge. Every 20 fLs the comparator is sampled. If the capacitor voltage (Vd is below Vin the RC network will receive
a positive pulse. The inverse is true if Vc is above Vin at
sample time. Note that with this approach, the PWM waveform is broken up into several small pulses over a fixed
period instead of having a, single pulse represent the duty
cycle; thus a relatively small RC time constant can be used.

Mathematical Analysis:
let

n = total number of Ton pulses and

then

Vdt) = Vc + n[ (Vout - Vd (1 - e - tlRC)]
m[ (Vc - Va) (1 - e - tlRC)]

let

Vc = Vin at start of conversion and
K = (1 -

e -;-

then

Vin = Vin

2.0 IMPLEMENTATION

m = total number of Toff pulses

Figure 1 describes the basic circuit schematic that uses a
National Semiconductor COP822C microcontroller, a low
cost LM2901 comparator, two 100k resistors, and a
0.047 mfd film capacitor. The CMOS COP822C microcontroller provides a squarewave signal with logic levels very
close to GND and Vee. This generates a small ramp voltage
on the capacitor for the LM2901 quad comparator input.
+12V

Vin >-.....JW\r---I

KnVout

KmVo - KVin (n

KmVO

let
Vout = Vref - Vas
. solving for Vin:

100k

Vin = nVref/(n + m)
- (nVos -mV o) (1/(n

vee

l>-----1LO

(0 - 5)V

t/RC)

KnVout - KnVin ~ KmVin

COP822C

(3)

Note that the RC value drops out of the equation and therefore is not an error factor.

r-__~1~0~0~k--~~u~t~L1
Vc

VOLTS

~ 0.047mfd
C

20 .",

",4_7-,--......&.._1M
... CKO
CKI GND

Ton

Vo~~==~~~======-=~::--~--+
TIME
TL/DD/l0407-2

FIGURE 2. PWM Signal

TL/DD/l0407-1

FIGURE 1. Basic Circuit

2-60

conversions are started, the X register is initialized to 00 for
RAM location 00. The accumulator is then loaded with the
current RAM pointer (LD A,X), OR'ed with the LDATA
(OR A,LDATA), and finally the LDATA register is modified to
provide for the proper output select (X A,LDTA).

3.0 SOFTWARE DESCRIPTION
Single Channel

Referring to the flow chart in Figure 3, and the code listed in
Figure 4, the software counters Ton and TOTAL are first
pre loaded with the FF. The accumulator and register OF1
are then loaded with 2 to provide for an initialization and
final conversion cycle. Next, the L port is configured to complete the initialization of the microcontroller.

Following the actual conversion cycle, the result is stored at
the current RAM pointer (X A, [X + » which also auto-increments the X register. The next conversion will use this to
select the next channel and determine where to store the
result. Once the eighth channel is converted, the IFEQ A,X
instruction will be true and the RAM pointer will be reset
(LD X, # 00) before the next conversion is started.

The comparator output is checked with the IFBIT O,OD2 instruction. This will determine whether the RC network will
receive a positive (Vred or ground pulse. You can think of
the microcontroller as part of the feedback path of the comparator. The micro controller uses the comparator output to
decide what level output on L1 is required to keep the capacitor equal to the unknown input voltage. Each time the
negative or GND pulse is applied, the Ton counter is decremented by DRSZ. Similarly, each time a sample loop is
completed the TOTAL counter is decremented by DRSZ.
Note that NOP instructions are used in the high and low
loops. These are necessary to provide exactly the same
cycles for a high or low L1 output pulse.
Once the TOTAL register is decremented to zero, the initialization loop is completed. Immediately afterwards, the L1
output is put in TRI-STATE® mode to minimize capacitor
voltage variations while other instructions are completed.
After the first conversion, the IFEQ A,OF1 instruction will be
true and the Ton and TOTAL registers will be reloaded with
FF. Following this, the L1 pin is restored as a high output
and the OF1 multiplier is decremented.
At this point the capacitor is equal to Vin and the actual
conversion is started. When the TOTAL register is decremented to zero (255 samples later), the conversion is complete. Ton will not be reloaded since OF1 was decremented
and IFEQ A,OF1 will no longer be true. The accumulator is
then loaded with Ton and stored in RAM location 00 with
XA,OO.

CAPACITOR IS
INITIALIZED; RELOAD
TON a: TOTAL COUNTERS

The final two instructions (RBIT 1,LCONF & RBIT 1 [B» are
optional depending on the application and the amount of
additional code required. This will prevent the capacitor
from decaying appreciably between conversions and allow
for a much quicker capacitor initialization time. Otherwise
more time may be required, or a diode speed-up circuit as
shown in Figure 7d is required to fully charge the capacitor
prior to starting the actual conversion.

Eight Channel

This is bascially the same as that for the single channel.
Referring to the flow chart in Figure 5 and the code in Figure
6, the differences are in the front and back ends. Before the

TlIDD/10407-7

FIGURE 3. PWM AID Flow Chart

2-61

......
~

---------fL2
~-----------~---400

r----------4L3
L4

TLIDDI 10407-5

B. High Drive with Multiple Outputs
TLlDD/10407-4

A. Multiple Channels with LP339 Low Ibos Comparator
FIGURE 7. Suggested Circuits

2-65

.....
0

----------1 L3
'--J\~_----I

PWt.l

~ 0.04' mid '/0

TLlDD/10407-9

D. Eight Channel PWM AID Circuit
FIGURE 7. Suggested Circuits (Continued)
a maximum peak-peak ramp voltage of < 1 LSB of the desired accuracy. For example, if 8-bit accuracy is desired and
the instruction cycle time is now 4 fJ-s instead of 1 fJ-s, multiply 4.7 ms by 4 to calculate the new RC.

5.0 CONCLUSION
The PWM AID technique described in this application note
provides a relatively fast discrete implementation with substantial cost savings compared to a dedicated hardware
AID. Minimal microcontroller I/O and software is required to
interface with a comparator and RC network. Depending on
the application requirements, the designer can tailor the basic 8-bit AID a number of ways. By varying the total software counts, the desired speed and resolution can be adjusted. The number of AID channels will determine the
number of comparators used. In chosing the comparator, it
is recommended that the designer refer to the data sheets
and match the Ibos and Vos to the desired accuracy.
When other than a 1 fJ-s instruction cycle is used, the RC
time constant of 4.7 ms should be scaled to provide for

Keep in mind that the comparator input voltage is limited so
that you do not get erroneous/nonlinear results. Another
possible problem is during development. When doing
in-circuit emulation with the development equipment, note
that there will be ground loops in the cable thus causing
errors in your measurements. You can reduce this by connecting an extra GND and Vee wire between your prototype
and development system power and GND. It is still possible
to see offsets in the sockets holding the COP8XX in the
development board, however this should be relatively small.
The best test is to take accurate measurements with an
emulator in the actual prototype circuit.

2-66

National Semiconductor
Application Note 662
Ramesh Sivakolundu

COP800 Based Automated
SecurityIMonitoring
System
INTRODUCTION

SYSTEM OVERVIEW

National Semiconductor's COP800 family of full-feature,
cost effective, fully static, single chip micro CMOS microcontrollers provide efficient system solutions with a versatile
instruction set and high functionality. The heart of the ASM
System prototype is a COP800 family member with at least
the following features: 4k bytes of on-board program memory, 192 bytes of on-board data memory, memory mapped
I/O, fourteen multi-sourced vectored interrupts and a versatile instruction set. The family member used is the
COP888CG microcontroller.

Figure 1 gives the block diagram of the ASM System prototype hardware. The application consists of following major
blocks:

This application note describes the implementation of a Security/Monitoring System using the COP888CG microcontroller. The COP888CG contains features such as:
• Low power HALT and IDLE modes
• MICROWIRE/PLUSTM serial communication
• Multiple mUlti-mode general purpose timers
• Multi-input wakeup/interrupt
• WATCHDOGTM and Clock monitor
• Maskable vectored interrupt scheme
• UART
In addition to these features common to the COP888 subfamily of microcontrollers, COP888CG has a full duplex,
double buffered UART and two Differential Comparators.
The COP888CG based Automated Security/Monitoring
(ASM) System consists of several features:

• Central Controlling Unit
• Receiver
• Sensors and Transmitters
• Keypad Unit
• Auto-Dialer Unit
• Data Storage Unit
• Display Terminal Unit
• LED Display Unit
The implementation allows easy expansion of the ASM System features by adding new blocks to the Central Controlling Unit.
COP888CG is the workhorse of the ASM System and provides the processing power to scan the keypad, service the
Receiver interrupts, update the real time clock, serially communicate with the LED display unit and Data Storage Unit,
activate the Auto-Dialer Unit and use the full-duplex double
buffered UART to interface with the Display Terminal Unit.
System capabilities may be enhanced or scaled down by
simply changing the processor's algorithm. The subsequent
sections describe each of the units and their interface with
the COP888CG.

• Automatic Telephone Dialing
• Real Time Clock
• Non-Volatile storage of real time information of events
• Continuous display of events on the terminal
• Battery operated remote sensors and transmitters
• Exit and Entry delays
• Expandable to add new features

CENTRAL
CONSOLE
UNIT

TL/DD/l0607-1

FIGURE 1. Block Diagram of Security/Monitoring System

2-67

AN-662

~G1U:["

~~114 T, I

, II

1111

S.~~~~::H:;B(;au

+--4--.fl~ CK,

*lol#ID

I\)

:: :~

13 14
<>---':~_--H-H_'~4 15

D433
D3 32

D231

D1 30
DO 21

~~D5~
J:.-I-l 1111 -:::!::-

r:iI

718

121l
15

"17
17 LO

J'~w
~~'

"II

O.lpr

I !~ "[

.21
11

TOHEMI"

1;Jt;'TOGGLE
SWITCH

~ •. ""F

~
O.OtlA r

TLIDD/10607-2

FIGURE 2. Schematic of the ASM System Prototype

HARDWARE DESCRIPTION

TP5088 is a low cost CMOS device that provides the tonedialing capability in microprocessor-controlled telephone
applications. TP5700A is a linear bipolar device which includes the functions required to build the speech circuit of a
telephone. It replaces the hybrid transformer, compensation
circuit and sidetone network used traditional designs.

This section describes the various blocks in the ASM System briefly and highlights the hardware considerations in the
design of the System.

Receiver Unit
The Receiver Unit operates with the Sensors and Transmitter Unit. An eight-key dip switch makes it possible to select
256 different digital codes. A detector LED indicates the
level of the radio frequency (RF) energy detected by the
receiver and enables the user to determine the best locations. for the transmitter(s) and receiver, assuring reliable
operation.

Data Storage Unit
The Data Storage Unit stores the real time data of events
that the Receiver Unit detects and informs the Central Controlling Unit. The storage is non-volatile and can be archived
for later references. The Terminal Unit can request the Central Controlling Unit to display the events and the data
stored in the Storage Unit. The telephone number to be
dialed by the Auto-Dialer Unit is also stored in this unit. This
unit interfaces with the COP888CG using the MICROWIRE/
PLUSTM serial communication protocol.

Figure 2 shows the interface between the COP888CG and
the Receiver Unit on the bi-directionalllO Port L capable of
functioning as Multi-Input WakeUp (MIWU). In this implementation the WR-200 series of receivers manufactured by
Visonic Ltd was used. These receivers are designed to operate with Visonic standard transmitters. The receiver operates on 12 VDC. When RF signal from the transmitter(s) is
detected, the receiver activates a relay which in turn interrupts the microcontroller. The output of the relay is connected to the Port L of the COP888CG whose alternate function
includes, the Multi-Input WakeUp feature. The COP888CG,
after a time delay of 10 seconds, activates the Auto-Dialer
Unit. The microcontroller turns on a LED to indicate an
alarm signal was.detected and is being processed.

In this implementation the COP888CG microcontroller interfaces with NM93C06A Serial EEPROM Memory. The
NM93C06A contains 256 bits of read/write EEPROM organized as 16 registers of 16 bits each. Written information
has a retention period of at least 10 years. Figure 2 shows
the interface between. COP888CG and NMC9306.
Any sequentially accessible memory device that is compatible with the MICROWIRE/PLUSTM serial communication
protocol can be used as a Data Storage Unit. The Central
Controlling Unit checks for the availability of memory and
informs the user of the same if memory is full. Upon receipt
of memory full prompt, the user can .decide to overwrite or
replace the memory device.

Sensors and Transmitters
This unit has a built-in reed switch which can be used with a
magnet to. activate the transmitter. An eight-key dip switch
forms the code selector and each key can be set to either
ON or OFF position to create a unique code. This code
should match with the code selected on the receiver unit.

Display Terminal Unit
The Display Terminal Unit interfaces with the COP888CG
through the. full-duplex, double buffered· UART. The
COP888CG is interrupted by the terminal and the microcontroller decodes the ASCII character sent and services the
corresponding request. The terminal keyboard can be used
to program the telephone number to be dialed by the AutoDialer Unit. The real time clock is displayed on the terminal
screen. Ihe user can request tne Central. Controlling Unit to
display the history of events monitored by the AMS System.
The Central Controlling Unit retrieves the information from
the Date Storage Unit and displays it on the screen.

Model WR-100 Universal Wireless Transmitter, manufactured by Visonic Ltd. was used in the implementation of the
Security /Monitoring System.

Keypad Unit
Til~

iZtjYjJc1U Ullii GUII:;i:;i:; UI 4 x 4 lIlatrix keyboard. Ine
Figure 2 shows the keyboard matrix interface to
COP888CG. The keyboard is scanned periodically by ad~
dressing a column in the keyboard matrix. The program senses the key closure in that column by testing the Port I lines
(10 to 13) which are connected to the rows of the keyboard
matrix. Thus, each key is associated with the conjunction of
one Port D output line and one Port I input line only.

The ASM System utilized a Visual 550 terminal. The terminal employs two independent display memories: alphanumerics and graphics. The alphanumeric functions of the
V550 is ANSI X3.64 compatible and the graphics functions
are fully compatible with Tectronix Plot 10® software.

The keypad unit is used to program the real time clock in
order to set the time and date. The telephone number to be
dialed in case of a security breach can also be programmed
through the keypad as well as the terminal keyboard in the
Terminal Unit.

With slight modification of the Central Controlling Unit's algorithm it is possible to make the ASM System interface
with any other terminal unit.

LED Display Unit

Auto-Dialer Unit
The Auto-Dialer Unit dials the number programmed by the
user upon detection ofRF signal by the Receiver from the
Sensors and Transmitter Unit. The unit consists of two ICs
and some peripheral circuitry. National Semiconductor's
TP5700A is the Telephone Speech Circuit and TP5088 is
the DTMF generator. These two chips are interfaced to the
COP888CG as in Figure 2. The COP888CG outputs the digit
to be dialed to TP5088 and the output of the DTMF generator is inputted to the Speech Circuit. The Speech Circuit
interfaces with the telephone lines.

The LED Display Unit is used to display the time and date
information. Figure 2 shows the interface between
COP888CG and the Display Terminal Unit. The COP888CG
communicates with this unit serially using the MICROWIRE/
PLUS protocol.
The NSM4000A LED Display with Driver is used in the ASM
System. The NSM4000A is a 4-digit 0.3" height LED display
with serial data-in parallel data-out LED driver designed to
operate with minimal interface to the data source. The Cen-

2-69

CD
CD

Descending Whistle
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78

0104 BDEE6C
0107 BDF075
010A 06
010B 9DFO
OlOD 8A
OlOE 9CFO
0110 8D
0111 DOOO
0113 DEEC
0115 AE
0116 92FF
0118 03
0119 8A
011A A6
011B 8D
011C 9DFD
011E 9402
0120 9CFD
0122 8E

TIMOUT: RBIT
IFBIT
JP
LD
INC
X

TM:

RETSK
LD
LD
LD
IFEQ
JP
INC
X

DONE:

(Continued)

RETSK
LD
ADD
X

TRUN,CNTRL
5,FCNTR
TM
A,FCNTR
A
A,FCNTR

STOP THE TIMER
COUNT CYCLES

FCNTR,#FCNT
B,#TAULO
A, [B]
A,#MINFREQ
DONE
A
A, [B]

RESET COUNT

A,SP
A,#002
A,SP

*** RESTORE STACK POINTER ***
*** AND RETURN TO CALLING ***
*** ROUTINE.
***

RET
.END

2~79

INCREMENT COUNT

CHANGE FREQUENCY
TIMER
MIN FREQ?
YES

STORE FREQ IN AUTO RELOAD

en
w

C")

Ascending Whistle

(Continued)

0,
0)

53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78

**** INTERRUPT ROUTINE ****
OOFF
0102
0103
0104
0107
010A
OlOB
010D
OlOE
0110
0111
0113
0115
0117
0118
011A
011C
011D
011F
0121
0123

OOFF
BDEF75
01
FF
BDEE6C
BDF075
06
9DFO
8A
9CFO
8D
DOlO
9DEC
920A
05
94FF
9CEC
8D
9DFD
9402
9CFD
8E

TIMOUT:

.=OFF
IFBIT
JP
JP
RBIT
IFBIT
JP
LD
INC
X

TM:

RETSK
LD
LD
IFEQ
JP
ADD
X

DONE:

RETSK
LD
ADD
X

TPND,PSW
TIMOUT

TEST TIMER PENDING FLAG

TRUN,CNTRL
5,FCNTR
TM
A,FCNTR
A
A,FCNTR

; STOP THE TIMER
FREQUENCY TIMED OUT?
YES, CHANGE FREQUENCY
NO, KEEP GOING
INCREMENT COUNT

FCNTR,#FCNT
A,TAULO
A,#MAXFREQ
DONE
A,#OFF
A,TAULO

;
;
;
;

RETURN
RESET COUNTER
CHANGE FREQUENCY
TIMER = MAX FREQUENCY
YES
INCREMENT FREQUENCY
STORE FREQ IN AUTO RELOAD

*** RESTORE STACK POINTER ***
*** AND RETURN TO CALLING ***
*** ROUTINE.
***

A,SP
A,#002
A,SP

RET
.END

2-81

Laser Gun

(Continued)

0')

113
114
115
116
117
118
119
120
121
122
123
124
125
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128
129
130
131
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138
139
140
141
142
143
144
145
146

004F
0050
0051
0052

C9
FO
AE
E5

TSTLUP: DRSZ
JP
LD
JP

LUPREG
RING
A, [BJ
SHIFT

EXTRACT THIS # ?
NO, KEEP ROTATING
YES

**** TIMER INTERRUPT ROUTINE ****
OOFF
0102
0103

OOFF
BDEF75
01
FF

0104
0107
0109
010A
010B
010C
010F
0112
0113
0116
0117
0118
0119
011B
011D
011F
0120
0121
0123
0124
0126

BDEE6C
DEFA
C8
01
OB
BDEF7C
BDEF6D
5D
BDEE7C
8F
C7
07
9DFD
9402
9CFD
8E
AE
9404
A6
D820
E5

IFBIT
JP
JP
TMOUT:

NXT:

NEWF:
NLST:

NF:

RBIT
LD
DRSZ
JP
JP
SBIT
RBIT
LD
SBIT
RETI
DRSZ
JP
LD
ADD
X
RET
LD
ADD
X
LD
JP
.END

OFF
TPND,PSW
TMOUT

; TEST TIMER PND FLAG
; ERROR

TRUN,CNTRL
B,#LUPCNT
TCNTR
NXT
NEWF
4,PSW
5,PSW
B,#RNGVAL
TRUN,CNTRL
EXITR
NF
A,SP
A,#002
A,SP
A, [BJ
A,#04
A, [BJ
TCNTR,#TCNT
NXT

2-97

STOP TIMER
TEST FOR NEW TONE
NO
;
;
;
;
;

ENABLE TIMER INTERRUPT
RESET TPND FLAG
POINT TO RANDOM #
RESTART TIMER
RETURN
EXIT COUNT
0
NO
*** RESTORE STACK POINTER ***
*** FROM TIMER INTERRUPT ***
*** AND RETURN TO MAIN
***

NEW TONE
INCR EXTRACTION VALUE
REINITIALIZE TONE TIME

CD
CD
CD

National Semiconductor
Application Note 666
Verne H. Wilson

DTMF Generation with a
« 3.58 MHz Crystal
z

697 Hz, 770 Hz, 852 Hz, and 941 Hz, while the high band
frequencies are 1209 Hz, 1336 Hz, 1477 Hz, and 1633 Hz.
The DTMF keyboard input decode subroutine assumes that
the keyboard is encoded in a low true row/column format,
where the keyboard is strobed sequentially with four low
true column selects with each returning a low true row select. The low true column and row selects are encoded in
the upper and lower nibbles respectively of the accumulator,
which serves as the input to the DTMF keyboard input decode subroutine. The subroutine will then generate the
DTMF hexadecimal digit associated with the DTMF keyboard input digit.

DTMF (Dual Tone Multiple Frequency) is associated with
digital telephony, and provides two selected output frequencies (one high band, one low band) for a duration of 100 ms.
DTMF generation consists of selecting and combining two
audio tone frequencies associated with the rows (low band
frequency) and columns (high band frequency) of a pushbutton touch tone telephone keypad.
This application note outlines two different methods of
DTMF generation using a COP820C/840C microcontroller
clocked with a 3.58 MHz crystal in the divide by 10 mode.
This yields an instruction cycle time of 2.79 I1-s. The application note also provides a low true row/column decoder for
the DTMF keyboard.

The DTMF keyboard decode subroutine (KBRDEC) utilizes
a common ROM table lookup for each of the two nibbles
representing the low true column and row encodings for the
keyboard. The only legal low true nibbles for a single key
input are E, 0, B, and 7. All other low true nibble values
represent multiple keys, no key, or no column strobe. Results from two legal nibble table lookups (from the same 16
byte ROM table) are combined to form a hex digit with the
binary format of OOOORRCC, where RR represents the four
row values and CC represents the four column values. The
illegal nibbles are trapped, and the subroutine is exited with
a RET (return) command to indicate multiple keys or no key.
A pair of legal nibble table lookups result in the subroutine
being exited with a RETSK (return and skip) command to
indicate a single key input. This KBRDEC subroutine uses
35 bytes of code, consisting of 19 bytes of program code
and 16 bytes of ROM table.

The first method of DTMF generation provides two PWM
(Pulse Width Modulation) outputs on pins G3 and G2 of the
G port for 100 ms. These two PWM outputs represent the
selected high band and low band frequencies respectively,
and must be combined externally with an LM324 op amp or
equivalent feed back circuit to produce the DTMF signal.
The second method of DTMF generation uses ROM lookup
tables to simulate the two selected DTMF frequencies.
These table lookup values for the selected high band and
low band frequencies are then combined arithmetically. The
high band frequencies contain a higher bias value to compensate for the DTMF requirement that the high band frequency component be 2 dB above the low band frequency
component to compensate for losses in transmission. The
resultant value from the arithmetic combination of sine wave
values is output on L port pins LO to L5, and must be combined externally with a six input resistor ladder network to
produce the DTMF signal. This resultant value is updated
every 11811-s. The COP820C/840C timer is used to time out
the 100 ms duration of the DTMF. A timer interrupt at the
end of the 100 ms is used to terminate the DTMF output.
The external ladder network need not contain any active
components, unlike the first method of DTMF generation
with the two PWM outputs into the LM324 op amp.

DTMF GENERATION USING PWM AND AN OP AMP

The associated COP820C/840C program for the DTMF
generation is organized as three subroutines. The first subroutine (KBRDEC) converts the low true column/row input
from the DTMF keyboard into the associated DTMF hexadecimal digit. In turn, this hex digit provides the input for the
other two subroutines (DTMFGP and DTMFLP), which represent the two different methods of DTMF generation.
These three subroutines contain 35, 94, and 301 bytes of
COP820C/840C code respectively, including all associated
ROM tables. The Program Code/ROM table breakdowns
are 19/16, 78/16, and 88/213 bytes respectively.
DTMF KEYBOARD MATRIX

The matrix for selecting the high and low band frequencies
associated with each key is shown in Figure 1. Each key is
uniquely referenced by selecting one of the four low band
frequencies associated with the matrix rows, coupled with
selecting one of the four high band frequencies associated
with the matrix columns. The low band frequencies are

The first DTMF generation method (using the DTMFGP subroutine) generates the selected high band and low band
frequencies as PWM (Pulse Width Modulation) outputs on
pins G3 and G2 respectively of the G port. The COP820C/
840C microcontrollers each contain only one timer, and
three times must be generated to satisfy the DTMF application. These three times are the half periods of the two selected frequencies and the 100 ms duration period. Obviously the single timer can only generate one of the required
times, while the program must generate the two remaining
times. The solution lies in dividing the 100 ms duration time
by the half periods for each of the eight DTMF frequencies,
and then examining the respective high band and low band
quotients and remainders. Naturally these divisions must be
normalized to the instruction cycle time (te). 100 ms represents 35796 te's. The results of these divisions are detailed
in Table I.
The four high band frequencies are produced by running the
COP820C/840C timer in PWM (Pulse Width Modulation)
mode, while the program produces the four low band frequencies and the 100 ms duration timeout. The programmed times are achieved by using three programmed
register counters RO, R2 and R3, with a backup register R1
to reload the counter RO. These three counters represent
the half period, the 100 ms quotient, and the 100 ms remainder associated with each of the four low band frequencies.

2-98

1633

:iv»
mo 1477
r5~ 1336~
:i:
1209

:iv»

mB
~e:

697- 1

770- 4

0)
0)

I
3

852- 7

941-

....I

R
0
W
S

COLUMNS

TL/DD/l0740-22

FIGURE 1. DTMF Keyboard Matrix

TABLE I. Frequency Half Periods, Quotients and Remainders

Low Band Frequencies

High Band Frequencies

Freq.
Hz

Half
Period
In /-Ls

Half
Period
Inte's

Quotient

697

717.36

257

139

770

649.35

232

154

852

586.85

210

170

941

531.35

190

188

1209

413.56

148

241

128

1336

374.25

134

267

1477

338.53

121

295

101

1633

306.18

110

325

Note: 100 ms represents 35796 !c's.

2-99

100 ms/O.5P
Inte's
Remainder

CD
CD
CD

Program

LUP1:

BYP1:

BYP2:

LUP2:

LD
LD

B,#PORTGD
X,#R1

LD
IFBIT
JP
X
SBIT
JP
NOP
RBIT
X
DRSZ
JP
JP
DRSZ
JP

A,[X-]
2,[B]
BYP1
A,[X+]
2,[B]
BYP2

LD
IFEQ
JP
NOP
NOP
IFEQ
JP
LAID
NOP
JP

A,[X]
,I\, f'31
LUP1

the selected low band frequency. Furthermore, the toggling
of the G2 output bit (achieved with either a set or reset bit
instruction) must also be exactly time balanced to maintain
the half period time integrity. Local stall loops (consisting of
a DRSZ instruction followed by a JP jump back to the DRSZ
for a two byte, six instruction cycle loop) are embedded in
both the half period and remainder loops. Consequently, the
ROM table parameters for the half period and remainder
counters are approximately only one-sixth of what otherwise
might be expected. The program for the half period loop,
along with the detailed time balancing of the loop for each
of the low band frequencies, is shown in Figure 2.

Bytes!
Cycles
2/3
2/3
1/3
1/1
1/3
1/3
1/1
1/3
1/1
1/1
1/3
1/3
1/3
1/3
1/3
1/3

2,[B]
A,[X+]
R2
LUP2
FINI
RO
LUP2

1/3
'2./'2.
1/3
1/1
1/1
2/2
1/3
1/3
1/1
1/3

A,#38
LUP1

LUP1

Table III
Frequency
[(38 - 1)
[(33 - 1)
[(31 - 1)
[(26 - 1)

Stall
Loop
x 6]
x 6]
x 6]
x 6]

Conditional
Cycles

Total
Cycles

3
3
3
3

3
3
3
3
3

3
1
3
'2.
3

2
3
3
1
3

Total
Cycles
+ 35
+ 40
+ 30
+ 40

Half
Period
= 257
= 232
= 210
= 190

FIGURE 2. Time Balancing for Half Period Loop

2-101

Cycles

enen

CD
CD
CD

TABLE IV. Time Balancing for Remainder Loop

:2:
<

Table III
Remainder
[(10 - 1)
[( 9 - 1)
[(14 - 1)
[(10 - 1)

RLoop
Overhead
+ 20
+ 20
+ 20
+ 20

Stall
Loop
x 6]
x 6]
x 6]
x 6]

The selected high band frequency is achieved by loading
the half period count in te's minus one (from Table III) into
the timer auto reload register and running the timer in PWM
output mode. The minus one is necessary since the timer
toggles the G3 output bit when it underflows (counts down
through zero), at which time the contents of the autoreload
register are transferred into the timer.
In summary, the input digit from the keyboard (encoded in
low true column/row format) is translated into a digit matrix
vector XXXXRRCC which is checked for 1001RRCC to indicate a single key entry. No key or multiple key entries will
set a flag and terminate the DTMF subroutine. The digit
matrix vector for a single key is transformed into the core
vector OOOORRCC. The core vector is then translated into
four other vectors (T, F, Q, R) which in turn are used to
select four parameters from a 16 byte ROM table. These
four parameters are used to load the timer, and the respective half period, quotient, and remainder counters. The 16
byte ROM table must be located starting at ROM location
0030 (or OX30) in order to minimize program size, and has
reference setups with the "OR A, # 033" instruction for the F
vector and the "OR A,#030" instruction for the T vector.

The timer is initialized to a count of 15 so that the first timer
underflow and toggling of the G3 output bit (with timer PWM
mode and G3 toggle output selected) will occur at the same
time as the first toggling of the G2 output bit. The half period
counts for the high band frequencies minus one are stored
in the timer section of the ROM table. The selected value
from this frequency ROM table is stored in the timer autoreload register. The timer is selected for PWM output mode
and started with the instruction lD [8],#080 where the 8
pointer is selecting the CNTRl register at memory location
OEE.
This first DTMF generation subroutine for the COP820C/
840C uses 94 bytes of code, consisting of 78 bytes of program code and 16 bytes of ROM table. A program test routine to sequentially call the DTMFGP subroutine for each of
the 16 keyboard input digits is supplied with the listing for
the DTMF35 program. This test routine uses a 16 byte ROM
table to supply the low true encoded column/row keyboard
input to the accumulator. An input from the 10 input pin of
the I port is used to select which DTMF generation subroutine is to be used. The DTMFGP subroutine is selected with
10 = o.
A TYPICAL OP AMP CONFIGURATION FOR MIXING THE
TWO DTMF PWM OUTPUTS IS SHOWN IN FIGURE 3.

The three parameters associated with the two R bits of the
core vector require a mUlti-level table lookup capability with
the LAID instruction. This is achieved with the following section of code in the DTMF subroutine:

LD
X

LD
LAID
X

DEC

B,#Rl
A,[B]
A,[B,]
A, [B+]

IFBNE

LUP

D:::~ -1

DTI.4F2
HI BAND

-1

:IL

Table I
Remainder
73
68
96
76

This program loads the F frequency vector into R1, and then
decrements the vector each time around the loop. The vector is successively moved with the exchange commands
from R1 to R2 to R3 as one of the same exchange commands loads the data from the ROM table into R1, R2, and
R3. This successive decrementation of the F vector changes the F vector into the Q vector, and then changes the Q
vector into the R vector. These vectors are used to access
the ROM table with the LAID instruction. The 8 pointer is
incremented each time around the loop after it has been
used to store away the three selected ROM table parameters (one per loop). These three parameters are stored in
sequential RAM locations R1, R2, and R3. The IF8NE test
instruction is used to skip out of the loop once the three
selected ROM table parameters have been accessed and
stored away.

Note that the Q value in Table III is one greater than the
quotient in Table I to compensate for the fact that the quotient count down to zero test is performed early in the half
period loop. The overhead in the remainder loop is 20 instruction cycles. The detailed time balancing for the remainder loop is shown in Table IV.

LUP:

Total
Cycles
= 74
= 68
= 98
= 74

10Ok
•

47k

•

• DIFFERENT VALUES TO COMPENSATE
FOR 2 dB OFFSET
....

1t-1..JV'.i'Y-~~~ftv--------.

.~f-

2 PWM Outputs:
1 High Band
1 Low Band

.........w"'~"'....-ILM

324

DTt.CF OUT

TL/00/10740-23

FIGURE 3. Typical Op Amp Configuration for Mixing DTMF PWM Outputs
2-102

values from the selected low band and high band sine wave
frequency tables in the ROM. The ROM table offset frequency pointers (LFPTR and HFPTR) must increment each
time and then wrap around from top to bottom of the two
selected ROM tables. The ROM table size parameters
(LFTBSZ and HFTBSZ) for the selected frequencies are
tested during each LUP42 to determine if the wrap around
from ROM table top to bottom is necessary. The wrap
around is implemented by clearing the frequency pointer in
question. Note that the ROM tables are mapped from a reference of 0 to table size minus one, so that the table size is
used in a direct comparison with the frequency offset pointer to test for the need for a wrap around. Also note that the
offset pointer incremented value is used during the following
LUP42 cycle, while the pre-incremented value of the pointer
is used during the current cycle. However, it is the incremented value that is tested versus the table size for the
need to wrap around.

DTMF GENERATION USING A RESISTOR LADDER
NETWORK
The second DTMF generation method (using the DTMFLP
subroutine) generates and combines values from two table
lookups simulating the two selected sine waves. The high
band frequency table values have a higher base line value
(16 versus 13) than the low band frequency table values.
This higher bias for the high frequency values is necessary
to satisfy the DTMF requirement that the high band DTMF
frequencies need a value 2 dB greater than the low band
DTMF frequencies to compensate for losses in transmission.
The resultant value from arithmetically combining the table
lookup low band and high band frequency values is output
on pins LO to L5 of the L port in order to feed into a six input
external resistor ladder network. The resultant value is updated every 117% J-I-s (one cycle of the LUP42 program
loop). The LUP42 program loop contains 42 instruction cycles (tc's) of 2.7936511 J-I-s each for a total loop time of
117% J-I-s. The COP820C/840C timer is used to count out
the 100 ms DTMF duration time.

>
z

C')
C')

After the low band and high band ROM table sine wave
frequency values are accessed in each cycle of the LUP42
program, they are added together and then output to pins
LO-L5 of the L port. As stated previously, the low band
frequency values have a lower bias than the high band frequency values to compensate for the required 2 dB offset.
Specifically, the base line and maximum values for the low
frequency values are 13 and 26 respectively, while the base
line and maximum values for the high frequency values are
16 and 32 respectively. Thus the combined base line value
is 29, while the combined maximum value is 58. This gives a
range of values on the L port output (LO-L5) from 0 to 58.

An interrupt from the timer terminates the 100 ms DTMF
output. Note that the Stack Pointer (SP) must be adjusted
following the timer interrupt before returning from the
DTMFLP subroutine.
The DTMFLP subroutine starts by quadrupling the value of
the DTMF hex digit value in the accumulator, and then adding an offset value to reach the first value in the telephone
key table. The telephone key ROM table contains four values associated with each of the 16 DTMF hex keys. These
four values represent the low and high frequency table sizes
and table starting addresses associated with the pair of frequencies (one low band, one high band) associated with
each DTMF key. The FRLUP section of the program loads
the four associated telephone key table values from the
ROM table into the registers LFTBSZ (Low Freq Table
Size), LFTADR (Low Freq Table Address), HFTBSZ (High
Freq Table Size), and HFTADR (High Freq Table Address).
Th~ proGram th~n !n!t!a!l~~s the t!mer and autcre!c:!d regl!Oter, starts the timer, and then jumps to LUP42. Note that the
timer value in tc's is 100 ms plus one LUP42 time, since the
initial DTMF output is not until the end of the LUP42 program.

The minimum time necessary for the LUP42 update program loop is 36 instruction cycles including the jump back to
the start of the loop. Consequently, two LAID instructions
are inserted just prior to the jump back instruction at the end
of LUP42 to supply the six extra Nap instruction cycles
needed to increase the LUP42 instruction cycles from 36 to
42. A three cycle LAID instruction can always be used to
simulate three single cycle Nap instructions if the accumulator data is not needed.
Table V shows the multiple LUP42 approximation to the
eight DTMF frequencies, including the number of sine wave
cycles and data points in the approximation. As an example,
three cycles of a sine wave with a total of 19 data points
across the three cycles is used to approximate the 1336 Hz
DTMF frequency. The 19 cycles of LUP42 times the LUP42
time of 117% J-I-s is divided into the three cycles to yield a
value of 1345.69 Hz. This gives an error of +0.73% when
compared with the DTMF value of 1336 Hz. This is well
within the 1.5% North American DTMF error range.

Multiples of the magic number 118 J-I-s (approximately) are
close approximations to all eight of the DTMF frequencies.
The LUP42 program uses 42 instruction cycles (of
2.7936511 J-I-s each) to yield a LUP42 time of 117% J-I-s. The
purpose of the LUP42 program is to update the six L port
outputs by accessing and then combining the next set of

TABLE V. DTMF Frequency Approximation Table
DTMF
Freq.
697
770
852
941
1209
1336
1477
1633

# of Sine

# of Data

Wave Cycles
4

Points
49
11
10
9
7
19
23
21

3
4

Calculation
4/(49 x 117%)
1/(11 x 117%)
1/(10x117%)
1/(9x117%)
1/(7x117%)
3/(19x 117%)
4/(23 x 117%)
4/(21 x 117%)

2-103

Approx.
Freq.
= 695.73
= 774.79
= 852.27
= 946.97
= 1217.53
= 1345.69
= 1482.21
= 1623.38

% Error

-0.18
+0.62
+0.03
+0.63
+0.71
+0.73
+0.35
-0.59

~
~

zc:r:

r-------------------------------------------------------------------------------~

table is equal to 196. The surrounding rectangle for the
three cycles of sine wave is 19 by 16 for a total area of 304.
The ratio of 196/304 is 64.47% compared with the 2/rr
ratio of 63.66%. Thus the sine wave approximation gives an
area abundance of 0.81 % (equal to 64.47 - 63.66).

The frequency approximation is equal to the number of cycles of sine wave divided by the time in the total number of
LUP42 cycles before the ROM table repeats.
The values in the DTMF sine wave ROM tables are calculated by computing the sine value at the appropriate points,
scaling the sine value up to the base line value, and then
adding the result to the base line value. The following example will help to clarify this calculation.

An application of the sine wave area criteria is shown in the
generation of the DTMF 852 Hz frequency. The ten sine
values calculated are 0,7.64,12.36,12.36,7.64,0, -7.64,
-12.36, -12.36, and -7.64. Rounding off to the nearest
integer yields values of 0, 8, 12, 12, 8, 0, - 8, -12, -12
and -8. The total of these values (absolute numbers) is 80,
while the area of the surrounding rectangle is 130 (10 x 13).
The ratio of 80/130 is 61.54% compared with the 2/rr ratio
of 63.66%. Thus the sine wave approximation gives an area
deficiency of 2.12% (equal to 63.66 - 61.54), which is overly deficient. Consequently, two of the ten sine values are
augmented to yield sine values of 0, 8, 12, 13*, 8, 0, -8,
-12, -13 *, and - 8. This gives an absolute total of 82 and
a ratio of 82/130, which equals 63.08% and serves as a
much better approximation to the 2/rr ratio of 63.66%.
The sine wave area criteria is also used to modify two values in the DTMF 941 Hz frequency. The nine sine values
calculated are 0, 8.36, 12.80, 11.26, 4.45, - 4.45, -11.26,
-12.80, and - 8.36. Rounding off to the nearest integer
yields values of 0,8,13,11,4, -4, -11, -13, and -8. The
total of these values (absolute numbers) is 72, while the
area of the surrounding rectangle is 117 (9 x 13). The ratio
of 72/117 is 61.54% compared to the 2/rr ratio of 63.66%.
Thus the sine wave approximation gives an area deficiency
of 2.12% (equal to 63.66 - 61.54),which is overly deficient.
Rounding up the two values of 4.45 and - 4.45 to 5 and - 5,
rather than down to 4 and - 4, yields values of 0, 8, 13, 11,
5, - 5, -11, -13 and - 8. This gives an absolute total of
74 and a ratio of 74/117, which equals 63.25% and serves
as a much better approximation to the 2/rr ratio of 63.66%.

Consider the three cycles of sine wave across 19 data
points for the 1336 Hz high band frequency. The first value
in the table is the base line value of 16. With 2rr radians per
sine wave cycle, the succeeding values in the table represent the sine values of 1 x (6rr/19), 2X (6rr/19), 3 x
(6rr/19), ... , up to 18 X (6rr/19). Consider the seventh
and eighth values in the table, representing the sine values
of 6 x (6rr/19) and 7 x (6rr/19) respectively. The respective calculatons of 16 x sin[6 x (6rr/19)1 and 16 x sin[7
x (6rr/19)1 yield values of -5.20 and 9.83. Rounding to
the nearest integer gives values of - 5 and 10. When added
to the base line value of 16, these values yield the results 11
and 26 for the seventh and eighth values in the 1336 Hz
DTMF ROM table. Symmetry in the loop of 19 values in the
DTMF table dictates that the fourteenth and thirteenth values in the table are 21 and 6, representing values of 5 and
-10 from the calculations.
The area under a half cycle of sine wave relative to the area
of the surrounding rectangle is 2/rr, where rr radians represent the sine wave half cycle. This surrounding rectangle
has a length of rr and a height of 1, with the height representing the maximum sine value. Consequently, the area of
the surrounding rectangle is rr. The integral of the area under the half sine wave from 0 to rr is equal to 2. The ratio of
2/rr is equal to 63.66%, so that the total of the values for
each half sine wave should approximate 63.66% of the sum
of the max values. The maximum values (relative to the
base line) are 13 and 16 respectively for the low and high
band DTMF frequencies.

With these modified values for the 852 and 941 DTMF frequencies, the area criteria ratio of 2/rr = 63.66% for the
sine wave compared to the surrounding rectangle has the
following values:

For the previous 1336 Hz example, the total of the absolute
values for the 19 sine values from the 1336 Hz ROM
DTMF
Freq.
697 Hz
770Hz
852 Hz
941 Hz
1209 Hz
1336 Hz
1477 Hz
1633 Hz

Sum of
Values
406
92
82
74
72
196
232
216

Rectangle
Area
49x 13 = 637
1.1 x 13 = 143
10 x 13 = 130
9x13=117
7x16=112
19 x 16 = 304
23 x 16 = 368
21 x 16 = 336

2-104

Percentage

Diff.

63.74%
64.34%
63.08%
63.25%
64.29%
64.47%
63.04%
64.29%

+0.08%
+0.68%·
-0.58%
-0.41%
+0.63%
+0.81%
-0.62%
+0.63%

l>
The LUP42 program loop is interrupted by the COP820C/
840C timer after 100 ms of DTMF output. As stated previously, the Stack Pointer (SP) must be adjusted (incremented
by 2) following the timer interrupt before returning from the
DTMFLP subroutine.

In summary, the DTMF35 program assumes a COP820C/
840C clocked with a 3.58 MHz crystal in divide by 10 mode.
The DTMF35 program contains three subroutines,
KBRDEC, DTMFGP, and DTMFLP. The KBRDEC subroutine is a low true DTMF keyboard decoder, while the
DTMFGP and DTMFLP subroutines represent the alternative methods of DTMF generation.

This second DTMF generation subroutine for the
COP820C/840C uses 301 bytes of code, consisting of 88
bytes of program code and 213 bytes of ROM table. The
following is a summary of the DTMFLP subroutine code allocation.
DTMFLPCode
Allocation
1. Subroutine Header Code
2. Interrupt Code
3. LUP42 Code
4. Telephone Key Table
5. Sine Value Tables

SUMMARY

The KBRDEC subroutine provides a low true decoding of
the DTMF keyboard input and assumes that the keyboard
input has been encoded in a low true column/row format,
with the columns of the keyboard being sequentially
strobed.
The DTMFGP subroutine produces two PWM (Pulse Width
Modulation) outputs (representing the selected high and low
band DTMF frequencies) for combination with an external
op amp network (LM324 or equivalent).

# of
Bytes
42
16
30
64
149

The DTMFLP subroutine produces six bits of combined high
band and low band DTMF frequency output for combination
in an external resistor ladder network. This output represents a combined sine wave simulation of the two selected
DTMF frequencies by combining values from two selected
ROM tables, and updating these values every 118 ""s.
The three DTMF35 subroutines contain the following number of bytes of program and ROM table memory:

Total
301
A program test routine to sequentially call the DTMFLP subroutine for each of the 16 DTMF keyboard input digits is
supplied with the listing for the DTMF35 program. This test
routine uses a 16 byte ROM table to supply the low true
encoded column/row keyboard input to the accumulator. An
input from the 10 pin of the I port is. used to select which
DTMF generation subroutine is to be used. The DTMFLP
subroutine is selected with 10 = 1.

# of Bytes
of Program
19
78
88

Subroutine
KBRDEC
DTMFGP
DTMFLP

A TYPICAL RESISTOR LADDER NETWORK IS SHOWN IN
FIGURE 4.

# of Bytes
of ROM Table
16
16
213

Total #
of Bytes
35
94
301

2R
. on.crs.

~-""---I""'--O
2R

on.crs

OTt.lr OUT

I-

on.cr4 --IV"IV
,,\t,,-.
S SINE WAVE OUTPUTS

2R
on.cr3 --"IV.V."\t-.....
2R
on.cr2 --'lJVv
.-.
2R
OTt.lFl-...."IV"'''V,,''\t-'''-o

TLIOO/10740-24

FIGURE 4. Typical Resistor Ladder Network

2-105

0,
en
en

CD
CD
CD

c:t

2
3
4
S
6
7
8
9

DTMF GENERATION WITH A 3.58 MHZ
CRYSTAL FOR COP820C/840C .

VERNE H. WILSON
10/28/89

DTMF - DUAL TONE MULTIPLE FREQUENCY
PROGRAM NAME: DTMF3S.MAC
.TITLE DTMF35
.CHIP 840

12
13
14
15
16
17
18
19
20
21
22
23
24
2S
26
27
28
29
30
31
32
33

34
3S
36
37
38
39
40
41
42
43
44

45
46
47
48
49
SO

THIS DTMF PROGRAM IS BASED ON A COP620C/640C RUNNING
WITH A CKI CLOCK OF 3.579545 MHZ (TV COLOR CRYSTAL
FREQUENCY) IN DIVIDE BY 10 MODE, FOR AN INSTRUCTION
CYCLE TIME OF 2.7936511 MICROSECONDS.
THIS PROGRAM CONTAINS THREE SUBROUTINES, ONE FOR A
LOW TRUE ROW/COLUMN DTMF KEYBOARD DECODING (KBRDEC),
AND THE OTHER TWO (DTMFGP, DTMFLP) FOR ALTERNATE
METHODS OF DTMF GENERATION.
KEYBOARD INPUT DATA IS IN ACCUMULATOR WITH A
LOW TRUE FORMAT AS FOLLOWS:
BITS 7 TO 4 : LOW TRUE COLUMN VALUE (E,D,B,7)
BITS 3 TO 0 : LOW TRUE ROW VALUE (E,D,B,7)
ASSUMPTION MADE THAT COLUMN STROBES (LOW TRUE) ARE
OUTPUT, WHILE ROW VALUES (LOW TRUE) ARE INPUT.
THE FIRST METHOD OF DTMF GENERATION
GENERATING TWO PWM OUTPUTS ON THE G
OUTPUT PINS. THESE TWO OUTPUTS NEED
EXTERNALLY WITH AN APPROPIATE LM324
CIRCUIT TO GENERATE THE DTMF.

CONSISTS OF
PORT G2 AND G3
TO BE MIXED
OP AMP FEEDBACK

THE SECOND METHOD OF DTMF GENERATION USES ROM LOOKUP
TABLES TO SIMULATE THE TWO DTMF SINE WAVES AND
COMBINES THEM ARITHMETICALLY. THE RESULT IS OUTPUT ON
THE LOWER SIX BITS OF THE L PORT (LO - L5). THESE SIX
OUTPUTS ARE COMBINED EXTERNALLY WITH A LADDER NETWORK
TO GENERATE THE DTMF.
THE SECOND DTMF GENERATION METHOD USES APPROXIMATELY
THREE TIMES. AS MUCH ROM CODE (INCLUDING PROGRAM CODE
AND ROM TABLES) AS THE FIRST METHOD, BUT HAS THE
ADVANTAGE OF ELIMINATING THE COST OF THE EXTERNAL
ACTIVE COMPONENT (LM324 OR EQUIVALENT).
BOTH OF THE DTMF SUBROUTINES GENERATE THEIR OUTPUTS
FOR A PERIOD OF 100 MILLISECONDS.
TL/DD/10740-1

2-106

»
z
I

52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70

0000
OODO
OODI
00D4
00D5
00D7
OODC
OOEA
OOEB
OOEC
OOED
OOEE
OOEP
OOPO
OOF!
00P2
00F3

72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

0)
0)
0)

DECLARATIONS:

0000 DD2F

0002
0004
0006
0007
0008
OOOA
OOOB
OOOC
OOOE
OOOP
0011
0012
0014
0015
0016
0018
0019

DEDC
9EOO
AO
AE
9405
A6
6C
9420
A4
3210
Al
DED7
70
03
3040
02
308E

001B DEDC
OOID E8

,
START:

LOOP:

BYPA:
BYPB:

KDATA
PORTLD
PORTLC
PORTGD
PORTGC
PORTI
PORTD
TMRLO
TMRHI
TAULO
TAUHI
CNTRL
PSW
RO
Rl
R2
R3

0
000
ODI
004
OD5
OD7
ODC
OEA
OEB
OEC
OED
OEE
OEP
OPO
OPI
OP2
OP3

*** KEYBOARD DATA ***
PORTL DATA REG
PORTL CONPIG REG
PORTG DATA REG
PORTG CONPIG REG
PORTI INPUT PINS
PORTD REG
TIMER LOW COUNTER
TIMER HIGH COUNTER
TMR AUTO RELOAD REG LO
TMR AUTORELOAD REG HI
CONTROL REG
PROC STATUS WORD
LB PREO LOOP COUNTER
LB FREQ LOOP COUNT
LB FREQ 0 COUNT
LB FREQ R COUNT
INITIALIZE STACK PTR

SP,U02F

LD
LD
RC
LD
ADD
X
RBIT
ADD
LAID
JSR
SC
LD
IPBIT
JP
JSR
JP
JSR

KEYBOARD HEX DIGIT MATRIX
1 2 3 A
B,UPORTD
4 5 6 B
[B],UO
7 8 9 C
0 U D
DTMF TEST LOOP
A, [B)
SEQUENCE IS 1,5,9,0,4,
A,U5
8,U,A,7,0,3,B,*,2,6,C
A, [B)
HEX MATRIX TO LOOKUP
4, [B)
TABLE FOR LOW TRUE
A,U020
COLUMN/ROW INPUT TO
KBRDEC
KBRDEC SUBROUTINE
SET C IP NOT SINGLE KEY
B,UPORTI
TEST BIT 0 OF PORTI TO
DETERMINE WHICH
0, [B)
DTMP SUBROUTIINE
BYPA
TWO PWM OUTPUTS ON
DTMPGP
G PORT PINS G2,G3
BYPB
SIX
LADDER OUTPUTS ON
DTMPLP
L PORT PINS LO - LS
B,UPORTD
DO WILL TOGGLE POR EACH
CALL OF SUBROUTINE
LOOP

LD
JP

TLlDD/l 0740-2

2-107

CD
CD
CD

Z
137
138
139
140
141
142
143

144
145

146
147

HALF PERIODS FOR THE 8 DTMF FREQUENCIES (697,770,852,
941,1209,1336,1477, AND 1633 KHZ) ARE 257,232,
210,190,146,134,121, AND 110 Te's RESPECTIVELY
THE 100 MSEC DIVIDED BY. HALF PERIOD QUOTIENTS ARE
139,154,170,186,241,267,295, AND 325 RESPECTIVELY
THE 100 MSEC DIVIDED BY HALF PERIOD REMAINDERS ARE
72,67,95,75,127,17,100, AND 45 RESPECTIVELY

148

149
150
151
152
153
154
155
156
157
156
159
160
161
162
163
164
165
166
167
166
169
170
171

172
173
174
175
176
177
176
179
180
161
182
183
184

BINARY FORMAT FOR THE HEX DIGIT KEY VALUE FROM THE
KBRDEC SUBROUTINE IS OOOORRCC,
WHERE
RR IS ROW SELECT (LB FREQUENCIES)
CC IS COLUMN SELECT (HB FREQUENCIES)
FREQUENCY VECTORS (HB & LB) FOR FREQ PARAMETER TABLE
MADE FROM KEY VALUE
HB FREQ VECTORS (4) END WITH 00 FOR TIMER COUNTS,
WHERE VECTOR FORHAT IS 0011CCOO
LB FREQUENCY VECTORS (12) END WITH:
11 FOR HALF PERIOD LOOP COUNTS,
WHERE VECTOR FORMAT IS 0011RRl1
10 FOR 100 MSEC DIVIDED BY HALF PERIOD QUOTIENTS,
WHERE VECTOR FORMAT IS 0011RRI0
01 FOR 100 MSEC DIVIDED BY HALF PERIOD REMAINDERS,
WHERE VECTOR PORMAT IS 0011RR01
PREQ PARAMETER TABLE AT HEX 003*

(REQUIRED LOCATION)

KEY VALUE
OOOORRCC
TIMER
R1
R2
R3

F
Q

CCOO
RRll
RRI0
RROI

TLlDD/l0740-4

2-109

en
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CD
CD
CD

165
166
167
166
169
190
191
192
193
194
195
196
197
196
199
200
201
202
203
204
205
206
207
206
209
210
211
212
213
214
215
216
217
216
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235

.FORM
FREQUENCY AND 100 MSEC PARAMETER TABLE
0030
0031
0032
0033
0034
0035
0036
0037
0036
0039
003A
003B
003C
003D
003E
003F

93
OA
6C
26
65
09
9B
21
76
OE
AB
IF
6D
OA
BD
lA

0040
0042
0044
0045
0046
0047
0046
0049
004B
004D
004E
004F
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
005A
005C
OOSD
OOSF
0061

DED5
9B3F
6B
6A
SF
A6
AE
9733
DEFI
A6
AE
A4
A2
8B
44
F9
SF
AE
65
AO
BO
BO
9730
A4
DEEA
9AOF
9AOO

.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE

147
10
140
36
133
9
155
33
120
14
171
31
109
10
169
26

LD .
LD
RBIT
RBIT·
LD
X
LD
OR
LD
X
LD
LAID
X
DEC
IFBNE
JP
LD
LD
SWAP
RC
RRC
RRC
OR
LAID
LD
LD
LD

B,UPORTGC
[B-],U03F
3, [B]
2, [B]
B,UKDATA
A, [B)
A, [B)
A,U033
B,URI
A, [B)
A, [B)

:
DTMFGP:

LUP:

A,(B+)
A
U4
LUP
B,UKDATA
A, [B)
A

T
R
Q
F
T
R
Q
F
T
R
Q
F
T
R
Q
F

CONFIGURE G PORT
FOR OUTPUTS
OPTIONAL HB RESET
OPTIONAL LB RESET
STORE KEY VALUE
KEY VALUE TO ACC
CREATE LB FREQ VECTOR
FROM KEY VALUE
THREE PARAMETERS
FROM LOW BAND
FREQ ROM TABLE
TO Rl,R2,R3

KEY VALUE TO ACC
CREATE HB FREQ VECTOR
FROM KEY VALUE

A
A
A,U030
B,UTMRLO
[B+),UI5
[B+) ,UO

HB FREQ TABLE
(1 PARAMETER)
INSTRUCTION CYCLE
TIME UNTIL TOGGLE
TL/DD/l0740-5

2-110

z
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274

0063
0064
0066
0068
006A
006C
006D
006E
006F
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079

A2
9AOO
9EBO
DED4
DCFl
BB

007A
007B
007D
007E
007F
0080
0082
0083
0084
0085
0086
0087
0088
008B
008C
008D

BE
921F
EE
B8
B8
9226
E9
A4
B8
E6
C3
FE
BDEE6C
6B
6A
8E

LUPI :

03
B2
7A
03
B8
6A
B2
C2
01
OE
CO
FE

BYPl:
BYP2:
LUP2:

FINI:

X
LD
LD
LD
LD
LD
IFBIT
JP
X
SBIT
JP
NOP
RBIT
X
DRSZ
JP
JP
DRSZ
JP

A, [B+]
[B+],#O
[B],#OBO
B,#PORTGD
X,URI
A,[X-]
2, [B]
BYPI
A, [X+]
2, [B]
BYP2

HB FREQ PARAMETER TO
AUTO RELOAD REGISTER
START TIMER PWM

2, [B]
A, [X+]
R2
LUP2
FIN I
RO
LUP2

RESET LB OUTPUT

LD
IFEO
JP
NOP
NOP
IFEO
JP
LAID
NOP
JP
DRSZ
JP
RBIT
RBIT
RBIT
RET

A, [X]
A,#31
LUPI
A,U38
LUPI
LUPI
R3
FINI
4,CNTRL
3, [B1
2, [BJ

TEST LB OUTPUT
SET LB OUTPUT

DECR. QUOT. COUNT
"Q COUNT FINISHED
DECR. F COUNT
LB (HALF PERIOD)

******************
***
** *
***
***
***
***
***
***
******************

BALANCE
LOW BAND
FREQUENCY
RESIDUE
DELAY FOR
EACH OF THE
FOUR LOW BAND
FREQUENCIES

DECR. REMAINDER COUNT
REM. COUNT NOT FINISHED
STOP TIMER
OPTIONAL CLR HB OUTPUT
OPTIONAL CLR LB OUTPUT
RETURN FROM SUBROUTINE

TL/DD/10740-6

2-111

en
en

CD
CD
CD

Z
<

275
276
277
276
279
260
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325

.FORM
SECOND DTMF SUBROUTINE (DTMFLP) PRODUCES SIX
COMBINED tow BAND AND HIGH BAND FREQUENCY
SINE WAVE OUTPUTS ON PINS LO - L5
SIX L PORT OUTPUTS (LO - L5) FEED INTO AN EXTERNAL
RESISTOR LADDER NETWORK TO CREATE THE DTMF OUTPUT.
FOUR VALUES FROM A KEYBOARD
INTO LFTBSZ (LOW FREQ TABLE
FREQ TABLE ADDRESS). HFTBSZ
AND HFTADR (HIGH FREQ TABLE

ROM TABLE ARE LOADED
SIZE). LFTADR (LOW
(HIGH FREQ TABLE SIZE).
ADDRESS).

LUP42 USES THE LFPTR (LOW FREQ POINTER) AND HFPTR
(HIGH FREQ POINTER) TO ACCESS THE SINE DATA TABLES
FOR THE SELECTED FREQUENCIES ONCE PER LOOP. THESE
POINTERS ARE BOTH INCREMENTED ONCE PER LUP42.
LUP42 PROGRAM LOOP UPDATES THE OUTPUT VALUE EVERY
117 1/3 uSEC BY SELECTING AND THEN COMBINING NEW
VALUES FROM THE SELECTED LOW BAND AND HIGH BAND
FREQUENCY ROM TABLES WHICH SIMULATE THE SINE WAVES
FOR THE TWO FREQUENCIES.
MULTIPLES OF THE MAGIC NUMBER OF APPROXIMATELY
118 uSEC ARE .CLOSE APPROXIMATIONS TO ALL EIGHT OF
THE DTMF FREQUENCIES.
COP820C/840C TIMER USED TO INTERRUPT THE DTMF LUP42
PROGRAM LOOP AFTER 100 MSEC TO FINISH THE DTMF
OUTPUT AND RETURN FROM THE DTMFLP SUBROUTINE. NOTE
THAT THE STACK POINTER (SP) MUST BE ADJUSTED AFTER
THE INTERRUPT BEFORE RETURNING FROM THE SUBROUTINE.

DECLARATIONS:
0005
0006
0007
0008
0009
OOOA
OOOB

LFPTR
TEMP
HFPTR
LFTBSZ
LFTADR
HFTBSZ
HFTADR

05
06
07
08
09
OA
OB

0004

TRUN

LOW FREQ POINTER
TEMPORARY
HIGH FREQ POINTER
LO FREQ TABLE SIZE
LO FREQ TABLE ADDR
HI FREQ TABLE SIZE
HI FREQ TABLE ADDR

TL/DD/10740-7

2-112

326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366

»
z

,
008E
0091
0094
0097
0098
009A
009B
009C
009D
009E
OOAO
OOAl
OOA2
00A3
00A4
00A5
00A6
00A7
00A9
OOAB
OOAD
OOAF
OOBl
00B3
00B5
00B6

BCDlFF
BCD01D
BC0500
58
9AOO
AO
65
BO
BO
94B8
A6
AE
A4
A2
8A
4C
F9
DEEA
9AOO
9A8C
9AOO
9A8C
9A80
9Bll
7C
210F

DTMFLP:

FRLUP:

PORTLC,#OFF
PORTLO,#29
LFPTR,#O
B,#HFPTR
[B+]'#O

LD
LD
LD
LO
LD
RC
SWAP
RRC
RRC
ADD
X
LD
LAID
X
INC
IFBNE
JP
LD
LO
LD
LD
LD
LO
LO
SBIT
JMP

A
A
A
A,#OB8
A, [B]
A, [B)
A, [B+ )
A
#OC
FRLUP
B,#TMRLO
[B+],#O
[B+),#140
[B+) ,#0
[B+) ,#140
[B+],#080
[B-) ,#011
TRUN,[B]
LUP42

INITIALIZE PORT L
FOR NO TONE OUT
INITIALIZE OFFSET
POINTERS FOR
DTMF SINE WAVE
TABLE LOOKUP
QUADRUPLE KEY
VALUE AND ADD
OFFSET FOR KEY
TABLE LOOKUP
LOAD FOUR VALUES
FROM ROM KEY
TABLE INTO LOW
FREQ LFTBSZ,
LFTADR, AND HI
FREQ HFTBSZ,
HFTADR
INITIALIZE TIMER
WITH A tC COUNT
EQUIVALENT TO
100 MSEC PLUS
A LUP42 TIME
TIMER PWM, NO OUT
ENABLE TMR IHTRPT
START TIMER

TELEPHONE KEY TABLE:
TABLE FORMAT:
PARAMETER
PARAMETER
PARAMETER
PARAMETER

1:
2:
3:
4:

# OF
BASE
# OF
BASE

LOW FREQ TABLE VALUES
ADDR. OF LOW FREQ VALUES
HIGH FREQ TABLE VALUES
ADDR. OF HIGH FREQ VALUES

KEY 1
00B8 31
00B9 2D
QQuA 07
OOBB 7C

367
368
369 OOBC
OOBD
OOBE
OOBF
370

.BYTE

49,02D,7,07C

.BYTE

49,020,19,083

KEY 2
31
2D
13
83

TlIDD/l0740-8

2-113

m
en
en

(Q
(Q
(Q

DISPLAY TIME IS ISEC.
iLCD DRIVE ROUTINE FOR CUSTOMIZED 2 WAY MULTIPLEX
;LCD
TLlDD/l0788-12

2·136

iROUTINE CONVERTS BCD DATA STORED IN RAM LOCATIONS
iBCDLO, BCDHI INTO LCD OUTPUT DATA STORED AT
iMWBUFO
LPORT DATA
iMWBUFl = DPORT DATA
iMWBUF2 = G-PORT DATA (GO,Gl ONLY, OTHER BITS
STAY UNCHANGED)
iSUBROUTINES INCLUDED:
iSEGO: GETS LCD SEGMENT DATA FOR TIMEPHASE TA
iSEG1: GETS LCD SEGMENT DATA FOR TIMEPHASE TB
iSEG2: GETS LCD SEGMENT DATA FOR TIMEPHASE TC
iSEG3: GETS LCD SEGMENT DATA FOR TIMEPHASE TD
iDISPD:
SWITCHES THE DISPLAY OFF AND
CONFIGURES G-,L- AND D-PORTS
iTTPND:
CHECKS TIMER PENDING FLAG (REFRESH
RATE GENERATION)
iSEGOUT: OUTPUTS LCD SEGMENT AND BACKPLANE DATA
; SUBROUTINES SEGO ...
SEGl MUST FOLLOW DIRECTLY AFTER
iTABLE, BECAUSE OF THE USE OF THE LAID-INSTRUCTION

LOOK-UP

. LOCAL
SEGO:
LD
LD
LD
LD

B,#OFFl iPOINT TO OFFSET 1 REG.
[B+],#OOO
[B+],#OOO
A,#OOB

IFBIT
INCA

#05,BCDHI iWEIGHT >= 200 POUNDS?
iYES DISPLAY DIGIT5 ("2")

IFBIT
JP
ADD

#POUND,FLAG
$LPORT
A,#OO2

X
LD
LD
LD
AND
ADD
LAID
X

A, [B)
X,#BCDLO
B,#MWBUFO
A, [X]
A,#OOF iELIMINATE DIGITl BITS
A,OFF2
iGET DIGITl DATA
iSAVE DIGITl DATA
A, [B]
iIN MWBUFO
A, [X+]
A,#OFO iELIMINATE DIGITl BITS
A
A,OFFl iALWAYS DISPLAY DECIMAL POINT
iGET DIGITl DATA
A
A, [B]
iSTORE DIGITl AND
iDIGIT2 DATA IN MWBUFO
A, [B+]

$TWO:

$POUND:

SLPORT:

LD
AND
SWAP
ADD
LAID
SWAP
OR
X

TLIDD/10788-13

2·137

,----------------------------------------------------------------------,

$DPORT:
LD
IFBIT
JP
AND
ADD
JP

A, [Xl

#04,BCDHI
$ADD1
A,#OOF
A,OFF2 iDISPLAY NO LEADING ZERO
$GET

$ADD1 :
ADD

A,#OOF
A,OFF1

LAID
X

A, [B+]

AND

iDISPLAY "1"

(DIGIT4)

$GET:
iGET DIGIT3 DATA
iSTORE DIGIT3 DATA IN
iMWBUF1

$GPORT:
LD
LAID

A,OFF3

A,#OFC
A, [BJ

iGET DIGITS

("2") AND SPECIAL
iSEGMENT DATA
iSET BITS 2 ... 7 TO 1
iSAVE DATA IN MWBUF2

RET
SEG1:
LD
LD
LD
LD
JP

B,#OFF1
[B+],#OlB
[B+],#010
A,#OS6
$TWO

LD
LD
LD
LD
JP

B,#OFF1
[B+],#030
[B+],#030
A, #OSA
$TWO

LD
LD
LD
LD
JP
. LOCAL

B,#OFF1
[B+J,#04B
[B+],#040
A,#OSE
$TWO

IFBIT
JP
JP

#POUND,FLAG
MULT2
LDT

LD
LD

B,#BUF12LO
[B+],#22

SEG2:

SEG3:

DISPL:

MULT2:

iCALCULATE WEIGHT IN POUNDS
i (Multiplication of kg *2.2)
TL/DD/107BB-14

2-138

»
z

LD
JSR
LD
JSR
LD
LD
JSR

X,#STALO
MULBI168
B,#BUF12LO
COPY
STAHI+1,#00
DIVO,#lO
DIVBI248

JSR
LD

BINBCD16
COUNT, #50

LD
LD
LD
LD
LD
LD

B,#TMRLO
[B+],#OE8
[B+],#003
[B+],#OE8
[B+],#003
[B+],#090

......
Col

LDT:
iCONVERT BINARY TO BCD WEIGHT
iREPEAT DISPLAY LOOP 50 TIMES
i (=1 SEC DISPLAY TIME)
iLOAD TIMER WITH 1000(03E8h)
(=50 Hz LCD REFRESH AT tc=5us)
iLOAD AUTOREG. WITH 1000

iCNTRL-REG.:"TIMER WITH AUTOiLOAD"- MODE, START TIMER
[B+],#010 iPSW-REG.:RESET TPND FLAG

JSR

SEGO

JSR

TTPND

SBIT
LD
RBIT
SBIT
LD
RBIT
JSR
JSR
JSR

#BP1, [B]
A, [B+]
#BP2, [B)
#BP1, [B]
A, [B-]
#BP2, [B]
SEGOUT
SEG1
TTPND

SBIT
LD
RBIT
SBIT
LD
RBIT
JSR
JSR
JSR

#BP2, [B)
A, [B+]
#BP1, [B)
#BP2, [B)
A, [B-]
#BP1, [B]
SEGOUT
SEG2
TTPND

RBIT
LD
RBIT
SBIT
LD

#BP1, [B]
A, [B+]
#BP2, [B]
#BP1, [B)
A, [B-]
#BP 2, [B]
SEGOUT

DISP1:

TPO:

iGET 7-SEGM. DATA FOR REFRESH
iTIMEPHASE Ta
iTEST TIMER PENDING FLAG
iBACKPLANE REFRESH Ta
iPOINT TO G-CONFIG.-REG.
iPOINT TO G-DATA REG.
iSEGMENT DATA OUT
iGET 7-SEG. DATA FOR Tb

TP1:

iPOINT TO G-CONF.-REG.
iPOINT TO G-DATA REG.
iGET 7-SEGM. DATA FOR Tc

TP2:

RB I T

JSR

iPOINT TO G-CONFIG.-REG.
iPOINT TO G-DATA-REG.

TLlDD/l07BB-15

2·139

M ,-------------------------------------------------------------------------,

I"CD

JSR
JSR

SEG3
TTPND

RBIT
RBIT
LD
RBIT
SBIT
JSR
DRSZ
JP
LD
DRSZ
JP
JSR
RET

#BP1, [B]
#BP2, [B]
A, [B+]
#BP1, [B]
#BP2, [B]
SEGOUT
COUNT
DISPl
COUNT, #50
COUNT2
DISPl
DISPD

LD
LD
LD
LD
LD
LD
LD
RET

B,#PORTLD
[B+],#OOO
[B+],#OFF
B,#PORTGD
[B+],#OOO
[B+],#037
PORTD,#OOO

TP3:

ilOSEC OVER?
iNO, DISPLAY WEIGHT
iYES ROUTINE FINISHED

iSWITCH DISPLAY OFF

DISPD:

iOUTPUT 0 TO L PORT
iL-PORT = OUTPUT PORT
iOUTPUT 0 TO G OUTPUTS
iGO .. G2,G4,G5=OUTPUTS
iOUTPUT 0 TO D-PORT

SEGOUT:
LD
LD

A, [B+]

A,PORTLD

A, [B+]
A,PORTD
X,#PORTGD

LD
LD
AND

B,#MWBUFO

A, [X]
A, [B]

A, [B]

AND

A,#003

A, [B]

A, [Xl

iPOINT TO MWBUFl
iOUTPUT 7 SEG. DATA IN
iMWBUFO TOL-PORT
iPOINT TO MWBUF2
iOUTPUT MWBUFl TO D-PORT
iAND MWBUF2 WITH PORTGD
iLEAVE BITS 2 ... 7 UNCHANGED
iSTORE RESULT (A')IN
iMWBUF2,LOAD A WITH
iORIGINAL MWBUF2 VALUE
iAND 007 WITH ORIGINAL
i MWBUF2 (A"), SET BITS: '0, 1 TO
iCORRECT VALUE
iOR A' WITH A" ,RESTORE ORIGINAL
;'G2 ... G7 BITS
iOUTPUT RESULT TO G-PORT

RET
TLlDD/10788-16

2-140

;16 BIT BINARY TO BCD CONVERSION
;THE MEMORY ASSIGNMEMTS ARE AS FOLLOWS:
;BINLO: RAM ADRESS BINARY LOW BYTE
;BCDLO: RAM ADRESS BCD LOW BYTE
;COUNT: RAM ADRESS SHIFT COUNTER (OFO ... OFB,OFF)
;BCD NUMBER IN BCDLO,BCDLO+1,BCDLO+2
;

;MEMORY ADRESS
; DATA

M(BINLO+1)
BINARY HB

M(BINLO)
BINARY LOW BYTE

;MEMORY ADRESS
; DATA

M(BCDLO+2)
BCD HB

M(BCDLO+1)
BCD

M(BCDLO)
BCD LOW BYTE

BINLO = STALO
. LOCAL
$BCDT
(BCDLO + 3) &OF
$BINT
(BINLO + 2) & OF
BINBCD:
LD
LD

COUNT,#16 ;LOAD CONTROL REGISTER WITH
;NUMBER OF LEFTSHIFTS TO
;EXECUTE
B,#BCDLO ;LOAD BCD-NUMBER LOWEST BYTE
;ADRESS
;CLEAR BCD RAM-REGISTERS

$CBCD:
LD
IFBNE
JP

[B+],#OO
#$BCDT
$CBCD

LD
RC

B,#BINLO

LD
ADC
X

A, [B]
A, [B)
A, [B+]

IFBNE
JP
LD

#$BINT
$LSHFT
B,#BCDLO

LD
ADD
ADC

A,#066

;LEFTSHIFT BINARY NUMBER

$LSH:
$LSHFT:

;IF MSB IS SET, SET CARRY

$BCDADD:
A, [B]

A, [B)

DCOR

A, [B+]

IFBNE

#$BCDT

JP
DRSZ
JP
RET
. LOCAL

$BCDADD
COUNT
$LSH

;ADD CORRECTION FACTOR
;LEFTSHIFT BCD NUMBER
; (BCD=2**WEIGHT OF
;BINARY BIT (=CARRY BIT))
iDECIMAL CORRECT ADDITION

TLlDD/10788-17

iDECREMENT SHIFT COUNTER

TL/DD/10788-18

2-141

C")

r--

iBINARY DIVIDE 24BIT BY 8BIT (Q=Y/Z)
iYL: LOW BYTE RAM ADRESS DIVIDEND
iZL: LOW BYTE RAM ADRESS DIVISOR
iCNTR: RAM ADRESS SHIFT COUNTER (OFO ... OFB,OFF)
iQUOTIENT AT RAM LOCATIONS YL .. YL+2
iREMAINDER AT YL+3
iQUOTIENT IS ALL 'l's IF DIVIDE BY ZERO, REMAINDER
iTHEN CONTAINS YL
iTHE MEMORY ASSIGNMENTS ARE AS FOLLOWS:

M(YH+l)

M(YH)
Y(HIGH BYTE)

M(YL+l)
Y

M(YL)
Y(LOW BYTE)

M(ZL)
Z
i

iROUTINE NEEDS 1.2lms FOR EXECUTION AT tc=lus
ZL
YL
CNTR
. LOCAL
$YH
$BTY
DIVBI248:
LD
LD
LD
LD
$LSHFT:
LD
RC
$LUP:
LD
ADC
X

IFBNE
JP
LD
IFC
JP

DIva
STALO
COUNT
YL+2
($YH&00F)+2 iPARAMETER FOR "IFBNE"-INSTR.
CNTR,#a18
B,#$YH+l
[B] , #000
X,#$YH+l
B,#YL

;INITIALIZE SHIFT COUNTER
iFOR 24 COUNTS
;PUT a IN M(YH+l)

iLEFT SHIFT DIVIDEND

A, [B]
A, [B]
A, [B+]

#$BTY
$LUP
B,#ZL
$SUBT

$TSUBT:
SC
LD
SUBC
IFNC
JP

iSUBTRACT AND TEST
iSUBTRACT Z FROM M(YH+l,YH+2)
A, [X]
A, [B]

$TEST
Tl/DD/10788-19

2-142

$SUBT:
;SUBTRACT Z FROM M(YH+l,YH+2)
LD
SUBC

A, [X]
A, [B)

A, [X]

LD
SBIT

B,#YL
#0, [B]

DRSZ
JP
RET
. LOCAL

CNTR
$LSHFT

$TEST:
;24 SHIFTS EXECUTED?
iNO, LEFT SHIFT DIVIDEND

iBINARY MULTIPLIES A 16BIT VALUE (Xl)
iWITH A 8BIT VALUE (X2): M = Xl * X2
iXIL: RAM ADRESS Xl LOW BYTE

iX2L: RAM ADRESS X2
iCOUNT RAM ADRESS SHIFT COUNTER
iM

IS STORED AT RAM ADRESSES X2L ... X2L+2

MEMORY ASSIGNMEMTS ARE AS FOLLOWS:
iMEMORY
M(X2L+2)
M(X2L+I)
M(X2L)
iDATA
a
a
X2

iTHE

i-----------------------------------------------------M(XIL+I)
Xl (H.B.)

iMEMORY
iDATA

M(XIL)
Xl (LOW BYTE)

iTHE EXECUTION TIME FOR THE ROUTINE AT tc=lus IS 240us

. LOCAL
MULBII68:
LD
LD
LD
RC

COUNT,#9 ;PRESET SHIFT COUNTER
[B+],#OO iPRESET X2L+I,X2L+2 WITH '0'
[B) , #00

LD
RRCA

A, [B)

A, [B-]
A, [B)

$LOOP:

LD
RRCA
X

A, [B-]

LD
RRCA

A, [B]

A, [B+]

;RIGHT SHIFT

EI
TLIDD/10788-20

2-143

....

Cf)

c:(

A, [B+]

LD
IFNC
JP
RC
LD

A, [B-]

LD
ADC
X
LD
ADC
X

A,
A,
A,
A,
A,
A,

DRSZ
JP
RET
. LOCAL
.END

COUNT
$LOOP

$TEST

[X+]
[B]
[B+]
[X-]
[B]
[B]

iINCREMENT B POINTER
iMOST SIGN. BIT OF X2 SET?
iNO,TEST SHIFT COUNTER
iYES,RESET CARRY
iPOINT TO 2nd HIGHEST BYTE
iOF RESULT
iDO WEIGHTED ADD

$TEST:
i8 RIGHT SHIFTS EXECUTED?
;NO,SHIFT
iYES,MULIPLICATION FINISHED
TL/DD/10788-21

2-144

PC® MOUSE
Implementation Using
COP800

National Semiconductor
Application Note 681
Alvin Chan

ABSTRACT

which in turn generates signals to the microcontroller. The
opto-mechanical mouse uses disks that contain evenly
spaced slots. Each disk has a pair of LEOs on one side and
a pair of photo-transistors on the other side.

The mouse is a very convenient and popular device used in
data entry in desktop computers and workstations. For
desktop publishing, CAO, paint or drawing programs, using
the mouse is inevitable. This application note will describe
how to use the COP822C microcontroller to implement a
mouse controller.
INTRODUCTION

Mouse Systems was the first company to introduce a mouse
for PCs. Together with Microsoft and Logitech, they are the
most popular vendors in the PC mouse market. Most mainstream PC programs that use pointing devices are able to
support the communication protocols laid down by Mouse
Systems and Microsoft.
A typical mouse consists of a microcontroller and its associated circuitry, which are a few capacitors, resistors and transistors. Accompanying the electronics are the mechanical
parts, consisting of buttons, roller ball and two disks with
slots. Together they perform several major functions: motion detection, host communication, power supply, and button status detection.
MOTION DETECTION

Motion detection with a mouse consists of four commonly
known mechanisms. They are the mechanical mouse, the
opto-mechanical mouse, the optical mouse and the wheel
mouse.
The optical mouse differs from the rest as it requires no
mechanical parts. It uses a special pad with a reflective surface and grid lines. Light emitted from the LEOs at the bot-

tom or lhe mOU5e is rellt::clt::u lJy [btl

tiUliliCtI

anu lIIovtlllltml

is detected with photo-transistors.
The mechanical and the opto-mechanical mouse use a roller ball. The ball presses against two rollers which are connected to two disks for the encoding of horizontal and vertical motion. The mechanical mouse has contact points on
the disks. As the disks move they touch the contact bars,

The wheel mouse has the same operation as the mechanical mouse except that the ball is eliminated and the rollers
are rotated against the outside surface on which the mouse
is placed.
HOST COMMUNICATION

Besides having different operating mechanisms, the mouse
also has different modes of communication with the host. It
can be done through the system bus, the serial port or a
special connector. The bus mouse takes up an expansion
slot in the PC. The serial mouse uses one of the COM ports.
Although the rest of this report will be based on the optomechanical mouse using the serial port connection, the
same principle applies to the mechanical and the wheel
mouse.
MOTION DETECTION FOR THE OPTO-MECHANICAL
MOUSE

The mechanical parts of the opto-mechanical mouse actually consist of one roller ball, two roilers connected to the
disks and two pieces of plastic with two slots on each one
for LED light to pass through. The two slots are cut so that
they form a 90 degree phase difference. The LEOs and the
photo-transistors are separated by the disks and the plastic.
As the disks move, light pulses are received by the phototransistors. The microcontroiler can then use these quadrature signals to decode the movement of the mouse.

Figure fa shows the arrangement of the LEOs, disks, plastic
and photo-transistors. The shaft connecting the disk and
the ball is shown separately on Figure lb. Figure 2 shows
the signals obtained from the photo-transistors when the
mouse moves. The signals will not be exactly square waves
because of unstable hand movements.

2-145

»
z

co
.....

LED

PHOTO-TRANSISTOR

DISK

TL/DD/10799-1

90° phase difference

TL/DD/10799-2

b
FIGURE 1

disk

phototranslstors

LED

<[]

TRKYl

LED

<[]

TRKYO

LED

,c:J

TRKXO

vertical motion

LED

phototranslstors

TRKXl

horizontal motion

TL/DD/10799-3

TRKl

TRKO

ccw

TL/DD/10799-4

Signals at phototransistors are similar for vertical and horizontal motion,
Track 1 leads track 0 by 90 degrees

FIGURE 2

. 2-146

l>
RESOLUTION, TRACKING SPEED
AND BAUD RATE

utilized. Therefore the microcontroller and the mouse hardware should have very little power consumption. National
Semiconductor's COP822C fits into this category perfectly.
The voltage level in the RS232 lines can be either positive
or negative. When they are positive, the power supply can
be obtained by clamping down with diodes. When they are
negative, a 555 timer is used as an oscillator to transform
the voltage level to positive. The 1966 National Semiconductor Linear 3 Databook has an example of how to generate a variable duty cycle oscillator using the LMC555 in
page 5-282.

The resolution of the mouse is defined as the number of
movement counts the mouse can provide for each fixed distance travelled. It is dependent on the physical dimension of
the ball and the rollers. It can be calculated by measuring
the sizes of the mechanical parts.
An example for the calculation can be shown by making the
following assumptions:
• The disks have 40 slots and 40 spokes
• Each spoke has two data counts
(This will be explained in the section "An Algorithm for
Detecting Movements")

While the RTS and DTR lines are used to provide the voltage for the mouse hardware, the TXD line of the host is
utilized as the source for the communication signals. When
idle, the TXD line is in the mark state, which is the most
negative voltage. A pnp transistor can be used to drive the
voltage of the RXD pin to a voltage level that is compatible
with the RS232 interface standard.

• Each slot also has two data counts
• The roller has a diameter of 5mm
For each revolution of the roller, there will be 40 X 2 x 2 =
160 counts of data movement. At the same time, the mouse
would have travelled a distance of 7T x 5 = 15.7mm.
Therefore the resolution of the mouse is 15.7/160 =
O.098mm per count. This is equivalent to 259 counts or dots
per inch (dpi).

AN ALGORITHM FOR DETECTING MOVEMENTS
The input signal of the photo-transistors is similar to that
shown in Figure 2. Track 1 leads track 0 by 90 degrees.
Movement is recorded as either of the tracks changes state.
State tables can be generated for clockwise and counterclockwise motions.

The tracking speed is defined as the fastest speed that the
mouse can move without the microcontroller losing track of
the movement. This depends on how fast the microcontroller can sample the pulses from the photo-transistors. The
effect of a slow tracking speed will contribute to jerking
movements of the cursor on the screen.

With the two tracks being 90 degrees out of phase, there
could be a total of four possible track states. It can be observed that the binary values formed by combining the present and previous states are unique for clockwise and counter-clockwise motion. A sixteen entry jump table can be
formed to increment or decrement the position of the cursor. If the value obtained does not correspond to either the
clockwise or counter-clockwise movement, it could be treated as noise. In that case either there is noise on the microcontroller input pins or the microcontroller is tracking motions faster than the movement of the mouse. A possible
algorithm can be generated as follows. The number of instruction cycles for some instructions are shown on the left.

The baud rate is fixed by the software and the protocol of
the mouse type that is being emulated. For mouse systems
and microsoft mouse, they are both 1200. Baud rate will
affect both the resolution and the tracking speed. The internal movement counter may overflow while the mouse is still
sending the last report with a slow baud rate. With a fast
baud rate, more reports can be sent for a certain distance
moved and the cursor should appear to be smoother.
POWER SUPPLY FOR THE SERIAL MOUSE
Since the !:er!~1 pert cf the PC h~~ r.o pc'::cr ~:.:;;;;!y !:r.c~,
the RTS, CTS, DTR and DSR RS232 interface lines are
(TRK1, TRKO)t

o
o

o
1

(TRK1, TRKOh-1
CCW

o
o

Binary Value

(TRK1, TRKOh

D
1

0
0

(TRK1, TRKOh-l
CW
0
0
0

2-147

Binary Value
8
7
E

.......

'I"""

co
CD

CYCLES

;***************************************************
SAMPLE SENSOR INPUT
INC OR DEC THE POSITION

;***************************************************
SENSOR:
LD
LD
RRC
AND
X

B,#GTEMP
A,PORTGP
A
A,#O:3C
A, [BJ

LD
RRC
RRC
AND
OR
OR
JID

A,
A
A
A,
A,
A,

NOISEX:

YDIR

INCX:

LD
INC
JP

A,XINC.
A
COMX

DECX:

LD
DEC

A,XINC
A

IFEQ
JP
X
LD
SBIT
LD

A, #080
YDIR
A, XINC
B, #CHANGE
RPT, [BJ
B, #TRACKS

LD
SWAP
RRC
RRC
RRC
AND
OR

A, [B-J
A
A
A
A
A, #OCO
A, [BJ

:3
1

2
1

2
1
1

2
1

2
3

:3
1

G6,G5,G4,G:3
(GTEMP)

[B+J

(GTEMP) X IN 3,2

#03
[BJ
#OBO

(TRACKS)
X MOVEMENT TABLE

COMX:
2
1

3
1
1
1

YDIR:
2
1
1
1
1

2
1

(TRACKS) Y IN 5, 4

(GTEMP)

2-148

3
1
3

SWAP
OR
JID

A
A, #OCO

NOISEY:

ESENS

INCY:

LD
INC
JP

A, YINC
A
COMY

LD
DEC

A, YINC
A

IFEQ
JP
X
LD
SBIT.
LD

A, #080
ESENS
A, YINC
B, #CHANGE
RPT, [B]
B, #GTEMP

LD
X
RET

A, [B+ ]
A, [B]

(GTEMP) IN5, 4, I, 0
(TRACKS) NEW TRACK STATUS

NOISEX
INCX
DECX
NOISEX
DECX
NOISEX
NOISEX
INCX
INCX
NOISEX
NOISEX
DECX
NOISEX

1
2
3

Y MOVEMENT TABLE

DECY:
COMY:
2
1
3
1
1
1

ESENS:
2
1

.=OBO
MOVEMX:
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDn
.ADDR
.ADDR

1
2
3

4
5
6
7

8
9

; A
B
C

D:::::C;~

INCX
NOISEX

; E
; F

NOISEY
INCY
DECY
NOISEY
DECY
NOISEY
NOISEY
INCY
INCY
NOISEY
NOISEY
DECY
NOISEY
DECY
INCY
NOISEY

.=OCO
MOVEMY:
.ADDR
.ADDR
• AD DR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR

1
2
3

; 4
5
6
7
8
9

;
;
;
;

A
B
C
D
E
; F

2·149

....
CO

'I"'"

~
Z

A MOUSE EXAMPLE

Going through the longest route in the sensor routine takes
75 instruction cycles. So at 5 MHz the microcontroller can
track movement changes within 150 Ils by using this algorithm.

The I/O pins for the COP822C are assigned as follows:

MOUSE PROTOCOLS
Since most programs in the PC support the mouse systems
and microsoft mouse, these two protocols will be discussed
here. The protocols are byte-oriented and each byte is
framed by one start-bit and two stop-bits. The most commonly used reporting mode is that a report will be sent if
there is any change in the status of the position or of the
buttons.

L
X5
Y5

o
o

X4
Y4

Y7
X3
Y3

2
Y6
X2
Y2

X7
X1
Y1

0
X6
XO
YO

Bit
Number
Byte 1
Byte 2
Byte 3

L. R = Key data (Left, Right key) 1 = key depressed

Positive = South

In the Microsoft Compatible Format, data is transferred in
the form of seven-bit bytes. Y movement is positive to the
south and negative to the north.

The main program starts by doing some initializations. Then
it loops through four subroutines that send the report, sense
the movement, sense the buttons, and set up the report
format.

FIVE BYTE PACKED BINARY FORMAT
(MOUSE SYSTEMS CORP)

X7
Y7
X7
Y7

0
X6
Y6
X6
Y6

0
X5
Y5
X5
Y5

0
X4
Y4
X4
Y4

0
X3
Y3
X3
Y3

L*
X2
Y2
X2
Y2

M*
X1
Y1
X1
Y1

0
R*
XO
YO
XO
YO

Interrupt Input (Monitoring RTS Toggle)
Reserved for Input Data (TXD of Host)
Output Data (RXD of Host)
LED Sensor Input
Button Input
Jumper Input (for Default Mouse Mode)

The other interrupt comes from the GO pin. This is implemented to satisfy the microsoft mouse requirement. As the
RTS line toggles, it causes the microcontroller to be interrupted. The response to the toggling is the transmission of
the character "M" to indicate the presence of the mouse.

= X distance 8-bit two's complement value -128 to + 127
YO-Y7 = Y distance 8-bit two's complement value -128 to + 127
XO-X7

Function

GO
G1
G2
G3-G6
LO-L2
L3

The timer is assigned for baud rate generation. It is configured in the PWM auto-reload mode (with no G3 toggle output) with a value of 1AO hex in both the timer and the autoreload register. When operating at 5 MHz, it is equivalent to
833 Ils or 1200 baud. When the timer counts down, an interrupt is generated and the service routine will indicate in a
timer status byte that it is time for the next bit. The subroutine that handles the transmission will look at this status
byte to send the data.

MICROSOFT COMPATIBLE DATA FORMAT
6

Subroutine "SDATA" uses a state table to determine what
is to be transmitted. There are 11 or 12 states because
microsoft has only 7 data bits and mouse systems has 8.
The state table is shown below:

Bit
Number
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5

SENDST

o
1
2-8
2-9
9-10
10-11
11
12

= Key data (Left, Middle, Right key), 0 = key depressed
= X distance 8-bit two's complement value -127 to + 127
YO-Y7 = Y distance 8-bit two's complement value -127 to + 127
L0, MO, RO

XO-X7

In the Five Byte Packed Binary Format data is transferred in
the form of eight-bit bytes (eight data bits without parity).
Bytes 4 and 5 are the movement of the mouse during the
transmission of the first report.

State
IDLE
START BIT
DATA (FOR MICROSOFT)
DATA (FOR MOUSE SYSTEMS)
STOP BIT (FOR MICROSOFT)
STOP BIT (FOR MOUSE SYSTEMS)
NEXT WORD (FOR MICROSOFT)
NEXT WORD (FOR MOUSE SYSTEMS)

The G2 pin is set to the level according to the state and the
data bit that is transmitted.

THE COP822C MICROCONTROLLER

Subroutine "SENSOR" checks the input pins connected to
the LEDs. The horizontal direction is checked first followed
by the vertical direction. Two jump tables are needed to
decode the binary value formed by combining the present
and previous status of the wheels. The movements are recorded in two counters.

The COP822C is an 8-bit microcontroller with 20 pins, of
which 16 are I/O pins. The I/O pins are separated into two
ports, port L and port G. Port G has built-in Schmitt-triggered inputs. There is 1k of ROM and 64 bytes of RAM. In
the mouse application, the COP822C's features used can
be summarized below. Port G is used for the photo-transistor's input. Pin GO is used as the external interrupt input to
monitor the RTS signal for the microsoft compatible protocol. The internal timer can be used for baud rate timing and
interrupt generation. The COP822C draws only 4 mA at a
crystal frequency of 5 MHz. The instruction cycle time when
operating at this frequency is 2 Ils.

Subroutines "BUTUS" and "BUTMS" are used for polling
the button input. They compare the button input with the
value polled last time and set up a flag if the value changes.
Two subroutines are used for the ease of setting up reports
for different mice. The same applies for subroutines
"SRPTMS" and "SRPTUS" which set up the report format
for transmission. The status change flag is checked and the
report is formatted according to the mouse protocol. The

2-150

It uses only one byte and one instruction cycle. With autoincrement or autodecrement, it uses one byte and two instruction cycles. In order to utilize this addressing mode more
often, the organization of the RAM data has to be carefully
thought out. In the mouse example, it can be seen that by
placing related variables next to each other, the saving of
code and execution time is significant. Also, if the RAM data
can fit in the first 16 bytes, the load B immediate instruction
is also more efficient. The subroutine "SRPTMS" is shown
below and it can be seen that more than half the instructions are B register indirect which are efficient and compact.

movement counters are then cleared. Since tho sign of the
vertical movement of mouse systems and microsoft is reversed, the counter value in subroutine "SRPTMS" is complemented to form the right value.
There is an extra subroutine "SY2RPT" which sets up the
last two bytes in the mouse systems' report. It is called after
the first three bytes of the report are sent.
The efficiency of the mouse depends solely on the effectiveness of the software to loop through sensing and transmission subroutines. For the COP822C, one of the most
effective addressing modes is the B register indirect mode.

VARIABLES
WORDPT
WORD1
WORD2
WORD3
CHANGE
XINC
YINC
NUMWORD
SENDST

=
=
=
=
=
=
=
=
=

000
001
002
003
004
005
006
007
008

;WORD POINTER
;BUFFER TO STORE REPORTS
;MOVEMENT CHANGE OR BUTTON PRESSED
;X DIRECTION COUNTER
;Y DIRECTION COUNTER
;NUMER OF BYTES TO SEND
;SERIAL PROTOCOL STATE

;******************************************************
SUBROUTINE SET UP REPORT 'SRPT' FOR MOUSE SYSTEMS
CHANGE OF STATUS DETECTED
SET UP THE FIRST 3 WORDS FOR REPORTING
IF IN IDLE STATE

;******************************************************
SRPTMS:
LD
IFEQ
RET
RBIT

A,CHANGE
A, #0

EXIT IF NO CHANGE
DISABLE INTERRUPT

LO
LD
X

GIE, PSW
#WOHOPT
[B+], #01
A, BUTSTAT
A, [B+]

LD
X

A, XINC
A, [B+]

(WORD2)

SC
CLR
SUBC
X

A
A, YINC
A, [B+]

FOR MOUSE SYSTEM NEG Y
(WORD3)

RBIT
SBIT
LD
LD
LD

RPT, [B]
SYRPT, [B]
A, [B+]
[B+], #0
[B+] , #0

(CHANGE) RESET CHANGE OF STATUS
; (CHANGE)
INC B
(XINC)
(YINC)

LD
LD
SBIT
RET

[B+], #03
[B], #01
GIE, PSW

(NUMWORD) SEND 3 BYTES
(SENDST) SET TO START BIT STATE
ENABLE INTERRUPT

L1)

is,

(WORDPT) SET WORD POINTER
(WORD1)

2-151

,....
co

:Z
<

CONCLUSION

Feature
PortG
GO
Timer
Low Power
Small Size

The COP822C has been used as a mouse controller. The
code presented is a minimum requirement for implementing
a mouse systems and microsoft compatible mouse. About
550 bytes of ROM code has· been used. The remaining
ROM area can be used for internal diagnostics and for communicating with the host's mouse driver program. The unused 1/0 pins can be used to turn the LED's on only when
necessary to save extra power. This report demonstrated
the use of the efficient instruction set of the COP800 family.
It can be seen that the architecture of the COP822C is most
suitable for implementing a mouse controller. The table below summarizes the advantages of the COP822C.

Advantage
Schmitt Triggered Input for Photo-Transistors
External Interrupt for RTS Toggling
For Baud Rate Generation
4mAat5 MHz
20-Pin DIP

REFERENCE
The mouse still reigns over data entry-Electronic Engineering Times, October 1988.
MICE for mainstream applications-PC Magazine, August
1987.
Logimouse C7 Technical Reference Manual-Logitech,
January 1986.

APPENDIX A-MEMORY UTILIZATION
RAM Variables
TEMP
ASAVE
PSSAVE

OF1
OF4
OF6

WorkSpace
Save A Register
Save PSW Register

WORDPT
WORD1
WORD2
WORD3
CHANGE
XINC
YINC
NUMWORD
SENDST
TSTATUS
MTYPE
GTEMP
TRACKS
BTEMP
BUTSTAT

000
001
002
003
004
005
006
007
008
OOA
OOB
OOC
OOD
OOE
OOF

Word Pointer
Buffer to Store Report
Buffer
Buffer
Movement or Button Change
X Direction Counter
Y Direction Counter
Number of Bytes to Send
Serial Protocol State
Counter Status
Mouse Type
Track Input from G Port
Previous Track Status
Button Input from L Port
Previous Button Status

APPENDIX B-SUBROUTINE SUMMARY
Subroutine
MLOOP
SENSOR
INTRP
SRPTUS
SRPTMS
SDATA

Location
03D
077
OFF
136
16C
191

SY2RPT
BUTUS
BUTMS

101
200
210

Function
Main Program Loop
Sample Photo-Transistor Input
Interrupt Service Routines
Set Up Report for Microsoft
Set Up 1st 3 Bytes Report for Mouse Systems
Drive Data Transmission Pin According to Bit
Value of Report
Set Up Last 2 Bytes Report for Mouse Systems
Sample Button Input for Microsoft
Sample Button Input for Mouse Systems

2-152

»
z

APPENDIX C-SYSTEM SCHEMATIC, SYSTEM

Flowchart, complete program listing.

lOOk

(X)

.......

+5V

1 R7 2
82k

+5V
lW

1
Rll
10k
2

2 R8 1
82k

q22PF'
Cl

50V

1 R12 2
10k

50V

2 R13 1

1 R9 2
10k
82k

2
R14
820

2 RIO 1
82k

LtD

LED

I LllJLl/lU'~~-O

Note 1: All diodes are 1N4148.
Note 2: All resistor values are in ohms, 5%, YaW.
Note: Unless otherwised specified

FIGURE 3. System Schematic

2-153

,...

:2:

Flowchart for Mouse Systems and Microsoft Mouse

205
206
201
20B
209 0061 BDD213
210 006A 06
211
212
m 006B 54
214 006C 7F
215 0060 SCOFB1
216 0010 BE
211
21B
219 0011 54
220 0012 6F
221 0013 scoroo
222 0016 BE
223
224
225
226
221
22B
229
230
231
232
233 0011 53
234 0018 9006
235 OOJA SCDOOr
236 0010 BO
231 om 953c
23B OOBO A6
239
240
241
242
243
244
245
246
241
24B
249
250
251
252 00B1 M
253 00B2 BO
254 00B3 80
255 00B4 9503

SEL&CT I(XJSE UP!:
itt tt ****tt *tt *tt** ********•• aaa*******a** *****tt a**

CD
......

SELECT:
IFBIT
JP

SII, PORTLP
SYM

B, 'MTYPE
USOFT, [B)
BUTSTAT,'OB7

i (HTYPE) IS MICROSOFT
i NO KEY PRESSED

B, 'MTYPE
USOFT, [B)
BUTSTAT,'O

i (MTYPE) IS KXlSE
i NO KEY PRESSED

iCHECK JUHPER

USM:
SBIT
lD

HOOSE

RET
SYM:
lD

RBIT
1D
RET

SYSTEMS

itt *** *U U U U U ***a*a. aaa*a*a. aa*a***tt ****** **** *
SAMPLE SENSOR INPUT
INC OR DEC THE POS ITIOO
-121 IS USED INSTEAD OF -12B IN CHECKING
NEGATIVE GOING POSITION SO THAT BOTH
MICROSOFT AND MOUSE SYSTEMS FIT IN
i **********au* U *** ***. **a*a*aa*****at **** aU aa** a*
SENSOR:
lD
lD
lD

RRC
AND

CCII

B, 'GTEHP
A,PORTGP
PORTlD, ,or
A
A,'03C
A, [BI

(NOT USED) TURN OFr LED

i G5 ,G4,G3,G2
i (GTEHP)

(TRKl, TRKO)t-l
0 1
1
1
1
0
0
0

(TRKl, TRKO)t
0 0
0 1
1 1
1
0

A, [B+)
A
A
A,'03

; (GTEMP) x IN 3,2

CII

RRC
RRC
AND

iGET X TRACKS
TL/OO/l0799-11

2-159

,...

:2:

256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
214
215
216
217
278
279
280
281
282
283
284
285
286
2B1
288
289
290
291
292
293
294
295
296
291
29B
299
300
301
302
303
304
305
306

OR
OR

0086 87
0087 9780
0089 AS
OOBA OF

A, [B)
A,'OBO

:OVERIAY IIITH PREVIOUS (TRACKS)
: X KJVEHENT TABLE

JID
NOISEX: JP

YDIR

INCX:
OOBB 9005
OOBO BA
OOBE 03

A, XINC
A

I1J
INC
JP

COO

I1J
DEC

A,XINC
A

IFEO
JP
X
I1J
SBIT
I1J

A,'80
YDIR
A,XlNe
B, 'CHANGE
RPT, [B)
B, 'TRACKS
B, 'TRACKS
A, (B-)
A
A
A
A
A, ,oeD
A, [B)
A
A, ,oeD

:CHECK IF LIMIT IS REACHED

DECX:
OOBF 9005
0091 8B

:CHECK FOR LIMIT

COHX:
0092
0094
0095
0097
0098
0099

9250
05
9C05
5B
18
52

009A
009B
009C
0090
009E
009F
OOAD
00A2
00A3
OOM
OOM

52
AB
65
BO
BO
BO
95CO
B1
65

I1J
I1J
SIIAP
RRC
RRC
RRC
AND
OR
SWAP
OR

JID

:YES 00 NOTHING
:ELSE NEil POSITION
; (CHANGE)

YDIR:

nco

: (TRACKS) Y IN 5,4

: (GTEMP)
:Y KJVEHENT TABLE

.=080

OOBO
KJVEMX:
0080
0081
0082
00B3
00B4
00B5
00B6
00B7
OOBS
0089
OOBA
OOBB

SA
8F
SB
SA
8B
8A
8A
8F
8F
8A
8A
8B
oose 8A
OOBD BB
OOBE 8F

.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADDR
.ADOR
.ADDR
.ADOR
.ADDR
.ADOR
.ADDR
.ADDR
.ADOR

NOISEX
DEC X
INCX
NOISEX
INCX
NOISEX
NOISEX
OECX
DEC X
NOISEX
NOISEX
INeX
NOISEX
INCX
DECX

;0
;1
;2
;3
;4
:5
;6
;7
;8
;9
;A
;8
;C

;D
;E
TL/DD/10799-12

2-160

l>
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326

.ADOR

OOBF SA

OOISEX

.=OCO

OOCO

-&.

KlVEI1Y:
OOCO
OOCI
OOC2
OOC3
OOC4
OOCS
OOC6
OOC7
OOCS
OOC9
OOCA
OOCB
OOCC
OOCO
OOCE
OOCF

.ADOR
.ADOR
.ADOR
.ADOR
.ADOR
.ADOR
.ADOR
.ADOR
.ADOR
.ADOR
.ADOR
.ADOR
.ADOR
.ADOR
.ADDR
.ADOR

DO
01
05
DO
05
DO
DO
01
01
DO
DO
05
DO
05
01
DO

OOISEY
INCY
OECY
OOISEY
OEeY
OOISEY
OOISEY
INCY
INCY
OOISEY
OOISEY
OECY
OOISEY
OECY
INCY
NOISEY

;0
;1

;2
;3
;4
;5
;6
;7
;8
;9
;A
:B
;C
;0
;E
;F

327
328
329
330
331
332
333
334
335
336
337
33B
339
340
341
342

0000 OF

NOISEY: JP

ESENS

0001 9006
0003 BA
0004 03

IOCY:

lD
IOC
JP

A, YINC
A
COHY

lD
DEC

A, YINC
A

IFEQ

A,'080
ESENS
A, YINC
B,'CHANGE
RPT, (B]
B,'GTEMP

DECY:
0005 9006
0007 BB
COMY:
0008
OOOA
OOOB
OODO
OOOE
OOOF

9280
05
9C06
5B
78
53

OOEO
OOEI
00E2
OOEJ

53
M
A6
8E

343
344
345
346
347
348
349
350
351
352

JP
X
lD

SBIT
lD

; (CHANGE)

ESENS:

oorr

j53
354
355
356
357 OOFF 9CF4

lD
lD
X
RET

B,'GTEMP
A, (Bf]
A, (B]

: (GTEMP) IN 5,4,1,0
; (TRACKS) NEil TRACK STATUS

.=OFr
; .................................. u ........ uuu.

INTERRUPT ROUTINES
; III HI H H IIIIIH I HH II 1111111111 II II IIH 111111111

INTRP: X

A,ASAVE
TLIDD/10799-13

2-161

..-

co
U)
Z

358
359
360
361
362
363
364
365
366
367
368
369
370

0101
0104
0105
0108

BOEF7S
07
BOEF73
OA

TPND,PSW
TINTR
IPND,PSII
XINTR

ID
RETI

A, ASAVE

INTRET:
0109 9DF4
010B 8F

; INTERRUPT RETURN

; tt tttt u u UU Ult ttUttt t t t u Ut**ttt tt tt ttU t Ut t

TIMER INTERRUPT
DPDATE ALL THE COUNTERS

371

; tt tltt ttu u u u u UU Utt u u t Ut ttU t ttt tttt tU t t

372
373
374 OlOC BOEF6D
375 010F BOOA7A
376 0112 F6
377
378

TINTR:
RBIT
SBIT
JP

TPND,PSii
TBAOB, TSTATUS
INTRET

; SET BIT IN TSTATUS

; u t t tt Utt t Ut ttU Uti Utt ttt t U t t t t tt tt tt tttt t ttt III t tt t

m
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400

IFBIT
JP
IFBIT
JP

EXTERNAL INTERRUPT
RESPONSE TO RTS ro;GLING
BY SENDING AN ' 1'1' 4DH
;ttttttttttttttltttttttllttttttttlltlltttttttttttltttttttt

0113
0116
0119
OllA

BOEF6B
BOOB71
01
EE

OllB Be01FF
OIlE Be024D
0121 Be0702

XINTR: RBIT
IFBIT
JP
JP
XINTRl:
ID
ID
ID

IPND, PSW
DSOFT, HTYPE
XINTR1
INTRET
l«)RDl,IOFF
l«)RD2, I'M'
NOMl«)RD,I02

;ONLY IF MICROSOFT PROTOCOL
;CONTINUE
;ELSE DO NOTHING
;ALL MARK

0124 9D08
0126 9200
0128 05

ID
IF£O
JP

A,SENDST
A,IO
RTSR2

0129 BeOOOl

LD
JP

l«)RDPT, ,;,uRDl
INTRET

; FAKE CONTINUE LAST CHAR

ID
ID
JP

l«)RDPT,I;,uRD2
SENDST,IOI
INTRET

;'1'1' ONLY

om 2109

m om BeOO02

402 om Be0801
403 0134 2109
404
405
406
407
408

; IF IDLE, SEND ' 1'1'

RTSR2:

tt tttt u u u u Utt U tt u u u u Uti U U t t t t tU uUt. t t. ut

SUBROUTINE SET UP REPORT ' SRPT' FOR MICROSOFT
------------CHANGE OF STATUS DETECTED
TL/DD/10799-14

2-162

409

410
4ll
412
413
414
415
416

0)
Q)

; ** 1** I ** U I I ** ** U I U I I I I I I I I I I I I I U ** I UI I Itt tt ** U ** Itt

.....

SRPTUS:
0136
0137
0138
0139

5B
70
01
8E

ID
1FBIT
JP
RET

B, 'CHANGE
RPT,IB}
SROSI

RBIT

GIE,PSW
B, ,I()RDPT
IBt}, 'WORDI
A,XlNe
A
A
A
A,I03
A,IB]

;X7,X6
; !WORD1)

A, YlNe
A
A, 'OC
A,IB}
A,I040
A, BUTSTAT
A,IBtJ

;Y7, Y6
; !WORD!)
;SET BIT 6
;GET BUTTON STATUS
; !WORDI)

A,XINe
A, '03F
A,IBt}

;XO-X5
; !i/ORD2)
;YO-Y5
; !WORD3)
; !CHANGE) RESET CHANGE OF STATUS
;INC B
; !XINC)
; (YINC)

;EXIT IF NOT CHANGE

SROSl:

4lB
419 0l3A BO EF6 8
420 0130 SF
421 om 9AOI
422 014 0 9005
423 0142 65
424 0143 BO
425 0144 BO
426 0145 9503
427 0147 A6
428
429 0148 9006
430 014A 65
431 014B 950C
432 0140 87
mOl4E9740
434 0150 BOOF87
435 0153 A2

436
437 0154 9005
438
439
440
441
442
443
444
445
446
447

>
Z

SET UP THE 3 I«lRDS FOR REPORTING IF IN IDLE STATE

0156 953F
0158 A2
0159
015B
0150
015E

ID
ID
ID

SWAP
RRC
RRC

AND
X
ID

SWAP
AND
OR
OR
OR
X
ID
AND

;OISABLE INTERRUPT
; !WORDPT) SET I()RD POINTER

9006
953F
A2
68
om M
0160 9ADO
0162 9AOO

ID
ID
ID

A, YlNe
A,103F
A,IBt}
RPT,IB]
A,IB+]
[B+],'O
[B+], '0

449 0164 9A03
450 0166 9EOI

ID
ID

IB+],103
IBJ,IOI

; (NDMI'KlRD) SEND 3 BYTES
; !SENOST) SET TO START BIT STATE

452 0168 BOEF78
453 016B 8E
454

SBIT
RET

GIE,PSii

; ENABLE INTERRUPT

ID
AND

X
RBIT

448

m
.e<

,""

456
457
458
459

!!!tt11t~:'J..11.1.111.L.l1111'.U""""".'.""'U'.'.".'.

SUBROUTINE SET UP REPORT ' SRPT' FOR KlUSE SYSTEMS

--------------- ... -

CHANGE OF STATUS DETECTED
SET UP THE FIRST 3 I«lRDS FOR REPORTING
Tl/OO/l0799-15

2-163

,..

460
461
462
463
464 016C 5B
m 016070
466 om 01
461 Ol6F 8&
468
469
m 0170 BOEF68
m 0113 5F
m 0114 9A01
mom 900F
414 0118 A2

IF IN IDLE STATE

; tI tIti tIti tltiUUtltl ttl t t tit t Itl I til titltltltltl tltt Itt

SRPTI1S:

ID
IFBIT
JP
RET

B, 'CHANGE
RPT, [B)
SRMS1

RBIT
ID
ID
ID
X

GIE,PSI!
B,Il«lRDPT
[B+),liIORDI
A, BOTSTAT
A, [B+)

mom 9005
m 0118 A2

ID
X

A,XINe
A, [B+)

I (iIORD2)

m
480
481
482
483
484
m
486
481
488
489
490
491

m
m

;EXIT IF NO

CH~E

SRMSl:
IDISABLE INTERRUPT
I (iIORDPT) SET l«lRD POINTER .
I (iIORDlI

om
0110
am
am

Al
64
BOom
A2

CLR
SUBC

A, YINC
A, [8+)

IFOR IoIlUSE SYSTEM NEG Y
I (iIORD3)

0182
0183
0184
0185
0181

68
19
AA
9AOO
9AOO

RBIT
S81T
ID
ID
ID

RPT, (8)
SYRPT, [B)
A, [B+)
[B+),IO
[B+),IO

I (CHANGE) RESET CHANGE OF STATUS
I (CHANGE)
IINC 8
I (XIOC)
I (YIOC)

ID
ID

[B+),103
[B),101

I (NUMiIORD) SEND 3 BYTES
; (SENDST) SET TO START BIT STATE

SBIT
RET

GIE,PSI!

IENABLE INTERROPT

0189 9A03
0188 9EOI

492
m 0180 BOm8
494 0190 8E

m
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510

tt tltt tt ttltt tIltititi tttl ttttttt I I It I titt ttl I ttlt tttt tltt

SUBROOTINE TO SEND DATA 'SDATA'
CHECK THE BIT TO SEND AND DRIVE THE OOTPOT TO THE
DES IRED VALUE
SENDST
0
1
2-8
2-9
9-10
10-11

11
12

STATE
IDLE
START BIT
DATA
(FOR IoIlUSE SYSTEMS)
DATA
STOP BIT
STOP BIT (FOR MOOSE SYSTEMS)
NEXT l«lRD
NEXT l«lRD (FOR MOOSE SYSTEMS)
TL/DD/10799-16

2-164

511
512
513
514
SIS
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
5S7
558
559
560
561

>
Z

0)
Q)

;UttitUti Uti UUtttt ttt t ttl t it it tUtti U UU tittttltitU

0191
0192
0193
0194

55
72
01
8E

SOATA: ID
IFBIT
JP
RET

0195
0196
0197
0199
019B

RBIT

ID
ID

B, ITSTATUS
TBAOS, [B]
SOATAI

; (T5TATU5)CHECK IF SAOO RATE TIMER ENDS

SOATAI:
9D08
mo
AS

OR
JID
RET

019C 8E

IOLE:

019D 77
om 16

STAT9: IFBIT
JP
DATAB:

om 9DOO
01Al 9<:FE
01A3
01114
01A5
01A6
01A7
01119
DIM
01AB
OIAC

AO
lIE
BO
A6
DED4
88
7A
89
611

01AD
OlAF
01BO
0lB2

9008
8A
9<:08
8E

TBAOB, [B]
A, [B+]
A,SENDST
A, ,OFO

; (T5TATU5)
; INC B TO (MTYPE)

;EXIT IF IDLE
OSOFT, [B]
STOPB
A,WDROPT
A,B

; (MTYPE)

;B POINTS TO THE illRO

A, [B]
11
A, [B]
B,IPORTGD

IFC
SBIT
IFNC
RBIT

00, [B]

ID
RRC

INC
X
RET

; XHIT LEAST SIG BIT

00, [S]

A,SENDST
A
A,SENDST
;EXIT

01B3 77
01B4 04

STATl1: IFBIT
JP

OSOfT, [B]
NXWDRO

01B5 8OD47A
01B8 F4

STOPB: SBIT
JP

oo,PORTGD
NEXT

0189 9000
01BB 8A

NXWORO: ID
INC

A,WOROPT
A

; (MTYPE)

c, ."~~:; 70

Ol~C ~07e!

Irc~

:S,::~:7"~~

;~;~:·~L.n

OlBF 09
01CO 9C00
01C2 BeOBOI

JP
X
ID

ENDRPT
A,WOROPT
SENOST,IOI

; END OF REPORT

:L~;~

; SEND START BIT
TLlDD/10799-17

2-165

......

STATUS LEOS
INPUT COI.4I.4AND
SWITCHES

Vee
11
12
13
14
15
16
17
18

......
-&.

Vee

LO
Gl

COP820C
L4

LED
DRIVER

10
4

7
DS75492

L7
Vee
DO

COI.4I.4AND
READY
INTERRUPT
PUSHBUTTON

-r

01
25 GO

02
03

11.14

VI.40TOR

1.40TOR
DRIVER

4.15.12.13
23

GND

DS3658

RED

TL/DD/11044-1

FIGURE 1. Schematic Diagram

2-171

,.... r-------------------------------------------------------------------------------------------,
~

......

Program Code Flow Chart

NATIONAL SEMICONDUCTOR CORPORATION
COP800 CROSS ASSEMBLER, REV: 01, 12 OCT 88

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
162
163

0005
0008
OOOB
OOOE
0011
0014
0017
0018
001A
001C
001E
0020
0022

BCEF03
BCD401
BCD53E
BCDC09
BCDI00
BCDOFF
5F
9A09
9AOC
9A06
9E03
0200
BC0700

LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD

.:...
......

PSW,.003
PORTGD,#Ol
PORTGC,'03E
PORTD,#09
PORTLC, .00
PORTLD,#OFF
B, "(SO
[B+),#09
[B+J,'OC
[B+),#06
[B),#03
STPPTR,#OO
FLGREG, #00

;READ, DECODE, AND EXECUTE COMllAND
0025
0028
002A
0020
002F
0032
0033
0036
0038
003A

BD0479
3081
BD0469
9C04
B00470
08
BD0472
3041
305F
EA

003B 308E
0030 BCD401
0040 E4

TOP:

SBIT
JSR
RBIT
IFBIT
JP
IFBIT
JSR
JSR
JP

READY,PORTGD
WAIT
READY , PORTGD
A,CUD
GO,CMD
STOP
MODE,CWO
SSTEP
CONT
TOP

JSR
LD
JP

TMRSET
PORTGD,'Ol
TOP

STOP:

;SINGLE STEP THE UOTOR
308E
BC0410
3081
8A
9CFO
9004
65
950F
8A
9CFl
CO
06
Cl
01
80

MID:

; INIT STEP POINTER
;INIT FLAG REGISTER

s.sss ••••••••••••••••••••••• _.

TURN ON READY FOR NEXT CWD LED
WAIT FOR CMD AND READ CUD
TURN OFF READY FOR NEXT CUD LED
STORE IN CUD REGISTER
IF STOP BIT SET
THEN STOP WOTOR
ELSE CHEK WODE
IF WODE SET THEN GO SINGLE STEP
ELSE GO CONTINUOUS
GO WAIT FOR NEXT COMMAND
STOP THE UOTOR
STOP THE TIMER
TURN OFF ALL LEOS
GO WAIT FOR NEXT CUD

*** ••••••• * •••••••••••••••••••
JSR
LD
JSR
INC

TP2:

;CONFIG PORTG FOR OUTPUTS
;START MOTOR DRIVE VALUE
;CONFIG PORTL FOR INPUTS
;CONFIG PORTL FOR WEAK PULL-UPS
;SETUP UOTOR DRIVE VALUES

(SS)

SSTEP:
0041
0043
0046
0048
0049
004B
0040
004E
0050
0061
0063
0054
0055
0056
0067

;GLOBAL INT ENABLE/EXTINT ENABLE

LD
SWAP
AND
INC
X
ORSZ
JP
ORSZ
JP
RETSK

TMRSET
PORTGD,#010
WAIT
A
A,CREGO
A,ClID
A
A, .OF
A
A,CREGl
CREGO
no
CREGl
002

STOP TIMER
TURN ON SS LED (RST ALL OTHER LEOS)
WAIT FOR CMD BYTE 2 (' STEPS)
ADD 1 TO CORRECT FOR LOOP
STORE .STEPS IN LOBYTE COUNT REG
LOAD HIBYTE • STEPS
WOVE TO LOWER NIBBLE
GET RID OF UPPER BITS
ADD 1 TO CORRECT FOR LOOP
MOVE TO HIBYTE OF COUNT REG
DECR LOBYTE AND IF NOT ZERO
TH~N GO !)O .'. STEP
ELSE DECR HIBYTE AND IF NOT ZERO
THEN GO DO A STEP AND RST LO COUNT
ELSE END OF LOOP
RETURN
TLIOO/11044-5

2·175

oo::t'
~

......
Z

NATIONAL SEMICONDUCTOR CORPORATION
COP800 CROSS ASSEMBLER, REV: D1, 12 OCT 88

c:(

154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204

0058
005A
005C
005E

DOFF
3098
3158
F4

002:
DO:

LD
JSR
JSR
JP

CREGO,IOFF
NXTVAL
DELAY
TP2

jRUN THE MOTOR CONTINUOUSLY
005F
0062
0063
0064
0066
0067
0069
006C
006E
006F
0071
0072
0074
0075
0077
0078
007A
0070
0080

BDEE74
01
03
3148
8E
308E
BCD420
3126
AE
9CEB
AB
9CED
AE
9CEA
AE
9CEC
BDEF7C
BDEE7C
8E

RESET LOBYTE OF COUNTER
STEP THE MOTOR
SLOW THE STEPPING
GO TO TOP OF LOOP
(NS

NON-STOP

CONTINUOUSLY)

;*************** ••• * •••••••••••

CONT:
IFBIT
JP
JP
CHKSPD: JSR
RET
SETGO: JSR
LD
JSR
LD
X
LD
X
LD
X
LD
X
SBIT
SBIT
RET

TRUN,CNTRL
CHKSPD
SETGO
SPEED
TMRSET
PORTGD,1020
TIMVAL
A, [B1
A,TMRHI
A, [B-1
A,TAUHI
A, [B1
A,TMRLO
A, [B)
A,TAULO
ENTI,PSW
TRUN,CNTRL

jlF MOTOR ALREADY RUNNING NS
jTHEN CHECK THE CURRENT SPEED
jELSE GO START THE MOTOR
jCOMPARE INPUT WITH ACTUAL SPD
jlF EQUAL RET ELSE RESTART MOTOR
jSTOP THE TIMER
jTURN ON CONTINUOUS LED
jCALCULATE TIMER (SPEED) VALUE
jLOAD A WITH TVALI
jMOVE SPEED VAL INTO TIMER
jLOAD A WITH TVALI POINT TO TVALO
jMOVE SPEED VAL INTO AUTORELOAD REG
jLOAD A WITH TVALO
jYOVE SPEED VAL INTO TIYER
jLOAD A WITH TVALO
jENABLE TIMER INTERRUPT
jSTART THE TIMER
JRET TO MAIN AND WAIT FOR TMRINT

jSUPPORT ROUTINES ••••••••••••••••••••••••••••••••••••••••••• ** •••• * •• *
WAIT:
0081
0084
0085
0086
0089
008B
008D

BD0770
01
FB
BD0768
9DD2
98FF
8E

OUT:

TMRSET:
008E
0091
0094
0097

BDEE6C
BDEF6D
BDEF6C
8E

;

..............................

jWAIT FOR AN EXTERNAL INTERRUPT TO SIGNAL AN INCO .... ING COMMAND
jREAD THE INCO.... ING CO....AND FROY PORT L
IFBIT
INT,FLGREG
jlF EXTERNAL INTERRUPT OCCURED
JP
OUT
jTHEN JUMP OUT OF LOOP
JP
WAIT
jELSE CONTINUE TO WAIT
RBIT
INT,FLGREG
jRESET EXTERNAL INTERRUPT FLAG
LD
A,PORTLP
jREAD INCOMWING COMMAND
XOR
A,IOFF
jCOYPLEMENT INCO.... ING CO....AND
RET
jRETURN CO.... AND IN ACC

; ••••••••••••••• ** •••••••••••••
jRESET THE TIMER
RBIT
TRUN,CNTRL
RBIT
TPND,PSW
RBIT
ENTI,PS"
RET

STOP THE TIMER
RESET THE TIMER PENDING BIT
DISABLE TIMER INTERRUPT

TL/DD/ll044-6

2-176

»
Z

NATIONAL SEMICONDUCTOR CORPORATION
COP800 CROSS ASSEMBLER, REV: D1, 12 OCT 88

..!.J
......
~

205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
260
~51

:***-****** •• **** •• ************

NXTVAL:
0098
009A
009C
009F
OOAO
OOAl
00A2
00A3
00A5
00A7
00A9
OOAB
OOAD
OOAE
OOBO
OOBl
00B2
00B3
00B4
00B6
00B7

9DF2
DED4
8D0471
11
6A
7B
8B
92FF
9803
9CF2
9DF2
9CFE
AE
9CDC
8E
6B
7A
8A
9204
64
EF

OOFF
OOFF
0102
0103
0106
0107
010A

BDEF75
08
BDEF73
16
BDEF78
80

010B
0100
010F
0111
0114
0116
0118
011A

9CF9
90FE
9CFA
BDEF6D
3098
9DFA
9CFE
9DF9

DPTR:

WRVAL:

IPTR:

iSEND THE NEXT DRIVE VALUE TO STEP THE MOTOR ONE STEP IN THE
iAPPROPRIATE DIRECTION (CW OR CCW)
iLOAD STEP VALUE POINTER
LD
A,STPPTR
LD
iPOINT TO PORT G
B, 'PORTGD
IFBIT
DIR,CMO
i IF CLOCKWISE
JP
iTHEN GO INCREMENT POINTER
IPTR
CW, [B)
RBIT
iELSE RST CW LED
SBlT
CCW,[B]
iTURN ON CCW LED
DEC
A
iAND DECREMENT POINTER
IFEQ
iIF OFF BOTTOM OF STEPS
A, 'OFF
LD
A,103
iTHEN LOOP TO TOP OF STEPS
iA -) STPPTR (SAVE NEW STPPTR)
X
A,STPPTR
LD
A,STPPTR
i[STPPTR] -) PORTD (LOOKUP VAL)
X
A,B
A, [B)
LD
X
A,PORTD
iWRITE STEP VALUE TO MOTOR
RET
CCW, [B)
RBIT
iTURN OFF CCW LED
SBlT
CW, [B)
iTURN ON CW LED
INC
A
iiNCREMENT THE STEP POINTER
IFEQ
A,104
ilF OFF TOP OF STEPS
CLR
iTHEN LOOP TO BOTTOM OF STEPS
A
JP
WRVAL
iGO WRITE VALUE TO MOTOR

ilNTERRUPT HANDLERS
= OFF
i""""""'*""'*"""""
iBRANCH TO THE APPROPRIATE INTERRUPT HANDLER
IFBIT
TPND,PSW
iTIUER UNDERFLOW
JP
TIdRINT
IFBIT
IPND,PSW
iEXTERNAL INTERRUPT
JP
EXTINT
S81T
iSOFTWARE TRAP
GIE,PSW
RETSK

i"""""""""""'****'*'

TMRINT:

O!!C

iRESET THE TIUER INTERRUPT PENDING BIT AND STEP THE MOTOR
A,OF9
X
iCONTEXT SAVE ROUTINE
LO
A,B
X
A,OFA
RBIT
TPND,PSW
RESET PENDING BIT
JSR
NXTVAL
STEP THE MOTOR
LD
A,OFA
CONTEXT RESTORE ROUTINE
X
A,B
LD
A,OF9

.. .....

" ...

262
253
264 0110 B00778
266 0120 3158

EXTINT:
SBlT
JSR

INT,FLGREG
DELAY

*** ••••• *.* •• *.** ••• *.* •• * ••••
SET INTERRUPT OCCURED FLAG
WAlT
TL/DD/11044-7

2-177

r::

:Z
«

NATIONAL SEMICONDUCTOR CORPORATION
COP800 CROSS ASSEMBLER, REV: 01, 12 OCT 88
256
257
258
259
260
261
262
283
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306

0122 BOEF6B
0125 8F

RBIT
RETI

IPND,PSW

:RESET PENDING BIT

:SUPPORT ROUTINES CONTINUED
TIWVAL:

0126
0128
012B
012C
012F
0130
0133
0134
0138
0138
0139
013B
013D
013E
0140
0142
0143
0145
0147

B00475
OE
B00416
05
9A02
9E08
8E
9A88
9E13
8E
9A18
9E27
8E
9A54
9E9C
8E

0148
014A
014C
014F
0160
0151
0153
0156
0157

3126
9D14
BDEC82
01
80
9D16
BDED82
8E
8D

DE14
BOO474
17

: ••••••••••••••••••••••••••••••
:Ourlng continuous operation, the motor Is stepped once every
:tlmer underflow. Therefore, a timer value Is calculated that will
:produce tllller underflows every X microseconds causing the motor
: to atep Xsteps/second.
:For example: To step 100 times per second.
microseconds/step z 1000000uS/lec x lsec/l00steps = 10000
10000uS/step • 02718Hex uS/step
luS • one count down of the timer
Therefore, load the timer with 02118H lor 100 steps/sec.

LD
IFBIT
JP
IFBIT
JP
IFBIT
JP
FASTER: LO
LD
RET
FAST:
LD
LD
RET
SLOW:
LD
LD
RET
SLOWER: LD
LD
RET
SPEED:

TSTHI:

B,nVALO
4,CND
SLOWER
5,CND
SLOW
8,CND
FAST
[B+],102
[B],108

:POINT TO STORAGE FOR TIWVAL
:IF LOWEST SPEED BIT SET
:THEN USE SLOWEST SPEED
:IF SECOND LOWEST SPD BIT SET
:THEN USE SLOW SPEED
:IF SECOND HIGHEST SPD BIT SET
:THEN USE FAST SPEED
:ELSE USE FASTEST SPEED
:400steps/sec = 2rev/sec

[B+],1088
[B],1013

:200steps/sec

[B+],I018
[B],1027

:100steps/sec

[B+], 1054
[B],109C

:25steps/sec

1rev/sec

=
=

.5rev/sec

.125rev/aec

: * ••• ** •••••• ** ••••••• ::a . . . . . . . . .
:CONPARE CURRENT MOTOR SPEED WITH DESIRED MOTOR SPEED
JSR
TINVAL
:CALCULATED DESIRED SPEED VAL
LD
A,TVALO
IFEQ
A,TAULO
:IF DESIRED LBYTE EQUALS CURRENT LBYTE
JP
TSTHI
:THEN GO TEST HI-BYTE
RETSK
;ELSE NOT EQUAL RETURN AND SKIP
LD
A,TVALI
IFEQ
A,TAUHI
:IF HI-BYTE EQUALS CURRENT HI-BYTE
RET
:THEN DESIRED = CURRENT RETURN
RETSK
:ELSE DESIRED != CURRENT RET & SKIP

DELAY:
: INSERT A DELAY
TL/DD/ll044-8

2-178

NATIONAL SEMICONDUCTOR CORPORATION
COP8DD CROSS ASSEMBLER, REV: D1, 12 OCT 88

307
308
309
310
311
312
313
314
315

0158
015A
015C
0150
015E
016F
0160

0301
04H
C4
FE
C3
FA
8E

OLYl :
OLY2:

LO
LO
ORSZ
JP
ORSZ
JP
RET

:FOR SINGLE STEP & EXTINT DEBOUNCE
:APPROX .256.S X 6

OF3.'01
OF4.'OFF
OF4
OLY2
OF3
OLYl

.ENO
TL/DD/11044-9

B
CWO
CREGl
OLYl
OPTR
FAST
GO
IPTR
MSl
NS
PORTGC
PORTLC
READY
SLOWER
SSTEP
TAUHI
TC3
TMRLO
TPNO
TVALl

OOFE
0004
OOFl
015A
OOAO
0139
0000
OOBl
0001
0005
0005
0001
0001
0143
0041
OOED
0005
OOEA
0005
0016

BUSY
CNTRL
Cif
OLY2
ENI
FASTER
IEOG
UIO
MS2
NXTVAL
PORTGO
PORTLO
SETGO
SP
STEPS
TAULO
TUIVAL
TMRSET
TRUN
WAIT

0002
OOEE
0002
015C
0001
0134
0002
0055
0002
0098
0004
0000
0087
OOFO
0005
OOEC
0126
008E
0004
0081

CCW
CONT
OELAY
00
ENTI
FLGREG
INT
UOOE
MS3
OUT
PORTGP
PORTLP
SIOR
SPEED
STOP
TCl
TWRHI
TOP
TSTHI
WRVAL

0003
006F
0168
005A
0004
0007
0000
0002
0003
0088
0006
0002
00E9
0148
003B
0007
OOEB
0025
0151
00A7

CHKSPO
CREGO
OIR
D02
EXTINT
GIE
IPNO
!.ISO
WSEL
PORTO
PORTI
PSW
SLOW
SS
STPPTR
TC2
TWRINT
TP2
TVALO
X

0064
OOFO
0001
0058
0110
0000
0003
0000
0003
OOOC
0007
OOEF
013E
0004
00F2
0008
010B
0053
0014
OOFC
TLlDD/11044-10

MACRO TABLE

NO WARNING LINES
NO ERROR LINES
282

ROW BYTES USED

SOURCE CHECKSUM
OBJECT CHECKSUM

80CO

= 0520

INPUT
FILE C:WOTOR.WAC
LISTING FILE C:MOTOR.PRN
C~J~Ci

r,L~

C:.u,un.L.

TL/DD/11044-11

2·179

MF2 Compatible Keyboard
with COPS Microcontrollers

National Semiconductor
Application Note 734
Volker Soffel

ABSTRACT

AT, PS/2). In the meantime it has become an industry standard and today nearly all PCs have an MF2 compatible keyboard. As the name suggests, this keyboard features all operation modes which are necessary to stay compatible with
the older XT and AT type keyboards. In the following chapters the features and functions of an MF2 keyboard as well
as their implementation with a COP8 microcontroller are described.

This application note describes the implementation of an
IBM MF2 compatible keyboard with National Semiconductor's COP888CL or COP943C/COP880CL microcontrollers.
Two different solutions have been developed. One solution,
suitable for laptop/notebook keyboards is based on. the
COP888CL with special power saving techniques. The other
for most price competitive standard desktop keyboards is
based on the COP943C/COP880C microcontrollers. The
same principles can be applied to all types of keyboards or
data input devices.

FEATURES
• Single chip solution
• Low cost R/C or ceramic oscillator optional
• LED direct drive capability
• I/Os with software programmable on chip pull-ups
• Current saving M2CMOS technology
• Multi-input wakeup and HALT mode for further power
consumption reduction (COP888CL only)
• Software key rollover

MF2 KEYBOARD KEY-LAYOUT
Figure 1 shows the key layout of the U.S. version of an MF2
keyboard. Its outer appearance is characterized by 101 keys
(102 for some countries), a separate cursor and numeric
key pad, and 12 function keys in the upper row. The keyboard sends a "make" code if a key is depressed and a
"break" code if the key is released. These make and break
codes are independent of any country-specific keyboard
layouts, which means they are independent of the symbols
printed on the keys. These codes are solely determined by
the physical position of a key on the keyboard. The physical
position of a key on an MF2 keyboard is defined by its assigned key number, which is shown in Figure 1.

• Schmitt triggers on keyboard data and clock lines

HARDWARE

INTRODUCTION

Laptop/Notebook Keyboard With COP888CL

The expression MF2 keyboard stands for multi-functional
keyboard version 2. This type of keyboard was first developed and defined by IBM for use with all types of PC (XT,

Figure 2 shows the schematics of an MF2 keyboard with a
COP888CL microcontroller. The G, C and L ports of the
COP888CL are software programmable I/Os and can be
programmed either as TRI-STATE® inputs, inputs with weak
pull-up, push-pull output low, or push-pull output high.

k8Y--.ffD1}

keynUmber~

rrr;n

/:lil'
01190 . . 95 Vl00 105
7181191

'9r ~·······ror

141 J 51
92

102 106

12Jl.!J

98··103 tnt.

1-99104 108
TLlDD/ll091-10

FIGURE 1. MF2 Keyboard U.S. Layout

2-180

Vee

(Ho~

Dlf

l(Hote 1)
=?C2

+C3

.381

~
~

.J1.

Vee
GHO
10
11
12
13

~16

...,li

Vee
:

)

...•..•...

. .
~R31 ar§
~

V6
~

f '\7'

..:.

39
GO

R
S W
0
8

Data
Clock

~Rl

-~Cl

Vee

R2
7

42
G3
LO
L1
L2
L3
L4
L5
L6
L7

CKO

44-Pln PLCC
CKI

~Pl

r-<>

06 07

- ~P3

35
Hum
Lock

"'7

1
2
3
4
5

I-

6
col 8

36
Scroll
Lock

.1.
row 1

G5 29 ' ...... 02
~~ 30 I~ 1~03
02 31
I~ ' ...... 04
03 32
I """II, ..... 05
04 33
I~ IA06 row 16

13
14
14
15
5
G6

~ r-oP2

08~ ~~

coil

21
22
23
24
43
44
1
2
C3 41
G2 3
G4 4

COP
BBBCl

2
4

:0-

17
18
19
20
25
26
27
28

C4
C5
C6
C7
CO
Cl
C2

:C6 :C7

Vee

-¥

(Note 4)

r1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

..!.!
J4

Caps
Lock

Vee

(Note 2)
R7:

R81 : R6

11 I 1
4

TL/DD/11091-11

Note 1: C2 (47,.F level off capacitor) can be removed when the power supply ripple < ±10%, 0.5 V/ms.
Note 2: Jumper P1: Mode select: 0

XT-mode, 1

AT-mode. Jumper P2, P3: not used.

Note 3: Care must be taken if there are pullups in the computer system that clock/data line current < 3 mAo
Note 4: Diodes 02-06 should be removed if keyboard has hardware keyrollover (diodes in matrix).

FIGURE 2. MF·2 Keyboard Schematics with a 44·Pin COP888CL

2-181

The microcontroller provides the option of using a low cost
RIC oscillator with frequency variation tight enough to fulfill
the requirements for a keyboard, in addition to the option of
using a crystal or a ceramic clock.

The keyboard is organized as an 8 input by 16 output matrix.
The COP888CL's L port is configured as a weak pull-up
input port, thus allowing the use of the multi-input wakeup
feature. Most of the time the chip is in the current saving
HALT mode (Idd :5: 10 ""A). Any keystroke or a data transmission from the computer will create a high to low transition on one of the L lines, which wakes up the ""C from
HALT mode. After returning from the HALT mode, the keyboard is scanned in order to detect which key is pressed
and the appropriate key code is sent to the computer. This
event-driven keyboard scanning results in lowest possible
current consumption as HALT mode is even entered between successive single keystrokes. The diodes in the
D-lines of the key matrix prevent a high current from being
drawn. When two keys in the same column are pressed, two
outputs could be potentially connected together: one of the
D output lines, which is high and the polled line, which is
pulled low. In this case, excessive current would be drawn
without the protection diodes. These diodes can be omitted
if the keyboard already has decoupling diodes in its matrix
(hardware key rollover). All other matrix lines source current
in the ""A range and there is no need for current limiting
diodes.

The XT or AT/PS-2 operation mode can be selected via a
hardware switch. Additional inputs for customer specific settings are available.
The three LEDs of an MF2 keyboard are driven directly by
three of the COP888CL's high sink D-lines (max. 15 rnA for
each pin), thus eliminating the need for additional LED drivers or transistors.
The keyboard logic generates a Power-On Reset (POR) signal when the power is first applied to the keyboard. After
POR the keyboard performs the Basic Assurance Test
(BAT). The BAT consists of a keyboard controller self-test.
During the BAT, any activity on the data and clock lines is
ignored. The 3 keyboard LEDs are turned on at the beginning and turned off at the end of the BAT. Upon satisfactory
completion of the BAT, the keyboard sends the BAT completion code (hex AA) to the computer and keyboard scanning begins. Any code other than hex AA is interpreted by
the computer as a BAT error.

Desktop Keyboard .wIth COP943C or COP880C

The GO and G3 pins .are used for the keyboard data and
clock lines. The pull-ups on these lines ensure a defined
logic "1" level. The keyboard interface on the computer
side uses open collector drivers and the GO, G3 pins of the
COP888CL are configured as TRI-STATE (Hi-Z) inputs
when a "1" is written to the data or clock line. To output a
logic "0" the ""C pulls the data or clock line low (push-pull
low output). A maximum current of 3 rnA can be sunk into
the data and clock pins. Schmitt triggers on the data and
clock line inputs reduce the risk of errors in the data received by the keyboard.

Figure 3 shows the schematic for an MF2 keyboard with the
COP943C/COP880C. The· only difference compared to
COP888CL solution is that the COP943C/COP880C microcontrollers do not have the multi-input wakeup feature,
which allows an event driven keyboard scanning. The key
matrix is therefore continuously scanned in a loop. With the
COP943C/COP880C solution a part of the I port is used as
the key matrix input. The I port is a TRI-STATE (Hi-Z) input
port (requires external pull-ups).

2-182

Vee

(

Vee

(Note 3) C)
~

~ Rl

(Note 1)

Vee

=fC3

35
GO

341

36
Gl
10
11
12
13
14
15
L6
L7

Vee

==C2

GND

Vee

..........

~ CKO

..i..i

COP
943C
40-Pin DIP

i Q§ ~R2
•

5
2
4
1
3
6

Data
Clock

-~Cl

Vee

7 CKI

:C6 :C7

V~PI .~.

4
G5
5
G6

D3 02
28
Num
Lock

(Note 2)

27
Scroll
Lock

L2
L3
L4
L5
CO
Cl
C2
C3
G2
G3
G4
05
06
D7

9
10
11
12
13
14
23
24

17
18
19
20
21
22
39
40
1
2
37
38
3
30
31
32

ARRI
coil

col 8

~1"71
2
3
4
5
6
7

.!.
row 1

IAD2
1~I ..... D3
"""I...!IID4 row 16

29
Caps
Lock

r1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

J!.

(Note 4)

Vee
R7! !R81 !R6

d±tb
J2

TLIDD/ll091-12

Note 1: C2 (47 /LF level off capacitor) can be removed when the power supply ripple < ± 10%,0.5 V/ms.
Note 2: Jumper Pl: Mode select: 0

XT-mode, 1

AT-mode. Jumper P2: P3: not used.

Note 3: Care must be taken if there are pullups in the computer system that clock/data line current < 3 mAo
Note 4: Diodes 02-04 should be removed if keyboard has hardware keyrollover (diodes in matrix).

FIGURE 3. MF-2 Keyboard Schematic with a 40-Pin COP943C/COP880C

2-183

C")

......

zoCt

r---------------------------------------------------------------------------------------~

Key Matrix Organization

Hex". looking at Figure 1, one can see that key number
"58" belongs to the left "CNTRl" key. Note that the
"SHIFT", "CNTRl" and "AlT" keys are located in their
own matrix lines, separate from all other keys. The reasons
for that will be explained in the chapter "Software Key Rollover".

Figure 4 shows an example of what an MF2 keyswitch matrix could look like. Each key position in the matrix is marked
with its key number.

For example: Key number "58" is located at the key matrix
position number "2" and has the AT-set make code "14

1
C4

5
CO

6
Cl

10
G4

11
G5

15
03

16
04
TL/DD/ll091-13

FIGURE 4. Keyboard Matrix COP888CL AT Code Set

2-184

matrix input lines aro read and the 8-bit input value is compared with the result of the previous scanning of the same
matrix output line (a history of the previous scan is kept in
the /-LC's RAM). Thus the keyboard microcontroller's key
detection routine detects any key change in that matrix output line (key pressed or released) since the previous scan. It
is important to recognize released keys, as the MF2 keyboard not only sends a key's "make" code when the key is
pressed, but also a key's "break" code when the key is
released. Key debouncing is performed by software by making sure that the time between two scans is bigger than the
key bounce time (typically 8 ms).

Code Sets

The MF2 keyboard supports 3 different sets of make and
break codes. Code set 1 is used for XT fPC and PS/2-30
compatible computers. Code set 2 is used for AT and all
other PS/2 models compatible computers and code set 3 is
used for workstations and terminal emulations on the PC.
The country specific keyboard driver on the PC side converts the "key position" codes from the keyboard into the
ASCII codes that correspond to the characters printed on
the keycaps (as long as the right driver is installed on the
PC). Appendix 1 gives a complete overview of the key numbers and their make and break codes for all 3 code sets.
The symbols of the U.S. keyboard layout are only listed for
reference and are different for other country layouts. The
break code for code set 1 is equal to the make code with
the most significant bit set. The make codes preceded with
a "FO Hex" code give the break codes of code sets 2 and 3.

Software Key Rollover

Software key rollover means that no decoupoing diodes are
used in the key switch matrix. However, the keyboard action
is still N key rollover in nature. That is, if N keys are depressd in some sequence and held down, the make code of
these keys is transmitted in that sequence. However, if
three keys from three corners of a rectangle in the key
switching matrix are depressed, a "ghost" key (a key which
is not really pressed) would be created (see Figure 5). To
prevent this, a special algorithm, which checks for such special key combinations, has been implemented into the keyboard software. If a "ghost" key has been detected the keyboard outputs the "key detection error code" and the N key
rollover reverts to a 2 key rollover. To ensure that all 3-key
combinations used on a PC (e.g., CNTRl + AlT + DEL) are
still possible, keyboard manufacturers using this method organize the key switch matrix accordingly (an example is given in Figure 4).

KEYBOARD SOFTWARE

The software of the keyboard microcontroller can be subdivided into the following five main tasks:
• key detection
• software key rollover
• key decoding and encoding
• keycode transmission
• keyboard command set
Key Detection

Key detection is done by scanning the keyboard matrix in
the following way. Sequentially each of the 16 matrix output
lines are pulled low, while all the others are high. The 8

pressed key

@ ghost

~
]

key

Jr-'' ' 'd

FO-49

Typematic

FO-4A

Typematic

Shift(R)

FO-59

Make/Break

Ctrl (L)

FO-14

Make/Break

Alt(L)

FO-11

Make/Break

Space

FO-29

Typematic

Alt(R)

EO-38

EO-B8

EO-11

EO-FO-11

Make

Ctrl(R)

EO-lO

EO-90

EO-14

EO-FO-14

Make

Num Lk

FO-77

Make

7 Home

FO-6C

Make

FO-6B

Make

End

FO-69

Make

FO-75

Make

FO-73

Make

FO-72

Make

Ins

FO-70

Make

100

FO-7C

Make

·101-Keyboard only
··102-Keyboard only

2-197

"1::1'

('I)

......
z

Key Position
and
Symbol

or < NUM Lock On/Shift On>
Table I
(XT and PS/2 30)

Table II
(AT and PS/2 50, 60, 80)

Make

Break

Make

Break

Code

Type

EO-52
EO-53
EO-4B
EO-47
EO-4F
EO-48
EO-50
EO-49
EO-51
EO-4D

EO-D2
EO-D3
EO-CB
EO-C7
EO-CF
EO-C8
EO-DO
EO-C9
EO-D1
EO-CD

EO-70
EO-71
EO-6B
EO-6C
EO-69
EO-75
EO-72
EO-7D
EO-7A
EO-74

EO-FO-70
EO-FO-71
EO-FO-6B
EO-FO-6C
EO-FO-69
EO-FO-75
EO-FO-72
EO-FO-7D
EO-FO-7A
EO-FO-74

67
64
61
6E
65
63
60
6F
6D
6A

Make
Typematic
Typematic
Make
Make
Typematic
Typematic
Make
Make
Typematic

Lock On/Shift Off>

Table I: Make Code = = EO-2A-Make Code
Break Code = = Break Code-EO-AA
Table II: Make Code = = EO-12-Make Code
Break Code = = Break Code EO-FO-12

*. Cursor Pad Key-

Table I: Make Code = EO-AA-Make Code
Break Code = Break Code-EO-2A
Table II: Make Code = EO-FO-12-Make Code
Break Code = Break Code EO-12

2-198

Key Code of "Pause", "PRTSC" and "I" Keys
TABLE I. XT and PS/2 30
Key Position
and Symbols
126

E1-10-45-E1-90-C5

No Break Code (Make Only)

EO-46-EO-C6

No Break Code (Make Only)

Print Screen

EO-2A-EO-37

EO-B7-EO-AA

Shift-"PRTSC"

EO-37

EO-87

Ctrl-"PRTSC"

EO-37

EO-87

Alt-"PRTSC"
95

Break

Ctrl-"Pause"

Pause

124

Make

EO-35

EO-85

EO-AA-EO-35

EO-B5-EO-2A

Shift-"/"

TABLE II. AT and PS/2 50, 60, 80
Key Position
and Symbols
126

Make

Pause

124

E1-14-77-E1-FO-14-FO-77

No Break Code (Make Only)

Ctrl-"Pause"

EO-7E-EO-FO-7E

No Break Code (Make Only)

Print Screen

EO-12-EO-7C

EO-FO-7C-EO-FO-12

Shift-"PRTSC"

EO-7C

EO-FO-7C

Ctrl-"PRTSC"

EO-7C

EO-FO-7C

Alt-"PRTSC"
95

Break

Shift-"/"

FO-84

EO-4A

EO-FO-4A

EO-FO-12-EO-4A

EO-FO-4A-EO-12

TABLE III. Terminal Mode
Key Position and Symbols

Code

Type

126

Pause

Make

124

Print Screen

Make

APPENDIX II. REFERENCES
1. IBM Technical Reference Manuals XT, AT and PS/2
2. Chico ny, Chicony Keyboards General Specification, 1988
3. C' T Magazin fuer Computertechnik, No.6, 1988, pages 148ft. No.7, 1988, pages 178ft. Martin Gerdes, "Knoepfchen,
Knoepfchen"

2-199

National Semiconductor
Application Note 739
Michelle Giles

RS-232C Interface with
COP800
INTRODUCTION
This application note describes an implementation of the
RS-232C interface with a COP888CG. The COP888CG 8-bit
microcontroller features three 16-bit timer/counters,
MICROWIRE/PLUSTM Serial I/O, multi-source vectored interrupt capability, two comparators, a full duplex UART, and
two power saving modes (HALT and IDLE). The COP888CG
feature set allows for efficient handling of RS-232C hardware handshaking and serial data transmission/reception.
SYSTEM OVERVIEW

In this application, a COP888CG is connected to a terminal
using the standard RS-232C interface. The serial port of the
terminal is attached to the COP888CG interface hardware
using a standard ribbon cable with D8-25.connectors on
either end. The terminal keyboard transmits ASCII characters via the cable to the COP888CG interface. All characters
received by the COP888CG are echoed back to the terminal
screen. If the COP888CG detects a parity or framing error, it
transmits an error message back to the terminal screen.
HARDWARE DESCRIPTION
The COP888CG features used in this application include the
user programmable UART, the 8-bit configurable L PORT,
and vectored interrupts. In addition to the COP888CG, the
RS-232C interface requires a DS14C88 driver and a
DS14C89A receiver. The DS14C88 converts TIL/CMOS
level signals to RS-232C defined levels and the DS14C89A
does the opposite. Figure 1 contains a diagram of the
COP888CG interface hardware.

The COP888CG is configured as data communications
equipment (DCE) and the terminal is assumed to be data
terminal equipment (DTE). The following RS-232C signals
are used to communicate between the COP888CG (DCE)
and the terminal (DTE):
RS-232C Signal Name

Signal Origin

TxD (Transmit Data)
RxD (Receive Data)
CTS (Clear To Send)
RTS (Request To Send)
DSR (Data Set Ready)
DTR (Data Terminal Ready)
DCD (Data Carrier Detect)

DTE
DCE
DCE
DTE
DCE
DTE
DCE

. The terminal is setup to interface with the COP888CG by
selecting the 9600 baud, 7 bits/character, odd parity and
one stop bit options. The local echo back of characters is
disabled to allow the COP888CG to perform the echo back
function. The terminal is also configured to use the hardware control signals (CTS, DSR, RTS, DTR) for handshaking.
SOFTWARE DESCRIPTION

The software for this application consists of an initialization
routine, several interrupt routines, and a disable routine.
These routines handle RS-232Chandshaking, transmitting
and receiving of characters, error checking, and echoing
back of received characters. Figures 2 thru 5 contain flowcharts of the routines. The complete code is given at the
end of this application note.
The initialization routine configures the UART, initializes the
transmit/receive data buffer, and enables the 8-bit L PORT
handling of RS-232C control signals. In this particular example, the UART is configured to operate at 9600 8AUD in full
duplex, asynchronous mode. The framing format is chosen
to be: 7 bits/character, odd parity, and one stop bit. Different baud rates, modes of operation, and framing formats
may be selected by setting the ENUCMD, ENUICMD,
8AUDVAL and PSRVAL constants located at the beginning
of the code to alternative values. (Refer to the COP888CG
data sheet or COP888 Family User's Manual for details on
configuring the UART.) Each RS-232C control signal is assigned to an L PORT pin. Pins LO, L2, L5 and L6 are configured as outputs for the DCD, TxD, CTS and DSR signals,
respectively. Pins L3, L4 and L7 are configured as inputs for
TxD, RTS and DTR, respectively. The transmit/receive data
buffer is a circular buffer whose location and size is selected
by setting the START and END constants located at the
beginning of the program. The initialization routine sets up
the buffer based on these constants.
The interrupt routines respond to transmit buffer empty, receivebuffer full, and L PORT interrupts. A generic context
switching routine is used for entering and exiting all interrupts. This routine saves the contents of the accumulator,
the PSW register and the 8 pointer before vectoring to the
appropriate interrupt routine. It also restores the contents of
saved registers before a return from interrupt is executed.

Five general purpose I/O pins on the COP888CG L PORT
are used for the control signals CTS, DSR, DCD, RTS and
DTR. Two additional L PORT pins are used for TxD and
RxD. These two general purpose pins are configured for
their alternate functions, UART transmit (TDX) and UART
receive (RDX). According to the RS-232C interface standard, DCE transmits data to DTE on RxD and receives data
from DTE on TxD. Therefore, the UART transmit data pin
(TDX) is used for the RS-232C receive data signal (RxD)
and the UART receive data pin (RDX) is used for the RS232C transmit data signal (TxD). In this example, all handshaking between DCE and DTE is performed in hardware.

The UART transmitter interrupt is called when the transmit
buffer empty flag (T8MT) is set. This routine checks for active RTS and DTR control signals. If both signals are active
and there is data to be transmitted, a byte of data is loaded
into the UART transmit buffer. Otherwise, the UART transmitter is disabled.
The L PORT interrupts are used to indicate an active-low
transition of RTS and/or DTR. When both signals are active
(the remote receiver is ready to accept data), this routine
enables the UART transmitter.
The UART receiver interrupt routine is called when the receive buffer full flag (R8FL) is set. This routine reads the

2-200

CONCLUSION

UART receive buffer and checks for errors. If no errors are
detected, the incoming data is placed in the data buffer for
echoing. If errors are detected, an error message is queued
for transmission.

The user configurable UART, multiple external interrupt capabilities, and vectored interrupt scheme of the COP888CG
microcontroller allow for an efficient implementation of the
RS-232C interface standard. This application note shows
how the COP888CG may be configured for connection to a
terminal using these features. However, the code for this
application can be easily adapted to other applications requiring different baud rates or framing formats, connection
to a modem (DCE), separate transmit and receive buffers,
incoming command decoding and/or handling of character
strings. The versatility of the RS-232C standard and the
COP888CG provides a means to develop practical solutions
for many applications.

The receiver interrupt disables the remote transmitter by deactivating CTS whenever the transmit/receive data buffer is
almost full. This action prevents the data buffer from overflowing. Note that CTS is turned off before the buffer is completely full to insure buffer space will exist for storing characters which are in the process of being sent when CTS is
deactivated.
The disable routine clears the UART control registers, disables the L PORT interrupts, and de-activates the RS-232C
control signals.

~
OB-25
CONNECTOR

+12V
LO
L2 (TDX)

OCO

L3 (ROX)
L4
L7

RXO

9
CTS
y

OS14C88

OSR

OCO

RXO

CTS

OSR

[i3
7

TXO

fiO
12

COP888CG
L6

2
4

1
H-12V

RTS

3
5

2
NC6 OS14C89A
5

~!C-

TER~INAL

~
1

9
NC7

RTS
~

~
FIGURE 1. Interface Diagram

2-201

TXO

~
CABLE TO

+5V
3

OTR

2
~

TLIDD/11110-1

RECEIVE INTERRUPT
VECTOR TO
1 - - - - - - - - - 1 APPROPRIATE
ROUTINE

TRANSMIT INTERRUPT
C

• - - - - - - - - - - - - - - - - - .Ir - - - - - - - - - - - - - - - - _.

TL/DD/11110-2

FIGURE 2. Main Program Flow

2-202

READ DATA rROt.4 RBur
STORE DATA IN DATA BurFER
INCREt.4ENT DATA BUFFER TAIL PTR

PLACE 'ERROR' IN DATA BUFrER
INCREt.4ENT TAIL POINTER
SAVE NEW TAIL POINTER
Tl/DD/llll0-3

FIGURE 3. Receiver Interrupt Routine

2-203

YES

READ DATA FROM DATA BUFFER
STORE DATA IN TBUF
INCREMENT DATA BUFFER HEAD PTR

SET HEAD PTR
TO START OF
DATA BUFFER

DISABLE TRANSMITTER

TL/DD/11110-4

FIGURE 4. Transmitter Interrupt Routine

2-204

TLIDDI 1111 0-5

FIGURE 5. L Port Interrupt Routine

2-205

C")

r--

NATIONAL SEMICONDUCTOR CORPORATION
COP800 CROSS ASSEMBLER, REV:D1, 12 OCT 88

154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193

011E
0120
0122
0124
0125
0127
012A
012C
012D
012F
0131
0133
0135
0137
0138
013B
013C
013E
0140
0142
0145

9DIF
9CFE
9DB9
A2
9DBB
BDBC78
60E0
lA
9DFE
921E
9810
9CIF
9DIE
Al
BDIF81
89
940E
9303
2107
BDD07D
2107

0147
014A
014C
014E
0150
0152
0154
0156
0158

BCIE10
9F10
6020
9A50
6040
9A46
6080
9A44
9A20

1~'} ~1~:1 ~n~5

195
196
197
198
199
200
201
202
203
204

015C
015E
0160
0162
0164
0166
0168
016A
016C

9A52
9A52
9A4F
9A52
9A0A
9A0D
9DFE
9C1F
2107

.......

iUART RECEIVE INTERRUPT
The UART receive interrupt does the following:
1. Reads the received data
2. Checks for receiver errors
3. If no errors detected, places the received data in
the transmi t /recei ve buffer and enables the transmitter.
4. If errors detected, the transmit/receive buffer is cleared
of ALL data and an error nlessage is placed in the data buffer.
RCVINT:
iRECEIVER INTERRUPT
LD
A, TAIL
iGET TAIL POINTER
X
A,B
LD
A, RBUF
iREAD RECEIVED DATA
A, [B+]
iSTORE RECEIVED DATA
X
iREAD ERROR REGISTER
LD
A,ENUR
iENABLE TRANSMITTER INTERRUPT
SBIT
TIE, ENUI
ANDSZ
iCHECK FOR PE, DOE, FE
A,10E0
ERROR
iTHROW DATA AWAY IN BUFFER
JP
iLOAD ACC WITH NEW TAIL PTR
LD
A,B
IFEQ
iIF END OF DATA BUFFER
A,IEND+1
i SET TAIL PTR TO START OF BUFFER
LD
A, ItSTART
iSAVE TAIL PTR
X
A, TAIL
i IS DATA BUFFER FULL?
A, HEAD
LD
SC
SUBC
A, TAIL
iA
HEAD - TAIL
i IF BORROWED -

100

II)

-<
~
z

II)

;:;;

(,.)

>
;:::

z>0

(,.)

DRIVE VOLTAGE VRt.l5
In this example:
VrmsON = 0.707·Vop
VrmsOFF = O.40S·Vop

FIGURE 3. Example Curve: Contrast vs r.m.s. Drive Voltage
.

2-222

TL/DD12076-3

The backplane signals are generated with the voltage steps
av, Vop/2 and Vop at the backplanes; also see Figure 4.

While the backplane control timing continuously repeats after 6 timephases, the segment control depends on the combination of segments just being activated.

Two resistors are necessary for each backplane to establish
all these levels.

TABLE I. Possible Segment ON/OFF Variations

The backplane connection scheme is shown in Figure 1.

Tiphtab Address Segment A Segment B SegmentC

The Vop/2 level is generated by switching the appropriate
COP's port pin to Hi-Z.

off

TIMING CONSIDERATIONS

off

A Refresh cycle is subdivided in 6 timephases. Figure 4
shows the timing for the backplanes during the equal distant
timephases 0 ... 5.

off

The following timing considerations show a simple way how
to establish a discrimination ratio of 1,732.

Backplane Control
~ "REFRESH" --------1
~
CYCLE ~

I0 ~ 1 ~ 2 ~ 3 ~ 4 ~ 5 ~

TlMEPHASE

BP1

V O P [ 8 j '. . . .
VOP/;

···1····r···T···1····[·

. . · . . . .:. . :. .
HJ . . ,.

. .. _.,

•

Each figure shows in the first 3 graphs the constant backplane timing.
The 4th graph from the top shows the segment control timing necessary to switch the 3 segments (SAISB/SC), activated from one pin, in the eight possible ways.

•

_.~

::::

:... : : I·"C·

•

VOP

•

_::

VOP.

VOP/2

BP3

... ,

::
•

BP2

Figure 5 through Figure 12 below show all possible combinations of controlling a "Segment Triple" with help of the 3
backplane connections and one segment pin. The segment
switching has to be done according to the ON/OFF combination required (see also Table I) .

. ..

•

. .r

eE
•

VOP/2:

The 3 lower graphs show the resulting r.m.s. voltages
across the 3 segments (SA, SB, SC).

•

:::

TL/DD12076-4

Note: After timephase 5 is over the backplane control timing starts with
timephase 0 again.

FIGURE 4. Backplane Timing

2-223

~ .---------------------------------------------------------------------------------------~
Lt)

Segment/Backplane Control-Timing

*RC)
To prevent a flickering display one should aim at a minimum
refresh frequency of frefr = 30 Hz. This means an interrupt
frequency of fint = 6 x 30 Hz = 180 Hz. So, the maximum
charge up time Tmax must not exceed 5.5 ms (Tmin
2.78 ms).
.
With the formula:
TL/DD12076-13

RCmax=Tmax/(-ln(1-(VTH/Vcc)max»=5.5 msXO.849

FIGURE 13. Flowchart for Initialization Routine

RC max = S.48 ms

(RCml n

= 5.98 ms)

2. The update routine calculates the port-data for each timephase according to the BCD codes in the RAM locations
'dlglt1' ••• 'dlglt4' and the speCial segments. This routine
is only called if the display image changes.

The maximum RC time-constant is calculated. The minimum
RC time constant can be calculated similarly.
A capacitor in the nF-range should be used (e.g. 68 nFl,
because a bigger one needs too much time to discharge. To
discharge a 68 nF Cap., the GO pin of the device has to be
low for about 40 ,..,s.

2-228

These 3 bits address the 8 bytes of the tiphtab table in
ROM. Each byte of this table contains the time curve for a
segment pin (only 6 bits out of 8 are used).Using this information, the program creates the lists for port D and port L
(pod1st, poI1st). Every byte of this list contains the timing
representatives for the pins 00-03 and LO-L7, to allow
an easy handling of the refresh routine.

The routine converts the BCD code to a list 1st, which is
used by the refresh routine. Figure 14 gives an overview and
illustrates the data flow in this routine.
In Figure 15 the data flow chart is filled with example data
according to the display image in Figure 16.
First the routine creates the seg1st (4 bytes long), which
contains the "on/off" configuration of each segment of the
display. The display has 36 segments but the 4 bytes have
only 32 bits, so the four special segments S1 are stored in
the specbuf location. The bcdsegtab table (in ROM) contains the LOOK-UP data for all possible Hex numbers from
to F.

The external interrupt has to be disabled while the copy
routine is working, because the mixed data of two different
display images would result in improper data on the display.
Figure 17 shows the flowchart of the update routine. The
Flowchart of the convert subroutine is shown in Figure 18.

The routine takes three bits at the beginning of each timephase from the seg1st.

MEMORY REQUIREMENTS
ROM: 152 bytes inc!. look up tables
RAM: 43 bytes (Figure 15 illustrates the RAM locations)

2-229

~
II)

,-------------------------------------------------------------------------------------------,

S2 = 1

:Z
ct

~
.

ErDGA~CB

DIGITl

'0'

DIGIT2
DIGIT3
DIGIT4

'1'
'2'
'3'
'4'

ADDRESS

SPECIAL
SPECBur

SPECIAL SEGt.4ENTS
'51

t--r---r---j SEGLST

TEMP

BCDSEGTAB

'6'
'7'
'8'
'9'
'A'
'B'
'C'

'0'
'E'

'r'
3 BIT ADDRESS

[

!IIIII

TIPHASE

F~: t--------j

PODLST

TlPHTAB

3
4
S
6
7

: -{ t--------j
: -3- t--------j
[ ::: t--------j

, -0- 1---------1 POLLST
: -( 1---------1

F;:

1---------1

: -4-

::s: 1---------1
TIPHASE]
: -0-

,.-_.z...._-, LST

: -( .--------1

: -2- . -______-1

RAM LOCATIONS

: -3- . -______-1
: -4- . -______-1

: -s- .-______-1
• __ ' - -_ _ _ _...J

TL/DD12076-14

FIGURE 14. Data Flow Chart for Update Routine

2-230

»
z

52 = 1

FDGA~C8
'0'
'1'
'A'
'3'

00000000
00000001
00001010
00000101
I

00
01
OA
03

DIGITI
DIGIT2
DIGIT3
DIGIT4

SPECIAL SEGI.IENTS

SI.!
'0
10

110001000188 SPECIAL

ADDRESS

I1 000 1 000 I,!

SPECBUF

~~~~~ E8 SEGLST Ir---'--........,
>1,

031

III

II'

DB
3F

TEMP

3 BIT ADDRESS

TIPHASE

: _0_ OOOOxxxx
: 1 OOOOxxxx
:-2 0111xxxx
~ -311 1 1x x x x
~( 1 1 1 1 x x x x
~_5_ 1000xxxx
,0 10100010
~
1010001 1
: ~2~ 01110110
: 3 01011101
: -4- 01011100
: ~5~ 10001001

-,-

0
1
2
43
4
5
6

Ox PODLST
Ox
7x
Fx
Fx
8x
A2 POLLST
A3
76
50
5C
89

TlPHTAB
':"::"':":::'::

';f'.:'t:fl.;::tH

TIPHASEJ_
:0

:-,: -2: -3: -4: -5-

._-

xxxxOOOO
00101010
xxxxOOOO
00111010
x v x)( 01 1 1
01100111
x x x xliii
1 1010101
x x x xliii
1 1000101
xxxxl000
10011000

xO LST
2A
xO
3A

x7
67
xF
05
xl
C5
xF
98

1::::,:::,:::::,:,:::,:::::,: ::::::::1

ROM LOCATIONS

KAM LUCAIIUN:l

TL/DD12076-15

FIGURE 15. Data Flow Chart for Update Routine

2-231

nnrlrl
nnrln

·o-oo~oo~o.-.

DIGIT - - 1 - - - - 2 - - - - 3 - - - - 4

TLlDD12076-16

FIGURE 16. Display Example
3. The refresh routine is the interrupt service routine of the
external interrupt and is invoked at the beginning of a new
timephase. First the routine discharges the external capacitor and switches the GO/INT pin back to the input mode, to
initialize the next timephase. The backplane ports G2, G4
and G5 and the segment pin ports D and L are updated by
this routine according to the actual timephase. For the backplanes the data are loaded from the bptab table in ROM.
Table II shows how the bptab values are gathered. Figure

For a non flickering display, the refresh frequency must be
30 Hz minimum. One. refresh cycle has six timephases and
is max. 33 ms long. So each timephase is 5.5 ms long. With
an oscillator (CKI) frequency of 2 MHz, one instruction cycle
takes 1/(2 MHz/10) = 5 Ils to execute. During one timephase the controller can execute:
. 5.5 ms/5 Ils = 1100 cycles. So the refresh routine needs
134/1100 = 0.122 = 12.2% of the whole processing time
(in this case).

20 shows the flowchart for the refresh routine.
TIME REQUIREMENTS

With a refresh frequency of 50 Hz the routine needs about
20.1 % of the whole processing time.

The routine runs max. 150 cycles.

The refresh routine needs about 103 ROM bytes.
TABLE II. Phase Values
G2

Portg Data

Hex

Portg Conflg.

Hex

0/0

1/1

XXOOX1XX

1/1

0/0

XX01XOXX

1/1

0/0

XX10XOXX

0/0

0/1

XXOOXOXX

XXOOX1XX

0/0

0/1

0/0

XXOOXOXX

XX01XOXX

0/1

0/0

XXOOXOXX

XX10XOXX

Tlphase

0/0

data/configuration register of portg
0/0 : Hi-Z input
0/1 : output low
111 : output high

2-232

»
z

SUMMARY OF IMPORTANT DATA

LCD type:

3 way multiplexed

Amount of segments:

VOP = (Vee> (range):
Oscillator frequency:

2.5V to 6V
2 MHz (typ.)

Instruction cycle time:
ROM requirements:

5 !-'-s

init routine:
update routine:
refresh routine:
total:
RAM requirements:
permanent use:
temporary use:
stack:
total:

en
w

37 bytes

152 bytes
103 bytes
292 bytes
25 bytes
18 bytes
6 bytes
49 bytes
(also see Figure 19'j

Timer:

not used

External interrupt:

with RC circuit used as time-base generator

Ports 0, L:

used for LCD control

PortG:

3 G-pins are still free for other
purposes +

Port I:

can be used as key-inp.

2-233

TL/DD12076-17

FIGURE 17. Flowchart for Update Routine

2-234

>
Z

cD
c.n
w

TL/DD12076-1B

FIGURE 18. Flowchart for Convert Subroutine

2-235

C")
Il)

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF

LST

SEGLST

10
11
12
13
14
15
16
17
18
19
lA
lB
lC
lD
1E
1F

PODLST

POLLST

SPECBUF
TEMP
TIPHASE
SPECIAL

20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F

DIGITI
DIGIT2
DIGIT3
DIGIT4
ACCSTO
BSTO
PSWSTO

STACK

RAM LOCATION TABLE

FO !POD,ur

F1
F2
F3
F4
F5
F6
F7

POLBUF
POGDBUF
POGCBUF
FLAGS

"I
F9
FA
FB
FC
FD
FE
FF

~
~
X
SP
B

TEMPORARY USED FROM
UPDATE ROUTINE
CONTAIN THE DISPLAY IMAGE

IIIIIIIIIIIIIII CONTINUAL USED FOR
LCD REFRESHING

I88888J USED BY COP8 CORE

FIGURE 19. RAM Assignment

2-236

FREE RAM LOCATIONS

TLlDD12076-19

z
cO
U1
W

TLlDD12076-20

FIGURE 20. Flowchart for Refresh-Routine

2·237

~ r-----------------------------------------------------------------------~

Z
~

Listing

DEMO FOR COP820CJ:
3 WAY MULTIPLEXED LCD DRIVER DEMO
CONSTANT DISPLAY "OlA3" and two special segments on
.incld cop820cj.inc
iRAM assignments
tiphase=OlE
special=OlF

ithis byte must contain the
ion/off, configuration of
ithe extra segments
i (' -, , , low bat' , etc. )

digitl=020
digit2=021
digit3=022
digit4=023

iin these RAM locatio~s the
iBCD code of the display
idigits are stored.

accsto=024

iaccu buffer used

dur~ng

iinterrupt service routine
ibbuffer
iPSW buffer

bsto=025
psws'to=026
iregister definition:

iPortd buffer
iPortl buffer
iPortgd buffer
iPortgc buffer
iflag byte for podfla

podbuf=OfO
polbuf=Ofl
pogdbuf=Of2
pogcbuf=Of3
flags=Of4
iflag definition in flags byte
podfla=07

i************** initialization routine

*********************.~****Xy~~

init:
ld sp,lt02f

iinitialize

ld portlc,fOff
ld portgc,f037

iport 1 output
iport g:Gl,G2,G4,G5 are
ioutputs
iall outputs low, all
iinputs Hi-Z
iC at GO is discharged
;begin with timephase 0
;~xt. in~errupt enable

ld portgd,fOO
ld tiphase,itOO
ld psw,/t002

stackpoin~er

TL/DD12076-21

2-238

begin:

interrupts are welcome now
now the external C can be
charged

sbit #gie,psw
rbit #OO,portgc
ld b,#special
ld [b+],#088

ld
ld
·ld
Id

itwo special segments
i are 'ON'

idisplay:"01A3"
idigitl
idigit2
idigit3
idigit4

[b+],#OO
[b+],!tOOl
[b+], !tOOA
[b],#003

i************** main program **************************************
loop:
jsr update
jp loop
i************** update subroutine *********************************
iRAM definitions:

ibuffer for 'special'
itemporary used

specbuf=OlC
temp=OlD
ipointer on tables:
podlst==OlO
pollst=016
1st
=000

iadress of list for port d
iadress of list for port 1
imain list for display
iroutine to refresh
iport d,l each timephase

seglst=OOC

ithis list contains the
ion/off configuration of
ithe segments

.=0200

.local
update:

nxtdig:

ld a, special
x a,specbuf
ld x,itseglst
ld b,itdigitl

iload 'special' register
itO the buffer 'specbuf'
iX points the segmentlist
ib points digitlist

ld a, [b+]

iload BCD code of
icurrent digit
iset pointer on look up
itable for segment setting
iload segment data of
icurrent digit
i store it to RAM ,
iload special bit
ito car::y

add a,#L(bcdsegtab)
laid

a,temp
ld a,specbuf
r::c a

TL/DD12076-22

2-239

»
z

~ r-----------------------------------------------------------------------------------~
II)

iprepare for next
ispecial segment
ispecial bit not set?
ithen reset it in the
itemp byte
istore temp
ito the seglst list
i i f not last digit
iload data for next digit

x'a,specbuf

<.C

ifnc
rbit #2,temp
ld a,temp
x a, [x+J
ifbne #04
jp nxtdig

iset flag for working at
iport d list
iconvert 3 bits from the
isegment bytes to the
itimephaselist for portd

sbit #podfla,flags
jsr convert

ishift with carry
shwc:
nxtshwc:

ib points seglst
iload special segment bit
ito carry

ld b,#seglst
Id a,specbuf
rrc a
x a,specbuf

iprepare for next
ispecial segment
ishift the segmentbyte
ithree positions right
iand append the special
isegment bit

ld a, [bJ
rrc a
rrc a
rrc

istore shifted byte
iend of segment list
inot reached?
ithen shift the next
isegment byte

x a, [b+J
ifbne #00
jp nxtshwc
rbit #podfla,flags

ireset flag for working
i at port 1 list'
iconvert 3 bits of the
isegment bytes to the
itimephaselist for port 1

jsr convert
ishift (without carry)
sh~ft:

nxtshift:

iO points segmnet list
iload segment byte
ishift the segmentbyte
ithree positions right

ld b,#seglst
ld a, [b]
rrc a
rrc a
rrc a
x a, [b+]
ifbne itOO

istore shifted byte
iend of segment list
inot reached?
ithen shift the next
isegment byte '

jp nxtshift

TL/DD12076-23

2-240

convert 3 bits of the
segment bytes to the
timephaselist for port 1

jsr convert

iCOPY portdata to the list on which the refresh routine will access
copy:
idisable interrupt to
iprevent fail display
ib points podlst
iX points refresh list
iload portbyte
iswap it
istore it to refresh list
iincrement x
i i f the end of the podlst
iis not reached
ithen next timephase
ib points pollst
iX points refresh list
iincrement x
iload portbyte
iswap it
istore it to refresh list
iif the end of the pollst
iis not reached
ithen next timephase
irefresh routine allowed
iagain

rbit #eni,psw

nxtd:

ld b,#podlst
ld x,#lst
ld a, [b+]
swap a
x a, [x+]
ld a, [x+]

ifbne #06

nxtl:

jp nxtd
ld b,#pollst
ld x,#lst
ld a, [x+]
ld a, [b+]
swap a

x a, [x+]
ifbne #OC
jp nxtl
sbit #eni,psw

iend of update routine

ret
isubroutines for update routine:
convert:

iX points segment list
iload segment byte
imasK ont first three bits
ipointer on timephase table
iload timephase curve for
ione segment pin
ib points list for portd
iworking at podlst ?
ithen b points on podlst

ld x,#seglst
nxtsgl:

lq. a,

[x+]

and a,~007
add a,#L(tiphtab)
laid
ld b,#pollst
ifbit #podfla,flags
ld b,#podlst

ishift timephase data according to 3 bits
ipossible with 3 segments)

( 8 combinations are

tipsh:
x a,temp

istore timephase curve to
itemp buffer

ld a,temp
r=c a

iload timephase curve again
ishift out one bit into

nxtphsh:

TL/DD1207S-24

2-241

an
en

r-------------------------------------------------------------------------------~

icarry bit
istore shifted curve
iload portbyte
ishift in one bit from
. i carry bit
istore shifted portbyte
iagain
iend of podlst ?

x a,temp
ld a, [b]
rrc a

oCt

x a, [b+]
ld a,#pollst
ifeq a,b
jp eplst
ifbne /tOC
jp nxtphsh

ithen return
ielse end of pollst

eplst:

iif the end of the segment
ilist is not reached
iwork at next segment byte

ld a,#L(seglst+4)
ifgt a,x
jp nxtsgl
ret·
bcdsegtab:

iin this bytes are the on/off configuration of the segments
ifor a digit are stored. there are only 7 bits of each byte
ithe configuracion of the 2 special segments is stored
;in the 'special' byte .
. BYTE OEF,007,OBD,03F
.BYTE OS7,07E~QFE,00F
.BYTE OFF,07F,ODF,OF6
.BYTE OEC,OB7,OFC,ODC

; , 0' ... ' 3 I
;' 4' ... ' 7'

;' 8' ... ' B'

; 'e' ... 'F'

tiphtab:
ione pin controls 3 segments. there are 8 possible
;combinations. for each combination there is one byte.
;6 bits of one byte control the pin for each timephase .
. BYT~ 007,00E,01S,01C / 023,02A,031,038

;************** interrupt service routine *************************
.=Off
refresh:
istore accu
istore b

x a,accsto
ld a,b
x a,bsto
ld b,#portgd

idischarge C
rbit #00, (bj
ld a, [b+j
sbit #OO,(bj

increment b (b=#portgc)
by switching GO to a
low output
TL/DD12076-25

2-242

ld a , (b]
x a,pswsto

iload psw
istore psw

ld a/tiphase
add a,tiphase

iaccu:=tiphase*2

x a,b

istore accu in b
iload portbyte from
irefresh list('lst')
;store it to port d buffer
iload portbyte
istore it to port 1 buffer
iaccu:=tirnephase*2+2
iaccu points on
ibackplane table
istore pointer

ld a, (b+]

x a/Podbuf
ld a, (b+]

x a,polbuf

ld a,b
add a,#L(bptab)-2
x a,b

ld a,b
laid
x a/Pogdbuf
ld a, [b+]
ld a,b
laid
x a,pogcbuf

iload port g data byte
istore it to port g data
ibuffer
iincrement b
iload pointer
iload portg conf. byte
istore it to buffer
ib points buffer list

hi pO.t:tgc, #00

;all backolanc ~ircs on
iVop/2 le~el to prevent
ispikes

irefresh port d
I

irefresh port 1

x a,portgd

irefresh port g data

Id a, (b+]
x a/Port:.gc

irefresh port g config.

ld a,tiphase
inc a
ifeq a,lt06
Id a,ltOO
x a,tiphase
Id b,#pswsto
rc
ifbit #07, [b]

CD
C.J1
W

ireset ext. interrupt
ipending flag

ld b, #podbuf
ld a, [b+]
x a,portd
ld a, [b+]
x a,portld

Id a, (b+]

»
z

can be charged again

rbit #00, (b]
ld b,#psw
rbit #ipnd, (b]

iupdate tirnephase counter
I

itiphase = 0 .. 5

irestore carry bit
TUDD12076-26

2·243

sbit #07,psw
i fb i t # 6, [b )
sbit #06,psw

irestore halfearry bit

ld a,bsto
x a,b
Id a,aeesto

irestore b
irestore aeeu

reti
bptab:

ireturn from led
irefresh routine

.BYTE 004,004,010,010,020,020
.BYTE 000,004,OO~,010iOOOI020

.END
TL/DD12076-27

2-244 .

Section 3
MICROWIRE/PLUSTM
Peripherals

Section 3 Contents
MICROWIRE and MICROWIRE/PLUS: 3-Wire Serial Interface ...........................
COP472-3 Liquid Crystal Display Controller . . .. . . .. . . . . . . .. . . . .. . .. . . .. .. . . . . . . .. . .. .. .

3-2

3-3
3-7

(;

t;(INational Semiconductor

:§
:n

m
Q)

MICROWIRETM and MICROWIRE/PLUSTM:
3-Wire Serial Interface

::::J
Co

(;

:§

National's MICROWIRE and MICROWIRE/PLUS provide
for high-speed, serial communications in a simple 3-wire implementation.

The control register (CNTRl) is used to configure and control the mode and operation of the interface through userselectable bits that program the internal shift rate. This
greatly increases the flexibility of the interface.

Originally designed to interface COP400 microcontrollers to
peripheral devices, the MICROWIRE protocol has been extended to both the COP800 and HPCTM families with the
enhanced version, MICROWIRE/PlUS.

MICROWIRE/PlUS can also provide additional I/O capability for COP800 and HPC microcontrollers by connecting, for
example, external 8-bit parallel-to-serial shift registers to 8bit serial-to-parallel shift registers.

Because the shift clock in MICROWIRE/PlUS can be internal or external, the interface can be designated as either
bus master or slave, giving it the flexibility necessary for
distributed and multiprocessing applications.

And it can interface a wide variety of peripherals:
a Memory (CMOS RAM and EEPROM)
13 A/D converters
13 Timers/counters
a Digital phase locked-loops
13 Telecom peripherals
13 Vacuum fluorescent display drivers
II lED display drivers
• LCD display drivers

With its simple 3-wire interface, MICROWIRE/PlUS can
connect a variety of nodes in a serial-communication network.
This simple 3-wire design also helps increase system reliability while reducing system size and development time.
MICROWIRE/PLUS consists of an 8-bit serial shift register
(SIO), serial data input (SI), serial data output (SO), and a
serial shift clock (SK).

Both MICROWIRE and MICROWIRE/PlUS give all the
members of National's microcontroller families the flexibility
and design-ease to implement a solution quickly, simply,
and cost-effectively.

Because the COP800 and HPC families have memorymapped architectures, the contents of the SIO register can
be accessed through standard memory-addressing instructions.

/
8-81T AID
CONVERTER
ADC08XX

COP8
(MASTER)

CHIP SELECT LINES

/
AUDIO
AND
RADIO
DEVICES

EEPROM
NMC93XXX

/
LCD
DISPLAY
DRIVER
COP 472

LINES

ISDN TRANSCEIVERS
TP3400
DASL
TP3410
EC
TP3420
SIO

t
1

COPS
(SLAVE)

LINES

/
so
SK
SI

TL/XX/0074-1

3-3

:n
m

.......

"'D

r
C
en

(J)

::l

MICROWIRE/PLUS Block Diagram

...J

a..

.......

a::

-I"-

3:
o

L-...-

a::
o

:e
"C

8-BIT SIO
MSB LSB
REGISTER

SI
SHIFT CLOCK

a::

CKl/l0--+

o
a::

:e
INTERNAL
A DATA BUS",

)
'I

CNTRL
REGISTER

"-I.-

TLlXX/0074-2

3-4

o
:0

MICROWIRE and MICROWIRE/PLUS Peripherals
Part Number

Description

Oatabook

AID CONVERTERS AND COMPARATORS

ADC0811

11 Channel 8-Bit AID Converter with Multiplexer

Linear

ADC0819

19 Channel 8-Bit AID Converter with Multiplexer

Linear

ADC0831

1 Channel 8-Bit AID Converter with Multiplexer

Linear

ADC0838

8 Channel 8-Bit AID Converter with Multiplexer

Linear

o
:0

ADC0832

2 Channel 8-Bit AID Converter with Multiplexer

Linear

ADC0833

4 Channel 8-Bit AID Converter with Multiplexer

Linear

ADC0834

4 Channel 8-Bit AID Converter with Multiplexer

Linear

ADC0852

Multiplexed Comparator with 8-Bit Reference Divider

Linear

ADC0854

Multiplexed Comparator with 8-Bit Reference Divider

Linear

DISPLAY DRIVERS
COP472-3

3 x 12 Multiplexed Expandable LCD Display Driver

Microcontroller

MM5450

35 Output LED Display Driver

Interface

MM5451

34 Output LED Display Driver

Interface

MM5483

31 Segment LCD Display Driver

Interface

MM5484

16 Segment LED Display Driver

Interface

MM5486

33 Output LED Display Driver

Interface

MM58201

8 Backplane and 24 Segment Multiplexed LCD Driver

Interface

MM58241

32 Output High Voltage Display Driver

Interface

MM58242

20 Output High Voltage Display Driver

Interface

MM58248

35 Output High Voltage Display Driver

Interface

MM58341

32 Output High Voltage Display Driver

Intorfaco

MM58342

20 Output High Voltage Display Driver

Intorfnco

MM58348

35 Output Hi!]h VoltEl!]8 Display Drivflr

IntArfAcfl

16 x 16 CMOS EEPROM

Memory

NM93C13

16 x 16 CMOS EEPROM

Memory

NM93C14

64 x 16 CMOS EEPROM

Memory

NM93C46

64 x 16 CMOS EEPROM

Memory

NM93CS06

16 x 16 CMOS EEPROM with Write Protect

Memory

NM93CS46

64 x 16 CMOS EEPROM with Write Protect

Memory

NM93CS56

128 x 16 CMOS EEPROM with Write Protect

Memory

NM93C56

128 x 16 CMOS EEPROM

Memory

NM93CS66

256 x 16 CMOS EEPROM with Write Protect

Memory

NM93C66

256 x 16 CMOS EEPROM

Memory

MEMORY DEVICES
NM93C06

Note: The low voltage (2V-6V) versions of the NM93C06. NM93C46. NM93C56 and NM93C66 are also available.

3-5

::s

:E
:E
m

........

"'C

c:
en

:::l
...J

......
w

MICROWIRE and MICROWIRE/PLUS Peripherals (Continued)
Part Number

TELECOM DEVICES

AUDIO AND RADIO DEVICES

oa:
~

TP3420

Description

S Interface Device (SID)

Databook

Telecom

DS8906

AM/FM Digital PLL Synthesizer

Interface

DS8907

AM/FM Digital PLL Frequency Synthesizer

Interface

DS8908

AM/FM Digital PLL Frequency Synthesizer

Interface

DS8911

AM/FM/TV Sound Up-Conversion Frequency Synthesizer

Interface

LMC1992

Stereo Volume/Tone/Fade with Source Select

Linear

LMC1993

Stereo Volume/Tone/Fade/Loudness with Source Select

Linear

LMC835

7 Band Graphic Equalizer

Linear

"C
C

w
a:

io
o

.(jjl) Nat ion a I

"-...
~

S em i co nd u c tor

N
W

•

COP472-3 Liquid Crystal Display Controller
General Description

Features

The COP472-3 Liquid Crystal Display (LCD) Controller is a
peripheral member of the COPSTM family, fabricated using
CMOS technology. The COP472-3 drives a multiplexed liquid crystal display directly. Data is loaded serially and is held
in internal latches. The COP472-3 contains an on-chip oscillator and generates all the multi-level waveforms for backplanes and segment outputs on a triplex. display. One
COP472-3 can drive 36 segments multiplexed as 3 x 12
(4% digit display). Two COP472-3 devices can be used together to drive 72 segments (3 x 24) which could be an 8%
digit display.

Direct interface to TRIPLEX LCD
.. Low power dissipation (100 p.W typ.)
Il Low cost
. Il Compatible with all COPS processors
1:1 Needs no refresh from processor
II On-chip oscillator and latches
IJ Expandable to longer displays
a Operates from display voltage
a MICROWIRETM compatible serial 1/0
IJ 20-pin Dual-In-Line package and 20-pin SO
D

Blocle Diagram

BPA BPs BPe

12 SEGMENT BUFFERS

Vee

GNO

SK
CS
TLlDD/6932-1

3-7

C")

.....

Absolute Maximum Ratings

D..

Voltage at CS, 01, SK pins

Voltage at all other Pins

-0.3Vto +9.5V

Operating Temperature Range

- 65°C to + 150·C

Storage Temperature
Lead Temp. (Soldering, 10 Seconds)

-0.3V to Voo+0.3V

300·C

O·Cto 70°C

DC Electrical Characteristics
GND = OV, Voo = 3.0V to 5.5V, T A = O·C to 70·C (depends on display characteristics)

Parameter

Min

Max

Units

3.0

5.5

Volts

Voo=5.5V

250

,..,A

Voo=3V

100

,..,A

0.7 Voo

0.8
9.5

Volts
Volts

0.6
Voo-0.6

Voo

Volts
Volts

Voo-O.4

Voo

%Voo+~V

Conditions

Power Supply Voltage, Voo
Power Supply Current, 100 (Note 1)

Input Levels
DI,SK,CS
VIL
VIH
BPA (as Osc. in)
VIL
VIH
Output Levels, BPC (as Osc. Out)
0.4

VOL
VOH

Volts
Volts

Backplane Outputs (BPA, BPB, BPC)
Volts
Volts

VBPA, BPS, SPC ON
VSPA, SPS, SPC OFF

During
BP+ Time

Voo-t::.V
% Voo-t::.V

VSPA, BPS, BPC ON
VSPA, SPS, SPC OFF

During
BP- Time

%VDO-~V

%Voo+~V

VSEGON
VSEG OFF

During
BP+ Time

%VDD-~V

%Voo+~V

VSEGON
VSEG OFF

During
BP- Time

Voo-~V

Voo

%VDO-~V

%Voo+~V

Volts
Volts

Voo

Volts
Volts

Segment Outputs (SA1 - SA4)
Volts
Volts

Internal Oscillator Frequency

kHz

Frame Time (Int. Osc. -;- 192)

2.4

12.8

Scan Frequency (1 ITSCAN)

208

SK Clock Frequency

250

kHz

SKWidth

1.7

,..,s

1.0
100

,..,S

1.0
1.0

,..,s

01
Data Setup, tSETUP
Data Hold, tHOLO

CS
tSETUP
tHOLO
Output Loading Capacitance

,..,S
100

Note 1: Power supply current is measured in stand-alone mode with all outputs open and all inputs at VDO.
Note 2: AV=O.05Voo.

3·8

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at CS, 01, SK Pins
Voltage at All Other Pins
Operating Temperature Range

- 65·C to + 150·C

Storage Temperature
Lead Temperature

300·C

(Soldering, 10 seconds)

- 0.3V to + 9.5V
-0.3V to Voo+0.3V
-40·C to +S5·C

DC Electrical Characteristics
ov, Voo = 3.0V to 5.5V, TA = -40·C to

GND =

Parameter

+S5·C (depends on display characteristics)
Conditions

Power Supply Voltage, Voo
Power Supply Current, 100 (Note 1)

Min

Max

Units

3.0

5.5

Volts

Voo=5.5V

300

p.A

Voo=3V

120

p.A

0. 7Voo

O.S
9.5

Volts
Volts

Voo-0.6

0.6
Voo

Volts
Volts

0.4
Voo-O.4

Voo

Volts
Volts

Input Levels
DI,SK,CS
VIL
VIH
SPA (as Osc. In)
VIL
VIH
Output Levels, SPC (as Osc. Out)
VOL
VOH
Backplane Outputs (BPA, BPS, BPC)
VBPA, BPB, BPC ON
VBPA, BPB, BPC OFF

During
BP+ Time

Voo,-AV
%Voo-AV

Voo
%Voo+AV

Volts
Volts

VBPA, BPB, BPC ON
VBPA, BPB, BPC OFF

During
BP- Time

0
%Voo-AV

AV
%Voo+AV

Volts
Volts

During
BP+ Time

0
%Voo-AV

AV
%Voo+AV

Volts
Volts

During
BP- Time

Voo-AV
%Voo-AV

Voo
%Voo+AV

Volts
Volts

5.:gm.:r.t C~tp~t::: (5/''1 - S:\4)
VSEG ON
VSEG OFF
VSEG ON
VSEG OFF
Internal Oscillator Frequency

kHz

Frame Time (Int. Osc. -:-192)

2.4

12.S

Scan Frequency (1 IT SCAN)

208

250

kHz

SK Clock Frequency
SKWidth

1.7

p.s

1.0
100

p's
ns

1.0
1.0

P.s
p.s

01
Data Setup, tSETUP
Data Hold, tHOLO
CS
tSETUP
tHOLO
Output Loading Capacitance

100

Note 1: Power supply current is measured in stand'alone mode with all outputs open and all inputs at Vee.
Note 2: ilV = 0.05 Vee.

3-9

C")

N
......

Dual-In-Llne Package

c..
0
0

SBl
SC3
SB3

SA2
SB4
SB2

20
19
lB

SA4
SA3 '

BPB'
BPC
BPA
SK
SC4
SC2
SAl

16
15
14
13
12
11

Vee
GNO
01

Description
Chip select .
.Power supply (display voltage)
Ground
Serial data input
Serial clock input
Display backplane A (or oscillator in)
Display backplane B
Display backplane C (or oscillator out)
12 multiplexed outputs

Voo
GND
01
SK

BPA
BPs
BPc
SA1-SC4
TLlDD/6932-2

TopVI~w

Order. Number COP472MW-3 or COP472N-3
. '. ' See NS Package Number M20A or ~20A
FIGURE 2. Connection Diagram

~II_~SETUP

cs ---,-

I-

WID~H

I I
SK

TL/DD/6932-3

FIGURE 3. Serial Load Timing Diagram

osc
Vee'

BPA :::

o
Vee

BPB

'I,'I,
o

Vee

BPC:::~~~ .'

o
Veo

'I,

SEGMENT 'I,

o
TL/DD/6932-4

FIGURE 4. Backplane and SegmenfWaveforms
l ..

SC1

'--_ _ _-asp
TL/DD/6932-5

FIGURE 5. Typical Display Internal Connections
Epson LD-370

3·10

~--------------------------------------------------------------~O

o-a

Functional Description
The COP472-3 drives 36 bits of display information organized as twelve segments and three backplanes. The
COP472-3 requires 40 information bits: 36 data and 4 control. The function of each control bit is described below.
Display information format is a function of the LCD interconnections. A typical segment/backplane configuration is illustrated in Figure 5, with this configuration the COP472-3 will
drive 4 digits of 9 segments.

BPC
BPB
BPA
BPB
BPC
BPB
BPA
BPA

SH
SG
SF
SE
SD
SC
SB
SA

9
10
11
12
13
14
15
16

SA2,
SB2,
SC2,
SC2,
SB2,
SA2,
SA2,
SB2,

BPC
BPB
BPA
BPB
BPC
BPB
BPA
BPA

SH
SG
SF
SE
SD
SC
SB
SA

Digit 2

17
18
19
20
21
22
23
24

SA3, BPC
SB3, BPB
,SC3, BPA
SC3, BPB
SB3, BPC
SA3, BPB
SA3, BPA
SB3, BPA

SH
SG
SF
SE
SD
SC
SB
SA

Digit3

25
26
27
28
29
30
31
32

SA4, BPC
SB4, BPB
SC4, BPA
SC4, BPB
SB4, BPC
SA4, BPB
SA4,BPA
SB4, BPA

SH
SG
SF
SE
SD
SC
SB
SA

Digit 4

33
34
35
36
37
38
39
40

SC1, BPC
SC2, BPC
SC3, BPC
SC4, BPC
not used
Q6
Q7
SYNC

SPA
SP2
SP3
SP4

Digit 1
Digit 2
Digit 3
Digit 4

The fifth set of 8 data bits contains special segment data
and control data in the following format:

I SYNC I Q7 I Q6 I X I SP4 I SP3 I SP2 I SP1 I
The first four bits shifted in contain the special character
segment data. The fifth bit is not used. The sixth and seventh bits program the COP472-3 as a stand alone LCD driver or as a master or slave for cascading COP472-3's. BPC
of the master is connected to BPA of each slave. The following table summarizes the function of bits six and seven:

Data to
Numeric Display

SA1,
SB1,
SC1,
SC1,
SB1,
SA1,
SA1,
SB1,

CONTROL BITS

TABLE I. COP472-3 Segment/Backplane
Multiplex Scheme

1
2
3
4
5
6
7
8

Data is shifted into an eight bit shift register. The first bit of
the data is for segment H, digit 1. The eighth bit is segment
A, digit 1. A set of eight bits is shifted in and then loaded into
the digit one latches. The second set of 8 bits is loaded into
digit two latches. The third set into digit three latches, and
the fourth set is loaded into digit four latches.

Two or more COP472-3 chips can be cascaded to drive
additional segments. There is no limit to the number of
COP472-3's that can be used as long as the output loading
capacitance does not exceed specification.

Segment,
Backplane

Data is loaded in serially, in sets of eight bits. Each set of
segment data is in the following format:

To adapt the COP472-3 to any LCD display configuration,
the segment/backplane multiplex scheme is illustrated in
Table I.

Bit Number

oI:loo

SEGMENT DATA BITS

Digit 1

Function
Slave
Stand Alone

Not Used

Master

BPC Output

BPAOutput

Backplane
Output
Backplane
Output
Internal
Osc. Output
Internal
Osc. Output

Oscillator
Input
Backplane
Output
Oscillator
Input
Backplane
Output

The eighth bit is used to synchronize two COP472-3's to
drive an 8%-digit display.

3-11

N
W

•

C")

LOADING SEQUENCE TO DRIVE A 41f2-DIGIT DISPLAY

"'I:t

Steps:

.......

o
o

1. Turn CE low.
2. Clock in 8 bits of data for digit 1.
3. Clock in 8 bits of data for digit 2.
4. Clock in 8 bits of data for digit 3.
5. Clock in 8 bits' of data for digit 4.
6. Clock in 8 bits of data for special segment and control
function of BPC and BPA.

I0 I

SP4

I, SP3 I

SP2

SP1

Vee

7. Turn CS high.
Note: CS may be turned high after any step. For example to
load only 2 digits of data, do steps 1, 2, 3, and 7.

CS must make a high to low transition before loading data in
order to reset internal counters.

COP800

LOADING SEQUENCE TO DRIVE AN
81f2-DIGIT DISPLAY

SO 1 - - - - - - - 4
SK 1--------4
GNO

Two or more COP472-3's may be connected together to
drive additional segments. An eight digit multiplexed display
is shown inFigure 7. The following is the loading sequence
to drive an eight digit display using two COP472-3's. The
right chip is the master and the left the slave.

DISPLAY
VOLTAGE

00 1--------4L-_..,....._..J

Tl/DD/6932-6

FIGURE 6. System Diagram -,4112 Digit Display

Steps:
1. Turn CS low on both COP472-3's.
2. Shift in 32 bits of data for the slave's four digits.
3. Shift in 4 bits of special segment data: a zero and three
ones.
1

SP4

SP3

SP2

SP1

This synchronizes both the chips and BPA is oscillator
input. Both chips are now stopped.
4. Turn CS high to both chips.
5. Turn CS low to master COP472-3.
6. Shift in 32 bits of data for the master's 4 digits.
7. Shift in four bits of special segment data, a one and
three zeros.

I0 I

SP4

SP3

SP2

SP1

Voo

COP800
SO~--~~~---~

This sets the master COP472-3 to BPA as a normal
backplane output and BPC as oscillator output. Now
both the chips start and run off the same oscillator.
8. Turn CS high.

GNO

The chips are now synchronized and driving 8 digits of display. To load new data simply load each chip separately in
the normal manner, keeping the correct status bits to each
COP472-3 (0110 or 0001).

SK~-----~~------..J
0 0 1 - - - - -.....
01 ~----------.....

TLlDD/6932-7

FIGURE 7. System Diagram - 8112 Digit Display

3-12

Section 4
COPS Development
Support

Section 4 Contents
Development Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP8 Development System .........................................................

4-2

4-3
4-6

tfI

c(I)

Nat ion a I Se m i con due tor

<
(I)
0"

3
(I)

-...
::::I

Development Support

ecn

"C
"C

Our job doesn't end when you buy a National microcontroller, it only begins.
.

Mlcrocontroller Development Support
HPC!M Family
.

The next step is to help you put that microcontroller to
work-delivering real-world performance in a real-world application.

Mlcrocontroller Development Support
COP400 Family

HPC-MDS is a complete packaged system for all members
of the HPC family except for HPC461 00. The host system is
IBM PC/AT® (PC-DOS, MS-DOS) and Sun® SPARCstation
(SunOSTM) .. It provides true real time in-system emulation
with support tools such as ANSI compatibleC-Compiler, assembler, Linker. and Source/Symbolic debugger. The de~
bugger interface is based on M.S-Windows 3.0 for IBM
PC/AT and a line debugger for Sun SPARCstation users.

The COPSTM Microcontroller Development system is a
complete, inexpensive system, designed to support both
hardware and software development of the COP400 family
of microcontrollers.

HPC-MDS gives the user the flexibility to sYmbolically debug
his code and download it to the target hardware. The user
can set breakpoints and traces, can execute" time measurements and examine and modify internal registers and I/O.

Using a standard IBM® PC® platform as a host, this system
provides the tools to write, assemble, debug and emulate
software for user target design.

A low cost HPC designer's kit is also available. The kit has
complete in-system emulation capability and is packaged
with an evaluation version of C compiler and full package of
Assembler/Linker.

That's why we offer you such a comprehensive, powerful,
easy-to-use package of development tools.

The development system itself consists of two circuit
boards that interface with each other and to the host computer using a software package. The first board is called the
Brain Board. It provides the major functional features of the
system, linking the various elements of the host system.
The other board is called the Personality Board and it is
common for all members of the COP400 family of microcontrollers.

The HPC46100 DSP-Microcontroller, is supported by a development kit for ROM emulation, logic and timing analysis,
code debug with inverse assembly and PC based debug
monitor. The kit consists of a Logic Analyzer Interface
Board, a Target Board, Assembler/Linker/Librarian software, an inverse assembler to run on Hewlett-Packard 1650
and 16500A/B logic analyzers and PC based debug monitor, "The Serial Hook".
Third Party development support is also available for various sources for the HPC family.
Hewlett Packard offers HP64775 emulator/analyzer for
30 MHz HPC 16083/16064 and 20 MHz 16400E emulation.
The stand alone HP system provides a very fast serial link to
the host system and offers complete emulation and timing
and logic analysis capability. The software tools for HP emulator are provided by National Semiconductor®.
Signum System offers a USP-HPC in-circuit emulator for the
HPC46100 with 40 MHz 1 wait state real time emulation.
This system is supported with 256 kbyte overlay emulation
memory, 32k frames deep trace buffer memory, complex
breakpoints, high level language source/symbolic debugger, fast serial download and a window based menu driven
user interface.

Mlcrocontroller Development Support
copeoo Family

MetaLink Corporation's iceMASTERTM COP8 Model 400 InCircuit Emulator provides complete real-time full speed emulation of all COP8 family devices. It consists of a base unit
and interchangeable probe cards, which support various
configurations and packages. The source symbolic debugger with a window based user interface is a powerful tool to
accomplish software and hardware debug and integration
tasks.
COP800 code development is supported by a macro crossassembler running DOS on the IBM compatible PC.
COP800 development is also supported with a low cost Designer's Kit. The Designer's Kit includes a simulator with a
window based menu driven user interface and the COP8
cross-assembler. It is a tool designed for product evaluation
and code development and debug. It comes equipped with
complete debug capability and full assembler. The host for
the designer kit is an IBM PC/XT/AT or compatible running
DOS.

The language tools hosted on the IBM PC/AT and compatibles and Sun SPARCstation are available from National
Semiconductor to support third party emulation systems.

4-3

...

c.
c.
::s

(/)
~

c
CD
E
c.
o
G>

>
CD

~------------------------------------------------------------------------------------------,

Dlal-A-HeJper

Emulation Tochnology offers a passive preprocessor and
inverse assembler package for HP1650 and 16500A series
of Logic analyzers. The preprocessor provides a low cost
and convenient way of doing timing and state analysis of the
HPC based design.
Emulation Technology also offers debug tool accessories
for 68-pin PLCC and 80-pin (QFP) Quad Flat Packages. This
includes PLCC to QFP adapter, QFP test clip and a QFP
surface mount replacement base.

Voice:

(408) 721-5582 (8 a.m.-5 p.m. PSn

Modem:

(408) 739-1162 (24 Hrs.lday)

Setup:

Baud rate 300 bps or 1200 bps 8 bits, no parity,
1 stop

Dedicated Applications Engineers
We've assembled a dedicated team of highly trained, highly
experienced engineering professionals to help you implement your solution quickly, effectively, efficiently and to ensure that it's the best solution for your specific application.

Programming support for the HPC emulator devices is available from Data 110 on their Unisite models.
For more details on the third party support tools for NSC's
microcontroller products, please contact the third party office in your area or the National Semiconductor sales office.

At National, we believe that the best technology is also the
most usable technology. That's why our microcontrollers
provide such practical solutions to such real design problems. And that's why our microcontroller development support includes such comprehensive tools and such powerful
engineering resources.

Dlal-A-Helper On-Line Applications Support
Dial-A-Helper lets you communicate directly with the Microcontroller Applications Engineers at National.

No one makes more microcontrollers than National and no
one does more to help you put those microcontrollers to
work.

Using standard computer communications software, you
can dial into the automated Dial-A-Helper Information System 24 hours a day.
.
You can leave messages on the electronic bulletin board for
the Applications Engineers, then retrieve their responses.
You can select and then download specific applications
data.

4-4

NOTES

t!lNational Semiconductor

cQ)

COPS Development System

E
c..
o
a;
>
Q)

iceMASTERTM COP8/400

C
co

TL/DD/11386-1

Product Overview
The ice MASTER COP8/400 in-circuit emulator manufactured by MetaLink Corporation and marketed by
National Semiconductor provides complete real-time
emulation support for all members of the COP8 family.
This stand-alone system is designed to provide maximum flexibility to the user through the interchangeable
probe cards to support the various configurations and
packages of the COP8 family. The interchangeable
probe card connects to a common base unit which is
linked with an IBM® PC® host through the RS-232
serial communications channel. Full assembly-level
symbolic debugging is supported.

•

MetaLink COP8 ice MASTER Feature List
o

o
o
o

Flexible, easy-to-use windowed interface, with window size, position, contents and color being completely configurable.
Fast serial download with 115.2 kBaud using a
standard PC COMM port.
Context-sensitive hypertext on-line help system.
Commands can be accessed via pull-down menus
and lor redefinable hot keys.
Dynamically annotated code feature displays contents of all accessed (read and write) memory locations and registers, as well as flow-of-control direction change markers next to each instruction executed when single-stepping.

•

4-6

4k-frame trace buffer captures data in real-time.
Trace information consists of address and data bus
values and user-selectable probe clips (external
event lines). Trace buffer data can be viewed as
raw hex or disassembled instructions. The probe
clip bit values can be displayed in binary, hex or
digital waveform formats.
Performance analyzer with a resolution better than
6 t-ts. Up to 15 independent memory areas based
on code address, line number or label ranges can
be defined. Analysis results can be viewed in bar
graph format or as actual frequency count.
32k of break and trace triggers. Triggers can be
enabled, disabled, set or cleared. They can be simple triggers based on code or address ranges or
complex triggers based on code address, direct address, opcode value, opcode class or immediate
operand. Complex breakpoints can be ANDed and
ORed together.
Memory operations for program memory include
single-line assembler, disassembler, view, change,
and write to file.
Memory operations for data memory include fill,
move, change, compare, dump to file and examine,
modify for registers and program variables.
Complete status of debugger including breakpoints, trace triggers, etc. can be saved to file for
later resumption of debugging process.

~------------------------------------------------------------~o

o"tJ

Specifications

EMULATOR SYSTEM REQUIREMENTS

User Window Controls:
Selectable (On/Off)
Movable
Resizable
Scrollable
Color Selection
Highlighting
Function/Hot Key Access:
User-Assignable

Basic Emulator System Model 400
Interchangeable Probe Card
+ 5V, 1.5A Power Source
MODELS

400 Emulator with:
4k Trace Buffer
2 Performance Analyzers
Full WATCHDOGTM Timer Support

EMULATION CONTROLS
FILE FORMATS

Reset from Emulator
Reset from Target
Reset Processor
Go
Go From
Go Until
Slow Motion
Step
Step Line
Step Over
Step To
Repetition Counter

Intel HEX and National Semiconductor
MACRO

Repetitive Routines
User-created and callable
MEMORY OPERATIONS

Program Memory:
Single Line Assembler
Disassemble
Disassemble to File
View/Change
Mapping
Data/Code Memory:
Dump
Dump to File
Fill
Move
Change
Compare
Registers:
Examine/Modify
Program Variables:
Examine/ Modify

PERFORMANCE ANALYZER

Real-Time Program Profiling
5.4 p.s Sampling Period
7 Year Duration
Display Options:
Bar Graph
Frequency Count
Display Modes:
Raw
Symbolic
Up to 15 Bin Cupucity:
Multiple Ranges per Bin
User-Controlled Bin Setup:
By Address
By Symbol
Automatic

OPERATING CHARACTERISTICS

Electrically Transparent
Operationally Transparent

USER INTERFACE
Keyboard or Mouse Control
Pull·Down and Pop-Up Menus
Main Screen Windows:
Registers/SFRs/PSW Bits
Stack
Up to 5 Internal Data Memory
Up to 5 Code Memory
Source Program
Watch
System Status

TRACE

Trace Triggers:
Start
Center
End
Variable
4k-Frame Trace Buffer

4-7

(I)

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CD
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3

CD
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C
co

(.)

Specifications (Continued)
WARRANTY

Trace Contents:
Address
Data
External Clips
Trace Display Modes:
Raw Hex
Symbolic
Binary (Clips)
Digital Waveform (Clips)
Trace Buffer Operations:
Write Buffer to File
Search Trace Buffer

One (1) year limited warranty, parts and labor, for registered users.
iceMASTER COP8

Emulation Memory
Program
RealTime:
Breakpoints:
Trace On:
Trace Off:
Pass Count
Trigger Conditions:
PC Address and Range
Opcode Value
Opcode Class
SFRs/Registers
Direct Byte Address and Range
Direct Bit Address and Range
Immediate Operand Value
Read/Write to Bit Address
Register Address Modes
Read/Write to Register Address
Logical AND/OR of
Any of the Above
External Input
Operating Modes
Single-Chip/ROM

HELP

On-Line
Context Sensitive
Hypertext/Hyperlinked
SOURCE/SYMBOLSUPPORT

Source-Level Debug
ELECTRICAL SPECIFICATIONS

Input Power (Maximum):
1.5A @ +5 VOC ±5%
MECHANICAL SPECIFICATIONS

Emulator Dimensions:
1.0" x 7.0" x 5.5"
(2.5cm x 17.8cm x 14cm)
Probe Card Cable Length:
14.0" (35.6cm)
Emulator Weight:
2.0 Ibs. (0.9 kg)

32k
DC -10 MHz
32k
32k
32k
32K
X
X

X
X
X
X
X
X
X

X
X
X
X

HOST SYSTEM REQUIREMENTS

IBM PC-XT /PC-AT or compatibles, 640 kbytes of
Memory with 5.25" Double Density Floppy Drive.
RS-232 Serial Port
MS-DOS or PC-DOS Operating System

4-8

a"'D

Ordering Information

Emulator Ordering Information

Part Number

Description

<
(1)

IM-COP8/400

MetaLink base unit in-circuit emulator for all COP8 devices, symbolic debugger software and
RS-232 serial interface cable

MHW-PS3

Power Supply: 11 OV 160 Hz

MHW-PS4

Power Supply: 220V 150 Hz

(1)

3(1)

:::J

(1)

Probe Card Ordering Information

Device
COP880C, 8780C

Package

Voltage Range

Probe Card

44 PLCC

4.5V-5.5V

MHW-880C44D5PC

2.5V-6.0V

MHW-880C44DWPC

4.5V-5.5V

MHW-880C40D5PC

COP880C, 8780C

40 DIP

2.5V-6.0V

MHW-880C40DWPC

COP881C, 8781C, 840C, 820C

28 DIP

4.5V-5.5V

MHW-880C28D5PC

2.5V-6.0V

M HW-880C28DWPC

20 DIP

4.5V-5.5V

MHW-880C20D5PC

2.5V-6.0V

MHW-880C20DWPC

COP842C, 822C, 8742C

COP820CJ

COP822CJ

28DIP

20DIP

COP8640C, 8620C

28DIP

COP8642C, 8622C

20 DIP

COP888CF

44 PLCC

40 DIP

4.5V-5.5V

MHW-820CJ28D5PC

2.3V-6.0V

MHW-820CJ28DWPC

4.5V-5.5V

MHW-820CJ20D5PC

2.3V-6.0V

MHW-820CJ20DWPC

4.5V-5.5V

MHW-8640C28D5PC

2.5V-6.0V

MHW-8640C28DWPC

4.5V-5.5V

MHW-8640C20D5PC

2.5V-6.0V

MHW-8640C20DWPC

4.5V-5.5V

MHW-888CF44D5PC

2.5V-6.0V

MHW-888CF44DWPC

4.5V-5.5V

MHW-888CF40D5PC

2.5V-6.0V

MHW-888CF40DWPC

COP884CF

28DIP

4.5V-5.5V

MHW-884CF28D5PC

2.5V-6.0V

MHW-884CF28DWPC.•

COP888CL

44 PLCC

4.5V-5.5V

MHW-888CL44D5PC

2.5V-6.0V

MHW-888CL44DWPC

40 DIP

4.5V-5.5V

MHW-888CL40D5PC

2.5V-6.0V

MHW-888CL40DWPC

4-9

E
Q)

Ordering Information (Continued)

Probe Card Ordering Information (Continued)

C
CP

Package

Device

a.
o
>
Q)

COP884CL

COP888CG, 888CS

28 DIP

4.SV-S.SV

MHW-884CL28DSPC

2.SV-6.0V
44 PLCC

4.SV-S.SV

MHW-888CG44DSPC

2.SV-6.0V

MHW-888CG44DWPC

40DIP

4.SV-S.SV

MHW-888CG40DSPC

2.SV-6.0V

MHW-888CG40DWPC

4.SV-S.SV

MHW-884CG28DSPC

2.SV-6.0V

MHW-884CG28DWPC

COP884CG,884CS

Probe Card

MHW-884CL28DWPC

(.)

Voltage Range

28DIP

LANGUAGE TOOLS

Product

NSID

Description

Includes

Number

COP800 Family

MOLE-COP8-IBM

Assembly Language
Software for the COP800
Family

COP800 System
Software User's Manual

424410S27

Single-Chip Emulator
Form, Fit, Function Emulator Ordering Information

Part
Number
COP880C

Emulator
Part Number

Package

COP880CMHEL-X

44 LDCC

COP8780CV

44 PLCC

COP8780CEL

44 LDCC

COP880CMHD-X

40 DIP

Clock
Option
X
X
X

=
=

1: Crystal
2: External
3: RIC

Programmable

=
=
=

1: Crystal
2: External
3: RIC

COP8780CJ
COP881C,
COP840C,
COP820C

COP881 CMHD-X

COP8780CN

Multi-Chip Module, UV Erasable

One-Time Programmable
UV Erasable

X
X
X

Programmable

COP8780CN

Description

Multi-Chip Module, UV Erasable

One-Time Programmable
UV Erasable

28 DIP

X
X
X

=
=
=

1: Crystal
2: External
3: RIC

Programmable

Multi-Chip Module, UV Erasable

. One-Time Programmable
UV Erasable

COP8780CJ

4-10

a."

Single-Chip Emulator (Continued)

co
C

Form, Fit, Function Emulator Ordering Information (Continued)

Part
Number
COP881C,
COP840C,
COP820C

Emulator
Part Number
COP881 CMHEA-X

COP8781CWN

Clock
Option

Package
28 LCC
(Shoebox)
28S0

COP842C

COP842CMHD-X
COP822CMHD-X

COP842C,
COP822C

COP8742CN

Programmable

One-Time Programmable

20 DIP

X = 1: Crystal
X = 2: External
X = 3: RIC

Multi-Chip Module, UV Erasable

20 DIP

Programmable

One-Time Programmable
UV Erasable

20S0

Programmable

COP8640C,
COP8620C

One-Time Programmable
UV Erasable

X = 1: Crystal
X = 2: External
X = 3: RIC

COP8640CMHD-X

28 DIP

COP8640CM H EA-X

28 LCC
(Shoebox)

COP8642C,
COP8622C

COP8642CMHD-X

20 DIP

X = 1: Crystal
X = 2: External
X = 3: RIC

Multi-Chip Module, UV Erasable

COP820CJ

COP820CJMHD-X

28 DIP

Multi-Chip Module, UV Erasable

COP820CJMHEA-X

28 LCC
(Shoebox)

X = 1: Crystal
X = 2: External
X = 3: RIC

COP822CJ

COP822CJMHD-X

20 DIP

X = 1: Crystal
X = 2: External
X = 3: RIC

Multi-Chip Module, UV Erasable

COP888CL

COP888CLMHEL-X

44 LDCC

Multi-Chip Module, UV Erasable

COP888CLMHD-X

40 DIP

X = 1: Crystal
X = 3: RIC

COP884CL

COP884CLMHD-X

28 DIP

Multi-Chip Module, UV Erasable

COP884CLMHEA-X

28 LCC
(Shoebox)

X = 1: Crystal
X = 3: RIC

COP888CFMHEL-X

44 LDCC

COP888CFMHD-X

40 DIP

COP884CFMHD-X

28 DIP

COP884CFMHEA-X

28 LCC
(Shoebox)

COP888CGMHEL-X

44 LDCC

COP888CGMHD-X

40 DIP

COP888CF

COP884CF

COP888CG

Multi-Chip Module, UV Erasable
Multi-Chip Module, Same Footprint
as 28 SO, UV Erasable

Multi-Chip Module, Same Footprint
as 28 SO, UV Erasable

X = 1: Crystal
X = 3: RIC

Multi-Chip Module, UV Erasable

X = 1: Crystal
X = 3: RIC

Multi-Chip Module, UV Erasable

X = 1: Crystal
X = 3: RIC

4-11

CD
:::l

( J)

'<
en

UV Erasable

COP8742CMC

0'
3

"'C

Multi-Chip Module, Same Footprint
as 28 SO, UV Erasable

COP8742CJ
COP8742CWM

Description

X = 1: Crystal
X = 2: External
X = 3: RIC

COP8781CMC

COP822C

<
CD

Multi-Chip Module, Same Footprint
as 28 SO, UV Erasable
Multi-Chip Module, UV Erasable

C1>
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>
C1>

Single-Chip Emulator (Continued)
Form, Fit, Function Emulator Ordering Information (Continued)

Emulator

Part
Number
COP884CG

Part Number
COP884CGMHD-X

28 DIP

COP884CGMHEA-X

28 LCC
(Shoebox)

COP888EGMHEL-X

44 LDCC

COP888EGMHD-X

40 DIP

COP884EGMHD-X

28 DIP

COP884EGMHEA-X

28 LCC
(Shoebox)

COP888CSMHEL-X

44 LDCC

COP888CSMHD-X

40 DIP

COP884CSMHD-X

28 DIP

COP884CSM H EA-X

28LCC
(Shoebox)

D-

COP888EG

COP884EG

COP888CS

COP884CS

Clock
Option

Package

Description

X
X

=
=

1: Crystal
3: RIC

X
X

=
=

1: Crystal
3: RIC

Multi-Chip Module, UV Erasable

X
X

=
=

1: Crystal
3: RIC

Multi-Chip Module, UV Erasable

X
X

=
=

1: Crystal
3: RIC

Multi-Chip Module, UV Erasable

X
X

=
=

1: Crystal
3: RIC

Multi-Chip Module, UV Erasable

Multi-Chip Module, UV Erasable
Multi-Chip Module, Same Footprint
as 28 SO, UV Erasable

Multi-Chip Module, Same Footprint
as 28 SO, UV Erasable

Programming Support
The main board and scrambler boards can be purchased separately or as a set. The table below lists
the product identification numbers of the Duplicator
Board products.
Product ID

Description

Product ID

Description

COP8-PRGM-28D

COP8 Duplicator Board for
28-pin DIP Multi-Chip
Module (MCM) and for use
with Scrambler Boards

COP8-SCRM-87B

Scrambler Board for
COP8780 devices, 20-pin
DIP, 20-pin SO, 44-pin
PLCC/LDCC

COP8-SCRM-DIP

MCM-Scrambler Board for
20-pin DIP and 40-pin DIP

COP8-PRG M-87A

COP8-SCRM-PCC

MCM-Scrambler Board for
44-pin PLCC/LDCC

COP8 Duplicator Board with
COP8-SCRM-87 A
Scrambler Board

COP8-PRG M-87B

COP8 Duplicator Board with
COP8-SCRM-87B
Scrambler Board

COP8-PRGM-SBX

COP8 Duplicator Board with
COP8-SCRM-SBX
Scrambler Board

COP8-SCRM-SBX

Scrambler Board for 28-pin
LCC MCM Package
(Shoebox)

COP8-PRGM-DIP

COP8-PRGM-PCC

COP8-SCRM-87 A

COP8 Duplicator Board with
DIP MCM Scrambler Board
(PRGM-28D and SCRMDIP)
COP8 Duplicator Board with
PLCC/LDCC MCM
Scrambler Board (PRGM280 and SCRM-PCG)
Scrambler Board for
COP8780 devices, 28-pin
DIP, 40-pin DIP, 28-pin SO

4-12

(')

Programming Support (Continued)

co
C

The COP device pin/package types, COP device
numbers, and the Duplicator Board product identification number for each package type are listed in the
table below.
Package Type

(1)

COP Devices

COP Duplicator
Product 10 #

20-Pin DIP

842CMH, 8642CMH, 822CJMH

COP8-PRGM-DIP

28-Pin DIP

884CLMH/CFMH/CGMH/EGMH/CSMH,
881CMH, 8640CMH, 820CJMH

COP8-PRGM-28D

28-Pin LCC (Shoebox)

881 CMH, 820CJMH, 8640CMH,
884CFMH/CLMH/CGMH/EGMH/CSMH

COP8-PRGM-SBX

40-Pin DIP

888CLMH/CFMH/CGMH/EGMH/CSMH,
880CMH, 943CMH

COP8-PRGM-DIP

44-Pin PLCC/LDCC

888CLMH/CFMH/CGMH/EGMH/CSMH,880CMH

COP8-PRG M-PCC

28-Pin DIP or SO,
40-Pin DIP

8780C, 8781 C

COP8-PRGM-87 A

20-Pin DIP or SO,
44-Pin PLCC/LDCC

8780C,8742C

COP8-PRGM-87B

4-13

<
(1)
0'
"C
3(1)

:::s

CJ)

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(II
(1)

COPBOO DESIGNER'S TOOL KIT

>en
cG)
E

C
CO

0..

o
o

TL/DD/1138S-2

General Description

Features

The COP800 Designer's Tool Kit is available today to
help you evaluate National's COP800 microcontroller
family. The Kit contains programmer's manuals, device data sheets, application notes, and pocket reference guides for immediate in-circuit evaluation. The
Designer Kit includes an assembler and simulator,
which allow you to write, test and debug COP800
code before your target system is finalized.
The simulator can handle script files that simulate
hardware inputs and interrupts to the device being
simulated. Any simulator command and comments
may be included in a script file. The simulator also
supports an additional command called WAIT, used to
simulate machine cycles to delay before continuing
with the script file.
A capture file feature enables you to record current
cycle count and changes to an output port which are
caused by the program under test. When used in combination with script files, this feature provides powerful
software testing and debug capability.

•
•
•
•
•
•
•
•
•

4-14

Software simulator
Assembler
Programmer's manuals
Device data sheets
Application notes
Assembler manual
Tool kit user's guide
Pocket reference guides
COP8 SIM user's guide

Features

0
0

(Continued)

"tJ

(X)

Simulator Commands

@RAM [ramadd]

ASM [add]

SR [add]
CAPTURE fname
CAPTUREOFF
CYn
DASM [add]

EVAL n [op] [n]

LISTON

Causes a break in execution to
occur when a write to the
specified RAM location is
attempted.
Assembles directly to ROM at
specified address or starting at
last address used by command.
Set breakpoint at the indicated
ROM address.
Saves all hardware outputs in
the file specified.
Stops capture and closes
capture file.
Sets cycle counter.
Disassembles memory to
screen starting at specified
address or last location
disassembled.
Evaluates input in decimal, hex,
and binary. Can do simple
calculations where op may be

LlSTOFF
LOAD filename
PRINTON
PRINTOFF
RAM add [n]
REG
RESET
RESTORE fname

ROM add [n]
SAVE filename

+, -, I,or *.
GO [add] [add]
GOTILadd

SCRIPT fname
STEP [n]

Sets breakpoint at second
address. Go from first address.
Go from the current PC until the
PC = add.

STEPTILadd
QUIT, EXIT

Ordering Information
NSID

Description

Includes:

COPB-TOOL-KIT

COPBOO Designer's
Tool Kit

Software Simulator
Assembler
Programmer's Manual
Assembler Manual
Tool Kit User's Guide

4-15

(1)

Turns on screen listing during
stepping.
Turns off screen listing.
Loads Intel hex format file into
simulator.
Sends all debug output to
printer.
Stops sending debug output to
printer.
Sets RAM location at indicated
address to value specified.
Shows register status in debug
window.
Simulates a hardware reset.
Restores simulator state from a
file created with the SAVE
command.
Sets ROM location at indicated
address to value specified.
Saves the simulator state in the
specified file.
Executes a script file.
Single step execution of n
instructions.
Single step until the PC = add.
Return to DOS.

<
CD
0
"C
3(1)

....::J

....rn
(1)

Section 5
Appendices!
Physical Dimensions

Section 5 Contents
Surface Mount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLCC Packaging ...................................................................
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors

5·2

5-3
5-23
5-27

c....

Dr
(')

/fINational Semiconductor

C
:J

Surface Mount
Cost pressures today are forcing many electronics manufacturers to automate their production lines. Surface mount
technology plays a key role in this cost-savings trend because:

SURFACE MOUNT PACKAGING AT NATIONAL
To help our customers take advantage of this new technology, National has developed a line of surface mount packages. Ranging in lead counts from 3 to 360, the package
offerings are summarized in Table I.

1. The mounting of devices on the PC board surface eliminates the expense of drilling holes;

Lead center spacing keeps shrinking with each new generation of surface mount package. Traditional packages (e.g.,
DIPs) have a 100 mil lead center spacing. Surface mount
packages currently in production (e.g., SOT, SOIC, PCC,
LCC, LDCC) have a 50 mil lead center spacing. Surface
mount packages in production release (e.g., PQFP) have a
25 mil lead center spacing. Surface mount packages in development (e.g., TAPEPAK®) will have a lead center spacing of only 12-20 mils.

2. The use of pick-and-place machines to assemble the PC
boards greatly reduces labor costs;
3. The lighter and more compact assembled products resulting from the smaller dimensions of surface mount
packages mean lower material costs.
Production processes now permit both surface mount and
insertion mount components to be assembled on the same
PC board.

TABLE I. Surface Mount Packages from National

Package
Type

Small Outline
Transistor

Small Outline
IC(SOIC)

(SOn

Package
Material

Plastic Chip
Carrier (PCG)

Plastic Quad
Flat Pack

Leadless Chip
Carrier (LCG)

(PQFP)

(LDCC)

Leaded Chip
Carrier

3n:~~vQ
Ceramic

Plastic

Gull Wing

J-Bend

Gull Wing

Lead Center
Spacing

50 Mils

25 Mils

50 Mils

Tape & Reel
Option

Yes

tbd

Lead Bend

Lead Counts

SOT-23
High Profile
SOT-23
Low Profile

SO-8(*)
SO-14(*)

PCC-20(*)
PCC-28(*)

SO-14 Wide(*)
SO-16(*)
SO-16 Wide(*)
SO-20(*)
SO-24(*)

PCC-44(*)
PCC-68
PCC-84
PCC-124

"In production (or planned) for linear products.

5-3

PQFP-84
PQFP-100
PQFP-132
PQFP-196(*)
PQFP-244

Ceramic

Gull Wing

LCC-18
LCC-20(*)

LDCC-44

LCC-28

LDCC-68

LCC-32
LCC-44 (*)
LCC-48
LCC-52
LCC-68
LCC-84
LCC-124

LDCC-84
LDCC-124

1:
::l

r-----------~----------------------------------------------------------------------------~

Linear functions available in surface mount include:

(1)
(.)

• Op amps

«I

• Comparators

::l

• Regulators

...

TABLE II: Surface Mount Package
Thermal Resistance Range"

LINEAR PRODUCTS IN SURFACE MOUNT

• References
• Data conversion
• Industrial
• Consumer
• Automotive
A complete list of linear part numbers in surface mount is
presented in Table III. Refer to the datasheet in the appropriate chapter of this databook for a complete description of
the device. In addition, National is continually expanding the
list of devices offered in surface mount. If the functions you
need do not appear in Table III, contact the sales office or
distributor branch nearest you for additional information.

Package

Thermal Resistance'"
(eJA.oC/W)

SO-8
SO-14
SO-14 Wide
SO-16
SO-16 Wide
SO-20
SO-24

120-175
100-140
70-110
90-130
70-100
60-90
55-85

PCC-20
PCC-28
PCC-44

70-100
60-90
40-60

• Actual thermal resistance for a particular device depends on die size.
Refer to the datasheet for the actual IIjA value.
··Test conditions: PCB mount (FR4 material), still air (room temperature),
copper traces (150 x 20 x 10 mils).

Automated manufacturers can improve their cost savings by
using Tape-and-Reel for surface mount devices. Simplified
handling results because hundreds-to-thousands of semiconductors are carried on a single Tape-and-Reel pack (see
ordering and shipping information-printed later in this section-for a comparison of devices/reel vs. devices/rail for
those surface mount package types being used for linear
products). With this higher device count per reel (when compared with less than a 100 devices per rail), pick-and-place
machines have to be re-Ioaded less frequently and lower
labor costs result.

Given a max junction temperature of 150°C and a maximum
allowed ambient temperature, the surface mount device will
be able to dissipate less power than the DIP device. This
factor must be taken into account for new designs.
For board conversion, the DIP and surface mount devices
would have to dissipate the same power. This means the
surface mount circuit would have a lower maximum allowable ambient temperature than the DIP circuit. For DIP circuits where the maximum ambient temperature required is
substantially lower than the maximum ambient temperature
allowed, there may be enough margin for safe operation of
the surface mount circuit with its lower maximum allowable
ambient temperature. But where the maximum ambient temperature required of the DIP current is close to the maximum allowable ambient temperature, the lower maximum
ambient temperature allowed for the surface mount circuit
may fall below the maximum ambient temperature required.
The circuit designer must be aware of this potential pitfall so
that an appropriate work-around can be found to keep the
surface mount package from being thermally overstressed
in the application.

With Tape-and-Reel, manufacturers save twice-once from
using surface mount technology for automated PC board
assembly and again from less device handling during shipment and machine set-up.
BOARD CONVERSION

Besides new designs, many manufacturers are converting
existing printed circuit board designs to surface mount. The
resulting PCB will be smaller, lighter and less expensive to
manufacture; but there is one caveat-be careful about the
thermal dissipation capability of the surface mount package.
Because the surface mount package is smaller than the traditional dual-in-line package, the surface mount package is
not capable of conducting as much heat away as the DIP
(Le., the surface mount package has a higher thermal resistance-see Table II).

SURFACE MOUNT LITERATURE

National has published extensive literature on the subject of
surface mount packaging. Engineers from packaging, quality, reliability, and surface mount applications have pooled
their experience to provide you with practical hands-on
knowledge about the construction and use of surface mount
packages.

The silicon for most National devices can operate up to a
150°C junction temperature (check the datasheet for the
rare exception). Like the DIP, the surface mount package
can actually withstand. an ambient temperature of up to
125°C (although a commercial temperature range device
will only be specified for a max ambient temperature of 70°C
and an industrial temperature range device will only be
specified for a max ambient temperature of 85°C). See
AN-336, "Understanding Integrated Circuit Package Power
Capabilities", (reprinted in the appendix of each linear databook volume) for more information.

The applications note AN-450 "Surface Mounting Methods
and their Effect on Product Reliability" is referenced on
each SMD datasheet. In addition, "Wave Soldering of Surface Mount Components" is reprinted in this section for your
information.

5-4

en
c:

....

TABLE III. Linear Surface Mount Current Device listing

Amplifiers and Comparators
Part Number
LF347WM
LF351M
LF451CM
LF353M
LF355M
LF356M
LF357M
LF444CWM
LM10CWM
LM10CLWM
LM308M
LM308AM
LM310M
LM311M
LM318M
LM319M
LM324M
LM339M
LM346M
LM348M
LM358M
LM359M

Data Acquisition Circuits

Part Number

Part Number
ADC0802LCV
ADC0802LCWM
ADC0804LCV
ADC0804LCWM
ADC0808CCV
ADC0809CCV

LM392M
LM393M
LM741CM
LM1458M
LM2901M
LM2902M
LM2903M
LM2904M
LM2924M
LM3403M

ADC0811BCV
ADC0811CCV
ADC0819BCV
ADC0819CCV
ADC0820BCV
ADC0820CCV

LM4250M
LM324M
LM339M
LM365WM
LM607CM
LMC669BCWM
LMC669CCWM
LF441CM

:5:

::::J

DAC0808LCM
DAC0830LCWM
DAC0830LCV
DAC0832LCWM
DAC0832LCV

Industrial Functions

Part Number

LM317LM
LF3334M

LM2931 M-5.0
LM3524M
LM78L05ACM
LM78L12ACM
LM78L15ACM

LM385M
LM385M-1.2

ADC1025BCV
ADC1025CCV
DAC0800LCM
DAC0801LCM
DAC0802LCM
DAC0806LCM
DAC0807LCM

ADC0838BCV
ADC0838CCV
ADC0841BCV
ADC0841CCV
ADC0848BCV
ADC0848CCV
ADC1005BCV
ADC1005CCV

Regulators and References

LM336M-?.5
LF336BM-2.5
LM336M-5.0
LM336BM-5.0
LM337LM

Part Number

(")

Part Number

AH5012CM
LF13331M
LF13509M
LF13333M
LM555CM

LM13600M
LM13700M
LMC555CM
LM567CM
MF4CWM-50

Livi556CM

MF4CWM-lUU
MF6CWM-50
MF10CCWM
MF6CWM-100
MF5CWM

LM567CM
LM1496M
LM2917M

LM79L05ACM
LM79L12ACM
LM79L15ACM
LP2951ACM
LP2951CM

LM3046M
LM3086M
LM3146M

LM385BM-1.2
LM385M-2.5
LM385BM-2.5
LM723CM
LM2931CM

Commercial and Automotive
Part Number

Part Number

LM386M-1
LM592M
LM831M
LM832M
LM833M

LM1837M
LM1851M
LM1863M
LM1865M
LM1870M

LM837M
LM838M
LM1131CM

LM1894M
LM1964V
LM2893M
LM3361AM
LM1881 M

f.5.',.',
sa
5-5

-6
c

:!E

Hybrids

Part Number

.::::s..

LHOO02E
LH4002E

LH0032E
LH0033E

C'O

A FINAL WORD
National is a world leader in the design and manufacture of
surface mount components.
Because of design innovations such as perforated copper
leadframes, our small outline package is as reliable as our
DIP-the laws of physics would have meant that a straight
"junior copy" of the DIP would have resulted in an "S.O."
package of lower reliability. You benefit from this equivalence of reliability. In addition, our ongoing vigilance at each
step of the production process assures that the reliability we
designed in stays in so that only devices of the highest quality and reliability are shipped to your factory.

Package

Package
Designator

Max/Rail

Per Reel·

SO-8
SO-14
SO-14 Wide
SO-16
SO-16 Wide
SO-20
SO-24

M
M
WM
M
WM
M
M

100
50
50
50
50
40
30

2500
2500
1000
2500
1000
1000
1000

V
V
V

50
40
25

1000
1000
500

PQFP-196

TBD

TP-40

100

TBD

E
E

50
25

PCL-20
PCL-28
PCL-44

LCC-20
LCC-44

Our surface mount applications lab at our headquarters site
in Santa Clara, California continues to research (and publish) methods to make it even easier for you to use surface
mount technology. Your problems are our problems.

·Incremental ordering quantities. (National Semiconductor reserves the right
to provide a smaller quantity of devices per Tape-and-Reel pack to preserve
lot or date code integrity. See example below.)

Example: You order 5,000 LM324M ICs shipped in Tapeand-Reel.

When you think "Surface Mount"-think "National"l

• Case 1: All 5,000 devices have the same date code

Ordering and Shipping Information

• You receive 2 SO-14 (Narrow) Tape-end-Reel
packs, each having 2500 LM324M ICs

When you order a surface mount semiconductor, it will be in
one of the several available surface mount package types.
Specifying the Tape-and-Reel method of shipment means
that you will receive your devices in the following quantities
per Tape-and-Reel pack: SMD devices can also be supplied
in conventional conductive rails.

• Case 2: 3,000 devices have date code A and 2,000 devices have date code B
• You receive 3 SO-14 (Narrow) Tape-and-Reel
packs as follows:
Pack # 1 has 2,500 LM324M ICs with date code A
Pack # 2 has 500 LM324M ICs with date code A
Pack # 3 has 2,000 LM324M ICs with date code B

Short-Form Procurement Specification
TAPE FORMAT

Trailer (Hub End)·

Carrier·

Leader (Start End)·

Empty Cavities,
min (Unsealed
Cover Tape)

Empty Cavities,
min (Sealed
Cover Tape)

Filled Cavities
(Sealed
Cover Tape)

Empty Cavities,
min (Sealed
Cover Tape)

Empty Cavities,
min (Unsealed
Cover Tape)

SO-8 (Narrow)

2500

SO-14 (Narrow)

2500

SO-14 (Wide)

1000

Small Outline IC

SO-16 (Narrow)

2500

SO-16 (Wide)

1000

SO-20 (Wide)

1000

SO-24 (Wide)

1000

Plastic Chip Carrier IC
PCC-20

1000

PCC-28

750

PCC-44

500

"The following diagram Identifies these sections of the tape and Pin # 1 device orientation.

5-6

Short-Form Procurement Specification

:l.
D)
n

(Continued)

DEVICE ORIENTATION

3:
o

DIRECTION
OF FEED

TRAILER
, - SECTION

---1~~lfooII"I-----

___

--CARRIER SECTION

- - - - - - - - - J...jI. . .I - - - - - - - - - - - ...l
-----,

>OOOOOOOOOOOOOOOOOOOOOOOOOOO( OOOIOOOOOOOOOOOOOOOO~

II
I

HUB
END

I
i
\

~-"7-'-'"

J'---,---"

I
• EMPTY
CAVITIES
• UNSEALED
COVER TAPE

I
I
I

• EMPTY
. CAVITIES
• SEALED
CDVERTAPE

'i ~"

• FILlfD CAVITIES

•

S~~~~~~R~~~

r:~-_...;..::.,

I
I

~~~,.H-.L- ~~~JNTATIDN

• EMPTY
CAVITIES
• SEALED

___

~O~~~~
0

• EMPTY
CAVITIES
• UNSEALED
COVER TAPE

;;,
I
I

I
I
I

I
I

I _________ JI

I
IL: _________ I

SO-IC
DEVICES

PeC-IC
DEVICES

TLIOO/1132S-7

MATERIALS

• Reel:
(1) Solid 80 pt fibreboard (standard)

• Cavity Tape: Conductive PVC (less than 105 Ohms/Sq)

(2) Conductive fibreboard available

• Cover Tape: Polyester

(3) Conductive plastic (PVC) available

(1) Conductive cover available
TAPE DIMENSIONS (24 Millimeter Tape or Less)

'" ___ Po 1n PITCH CUMUl~JIVE
TAPE TOLERANCE ~ O. 2 mm

DEVICE ORIENTATION

PIN
1

sO-Ie
PCC-IC
TLIOO/1132S-8

5-7

C
::::J

c::

::l

Short-Form Procurement Specification

CI)
(.)

-...

::l

w I

(Continued)

Small Outline IC

SO-8
12±.30 8.0±.10
(Narrow)

5.5±.05 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 6.4±.10

5.2±.10

2.1 ±.10 1.55±.05 30

SO-14
16±.30 8.0±.10
(Narrow)

7.5±.10

1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 6.5±.10

9.0±.10

2.1 ±.10 1.55±.05 40

16±.30 12.0±.10 7.5 ± .10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10

9.5±.10

3.0±.10 1.55±.05 40

SO-14
(Wide)

SO-16
16±.30 8.0±.10
(Narrow)
SO-16
(Wide)

SO-20
(Wide)

SO-24
(Wide)

7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 6.5±.10

16±.30 12.0±.10 7.5±.10

10.3±.10 2.1 ±.10 1.55±.05 40

1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10 10.76±.10 3.0±.10 1.55±.05 40

24±.30 12.0±.10 11.5±.10 1.75± .10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10 13.3±.10 3.0±.10 2.05±.05 50
24±.30 12.0±.10 11.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10 15.85±.10 3.0±.10 2.05±.05 50

Plastic Chip Carrier IC

PCC-20

16±.30 12.0±.10 7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 9.3±.10

PCC-28

24±.30 16.0±.10 11.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 13.0±.10 13.0±.10 4.9±.10 2.05±.05 50

Note 1:

9.3±.10

4.9±.10 1.55±.05 40

Ao. 80 and Ko dimensions are measured 0.3 mm above the inside wall of the cavity bottom.

Note 2: Tape with components shall pass around a mandril radius R without damage.
Note 3: Cavity tape material shall be PVC conductive (less than 10S Ohms/Sq).
Note 4: Cover tape material shall be polyester (30-65 grams peel-back force).
Note 5: D1 Dimension is centered within cavity.
Note 6: All dimensions are in millimeters.

REEL DIMENSIONS

TMAX

I-B

LABEL-

UJ 0:::

-1«

«e:

~0:::1D
UJo:::

:::c«

=:::::::=:

I-

~;;;;;::;:::::;:::;::::;:h:

A- 42a = 4.6

T (OC)

100 110 120 130 140 150 160,170 180
Tg

TL/DD/11325-11

FIGURE 1. Thermal Expansion and Glass Transition Temperature
5-11

s:
o
c

::::s

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:!:
CD

-...
(.)

a:s

::s

Wave Soldering of Surface Mount Components (Continued)
Since the package is of very small mass and experiences a
rather sharp thermal shock followed by stresses created by
the mismatch in expansion, the results show the package
being susceptible to failures after being immersed in excess
of 6 seconds in a solder pot. In the second case where the
packages were mounted, the effect of severe temperature
excursion was reduced. In the second case where the packages were mounted, the effect of severe temperature excursion was reduced. In any case, because of the repeated
treatment, the package had failures when subjected in excess of 6 seconds immersion in hot solder. The safety margin is therefore recommended as maximum 4 seconds immersion. If packages were immersed longer than 4 seconds, there is a probable chance of finding some long term
reliability failures even though the immediate electrical test
data could be acceptable.

85% relative humidity. Once cycle of approximately 100
hours has been shown to be equivalent to 2000 hours in the
85/85 condition. Should the packages start to fail within the
first cycle in the test, it is anticipated that the boards with
these components in the harsh operating environment
(85°C/85% RH) will experience corrosion and eventual
electrical failures within its first 2000 hours of operation.
Whether this is significant to a circuit board manufacturer
will obviously be dependent on the products being manufactured and the workmanship or reliability standards. Generally in systems with a long warranty and containing many
components, it is advisable both on a reputation and cost
basis to have the most reliable parts available.
TEST RESULTS
The comparison of vapor phase and wave-soldering upon
the reliability of molded Small-Outline packages was performed using the bias moisture test (see Table IV). It is
clearly seen that vapor phase reflow soldering gave more
consistent results. Wave-soldering results were based on
manual operation giving variations in soldering parameters
such as temperature and duration.

Finally, Table VI examines the bias moisture test performed
on surface mount (SOIC) components manufactured by various semiconductor houses. End point was an electrical test
after an equivalent of 6000 hours in a 85/85 test. Failures
were analyzed and corrosion was checked for in each case
to detect flaws in package integrity.

TABLE IV. Vapor Phase vs. Wave Solder

TABLE VI. U.S. Manufacturers Integrated Circuits
Reliability in Various Solder Environments
(# Failure/Total Tested)

1. Vapor phase (60 sec. exposure @215°C)
= 9 failures/1723 samples
= 0.5% (average over 32 sample lots)
2. Wave solder (2 sec total immersion @ 260°C)
= 16 failures/1201 samples
= 1.3% (average over 27 sample lots)
Package: SO-14 lead
Test:
Bias moisture test 85% R.H.,
85°C for 2000 hours
Device:
LM324M
In Table V we examine the tolerance of the Small-Outlined
(SOIC) package to varying immersion time in a hot solder
pot. SO-14 lead molded packages were subjected to the
bias moisture test after being treated to the various soldering conditions and repeated four (4) times. End point was an
electrical test after an equivalent of 4000 hours 85/85 test.
Results were compared for packages by itself against packages which were surface-mounted onto a FR-4 printed wire
board.

Unmounted

Mounted

0/114

0/84

Solder Dip
2 sec@ 260·C

2/144 (1.4%)

0/85

Solder Dip
4 sec@ 260°C

0/83

Solder Dip
6 sec@ 260°C

13/248 (5.2%)

1176 (1.3%)

Solder Dip
10 sec @260°C

14/127 (11.0%)

3179 (3.8%)

Package:
Device:

Vapor
Phase
30 sec

Wave
Solder
2sec

Wave
Solder
4sec

Wave
Solder
6sec

Wave
Solder
10sec

ManufA
Manuf B
ManufC

8/30*
2/30*
0/30

1/30·
8/30*
0/29

0.30
2/30*
0/29

12/30*
22/30*
0/30

16/30*
20/30*
0/30

ManufD
Manuf E
Manuf F
ManufG

1/30*
1/30**
0/30
0/30

0/30
0/30
0/30
0/30

12/30*
0/30
0/30
0/30

14/30*
0/30
0/30
0/30

2/30*
0/30
0/30
0/30

·Corrosion-failures
··No Visual Defects-Non-corrosion failures
Test: Accelerated Bias Moisture Test; 85% R.H./85'C, 6000 equivalent
hours.

SUMMARY
Based on the results presented, it is noted that surfacemounted components are as reliable as standard molded
DIP packages. Whereas DIPs were never processed by being totally immersed in a hot solder wave during printed circuit board soldering, surface mounted components such as
SOles (Small Outline) are expected to survive a total immersion in the hot solder in order to capitalize on maximum
population on boards. Being constructed from a thermoset
plastic of relatively low Tg compared to the soldering temperature, the ability of the package to survive is dependent
on the time of immersion and also the cleanliness of material. The results indicate that one should limit the immersion
time of package in the solder wave to a maximum of 4 seconds in order to truly duplicate the reliability of a DIP. As the
package size is reduced, as in a SO-8 lead, the requirement
becomes even more critical. This is shown by the various
manufacturers' performance. Results indicate there is room
for improvement since not all survived the hot solder immersion without compromise to lower reliability.

TABLE V. Summary of Wave Solder Results
(85% R.H./85°C Bias Moisture Test, 2000 hours)
(# Failures/Total Tested)

ControllVapor Phase
15 sec @ 215°C

Package
SO-8

SO-14 lead
LM324M
5-12

The SO (small outline) package has been developed to
meet customer demand for ever-increasing miniaturization
and component density.

All SO packages tested on 85%RA, 85°C were assembled
on PC conversion boards using vapor-phase reflow soldering. With this approach we are able to measure the effect of
surface mounting methods on reliability of the process. As
illustrated in Figure A no significant difference was detected
between the long term reliability performance of surface
mounted S.O. packages and the DIP control product for up
to 6000 hours of accelerated 85%/85°C testing.

S.O. Package

_I 1-

(1)

In order to achieve reliability performance comparable to
DIPs-SO packages are designed and built with materials
and processes that effectively compensate for their small
size.

COMPONENT SIZE COMPARISON

SURFACE-MOUNT PROCESS FLOW

TYPICALLY 0.050" LEADSPACING

The standard process flowcharts for basic surface-mount
operation and mixed-lead insertion/surface-mount operations, are illustrated on the following pages.

TL/DD/11325-12

Standard DIP Package

Usual variations encountered by users of SO packages are:
• Single-sided boards, surface-mounted components only.
• Single-sided boards, mixed-lead inserted and surfacemounted components.

r--,
I

• Double-sided boards, surface-mounted components only.

L_-'

-.J 1-

• Double-sided boards, mixed-lead inserted and surfacemounted components.
In consideration of these variations, it became necessary for
users to utilize techniques involving wave soldering and adhesive applications, along with the commonly-used vaporphase solder reflow soldering technique.

TYPICALLY 0.100" LEADSPACING

TL/DD/11325-13

PRODUCTION FLOW

Because of its small size, reliability of the product assembled in SO packages needs to be carefully evaluated.

Basic Surface-Mount Production Flow

SO packages at National were internally qualified for production under the condition that they be of comparable reliability performance to a standard dual in line package under
all accelerated environmental tests. Figure A is a summary
of accelarated bias moisture test performance on 30V bipolar and 15V CMOS product assembled in SO and DIP (control) packages.
.

COMPONENTS

SUBSTRATES

V+= 15VCMOS
30V BIPOLAR
85% RH/85 0 C
TEST CON DITION
DIP

2000

4000

6000

TEST TIME (HRS)
TLlDD/11325-14

FIGURE A

TLlDD/11325-15

5-13

...c

Small Outline (SO) Package Surface Mounting MethodsParameters and Their Effect on Product Reliability

3:
o

C
:::J

-...
c:::

:::l

Thermal stress of the packages during surface-mounting
processing is more severe than during standard DIP PC
board mounting processes. Figure B illustrates package
temperature versus wave soldering dwell time for surface
mounted packages (components are immersed into the
molten solder) and the standard DIP wave soldering process. (Only leads of the package are immersed into the molten solder).

Mixed Surface-Mount and Axial-Leaded Insertion
Components Production Flow

G)
(.)

:::l

SOLDER TEMPERATURE 260°C
250
200
u

150
100
50

1 2 3 4 5 6 7 8 9 10 SEC.
DWELL TIME
TL/DD/11325-17

FIGURE B

For an ideal package, the thermal expansion rate of the
encapsulant should match that of the leadframe material in
order for the package to maintain mechanical integrity during the soldering process. Unfortunately, a perfect matchup
of thermal expansion rates with most presently used packaging materials is scarce. The problem lies primarily with the
epoxy compound.
Normally, thermal expansion rates for epoxy encapsulant
and metal lead frame materials are linear and remain fairly
close at temperatures approaching 160°C, Figure C. At lower temperatures the difference in expansion rate of the two
materials is not great enough to cause interface separation.
However, when the package reaches the glass-transition
temperature (Tg) of epoxy (typically 160-165°C), the thermal expansion rate of the encapsulant increases sharply,
and the material undergoes a transition into a plastic state.
The epoxy begins to expand at a rate three times or more
greater than the metal leadframe, causing a separation at
the interface.

TL/DD/11325-16

z:
o

enz:

«
a..
x

LIJ

-l

::::::E

LIJ

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I-

100 110 120 130 140 150 1601170 180

T(OC)
TL/DD/11325-1B

FIGUREC

5-14

(J)

The basic component-placement systems available are
classified as:

When this happens during a conventional wave soldering
process using flux and acid cleaners, process residues and
even solder can enter the cavity created by the separation
and become entrapped when the material cools. These
contaminants can eventually diffuse into the interior of the
package, especially in the presence of moisture. The result
is die contamination, excessive leakage, and even catastrophic failure. Unfortunately, electrical tests performed immediately following soldering may not detect potential flaws.

(a) In-line placement

dwell time 2 seconds

e, X-V moving

Multiple pickup heads

Whole array of components placed onto the PCB at
the same time

SO packages vapor-phase reflow soldered on
PC boards
Group 3-6 SO packages wave soldered on PC boards
dwell time 4 seconds

Either a X-V moving table system or a
pickup system used

(d) Sequential/simultaneous placement

Standard DIP package

456-

Boards indexed under head and respective components placed

-Individual components picked and placed onto boards

Group 2 -

Group 3 -

Figure D is a summary of accelerated bias moisture test
performance on the 30V bipolar process.
Group 1 -

Fixed placement stations

X- Y moving table, multiple pickup heads system

- Components placed on PCB by successive or simultaneous actuation of pickup heads
The SO package is treated almost the same as surfacemount, passive components requiring correct orientation in
placement on the board.
Pick and Place Action

dwell time 6 seconds
dwell time 10 seconds

....t-

..:
c::

#5 (6 SEC)

:::

#4 (4 SEC)

....
c::

2000

4000

6000

TEST TIME (HRS)
TL/00/11325-19

FIGURED

It is clear based on the data presented that SO packages
soldered onto PC boards with the vapor phase reflow process have the best long term bias moisture performance
and this is comparable to the performance of standard DIP
packages. The key advantage of reflow soldering methods
is the clean environment that minimized the potential for
contamination of surface mounted packages, and is preferred for the surface-mount process.

TLl00/11325-20

BAKE

This is recommended, despite claims made by some solder
paste suppliers that this step be omitted.
The functions of this step are:

When wave soldering is used to surface mount components
on the board, the dwell time of the component under molten
solder should be no more than 4 seconds, preferrably under
2 seconds in order to prevent damage to the component.
Non-Halide, or (organic acid) fluxes are highly recommended.

• Holds down the solder globules during subsequent ref low
soldering process and prevents expulsion of small solder
balls.
• Acts as an adhesive to hold the components in place during handling between placement to reflow soldering.
• Holds components in position when a double-sided surface-mounted board is held upside down going into a vapor-phase ref low soldering operation.

PICK AND PLACE

The choice of automatic (all generally programmable) pickand-place machines to handle surface mounting has grown
considerably, and their selection is based on individual
needs and degree of sophistication.

• Removes solvents which might otherwise contaminate
other equipment.
• Initiates activator cleaning of surfaces to be soldered.
• Prevents moisture absorption.

5-15

D)
(')

(b) Sequential placement

Most soldering processes involve temperatures ranging up
to 260°C, which far exceeds the glass-transition temperature of epoxy. Clearly, circuit boards containing SMD packages require tighter process controls than those used for
boards populated solely by DIPs.

c:::
.....

c::::

::::J

c
:::s

CJ)

u
m

The process is moreover very simple. The usual schedule is
about 20 minutes in a 65°C-95°C (dependent on solvent
system of solder paste) oven with adequate venting. Longer
bake time is not recommended due to the following reasons:

In-Line Conveyorized Vapor-Phase Soldering
CONDENSATION

J ~L

:::s
en

• The flux will degrade and affect the characteristics of the
paste.

"roR

PRODUCT

----I-BaT-~-J----illill----

• Solder globules will begin to oxidize and cause solderability problems.
• The paste will creep and after reflow, may leave behind
residues between traces which are difficult to remove and
vulnerable to electro-migration problems.

COILS

REFLOW SOLDERING
IMMERSION HEATER

There are various methods for reflowing the solder paste,
namely:

TLlDD/11325-21

The question of thermal shock is asked frequently because
of the relatively sharp increase in component temperature
from room temperature to 215°C. SO packages mounted on
representative boards have been tested and have shown
little effect on the integrity of the packages. Various packages, such as cerdips, metal cans and TO-5 cans with glass
seals, have also been tested.

• Hot air reflow
• Infrared heating (furnaces)
• Convectional oven heating
• Vapor-phase reflow soldering
• Laser soldering
For SO applications, hot air reflow/infrared furnace may be
used for low-volume production or prototype work, but vapor-phase soldering reflow is more efficient for consistency
and speed. Oven heating is not recommended because of
"hot spots" in the oven and uneven melting may result. Laser soldering is more for specialized applications and requires a great amount of investment.

Vapor-Phase Furnace

HOT GAS REFLOWIINFRARED HEATING

A hand-held or table-mount air blower (with appropriate orifice mask) can be used.
The boards are preheated to about 100°C and then subjected to an air jet at about 260°C. This is a slow process and
results may be inconsistent due to various heat-sink properties of passive components.
Use of an infrared furnace is the next step to automating the
concept, except that the heating is promoted by use of IR
lamps or panels. The main objection to this method is that
certain materials may heat up at different rates under IR
radiation and may result in damage to these components
(usually sockets and connectors). This could be minimized
by using far-infrared (non-focused) system.
VAPOR-PHASE REFLOW SOLDERING
TLlDD/11325-22

Currently the most popular and consistent method, vaporphase soldering utilizes a fluoroinert fluid with excellent
heat-transfer properties to heat up components until the solder paste reflows. The maximum temperature is limited by
the vapor temperature of the fluid.

Batch-Fed Production Vapor-Phase Soldering Unit
SECONDARY
COILS

The commonly used fluids (supplied by 3M Corp) are:
• FC-70, 215°C vapor (most applications) or FX-38
• FC-71 , 253°C vapor (low-lead or tin-plate)

PRIMARY COILS

HTC, Concord, CA, manufactures equipment that utilizes
this technique, with two options:
• Batch systems, where boards are lowered in a basket and
subjected to the vapor from a tank of boiling fluid.
• In-line conveyorized systems, where boards are placed
onto a continuous belt which transports them into a concealed tank where they are subjected to an environment
of hot vapor.
Dwell time in the vapor is generally on the order of 15-30
seconds (depending on the mass of the boards and the
loading density of boards on the belt).

TL/DD/11325-23

5-16

Solder JoInts on a SO-14 Package on PCB

r:::
....

D)
(')
(1)

s::
o

r:::

::::J

TL/DD/11325-24

TL/DD/11325-25

The SO package is molded out of clean, thermoset plastic
compound and has no particular compatibility problems with
most printed circuit board substrates.

The typical lithographic "footprints" for SO packages are
illustrated below. Note that the 0.050" lead center-center
spacing is not easily managed by commercially-available air
pressure, hand-held dispensers.

PRINTED CIRCUIT BOARD

Using a stainless-steel, wire-mesh screen stencilled with an
emulsion image of the substrate pads is by far the most
common and well-tried method. The paste is forced through
the screen by a V-shaped plastic squeegee in a sweeping
manner onto the board placed beneath the screen.

The package can be reliably mounted onto substrates such
as:
• G10 or FR4 glass/resin
• FR5 glass/resin systems for high-temperature
applications

The setup for SO packages has no special requirement
from that required by other surface-mounted, passive components. Recommended working specifications are:

• Polymide boards, also high-temperature
applications
• Ceramic substrates

• Use stainless-steel, wire-mesh screens, # 80 or # 120,
'."!!re d!:!mct~r 2.6 m:!:. Rl!!~ cf thu~~: ~~:.h cpcr.;ng
should be approximately 2.5-5 times larger than the average particle size of paste material.

General requirements for printed circuit hmmfR ArA:
• Mounting pads should be solder-plated whenever
applicable.

• Use squeegee of Durometer 70.

• Solder masks are commonly used to prevent solder bridging of fine lines during soldering.

• Experimentation with squeegee travel speed is recommended, if available on machine used.

The mask also protects circuits from processing chemical
contamination and corrosion.

• Use solder paste of mesh 200-325.

If coated over pre-tinned traces, residues may accumulate
at the mask/trace interface during subsequent reflow,
leading to possible reliability failures.

• Mesh pattern should be 90 degrees, square grid.

Recommended application of solder resist on bare, clean
traces prior to coating exposed areas with solder.

• Snap-off height of screen should not exceed
damage to screens and minimize distortion.

• Emulsion thickness of 0.005" usually used to achieve a
solder paste thickness (wet) of about 0.008" typical.

General requirements for solder mask:
-

Good pattern resolution.

Complete coverage of circuit lines and resistance to
flaking during soldering.

Adhesion should be excellent on substrate material to
keep off moisture and chemicals.

Compatible with soldering and cleaning requirements.

Va" , to avoid

SOLDER PASTE

Selection of solder paste tends to be confusing, due to numerous formulations available from various manufacturers.
In general, the following guidelines are sufficient to qualify a
particular paste for production:
• Particle sizes (see photographs below). Mesh 325 (approximately 45 microns) should be used for general purposes, while larger (solder globules) particles are preferred for leadless components (LCG). The larger particles
can easily be used for SO packages.

SOLDER PASTE SCREEN PRINTING

With the initial choice of printed circuit lithographic design
and substrate material, the first step in surface mounting is
the application of solder paste.

5-17

C
::l

o
:E

-...
Q)
(.)

::l

CJ)

• Uniform particle distribution. Solder globules should be
spherical in shape with uniform diameters and minimum
amount of elongation (visual under 100/200 X magnification). Uneven distribution causes uneven melting and subsequent expulsion of smaller solder balls away from their
proper sites.

• Composition, generally 60/40 or 63/37 Sn/Pb. Use 62/36
Sn/Pb with 2% Ag in the presence of Au on the soldering
area. This formulation reduces problems of metal leaching
from soldering pads.
• RMA flux system usually used.
• Use paste with aproximately 88-90% solids.

••••
l ••••

RECOMMENDED SOLDER PADS FOR SO PACKAGES

SO-16L,SO-20

50-8,50-14,50-16
0.04S" : O.OOS"

r····~

L•••• ~05.

0.24S"

0.030" :O.OOS"

0.160"

-l I- --l

0.420· MIN

!-O.OSO"TYP
TL/DD/11325-26

SOT-23
0.030" :O.OOS"1

0.3].005.

0.030" :O.OOS"-.I

1- --l

004S"
:O.OOS"

1-~TYp
TLlDD/11325-27

012['!~.3;~.
TLlDD/11325-28

Comparison of Particle Size/Shape of Various Solder Pastes
200 x Alpha (62/36/2)

200 X Kester (63/37)

TLlDD/11325-30

TLlDD/11325-29

5-18

r:::::
-.

Comparison of Particle Size/Shape of Various Solder Pastes (Continued)

(")

200 x Fry Metal (63/37)

Solder Paste Screen on Pads

3:
o

r:::::

::l

TL/DD/11325-32

TL/DD/11325-31

200 ESL (63/37)

TL/DD/11325-33

5-19

C
:::J

::E
CD

-...
(.)

:::J

CLEANING

Hot·Alr Rework Machine

The most critical process in surface mounting SO packages
is in the cleaning cycle. The package is mounted very close
to the surface of the substrate and has a tendency to collect
residue left behind after reflow soldering.
Important considerations in cleaning are:
• Time between soldering and cleaning to be as short as
possible. Residue should not be allowed to solidify on the
substrate for long periods of time, making it difficult to
dislodge.
• A low surface tension solvent (high penetration) should be
employed. Solvents commercially available are:
Freon TMS (general purpose)
Freon TE35/TP35 (cold-dip cleaning)
Freon TES (general purpose)

TL/DD/11325-35

lead tips
onto the
position,
standard

It should also be noted that these solvents generally will
leave the substrate surface hydrophobic (moisture repellent), which is desirable.

WAVE SOLDERING

Prelete or 1,1,1-Trichloroethane
Kester 5120/5121

In a case where lead insertions are made on the same
board as surface-mounted components, there is a need to
include a wave-soldering operation in the process flow.

• A defluxer system which allows the workpiece to be subjected to a solvent vapor, followed by a rinse in pure solvent and a high-pressure spray lance are the basic requirments for low-volume production.

Two options are used:
• Surface mounted components are placed and vapor
phase reflowed before auto-insertion of remaining components. The board is carried over a standard wave-solder
system and the underside of the board (only lead-inserted
leads) soldered.

• For volume production, a conveyorized, multiple hot solvent spray/jet system is recommended.
• Rosin, being a natural occurring material, is not readily
soluble in solvents, and has long been a stumbling block
to the cleaning process. In recent developments, synthetic flux (SA flux), which is readily soluble in Freon TMS
solvent, has been developed. This should be explored
where permissible.

• Surface-mounted components are placed in position, but
no solder paste is used. Instead, a drop of adhesive about
5 mils maximum in height with diameter not exceeding
25% width of the package is used to hold down the package. The adhesive is cured and then proceeded to autoinsertion on the reverse side of the board (surface-mounted side facing down). The assembly is then passed over a
"dual wave" soldering system. Note that the surfacemounted components are immersed into the molten solder.

The dangers of an inadequate cleaning cycle are:
• Ion contamination, where ionic residue left on boards
would cause corrosion to metallic components, affecting
the performance of the board.
• Electro-migration, where ionic residue and moisture present on electrically-biased boards would cause dentritic
growth between close spacing traces on the substrate,
resulting in failures (shorts).

Lead trimming will pose a problem after soldering in the
latter case, unless the leads of the insertion components
are pre-trimmed or the board specially designed to localize
certain areas for easy access to the trim blade.

REWORK

The controls required for wave soldering are:

Should there be a need to replace a component or re-align
a previously disturbed component, a hot air system with appropriate orifice masking to protect surrounding components may be used.

• Solder temperature to be 240-260°C. The dwell time of
components under molten solder to be short (preferably
kept under 2 seconds), to prevent damage to most components and semiconductor devices.

When rework is necessary in the field, specially-designed
tweezers that thermally heat the component may be used to
remove it from its site. The replacement can be fluxed at the

• RMA (Rosin Mildly Activated) flux or more aggressive OA
(Organic Acid) flux are applied by either dipping or foam
fluxing on boards prior to preheat and soldering. Cleaning
procedures are also more difficult (aqueous, when OA flux
is used), as the entire board has been treated by flux (unlike solder paste, which is more or less localized). Nonhalide OA fluxes are highly recommended.

Hot·Alr Solder Rework Station

RETRACT POSITION

HEAT SHIELD

//~G
-!:z:r'T:E::':'-BOARD ON

or, if necessary, solder paste can be dispensed
pads using a varimeter. After being placed into
the solder is reflowed by a hot-air jet or even a
soldering iron.

• Preheating of boards is essential to reduce thermal shock
on components. Board should reach a temperature of
about 100°C just before entering the solder wave.
• Due to the closer lead spacings (0.050" vs 0.100" for
dual-in-line packages), bridging of traces by solder could
occur. The reduced clearance between packages also
causes "shadowing" of some areas, resulting in poor solder coverage. This is minimized by dual-wave solder systems.

x-v TABLE

HOT AIRTL/DD/11325-34

5-20

CJ)

...c:::

Mixed Surface Mount and Lead Insertion

ADHESIVE

/\
~f=!l
(a) Same Side

c::t .

(b) Opposite Sides

tttt
PREHEAT

TURBULENT

FOAM FLUXER

WAVE
SOLDER FLOW
TL/DD/11325-36

Dual Wave

A typical dual-wave system is illustrated below, showing the
various stages employed. The first wave typically is in turbulence and given a transverse motion (across the motion of
the board). This covers areas where "shadowing" occurs. A
second wave (usually a broad wave) then proceeds to perform the standard soldering. The departing edge from the

sc!der is such to

redL!c~ "~c!c!~~,"

:.r.d :: :t!!1 fl!rth~r r:dt!::d

by an air knife placed close to the final soldering step. This
air knife will blow off excess solder (still in the fluid stage)
which would otherwise cause shorts (bridging) and solder
bumps.
AQUEOUS CLEANING
• For volume production, a conveyorized system is often
used with a heated recirculating spray wash (water temperature 130°C), a final spray rinse (water temperature
45-55°C), and a hot (120°C) air/air-knife drying section.
• For low-volume production, the above cleaning can be
done manually, using several water rinses/tanks. Fastdrying solvents, like alcohols that are miscible with water,
are sometimes used to help the drying process.

TL/DD/11325-37

CONFORMAL COATING
Conformal coating is recommended for high-reliability PCBs
to provide insulation resistance, as well as protection
against contamination and degradation by moisture.

• Neutralizing agents which will react with the corrosive materials in the flux and produce material readily soluble in
water may be used; the choice depends on the type of flux
used.

Requirements:

• Final rinse water should be free from chemicals which are
introduced to maintain the biological purity of the water.
These materials, mostly chlorides, are detrimental to the
assemblies cleaned because they introduce a fresh
amount of ionizable material.

• Complete coating over components and solder joints.
• Thixotropic material which will not flow under the packages or fill voids, otherwise will introduce stress on solder
joints on expansion.
• Compatibility and possess excellent adhesion with PCB
material/ components.
• Silicones are recommended where permissible in
application.
5-21

Min

Max

Min

Max

Min

Max

Min

Max

0.985 sq.
(25.02)

0.995 sq.
(25.27)

0.165 sq.
(4.191)

0.180 sq.
(4.572)

0.945 sq.
(24.00)

0.955 sq.
(24.26)

0.910 sq.
(23.11)

0.930 sq.
(23.62)

"l>

1.185 sq.
(30.10)

1.195 sq.
(30.36)

0.165 sq.
(4.191)

0.180 sq.
(4.572)

1.150 sq.
(29.21)

1.158 sq.
(29.41)

1.110 sq.
(28.20)

1.130 sq.
(28.70)

G')

124

1.685 sq.
(49.13)

1.695 sq.
(49.39)

0.180 sq.
(4.572)

0.200 sq.
(5.080)

1.650 sq.
(41.91)

1.658 sq.
(42.11)

1.610 sq.
(40.90)

1.630 sq.
(41.40)

TABLE III. Package Thermal Resistance
(Deg. C/Watt, Junction-to-Amblent, Board Mount)
Device Size

Lead Count
1,000 MII2

10,000 Mil2

102

100,000 MII2

84*

124*

"Estimated values

and development have gone into steadily improving our
P-DIP quality and maintaining a leadership position in plastic
package reliability. All of this technology can be directly applied to the PLCC. Table V shows the results of applying this
technology to the PLCC. As we make further advances in
plastic package reliability, these will also be applied to the
PLCC.

Package Design Criteria
Experience has taught us there are certain criteria to the
PLCC design which must be followed to provide the user
with the proper mechanical and thermal performance.
These requirements should be carefully reviewed by the
user when selecting suppliers for devices in PLCC. Some of
these are covered by the JEDEC registration and some are
not. These important requirements are listed in Table IV.

Socl0.004
(1.11Z±0.102)
UVWINDDW

5-29

en
c

"iii

cQ)

16 Lead (0.300" Wide) Molded Small Outline Package, JEDEC
NS Package Number M 16B

o
m
u

d
.
.
inches
All imenslons are In millimeters

"iii

>.c
a.
LEAD NO 1
IDENTIFICATION

0.2914-0.2992

I~~~--------------~ '~. '~~:j::~:'
~.~ .:;~:::.:::.

~II
lliIj-H
0.0925-0.1043
2.35-2.55

I I';'I;'® I+® I-I

~n'm""'l

0.0040-0.0118

,U,,", L _ _
PLANE

[~H'~_

--rI

0.014

It.=.l..1:.!....
0Jifu1

"ii:35

"'m~

ALL LEADS
0.0160-0.0500 TYP ALL LEADS
0.40-1.27

ALL LEAD TIPS

WI6B(REVF)

20 Lead (0.300" Wide) Molded Small Outline Package, JEDEC
NS Package Number M20B
All dimensions are in inches (millimeters)

rir20

0.394-0.419

~·,~:t' ; : : ;:;: ;:;: :; : ;: : ;: ;: : ;: :;: ;: ;: : ;: ;: : :;:;: : :;: ;~
1

910--r
..!!:!!!!!.MAX
(0.254)

0.093 -0.104
(2.362 -2.642)

8' MAX TYP

t=~=====:;~Pl ""+M
0.1109-0.013

TYP ALL LEADS

0.016-0.050
'-(0.406-1.270)
TYP ALL LEADS

•

f~
t
(03561

miliilt16rii15:::.

0050

(l~~a)

JL
'

IL~PLANE

0014-0020yyp
(0.356 -0 508)

...!!Jl!!!TYP

lO 203)

5-30

M200("'VF)

28 Lead (0.300" Wide) Molded Small Outline Package, JEDEC
NS Package Number M288
All dimensions are in inches (millimeters)

0.420 (10.65)
0.393 (10.00)

!
I'

0.030 (0.75) 450
0.009 (0.25)x

-I

0.713 (18.10)
0.696 (17.70)

:::r:~fi:;:=====tt=-1=~::;~"1::::; g::~l
\Je~:

0.050 (1.27)

0.020 (0.49)
0.013 (0.35)

Bse

0.012 (0.30)
0.003 (0.10)

0.050 (1.27)
0.015 (0.40)

W288 (REV A)

20 Lead (0.300" Wide) Molded Dual-in-Line Package
NS Package Number N20A
1.013-1.040
(25.73-26.42)

0.092 XO.OlO
(2.l37 X 0.762)
MAX OP

=:1

~~=======17===16==1=5==1=4==1l==1=2==1=1~

PIN NO.lIDENT

All dimensions are in inches (millimeters)

t0.260 ±O.OoS
(6.604 ±0.127)

(~:~:~)J
MIN

0.032±0'00S~O
19

(0.81liO.127)

RAO

PIN NO. lIDENT~

~~~~~~~~~

OPTION 2

D.loO-0.l20

~
0.325

~~:~~

0.065
(1.651)

~h-~ri-~~~M-~~n-~
0.009_0.o1JJ
(0.229-0.381 )
TYP
0.060 :1:0.005
(1.524:1:0.127)

0.020
(0.508)
MIN

f8.25S +1.016)
~
-0.381
N20AIREVGI

5-31

en
c
"en
c

28 Lead (0.600" Wide) Molded Dual-in-Line Package
NS Package Number N288
All dimensions are in inches (millimeters)

E
is

m
(,)
"en
>.c
D.

PIN NO.1 10ENT

1.393-1.420 --------I~
~-------(35.38-36.07)

0.125-0.145
(3.175-3.683)
N28B(REV EI

40 Lead (0.600" Wide) Molded Dual-in-Line Package
NS Package Number N40A
All dimensions are in inches (millimeters)

1------------(~;~:=!zO~:)------------I·1
ZI

0.062
(1.575)
RAO

PIN ND.lIDENT

0.550±0.005

Cr.~~~~~~~~~~~~~~~~~rT.~+~~~~~~

•.'m

0.075 to.DI5
(1.905 iO.381)

N40A(REVE)

5-32

44 Lead Molded Plastic Leaded Chip Carrier
NS Package Number V44A
All dimensions are in inches [millimeters]

0.017:1:0.004 TYP
[0.4.3:1:0.10]
45 0 X 0.045
[1.14]
39
0.029±0.003 T P

[O.H±O.OS]

Y
0.610:1:0.020
[15.49±0.51j TYP

SEATING PLANE
17

L' 5'
-l

MIN TYP

'2S 0 . 050
[1.27jTYP

0.1 05±0.0 15 TYP
[2.67:1:0.3S]

0.500
[12.70]TYP

0.165-0.1S0

1-----1- [4.19-4.57] TYP

VHA (REV K)

68 Lead Molded Plastic Leaded Chip Carrier
NS Package Number V68A
All dimensions are in inches [millimeters]
0.017:1:0.004 TYP
[0.43±0.10]
45 0 X 0.045

[1.14]

10 , { f - - - - - - - - T - - - - - 1 h 60
0.029±0.003 TYP

[O.74±O.OS]
0.910±0.020 TYP
[23.11±0.51]

SEATING PLANE
26

O.SOO

3
0.050 TYP
[1.27]

[20.32] TYP
V68A (REV J)

5-33

· NOTES

ttlNational Semiconductor
Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
literature.
This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
For datasheets on new products and devices still in production but not found in a databook, please contact the National
Semiconductor Customer Support Center at 1-800-272-9959.
We are interested in your comments on our technical literature and your suggestions for improvement.
Please send them to:
Technical Communications Dept. M/S 16-300
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090

ADVANCED BiCMOS LOGIC (ABTC, IBF, BiCMOS SCAN, LOW VOLTAGE
BiCMOS, EXTENDED TTL TECHNOLOGY) DATABOOK-1994
ABTC/BCT Description and Family Characteristics • ABTC/BCT Ratings, Specifications and Waveforms
ABTC Applications and Design Considerations • Quality and Reliability. Integrated Bus Function (IBF) Introduction
54174ABT3283 Synchronous Datapath Multiplexer. 74FR900/25900 9-Bit 3-Port Latchable Datapath Multiplexer
54174ACTQ3283 32-Bit Latchable Transceiver with Parity Generator/Checker and Byte Multiplexing
SCAN18xxxA BiCMOS 5V Logic with Boundary Scan. 74LVT Low Voltage BiCMOS Logic
VME Extended TTL Technology for Backplanes

ALS/AS LOGIC DATABOOK-1990
Introduction to Advanced Bipolar Logic • Advanced Low Power Schottky. Advanced Schottky

ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD CELLS-1987
SSI/MSI Functions • Peripheral Functions. LSIIVLSI Functions • DeSign Guidelines • Packaging

CMOS LOGIC DATABOOK-1988
CMOS AC Switching Test Circuits and Timing Waveforms. CMOS Application Notes. MM54HC/MM74HC
MM54HCT/MM74HCT. CD4XXX. MM54CXXX/MM74CXXX. Surface Mount

CLOCK GENERATION AND SUPPORT (CGS) DESIGN DATABOOK-1994
Low Skew Clock Buffers/Drivers • Video Clock Generators • Low Skew PLL Clock Generators
Crystal Clock Generators

COP8™ DATABOOK-1994
COP8 Family • COP8 Applications • MICROWIRE/PLUS Peripherals • COP8 Development Support

CROSSVOLTTM LOW VOLTAGE LOGIC SERIES DATABOOK-1994
LCX Family • LVX Translator Family • Lyx Bus Switch Family • LVX Family • LVQ Family • LVT Family

DATA ACQUISITION DATABOOK-1993
Data Acquisition Systems • Analog·to·Digital Converters • Digital·to·Analog Converters • Voltage References
Temperature Sensors. Active Filters. Analog Switches/Multiplexers. Surface Mount

DATA ACQUISITION DATABOOK SUPPLEMENT-1992
New devices released since the printing of the 1989 Data Acquisition Linear Devices Databook.

DISCRETE SEMICONDUCTOR PRODUCTS DATABOOK-1989
Selection Guide and Cross Reference Guides • Diodes • Bipolar NPN Transistors
Bipolar PNP Transistors. JFET Transistors • Surface Mount Products. Pro· Electron Series
Consumer Series • Power Components. Transistor Datasheets • Process Characteristics

DRAM MANAGEMENT HANDBOOK-1993
Dynamic Memory Control • CPU Specific System Solutions. Error Detection and Correction
Microprocessor Applications

EMBEDDED CONTROllERS DATABOOK-1992
COP400 Family • COP800 Family • COPS Applications • HPC Family • HPC Applications
MICROWIRE and MICROWIRE/PLUS Peripherals. Microcontroller Development Tools

FDDI DATABOOK-1991 .
FOOl Overview • DP83200 FOOl Chip Set • Development Support • Application Notes and System Briefs

F100K ECl lOGIC DATABOOK & DESIGN GUIDE-1992
Family Overview • 300 Series (Low-Power) Datasheets • 100 Series Datasheets • 11 C Datasheets
Design Guide • Circuit Basics • Logic Design • Transmission Line Concepts • System Considerations
Power Distribution and Thermal Considerations. Testing Techniques. 300 Series Package Qualification
Quality Assurance and Reliability. Application Notes

FACTTM ADVANCED CMOS lOGIC DATABOOK-1993
Description and Family Characteristics • Ratings, Specifications and Waveforms
Design Considerations • 54AC17 4ACXXX • 54ACT174ACTXXX • Quiet Series: 54ACQ17 4ACQXXX
Quiet Series: 54ACTQ174ACTQXXX. 54FCT174FCTXXX. FCTA: 54FCTXXXA174FCTXXXAlB

FAST® ADVANCED SCHOTTKY TTL lOGIC DATABOOK-1990
Circuit Characteristics. Ratings, Specifications and Waveforms. DeSign Considerations. 54F174FXXX

FAST® APPLICATIONS HANDBOOK-1990
Reprint of 1987 Fairchild FAST Applications Handbook
Contains application information on the FAST family: Introduction. Multiplexers. Decoders. Encoders
Operators. FIFOs. Counters. TIL Small Scale Integration. Line Driving and System Design
FAST Characteristics and Testing. Packaging Characteristics

HIGH-PERFORMANCE BUS INTERFACE DATABOOK-1994
QuickRing • Futurebus + /BTL Devices • BTL Transceiver Application Notes • Futurebus + Application Notes
High Performance TIL Bus Drivers. PI-Bus. Futurebus+ /BTL Reference

IBM DATA COMMUNICATIONS HANDBOOK-1992
IBM Data Communications • Application Notes

INTERFACE: DATA TRANSMISSION DATABOOK-1994
TIAIEIA-232 (RS-232) • TIAIEIA-422/423 • TIAIEIA-485 • Line Drivers. Receivers • Repeaters
Transceivers. Low Voltage Differential Signaling. Special Interface. Application Notes

LINEAR APPLICATIONS HANDBOOK-1994
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to 'explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.

LINEAR APPLICATION SPECIFIC IC's DATABOOK-1993
Audio Circuits • Radio Circuits • Video Circuits • Display Drivers • Clock Drivers • Frequency Synthesis
Special Automotive • Special Functions • Surface Mount

LOCAL AREA NETWORKS DATABOOK-1993 SECOND EDITION
Integrated Ethernet Network Interface Controller Products • Ethernet Physical Layer Transceivers
Ethernet Repeater Interface, Controller Products. Token-Ring Interface Controller (TROPIC)
Hardware and Software Support Products • FOOl Products. Glossary and Acronyms

LOW VOLTAGE DATABOOK-1992
This databook contains information on National's expanding portfolio of low and extended voltage products. Product datasheets
included for: Low Voltage Logic (LVQ), Linear, EPROM, EEPROM, SRAM, Interface, ASIC, Embedded Controllers, Real Time
Clocks, and Clock Generation and Support (CGS).

MASS STORAGE HANDBOOK-1989
Rigid Disk Pulse Detectors • Rigid Disk Data Separators/Synchronizers and ENDECs
Rigid Disk Data Controller. SCSI Bus Interface Circuits. Floppy Disk Controllers • Disk Drive Interface Circuits
Rigid Disk Preamplifiers and Servo Control Circuits • Rigid Disk Microcontroller Circuits • Disk Interface Design Guide

MEMORY DATABOOK-1994
FLASH • CMOS EPROMs • CMOS EEPROMs • PROMs • Application Notes

MEMORY APPLICATIONS HANDBOOK-1994
FLASH • EEPROMs • EPROMs • Application Notes

OPERATIONAL AMPLIFIERS DATABOOK-1993
Operational Amplifiers • Buffers. Voltage Comparators. Instrumentation Amplifiers • Surface Mount

PACKAGING DATABOOK-1993
Introduction to Packaging • Hermetic Packages • Plastic Packages. Advanced Packaging Technology
Package Reliability Considerations • Packing Considerations • Surface Mount Considerations

POWER IC's DATABOOK-1993
Linear Voltage Regulators • Low Dropout Voltage Regulators • Switching Voltage Regulators. Motion Control
Peripheral Drivers • High Current Switches • Surface Mount

PROGRAMMABLE LOGIC DEVICE DATABOOK AND
DESIGN GUIDE-1993
Product Line Overview • Datasheets • Design Guide: Designing with PLDs • PLD DeSign Methodology
PLD Design Development Tools • Fabrication of Programmable Logic • Application Examples

REAL TIME CLOCK HANDBOOK-1993
3-Volt Low Volta(:le Real Time Clocks • Real Time Clocks and Timer Clock Peripherals • Application Notes

RELIABILITY HANDBOOK-1987
Reliability and the Die. Internal Construction· Finished Package. MIL-STD-883. MIL-M-38510
The Specification Development Process. Reliability and the Hybrid Device. VLSIIVHSIC Devices
Radiation Environment • Electrostatic Discharge • Discrete Device • Standardization
Quality Assurance and Reliability Engineering • Reliability and Documentation. Commercial Grade Device
European Reliability Programs • Reliability and the Cost of Semiconductor Ownership
Reliability Testing at National Semiconductor. The Total Military/Aerospace Standardization Program
883B/RETSTM Products. MILS/RETSTM Products. 883/RETSTM Hybrids • MIL-M-3851 0 Class B Products
Radiation Hardened Technology • Wafer Fabrication • Semiconductor Assembly and Packaging
Semiconductor Packages. Glossary of Terms. Key Government Agencies. AN/ Numbers and Acronyms
Bibliography. MIL-M-38510 and DESC Drawing Cross Listing

SCANTM DATABOOK-1994
Evolution of IEEE 1149.1 Standard. SCAN BiCMOS Products. SCAN ACMOS Products. System Test Products
Other IEEE 1149.1 Devices

TELECOMMUNICATIONS-1994
COMBO and SLiC Devices • ISDN. Digital Loop Devices. Analog Telephone Components • Software
Application Notes

VHC/VHCT ADVANCED CMOS LOGIC DATABOOK-1993
This databook introduces National's Very High Speed CMOS (VHC) and Very High Speed TTL Compatible CMOS (VHCT)
designs. The databook includes Description and Family Characteristics • Ratings, Specifications and Waveforms
Design Considerations and Product Datasheets. The topics discussed are the advantages of VHCIVHCT AC Performance,
Low Noise Characteristics and Improved Interface Capabilities.

NOTES

NATIONAL SEMICONDUCTOR CORPORATION DISTRIBUTORS
ALABAMA
Huntsville
Anthem Electronics
(205) 890-0302
Hamilton/Hallmark
(205) 837-8700
Pioneer Technology
(205) 837-9300
Time Electronics
(800) 258-8513
ARIZONA
Phoenix
Hamilton/ Hallmark
(602) 437-1200
Scottsdale
Alliance Electronics Inc.
(602) 483-9400
Tempe
Anthem Electronics
(602) 966-6600
Bell Industries
(602) 966-7800
Time Electronics
(602) 967-2000
CALIFORNIA
Agora Hills
Bell Industries
(818) 706-2608
Pioneer Standard
(818) 865-5800
Time Electronics
(818) 707-2890
Calabasas
F/X Electronics
(818) 591-9220
Chatsworth
Anthem Electronics
(818) 775-1333
Costa Mesa
HamiltonlHalimark
(714) 641-4100
Irvine
Anthem Electronics
(714) 768-4444
Bell Industries
(714) 727-4500
Pioneer Standard
(714) 753-5090
Zeus Eltlct. an Arruw Cu.
(714) 581-4622
Los Angeles
Bell Industries
(310) 447-6321
Rocklin
Anthem Electronics
(916) 624-9744
Bell Industries
(916) 652-0414
Roseville
Hamilton/Hallmark
(916) 624-9781
San Diego
Anthem Electronics
(619) 453-9005
Hamilton/Hallmark
(619) 571-7540
Pioneer Standard
(619) 546-4906
Time Electronics
(619) 674-2800
San Jose
Anthem Electronics
(408) 453-1200
HamiltonlHalimark
(408) 743-3300
Pioneer Technology
(408) 954-9100
Zeus Elect. an Arrow Co.
(408) 629-4789

Sunnyvale
Bell Industries
(408) 734-8570
Time Electronics
(408) 734-9888
Tustin
Time Electronics
(714) 669-0100
Woodland Hills
Hamilton/Hallmark
(818) 594-0404
Time Electronics
(818) 593-8400
COLORADO
Denver
Bell Industries
(303) 691-9010
Englewood
Anthem Electronics
(303) 790-4500
Hamilton/Hallmark
(303) 790-1662
Time Electronics
(303) 721-8882
CONNECTICUT
Cheshire
Hamilton/Hallmark
(203) 271-2844
Shelton
Pioneer Standard
(203) 929-5600
Waterbury
Anthem Electronics
(203) 575-1575
FLORIDA
Altamonte Springs
Anthem Electronics
(407) 831-0007
Bell Industries
(407) 339-0078
Pioneer Technology
(407) 834-9090
Deerfield Beach
Pioneer Technology
(305) 428-8877
Fort Lauderdale
Hamilton/Hallmark
(305) 484-5482
Time Electronics
(305) 484-1778
Lake Mary
Zeus Elect. an Arrow Co.
(407) 333-9300
Largo
Hamilton/Hallmark
(813) 541-7440
Orlando
Chip Supply
Die Distributor
(407) 298-7100
Time Electronics
(407) 841-6565
Winter Park
Hamilton/Hallmark
(407) 657-3300
GEORGIA
Duluth
Hamilton/Hallmark
(404) 623-4400
Pioneer Technology
(404) 623-1003
Norcross
Bell Industries
(404) 662-0923
Time Electronics
(404) 368-0969

ILLINOIS
Addison
Pioneer Electronics
(708) 495-9680
Bensenville
Hamilton/Hallmark
(708) 860-7780
Elk Grove Village
Bell Industries
(708) 640-1910
Schaumburg
Anthem Electronics
(708) 884-0200
Time Electronics
(708) 303-3000
INDIANA
Fort Wayne
Bell Industries
(219) 423-3422
Indianapolis
Advent Electronics Inc.
(317) 872-4910
Bell Industries
(317) 875-8200
Hamilton/Hallmark
(317) 872-8875
Pioneer Standard
(317) 573-0880
IOWA
Cedar Rapids
Advent Electronics
(319) 363-0221
KANSAS
Lenexa
Hamilton/Hallmark
(913) 332-4375
KENTUCKY
Lexington
Hamilton/Hallmark
(602) 288-4911
MARYLAND
Columbia
Anthem Electronics
(410) 995-6840
Bell Industries
(410) 290-5100
Hamilton/Hallmark
(11C) ~ee·~e~a
Time Electronics
(410) 720-3600
Gaithersburg
Pioneer Technology
(301) 921-0660
MASSACHUSETTS
Andover
Bell Industries
(508) 474-8880
Beverly
Sertech Laboratories
(508) 927-5820
Lexington
Pioneer Standard
(617) 861-9200
Newburyport
Rochester Electronics
"Obsolete Products"
(508) 462-9332
Norwood
Gerber Electronics
(617) 769-6000
Peabody
Hamilton/Hallmark
(508) 532-3701
Time Electronics
(508) 532-9900

Tyngsboro
Port Electronics
(508) 649-4880
Wilmington
Anthem Electronics
(508) 657-5170
Zeus Elect. an Arrow Co.
(508) 658·0900
MICHIGAN
Grand Rapids
Pioneer Standard
(616) 698·1800
Novi
Hamilton/Hallmark
(313) 347-4271
Plymouth
Pioneer Standard
(313) 416-2157
Wyoming
R. M. Electronics, Inc.
(616) 531-9300
MINNESOTA
Bloomington
Hamilton/Hallmark
(612) 881-2600
Eden Prairie
Anthem Electronics
(612) 944-5454
Pioneer Standard
(612) 944-3355
Edina
Time Electronics
(612) 943-2433
Thief River Falls
Digi-Key Corp.
"Catalog Sales Only"
(800) 344-4539
MISSOURI
Earth City
Hamilton/Hallmark
(314) 291-5350
Manchester
Time Electronics
(314) 391-6444
NEW JERSEY
Cherry Hill
Hamilton/Hallmark
(609) 424-0110
Fairfield
Bell Industries
(201) 227-6060
Hamilton/Hallmark
(201) 575-3390
Pioneer Standard
(201) 575-3510
Marlton
Time Electronics
(609) 596-6700
Mount Laurel
Seymour Electronics
(609) 235-7474
Parsippany
Hamilton/Hallmark
(201) 515-1641
Pine Brook
Anthem Electronics
(201) 227-7960
Wayne
Time Electronics
(201) 785-8250
NEW MEXICO
Albuquerque
Bell Industries
(505) 292-2700
Hamilton/Hallmark
(505) 828-1058

NATIONAL SEMICONDUCTOR CORPORATION DISTRIBUTORS (Continued)
NEW YORK
Binghamton
Pioneer
(607) 722·9300

Buffalo
Summit Electronics
(716) 887-2800

Commack
Anthem Electronics
(516) 864-6600

Fairport
Pioneer Standard
(716) 381-7070

Hauppauge
Hamilton/Hallmark
(516) 434-7490

Time Electronics
(516) 273-0100

Port Chester
Zeus Elect. an Arrow Co.
(914) 937-7400

Rochester
Hamilton/Hallmark
(800) 475-9130

Summit Electronics
(716) 334-8110

Ronkonkoma
Hamilton/Hallmark
(516) 737-0600

Syracuse
Time Electronics
(315) 432-0355

Westbury
Hamilton/Hallmark Export Div.
(516) 997-6868

Woodbury
Pioneer Electronics
(516) 921-8700

Seymour Electronics
(516) 496-7474

NORTH CAROLINA

Morrisville
Pioneer Technology
(919) 460-1530

Raleigh
Hamilton/Hallmark
(919) 872-0712

OHIO

Cleveland
Pioneer
(216) 587-3600

Columbus
Time Electronics
(614) 794-3301

Dayton
Bell Industries
(513) 435-8660

Bell Industries·Military
(513) 434-8231

Hamilton/Hallmark
(513) 439-6735

Pioneer Standard
(513) 236-9900

OKLAHOMA

Tulsa
Hamilton/Hallmark

Houston
Hamilton/Hallmark
(713)781-6100

Calgary
Electro Sonic Inc.
(403) 255-9550

(918) 254-6110

Pioneer Standard

Semad Electronics

Pioneer Standard

(713) 495-4700

(403) 252-5664

(918) 665-7840

Radio Inc.
(918) 587-9123

OREGON

Beaverton
Anthem Electronics
(503) 643-1114

Bell Industries
(503) 644-3444

Hamilton/Hallmark
(503) 526-6200

Richardson
Anthem Electronics
(214) 238-7100

Time Electronics
(214) 644-4644

UTAH

Midvale
Bell Industries
(801) 255-9611

Salt Lake City
Anthem Electronics

Pioneer Technology

(801) 973-8555

(503) 626-7300

Hamilton/Hallmark

Portland
Time Electronics
(503) 684-3780

PENNSYLVANIA

Horsham
Anthem Electronics
(215) 443-5150

Pioneer Technology
(215) 674-4000

Mars
Hamilton/Hallmark
(412) 281-4150

Pittsburgh
Pioneer Standard
(412) 782-2300

Trevose
Bell Industries
(215) 953·2800

TEXAS

Austin
Hamilton/Hallmark
(512) 258-8848

Minco Technology Labs.
(512) 834·2022

Pioneer Standard
(512) 835-4000

Time Electronics
(512) 346·7346

Carrollton
Zeus Elect. an Arrow Co.
(214) 380-6464

Dallas
Hamilton/Hallmark
(214) 553-4300

Pioneer Standard
(214) 386-7300

(801) 266-2022

West Valley
Time Electronics
(801) 973-8494

WASHINGTON

Bellevue
Pioneer Technology
(206) 644-7500

Bothell
Anthem Electronics
(206) 483-1700

Kirkland
TIme Electronics
(206) 820-1525

Redmond
Bell Industries
(206) 867-5410

Hamilton/Hallmark
(206) 881-6697

WISCONSIN

Brookfield
Pioneer Electronics
(414) 784-3480

Mequon
Taylor Electric
(414) 241-4321

New Berlin
Hamilton/Hallmark
(414) 780-7200

Waukesha
Bell Industries
(414) 547-8879

Hamilton/Hallmark
(414) 784-8205

CANADA

WESTERN PROVINCES
Burnaby
Hamilton/Hallmark
(604) 420-4101

Semad Electronics
(604) 451-3444

Zentronics
(403) 295-8838

Edmonton
Zentronics
(403) 482-3038

Markham
Semad Electronics Ltd.
(416) 475-6500

Richmond
Electro Sonic Inc.
(604) 273-2911

Zentronics
(604) 273-5575

Winnipeg
Zentronics
(204) 694-1957

EASTERN PROVINCES
Mississauga
Hamilton/Hallmark
(416) 564·6060

Time Electronics
(416) 672-5300

Zentronics
(416) 507-2600

Nepean
Hamilton/Hallmark
(613) 226-1700

Zentronics
(613) 226-8840

Ottawa
Electro Sonic Inc.
(613) 728-8333

Semad Electronics
(613) 526-4866

Pointe Claire
Semad Electronics
(514) 694-0860

Ville St. Laurent
Hamilton/Hallmark
(514) 335-1000

Zentronics
(514) 737-9700

Willowdale
ElectroSonic Inc.
(416) 494-1666

Winnipeg
Electro Sonic Inc.
(204) 783-3105

fjlNationa l Semiconductor

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1994 National Semiconductor

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