1994_National_Linear_Applications_Handbook 1994 National Linear Applications Handbook
User Manual: 1994_National_Linear_Applications_Handbook
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LINEAR APPLICATIONS
HANDBOOK
The purpose of this handbook is to provide a fully indexed
and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from
National Semiconductor.
Individual application notes are normally written to explain
the operation and use of one particular device or to detail
various methods of accomplishing a given function. The organization of this handbook takes advantage of this innate
coherence by keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.
Many of the application schematics call out the generic family, identified by either the military temperature range version
or commercial temperature range version of the device.
Generally, any device in the generic family will work in the
circuit. For example, an amplifier indicated as an LM108
refers to the generic "108" family, and does not imply that
only military-grade devices will work in the application. Military (or industrial) and prime electrical ("A") grade devices
need only be considered when their tighter electrical limits
or wider temperature range warrants their use.
"'"
The temperature range of linear devices is indicated by either the first digit in the part number, or a letter following the
base part number.
Specified Temperature
Range
Military
- 55"C s: TA s: + 125"C
Extended·
-40"C s: TA s: +125"C
Industrial·
- 25"C s: TA s: + 85"C
Commercial O"C s: TA s: + 70"C
Grade
Part Number
LM1 XX or LMXXXM
LMXXXE
LM2XX or LMXXXI
LM3XX or LMXXXC
'Some industrial temperature range devices may be rated
for the extendBiJ (also known as automotive) temperature
range. Other extended temperature range devices may not
include a temperature range designation in their part number. Check the device datasheet for the specified temperature range(s).
Because commercial parts are less expensive than military
or industrial, these points should be kept in mind when trying to determine the most cost-effective approach to a,given
design.
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NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
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National does not assume any responsibility for use of any circuitry described, no circuM patent IlCi1n.... are implied, and National reserves the right, at any time
to change said circuitry or epacificatlona.
without notice,
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Linear Applications Numerical List
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Application Notes
AN-3
AN-4
AN-13
AN-20
AN-23
AN-24
AN-29
AN-30
AN-31
AN-32
AN-41
AN-42
AN-46
AN-48
AN-49
AN-56
AN-69
AN-71
AN-72
AN-74
AN-79
AN-82
AN-87
AN-88
AN-97
AN-103
AN-104
AN-110
AN-116
AN-127
AN-146
AN-154
AN-156
AN-161
AN-162
AN-173
AN-178
AN-181
AN-182
AN-184
AN-193
AN-200
AN-202
AN-210
AN-211
AN-222
Drift Compensation Techniques for Integrated DC Amplifiers ........................ .
Monolithic Op-Amp-The 'Universal Linear Component ........•.....................
Application of the LH0002 Current Amplifier. ........................•............•.
An Application Guide for Op Amps ............................................... .
The LM105c-An Improved Positive Regulator .........................•............
A Simplified Test Setfor Op Amp Characterization ................................. .
IC Op Amp Beats FETs on Input Current .......................................... .
Log Converters ........................................•......•......•.........
Op Amp Circuit Collection ...................................................... .
FET Circuit Applications .................................•.......................
Precision IC Comparator Runs from + 5V Logic Supply ............................. .
IC Provides On-Card Regulation for Logic Circuits ................•.................
The Phase Locked Loop IC as a Communications System Building Block ............. .
Applications for a New Ultra-High Speed Buffer .................•.•.................
Pin Diode Drivers ..............................••.......................•.......
1.2V Reference ........................................••......................
LM380 Power Audio Amplifier ...................•...........•....................
Micropower Circuits Using the LM4250 Programmable Op Amp •......•...............
The LM3900-A New Current-Differencing Quad + Input Amplifiers •........•........
LM139/LM239/LM339-A Quad of Independently Functioning Comparators ..•........
IC Pre-Amp Challenges Choppers on Drift ..••..••.•..•............•...............
LM125/LM126 Precision Dual-Tracking Regulators ............•......•.............
Comparing the High Speed Comparators ...•...........•..••.•....•.••...••......•
CMOS Linear Applications ..... '................................••.....•..........
Versatile Timer Operates from Microseconds to Hours •............•.............•..
LM340 Series Three Terminal Positive Regulators .•.•..•..................•........
Noise Specs Confusing? ....................................................... .
Fast IC Power Transistor with Thermal Protection ..••..•..•..••••.....••••.••.......
Use the LM158/258/358 Dual, Single Supply Op Amp .........•..•....•.•••...••...
LM143 Monolithic High Voltage Operation Amplifier Applications ...•. , " •...•......•.
FM Remote Speaker System ................................................... .
1.3V IC Flasher, OSCillator, Trigger or Alarm ...•......••.................•..........
Specifying, AID and D/A Converters ........•...•••......••...•••....•••.•.......•
IC Voltage Reference Has 1 ppm per Degree Drift .............•....................
LM2907 TachometerlSpeed Switch Building Block Applications ••••.•...•... , .•......
IC Zener Eases Reference Design ...••.•.•.•••.....•........•....................
Applications for an Adjustable IC Power Regulator •..........•••....•••...•....... '.'
3-Terminal Regulator is Adjustable ........................•....•.•.....•• , ...••...
Improving Power Supply Reliability with IC Power Regulators ..•.•.•............. ',' ...
References for AID Converters .............................•.•.•.....••......•..
Single Chip Data Acquisition System Simplifies Analog to Digital Conversion .........•.
CMOS AID Converter Chips Easily Interface to 8080A Microprocessor System ~ .•.•...•
A Digital Multimeter Using ADD3501 ........................••..•.....•••.....•...
New Phase-Locked Loops Have Advantage as Frequency to Voltage Converters
(and more) ...............................•..........•....•.•.....••....•••..
New Op Amps Ideas .•......••........•...•.•••...••••...•.......•••...•........
Super Matched Bipolar Transistor Pair Sets New Standard for Drift and Noise •...•••...
iii
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Linear Applications Numerical List (Continued)
Application Notes
Date
AN-225
AN-227
AN-233
AN-236
AN-237
AN-240,
AN-241.
AN-242.
AN-245 ,
AN-247
IC Temperature Sensor Provides Thermocouple Cold.Junction Compensation ........••
Applications of Wideband Buffers .••.........•..•••...•..••...••..•••...••..•••...
The AID Easily Allows Many\.lrll!suat.Appli:",,; :::.
>...... ,';'..... '...........................................
viii
Device!Application Literature Cross-Reference (Continued)
Devtce Number
Application Uteratur.
LM12 •.••••.•.•.•••.•.••••.•.•.•.•..•.•......•.•••.••••...•••..•..•••.••.•.•.•.•.••.•.•.•. AN-446. AN-693. AN-70s
LM101 .......•..••....•.•......•........•.•.•••••.••••••••.•.•...•..•• AN-4. AN-13. AN-20. AN-24. LB-42. Appendix A
LM101A ....•.•.•........• AN-29. AN-30. AN-31. AN-79. AN-241 AN-711. LB-1. LB-2. LB-4. LB-8. LB-14. LB-16. LB-19. LB-28
LM102 .................................................................. AN-4. AN-13. AN-30. LB-1. LB-5. LB-6. LB-11
LM103 .•...•.••........•.•..•.•••...•..•...•...•...•....•...........••....•...•.•.•.•••..•..•...... AN-11O. LB-41
LM105 ............•....•...•..• , •.•.•.•••••••........••.•.•••••.. , .•••.......•.. , ••......•..•. AN-23. AN-110. LB-3
LM106 •....•.•...••..•..•......•...•.....•......•.•.••...•.•............•.•.................•.. AN-41. LB-6. LB-12
LM107 .................................................................AN-20.AN-31. LB-1. LB-12. LB-19. Appendix A
LM108 ••••••••.•.•.•.••••.•.•..•.•.•.•...•......•... AN-29.AN-30. AN-31. AN-79. AN-211. AN-241. LB-14. LB-15. LB-21
LM108A •• ; ...................................................................................AN-260. LB-15. LB-19
LM109 .........•..•...•.•.•...••.•.•.•.•.....••.••••.•.•...•.•.•.........••..•...•..••••..•.....•... AN-42.LB-15
LM109A .•••••••.•..•.••••.•.•.•...••••••.•.••••.•.•.•..••....•.•.....•.•...................•..•...•••...•.• LB-15
LM110 .•••.••.•••••..•.•.••••.•••.•.•.•..•••••.•.•.•.••••••.•••.••.••••..•....•..••....•.•.•..••.•... LB-11. LB-42
LM111 •.•.••••••••.••••••••••••.•••.......•.•.............••..•.•.•..•.... AN-41. AN-103. LB-12. LB-16. LB-32. LB-39
LM112 .....................................................................................................LB-19
LM113 .•••••.•.••.•.•.•.•.....••.....•....•••...•......•.•.•.........•.... AN-56. AN-11 O. LB-21. LB-24. LB-28. LB-37
LM117 ••.•..•••.•.•••.•.••.••••••••••••.•••....•.•..•.•.•.•.•.••.•.•.....••.. AN-178.AN-181. AN·182. LB-46. LB-47
LM117HV .........•..•.••.••...•....•...•......•...•..•......•..•.•..•...•.•......................... LB-46.LB-47
LM118 ••.•...•.•.•.••.•.•........•.••.•.•.....•.•...•....••.•.......•.......• LB-17. LB-19. LB-21. LB-23. Appendix A
LM119 •••.••••••••.•••..•••.•••••.••••••••••..•...•••.•••.•.••••.•.•.•...••.•.•.•.•..••••....•.••..•......• LB-23
LM120 •.•.•.•.•.••••••.•.•.••••.•..••.•••••.•.••••.•.••••.•.•.•.•.••.•.•.•••...•..•.••..•.•.••.•.....•.... AN-182
LM121 .......................................................................AN-79. AN-104. AN-184. AN-260. LB-22
LM121A ••..••.•.•.••.••••••••••.•.•••••••....•.••••••.•.•.•.•••.•..•.•.•••.•....•••.••••..•...•.•.••.•.•.•. LB-32
LM122 ........•......•..•....•...•.•••.......••...•..•.•...•..............•...•........•............AN-g.7. LB-38
LM125 .••...•..•.•...••.•..•.••••••.....•.•..•.••..•.•.••••.•.....•.•..•......•.......................•.••. AN-82
LM126 ••.•.•...•.•..•••.•.•..•...•...•......•.•...••.....•..........•••.••.••.•..•.•.•........•. , .•.•.•.••• AN-82
LM129 .•.•.••.....•.•.••.•.•.•.•.•••..•.••••••••••••••.•.•••••..•.•••...••.......• AN-173. AN-178. AN-262. AN-266
LM131 ...•.•..........•..••..•...•..•.••.••.•.•........•.•...•....•.••.••.•..•.•.•.•...AN-210. AN-460. Appendix D
LM131A ••••••••••••.•.••••••••.•.••••••••••.••..•.••••••••.•.•.•.•..•.•.•...•.•....•.•.•.•••..•...•.....• AN-210
LM134 •............•......•...••.•.•.•••..•...•...•.•..•..•••.•.....•.....•..••.•..•.•.•....•...... LB-41.AN-460
LM135 ....................................................................AN-225. AN-262. AN-292. AN-298. AN-460
LM137 ...•.•.•.•...•.••.•...•.•..•.•..•..•......••..........•••..•.••...•.•..••.•.•.••••.••••••••..••.•.•.• LB-46
LM137HV ••••.•••.•••••••••••••••••••••••.•.••••••••••.•.••••...•••.•••.•.••.....•....•.•..............•..• LB-46
LM138 •.....•..•...••.•....•...••..•.•..•.•••••.•...•.••...•.•.•.•..••.••••.•••••....•.•.•.•.•..•.•...•.•.• LB-46
LM139 ••••.•••.•..•••.•.•'.•......•••.•••.•.••.•.•••.•...••.•••.•.•.•••.•.•.••••.••••..•..•.......•••.•••..• AN-74
LM143 .•••.•.•••••.••••.•.•••.•••••••••••••••••••••.••.•••.••.•••••.••.•.•.•••••.•.•....•.•...••.. AN-127.AN-271
LM148 •..•..••..•..•.•.•.•..•••. '......•.•.•••..•...•••..•...•....•..•••.•....•.....•....••••..•..•.......•AN-260
LM150 '" .••••.•.•...••••.•.•••.••.•••••••.•.•..•••••.•.•.•••••.••.•••••••••••••••••••••••••••.•••.•.•.•••. LB-46
LM156 •.•• ; •.•.•••••..•••.•.•••.••••••••••••••.••••••.••••••••••••••••.•••.••..••...•.....•••......•...•.. AN-116
LM160 ......•.•.•.•••.••.•.•.•.•••....•.••• , •••••.•...••.•.•...•••..•.••..•.•.•.••.•.•.•.•.•..•••••.•.•...• AN-87
LM161 .••...•...•.••••.••.••.•.•.•••.•.•..•••••••.••.....•.•.•..•..........•.••••••••••••.•.•••.... AN-87. AN-266
LM163 .•.•.....•.••.•.•.•.•.••••••.•••.•.••.•••••••••.••••.••••••••••••••••••••••••••••••••••......•.•.•.. AN-295
LM194 •••••••.•••••..••••••••••••••••••.••••.•••••.•.•.....••••.......•..•••..•........•.•.•.....•• AN-222. LB-21
LM195 •....•..•.•.••••...•..••• , ..•••••••.•••••.•...•.••.•••••.•.•••••.••••.•.••.•.•.•••.•••••.•.••••••••• AN-110
LM199 ............................................................................................AN-161.AN-260
LM199A •••••••••••••••••.••••••••••••••••••••••.•••••..•.•••.•.•..••....••.••.......•..•.....•...•..•...• AN-161
LM211 ••••••••••••••••••••.••••••••.•••.•••••••••••••••••••••.•.•.•.••..•.•.•••....•.•.•..•....••.••..•.•.• LB-39
LM231 •.• , •.••••••.•.•.•.•.•.•.•. " .•.•.•••.•.••••••...•••.•.•.•.••••••••.•.•.••••.•.•.•.•.••••••••••••••• AN-210
LM231A ........•.•...••...•.•.•.•.•••••.••••••••••••.••••••••••••••••.••••••••.•••••.•.••••••••.•.•.•.•.• AN-210
LM235 ••••••••••••••••••• '••••••••••..••••••••••••••••••.•.•.•.••••••.•••.•.••••••.••..•.•...•.•....•.....• AN-225
LM239 •.•.••••••••••••••.••••••.•.•••.•••••..•.•..•••••.•....••....••.•••••..•.•.•.•••.•.•.•.••••..••••.••• AN-74
ix
DevlcelApplication Literature Cross-Reference (Continued)
Device Number
Application Uterature
LM258 .....................................................................................................AN-1 1.6
LM260 ...•....••••.....•...•........•••.•••.•.•••.•••••.••...•....•.••.•.••••.••••••.•..•.••.••.....•.......••. AN-87
LM261 •.•..•.••.•.•..•.•.•••..••....•....••...•..•••..•••.••.••••••...••...•..•.•.••.•.•.••.•.••••.•.••.•.• AN-87
LM34 •••...•.••. " •••....•••....•..• '..•...•...•...••••••.•.•.•..••....••...•...••....•.•..•.•.•....•..••.•. AN-460
LM35 ...•.........•••.•.•.•.••••.•.••••...••••••••••••••.••••••••.••••••••••••••••.••••••.••••.•..•.•..•.• AN-460.
LM301A ......................................................................................AN-178, AN-181, AN·222
LM308 .•..•••••.•.•.••••.•.•••....•....•••....•..•...••.•••.•.•.••• AN-88, AN-184, AN-272, LB-22, LB-28, Appendix D
LM308A .............................................................................................AN-225, LB-24
LM309 ............................................... , •.• : ........................................... AN-178, AN-182
LM311 .......•....•.......• AN-41 , AN-1 03, AN-260, AN-263, AN-288, AN-294, AN-295, AN-307, .LB"12, LB-16, LB-18, LB-39
LM313 ..•...•.••.•.••...•.••••••••.•••..•••.••••.••••.•.••.••••••.•.•.••.••...•.••••••.••••.•.•..•.••••..• AN-263
LM316 ....................................................................................................AN-258
LM317 .•.••••.•••••.•.•..•.•..•.•..•.•••......•.•.•..••...•.••••••.•.•.••••..••.•.•..•...•..• AN-178, LB-35, LB-46
LM317H ...•.•....•.•.•..•.••••••••.••.•.••••••••.••••••••••••••.•.•••••••••••.•.••.••••.•••••..•.••.•.•..•. LB-47
LM318 ...........•.•....•••.•..•••.••••••••.•••••••••••.••••.•..•••••.••••••••••••••.•.•..•••••.••. AN-299, LB·21
LM319 .....•. '..• ,,' .•.' ......................................................................AN-828, AN-271, AN-293
LM320 .........•.•.••.•.•.•..•••.••••••.••••••.•.••••.••••••.••••••••••••••••••••••••••.•••••••••••.•••••• AN-288
LM321 ...... ,. .............••••.•.....•..........•..•.. '.' ..••••.•.•..•....•.•....•.•.•.••.•.•..•.....•...•.•. LB-24
LM324 ............................................. AN-88, AN-258, AN-274, AN-284, AN-301, LB-44, AB-25, Appendix C
LM329 •......•..•.•••.•..•••.••.•.••••••••..•.•.••.•••.•.••••...••.•....•• AN-256, AN-283, AN-284, AN-295, AN-301
LM329B ................•..•....•...•.••.•.•.••••••••..••••••••••••••••.•••••••••••••.•••••.••.•••••••.•.. AN-225
LM330 •..•...••..••.•••••••.•...••.•....•.•.•...•..•......•••••••••.•.•.•.......•.•••..........•.....•.•.. AN-301
LM331 .....••..•...••.•••.••.•.•.••••• AN-210, AN-240, AN-265, AN-278, AN-285, AN-311, LB-45, Appendix C, Appendix D
LM331A ..••......•.........•.•........•..•.•.•..•.•..•.•...••.•.•..•.•.••.•.•..•.•.•....•...••AN-210, Appendix C
LM334 ••••••.••..•...••.•.•.•••••••••••••.•.•••..••••••••••••••••••...•......•.......•.•.. AN-242, AN-256, AN-284
LM335 .•....•.•.••••.••••••.••.• '.' ••.•.•••••••••.•••.•••••••••.•.••.••••••.•.••.•.•.••.•.• AN-225, AN-263, AN-295
LM336 ....................................................................................AN-202, AN-247, AN-258
LM337....•.••.••••••.•••...•..•.•.••.•.•.••.••••.•.••••.•••.••.•.••.•.•.•..•.•.•.••••..•.•..•...•.•....••.. LB-46
LM338 ..•......•.•....•.••••.•.•.••••.•••••••.•.•.•.••••.••••••.•••••••••••.••••.•.••.•.••••••.•••••• LB-49, LB-51
LM339 ......................................................................................AN-74, AN-245, AN-274
LM340 .••.....•.......... : .........................................................................AN-1 03, AN-182
LM340L. ...•..•.•••••••••••••.•.•..••••.•.•.••.•••.••.•.•..•.•.•.•...' .••.•.•..•...•.••••.•.••.••.•.•.••.•. AN-256
LM342 ............................................................................, ....................... '. AN-288
-LM346 •.••••...•••...•••...•.•..•.•.••.•.•...••••.•....•.•..•.••...•..•.•.•......•.•.••.••.•.•....• AN-202, LB-54
LM348 ..............................................................................................AN-202, LB-42
LM349 ........•...................•..•...••.•.••••.•.••••.•.••.•..••.•••••..••••.•.•.••••••.••.••••.•.•.••. ; LB-42
LM358 ........•.•....•.........•....•••..••••••••••.•.• AN-116, AN-247, AN-271, AN-274, AN-284, AN-298, Appendix C
LM358A ..•.•.•.•......•..•...•.•.•.....••.•.•....•.••.•.....•.•.••..•.•.•..•.•.•.•...•••..•.•..•..•.•.Appendix D
LM359 •..•.•.•..•.•..•••.•.•..•.•....•.•.••••••..•••••.••.•.••.•.••...•.•.• : •••......•.•..•.•..•.•.. AN-278,AB-24
LM360 .........•....•.•.•..•...•..•.•.•.•••.•.•••.•..•.•.••••••.•••••.•.•.••••.•.••.•.•.•.••.••••••••.••••. AN-87
LM361 ...............................................................................................AN-87,AN-294
LM363 .....................................................................................................AN-271
LM380 ...............................................................................................AN-69, AN-146
LM382 •.. , ., •.•. , •.••.. , .••.•...••.•.•••••••••.•.••••.••••••.•.••.•.•.••••.••.••••••.•.••••.•.••.•.•••..•. AN-147
LM385 •....•...•.......•.•••.•.•.••.•.••••••.••••.••••.•.•. AN-242, AN-256, AN-301, AN-344, AN-460, AN-693, AN-n7
LM386 .........•.....•.....•.........•...•.•....•.•....••.•.••..•..•...•.•..•......••••..•..••.•..•...•.... LB-54
LM391 ..................•..•.....••.•.••.•.•..•.•....•••..•••.•..•••.••.•.•..•.•.•..•.•.••••.•..•.•.•..•.. AN-272
LM392 ....•.•..•.••.........•.....•.•..•.....•..•••.••.•..•••.•••.•••.•.•.•...••.•.••...•.••.....• AN-274, AN-286
LM393 •.•.••.•.••..•••••.•.•••..•.•....•.••.•.•.••.•.•.•....•.••.•.•..•••.••.•.•.. AN-271, AN-274, AN-293, AN-694
LM394 .•.••.•••••••....••••••.•.••••••••..•.••••••••.••••.•• AN-282, AN-263, AN-271, AN-293, AN-299, AN-311; LB·52
LM395 ......•.•.•..•.••••.•••.••••.•.•.••••••••••••• AN-178, AN-181, AN-262, AN-283, AN-266, AN-301, AN-460, LB-28
x
Device!Application Literature Cross-Reference (Continue2 ,,:
Dielectric Absorption: AN..260
Differential Analog Input: AN-233
Dual Slope Converter: AN-260
• Er'ro~:::"N.156
FET Switched Multiplexer: AN-260
Free-Running Interface: LB-53
Grounding Considerations: AN-274
Integrating Converters: AN-260
Integrating 10-Bit:AN-262'
Integrator Comparator: 'AN-260
Unearity Error Specificatioris~ AN-156 '
Logarithmic: AN-274
'o
"j,
Microprocessor Compatible: AN-284
Microprocessor Controlled Offset Adjust: AN-274
Microprocessor Interfacing: AN-274
Offset Adjust: AN-274
Ramp Generator: AN-260
Ratiometric Conversion: AN-247
References: AN-184
Resolution: AN-156, AN-276
Sampled Data Comparator: AN-276
Sampled Data Comparator Input AN-274
Single Slope Converter: AN-260
Single Supply: AN-245, AN:284 '
Span Adjustment: AN-233, AN-274
Specifications: AN-156, AN-769'
Successive Approximation Register: AN-193
Testing: AN-179, AN-233
Voltage Comparator! AN-276
Voltage Mode: AN-284
,'o
Z-80 Interface: AN-247
10-Bit Data Formats: AN-277
12-Bit Serial Output: AN-245
15-Bit Single Slope Integrating Converter: AN-295
6800 p.P Interface:'AN-247 ''o
8080 p.P Intertace: AN-247
ANALOG·TO·DIGITAL CONVERTER
As a Divider: AN-233
As a Voltage Comparator: AN-233
" ' ..
High Speed: AN-237
'
AND GATE: AN-72, AN-74
ANTI·LOG GENERATOR: AN-30, AN-31
ARC PROTECTION (CRT): AN-861
ATTENUATION
'
Digital: AN-284 (See also AGe)
AUDIO AMPLIFIERS: AN-32, AN-69,AN-72,
AN-346, AN-898
'
Bridge Amplifier: AN-69
Intercom: AN-69
Phono: AN-346
Power Am~lifier: AN~9 ,
xiv
Subject Index (Continued)
RIM: AN-346
Tone Control: AN-69
Voltage-COntrolled: AN-299
1A Class AB Current Booster: AN-127
100 mA Current Booster: AN-127
(See also FM Stereo, Amplifiers)
AUDIO PREAMPLIFIER
Flat: AN-346
Phono: AN-346
AUDIO MIXER: AN-72
AUTO ERROR CORRECTION: AN-360
AUTO GAIN RANGING: AN-360
AUTOMATIC GAIN CONTROL (See AGC)
AUTOMOTIVE
Anti-Skid Circuit: AN-162
Tachometer: AN-162
BANDPASS FILTER: AN-72, AN-307, AN-346, AN-779,
LB-11
BANDWIDTH, EXTENDED: AN-29, LB-2, LB-4,
LB-14, LB-19, AN-813
BANDWIDTH, FULL POWER: LB-19, AN-769
BATTERY
Charger: LB-35
BATTERY POWERED AMPLIFIERS: AN-71
BESSEL FILTER: AN-779
BI.QUAD FILTER: AN-72
BIAS CURRENT (See Drift Compensation)
Compensation: AN-3
Drift COmpensation: AN-3
BIAS CURRENT TEST SET: AN-24
BLINKER
Lamp: AN-11 0
Low Voltage IC: AN-154
Two Wire: AN-154
BOARD LAYOUT: AN-29, AN-813, AN-861
BOLOMETER (COMPARATOR): LB-32
BOOTSTRAPPED SHUNT FREQUENCY
COMPENSATION: AN-29
BREAKER POINT DWELL METER: AN-162
BRIDGE AMPLIFIER: AN-29, AN-31
BUFFERS: AN-49, AN-227
High Current: AN-4, AN-13, AN-29, AN-31,
AN-46, AN-272, LB-44
Using CMOS Amplifiers: AN-88
(See also Voltage Followers)
BUTTERWORTH FILTER: AN-779
BYPASSING, SUPPLY TERMINAL: AN-4, AN-227,
AN-253, LB-2, LB-15
CABLE DRIVER: AN-813
CAD SYSTEM: AB-7
CALIBRATOR
Oscilloscope Square Wave: AN-154
CAPACITANCE MULTIPLIER: AN-29, AN-31
Digitally Controlled: AN-271
Programmable: AN-344
CAPACITIVE TRANSDUCER: AN-162
CAPACITORS
Bypass: AN-4, AN-428, LB-2, LB-15
COmpensation: AN-29
(See also Frequency COmpensation)
Dielectric Polarization: AN-29
Electrolytic as Timing Capacitor: AN-97
Filter, Power Supply: AN-23
Multiplier, Capacitance: AN-29, AN-31
Tantalum Bypass: LB-15
CARRIER CURRENT TRANSCEIVER: AN-146
CASCODE AMPLIFIER: AN-32
CHARGER: LB-35
CHEBYSHEV FILTER: AN-779
CHOPPER AMPLIFIERS, ALTERNATIVES: AN-79
CHOPPER DRIVES: AN-828
CHOPPER STABILIZED AMPLIFIER: AN-49
CIRCUIT DESCRIPTIONS: AN-49
LH0002 Current Amplifier: AN-13
LH0033 Buffer Amplifier: AN-48
LM34/LM35 Temperature Sensor: AN-460
LM105/LM205/LM305 Positive Voltage
Regulator: AN-23
LM108/LM208/LM308 Operational Amplifier: AN-29
LM109/LM209/LM309 Three Terminal
Regulator: AN-42
LM110/LM210/LM310 Voltage Follower: LB-11
LM111/LM211/LM311 Voltage
Comparator: AN-41, LB-12
LM113 1.2 Volt Reference Diode: AN-56
LM118/LM218/LM318 High Slew Rate Op Amp: LB-17
LM565 Phase Locked Loop: AN-46
LM1894 DNRTM: AN-386
LM3900 Quad Amplifier: AN-72
LM4250 Micropower Programmable Op Amp: AN-71
CLAMP
Back Porch: AN-861
Grid (CRn: AN-867
Precision: AN-31 , LB-8
CLASS A AUDIO AMPLIFIER: AN-72
CMOS LINEAR AMPLIFIERS (See Amplifiers, CMOS)
CMOS LOGIC VOLTAGE REGULATOR: AN-71
COAXIAL CABLE DRIVE: AN-227
COLD JUNCTION COMPENSATION: AN-222, AN-225
COMMUTATION: AN-49
COMPARATORS (See Voltage Comparators)
COMPENSATION, DRIFT (See Drift Compensation)
COMPENSATION, FREQUENCY
(See Frequency Compsnsatlon)
COMPENSATION, TEMPERATURE
(See Drift Compensation)
xv
...
=
"CI
.5
'0
CD
~
Subject Index (Continued)
COMPONENT NOISE (See Nolae. CoInponent). CONTINUITY CHECKER. AUDIBLE: AN-154
CONTROL SYSTEM. ENVIRONMENTAL: AN-19S
CONVERTER
100 MHz: AN-32
AC to DC: AN-S1, LB-8
Analog-to-Digital: (See Analog-to-Digital)
Cable: AN-S91
Current-to-Voltage: AN-20, AN-31 - DC-to-DC: LB-18 (See also SWitching Regulator)
Digitally Programmable Band Pass Filter. AN-299
Digitally Programmable Panner Attenuator: AN-299
Frequency to Voltage: AN-97, AN~210, LB-45,
Appendix C, Appendix 0
Logarithmic: AN-29, AN-SO, AN-S1
Phono Preamp: AN-299
Voltage Controlled Amplifier: AN-299
VOltage-to-Frequency: AN-286, AN-299, Appendix 0
COUNTER. PULSE: AN-72
CRT DEFLECTION CIRCUITRY: AN-856
CRT MONITOR: AN-656
CROSSOVERS
Active: AN-S46
CRYSTAL OSCILLATOR: AN-32, AN-41, AN-74, AN-402
CUBE GENERATOR: AN-SO, AN-S1
CURRENT AMPLIFIER
High Output: AN-227, AN-262
CURRENT BOOSTER: AN-127, AN-2l!7
CURRENT LIMITING
Adjustable: AN-21
External: AN-21 , AN-29, AN-227
External Circuit: AN-82, AN-227
Foldback: AN-82 (See Foldback Current Limiting)
Output Short Circuit: AN:72, AN-227
Sense Voltage Reduction: AN-21 , AN-31, AN-32
Switchback (See Foldback Current Limiting)
Switching Regulator: AN~21_
Two Terminal Current Limiter: AN-110
1A, 65V Power Supply with Variable Current
Limit: AN-127
CURRENT LOOP: AN-300
CURRENT MEASUREMENT: AN-SOO
CURRENT MIRROR: AN-72
CURRENT MOTOR: AN-31, AN~S2, AN-SOO (See also Current-to-VoltageConverterj'
CURRENT NOISE (See No.... Current)
CURRENT SINK
Digitally Controlled: AN-271
Fixed: AN-72
Precision: AN-20, AN-S1-, AN-S2
CURRENT SOURCE
Bilateral: AN-29, AN-S1
High Compliance: AN-127
High Current: AN-42
Multiple: AN-72
Precision: AN-20, AN-S1, AN-S2
Programmable: AN-S44
Two Terminal: AN-110
200 mA: AN-10S
CURRENT-TO-FREQUENCY CONVERTER: AN-240CURRENT-TO-VOLTAGE CONVERTER: AN-20, AN-31
DATA ACQUISITION SYSTEM: AN-906
D-TO-A CONVERTER: (See Dlgltal-ta-Analog)
DC SERVO-MOTOR CONTROLLERS: AN-460
r-,
DCoTO-AC CONVERTER: LB-18
DELAY SWITCH: AN-110
Two Terminal: AN-97 (See also TImers)
DEMODULATORS: AN-49
AM-FM: AN-46
FrequencY Shift Keying: AN-46
IRIG Channel: AN-46
Weather Satellite Picture: AN-46
DETECTORS: AN-391
Peak: AN-87, AN-S86
Pulse Width: (See Pulse Width Detectors)
Synchronous: AN-S91 _
True RMS: LB-2SZero Cross: AN-74
(See also Demodulators)
DIELECTRIC ABSORPTION: AN-260 DIELECTRIC POLARIZATION CAPACITOR: AN-29
DIFFERENCE AMPLIFIER: AN-20, AN-29, AN-31,
AN-72
DIFFERENCE INTEGRATOR: AN-72
DIFFERENTIAL SIGNAL COMMUTATOR: AN-49
DIFFERENTIATOR: AN-20, AN-31, AN-72
DIGITAL DIVIDER
Variable Ratio: AN-286
DIGITAL GAINSET:AN-344 _
:,
DIGITAL INSTRUMENTATION AMPLIFIER: AN-344
DIGITAL MULTIMETER: AN-202 DIGITAL SWITCHING CIRCUITS: AN-72
DIGITAL-Ta-ANALOG CONVERTER: AN-48
Amplifier Gain Control: AN-271, AN-284
Composite Low Offset Fast Amplifier: AN-271
Digitally Controlled AC Attenuator: AN-284 - _
Digitally Controlled Capl\citance Amplifier: AN~271
Digitally Controlled Curren~ Sink: AN-271Digitally Controlled Functiciri ,13enerator: AN-271
High Voltage Output: AN-2i1: AN-29S_ Output Range Level Shifting: AN-27_1
Plate Drivlng Deflection Amplifier: AN-293
Processor Controlled Shaker Table Driver: AN-29S
Scanner Control: AN-29S
xvi
".,.:",
tn
c
Subject Index (Continued)
Single Supply Voltage Mode: AN·271
Temperature Limit Controller: AN·293
Used as a Digitally Programmable
Potentiometer: AN·271
Vernier Adjustment: AN·271
4-Quadrant Multiplexing: AN·271
4 to 20 mA Current Loop: AN·271
DIODE
Catch: AN·22
Clamps: AN·861
Precision: AN·31 , AN·173, LB·8
Protective: AN·21 , AN·861
Reference: AN·56, AN·11 0
Zener: AN·56
Zenered Transistor Base-Emitter Junction: AN·71
DISCRETE TIME SYSTEM: AN·236
DISCRIMINATOR, MULTIPLE APERTURE
WINDOW: AN·31
DIVIDER, ANALOG: AN·4, AN·30, AN-31, AN·222
DNRTM
Applications: AN·390
Calibration: AN-390
Cascading: AN-390
Circuit Design: AN-386
Operating Principles: AN·384
DOUBLE ENDED LIMIT DETECTOR: AN·31
DOUBLE SIDEBAND MODULATOR: AN-38, AN-49
DOUBLER,FREQUENCY:AN-41
DRIFT
Minimizing in Amplifiers: LB·22, LB·32, AN·242
DRIFT COMPENSATION: AN·79, AN·242
Bias Current: AN·3, AN·20, AN·29, AN-31
Board layout AN·29
Gain, Transistor: AN·56
Guarding Inputs: AN·29
Integrator, Low Drift: AN·31
Non·Linear Amplifiers: AN-4, AN-31
Offset Voltage: AN·3, AN·20, AN·31 , AN·242
Reset Stabilized Amplifier: AN·20
Sample and Hold: AN-4, AN·29
Transistor Gain: AN·56
Voltage Regulator: AN·21 , AN·23, AN-42, LB·15
DRIFT, VOLTAGE AND CURRENT: AN·29
(See also Drift Compensation)
DRIVERS
Cable: AN·813
Chopper: AN-828
LlR: AN·828
MOS Clock Driver: AN·74
Zero Crossing Detector and Line Driver: AN·162
(See also Voltage Followers, Buffers, Amplifiers)
DUAL TRACKING REGULATORS
(See Regulators, Dual Tracking)
DIGITAL VOLT METER (DVM): AN·200
DWELL METER: AN·162
DYNAMIC SPECIFICATIONS: AN·769
ECL (See Emitter Coupled Logic)
ELECTRONIC SHUTDOWN: AN·82, AN·103
ELLIPTIC FILTER: AN· 779
EMI (Electromagnetic Interterence): AN-861
EMITTER COUPLED LOGIC, DIRECT
INTERFACING: AN·87
EQUALIZER, GRAPHIC: AN-435
ERRORS
Low Error Amplifiers: LB·21
Reducing Comparator Errors for 1 p.V Sensitivity: LB·32
FEEDFORWARD COMPENSATION: LB·2, LB·14, LB·17
FERRITE BEAD: AN·23
FET
Amplifier:. A/Ii·32
Operational Amplifier Input: AN·4, AN-29, AN-32,
AN·447
Switches: AN·32, AN-447
Volt Meter, FET VM: AN·32
FILTER: AN-307
Adjustable Q: AN·31 , LB·!;,
Bandpass: AN·72, AN·712, AN·779, LB·11 (See also
Filter, Notch)
Bessel: AN·779
Bi·Quad: AN·72
Butterworth: AN·779
Chebeyshev: AN·779
Digitally Programmable Gain: AN·269
Elliptic: AN·779
Full Wave Rectifying and Averaging: AN·20, AN-31
High Pass Active Filter: AN·31 , AN·72, AN·227,
AN-346, LB·11, AN·779
Infresound: AN-346
Low Pass Active Filter: AN·20, AN·31, AN·72,
AN·286, AN·346, AN·779
Low Distortion: AN·346, AN·386
Low Pass Adjustable: AN-384, AN·386
Notch: AN·31 , AN-48, AN·227, AN·712. AN·779, LB·5,
LB·11
Notch, Adjustable Q: AN·31 , AN·779, LB·5
PID: AN-893, AN·706
Power Supply: AN·23, LB·10
Programmable: AN-344
Sallen Key: AN·779
Sensitivity Functions: AN·72
Surface Acoustic Wave: AN-391
Switched Capacitor: AN·779
Tone Control: AN·32
Ultrasound: AN·346
Vestigial Side Band: AN·402
xvii
f
I
...
'~ r-----------------~----------------------------------------------------------~
i
1
2i
c;J
Subject Index (Continued)
FLASHER
Inexpensive IC: AN·154
Lamp: AN·11 0
Two Wire: AN·154
FLIP-FLOP, TRIGGER: AN·72
FLUID LEVEL CONTROL: AB·10
FLYBACK POWER SUPPLY: AN·S56
FM
Blend: AN·390
Calibration Modulation Level: AN-402
FM STEREO
Remote Speaker: AN·146
FOLDBACK CURRENT LIMITING
Negative Voltage Regulator: AN·21 , LB-3
Positive Voltage Regulator: AN.23, LB-3
Power Dissipation Curve: AN·23
Temperature Sensitivity: AN·23
(See also Current Limiting, Foldback)
FOLLOWERS, VOLTAGE (See Voltage Followers)
FREQUENCY COMPENSATION: AN·79
Bandwidth, Extended: AN·29, LB·2, LB·4, LB·14,
LB·19, LB·42
Bootstrapped Shunt: AN·29
capacitance, Stray: AN-4, AN-31, AN·428
Capacitive Loads: AN·4, AN-447, LB·14, LB·42
Differentiator: AN·20
Feedforward: LB·2, LB·14, LB·17
Ferrite Bead: AN·23
Hints: AN·4, AN·20, AN·23, AN-41, AN-447,
LB·2, LB-4, LB·42
Multiplier: AN·210
Multivibrator: AN·4
Oscillation, Involuntary: AN-4, AN·20, AN·29
FREQUENCY DOUBLER: AN-41
FREQUENCY RESPONSE: LB·19
(See also Frequency Compensation)
FREQUENCY SHIFT KEYING DEMODULATOR: AN-46
FREQUENCY-TO-CURRENT CONVERTER: AN·162
FREQUENCY-To-VOLTAGE CONVERTER: AN·97,
AN·162, AN·21 0
FULL POWER BANDWIDTH: LB·19, AN·769
FUNCTION GENERATOR (See Generator)
GAI~ CONTROL
Digital: AN·269
Voltage Controlled: AN·299 (See also AGC) .
GAIN TEST SET: AN·24
GATES, OR AND AND: AN·72
GENERATOR
Digitally Controlled: AN·435
Multiple Function: AN·115, LB·23
One Shot: AN·88
Programmable: AN·344
Pulse Generator: AN·74
Sine Wave: AN·115
Square Wave: AN·74, AN·88, AN·154, LB·23
Staircase: AN·88, AN·162
Time Delay: AN·14
Triangle Wave: LB·23 (See also OSCillator)
GRAPHIC EQUALIZER
Digitally Controlled: AN·435
GUARD DRIVER: AN-48, AN·227
GUARDING AMPLIFIER INPUTS: AN·29
GYRATOR (See Inductor, Simulated)
H-BRIDGE: AN-693, AN·694
HALL EFFECT SENSOR (COMPARATOR): LB·32
HARMONIC DISTORTION: AN·769
HIGH FREQUENCY: AN·227~ AN·253, AN·391
HIGH PASS ACTIVE FILTER: AN-31, AN·72, AN-307,
AN·346, AN·779, LB·11
HIGH PASS FILTER: AN·227, AN·307, AN·346
HIGH SPEED DUAL COMPARATOR: AN·115
HIGH SPEED OP AMP: AN·278, AN-428, AN-813, LB-42 .
HIGH SPEED PEAK DETECTOR: AN·227
HIGH SPEED SHIELD/LINE DRIVER: AN·227
HIGH VOLTAGE
Driver: AN-49
Flasher: AN·154
Op Amp: AN·127
Regulator: AN·103
HUMIDITY MEASUREMENT: AN·256
INDICATOR
Applications: AN·154
INDUCTANCE-RESISTANCE (L/R) DRIVERS: AN-828
INDUCTOR
Core, Switching Regulator: AN-21
Ferrite Bead: AN-23
Simulated: AN-31, AN-435, AN-712
Voltage·Controlled: AN·712
INSTRUMENTATION AMPLIFIER
(See AmplHlers, Instrumentation)
INPUT GUARDING: AN-29, AN-48
INTEGRATOR: AN-20, AN·29, AN-31, AN-32,
AN-72
INTERMODULATION DISTORTION: AN·769..
INTERNAL TIMER: AN·31
INTRUSION ALARM
Fiber Optic: AN·266
INVERTING AMPLIFIER: AN·20, AN-31, AN·n,
AN·72, LB·17
ISOLATED INPUT SIGNAL CONDITIONING
AMPLIFIER: AN·266
ISOLATION AMPLIFIER: AN·266, AN·285
ISOLATION, DIGITAL: AN-41
xviii
Subject Index (Continued)
ISOLATION TECHNIQUES
MODEM FILTER: AN-307
Thermocouple: AN-298
MODULATION AND DEMODULATION: AN-38, AN-49,
AN-402
Transformer: AN-266, AN-285
MODULATOR
JFETs: AN-32
FM Audio: AN-402
JUNCTION TEMPERATURE, MAX ALLOWABLE: AN-336
Pulse Width: AN-31
LAMP DRIVER
Ground Referenced: AN-72
MOISTURE DETECTOR: AB-10, AN-154
Voltage Comparator: AN-4, AN-72, LB-12
MONOSTABLE MULTIVIBRATORS (See Multlvlbrator)
LARGE SIGNAL RESPONSE: LB-19
MOS ANALOG SWITCH: AN-49
LED (See Light Emitting Diode)
MOS DIFFERENTIAL SWITCH: AN-49
LEVEL DETECTOR WITH HYSTERESIS: AN-87
MOTION CONTROL: AN-693, AN-706
LEVEL SHIFTING AMPLIFIER: AN-4, AN-13,
AN-32, AN-41, AN-48
MOTION DETECTOR (See Sensor, Air; Sensor, Liquid)
LIGHT ACTIVATED SWITCH: AN-10
MOTOR SPEED CONTROLLER: AN-292
LIGHT EMITTING DIODE
MOTOR, STEPPER: AN-828
MOTOR CONTROL: AN-693, AN-694
1.5V LED Flasher: AN-154
MOTOR TORQUE CONTROLLER: AN-693, AN-828
LIMIT DETECTOR: AN-31
MULTIPLEXER (See Analog Switch)
LIMITER (See Clamp)
MULTIPLIER
LINE DRIVER: AN-13, AN-48
Analog: AN-4, AN-20, AN-30, AN-31 , AN-222
LINE RECEIVER AMPLIFIER: AN-72
Capacitance: AN-29, AN-31
LINE RECEIVERS, COMPARATORS SUITABLE
FOR: AN-87
Cube Generator: AN-30, AN-31
Resistance: AN-29
LIQUID DETECTOR:AB-10, AN-154
LM12 150-WATT OP AMP: AN-446
MULTIVIBRATOR: AN-4, AN-24, AN-31 , AN-41,
AN-71 , AN-72, AN-74
LOGARITHMIC AMPLIFIER: AN-29, AN-30,
AN-31 , AN-211
NEGATIVE AND POSiTIVE VOLTAGE REGULATORS
(See Symmetrical Voltage Regulators)
DAC Controlled Scale Factor: AN-269
NEGATIVE REGULATOR
(See Negative Voltage Regulators)
Digitally Programmable: AN-269
LOGARITHMIC CONVERTER: AN-311
NEGATIVE VOLTAGE REFERENCE: AN-20, AN-31
LOW PASS ACTIVE FILTER: AN-20, AN-31 , AN-72,
AN-307, AN-346, AN-779
NEGATIVE VOLTAGE REGULATOR
Circuit Description LM104/LM204/LM304: AN-21
Drift Compensation
(See Drift Compensation, Voltage Regulator)
LOW DRIFT AMPLIFIERS (See Amplifiers, Low Drift)
LVDT
Foldback Current Limiting: AN-21, LB·3
Position Sensor: AN-301
MACROMODELS (See Models, Spice)
High Current: AN-21,
MAGNETIC
High Voltage: AN-21
Hints: LB-15
Variable Reluctance Pickup Buffer: AN-162
MAGNETIC FIELD SENSOR: AN-301
Line Regulation Improvement: AN-21
MAGNETIC TAPE: AN-390
Low Dropout Voltage: AN-211
MAGNETIC TRANSDUCER AMPLIFIER: AN-74
Overvoltage Protection: AN-21
METER AMPLIFIER: AN-71, AN-222, AN-265
Power Dissipation:,AN-21
MICROPHONE PREAMPLIFIER: AN-299, AN-346
Precision, Stable: LB-15
MICROPOWER
Amplifier: AN-71 , AN-211
Programmable: AN,20, AN-31
Protective Diodes: AN-21
Circuit Description LM4250 Programmable
Op Amp: AN-71
Remote Sensing: AN-21
Voltage Comparator: AN-71
Switching: AN-21
Ripple: AN-21
Three Terminal: AN-182
MIXER
Audio: AN-72
Transient Response: AN-21
NIXIE DRIVER: AN-32
Low Frequency: AN-72'
MODELS
Spice: AN-813, AN-840, AN-856
xix
Subject Index (Continued)
NOISE:
Component: AN-104
Figure: AN-104. AN-222. AN-391
Filtering in Microvolt Comparators: LB-32
Generator. "Buzz Box": AN-154
ifF: AN-104
Measurement: AN-180
Television Receiver:'AN-391
Thermal: AN-104
Theory: AN-222
Voltage: AN-104
Weighting: AN-384
NOISE REDUCTION'
Audio: AN-384. AN-'386
Comparison of Types: AN-384
Complementary: AN-384
FM: AN-390
Masking: AN-384. AN-386
Single-Ended: AN-384.AN-386. AN-390
Tape: AN-390
Television Audio: AN-390
VTR: AN-390
NON-INVERTING AMPLIFIER: AN-20. AN-31. AN-72
NON-LINEAR AMPLIFIER: AN-4. AN-31
NORTON AMPLIFIER: AN-72. AN-278
NOTCH FILTER: AN-31. AN-48. AN-a07. AN-779. LB-5.
LB-11
'
L/C: AN-402
Morse Code: AN-154
Multivibrator: AN-4. AN-24. AN-31. AN-41. '
AN-71. AN-72
One Shot: AN-88
Piezoelectric Driver: AN-72
Programmable "Unijunction": AN-72
Pulse: AN-97
Pulse Output: AN-71, AN-72
Quadrature Output: AN"31. LB-t6
RF: AN-4Q2
RF JFET: AN-32
Sawtooth: AN-72
Sine Wave: AN-20. AN-29, AN-31. AN-32.
AN-72. AN-115. AN-264. AN·712. LB-16
Square Wave: AN-88
Staircase: AN-72
Television: AN-402
Triangle Wave: AN-20. AN-24. AN-31. AN-72
Tunable Frequency: LB-16
Vestigial SidE! Band: AN·402
Video: AN-402
Voltage-Contro"ed: AN-24. AN-72. AN~81. '
AN-146. AN-162. AN-391, Appendix C
Wien Bridge: AN-20. AN-31. AN~2
OVERSPEED LATCHESIINDICATORS
(See Frequency-to-Voltage)
PACKAGE POWER CAPABILITIES: AN-336
PARALl.ELlNG OP AMP: LB-44
PEAK DETECTOR: AN-4. AN-31, AN-72, AN-74.
AN-87. AN-227. AN-386
PHASE
Phase Shift Oscillator: AN-88
PLL Range Extender: AN-162
Wide Range Phue,Shifter: AN-391
PHASE COMPARATOR: AN-72
PHASE LOCKED LOO!': AN.146, AN-391, AN-81
Advantages as Voltage-to-Frequency
Converter: AN-210
Circuit DeSCription, LM565: AN-46,
Damping: AN~
FM Audio Modulation: AN-402
Locking: AN~46
Loop Filter: AN-46
Multiamplifier: AN-72
Noise Performance: AN-46
Phase Comparator: AN-72
Theory: AN-46
VCO: AN-72
PHASE SHIFT OSCILLATOR: AN-88
PHASE SHIFTER: AN-32
PHONO PREAMPLIFIER: AN-32. AN-222. AN-346
PHOTOCELL AMPLIFIER: AN-20
OFFSET,
Ajusting Offset and Drift to Almost
Zero: AN-79. LB-32. AN-242
Drift Compensation: AN-3
Voltage Compensation: AN-3
OFFSET CURRENT TEST SET: AN-24
OFFSET VOLTAGE ADJUSTMENT: LB-9
OFFSET VOLTAGE COMPENSATION
(See Drift Compensation)
OFFSET VOLTAGE TEST SET: AN-24
ONE SHOT: AN-72. AN-88
OPERATIONAL AMPLIFIERS:
(See Amplifiers, Operational)
OPERATIONAL AMPLIFIER TESTlNG:AB-12
OPERATIONAL AMPLIFIER TEST SET: AN-24
OPERATIONAL AMPLIFIER VOLTAGE
REFERENCE: AN-288
OPTICALLY ISOLATED SWITCHES
(See SWitches, Optically Isolated)
OR GATE: AN-72. AN-74
Regulator: AN-103
OSCILLATION, INVOLUNTARY
(See Frequency Compensation)
OSCILLATOR
Crystal: AN-41. AN-74, AN-402
Crystal JFET: AN-32
Fiber Optic: AN-266
Inexpensive IC: AN-154
xx
Subject Index (Continued)
PHOTODIODE
Amplifier: AN-20, AN-29, AN-31 , AN-244, LB-12
Level Detector: AN-41 , AN-244
PHOTORESISTOR AMPLIFIER: AN-29
PID CONTROLLER: AN-693, AN-706
PIN DIODE DRIVER: AN-49
PIN DIODE SWITCHING: AN-49
POLARITY SWITCHER: AN-344
POLARIZATION, DIELECTRIC: AN-29
POSITION SENSOR: AN-162
LVDT: AN-301
POSITIVE AND NEGATIVE VOLTAGE REGULATORS
(See Symmetrical Voltage Regulators)
POSITIVE REGULATOR (See Regulator, Positive)
POSITIVE VOLTAGE REFERENCE: AN-20, AN-31 , AN-56
POSITIVE VOLTAGE REGULATOR
Adjustable Output: AN-42, AN-178, AN-181,
AN-182, LB-35
Bootstrapped Regulator: AN-211
Circuit Description LM105/LM205/LM305: AN-23,
AN-211
Circuit Description LM109/LM209/LM309: AN-42
CMOS Compatible: AN-71
Current Limit: AN-72, AN-211
Drift Compensation
(See Drift Compensation, Voltage Regulator)
Failure Mechanisms: AN-23
Filtering, Power Supply: AN-23
Fixed Output: AN-42
Foldback Current Limiting: AN-23
Heat Dissipation: AN-23
High-Current: AN-23, AN-72
High Voltage: AN-72, AN-211, LB-47
Hints: AN-23, LB-15
Low Voltage: AN-56, AN-211
Micropower Quiescent Power Drain: AN-71 , AN-211
NPN Pass Transistors: AN-72
Power Limitations: AN-23
Precision: AN-42, LB-15
Programmable Low Power: AN-20, AN-31
Protection: AN-23, AN-72
Ripple Induced Failures: AN-23
Switching Regulator (See Switching Regulator)
Temperature Compensation: AN-42, LB-15
Three Terminal: AN-103, AN-178, AN-182, LB-35
Trimming Output Voltage: LB-46
(See also Voltage Regulators)
POWER AMPLIFIER (See Butter, High Current)
POWER CAPABILITIES, IC PACKAGE: AN-336
POWER DISSIPATION
Regulator: AN-82, AN-103
H-Bridge: AN-694
POWER LINE CARRIER: AN-146
POWER SUPPLY: AN-56
General Purpose: LB-28
Monitor: LB-48
Programmable: LB-49 (See also Regulators)
Split: AN-69, AN-71
PREAMPLIFIER
CRT: AN-861
Phono: AN-32, AN-222, AN-346
Servo: AN-4, AN-31
Stereo: AN-346
Video: AN-861
(See also Amplifiers, Preamp)
PRECISION REFERENCE: AN-161, AN-173
PROGRAMMABLE GAIN: AN-289
PROGRAMMABLE OP AMP: AN-71
PROGRAMMABLE "UNIJUNCTION"
OSCILLATOR: AN-72
PROGRAMMABLE VOLTAGE REGULATOR:
AN-20, AN-31
PULSE AMPLIFIER: AN-13, AN-813
PULSE COUNTER: AN-72
PULSE GENERATOR: AN-71 , AN-72, AN-74
PULSE STRETCHER:
Proportional: AN-266
PULSE WIDTH DETECTOR: AN-97
PULSE WIDTH MODULATOR: AN-21 ,
AN-31 , AN-74, LB-18
PULSE WIDTH MULTIVIBRATOR: AN-292
PYROELECTRIC
Accelerometer: AN-301
Detector Amplifier: AN-301
Resonator Temperature Sensor: AN-301
QUAD AMPLIFIER: AN-71 , AN-72
QUAD COMPARATOR: AN-74
QUADRATURE OSCILLATOR: AN-31 , AN-307, LB-16
RATE GYRO: AN-301
RECEIVER
FM Remote Speaker: AN-146
Infared: AN-290
Television: AN-391
VHF: AN-290
Ultrasonic: AN-290
RECTIFIER, FAST HALF·WAVE: AN-31 , LB-8
RECTIFIER, FULL·WAVE: AN-20, LB-8
REFERENCE
Low Drift Precision 6.9V: AN-161, AN·173, AN-184
Micropower: AN-222, LB-34, LB-41
Precision: AN-79, AN-161, LB-41
REFERENCE DIODE: AN-11 0
REFERENCE VOLTAGE: AN-211
REFERENCE VOLTAGE DETECTOR: AN-300
REFERENCE VOLTAGE REGULATOR: AN-20, AN-31
REGULATORS (See Voltage Regulators)
xxi
Subject Index (Continued)
RELAY DRIVER: AN-72
REMOTE LINKS
Infared: AN-290
VHF: AN-290 '
Ultrasonic: AN-290
REMOTE SENSING
High Current Negative Regulator: AN-21 '
High Negative Voltage: AN-21
REMOTE SPEAKER SYSTEM: AN-146 ,
REMOTE TEMP SENSOR/ALARM: AN-74
RESET STABILIZED AMPLIFIER: AN-20 '
RESISTANCE
Choice of Resistors fo(Op Amps: AN"79
Tester for Low Values of Resistance: LB-32 "
RESISTANCE MULTIPLICATION: AN-29
RESISTOR VALUES, STANDARD: Appendix E
RF: AN-391
RF AMPLIFIER
Cascade: AN-32, AN-813
RF OSCILLATOR (See Oscillator; RF)
RIAA PHONO PREAMPLIFIER: AN-222,
AN-299, AN-346
RIPPLE, POWER SUPPLY: AN-21 , AN-23,' LB-10
RISE TIME, AMPLIFIER: LB-19
RMS
True RMS Detector: LB-25
ROOT EXTRACTO~: AN4, AN-31, AN-222
RTD CONTROLLER: AN-292
SAFE AREA PROTECTION: AN-103
SALLEN-KEY FILTER: AN-779
SAMPLE AND HOLD: AN-4, AN-2!j1"AN-31, AN-32,
AN-72, AN-266, AN-294, LB-11.LB-45
Circuit: AN-286
Extended HO~D Time: AN-245, AN-294
High Speed: AN-253, AN-294
HOLD Step: AN-294
Infinite: AN-245
Infinite HOLD Time: AN-245, AN-294
Reduction of HOLD Step: AN-245, AN-294
Terms: AN-266
SAMPLING THEOREM: AN-236
SAWTOOTH ~ENERATOR: ANc72
SCHMITT TRIGGER: AN-~2, AN-,72 '
SENSE VOLTAGE (See Current Umltlng)
SENSITIVITY FUNC!IONS: AN-72
: '''',
SENSOR
Mass Velocity: AN-162
Rotational Velocity: AN-162
SERVO PREAMPLIFIER: AN-4, AN-31
, "
SETTLING TIME:, LB-n' .
, ,
SHORT CIRCUlfpROTECTION (See Current limiting)
SIGNAL-To-NOI$~ :RATIO: AN-1 04,' AN-769 ' " ,'. ,
,
"I' ~
SINE SHAPER: AN-263
SINE WAVE GENERATOR: AN-115, AN-263,
AN-269, AN-307
SINE WAVE OSCILLATOR: AN-20, AN~29, AN-31,
AN-32, AN-72, AN-263, LB-16
Crystal: AN-263
Digital: AN-263
High Voltage: AN-263
Phase Shift: AN-263
Sine Wave Voltage Reference: AN-262,
Tuning Fork: AN-263
Voltage-Contro,led: ,AN-262
Wien Bridge: AN-263 '
SINE WAVE RESPONSE: LB-19
SINGLE SUPPLY' AMPLIFIER: AN-72
SINGLE SUPPLY OPE~TlQN: AN-31, AN-48
SIREN OSCILLATOR: AN-154
SLEW RATE: LB-17, LB-19, LB-42
(See also Frequency Compensation, Feedforward)
SLEW RATE LIMITING: LB-19
SMALL SIGNAL RESPONSE: LB-19
SIN RATIO (See Signal-to-Noise Ratio)
SOLAR CELL AMPLIFIER: AN-4
SOUND
Peak: AN-384
Pressure: AN-384
Sound Effects Oscillator: AN·154
SPEED SENSOR (See SensGr, Speed)
SPEED SWITCH (See Frequency-ta-Voltage Converter)
SPICE (See Models)
SQUARE ROOT CIRCUIT: AN-4, AN-31 , AN-222
SQUARE WAVE GENERATOR: AN-74, AN-88, AN-115,
AN-154. AN-222. LB-23
SQUARING AMPLIFIER: AN-72. AN-222
SQUARING CIRCUITS: AN"222
STAIRCASE GENERATOR: AN-72, AN-88
(See also Generator, Staircase)
STANDARD VALUES RESISTOR: Appendix E
STEP RESPONSE: LB-19
STEPPER MOTOR: AN-828
STEREO (See FM Stereo)
STEREO PREAMPLIFIER: AN-346
STRAIN GAUGE CONVERTER: ,AN-301
SUBTRACTOR (See' Difference Amplifier)
SUMMIt-..-- OUTPUT
R3
ISOK
TUH/6925-1
Figure 1. Summing amplifier with blas-current compensation for fixed source resistances
Figure 2 shows a similar circuit for a non-inverting amplifier.
The offset voltage produced across the DC resistance of
the source due to the input current is cancelled by the drop
across R3. For proper adjustment range, R3 should have a
maximum value about three times the source resistance
and the equivalent parallel resistance of R1 and R2 should
be less than one-third the input source resistance.
This circuit has the same advantages as that in Figure 1,
however, it can only be used when the input source has a
fixed DC resistance. In many applications, such as long-interval integrators, sample-and-hold circuits, switched-gain
amplifiers or voltage followers operating from unknown
source, the source impedance is not defined. In these cases
other compensation schemes must be used.
Figure 3 gives a compensation technique which does not
depend upon having a fixed source resistance. A current is
injected into the input terminal from the base of a PNP transistor. Since NPN input transistors are used on the integrated amplifier,' the base current of the PNP balances out the
'This is true lor all monolRhic, ~rational amplifiers presently available.
R2
10K
RI
IK
OUTPUT
INPUT
&1
TUH/6925-2
Figure 2. Non-lnvertlng amplifier with bias-current compensation for fixed source resistances
impedance (to about ,150 MOl because the current $upplied
by the PNP will varY with the inputvoltSge' level.
If this '?haracte(istic is objectionable, the more-complicated
circuit sllown in Figure 4 Can be used.
'
' ".
The emitter of the PNP' transistor is fed, from a current
source so that the compensating current does not vary with
input-voltage level. The design of the current source is such
as to give it about the same characteristics
tho.se, ori the
input stage of the better mono.lithic amplifiers; to give closer compensation with changes in temperature and supply
voltage. The circuit makes use of the emitter base voltage
differential between two transistors operated at different
colleCtor eurrei1ts. 1,2 Althc>ugh 'It is recommended in the ref'erences' that these tranSistorS be well matched; it is not
really necessary since the devices are -operated at much
different collector currerits.
'
FlfJuie '5 shows another compensatio!) scheme f9r the voltage follOwer connection. This circUit.is milch simpler than
that shown, in Figure 4, but the te,mperature compensation is
not quite as good. The compensating current is 'obtained
through a resistor connected across a diode which is bootstrapped to the output. The diode acts as a regulator so that
the cOmpensating current does not change appreciably with
'sign8llevel,giving input impedances about 1000 MO. The
negative temperature coefficient of the diode voltage also
provides some temperature compensation.
y+
R,'
'.IM
,NPUT
as
--+--........;Of
OUTPUT
TL/H/6925-3
Figure 3. Summing amplifier with blas-current compensatiGn
r------t-- v·
AI
IIOK
HI
10K
01
112'
1M
, V'
.>'-"-OUTfIIT
.INPUT - - -. . ._-_......;..
INPUTS
OUTPUT'
'Select for zero Input current
CI
IOpf
TLlH/6925-5
v-
, FIgure 5. VGRage fGllGwer with bias-currant compensa,tlGn
All the c;:ircuits discussed thus far have been tailored for
particular applications. Figure 6 shows a completelS'-general
scheme wherein both inputs are current compensated over
against power supthe full common mocie range as well
ply and temperature' variations. This circuit is suitable for
use either as a summing amplifier or as anon-inverting amplifier. It is not required that the DC impedance seen by both
inputs be equal, although lower drift can be expeCted if they
are.
As was mentioned earlier, all the bias compensation circuits
require adjustment. With the circuits in Figures 1 and 2, this
is merely a matter of adjusting the potentiometer for zero
output with zero input. It is not so simple with the other
circuits, however. For one, it is difficult to use potentiometers because a very wide range of resistance values are
required to accommodate expected unit-to-unit variations.
Resistor selection must therefore be used. Test circuits for
selecting bias compensation resistors are given in Figure 7.
'Select for zero Input currant
as
TL/H/6925-4
Figure 4. Blas-current compensatlGnfGr nGn-invertlng
amplifier Gperated Gver large commGn mGde
range
base current of the NPN. Further, since a silicon-planar PNP
transistor has apprOximately the saine current-gain versus
temperature characteristic as the integrated tranSistors, an
improvement in temperature drift will also be realized. t
However, perfect compensation should,not be expected because of unit-to-unit variations in the temperature characteristics of both the PNP transistor and the integrated circuit.
Although the circuit in Figure 3 works well for the summing
amplifier connection, it does have limitations in other applications. It could, for example, be used for the voltage follower configuration by connecting the base of the PNP to the
non-inverting input. However, this would reduce the input
;The 709 and the LM101.
til the operational amplifier usea a Darlington input stage, however, the drift
compensation will not be nearly as good.
2
It is worthwhile noting here that these expressions make no
assumptions about the current gain of the transistors. It is
shown in References 5 and 6 that the emitter-base voltage
is a function of collector current, not emitter current. Therefore, the balance will not be upset by base current (except
for interaction with the DC source resistance).
The first term in Equation (1) is the offset voltage of the two
transistors for equal collector currents. It can be seen that
this offset voltage is directly proportional to the absolute
temperature-a fact which is substantiated by experiment.4
The second term is the change of offset voltage which arises from operating the transistors at unequal collector currents. For a fixed ratio of collector currents, this is also proportional to absolute temperature. Hence, if the collector
currents are unbalanced in a fixed ratio to give a zero emitter-base voltage differential, the temperature drift will also
be zero.
r---------~t_--V'
R2'
13K
R.
20K
·Select for zero input current on
non·invertlng input
··Select for zero input current on
V·
inverting input
R3
2M
R4"
Experiment indicates that this is indeed true. Thermal drifts
less than 100 P.V over the - 55'C to + 125'C temperature
range have been realized consistently. In order to obtain
these low drifts, however, it is almost necessary to use a
monolithic transistor pair, since a 0.05~C temperature differential will give a 100 p.V drift. With a monolithic pair, the
physical proximity of the devices as well as the high thermal
conductivity of silicon holds this differential to an absolute
minimum.
For low drift, the transistors must operate from a low
enough source resistance that the voltage drop across the
source due to base current (or base current differential if
both bases see the same resistance) is insignificant. Furthermore, the transistors must be operated at a low enough
collector current that the emitter-contact and base-spreading resistances are negligible, since Equatibn (1) assumes
that they are zero.
A complete amplifier using this, principle is shown in Figure
8. A monolithic transistor pair is used as a preamplifier for a
conventional operational amplifier. A null potentiometer,
which is set for zero output for zero input, unbalances the
collector load resistors of the transistor pair such that the
collector currents are unbalanced for zero offset. This gives
minimum drift. An interesting feature of the circuit is that the
performance is relatively unaffected by supply voltage variations: a 1V change in either supply causes an offset voltage
change of about lOp. V. This happens because neither term
in Equation (1) is affected by the magnitude of the collector
currents.
2M
V·
OUTPUT
INPUTS
TLlH/6925-6
Figure 6. Bias-current compensation for differential In-
puts
offset voltage compensation
The highly predictable behavior of the emitter-base voltage
of transistors has suggested a unique drift compensation
method; it is shown in Reference 3 that the offset voltage
drift of a differential transistor pair can be reduced by about
an order of magnitude by unbalancing the collector currents
such that the initial offset voltage is zero. The basis for this
comes from the equation for the emitter-base voltage differential of two transistors operating at the same temperature:
,
kT
IS2 kT
IC2
loge - - - loge (1)
IS1
q
IC1
q
where k is Boltzmann's constant, T is the absolute temperature, q is the charge of an electron, IS is a constant which
depends only on how the transistor is made and Ic is the
collector current. This equation is derived in Reference 2.
~VBE = -
Cl
'OOpF
Rl
11M
TLlH/6925-7
Figure 7. Test Circuits for selecting bias-compensation resistors
3
CO)
Z•
AI
10K
III
II(
+15V
R5
10K
R4
75K
III
R3
75K
, III
Rl
>-..-- OUTPUT
Ion
III
01
Cl
Q2
30pF
THERMOCOUPLE
R2
75K
-15V,
TLlH/6925-8
Figure 8. Example of a DC amplifier using the drlft-compensatlon technique
In order to get low drift. it is necessary that the gain of the
preamplifier be high enough so that the drift of the opera·
tional amplifier does not degrade performance. The gain
can' be determined frorTi the expresSion for the transconductance of the input transistors:
'
..!!9... =
aveE
qle
kT
With the circuit shown in FJgure 8. Equation (8) gives a 25
p.V input·referred drift for every 10 mV of offset voltage drift
or for every 100 nA of offset current drift. It is obvious from
this that the offset current drift is most important if an opera·
tional amplifier with bipolar input transistors is used.
Another important consideration is the matching of the col·
lector load resistors on the preamplifier stage. A 0.1·percent
imbalance in the load resistors due to thermal mismatches
or any other cause will produce a 25 p.V shift in offset. This
includes the balancing potentiometer which can introduce
an error that will, depend on how far it is set off midpoint if it
has a different temperature coefficiel)t than the resistors.
The most obvious use of this type of low drift amplifier is
with thermocouples. magnetometers. current shunts. wire
strain gauges or similar signal sources where very low drift
is required and the source resistance is low enough that the
bias currents do not cause a problem. The 0.5 to 1 p.V/oC
drift· realized with this relatively simple amplifier over a
- 55°C to + 125°C temperature range compares favorably
with the drift figures achieved with chopper amplifiers: 0.4
p.V/oC for mechanical choppers. 0.5 lJ.V/oC with photoelec·
tric choppers over a O"C to 55°C temperature range and 2
p.V,oC with field-effect·transistor choppers over a - 55°C to
+ 125°C temperature range. In order to give some apprecia·
tlon of the level of performance. it is interesting to note that
no substantial improvement in performance would be real·
ized by operating the amplifier ,in a temperature·controlled
oven. Any improvement would be masked by various ther·
mo-electric effects not directly associated with the amplifier
unless extreme care were taken in the choice of input lead
(2)
The voltage gain is
(3)
(4)
where RL is the average value of the two collector load
resistors on the Input stage and Ie is the average of the two
collector currents.
Substituting Equation (2). this becomes
Av = qlCRL
kT
(5)
qVRL
kT
(6)
=
The input referred drift is then
'v
.. IN =
I1Vos
+ RL I1los
(7)
Av
where 11Vos is the offset voltage drive of the operational
amplifier and I110s is its offset current drift.
Using Equation (7).
'
I1V
- kT (I1 Vos + RLI1 10S)
qVRL
'0rffIs of 0.05 p.v/'C over a 0-50'C temperature range ware reported in
Rafarence 3 using matched discrete transistors in one can.
(8)
IN -
4
r-----------------------------------------------------------,~
references
material, the method of making connections and the balancing of thermal paths. These factors are, in fact, important
when making oven tests to verify the drift of the amplifier
since thermoelectric effects can easily produce drift voltages larger than those of the amplifier if they are not properly handled.
1. R. J. Widlar, "A Unique Circuit Design for a High Performance Operational Amplifier Especially Suited to Monolithic Construction," Proc. of NEG, Vol. XXI, pp. 85-89, October, 1965.
2. R. J. Widlar, "Some Circuit Design Techniques for Linear
Integrated Circuits," IEEE Trans. on Circuit Theory, Vol.
XII, pp. 586-590, December, 1965.
summary
A number of compensation circuits designed to increase the
DC resolution of monolithic operational amplifiers have
been presented. Both current compensation techniques for
high impedance levels as well as methods of achieving
chopper-stabilized drift performance at low impedance levels have been covered.
Fairly-simple current compensation which requires that the
impedance levels be fixed have been described along with
compensation which is effective in cases where the source
impedance is not well defined. This latter category includes
long-interval
integrators,
sample-and-hold
circuits,
switched-gain amplifiers or voltage followers which operate
from an unknown source. The application of these schemes
is generally limited to integrated amplifiers since modular
amplifiers almost always incorporate current compensation.
The drift-reduction techniques provide stabilities better than
0.5 p'vrc for low impedance sources, such as thermocouples, current shunts or strain· gauges. With a properly designed circuit, compensation depends only on a single room
temperature adjustment, so excellent performance can be
obtained from a fairfy-simple amplifier.
3. A. H. Hoffait and R. D. Thorton, "Limitations of Transistor
DC Amplifiers," IEEE Proc., Vol. 52, pp. 179-184, February, 1964.
4. A. Tuszynski, "Correlation Between the Base-Emitter
Voltage and Its Temperature Coefficient," Solid State Design, pp. 32-35, July, 1962.
5. C. T. Sah, "Effect of Surface Recombination and Channel
on P-N Junction and Transistor Characteristics," IRE
Trans. on Electron Devices, Vol. ED-9, pp. 94-108, January, 1962.
6. J. E. Iwersen, A. R. Bray, and J. J. Kleimack, "Low-Current Alpha in Silicon Transistors," IRE Trans. on Electron
Devices, Vol. ED-9, pp. 474-478, November, 1962.
5
f
~~--~~------~----~------------~----------------~
~ lVIonolithic, Op Amp~The
National Semiconductor
Application Note 4
Universal Linear
Component
Robert J. Widlar
Apartado Postal 541
Pl!~rto Vallart8.,,Jalisco
Mexico
',I
:.;;
',:'
R1'
l&OK ,
Introduction
Operational amplifiers are undoubtedly the easiest and best
way of performing a wide range of linear functions from simple amplification to complex analog computation. The cost
of monolithic amplifiers is now less than $2.00,in laFge
quantities, which makes it attractive to" design them into circuits where they would not 9therwise !le' considered. ·Yet
low cost is not the only attraction of monolithic amplifiers.
Since all components are simultaneously fabricated on one
chip, much higher circuit complexities than can be used with
discrete amplifiers are economical. This can be used to give
improved performance. Further, there are no insurmountable technical difficulties to temperature stabilizing the amplifier chip, giving chopper-stabilized performance with little
added cost.
~'.:.6_. .~_ E~UT'
Cl' .
"\
.
O,Ol"JI,",'
,"
,
R3
160K,
R2
910K
'Chosen for oscillation at 100 Hz.
Operational amplifiers are designed for high gain, low offset
voltage and low input current. As a result, dc biasing is considerably simplified in most applications; and they can be
used with fairly simple design rules because many potential
error terms can be neglected. This article will give examples
demonstrating the range of usefulness of operational amplifiers in linear circuit deSign. The examples are certainly not
all-inclusive, and it is hoped that they will stimulate even
more ideas from others. A few practical hints on preventing
oscillations in operational amplifiers will also be given since
this is probably the, largest single problem that many engineers have with these devices.
TL/HI73S7-1
Figure 1. Free-running rnultlvlbrator
Another advantage of the circuit is that it will always self
start and cannot hang up since there is more dc negative
feedback than positive feedback. This can be a problem
with many "textbook" multivibrators.
Since the operational amplifier is used open loop, the usual
frequency compensation components are not required
since they will only slow it down. But even without the 30 pF
capacitor, the LM101 does have speed limitations which restrict the use of this circuit to frequencies below about 2
kHz.
The large input voltage range of the LM101 (both differential
and single ended) permits large voltage swings on the input
so that several time constants of the timing capacitor, C1,
can be used. With most other amplifiers, R2 must be reduced to keep from exceeding these ratings, which requires
that C1 be increased. Nonetheless, even when large values
are needed for C1, smaller polarized capacitors may be
used by returning them to the positive supply voltage instead of ground.
Although the deSigns presented use the LM101 operational
amplifier and the LM102 voltage follower produced by National Semiconductor, most are generally applicable to all
monolithic devices if the manufacturer's recommended frequency compensation is used and differences in maximum
ratings are taken into account. A complete description of
the LM101 is given elsewhere;l but, briefly, it differs from
most other monolithic amplifiers, such as the LM709,2 in
that it has a ± 30V differential input voltage range, a + 15V,
-12V common mode range with ± 15V supplies and it can
be compensated with a single 30 pF capacitor. The
LM102,3 which is also used here, is designed specifically as
a voltage follower and features a maximum input current of
10 nA and a 10 V/IJ-s slew rate.
levelahlHlng amplifier
Frequently, in the design of linear equipment, it is necessary
to take a voltage which is referi'ed to some dc level and
produce an amplified output which is referred to ground.
The most straight-forward way of doing this is to use a differential amplifier similar to that shown in Figure 2s. This
circuit, however, has the disadvantages that the signal
source is loaded by current from the Input divider, R3 and
R4, and that the feedback reSistors must be very well
matched to prevent erroneous outputs from the common
mode input signal.
operational-amplifier oacillator
The free-running multivibrator shown in Figure 1 is an excellent example of an application where one does not normally
consider using an operational amplifier. However, this circuit
operates at low frequencies with relatively small capacitors
because it can use a longer portion of the capaCitor time
constant since the threshold point of the operational amplifier is well determined. In addition, it has a completely-symmetrical output waveform along with a buffered output, although the symmetry can be varied by returning R2 to some
voltage other than ground.
6
r--------------------------------------------------------------------,~
A circuit which does not have these problems is shown in
which makes the output signal directly compatible with DTL
or TIL integrated circuits. An LM103 breakdown diode
clamps the output at OV or 4V in the low or high states,
respectively. This particular diode was chosen because it
has a sherp breakdown and low equivalent capacitance.
When working as a comparator, the amplifier operates open
loop so normally no frequency compensation is needed.
Nonetheless, the stray capacitance between Pins 5 and 6 of
the amplifier should be minimized to prevent low level oscillations when the comparator is in the active region. If this
becomes a problem a 3 pF capacitor on the normal compensation terminals will eliminate it.
FtglJfS 2b. Here, an FET transistor on the output of the operational amptifl9r produces a voltage drop across the feedback resistor, R1, which is equal to the input voltage. The
voltage across R2 will then be equal to the input voltage
multiplied by the retio, R2/R1; and the common mode rejection will be as good as the basic rejection of the amplifier,
independent of the resistor tolerances. This voltage is buffered by an LM102 voltage follower to give a low impedance
output.
An advantage of the LM101 in this circuit is that it will work
with input voltages up to its positive supply voltages as long
as the supplies are less than ± 15V.
FtglJfS 3b shows the connection of the LM101 as a comparator and lamp driver. 01 switches the lamp, with R2 limiting
the current surge resulting from tuming on a cold lamp. R1
determines the base drive to 01 while 01 keeps the amplifier from putting excessive reverse bias on the emitter-base
junction of 01 when it turns off.
voltage comparators
The LM101 is well suited to comparator applications for two
reasons: first, it has a large differential input voltage range
and, second, the output is easily clamped to make it compatible with various driver and logic circuits. It is true that it
doesn't have the speed of the LM71 ()4 (10 p.s versus 40 ns,
under equivalent conditions); however, in many linear appli- .
cations speed is not a problem and the lower input currents
along with higher voltage capability of the LM101 is a tremendous benefit.
Two comparator circuits using the LM101 are shown in Figurs 3. The one in FigUfS 3s shows a clamping scheme
more output current awing
Because almost all monolithic amplifiers use class-B output
stages, they have good loaded output voltage swings, delivering ± 10V at 5 rnA with ± 15V supplies. Demanding much
more current from the integrated circuit would require, for
one, that the output transistors be made considerably larg-
y+
I .i{.~----~~:~D~~------~
D.I%
INPUT
>--.--
R3
IK
D.I%
OUTPUT
CI
ID pF
TLlH/7357 -2
a. standard dlfferentlalempllfler
y+
r~
T
~oii6__•
___ OUTPUT
TL/H/7357 -3
b.level-Isolatlon amplifier
Figure 2. Level-shlftlng amplifiers
7
f
•Z r-----------------------------------------------------------------------------~
oC
OUTPUT
INPUT
"TLlHI7357 -4
,YREF
.. •TUH/73~7~
a. comparator for'drlvlng DTL and
TTL Integrated circUits
b. CQmparator and lamp driver, '
,',
;to
FigureS::, Voltage comparator circuits
y+
OUTPUT
"',,
SUCh a circuit is illustrated in F/{Jure5. A matchedFET pair,
connected as source followers, is put in front of an integrat~ operationall\mplifier. The composite circuit hl¥,l,roughly
tliesame gain as the integrat~d circuit by itself IiIlld is compensated for unity gain with a 30 pF capacitor as shown.
Although it works well as a summing amplifier, the circuit
leaves something to be desired in applications requiring
high common mode rejection. This happens both because
resistors are used for current sources and because the
FErs by themself do not have good common mode rejeetion.·'
'
_ - -. .- - - - - - - - - 1 5 V
Cl
30pF
INPUTS
Tl/H17357-8
+
Figura 4. High current output butter
er. In addition, the increased dissipation could give rise to
troublesome thermai gradients on the chip as well as excessive package heating in high-temperature applications. It iI\!,
therefore advisable to use an external buffer when large
output currents are needed.
OUTPUT
Rl'"
120K
A simple way of accomplishing this is shown in Fipure 4. A
pair of complementary transistors are used on the output of
the LM101 to get the increased current swing. Although this
circuit does have a dead zone, it can be neglected at frequencies below 100Hz because of the high gain of the
amplifier. R1 is included to eliminate parasitic oscillations
from the output transistors. In addition, adequate bypassing
should be used on the collectors of the output transistors to
insure that the output signal is not coupled back into the
amplifier. This circuit does not have current limiting, bUt, it
can be added by putting SOO resistors in serie,s with the
collectors of 01 and 02.
'
-15V
TUH/7357-7
Figura 5. FET operational amplifier
atorage circuits
A sample-and-hold circuit which combines the low input current ,of FErs with, the low ofts" voltage of monolithic amplifiers is shown in Fl{JUfe 6. The circuit is a unity gain amplifier
employing an operational amplifier and an FET source follOWer. In operation, when the sample switch, 02, is turned
, on, it closes the feedbaCk loop to make the output equal to
the input, diflering only by the offset voltage of the LM101.
When the switch is opened, the charge stored on C2 holds
the output at a !evel equal to the last vaiue of the input
voltage.
an tel amplifier
For ambient temperatures less than about 70"C, juncti()n
field effect transistors can give exceptionally low input currents when they are used on the input stage of an operational amplifier. However, monolithic FET amplifiers are not
now available since it is no simple matter to diffuse high
quaiity FET's on the same chip as the amplifier. Nonetheless, it is' possible to make a good FET amplifier using a
discrete FET pair in conjunction with a monolithic circuit.
Some care must be taken in the selection of the holding
capaCitor. Certain types, including paper and mylar, exhibit a
"polariZatIOn phenomenon which causes the sampled volt-
8
Dl
2N3456
O U T P U T - - 4 t - - - - - - - _ t - - - - - -....
INPUT
v+
---..o:t
'Polycarbonate-dielectric capacitor
Cl
30pF
TL/H17357 -8
Figure 6. Low drift sample and hold
age to drop off by about 50 mV, and then stabilize, when the
capacitor is exercised over a 5V range during the sample
interval. This drop off has a time constant in the order of
seconds. The effect, however, can be minimized by using
capacitors with teflon, polyethylene, glass or polycarbonate
dielectrics.
Further, gain can also be provided by feeding back to the
inverting input of the LM101 through a resistive divider instead of directly.
The peak detector in Figure 7 is similar in many respects to
the sample-and-hold circuit. A diode is used in place of the
sampling switch. Connected as shown, it will conduct whenever the input is greater than the output, so the output will
be equal to the peak value of the input voltage. In this case,
an LM102 is used as a buffer for the storage capaCitor,
giving low drift along with a low output resistance.
As with the sample and hold, the differential input voltage
range of the LM101 permits differences between the input
and output voltages when the circuit is holding.
Although this circuit does not have a particularly low output
resistance, fixed loads do not upset the accuracy since the
loading is automatically compensated for during the sample
interval. However, if the load is expected to change after
sampling, a buffer such as the LM102 must be added be·
tween the FET and the output.
A second pole is introduced into the loop response of the
amplifier by the switch resistance and the holding capacitor,
C2. This can cause problems with overshoot or oscillation if
it is not compensated for by adding a resistor, R1, in series
with the LM101 compensation capaCitor such that the
breakpoint of the R1C1 combination is roughly equal to that
of the switch and the holding capacitor.
non·llnear amplifiers
When a non-linear transfer function is needed from an operational amplifier, many methods of obtaining it, present
themself. However, they usually require diodes and are
therefore difficult to temperature compensate for accurate
breakpoints. One way of getting around this is to make the
output swing so large that the diode threshold is negligible
by comparison, but this is not always practical.
It is possible to use an MOS transistor for 01 without worrying about the threshold stability. The threshold voltage is
balanced out during every sample interval so only the shortterm threshold stability is important. When MOS transistors
are used along with mechanical switches, drift rates less
than 10 mV/min can be realized.
Additional features of the circuit are that the amplifier acts
as a buffer so that the circuit does not load the input Signal.
A method of producing very sharp, temperature-stable
breakpoints in the transfer function of an operational amplifier is shown in FlfJure 8. For small input signals, the gain is
determined by R1 and R2. Both 02 and 03 are conducting
to some degree, but they do not affect the gain because
their current gain is high and they do not feed any appreciable current back into the summing mode. When the output
voltage rises to 2V (determined by R3, R4 and V-), 03
draws enough current to saturate, connecting R4 in parallel
with R2. This cuts the gain in half. Similarly, when the output
voltage rises to 4V, 02 will saturate, again halving the gain.
OUTPUT --4~.:.c~
Temperature ,compensation is achieved in this circuit by in·
cluding 01 and 04. Q4 compensates the emitter-base voltage of 02 and 03 to keep the voltage across the feedback
resistors, R4 and R6, very nearly equal to the output voltage
while 01 compensates for the emitter base voltage of these
transistors as they go into saturation, making the voltage
across R3 and R5 equal to the negative supply voltage. A
detrimental effect of 04 is that it causes ,the output resistance of the amplifier to increase at high output levels. It may
therefore be necessary to use an output buffer if the circuit
must drive an appreciable load.
Dl
FD300
lNPUT-----=I
servo preamplifier
In certain servo systems, it is desirable to get the rate signal
required for loop stability from some sort of electrical, lead
network. This can, for example, be accomplished with reactive elements in tlie feedback network of the servo preamplifier.
Cl
30pF
TL/H/7357 -9
Figure 7. Positive peak detector with buffered output
9
.-•
Z
R5
187.5K
--...._-OUTPUT
C2
30pF
TlIH/7357-11
Figure 9. Saturatlrlg servo preamplifier with rate feed.
.
back
10
_ - - - -. .---15V
R14
10K
R13
10K
R12
10
Rll
10K
04
lMl03
2.4V
R3
lK
_---'02'----..
~--. .- - - . . r 0 3 · - - - -
RS
R7
lK
lK
03
02
lN457
lN457
'tLM394
TLlH/7357-12
Figure 10. Analog multiplier/divider
allel with the output of the other two log convertors. Therefore, the emitter-base of 04 will see the log of E3 subtracted
from the sum of the logs of E1 and E2. Since the collector
current of a transistor varies as the exponent of the emitter-.
base voltage, the collector current of Q4 will be proportional
to the product of E1 and E2 divided by E3. This current is
fed to the summing amplifier, A4, giving the desired output
This circuit can give 1-percent accuracy for input voltages
from 500 mV to 50V. To get this precision at lower input
voltages, the offset of the amplifiers handling them must be
individually balanced out. The zener diode, D4, increases
the the collector-base voltage across the logging transistors
to improve high current operation. It is not needed, and is in
fact undesirable, when these transistors are running at currents less than 0.3 mAo At currents above 0.3 mA, the lead
resistances of the transistors can become important (0.250
is 1-percent at 1 mAl so the transistors should be installed
with short leads and no sockets.
between cans appear as inaccuracies in scale factor (0.3percentl"C) rather than a balance error (8-percent/·C). R12
is a balance potentiometer which nulls out the offset voltages of all the logging transistors. It is adjusted by setting all
input voltages equal to 2V and adjusting for a 2V output
voltage.
The logging transistors provide a gain which is dependent
on their operating level, which complicates frequency compensation. Resistors (R3, RS and R7) are put in the amplifier
output to limit the maximum loop gain, and the compensation capacitor is chosen to correspond with this gain. As a
. result, the amplifiers are not especially designed for speed,
but techniques for optimizing this parameter are given in
reference S.
Finally, clamp diodes D1 through D3, prevent exceeding the
maximum reverse emitter-base voltage of the logging transistors with negative inputs.
root extractor'
An important feature of this circuit is that its operation is
independent of temperature because the scale factor
change in the log converter with temperature is compensated by an equal change in the scale factor of the antilog
generator. It is only required that 01, 02, 03 and Q4 be at
the same temperature. Dual transistors should be used and
arranged as shown in the figure so that thermal mismatches
Taking the root of a number using log converters is a fairly
simple matter. All that is needed is to take the log of a
voltage, divide it by, say Va for the square root, and then
'The "extraction" used here doubtless has origin In !he dental operation
most of us would feer less !hen hevlng to find even a square root without
tables or other aids.
11
AN-4
+15V
•
R8
150K
'~..
Rl
10K
INPUT
'"N'.
• -I
.....
RIO
R7
20K
.-____"'.. Ql*_""_----
10K
'='
R4
20K
~u.
."
..
-..-
OUTPUT
C2
300 pF
TUHI7357-13
'tLM3114
Figure 11. Root extractor
r-----------------------------------------------------------'.
f
RZ
E'N
...
CD
Rl
I
Z
C
...'"
...
EOUT
CO
CO
R3
10
100
lK
10K
lOOK
1M
10M
FREQUENCY - Hz
TlIH/7357-14
TlIH17357-15
a. measuring loop gain
b. typical response
Figure 12. illustrating loop gain
take the antilog. A circuit which accomplishes this is shown
in Figure 11. Al and 01 form the log converter for the input
signal. This feeds 02 which produces a level shift to give
zero voltage into the R4, R5 divider for a 1V input. This
divider reduces the log voltage by the ratiO for the root desired and drives the buffer amplifier, A2. A2 has a second
level shifting diode, 03, its feedback network which gives
the output voltage needed to get a 1V output from the antilog generator, consisting of A3 and 04, with a unity input.
The offset voltages of the transistors are nulled out by imbalancing R6 and R6 to give 1V output for 1V input, since
any root of one is one.
and capacitive loading, or the circuit can even oscillate with
worst-case units.
The basic requirement for frequency compensating a feedback amplifier is to keep the frequency roll-off of the loop
gain from exceeding 12 dB/octave when it goes through
unity gain. Figure 12a shows what is meant by loop gain.
The feedback loop is broken at the output, and the input
sources are replaced by their equivalent impedance. Then
the response is measured such that the feedback network
is included.
Figure 12b gives typical responses for both uncompensated
and compensated amplifiers. An uncompensated amplifier
generally rolls off at 6 dBloctave, then 12 dB/octave and
even 18 dB/ octave as various frequency-limiting effects
within the amplifier come into play. If a loop with this kind of
response were closed, it would oscillate. Frequency compensation causes the gain to roll off at a uniform 6 dBloctave right down through unity gain. This allows some margin
for excess rolloff in the external circuitry.
02 and 03 are connected as diodes in order to simplify the
cirCUitry. This doesn't introduce problems because both operate over a very limited current range, and it is really only
required that they match. R7 Is a gain-compensating resistor which keeps the currents in 02 and 03 equal with
changes in signal level.
As with the multiplier/divider, the circuit is insensitive to
temperature as long as all the transistors are at the same
temperature. Using transistor pairs and matching them as
shown minimizes the effects of gradients.
Some of the external influences which can affect the stability of an operational amplifier are shown in Figure 13. One is
the load capacitance which can come from wiring, cables or
an actual capacitor on the output. This capaCitance works
against the output impedance of the amplifier to attenuate
high frequencies. If this added rolloff occurs before the loop
gain goes through zero, it can cause instability. It should be
remembered that this single rolloff point can give more than
6 dBloctave rolloff since the output impedance of the amplifier can be increasing with frequency.
The circuit has 1-percent accuracy for input voltages between 0.5 and 50V. For lower input voltages, Al and A3
must have their offsets balanced out individually.
frequency compensation hints
The ease of designing with operational amplifiers sometimes obscures some of the rules which must be followed
with any feedback amplifier to keep it from oscillating. In
gen.eral, these problems stem from stray capaCitance, excessive capacitive loading, inadequate supply bypassing or
improper frequency compensation.
R3
r-----~~-----,---<~N
Rl
In frequency compensating an operational amplifier, it is
best to follow the manufacturer's recommendations. However, if operating speed and frequency response is not a
consideration, a greater stability margin can usually be 0btained by increasing the size of the compensation capacitors. For example, replacing the 30 pF compensation capaCitor on the LM101 with a 300 pF capacitor will make it
ten times less susceptible to oscillation problems in the unity-gain connection. Similarly, on the LM709, using 0.05 p.F,
1.5 kO, 2000 pF and 510 components instead of 5000 pF,
1.5 kO, 200 pF and 510 will give 20 dB more stability margin. Capacitor values less than those specified by the manufacturer for a particular gain connection should not be used
since they will make the amplifier more sensitive to strays
>-"-~EoUT
R2
-
TlIH/7357-16
Figure 13. External capacitances that affect stability
13
A second source of excess rolloff is stray capacitance on
the inverting input. This becomes extremely important with
large feedback resistors as might be used with an FET-input
amplifier. A relatively simple method of compensating for
this stray capacitance is shown in Ftgure 14: a lead capacitor, Cl, pUt across the feedback resistor. Ideally, the ratio of
the stray capacitance to thEilead capacitor should be equal
to the closed-loop gain of the ·amplifier. However, the lead
capaCitor can be made larger as long as the amplifier is
compensated for unity gain. The only disadvantage of doing
this is that it will reduce the bandwidth of the amplifier. Oscillations can also result if there is a large resistance on the
non-inverting input of the amplifier. The differential input impedance of the amplifier falls off at high frequencies (especially with bipolar input tranSistors) so this resistor can produce troublesome rolloff if it is much greater than 10K, with
most amplifiers. This is easily corrected by bypassing the
resistor to ground.
When the capacitive load on an integratl!d amplifier is much
greater than 100 pF, some consideration must be given to
its effect on stability. Even though the amplifier don not
oscillate readily, there may be a worst-case set of conditions under which it will. However, the amplifier can be stabilized for any value of capacitive loading using the circuit
cause instability. To use this circuit, the amplifier must be
compensated for unity gain, regardless of the closed loop
dc gain:Tfie value ofCl is not tOo important, but at a minimum its capacitive reactance should be one-tenth the resistance of R2',at the unity-gain crossover frequency of the
amplHier.
."
.
When an ope~ational amplifier is qperated open loop, it
might appear at first glilnce that it needs no frequency compensation. However, this is not always the case .beCli.use
the external compensation is sometimes required to stabilize internal feedback loops.
The LM10l will not oscillate when operated open loop, although there may be problems if the capacitance between
the balance terminal on pin 5 and the output is not held to
an absolute minimum. Feedback between these two points
is regenerative if it is not balanced out with a larger feedback capacitance acrosS the Compansatlon terminals. Usuaily a 3 pFcompensation capacitor will completely eliminate
the p~oblem. The LM709 will,osciuate when operated open
loop unless a 10 pF capacitor is connected across the input
compensation terminals and a :3 pF capacitor .is connected
on the output compensation terminals.
Problems encountered with supply bypassing are insidious
in that they will hardly ever show up· in a Nyquist plot. This
problem has not really been thoroughly investigated, probably ,because. one sure ·cure is known: bypass the positive
and negative supply terminals of each amplifier to ground
with at least a 0.01 'p.F capacitor.
For exemple, a LM101 can take over 1 mH inductance in
either supply lead without oscillation. This should not suggest that they should be run without bypass capacitors. .It
has been established that 100 LM101!s on a single printed
circuit board with common supply blJsses will oscillate if the
supplies are not bypassed about every fifth device. This
happens even though the inputs and outputs are completely
isolated.
The LM709, on the other hand, will oscillate under many
load conditions with as .litJie as 18 inches of wire between
the negative supply lead and a bypass capacitor. Therefore,
It Is almost essential to have a set of bypass capacitors for
every device.
Operational amplifiers are specified for power supply rejection at frequencies less than the first break frequency of the.
open loop gain. At higher frequencies, the rejection can be
reduced depending on how the amplifier Is frequency Compensated. For'both the LM101 and tM709,the rejection of
high ffeqUency signals on the positive' supply is excellent.
HOwever; the situation is different for the negative supplies.
These two amplifiers· have cOmpensation: capacitors from
the output down to a signal point which' is referred to the
negative supply, causing the high frequency rejection for the
negative sllPply to be much reduced. It is therefore Important to have sufficient. bypassing on the negative supply to
remove transients if they can cause ,trouble appearing on
the output. One fairly large (22p.F) tantalum capacitor on
the negative power lead for each printed-circuit card Is usually enough .to solve. potential problems.
When high-current buffers
used in conjunction with operatienal amplHiers, supply'bypassing and decoupling are
even more irnporblnt since they can feed a considerable
amount· of signal back intO the supply lines. For reference,
bypass capaCitOrs of at least 0.1 p.F are required for a
50 mA buffer. "
.
CI
A2
ft1
>-.~","-EoUT
. TUHI73S'7-17
Figure 14. Compensating strey Input capecltence.
shown in FIfJUTe 15. The capacitiVe load is isolated from thEi
output of the amplifier with R4 Which has a Value of 50n to
lOOn for both theLM10l and the LM709. At high frequencieS. the feedback path is through the lead Capacitor, Ct, so
that the lag produced by the load capaCitance does not
CI'
ft2
are
TLlH/7357 -18
Figure 15. Compensating tor verY larGe cap8cltlveloada
to
When emitte(followers are used drive long cables, additional preCautions are required. 'An emitter follower by it14
l>
self-which is not contained in a feedback loop-will frequently oscillate when connected to a long length of cable.
When an emitter follower is connected to the output of an
operational amplifier, it can produce oscillations that will
persist no matter how the loop gain is compensated. An
analysis of why this happens is not very enlightening, so
suffice it to say that these oscillations can usually be eliminated by putting a ferrite beadB between the emitter follower
and the cable.
monolithic amplifiers, it is almost foolish to design dc amplifiers without integrated circuits. Moreover, the price makes it
practical to take advantage of operational-amplifier performance in a variety of circuits where they are not normally
used.
Many of the potential oscillation problems that can be encountered in both discrete and integrated operational amplifiers were described, and some conservative solutions to
these problems were presented. The areas discussed Included stray capaCitance, capacitive loading and supply bypaSSing. Finally, a simplified method of quickly testing the
stability of amplifier circuits over a wide range of operating
conditions was suggested.
Considering the loop gain of an amplifier is a valuable tool in
understanding the influence of various factors on the stability of feedback amplifiers. But it is not too helpful in determining if the amplifier is indeed stable. The reason is that
most problems in a well-designed system are caused by
secondary effects-which occur only under certain conditions of output voltage, load current, capacitive loading,
temperature, etc. Making frequency-phase plots under all
these conditions would require unreasonable amounts of
time, so it is invariably not done.
tThe frequancy-ilomain characteristics con be determined from the impulse
response of a network and this ie dlrectty relatable to the step response
through the convolution Integral.
reterences
1. R. J. Widlar, "Monolithic Op Amp with Simplified Frequency Compensation", EEE, Vol. 15, No.7, pp. 58-63, July,
1967.
A better check on stability is the small-signal transient response. It can be shown mathematically that the transient
response of a network has a one-for-one correspondence
with the frequency domain response. t The adVantage of
transient response tests is that they are displayed instantaneously on an OSCillOSCOpe, so it is reasonable to test a
circuit under a wide range of conditions.
2. R. J. Widlar, "A Unique Circuit Design for a High Performance Operational Amplifier Especially Suited to Monolithic Construction", Proc. of NEG, Vol. XXI, pp. 85-89, October, 1965.
3. R. J. Widlar, "A Fast Integrated Voltage Follower with
Low Input Current", National Semiconductor AN-5,
March, 1968.
Exact methods of analysis using transient response will not
be presented here. This is not because these methods are
difficult, although they are. Instead, it is because it is very
easy to determine which conditions are unfavorable from
the overshoot and ringing on the step response. The stability margin can be determined much more easily by how
much greater the aggravating conditions can be made before the circuit oscillates than by analysis of the response
under given conditions. A little practice with this technique
can quickly yield much better results than classical methods
even for the inexperienced engineer.
4. R. J. Widlar, "The Operation and Use of a Fast Integrated
Circuit Comparator", Fairchild Semiconductor APP-116,
February, 1966.
5. "Handbook of Operational Amplifier Applications", BurrBrown Research Corporation, Tucson, Arizona.
6. J. F. Gibbons and H. S. Horn, "A Circuit with Logarithmic
Transfer Response over Nine Decades", IEEE Trans. on
Circuit Theory, Vol. CT-11, pp. 378-384, September,
1964.
7. R. J. Widlar and J. N. Giles, "Avoid Over-Integration",
EIBCtronic Design, Vol. 14, No.3, pp. 56-62, Feb. 1. 1966.
summary
A number of circuits using operational amplifiers have been
proposed to show their versatility in circuit design. These
have ranged from low frequency oscillators through circuits
for complex analog computation. Because of the low cost of
8. Leslie Solomon, "Ferrite Beads", Electronics World, pp.
42-43, October, 1966.
15
z
•
~
Ij
National Semiconductor' ,
Application:Note13
Application ,of the LHOOO2,
Current Amplifier
" tjt,·,
"
","
INTRODUCTION
'.,'
The LH0002 Current Amplifier integrated building block provldes a wide band unity gain amplifier capable of providing
peak currents of up to ± 200 mA into a 500 load.
The circuit uses thick film technology to integrate 2"NPN
and 2 PNP complementary matched silicon transistors With
4 cermet resistors on a single aluinina ceramic substrate. A
circuit schematic is shown in Figure 1. The negative thermal
feedback provided by the close proximity 9f the components on a single substrate eliminates any thermal runaway
problem that could occur if this circuit were constructed tISing discrete components.
"',
"
"v+
v+
'1
,
2
"
4~R~
5kSl
"
,~
'" ....-3
,I'll
,03
'
"
~:
A typical circuit features a dynamic input impedance of
200 kO. an output impedanca of 60. DC to 50 MHz bandwidth. and an output voltage swing that approaches supply
voltage. A complete list of the guaranteed and Wlical values
for the ,electrical characteristics under the stated qonditions
is given in Table I. These features make the LH0002 ideal
for integration with an operational amplifier il'1side a closed
loop configuration to increase its current output. The symmetrical class AB output portion of the circuit also provides
a constant low output impedance for both the' positive and
negative slopes of output pulses.
INPUT
....-4 OUTPUT
.~
R4
"lSl
L...f..02,
....
~5
04
.....
~Rl
."un
"
~
CIRCUIT OPERATION
,
The majority 01 circuit applications will use symmetrical power supplies. with equal positive voltage being IIPplied to pins
1 and 2. and equal negative voltage applied ta pins 6 and 7.
i'
.,
7
&
v-
vTUK173is-1
"
FIGURE 1: 'ClrculfSch.matlc
TABLE I. Electrical characteristics, specification applies for TA = 25"C
with + 12.0V on pins 1 and 2; -12.0V on pins 6 and 7.
Parameters
Voltage Gain
.,
Conditions
Rs = .19 kO. RL = 1.0 kO
VIN = 3.0 Vpp• f = 1.0 kHz
TA = 55·Cta 125·C
Min
'.
Typ
Max
Units
:
0.95
0.97
,
"
Input Impedance
RS = 200 kO. Y,N = 1.0 Vrms•
f= 1.0kHz.RL= 1.0kO
180
200
-
kO
Output Impedance
VIN = 1.0Vrrns.f = 1.0 kHz
RL = 500. Rs = 10 kO
-
6
10
0
Output Voltage Swing
RL = 1.0 kO. 1 = 1.0 kHz
±10
±11
-
V
DC Input Offset Voltage
Rs = 10 kO. RL = 1.0 kO
TA = -55·Cta 125·C
-
±40
±loo
mV
DC Input Offset Current
Rs = 10kO. RL = 1.0kO
TA = -55·Cto 125°C
-
±6.0
±10
/LA
Harmonic Distortion
VIN = 5.0Vrms• f = 1.0 kHz
-
0.1
Bandwidth
VIN = 1.0 Vrms. RL = 500
RS = 1000
30
Positive Supply Current
RS = 10 kO. RL = 1 kO
Negative Supply Current
Rs = 10 kO. RL = 1 kO
-
16
50
-
MHz
+6.0
+10.0
mA
-6.0
-10.0
mA
%
~
Z
The reason that pin 2 and pin 6 are not connected internally
to pin 1 and pin 7, respectively, is to increase the versatility
of circuit operation by allowing a decreased voltage to be
applied to pins 2 and 6 to minimize the power dissipation in
03 and 04. The larger voltage applied to the input stage
also provides increased current drive as required to the output stage.
The operation of the circuit can be understood by considering that the input pin 8 is at VIN. The emitter of 01 will be
approximately O.SV more positive than VIN at 25°C, and the
converse is true for 02. This O.SV will provide a forward bias
on 03 to cancel out the 01 base to emitter drop which in
tum would provide VIN at the output if all junctions, resistors,
power supplies, etc., were electrically identical. The greatest
error is introduced because the forward drops in the baseemitter junctions for the NPN and PNP devices are Slightly
different. For example, the VSE of the NPN will be typically
O.SV and the VSE of the PNP will be typically O.64V under
the same conditions of IC = 2.4 rnA at VCE = 12.0Vat
25°C. These are the approximate input stage circuit conditions for 01 and 02 for plus and minus 12V supplies. Fortunately, this error in both input and output offset voltage is
almost always negligible when it is used inside the closed
loop of a high gain operational amplifier.
A plot of input impedance vs frequency is shown in Figure 2.
Inspection of this plot shows that the input impedance can
be closely approximated to that of a simple first order linear
network with a 45° phase lag at O.S MHz and a 90" phase
lag at approximately one decade higher in frequency. This
information is very useful for designers who have to integrate circuits which have large source impedances over a
wide frequency range. The output impedance of the amplifier is very low, SO typically, and in conjunction with a voltage
bandwidth of approximately 50 MHz can be considered to
be insignificant for most applications for this type of device.
_
1'"
ii
I
~
i!!!!!
i
,oo
.._ _ DE ....
_~
....
D
'.-/
D
..,
~
D.2
u
....
1.0
2.0
:!
7
-1&
'HASi -
-I
l./
D.l
&.8 10.0
2D.D
fRE~UENCY
IMHzl
5...
~
....
D
50.0 100
TUK17315-3
FIGURE 3. Frequency Response
APPLICATIONS
Figure 4 shows the LH0002 integrated with the LM10l in a
booster follower configuration. The configuration is stable
without the requirement for any external compensation;
however, it would behoove the designer to be conservative
and bypass both the negative and positive power supplies
with at least a 0.01 p.f capacitor to cancel out any power
supply lead inductance. A 1000 damping resistor, located
right at the input of the LH0002, might also be required between the operational amplifier and the booster amplifier.
The physical layout will determine the requirement for this
type of oscillation suppression. Current limiting can be added by incorporating series resistors from pins 2 and 6 to
their respective power supplies. The exact value would be a
function of power supply voltage and required operating
temperature.
A breadboard of this configuration was assembled to empirically check the increase in offset voltage due to the addition
of the LHOO02. The offset voltage was measured with and
without an LHOOO2 inside the loop with a voltage gain of
100, at-55·C, 25·C and 125"C. The additional offset voltage was less than 0.3% for all three temperature conditions
even though the offset voltage of the LH0002 is much higher than that of the LM101. The high open loop gain of the
LM101 divides out this source of circuit error. The integration of this device also allows higher closed loop circuit gain
without excessive cross-over distortion than would be obtainable with the simple booster amplifier shown in Ftgure 5.
Figure 6 shows the LH0002 being used as a level shifter
with a high pass filter on the input in order to reference the
output to zero quiescent volts. The purpose of the 10 kO
resistor is to provide current bias to the circuit's input transistors to reduce the output offset voltage. Figure 3, Input
Impedance VB Frequency, provides a useful design aid in
order to determine the value of the capacitor for the particular application. The 10 kO resistor, of course, has to be
considered as being in parallel with the circuit's input impedance.
For a pulse input Signal, the output impedance of the circuit
remains low for both the positive and negative portions of
the output pulse. This circuit provides both fast rise and fall
times for pulse Signals, even with capacitive loading. The
LH0002 data sheet shows typical rise and fall times for both
positive and negative pulses into a 500 load.
-'00
"
,.
~
~
-=
I - - -24 ~
JF--
~ 0.2
MAGNITUDE
6
50 ohm•• V, - ±12.OV
...~
1TT
2
FREQUENCY RESPONSE
v.. -l.OV ..... lit. TA=2Ii"C
~
-32
"\
CD
III
/
~
... D.4
I;I"PHASE
........
VOLTAGE GAIN
~u
A plot of the yoltage bandwidth is shown in F/{/Ure 3. Inspection of this plot shows that phase information as well as gain
information was included to assist users of this device. For
example, at 10 MHz, less than an 8· phase lag would be
subtracted from the phase margin of an operational amplifier when it is integrated with this device. The open loop gain
of the operational amplifier would be decreased by less than
10% at 10 MHz and therefore can be considered to be insignificant for most applications.
v.",Wr., I\-e ..... v... ± 12.GV
R.=101( .... TA""zrc
-4G
1.0
~ D.I
.....•
Co)
o
FREQUENCY IMHa)
TL/K17315-2
FIGURE 2. Input Impedance vs Frequency
17
-
~ ~----------------------------------------------------------~----------------~
z•
cc
R2
VS=:l:5VTO:l:15V
Rl
INPUT'J,JIIv-"":'I
OUTPUT
",--oVOUT'
TLlK/7315-S
FIGURE 4. LM101-LHOOO2 Booster Ampllfler Integration
V"
TLlK/731S':&
FIGURE 5. Simple Booster'Ampllfier
pedance level of the pulse, the polarity of the pulses, or,
with the aid of a center·tapped Winding, positive and nega·
tive pulses simultaneously.
The LH0002 can also be used to drive long transmission
lines. FI{}/Jre 8 shows a circuit configuration to match the
output impedance of the amplifier to'the load and coaxial
cable for proper line termination to minimize reflections. A
capacitor can be added to empirically adjust the time response of the 'waveform.,
TL(Kl731S-7
FIGURE 6. Level ShlHer
Figure 7 shows the LH0002 being used to drive a pulse·
tranSformer. The low output offset voltage allows the pulse
transformer to be directly coupled to the amplifier without
using a coupling capacitor to prevent saturation.' The pulse
transformer can be used to change the amplitude and im-
Select capacitor to adiust time response of pulse.
TLlKI731S_9
FIGURE 8. Transmission Une Driver
SUMMARY
The multitude of different applications suggested in this arti·
cle showS the versatility of the LHOOO2. The applications
specially covered were for a differential input-output operational amplifier, booster amplifier, level shifter, driver for a
pulse·transformer, and transmission line driver.
TL/K/7315-8
FIGURE 7. Driver for a Pulse-Transformer
18
National Semiconductor
Application Note 20
An Applications Guide for
OpAmps
INTRODUCTION
The general utility of the operational amplifier is derived
from the fact that it is intended for use in a feedback loop
whose feedback properties determine the feed-forward
characteristics of the amplifier and loop combination. To suit
it for this usage, the ideal operational amplifier would have
infinite input impedance, zero output impedance, infinite
gain and an. open-loop 3 dB point at infinite frequency rolling
off at 6 dB per octave. Unfortunately, the unit cost-In quantity-would also be infinite.
Intensive development of the operational amplifier, particularly in integrated form, has yielded circuits which are quite
good engineering approximations of the ideal for finite cost.
Quantity prices for the best contemporary integrated amplifiers are low compared with transistor prices of five years
ago. The low cost and high quality of these amplifiers allows
the implementation of equipment and systems functions impractical with discrete components. An example is the low
frequency function generator which may use 15 to 20 operational amplifiers in generation, wave shaping, triggering and
phase-locking.
The availability of the low-cost integrated amplifier makes it
mandatory that systems and equipments engineers be familiar with operational amplifier applications. This paper will
present amplifier usages ranging from the simple unity-gain
buffer to relatively complex generator and wave shaping circuits. The general theory of operational amplifiers is not
within the scope of this paper and many excellent references are available in the literature.' ,2,3,4 The approach will
be shaded toward the practical, amplifier parameters will be
discussed as they affect circuit performance, and application restrictions will be outlined.
The applications discussed will be arranged in order of increasing complexity in five categories: simple amplifiers, operational circuits, transducer amplifiers, wave shapers and
generators, and power supplies. The Integrated amplifiers
shown in the figures are for the most part internally compen-
sated so frequency stabilization components are not shown;
however, other amplifiers may be used to achieve greater
operating speed in many circuits as will be shown in the text.
Amplifier parameter definitions are contained in Appendix I.
THE INVERTING AMPLIFIER
The basic operational amplifier circuit is shown in Figuf8 1.
This circuit gives closed-loop gain of R2/R1 when this ratio
is small compared with the amplifier open-loop gain and, as
the name implies, is an inverting circuit. The input impedance is equal to R1. The closed-loop bandwidth is equal to
the unity-gain frequency divided by one plus the closed-loop
gain.
The only cautions to be observed are that R3 should be
chosen to be equal to the parallel combination of R1 and R2
to minimize, the offset voltage error due to bias current and
that there will be an offset voltage at the amplifier output
equal to closed-loop gain times the offset voltage at the
amplifier input.
.".
~'.
.......
-"'
2~
".--
v:
LM107 ~I~-vou.
~+
~~
:io R3
~~
':"
R2
VOUT = Fi1VIN
R3 = RI
II R2
For minimum error due
to input bias current
TLlH/6822-1
FIGURE 1. Inverting AmplHler
Offset voltage at the input of an operational amplifier is
comprised of two components, these components are identified in specifying the amplifier as input offset voltage and
input bias current. The input offset voltage is fixed for a
particular amplifier, however the contribution due to input
19
bias current is dependent on the circuit configuration used.
.:For 'minimum offset voltage at the amplifier. input without
,:9Ircuit.'adjustment the source resistance for both inputs
'., should be equal. In this case the maximum offset voltage
would be the algebraic sum of amplifier offset voltage and
the voltage drop across the source resistance due .to offset
current. Amplifier offset voltage is the predominant error
term for low sourqe resistance~ and offset current causes
the main error for high source. resistances.
In high source resistance applications, offset voltage at the
amplifier output may be adjusted by adjusting the value of
R3 and using the variation in voit8ge drop across it as an
input offset voltage trim.
'
Offset voltage, at the amplifier output is not as important in
AC coupled applications. 'Here the only consideration is that
any offset voltage at the,' output reduces the peak to peak
linear output swirigof the amplifier.
The gain-frequency ch~acteristic of. the amplifier and its
feedback network must be such that Oscillation does not
occur. To meet this condition, the phase shift through amplifier and feedback network niust never exceed 180· for any
frequency where the, gain of the amplifier and its feedback
network is greater than unity. In practical applications, the
phase shift should not approach 180" since this is the situation of conditional stability. Obviously the most critical case
occurs when the attenuation of the feedback network Is
zero.
Amplifiers which are not internally compensated may be
used to achieve increased performance in circuits where
feedback network attenuation is high. As an example, the
LM 101 may be operated at unity gain in the Inverting amplifier circuit with a 11$ pF'compensatlng capacitor, since the
feedback network has an att,enuation of 6 dB, while it requires 30 pF in the non-inverting unity gain connection
where the feedback network has zero attenuation. Since
amplifier slew rate is dependent on compensation, the
LM101 slew rate in the inverting unity gain connection will
be twice that for the non-inverti'ng connection and the inverting gain of ten connection will yield eleven times the
slew rate of t.he non-inverting unity gain connection. The
compensation trade-off for a particular connection is stability versus bandwidth, larger values of compensation capacitor yield greater stability and lower bandwidth and, vice
versa.
The preCeding discussion of offset voltage, bias current and
stability is applicable to most amplifier applications and will
be referenced in later sections. A more complete treatment
is contained in Reference 4.
THE NON-INVERTING AMPLIFIER
Figure 2 sh~~s Ii high' input impedance non-inverting circuit.
This circuit gives a closed-loop gain equal to the ratio of the
sum of R1 and R2 to R1 and a closed~loop 3 dB bandwidth
equal to the amplifier unity-gain frequency divided by the
closed-loop gain.
The primary differences between this connection and the
inverting circuit are that the output is not inverted and that
the input impedance is very high and is equal to the differential input impedance multiplied by loop gain. (Open loop
gain/Closed loop gain.) In DC coupled applications, input
impedance is not as important as input current and its voltage drop across the source resistance.
Applications cautions are the same for this amplifier as for
the inverting amplifier with one exception. The amplifier output will go into saturation if the input is allowed to float. This
may be important if the amplifier must be switched from
source to source. The compensation trade off discussed for
the inverting amplifier Is also valid for this connection.
Y'N----I
>'..... You,
R2YOUT =
R1
~YIN
R1
II R2 = RsoURCE
For minimum error due
'="
to Input bias current,
TL/H/8822-2
FIGURE 2. Non-Inverting Amplifier
THE UNITY-GAIN BUFFER
The unity-gain buffer is shown in Figure 3. The circuit gives
the highest input impedance of any operational amplifier circuit. Input impedance Is equal to the differential input impedance multiplied by the open-loop gain, in paraliElI with common mode input impedance. The gain error of this circuit is
equal to the reciprocal of the amplifier open-loop gain or to
the common mode rejection, whichever is less.
You,
YOUT = YIN
R1
RI
= RSOURCE
For minimum error due
10 Input blas current
TLlH/8822-3
FIGURE 3. Unity Gain Buffer
20
Input impedance is a misleading concept in a DC coupled
unity-gain buffer. Bias current for the amplifier will be supplied by the source resistance and will cause an error at the
amplifier input due to its voltage drop across the source
resistance. Since this is the case, a low bias current amplifier such as the LH1026 should be chosen as a unity-gain
buffer when working from high source resistances. Bias current compensation techniques are discussed in Reference
RI
>,;,8.- VOUT
V
=(RI+R2)~V -~v
OUT
R3 + R4 RI 2 RI '
For RI = R3 and R2 = R4
R3
5.
VOUT
The cautions to be observed in applying this circuit are
three: the amplifier must be compensated for unity gain operation, the output swing of the amplifier may be limited by
the amplifier common mode range, and some amplifiers exhibit a latch-up mode when the amplifier common mode
range is exceeded. The LM107 may be used in this circuit
with none of these problems; or, for faster operation, the
LM102 may be chosen.
v.-"""""
Circuit bandwidth may be calculated in the same manner as
for the inverting amplifier, but input impedance is somewhat
more complicated. Input impedance for the two inputs is not
necessarily equal; inverting input impedance is the same as
for the inverting amplifier of Figure 1 and the non-inverting
input impedance is the sum of R3 and R4. Gain for either
input is the ratio of R1 to R2 for the special case of a differential input single-ended output where R1 = R3 and R2 =
R4. The general expression for gain is given in the figure.
Compensation should be chosen on the basis of amplifier
bandwidth.
Care must be exercised in applying this circuit since input
impedances are not equal for minimum bias current error.
A4
AZ
R3
>6........A5
V,)
FIGURE 5. Difference Amplifier
v,-,.,.iV-t....-Y,iV-.,
AI
= ~ ('12 -
RI
RI II R2 = R3 II R4
TL/H/6822-5
For minimum offset error
due to input bias current
VOUT
V,+ V2
VOUT= -R4 ( - +Va)
RI
R2 R3
R5 = RI II R2 ! R3 UR4
For minimum offsaI error due
to input bias current
DIFFERENTIATOR
The differentiator is shown in Fl{Jure 6 and, as the name
implies, is used to perform the mathematical operation of
differentiation. The form shown is not the practical form, it is
a true differentiator and is extremely susceptible to high frequency noise since AC gain increases at the rate of 6 dB
per octave. In addition, the feedback network of the differentiator, R1C1, is an RC low pass filter which contributes
90" phase shift to the loop and may cause stability problems
even with an amplifier which is compensated for unity gain.
TLlH/6822-4
FIGURE 4. Summing Amplifier
SUMMING AMPLIFIER
The summing amplifier, a special case of the inverting amplifier, Is shown in Figure 4. The circuit gives an inverted
output which is equal to the weighted algebraic sum of all
three inputs. The gain of any input of this circuit is equal to
the ratio of the appropriate input resistor to the feedback
resistor, R4. Amplifier bandwidth may be calculated as in
the inverting amplifier shown in Figure 1 by assuming the
input resistor to be the parallel combination of R1, R2, and
R3. Application cautions are the same as for the inverting
amplifier. If an uncompensated amplifier is used, compensation is calculated on the basis of this bandwidth as is discussed in the section describing the simple inverting amplifier.
The advantage of this circuit is that there is no interaction
between inputs and operations such as summing and
weighted averaging are implemented very easily.
">:,',,--VOUT
d
VOUT = -RICI Cij(VIN)
THE DIFFERENCE AMPLIFIER
The difference amplifier is the complement of the summing
amplifier and allows the subtraction of two voltages or, as a
special case, the cancellation of a signal common to the
two inputs. This circuit is shown in Figure 5 and is useful as
a computational amplifier, in making a differential to singleended conversion or in rejecting a common mode signal.
_
RI = R2
For minimum offset error
due to Input bias current
TLlH/6822-6
FIGURE 6. Dlfferentlator
21
a 'low-pass filter with a frequency response decreasing at
6 dB per octave. An amplitude-frequency plot is shown in
Figuf'9 10;: '
, ,(
..
~:I ~
VIN~
You,
CI
Ie
1
= 2;;A2C1
1
Ih =
Ie
1
2riiiC1 = 2".R2C2
< i), < lunily gain
TlIH/6822-7
FIGURE 7. Practical Dlfferentlator
A practical differentiator is shown in F/{Juf'9 7. Here both the
stability and noise problems are corrected by addition of two
additional components, R1 and C2. R2 a('ld C2 form a 6 dB
per octave high frequency roll-off in the feedbac~ network
and R1 C1 form a 6 dB per octave roll-off network in the
input network for a total high frequency roll-off of 12 cjB per
octave to reduce the effect of high frequency input and amplifier noise. In addition R1C1 and R2C2 form lead networks
in the feedback loop which. if placed balow the ampliiier
unity gain frequency, provide 90" phase lead to compensate
t~e 90" phase lag of R2C1 and prevent loop instability. A
gain frequency plot is shown in Figure 8 for clarity.,
TL/H/6822-IO
FIGURE 10. Integrator Frequency Response
The circuit must be provided with an external method of
establishing initial conditions. This is shown in the figure as
SI. When SI is in position 1. the amplifier is connected in
unity-gain and capacitor C1 is discharged, setting an initial
condition of zero volts. When SI is in position 2. the amplifier is connected as an integrator and its output will change in
accordance with a constant times the time integral of the
input voltage.
The cautions to be observed with this circuit are two: the
amplifier used should generally be stabilized for unity-gain
operation and R2 must equal R1 fpr minimum error due to
bias current:
'
.r---,.~~~~~~
Qr---+---~---r---;
SIMPLE LOW·PASS FILTER
The simple low-pass filter is shown in F/{Juf'9 11. This Circuit
has a 6 dB per octave roll-off after a closed-loop 3 dB point
defined by fc• Gain below this corner frequency is defined, by
the ratio of R3 to R1. The circl,lit may be considered as an
AC integrator at frequencies well above fc; however, the
time domain response is that of a single RC rather than an
integral.
TlIH/6822-8
FIGURE 8. Dlfferentlator Frequenc~ Response
INTEGRATOR
The integrator is shown in Fig(Jf'9 9 and performs the mathematical operation of, integration. This circuit is essentially
. . ------~ 5,111
I
I
I
RI
V,., .....IV\jI\r-.....
VOUT
z
I
I
I
1,
I
A=~
V . - - - 'U
'
L
FIGURE
VOUT
Ie
11.~lmple
Rl
TL/Hi6822-11
Low Paas Filter, ,
R2 should be chosen equal to the parallel combination of
R1 and R3 to minimize errors due to bi~s burren!. The,amplifier should be compensat8d for unity-gain or an internally
compensated amplifier can be used.
= Rl1el tV1Ndt
1
= 2riiiC1
'
1
, Ie = 2iTR3t:l
TL/H/6822-9
Rl - R2
For minlmtlm offset etrOt
due to input bias current
FIGURE 9. Integrator
22
.
'.
41
i..
:
20
-20
'CELL
~'IID
•
""'L
"
III
1011
llDOI
AI
PCI
v-
1_
RELATIVE FREQUENCY
Tl/H/6822-14
TUH/6622-12
FIGURE 14. Amplifier for Photoconductive Cell
FIGURE 12. Low Pass Filter Response
PHOTOCELL AMPLIFIERS
Amplifiers for photoconductive, photodiode and photovoltaic cells are shown in Figures 14, 15 and 16 respectively.
All photogenerators display some voltage dependence of
both speed and linearity. It is obvious that the current
rhough a photoconductive cell will not display strict proportionality to incident light if the cell terminal voltage is allowed
to vary with cell conductance. Somewhat less obvious is the
fact that photodiode leakage and photovoltaic cell internal
losses are also functions of terminal Voltage. The current-tovoltage converter neatly sidesteps gross linearity problems
by fixing a constant terminal voltage, zero in the case of
photovoltaic cells and a fixed bias voltage in the case of
photoconductors or photodiodes.
A gain frequency plot of circuit response is shown in Rguf8
12 to illustrate the difference between this circuit and the
true integrator.
THE CURRENT·TO·VOLTAGE CONVERTER
Current may be measured in two ways with an operational
amplifier. The current may be converted into a voltage with
a resistor and then amplified or the current may be injected
directly into a summing node. Converting into voltage is undesirable for two reasons: first, an impedance is inserted
into the measuring line causing an error; second, amplifier
offset voltage is also amplified with a subsequent loss of
accuracy. The use of a current-to-voltage transducer avoids
both of these problems.
The current-to-voltage transducer is shown in Figure 13.
The input current is fed directly into the summing node and
the amplifier output voltage changes to extract the same
current from the summing node through R1. The scale factor of this circuit is R1 volts per amp. The only conversion
error in this circuit is Ibias which is summed algebraically with
I'N·
-'D
AI
01
•
>-4,,-V DUT
Rt
v>1"'"'4",-VOU T
Tl/H/6B22-15
VOUT
FIGURE 15. Photodiode Amplifier
= liN R1
Photodetector speed is optimized by operating into a fixed
low load impedance. Currently available photovoltaic detectors show response times in the microsecond range at zero
load impedance and photoconductors, even though slow,
are materially faster at low load resistances.
Tl/H/6822-13
FIGURE 13. Current to Voltage Converter
This basic circuit is useful for many applications other than
current measurement. It is shown as a photocell amplifier in
the following section.
The only design constraints are that scale factors must be
chosen to minimize errors due to bias current and since
voltage gain and source impedance are often indeterminate
(as with photocells) the amplifier must be compensated for
unity-gain operation. Valuable techniques for bias current
compensation are contained in Reference 5.
RI
'CELl"'-
>""'4t--VOUT
vour =
'CELL R1
TUH/6B22-16
FIGURE 16. Photovoltaic Cell Amplifier
23
The feedback resistance, R1, is dependent on cell sensitivity and should be chosen for either maximum dynamic range
or for a desired scale factor. 'R2 is electiVe: in the case of
photovoltaic cells or of photodiodes, it is not required in the
case of photoconductive cells, it should be chosen to minimize bias currerit error over tM operating ~arge.
The amplifiers used must be compensated for unity-gain
and additional compensetion may be required depending on
load reactance and externai transi~tor parameters.
Ot
IN4I11
I.IV
PRECISION CURRENt SOURCE
The precision current soorce is shown in F1f}Ur6S 17 and 18.
The configurations shown will sink or source conventional
current respectively.
>--.-V
v·
OUT
t
02
ZNZZI9
TL/H/8822-19
FIGURE 198. PoSitive V0\tS~e Reterence
ADJUSTABLE VOLTAGE REFERENCES
Adjustable voltage reference circuits are,' shown i'nFigures
19 and 20. The two circuits shown have differlilnt areas of
applicability. The basic difference between the two is that
Figure 19 illustrates a voltage source which provides a voltage greater than the reference diode while Figure 20 iliustrates a voltage source which provides a voltage lower than
the reference diode. The figures sliow both positive and
negative voltage sources.
'
10= VIN
,
'
AI
VIN:;' OV
TlIH/6822-17
FIGURE 17. Precision Current Sink
Caution must be exercised in applying these circuits. The
voltage compliance of the source extends from BVCEA of
the external transistor to approximately 1 volt more negative
, than VIN. The compliance of the current sink is the same in
the positive direction.
The impedance of these current g~nerators is essentially
infinite for small currents and they are accurate so long as
VIN is much greater than Vos and 10 is much greater than
lbias·
The source and sink illustrated in Agures 17 and 18 use an
FET to drive a bipolar output transistor. It Is possible to use
a Darlington connection in piece of the FET-bipolar combination incases where the output current is high and 'the
base current of the Darlington input would not cause a significant error.
01
IN4111
UV
>--.-VOUT
RI
• "
,
,
,
TlIH/6822-20
FIGURE 19b. Neg~lve VoltsgeReference
High preCision extended temperature 'applications of the cir~
cuit of Figure 19 require that the range of adjustment of
VOUT be restricted. When this is done, R1 may be chosen to
provide optimum zener current for minimum zener T.C.
Since Iz Is not a function of V+, reference T.e. will be independent of V+ .
R2
10K
TlIH/6822-18
FIGURE 18. Precision Current Source
24
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f<:»
Rl
_-------4I~-v·
lOOK
... ~"
.
Cl
O.l,...F
>-'''-V
01
lN4611
I.IV
2
RZ
410K
OUT
>--4...-
R3
VOUT
lK
R3
C2
410K
O.t""F~
TLlH/6822-21
FIGURE 2Oa. Positive Voltage Reference
TL/H/6822-23
FIGURE 21. Reset Stabilized Amplifier
-
>.::....-V
01
IN4111
I.BV
The connection is useful in eliminating errors due to offset
voltage and bias current. The output of this circuit is a pulse
whose amplitude is equal to VIN. Operation may be understood by conSidering the two conditions corresponding to
the position of 5,. When 5, is in position 2, the amplifier is
connected in the unity gain connection and the voltage at
the output will be equal to the sum of the input offset voltage and the drop across R2 due to input bias current. The
voltage at the inverting input will be equal to input offset
voltage. CapaCitor C1 will charge to the sum of input offset
voltage and VIN through R1. When C1 is charged, no current flows through the source resistance and R 1 so there is
no error due to input resistance. 5, is then changed to position 1. The voltage stored on C1 is inserted between the
output and inverting input of the amplifier and the output of
the amplifier changes by VIN to maintain the amplifier input
at the input offset voltage. The output then changes from
(Ves + IbiasR2) to (VIN + IbiasR2) as 5, is changed from
position 2 to position 1. Amplifier bias current is suppHed
through R2 from the output of the amplifier or from C2 when
5, is in pOSition 2·and position 1 respectively. R3 serves to
reduce the offset at the amplifier output if the amplifier must
have maximum linear range or if it is desired to DC couple
the amplifier.
OUT
Rt
VTL/H/6822-22
FIGURE 20b. Negative Voltage Reference
The circuit of Figuf'92O is suited for high precision extended
temperature service if V + is reasonably constant since Iz is
dependentori' \(+. R1, R2, R3, and R4 are chosen to provide the proper Iz for minimum T.C. and to minimize errors
due to Ibias.
The circuits shown should both be compensated for unitygain operation or, if large capacitive loads are expected,
should be overcompensated. Output noise may be reduced
in both circuits by bypassing the amplifier input.
An additional advantage of this connection is that input resistance approaches infinity as the capacitor C1 approaches full charge, eliminating errors due to loading of the
source resistance. The time spent in position 2 should be
long with respect to the charging time of C1 for maximum
accuracy.
The circuits shown employ a single power supply, this requires that common mode range be considered in choosing
an. amplifier for these applications. If the common mode
rllnge requirements are in excess of the capability of the
amplifier, two power slipplies may be used. The LH101.may
be used with a single power supply since the common mode
range is from V+ to within approximately 2 volts of V-.
The amplifier used must be compensated for unity gain operation and it may be necessary to overcompensate' because of the phase shift across R2 due to C1 and the amplifier input capacity. Since this connection is usually used at
very low switching speeds, slew rate is not normally a practical consideration and overcompensation does not reduce
accuracy.
THE RESET STABILIZED AMPLIFIER
The reset stabilized amplifier is a form of chopper-stabilized
amplifier and is shown in Figuf'921. As shown, the amplifier
is operated closed-loop with a gain of one.
25
~
Z
R5
C
~&"'-VOUT
v,
v·
v.
RS
= Rl
v,
>
(~~)
0
V
V, V2
oUT = "10
TUH/68.22-24
FIGURE 22. Analog Multiplier
THE ANALOG MULTIPLIER
A simple embodiment of the analog multiplier is shown in
Figure 22. This circuit circumvents many of the problems
associated with the log-antilog circuit and provides three
quadrant analog multiplication which is relatively temperature insensitive and which is not subject to the bias current
errors ·which plague most multipliers.
Circuit operation may be understood by considering A2 as a
controlled gain amplifIer, amplifying V2, whose gain Is dependent .on the ratio of the resIstance of PC2 to Ro and by
consIderIng A1 as a control amplifier which establishes the
resistance of PC2 as a function of V1. In this way It Is seen
that VOUT is a function of both V1 and V2.
A1, the control amplifier, provides drive tor the lamp, l1.
When an input voltage, V1, is present, L1 is driven by A1
until.- the current to the summing junction ·from the negative
supply through PC1 is equal to the current to the summing
junction from V1 through R1. Since the negative supply voltage is fixed, this forces the resistance of PC1 to a value
proporlional to R1 and to the ratio of V1 to V-. L1 also
illuminates PC2 and, if the photoconductors are matched,
causes PC2 to have a resistance equal to PCl.
A2' the controlled gain amplifier, acts as an inverting amplifier whose gain is equal to the ratio of the resistance of PC2
to R5. If R5 is chosen equal to the product of R1 and V-,
then VOUT becomes simply the product of V1 and V2. R5
may be scaled in powers of ten to provide any required
output scale factor.
PC1 and PC2 should be matched for best tracking over temperature since the T.C. of resistance is related to resistance
match for cells of the same geometry. Small mismatches
may be compensated by varying the value of R5 as a scale
factor adjustment The photoconductive cells should receiveequal illumination trom L1, a convenient method is to
mount the cells in holes in an aluminum block and to mount
the lamp midway between them. This mounting method pr0.vides controlled spacing and also provides a thermal. bridge
between the two cells to reduce differences in cell temperature. This technique may be extended to the use of FET's or
other devices to meet special resistance or environment requirements.
The circuit as shown gives an inverting output whose magnitude is equal to one-tenth the product of the two analog
inputs. Input V1 is restricted to positive values, but V2 may
assume both positive and negative values. This circuit Is
restricted to low frequency operation by the lamp time con-
stant
R2 and R4 are chosen to minimize errors due to input offset
current as outlined in the section describing the photocell
amplifier. R3 is included to reduce in-rush current when first
turning on the lamp, L1.
THE FULL-WAVE RECTIFIER
AND AVERAGING FILTER
The circuit shown in Flflure 23 is the heart of an average
reading, !TnS calibrated AC voltmeter. As shown, it is a rectifier and averaging filter. Deletion of C2 removes the averaging function and provides a precision full-wave re«tifier, and
deletion of C1 provides an absolute value generator.
Circuit operation may be understood by following the signal
path !or negative and then for positive inputs. For negative
signals, the output of amplifier A1 is clamped·to +O.7V bY
01 and disconnected trom the summing point of A2 by 02.
A2 then functions as a simple unlty-gain inverter with input
resistor, R1, and feedback resistor, R2, giving a positive go.
ing output.
.
For positive inputs, A1 operates as a normal amplifier c0nnected to the A2 summing point through resistor, R5. Amp"fier A1 then acts as a simple unity-gain inverter with input
26
,..
Rl
20K
20K
1"
Cl
At
INPUT
~H
4.7,..F
+
01
FOII.&
4.7,..F
1"
«:)
DC
OUTPUT
CAL
1"
1"
•
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UK
R4
20K
R3
20K
Z
R2
02
FOUI&
R5
10K
1"
C2
4.7,..F
RI
10K
TL/H/6822-25
FIGURE 23. Full-Wave Rectifier and Averaging Filter
resistor, R3, and feedback resistor, R5. A 1 gain accuracy is
not affected by 02 since it is inside the feedback loop. Positive current enters the A2 summing point through resistor,
R1, and negative current is drawn from the A2 summing
point through resistor, R5. Since the voltages across R1 and
R5 are equal and oPPOsite, and R5 is one-half the value of
R1, the net input current at the A2 summing point is equal to
and opposite from the current through R 1 and amplifier A2
operates as a summing inverter with unity gain, again giving
a positive output.
with decreasing frequency. When this network-the Wien
Bridge-is used as a positive feedback element around an
amplifier, oscillation occurs at the frequency at which the
phase shift is zero. Additional negative feedback is provided
to set loop gain to unity at the oscillation frequency, to stabilize the frequency of oscillation, and to reduce harmonic
distortion.
Cl
2.2,..F
The circuit becomes an averaging filter when C2 is connected across R2. Operation of A2 then is similar to the Simple
Low Pass Filter previously described. The time constant
R2C2 should be chosen to be much larger than the maximum period of the input voltage which is to be averaged.
.--.......-
Capacitor Cl may be deleted if the circuit is to be used as
an absolute value generator. When this is done, the circuit
output will be the positive absolute value of the input voltage.
VOUT = 18.5 Vpp
10Hz
01
lN457
The amplifiers chosen must be compensated for unity-gain
operation and RS and R7 must be chosen to minimize output errors due to input offset current.
02
lN155
Uv
SINE WAVE OSCILLATOR
An amplitude-stabilized sine-wave oscillator is shown in Figure 24. This circuit provides high purity sine-wave output
down to low frequencies with minimum circuit complexity.
An important advantage of this Circuit is that the traditional
tungsten filament lamp amplitude regulator Is eliminated
along with its time constant and linearity problems.
TlIH/6822-2&
In addition, the reliability problems associated with a lamp
are eliminated.
FIGURE 24. Wlen Bridge Sine Wave Oscillator
The Wien Bridge oscillator is widely used and takes advantage of the fact that the phase of the voltage across the
parallel branch of a series and a parallel RC network connected in series, is the same es the phase of the applied
voltage across the two networks at one particular frequency
and that the phase lags with increasing frequency and leads
The circuit presented here differs from the classic usage
only in the form of the negative feedback stabilization
scheme. Circuit operation is as follows: negative peaks in
excess of -8.25V cause 01 and 02 to conduct, charging
27
The integrator then generates a negative-going ramp with a
rate of 1+ IC1 volts per second until its output equals the
negative trip point of the threshold detector. The threshold
detector then changes to the negative output state and supplies a negative current, 1-, at the integrator summing point.
The integrator now generates a positive-going ramp with a
'rate of 1-1C1 volts per second until its outpUt equals the
positive trip point of the threshold detector where the detector again changes output state and the cycle repeats.
Triangular-wave frequency is determined by R3, R4 and C1
and the positive and negative saturation voltages of the amplifier A1. AmplitUde is determined by the ratio of R5 to the
combination of R1 and R2 and the threshold detector saturation voltages. Positive and negative ramp rates are equal
and positive and negative peaks are equal if the detector
has equal positive and negative saturation voltages. The
output waveform may be offset with respect to ground if the
inverting input of the threshold detector, A 1, is offset with
respect to ground.
The generator may be made independent of temperature
and supply voltage if the detector is clamped with matched
zener diodes as shown in Figure 26.
The integrator should be compensated for unity-gain and
the detector may be compensated if power supply impedance causes oscillation during its,transition time. The curr.ent into the integrator should be large with respect to Iblas
for maximum symmetry, and offset voltage should be small
with respect to VOUT peak.
C4. The charge stored in C4 provides bias to Q1, which
determines amplifier gain. C3 is a low frequency roll-off capacitor in the feedback network and prevents offset voltage
and offset current errors from being multiplied by amplifier
gain.
Distortion is determined by amplifier open-loop gain and by
the response time of the negative feedback lopp filter, R5
and C4. A trade-off is necessary'in determining ampntude
stabilization time constant and oscillator" distortion. R4 i&
chosen to adjust the negative feedback loop so that the
FET is operated at a small negative gate bias. The circuit
shown provides optimum values for a general purpose oscillator.
TRIANGLE-WAVE GENERATOR
A constant amplitude triangular-wave generator is shown in
Figure 25. This circuit provides a variable frequency triangular wave whose amplitude is independent of frequency.
l.rEIHIATDR
..CI,,,F
RI
HZ
10K
III
l1li'
UK
TL/H/6822-27
FIGURE 25. Triangular-Wave Generator
>'~'Y1"r-~~" TD INTEGRATOR INPUT
The generator embodies an integrator as a ramp generator
and a threshold detector with hysterisis as a reset circuit.
The integrator has been described in a previous section and
requires no further explanation. The threshold detector is
similar to a Schmitt Trigger in that it is a latch circuit with a
large dead zone. This function is implemented by using positive feedback around an operational amplifier. When the
amplifier output is in either the positive or negative saturated
state, the positive feedback network provides a voltage at
the non-inverting Input which is determined by the attenuation of the feed-back loop and the saturation voltage of the
amplifier. To cause the amplifier to change states, the voltage at the input olthe amplifierinust be caused to change
polarity by an amount In excess of the amplifier input offset
voltage. When this is done the amplifier saturates in the
OPPOSite direction and remains In that state until the voltage
at its input again reverses. The complete circuit operation
may be understood by examining the operation with the output of the threshold detector'in the positive state. The detector pOSitive saturation voltage is applied to the integrator
summing junction through the combination R3 and R4 causing a current I + to flow.
RI
,11K
.....
'RI
11K
RI
1M
----~M,.--~ ~:~~:TEGRATDR
TUH/6822-28
FIGURE 26. Thre8hold Detector with Regulated Output
TRACKING REGULATED POWER SUPPLY
A tracking regulated power supply is shown in Figure 21.
This supply is very suitable for powering an operational amplifier system since pOSitive and negative voltages track,
eliminating common mode Signals originating in the supply
voltage. In addition, only one voltage reference and a minimum number' of passive components are required.
'
28
.qV UNREGULATED
PROGRAMMABLE BENCH POWER SUPPLY
The complete power supply shown in Figure 28 is a programmable positive and negative power supply. The regulator section of the supply comprises two voltage followers
whose input is provided by the voltage drop across a reference resistor of a preCision current source.
T1
TRIAD.X
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- 50l'fT TSOI'F
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TL/H/6622-30
....--.--.....~-t-••.s.c.
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12V
Output voltage Is variable from ± 5V to
±35V.
04
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R3
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UK
1%
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FOR
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01
2N260&
2.W
Negative oulput tracks positive oulputto
within the ratio of R6 to R7.
TL/H/6822-29
FIGURE 27. Tracking Power Supply
RI
RI
ilK
Power supply operation may be understood by considering
first the positive regulator. The positive regulator compares
the voltage at the wiper of R4 to the voltage reference, 02.
The difference between these two voltages is the input volt·
age for the amplifier and since R3, R4, and R5 form a negative feedback loop, the amplifier output voltage changes in
such a way as to minimize this difference. The voltage reference current is supplied from the amplifier output to increase power supply line regulation. This allows the regulator to operate from supplies with large ripple voltages. Regulating the reference current in this way requires a separate
source of current for supply start-up. Resistor R1 and diode
01 provide this start-up current. 01 decouples the reference
string from the amplifier output during start-up and R 1 supplies the start-up current trom the unregulated positive supply. After start-up, the low amplifier output impedance reduces reference current variations due to the current
through R1.
The negative regulator is simply a unity-gain inverter with
input resistor, RS, and feedback resistor, R7.
'='
C3
_,F
V+
TUH/6822-31
b.
...IV
The amplifiers must be compensated for unity-gain operation.
The power supply may be modulated by injecting current
into the wiper of R4. In this case, the output voltage variations will be equal and oppOSite at the positive and negative
outputs. The power supply voltage may be controlled by
replacing 01, 02, R1 and R2 with a variable voltage reference.
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1%
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12V
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1"
FOR
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-
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TUH/6622-32
c.
FIGURE 28. Low·Power Supply for
Integrated Circuit Testing
29
Programming sensitivity of th6 positivsarid negative supply
is 1V11000n of resistors R6-and R-12 resp~ively. The out~
put voltage of the positive regulator;may be_varied from approximately + 2V to -h38V with respect .to around and-the
negativ.e regulator output voltage may be varied from -S8Y
to OV with respect to ground. Since LM107 amplifiers are,
used, the supplies are inherently short circuit proof. This
current limiting feature alsO serves to protect a test circuit if
this supply·is-used in integrated circuiUesting.
Internally compensated amplifiers may be used in this application if the expecte!! capacitive loading is small. If large
capacitive -loads are expected, an externally compensated
amplifier should be used and the amplifier shouid be overcompensated for additional stability. Power supply noise
may be reduced by bypassing the amplifier inputs to ground
with capacitors in the 0.1 to 1.0 p.F range.
Input Resistance: The ratio of the change in input voltage
to the change in Input current on either input with the other
grounded.
Supply Current: The current required from the power supply to operate the amplifier with no load and the output at
zero.
Output Voltage Swing: The peak output voltage swing, referred to zero, that can b~ obtained without Clipping.
Large-8lgnal Voltage G8ln:The ratio of the output voltage
swing to the change in input volta,ge required to drive the
output from zero to this voltage.
Power Supply ReJection: The ratio of the change in input
offset voltage to change in power supply voltage producing
it.
Slew Rate: The internally-limited rate of change in output
vol1age with a large-amplriude step funCtIon applied to the
input.
CONCLUSIONS
The foregoing circuits are illustrative of the versatility of the
integrated operational amplifier and· provide a guide to a
number of useful applications. The cautions noted in each
section will show the more common pitfalls encountered in
amplifier usage.
REFERENCES
1. D.C. Amplifier Stabilized for Zero and Gain; Williams, Tapley, and Clark; AlEE Transactions, Vol. 67, 1948.
2. Active Network" Synthesis; K. L. Su, McGraw-Hili Book
Co., Inc., New York, New York.
3. Analog Computation; A. S. Jackson, McGraw-Hili Book
Co., Inc., "New York, New York.
4. A Palimpsest on the Electronic Analog Art; H. M. Paynter,
Editor. Published by George A. Philbrick Researches,
Inc., Boston, Mass.
5. Drift Compensation Techniques for Integrated D.C. Am~
plifieni; R. J. Widlar, EDN, June 10, 1968.
6. A Fast Integrated Vo~ge Follower With Low Input Current; R. J. Widlar, _Microelectronics, Vol. 1 No.7, June
1968.
APPENDIX I
DEFINITION OF TERMS
Input Offset Voltage: That voltage Which must be applied
between the input terminals through two equal resistances
to obtain zero output voltage.
Input Offset Current: The difference, in the _currents into
the two input terminals wh4!'ri- the output is at zero.
Input Bias Current: The average of the two input currents.
Input Voltage Range: The range of voltages on the input
terminals for which the amplifier operates within specifications.
- Common Mode Rejection Ratio: The ratio of the input
voltage range to the peak-to-peak change in input offset
vol1age over this range.
30
National Semiconductor
Application Note 23
The LM 10S-An Improved
Positive Regulator
Robert J. Widlar
Apartado Postal 541
Puerto Vallarta, Jalisco
Mexico
Introduction
I
l
IC voltage regulators are seeing rapidly increasing usage.
The LM100, one of the first, has already been widely accepted. Designed for versatility, this circuit can be used as a
linear regulator, a switching regulator, a shunt regulator, or
even a current regulator. The output voltage can be set between 2V and 30V with a pair of external resistors, and it
works with unregulated input voltages down to 7V. Dissipation limitations of the IC package restrict the output current
to less than 20 mA, but external transistors can be added to
obtain output currents in excess of 5A. The LM100 and an
extensive description of its use in many practical circuits are
described in References 1-3.
z
"""""'
"
I'
LM100
co
; -D.2
...::: -0.4
1
1
LM10S
>
1\
I
'"~
c:
\
I
SHORT CIRCUIT
-0.6
...>
~ -.01
:::>
co
-1.0
C'IRREL) I
Rac" Ion
TI" 2S'C
o
One complaint about the LM100 has been that it does not
have good enough regulation for certain applications. In addition, it becomes difficult to prove that the load regulation is
satisfactory under worst-case design conditions. These
problems prompted development of the LM105, which is
nearly identical to the LM 100 except that a gain stage has
been added for improved regulation. In the great majority of
applications, the LM105 is a plug-in replacement for the
LM100.
,
10
,
,
1
,
,
I
20
30
40
LOAD CURRENT (mAl
TLlH/6906-1
a. TJ
-,.....
l
z
5!
~
= 25'C
1
-~
,
)
LM100 ' \
-0.2
...:;: -0.4
1\
-0.6
\
'"~
co
>
!; -O.B
Rsc" Ion
Tj • 125'C
~
:::>
co -1.0
o
LM105,_
L
>
the Improved regulator
The load regulation of the LM100 is about 0.1 %, no load to
full load, without current limiting. When short circuit protection is added, the regulation begins to degrade as the output
current becomes greater than about half the limiting current.
This is illustrated in Figure 1. The LM105, on the other hand,
gives 0.1 % . regulation up to currents closely approaching
the short circuit current. As shown in Figure 1b, this is particularly significant at high temperatures.
The current limiting characteristics of a regulator are important for two reasons: First, it is almost mandatory that a
regulator be short-circuit protected because the output is
distributed to enough places that the probability of it becoming shorted is quite high, Secondly, the sharpness of the
limiting characteristics is not improved by the addition of
external booster transistors. External transistors can increase the maximum output current, but they do not improve the load regulation at currents approaching the short
1
lL
II
SHORT CIRCUIT
CURRENT
itA""
I
10
Ii
Ii
20
30
LOAD CURRENT (mAl
TL/H/6906-2
b. TI = 125'C
Figure 1. Comparison between the load regulation of
the LM100 and LM105 for equal short circuit
currents
circuit current. Thus, it can be seen that the LM105 provides
more than ten times better load regulation in practical power
supply designs.
31
Figure 2 shows that the LM105 als()',provides better line
regulation than the LM100. These curves give the. percept'.' age change in output voltage for an incremental change in
the unregulated input voltage. They show that the line regulation is worst for small differences between the input and
output voltages. The LM105 provides about three times better regulation under worst case conditions. Bypassing the
internal reference of the regulator makes the ripple rejection
of the LM105 almost a factor of ten better than the LM100
over the entire operating range, as shown in the figure. This
bypass capaCitor also eliminates noise generated in the internal reference zener of the IC.
a.1
r-'~=,,"""'_---""'-""'-UNREGULATEol""T
BOOSTER OUTPUT
CUriRENT 'LlMIT
REGULATED OUTPUT
.+-_....__
.;...J
C_ENSATIONI
SHUTDOWN
VOUT -lOY
~'~fIO=~
II""
~~
LMIO. R1J'I'U
REJ~~~Iiii"-
I IIIII
..011
ID
. } - - + , . + - fEEDBACK
r--
"N,·,D,F
I~IZDH •
Z8
'--............- - - - - - - - - - - - - GROUNO
.
10
.
.
TL/H/6806-5
Figure 4. SchemaUc diagram of the LM105 regulator
INPUT·OUTPUT VOLTAGE olFFERENnAL (VI
04, divided down by R1 and R2 and connected in series
with a diode-connected transistor, 07. The negative temperature coefficient of 07 cancels out the positive cOefficient of
the voltage across R2, producing .a temperature-compen.sated 1.aV on the base of oa. This point is also brought
outside the circuit so that an external capacitor can be added to bypass any rioise from. the zener diode.
.
TLlH/6906-3
Figure 2. Comparison between the line regulation cha....
acterlsUes of the LM100 and LM105
The LM105 has also benefited from the use of new IC components developed after the LM100 was deSigned. These
have reduced the Internal pQwer consumption so that the
LM105 can be specified for input ,(oltages up to 50V and
output voltages to 40V. The minimum preload current reo
quired by the LM100 is not needed on the LM105.
Transistors oa and 09 make up the error amplifier of the
circuit. A gain of 2000 is obtained from this single stage by
using a current source, another collector on 02, as a collector load. The output of the amplifier is buffered'by 011 'and
used to drive the series·pass transistor, 012. The collector
of 012 is brought out so that an external PNP transistor, or
PNP-NPN combination, can be added for increased output
current.
circuit description
The differences between the LM100 and th" LM105 can be
seen by comparing the schematic diagrams in Figures 3 and
4. Q4 and 05 have been added to the LM105 to form a
common·collector, common-base, common-emitter amplifi·
er, rather. than the single eommon-emitter differential amplifier of the LM100.
Current limiting is 'provided by 010. When the voltage
across an external resistor connected between Pins 1· and a
. becomes high enough to turn on 010, it removes the base
drive from 011 so the regulator exhibits a constant-current
characteristic. Prebiasing the current limit transistor with a
portion of the emitter-base voltage of 012 from R6 and R7
reduces the current limit sense voltage: This increases' the
In the LM100, generation of the reference voltage starts
with zener diode, 01, which is supplied with a fixed current
from one of the collectors of 02. This regulated vollage,
which has a positive temperature coefficient, is buffered by
---..,.-...,..-1~3ll.~~\GULATEo
r - ' _ - - - -.....
"VV"""'....' f~..:WENT
.l-....
~,.,.,....."""'+<-----t-'-. :~~~fTEo
03
. -_ _ _ _ _
J ~~::~::TIONI
~~....-~oa!....l-----· fEEDBACK
'--__+-_______5 :m=:NCE
R3
UK
4
L - -____--~_-------GROUNO
TLlH/6806-4
Figure 3. Schematic diagram of the LM100 regulator
32
power limitation.
efficiency of the regulator, especially when foldback current
limiting is used. With foldback limiting, the voltage dropped
across the current sense resistor is about four times larger
than the sense voltage.
Although it is desirous to put as much of the regulator as
possible on the IC chip, there are certain basic limitations.
For one, it is not a good idea to put the series pass transistor on the chip. The power that must be dissipated in the
pass transistor is too much for practical IC packages. Further, IC's must be rated at a lower maximum operating temperature than power transistors. This means that even with
a power package, a more massive heat sink would be required if the pass transistor was included in the IC.
As for the remaining details, the collector of the amplifier,
09, is brought out so that extemal collector-base capacitance can be added to frequency-stabilize the circuit when it
is used as a linear regulator. This terminal can also be
grounded to shut the regulator off. R9 and R4 are used to
start up the regulator, while the rest of the circuitry establishes the proper operating levels for the current source
transistor, 02.
Assuming that these problems could be solved, it is still not
advisable to put the pass transistor on the same chip with
the reference and control circuitry: changes in the unregulated input voltage or load current produce gross variations
in chip temperature. These variations worsen load and line
regulation due to temperature interaction with the control
and reference circuitry.
The reference circuitry of the LM105 is the same, except
that the current through the reference divider, R2, RS and
R4, has been reduced by a factor of two on the LM105 for
reduced power consumption. In the LM105, 02 and as form
an emitter coupled amplifier, with as being the emitter-follower input and 02 the common-base output amplifier. RS is
the collector load for this stage, which has a voltage gain of
about 20. The second stage is a differential amplifier, using
04 and 05. 05 actually provides the gain. Since it has a
current source as a collector load, one of the collectors of
012, the gain is quite high: about 1500. This gives a total
gain in the error amplifier of about SO,OOO which is ten times
higher than the LM100.
To elaborate, it is reasonable to neglect the package problem since it is potentially solvable. The lower, maximum operating temperatures of IC's, however, present a more basic
problem. The control circuitry in an IC regulator runs at fairly
low currents. As a result, it is more sensitive to leakage
currents and other phenomena which degrades the performance of semiconductors at high temperatures. Hence,
the maximum operating temperature is limited to 150"C in
military temperature range applications. On the other hand,
a power transistor operating at high currents may be run at
temperatures up to 200"C, because even almA leakage
current would not affect its operation in a properly designed
circuit. Even if the pass transistor developed a permanent
1 mA leakage from channeling, operating under these conditions of high stress, it would not affect circuit operation.
These condItions would not trouble the pass transistor, but
they would most certainly cause complete failure of the control circuitry.
It is not obvious from the schematic, but the first stage (02
and aS) and second stage (04 and 05) of the error amplifier are closely balanced when the circuit is operating. This
will be true regardless. of the absolute value of components
and over the operating temperature range. The only thing
affecting balance is component matching, which is good in a
monolithic integrated circuit, so the error amplifier has good
drift characteristics over a wide temperature range.
Frequency compensation is accomplished with an external
integrating capaCitor around the error amplifier, as with the
LM100. This scheme makes the stability insensitive to loading conditions-resistive or reactive-while giving good
transient response. However, an internal capaCitor, Cl, is
added to prevent minor-loop oscillations due ·to the increased gain.
These problems are not eliminated in applications with a
lower maximum operating temperature. Integrated circuits
are sold for limited temperature range applications at considerably lower cost. This is mainly based on a lower maximum junction temperature. They may be rated so that they
do not blow up at higher temperatures, but they are not
guaranteed to operate within specifications at these temperatures. Therefore, in applications with a lower maximum ambient temperature, it is necessary to purchase an expensive
full temperature range part in order to take advantage of the
theoretical maximum operating temperatures of the IC.
Additional differences between the LM100 and LM105 are
that a field-effect transistor, 018, connected as a current
source starts the regulator when power is first applied.
Since this current source is connected to ground, rather
than the output, the minimum load current before the regulator drops out of operation with large input-output voltage
differentials is greatly reduced. This also minimizes power
diSSipation in the integrated circuit when the difference between the input and output voltage is at the worst-case value. With the LM105 circuit configuration, it was also necessary to add 017 to eliminate a latch-up mechanism which
could exist with lower output-voltage settings. Without 017,
this could occur when as saturated and cut off the second
stage amplifiers, 04 and 05, causing the output to latch at a
voltage neariy equal to the unregulated input.
Figure 5 makes the point about dissipation limitations more
strongly. It gives the maximum short circuit output current
for an IC regulator in a TO-5 package, assuming a 25°C
temperature rise between the chip and ambient and a quiescent current of 2 mAo Dual-in-line or flat packages give results which are, at best, slightly better, but are usually
worse. If the short circuit current is not of prime concern,
Figure 5 can also be used to give the maximum output current as a function of input-output voltage differential, However, the increased dissipation due to the quiescent current
flowing at the maximum input voltage must be taken into
account. In addition, the input-output differential must be
measured with the maximum expected input voltages.
SS
sa
.....
~
~
\
40
,
TIT
\
INFINITE HEAT
\SINK':' 500 laW
30
\
co
...
>
f
!!
Thia would happen if an NPN transistor was used In a com.
pound emitter follower connection wIIh the NPN output tran·
slstor of the IC. A single-diffused, wide base transistor like
the 2N3740 is recommended because it causes fewer oscil·
latlon problems than double-diffused, planar dfilvices.ln ad·
dition, it seems to be less prone to failure under Qverload
conditions; and low cost devices are available in power
packages like the T0-66 or even TO-3.
When the maximum dissipation in the pass transistor is less
than about 0.5W, a 2N2905 may be used as a pass trailsis·
tor. However,1t is generally necessary to carefully observe
thermal deratings and provide some sort of heat sink.
In the circuit of Fl(Juf88, the output voltage is determined by
A1 and A2. The resistor values are selected based on a
feedback voltage of 1.8V to Pin 6 of the LM105. To keep
thermal drift of the output voltage within specifications, the
parallel combination of AI and A2 should be approximately
2K. However, this reSistance is not critical. Variations of
± 30% will not cause an appreciable degradation of temper·
ature drift.
The 1 j.lF output capaCitor, C2, is required to suppress osCii.
lations in the feE!dback loop involving the external booster
transistor, ai, and the output transistor of the LM1 05: Cl
compensates the internal regulator circuitry to make the sta·
billty independent for all loading conditions. C3 is not nor·
mally required if the lead length between the regulator and
the output filter of the rectifier is short.
Current limiting is provided by A3. The current limit resistor
should be selected so that the maximum' voltage drop
across it, at full load current, is equal to the voltage given in
Figuf8 7 at the maximum junction temperature of the IC.
This assures a no load to full load regulation better t\lan
0.1 % under worst·case cOnditions.
~d~
ZO
NO HEATSINK
117mW
10
IlT.IZ5JCI
10 ·2mA
'-...
1.0
,
r-..
10
100
OUTPUT CURRENT (mA)
TL/H/6906-6
Figure 5. Dissipation limited short circuit output current
for an Ie regulator In a T0-5 package
The 25'C temperature rise assumed in arriving at Figuf8 5 is
not at all unreasonable. With military temperature range
parts, this is valid for a maximum junction temperature of
150'C with a 125'C ambient. For low cost parts, marketed
for limited temperature range applications, this maximum
differential appropriately derates the maximum Junction tem·
perature.
In practical designs; the maidmum permissible dissipation
will always be to the left of the curve shoviln for an infinite
heat sink in Figuf8 5. This curve is realized with the package
immersed in circulating acetone, freon or mineral oil. Most
heat sinks are not quite as good.
To summarize, power transistors can be run with a temperature differentiai, junction to ambient, 3 to 5 times as great as
an integrated circuit. This means that they can dissipate
much more power, even with a smaller heat sink. This, cou·
pled with the fact that low cost, multilead power packages
are not available and that there can be thermal interactions
between the control circuitry and the pass transistor, strong·
Iy suggests that the pass transistors be kept separate from
the integrated circuit.
zoo
..
using booster transiators
Figuf8 6 shows how an external pass transistor is added to
the LM105. The addition of an external PNP transistor does
not increase the. minimum input output voltage differential.
r---...
"N........-----4~'.;.
....._
R3
8.16
RI
Cl
U&K
8
47 pF
1%
L.... 1
7
2N37~ ?J---<~ LM105
~ ~
·lu
Y
V,N
To.Ol.F
IIJ--4_e
5
1
II!
."
VOUT -6V
I'
140
I'
:)'
100
211 40
10
80
100 120
140 110
JUNCTION TEMPERATURE I'C)
TL/H/6906-8
Figure 7. Maximum voltage drop across current limit reo
.alator at full load for worst case load regulation of 0.1%
The. short circuit output curr~nt is also determined by AS.
FI(JUf8 8 shows the voltage drop across this nJsistor, when
the output is shorted, as a function of junction temperature
in the IC.
With the type of current limiting used in Figuf8 6, the dissipa·
tion under short circuit conditions can be more than three
times the worst·case full load dissipation. Hence, the heat
-:~czt
"r-l.F
HZ
3.15K
1%
rT~~-r~rr'-rT~~
tSolld 1I.lIlum
--4~-----~~----~-~--GROUND
TLlH/6906-7
Figure 6. 0.2A regulator
34
the current is reduced to a value determined by the current
limit resistor and the current limit sense voltage of the
LM105.
0.&
~
...
~...
co
>
0.5
•
I:j
!:
0.4
;;
0.3
...
... i'.
18
I...... r-....
I...... "
!
...
~
12
CD
10
...
r-... ......
~
co
......
LIMITING
~~,
CHtRjCTjRISTlj)
Vj
::I
LOADLlN~.
::I
0.2
-15 -50 -25 0
::I
co
25 50 15 100 125 150
JUNCTION TEMPERATURE (OCI
1/
4
If'
o~
TL/H/6906-9
o
Figure 8. Voltage drop across current limit resistor required to Initiate current limiting
I
~ ~ ItCURRENT-
NORMAL
>
III:
III:
...
I
14
,.fl
.,
~.
0.5
SOURCE 1
LfA LliE
j
J
L'
STABLE
·oPERATING POINT
1.0
1.5
2.0
2.5
OUTPUT CURRENT (1\1
sink for the pass transistor must be designed to accommodate the increased dissipation if the regulator is to survive
more than momentarily with a shorted output. It is encouraging to note, however, that the short circuit current will decrease at higher ambient temperatures. This assists in protecting the pass transistor from excessive heating.
TLIH/6908-11
Figure 10. Umltlng characteristics of regulator using
foldback current limiting
Figure 10 illustrates the limiting characteristics. The circuit
regulates for load currents up to 2A. Heavier loads will
cause the output voltage to drop, reducing the available current. With a short on the output, the current is only 0.5A.
foldback current limiting
With high current regulators, the heat sink for the pass transistor must be made quite large in order to handle the power
dissipated under worst·case conditions. Making it more than
three times larger to withstand short circuits is sometimes
inconvenient in the extreme. This problem can be solved
with foldback current limiting, which makes the output current under overload conditions decrease below the full load
current as the output voltage is pulled down. The short cir·
cuit current can be made but a fraction of the full load current.
A high current regulator using foldback limiting is shown in
Ftgure 9. A second booster transistor, 01, has been added
to provide 2A output current without causing excessive dissipation in the LM105. The resistor across its emitter base
junction bleeds off any collector base leakage and estab·
lishes a minimum collector current for 02 to make the circuit
easier to stabilize with light loads. The foldback characteristic is produced with A4 and A5. The voltage across A4
bucks out the voltage dropped across the current sense
resistor, A3. Therefore, more voltage must be developed
across A3 before current limiting is initiated. After the output
voltage begins to fall, the bucking voltage is reduced, as it is
proportional to the output voltage. With the output shorted,
In deSign, the value of A3 is determined from
(1)
where Vlim is the current limit sense voltage of the LM10.5,
given in Ftgure 8, and ISC is the design value of short circuit
current. A5 is then obtained from
. = VOUT + Vsense ,
.(2)
As
Ibleed + 'bias
where VOUT is the regulated output voltage, Vsense is maXimum voltage across the current limit resistor for 0.1 % regu~
lation as indicated in Figure 7, Ibleed is the preload· current
on the regulator output provided by A5 and Ibias is the maximum current coming out of Pin 1 of the LM105 under full
load conditions. Ibias will be equal to 2 rnA plus the worstcase base drive for the PNP booster transistor, 02. Ibleed
should be made about ten times greater than Ibias'
Finally, R4 is given by
V",se""nse",,
A4 = "IF.",L"-A",3c...-_
(3)
Ibleed
where IFL is the output current of the regulator at full load.
C4
O.H"F
R3
r - -....-
0.1
....~w_+-----
.....--....RI
VOUT = 15V
+ at
IUKT4.1"F
CI
41pF
V,N >18V _ ....-
'"
R2
--+_-{
UK
....
1%
tSolid tantalum
*Ferroxcube K5-001'()O/3B
Figure 9. 2A regulator with foldback current limiting
35
TLIH/B90B-10
short circuited output. This is illustrated in Figure 11. However, if the maximum dissipation is calculated with the worstcase input voltage, as it should be, the power peak is not
too high. .
It is recommended that a ferrite bead be strung on the emitter ofthe pass transistor, as shown in Rgure 9, to suppress
oscillations that may show up with certain phySical configurations. It is advisable to also include C4 across the current
limit resistor..
25
In some applicationiil, the power dissipated in 02 becomes
too great for a 2N2905 under worst-case conditions. This
can be true even if a heat sink is used, as it should be in
almost aU applications. When dissipation is a problem, the
2N2905 can be.replaced with a 2N3740. With a 2N3740, the
ferrite bead and C4 are not needed because this transistor
has a lower cutoff frequency.
.
~
,-
20
.L
;0:
i.
co
IE
15
1/
10
I- VIN =25V
!...
One of the advantages of ·foldback limiting is that it sharpens the limiting characteristics of the IC. In addition, the
maximum output curren. is less sensitive to variations in the
current limit sense voltage of the IC: in this circuit, a 20%
change in sense voltage will only affect the trip current by
5%. The temperature sensitivitY of the full load current is
likewise reduced by a factor of four, while the short circuit
current is.I)Ot.
--..
t-IFL
o
=2,oA
t-I"j' "'fA
8
024
8
~
"
~
"
OUTPUT VOLTAGE (V)
TUH/6906-12
FIGure 11_ Power dlStllpatlon In series pass transistors
under overload conditions In regulator' using
foldback current limiting
Even though the voltage dropped across the sense resistor
is larger with. foldback limiting, the minimum input-output
voltage differential of the complete regulator is not increased above the 3V specified for the LM105 as long as
this drop is less than 2V. This can be attributed to the low
sense voltage of the IC by itself.
high current regulator
The output current of a regulator using the LM105 as a control element can be increased to any desired level by adding
more booster transistors, increasing the effectiVe current
gain of the pass transistors. A circuit for a 10A regulator is
shown in Figul'8 12. A third NPN transistor has been included to get higher current. A low frequency device is used for
03 because it seems to better withstand abuse. However,
high frequency transistors must be used to drive it. 02 and
03 are both double-diffused transistors with good frequency
response. This insures that 03 will present the domin.ant lag
in the feedback loop through the booster transistors, and
back around the output transistor of the LM105. This is further insured by the addition of C3.
Rgul'8 10 shows that foldback limiting can only be used with
certain kinds of loads. When the load looks predominately
like a current source, the load line can intersect the fold back
characteristic at a point where it will prevent the regulator
from coming up to'voltage, even without an overload. Fortunately, most solid state circuitry presents a load line which
does not intersect. However, the possibility cannot be ignored, and the regulator must be designed with some
knowledge of the load.
with foldback limiting, power dissipation in the pass transistor reaches a maximum at some point between full load and
r-........i t........-t~........~....~--~~--~............................i t........~t----VouT=5V
C3t
3.3~F
I
R3
0.18
R4
03
'" ~ """
47
RI
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TUH/6906-13
Figure 12. 10A regulator with foldback current limiting
36
The circuit, as shown, has a full load capability of 10A. Foldback limiting is used to give a short circuit output current of
2.5A. The addition of
increases the minimum input-output voltage differential, by 1V, to 4V.
through the reverse biased pass transistors or the control
Circuitry, frequently causing destruction. This phenomenon
is especially prevalent when solid tantalum capaCitors are
used with high-frequency power inverters. The maximum
ripple allowed on these capacitors decreases linearly with
frequency.
The solution to this problem is to use capaCitors with conservative voltage ratings. In addition, the maximum ripple
allowed by the manufacturer at the operating frequency
should also be observed.
The problem can be eliminated completely by installing a
diode between the input and output of the regulator such
that the capaCitor on the output is discharged through this
diode if the input is shorted. A fast switching diode should
be used as ordinary rectifier diodes are not always effective.
Another cause of problems with regulators is severe voltage
transients on the unregulated input. Even if these transients
do not cause immediate failure in the regulator, they can
feed through and destroy the load. If the load shorts out, as
is frequently the case, the regulator can be destroyed by
subsequent transients.
This problem can be solved by specifying all parts of the
regulator to withstand the transient conditions. However,
when ultimate reliability is needed, this is not a good solution. Especially since the regulator can withstand the tranSient, yet severely overstress the circuitry on its output by
feeding the transients through. Hence, a more logical recourse is to include circuitry which suppresses the transients. A method of dOing this is shown in Figure 13. A zener
diode, which can handle large peak currents, clamps the
input voltage to the regulator while an inductor limits the
current through the zener during the transient. The size of
the inductor is determined from
as
dominant failure mechanisms
By far, the biggest reason for regulator failures is overdissipation in the series pass transistors. This has been borne
out by experience with the LM100. Excessive heating in the
pass transistors causes them to short out, destroying the IC.
This has happened most frequently when PNP booster transistors in a TO-5 can, like the 2N2905, were used. Even with
a good heat sink, these transistors cannot dissipate much
more than 1W. The maximum dissipation is less in many
applications. When a single PNP booster Is used and power
can be a problem, it is best to go to a transistor like the
2NS740, in a TO-66 power package, using a good heat sink.
Using a compound PNP/NPN booster does not solve all
problems. Even when breadboarding with transistors in TOS power packages, heat sinks must be used. The TO-S
package is not very good, thermally, without a heat sink.
Dissipation in the PNP transistor driving the NPN series
pass transistor cannot be ignored either. Dissipation in the
driver with worst-case current gain in the pass transistor
must be taken into account. In certain cases, this could require that a PNP transistor in a power package be used to
drive the NPN pass transistor. In almost all cases, a heat
sink Is required if a PNP driver transistor in a TO-5 package
is selected.
With output currents above SA, it is good practice to replace
a 2NS055 pass transistor with a 2NS772. The 2NS055 is
rated for higher currents than SA, but its current gain falls off
rapidly. This is especially true at either high temperatures or
low input-output voltage differentials. A 2NS772 will give
substantially better performance at high currents, and it
makes life much easier for the PNP driver.
L = I1Vl1t
I
The second biggest cause of failures has been the output
filter capacitors on power inverters providing unregulated
power to the regulator. If these capaCitors are operated with
excessive ripple across them, and simultaneously near their
maximum dc voltage rating, they will sputter. That is, they
short momentarily and clear themselves. When they short,
the output capacitor of the regulator is discharged back
where 11V is the voltage by which the input tranSient exceeds the breakdown voltage of the diode, I1t is the duration of the transient and I is the peak current the zener can
handle while still clamping the input voltage to the regulator.
As shown, the suppression circuit will clamp 70V, 4 ms tranSients on the unregulated supply.
11
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Figure 13. Suppression circuitry to remove large voltage spikes from unregulated supplies
S7
Overstressing series pass transistors has been the biggest
conclusions
cause of failures with IC regulators. This not only applies to
TheLM105'is an exact replacement for the LM100 in the
majority of applications, providing abOut ten times better . the transistors .within the IC, but also to the external booster
transistors. Hence, in designing a regulator, it i.s of ,utmost,
regulation. There are, however, a few differences: .
importance to determine the worst-case power dissipation
In switching regulator applicatlonS,2 the size of the resistor
in all the driver and pass transistors. Devices must tlien be
used to provide positive feedback should be doubled the
selected which can handle the power. Further, adequate
impedance seen looking back into the reference bypassterheat sinks must be provided as ellen power transistors cahminal is twice that of the LM100 (2 kG versus l' kG). In
not dissipate much power'by themselves.
addition, the minimum output voltage of the LM105 is 4.5V,
Normally, the highest power diSSipation occurs when the
compared with 2V for the LM100. In low voltage regulator
output of the regulator is shorted. If this condition requires
applications" the effect of this is obvious. However, it also
heat sinks which are so large as to be impractical, foldback
imposes some limitations on current regulator and shunt
current limiting can be used. With foldback limiting; the paw- . .
regulatOr deslgns.3 Lastly, clamping the compensation terer dissipated under short circuit conditions can actually be
minal (Pin 7) within a diode drop of ground or the output
made less than the dissipation at full load.
terminal will not guarantee that the regulator is shut off, as it
will with the LM100. This restricts the LM105 in the overload
The LM105 is designed primarily as a positive voltage regu-,
lator. A negative regulator, the LM 104, which is a functional
shutoff schemes3 which can be used with the LM100.
complement to the LM105, is described in Reference 4.
Dissipation limitations of practical packages dictate that the
output current of an IC regulator be less than 20 mAo Howreferences
ever, external booster transistors can be added to get any .
1. R. J. Widlar, "A Versatile, Monolithic Voltage Regulator",
output current desired. Even with satisfactory packages,
National Semiconductor AN-t, February, 1967.
considerably larger heat sinks would be needed if the pass
2. R. J. Widlar, "DeSigning Switching Regulators," National
transistors were put on the same chip as the reference and
.
Semiconductor AN-2, April, 1967.
control circuitry, because an IC must be run at a lower maximum temperature than a power transistor. In addition, heat
3. R. J. Widlar, "New Uses for the LM100 Regulator," Nationsl Semiconductor AN-8, June, 1968..
.
diSSipated in the pass transistor couples into the low level
circuitry and degrades. performance. All this suggests that
4. R. J. Widlar, "Designs for Negative Voltage Regulators,"
the pass transistor be kept separate from the IC.
National Semiconductor AN-2t, October, 1968.
as
38
A Simplified Test Set for Op
Amp Characterization
National Semiconductor
Application Note 24
M. Yamatake
INTRODUCTION
The test set described in this paper allows complete quantitative characterization of all dc operational amplifier parameters quickly and with a minimum of additional equipment.
The method used is accurate and is equally suitable for laboratory or production test-for quantitative readout or for
limit testing. As embodied here, the test set is conditioned
for testing the LM709 and LM10l amplifiers; however, simple changes discussed in the text will allow testing of any of
the generally available operational amplifiers.
POWER SUPPLY
BasiC waveforms and dc operating voltages for the test set
are derived from a power supply section comprising a positive and a negative rectifier and filter, a test set voltage
regulator, a test circuit voltage regulator, and a function generator. The dc supplies will be discussed in the section dealing with detailed circuit description.
The waveform generator provides three output functions, a
± 19V square wave, a -19V to + 19V pulse with a 1 % duty
cycle, and a ± 5V triangular wave. The square wave is the
basic waveform from which both the pulse and triangular
wave outputs are derived.
Amplifier parameters are tested over the full range of common mode and power supply voltages with either of two
output loads. Test set sensitivity and stability are adequate
for testing all presently available integrated amplifiers.
The paper will be divided into two sections, i.e., a functional
description, and a discussion of circuit operation. Complete
construction information will be given including a layout for
the tester circuit boards.
The square wave generator is an operational amplifier connected as an astable multivibrator. This amplifier provides
an output of approximately ± 19V at 16 Hz. This square
wave is used to drive junction FET switches in the test set
and to generate the pulse and triangular waveforms.
The pulse generator is a monostable multivibrator driven by
the output of the square wave generator. This multivibrator
is allowed to swing from negative saturation to positive saturation on the positive going edge of the square wave input
and has a time constant which will provide a duty cycle of
approximately 1%. The output is approximately -19V to
+19V.
FUNCTIONAL DESCRIPTION
The test set operates in one of three basic modes. These
are: (1) Bias Current Test; (2) Offset Voltage, Offset Current
Test; and (3) Transfer Function Test. In the first two of these
tests, the amplifier under test is exercised throughout its full
common mode range. In all three tests, power supply voltages for the circuit under test may be set at ± 5V, ± 10V,
±15V, or ±20V.
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FIGURE 1. Functional Diagram of BIas Current Test Circuit
39
The, bias current C\is~lay of Ifiqure 2 has the ,deted advantage that incipient breakdown' of the input stage of the device under t~st at the extremes .of, tI'Ie commofl mQde range
is easily detected. . '
, ,
::':"the triangular wave generator is a dc stabilized integrator
":,driveri by, the output of the square wave generator and pro, . vides a ±5V output at the square wave frequency, inverted
respect to the square wave.
, The p~rpose of these various outputs from the power supply
section will be discussed in the functional description.
. with
,
If either or both the upper or lower trace in the bias current
display exhibits curvature near the horizontal ends of the
oscilloscope face, then the bias current· ot· th'at input 'of the
amplifier is shown to be. dependent on common mode voltage. The usual causes of this dependency are ,low breakdown voltage of the differential input stage or current sink.
B~AS
CURRENTTEST,
A functional oiagram of the bias current test circuit js shown
in Figure 1. The, output of the triangular wave generator and
,the output of the test circuit, respectively, drive the horizontal and vertical deflection of an oscilloscope.
The device under test, (cascaded with the integrator, A7), is
connected in a differential amplifier configuration by R1, R2,
R3, and R4' The inputs of this .differential amplifier are driven
in common ,from the output of the triangular wave generator
through attenuator Rs and amplifier As. The inputs of the
device under test are connected to the feedback network
through resistors R5 and R6, shunted by the switch S5a and
S5b"
,
'
,
OFFS!riVOLTAGE,'OFFSEfCURRENTTiOST , ,.' ,
The offset voltage and offset current tests are performed in
the same gelJeral, way as the bias cur~eflt test. The only
pifference is that the switches S5a and S5b·are closed on
the same half-cyc;le of the triangular wave inpU1.
The synchronous operation of S5a and S5b forces the amplifier under test to Oraw its input currents through matched
high and low input resi,stors (In alternate halves of. the input
triangulijr wave. The difference between the voltage drop
across the two value;; of input resistors is propo,rtional to the
difference in input current to the two inputs, of the amplifier
under test and may be measured ,as the'verticalspacing
between the tWo traces appearin!! on the face of the' oscilloscope.
Offset voltage is measured as the vertical spacing,between
the trace corresponding to one of the two values of source
resistance and the zero volt baseline. Switch Ss and'Resistor Rg are a base line chopper"whose purpose is to provide
'a baseline reference which is, independent of test set 'and
oscilloscope drift. 56 is driven from the pulse output of the
function generator and has a duty cycle of approximately
1% of the triangular wave.
Figure 3 is a photograph of the various waveforms present,ed during this test. Offset voltage and offset current are
displayed at a sensitivity of 1 mV and 100 nA per divillion,
respectively, and both parameters are displayed over a
common mode range of, ± 10V.
The feedback network provides a closed loop gain of 1,000
and the, integrator time constant serves to reduce noise at
the output of the test circuit as well as allowing the output of
the device unde,r test to remain near zero volts. ,
The bias current tellt is accomplished by allowing the device
, under test to draw input current to one of its il)puts through
the corresponding input, resistor on positive going 01', negative going halves of the triangular wave generator, output.
. This is accomplished by closing S5a or S5b on alternate
halves of the triangular wave input. The voltage appearing
across the input resistor is equal to input current times the
input resistor. This voltage is multiplied by 1,000 by the
feedback loop and appears at the integrator output and the
vertical input of the oscilloscope. The vertical separaton of
the traces representing the two input currents of the amlllifier under test is equivalent to the total bias current of the
amplifier under test.
The bias current over the entire common mode range may
be examined by setting the output of As equal to the amplifier common mode range. A photograph of the bias current
oscilloscope display is given as Figure 2. In this figure, the
total input current of an amplifier is displayed over a ± 10V
common mode range with a sensitivity of 10P nA per vertical
division.
TLlH/7190-3
FIGURE 3. Offset Voltage, Offset Current
and Common Mode Rejection Display
TL/HI7190-2
FIGURE 2. Bias Current and Common
Mode Rejection Display
40
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TL/HI7190-4
FIGURE 4. Functional Diagram of Transfer Function Circuit
TRANSFER FUNCTION TEST
A functional diagram of the transfer function test is shown in
Figure 4. The output of the triangular wave generator and
the output of the circuit under test, respectively, drive the
horizontal and vertical inputs of an oscilloscope.
The device under test is driven by a ±2.5 mV triangular
wave derived from the ±5V output of the triangular wave
generator through the attenuators R 11, R12, and R1, Ra and
through the voltage follower, A7. The output of the device
under test is fed to the vertical input of an oscilloscope.
Amplifier A7 performs a dual function in this test. When 57 is
closed during the bias current test, a voltage is developed
across C1 equal to the amplifier offset voltage multiplied by
the gain of the feedback loop. When 57 is opened in the
transfer function test, the charge stored in C1 continues to
provide this offset correction voltage. In addition, A7 sums
the triangular wave test signal with the offset correction voltage and applies this sum to the input of the amplifier under
test through the attenuator R1, Rs. This input sweeps the
input of the amplifier under test ±2.5 mV around its offset
voltage.
Figure 5 is a photograph of the output of the test set during
the transfer function test. This figure illustrates the function
of amplifier A7 in adjusting the dc input of the test device so
that its transfer function is displayed on the center of the
oscilloscope face.
TL/HI7190-5
FIGURE 5. Transfer Function Display
Gain is displayed as the slope, a VOUT' aVIN of the transfer
function. Gain linearity is indicated change in slope of the
VOUTIVIN display as a function of output voltage. This display is particularly useful in detecting crossover distortion in
a Class B output stage. Output swing is measured as the
vertical deflection of the transfer function at the horizontal
extremes of the display.
The transfer function display is a plot of VIN va VOUT for an
amplifier. This display provides information about three amplifier parameters: gain, gain linearity, and output swing.
41
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FIGURE 6. Power Supply and Function Generator
DETAILED CIRCUIT DESCRIPTION
comprising R7, Rs, Rg, R,O, and R26. ThE!' output of this,
divider is + 10V to + 2.5V according to the position of S2a
and is fed to the non-inverting, gain-of-two amplifier, A2. A2
is powered from +28V and provides +20V to +5V at its
output. A3 is a unity gain inverter whose input is the output
of A2 and which is powered from -28V. The c6mphilmentsry outputs of amplifiers A2 and A3 provide dc power to the
circuit under test.
POWER SUPPLIES
As shown in Figure 6, which is a comple,te schematic of the
poWer supply and function generator, two power supplies
are provided in the test set. One supply provides a fixed
± 20V to power the circuitry in the test set; the other provides ± 5V to ± 20V to power the circuit under test.
The test set power supply regulator accepts + 28V from the
positive rectifier and filter and provides + 20V through the
LM100 positive regulator. Amplifier A, is powered from the
negative rectifier and filter and operates as a unity gain inverter whose input is + 20V from the positive regulator, and
whose output is -20V.
LM101 amplifiers are used as A2 and Aa to allow operation
from one ground referenced voltage each and to provide
protective current limiting for the device under test.
FUNCTION GENERATOR
The function generator provides three outputs, a ± 19V
square wave, a -19V to + 19V pulse having a 1 % duty
cycle, and a ±5V triangular wave. The square wave is the
The test circuit power supply is referenced to the + 20V
output of the positive regulator through the variable divider
42
operated synchronously from the output of 011. During the
transfer function test, Oa and 07 are switched on continuously by turning off 011. R42 and R4S maintain the gates of
the FET switches at zero gate to source voltage for maximum conductance during their on cycle. Since the sources
of these switches are at the common mode input voltage of
the device under test, these resistors are connected to the
output of the common mode driver amplifier, As.
The input for the integrator-feedback buffer, A7, is selected
by the FET switches 04 and Os. During the bias current and
offset voltage offset current tests, A7 is connected as an
integrator and receives its input from the output of the davice under test. The output of A7 drives the feedback resistor, R40. In this connection, the integrator holds the output
of the device under test near ground and serves to amplify
the voltages corresponding to bias current, offset current,
and offset voltage by a factor of 1,000 before presenting
them to the measurement system. FET switches 04 and 05
are turned on by switch section Sl b during these tests.
FET switches 04 and Os are turned off during the transfer
function test. This disconnects A7 from the output of the
device under test and changes it from an integrator to a
non-inverting unity gain amplifier driven from the triangular
wave output of the function generator through the attenuator R33 and R34 and switch section Sla. In this connection,
amplifier A7 serves two functions; first, to provide an offset
voltage correction to the input of the device under test and,
second, to drive the input of the device under test with a
± 2.5 mV triangular wave centered about the offset voltage.
During this test, the common mode driver amplifier is disabled by switch section Sl a and the vertical input of the
measurement oscilloscope is transferred from the output of
the integrator-buffer, A7, to the output of the device under
test by switch section Sl d. S2a allows supply voltages for
the device under test to be set at ± 5, ± 10, ± 15, or ± 20V.
S2b changes the vertical scale factor for the measurement
oscilloscope to maintain optimum vertical deflection for the
particular power supply voltage used. S4 is a momentary
contact pushbutton switch which is used to change the load
on the device under test from 10 kG to 2 kG.
A delay must be provided when switching from the input
tests to the transfer function tests. The purpose of this delay
is to disable the integrator function of A7 before driving it
with the triangular wave. If this is not done, the offset correction voltage, stored on C16, will be lost. This delay between opening FET switch 04, and switch Os, is provided by
the RC filter, R3S and C19.
Resistor R41 and diodes 07 and De are provided to control
the integrator when no test device is present, or when a
faulty test device is inserted. R41 prOVides a dc feedback
path in the absence of a test device and resets the integrator to zero. Diodes ~ and 08 clamp the input to the integrator to approximately ±. i vol1s when a faulty device is inserted.
FET switch 01 and reSistor R28 provide a ground reference
at the beginning of the 50-ohm-source, offset-voltage trace.
This trace provides a ground reference which is independent of instrument or oscilloscope calibration. The gate of
01 is driven by the output of monostable multlvibrator A5,
and shorts the vertical oscilloscope drive Signal to ground
during the time that As output is positive.
basic function from which the pulse and triangular wave are
derived, the pulse is referenced to the leading edge of the
square wave, and the triangular wave is the inverted and
integrated square wave.
Amplifier A4 is an astable multivibrator generating a square
wave from positive to negative saturation. The amplitude of
this square wave is approximately ± 19V. The square wave
frequency Is determined by the ratio of Rla to R1S and by
the time constant, R17Cg. The operating frequency is stabilized against temperature and power regulation effects by
regulating the feedback signal with the divider R19, Os and
Da·
Amplifier As is a monostable multivibrator triggered by the
positive going output of ~. The pulse width of As is determined by the ratio of R20 to R22 and by the time constant
R21Cl0. The output pulse of As is an approximately 1% duty
cycle pulse from approximately -19V to + 19V.
Amplifier As is a dc stabilized integrator driven from the amplitude-regulated output of ~. Its output is a ± 5V triangular
wave. The amplitude of the output of As is determined by
the square wave voltage developed across 05 and Os and
the time constant Radi C14. DC stabilization is accomplished
by the feedback network R24, R2S, and C1S. The ac attenuation of this feedback network is high enough so that the
integrator action at the square wave frequency is not degraded.
Operating frequency of the function generator may be varied by adjusting the time constants associated with A4, A5,
and As in the same ratio.
TEST CIRCUIT
A complete schematic diagram of the test circuit is shown in
Figure 7. The test circuit accepts the outputs of the power
supplies and function generator and provides horizontal and
vertical outputs for an X-V oscilloscope, which is used as
the measurement system.
The primary elements of the test circuit are the feedback
buffer and integrator, comprising amplifier A7 and its feedback network Cla, R31, R32, and C17, and the differential
amplifier network, comprising the device under test and the
feedback network R40, R43, R44, and RS2. The remainder of
the test circuit provides the proper conditioning for the davice under test and scaling for the oscilloscope, on which
the test results are displayed.
The amplifier Aa provides a variable amplitude source of
common mode signal to exercise the amplifier under test
over its common mode range. This amplifier is connected as
a non-inverting gain-of-3.6 amplifier and receives its input
from the triangular wave generator. Potentiometer R37 allows the output of this amplifier to be varied from ± 0 volts
to ± 18 volts. The output of this amplifier drives the differential input resistors, R43 and ~, for the device under test.
The resistors R4S and R47 are current sensing resistors
which sense the input current of the device under test.
These resistors are switched into the circuit in the proper
sequence by the field effect transistors Os and 07. Oa and
07 are driven from the square wave output of the function
generator by the PNP pair, 010 and 011, and the NPN pair,
08 and 09. Switch sections Slb and Slc select the switching sequence for 08 and 09 and hence for Os and 07. In
the bias current test, the FET drivers, 08 and 09, are
switched by out of phase signals from 010 and 011. This
opens the FET switches Oa and 07 on alternate half cycles
of the square wave output of the function generator. During
the offset voltage, offset current test, the FET drivers are
Switch S3, R27, and R28 provide a 5X scale increase during
input parameter tests to allow measurement of amplifiers
with large offset voltage, offset current, or bias current.
Switch Ss allows amplifier compensation to be changed for
101 or 709 type amplifiers.
43
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TUH/7190-7
FIGURE 7. Test Circuit
CALIBRATION
Calibration of the test system is relatively simple and reo
quires only two adjustments. First, the output, of the main
regulator is set up for 20V. Then, the triangular wave gener~
ator is adjusted to provide ± SV output by seleCting Rad].
This sets, the horjzontal sweep for. the Y oscilloscope
used as the measurement system. The oscilloscope is then
set up for 1VI division vertical and'ior a full 10 division hori·
zontal sweep.
Scale factors for the three, test positions ,are:
1. Bias Current Display (Figure 2)
100 nA/div. vertical
Ibias total
Common Mode Voltage
Variable horizontal
2. Offset Voltage-OHset Curtent (Figure 3)
loffsat
'
1PO riA/div. vertical
3. Transfer Function (Figure 5)
VIN
O.S mVldiv.
SVldiv. @ Vs
SV/div. @ Vs
2V/div.@Vs
1V/div. @ Vs
VOUT
x·
Voffsat
Common Mode Voltage
Gain =
±20V
±1SV
±10V
±SV
~VOUT
~VIN
CONSTRUCTION
Test set construction is simplified through the use of inte·
grated circuits and etched circuit layout.
Figure 8 gives photographs of the completed tester. F/{/ure
9, shows the parts location for the components on the circuit
board layout of Figure 10. An attempt should be made to
1 mVldiv. vertical
variable horizontal
44
adhere to this layout to insure that parasitic coupling be·'
tween elements will not cause oscillations or give calibration
problems.
Grayhill 30·1 Series 30 subminiature
pushbutton switch
55.56
Table I is a listing of special components which are needed
to fit the physical layout given for the tester.
TABLE I. Partial Parts List
T1
S1
Triad F·90X
Centralab PA2003 non·shorting
S2
Centralab PA2015 non·shorting
Alcoswitch MST·1050 SPOT
CONCLUSIONS
A semi·automatic test system has been described which will
completely test the important operational amplifier parameters over the full power supply and common mode ranges.
The system is simple. inexpensive. easily calibrated. and is
equally suitable for engineering or quality assurance usage.
TLlHI7190-8
FIGURE 8a. Bottom of Test Set
45
~ r---------~-------------------------------------------------------------------
c
TlIHI7190-10
FIGURE 8c. Jacks
46
--+-
--1"'--~
-C13
-1---
"r~:K
-~~~~oo~
L - - _ ..
-C12
r
" ._
------
TL/HI7190- "
FIGURE 9. Component Location, Top View
47
TL/HI7190-12
FIGURE 10. Circuit Board Layout
48
National Semiconductor
Application Note 29
ICOp Amp Beats FETs
on Input Current
Robert J. Widlar
Apartado Postal 541
Puerto Valiarta, Jalisco
Mexico
abstract
A monolithic operational amplifier having input error cur·
rants in the order of 100 pA over a - 55'C to 125'C temper·
atura range is described. Instead of FETs, the circuit used
bipolar transistors with cu"ent gains of 5000 so that offset
voltage and drift are not degraded. A power consumption of
1 mWat low voltage is also featured.
10.7
~
z 10"
;=
...
...
-
==
~
LM709
I
II!
II!
...=Co>
~
A number of novel circuits that make use of the low currant
characteristics of the amplifier ara given. Further, special
design techniques required to take advantage of these low
currents ara explored. Component selection and the treat·
ment of printed circuit bpards is also covered.
.....=-
10"
......... -
-'
--
C7
10.1•
!!!
LMIOIA
~~
FET=
LMID8
10.11 L......J...--L_.L-..L~_L.......L.....J
·75 -50 -25 0 25 50 75 100 125
Introduction
A year ago, one of the loudest complaints heard about IC op
amps was that their input currents were too high. This is no
longer the case. Today ICs can provide the ultimate in per·
formance for many applications---even surpassing FET am·
pllfiers.
TEMPERATURE rC)
TL/H/6875-1
Figure 1. Comparing IC op amps with FET-input amplifier
log switches or printed circuit boards, rather than by the op
amp itself.
FET input stages have long been considered the best way
to get low input currents in an op amp. Low·picoamp input
currents can in fact be obtained at room temperature. How·
ever, this current, which is the leakage current of the gate
junction, doubles every 10'C, so performance is severely
degraded at high temperatures. Another disadvantage is
that it is difficult to match FETs closely. 1 Unless expensive
selection and trimming techniques are used, typical offset
voltages of 50 mV and drifts of 50 p.W'C must be tolerated.
Super gain transistors2 are now challenging FETs. These
devices are standard bipolar transistors which have been
diffused for extremely high current gains. Typically, current
gains of 5000 can be obtained at 1 p.A collector currents.
This makes it possible to get input currents which are com·
petitive with FETs. It is also possible to operate these tran·
sistors at zero collector base voltage, eliminating the leak·
age currents that plague'the FET. Hence they can provide
lower error currents at elevated temperatures. As a bonus,
super gain transistors match much better than FETs with
typical offset voltages of 1 mV and drifts of 3 p.V/'C.
effects of error current
In an operational amplifier, the input current produces a volt·
age drop across the source resistance, causing a de error.
This effect can be minimized by operating the amplifier with
equal resistances on the two inputs. 5 The error is then pro·
portional to the difference in the two input currents, or the
offset current. Since the current gains of monolithic transis·
tors tend to match well, the offset current is typically a factor'
of ten less than the input currents.
;; 100
.!
...
TA = 2S'C
'"c
!:;
C7
>
......'"
:t
...=...!!!z
.......
.
10
§~~~ ~)~
c
>
:;
...
C7
~
/
1.0
I
~ E'~~~
I--~ r==-~r- r--'"
C7
Figura 1 compares the typical input offset currents of IC op
amps and FET amplifiers. Although FETs give superior per·
formance at room temperature, their advantage is rapidly
lost as temperature increases. Still, they are clearly better
than early IC amplifiers like the LM709.3 Improved devices,
like the LM101A,4 equal FET performance over a -55'C to
125'C temperature range. Yet they use standard transistors
in the input stage. Super gain transistors can provide more
than an order of magnitude improvement over the LM101A.
The LM108 uses these to equal FET performance over a
O'C to 70'C temperature range.
In applications involving 125'C operation, the LM108 is
about two orders of magnitude better than FETs. In fact,
unless special precautions are taken, overall circuit perform·
ance is often limited by leakages in capacitors, diodes, ana·
I
/'
./
I
V
Vas =Vos + Rs los
=
I
0.1
Ik
10k
lOOk
1M
10M 100M IG
INPUT RESISTANCE In)
TL/H/6875-2
Figure 2. Illustrating the effect of source resistance on
typical Input error yoltage
Naturally, error current has the greatest effect in high im·
pedance circuitry. Figure 2 illustrates this point. The offset
voltage of the LM709 is degraded significantly with source
resistances greater than 10 kO. With the LM101A this is
extended to source resistances high as 500 kO. The
LM1 08, on the other hand, works well with source resistanc·
es above 10 MO.
Reprinted from ££E, December 1969.
49
Applications that require low error currents include amplifiers for photodiodes or capacitive transducers, as these usually operate at megohm impedance. levels. Sample-andhold-circuits, timers, integratdrs and analog memories also
benefit from low error currents. For example, with the
LM709, worst case drift rates for these kinds of circuits is in
the order of 1.5 V/sec. The LM10S improves this to 3 mVI
sec.-worst case over a - 55°C to 125°C temperature
range. Low input currents are also helpful in oscillators and
active filters to get low frequency operation with reasonable
capacitor values. The LM10S can be used at a frequency of
1 Hz with capacitors no larger than 0.01 "F. In logarithmic
amplifiers, the dynamic range can be extended by nearly 80
dB by going from the LM709 to the LM10S. In other applications, having low error currents often permits an entirely different design approach which can greatly simplify circuitry.
'High. source resistances have an even greater effect on the
drift of an amplifier, as shown in Figure 3. The performance
of lhe LM709 is worsened with sources greater than 3 kO.
The LM101A holds out to 100 kO sources, while the LM10S
still works well at 3 MO.
..
....
1000~m
....>
100
0-
10
..!
II:
co
II:
a::
ii
co
theLM108
1.0 L..--'-_--I...._.L-....J._-L_..1
lk 10k lOOk 1M 10M 100M lG
Figure 4 shows a simplified schematic of the LM10S. Two
kinds of NPN transistors are used on the IC chip: super gain
(primary) transistors which have a current gain of 5000 with
a breakdown voltage of 4V and conventional (secondary)
transistors which have a current gain of 200 with an SOV
breakdown. These are differentiated on the schematic by
drawing the secondaries with a wider base.
INPUT RESISTANCE ISl)
TL/H/6875-3
Figure 3. Degradation of typical drift characteristiCS
with high source resistances
It is difficult to include FET amplifiers in Figure 3 because
their drift is initially 50 "VloC, unless they are selected and
trimmed. Even though their drift may be well controlled' (5
"V fOC) over a limited temperature range, trimmed amplifiers
generally exhibit a much higher drift over a -55°C to 125°C
temperature range. At any rate, their average drift rate
would, at best, be like that of the LM101A where 125°C
operation is involved.
Primary transistors (01 and 02) are used for the input stage;
and they are operated in a cascode connection with Os and
06. The bases of Os and 06 are bootstrapped to the emitters of 01 and 02 through 03 and 04, so that· the input
transistors are pperated at zero collector-base voltage.
. Hence, circuit performance is not impaired by the low breakdown of the primaries, as the secondary transistors stand
COMPENSATION
r-------~---------e~--~-----------------t~~--~-------v+
Rl
20K
R2
20K
. .----'OUTPUT
INPUTS 01
..
+~--
~+-----~~-----{
~----~----------------~I-------~----e------v-
TL/H/6875-4
Figure 4. Simplified schematic of the LM108
50
off the commom mode voltage. This configuration also improves the commom mode rejection since the input transistors do not see variations in the commom mode voltage.
Further, because there is no voltage across their collectorbase junctions, leakage currents in the input transistors are
effectively eliminated.
There has been conSiderable discussion about using Darlington input stages rather than super gain tranSistors to
obtain low input currents.8, 7 It is appropriate to make a few
comments about that here.
Darlington inputs can give about the same input bias currents as super gain transistors-at room temperature. However, the bias current varies as the square of the transistor
current gain. At low temperatures, super gain devices have
a decided advantage. Additionally, the offset current of super gain transistors is considerably lower than Darlingtons,
when measured as a percentage of bias current. Further,
the offset voltage and offset voltage drift of Darlington transistors is both higher and more unpredictable.
Experience seems to tell the real truth about Darlingtons.
Ouite a few op amps with Darlington input stages have been
introduced. However, none have become industry standards. The reason is that they are more sensitive to variations in the manufacturing process. Therefore, satisfactory
performance speCifications can only be obtained by sacrificing the manufacturing yield.
The Second stage is a differential amplifier using high gain
lateral PNPs (Og and 010).6 These devices have current
gains of 150 and a breakdown voltage of 80V. Al and A2
are the collector load resistors for the input stage. 07 and
08 are diode connected laterals which compensate for the
emitter-base voltage of the second stage so that its operating current is set at twice that of the input stage by A4.
The second stage uses an active collector load (015 and
016) to obtain high gain. It drives a complementary class-B
output stage which gives a substantial load driving capability. The dead zone of the output stage is eliminated by biasing it on the verge of conduction with 011 and 012.
Two methods of frequency compensation are available for
the amplifier. In one a 30 pF capacitor is connected from the
input to the output of the second stage (between the compensation terminals). This method is pin-compatible with the
LM101 or LM101A. It can also be compensated by connecting a 100 pF capacitor from the output of the second stage
to ground. This technique has the advantage of improving
the high frequency power supply rejection by a factor of ten.
A complete schematic of the LM108 is given in the Appendix along with a description of the circuit. Tl:lis includes such
essential features as overload protection for the inputs and
outputs.
eao
501
1... 400
. ,,-
......
a: 300
a::
>- 200
...'"t
100
performance
o
The primary design objective for the LM108 was to obtain
very low input currents without sacrificing offset voltage or
drift. A secondary objective was to reduce the power consumption. Speed was of little concern, as long as it was
comparable with the LM709. This is logical as it is quite
difficult to make high-impedance circuits fast; and low power
circuits are very resistant to being made fast. In other respects, it was desirable to make the LM1 08 as much like the
LM101A as possible.
i...
...a:
a:
...£
..
...
1.0
......
....
0.&
!! 0.1.
0.0&
•
......
LUI ..
-55 -35 -IS 5
'
I.
LUI ..
12I"C
15
20
TL/H/687S-6
Figure 6_ Supply current
The supply current of the LM 108 is plotted as a function of
supply voltage in Figure 6. The operating current is about an
order of magnitude lower than devices like the LM709. Furthermore, it does not vary radically with supply voltage
which means that the device performance is maintained at
low voltages and power consumption is held down at high
voltages.
.IAS
r""'" ....;;~
-
TA
SUPPL VVOLTAGE (±VI
15
r-
0.1&
-
TA = 25°C
"".
5
2.0
1.&
TA ' _55°C
. I.
i
i"'Oo
--~
OffSET
~
l/"
T~~21~C/
TEMPERATURE (OCI
TUH/687S-S
o
Figure 5. Input currents
Figure 5 shows the input current characteristics of the
LM108 over a -55°C to 125°C temperature range. Not only
are the input currents low, but also they do not change radically over temperature. Hence, the device lends itself to relatively simple temperature compensation schemes, that will
be described later.
, 1\
VI· ±lIiV
LUi"
TA = 125·C
o
2S 45 &5 15 IDS 125
-"
TA' -55·C
o
1.00
..-
~ "':,...
./'
V
·2
OUTPUT CURRENT (unAl
TUH/687S-7
Figure 7. Output swing
The output drive capability of the circuit is illustrated in Figure 7. The output swings to within a volt of the supplies,
51
which is especially important when operating at low voltages. The output falls off rapidly as the current increases
above a certain level and the short circuit protection goes
into effect. The useful output drive is limited to about
±2 mA. It could have been increased by the addition of
Darlington' transistors on the output, but this would have
restricted the voltage swing at low supply voltages. The amplifier, incidentally, works with common mode signall/ to
within a volt of the supplies so it can be used with supply
voltages as low as ±2V.
With unity gain compensation, both methods give a 75-de-,
gree stability margin., However, the shunt compensation has
a 300 ,kHz small Signal bandwidth as opposed tGl ,1 MHz for
the other soheme. Because the compensation capac;itGlr is
not included on the IC'chip, it can be, tailored to ,fit ,the appli,
cation. When the amplifier is used only at low:frequllncies.
the compensation capacitor can be Increased to give a
greater stability margin. Thill makes the circuit less sensitive
to capacitive loading. slrllY Capacitances or improper supply
bypassing. Overcompensating also reduces the high frequencY noi~ outPut of the amplifier.
With closed-loop,gains greater than one. Itte high frequency
performance can be optimized by making the compensation
capacitor smaller. If unity-gain compensation is used for an
amplifier with a gain of ten, the gain error will exceed 1-per;
cent at frequencies above 400 Hz. This can be, extended to
4 kHz by reducing the compensation capaCitor ,to 3 pF. The
formula for determining Ihe minimum 'capacitor value is giv,en in Figure 9a., It should be noted that the capaCitor value
does not really depend on the closed-loop gain. In!\tead, it
depends on the high frequency attenuation in the feedback
networks and, therefore, the values of R1 and R2. When it is
desirable to optimize performance at high frequencies, the
standard compensation should be used. With smail capacitor values. the stability margin obtained With shunt compensation i,s inadequate'for conservative designs.
The frequency response of an operational amplifier is considerably different for large output signals than it is for small
signals. This, is indicated in' Figure 10. With unity,gain compensation, the small signal bandwidth of the LM108 Is 1
MHz. Yet full output swing cannot be obtained above 2 kHz.
This corresponds to a slew rate of 0.3 V/ p.s. Both the fulloutput bandwidth and the slew rate can be, increased by
using smaller compensation capaCitors. as is indicated in
the figure. However, this is only applicable for higher closed
loop gains. The results plottEld in Figure 10 are for standard
compensations. With ,unity gain compensation" the' same
curves are obtained for the shunt compensation scheme.
Classical op amp theory establishes output resistance as an
Important design parameter. This is not true for IC op amps:
The output resistance of most devices is low enough that it
can be Ignored, because they use class-B output stages. At
low frequencies, thermal feedback between the output and
120
100
'ii
:!!
..
.
~
,C
,co
'" "-'"
10
10
~
40
co
20
>
~ ~ Ct" 3PF-1- cr= 3 PFm-
GAIN
C. =100 pf---1
""-
-
LMI~--tI
10
101
"
'C;-
135 :;
~
ID
i
30 pF
""
'H~-I--
-ZI
....
'V--
110
Cs=IOG:~ ~
~Ct- 30pF
Ik
I... lOOk 1M IDM
FREOUENCY (Hzl
TL/H/6875-8
Figure 8. Open loop frequency response
The open loop frequency response, plotted in Figure 8, indicates that the frequency response is about the same as that
of the LM709 or the LM101A. Curves are given for the two
compensation circuits shown In Figure 9. The standard
compensation is Identical to that of the LM101 or LM101A.
The alternate compensation scheme gives much better rejection of high frequency power supply noise, as will be
shown later.
R2
RI
VOUT
R3
~"' R~~~2
Co
1&
= 30pF
\
12
TL/H/8875-9
,
TA - 25'C
Va - :tI6V
111111
C,-3pF
a. standard compensstlon Circuit
RI
lUll
RZ
• 3D pF
,
'
~
LMI08
Vour
I.
R3'
Cs
10k
lDOk
1M
FREQUENCY (Hz)
~'OOPF
TL/H/6875-11
Figure 10. Large signal frequency response
TLlH/6875-10
b. alternate compensatlo,:, circuit
Figure 9. Compensation Circuits
52
input stages determines the effective output resistance, and
this cannot be accounted for by conventional design theories. Semiconductor manufacturers take care of this by
specifying the gain under full load conditions, which combines output resistance with gain as far as it affects overall
circuit performance. This avoids the fictitious problem that
can be created by an amplifier with infinite gain, which is
good, that will cause the open loop output resistance to
appear infinite, which is bad, although none of this affects
overall performance Significantly.
III'
120
100
;;
..•
:a ID
u
JiG
0:
..
40
.
2D
~
:0
,......,.".....-...---.--r--r=--..
-2D '-_.l.---I_-1_--1-_.....J
100
Ik
10k
lOOk 1M
10M
FREQUENCY (Hz)
§ 10>
rJ
TL/H/6875-13
•
.....
Figure 12. Power supply rejection
c
Av ·I.C!=30pF
Av '1010. cia 0 pF
~
...
.
;::
13
Power supply rejection is defined as the ratio of the change
in offset voltage to the change in the supply voltage producing it. Using this definition, the rejection at low frequencies is
unaffected by the closed loop gain. However, at high frequencies, the opposite is true. The high frequency rejection
is increased by the closed loop gain. Hence, an amplifier
with a gain of ten will have an order of magnitude better
rejection than that shown in Figure 12 in the Vicinity of
100 kHz to 1 MHz.
The overall performance of the LM108 is summarized in
Table I'. It is apparent from the table and the previous discussion that the device is ideally suited for applications that
require low input currents or reduced power consumption.
The speed of the amplifier is not spectacular, but this is not
usually a problem in high-impedance Circuitry. Further, the
reduced high frequency performance makes the amplifier
easier to use in that less attention need be paid to capacitive loading, stray capacitances and supply bypassing.
Av·ltioa.C!~30pF
r
r
~:0
TA ·25°t
lOUT- t1 ..A
V.' .\lV
Ie-'
10"
10
100
Ik
10k
lOOk 1M
10M
FREQUENCY (HI)
TL/H/6875-12
Figure 11. Closed loop output impedance
The closed loop output impedance is, nonetheless, important in some applications. This is plotted for several operating conditions in Figure 11. It can be seen that the output
Impedance rises to about 5000 at high frequencies. The
increase occurs because the compensation capaCitor rolls
off the open loop gain. The output resistance can be reduced at the intermediate frequencies, for closed loop gains
greater than one, by making the capacitor smaller. This is
made apparent in the figure by comparing the output resistance with and without frequency compensation for a closed
loop gain of 1000.
The output resistance also tends to increase at low frequencies. Thermal feedback is responsible for this phenomenon.
The data for Figure 11 was taken under large-signal conditions with ± 15V supplies, the output at zero and ± 1 mA
current swing. Hence, the thermal feedback is accentuated
more than would be the case for most applications.
applications
Because of its low input current the LM108 opens up many
new design possibilities. However, extra care must be taken
in component selection and the assembly of printed circuit
boards to take full advantage of its performance. Further,
unusual design techniques must often be applied to get
around the limitations of some components.
sample and hold circuits
The holding accuracy of a sample and hold is directly related to the error currents in the components used. Therefore,
it is a good circuit to start off with in explaining the problems
In an op amp, it is desirable that performance be unaffected
by variations in supply Voltage. IC amplifiers are generally
better than discretes in this respect because it is necessary
for one single design to cover a wide range of uses. The
LM108 has a power supply rejection which is typically in
excess of 100 dB, and it will operate with supply voltages
from ±2V to ±20V. Therefore, well-regulated supplies are
unnecessary, for most applications, because a 20-percent
variation has little effect on performance.
The story is different for high-frequency noise on the supplies, as is evident from Figure 12. Above 1 MHz, practically
all the noise is fed through to the output. The figure also
demonstrates that shunt compensation is about ten times
better at rejecting high frequency noise than is standard
compensation. This difference is even more pronounced
with larger capacitor values. The shunt compensation has
the added advantage that it makes the circuit virtually unaffected by the lack of supply bypassing.
SAMPLE _ _ _ _. ._..,
INPUTr-. .-
....
C2
30pF
TLlH/6875-14
Figure 13. Sample and hold circuit
involved. Figure 13 shows one configuration for a sample
and hold. During the sample interval, Q1 is turned on, charging the hold capacitor, C1, up to the value of the input Signal.
'See Appendix Heading In This Appllcalion Note.
53
When 0, is turned off, C, retains this voltage. The output is
obtained from an op amp that buffers the 'capacitor so that it
is not discharged by any loading. In the holding mode, an
error is generated as the capacitor looses charge to supply
circuit leakages. The accumulation rate for error is given by
dV
tlve diodes on the, gates,. special arrangements must be
made to drive 02 so' ,the diode does not become forward
biased.
In selecting the hold capacitor, low leakage is not the only
requirement. The capacitor mulit also be free of dielectric
polarization phenomena: 8 This rules out such types as paper, mylar, electrolytic, tantalum or high-K· ceramic. For
small capaeitor values, glass'or silvered-mica capacitors are
recommended. For the larger values, ones with teflon, polyethylene or polycarbonate dielectrics should be used.
IE
dt= C,'
where dVIdt is the time rate of change in output voltage and
IE is the sum of the input current to the op amp, the leakage
current of the holding capacitor, board leakages and the
"off" current of the FET switch.
The low input current of the LM108 gives a drift rate, in hold,
of only 3 mVisec when a 1 /'oF hold capaCitor is used. And
this number is worst case over the military temperature
range. Even if this kind of performance is not needed, it may
still be beneficial to use the LM108 to reduce the size of the
hold capaCitor. High quality capaCitors in the' larger sizes are
bulky and expensive. Further, the switches must have a low
"on" reSistance and,be driven from a low impedance source
to charge large capacitors in a short period of time.
When high-temperature operation is involved, the FET leakage can limit circuit performance. This can be minimized by
using a junction FET, as indicated, because commercial
junction FETs have lower leakage than theil"' MOS counterparts. However, at 125°C even junction devices are a problem. Mechanical sWitches, such as reed relays, are quite
satisfactory from the standpoint of leakage. However, they
are often undesirable because they are sens~ive to vibration, they are too slow or theY require excessive drive power: If this is the case, the circuit in F/{Jure 14 can be used to
eliminate the,FET leakage.
If the sample interval is less than about 100 /'os, the LM 108
may not be fast enough to 'work properly. If this is the case,
it is advisable to substitute the LM102A,9 which is a voltage
follower designed for both low input current and high speed.
It has a 30 VI /'os slew rate and will operate with sample
intervals as short as 1 /'os.
INPUT
When the hold capacitor is larger than 0.05 /'oF, an isolation
resistor should be included between the capacitor and the
Input of the amplifier (R2 in Figure 14). This resistor insures
that the IC will not be damaged by shorting the output or
abruptly shutting down the supplies when the capacitor,is
charged. This precaution is not peculiar to the LM108 and
should be observed on any IC op amp.
OUTPUT
Integrators
cz
3G,F
Integrators are.a lot like sample-and-hold circuits and have
essentially the same design problems. In an integrator, a
capacitor is used as a storage element; and the error accumulation rate is again proportional to the input current of the
cipamp.
TL/H/687S-is
trellon, polyethylene or polycarbonele dielectric capacitor
Worst case drift Ie.. trnIn 3 mVlsec
Figure 14. Sample and hold ,that eliminates leakage In
FET switches
Figure 15 shows a circuit that can compensate for. the bias
current of the amplifier. A current is fed into the, summing
node through R,10 supply the bias current. The potentiometer, R2, is adjusted so that this current exactly equals the
bias current, reducing the drift rate to zero.
When using P-channel MOS sWitches, the substrate must
be connected to a voltage which is always more positive
than the input signal. The source-to-substrate junction becomes forward biased if this ,is not done. The troublesome
leakage current, of a MOS device occurs across the substrate-to-drain junction. In Figure 14, this current is routed to
the output of the buffer amplifier through R, so that it does
not contribute to the error current.
R3
I50K
r--"'-""'''''- v+
The main sample switch is 0" while 02 isolates the hold
capaCitor from the leakage of 0,. When the sample pulse is
applied, both FETs tum on charging C, to the input voltage.
Removing the pulse shuts off both FETs, and the output
leakage of 0, goes through R1 to the output. The voltage
drop across R, is less than 10 mV, so the substrate of 02
can be bootstrapped to the output of the LM 108. Therefore,
the voltage across the substrate-drain junction is equal to
the offset 'voltage of the amplifier. At this low voltage, the
leakage of the FET is reduced by about two orders of magnitude.
INPUT-~M_•
. , . . . - - - - - -...
~~""'-IOUTPUT '
It is necessary, to use MOS switches when bootstrapping
the leakages in this fashion. The gate leakage of aMOS
device is still negligible at high temperatures; this is not the
case with junction FETs. If the MOS transistors have protec-
TllH/6875-16
Figura 15. Integrator with bias current compensation
54
The diode is used for two reasons. First, it acts as a regulator, making the compensation relatively insensitive to variations in supply voltage. Secondly, the temperature drift of
diode voltage is approximately the same as the temperature
drift of bias current. Therefore, the compensation is more
effective if the temperature changes. Over a O'C to 70'C
temperature range, the compensation will give a factor of
ten reduction in input current. Even better results are
achieved if the temperature change is less.
currents. At the end of the integration interval, Os removes
the compensating error accumulated on C2 as the circuit is
reset.
In applications involving large temperature changes, the circuit in Figure 16 gives better results than the compensation
scheme in Figure 15-especially under worst case conditions. Over a - 55'C to 125'C temperature range, the worst
case drift is reduced from 3 mY/sec to 0.5 mY/sec when a
1 ,..F integrating capaCitor is used. If this reduction in drift is
not needed, the circuit can be simplified by eliminating R4,
C2 and 03 and returning the non-inverting input of the amplifier directly to ground.
In fabricating low drift integrators, it is again necessary to
use high quality components and minimize leakage currents
in the wiring. The comments made on capacitors in connection with the sample-and-hold circuits also apply here. As an
additional precaution, a resistor should be used to isolate
the inverting input from the integrating capaCitor if it is larger
than 0.05 ,..F. This resistor prevents damage that might occur when the supplies are abruptly shut down while the integrating capacitor is charged.
Some integrator applications require both speed and low
error current. The output amplifiers for photomultiplier tubes
or solid-state radiation dectectors are examples of this. Although the LM108 is relatively slow, there is a way to speed
it up when it is used as an inverting amplifier. This is shown
in Figure 17.
The circuit is arranged so that the high-frequency gain characteristics are determined by A2, while Al determines the dc
and low-frequency characteristics. The non-inverting input
of A, is connected to the summing node through R,. A, is
operated as an integrator, going through unity gain at
500 Hz. Its output drives the non-inverting input of A2. The
inverting input of A2 is also connected to the summing node
through C3. Cs and Rs are chosen to roll off below 750 Hz.
Hence, at frequencies above 750 Hz, the feedback path is
directly around A2, with AI contributing little. Below 500 Hz,
however, the direct feedback path to A2 rolls off; and the
gain of AI is added to that of A2.
Normally, it is necessary to reset an integrator to establish
the initial conditions for integration. Resetting to zero is
readily accomplished by shorting the integrating capacitor
with a suitable switch. However, as with the sample and
hold circuits, semiconductor switches can cause problems
because of high-temperature leakage.
A connection that gets rid of switch leakages is shown in
Figure 16. A negative-going reset pulse turns on 0, and 02,
R2
v·
lOOK
RI
-
20M
1....--f--4t-RESET
1%
INPUT-""'tJ"",....--·n---~1
R3
10K
> .......-4f-OUTPUT
R4
20M
The high gain frequency amplifier, A2, is an LM101A connected with feed-forward compensation. 10 It has a 10 MHz
equivalent small-signal bandwidth, a 10V/,..s slew rate and
a 250 kHz large-signal bandwidth, so these are the high-frequency characteristics of the complete amplifier. The bias
current of A2 is isolated from the summing node by C3.
Hence, it does not contribute to the dc drift of the integrator.
The inverting input of AI is the only de connection to the
summing junction. Therefore, the error current of the compOSite amplifier is equal to the bias current of A,.
TLlH/687S-17
·Q1 and 03 should not have internal gate-protection diodes.
Figure 16_ Low drift Integrator with reset
shorting the integrating capacitor. When the switches turn
off, the leakage current of 02 is absorbed by R2 while 0,
isolates the output of 02 from the summing node. 0, has
practically no voltage across its junctions because the substrate is grounded; hence, leakage currents are negligible.
If A2 is allowed to saturate, A, will then start towards saturation. If the output of A, gets far off zero, recovery from saturation will be slowed drastically. This can be prevented by
putting zener clamp diodes across the integrating capacitor.
A suitable clamping arrangement is shown in Figure 17. 0,
and 02 are included in the clamp circuit along with R5 to
keep the leakage currents of the zeners from introducing
errors.
In addition to increasing speed, this circuit has other advantages. For one, it has the increased output drive capability
of the LMI 01 A. Further, thermal feedback is virtually eliminated because the LM108 does not see load variations.
Lastly, the open loop gain is nearly infinite at low frequencies as it is the product of the gains of the two amplifiers.
The additional circuitry shown in Figure 16 makes the error
accumulation rate proportional to the offset current, rather
than the bias current. Hence, the drift is reduced by roughly
a factor of 10. During the integration interval, the bias current of the non-inverting input accumulates an error across
R4 and C2 just as the bias current on the inverting input
does across R, and C,. Therefore, if R4 is matched with R,
and C2 is matched with C, (within about 5 percent) the output will drift at a rate proportional to the difference in these
55
en
N
Z•
RS
2K
Dl
CC
D4
D3
D2
":'
CL
Ro
INPUT
R4
SK
Rl
ISDK
Cl
0.002 ~F
C5
10,F
C3
0.002 ~F
R2
1M
DUTPUT
R3
1M
":'
':"
TLlH/6875-1 B
Figure 17. Fast Integrator
C2
D.OhF
1%
C3
0.01 ~F
1%
SINE
OUTPUT
R3
10M
1%
Rl
22M
1%
COSINE
OUTPUT
CS
30 pF
R2
22M
1%
Dl
&.3V
R4
50K
02
&.3V
. '.
"
TL/H/6875-19
Figure 18. Sine wave oscillator
A unique solution to most of these problems is shown In
Figure 18. AI is connected as a two-poie low-pass. 'active
filter, and A2 is connected as an integrafor. Sincathe ultimate phase lag introduced by the amplifiers is 270 degl'ElEls,
the circuit can be made to oscillate if the loop gain is high
enough at the frequency where the lag is 180 degrees. The
gain is actually made somewhat higher than is required· for
oscillation to insure starting. Therefore, the amplitude builds
up until it is limited by some nonlinearity in the system.
sine wave oscillator
Although it is comparatively easy to build an oscillator that
aprC?ximates a sine wave, making one that delivers a highIlurity sinusoid with astable frequency and amplitude is another story, Most sa,tisfactory deSigns are relatively complicated and require individual trimming and temperature compensation to make them work. In addition, tliey generally
take a long time to stabilize to the final output amplitude.
56
Amplitude stabilization is accomplished with zener clamp diodes, 01 and 02. This does Introduce distortion, but it is
reduced by the subsequent low pass filters. If 01 and 02
have equal breakdown voltages, the resulting symmetrical
clipping will virtually eliminate the even-order harmonics.
The dominant harmonic is then the third, and this is about
40 dB down at the output of A1 and about 50 dB down on
the output of A2. This means that the total harmonic distortion on the two outputs is 1 percent and 0.3 percent, respectively.
R2
10M
C2
30 pF
R3
lK
1%
~----~~------~-~C
Rl
The frequency of oscillation and the oscillation threshold
are determined by R1, R2, Ra, Clo C2 and Ca. Therefore
precision components with low temperature coefficients
should be used. If Ra is made lower than shown, the circuit
will accept looser component tolerances before dropping
out of oscillation. The start up will also be quicker. However,
the price paid is that distortion is increased. The value of R4
is not critical, but it should be made much smaller than R2
so that the effective resistance at R2 does not drop when
the clamp diodes conduct.
The output amplilude is determined by the breakdown voltages of 01 and 02. Therefore, the clamp level should be
temperature compensated for stable operation. Diode-connected (collector shorted to base) NPN transistors with an
emitter-base breakdown of about 6.3V work well, as the
positive temperature coefficient of the diode in reverse
breakdown nearly cancels the negative temperature coefficient of the forward-biased diode. Added advantages of using transistors are that they have less shunt capaCitance
and sharper breakdowns than conventional zeners.
Cl
10PF~
10M
1%
TL/H/6875-20
Figure 19. CapaCitance multiplier
The performance of the circuit is described by the equations
given in Figure 19, where C is the effective output capacitance, IL is the leakage current of this capacitance and Rs is
the series resistance of the multiplied capaCitance. The series resistance is relatively high, so high.Q capaCitors cannot be realized. Hence, such applications as tuned circuits
and· filters are ruled out. However, the multiplier can still be
used in timing circuits or servo compensation networks
where some resistance is usually connected in series with
.the capacitor or the effect of the resistance can be compen'sated for.
One final point is that the leakage current of the multiplied
capacitance is not a function of the applied voltage. It persists even with no voltage on the output. Therefore, it can
glilner!lte offset errors in a Circuit, rather than the scaling
errors caused by conventional capacitors.
The LM108 is particularly useful in this circuit at low frequencies, since it permits the use of small. capacitors. The
circuit shown oscillates at 1 Hz, but uses capacitors in the
order of 0.01 ",F. This makes it much easier to find temperature-stable precision capacitors. However, some judgment
must be used as large value re.sistors with low temperature
coefficients are not exactly easy to come by.'
The LM 108s are useful in this circuit for output frequencies
up to 1 kHz, Beyond that, better performance can be realized by substituting and LM102A for A1 and an LM101Awith
feed-forward compensation for A2. The improved high-frequency response of these devices eXtend the operating frequency out to 100 kHz.
Instrumentation amplifier
In many instrumentation applications there is frequently a
need for an amplifier with a high-impedance differential input and a single ended output. Obvious uses for this are
amplifiers for bridge-type signal sOl!rces such as strain
gages, temperalure sensors or pressure transducers. General purpose op amps have satisfactory input characteristics, but feedback must be added to determine the effective
gain. And the addition of feedback can drastically reduce
the input resistance and degrade common mode rejection.
Figure 20 shows the classical op amp circuit for a differential amplifier. This circuit has three main disadvantages.
First, the input resistance on the .inverting input is relatively
low, being equal to Rt. Second, there usually is a large difference in the input resistance of the two inputs, as is indicated by the equations on the .schematic. Third, the common mode rejection is greatly affected by resistor matching
and by balanCing of the source resistances. A 1-percent
deviation in anyone of the resistor values reduces the common mode rejection to 46 dB for a closed loop gain of 1, to
60 dB for a gain of 10 and to 80 dB for a gain of 100.
Clearty, the only way to get high input impedanc~ is to use
very large resistors in the feedback network. The op amp
must operate from a source resistance which is orders of
magnitude larger than the resistance of the signal source.
Older IC op amps introduced excessive offset and drift
when operating from higher resistances and. could not be
used successfully. The LM108, however, is relatively unaffected by the large resistors, so this approach can sometimes be employed.
capaCItanCe multiplier
Large capacitor values can be eliminated from most systems just by raising the impedance levels, if suitable· op
amps are available. However, sometimes it is not possible
because the impedance levels are already fixed by some
element of the system like a low impedance transducer. If
this is the case, a capacitance multiplier can be uSE!d to
increase the effective capaCitance of a small capaCitor anc;t
couple it into a low impedance system,
Previously, IC op amps could not be used effectively as capacitance multipliers because the equivalent leakages generated due to offset current were significantly greater than
the leakages of large tantalum capacitors, With the LM108,
this has changed. The circuit shown in Figure 19 generates
an equivalent capaCitance of 100,000 J.l.F with a worst case
leakage of 8 ",A-over a - 55°C to 125°C temperature
range.
'Large·value resistors are available from Victoreen Instrument, Cleveland,
Ohio and Pyrofilm Resistor Co., Whippany, New Jersey.
57
With large input resistors, the, feedback resistors, Ra and
R4, can get ql!ite large for higher closed loop gains. For
example, if R1 and R2 are 1 MO, Ra and R4 must be
100 MO for a gain of 100. It is difficult to accurately match
resistors that are this high in value, so Common mode rejection may suffer. Nonetheless, anyone of the resistors can
be trimmed to take out common mode feedthrough caused
either by resistors mismatches or the amplifier itself.
RI
When the bridge goes off balance, the op amp maintains
the voltage between its input terminals at zero with current
fed back from the output through Ra. This circuit does not
act like a true differential amplifier for large imbalances in
the bridge. The voltage drops across the two sensor resistors, S1 and S2, beccme unequal as the bridge goes off
balance, causing some non-linearity in the transfar function.
However, this is not usually objectionable for small signal
swings.
--W"'""-..,
R3 ,
-"V\I\r-4....
H,.· HI _
RI
lOOK
1.1%
IK
H3
IK
I!IIK
D.I%
1.'%
1.1"
HZ
H4
INPUTS
OUTPUT
+ R2
-JV\I\r-4H
R,.· H2 + R4 _
H4
R3
= R4
Av=~
RI
TLlH/6875-21
-
Figure 20. Feedback connection for a differential amplifier
_
'NPUTS_+
RI = R4
R2 = R3
A,,=1+!!!
Another problem caused by large feedback resistors is that
stray capaCitance can seriously affect the high frequenCy
common mode rejection. With 1 MO input resistors, a 1 pF
mismatch in stray capacitance from either input to ground
can drop the common mode rejection to 40 dB at 1500 Hz.
The high frequency rejection can be improved at the expense of frequency response by shunting Ra and R4 with
matched capacitors.
With high impedance bridges, the feedback resistances become prohibitively large even ,for the LM108, so the circuit in
Figure 20 cannot be used. One possible alternative is
shown in Fl{Jure 21. R2 and Ra are, chosen so that their
equivalent parallel resistance is equal to R1. Hence, the output of the amplifier
be zero when the bridge is balanced.
R2
Tt/H/6875-23
Figure 22_ Differential Input Instrumentation amplHler
Figure 22 shows a true differential connection that has few
of the problems mentioned previously. It has an input resistance greater than 10100, yet it does not need large resistors in the feedback cirCuitry. With the component values
shown, A1 is connected as a non-inverting amplifier with a
gain of 1.01; and it feeds into A2 which has an inverting gain
of 100. Hence, the total gain from the input of A1 to the
output of A2 is 101, which is equal to the non-inverting gain
of A2. If all the resistors are matched, the circuit responds
only to the 'differential input signal-not the common mode
voltage.
This circuit has the same sensitivity to resistor matching as
the previous circuits, with a 1 parcent mismatch between
two resistors lowering the common mode rejection to 80 dB.
However, matching is more easily accol1)plished Ile<;ause of
the lower resistor values. Further. the high frequency common 'mode rejection is less affected by stray capaCitances.
The I'ligh frequency, rejection is limited, though, by the response of A1 '
,
will
,...-~...-v+
51
lOOK
AI
lOOK
OUTPUT
logarithmic converter
52
lOOK
AZ
Ian
R3
5M
RI
A logarithmic amplifier is another circuit that can take advantage of the low input current of an op amp to increase
dynamic range. Most practical log converters make use of
the logarithmic relationship between the emitter-base voltage of standard double-diffused transistors and their collector current This logarithmic characteristic has been proven
true for over 9 decades of collector current. The only problem involved in using transistors as logging elements is that
the scale factor has a temperatllre sensitivity of 0.3 percent/·C. However, temperature compensating resistors
have been developed to compensate for this characteristic,
making possible log converters that are aecurate over a
wide temperature range.
= R2I/R3
TL/H/6875-22
Figure 21. Amplifier for bridge transducera
58
V+
2N2820
z
I'V
83"
I.IM
III
Rs
---4 t---....,
INPUT-"lM_. .
RZ
2K
I..
HI
IS.7K
III
SIt
T IK
+O.8ll/C
RiI"
1.5M
C4
150pF
OUTPUT
10 nA
<
liN
<
1
TL/H/6875-24
mA
tl kIl (±1%) at 25"C, +3500
Sensitivity is 1V per decade.
ppmrc.
Available from Vishay Ultronlx, Grand Junc-
tion, CO, 081 Series.
"Determinaa current for zero crossing on
OIItput 10 p.A as shown.
Figure 23. Temperature compensated one-quadrant logarithmic converter
Figure 23 gives a circuit that uses these techniques. 01 is
the logging transistor, while Q2 provides a fixed offset to
temperature compensate the emitter-base tum on voltage
of 01. 02 is operated at a fixed collector current of 10 p.A by
A2, and its emitter-base voltage is subtracted from that of
01 in determining the output voltage of the circuit. The collector current of 02 is established by R3 and V+ through
A2·
The collector current of 01 is proportional to the input current through Rs and, therefore, proportional to the input voltage. The emitter-base voltage of 01 varies as the log of the
input voltage. The fixed emitter-base voltage of 02 subtracts from the voltage on the emitter of 01 in determining
the voltage on the top end of the temperature-compensating resistor, 51'
these transistors. Accuracy for low input currents is determined by the error caused by the bias current of AI' At high
currents, the behavior of 01 and 02 limits accuracy. For
input currents approaching 1 mA, the 2N2920 develops logging errors in excess of 1 percent. If larger Input currents
are anticipated, bigger transistors must be used; and R2
should be reduced to insure that A2 does not saturate.
trensducer amplifiers
With certain transducers, accuracy depends on the choice
of the circuit configuration as much as it does on the quality
of the components. The amplifier for photodiode sensors,
shown in FIgure 24, illustrates this point. Normally, photodiodes are operated with reverse voltage across the junction.
At high temperatures, the leakage currents can approach
the signal current. However, photodiodes deliver a short-circuit output current, unaffected by leakage currents, which is
not significantly lower than the output current with reverse
bias.
The signal on the top of 51 will be zero when the input
current is equal to the current through R3 at any temperature. Further, this voltage will vary logarithmically for changes in input current, although the scale factor will have a
temperature coefficient of -0.3%/oC. The output of the
converter is essentially multiplied by the ratio of R 1 to SI.
Since SI has a positive temperature coefficient of 0.3 percentl"C, it compensates for the change in scale factor with
temperature.
HI
III
."
In this circuit, an LM101A with feedforward compensation is
used for A2 since it is much faster than the LM 108 used for
AI' Since both amplifiers are cascaded in the overall feedback loop, the reduced phase shift through A2 insures stability.
II
Certain things must ba considered in designing this circuit.
For one, the sensitivity can be changed by varying R1. But
Rl must be made considerably larger than the resistance of
51 for effective temperature compensation of the scale factor. 01 and 02 should also be matched devices in the same
package, and 51 should be at the same temperature as
TL/H/6875-25
Figure 24. Amplifier for photodlode senaor
59
~ r-----------------------------------------------------------------------------~
.~
:i
r---4...- - - - - - 4.... OUTPUT
RI
2M
1%
R3
R2
2M
1%
515
1%
CI
IO,.F
R2> RI
R2» RS
A _R2(RS+R4)
R1RS
. v-
R5
E:::J
1M
TRANSDUCER
J
TL/H/6875-27
TUH/6875-26
Figure 25. Amplifier for piezoelectric transducers
Figure 26. Inverting amplifier with high Input resistance
The circuit shown in F/{Juf'824 responds to the short·circuit
output current of the photodiode. Since the voltage across
the diode is only the offset voltage of the amplifier, inherent
leakage is reduced by lit least two orders of magnitude.
Neglecting the offset current of the amplifier, the output cur-.
rent of the sensor is multiplied by R1 plus R2 in determining
the output voltage,
Figuf'8 25 shows an amplifier for high-impedance ac transducers like a piezoelectric accelerometer. These sensors
normally require a high-input-resistance amplifier. The
LM108 can provide input resistances in the range of 10 to
100'MO, using conventional circuitry. However, conventional designs are sometimes ruled out either because large
resistors cannot be used or because prohibitively large input
resistances are needed.
Using the circuit in Flguf'8 25, input resistances that are orders of magnitude greater than the values of the dc return
resistors c.an be obtained. This is accomplished by bootstrapping the resistors -to the output. With this arrangement,
the lower cutoff frequency of a capacitive transducer is. determined more by the RC product of R1 and C1 than it Is by
resistor values and the equivalent capaCitance of the trans·
ducer.
Another disadvantage of the circuit is that four resistors determine the gain, instead of two. Hence, for a given resistor
tolerance, the worst-case gain deviation is greater, although
this is probably more than offset by the ease of getting better tolerances in the low resistor values.
current sources
Although there are numerous ways to make current sources
with op amps, most have limitations as far as their application is conCerned. Figuf'827, however, shows a current
source which is fairly flexible and has few restriCtions as far
as its use is concerned. It supplies a current that is proportional to the input voltage and drives a load referred to
ground or any voltage within the output-swing capability of
the amplifier.
.RI
2M
1%
V,N
--JI,I\I\Io.....- ...
I
OUT
RSVIN
= R1'Fi5
RS=R4+R6
Rl - R2
resistance multiplication
When an inverting operational amplifier must have high input reSistance, the resistor val~s required can get out of
hand. For example, If a 2 MO input resistance Is needed for
an amplifier with a gain of 100, a 200 MO feedback resistor
Is called for. This resistance can, however, be reduced usIng the circuit In Figuf'8 26. A divider with a ratio of 100 to 1
(Rs and R4) is added to the Qutput of the amplifier: Unitygain feedback is applied from the output of the divider, givIng an overall gain of 100 using only 2 MO resistors.
This circuit does increase the offset voltage somewhat. The
output offset voltage is given by
VOUT=
-I\I\,.,...
R3
1M
1%
RI
2M
1%
--~N_-"-louT
R4
1M
1%
TUH/8875-26
Figure 27. Bllaterel current source
With the output gro.unded, It Is relatively obvIous that the
output current will be_ determIned by Rs and the gain setting
of the op amp, yielding
+ R2) AvVoa·
R;-
( R1
The ~ffset voltage is only multiplied by Av +1 in a conventional inverter. Therefore, the circuit in FIgure 26. multiplies
the offset by 200, instead of 101. This multiplication factor
can be reduced to 110 by increasing R2 to 20 MO and Rs to
5.55k.
RaVIN
lOUT = -'"---.
R1 Rs
When the output is not at zero, it would seem that the current through R2 and R4 would reduce accuracy. Nonetheless, if R1 = R2 and Rs = R4 + Rs, the output current will
60
be independent of the output voltage. For Rl
the output resistance of the circuit is given by
ROUT"" R5
+ R3 » R5,
Rgure 29 shows a comparator for voltages of opposite polarity. The output changes state when the voltage on the
junction of R1 and R2 is equal to VTH. Mathematically, this is
expressed by
Cl~)
where R is anyone of the feedback resistors (Rl, R2, R3 or
R4) and aR is the incremental change in the resistor value
from design center. Hence, for the circuit in Figure 27, a 1
percent deviation in one of the resistor values will drop the
output resistance to 200 kO. Such errors can be trimmed
out by adjusting one of the feedback resistors. In design, it
is advisable to make the feedback resistors as large as possible. Otherwise, resistor tolerances become even more critical.
The circuit must be driven from a source resistance which is
low by comparison to Rl, since this resistance will imbalance the circuit and affect both gain and output resistance.
As shown, the circuit gives a negative output current for a
positive input voltage. This can be reversed by grounding
the input and driving the ground end of R2. The magnitude
of the scale factor will be unchanged as long as R4
R5.
Rl
v,-oJ\jl\l\_..
OUTPUT
AZ
V2-~M_""'t
»
voltage comparators
TlIH/6875-30
Figure 29. Voltage comparator with output buffer
...ike most op amps, it is possible to use the LM10S as a
voltage comparator. Figure 28 shows the device used as a
simple zero-crossing detector. The inputs of the Ie are pro-
The LM10S can also be used as a differential comparator,
going through a transition when two input voltages are
equal. However, resistors must be inserted in series with the
inputs to limit current and minimize loading on the Signal
sources when the input-protection diodes conduct. Figure
29 also shows how a PNP transistor can be added on the
output to increase the fan out to about 20 with standard DTL
or TIL.
Al
1M
lNPUT-~M_i;,j
-
power booster
The LM10S, which was designed for low power consumption, is not able to drive heavy loads. However, a relatively
simple booster can be added to the output to increase the
output current to ± 50 mAo This circuit, shown in Figure 30,
has the added advantage that it swings the output up to the
supplies, within a fraction of a volt. The increased voltage
swing is particularly helpful In low voltage circuits.
Tl/H/6875-29
Figure 28. Zero crossing detector
tected internally by back-to-back diodes connected between them, therefore, voltages in excess of 1V cannot be
impressed directly across the inputs. This problem is taken
care of by R1 which limits the current so that input voltages
in excess of 1 kV can be tolerated. If absolute accuracy is
required or if R1 is made much larger than 1 MO, a compensating resistor of equal value should be inserted in series
with the other input.
In Figure 28, the output of the op amp is clamped so that it
can drive DTL or TIL directly. This is accomplished with a
clamp diode on pin S. When the output swings positive, it is
clamped at the breakdown voltage of the zener. When it
swings negative, it is clamped at a diode drop below ground.
If the 5V logic supply is used as a positive supply for the
amplifier, the zener can be replaced with an ordinary silicon
diode. The maximum fan out that can be handled by the
device Is one for, standard DTL or TIL under worst case
conditions.
As might be expected, the LM10S is not very fast when
used as a comparator. The response time is up in the tens
of microseconds. An LM10311 is recommended for 01. rather than a conventional alloy zener, because it has lower
capacitance and will not slow the circuit further. The sharp
breakdown of the LM103 at low currents is also an advantage as the current through the diode in clamp is only
10 p.A.
r-----.-
v•
OUTPUT
AZ
470
~
__________
~_v-
TL/H/6875-31
Figure 30. Power booster
61
In Figure 30, the output transistors are driven from the su~
At elevated temperatures, even the leakage of clean boards
can be a headache. At 125"C the leakage resistance between adjacent runs on a printed circuit board is about
1011 n (O.OS-inch separation parallel for 1 inch) for high
quality epoxy-gla~ boards that have been properly 9'eaned.
Therefore, the boards can easilY prodoce 'errOr currents in
the order of 200 pA and much more if iheybecome contaminated. Conservative practice dictates that the boards be
cOatedwitl1 epoxy or silicone rubber idter ciENin1ng to ptevent cdntainlnatjon. Silicone rubber is theellSiest to uiIEI.
However, if the better durability of epoxy' is n&adad, care
must be taken'to make 'Sure that it gets thoroughly cured.
Otherwise, the epdXy will make high temperature leakage
much worse.
cafe must also be exercised to insure that the circuit board
is protected from condensed water vapor when operating in
the vicinity of O"C. This can usually be accomplished by
coating tlia board as mentioned above.
PlY leads of the op amp. It is important that Rj and R2 be
made low enough so Q1 and Q2 are not turned on by the
worst case quiescent current of the amplifier. The output of
the op amp is loaded heavily to ground with Rs and R4.
When the output swings about 0.5V positive, the increasing
positive supply current will tum on Q1 which pulls up the
load. A similar Situation occurs with Q2 for negative output
swings.
The bootstrapped shunt compensation shown in the ,figure
is the only one that seems to work for all loading conditions.
This capacitor, C1, can be ma(le inversely proportional to
the closed loop gain to optimize frequency response. The
value given is for unity-gain follower connection. C2 is also
required for loop stability.
The circuit does have a dead zone in the open loop transfer
characteristic. However, th~ low frequency gain is high
enough so that It can be neglected. Around 1 kHz, though,
the dead zone becomes quite noticeabre.
Current limiting can be incorporated into the circuit by adding resistors in series with the emitters of Q1 and Q2 because the short circuit protection of the LM 108 limits the
maximum voltage drop across R1' and R2.
a
L Inverting amplifier
RI '
RZ
INPUT-~"",""--'"\I\J\r.--...
board construction
As indicated previously, certain precautions must be observed, when building circuits that are sensitive to ,!ery low
currents. If proper care' is not taken, board leakage currants
can easilybecorT1e .much larger than the error currents of
the rip amp: To, prevent 'this, it is neCesslW to thoroughly
cl9ari printed circuit boards. Even experimental breadboards must be cleaned with trichloroethlene or alcohol to
remove solder fluxes, and blown dry with compresS$d"air.
These fluxes may be insulators at low impedance levelslike in electric motors-but they certainly are 'not in high
impedance circuits. In addition to causing gr~s errors, their
presence can make the circuit behave erratically, ~specially
as tl1e temperature is changed. '
,
OUTPUT
TLlH/6875-33
b.follower
AI,
COMPENSATION
"
'~
v+, "~
OUTPUT _ _ _
1
,
I
I
''-
OUTPUT
INI'UT---9=-1
\
,
.-.---.
TLlH/6875-34
c. non1nverflng amplifier
AZ
TLlH/6875-32
Bottom View
Figure 31. Printed circuit' layout for Input guarding with
TQ-S package
OUTPUT
AI
c,
TLlH/6875-36
Figure 32. Connection of Input guards
62
guarding
Guarding a non-inverting amplifier is a little more complicated. A low impedance point must be created by using relatively low value feedback resistors to determine the gain CAl
and A2 in F/(lure 32c). The guard is then connected to the
junction of the feedback resistors. A resistor, As, can be
connected as shown in the figure to compensate for large
source resistances.
With the dual-in-line and flat packages, it is far more difficult
to guard the inputs, if the standard pin configuration of the
LM709 or LM101A is used, because the pin spacings on
these packages are fIXed. Therefore, the pin configuration
of the LM108 was changed, as shown in Figure SS.
Even with properly cleaned and coated boards, leakage currents are on the verge of causing trouble at 125·C. The
standard pin configuration of most IC op amps has the input
pins adjacent to pins which are at the supply potentials.
Therefore, it is advisable to employ guarding to reduce the
voltage difference between the inputs and adjacent metal
runs.
A board layout that includes input guarding is shown in Figure 31 for the eight lead TO-5 package. A ten-lead pin circle
is used, and the leads of the IC are formed so that the holes
adjacent to the inputs are vacant when it is inserted in the
board. The guard, which is a conductive ring surrounding
the inputs, is then connected to a low impedance point that
is at the same potential as the inputs. The leakage currents
from the pins at the supply potentials are absorbed by the
guard. The voltage difference between the guard and the
inputs can be made approximately equal to the offset voltage, reducing the effective leakage by more than three orders of magnitude. If the leads of the integrated circuit, or
other components connected to the input, go through the
board, it may be necessary to guard both sides.
conclusions
IC op amps are now available that equal the input current
speCifications of FET amplifiers in all but the most restricted
temperature range applications. At operating temperatures
above 85·C, the IC is clearly superior as it uses bipolar transistors that make it possible to eliminate the leakage currents that plague FETs. Additionally, bipolar transistors
match better than FETs, so low offset voltage and drifts can
be obtained without expensive adjustments or selection.
Further, the bipolar devices lend themselves more readily to
low-cost monolithic construction.
Figure 32 shows how the guard is commited on the morecommon op amp circuits. With an integrator or inverting amplifier, where the inputs are close to ground potential, the
guard is simply grounded. With the voltage follower, the
guard is bootstrapped to the output. If it is desirable to put a
resistor in the inverting input to compensate for the source
resistance, it is connected as shown in Figure 32b.
These amplifiers open up new application areas and vastly
improve performance in others. For example, in analog
memories, holding intervals can be extended to minutes,
even where -55·C to 125·C operation is involved. Instrumentation amplifiers and low frequency waveform generators also benefit from the low error currents.
14
14
13
BALANCE/COMPENSATION 3
COMPENSATION 2
12 COMPENSATION
13
12 COMPENSATION
GUARD 3
IN'UT 4
11
v+
'N'UT 4
"
IN'UT 5
10 OUTPUT
IN'UT 5
II OUTPUT
y- I
9
BALANCE
y+
GUARD •
V- 7
TUH/6875-37
TL/H/6875-39
NOTE: Pin 6 connected to bottom of package.
NOTE: Pin 7 connected to bottom of package
TOp View
Top View
Figure 33. Comparing connection diagrams of the LM101A and LM108, showing addition of guarding
63
When Operating above 85"C, Overall performance is fre' .
quently limited by components other than the op amp, unless certain precautions are observed. It is generally necessary to redesign circuits using semiconductor switches to .
reduce the effect of their leakage currents. Further, high .
quality capaoitors must be used, and care must be exercised in selecting large value resistors. Printed oircuit board
leakages can also be troublesome unless the boards are
properly treated. And above 100"C, it is almost mandatory
to employ guarding on the boards to protect the inputs, if
the full potential of the amplifier is to be realized.
appendix
A oomplete schematio of the LM108 is given in Figure A 1. A
desoription of the basio oircuit is presented along with a
simplified sohematio earlier in the. text. The purpose of this
Appendix is to explain some of the more subtle features of
the design.
The ourrent source supplying the input'transistors is 029. It
is designed to supply a total input stage current of 6 p.A at
25"C. This ourrent drops to 3 p.A at - 55°C but increases to
only 7.5 p.A at 125°C. This temperature characteristio tends
COMPENSATION
to compensate for the current gain falloff of the input transistors at lOW temperatures without cre!lting stability problems at high temperatures.
The biasing 'clrcultry fOr the input current source is nearly
identical to that in the LM101A, and a complete description
is given in Reference 4. However, a brief explanation follows.
A collector FET,S 023, which has a saturation current of
about 30 p.A, establishes the collector current of 024; ,This
FET provides the Initial turn-on current for the clrouit arid
insures starting under all conditions. The purpose ofR14 is'
to compensate for production and temperature variations In
the FEr current. It is a collector resistor (indicated by the T
through it) 'made of the same semiconductor material as the
FEr channel. As the FEr current varies, the drop across
R14 tends to oompensate for changes in the emitter base
voltage of 024.
The collector-emitter voltage of 024 is equal to the emitter
base voltage ,of 024 plus that of 025. This voltage is deliv:
ered to 026 and 029. 0 25 and 024 are operated at substantially higher currents than 026 and 029. Hence, there is a
COMPENSATION
r-~----~~-+--e--1~--~t-~--~t------------------t~------v+
l~-4I~'W~. . . OUTPUT
+
---+------....-r
~-Y~~~~~--~~~--~~~----~------v
TLlH/6875-40
Figure A 1. Complete schematic of the LM108
64
differential in their emitter base voltages that is dropped
across'A19 to determine the input stage current. A18 is a
pinched base resistor, as is indicated by the slash bar
th~ough it. This resistor, which has a large positive temperature coefficient, operates in conjunction with R17 to help
shape the temperature characteristics of the input stage
current source.
TABLE I. Typical Performance of the LM108 Operational
Ampllfler(TA = 25°C and Vs = ±15V)
Input Offset Voltage
0.7mV
Input Offset Current
50pA
Input Bias Current
Input Resistance
Input Common Mode Range
The output currents of 026, 025, and 023 are fed to 012,
which is a controlled-gain lateral PNP.6 It delivers one-half
of the combined currents to the output stage. 011 is also
connected to 012, with its output current set at approximately 15 p.A by A7. Since this type of current source
makes use of the emitter-base voltage differential between
similar transistors operating at different collector currents,
the output of 011 is relatively independent of the current
delivered to 012. 12 This current is used for the input stage
bootstrapping circuitry.
Common Mode Rejection
Offset Voltage Drift
Offset Current Drift
3 p.VI"C
0.5pAI"C
Voltage Gain
Small Signal Bandwidth
300V/mW
1.0 MHz
0.3V/p.s
Slew Rate
Output Swing
Supply Current
020 also supplies current to the class-B output stage. Its
output current is determined by the ratio of A 15 to A12 and
the current through A12. R13 is included so that the biasing
circuit is not upset when 020 saturates.
One major departure from the simplified schematic is the
bootstrapping of the second stage active loads, 021 and
022, to the output. This makes the second stage gain dependent only on how well 09 and 010 match with variations
in output voltage. Hence, the second stage gain is quite
high. In fact, the overall gain of the amplifier is typically in
excess of 106 at dc.
0.8nA
70MO
±14V
100dB
Power Supply Rejection
Operating Voltage Range
±14V
300 p.A
100dB
±2Vto ±20V
references
1. R. J. Widlar, "Future Trends in Intregrated Operational
Amplifiers," EDN, Vol. 13, No 6, pp 24-29, June 1968.
2. R. J. Widlar, "Super Gain Transistors for IC," IEEE Journal of Solid-State Circuits, Vol. SC-4, No.4, August, 1969.
3. R. J. Widlar, "A Unique Circuit Design for a High Performance Operational Amplifier Especially Suited to Monolithic Construction," Proc. of NEG, Vol.XXl, pp. 85-89, October, 1965.
The second stage active loads drive 014. A high-gain primary transistor is used to prevent loading of the second
stage. Its collector is bootstrapped by 013 to operate it at
zero collector-base voltage. The class-B output stage is actually driven by the emitter of 014'
A dead zone in the output stage is prevented by biasing 018
and 019 on the verge of conduction with 015 and 016. A9 is
used to compensate for the transconductance of 015 and
016, making the output stage quiescent current relatively
independent of the output current of 012. The drop across
this reSistor also reduces quiescent current.
For positive-going outputs, short circuit protection is provided by Al0 and 017. When the voltage drop across Al0 turns
on 017, it removes base drive from 018. For negative-going
outputs, current limiting is initiated when the voltage drop
across All becomes large enough for the collector base
junction of 017 to become forward biased. When this happens, the base of 019 is clamped so the output current
cannot increase further.
4. A. J. Widlar, "I.C. Op Amp with Improved Input-Current
Characteristics," EEE, pp. 38-41, December, 1968.
5. R. J. Widlar, "Linear IC's: part 6; Compensating for Drift,"
Electronics, Vol. 41, No.3, pp. 90-93, February, 1968.
6. R. J. Widlar, "Design Techniques for Monolithic Operational Amplifiers," IEEE Joumal of Solid-State Circuits,
Fol. SC-4, No.4, August 1969.
7. D. R. Sulllivan and M. A. Maidique, "Characterization and
Application of a New High Input Impedance Monolithic
Amplifier," Transitron Electronic Corporation Application
Brief.
8. Paul C. Dow, Jr., "An Analysis of Certain Errors in Electronic Differential Analyzers, II-Capacitor Dielectric Absorption," IRE Trans. on Electronic Computers, pp. 1722, March, 1958.
9. R. J. Widlar, "A Fast Integrated Voltage Follower with
Low Input Current," Microelectrics, Vol. 1, No.7, June,
1968.
10. R. C. Dobkin, "Feedforward Compensation Speeds Op
Amp," National Semiconductor LB·2, March, 1969.
11. R. J. Wildlar, "A New Low Voitage Breakdown Diode,"
National Semiconductor TP·5, April, 1968.
Input protection is provided by 03 and 04 which act as
clamp diodes between the inputs. The collectors of these
transistors are bootstrapped to the emitter of 028 through
A3. This keeps the collector-isolation leakage of the tranSistors from showing up on the inputs. R3 is included so that
the bootstrapping is not disrupted when 03 or 04 saturate
with an input overtoad, Current-limiting resistors were not
connected in lIeries with the inputs, since diffused resistors
cannot be employed such that they work effectively, without
causing high temperature leakages.
12. R. J. Widlar, "Some Circuit DeSign Techniques for linear Integrated Circuits," IEEE Transactions on Circuit
Theory, Vol. CT-12, No.4, pp. 586-590, December,
1965.
65
~
~ L.og Converters
National Semiconductor
Application Note 30
One of the most predictable non-linear elements commonly
available is the bipolar transistor. The relationship between
collector current and emitter base voltage is precisely logarithmic from currents below one picoampto currents above
one milliamp. Using a matched pair of transistors and integrated circuit operational amplifiers, it is relatively easy to
construct a linear to logarithmic converter with a dynamic
range in excess of five decades.
The circuit in Figure 1 generates a logarithmic output voltage for a linear input current. Transistor 01 is used as the
non-linear feedback element around an LM10B operational
amplifier. Negative feedback is applied to the emitter of 01
through divider, Ri and R2, and the emitter base junction of
02. This forces the collector current of 01 to be exactly
equal to the current through the input resistor. Transistor 02
is used as the feedback element of an LM101A operational
amplifier. Negative feedback forces the collector current of
02 to equal the current through R3. For the values shown,
this current is 10 pA Since the collector current of 02 remains constant, the emitter base voltage also remains constant. Therefore, only the VSE of 01 varies with a change of
input current. However, the output voltage is a function of
the difference in emitter base voltages of 01 and 02:
Rl + R2
EOUT = ~ (VSE2 - VSE1)'
for EIN :2: O. This shows that the output is proportional to the
logarithm of the input voltage. The coefficient of the log
term is directly proportional to absolute temperature. WIthout compensation, the scale factor will also vary directly
with temperature. However, by making R2 directly proportional to temperature, constant gain is obtained. The temperature compensation is typically 1 % over a temperature
range of -25°C to 1000C for the reSistor specified. For limited temperature range applications, such as OOC to 500C, a
430.0 sensistor in series with a 570.0 resistor may be substituted for the 1k resistor, also with 1 % accuracy. The divider,
Rl and R2, sets the gain while the current through R3 sets
the zero. With the values given, the scale factor is 1V/decade and
EOUT = - [109l0
(4)
where the absolute value sign indicates that the dimensions
of the quantity inside are to be Ignored.
Log generator circuits are not limited to inverting operation.
In fact, a feature of this circuit is the ease with which non-inverting operation is obtained. Supplying the input signal to
A2 and the reference current to Al results in a log output
that is not inverted from the input. To achieve the same
100 dB dynamic range in the non-inverting configuration, an
LM10B should be used for A2, and an LM101A for Al. Since
the LMl0B cannot use feedforward compensation, it is frequency compensated with the standard 30.pF capacitor.
The only other change is the addition of a clamp diode connected from the eMitter of 01 to ground. This prevents damage to the logging transistors if the input signal should go
negative.
(1)
For matched transistors operating at different collector currents, the emitter base differential is given by
Ic
kT
(2)
.1VSE = - loge ~,
q
IC2
where k is Boltzmann's constant, T is temperature in degrees Kelvin and q is the charge of an electron. Combining
these two equations and writing the expression for the output voltage gives
-kT
EOUT -_ - [Rl
- -+-R2]
- Ioge [EIN
- -R3
-]
q
R2
EREFRIN
I~:~ 1+ 5]
(3)
EREF
IIV
R3
1.5M
III
RON
EON
"IV
Rl·
Ret
RON
1M
IOIK
RI
IK
-'5V
-
TL/HI727S-1
'I kIl (±1%) at 25"C, +3500 ppmrc.
Available from Vishay Ultronix, Grand Junction, CO, 081 SerIes.
tOllset Voltage Adjust
FIGURE 1. Log Generator with 100 dB Dynamic Range
66
The log output is accurate to 1% for any current between
10 nA and 1 rnA. This is equivalent to about 3% referred to
the input. At currents over 500 jJA the transistors used deviate from log characteristics due to resistance in the emitter,
while at low currents, the offset current of the LM 108 is the
major source of error. These errors occur at the ends of the
dynamic range, and from 40 nA to 400 jJA the log converter
is 1 % accurate referred to the input. Both of the transistors
ara used in the grounded base connection, rather than the
diode connection, to eliminate errors due to base current.
Unfortunately, the grounded base connection increases the
loop gain. More frequency compensation is necessary to
prevent oscillation, and the log converter is necessarily
slow. It may take 1 to 5 ms for the output to settle to 1% of
its final value. This is especially true at low currents.
Anti-log or exponential generation is simply a matter of rearranging the circuitry. Figure 3 shows the circuitry of the log
converter connected to generate an exponential output
from a linear input. Amplifier Al in conjunction with transistor 01 drives the emitter of 02 in proportion to the input
voltage. The collector current of 02 varies exponentially
with the emitter-base voltage. This current is converted to a
voltage by amplifier A2. With the values given
EOUT = 10 -IEIN1.
The circuit shown in Fig/Jf8 2 is two orders of magnitude
faster than the previous circuit and has a dynamic range of
80 dB. Operation is the same as the circuit in Figure 1,
except the configuration optimizes speed rather than dynamic range. Transistor 01 is diode connected to allow the
use of feedforward compensation 1 on an LM101A operational amplifier. This compensation extends the bandwidth
to 10 MHz and increases the slew rate. To prevent errors
due to the finite hFE of 01 and the bias current of the
LM101A, an LM102 voltage follower buffers the base current and input current. Although the log circuit will operate
without the LM102, accuracy will degrade at low input currents. Amplifier A2 is also compensated for maximum bandwidth. As with the previous log convertsr, Rl and R2 control
the sensitivity; and R3 controls the zero crossing of the
transfer function. With the values shown the scale factor is
W/decade and
EOUT = - [109l0
I~:: I + 4]
(6)
Many non-linear functions such as XYo, X2, X3, 1/X, XV, and
X/V are easily generated with the use of logs. Multiplication
becomes addition, division becomes subtraction and powers become gain coefficients of log terms. FJgure 4 shows a
circuit whose output is the cube of the input. Actually, any
power function is available from this circuit by changing the
values of Rg and Rl0 in accordance with the expression:
16.7Rp
EOUT = EIN Rp + RIO.
(7)
Note that when log and anti-log circuits are used to perform
an operation with a linear output, no temperature compensating resistors at all are needed. If the log and anti-log
transistors are at the same temperature, gain changes with
temperature cancel. It is a good idea to use a heat sink
which couples the two transistors to minimize thermal gradients. A 1'C temperature difference between the log and
anti-log transistors results in a 0.3% error. Also, in the log
converters, a 1'C difference between the log transistors and
the compensating resistor results in a 0.3% error.
Either of the circuits in FJgures 1 or 2 may be used as dividers or reciprocal generators. Equation 3 shows the outputs
of the log generators are actually the ratio of two currents:
(5)
from less than 100 nA to 1 rnA.
EREF ISV
R3
15aK
1%
R4
ZK
HI
IUK
1%
CS
l5IpF
'HZ
IK
1%
'I kll (± 1%) at 25'C, + 3500 ppmrc.
Available from Vishay UItronIx,
Grand Junction, CO, 081 Series.
FIGURE 2. Fast Log Generator
67
TLlH17275-2
output voltage by ~ and R7, with the scale factor set by R7
at Ef E3/10E2.
Measurement Of transistor current gains over a wide range
of operating currents Is art application particularly suited to
log multiplier/dividers. USing the circuit irt Figure 5, PNP current gains can be: measured at currents from- '0.4 p,A' to
1 mAo The collector current is the input signal to Aj, the
base current i,iI the input signal to A2, and II fixed voltage to
R5 sets'the scale factor. Since A2 holds thEi base at ground,
a single resistor from the emitter to the pOSitive supply is all
that is needed to establish the operating current. The output
is proportiortal to collector current divided by base current,
or hFE.
In addition to their application in performing fUnctional operations, log generatorS can provide a significant increase in
the input current and the current through Rs. When used as
a log generator, the current through R3 was held constant
by connecting Rs to a fixed voltage. Hence, the output was
just the log of the Input. If R3 is driven' by an input voltage,
rather than the 15V ,reference, the output of the log generator is the log ratio of the input current to the' current through
R3. The anti-log of this voltage is the quotient. Of course, if
the divisor is constant, the output is the reciprocal.
A complete one quadrant multiplier/divider is shown in Figure 5. It is basically the log generator shown in Figure 1
driving the anti-log generator shown in Figure 3., The log
generator output from Ai drives the base of Q3 with a voltage proportional to the log of E1/E2. Transistor Qs adds a
vol~ge proportional to the log of E3 and drives the anti-log
transistor, Q4' The collector current of Q4 is converted to an
EREF 15V
R3,
HI
IIOK
'"
11K
21_
1"
EOUT
HI
15.1K
1"
E'N-W~.
C3
151pF
'R3
lK
1"
'1 kO (±1%) at 25'C, +3500 ppmrc.
Available from Vishay Ultronlx,
Grand Junction, CO, Qal SerIes.
TL/H17275-3
FIGURE 3. Anti-Log Generator
'5V
R4
I.IM
1"
TL/H17275-4
FIGURE 4. Cube Generator
the dynamic range of signal processing systems. Also, unlike a linear system, there is no loss in accuracy or resolution when the input signal is small compared to full scale.
Over most of the dynamic range, the accuracy is a pereentof-signal rather than a percent-of-full-scale. For example,
using log generators, a simple meter can display Signals
with 100 dB dynamic range or an oscilloscope can display a
10 mV and 10V pulse simultaneously. Obviously, without the
log generator, the low level Signals are completely lost.
zeroed, if necessary, to improve accuracy with low input
voltages.
The log converters are low level circuits and some care
should be taken during construction. The input leads should
be as short as possible and the input circuitry guarded
against leakage currents. Solder residues can easily conduct leakage currents, therefore circuit boards should be
cleaned before use. High quality glass or mica capacitors
should be used on the inputs to minimize leakage currents.
Also, when the + 15V supply is used as a reference, it must
be well regulated.
To achieve wide dynamic range with high accuracy, the input operational amplifier necessarily must have low offset
voltage, bias current and offset current. The LM 108 has a
maximum bias current of 3 nA and offset current of 400 pA
over a - 55°C to 125°C temperature range. By using equal
source resistors, only the offset current of the LM 108 causes an error. The offset current of the LM108 is as low as
many FET amplifiers. Further, it has a low and constant temperature coefficient rather than doubling every 10"C. This
results in greater accuracy over temperature than can be
achieved with FET amplifiers. The offset voltage may be
REFERENCES
1. R. C. Dobkin, "Feedforward Compensation Speeds Op
Amp", National Semiconductor Corporation, Linear Brief
2, April, 1969.
2. R. J. Widlar, "Monolithic Operational Amplifiers-The
Universal Unear Component", National Semiconductor
Corporation, AN-4, April, 1968.
R8
2K
~
auT " " E.
•
E
>"'--FOR
E,. E•• E. ~D
C7
CI
3DpF
'lIpF
TLlHI727S-S
FIGURE 5. Multiplier/Divider
69
..
C?
~
a
~------------------------------------------------------------------------------------,
~
National Semiconductor
Application Note 31
Op Amp Circuit Collection
SECTION 1-BASIC CIRCUITS
Inverting Amplifier
Non-Inverting Amplifier
RZ
HZ
Rl
Rl
YOUT
VOUT=-~VIN
AI
VOUT=~VIN
AI
AIN = Rl
TLlH/7057-2
TUHI7057-1
Difference Amplifier
Inverting Summing Amplifier
RZ
v,-~"''''_''''''\I\j~--..,
Rl
Rl
v,-AtA,.,.....;,a
R4
RZ
V3-'VI.,."....~
VOUT
R3
VOUT
. AI + A2)· R4
A2
Vour= ( Fi3+"R4 Ai V2-Ai Vl
R3
R4
VOUT
,ForRI = A3 and A2 = R4
.
R5
Vour .= ~(V2
- VIl
AI
VI
V2
Va)
= -A4 ( Ai
+ Fi2 + R3
A5 = A1IIR211R311R4
For minimum offset error
due 10 Input bias current
Tl/HI7057 -3
AIIIA2 = A311A4
For ·mlnlmum offset error
due 10 Input bias current
TLlH/7057-4
Inverting Amplifier with High Input Impedance
Cl
3pF
Non-Inverting Summing Amplifier
. Rl
111M
III
INPUT -~""--4"'--W"",,--e
10K
E,'-~"'.-=t
10K
OUTPUT
'As
= Ik
'Source Impeclenoe
less than lOOk
gives less than I %
R3
gain error.
.
i.1M
for I % accuracy
TLlHI7057-5
1_
C2
lDDpF
'::"
Faat Inverting Amplifier with High Input Impedance
TLlH/7057-6
Non-Inverting AC Amplifier
Cl
5pF
Rl
RZ
1M
IBM
RZ
lDK
III
VOUT
R3
.IDK
OUTPUT
AIN = A3
R3
= R1IIR2
TL/H17057 -8
70
Practical Dlfferentlator
Integrator
C2
INTEGRATE
100
--. !I. . ---.I
V1N-vv".--,
RI
I
le=~
Vour =
I
Ie =
It. = 2.iii1C1 = 2rli2C2
Ie
-
VOUT
RI~I t,VINdl
I
2.iii1C1
RI = R2
For minimum offset error due
to Input bias current
30 pF
< It. < lunity gain
CI
> - - " - VOUT
CI
I
I RESET
R3
R2
TL/H/7057-9
TL/HI7057-10
Fast Integrator
C3
RI
V,N-.J\MIr---t....----1I-----,
Current to Voltage Converter
.---....
RI
..
I----~
--VOUT
VOUT
VOUT
= l,N RI
'For minimum error due to
bias current R2 = RI
TUH17057-12
CI
I5IpF
TL/HI7057-11
Circuit for Operating the LM101
without a Negative Supply
RI
Circuit for Generating the
Second Positive Voltage
,..------4....
R2
+Iav
V'N
R3
+lIV -
+20V
Rl
10K
1%
R2
10K
1%
CI
30pF
....- . - - - - - - - - - - " " " ' TUHI7057-14
TL/HI7057-13
71
_ r-~------------------------------------------------------------------------------~
'1.
Neutrallzlng1nput Capacitance
Double-Ended Umlt Detector
z
cc:
to Optimize Re.pon.e Time
VUT
RZ
Al
>...::....-DUTPUT
INPUT--Jl,JV\o_';"""--~ ~---'
VLT ,; VIN .,; VUT
VOUT ":' f}VIor
TUH17057-1S
VIN
Integrator with Bias CUrTent Compensation
R3*
zaK
< VLT or VIN > VUT
TL/HI7057-19
---t....~RI\j4~-y+
Multiple Aperture Window DISCriminator
15K
V'N~"--..:..i
AZ
2.2M
Rl
V'N-~~~""'4"'-----;;;"-_
C2
>"""4"'-VOUT
01
• Adjust for zero Integrator drift.
Current driIt typically D.l, nlA'C
over - 55'C to 125'C
temperature range.
V,-"'-OUTPUT
___~OUTPUT
RI
2IIIIK
Jt,J~...
RANGE = ±Y
R5
= 1 + R4'+'A2
INPUT
(~)
TL/H17057-22
RZ
IOllS2
-Y
TLlH/7057-21
Offset Voltag. AdJu.tment for Voltage Followers
+y
Offset Voltag. Adju.tm.nt for Differential Ampll"ers
RZ
R3
IK
RI
EI
-"VV\I_.-..
_____
INPUTS
INPUT
RANGE
=
±V
~OUTPUT
RI
>-4t--OUTPUT
EZ-+~M~""
R3
(~)
TLlHI7057-23
R4
10
'::'
RANGE = ±Y
GAIN=~
Rl
Offset Voltage Adjustment for Inv.rtIng
Ampllf'.r. U..ng 18 kO Source R....tanc. or Lass
+y
R3
>-",-OUTPUT
Rl = 2000 R311R4
R411R3 ,; 10 kll
RANGE = ±Y
73
(R3~R4)
TLlH/7057-25
(~) (Rl ~ R3)
TLlHI7057-24
~
CO?
~
;------------------------------------------------------------------------------------------,
SECTION 2-SIGNAL GENERATION '
.>
..
Low Frequency Sine Wave Generator wIth Quadrature Output·
i""",.n'
C2
UhF
'"
...C3,,.F
.~
R3
'OM
'"
~·_._COs.NE
OUTPUT
~
cs
3tpF
R2
12M
to·' liz
1M
0'
UK
UV
'"
02
UV
TUHn057-28
High Frequency Sine Wave Generator with Quadrature Output
.. C3
C2
,,.
ZlGpF
:,
'lOpF
SINE OUTPUT
'"
.--01 ..--..-
COSINE OUTPUT
RI
ZZlK
'"
AI
ZZlK
'".
Ri
2K
D'
1.3V
10
= 10 kHz
D2
UV
TUHn057-27
74
free..Runnlng Multlvlbrator
>--.-
-EOUT
0.01
~F
LI'
OUTPUT
CI
.01
R3
llOK
'1
. '
R2
RI
110K
.
.....
R3
150
>·-.......
CI'
f
Weln Bridge Sine Wave Oscillator
RI
IIOK
.
ZOIK
-- -"."
'"
RI = R2
CI = C2
,
'Chosen for oscillation all 00 Hz
TLlH17057 -28
'Eldema 1869
IOV, 14 rnA Bulb
1= _ _
'_
2"RICI
TL/HI70S7-29
Function Generator
CI
0.1 pF
RI
HZ
10K
1M
TLlH/7057-30
Pulse Width Modillator .
V,N
RI
lOOK
HZ
lOOK
!IV
....----f--
CI
YqUT
,47pF ~
. RS
10K
DI
I.ZY
R3
IlIOn
D2
I.2Y
TLlHI7057 -31
75
Bilateral Currant Source
Bilateral Current Source
RI
R3
1M
2M
•
I" .
HI
IOIK
8.1"
V'N_""""~"
lOUT
I" __'"
__¥""
R3VIN
= 'Fi1Fi5
R3-R4+R5
Rl = R2
R4
I
OUT ~
4UK
0.1"
R3VIN
'Fi1Fi5
-
R3=R4+R5
Rl = R2
~----~~----~-~UT
R4
TLlH/7057-32
1M
I"
TLlHI7057-83
Wain Bridge Oscillator with FET Amplituda Stabilization
3K
SlK
lOll
lOll
Rl = R2
01 = C2
1
L--"'--4~-IIi
I=~
76
TUH/7057-34
!-
Low Power Supply for Integrated CIrcuit Testing
...IV
-'IV
AI JTAIM
A3
5.IK
03
IN1"
I2V
04
LMI03
UK
'"
III
RI
os
01
LMID3
1.7V
IN151
IZV
01
2.7V
RII
UK
6.IK
fOR
le2 =I.IO ..A
1_
]
,,,
III
TRIM
FOR
Ic . ·'.·A
03
2112414
R7
RI
UK
UK
C3
30G ,F
'Vour = lV/kG
VV·
1l.IH17057 -91
TUH17057-35
PositIve Voltage Reference
PosItIve Voltage Referance
r-------------~---v·
01
IN.."
I.8V
RI
YOUT
01
INC."
R2
You,
UV
R3
R4
TUHI7057-37
':"
TL/H/7057-36
77
~
(II)
i
r------------------------------------------------------------------------------------------,
','
Negative Voltage Referel1ce',
'Negative Voltage Reference
01 . ,.
IMII
UV
VOUT
01
IN4I11
UV
AI
\/TLlHI7057-39
TUH/7057-38
Precision Current SInk
Precision ClJl,T8nt Source
AI
-
TL/H/7057-41
TL/H/7057-40
SECTION 3 - SIGNAL PROCESSING
DIHerentlal-lnput Instrumentation Amplifier
HZ
"
1.1"
>·;.....-OUTPUT
,. RI
R3
"
1.1"
1.1"
TLlH/7057-42
78.
Variable GaIn, Dlfferentlal·lnput InstrumentatIon AmplifIer
I
R3
11K
R5
11K
D.I%
0.1%
v,
IALANCE
RZ
R4
11K
1.1%
IDK
D.I%
'Gain adjust
Av
= 10- 4 AS
TUH/7057 -.:I
Instrumentation Amplifier wIth ± 100 Volt Common Mode Range
R3
ot
0.1%
RI
SlK
0.1%
R4
5Kt
0.1%
OUTPUT
A3 = A4
AI = RS = 10R3
Av=~
AS
AI = AS
A2 = A3
'tMatchlng delennlnes common
mode rejection.
= 10A2
+ ...._----INPUTS - - - -.....
TUHI7057 -44
79
Instrumentation Amplifier with
t
10.yolt Common MQde.Range
Rat\" .
lOOK,
0.1%:.
'.'.'1
~.:'
..
" 6
'"-"
114
UK R5'
1% 10K
0.1%
Al=: A4
A2 = R5.
=:.
~6
R7.
t'Matching Determines CMAA
R7t
+
AY=~(I
+~)
R2
R3
lOOK
0.1%
C2
~ lOOpF
TLlHI7057 -45
High Input Impedance Instrumentation AmplHler
R3t
IK
0.1%
RI'
.."""
lOOK
'
. i
114'
lOOK
U,I..,,,
".:'
'
OUTPUT
CI.
C2
~I~PF
'tMalching determines CMI'IA
«
tMay be deleted to maximiZe bandwldih
_
,,""'r.'"
...L. 100 pF ',.'
-=-'
:=
AI " A4; A2
Ay=,1
INP,UTS_+
'.~
=lA3
A1
+Fi2
..
TLlH/7057-45
~" l
Bridge Amplifier with Low Noise Compensation
Ril
~.,.
RI
1M
0.1%
Rl
5111
1"
>;..e.....--OUTPUT
'Aeducas feed through 01
power supply noise by 20 dB
and makee supply bypassing
unneceesery.
tTrim for best common
Rit
1M
0.1%
mode rejection
:!:Gain adjust
TLlH/7057-47
80
Precision Diode
>""-4,-,- V
y'
OUT
E,.
RI
R2
RS1
= RS2
VOUT
= V+
(I
-.!!!.)
RS1
TL/HI7057-48
TL/H17057-49
Precision Clamp
Fast Half Wave Rectifier
R,.
C2
JpF
E,.--'\Nv--4~-------.-EoUT
01
lN914
~--~~~---4~--EOUT
01
INtI.
·EAEF must have a source impedance of lass than 200.11 H
02;8 used.
D2
E"EF·--"'~-.~--'
IN''4
02
lN914
TLlH17057-50
TL/H17057-51
Precision AC to DC Converter
C2
RI
I.""
HK
III
RJ
R2
2IK
III
HI
11K
III
r-~t-~~~--~-~~~-~-~~~--~--EouT
20K
III
DI
INII'
D2
INII.
CJ'
lIpF
'Faadlorward compensation can be used to make a fast full wava rectifier without a fiRar.
TLlHI7057-52
Low Drift Peak Detector
RJ
20K
OUTPUT
CI
3hF
TLlHI7057 -53
81
.. ,------------------------------------------------------------------------------------------,
i
Absolut'~alue Amplifier r.Jth
Polarity Detector
I~T~~~~~----~~r_--~
~=-_4I.... OUTPUT
R3
POLARITY
SIGNAL
R2
R4+R3
R1=~
-
TL/H/7057-54
Sampl, and Hold
qUTPUT
INPUT
'Polyc8rbonate-dielectric capaciIor
SAMPLE
TLIH/7057-65
Sample and Hold
Rl
1M
INPUT
SAMPLE
OUTPUT
*Worst case drift less than 2.5 mVlsec
tTefIon. PoIyeIhyI_ or Polycarbonale
DleIecIrIc C8pacItor
cz
3DpF
82
TL/HI7057-58
Low Drift Integrator
R2
IOBII
y'
Rl
20M
....--tl-~..-RESET
1%
INPUT--"I"",....--..ct·--~.
R3
10K
>-4I__-I-,ourpUT
TLlH/7057-57
Worst case drill less than 500 IN/sec over - WC to + 125"C.
'01 and Q3 should not have Internal gate-protection diodes.
Faet t Summing Amplifier with Low Input Current
cu
INNT-~~~"-----------4I---i
OUTPUT
TL/H/7057-58
, In addition to Increasing apead,1ha LMl01A ralsas high and low frequency
gain, i~ outpu1 drive capability and eliminates tharmal feedback.
t Power BandwIdth: 250 kHz
Small Signal Bandwidth: 3.5 MHz
81_ Rate: 1OVl,...
*
C5
83
= 6 X 10- 8
R,
9- , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
~
Fast Integrator,wlthLow Input Current
RS
01
02
2K
',03
D4
R.
INPUT--.M_.----...,.------4II....----1 .....- -...
RI
150K
'CI
0.102 pF
C3
0.102 pF
>---4t--10UTPUT
R2
,1M
TLlHI7057-59
A~uatable Q Notch Filter
-------,
RI
R2
11M
11M
>,,;'~I-"'''''- VOUT
CI
2JOpF
I
fo -
2.rli1Ci'
.....-
~60Hz
RI = R2 - R3
CI - C2 = C23
R4
....c;siK
TLlHI7057 -60
84
easily Tuned Notch FIlter
R3
4K
•.1%
Rl
4'
'.1%
Tuned Circuit
RZ
VIOl
>;......
- - VOUT
4K
'.1%
VOUT
.,FCl
I _
1
o - 2"'~R1A2C1C2
TLlHf7057-82
R4 - AS
A1
~
R4 =
A3
Yo AI
1
to - 2"'A4J!m;2
TLlHf7057-61
Two-Stage Tuned Circuit
OUTPUT
1
fo -
INPUT
2...JR1R2C1C2
TLlHf7D57-83
85
Negative Capacitance Multiplier ,',
". ".\
R3
IK '"
;.).,;<'
-C_
AI
laM
'"
C2
31pF
TLfHf1OS7 -66
Variable CapacitanCe Multiplier
III
III
RZ
1111
R3
211
... ..:
CI
Ui,.F
C_
TLfHf7057 -66
"
Simulated Inductor
,
",
Capacltanc;e .,ultlpller
,,"
~""~'
tOM
C
~
L;" RI R2CI
I
Rs-R2
Rp
= Rl
= !!!CI
R3
= Vas + IosRI
IL
R3
Rs = R3
A3
IK
-
C2
3O,F
CI
,o""~
TLfHf7057-1fT
Rt
'"
......-
C
,,,
111M
TLfHf7057-68
86
High PaIS Active Filter
HI
l1GK
Cl·
>;"'-4~-DUTPUT
1I.D2""
IIIPIIT---I ~.... -...n--• ....::~
TL/H/7057-71
'Values are for 100 Hz cutoff. Use metallzed polycarbonate capacitors for good temperature stability.
Low Pass Active Filter
CI'
94G,F
~;"'-4""-
HI
OUTPUT
Z4K
INPUT -~Vto~"'~N,,""."";~
TL/HI7057-72
'Values are for 10kHz cutoff. Use silvered mica capacitors for good tamparature stability.
Nonlinear Operational AmplHler with Temperature Compensated Breakpoints
HI
HS
11K
lIUK
H3
QZ
ZNZI05
R4
lOOK
101K
y-. -IIV
HZ
lOOK
HI
10K
OUTPUT
INPUT
•
Cl
30pF
TUH17057-73
87
~
~
~
;------------------------------------------------------------------------------------------,
Current Monitor
saturating Servo Preamplifier with
Rate Feedback
INPUT
VOLTAGE
RZ
tao
t"
R3
t .."
Ct
SOpf~
>-........-OUTPUT
at
MONITOR
OUTPUT
Sv/A
cz
30pF
TLlH/7057-75
TLlH/7057-74
'Flower Booster
,',
',. ,
"
--
"
,
. ."
.
":
QZ
ZIIR2t1
HZ
47'.
I
yTLlH17057-76
,~!...-."".
",
88
,~.
Analog Multiplier
y+
RS
>;.'.-
v,
Y-
YOUT
Ya
TLlHI7057-77
Long Interval Timer
Faet Zero Croaelng Detector
RI
.NPUT -~fIr-41"'"
OUTPUTt
HZ
RZ
310K
03
lMI03
3.3Y
Y--~~"--"
R3
RI
15K
'Low leakage -0.017 p.F per second delay
UK
'----+-y-·-ISY
TL/HI7057 -79
Propagation delay approximately 200 ns
tOTL or TTL fanout of three.
TL/HI7057-78
Miriimize stray capacitance
Pin 8
Amplifier for Piezoelectric Transducer
Temperature Probe
_--.-------4,..-OUTPUT
-
CI
I.,.F
Rt
tK
R3'
HZ
c:::2
-:r
12K
TRANSOUCER
ZS01C
Ri
Z4.3K
1%
'Set for OV at O'C
tAdjust for 100 mvrc
-tty - - . - - - - - - - - '
TLlHI7057-81
Low frequency cu10ff - Rt CI
TLlHI7057-80
89
..CO?
z:
4(:
Photodlode Amplifier
Photodlode Amplifier
HI
HI
liM
I"
> .........V
OUT
OUTPUT
VOUT * Rlla.
Your = 10VlpA
TUH/7057-82
-
TUH/7057-83
'Operating pholodloda with lass than 3 mY
across H eliminates leakage Cumllllll.
High Input Impedance AC Follower
CI
UI"F
INPUT.---i
~""-411""- OUTPUT
~. .- -..
Tl/H/7057-84
. TemPera~re Compensated Logarithmic Converter
YO.ISV
ZNZIZO
113"
.UM
1"
INPUT-'lNii-. .- -..... I - - -.....
tl k!I (±I%)at25"C, +3500ppmrc.
Available ""'" VIShay Ultronix,
Gland Junction, CO, Q81 ~
RZ
'~nas CUINI1I
ZK
for ~
crossing on ou\pUt 10 pA
as shown.
HI
IUK
111
Sit
IK
+G.3lII C
C4
lSOpF
CI
3118pF
TUH/7057-85
10 nA < liN < I rnA
Sensitivity Is 1V per decade
90
!-
...
.
I!i
a"
!
i
I
,. I.
....
II:
·1
""2
I!
" ,,~
91
.- r-------------------------------------------------------------------------------------~
~.
Multiplier/Divider
I
RI
IGlII
1%
£,
R7
1.5M
1%
15V~MM...- - - - - - . "
RI
1.5M
TVH/7067-11
92
FaIt Log Generator
E...
\IV
R3
IIIK
r-------------~QI~------~
__
.,1
------~
R4
CI
2K
lDpF
RON
-y",..,...-..:.t
11K
Eo.
RS
ll1K
louT
tl kfi (±1%) at 25"C, +3500 ppmrc.
Available from Vishay Uilronix,
Grand Junction, CO, 081 Series.
Cl
3"pF
cz
71pF
C3
IpF
T1JH/7057 -89
AntI-Log Generator
louT
RI
tl kfi (±1%) at 25"C, +3500 ppmrc.
Available from Vishay Ullronilc,
Grand Junctfon, CO, 081 Sariaa.
ll1K
Tl/H/7057 -90
93
=
'~' FET Circuit Application$
;' , Nation'al Semiconductor
Application Note 32
;'"
....-o OUTPUT
>~
"
INPUT
, 'r~~
o-..--~
J \.
"
SAMPLE
,'PoIycarbonate dielectric
.-- +15V, SAlllPL~
L.J -15V
HO.l,O
-,
'
~."
\','
TLlH/8791-1
Sample and Hold With Oflaat Adjustment
The 2N4339 JFET was selected because of its low IGSS
age. Leakages of this level put the burden of circuit perform- •
« 100 pAl, very-low IO(OFF) «50 pAl and low pinchoff vQIt-,' ,/ilOC8 on clean, solder-resin free, low leakage circuit layout
RESET
r - -...."""'::---4,..-oV+
2N3&84
__--+-00 OUTPUT
RI
2N3&88
TLlH/8791-3 :
-IIV
TLlH/6791-2
Long Time Comparator
The 2N4393 is operated as a Miller Integrator. The high Vis
of the 2N4393 (over 12,000 p.mhos @ 5 mAl yields a stage
gain of about 60. Since the equivalent capacitance looking
into the gate Is C times gain and the gate source resistance
can be as high as 10 MO, time constants as long as a
minute can be achieved.
JFET AC Coupled Integrator
This circuit utilizes the ",...-amp" technique to achieve very
high voltage gain. Using Cl in the circuit as a Miller Integra- '
tor, or capacitance multiplier, allows this simple circuit to '
handle very long time constants.
'
+30V
2.2M
.001 jJF
~N ~ :;-II--I--"'-~~h
en. <: .2& pF
10M
OUTPUT
1M
TLlH/6791 -4
Ultra-High ZIN AC Unity Gain Amplifier
Nothing is left to chance in reducing input capacitance. The
2N4416. which has low capacitance in the first place. is
operated as a source follower with bootstrapped gate bias
resistor and drain. Any input capacitance you get with this
circuit is due to poor layout techniques.
SHUNT
P£AKING COIL
+V
1--t....---400UTPUT
2N3823
TLlH/6791 -6
TLlH/6791 -5
FET Cascode Video Amplifier
JFET Pierce Crystal Oscillator
The FET cascode video amplifier features very low input
loading and reduction of feedback to almost zero. The
2N3823 is used because of its low capacitance and high
Yfa. Bandwidth of this amplifier is limited by RL and load
capacitance.
The JFET Pierce crystal oscillator allows a wide frequency
range of crystals to be used without circuit modification.
Since the JFET gate does not load the crystal. good Q is
maintained thus insuring good frequency stability.
95
..;---------------------------------------------------------------------------------,
~
CW)
z
cc
.iV- .
ZM
UK
10M
IVf
",.,
UK
SEll$.
SZ8
SZC
,', SK
• ,f.'
OFF
8M
,
5Y
,/
1M
'J'
,
IOV
BOOK
ZN4348
1M
'1;
.....
~
3.3M
lK
SOV
lOOK
IDlY
10K
,,---o5OClY
loil
,,---oIOOOV
SZA
10K
. ,:;
",
TUH/6781-7
FETVM-FET Voltmeter
This FETVM replaces ttifl function ot the VTVM while at the
same time ridding the instrument pf the usual line cord. In
addition, drift r~tes .are flil/",supepor to vacuum tube circuits
O.5~~1t
scal~
"';hl~h
allowing a
full
range
is impractical with
most vacuum tllbes. The low-lea!",~-oOUT"'T
0':.
IIOK
.1033.F
.1033F
TL/H/8791-8
HI-FI Tone Control Circuit (High Z Input)
The 2N3684 JFET provides the function of a high input
impedance and low noise characteristics to buffer an op
amp-operated feedback type tone control circuit.
Rs
DiffERENTIAL
INSTRUME.T
INPUT
>"~ODUTPUT
As
OoJV..,.,--!-.,
TOGGLE
DRIVE
- - - TO ADDITIDNAL
_ _ _ MULTIPLEX STAGES
~~~~r:-4""'0TDGGLE
..
DRIVE
R".scALlNG RESISTORS
DIFFERE.TIALQ.---JI,J..,.,---.......
INSTRUMENT
Rs'
INPUTQ._ _ _
JV""_------I
TL/H/6791-IO
Differential Analog Switch
(- 25 to + 125D CJ, this makes it an unusual but ideal choice
for an accurate multiplexer. This close tracking greatly reduces errors due to common mode signals.
The FM1208 monolithic dual is used in a differential multiplexer application where ROS(ON) should be closely
matched. Since ROS(ON) for the monolithic dual tracks
at better than ± 1% over wide temperature ranges'
IK
....-"lM_-o+ISV
:-1
.OI.F
ISOK
24K
INPUT
(Clt--. .-~.....,
.004~
OUTPUT
":"
828K
470
22K
330K
.--------4t-~.,..,.-_o -15V
IK
TUH/6791-11
Magnetic-Pickup PhORO Preamplifier
This preamplifier provides proper loading to a reluctance
phono cartridge. it provides approximately 25. dB of gain at
1 kHz (2.2 mV input for 100 mVoutput), it features S + N/N
ratio Of better .than - 70 dB (referenced to 10 mV input at
1 !tHz) .and has a dynamic range of 84 dB (referenced to
1 kHz). The feedback provides for RIM equalization.
9.7
~ ~-----------------------------------------------------------------------------------------,
~
zc(
+IV
lK
BIPOLAR
LOGIC
ELEMEMT
MOS
LOGIC
ELEMENT
WITH
NEGATIVE
SUPPLY,
-v
GAIN CONTROL
-v
TL/H/6781-12
TL/H/6781-13
Negative to Positive Supply LogiC Level Shifter
This simple circuit provides for level shifting from any logic
function (such as MOS) operating from minus to ground
supply to any logic level (such as TIL) operating from a plus
to ground supply. The 2N~970 provides a low rds(ON) and
fast switching times.
"
Variable Attenuator
The 2N3685 acts as a voltage variable resistor with an
ROS(ON) of 8000 max. The 2N3685 JFET will have linear
resistance over several decades of resistance providing an
excellent electronic gain control.
2_1
21143t11
VIDEO
VlOEO
INPUT
OUTPUT
-1.Vo-+....,
1.~~'-----------~~~
\
\
":" \
~'0I1uf
-=-
\ 1.><11-\----.....
\
\
,
, '-- --.l-O
TLlH/6781-14
Voltage Controlled Variable Gain Ampllfle"
The 2N4391 provides a low ROS(ON) (less than 300). The
tee attenuator provides for optimum dynamic linear range
for attenuation and if complete turnoff is desired, attenua-
tion of greater than 100 dB can be obtained at 10 MHz
providing proper RF construction techn,iques are employed.
_-----...-oy+
I. '
~+---oVOUT
Av
i
= = 500 TYPICAL
,.= Yoo
Yia
TLlH/6791-15
Ultra-High Gain Audio Amplifier
Sometimes called the "JFET" p. amp," this 'circuit provid~
a very low pOwer, high gain amplifying function. Since p. of a
JFET increases as drain current decreases, the lower d(ain
current is, the more gain you\ get. You do saa,ifice input
dynamic 'range within<:reasing gain" however.
"
98
'K
,%
INPUT
>-"'~JOUTPUT
TL/H/6791-16
Level-Shlftlng-laolatlon Amplifier
The 2N4341 JFET is used as a level shifter between two op
amps operated at different power supply voltages. The
JFETls ideally suited for this type of application because
10 = Is·
r-J\J~-D+V
...
_1
r----~ _-Ov+
0
V'N
+5IV
PAElIAI 0-"';"'-4.
LINE
ZNZZII
10K
I
VIN
o -,jf1"
OTL·TTL
IIPOLAR
LOGIC
VIN> OV
TLlH/6791-16
·Trademark of the
B"1'"OU9hs COIp.
TlIH/6791-17
FET Nlxla· Drivers
Precision Current Sink
The 2N3684 JFETs are used as Nixie tube drivers. Their Vp
of 2-5 volts ideally matches DTL-TTL logic levels. Diodes
are used to a + 50 volt prebias line to prevent breakdown of
the JFETs. Since the 2N3684 is in a T0-72 (4 lead T0-18)
package, none of the circuit voltages appear on the
The JPET is immune to almost all of the failure mechanisms
found in bipolar tr~sistors used for this application.
The 2N3069 JFET and 2N2219 bipolar have inherently high
output impedance. Using R, as a current sensing resistor to
provide feedback to the LM101 op amp provides a large
amount of loop gain for negative feedback to enhance the
true current sink nature of this circuit. For small current values, the, 10k resistor and 2N2219 may be eliminated if the
source of ,he JFET is connected to R1'
can.
99
....- ...--0+_
+3OV
r·-:-U--,
I
.,
1
FROM
r-I4J.----~I..._:..
!:'!"'!""~'-O :~~~~TOR .
1
I·
1
..J..
-rI
I
I
I
...J..
..,....
I
TUH/6791-19
JFET-Bipolar ea.code Circuit
The JFET-Bipolar casccide circuit will provide full video output for the CRT cathode drive. Gain is about 90. The cascode configuration eliminates Miller capacitance problems
with the 2N4091 JFET. thus allowing direct drive from the
video detector. An m derived filter ulling stray capacitance
and a variable inductor prevents 4.5 MHz. sculld frequency
from being emplified bY the video amplif~.
~1&v
*PpIycarbonate dielectric capacitor
M
r-+1&V ISAMPLEI
..... L..I _IIIV (HOLDI
.LOW Drift Sample a,,~ Hold
TLIH/6791-20
and Q2 IGSS « 100 pAl as the only disehargepaths. Q2
serves a buffering function so feedback to the LM101 and
output current are supplied from Its source.
The JFETs. Q1 and Q2. provide complete buffering to C1.
the sample and hold capacitor. During sample. Q1 is turned
on and provides a path. rds(ON). for charging C1. During
held. Q1 is turned off thus leaving Q1 ID(OFF) «50 pAl
100
+11V 01
~ZOVQFF
lIa•• , O - - - - J
> ...- - 0 OUTPUT
.....---o.,IV
. . .-----0 -IIV
TLlH/8791-21
TLlH/6791-22
Weln Bridge Sine Wave Oscillator
JFET Sample and Hold Circuit
The major problem in producing a low distortion, constant
amplitude sine wave is getting the amplifier loop gain just
right. By using the 2N3069 JFET as a voltage variable resistor in the amplifier feedback loop, this can be easily
achieved. The LM103 zener diode providas the voltage reference for the peak sine wave amplitude; this is rectified .
and fed to the gate of the 2N3069, thus v8rying Its channel
resistance and, hence, loop gain.
The logic voltage is applied simultaneously to the sample
and hold JFETs. By matching input impedance and feedback resistance and capacitance. errors due to rds(ON) of
the JFETs is minimized. The inherent matched rds(ON) and
matched leakage currents of the FM1109 monolithic dual
greatly Improve circuit performance.
_ - -..-ov.
IK
I.
100
IK
HII3I
V,.O-.....~......,
2,,"1.
,,--"-4:)VOUT
TLlH/8791-24
TLlH/8791-23
HIgh Impedance Low
ca,.cItence Wideband Buffer
High Impedance Low capacltanC18 Amplifier
The 2N4416 features low input capacitance which makes
this compound-series feedback buffer a Wfde..band unity
gain amplifier.
This compound series-feedback circuit provides high input
impedance and stable, wide-band gain for general purpose
video amplifier applications.
101
Nr-----------------------------------------------------------------------------~
~
-BV
~'
r - -...-~--'-.;.'..l.';.'..............;..;.......-
UK
.........."O+12V
v,.o-+~~
1M
':'
TLlH/e79I-25
' I
Stable Low FI1IqIItIncy Crystal Oacillator
This Co/pltts-Crystal OScIllatOr is ideai for low frequency
crystal oscillator circuits. Excellent stability is assured because the 2N3823 JFeT circuit loading does not vary with
temperature.
."
~
po
TUH/6791-28
I
Ii to 3W Pllaae Shlft~
Each stage provid~ to 1sO- phase shift. By ganging the
two stagas. 0" to 360" phase shift Is achieved. The 2N3070
JFETs are ideal since they do not load the phase shift networks.
'
.. /
,.'
',.i:'
!''.
,
~:,'
,
DTL·nL Controlled Buffered Analog Switch
2N4860
This analog switch U!I88the
JFET for its 25 ohm
rON and low leakage. THe LM102 serves as a voltage buffer.
This circuit can b$ Iidapted to a du~ trace oscilloscope
:!. .'
"
.,
:;.'
,i,
~
chopper. The DM7800 monoli~ic 'I,C.:'provides adequate
switch drive controll~ DTI,~TT.I;.,logiC le,vels.
..t
'1' .'~
-Va
20 MHz OSCILlATOR VALUES
Cl • 700 pF
Ll;;' 1.3
C2 = 75 pF
L2 = 1OT ~/[IIA >,I.' LONG
Veo * 16V
10 = 1 rnA
I'ii:
.~u
,
'
"Jt,/'tj",,",OV••
18l'MHzdScil:jjiroFrpER~iiANcE;"
..c:, "LOWpIIlT~TI<;lN2OMHzOSC" .,,)l - " . ,
'" "
~
':'
'2,ND Hi\fItooIONlC ,,,:60 d~.·. Ii
, ' , '. •,'
'
SRO HARMONIC> -70 dB
"'-~""'----4
41"
TLlH/8791-28
Low Dlatortion OtIcIllator
The 2N4416 JFET is capable of oscillating In a circuit where
harmonic distortion is very low. The JFET local oscillator
is excellent when a low harmonic content is required for a
good mixer circuit.
+-~F--tCl'JDUTPUT
AGCRANGEn ••
POWER GA.N.".
LI •.07 ,,"y CENlERlAP
U·.87 ,,"yTAP.14UP FROM GROUND
'='
TL/H/6791-29
200 MHz Caacode Amplifier
This 200 MHz JFET cascode circuit features low crossmodulatlon, large-signal handling ability, no neutralization, and
AGe controlled by biasing the upper cascode JFET. The
only special requlrament of this circuit is that loss of the
upper unit must be greater than that of the lower unit.
r-----------t---~.v
+
OUTPUT
IIIK
IIIK
Ik
3D.F
-v
TLlH/6791-30
FET Op Amp
The FM3954 monolithic-dual provides an ideal low-offset,
low-drift buffer function for the LM101A op amp. The excellent matching characteristics of the FM3954 track well over
its bias current range thus improving common mode rejection.
cor:,r,::~~o-fIIIIII~""""W\r-"4~""'14-0-lIv
ON +1.
OFF -21
'.114
,.114
L..I=- FROM OIPIDO
100pF
TLlH/6791-31
High Toggle Rate High Frequency Analog Switch
This commutator circuit provides low impedance gate drive
to the 2N3970 analog switch for both on and off drive conditions. This circuit also approaches the Ideal gate drive conditions for high frequency signal handling by providing a low
ac impedance for off drive and high ac impedance for on
drive to the 2N3970. The LH0005 op amp does the job of
amplifying megahertz signals.
103
.r-----------------------------------------------------------------------,
!i?
z~
"-+_I)IIIPUT 1
r'----"'1
I
r
~~"-OINPUT2
OTL
TTL
1M
INPUTS
;
:
~-"_OIN'UT.3
1M
':·3 !:::
,\'
i1\,-"-O 1.'UTt.
"
•
1M
'--------00
L _____ .J
DM7181
VOLTAGE TRANSlATOR
OUTPUT
TL/H/6791-32
4-Channel CommutatOr
This 4-channel commutator uses the 2N4091 to acllieve low
channel ON resistance «300) and low OFF ..ourrent leak·
age. The DM7800 voltage translatorie a monolithic device
..
,: .w./lic.hproyjdes from + 10V to - 20V gate drive to the
JFETswhile at tne same time providing DTL·TIL logic com.: patability.
.
RI
0.1
POSITIVE
1%
INPUT()O-.~N\I-"--O TO LOAD
VOLTAGE
_,'I
. MONITOR
• OUTPUT
•
5V/A
. RI R3
VOUT =R2"ll
'~, ",
,'
.
'.-.Current
,
~.
ruH/6791-34 .
Monftor
!,
R, senses current flow of a power supply. The JFET is used
as a buffer because 10 = Is. therefore the output monitor
"\
voltage accurately (8fIects the pow. StJpply ClJrrent flow:
104
TO C_ANION CIIANII£L
fOR mREO CIRCUIT
----4,..-..--....-...
r - - -...- -..
-D
,,.,
.!lV
: SO dB .,00 MHz
, INSERTION LOSS .. 8 dB
-
1M
1M
OFF
TLfH/6791-38
High Frequency SWitch
The 2N4391 provides a low on-resistance of 30 ohms and a
high off-impedance «0.2 pF) when off. With proper layout
and an "ideal" switch, the performance stated above can
be readily achieved.
106
National Semiconductor
Application Note 41
Precision IC Comparator
Runs from + 5V
Logic Supply
Robert J. Widlar
Apartado Postal 541
Puerto Vallarta, Jalisco
Mexico
Introduction
In digital systems, it is sometimes necessary to convert low
level analog signals into digital information. An example of
this might be a detector for the illumination level of a photodiode. Another would be a zero crossing detector for a magnetic transducer such as a magnetometer or a shaft-position pickoff. These transducers have low-level outputs, with
currents in the low microamperes or voltages in the low millivolts. Therefore, low level circuitry is required to condition
these signals before they can drive logic circuits.
A voltage comparator can perform many of these precision
functions. A comparator is essentially a high-gain op amp
designed for open loop operation. The function of a comparator is to produce a logic "one" on the output with a positive
signal between its two Inputs or a logic "zero" with a negative signal between the inputs. Threshold detection is acCOmplished by putting a reference voltage on one input and
the signal on the other. Clearly, an op amp can be used as a
comparator, except that its response time is in the tens of
microseconds which is often too slow for many applications.
A unique comparator design will be described here along
with some of its applications in digital systems. Unlike older
IC comparators or op amps, it will operate from the same 5V
supply as DTL or TTL logic circuits. It will also operate with
the single negative supply used with MOS logic. Hence, low
level functions can be performed without the extra supply
voltages previously required.
The versatility of the comparator along with the minimal circuit loading and considerable precision recommend it for
many uses, in digital systems, other than the detection of
low level signals. It can be used as an oscillator or multivibrator, in digital interface circuitry and even for low voltage
analog circuitry. Some of these applications will also be discussed.
circuit description
In order to understand, how to use this comparator, it is necessary to look briefly at the circuit configuration. Figure 1
shows a simplified schematic of the device. PNP transistors
r--4~--~----~------~----V+
R4
800
OUTPUT
R8
3
GROUND
113
,511Of'A
..
~
-----e~--~~---------v
TUH/7303-1
Figure 1. Simplified schematic of the comparator
buffer the differential input stage to get low input currents
without sacrifiCing speed. The PNP's drive a standard NPN
differential stage, 03 and 04. The output of this stage is
further amplified by the 05-06 pair. This feeds 09 which
provides additonal gain and drives the output stage. Current
sources are used to determine the bias currents, so that
performance is not greatly affected by supply voltages.
107
~
i
r------------------------------------------------------------------------------------------,
ThEl'OIJiPIlt transistor is 0", and it is protectedbyO,O and
, Rs which limit the peak olltput current. 1:heoutput lead,
, ,'since it is not connected to any other point in the circuit, can
either be, returned to the positive supply through a pull-up
resistor or switch loads that are connected to a voltage
higher than the positive supply voltage. The circuit will operate from a single supply if the negative supply lead is connected to ground. However, if a negative supply is available,
it can be used to increase the inpllt common mode range.
Table I summarizes the performance of the comparator
when operating from a 5V supply. The circuit will work with
mon,mode range of the IC. The output will directly driveOTL
or TTL.' The exaCt value of the pull up resistor, Rs, is deter·
mined by the speed required from the circuitsillC!'!' it must
drive any capacitive loading for posltive'going outPllt signals. An optional offset-balancing circuit using R3 and A4 is
'
included in the schematic. "
Figure 3 shows a connection for operating with MOS logic.
This is a level detector for a photodiode that operates off a
-10V supply. The output changes state when the diode
current reaches 1 pA Even at this low current, the error
contributed by the comparator is less than 1 %.
Table I. Important electrical characteristics of the
LM111 comparator when operating from single,
5V supply (TA = 25"C)
Umlts
Parameter
Min
Input Offset Voltage
Units
Typ
Max
0.7
3
mV
nA
Input Offset Current
4
10
Input Bias Current
60
100
Voltage Gain
100
V/mV
Response Time
200 '
ns
Common Mode Range
0.3
3.8
nA
50
V
Outpllt Current
50
rnA
5
,rnA
Supply Current
HZ
1M
--4...- ........-y-. ~Iav
TLlHI7303-3
V
Outpllt Voltage Swing
Fan Out (OTL/TTL)
HI
2.IM
Figure 3. Level detector to~ photOdlode
Higher threshold currents can be obtained by reducing R1,
R2 and R3 proportionally. At the swltclilng point, the voltage
,across the photodiode is nearly zero, so its leakage current
does not cause an error. The olltput switches between
ground and -10V, driving the data inputs of MOS logic directly.
8
3
supply voltages up to ± 15V with a corresponding Increase
in the input voltage range. Othl'lr characteristics are essentially unchanged at the higher voltages.
The circuit In Figure 3 can, of course, be adapted to work
, with a 5V supply. At any rate, the accuracy of the circuit will
depend on the supply-voltage regulation, since the reference is derived from the supply. F/{/ure 4 shows a method
low level applications
A circuit that will detect zero crossing in the output of a
magnetic transducer within a fraction of a millivolt is shown
in Figure 2. The magnetic pickup is connected, between the
two inputs of the comparator. The resis«ve divider, R, and
R2, biases the inpllts 0.5V above ground, within the com-
HI
3111
HI
UK
Dl
,LM113
UV
-
HZ
III
TLlHI7303-4
Figure 4. PreCision level detector tor photodlode
of making performance independent of supply voltage. 0, is
a temperature-compensated reference diode with a 1.23V
breakdown voltage. It acts as a shunt regulator and delivers
a stable voltage to the comparator. When the diode current
is large enough (abollt 10 pA) to make the voltage drop
MAGNETIC
PICKUP
TL/H/7303-2
Figure 2. Zero crossing detector tor magnetic transducer
108
The comparator can be strobed, as shown in Figure 6, by
the addition of 01 and Rs. With a logic one on the base of
01, approximately 2.S mA is drawn out of the strobe terminal of the LM111, making the output high independent of
the input signal.
across Rs equal to the breakdown voltage of D1, the output
will change state. R2 has been added to make the threshold
error proportional to the offset current of the comparator,
rather than the bias current. It can be eliminated if the bias
current error is not considered significant.
A zero crossing detector that drives the data input of MOS
logic is shown in Figure 5. Here, both a positive supply and
"'---"'---"'-V+'5V
R3
IZK
,,--.-V··5V
INPUT.....WIr-. .RI
Z4GK
...--f-.i.4
CI
RZ
41K
TTL
STROBE
RZ
11K
V-'-IOV
"='
TL/H/7303-6
TL/HI7303-5
Figure 6. Circuit for transmitting data between high-level logic and TTL
Sometimes it is necessary to transmit data between digital
equipments, yet maintain a high degree of electrical isolation. Normally, this is done with a transformer. However,
transformers have problems with low-duty-cycle pulses
since they do not preseve the dc level.
The circuit in Figure 7 is a more satisfactory method of obtaining isolation. At the transmitting end, a TTL gate drives a
gallium-arsenide light-emitting diode. The light output is optically coupled to a silicon photodiode, and the comparator
detects the photodiode output. The optical coupling makes
possible electrical isolation in the thousands of megohms at
potentials in the thousands of volts.
The maximum data rate of this circuit is 1 MHz. At lower
rates (- 200 kHz) Rs and C1 can be eliminated.
Figure 5. Zero crossing detector driving MOS logic
the -10V supply for MOS circuits are used. Both supplies
are required for the circuit to work with zero common-mode
voltage. An alternate balancing scheme is also shown in the
schematic. It differs from the circuit in F/{Jure 2 in that it
raises the input-stage current by a factor of three. This increases the rate at which the input voltage follows rapidlychanging signals from 7V /IJ-S to 1aV/ ,""s. This increased
common-mode slew can be obtained without the balancing
potentiometer by shorting both balance terminals to the
positive-supply terminal. Increased input bias current is the
price that must be paid for the faster operation.
digital Interface circuits
Figure 6 shows an interface between high-level logic and
DTL or TTL. The input signal, with OV and 30V logic states is
attenuated to OV and SV by R1 and R2' Rs and R4 set up a
2.SV threshold level for the comparator so that it switches
when the input goes through 1SV. The response time of the
circuit can be controlled with C1, if desired, to make it insensitive to fast noise spikes. Because of the low error currents
of the LM111, it is possible to get input impedances even
higher than the 300 kO obtained with the indicated resistor
values.
v· = 5V
multlvlbrators and OSCillators
The free-running multivibrator in Figure 8 is another example of the versatility of the comparator. The inputs are biased within the common mode range by R1 and R2. DC
stability, which insures starting, is provided by negative
feedback through Rs. The negative feedback is reduced at
high frequencies by C1. At some frequency, the positive
feedback through R4 will be greater than the negative feedback; and the circuit will oscillate. For the component values
r------~
__
- - _ 4 t _ - -__~V··5V
R5
SK
TTL
R3
OUTPUT
lK
HZ
50K
CI
0.01
~F
TLlH17303-7
Figure 7. Data transmission system with near-Infinite ground Isolation
109
,. r------------------------------------------------------------------------------------------,
9-
~
shown, the circuit delivers' a 100kHz square wave output.
The frequency can be changed by varying Cl or by adjusting
Rl through R4, 'while keeping their ratios constant.
Because of the low input current of the comparator, large
circuit impedances can be used. Therefore, low frequencies
can be obtained with relatively-small capacitor values: it is
no problem to get down to 1 Hz using a 1 p.F capacitor. The
speed of the comparator also permits operation at frequencies ab~ 100 kHz.
RI
24K
Y+·SY
tive feedback is obtained through a quartz crystal. The circuit oscillates when transmission through the crystal is at a
maximum, so tha crystal operates; in its series-resonant
RI
Y+'SY
R4
2K '
lOOK
RS
IK
R3
IUK
>.:...-..-
R2
IDaK
OUTPUT
R3
,SDK
SQUARE
>:.e...... WAVE
OUTPUT"
R4
41K
R2
TL/H/7303-9
Figure 9. Crystal-controlled oscillator
24K
mode. The high input impedance of the comparator and the
isolating capacitor, ~, minimize loading of the crystal and
contribute to frequency stability. As shown, the oscillator
delivers a 100kHz square-wave oUtput. '
TUH/7303-8
"TTL or DTL Fanout of two.
Figure 8. Fr...-unnlng multlvlbrator
frequency doubler
In a digital system, it is a relatively Simple matter to ,divide by
any integer. However, multiplying by an integer is quite another story especially if operation over a wide frequency
range and waveform symmetry, are required.
A frequency doubler that satisfies the above requirements is
shown in Figure 10. A comparator i,1I used to shape th~ in-
The frequency of oscillation depends almost entirely on the
resistance and capacitor values because of the precision of
the comparator. Further, the frequency changes by only 1%
for a 10% change in supply voltage. Waveform symmetry is
also good, but the symmetry can be' varied by changing the
ratio of Rl to R2.
A crystal-controlled oscillator that can be used to generate
the clock in slower digital systems is shown in Figure 9. It is
similar to the free running multMbrator, except that the posi-
V+.IV
HI
10K
H3
,IIIP\IT---+---'~
UK R4
lOOK
HI
5.IK
1/4DM1i488
o
DUIPUI
,H5
IOIK
Frequency Range
Input-5 kHz 10 50 kHz
....- - - - - - - - - - - - - - - - - -... OUtput-l0 kHz 10 100 kHz
TUH/7303-10
Figure 10. Frequency doubler
110
put signal and feed it to an integrator. The shaping is required because the input to the integrator must swing between the supply voltage and ground to preserve symmetry
in the output waveform. An LM108 op amp, that works from
the SV logic supply, serves as the integrator. This feeds a
triangular waveform to a second comparator that detects
when the waveform goes through a voltage equal to its average value. Hence, as shown in Figure 11, the output of the
RRSl' COMPARATOR
ampUl
r-1 . ,
---1 L...J
L
INTEGRATORDI/TPIIT
~
SECOND COMPARATOR . . ,
OI/TPIIT
......,
L...J
ClRCUITDUTPIIT
the linear region with source resistances above 10 kn, because the 1 MHz open loop gain of the comparator is about
80 dB. However, this does not affect the dc characteristics
and is not a problem unless the input signal dwells within
200 /LV of the transition level. But if the oscillation does
cause difficulties, it can be eliminated with a small amount
of positive feedback around the comparator to give a 1 mV
hysteresiS.
Stray coupling between the output and the balance terminals can also cause oscillations, so an attempt should be
made to keep these leads apart. It is usually advisable to tie
the balance pins together to minimize the effect of this feedback. If balancing is used, the same result can be accomplished by connecting a 0.1 /LF capaCitor between these
pins.
r-
L...J
Normally, individual supply bypasses on every device are
unnecessary, although long leads between the comparator
and the bypass capaCitors are definitely not recommended.
If large current spikes are injected into the supplies in
SWitching the output, bypass capacitors should be included
at these pOints.
lJ'UlJ1I
TL/H17303-11
Figure 11_ Waveforms for the frequency doubler
second comparator is delayed by half the duration of the
input pulse. The two comparator outputs can then be combined through an exclusive-OR gate to produce the doublefrequency output.
When driving the inputs from a low impedance source, a
limiting resistor should be placed in series with the input
lead to limit the peak current to something less than
100 mAo This is especially important when the inputs go
outside a piece of equipment where they could accidentally
be connected to high voltage sources. Low impedance
sources do not cause a problem unless their output voltage
exceeds the negative supply voltage. However, the supplies
go to zero when they are turned off, so the isolation is usually needed.
With the component values shown, the circuit operetes at
frequencies from S kHz to SO kHz. Lower frequency operation can be secured by increasing both C2 and C4.
application hints
One of the problems encountered in using earlier IC comparators like the LM710 or LMl 06 was that they were prone
to erratic operation caused by oscillations. This was a direct
result of the high speed of the devices, which made it mandatory to provide good input-output isolation and low-inductance bypassing on the supplies. These oscillations could
be particularly puzzling when they occurred internally, showing up at the external terminals only as erratic dc characteristics.
Large capacitors on the input (greater than 0.1 /LF) should
be treated as a low source impedance and isolated with a
resistor. A charged capacitor can hold the inputs outside the
supply voltage if the supplies are abruptly shut off.
Precautions should be taken to insure that the power supplies for this or any other IC never become reversed-even
under transient conditions. With reverse voltages greater
than lV, the IC can conduct excessive current, fuzing internal aluminum interconnects. This usually takes more than
O.SA. If there is a possibility of reversal, clamp diodes with
an adequate peak current rating should be installed across
the supply bus.
In general, the LM111 is less susceptible to spurious oscillations both because of its lower speed (200 ns response time
vs 40 ns) and because of its better power supply rejection.
Feedback between the output and the input is a lesser problem with a given source resistance. However, the LM111
can operate with source resistance that are orders of magnitude higher than the earlier devices, so stray coupling between the input and output should be minimized. With
source resistances between 1 kn and 10 kn, the impedance (both capacitive and resistive) on both inputs should
be made equal, as this tends to reject the signal fed back.
Even so, it is difficult to completely eliminate oscillations in
No attempt should be made to operate the circuit with the
ground terminal at a voltage exceeding either supply voltage. Further, the SOV output-voltage rating applies to the
potential between the output and the V- terminal. Therefore, if the comparator is operated from a negative supply,
the maximum output voltage must be reduced by an amount
equal to the voltage on the V- terminal.
111
.. r-------------------------------------------------------------------------------------,
i
The output circuitry is protected for shorts across the load. It
will not, for example, withstand a short to a voltage more
negative than the ground terminal. Additionally, with a sustained short, power dissipation can become excessive ,if the
voltage across the output transistor exceeds about 10V.
ThEiinput terminals can exceed the positive supply voltage'
without causing damage. However, the 30V maximum rating
between the inputs and the V- terminal must be observed.
As mentioned earlier, the inputs should not be driven more
negative than the V- terminal.
conclusions
A versatile voltage 'comparator that can perform many of the
precision functions required in digital systems has been produced. Unlike older comparators, the Ie can operate from
the same supply voltage as the digital Circuits. The comparator is, particularly 'useful in circuits requiring con~iderable
sensitivity and accuracy, such as threshold detectors lor low
level sensors, data transmission circuits or stable oscillators
and multivibrators.
'
The comparator can also be used in many analog systems.
It operates from standard ,± 15V op amp supplies, and Its dc
accuracy equals some 01 the best op amps. It is also an
order of magnitude, ,faster than op amps' used, as comparators.
The new comparator is 'Considerably more flexible than older devices. Not only will it drive RTL, DTL and TTL logic; but'
also it can interface with MOS logic or deliver ± 15V to FET
analog switches. The output, can switch 50V, ~O mA loads,
making it useful as a driver for relays, lamps or light-emitting
diodes. Further, a unique output stage enables it to drive
loads referred to either supply or to ground and provide
ground isolation between the comparator inputs and the
load.
"
The LM111 is a plug-in replacement lor comparators like
the LM710 and LM106 in applications where speed is not of
prime concern., Compared to its predecessors in other respects, it has many improved electrical specifications, more
design flexibility and fewer application problems.
112
National Semiconductor
Application Note 42
IC Provides On-Card
Regulation for
Logic Circuits
Robert J. Widlar
Apartado Postal 541
Puerto Vallarta, Jalisco
Mexico
Introduction
Because of the relatively high current requirements of digital
systems, there are a number of problems associated with
using one centrally-located regulator. Heavy power busses
must be used to distribute the regulated voltage. With low
voltages and currents of many amperes, voltage drops in
connectors and conductors can cause an appreciable percentage change in the voltage delivered to the load. This is
aggravated further with TTL logic, as it draws transient currents many times the steady-state current when it switches.
These problems have created a considerable interest in oncard regulation, that is, to provide local regulation for the
subsystems of the computer. Rough preregulation can be
used, and the power distributed without excessive concem
for line drops. The local regulators then smooth out the voltage variations due to line drops and absorb transients.
A monolithic regulator is now available to. perform this function. It is quite simple to use in that it requires no extemal
components. The integrated circuit has three active leadsinput, output and ground-and can be supplied in standard
transistor power packages. Output currents in excess of 1A
can be obtained. Further, no adjustments are required to set
up the output voltage, and overload protection is provided
that makes it virtually impossible to destroy the regulator.
The simplicity of the regulator, coupled with low-cost fabrication and improved reliability of monolithic circuits, now
makes on-card regulation quite attractive.
design concepts
A useful on-card regulator should include everything within
one package-including the power-contrOl element, or pass
transistor. The author has previously advanced arguments
against including the pass transistor in an integrated circuit
regulator. 1 First, there are no standard multi-lead power
packages. Second, integrated circuits necessarily have a
lower maximum operating temperature because they contain low-level circuitry. This means that an Ie regulator
needs a more massive heat sink. Third, the gross variations
in chip temperature due to dissipation in the pass transistors
worsen load and line regulation. However, for a logic-card
regulator, these arguments can be answered effectively.
For one, if the series pass transistor is put on the chip, the
integrated circuit need only have three terminals. HenCe, an
ordinary transistor power package can be used. The practicality of this approach depends on eliminating the adjustments usually required to set up the output voltage and limiting current for the particular application, as extemal adjustments require extra pins. A new solid-state reference, to be
described later, has sufficiently-tight manufacturing tolerances that output voltages do not always have to be individually trimmed. Further, thermal overload protection can protect an Ie regulator for virtually any set of operating conditions, making current-limit adjustments unnecessary.
Thermal protection limits the maximum junction temperature
and protects the regulator regardless of input voltage, type
of overload or degree of heat Sinking. With an extemal pass
transistor, there is no convenient way to sense junction temperature so it is much more difficult to provide thermal limiting. Thermal protection is, in itself, a very good reason for
putting the pass transistor on the chip.
When a regulator is protected by current limiting alone, it is
necessary to limit the output current to a value substantially
lower than is dictated by dissipation under normal operating
conditions to prevent excessive heating when a fault occurs. Thermal limiting provides virtually absolute protection
for any overload condition. Hence, the maximum output current under normal operating conditions can be increased.
This tends to make up for the fact that an Ie has a lower
maximum junction temperature than discrete transistors.
Additionally, the 5V regulator works with relatively low voltage across the integrated circuit. Because of the low voltage, the intemal circuitry can be operated at comparatively
high currents without causing excessive dissipation. Both
the low voltage and the larger intemal currents permit higher junction temperatures. This can also reduce the heat
sinking required-especially for commercial-temperature'range parts.
Lastly, the variations in chip temperature caused by dissipation in the pass transistor do not cause serious problems for
a logic-card regulator. The tolerance in output voltage is
113
~ r---------------------------------------------------------------------------------~
i
IOQ~e enqugh that it is relatively easy to design an internal
reference that is much more stable than required, even for
templilratUre variations as large as 150·C.
across R2 has a positive temperature coefficient. It will be
shown that the output voltage 'will be temperature compensated when the sum of the two voltages is equal to the
energy-band-gap voltage.
,circuit description
Conditions for temperature compensation can be derived
starting with the equation for the emitter-basa voltage of a
transistor which is2
The internal voltage reference for this logic-card regulator is
probably the most significant departure from standard design techniques. Temperature-compensated zener diodes
are normally used for the reference. However, these have
breakdown voltages between 7V and 9V which puts a lower
limit on the input voltage to the regulator. For low voltage
operation, a different kind of reference is needed.
VSE = V90( 1 -
;J
+ VSEO (
;J
(1)
To
kT log Ie
+nkT
- Ioge -+e-,
q
T
q
leo
The reference in the LM109 does not use a zener diode.
Instead, it is developed from the highly-predictable emitterbase voltage of the transistors. In its simplest form, the reference developed is equal to the energy-band-gap voltage
of the semiconductor material. For silicon, this is 1.205V, so
the reference need not impose minimum input voltage limitations on the regulator. An added advantage of this reterence is that the output voltage is well determined in a production environment so that individual adjustment of the
regulators is frequently unnecessary.
where VgO is the extrapolated energy-band-gap voltage for
the semiconductor material at absolute zero, q is the charge
of an electron, n is a constant which depends qn how the
transistor is made (approximately 1.5 for double-diffused,
NPN transistors), k is Boltzmann's constant, T is absolute
temperature, Ie is collector current and VeEo is the emitterbase voltage at To and leo.
The emitter-base voltage differential between two transistors operated at different current densities is given byS
A simplified version of this reference is shown in Figure 1.
aVeE =
in this circuit, Ql is operated at a relatively high current
Jl
qkT loge J;'
(2)
where J is current density.
Referring to Equation (1), the last two terms are quite small
and are made even smlliler by making Ie vaiy as absolute
temperature. At any rate, they can be ignored for now because they are of the same order as errors caused by nontheoretical behavior of the transistors that must be determined empirically.
R2
6k
Rl
600
If the reference is composed of VeE plus a voltage proportional to aVeE, the output voltage is obtained by adding (1)
in its simplified form to (2):
Vref = VgO (1 -
fo) + (;J +
VeEO
k;
loge~.
(3)
Differentiating with respect to temperature yields
......--_--'--_-GROUND
a Vref =
TL/H/8931-1
aT
Figure 1. The low voltage reference In one of Its simpler
forms.
_
~ + \reEO + !
To
TO
q
loge
:!i.
J2
(4)
For zero temperature drift, this quantity should equal zero,
giving
denSity. The current density of Q2 is about ten times lower,
and the emitter-base voltage differential (aVeE) between
the two devices appears across R3' If the transistors have
high current gains, the voltage across R2 will also be proportional to a VeE. Q3 is a gain stage that will regulate the
output at a voltage equal to its emitter base voltage plus the
drop across R2. The emitter base voltage of Q3 has a negative temperature coefficient while the a VeE cqmponent
(5)
The first term on the right is the initial emitter-base voltage
while the second is the component proportional to emitterbase voltage differential. Hence, if the sum of the two are
equal to the energy-band-gap voltage of the semiconductor,
the reference will be temperature-compensated. .
114
05. so that the /l. Vee component is not affected by changes
in the regular output voltage or the absolute value of components.
The voltage gain for the regulating loop is provided by 0, o.
with 09 buffering its input and 0" its output. The emitter
base voltage of 09 and 0'0 is added to that of 0'2 and O,s
and the drop across Rs to give a temperature-compensated. 5V output. An emitter-base-junction capacitor.
frequency compensates the circuit so that it is stable even
without a bypass capaCitor on the output.
The active collector load for the error amplifier is 017. It is a
multiple-collector lateral PNp4. The output current is essentially equal to the collector current of 02. with current being
supplied to the zener diode controlling the thermal shutdown. 02. by an auxiliary collector. 0, is a collector FET4
that. along with R,. insures starting of the regulator under
worst-case conditions.
The output current of the regulator is limited when the voltage across R14 becomes large enough to turn on 014. This
insures that the output current cannot get high enough to
cause the pass transistor to go into secondary breakdown
or damage the aluminum conductors on the chip. Further.
when the voltage across the pass transistor exceeds 7V.
current through R1S and Os reduces the limiting current.
A simplified schematic for a 5V regulator is given in F/{JIJre 2.
The circuitry produces an output voltage that is approximately four times the basic reference voltage. The emitterbase voltage of Os. 04. 05 and Os provide the negativetemperature-coefficient component of the output voltage.
The voltage dropped across Rs provides the positive-temperature-coefficient component. Os is operated at a considerably higher current density than 07. producing a voltage
drop across R4 that is proportional to the emitter-base voltage differential of the two transistors. Assuming large current gain in the transistors. the voltage drop across Rs will
be proportional to this differential. so a temperature-compensated-output voltage can be obtained.
C,.
r---op------1r-"--INPUT
Tl/H/6931-2
~----op--+----+---+
Figure 2. Schematic showing essential details of the 5V
regulator.
In this circuit. Os is the gain stage providing regulation. Its
effective gain is increased by using a vertical PNP. 09. as a
buffer driving the active collector load represented by the
current source. 09 drives a modified Darlington output stage
(0, and 02) which acts as the series pass element. With
this circuit. the minimum input voltage is not limited by the
voltage needed to supply the reference. Instead. it is determined by the output voltage and the saturation voltage of
the Darlington output stage.
F/{/ure 3 shows a complete schematic of the LM109. 5V
regulator. The /l. Vee component of the output voltage is developed across Rs by the collector current of 07. The emitter-base voltage differential is produced by operating 04
and Os at high current densities while operating Os and ~
at much lower current levels. The extra transistors improve
tolerances by making the emitter-base voltage differential
larger. Rs serves to compensate the transconductance4 of
OUTPUT
1M
B.3Y
L - _......_6-_...._ ......_ _....._ _ _ _ _.. GROUND
TLlH/6931-3
Figure 3. Detailed schematic of the regulator.
115
i
C
again to minimize the chance of secondary breakdown. The
performance of this protection circuitry is illustrated in Figure 4.
10
15
20
25
30
ground' when thereJs.a large capaCitor on the output. Fur-·
ther, if the input voltage tries to reverse, 01 will clamp this
for currents up to 1A.
The internal frequency compensation of the regulator per"
mits it to operate With or Without a bypass capacitor on the
output. However, an output capacitor does improve the transient response and reduce the high frequency output impedance. A plot oHhe output impedance in Figure 5 shows that
it remains low out to 10 kHz even without a capacitor. The
ripple rejection also remains high out to'1 0 kHz, as shown in
Figure 6. The irregularities in this curve aroiJnd 100 Hz are
caused by thermal feedback from the pass tranSistor to the
reference cirCUitry. Although an output capacitor is not required, it is necessary to bypass the input of the regulator
with at least a 0.22 p.F capacitor to prevent oscillations under all conditions.
35
INPUT VOLTAGE (V)
TL/H/6931-4
Figure 4. Current-limiting characterletlca.
Even though the current is limited, excessive dissipation can
cause the chip to overheat. In fact, the' dominant failure
mechanism of solid state regulators is excessive heating of
the semiconductors, particularly the pass transistor. Thermal protection attacks the problem directly by putting a temperature regulator on the IC chip. Normally, this regulator is
biased below its activation threshold; so it does not affect
circuit operation. However, if the chip approaches its maximum operating temperature, for any reason, the tempera-'
ture regulator turns on and reduces internal diSSipation to
prevent any further increase in chip temperature.
The thermal protection circuitry develops its reference voltage with a conventional zener diode, 02. 016 is a buffer that
feeds a voltage divider, delivering about 300 mV to the base
of 015 at 175'C. The emitter-basa voltage, 015, is tlie actual
temperature sensor because, with a constant voltage applied across the junction, the collector current rises rapidly
with increasing temperature.
Although some form of thermal protection can be incorporated in a discrete regulator, IC's have a distinct advantage:
the temperature sensing device detects increasas in junction temperature within milliseconds. Schemes. that sense
case or heat-sink temperature take several seconds, or
longer. With the longer response times, the pass transistor
usually blows out before thermal limiting comes into effect.
Another protective feature of the regulator is the crowbar
clamp on the output. If the output voltage tries to rise for
some reason, 04 will break down and limit the voltage to a
safe value. If this rise is caused by failure of the pass transistor such that the current is not limited, the aluminum conductors on the chip will fuse, disconnecting the load. Although this destroys the regulator, it does protect the load
from damage. The regulator Is also designed so that it Is not
damaged In the event the unregulated input is shorted to
lOll
Ik
10k
F~UENCY
lOOk
1M
(Hz)
TLlH/6931-S
Figure 5. Plot of output Impedance aa a function of frequency.
100
A4
--
-~~
T,.25oC
T,=ISOOC
T,=-~C
~
'" '"
\."1
\.
~.200mA
V'N=IOV
20
AVIN=3V ••,
10
lOll
1 k.
10k
lOOk
1W
FR£QUENCY (Hz)
TLlH/8931-8
Figure 6. Ripple reJection of the regulator.
Figure 7 is a photomicrograph of the regulator Chip. It' can
be seen that the'pass transistors, which must handl~ more
than 1A, occupy most of the chip area..The output transistor
is actually broken Into segments. Uniform current distribution is insured by a:iso breaking the. current limit resistor into
116
segments and using them to equalize the currents. The overall electrical performance of this IC is summarized in Table I.
output voltages. One circuit for dOing this is shown in
Figuf99.
r-;;-~L....-
INPUT
RI
300
1%
OUTPUT
R2
1%
TL/H/6931-9
Figure 9. Using the LM109 as an adjustable-output regulator.
TLlH/6931-7
Figure 7. Photomicrograph of the regulator shows that
high current pass transistor (right) takes more
ares than control circuitry (left).
TABLE I. Typical Characteristics of the
Logic-Card Regulator: T A = 2SOC
Parameter
Conditions
Output Voltage
Typ
5.0V
Output Current
1.5A
Output Resistance
6.0
0.030
Line Regulation
7.0V ~ VIN ~ 35V
Temperature Drift
-55°C
~
TA
~
IL ~2001mA
0.005%1V
125°C 0.02%I"C
Minimum Input Voltage lOUT = 1A
The regulated output voltage is impressed across R" developing a reference current. The quiescent current of the regulator, coming out of the ground terminal, is added to this.
These combined currents produce a voltage drop across R2
which raises the output voltage. Hence, any voltage above
5V can be obtained as long as the voltage across the integrated circuit is kept within ratings.
The LM1 09 was designed so that its quiescent current is not
greatly affected by variations in input voltage, load or temperature. However, it is not completely insensitive, as
shown in Figures 10 and 11, so the changes do affect regulation somewhat. This tendency is minimized by making the
reference current though R, larger than the quiescent current. Even so, it is difficult to get the regulation tighter than a
couple percent.
5.5 I--
6.5V
Output Noise Voltage
10Hz ~ f ~ 100 kHz
Thermal Resistance
Junction to Case
LM109H (TO-5)
LM1 09K (TO-3)
5.0
appllcstlons
Because it was designed for virtually foolproof operation
and because it has a singular purpose, the LM109 does not
require a lot of application information, as do most other
linear circuits. Only one precaution must be observed: it is
necessary to bypass the unregulated supply with a 0.22 p.F
capacitor, as shown in Figuf9 8, to prevent oscillations that
~::;:::
~
40 P.V
15°C/W
3°C/W
TIJ25o~
10-
4.5
5
-
1-
~~oe
TI =1500e
-
15
10
20
25
INPUT VOLTAGE (V)
TL/H/6931-10
Figure 10. Variation of quiescent current with Input volt·
age at various temperatures.
6.0
VIN = 10V
OUTPUT
5.5
5.0
TL/H/6931-8
Figure 8. Fixed 5V regulator.
.. ~ ~
I
......
.... -....;: ",IL =0
IL = lA"
~
~~
'"
can cause erratic operation. This, of course, is only neces-
4.5
-75-50-25 0 25 50 75 100 125 150
sary if the regulator is located on appreciable distance from
the filter capacitors on the output of the de supply.
Although the LM109 is designed as a fixed 5V regulator, it is
also possible to use It as an adjustable regulator for higher
JUNCTION TEMPERATURE (Oe)
TLlH/6931-11
Figure 11. Variation of quiescent current with tempera·
ture for various load currents.
117
..~ r----------------------------------------------------------------------------,
N
The LM109 can alsp be used as a current regulator as is
shown in Figure 12. The regulated output voltage is im,
pressed across Rl, which determines the output current.
The quiescent current is added to the current through Rl,
and this puts a lower limit of about 10 rnA on the available
output current.
INPUT
Rl
L---41-- OUTPUT
TUH/6931-12
Figure 12. Current regulator.
The increased failure resistance brought about by thermal
overload protection make the LM 109 attractive as the pass
transistor in other regulator circuits. A precisipn regulator
that employs the IG thusly is shown in Figure 13. An operational amplifier compares the output voltage with the output
voltage of a reference zener. The op amp controls the
LM109 by driving the ground terminal through an FET.
UU09
R2
6K
.OOS"
Ql
2N4343
Rl
30K
t Sold tantalum
TL/H/6931-13
Figure 13. High stability regulator.
by the reference zener, 01. Noise can be reduced by, insertiI'lg 100 kG, 1 % resistors in series with both inputs of the' op
amp and bypassing the non-inverting input to ground. A
100 pF capacitor should also be Included'between the output and the Inverting input to prevent frequency i[)$tabilily.
Tempenlture drift can be reduced by ildju~ng R4, which
determines the zener current, for minimum drift. For best
performance, remote sensing directly to' the load terminals,
as shown in the. diagram; should be used.
conclusions
The LM109 performs a complete regulation function on a
single silicon chip; requiring no external components. It
makes use of some, unique advantages of monolithic construction to achieve performance advantages lhat cannot
be obtained In discrete-component circuits. Further; the low
cost of thed~vice suggests its use in applications where
single-point regulatiOn could not be justifliid pr$Vi6usly.
Thermal overload protection' sig~ificantlyimprOves:the reliability of an IC regulator. 'It elien protecls the regillator for
unforseen fault conditions that may occur in field operation.
Although this can be accomplished easily in a monOlithic
regulator, it is usually not completely effective in a discrete
or hybrid device.
The internal reference developed for the ,LM109 also advances the state of the art for regulators. Not only does it
provide a low voltage, temperature-compensated reference
for the first time, but also it can be expected to have better
long term stability than conventionalzeners. Noise is il)herently much lower, and it can be manufactured to tighter tolerances.
reference
1. R.J. Widlar, "Designing Positive Voltage Regulators,'~
EEE, Vol. 17, No.6, pp. 90-97, June 1969.
2., J.S. Brugler, "Silicon Transistor Biasing for Linear Collector Currant Temperature Dependence, .. IEEE Joumal of
Solid State Circuits, pp. 57-58, June, 1967.
3. R.J. Widlar: "Some Circuit Design Techniques for Linear
. Integrated Circuits," IEEE Trans. on Circuit TheOry, Vol.
XII, pp. 586-590, December, 1965.
4. R.J. Wldlar, "Design of Monolithic Linear Circuits, .. Handbook of Semiconductor Electronics, Chapter X, pp.
to.1-10.32, L.P. Hunter, ed., McGraw-Hili Inc., ,New
York,1970.
The load and line regulation of this circuit is better than
0.001 %. Noise, drift and long term stability are determined
118
r----------------------------------------------------------------,~
~.
National Semiconductor
Application Note 46
Thomas B. Mills
The Phase Locked Loop IC
as a Communication
System Building Block
INTRODUCTION
The phase locked loop has been found to be a useful element in many types of communication systems. It is used in
two fundamentally different ways: (1) as a demodulator,
where it is used to follow phase or frequency modulation
and (2) to track a carrier or synchronizing signal which may
vary in frequency with time.
When operating as a demodulator, the phase locked loop
may be thought of as a matched filter operating as a coherent detector. When used to track a carrier, it may be thought
of as a narrow-band filter for removing noise from a signal.
Recently, a phase locked loop has been built on a monolithic integrated circuit, incorporating the basic elements necessary for operation: a double balanced phase detector and a
highly linear voltage controlled oscillator, the frequency of
which can be varied with either a resistor or capacitor.
It can be seen that the action of the veo is that of an
integrator in the feedback loop when the phase locked loop
is considered in servo theory.
A better understanding of the operation of the loop may be
obtained by considering that initially, the loop is not in lock,
but that the frequency of the input signal ej and veo eo are
very close in frequency. Under these conditions ed will be a
beat note, the frequency of which is equal to the frequency
difference of eo and ej. This signal is also applied to the
veo input, since it is low enough to pass through the filter.
The instantaneous frequency of the VCO is therefore
changing and at some point in time, if the veo frequency
equals the input frequency, lock will result. At this instant, Elf
will assume a level sufficient to hold the veo frequency in
lock with the input frequency. If the tuning of the VCO is
changed (such as by varying the value of the tuning capacitor) the frequency output of the veo will attempt to change;
however, this will result in an instantaneous change in
phase angle between 8j and eo, resulting in a change in the
dc level of ed which will act to maintain frequency lock: no
average frequency change will result.
Similarly, if el changes frequency, an instantaneous change
will result in a phase change between 8j and eo and hence a
dc level change in ed. This level shift will change the frequency of the veo to maintain lock.
The amount of phase error resulting from a given frequency
shift can be found by knowing the "dc" loop gain of the
system. ConSidering the phase detector to have a transfer
function:
~ = Ko(81 - 82}
and the voltage controlled oscillator to have a transfer function:
(6)
92 = KoElf
or taking the Laplace transform
BASIC PHASE LOCK LOOP OPERATION
1 shows the basic blocks of a phase locked loop.
The input signal ej is a sinusoid of arbitrary frequency, while
the VCO output Signal, eo, is a sinsuoid of the same frequency as the input but of arbitrary phase. If
ej = ~ Ej sin [lIIot + 91(t}]
(1)
eo = ~ Eo cos [lIIot + 92(t}]
(2)
the output of the multiplier (phase detector) is
ed=eleeo
= 2EjEo sin [lIIot + 91 (t}l e cos [lIIot + 9 2(t)]
= EjEo sin [91 (t) - 82(t}] + EjEo sin [2 1II0t + 91 (t) +
82(t}]
(3)
the low pass filter of the loop removes the ac components
of the multiplier output; the dc term is seen to be a function
of the phase angle between the veo and the input signal.
F/{/UfB
82 (s) = KoElf
(7)
s
TLlHf7363-1
the phase of the veo output will be proportional to the integral of the control voltage.
Combining these equations:
FIGURE 1_ BasiC Phase Locked Loop
The output of the VCO is related to its input control voltage
by
82(S} =
KoKd F(s}
81(S} s + KoKo F(s}
81(S} - 92(S} =
81(S}
s
(4)
for Elf = 0, Let 92 = 1119, then
92(t} = I EIf(t} dt
(5)
119
s
+ KoKo F(s}
(8)
(g)
•
..: AlIPllc8tibn of the final value theorem of Lapla!;e transforms
~ ",Ylell:ls .
data.modulati(j)n must be followed. The transfer function of
the filter is simply:
,,
. ,
, .,
, .lim 8 (s) _ 8 () =
t _.. 1
2S
lim
s_ 0 s
S281(S)
+ KoKo F(s)
.!!'=
(10)
c.• '
With a step change in phase of the input a81, the Laplace
transform of the input is
substitution IntO(8)
lim
.
_lim
t - .. 8e (t) - 8-0S
.
0
,I),"
KoKo/'I'1
s2 + S/'I'1 +
'1'1 = Rl
KoKo/'I'1
'.'
, In terjrls.· 6f servo theorY, the damping factOr and natural
frequen¢ies are
. .
(11)
(15)
(16)
/;.Ct)/s2
substitution of this value 8, into. ,(10) results .in
lim
lim
t - .. 8e(t) =8-0 .s
0,,'
Rl
aCt)ac.l'
+ KoKo F(s)
.KoKo F(o)
It.
,(12)
this result shows the resulting phase error is dependent on
the m1l9nitude of the frequency step and the "dc" loop gain
. KoKo, which is also caned .the velocity error coefficient Ky. It
should be noted that the ,dimensions of, KoKo are 1/sec.
This can also be seen by considering Ko = volts/radian,
while Ko =.radians/sec/volt. The prod\lct is
volts
radians/ sec
radian x
volt
(14)
Ct
the loop will eventually trayk oUt ~nychange of input phase,
and there .will be no phase error in thes~(!llIdy stat~soIUtion.
If the input is a step in frequency, of, magnitude aCt), the
change in input phase will be a ramp:
81(S) =
(13)
re~ults in
81(S) =
Sa81
+ KoKoF(sr=;
1,
1,+ SRj.Cl
82(S)
81(S) = a81 which gives 8 e(s) = 81(S) - 82(S)
s.
$(j
VOLTAGE·coilTROLLEO·
T1
OS~IL.LATOR
= RtCt
Tl.fHf7383-2
.1
sec
t
this can be thought of as the "dc", loop .gain. (Note that
additional dc gain between the phase detector and the Volt·
" IIge controlled oscillator will increase the loop gain and
hence reduce the steady state phase error resUlting from a
change in frequency of the input).
.
!II
z
...C
THE LOOP FILTER
In working with phase locked loops, it is necessary to con·
sider not only the "dc" performance deSQrjbed above, but
the "ac" or transient performance which is govemed by the
components of the loop filter placed between the phase
detector and the voltage controlled oscillator. In fact, it is
this loop filter that makes the phaSe looked loop so power.
, ful: only a resistor and capacijor are all that is needed to
produce an arbitrarily narrow bandwidth at any selected
center frequency..
,
The simplest filter is Ii single capacitor, F/{JIJrtJ 2, and is used
for wide bandwith applications, such as where wideb/i!nd
TLfHf7383-3
FIGURE 2. Phase Locked Loop with Simple Filter
From this it can be seen thatlS.rge time constants for R,1 Cl
or high loop gain will reduce the damping factor and hence
decrease stability. Therefore, if a narrow bandwidth is de·
sired, the damping factor )/1111 become very small and insta·
bility will result. It is not POssible to adjust bandwidth, loop
gain, and damping independently with this simple filter.
\' '!
120
With the addition of a damping resistor R2 as shown in Fig3, it is possible to choose bandwidth, damping factor
and loop gain independently; the transfer function of this
filter is
,0"
!s!=1+S7'2
Elf 1 + S7'1 .
the loop transfer function becomes:
'0
Uf6
~
(17)
82(S) =
8 z(s)
+ 1)(7'1 + 7'2>
KOKc! 7'2>/7'1 + KoKo/7'1
KoKo (87'2
(18)
s2 + s(1 +
the loop natural frequency is
_ [KoKo]'f2
fIln- - -
111'4
10-3
..J.r ""
III"
~
'0'
~
,0-'
I....
roo.
....
'0
+ '1"2(".1
TLiH/7363-6
FIGURE 4. Filter Time Constant vs Natural Frequency
(20)
.., fIln 7'2
10',,_
(21)
2
R'
RZ
If
T
CI
VOLTAGE CONTROLLED
OSCILLATOR
'1"2
I'
RAD)
m~
(19)
t =}[7'1 ~KOr2 [ 1 + 7'2 KoKo]
'1"1 = RICI
I'
'1"1
7'1
while the damping factor becomes
..
to'
KoK~~
= R2CI
1....
TLlH/7$3-4
I ....
,0-'
'1"2
TLiHI7363-7
FIGURE 5. Damping Time Conatant vs
Natural Frequency
BODE PLOT
t
... dllOCT
Considering the above discussion, there are really two primary considerations in designing a phase locked loop. The
use to which the loop is to be put will affect the design
criterion of the loop components. The two primary factors to
consider are:
I
I
I
I
,
,
I
...'
:-12
IdBIOCTI
......
DESIGN CONSIDERATIONS
I
BfO~,
1. Loop gain. As pointed out previously, this affects the
phase error between the input signal and the voltage controlled oscillator for a given frequency shift of the input
signal. It also determines the "hold in range" of the loop
providing no components of the loop go into limiting or
saturation. This is because the loop will remain in Ioc:k as
long as the phase difference between the input and the
veo is less than ± 90'. The higher the loop gain, the
further the input can change in frequency before the 90'
phase error is reached. The hold in range is
,
I
TLlHI7363-5
FIGURE 3. Phase Locked Loop with
Damping Resistor. Added
In practice, for a fixed loop gain KoKo, the natural frequency
of the loop may be chosen and will be dependent mainly on
7'1, since 7'2 < 7'1 in most cases. Then, according to (21),
damping may be determined by 7'2 and for all practical purposes, will be an independent adjustment. These equations
are plotted in Figures 4 and 5 and may be used for design
purPOses.
. AfIlH =
± Ko Ko
(22)
(providing saturation or limiting does not occur).
2. Natural Frequency. The bandwidth of the loop is determined by the filter components R" R2 and C" and the
loop gain. Since the loop gain is normally selected by the
criterion in 1. above, the filter components are used to
select the bandwidth. The selection of loop bandwidth
may be govemed by several things: noise bandwidth,
modulation rates if the·loop is to.be used as an FM de-
121
modulator, pull-in time and hold-in range. There are two
conflicting requirements that will !lave an affect on loop
bandwidth:
(a) Loop bandwidth must be as narrow as possible to
minimize output phase jitter due to external noise.
(b) The loop bandwidth should be made as large as possible to minimize, tran$ient error due ,to Signal modulation, output jitter due to internal oscillator (VCO) noise,
and to obtain best tracking and acquisition properties.
These two principles are in direct opposition and, depending
on what it is that the loop is to accomplish, an optimum
solution will lie somewhere between the two extremes.
if the phase locked loop is to be used to demodulate frequency modulation, the design should proceed with the criterion of b above. It is necessary to provide sufficient loop
bandwidth to acccmmodate' the expected modulation~ It
must be remembered that at all times, the loop must remain
in lock, (peak phase error less than 90"), even under extremes of modulation; such as, peaks or step changes in
frequency.
For the case of sinusoidal frequency modulation, the peak
phase error as a function of frequency deviation and damping factor is shown in Figure 6.
1.6
-
1.4
1.2
_Ii
.. a
NOISE PERFORMANCE·
Since one of the main uses of phase locked loops is to
demodulate or track signals in noise, it is helpful to look at
how noise affects the operation of the phase locked loop.
The phase locked loop, as mentioned earlier, may be
thought of as a filter with a fIXed, adjustable bandwidth. We
have sean how to calculate the loop natural frequency Oln
(15), (19), and the damping factor t (16), (20). Without going
through a derivation, the loop noise bandwidth BL may be
shown to be
BL =
J""o 1
H (jOl)
12
df = Oln
2
[t +~]
4,
Hz
...
BL
3.0
i
~
I
~
i
z
0.5
0.5
2.0
1.5
1.0
0.5
LOOP SlGNAL·TO·NOISE RATIO
TL/HI7363-13
FIGURE 11. Unlock Behavior of High-Galn,
Second-order Loop, = 0.707
When designing the loop filter components, enough bandwidth in the loop must be allowed for instantaneous phase
change due to input noise. In the previous section, the filter
was selected on the basis that the peak error due to modulation would be less than 90" (so the loop would not loose
lock). However, if noise is present, the peak phase error will
increase due to the noise. So if the loop is not to lose lock
on these noise peaks the peak allowable error due to modulation must be reduced to something less, on the order of
40· to 50".
t
10'
3.0
V
~a
(23)
I
1.0 1.5 2.0 2.5
DAMPING FACTOR - (
10
'"I
\. -~ """'"
o
20
z
:; 2.0
/
60
I
2.5
1.0
./
1= 100
I
= '/,(( + 1I4tl-
~1.5
200
iI
I
!~
it
9 500
~
for a high gain, second order loop. This equation is plotted
in Figure 10. It should be noted that the dimensions of noise
bandwidth are cycles per second while the dimensions of
Oln are radians per second.
3.5
~
~
LOCKING
Initially, a loop is unlocked and the VCO is running at some
frequency. If a signal is applied to the input, locking mayor
may not occur depending on several things.
If the signal is within the bandwidth of the loop filter, locking
will occur without a beat note being generated or any cycles
being skipped. This frequency is given by
3.5
TUH/7383-12
FIGURE 10. loop-Noise Bandwidth
(For High-Galn, Second-Order Loop)
Noise threshold is a difficult thing to analyze in a phase
locked loop, since we are talking about a statistical quantity.
Noise will show up in the input signal as both amplitude and
phase modulation. It can be shown that near optimum performance of a phase locked loop can be obtained if a limiter
is used ahead of the phase detector, or if the phase detector is allqwed to operate in limiting. With the use of a limiter,
amplitude modulation of the input signal by noise is removed, and the noise appears as phase modulation. As the
input signal to noise ratio decreases, the phase jitter of the
input signal due to noise increases, and the probability of
losing lock due to instantaneous phase excersions will Increase. In practice it is nearly impossible to acquire lock if
the signal to noise ratio in the loop (SNRlL = 0 dB. In ganeral, (SNRlL of + 6 dB is needed for acquisition. If modulation or transient phase error is present, a higher signal to
noise ratio is needed to acquire and hold lock.
A computer simulation performed by Sanneman and Rowbotham has shown the probability of skipping cycles for various loop signal to noise ratios for high gain, second order
loops. Their data is shown in Figure 11.
(24)
If the frequency of the input signal is further away from the
veo frequency, locking may still occur, with a beat note
being generated. The greatest frequency that can be pulled
in is called the "pull in frequency" and is found from the
approximation
.1Olp :::::
J2 ( 2 COlnKoKo -
2)1/2
Oln
(25)
which works well for moderate and high gain loops
(Oln/KoKo < 0.4).
An approximate expression for pull in time (the time required
to achieve lock from some frequency offset .1Ol) is given by:
T _ (.10l)2
P - :-::--9'
2C ClIn
A MONOLITHIC PHASE LOCKED LOOP
A complete phase locked loop has bean built on a monolithic integrated circuit. It features a very linear voltage controlled oscillator and a double balanced phase detector.
123
A simplified schematic of this voltage controlled oscillator is
is a voltage controlled current
shown in FIgUre 12.
source whose collector current is a linear function of the
control voltage ef.lnitially Qs is OFF and the collector current of Q2 passes through 02 and changes C in a linear
fashion. The voltage across C Is therefore a ramp. and continues to increase until 07 is turned ON; this turns OFF Qa.
causing Q9 and Q11 to tum ON. This in furn turns ON Qs.
With Qs ON. the anode of Dt is clamped close to - Vee and
02 stops conducting. since its cathode is more positive than
its anode.
All of the current supplied by Q2 is diverted through Oland
Q3. which sets up an equal current in Q4' This current is
suppliE!d by the charged capaCitor C (which now cjischarges
linearly). causing the voltage. acroSs It to decrease. This
cOntinues untU a lower .trip point is reached .and 07 .turns
OFF and the Cycle repeats. Due to the matchinll Of Q3 and
Q4. the charge current of C is equal to the disch~e current
and therefore the duty cycle is very nearly 50%. FlIlure 13
shows the wave forms at (1) and (2).
.
Q2
FlIlure 14 shows the double balanced phase detectorl;lnd
amplifier used in the microcircuit. Transistors Q1 through ~
are. switched with the output of the
while the input
veo.
+Vcc
SQUARE WAVE
OUTPUT
I,
TLlH/7361!-14
FIGURE 12. Simplified Voltage Controlled OSCillator
CAPACITOR
CAPACITOII
CHARGING -4.----*--'*-OISCHARGING
n/ Ctlm = 1, Ctlri = 2'IT X 220 Hz;
selecting a damping facter ef 0.707,
.. 8
.-----/
. = 0.702
. ",Ctl Ctln
er
b.Ctl
.
2 'IT X 1088Hz
.
8 e = 0.702 Ctln = 0.702 2 'IT x .220 Hz = 3.45 radians
BLOOP
BINPUT
b.Ctl
= 0.44 -Ctln- = 0.44 x
2 'IT
2
x 1088
'IT X
500
= 0:95 radians
.
lOOK r---------~------_,
this sheuld be a good choice, since it is clese to. 1 radian.
Operating at 14.5 kHz, the LM565 has a leep gain KoKo ef
10K
2.28 x 14.5 x 103 = 33 x 103 sec
lK
ttte value ef the leep filter capacitor, C1, can be feund from
F1!JUre 4:
, . .
'71
+ '72 =
3.5
X
100
10-3 sec
10
frem F1!JUre 5, the value ef '72 can be feund (fer a damping
factor ef 0.707)
.
'71
4.4 X 10- 4 sec
= (35 - 4.4) x 10-4 sec
C
-!1- 31.4 X
R
= 4.4 x 10-4 sec = 440
...
'72 =
.1-
2
R -
10
= 31.4 x 10- 4 sec
{}
= 0.6 Ctln = 0.6 x 3150 rad/sec
= 1890 Hz
t
'10K
lOOK
FSK DEMODULATOR
Frequency shift· k~ying (FSK) is widely used fer the vansmissien ef Teletype infermatien, both in the computer peripheral and communicatiens field. Standards have evolved
over the years, and the commenly usedfrequenCie$ are as
fellews:
a)
mark
2125
Hz
space 2975
Hz
b)
mark
1070
Hz
space 1270
Hz
c)
Hz
mark
2025
spece 2225
Hz
(a) is cemmenly used as subcarrier tones fer radio. Teletype,
while b) and c) are used as carriers fer data transmissien
ever telephene and .land lines.
As a deSign example, a demodulator fer the 2025 Hz and
2225 Hz mark and..space frequencies will be discussed.
Since this is an FM system employing square wave modulation, the natural frequency ef the loop must be cho.sen again
so. that peak phase errors do· not exceed 90" under all cenditiens. Ftgure 7 shol(llS peak phase error fer a step in frequency; if a damping factor ef 0.707 is selected, the peak
phase errer is
the complete circuit is shown in Figure 17. Measured perfermance ef the circuit is summarized belew with a fully
modulated Signal as described abeve and an input level ef
40 mVrms:
f3dB
lK
TLlH/7363-20
Leeking at Figure 10, the neise bandwidth BL can be estimated to. be
BL
!OO
-
FIGURE 18. Bode Plot for Circuit of FIgure 17
10- 4 sec '"
F
3.6k{}
-1,...
lXl0 S,...F
100 kHz
,the equivalent signal to. neise in the loop is ":8.4 dB' + 17
dB = + 8.6 dB which is clese to the above~meiltiened limit
of + 6 dB. It sheuld also be neted that io.ss of look was
neted with full medulatien of the sigl1al which' will degrade
thresheld semewhat (altheugh the m~rement is mere realistiC). .
.
.
this is unacceptable, since it weuld threw the loop eut ef
leck, so. it is necessary to. try a higher value, ef Ctln. Let Ctln =
2'ITx 500 Hz, then Ctlm/ Ctln = 0.44, and
.
8e
= 1890 Hz = 0.02 or -17 dB
200
0.8
770mVrms
0.4%
Output Level
Distertien
Signal to. Neise at verge ef less ef leck
(bandwidth ef neise = 100kHz)
-8.4 dB
It will be neted that the loop is capable ef demodulating
signals lewer in level than the neise; this is net in disagreement with earlier statements that less of leck eccurs at signal to neise raties ef appreximately + 6 dB because of the
bandwidths invelved. The abeve number ef -8.4 dB signal
to. neise fer thresheld was ebtained with a neise spectrum
8e
",Ctl Ctln
.-----/ = 0.45
128
.
+lZV
15K
15K
lOl'-FT
ZK
ZOK
UK
100
OUTPUT TO
PRINTER
MAGNET
ORIVER
10K
5,.,F
TUHI7363-21
FIGURE 19. FSK Demodulator (2025-2225 cps)
+Z4V
IZI
..,...50,.,F
15K
15K
..J..
15V
ZOOK
ZK
DUTPUTTD
PRINTER
MAGNET
DRIVER
Tl/HI7363-22
FIGURE 20. FSK Demodulator with DC Restoration
129
..,
CD
z
cc
INPUT FROM
TAPE RECORDER
00-4t---""-I
1---.
VIDEO
INFORMATION
HORIZONTAL
....- - - - - - -. . SYNC
TLlHI7363-23
FIGURE 21. Block Diagram of Weather satellite Demodulator
or
ative and switching occurs, the detected and filtered voltage
of pin 3 to the comparator will not follow the change. This is
a form of "dc restorer" circuit: it will track changes in drift,
making the comparator self compensating for changes in
frequency" etc.
ACJ)
8 e = 0.45,
CJ)n
ACJ)
CJ)n = 0.458;
WEATHER SATELLITE PICTURE DEMODULATOR
21T X 200 Hz = 1250, if 8 e = 1 radian,
1250 rad/ sec,
,
CJ)r1 = 0.45
1 radian
= 500 rad/sec
in our case, ACJ)
=
As a last example of how a phase locked loop can be used
in communications systems, a weather satellite picture demodulator is shown. Weather satellites of the Nimbus,
ESSA, and ITOS series continually photograph the earth
from orbits of 100 to 800 miles. The pictures are stored
immediately after exposure in an electrostatic storage vidicon, and read out during a succeeding 200 secOnd pariod.
The video information is AM modulated on a 2.4 kHz subcarrier which is frequency modulated on a 137.5 MHz RF
carrier. Upon re~ption, the output from the receiver FM
detector will be the 2.4 kHz tone cqntainlng AM video information. It is common practice to record the tone on an audio
quality tape recorder for subsequent demodulation and display. The 2.4 kHz subcarrier frequency maybe divided by
600 to obtain the horizontal sync frequency of 4 Hz.
fn = 80Hz
The final circuit is shown In Figure 19. The values of the
loop filter components (Cl = 2.2 ",F and Rl = 7000) were
changed to accommodate a keying rate of 300 baud
(150 Hz), since the values calculated above caused too
much roll off of a square wave modulation signal of 150 Hz.
The two 10k resistors and 0.02 /LF capacitors at the input to
the LM111 comparator provide further filtering of the carrier,
and hence smoother operation of the circuit.
A problem encountered with this Simple demodulator is that
of dc drift. The frequency must be adjusted ,to provide zero
volts to the input of the comparator so that with modulation,
switching occurs. Since the deviation of the signal is small
(approximately 10%), the peak to peak demodulated output
is only 150 mV. It should be apparent that any drift in freQuency of the veo will cause a dc change and hence may
lock the comparator in one state or the other. A circuit to
overcome this problem is shown in Figure 20. While using
the same basic demodulator configuration, an LM111 is
used as an accurate peak detector to provide a dc bias for
one input to the comparator. When a "space" frequency is
transmitted, and the output at pin 7 of the LM565 goes neg-
Due to flutter in the tape recorder, noise dunng reception,
etc., it is desirable to reproduce the 2.4 kHz subcarrier with
a phase locked loop, which will track any flutter and instability in the recorder, and effectively filter out noise, in addition
to providing a Signal large enough for the digital frequency
divider. In addition, an in phase component of the VCO signal may be used to drive a synchronous demodulator to
detect the video information. A block diagram of the system
is shown in Figure 21, and a complete schematic in FIgure
22.
130
+15V
41,.F
10K
l'
UK
+I5V
5,.F
22M
o--w
0.1
18K
18K
N:.,;
+IOV
22M
~
31.
/'
1.25
~
33K
.004
25K Si4
0
f
OVERTICAL
SWEEP
OJ;
VIDEO
OUTPUT
UK
1,.F
;t
61K
LMI596
UK
UK
4
4.1K
TO
"ORIZ
SYNC
O.I,.F
TUH/7383-24
FIGURE 22. Weather Satellite Picture Demodulator
9t-NY
The design of the loop parameters was based on the following objectives
fn = 10 Hz, (lin = 75 rad/sec
BL = 40 Hz (from FigUfB 10)
the complete loop filter, calculated from FigUfBS 4 and 5, is
shown in RgUfB 22. When the loop is in lock and the free
running frequency of the VCO is 2.4 kHz, the VCO square
wave at pin 4 of the 565 will be in quadrature (90") with the
input signal; however, the zero crossings of the triangle
wave across the timing capacitor will be in phase, and if
their signal is applied to a double balanced demodulator,
such as an LM1596, switching will occur in the demodulator
in phase with the 2.4 kHz subcarrier. The double balanced
demodulator will produce an output proportional to the amplitude of the subcarrier applied to its signal input. An emitter follower, Q1, is used to buffer the triangle wave across
the timing capacitor so excessive loading does not occur.
The demodulated video signal from the LM1596 is taken
across a 25k potantiometer and filtered to a bandwid1h of
1.4 kHz, the bandwidth of the transmittad video. Depending
on the type of display to be used (oscilloscope, slow scan
TV monitor, facsimile reproducer), it may be necessary to
further buffer or amplify the signal obtained. If desired, another load resistor may be used between pin 6 and VCO to
obtain a differential output; an operational amp could then
be used to provide more gain, level shift, etc.
A vertical sweep circuit is shown using an LM308 low input
current op amp as a Miller rundown circuit The values are
chosen to produce an output voltage ramp of -4.5V/220
sec, although this may be adjusted by means of the 22 meg.
charging resistor. If an oscilloscope is used as a readout,
the horizontal sync can be supplied to the trigger input with
the sweep set to provide a total sweep time of something
less than 250 ms. A camera is used to photograph the 200
second picture.
SUMMARY AND CONCLUSIONS
A brief review of phase lock techniques has been presented
and several design tools have been presented that may be
useful in predicting the performance of phase locked loops.
A phase locked loop integrated circuit has been described
and several applications have been given to illustrate the
use of the circuit and the design techniques presented.
REFERENCES
1. Floyd M. Gardner, "Phaselock Techniques", John loW/ey
and Sons, 1966.
2. Elliot L. Greenberg, "Handbook of Telemetry and Remote
ContrOl", McGraw-Hili; 1967.
3. Andrew Viterbi, "Principles of Coherent Communication",
Mr:G~w-Hill,
132
1966.
,----------------------------------------------------------------,
Applications for a New
Ultra-High Speed Buffer
INTRODUCTION
Voltage followers have gained in popularity in applications
such as semple and hold circuits, general purpose buffers,
and active filters since the introduction of IC operational amplifiers. Since they were not specifically designed as followers, these early IC's had limited usage due to low bandwidth, low slew rate and high input current. Usage of voltage
followers was expanded in 1967 with the introduction of the
LM102, the first IC designed specifically as a voltage follower. With the LM102, engineers were able to obtain an order
of magnitude improvement in performance and extend usage into medium speed applications. The LM110, an improved LM102, was introduced in late 1969. However, even
higher speeds and lower input currents were needed for
very fast sample and holds, A to D and D to A converters,
coax cable drivers, and other video applications.
The solution to this application problem was attained by
combining technologies into a single package. The result,
the LH0033 high speed buffer, utilizes JFET and bipolar
technology to produce a ultra-fast voltage follower and buffer whose propagation delay closely approaches speed-oflight delay across its package, while not compromising input
impedance or drive characteristics. Table I compares various voltage followers and illustrates the superiority of the
LH0033 in both low input current or high speed video applications.
".
~
OUTPUT
4
vTL/K17318-1
FIGURE 1. Simple Voltage Follower Schematic
zero volts for zero volts in. 03 and 04 eliminate loading the
input stage (except for base current) and CRl and CR2 establish the output stage collector current.
If 01 and 02 are matched, the resulting drift is reduced to a
few p.VI"C.
PERFORMANCE OF THE LHOO33 FAST VOLTAGE
FOLLOWER/BUFFER
The major electrical characteristics of the LH0033 are summarized in Table II. All the virtues of a ultra-high speed buffer have been incorporated.
Flgurs 3 is a plot of input bias current vs temperature and
shows the typical FET input characteristics. Other typical
performance curves are illustrated in Figures 4 through 10.
Of particular interest is Figurs 8, which demonstrates the
performance of the LHOO33 in video applications to over
100 MHz.
CIRCUIT CONSIDERATIONS
The junction FET makes a nearly ideal input device for a
voltage follower, reducing Input bias current to the picoamp
range. However, FET's exhibit moderate voltage offsets and
offset drifts which tend to be difficult to compensete. The
simple voltage follower of Flgurs 1 eliminates initial offset
and offset drift if 01 and 02 are identically matched transistors. Since the gate to source voltage of 02 equals zero
volts, then 01'S gate to source voltage equals zero volts.
Furthermore as VPl changes with temperature (approximately 2.2 mVl·C), VP2 will change by a corresponding
amount. However, as load current is drawn from the output,
01 and ~ will drift at different rates, A circuit which overcomes offset voltage drift is used in a new high speed buffer
amplifier, the LHOO33. Initial offset is typically 5 mV and
offset drift Is 20 p.v /·C. Resistor R2 is used to establish the
drain current of current source transistor, 02 at 10 mA.
The same drain current flows through 01 causing a voltage
at the source of approximately 1.tV. The 10 mA flowing
through Rl plus Oa's VeE of 0.6V causes the output to sit at
APPLICATIONS FOR ULTRA-FAST FOLLOWERS
The LHOO33's high input impedance (1011 0, shunted by
2 pF) and high slew rate assure minimal loading and high
fidelity in following high speed pulses and signals. As
shown below, the LH0033 is used as a buffer between MOS
logic and a high speed dual limit comparator. The device's
high input impedance prevents loading of the MOS logic
signal (even a conventional scope probe will distort high
output impedance MOS). The LH0033 adds about a 1.5 ns
to the total delay of the comparator. Adjustment of voltage
divider Rl, R2 allows interface to TIL, DTL and other high
speed logic forms.
TABLE I. COMPARISON OF VOLTAGE FOLLOWERS
Parameter
Conventional
Monolithic Op Amp
LM741
First Generation
Voltage Follower
LM102
Second Generation
Voltage Follower
LM110
Specially Designed
Voltage Follower
LHOO33
Input Bias Current
Slew Rate
Bandwidth
Prop. Delay Time
Output Current Capability
200nA
0.5 Vlp.s
1.0 MHz
350ns
±5mA
3.0nA
10V/p.s
10 MHz
35ns
±2mA
1.0nA
30V/p.s
20 MHz
18 ns
±2mA
0.05nA
1500V/p.s
100 MHz
1.2 ns
±100mA
133
~
rJ'
National Semiconductor
Application Note 48
5
INPUT
0-+11-1
Nt
Ne
10
v- .
L _ _ .''';' ...1
,
"..,
TLfKf7318-2
"
TopVlew
FIGURE 2. LHOO33 Schematic
,
.... ,
TABLE II
Parameter.
Conditions
Value
OutputOffsetVoltage Rs = 100kO
5 mY.
Input Bias Current
50 pA
Input Impedance
1011 0
VIN == 1.0Vrms
RL = lk, f = 1 kHz
0.98
Voltage Gain
VIN = 1.0 Vrrns
Rl = lk,f = 1 kHz,Rs = lOOk
Ol>ltput Voltage Swing Vs = ±15V, Rs = lOOk
±13V
RL = 'lk
Parameter·
Conditions,'
Output CUrrent Capability
SleW Rate
Rs=500, RL
Propagation Delay
Bandwidth
134
",oJ';
=;; 1~
VIN =1.0 Vrrns
Rs= 500, RL =1 k
. Value
±. ~OO. rnA peak
1~OOVIp's
1..2 ns
100 MHz
,.
.
...
v.-taW
L/l.L"
.... ,
V. -:11.
.....
.,
I'-
V.· ...V=
.III
L
~
•
II
L
J
•...
'II
FIGURE 3. Input Bias
Current vs Temperature
RL-ua
TA "lII"e
•
II
'II
_RATUREl'e,
V. -t,IV
'I ~
II
i
..
!
;
_T - - - 0
F=OUlfUT
TA *+UOC
..
II
•
..
II
TIME i0oi
:=
;!
II
j ..
J ..
'7
l..A
II
II
V
/ h
/. V
~
''\
I
I
1\'TA "II'C
1.-·,..C
~
•
I
i
.'T.....·e
'D
,.
... v..... c-v,
r ,.ZD
'I
U
FIGURE 9. Supply Current
vs Supply Voltage
ai
:
ill
./
I ..
U
'UZI.I
11'11
FIGURE 8. Frequency
Response
V.-tl.Y
110 • lID
U
u
Z.I
-- - .
R•• ,~
f-'" -;;
II
'II
_RATUREI'C'
FIGURE 10. Rise and Fall
Time vs Temperature
135
;
.. l1!
A
U
•...
•
II
FREauEIIC' .....'
1
lj
30
A'f-)
1.1
./ ~
./~
31
R. ·IIIJ
v. -,.IV,..
=U
FIGURE 7. Positive Pulse
Response
I'
.
V. -t'lV
1Io'1ID
i ,..
! ...
..
'I
FIGURE 5. Output Voltage vs
Supply Voltage
TIME c.I
FIGURE 6. Negative
Pulse Response
i
•
L
..
II
/
'/
sum' VOLTAGE ,tV,
I
II
Y """
"
'II
~=~:'~T-
II
/
~
TA *+ZS·I:
-
- , • url,R. ·IIIJ
I
'4
'I
I
FIGURE 4. Output Offset
Voltage vs Temperature
-
v•• illY
~ .... IIIJ
~
~
....... "'"
J
..
II
'II
_RATUREre,
i
......
1v....1V
1.,.00'1
~
... r-r- ...·,.In
R."'.ri
'II
TLlK/7318-3
':?
V'
,
<,
",.~
,
.,
Rl
BOOO
TOMOS
11454112
R2
,2000
Y-
Y•••• , '
YTLlK17318-4
FIGURE 11. High Speed Dual LImit Comperator for MOS Logic
close to the device under test and drives the cable shield
thus allowing higher speed operation since the deVice under
test does not have to chaige the cable.
The LH0033 was designed to drive long cables, shie,lded
cables, coaxial cables and other generally stringent line
driving requirements. It will typically drive 200 pF with, ,no,
degradation in slew rate and several thousand pF at a reduced rate. In order to prevent oscillations with large capacitive loads, provision, has been made to insert damping resistors between V+ and pin I, and V- and pin 9. Values
between 47 and 1000 workwell'for CL > 1000 pF. For nonreactive loads, pin 12 should be shorted to pin 1 and pin 10
shorted to pin 9. A coaxial driver is shown in F/{/ure 13. Pin 6
is shorted to pin 7, obtaining an initial offset of 5.0 mV, and
the 430 coupled with the LH0033's output impedance
(about 60) match the coaxial cable's characteristic impedance. Cl is adjusted as a function of cable length to optimize rise and fall time. Rise time for the circuit as shown in
Figure 12, is IOns.
n
.,
HORZ: 1On~1DIV
VERTj2V/f
TL/Kl7318-5
FIGURE 12. LHOO33 Pulse Response Into
10 Foot Open Ended epaxial cable
Another application that utilizes the low input current, high
speed and high capacitance drive capabilities of the
LH0033 is a shield or line driver for high speed automatic
test equipment. In this example, the LH0033 .is mounted
+15Y
'CI
91 pF
O.I,.F
~
INPUT
11 FT. OF RG -59
430
YERT: ZV/em
"aRIZ: 10 ""em
-15V
TLIKI7318-6
FIGURE 13
136
INPUT - -•
Offset null is accomplished by connecting a 1000 pot between pin 7 and Y-. It is generally a good idea to insert 200
in series with the pot to prevent excessive power dissipation
in the LH0033 when the pot is shorted out. In non-critical or
AC coupled applications, pin 6 should be shorted to pin 7.
The resulting output offset is typically 5 mY at 25°C.
The high output current capability and slew rate of the
LHOO33 are utilized in the sample and hold circuit of Figure
16. Amplifier, A1 is used to buffer high speed analog signals. With the configuration shown, acquisition time is limited by the time constant 'Of the switch "ON" resistance and
'sampling capacitor, and is typically 200 or 300 ns.
.-;~
A2'S low input bias current, results in drifts in hold mode of
v-
50 mY at 25°C
and
~ at 1250C.
sec
sec
The LH0033 may be utilized in AC applications such as video amplifiers and active filters. The circuit of Figure 17 utilizes boot strapping to achieve input impedances in excess
of 10 MO.
'
TL/K17318-7
FIGURE 14. Instrumentation Shield/Line Driver
The LHOO33's high input impedance and low input bias current may be utilized in medium speed circuits such as Sam~
pie and Hold, and 0 to A converters. Figure 15 shows an
LHOO33 used as a buffer in medium speed 0 to A converter.
R
R
R
2R
1000 ~IoJ\N~.
-t5V
TL/K/7318-8
FIGURE 15
137
.....
~~-----------------------------------------------------------,
'
.y.+
v+
z
c(
ANALOG
INPUT
OUI1'UT
2011
V-
V-
uv
r
~
I
I
I
LOGIC
INPUT
Z
L
'Polycarbonate at Teflon
-- 1.J
~
112111t01134
V-
TLlK/7318-9
FIGURE 16. High Speed Sample and Hold
V·
Vee =lZ.DV
.001 "F
INPUT
~ I -....~-t
1M
1M
.1I11.F
I"'UT
~ ....-4....-=-1
~-_OUTPUT
0.1 "F
1M
1M
fH",100MHz
TLlKl7318-10
TL/Kl7318-11
FIGURE 17. High Input Impedance
AC Coupled Amplifier
FIGURE 18. Single Supply AC Amplifier
typical application might be an interface to an MOS shift
register where V+ = 5.0V and V- = -25V. In this case,
an apparent output offset occurs. In reality, the output voltage is due to the LH0033's voltage gain of less than unity.
A single supply, AC coupled amplifier is shown in Figure 18.
Input impedance is approximately 50Ck and output swing is
in excess of 8V peak-to-peak with a 12V supply.
The LH0033 may be readily used in applications where symmetrical supplies are unavailable or may not be desirable. A
138
The :outt:;ut"VOI~ge shift due to asymmEltrical supplies may
be prEldiCt(ild by:'
, .',
(V+ - V-)
, a~o'~ (1 -~v)
2
= .005 (V+ - V-)
Output currents in excess of 100 mA may be obtained. InclUSion of 1500. resistors between pins 1 and 12, and 9 and
10 provide short circuit protection, while decoupling pins 1
and 9 with 1000 pF capacitors allow near full output swing.
where: Av = No load voltage gain, typically 0.99.
V+ = Positive Supply Voltage.
V- = Negative Supply Voltage.
The value for the short circuit current is given by:
V+
VIsc"'--=-RliMIT
RliMIT
where: Isc s; 100 mAo
For the foregoing application, avo would be -100 mV. This
apparent' "offset" may be adjustEld to zero as outlined
above.
SUMMARY
The advantages of a FET input buffer have been demonstrated. The LH0033 combined very high input impedance,
wide bandwidth, very high slew rate, high output capability,
and design flexibility, making it an ideal buffer for applications ranging from DC to in excess of 100 MHz.
Figure 19 shows a high Q, notch filter which takes advantage. of the LH0033's wide bandwidth. For the values
shown, the center frequencY is 4,5 MHz.
The LH0033 can also be usEld in conjunction with an operational amplifier as current booster as shown in Figure 20.
fo ~
Rl
2200
Rl
2200
1
2rli1C1
AI
~
Cl
~~
2 A2
2
vTL/K/7318-12
FIGURE 19. 4.5 MHz Notch FIlter
RF
+15V
. INPUT o-.J\I'\I\"'~
OUTPUT
lOUT> 100 mA
-
Isc ~
-15V
±15
"i5oii =
100 rnA
TL/K/7318-1S
FIGURE 20. Using LH0033 a8 an Output Buffer
139
,
:i
National Semiconductor
Application Note 49
PIN Diode Drivers
... ,"
INTRODUCTION
The DHOO35/DH0035C is a TTLlDTL compatible, DC coupled, high speed PIN diode driver. It is capable of delivering
peak currents in excess of one' ampere at speeds up to
10 MHz. This article demonstrates how the DH0035 may be
applied to driving PIN diodes and comparable loads which
require high peak currents at high repetition rates. The salient characteristics of the deVice are summarized in Table I.
TABLE I. DHOO35 Characteristics
Parameter
Conditions
Differential Supply
Voltage (V+ - V-)
Value
The charge cOntrol model of ~ diode1,2 leiads to the charge
continuity equation given in equation (1)~
i=dO+9
(1)
dt
7'
where: 0 = charge due excess minority carriers
T = mean lifetime of the minority carriers
Equation (1) implies a circuit model shown in FIgure 2. Under steady conditions :
= 0, hence:
o
30YMax.
Icc = -;: or 0 = ICC. 'I'
Output Current
1000mA
Maximum Power
1.5W
fc!elay
PRF = 5.0 MHz
10 ns
tnse
V+ - Y- = 20Y
10%t090%'
15ns
Y+ - Y- = 20Y
90% to 10%
10ns'
PIN DIODE SWITCHING REQUIREMENTS
Figure 1 shows a simplified schematic of a PIN diode switch.
Typically, the PIN diode is used in RF through microwave
frequency modulators and switches. Since the diode is in
shunt with the RF path, the RF signal is attenuated when
the diode is forward biased ("ON"), and is passed unattenuated when the diode is reversed biased ("OFP'). There are
essentially two considerations of interest in the "ON" condition. First, the amount of "ON" control current must be sufficient such that RF signal current will not significantly modu~
late the "ON" impedance of the diode. Secondly, the time
required to achieve the "ON" condition must be minimized.
(2)
where: I = steady state "ON" current.
ANODE
.
, G •
1
+
I'""'"
I = Total Current
loe = SS Control Current
IRF = RF SIgnal Current
T
TLlH/8750-2
FIGURE 2. Circuit Model for PIN Switch
The conductance is proportional to the current, I; hence, in
order to minimize modulation due to the RF Signal, ICC
iRF' Typical values for IDe range from 50 rnA to 200 mA
depending on PIN diode type, and the amount of modulation
that can be tolerat~d.
The time response of the excess charge, 0, may be evaluated by taking the Laplace transform of equation (1) and
solving for 0:
>
RfIN~
O(s) =
'-Ii'"
,
1
7'1(8)
+ S'l'
(3)
SQlving equation (3) fot O(t) yields:
O(t) = L -1 [O(s)) = 1'1' (1 - etlry
(4)
The time response of 0 is shown in FIfJIH8 3s. As can be
seen, several carrier lifetimes are required to achieve the
steady state "ON" condition (0 = ICC. '1').
Tl/H/8750-1
FIGURE 1. Simplified PIN Diode Switch
140
The turn off requirements for the PIN diode are quite similar
to the turn on, except that in the "OFF" condition, the
steady current drops to the diode's reverse leakage current.
The time response of the charge, hence the time for the
diode to achieve the "ON" state could be shortened by applying a current spike, Ipk, to the diode and then dropping
the current to the steady state value, loc, as shown in Figure 3b. The optimum response would be dictated by:
(Ipk) (t) = T. loe
(5)
A charge, loc • T, was stored in the diode in the "ON"
condition and in order to achieve the "OFF" state this
charge must be removed. Again, in order to remove the
charge rapidly, a large peak current (in the opposite direction) must be applied to the PIN diode:
o
-Ipk:> -
(6)
T
It is interesting to note an implication of equation (5). If the
peak turn on current were maintained for a period of time,
say equal to T, then the diode would acquire an excess
charge equal to Ipk • T. This same charge must be removed
at turn off, instead of a charge loe • T, resulting in a considerably slower turn off. Accordingly, control of the width of
turn on current peak is critical in achieving rapid turn off.
IDC
APPLICATION OF THE DH0035 AS A PIN DIODE DRIVER
I
Q
The DHOO35 is specifically designed to provide both the
current levels and timing intervals required to optimally drive
PIN diode switches. Its schematic is shown in Figure 4. The
device utilizes a complementary TTL input buffer such as
the DM7830/DM8830 or DM5440/DM7440 for its input signals.
I
I
------------
I
Two configurations of PIN diode switch are possible: cathode grounded and anode grounded. The design procedures
for the two configurations will be considered separately.
I
I
ANODE GROUND DESIGN
Selection of power supply voltages is the first consideration .
Table I reveals that the DH0035 can withstand a total of
30V differentially. The supply voltage may be divided symmetrically at ± 15V, for example. Or asymmetrically at
+ 20V and -10V. The PIN diode driver shown in Figure 5,
uses ± 10V supplies.
.. 6~
TUH/8750-3
FIGURE3a
When the 0 output of the DM8830 goes high a transient
current of approximately 50 mA is applied to the emitter of
01 and in turn to the base of Os.
Os has an hIe = 20, and the collector current is hIe X 50 or
1000 mA. This peak current, for the most part, is delivered
to the PIN diode turning it "ON" (RF is "OFF").
IDC -
Ipk flows until C2 is nearly charged. This time is given by:
C2tN
t=-Ipk
Q
I
I
__IL_.,-____
(7)
where: I:N = the change in voltage across C2.
Prior to as's turn on, C2 was charged to the minus supply
voltage of -10V. C2'S voltage will rise to within two diode
drops plus a Vsat of ground:
V = Iv-I- Vf(PIN Diode) - VfCR1 - VSaIQs
forV- = -10V, aV = 8V.
I
(8)
Once C2 is charged, the current will drop to the steady state
value, loe, which is given by:
V . V+
Vee
loe=----(9)
RM
R3
R1
where: Vee = 5.0V
I
I
R1 = 2500
R3 = 5000
TL/H/8760-4
FIGURE3b
. R (R3 (ay) (R1)
.. M - R1V+ + loCR3R1 + VCCR3
141
(9a)
y+
R3
IiOOfi
HI
OUTPUT
250n
01
Q&
12
InA
CRZ
4
R2
3kl'l
In8
TLlH;8750-5
FIGURE 4. DHOO35 Schematic Diagram
V'
i.OV
r---
11
!-._- .,
I
I
I
I
10
I
I
L-
~
,
r;;;;- ...,
Iii
o-~-L..-I
,
ch
250pF
I"
I
I
IN
I
II DIODE
I I SWITCH
>C)--:',..;;.---.....-----!-,-i
.
.112 DM8830
--1--~
I
...J
20pF
~
41
I
I
I'---...J
DH0035
-1--~~
-IOV =V'
TLlH/8750-8
FIGURE 5. cathode Grounded De.lgn
142
For the driver of Figure 5, and IDe = 100 mA, RM is 560
(nearest standard value).
Returning to equation (7) and combining it with equation (5)
we obtain:
t
= TIDe = C2V
Ipk
Ipk
Solving equation (10) for C2 gives:
to Os. 03 absorbs the stored base charge of Os facilitating
its rapid turn-off. As Os's collector begins to rise, 04 turns
"ON". At this instant, the PIN diode is still in conduction and
the emitter of 04 is held at approximately -0.7V. The instantaneous current available to clear stored charge out of
the PIN diode is:
(10)
C2 = loeT
(11)
V
ForT = 10ns,C2 = 120pF.
One last consideration should be made with the diode in the
"ON" state. The power dissipated by the DH0035 is limited
to 1.5W (see Table I). The DH0035 dissipates the maximum
power with Os "ON". With Os "OFF", negligible power is
dissipated by the device. Power dissipation is given by:
P diss .. [IDe (Iv-I
-
hfe
(hje
'"
(12)
("ON" time)
("ON" time + "OFF" time)
Pmax = 1.5W
loe,s;
(13)
R3
CATHODE GROUND DESIGN
Figure 6 shows the DH0035 driving a cathode grounded PIN
diode switch. The peak turn-on current is given by:
In terms of loe:
(pmax) _ (V+ - V-)2]
(D.C.)
500
Iv I _ aV
1
hfe + 1 = current gain of 04 = 20
VBE Q4 = base-emitter drop of 04 = 0.7V
Vf(PIN) = forward drop of the PIN diode = 0.7V
For typical values given, Ipk = 400 mAo Increasing V+
above 1OV will improve turn-off time of the diode, but at the
expense of power dissipation in the DH0035. Once turn-off
of the diode has been achieved, the DH0035 output current
drops to the reverse leakage of the PIN diode. The attendant power dissipation is reduced to about 35 mW.
= Duty Cycle =
[
+
+ 1) (V+)
where:
eN) + (V+ ;3V -)2]
x (D.C.) ,s; Pmax
where: D.C.
+ Vf(PIN)
I k = V+ - VBEQ4
p
R3
I k "" (V+ - V-I (hfe
p
R3
(12a)
+ 1)
(14)
= 800 mA for the values shown.
The steady state current, loe, is set by Rp and is given by:
For the circuit of Figure 5 and a 500/0 duty cycle, P diss =
0.5W.
Turn-off of the PIN diode begins when the 0 output of the
DM8830 returns to logic "0" and the <:i output goes to logic
"1". 02 turns "ON", and in turn, causes 03 to saturate.
Simuitaneously,01 is turned "OFF" stopping the base drive
..:.(V-::+:-=--_2_V..=.BE=IDe = - R3
- - + Rp
(15)
hje + 1
where: 2VBE = forward drop of 04 base emitter junction
plus Vf of the PIN diode = 1.4V.
143
·:
Y<;"OY
':
"hF
,::r ' :
.
r---i.---""l
I,
I
1
1
IQ
~
.
',,-
.----!r---- '
..L i.
I
'.
L
i
---.r~--
.,....,......,
,,1.1 ,PIN
I
II:I~~~I
1'-__ ...J '
',I
"ZO~~~3OIDM8B30,
,,
Ir
.>C)---:"---~...- - H
o--;'I--ILJ
f-J
'I
'
11
Iii
II
,,'
,"
1-
I
I
I
LOGIC
INPUT
ZOOpF
'.'
J
,
.:...J
Z
Ch
120 pF
':'
y- =-,D.Oy
FIGURE 6:Anode Grounded Driver
In terms of Rp, equation (15) becomes:
Rp = (hie + 1) (V+ - 2VSE) - locRe
(hie + 1) loe
Again the' power dissipated by the DH0035 must beconsidered. In the "OFF" state, the power dissipation is given by:
(15a)
For the circuit of Figufe6, and loc = 100 rnA, Rp is 620
(nearest standard value).
•
It now remains to select the value of C,. To do this, the
change in voltage across C, must be ,evaluated. In the
"ON" state, the voltage across C" Vc, is given by:
V+R3 + Rp(hle + 1) (2VSE)
(V )
CON =
R3 + (hie + 1) Rp
(18)
= 4.2V
10 ns and loe
(19)
=
The "ON" power dissipation is given by:
(21)
The peak turn-off current is, as indicated earlier, equal to
50 rnA x hje which is about 1000 rnA. Once the excess
stored charge is removed, the current through 05 drops to
the diodes leakage current. Reverse bias across the diode
= V- - \lsat .. -10\1 for the circuit of Figure 6.
REPETITION RATE CONSIDERATIONS
, The value of C4 is given, as before, by equation (11):
=
"OFF~'time
"OFF", time + "ON" time
(17)
= 8.0 - 3.8
For a diode with T
250 pF.
= duty cyc::le =
where: (VC)ON is defined by equation (16).
= 8.0V for the circuit of Figure 6.
V-
"
(20)
Total power dissipated by the DH0035 is simply PON +
POFF. For a 50% duty cycle and the circuit of Figure 6,
P diss = 616 mW.
Hence, the change in voltage across Cl is:
Cl = loeT
where: D.C.
"
'
'[V+ - \/-)2]
"PO;F =
R3,
(D.C.)
(VC)ON2
]
PON = [ ~ + loe X (VC)ON (1 - D.C.)
, In the "OFF" state, Vc is given by:
V = (VC)OFF - (VC)ON
'
(16)
For the values indicated above, (VC)ON = 3.8V.
(V)
- V+R3 -lv-IRp
cOFFRp+R3
,
100 rnA, C,
=
Although ignored until now, the PRF, in particular, the
"OFF" time of the PIN diode is important in selection of C2,
RM, and Cl, Rp. The capacitors must recharge completely
during the diode "OFF" time. In short:
144
4RMC2';;; toFF
(22a)
4 RpCl ,;;; toFF
(22b)
CONCLUSION
SUMMARY
The circuit of Figuf8 6 was breadboarded and tested in conjunction with a Hewlett-Packard 33622A PIN diode.
loe was set at 100 mA, V+ = 10V, V- = 10V. Input signal
to the DM8830 was a 5V peak, 100 kHz, 5 ,...S wide pulse
train. RF turn-on was accomplished in 10-12 ns while turnoff took approximately 5 ns, as shown in Figuf8s 7 and B.
In practice, adjustment C2 (Cll may be required to accommodate the particular PIN diode minority carrier lifetime.
A unique circuit utilized in the driving of PIN diodes has been
presented. Further a technique has been demonstrated
which enables the deSigner to tailor the DH0035 driver to
the PIN diode application.
REFERENCES
1. "Pulse, Digital, & Switching Waveforms", Jacob Millman
& Herbert Taub, McGraw-Hili Book Company, Inc., New
York, N.Y.
2. "Models of Transistors and Diodes", John G. Linvill,
McGraw-Hili Book Company, Inc., New York, N.Y.
3. Nationsl Semiconductor AN-1B, Bert Mitchell, March
1969.
4. Hewlett-Packard Application Note 314, January 1967.
145
:8.
:Z 1.2V. Reference
.c(
.
National Semiconductor
Application Note 56
INTRODUCTION
Temperature compensated zener diodes are the most easily used voltage reference. However, the lowest voltage teinperature-compensated zener is 6.2V. This makes it inconvenient to obtain a zero temperature-coefficient reference
when the operating supply voltage is 6V or lower. With the
availability of the LM113, this problem no longer exists.
The LM113 is a 1.2Vtemperature cOmpensated shunt regulator diode. The reference is synthesized using transistors
and reSistors rather than a breakdown mechanism. It provides extremely tight regulation over a wide range of operating currents in addition to unusually low breakdown voltage
and low temperature coefficient.
DESIGN CONCEPTS
The reference in the LM113 is developed from the highlypredictable emitter-base voltage of integrated transistors. In
its simplest form. the voltage is equal to the energy-bandgap voltage of the semiconductor material. For silicon, this
is 1.205V. Further, the output voltage is well determined in a
production environment.
A simplified version of this reference 1 is shown in Figure t.
In this circuit, 01 is operated at a relatively high current
density. The current density of 02 is about ten times lower,
and the emitter-base voltage differential (AVes between
the two devices appears across R3. If the transistors have
high current gains, the voltage across R2 will also be proportional to AVeE. 03 is a gain stage that will regulate the
output at a voltage equal to its emitter base voltage plus the
drop across R2' The emitter base voltage of 03 has a negative temperature coefficient while the AVSE component
across R2 has a positive temperature coefficient. It will be
shown that the output voltage will be temperature compensated when the sum of the two voltages is equal to the
energy-band-gap voltage.
Conditions for temperature compensation can be derived ,
starting with the equation for the emitter-base voltage of a
transistor which is2 .
VeE = Vgo (1 -
nkT I
To kTI
Ie
(1)
Oge- + - Oge-,
q
T
q
lco
where VgO is the extrapolated energy-band-gap voltage for
the semiconductor material at absolute zero, q is the charge
of an electron, n is a constant which depends on how the
transistor is made (approximately 1.5 for double-diffused,
NPN transistors), k is Boltzmann's constant, T is absolute
temperature, Ie is collector current and VeEo is the emitterbase voltage at To and lco.
The emitter-base voltage differential between two transistors operated at different current densities is given by
kT
J1
AVeE = -Ioge (2)
q
J2
where J is current denSity.
Referring to Equation (1), the last two terms are quite small
and are made even smaller by making Ie vary as absolute
temperature. At any rate, they can be ignored for now because they are of the same order as errors caused by nontheoretical behavior of the transistors that must be determined empirically.
If the reference is composed of VeE plus a voltage proportional to AVeE, the output voltage is obtained by adding (1)
in its simplified form to (2):
Vref = Vgo (1 -
aVref = _ VgO
aT
To
~
r---..--.....-e-
~) + VeEo
VREF = VaE
R2
+ ii3.1VaE
'-":"_"--':"'-.-GROUNO
TLlH17370-1
FIGURE 1. The Low Voltage Reference
In One of Its Simpler Forms
GJ +
k;
10ge~.
(3)
Differentiating with respect to temperature yields
v+
I
~) + VeEO (~) +
+ VeEo + ~IOge:!!.
To
q
J2
(4)
For zero temperature drift, this quantity should equal zero,
giving
kTO
J1
(5)
Vgo = VeEO + -I0geJ2 .
q
The first term on the right is the initial emitter-base voltage
while the second is the component proportional to emitterbase voltage differential. Hence, if the sum of the two are
equal to the energy-band-gap voltage of the semiconductor,
the reference will be temperature-compensated.
Figure 2 shows the actual circuit of the LM113. 01 and 02
provide the AVeE term and 04 provides the VeE term as in
the simplified circuit. The additional transistors are used to .
decrease the dynamic resistance, improving the regulation
of the reference against current changes. 03 in conjunction
with current inverter, Os and Os, provide a current source
load for 04 to achieve high gain.
Or and 09 buffer 04 against changes in operating current
and give the reference a very low output resistance. 08 sets
the minimum operating current of Or and absorbs any leak-
146
R4
Rl
3.9K
13.5K
R2
200
TLlH/7370-2
FIGURE 2. Schematic of the LM113
age from C9. Capacitors Cl, C2 and resistors Rg and Rl0
frequency compensate the regulator diode.
10
I 1111
mo c;
PERFORMANCE
The most important features of the regulator diode are its
good temperature stability and low dynamic resistance. Figure 3 shows the typical change in output voltage over a
-55°C to + 125°C temperature range. The reference volt·
age changes less than 0.5% with temperature, and the tem·
perature coefficient is relatively independent of operating
current.,
t::t
25°C
rt/
I.r~
F/{Jure 4 shows the output voltage change with operating
current. From 0.5 mA to 20 mA there is only 6 mV of
1'-55°C
-2
0.3
change. A good porIion of the output change is due to the
resistance of the aluminum bonding wires and the Kovar
leads on the package. At currents below about 0.3 mA the
diode no longer regulates. This is because there is insuffl·
cient current to bias the internal transistors into their active
region. F/{Jure 5 illustrates the breakdown characteristic of
the diode.
30
10
REVERSE CU RRENT ImA)
TL/H/7370-4
FIGURE 4. Output Voltage Change with Cu"ent
10'"
1.240
1.-1 iliA
...~ 1.230
'"~
~ 1.220
i!...
>
lI!
..,.
~
,.
~
A?1';
Zsoc
10'5
1.210
o.z
0.4
D..
~C
0.'
I
1.0
1.2
1.4
REVERSE VOLTAGE IV)
TLlH/7370-5
1.200
-55 -35 -15 5 25 45 &5 &5 1115 125
FIGURE 5. Reverse Breakdown Characteristics
TEMPERATURE rc)
APPUCATIONS
The applications for zener diodes are so numerous that no
attempt to delineate them will be made. However, the low
TLlH17370-3
FIGURE 3. Output Voltage Change with Temperature
147
r--4.....-.IIV
breakdown voltage and the tact tJ:ta,t the brea,kdown voltage
is equal to a physical property of silicon-the energy band
gap voltage-makes it useful in several interesting applications. Also the low temperature coefficient makes it'useful in
regulator applications-especially in battery powered systems where the input voltage is less than 6V.
Figure 6 shows a 2V voltage regulation which will operate
on input voltages of only 3V. An LM 113 is the voltl\ge reference and is driven by a FET current source, 01. An operational amplifier compares a fraction of the output voltage
with the reference. Drive is supplied to output transistor 02
through the V+ power lead of the operational amplifier. Pin
6 of the op amp is connected tothe LM113 rather, than the
output since this allows a lower'miriimum input voltage. The
dynamic resistance of the ,LM 113. is so low that current
changes from the output of the operational amplifier do not
appreciably affect regulation. Frequency compensation is
accomplished with both the 50 pF and the 1 p.F output capacitor.
OUTPUT
lM113
30K
1%
....~...---15V
TLlH17370-7
FIGURE 7. Amplifier Blaaing for
Constant Gain with Temperature
regulated against supply variations keeping the gain stable
over a wide supply range.
As shown, the gain will change less than two per cent over a
':"'55°C to + 125·C temperature range. Using the LM114A
monOlithic transistor and low drift metal film resistors, the
amplifier will have less than 2 p.VI"C voltage drift. Even lower drift may be obtained, by unbalancing the collector load
resistors to null out the initial offset. Drift under nulled condition will be typically less than 0.5 p.vrc.
The differential amplifier may be used as a pre-amplifier for
a low-cost operational amplifier such as an LM101A to improve its voltage drift characteristics. Sinoe the gain, of .the
operational amplifier is increased by ,a' factor of 100, the
frequency compensation capacitor must also be increased
from 30 pF to 3000 pF for unity gain operation. To realize
low voltage drift; case must be taken to minimize thermoelectriC potentials due to temperature gradients. For example, the, thermoelectric po~ential of some re,sistors may be
more than 30 p.Vre, so a 1°C temp!ll'ature gradient across
the resistor on a circuit board ,will cause much larger errors
than the amplifier drift alone. Wir.ewound resistors sugh as
Evenohm ar4!l' a good choice for I~w thermoelectric potential.
'
Figure 8 illustrates an electronic thermometer using an inexpensive silicon transistor as the temperature sensor. It can
provide better than 1°C accuracy over a 100"C range. The
emitter-bese turn-on voltage of silicon transistors is linear
with tempf/rature. If the operating current of the sensing
transistor is' milde proportionat to' absolute temperature the
nonlinearily of emitter-base voltage can be minimized. Over
a - 55°C to 125°C temperature range the 'nonlinearlly is less
than 2 mV or the equivalent of 1°C temperature change.
An LM113 diode regulates the input 'voltage to 1.2V. The
1.2V is applied through R2 to set the operating current of
the temperature-sensing transil!tor.
Resistor R4 biases the output of the amplifier for zero output
at O°C. Feedback, resistor R5 is then us8d to calibrate the
output scale factor to 100 mV1°C, Once the output is zeroed, adjusting the scale factor does not change the zero.
R2
620
RI
Q2
390
2N2905
01
lM113
I.2V
..""'w-+------..
-VOUT
R3
12.3K
,%
•
2V
C2t
I""
":'
t Solid lantalum
TLlH17370-8
FIGURE 6. Low Voltage Regulator Circuit
It is important to use an operational amplifier with low quiescent current such as an LM108. The quiescent current flows
through R2 and tends to turn on 02. However, the value
shown is low enough,to ,insure that 02 can be turned off at
worst case condition of no load ,and 125°C 'operation.
Figure 7 shows a differential amplifier with the current
source biased by an LM113. Since the LM113 supplies a
reference voltage equal to the energy band gap of silicon,
the output current of t,he 2N2222 will vary as absolute temperature. This compensates the temperature sensitivity of
the transconductance of the differential amplifier making the
gain temper!iture stable. Furthe~, the operating current is
148
+15V
I
I
I
I
,,
R5
R6
100 K'
lOOK
I
I
R2
3K
t Adiust for OV at O"C
, Adiust for 100 mV
rc '
-15V
TUH/7370-B
FIGURE 8. Electronic Thermometer
CONCLUSION
A new two terminal low voltage shunt regulator has been
described. It is electrically equivalent to a temperature-stable 1.2V breakdown diode. Over a -55°C to 125°C temperature range and operating currents of 0.5 mA to 20 mA the
LM113 has one hundred times better reverse characteristics than breakdown diode. Addiitionally, wideband noise
and long term stability are good since no breakdown mechanism is involved.
The low temperature coefficient and low regulation voltage
make it especially suitable for a low voltage regulator or
battery operated equipment. Circuit design is eased by the
149
fact that the output voltage and temperature coefficient are
largely independent of operating current. Since the reference voltage is equal to the extrapolated energy-band-gap
of silicon, the device is useful in many temperature compensation and temperature measurement applications.
REFERENCES
1. R.J. Widlar, "On Card Regulator for Logic Circuits, " NationalSemiconductor AN-42, February, 1971.
2. J.S. Brugler, "Silicon Transistor Biasing for Linesr Collector Current Temperature Dependence," IEEE Journal of
Solid State Circuits, pp. 57-58, June, 1967.
~
.-------------------------------------------------------------------------,
',~
LM380 Power Audio
_
Amplifier
~:
National Semiconductor
Application Note 69
" ',
;
INTRODUCTION
The LM380 is a power audio amplifier intended for consumer applications. It features 'an internally fixed gain of 50
(34 dB) and an output which automatically centers itself at
one-half of the supply voltage. A unique input stage allows
inputs to be ground referenced or AC coupled
required.
The output stage of the LM380 is protected with both short
circuit current limiting and thermal shutdown circuitry. All of
these internally provided features result in a minimum external parts count integrated circuit for audio applications.
This paper describes the circuit operation of the LM380, its
power handling capability, methods of volume and tone control, distortion, and various application circuits such as a
bridge amplifier, a power supply splitter, and a high input
impedance audio amplifier.
input is chosen to referencEithe' input' to ground, thus enabling the input transducer to be directly coupled.
, The output is biased to half; the supplY voltage by resistor
ratio R1/R2. NegatiVe DC feedback, through resistor R2,
balances the differential stage with the output at half supply,
since R1 = 2 R2 (Figure 1).
The second stage iSB Common emitter voltage gain amplifier with a current-source load. Internal compensation is provided by the pole-splitting capacitor C'. Pole-splitting compensation is used to preserve wide power bandwidth
(100 kHz at 2W, 80). The output is a quasi-complementary
pair emitter-follower.
The ampli(ier gain is internally fixed to 34 dB or 50. This is
" accomplished by the internal feedback network R2-RS. The
gain is twice that of the ratio R2/Rs due to the, ~ay!? cu~~ent
CIRCUIT DESCRIPTION
source which I?rovides the full differential gain of the input
Figure 1 shows a simplified circuit schematic of the LM380.
'stage.,
'" "
,.".', ,','. '"",,, ," '.,
The input stage i$ a PNP emitter-follower driving a PNP differential pair with a slave current-source load. The PNP
as
:
:
'
,
,
:
'
TABLE I. ElectrlcalCharacterlstlca (Note ')
' . , Min
Parameter
Condlt!oll8
POwer Output (rms)
Gain
Output Voltage Swing
Input Resistance
Total Harmonic Distortion
Power Supply Rejection
80 loads, 3% T.H.D. (Notes 3,4)
Supply Voltage Range
Bandwidth
Quiescent Output Voltage
Quiescent Supply Current
Short Circuit Current
Note 1: Vs
2.5
40
80 load
Po = 1W,(Notes4&5)
Cbypass = 5 p.F, t = 120 Hz
(Note 2)
Typ
Max
50
.14
150k
0.2
38
60
8
Po
= 2W,RL = 80
22
100k
8
9
7
10
25
1.3
= lBV; TA = 25"C unless oIherwiss spacIfIed.
Note 2: Relectlon ratio referred to output
Note 3: WHh device Pins 3. 4, 5, 10, 11. 12 soldered into a 11,.' epoxy glass board with 2 ounoa coppar 10K with a minimum surface of six square inches.
Note 4: If oscillation exis1s under 80ma load conditions. add a 2.70 resistor and 0.1
ssrIes network from Pin Blo ground.
Note 5: C!,ypase = 0.47 ,.F on Pin 1.
Note 6: Pins 3. 4, 5, 10, 11, 12 at 50"C deraleS 25'C/W above 5O"C casa.
,u=
150
i
r------------...---....-o V• II4I
HI
-]
BYPASS
III
1.1
HZ
25IC
OUTPUT
III
Rl
Rl
11.1
UK
-1M
(II
(3, 4. 5. 18. 11. lZI
(1I&ND
SID
TL/HI7S80-1
FIGURE 1
GENERAL OPERATING CHARACTERISTICS
3.5
The output current of the LM380 is rated at 1.3A peak. The
14 pin dual-in-line package is rated at 35°C/W when soldered into a printed circuit board with 6 square inches of 2
ounce copper foil (Figure 2). Since the device junction temperature is limited to 150"C via the thermal shutdown circuitry. the package will support 3 watts dissipation at 50"C ambient or 3.7 watts at 25°C ambient.
Figure 2 shows the maximum package dissipation versus
ambient temperature for various amounts of heat sinking.
I2.D
~
B.O
...~
...;;:
'"
6.0
i
.
E
c 2.5
..
i....
.
1:
~
~ ......
'> rt"
1.1
1.0
.~
~
4
...
n,. !"='"
~
,
rift3!ltiIST.
TII%
0.5
DIST•
LEVEL
D 0.5 I.D 1.5 2.0 2.5 3.0 3.6 4.0 4.5 5.0
OUTPUT POWER (WAnS)
TL/H17380-4
FIGURE 3b. Device DlsslpaUon
va Output Power - ao Load
4 SII.11 tD"'ER FOll'.C BOARD
1:-no IN comA FOIL p,e.HARD WC/.
~\IO.lfII COPHRFOllP.t.~~:
1
4.0
2.8
3.1
FAlElAIA,
2D
3D 40
50
60
70
E
80
..
i..
TLlH17380-2
FIGURE 2. Device Dissipation va Ambient Temperature
F/{Jures Sa, b, and c show device dissipation versus output
power for various supply voltages and loads.
3.6
2.5
z.o
V•
1.1
./
..,
.-
14V
..;'"
12V
'"\IV
1.8
....
"
"
•o o.s
1.5
3..
20\
1.1
o.s
:~I-
--
-I-
~
.,..
:-.... ~
~~
J."
..
~
111% DIST.
LE1VEL,
1.5 2.0 2.5 3•• 3.6 4.0 4.6 1.0
TL/H/7380-5
~-
3.5 4.D
OUTPUT POWER (WATTS)
V•
FIGURE 3c. Device Dissipation
vs Output Power -160 Load
iI.D 1.5 2.' 2.5
;::
3!lDIST.
LEVEL
OUTPUT POWER (lVATTS)
" f .G -
1.5
I
o o.s I.D
" '" ~[a:a: ! -
111%
LDJn
2.5
2••
!l!:
3!lDIST.
LEVEL
3.0
i.... ..
...
;;:
.....
I-
.
~~?.~l,~...'j':.~\~~.~~~A:'I~3rc/.
..... f-
TO
5!
-
VII.
z
;::
"""'- ......
TA -AMBIENTTEMl'ERATURE ('C)
i.
/
,.
2.'
~ I"
-
IIIFI!ITEME~TSI.J lrCI~
TO.O
'"'"
11
TLlH/7380-3
FIGURE 38. Device Dissipation
va Output Power - 40 Load
151
.~ ~----------------------------------------------~----------------------------~
The maximum device dissipalion is obtained f!'Om Figure 2
.-source impedance for Ihe inlegrator. Figure 6 shows supply
decoupling versus frequency for various bypass capacitors.
for Ihe heal sink and ambienllemperature condi.lions under
which Ihe device will be operating.: With Ihis,m~mum alBIASING
lowed dissipation, Fl!Jures Sa, band c show "'Ie maximum
The simplified schemalic of Figure 1 shows Ihal the LM380
power supply allowed (10 stay wilhln dissipation limits) and
is internally biased with the 150 kO resistance to ground.
Ihe output power delivered inlo 4, 8 or 160 loads. Thelhree
This enables input transducers which are referenced to
percenl 10lal-harmonic distortion line is approximalely Ihe
ground to be direct-coupled to either the inverttng or non-inon-sel of clipping.
verting ililPuts of the amplifier. The unused input may be
2.0
II ' I I ; I II RL =.n
eilher:1) left floating, 2) returned to ground through a resis1.8
II I 1,:1 II \IV
tor or capacitbr or 3) shorted ground. In most applications
~ 1.1
where the non-inverting input is used, Ihe inverting input is
'~7" ~EA~ ~I~K- .:....:.
~ 1A r- ~~~ER
co
left flO!lting. When the inverting input is used and the non-ini
'
1.2
;;;
verting input is left floating, the amplifier may be found to be
I
1.0
sensitive to board layoul since stray coupling to Ihe floating
1
I OJ
'. input is positive. feedback. This can be avoided byemploy.!. f~ 0.1
Ing 01]9 of three allerflatives: 1) AC grounding the unused
17
;:! DA r--;II'~
input with a small capacitor. This is preferred when using
~III
~
0.2
high $ource impedance transducer. 2) Returning the unused
o
Input to ground through a resistor. This Is preferred when
I .. 290 500 Ik 2k
Ilk 10k 201c
uslngmoderale to low' DC source impedance transducers
FREQUENCY (Hz)
and When output oliset from half supply voltage is critical.
TlfHI7380-6 .
The resistor is made equal to the resistance of the input
FIGURE 4. Total Harmonic Distortion vs Frequency
transducer, thus maintaining balance in the input differential
amplifier and minimizing output 'offsEll 3) Shorting the' unFigure 4 slJows lotal harmonic dislortion versus frequency
used inpt,lt to ground. This is used with low DC source imfor various. output jevels, while. Figure 5 shows the power
bandwidth of the LM3.80.
.
pedance. transducers or when output offsel voltage is· noncritical.
i
....
..
to
~
.w'
48
«
OSCILLATION
The normal p~e~ supply decoupling precauti~ sh.O~ld be
taken when installing the LM380. If Vs is more than 2" to a~
from Ihe power supply filter capaqitor it should tie decoUpled with a 0.1 J.LF disc ceramic capacitor at the Vs.terrninal
ofthelC..
The Rc and Co shoWn as dotted line components on Figure
7 and throughout Ihis paper suppresses a 5 to 10 MHz
•
Vee "',18V
35
;;; 30
~
......
..
~
~
• RL 0 -
2&·
I II
'ii
20
...
E
,
II
1·"1
.... = 8n I
>. 18
240"
'OI/T'~~
10
188
Ik
10k
.100k
v.
30Ir
11111.
•
l\ 3&0"
1M
l.aM
+Co~
FREQUENCY (Hz)
TLlHI7380-7
•
FIGURE 5. Output Voltage Gain va Frequency
Power supply ciecoupling is achieved Ihr9ugh the AC divider
formed by R1 (Figure 1) and an external bypass capacitor.
Resislor R1 is split inlo ~o 25 kO halves providing a high
.
4.Rc·
~2.7Sl
.....
.0·CC···
.hF:r:-
...
....
~
TLlHI7380-9
'F& Stability WIIh High Current Loads
FIGURE 7. Minimum Component Configuration "
small amplitude oscillation which can occur during Ihe negalive swing into a load which draws high currenl. The oscilla·
tion is of course alloo high of a frequency to pass through a
speaker, but it should be guarded againsl when operating in
an RF sensitive.environment.
'
10Hz..
.1.Hz·
lk~z..
10kHz
FREQUENCY
TL/Hf7380-8
FIGURE 6. Supply Decoupllng vs Frequency
152
This circuit has a distinct advantage over the circuit of Figure 7when transducers of high source impedance are used,
in that, the full input impedance of the amplifier is realized. It
also has an advantage with transducers of low source impedance since the signal attenuation of the input voltage
divider is eliminated. The transfer function of the circuit of
FIfJIJf8 10 is given by:
APPLICATIONS
With the internal biasing and compensation of the LM380,
the simplest and most basic circuit configuration requiras
only an output coupling capacitor as seen in FlIJure 7.
An application of this basic configuration is the phonograph
amplifier where the addition of volume and tone controls is
required. Figure 8 shows the LM380 with a voltage divider
volume control and high frequency roll-off tone control.
V.-I.V
Figure 11 shows th8 response of the circuit of FlIJure 10.
10
41
48
TLlH/7380-10
"For StabIlIty with High Currant Loads
3Ii
FIGURE 8. Phono Amp
When maximum input impedance is required or the signal
attenuation of the voltage divider volume control is undesir·
able, a "common mode" volume control may be used as
seen in FllJUre 9.
311
+lIV
lH.
Co
10H. l00H. 1kH. llkH. l00kH.
I/IIIJ~'F_
FREOUENCY
••
TLlH/7380-13
lie'
FIGURE 11. Tone Control Response
Most phonograph applications require frequency response
shaping to provide the RIM equalization characteristic.
When recording, the low frequencies are attenuated to prevent large undulations from destrOying the record groove
walls. (Bass tones have higher energy content than high
frequency tones). Conversely, the high frequencies are emphasized to achieve greater signal-to-noise ratio. Therefore,
when played l1ack the phono amplifier should have the inverse frequency response as shown in Figure 12.
2.70
.cc .....
o.l~F~';:-'
an
TLlH/7380-11
'For stability with High Currant Loads
FIGURE 9. "Common Mode" Volume Control.
.With this volume control the source leading impedance is
only the input impedance of the amplifier when in the fullvolume position. This reduces to one-half the amplifier input
ill1pedance at the zero volume position. Equation 1 describes the output voltage as a function of the potentiometer setting.
VOUT =
50 VIN ( 1 -
150 x 103
)
klRV + 150 x 103 0 ;<;kl ;<; 1
:--::,....;-:~.....,:..=---=
30
I,
II
!
...~
•
...
....
(1)
10
..
1M
1M
+11V
..
1M
Is
~
18
1M
30
10Hz
110Hz
I kHz
10kH.
l00kH.
FREOUENCY
TL/HI7380-14
'For stability with High Currant Losds
"Audfo Tape p~ (10"" of RT at 5O",,'Rotatlon)
FIGURE 12. RIAA Playback Equalization
This response is achieved with the circuit of Figure 13.
The mid-band gain, between frequencies f2 and f3, Figure
12, is established by the ratio of Rl to the input resistance
of the amplifier (150 kll)..
TL/H/7380-12
FIGURE 10. "Common Mode" Volume and Tone Control
This "common mode" volume control can be combined with
a "commcn mode" tone control as seen in FlIJure 10.
153
.~ .-~--~----------------------------------------------------------------------~
.~
~
.
Mid-band G' = R1 + 150 kO
~n, 150kO'
factor of four over the single amplifier. HOWever,.in most
cases the package dissipation. will ~. the first Parameter
Iimitipg power ,delivered to the.lqa!l. When. this ill the case,
the power 9apability.of the bridge will be only ,twice that of
. (3)
+11V
...~
,Co
1ft._~·F
.
~ 3.• , H-AA""f--biioN
f Z.5 Hr8YA-::I:;..+.....tt-r--I
2.70
:::::Cc:* 8n
a:
~ Z.O r~P1~::l;!t~-er1"-j
-.:!o..- o.1f,1F
CI
22IIpF
!f
R,·ulll
.
:2:
TUHI7380-15
1-':-~~;::+:.:t~~4-t1
I
H""'I--+:::6......r-+
.5 I-~F-I-I-+-+.,..
~
0 I-1-oJL......I--I--'--'-'"--'---o.....J
...
UI
2.D
3.0
4.0
U'
FIGURE 13. RIAA Phono Amplifier
Capacitor C1 sets the corner frequency f2 where
Ri = Xci·
1
Ci = - -
OUTPUT POW£R \WATTS!
TL/HI7380-17
FIGURE 15A. 80 Load
the single amplifier. Figures 15A and B show output power
versus device package dissipation for both 8 and 160 'Ioads
in the bridge configuration. The 3% and 10% harmonic
(4)
,
2'11"f2Ri
Capacitor C2 establishes the corner frequency f3 where Xc2
equals the impedance of the inverting input. This is normally
150 kO. However, in the circuit of Figure 13 negative feedback reduces the impedance at the inverting input as:
.~
c
.
.
= 1 + Aof3
c
~
(5)
Ao
fJ
= feedback, transfer fullction
:~ofJ).'
~
Vcc· 14V
II
•
E
}
I
,
I
I"S .... ....
11J%DIST. -
I LEV~T
LEVEL
3"DIST.
1234567
OUTPUT POWER \WATTS,1.!! LOAD
TL/H/7380-18
----;-...;...,=--"""'7"
2'11"f3 (1
--
HI:: ..:::.:.:'
~ "",, .,..
: o.s
~o-:
ZIV
I .,,:'!'
~
!:' 1
A = ,closed loop gain with exte~nal feedback.
Therefore'
C2 =
~
f
=
fJ =
/L
2.5
15 2
II 1.5
Where:
impedance at node, 6 without external feedback
(150 kO)
= gain without external feedback (50)
L..!..k~:""
1'00.'
vcc-
!3.0
Zo
Zo
1.5
, Bt,D
, For Slabilily wllh High CUrrent Loads
.Z
4.0 r'-r....,-.,.....-r-r-..,.......,,...-r""T"""""1
!3.1
150k )
2'11"f3 1 + 50P
FIGURE 15B. 160 Load
distortion contoiJrs double back due to the thermal limiting
of the LM380. Different amounts' of heat sinking will change
the point at- which the distortion contours bend. ' ' ,
The quiescent ~utpt4 voltage of the LM380 is specified at.9
± 1 volts with an 18 volt supply. Therefore, under the worst
case condition, It is possible tel have two volts DC across
.
.
the load.
(6)
(
BRIDGE AMPLIFIER
Where more power is desired than can be provided with one
amplifier, two amps may be used in the bridge configuration
shown in Figure 14.
v.
v.
TL/H/7380-16
TL/HI7380-19
'For ~bllity wlIh High CUrrent Loads
'For Stability wlIh High
FIGURE 14. Bridge configuratIon
This provides twice the voltage swing across the load for a
given supply, thereby, increasing the power capability, by a
Current Loads
FIGURE 16. Quiescent Balanett Control
an ,80apeaker this ,0.~5A which may: be,excessive.
Three alternatives are available; 1) care can be taken' to
,inatch ,the quiesCent voltages. 2) a non;polar capacitor may
be placed in series with the load, 3) the offset balance control of Figure'16 may be used.
Y/ittl
154
RI
J5K
RZ
UK
,-1
*
TL/HI7380-20
'For Stability with High Cu....nl Loads
FIGURE 17. Voltage Divider Input
vs
LISTEN
S1A
1 TALK
1
'::"
1
1
1
I
.
I·
_
-
:
1
. .'
"~
~--------------------------~
TL/HI7380-21
'For Stability with High Cu....nl LOads
FIGURE 18. Intercom
The circuits of Figures 14 and 16 employ the "common
mode" volume controi as shown before. However, any of
the various input,connection sChemes discussed previously
may be used. Figure '17 shows the bridge configuration with
the voltage divider input. As discussed in the "Biasing"
section the undriven input may be AC or DC grounded. If Vs
is an appreciable distance from the power supply (>3") filter capacitor it should be decouple(! with 1 p.F tantaulum
capacitor.
f
l
a
INTERCOM
The circuit of Figure 18 provides a minimum component Intercom, With switch 51 in the talk position, the speaker of
the master. station acts as the microphone with the aid of
,step-up transformer T1.
."
A turns ratio of ·25 and a device gain of 50 aHows a maximum loop gain of 1250. Rv provides a "common mode"
volume control. Switching 51 to the listen position reverses
the role of the master and, remote speakers.
LQW COST. DUAL SUPPLY
The circuit shown in Figure 19 demonstrates a minimum
parts count method of symmetrically splitting a supply ,voltage. Unlike the normal R, C, and power zener diode tech-
I
I
I
I
I
I
Rl~
lM~
I
I
I
TL/HI7380-22
FIGURE 19. Dual Supply
nique the LM380 circuit does not require a high standby
current and power dis.sipation to maintain regulation.
With a 20 volt input voltage (± 10 voit output) the circuit
.exhibits a change in output lioltage of approximately 2% per
100 mA of unbalanced load change. Any balanced load
change will reflect' only the regulation of the source voltage
VIN·
'
The'theoretlcal plus and ·minus output tracking ability is
100% since the device will pr.ovide an output voltage at
one-half of the instantaneous supply voltage in the absence
of a capacitor on the bypass terminal. The actual error in
BOOSTED GAIN USING POSITIVE FEEDBACK
For applications requiring gains higher than the internally
set gain of 50, it is possible, to apply positive feadback
around the LM380 for closed loopgains of up to 300. Figure
21 shqws a practical example of an LM380 in a gain of 200
circuit.
'. '.
tracking will be directly proportional to the unbalance in the
quiescent output voltage. An optional potentiometer may be
placed at pin 1 as shown in Figure 19 to null output offset.
The unbalanced current output ~or the circuit of Figu;e 18 is
limited by the power dissipation of the package.
In the case of sustained unbalanced excess loads, the de- ~
vice will go into thermal limiting 'as tne temperature sensing
circuit begins to function. For instantaneous high curr,ent
loads or short circuits the device limits ,the output current to
approximately 1.3 amperes until thermal shut-down takes
over or until the fault is removed.
,: V,· +-'IV
Vo
HIGH INPUT IMPEDANCE CIRCUIT
The junction FET isolation circuit shown in Figure 20, r~ises
the input impedance to 22 MO for low frequency input signals. The gate to drain capacitance (2 pF maximum for the
KE4221 shown) of the FET limits the input impedance as
frequency increases.
Rl
1%
0'
v.
-
1M
cz
24pF
III
TUH/7380-24
FIGURE 21. BOoatecI Gain 200
Using Positive Feedback
The equation describing the closed loop gain is:
G
v.. 0 - - " , - "
10..
AVCL =
-AWOl)
1 _ AWOl)
,
1
,
TLlHI7380-23
FIGURE 20
At 20 kHz the reactance of this capaCitor Is approximately
- j4 MO giving a net input impedance magnlttide of 3.9 MO.
The values chosen for Rt, Fla and C, provide an overall
circuit gain of, at least 45 for the complete range of parameters specified forthe KE4221.
When using another FET device the rllievant design equations are as:followa:·
ZIO
,r,.J
llG
'II
ZIG
t
!Ii
J
101
II
(~) (50)
R,
+-
(12)
R,
+-
R2
where AV(OI) Is,complex at high frequencies but is nominally
the 40 to 60 specified on the data sheet for the pass band
of the amplifier. If 1 + R,/R2 approaches the value of
AV(OI)' the denominator of equation 12 approaches zero, the
closed loop gain increases toward infinity, and the circuit
oscillates. This Is the reason for limiting the closed loop gain
values to 300 or less. FlflUre 22 shows the loaded and unloaded bode plot for the circuit shown in Figure 21.
RZ
Z2M
. Av =
1\
"
..
R ·In """'\
1/
\
V
D
10
(7)
.J.
\
IDa
lk
11k , . 1M
IUM
FREQUENCY (HzI ..
gm
TUH/7380-l/5
,
'( , VGS)"
, gm = gmO 1-
(8)
VGS =loSR,
(e)
FIGURE 22. Booated Gain Bode Plot
The 24 pF capacitor C2 shown on Figure 21 was added to
give an overdamped square wave response under fuliload
conditions. It causes ,a high frequency roli-off of:
(10)
f2 = 2'ITR2C2'
v;:
.
los = loSs ( 1
VGS)2
---vp
,
,
1·'
a
(13)
The circuit of Figure 21 will have very long (1000 sec) tum
on time ,if RL is not present, but only a 0.01 second turn on
tlme.with an 80 load.
The maximum value of R2 is determined by ttee product of
the gate reve~ leakage IGSS and R2 .. This voltage should
be 10 to 100 times smaller than Vp.The output impedance
,of the FET source follower is:
1
Ro=(11)
gm
so that the determining resistance for the interstage RC
time constant is the input resistance of the LM380.
158
Micropower Circuits Using
the LM4250 Programmable
OpAmp
National Semiconductor
Application Note 71
George Cleveland
INTRODUCTION
The LM4250 is a highly versatile monolithic operational amplifier. A single external programming resistor determines
the quiescent power dissipation, input offset and bias currents, slew rate, gain-bandwidth product, and input noise
characteristics of the amplifier. Since the device is in effect
a different op amp for each externally programmed set current, it is possible to use a single stock item for a variety of
circuit functions in a system.
This paper describes the circuit operation of the LM4250,
various methods of biasing the device, frequency response
considerations, and some circuit applications exercising the
unique characteristics of the LM4250.
Referring to Figure 1, 01 and 02 are high current gain lateral PNPs connected as a differential pair. Rl and R2 provide
emitter degeneration for greater stability at high bias currents. 03 and 04 are used as active loads for 01 and 02 to
provide high gain and also form a current inverter to provide
the maximum drive for the single ended output into Os. Os is
an emitter follower which prevents loading of the input stage
by the succeeding amplifier stage.
One advantage of this lateral PNP input stage is a common
mode swing to within 200 mV of the negative supply. This
feature is especially useful in single supply operation with
signals referred to ground. Another advantage is the almost
constant input bias current over a wide temperature range.
The input resistance RIN is approximately equal to 2fJ CRE
+ re) where fJ is the current gain, re is the emitter resistance of one of the input lateral PNPs, and RE is the resistance of one of the 10 kO emitter resistor. Using a DC beta
of 100 and the normal temperature dependent expression
for regives:
CIRCUIT DESCRIPTION LM4250
The LM4250 has two special features when compared with
other monolithic operational amplifiers. One is the ability to
externally set the bias current levels of the amplifiers, and
the other is the use of PNP transistors as the differential
input pair.
r-__________________-4~------------_1l7 V'
HI
lao
RI2
UK
RI
5K
RIO
IK
Rll
5K
rQU~IQES~C~EN·T~-t----~~~--------~~~~
~CURRENT SET
R5
l
lise•
..
RII
50
R13
100
OUTPUT
R17
100
OFFSET (5....._ _•
NUll
RC
R3
5K
R7
11K
5K
L-___-4~----~-~---~----~--_64 vFIGURE 1. LM4250 sChematic Diagram
157
TUH/7382-1
.....
~
r-------------------------------------------------------------------------------------~
,.IJ'I.'
.~
,
RIN ~ 2 MO
.
'kT'
grate<:! cirCllit chip. In applications where the reglliation of
the!J-+: suppiywithrespeet tothe'V", supply (lUi in the case
of tracking regulators) il! better than th~ V + supply with
respect to ground·thll set reslstor should be connected from
"
Pin 8 to V-. RSET is then:
+ 2 --
(1)
,
qlS;
~; ',"Where Is is input bias current. At room ·temperature ,this :for-
mul~,bEi6j)mes:
RSET =
V+
+ iv-H).5"
(4)
ISET
The transistor and resistor scheme shown in ,figure 3b allows one to switch th,e amplilier off. without disturbing the
main V+ and V:'" po~er sUPP,ly conn~ions. Attaching C1
acrosS the circuit prevents 'any switching .\(ansient fron'! appearing 'at the amplifier output.' The dual scheme shown in
Figure 3q has a constant set current flowing through RS1
a~ a varilible current through RS2. Transistor Q2 acts as an
emitter follower current sink 'whose value d~pends on the
control voltage Vc on the base. This circuit provides Ii mathTO PIN 8
TO PIN 8
I
I.
~~~~~~~~~
,.1
1.0
100
ISET",",)
:~SWITCH
TLlH/7382-2
'QI
--1
""
C'I
, .fIG~RI; 2., ",putRealatance VB ISET
Figure. 2 gives a, typical plot ,of RIN vs lset derived from the
above equation.
, "r". IOOOpF
Rs
:,',
Continuing with the circuit description. Qs level shifts downward to the base of Qs which is the second stage amplifier.
Qs is run as a common emitter amplifier with a current
source load (Q121 to provide maximum gain. The output of
Qs drives the class B complementary output stage composed of Q15 and Q1S.
The bias current levels in the LM4250 are sef by the amount
of current (Iset> drawn out of Pin 8. The constant current
sources Q10. Q11, and Q12 are controlled by the amount of
lset current through the diode connected transistor Q9 and
resistor R9. The constant collector current from Ql0 biases
the differential input stage. Therefore, the IElVel Q10 is set at
will control such amplifier characteristics
input bias current, input resistance, and amplifier slew rate. Current
source Qll biases Q5 and Qs. The current ratio between Q5
and Qs is controlled by constant current sink' Q7. Current
source Q12 sets the currents in~iodes'Ql3 and Q14 which
bias the output stage to the, verge of conduction, thereby
eliminating the dead zone in the class B output. 012 also
actS as the load for Qs and limits the drive current to Q15.
The output current limiting Is provided by Q16 and Q17 and
their associated resistqrs R16.and R17. When enough current is drawn from the output, Q16 turns on and limits ' the
base drive of QIS. Similarly Q17 turns on whet! the LM4250
attempts to sink too much current, limiting the base drive of
QIS and therefore output current. Frequency compensation
is provided by the 30 pF capaCitor across the second stage
amplifier, Qs, of the LM425o. this provides a 6 dB per octave rolloff of the open loop gain.
.
V-OR
GROUND
Y-OR
GROUND
TLlHI7382-4
TLlHI7382-3
sa
3b
TO PIN B
as'
, Vc
-vo
Y-OR
GROUND
V-OR
GROUND'
TLlHI7382-5
TL/H/7382-B
3c
3d
FIGURE 3. Biasing Schemes
od of ,varying the amplifier'S characteristics over a limited
rangll while the amplifier is in operation. The FET circuit
shown in Figure 3d covers the full range of set currents in
response to as Ii,ttle as a 0.5V gate potential change on a
low pinch-Off voltage FET such as the 2N3687. The,limit
resistor prevents excessive current flow out of the LM4250
,when the FET is fully turned on.
BIAS CURRENT SETTING PROCEDURE'
The single set resistor shown in Figure 3a offers the most'
straightforward method of biasing the LM4250. When the
set resistor is connected from Pin 8 to grollnd the resistance
value for a given set current is:
V+ -0.5
RSET=--ISET
,'.
FREQUENCY RESPONSE OF A
PROGRAMMABLE OP AMP
This section pr9Vides a method of determining the sine and
step voltage response of a programmable op amp. Both the
sine and step voltage responses of an amplifier are modified
when the rate of change of the output voltage reaches the
slew r~te Ii~it of the amplifier. The following analysis davel-
(3)
The 0.5 volts shown in Equation 3 is the voltage drop of the
master bias current diode connected transistor
on. the inte.
.
.
158
):.
ops the Bode plot as well as the small Signal and slew rate
limited responses of an amplifier to these two basic categories of waveforms.
SMALL SIGNAL SINE WAVE RESPONSE
The key to constructing the Bode plot for a programmable
op amp is to find the gain bandwidth product, GBWP, for a
given set currenl Quiescent power drain, input bias current,
or slew rate considerations usually dictate the desired set
current. The data sheat curve relating GBWP to set current
provides the value of GBWP which when divided by one
yields the unity gain crossover of fu. Assuming a set current
of 6 /l-A gives a GBWP of 200,000 Hz and therefore an fu of
200 kHz for the example shown in Figure 4. Since the device has a single dominant pole, the rolloff slope is - 20 dB
of gain per decade of frequency (-6 dB/octave). The dotted line shown on Figure 4 has this slope and passes
10
~- f _ ~BWP -t---i
,
'''-""111
40
I-_......_"'~.{'
"
/
,
z
:i
11,"'
SLOPE OF
-JOdBPER
DECADE OF FREQUENCY
10 kHz
100 kHz
(8)
S, = 2"IT fMAX Vp
(9)
Sr
fMAX = - (10)
2"ITVp
Figure 5 shows a quick reference graphical presentation of
this formula with the area below any Vpeak line representing
an undistorted small signal sine wave response for a given
frequency and amplifier slew rate and the area above the
Vpeak line representing a distorted sine wave response due
to slew rate limiting for a sine wave with the given Vpeak.
lOOk
o
I kHz
dVol
= 2"ITfV
dt t=o
p
The maximum sine wave frequency an amplifier with a given
slew rate will sustain without causing the output to take on a
triangular shape is therefore a function of the peak amplitude of the output and is expressed as:
'n~~~
100 Hz
(7)
S
.
dVo
r = maximum dt
GBWP' 200,000 Hz
10
dVo
T t = 2"IT fVp cos 2"IT ft
Vo = output voltage
Vp = peak output voltage
_!
I"A
(6)
where:
.------,r----.---.
ISET -
Vo = Vp sin2"ITft
rrm-rn~rn~OT~~~
~L~WRATE
I MHz
LIMITING
FREQUENCY
...,
.
.
TLiH/7382-7
;:
FIGURE 4. Bode Plot
through the 200 kHz fu point. Arbitrarily choosing an inverting amplifier with a closed loop gain magnitude of 50 determines the height of the 34 dB horizontal line shown in Figure 4. Graphically finding the intersection of the sloped line
and the horizontal line or mathematically dividing GBWP by
50 determines the 3 dB down frequency of 4 kHz for the
closed loop response of this amplifier configuration. Therefore, the amplifier will now apply a gain of -50 to all small
signal sine waves at frequencies up to 4 kHz. For frequencies above 4 kHz, the gain will be as shown on the sloped
portion of the Bode plot.
>-
C5
::0
10k
1111
11111
VPEAK ·,V
VPfAK "2vf.
VPEAK =4V
1k
V...K -BV
V... K -IIV
co
If
III
100
8M~~I~ SIGNI~L
10
.0001
_~E~~?IN~E lUI
.001
.01
0.1
1.0
10
REQUIRED MAXIMUM SLEW RATE "S;'iVl"sl
TLiH/7382-8
FIGURE 5. Frequency va Slew Rate Limit va Peak
Output Voltage
Large signal step voltage changes at the output will have a
rise time as shown in equation 5 until a signal with a rate of
output voltage change equal to the slew rate of the amplifier
occurs. At this point the output will become a ramp function
with a slope equal to Sr. This action occurs when:
SMALL SIGNAL STEP INPUT RESPONSE
The amplifier'S response to a positive step voltage change
at the input will be an exponentially rising waveform whose
rise time is a function of the closed loop 3 dB down bandwidth of the amplifier. The amplifier may be modeled as a
Single pole low pass filter followed by a gain of 50 wideband
amplifier. From basic filter theory', the 10% to 90% rise
time of a Single pole low pass filter is:
S s; VSlep
,
(ll)
tr
LOW PASS
FILTER RESPONSE
tr = 0.35
(5)
fSdS
For the example shown in Figure 4 the 4 kHz 3 dB down
frequency would give a rise time of 87.5 /l-s.
~
1.0 I+HP~i'tAN'I~rFVSTEP - 3ZV
VSTEp • 16V
VSTEp ·8V
~
0.1
"'~"
c
SLEW RATE LIMITED LARGE SIGNAL RESPONSE
0:
!
The final consideration, which determines the upper speed
limitation on the previous two types of Signal responses, is
the amplifier slew rate. The slew rate of an amplifier is the
maximum rate of change of the output signal which the amplifier is capable of delivering. In the case of sinosoidal signals, the maximum rate of change occurs at the zero crossing and may be derived as follows:
VSTEP =4V
VsTEp c 2V
VSTEP -IV
III
100
lDOD
10,800
I, ("sec) IO%TO IIt»\
TL/H17382-9
-See reference.
FIGURE 6. Slew Rate va Rlae TIme va Step Voltage
159
Z
•
.....
.-
....
r;-
z
c(
The 3 dB down (gain of -7.07) 'frequency observed for this
configuration was approximately 300 Hz which agrees fairly
closely with the 3.5 kHz GBWP divided by 10 taken from an
extrapolation of the data sheet typical GBWP versus ~t
current c u r v e . '
'
Figure 6 graphically expresses this formula and shows the
maximum amplitude of undistorted st!lP voltage for a given
slew rate and rise time. The area above each step voltage
line represents the undistorted low pass filter type response
mode of the amplifier. If the intersection of the rise time and
slew rate values of a particular amplifier configuration falls
below the expected step voltage amplitude line, the rise
lime will be determined by the slew rate of the amplifier. The
rise time will then be equal to the amplitude of the step
divided by the slew rate Sr.
Peak-to-peak output voltage swing into a 100 'kfi load is
0.7V" or ±0.,35V peak. An increase ,in supply voltage to
,;i: 1.35V such as deliVered by a pair of mercury cells directly
increases t~e output swing by ± 0.35V to 1.4V peak-topeak. Although this increases the power dissipation to ai>proxirnateiy 1 p,W per battery, power drain of 15 p,W,or
less ":,,i11 not affect the shelf life of a mercury cell.
a
FULL POWER BANDWIDTH
The full power bandwidth often found on amplifier specification sheets is the range of frequencies from zero to the
frequency found at the inte~ion on Figure 5 of the, mSllimum rated output voltage and the slew rate Sr of the amplifier. Mathematically this is:
"
'
Sr
ffullpower = - 2 - V
..
3.3M
+t.Ov
(12)
rated
The full power bandwidth of a programmable amplifier such
as the LM4250 varies with
the master bias set current., ,
,
The above analysis of sine wave and step voltage amplifier
responses applies for all single dominant pole op amps
such as the LM101A, LM1107, LM10SA, LM11?, LM11S,
and LM741 as well as the LM4250 programmable op amp.
500 MANO-WATTX10 AMPLIFIER
The X10 inverting amplifier shown in Figure 7demonstrates
the low power capability of the LM4250 at extremely low
values of supply, voltage and set current. The circuit draws
260 nA from the +,1.0V supply of which 50 nA flows
through the 12 'Mfi set resistor. The current into the -1.0V
supply is only 210 nA since the set resistor is tied to ground
rather than V~. Total quiescent power dissipation is:
Po = (260 nA)(1 V) + (210 nA)(1 vj
(13)
TUH/7382-10
FIGURE 7_ 500 nW x 10 Amplifier
MICRO-POWER MONITOR WITH HIGH CURRENT
SWITCH
(14)
Po = 470 nW
The slew rate determined,from the data sheet typical performance curve is 1 VIms for a .05 p,A set current. Samples
of actual values ol;>served were 1.2 V/ms for the negative
slew rate and 0.S5 V/ms for the positive slew rate. This
difference occurs due to the non-symmetry in, the, current
sources used for charging and disCl:larging the internal 30
pF compensation capacitor.
Figure 8 shows the combination of a micro-power comparator and a high current switch run from a separate supply.
This circ!!it provides a method of continuously monitoring an
input voltage while dissipating only 100 p.W of power and
still being capable of switching a 500 rnA load if the input
exceeds a given value. The reference voltage can be any
value between +S.5V and -S.5V. With a minimum gain of
approximately 100,000 the comparator can resolve input
voltage differences down into the 0.2 mV region.
V+
-IOV
-
,TUHI7382-11, '
FIGURE 8. p,-Power Comparator with
High Current SWitch
160
The bias current for the LM4250 shown in Figure 8 is set at
0.44 /LA by the 200 MO ASe! resistor. This results in a total
comparator power drain of 100 /LW and a slew rate of approximately 11 V Ims in the positive direction and 12.8 V Ims
in the negative direction. Potentiometer A, provides input
offset nulling capability for high accuracy applications.
When the input voltage is less than the reference voltage,
the output of the LM4250 is at approximately - 9.5V causing diode 0, to conduct. The gate of 0, is held at - 8.8V by
the voltage developed across A3. With a large negative voltage on the gate of 0, it turns off and removes the base
drive from 02. This results in a high voltage or open switch
condition at the collector of 02. When the input voltage exceeds the reference voltage, the LM4250 output goes to
+ 9.SV causing 0, to be reverse biased. 0, turns on as
does 02, and the collector of 02 drops to approximately 1V
while sinking the 500 mA of load current.
The load denoted as ZL can be resistor, relay coil, or indicator lamp as required; but the load current should not exceed
SOO mA. For V+ values of less than 15V and IL values of
less than 2S mA both 02 and A2 may be omitted. With only
the 2N4860 JFET as an output device the circuit is still capable of driving most common types of indicator lamps.
THE COMPLETE NANOAMMETER
The complete meter amplifier shown in Figure 10 is a differential current-to-voltage converter with input protection, zeroing and full scale adjust provisions, and input resistor balanCing for minimum offset voltage. Aesistor R'f (equal in
value to Af for measurements of less than 1 /LA) insures
that the input bias currents for the two input terminals of the
amplifier do not contribute significantly to an output error
voltage. The output voltage Vo for the differential current-tovoltage converter is equal to - 2 IfAf since the floating input
current liN must flow through Af and A'f. R'f may be omitted
R,
+I.SV
IN.,.
Rj
Ie METER AMPLIFIEA AUNS ON TWO FLASHLIGHT
BATIERIES
Meter amplifiers normally require one or two 9V transistor
batteries. Oue to the heavy current drain on these supplies,
the meters must be switched to the OFF position when not
in use. The meter circuit described here operates on two
1.5V flashlight batteries and has a quiescent power drain so
low that no ON-OFF switch is needed. A pair of Eveready
No. 950 "0" cells will serve for a minimum of one year
without replacement. As a DC ammeter, the circuit will provide current ranges as low as 100 nA full-scale.
TUH17382-13
+1.5V
0
1
., ":'1.5V
I
The basic meter amplifier circuit shown in Figure 9 is a current-ta-voltage converter. Negative feedback around the
amplifier insures that currents liN and If are always equal,
and the high gain of the op amp insures that the input voltage between Pins 2 and 3 is in the microvolt region. Output
POWER
SUPPLY
TL/H17382-14
FIGURE 10. Complete Meter Amplifier
- "R ,
Resistance Values for
DC Nano and Micro Ammeter
+1.5V
I FULL SCALE
Af[n]
R'Hn]
100nA
SOOnA
lp.A
5/LA
10/LA
50 p.A
100 p.A
1.5M
300k
300k
60k
30k
6k
3k
I.SM
300k
0
0
0
0
0
for Af values of 500 kO or less, since a resistance of this
value contributes an error of less than 0.1 % in output voltage. Potentiometer A2 provides an electrical meter zero by
forcing the input offset voltage Vos to zero. Full scale meter
deflection is set by A,. Both R, and A2 only need to be set
once for each op amp and meter combination. For a 50
microamp 2 kO meter movement, A, should be about 4 kO
to give full scale meter deflection in response to a 300 mV
output voltage. Oiodes 0, and 02 provide full input protection for overcurrents up to 75 mAo
-1.5V
TUHI7382-12
FIGURE 9. Basic Meter Amplifier
voltage Vo is therefore equal to -lfAf. Considering the
± 1.5V sources (± 1.2V end-of-life) a practical value of Vo
for full scale meter deflection is 300 mV. With the master
bias-current setting resistor (RS> set at 10 MO, the total quiescent current drain of the circuit is 0.6 /LA for a total power
supply drain of 1.8 /LW. The input bias current, required by
the amplifier at this low level of quiescent current, is in the
range of 600 pA.
With an Af resistor value of I.SM the circuit in Figure 10
becomes a nanommeter with a full scale reading capability
161
of 100 nA. Reducing Rf to 3 kO- in steps, as shown in Figuf'8
10 increases the full scale deflection to 100 lJA,the maxi·
mum for this circuit configuration. The voltage drop across
the two input terminals is equal to the output voltage Vo
divided by the open loop gain. Assuming an open loop gain
of 10,000 gives an input voltage drop of 30 p.V or less.
A 10 mV TO 100V FULL-SCALE VOLTMETER
A resistor inserted in series with one of the input leads of
the basic meter amplifier converts'it to Ii wide range voltme-'
ter circuit, as shown in F/gUf'8 12. This inverting amplifier has,
a gain varying from ':'30 for the 10 mV full scale range to
- 0.003 for the 1OOV full scale range. Figuf'8 12 also lists
the proper values of Rv, R" and R', for each' range. Diode!!
01 and 02 provide complete amplifier protection for input
overvoltages as high as 500V on the 10 mV range, but if
overvoltages of this magnitude are expected under continuous operation, the power rating of Rv should be adjusted
accordingly.
'
CIRCUIT FOR HIGHER CURRENT READINGS
For bC,current readings higher than 100 p.A, the inverting
amplifier configuration shown in Figuf'8 11 provides the required gain. Resistor RA develops a voltage drop in response to input current IA. This voltage is amplified by a
factor equal to the ratio of Rf/Re. Re must be sufficiently
larger than RA, so as not to load the input signal. Figuf'8 11
also shows the proper values of RA, Rs and Rf for full scale
meter deflections of from 1 rnA to 1OA.
Resistance Values for a DC Voltmeter
Resistance Values for DC Ammeter
V FULL SCALE
Rv[O]
Rf[O]
R'f[O]
10mV
100mV
100k
1M
10M
10M
10M
1.5M
1.5M
1.M
300k
30k
1.5M
1.5M
I FULL SCALE
RA[O]
Ra[O]
Rf[O]
1V
1 mA
10mA
100mA
1A
10A
3.0
.3
.3
.03
.03
3k
3k
30k
30k
30k
300k
300k
300k
300k
30k
10V
100V
R,
0
0
R,
+
+I.IV
!IA
1~5M
+I.5V
Rv
R.
+
01
RA
Ri
VOLTMETER
TLlHI7382-18
TLlH/7382-15
FIGURE 12. Voltmeter
FIGURE 11. Ammeter
162
01
,~
Rl
41K
, .....
....
+5V,
Vo
JLJl
R3
1M V.
+5V o-JtJI/Ir..:.e~
CI
~.OOI"F
":'
R5
2M
R4
1M
TL/HI7382-17
FIGURE 13. Pulse Generator
The output buffer 0, presents a constant load to the op
amp output thereby preventing frequency variations caused
by VHIGH and VLOW voltages changing as a function of load
current. The output of 0, will interface directly with a standard TTL or DTL ,ogic device. Reversing diode 01 will invert
the polarity of the generator output providing a series of
negative going pulses dropping from + 5V to the saturation
voltage of 0,.
LOW FREQUENCY PULSE GENERATOR USING A
SINGLE + 5V SUPPLY
The variable frequency pulse generator shown in Figure 13
provides an example of the LM4250 operated from a single
supply. The circuit is a buffered oUtput free running multivibrator with a constant width output' pulse occurring with a
frequency determined by potentiometer R2.
The LM4250 acts as a comparator for the voltages found at
the upper plate of capacitor C, and at the reference point
denoted as Vr on F/{Jure 13. Capacitor C, charges and discharges with a peak-to-peak amplitude of approximately 1V
determined by the shift in reference voltage Vr at Pin 3 of
the op amp. The charge path of C, is from the amplifier
output. whicl) is at its maximum positive voltage VHIGH (apprOximately V+ -0.5V). through R, and through the potentiometer R2. Diode D, is reverse biued during the charge
period. When C, charges to the Vr value determined by the
net result of ,VHIGH through resistor R5 and V+ through the
voltage dividElr made up of resistors R3 and R4 the amplifier
swings to its lOWer limit of apprOximately 0.5V causing C, to
begin discharging. The discharge path is through the forward biased diode D,. through resistor R,. and into Pin 6 of
the op amp. Since the impedance' in the discharge path
does not vary for ,R2 settings of from 3 kO to 5 MO. the
output pulse maintains a constant pulse width of 41 ,...s
± 1.5 ,...s over this range of potentiometer settings. Figure
14 shows, the output pulse frequency variation from 6 kHz
down to 360 Hz as R2 places from 100 kO up to 5 MO of
additional resistance ,in the charge path of C,. Setting R2 to
zero olims will short out diode D, and cause a symmetrical
square wave output ata frequency of 10kHz. 'Increasing the
value of C, will lower the range of frequencies available in
response to the R2 variation shown on Figure 14. Electrolytic capacitors may be used for the larger values of C, since it
has only positive voltages applied to it.
1.,000
i>
"
u
; 1,0110
c:o
...
...
II:
ioo
lOOk
1M
1M
R2ln's,
TL/HI7382-18
FIGURE 14. Pulse Frequency VB R2
The change in output frequency as a function of supply voltage is less than ±4% for a V+ change of 'from 4V:to 10V.
This stability of frequency versus supply voltage is due to
the fact that the reference voltage Vr and the drive voltage
for the capacitor are both direct functions of V + .
The power dissipation of the free, running multivibrator' is
300 ,...W 'and the power dissipation of the buffer circuit is
approximately 5.8 mW.
163
.- r-------------------------------------------------------------------------------------,
~
cc
+UV
8
RZ
10M
RS
10lIl
Re
1M
R8
1~
RU
R7
10lIl
1M
-1.SV
R3
10M
N!Ibt I: Quiescent Po = 10 jJ.W
Note 2: R2, R3, R4, RS, R6 and R7
1 % r8sist0rs
Nol\I 3: Rll and 01 are for
and AC CQmm~n moda rejection adlualmanis
oC
are
-I.SV
TL/H/7382-19
FIGURE 15. X 100 Instrumelltatlon Amplifier
Xl00 INSTRUMENTATION AMPLIFIER
100
The instrumentation amplifier circuit shown in FIgure 15 has
a full differential input center tapped to ground. With the
bias current set at approximately 0.1 pA. the impedance
looking into either VIN1 or V1N2 is 100 Mfi with respect to
ground. and the input bias current at either terminal is 0.2
nA. The two non-Inverting input stages A, and A2 apply a
gain of 10 to the input signal. and the differential output
stage applies an additional gain of -10 for a net amplifier
gain of -100:
80
ii
:!!
II:
..
II:
80
i!I
~
l
Vo = -100(VIN, - VINV.
(15)
The entire circuit can run from two 1.5V batteries connected
directly (no power switch) to the V+ and V- terminals. Witi1
a total current drain of 2.8 pA the quiescent power dissipation olthe circuit is 8.4 pW. This is low enough to have no
significant effect on the shelf life of most batteries.
40
·1111111 I
II~R~
It
~
~
ZO
10
100
1,000
10,000
FREQUENCV (Hz)
TLlHI7382-20
FIGURI;:
16. Avand CMRR vs Frequency
is the difference between the CMRR curve and Av curve.
For example. a 6Q Hz common mode Signal will be attenuated by 67 dB minus 40 db or 27 dB for an actual rejection
ratio of VINIVO equal to ~.4.
..
.
Potentiometer'R" provides a means for matching the gains
of A, and A2 to achieve maximum DC common mode rejection ratio CMRR. With R'l adjusted to Its null point for DC
common mode rejection the small AC CMRR trimmer capacitor C, will normally give an additional 10 to 20 dB ·of
CMRR over the operating frequency range. Since Cl actually balances wiring capacitance rather than amplifier frequency characteristics. it may be necessary to attach it to
Pin 2 of either A1 or A2 as required. Agure 16 shows the
variation of CMRR (referred to the input) with frequency for
this configuration. Since the circuit applies a gain of 100 or
40 dB to an input signal. the actual observed rejection ratio
The maximum peak-to-peak output Signal into a 100 kfi
load resistor is approximately 1;8V. With no input signal. the
noise seen at the output isepproximately 0.8 mVRMS or
8 "VRMS referred to the input. When dOing power dissipation measurements on this circuit. it should be kept in mind
that even a 1 Mfi oscilloscope probe placed between
+ 1.5V and -1.5V will more than double the power drawn
from the batteries.
164
5V REGULATOR FOR CMOS LOGIC CIRCUITS
The ideal regulator for low power CMOS logic elements
should dissipate essentially no power when the CMOS devices are running at low frequencies, but be capable of delivering full output power on demand when the CMOS devices are running in the 0.1 MHz to 10 MHz region. With a 10V
input voltage, the regulator shown in Fl{/UfS 17will dissipate
350 p.W in the stand-by mode but will deliver up to 50 rnA of
continuous load current when required.
The circuit is basically a boosted output voltage-follower referencad to a low current zener diode. The voltage divider
consisting of R2 and R3 provides a 5V tap voltage from the
6.5V referenca diode to determine the regulator output
Sinca a standard 6.5V zener diode does not exhibit good
regulation in the 2 p.A to 60 p.A reverse current region, 02
must be a special devica. An NPN transistor with its collector and base terminals grounded and its emitter tied to the
junction of RI and R2 exhibits a well-controlled base emitter
reverse breakdown voltage. A National Semiconductor process 25 small signal NPN transistor sorted to a
2N registration such as 2N3252 has a BVEBO at 10 IJ.A
specified as 5.5V minimum, 6.5V typical, and 7.0V maximum. USing a diode connected 2N3252 as a reference, the
regulator output voltage changed 78 mV in response to an
8V to 36V change in the input voltage. This test was done
under both no load and full load conditions and represents a
line regulation of better than 1.6%.
A load change from 10 p.A to 50 rnA caused a 1 mV change
. in output voltage giving a load regulation value of 0.05%.
When operating the regulator at load currents of less than
25 mA, no heat sink is required for 01. For load currents in
excess of 50 mA, 01 should be replaced by a Darlington
pair with the 2N3019 acting as a driver for a higher power
device such as a 2N3054.
REFERENCES
·Millman, J. and Halkias, C.C.: "Electronic Device and Circuits," pp. 465-466, McGraw-Hili Book Company, New
York,1967.
IV -3IV
ON HEAl SINK
v,N 0 - - -. .- - - - - -...- _
1,,--,,--,,-o~:mA
RI
510K
R.
S10K
&1
a.l.F
02"
i.5V
R3
111M
.GNOo-~----~~--~~--~----------~t---~~
"SEElUl
TlIHI7382-21
FIGURE 17.350 p.W Quleacent Drain 5 Volt Regulator
165
~,
::i•
'T'h
"LM3'900"
"e"
, :"A ' N
ew'" " :, "
,,',
,i.
NationalSemicondl.ictor' ,
Application Note 72
t
Cur~.~t-Diff~renc.:ir:'lg'Quad '
of :,' tl:1put ~mpli,f,ler!~
i'
'./
.
""
"~
',:,~
:
"
",'
? I '
,,',','.' ."',
!1
,"'",
"", :,.
'""
,
;-":"1
, PREFACE'
'
"
.,','
:
"
'" ,,',
Witll all the existing ,literature'~n "t\~wto appiy op amps~' ,why, should another application note be produced on this subjed1'
There:are two'alJswe,OI to this question'; ,1) the LM3900 op8r~,es in quite an unu$ualmann$r(comPared to a'c6nventional op' , , ;
amp) ,a/:lp therefore ne,~!1 ~/T1e 'exPlanatior:,'to f~mil~rizea new user with' tHi~ pi-oduct,and2)thEi staodal'd oP amp""
applications assume a split power '~uppl~ (± '15VDcli,sa,vailable and ciur emphasis'hEire' is direqtedto..v8rd circuits for lower:'"
cost single poWer supply Control ~enis. Some of these cirt;ults are sin\~ "rEl-bi~d" versions of coi'liientlonal handbOok
circuits but many are new approaches which' are made possible by sO(ne ,of the unique featureS of the LM390'O.',' ," '
~,~.
:
-
'"
.'~.
,
,,':,
1.0 AN INTRODUCTION
AMPLIFIER
TO THE NEW "NORTON"
7.0 DESIGNING WAVEFORM'OENEAAtORS (COntlriued)
7.3 Puls~ ~enerat()~,'
,
1.1 Basic Gain Stage
1.2 Obtaining a Non·inverting Input Function
1.3 The Complete Single-Supply Amplifier
7.4 Triangle Waveform Generator
7.5 Sawtooth Waveform Generator
7.5.1 Generating a Very Slow Sawtooth Waveform
,
2.0 INTRODUCTION TO APPLICATIONS
OF THE LM39QP
,
7.6 Staircase Waveform Generators
7.7 A Pulse Counter and a VC!ltage Variable
Pulse Counter
'" ..
7.8 An Up-down Stair~,;Nav~orm Generator
3.0 DESIGNING AC AMPLIFIERS:,
3.1 Single Power Supply Biasing
3.2 A Non-inverting Amplifier
3.3 "N VeE" Biasing
3.4 Biasing Using a Negative Supply
3.5 Obtaining High Input Impedatrlce and High Gain'
3.6 An Amplifier with a DC Gain,q
!
~
5•
~!
;~
'0
ii
~
I
i
u
;.
:!
I.
II
i
uj
III
II:
:::I
!
~
iii
I'
I'
i~
I'
I.
."
CN
iii
173
be analyzed. Figure 9b shows the complete equivalent circuit which, for convenience, can be separated into a biasing
equivalent circuit (FtgUre 10) and an AC equivalent circuit
(Figure 11). From the biasing model of Figure 10 we find the
output quiescent voltage, Vo, is: '
Vo = Vo- + (IB +1+) R2,
(1)
and
-why external voltages must be first converted to currents
(using resistors) before being applied to the inputs-and is
the basis for the current-mode (or Norton) type of operation.
With external input resistors-there is no limit to the "input
common-mode voltage range". The diode shown across the
( +) input actually exists as a diode in the circuit and the
diode across the (-) input is used to model the base-emitter junction of the transistor which exists-at this input.
Only the (-) input must be, supplied with a DC biasing cur-,
rent, lB. The (+) input couples only to the (-) input and
then to extract from this (-) input terminal the same current
(AI, the mirror gain, is approximately equal to 1) which is
entered (by the external circuitry) into the'( + ) input terminal.
This operation is described as a "current-mirror" as the current entering the (+) input is "mirrored" or "reflected"
about ground and is then extracted from, the ( - ) input.
There is a maximum or near saturation value of current
which the "mirror" at the ( + ) input can handle. This is listed
on the data sheet as "maximum mirror current" and ranges
from approximately 6 mA at 25"C to 3.8 mA at 7CrC.
This fact that the (+ ) input current modulates or affects the
(-) input current causes this amplifier to pass currents between the input terminals and is the basis for many new
application circuits-e8pecially when operating with only a
single power supply voltage.
The output is modeled as an active voltage source which
also depends upon the open-loop v,oltage Q8in, Av, but only
the (-) input voltage, V-, (not the differential input voltage). Finally, the output voltage of the LM3900 can swing
from essentially ground (+ 90 mV) to within one VBe of the
power supply voltage.
As an example of the use of the equivalent circuit of the
LM3900, the AC coupled inverting amplifier of FtgUre 9s will
o _+
1+ = -,-V_+-:':"'"....;.V:::c
R3
(2)
where
Vo+ ... Vo- "" 0.5Voc
IB' = INPUT bias current (30 nA)
and
V+ = Powersupplyvoltage.
If (2) is substituted into (1)
°
V+ -V +)
Vo = Vo- + ( IB, + ' :Ra
R2
(3)
which is an exact expression for Vo.
As the second term usually dominates (VO :> Vo-) and 1+
:> IB and V+ :> Vo + we can simplify (3) to provide a more
useful design relationship
R2
Vo "" R3 V+.
(4)
Using (4), if R3 = 2R2 W!il find
R2
V+
Vo .. 2R2 V+ = 2'
(5)
which shows that the output is easily biased to one-half of
the power supply voltage by using V+ as a biasing reference at the (+) input
R2
Tl/H/7383-1,O
(a) ATypical
TlIHI7383-12
BiaSed Amplifier
FIGURE 10_ Blallng Equivalent Circuit
HZ
R2
Y+~
Tl/H/7383-13
FIGURE 11. AC Equivalent Circuit
VD+_f
TLlH/738S-11',
(b) Using the LM3900 Equivalent Circutt
FIGURE 9. Applying the LM3900 Equivalent Circuit
174
r--------------------------------------------------------------------,>
The AC equivalent circuit of Figure 11 is the same as that
which would result if a standard IC op amp were used with
the (+ ) input grounded. The closed-loop voltage gain Avcl'
is given by:
Vo
R2
Av =-"'-Cl - VIN
Rl
if Av (open-loop) >
3.2 A NON-INVERTING AMPLIFIER
The amplifier in F/{/ure 13 shows both a non-inverting AC
amplifier and a second method for DC biasing. Once again
the AC gain of the amplifier is set by the ratio of feedback
resistor to input resistor. The small signal impedance of the
diode at the (+) input should be added to the value of Rl
when calculating gain. as shown in F/{/ure 13.
(6)
~~ .
H3
1M
The design procedure for an AC coupled inverting amplifier
using the LM3900 is therefore to first select Rl. CIN. R2. and
Co as with a standard IC op amp and then to simply add Rs
= 2R2 as a final biasing consideration. Other biasing techniques are presented in the following sections of this note.
For the switching circuit applications. the biasing model of
Figure 10 is adequate to predict circuit operation.
Although the LM3900 has four independent amplifiers. the
use of the label "Y4LM3900" will be shortened to simply
"LM3900" for the application drawings contained in this
note..
,.
C
~,.I -
HI
IOIK
I. =D
I.'
51K
If'
CT
3.0 Designing AC Amplifiers
TO OTHER
AMPLIFIERi
VRIF
R3
Ay = RI + rd
51K
rd=~n
":"
The LM3900 readily lends itself to use as an AC amplifier
because the output can be biased to any desired DC level
within the range of the output voltage swing and the AC gain
is independent of the biasing network. In addition. the single
power supply requirement makes the LM3900 attractive for
any low frequency gain application. For lowest noise performance. the (+ ) input should be grounded (Figure 9a) and
the output will then bias at + VBE. Although the LM3900 is
not suitable as an ultra low noise tape pre-amp. it is useful in
most other applications. The restriction to only shunt feedback causes a small input impedance. Transducers which
can be loaded can operate with this low input impedance.
The noise degradation which would result from the use of a
large input resistor limits the usefulness where low noise
and high input impedance are both required.
1
RZ
1M
12
v+
vOOC=T
TUH/7383-15
FIGURE 13. Non-Inverting AC Amplifier
Using Voltage Reference Biasing
By making R2 = Rs. VODC will be equal to the reference
voltage which is applied to the resistor R2. The filtered
V+ 12 reference shown can also be used for other amplifiers.
3.3 UN VBE" BIASING
A third technique of output DC biasing is best described as
the "N VBE" method. This technique is shown in Figure 14
and is most useful with inverting AC amplifier applications.
R2
3.1 SINGLE POWER SUPPLY BIASING
The LM3900 can be biased in several different ways. The
circuit in F/{/ure 12 is a standard inverting AC amplifier which
has been biased from the same power supply which is used
to operate the amplifier. (The design of this amplifier has
been presented in the previous section). Notice that if AC
ripple voltages are present on the V+ power supply line
they will couple to the output with a "gain" of %. To eliminate this. one source of ripple filtered voltage can be provided and then used for many amplifiers. This Is shown in the
next section.
10M
HI
1M
f-
R2
V..
Vo
l'
R3
I18K
":"
Vee = O.5Vce
Voce = VBE ( 1 + ~)
":"
Av" -~
RI
TUH/7383-16
1M
FIGURE 14. Inverting AC Amplifier Using N VBE Biasing
The input bias voltage (VBE) at the inverting input establishes a current through resistor Rs to ground. This current
must come from the output of the amplifier. Therefore. Vo
must rise to a level which will cause this current to flow
through R2. The bias voltage. VOl may be calculated from
the ratio of R2 to Rs as follows:
Vo
v+
voce=T
Ay"
_&
Voce = VBE
Rl
(1 + ::)
When NVBE biasing Is employed. values for resistors R,
and R2 are first established and then resistor Rs is added to
provide the desired DC output voltage.
TL/HI73B3-14
FIGURE 12. Inverting AC Amplifier
Using Single-Supply Biasing
175
~
N
W
~
i
r-----------------------------------------------------------------------,
point A isunity~R1';= Rs}. the Av of the complete stage win
be,set by the voltage. divider network composed of,fl4'o·R5.
and C2. As th,e value of Rs is decreased.< the Avof the stage
will approach the AC open loop limit of the amplifier. The
insertion of capacitor C2 allows the DC bias to be controlled
bYithe series combination o(Rs and R4 with no effect from
R5. Therefore. R2 may be selected to obtain the desired
output DC biasing level using any of the methqQ~ ,~hicl)
have been discussed. The circuit In Figure 16 has an input
impedal1ce of 1M and a gain oUOO,
For a design example (Figure 1'4). Ii Z in#" 1M'nAy '"' 10
are required.
SeI~R1
= 1M"
Calculate 1'12 "" A.,A1 = 10M.
To bias the output'vOltage at 7.5 Voc.Ra is'f6iJnd as:
,
":
\.
,
R2'
\
'
10M
R s = - - - = - - - ' ..
Vo -1
7.5 _ 1
vBE
0.5
or
3.6 AN' AMPLIFIER WITH A
RS "" 680kO.
3.4 BI~SING USING A NEGATIVE SUPPLY
is
If a negative power supply is available. the circuit of Figure
15 can be used. The DO bi/iSing current. I. is established by
the negative supply vclltage via Rs and provides' a very $table output quiescant point for the amplifier.
..
v.
A.
DCGAI~,CONTROL:
A DC galn control can be added to an amplifier as shown in
t;igure . 17: The out~ut of the amplif!er, i" kept fro!'"' being
qriVen to, saturation asthe DC.gain control vl\ried by providing a minimum I;>iasjng cur,rent )/ia A3" For in8l!imum gain.
CR2 is OFF and both the currentthr~ugh ~ an~ As e~ter
the (+ ) 'input and cause the output of ttle amplifier to bias at
apprOXimately 0.6 V +. For minimom galn. tR~ is ON lind
only the corrent through' As enterS the (+ ) 'input to bias the
output at approximately 0.3 V +. The proper output bias for
large output signal accommodation is provided for .the. m!OO7
mum galn situation. The DC gain control input ranges
Voc for minimum gain to less than 10 Voc for maximum
galn.
from
o
AV'"'
..
-~
A1
"TUHI7383-17
1.111'
FIGURE 15. Negative Supply Biasing
3.5 OBTAINING HIGH INPUT IMPEDANCE
AND HIGH 'GAIN
.
..
VA
va
= 100
Av= -~
AS
-
R3"
..,_
1:111
For the AC amplifiers which have been presented. a designer is able to obtain either high gain or high input impedance
with very little difficulty. The application which requires both
and still employs ,only one amplifier presents a new problem.,This can be achieved by the ~e of a circuitsimilar to
th~ one shown in Figllre 16. When the A., from the input to
1M
AZ
~111
,\
.
DC lAIN
CONT1IOL
(I-+1IVoc)
1M
I,
" TlIH/73B3-19
FIGURE,17. An, Amplifier wHh a DC Gain Control
Va = VREF
3.7 A LINE-RECEIVER AMPLIFIER'
use.
The line-receil(er amplifier is stJoWn in Figu/'fJ
Th~
of
both inputs cancels out e,ommon-mode signals. ,The line is
terminated by RLINE and the I~r,. input impedance of the
amplifier will not affect U1,is ma~hed loading.
18.
CI'
Al .
1••
"'
2M
. TlIHI7383-18
FIGURE 16. A HlghZIN High Gain Inverting AC Amplifier
TUHI7383-20
FIGURE 18. A Line-receiver Amplifier
176
Because the current mirror demands that the two current
sources be equal, the current in the two equivalent resistors
must be identical.
4.0 Designing DC Amplifiers
The design of DC amplifiers using the LM3900 tends to be
more difficult than the design of AC amplifiers. These difficulties occur when designing a DC amplifier which will operate from only a single power supply voltage and yet provide
an output voltage which goes to zero volts DC and also will
accept Input voltages of zero volts DC. To accomplish this,
the inputs must be biased into the linear region ( + VeE> with
DC input signals of zero volts and the output must be modified if operation to actual ground (and not VSAT) is required.
Therefore, the problem becomes one of determining what
type of network is necessary to provide an output voltage
(Vo) equal to zero when the input voltage (VIN) is equal to
zero. (See also section 10.15, "adding a Differential Input
Stage").
We will start with a careful evaluation of what actually takes
place at the amplifier inputs. The mirror circuit demands that
the current flOwing into the positive input ( + ) be equaled by
a current flowing into the negative input (-). The difference
between the current demanded and the current provided by
an external source must flow in the feedback circuit. The
output voltage is then forced to seek the level required to
cause this amount of current to flow. If, in the steady state
condition Vo = VIN = 0, the amplifier will operate in the
desired manner. This condition can be established by the
use of. common-mode biasing at the inputs.
R3 = R4
1+
1M
D.&V
D.&V
...
",",Z
TLlHI7363-22
FIGURE 20. An Ideal Circuit Model of a DC Amplifier
with Zero Input Voltage
If this is true, both R2 and R6 must have a voltage 'drop of
0.5 volt across them, which forces Vo to go to Vo MIN
(VSAT)·
4.2 ADDING AN OUTPUT DIODE FOR Vo = 0 VDC
For many applications a Vo MIN Of 100 mV may not be
acceptable. To overcome this problem a diode can be added between the output of the amplifier and the output terminal (Figure 21).
v'
OFFSET AO~
4.1 USING COMMON-MODE BIASING
FOR VIN = 0 VDC
Common-mode biasing is achieved by placing equal resistors between the amplifier input terminals and the supply
voltage (V+), as shown in Agure 19. When VIlli is set to 0
volts the circuit can be modeled as shown in Figure 20,
,
= 1-
Reql=Req2
R3
RI
ZiIIK
HZ
1.5M
R3
1M
UM
1M
H5
IIIK
CRI
y+
"::"
Vo ow VIN
Av=~
Rl
H8
lOOK
R3
HI
Av
1M
= 10
.
vol
11K
RZ
+V,.
"::"
'"::"
Tl/HI7363-23
I
I
.1
VIN
FIGURE 21. A Non-Inverting DC Amplifier with Zero
Volts Output for Zero Volts Input
The function of the diode is to provide a DC level shift which
will allow Vo to go to ground. With a load impedance (RLl
connected, Vo becomes a function of the voltage divider
formed by the series connection of R4 and RL.
.
0.5RL
If R4 = 100 RL, then Vo MIN = 101 RL'
-n,!..
R5
~
Rl = R2
R3 = R4
R5 = RS
RL
I
"::"
i
orVOMIN "" 5mVec·
An offset voltage adjustment can be added as shown (Rl)
to adjust Vo to OVec with VIN = 0 Voc.
The voltage transfer functions for the circuit in Figure 21,
both with and without the diode, are shown in Figure 22.
While the diode greatly improves the operation around 0
volts, the voltage drop across the diode will reduce the peak
output voltage swing of the state by approximately 0.5 volt.
When using a DC amplifier similar to' the one in Figure 21,
the load impedance should be large enough to avoid excessively loading the amplifief. The value of RL may be significantly reduced by replacing the diode with an NPN transistor.
TUH17383-21
FIGURE 19. A DC Amplifier Employing
Common-mode BIasing
where:
II R5,
R211 Rs,
REQI = Rl
RE~ =
and
177
...
2l1li
i
oJ
••
•
11
0
where
~ == VBEat either input terminal of the LM3900.,
Since the input current mirror demands that
1-= 1+;
TlIH/7383-24
and
1+ = 11 -12
and
1- = I~ + 14
Tl'lerefore
14 = 11 - 12 - 13·
Substituting in from the above equation
Vo - ~
(Vl'+ VA ,... ~)
(~), (V1 ,-.~)
~=
R1
-R2-~
FIGURE 22. Voltage Transfer Function for a DC
Amplifier with a Voltage Gain of 10
4.3 A DC COUPLED POWER AMPLIFIER (lL S; 3 AMPS)
The LM3900 may be used as a, power amplifier by the addition of a Darlington pair at the output. The circuit shown in
FlfJuie 23 can deliver in excess of 3 amps to the load when
the transistors are properly mounted on heat sinks.
anduRl "" Ri = Rs= R4
Vo = (Vl + VA - ~) or
v'
•
VON
1
....
C2
L-----'lM_---~~v.
""
",
TlIHI73B3-25
FIGURE 23. A DC Power AmplifIer
4.4 GROUND REFERENCING A DIFFERENTIAL
VOLTAGE
The circuit in Figure 24 employs the LM3900 to ground reference' a DC differential input voltage. Current 11 is larger
.,
••
'OM
, v. o---;.~IY-....,
V,
t
R:'
1"
+ ~ + ~::
I.IM
I
I
Vl
Vo = VA·
The resistors are kept large to minimize loading: With the
1(\ MO reslsto~ which are shown on the figure, an error
exists at smallva,lues of Vl due to the input bias current at
the (-) input. For simplicity this has been neglected in the
circuit description. Smaller R valu. reduce the percentage
error or the bias current can be supplied, by an IIdditional
amplifier (see Section 10.7.1).
For proper operation, the differential input voltage must be
limited to be within the output dynamiC voltage range of the
amplifier and the input voltage V2 must be greater than 1
volt. For example; if V2 = 1 volt, the input voltage Vl may
vary over the range of 1 volt to -13 volts when operating
from a 15 volt supply. Common-mode biasing may be added
as shown in Figure 25 to allow both Vl and V2 to be negative.
".
1l1li1
.M
(~) T
,
v,
c••
,.,.
••
• OM
.7 ..
HI
.8M
v,6--..,."...-.---.r
R4
t
'.,
I
..
TLlHI73B3-27
FIGURE 25. A Network to Invert and to Ground
Reference a Negative DC DlfferanUallnput Voltage
'IK
4.5 A UNITY GAIN BUFFER AMPLIFIER
The buffer amplifier with a gain of one is the simplest DC
application for the LM3900. The voltage applied to the input
(FIgure 26) will be reproduced at the output. However, the
input voltage must be greater than one VBe but less than
the maximum output swing. Common-mode biasing can be
added to extend VIN to 0 Voc, if desired.
TL/HI7383_26
FIGURE 24. Gr9undReferencinga Dlfferen.1aI
Input DC Voltage
than current 13 by a factor pr.oportional to the differential
voltage, VA. The currents labeled on FlfJure 24 are given by:
11
= Vl
+ VA -
~
Rl
178
.--------------------------------------------------------------------..
~
R
1M
N
>-..-ovo
R
1M
TL/H/7383-28
vo ~ vz +.,.
FIGURE 26. A Unlty-galn DC Buffer Amplifier
TLlHI7383-29
5.0 Designing Voltage Regulators
(a) Basic Current
Many voltage regulators can be designed which make use
of the basic amplifier of the LM3900. The simplest is shown
in Figure 27s where only a Zener diode and a resistor are
added. The voltage at the H input (one VeE "" 0.5 Vocl
appears across R and therefore a resistor value of 51 on will
cause approximately 1 mA of bias current to be drawn
through the Zener. This biasing is used to reduce the noise
output of the Zener as the 30 nA input current is too small
for proper Zener biasing. To compensate for a positive temperature coefficient of the Zener, an additional resistor cen
be added, R2, (F/{/Ure 27b) to introduce an arbitrary number,
N, of "effective" VeE drops into the expression for the output voltage. The negative temperature coefficient of these
diodes will' also be added to temperature compensate the
DC output voltage. For a larger output current, an emitter
follower (Ql of F/(/ure 270) cen be added. This will multiply
the 10 mA (max.) output current of the LM3900 by the p of
the added transistor. For example, a p = 30 will provide a
max. load current of 300 mAo This added transistor also
reduces the output impedance. An output frequency compensation capacitor is generally not required but may be
added, if desired, to reduce the output impedance at high
frequencies.
I
>-,,-oVo
~.!l
HI
TLlHI738S-S0
(b) Temperature Compensating
The DC output voltage can be increased and still preserve
the temperature compensation of Figure 27b by adding resistors RA and Re as shown in F/(/ure 27d. This also can be
accomplished without the added transistor, Ql. The unregulated input voltage, which is applied to pin 14 of the LM3900
(and to the collector of Ql, if used) must always exceed the
regulated DC output voltage by approximately 1V, when the
unit is not current boosted or approximately 2V when the
NPN current. boosting transistor is added.
TL/HI7383-S1
(e) Current Boosting
5.1 REDUCING THE INPUT-OUTPUT VOLTAGE
The use of an extamaJ PNP transistor will reduce the required (VIN - VOUT) to a few tenths of a volt. This will
depend on the saturation characteristiCS of the extamal
transistor at the operating current level. The circuit, shown
in Figure 28, uses the LM3900 to supply base drive to the
PNP transistor. The resistors Rl and R2 are used to allow
the output of the amplifier to turn OFF the PNP transistor. It
is important that pin 14 of the LM3900 be tied to the + VIN
line to allow this OFF control to properly operate. Larger
voltages are permissible (if the base-emitter junction of Ql
is prevented from entering a breakdown by a shunting diode, for example), but smaller voltages will not allow the
output of the amplifier to raise enough to give the OFF control.
Rl
RZ
Vo
v.
+
The resistor, Rs, is used to supply the required bias current
for the amplifier and R4 is again used to bias the Zener
diode. Due to a larger gain, a compensation capaCitor, Co,
is required. Temperature compensation could be added as
was shown in F/{/Ure 27b.
TLlH/738S-S2
(d) Raising Vo Wdhout Dialurbing Temparature Compansation
FIGURE 27. Simple Voltage Regulators
179
The base drive current for 01 is supplied via R1. The maximum current through"R1 should be limited to 10 mA as
...~y.-Vz++
, . . . - - - -...-
• I:"
T
v,
h.
+ VeE>
R1
To increase the maximum allowed input voltage reduce the
output ripple, or to reduce the (VIN - VOUT) req~irements of
this circuit, the connection described in the next section is
recommended.
IMAX = VIN (MAX! - (VA
':'
5.3 HIGH INPUT VOLTAGE PROTECTION AND LOW (VIN
- VOUT)
The circuit shown in F/{Jure 30 basically adds one additional
transistor to the circuit of Figure 29 to improve the performance. In this, circuit both transistors (01 and 02) absorb any
high input voltages (imd therefore need to,be high voltage
devices) without any ineraases in current (as with Rt of
ure 29). The resistor R1 (of F/{Jure 30) provides a "start-up"
,,' , ,
current into the base of 02.
A new input connection is shown on this regulator (the type
on F/{Jure 29 could also be used) to control the DC output
voltage. The Zener is biased via R4 (at approximately 1, mA).
The resistors Rs and Rs provide gain (non-inverting) to allow establishing Va at any desired voltage larger than Vz.
Temperature compensation of either sign (± TC) can be obtained by shunting a resistor from either the (+) input to
ground (to add + TC to Va) or from the (-) input to ground
(to add - TC to Va). To understand this, notice that the
resistor, R, from the (+ ) input to ground wi" add -, N VeE to
Va where
'
TLlHI7383-33
Fig-
FIGURE 28. Reducing (VIN - VOUT)
5.2 PROVIDING HIGH INPUT VOLTAGE PROTECTION
On~ of the four amplifiers can be used to regulate the sup·
ply line for the complete package (pin 14), to provide protection against large input voltage conditions, and in addition,
to supply current to an external load. This circuit is shown in
Figure 29. The regulated output voltage is the sum of the
Zener voltage, CR2, and the VeE of the inverting input terminal. Again, temperature compensation can be added as in
Figure 27b. The second Zener, CR1, is a low tolerance component which simply serves as a DC level shift to allow the
output voltage of the amplifier to control the conduction of
the external transistor, Q1. This Zener voltage should be
approximately one-half of the CR2 voltage to position the
DC Output voltage level of the amplifier approximately in the
,
center of the dynamic range.
N=1+Rs
..,.
R'
and VeE is the base emitter voltage of the transistor at the
(+) input This then also adds a positive temperature
change at the output to provide the desired temperature
correction.
The added, transistor, 02, also increases the gain (which
reduces the output impedance) and if a power device is
used for 01 large load currents (amps) can be supplied. This
regulator also supplies the power to the other three amplifiers of the LM3900.
"II.-....----t~_o v. - v,,++
Va,
CR'
5.4 REDUCING INPUT VOLTAGE DEPENDENCE AND
ADDING SHORT-CIRCUIT PROTECTION
To reduce ripple feedthrougl) and input voltage dependence, diodes can be added as shown in Figure 31 to dropout the start once start-up has been achieved. Short-circuit
protection can also be added as shown in F/{Jure 32.
The emitter reaistor of 02 will limit the maximum current of
02 to'(Vo - 2 VeE>/Rs.
TLlHI738S-34
FIGURE 28. High VIN Protection and S.If....gulatlon
.... 0-.....-
. . .""""-
.,
HI
'1M
11K
r __.....__...._ V.;..........2Vac
.:.:......._
13
IIIK
O ...
I'.'
+eo
R4
,'UK
V.
UV
TL/HI7383-S5
FI,GURE 30. A High VIN Protected, Low (VIN - VOUT) Regulator
180
+VlNo---4......-
ance is obtained with relatively low passive component impedance levels and in filters which do not demand high
gain, high Q (Q ~ 50) and high frequency (fo > 1 kHz)
simultaneously.
....
Rt
ttl
A measure of the effects of changes in the values of the
passive components on the filter performance has been given by "senSitivity functions". These assume infinite amplifier
gain and relate the percentage change in a parameter of the
CR.
filter, such as center frequency (fo), Q, or gain to a percentage change in a particular passive component. Sensitivity
functions which are small are desirable (as 1 or %).
CR2
CAl
= CA2 = CA3 = lN9l4
Negative signs simply mean an increase in the value of a
passive component causes a decrease in that filter performance characteristic. As an example, if a bandpass filter listed the following sensitivity factor
TLlHI73B3-36
FIGURE 31. Reducing VIN Dependence
to
ClIo
S
CRt
=
-%.
Cs
This states that "if Cs were to increase by 1 %, the center
frequency, ClIo, would decrease by 0.5%." Sensitivity functions are tabulated in the reference listed at the end of this
section and will therefore not be included here.
R2
A brief look at low pass, high pass and bandpass filters will
indicate how the LM3900 can be applied in these areas. A
recommended text (which provided these circuts) is, "Operational Amplifiers", Tobey, Graeme, and Huelsman,
McGraw Hill, 1971.
TLlHI7383-37
FIGURE 32. Adding Short-Circuit Current Limiting
6.1 BIASING THE AMPLIFIERS
6.0 Designing RC Active Filters
Active filters can be easily operated off of a single power
supply when using these multiple single supply amplifiers.
The general technique is to use the ( + ) input to accomplish
the biasing function. The power supply voltage, y+ , is used
as the DC reference to bias the output voltage of each amplifier at approximately Y+ /2. As shown in Figure 33, undesired AC components on the power supply line may have to
Recent work in RC active filters has shown that the performance characteristics of multiple-amplifier filters are relatively
insensitive to the tolerance of the RC components used.
This makes the performance of these filters easier to control in production runs. In many cases where gain is needed
in a system design it is now relatively easy to also get frequency selectivity.
The basis of active filters is a gain stage and therefore a
multiple amplifier product is a valuable addition to this application area. When additional amplifiers are available, less
component selection and trimming is needed as the performance of the filter is less disturbed by the tolerance and
temperature drifts of the passive components.
v+
¥
••
A.
+
TLlH/7383-38
(a) Biasing From a '"Noise-Free'" Power Supply
The passive components do contro/the parfonnsf1C6 of the
filter and for this reason carbon composition resistors are
useful mainly for room temperature breadboarding or for fi·
nal trimming of the more stable metal film or wire-wound
resistors. Capacitors present more of a problem in range of
values available, tolerance and stability (with temperature,
frequency, voltage and time). For example, the disk ceramic
type of capaCitors are generally not suited to active filter
applications due to their relatively poor performance.
v+
C1'-=-
-=-
R./2
TLlH17383-39
The impedance level of the passive components can be
scaled without (theoretically) affecting the filter characteristics. In an actual circuit; if the resistor values become too
small (:S:10 kO) an excessive loading may be placed on the
output of the amplifier which will reduce gain or actually
exceed either the output current or the package dissipation
capabilities of the amplifier. This can easily be checked by
calculating (or noticing) the impedance which is presented
to the output terminal of the amplifier at the highest operating frequency. A second limit sets the upper range of impedance levels, this is due to the DC bias currents ('" 30 nA)
and the input impedance of actual amplifiers. The solution
to this problem is to reduce the impedance levels of the
passive components (:S:10 MO). In general, better perform-
(b) Biasing From a '"Noisy" Power Supply
FIGURE 33. Biasing Considerations
be removed (by a filter capacitor, Figure 33b) to keep the
filter output free of this noise. One filtered DC reference can
generally be used for all of the amplifiers as there is essentially no signal feedback to this bias pOint.
In the filter circuits presented here, all amplifiers will be biased at y+ /2 to allow the maximum AC voltage swing for
any given DC power supply voltage. The inputs to these
filters will also be assumed at a DC level of y+ 12 (for those
which are direct coupled).
181
6.2 A HIGH PASS ACTIVE FILTER
A single amplifier high pass RC active filter .is shown in Figure 34. This circuit is easily biased using the ( +') input"of the
LM3900. The resistor, Rs, can be simply made equal to Ri!
and a bias reference of Y+ /2 will eStablish the output Cl
point at this value (V+ /2). The input is capacitively coupled
(C1) and there are therefore no further DC biasing problems.
Now we see that the value of R2 is quite large; but. the other
components look acceptable., Here is where impedance
scaling comes in. We can reduC$ R2 to the more convenient
value of 10 MO which is a factor of 1.59:1.'Reducing R1 by
this same scaling factor gives:
17.7 X 103
R1NEW =
1.59
= 11.1 kO
C2
and the capacitors are similarly reduced in impedance as:
47Gpf
. (C1= C2 =
fc=lkHz
(1.5~) (~OO) pF
C1NeW =477 pF.
To complete the design, Rs is !!lade equal to, R2 (10 MO)
and a YREF of V+ /2 is used to bias 'the output for large
signal accommo~ation.
Capacitor values should.be adjusted to use standard valued
components by using impedance scaling as a wider range
of standard resistor values is generally available.
Cl
4,.,f
~r
Cs ) NeW =
Va
8.3 A LOW PASS ACTIVE FILTER
A single amplifier low pass filter is shown in Figure 35. The
resistor, R4, is used to set the output bias level and is selected after the other resistors have been established.
83
10M
A2
1M
:rvHI7383-40
FIGURE 34. A High Pass Active Filter.,'
.
The design procedure for this filter is to select the pass
band gain, Ho, the 0 and the comer frequency,fe. ,A 0
value of 1 gives only a slight peaking near the bandedge
«2 dB) and smaller 0 values decrease this peaking. The
slope of the skirt of this filter is 12 dB/octave (or 40 dB/decade). If the gain, HO. is unity all eapacitors have the same
value. The design proceeds as:
Given: Ho, 0 and Cl)c = 2me
TO.find: R1, R2, C1'~' and Cs
let C1 = Cs and choose a convenient starting value.
Then:
Al
1M
A3
27GK
Va .
fo~lkHz
GAIN
R4
1.5M
=1
TLlH/7383·41
(1)
FIGURE 35. A Low Pass Active Pllter
The design procedure is as folloWs:
Given: Ho, 0, and.CI)~ =2wfe
To find: R1, R2, Rs, R4, C1,.. and C2.
Let C1 be a convenient value,
then
C:! = KC1
'(4)
where K is a constant which can be' used to adjust c(jmpo~
nant values. For example, with K ;,. 1, C1 ;;., C2. L.arger
values. of K can be used tq reduce R2 and 'Rs af the, eil.pense of. a larger value. for C2. . .
• .: .
. R2
R'I=-,
'(5j
.
He..
.
'.' ..
(2)
and
(3)
As a design example,
Require: Ho = 1,
0= 10, .
and
fe = 1 kHz (CI)e = 6.28 X 103 rps).
Start by seleciing Cl = 300 pF and then from equation (1)
R _
1
1 - (10) (6.28 X 10S) (3 X 10-10) (3)
'Fl. "=
1 .' [.1
,2. 20 Cl)cCl
Rl = 17;7ko
and from equation (2)
. R _
10' (3)
2 - (6.28 X 1OS) (3 X 10 10)
±
/1' + 402 (Ho
'\J.K
+ 1) ].
'.
(6)
and
(7)
R2 = 15.9MO
and from equation (3)
,"C1
C2="'1=C1
As a design example:
Require: HO'''''1. '
0= 1,
and
fe = 1kHz (CI)o .; 6.28
182
X.1 OS ~pS).
Start by selecting Cl = 300 pF and K = 1 so C2 is also 300
pF (equation 4).
6.4 A SINGLE-AMPLIFIER BANDPASS ACTIVE FILTER
The bandpass filter is perhaps the most interesting. For low
frequencies, low gain and low 0 (S: 10) requirements, a single amplifier realization can be used. A one amplifier circuit
is shown in Ftgure 38 and the design procedure is as follows;
Now from equation (6)
A2 = 2 (1)(6.28 X
1~S)(3 X 10- 10) [1 ± b +4 (2)]
A2 = 1.06MO
Given: He,
Then from equation (5)
0
and ClIo = 2'11"f.
To find: A" A2, A3, A4, Cl and C2.
Al = A2 = 1.06MO
Cl
510pf
and finally from equation (7)
As =
1
.
-----=------;:,...------
(6.28 X 10S)2 (3 X 10-10)2 (1.06 X 1()6) (1)
As = 266kO.
To select A4, we assume the DC input level is 7 Vee and
the DC output of this filter is to also be 7 Vee. This gives us
the circuit of Ftgure 36. Notice that He = 1 gives us not only
fo=lkHz
R4
6.2M
Q=5
GAIN = I
+JVOC
TLlH17383-44
FIGURE 38. A One Op Amp Bandpass Filter
Let C, = C2 and select a convenient starting value.
Then
o
A,=---
(8)
HeClloCl
v,
. . '
.
A2
TLlHI7383-42
=
FIGURE 36. Biasing the Low Pass Filter
(9)
20
equal resistor values (A, and A2) but simplifies the DC bias
calculation as 11 = 12 and we have a DC amplifier with a
gain of -1 (so if the DC input voltage increases 1 Vee the
output voltage decreases 1 Vee). The resistors A, and A2
are in parallel so that the circuit simplifies to that shown in
Ftgure 37 where the actual resistance values have been
added. The resistor A4 is given by
A4 =
o
-:-=-----=(2 0 2 - He) ClIo Cl
As=-CIIoCl
(10)
A4 = 2As(forVREF = V+)
(11)
and
As a design example:
Aequire: He = 1
0=5
2(~1 + As) + As
fo = 1 kHz (ClIo = 6.28 X 10S rps).
Start by selecting
or, using values
A4 = 2C
~O + 266k)
Ci = C2 = 510pF.
Then using equation (8)
'" 1.5 MO
A _
+1Voc
A,
IiOOK
5
, - (6.28 X 103)(5.1 X 10 10)
RI ~R2
= R112
==
1.57MO,
and using equation (9)
A _
R3
5
2 - [2(25) - 1] (6.28
Z10K
x 103) (5.1 x 10
A2 = 32kO
from equation (10)
2(5)
R3 = (6.28
x 103) (5.1 x 10 10)
As = 3.13MO,
and finally, for biasing, using equation (11)
A4 = 6.2 MO .
• 15Voc
TLIHI7383-43
FIGURE 37. Biasing Equivalent Circuit
183
10)
' "
~n
"
R2 = (40
Rs =
,
KQ
R2 = RI (2Q _ 1)
(13)
S-
R5=2~=80kO
R6 = 2
6.6 A THREE-AMPLIFIER BANDPASS ACTIVE FILTER
To reduce Q sensitivity to element variation even further or
to provide higher Q (Q> 50) a three amplifier bandpass filter
can be used. This circuit, FIfJUf8 40, pre-dates most of the
literature on RC active filters anll has been used on analog
computers. Due to the use of three amplifiers It often is
considered too~specially for low, Q applications.
The multiple amplifiers of the lM3900 makethis avery usefulcircuit. It has been called the "Bi..Quad" as ,It cen produce a transfer function wI1ich is "Quad" -ratic in bothnumerator and denominator (to give the "Bi"). A newer real..
As a design example:
Require: Q = 25 and fo = 1 kHz.
Select: CI = C2 = 0.1 jIoF
andK = 3.
Then from equation (12)
4-
= 59kO
These values, to the closest standard resistor values, have
been added to Figure 39.
(15)
(16)
R7 = KRI
He = 4CiK.
I -
[(40)(1~~ X 103]
(14)
and
R-R-R-
3(25)
and the second amplifier is blased by As. Notice that the
outputs of both amplifiers will be at V+ 12. TherefOre Rs and
R7 can be paralleled and
Rs = 2(As I R7)
or
RI
Q2 -1 - 2/K +1/KQ
+ _1_
Rs = 640
And R7 Is given by equation (15)
R7 =3 (40 kO) = 120 kO,
and the gain is obtained from equation (16) ,
He = .'25 (3) = 15 (23 dB).
To~p8rly bl,as the first amplifier "
a
(12)
'
40 X lOS
(25)2 -1 - 2/3
,
o.z
RI = R4 = R6 = O)oCI
x
,, ~
3(25)
1(3) [2(25) _ 11
R2 = 61 k~
and from equation (14)
Again, R5 Is Simply chosen as twice ~ and Rs must be
selected after Rs and R7 have been assigned values. The
design procedure Is as followS:
Given: Q and fo
To find: RI through R7, and CI atld
Let: CI = C2 and choose a convenient, starting value and
choose a value for K to reduce the spread of element values or to optimize sensitivity (1 s: KTypiClilIyS:10).
Then
R -
. .:
and from equation (13) ,
S.SA TWO-AMPLIFIER BANDPASSACT-~-OVo
f.-1kHz
Q - 25
GAIN = 15 (23 dB)
HZ
UK
.
FIGURE 38. ATwo
. Op Amp Bandpau FIlter
~
184
TLlHI7383-45
R8
200K
HI
lOOK
R~
470K
R4
10M
R7
470K
V'
fo~lkHz
0=50
Ho =
R8
1M
100 (40 dB)
y+
.
"IOUI!IE~. The "Bl-quad" RC Active
ization technique for this type of filter is the "$EIC9nd-d8gree
stete-variable network." Outputs can be taken at any of
three points to give low pass. high pass or bandpass response characteristics (see the reference cited).
Bandpass Filter
TLlH/7383-46
Then from equation (17).
A4 = (1.8 x lOS) [2(50) - 11
R4 = 17.8MO
From equation (18).
The bandpass filter is shown in FiguffJ 40 and the design
proceduf'8 by
the given relationship
Qo
QA =
2Qo
(21), '
1 + -Ao (C'.tIa - 2C'.t1p)
C'.tIa
where Ao is the open loop gain of the amplifier, C'.tIa is the
dominant pole of the amplifier and C'.tIp is the resonant frequency of the filter. The result is that the trade-off between
Q and center frequency (C'.tIp) can be determined for a given
set of amplifier characteristics. When QA differs significantly
from Qo excessive dependence on amplifier characteristics
is indicated. An estimate of the limitations of an amplifier
can be made by arbitrarily allowing approximately a 10%
effect on QA which results if
2Q
::' '
Ao C'0.tIa (C'.tIa - 2C'.t1p) = 0.1
"
or
" or
~= 1.9
therefqre,
'(aensitM- .
(;;) = 2.5
x 10-2 (~~) + 0.5:
fp;= Ufa.
Again, uSIng"datapf the Lfl,43900, fa= 1 kHz so this upper
frequency lim,it is approximately 2 kHZ for the assumed Q of
50. As indicated in equation (26) the value of QA can actualIyexceed the'value of Qo (Q enh~ent) and, as expectthe filter can even provide its own input (oscillating).
EXCess phase shift in the high frequency characteristics of
the amplifier typically caus,e unexpected oscillations. Phese
compensation can be uSEicl in the Bi-Quad network to reduce this problem (see L.C. Thomas paper).
Designing for large passband gain also increases filter de"p~nder!CY on th!! characteristics of the amplifier and finally
signal to noise ratio can u.ually be improved by taking gain
,in an input RC active filter (again see L.C. Thomas paper).
Somewhat larger Q's'can be achieved by adding more filter
sections, in either a synchronously tuned cascade (filters
, tuned to same center frequency a~ taking advantage of
, the bandwidth shrinkage factor which ,results from the series
connection) or as a standard multiple pole filter. All of the
,: conventional filters can be realized and selection is based
'.• upon all of the performance requirements which the application demands. The cost advantages of the LM3900, tha re!atively large bMdwidth 'and the ease of operation on a singlepower supply, )loltage rrake this product "n eXc:e"C:lnt
"building bli?~:~ for RG ,active filters. , " "
",,, .
7.0 De~~gningWavefor'm
Generators
(22)
As an example, using Ao = 2800 for the LM3900 we can
estimate the maximum frequency where'a Qo' = 50 would
be reasonable as
~=
2.5 X 10-2 (2.:
;1~3)
\,
.
~
.
The multiple amplifiers of the LM3900 can be used'to easilY
generate a wide variety of waveforms in the lowfreqU9ney
range (f :s; 10kHz). Voltage controlled oscill/ltors (VCO):s)
are also possible and are presented in ~on 8.0 "Designing Phase-locked Loops and Voltage, Controiled
+ 0.5
" '
eq;
HI '
,IOIK
Cl
D.1#lf
R4
11K
HZ
160K
H3
160K
RI
31K
RI
121.
CHI
GAIN CONTROLLED AMPLIFIER
":'
CRZ
R14
UM"
R13
12K
RII
1M
y+
CR3
va PEAK =
R1a
UM
2 VAEF
fo=lkHz
THO - 0.1% (VA - 5 vpl
+v ...
DIFFERENCE AVERAGER
TlIH/7383-48
FIGURE 41. A Slnewave Oaclllator
~86
Oscillators." In addition, power oscillators (such as noise
makers, etc.) are presented in section 10.11.3. The waveform generators which will be presented in this section are
mainly of the switching type, but for completeness a sinewave oscillator has been included.
7.3 PULSE GENERATOR
The squarewave generator can be slightly modified to provide a pulse generator. The slew rate limits of the LM3900
(0.5VI jJoS8C) must be kept in mind as this limits the ability to
produce a narrow pulse when operating at a high power
supply voltage level. For example, with a + 15 VOC power
supply the rise time, tr, to change 15V is given by:
15V
15V
tr = Slew Rate = 0.5V/ p.sec
7.1 A SINEWAVE OSCILLATOR
The design of a sinewave oscillator presents problems in
both amplitude stability (and predictability) and output waveform purity (THO). If an RC bandpass filter is used as a high
Q resonator for the oscillator circuit we can obtain an output
waveform with low liistortion and eliminate the problem of
relative center frequency drift which exists if the active filter
were used simply to filter the output of a separate oscillator.
A sinewave oscillator which is based on this principle is
shown in Figure 41. The two-amplifier RC active filter is
used as it requires only two capaCitors and provides an overall non-inverting phase characteristic. If we add a non·in·
verting gain controlled amplifier' around the filtar we obtain
the desired oscillator configuration. Finally, the sinewave
output voltage is sensed and regulated as the average value
is compared :tCl a DC reference voltage, VREF, by use of a
differential averaging circuit. It can be shown that with the
values selected for R15 and R16 (ratiO of 0.64/1) that there
is first order temperature compensation for CR3 and the
internal input diodes of the IC amplifier which is used for the
"difference averager". Further, this also provides a simple
way to regulate and to predict the magnitude of the output
sinewave as
tr = 30 p.sec.
The schematic of a pulse generator is shown in Figure 43. A
diode has been added, CR1, to allow separating the charge
path to Cl (via Rl) from the discharge path (via R2)' The
-
I CHARGE
CR.
R.
••• 4
3IK
Vo
+1 lVoe
PW '" 100 p.s
PRF .. 1 kHz
TLlH17383-49
FIGURE 43. A Pulse Generator
circuit operates as follows: Assume first that the output voltage has just switched low (and we will neglect the current
flow through R4). The voltage across Cl is high and the
magnitude of the discharge current (through R2l is given by
VCl - VBE
IOischarge S<
R2
Vo peak = 2 VREF
which is essentially independent of both temperature and
the magnitude of the power supply voltage (if VREF is de·
rived from a stable voltage source).
7.2 SQUAREWAVE GENERATOR
The standard op amp squarewave'generator has been modified as shown in Figure 42. The capacitor, Cl, alternately
This current is larger than that entering the (+) input which
is given by
H'
3IIK
IR3 =
V+ - VBE
R3
The excess current entering the (-) input terminal causes
the amplifier to be driven to a low output voltage state (saturation). This condition remains for the long time interval
(l/Pulse Repetition Frequency) until the R2Cl discharge
current equals the IR3 value (as CR, is OFF during this interval). The voltage across Cl at the trip point, VL, is given by
>"'-OVo
VL = (lR3) (R2),
TUHI7383-47
or
FIGURE 42. A Squarewave Oscillator
charges and discharges (via Rl) between the voltage limits
which are established by the resistors Ri!, R3 and R4. This
Combination produces a Schmitt Trigger circuit and the operation can be understood by noticing that when the output
is low (and if we neglect the current flow through R4) the
resistor R2 (3M) will cause the trigger to fire when the current through this resistor equals the current which enters
the ( +) input (via R3). This gives a firing voltage of approximately R2/(R3) V+ (or V+ 13). The other trip point, when
the output voltage is high,. is approximately [2(R2/R3ll V+,
as R3 = R4, or 2f.,(V+). Therefore the voltage across the
capacitor, .Cl, 'wili be the first one-half of an exponential
waveform between these voltage trip limits and will have
good symmetry and be essentially independent of the magnitude of the power supply voltage. If an unsymmetrical
squarewave is desired, the trip points can be shifted to produce any desired marklspace ratio.
(1)
At this time the output voltage will switch to a high state,
VOHio and the current entering the (+) input will increase to
IM+ =
187
V+- VBE
R3
+
VOHI - VBE
R4
.
~
~
011(
r------------------------------------------------------------------------------,
Also CR1 goes ON and the capacitor,C1; charges via R1.
Some of this charge current is diverted via R2 to ground (the
(-)input is at VCEsAT ,during this interval ~ the current
mirror is demanding more cUlTSnt than the (,.,.) input terminal can prov~e). The high trip voltage, Vwis given by
,
VH = (IM+) R2
or
V = (V+' - VBE VOHi- VBE) R
H
Rs
+,~
2·
2.0 Find R2 from equation (4) assuming C1
10-S
R2 = ,'---:-,'-'--:-::--::'.10- 8 1n
R2 =
144 kn
Rs = .!.:.(V_+_-..,.V""B=E>:...R...,2
,
VL
R _ (15 - 0.5) 1.44x 1()5
s1.5
4.0 Find
~
Rs = 1.39MO
from equation (2),
R
4
=
(VOHI - VBE>
VH V+ - Vse
R2-
R2C1
Rs,
(14.2 -0.5)
R4=--~3~--~1~5~-~0~.5~
or
1.44x 105 1.39x 108
~= 1.32MO
5.0 Find R1 from equation (5),
10-4
R1=------~----~--__
or
VH
T1 = R~1In(3)
,
VL
To provide a low duty cycle pulse train we select small values for both VH and VL (such as 3V and 1.5V) and choose a
starting value for C1. Then R2 is given by
T1
R2 =
(4)
C1 1n VL
-10- 8 In ( 1 - (14.2
~ 0.7))
104
R1 = ---,.----:,-:-In
13.5
104
R1 = 0.252 = 39.7 kO.
(1 - 2...)
---v;:; .
If R2 from (4) is not in the range of apprOximately 1(l0 kO to
1 MO, choose another value for C1. Now equation (1) can
be used to find a value for Rs to provide the VL which was
initially assumed. Similarly equation ,(2) allows R4 to be calculated. Finally R1 is determined by the required pulse width
(PW) as the capaCitor, C1, must be charged from VL to VH
by R1' This RC charging is given by (neglecting the loading
due to R2) ,
,
' T
VH .. (VOH; - Vo) (1,- e
(~:~)
3.0 Find Rs from equation (1)
_..2L
= VHe
o:ii94 =
0.01 poF,
';,
(2)
A design proceeds by first choosing the trip points for the
voltage across C1. The resistors Rs and R4 are used only
for this trip voltage control• .The resistor R2 affects, the discharge time, (the long interval) and also both ,of the trip voltages so this resistor is determined first from the required
pulse repetition frequency (PRF). The value of R2 is determined by the RC exponential discharge from VH to VL as
this time interval, T1, controls, the PRF (11 = 1/PRF). If we
start with the equation for the RC discharge we have
VL
1()5
==
Thesevalues (to the nearest 5% standard) have been added to Figure 43.
7.4 TRIANGLE WAVEFORM GENERATOR
Triangle waveforms are usually generated by an integrator
which receives first a positive DC input voltage, then a negative DC input voltage. The LM3900 easily provides tI:1is operation in a system which operates with only a single power
supply voltage by making use of the current mirror which
exists at the (+) Input. This allows the generation of a triangle waveform without requiring a negative DC input voltage.
The schematic diagram of a triangle waveform generator Is
shown in FIgure 44. One amplifier is doing the Integration by
-R1~1)
or
RI
1M
> ...._-o0UTPUT lI\I\
R1 "" -C11n ['1 _
]'
(5)
VH
VOHI- Vo
where T2 is the pulse width desired and Vo is the forward
voltage drop across CR1.
As a design example:
Required: Provide a 100 pos pulse avery 1 ms. The power
supply voltage is + 15 Voc
1.0 Start by chOOSing VL = 1.5V
and
VH = 3.0V
RI
OUTPUT I
, tlDI
114
Uti
SCHMITT· TRI.IER
1UHI7383~SO
FIGURE 44. A Triangle Waveform Generator
188
.--------------------------------------------------------------------,~
To provide a gated sawtooth waveform, the circuits shown
in Fiflure 45 can be used. In Figure 45(s), a positive ramp is
generated by integrating the current, I, which is entering the
(+) input Aeset is provided via Al and CAl keeps Al from
loading at the (-) input during the sweep interval. This will
sweep from Vo MIN to Vo MAX and will remain at Vo MAX
until reset. The interchange of the input leads, Figure 45(b),
will generate a negative ramp, from Vo MAX to Vo MIN.
operating first with the current through R1 to produce the
negative output voltage slope, and then when the output of
the second amplifier (the Schmitt Trigger) is high, the current through R2 causes the output voltage to increase. If Rl
= 2R2, the output waveform will have good symmetry. The
timing for one-half of the period (T12) is given by
T (R1Cl)AVO
2" = V+ - VBE
or the output frequency becomes
fo
="""-'-V:::-+...,-~V.".e::.E
2R1C1AVO
CRI
Rl
RESET o-W""",,M-~
where we have assumed Rl = 2R2, VeE is the DC voltage
at the (-) input (0.5 Vee), and AVO is the difference between the trip pOints of the Schmitt Trigger. The design of
the Schmitt Trigger has been presented in the section on
Digital and Switching Circuits (9.0) and the trip voltages control the peak-to-peak excursion of the triangle output voltage waveform. The output of the Schmitt circuit provides a
squarewave of the same frequency.
OUWUT
to
v'o--w_.....
I
-'-
:~
TVH/7383-51
(8) Positive Ramp
7.5 SAWTOOTH WAVEFORM GENERATOR
The previously described triangle waveform generator, Figure 44, can be modified to produce a sawtcoth waveform.
Two types of waveforms can be provided, both a positive
ramp and a negative ramp sawtooth waveform by selecting
Al and A2. The reset time is also controlled by the ratio of
Al and A2. For example, if Al = 10 A2 a positive ramp
sawtooth results and if R2 = 10 Al a negative ramp sawtooth can be obtained. Again, the slew rate limits of the
amplifier (0.5V/p.S) will limit the minimum retrace time, and
the increased slew rate of a negative going output will allow
a faster retrace for a positive ramp sawtooth waveform.
'1'0-"""'....-4
OUTPUT
:~
I
to
TVH/7383-52
(b) Negative Ramp
FIGURE 45. Gated Sawtooth Generator.
Cl
1.'
LDWLEAKAGE
v.
>---...~.....O()OUTPU1
v'
'.
.,
'+ oc'
v
1iV
•
1
'~I
I
•
1.3111
I
_._
AI
\l1li
."1.
IWEIP • 1001EC/V
'.\v..
RESET = 0.7 SECIY
SWEEP TIME
RATIO RESET TIME - 1010:1
All
1M
RESET
COIITAOl
•R1H1
•
1-.. .to
TL/H/7383-53
FIGURE 46. Generating Very Slow Sawtooth Waveforms
189
~
,1.6 STAIRCASE WAVEFORM.QENERATORS
A staii"casfl generator can be realized by supplyirig pulses to
itn,lntegrator eircWt The lM3900 also can"be used with a
squarewave input signal and a differentiating netWork"where
each ,transition Of the input ilqLiareWave causes a step in the
output waveform' (or' two steps per input cyele)~ This is
shown In Figure 47. These ,pulses of current are the charge
and discharge currents of the input capacitor, C1. The
charge current, Ie, enters the (t) input and is mirrored
about ground and Is "drawn into" the (-) input. The discharge current, 10, is Jlrllwn through the diode at .the input,
CR1, and therefore al!IQ'causes a step on the output stair-
7.5..1 GENERA'TNIIG A VERY S L O W , ;
SAWTOOTH WAVEFORM , ' ~,
The tM3900 'can; be used 'to generate avery slow sawtOoth
waVeforl'l'fWhlch can be'~ to' generateldng time delay
iiltervais. 'The'cirCuitis' shown fl'lFlgtire ,46 and uses fOi1r
aMplifiers; Amps 1 lrid 2 are,cascli.ded to inCrease the gain
Of the iritegratbr arid, the ciutpf:lf is the deSired very' slow
sawtooth ,waveform; Amp 3 is' used to exactly' Supply the
bias current to Amp 1.
With resistor Rs OPE/ned up and .the reset control at zero
volts• .the potentiometer, Rs, is adjusted to minimize .the drift
in .the output voltage of Amp 2 (thiil output mUst 'be kept in
the linear rangl;l to insure that Amp 2 is not In saturation).
Amp 4 is used to 'proVide a,biaS ritference which equals the
DC voltage 'at the (-) input of AITIP 3. Th8 resistor divider,
R7 ana Rg provides a 0.1 Vee reference voltage across Rg
which alsO, appears across RB. The current which flows
throll9h Rs, I, enters the (-) input of Amp 3 and causes the
current through Rs to drop by this amount This causes an
imbalance as now the current flow .through R4 is no longer
adequate to supply the input current of Amp 1. The net result is that .this same Cllrrent; Vis drawn from capacitor Cl
and causes the output 'voltage of Amp'2'to sweep slowly
positive. As a result of the high impedance v"ues used. the
PC component,. board used ,for this, circuit must first be
cleaned and .then coated With, silicone rubber to eliminate
the effects of Jeakage currents across .the: surface of the
board. The, DC leakage currents of the capacitor, Cl, must
also be'smali compared to the 10 nA charging current For
example. an insulation resistance Of 100,000 MO will leak
0.1 nA with 10 Voe across the capacitor and this leakage
rapidly increases at higher temperatures. Dielectric polarization of the dleleCtric'material may riot cause 'problems if the
circuit is not rapidly cycled. The resistor, Rs, and the capacitor, C1, can be scaled to provide other basic sweep rates.
For the values shown on: FiguiB 46 the 10 nA current and
.the 1p.F capaCitor establish a sweep rate of 100 sec/volt.
The reset control pulse (Amp 3 (+) input) c::auses Amp 3 to
go to the positive output saturation state and,the 10 MO
(R4l gives a reset rate qf 0.7 sec/vol'. The resll\tQr, J=ll,
prevents a large discharQe current of C1 from overdriving
.the (-) input and overloading)!)e input qlamp device. For "
larger charging currents, a resistor divider' ca.n be' placed
from the output of Amp 4 to ground and Rs ca.n,,~e trcim this
tap point directly to .the (-) input of Amp 1.
c;:,ase.
A free running staircase generat9r ,Is shown, 'in Figure' 48.
This'uses all four of.the amplifiers which a~e avallable in one
LM3900 package.
Amp 1
the input ~ulSes which "pump up" the staircase via r'rIsisfur R, (see seCtion 7:9 for the design of this
pulse generator). Amp' 2 dbes .the integrate ahd hold\tUnction and also supplies the outPut staircas'e waveform. 'AmPs
3 and 4 provide bo.th a compar!! and ,a one-shot multivi~
tor function (~ the SeCtl,on on DiQital and Sw,itching Circuits for, .the design of this dU1I1 functioron~shot). Resl~or
R,j is uS&d to sampl,e, t/le, staircase outpt.Jt voltage and to
co,iT)j)\",e I(with tile power supply voltage
via Rs. When
the Qutput e?,peeds lij)proximateiy ~O% 6f V, .the, connection '6f AmpS '3 and 4 causes a 1QO p.sec reset pulse to be
generatEid. Thi$ i$ cOupled to' thejnteg~tOr (Amp ~) via
and causes the st81rcaseoutput, voltage to fall to appro,!imately zero Volts. ,the neXt pulse out 'Of Amp 1 tl,ler\' startS a
provides
(V+l
Rli
new stepping tlYi:!e.
'
7.7 Ii. PULSE COUNTER AND A VOLTAGE VARIABLE
PULSE COUNTER
The basic circuit of Figure 48 can be used as a pulse counter, Simply by omitting Amp 1 and feeding input voltage pulses directly to R1' A simpler one-shot/comparator which requires only one amplifier can also be used in place of Amps
3 and 4 (again, see the section on Digital and Switching
Circuits). To extend .the time interval between pulses. an
additional amplifier can be used to supply base current to
,Amp 2, ,to 'eliminate the tendency for the output voltage to
drift up due to the 30 nA Input current (see section 7.5.1).
The Rulse, count can be made voltage variable simply by
remoVing th'ecomparator reference (Rs) from V+ and using
this as a control voltage input. Finally, .the input could be
derived, from differentiating a squarewave input as was
shoWn In F,gure 47 and if only one step per cycle were
, deslred, .the diode. CR, of Figure 47, can be eliminated.
ezLc:
lpF
Vo
~-4~OOUnvT
,
"2 STEPS/CYClE
TLIH/7383-54
FIGURE 47. Pumping the Staircase Via InputDlfferentJator
:;.. ,.,
190
7.8 AN UP-DOWN STAIRCASE WAVEFORM
GENERATOR
rent pulse is diverted to ground and the staircase then steps
"up". When the upper voltage trip pOint of Amp 2 (Schmitt
Trigger-see section on Digital and Switching Circuits) is
reached, 01 goes OFF and as a result of the smaller
"down" input resistor (one-half the value of the "up" resis·
tor, Rl) the staircase steps "down" to the low voltage trip
paint of Amp 2. The output voltage therefore steps up and
down between the trip voltages of the Schmitt Trigger.
A staircase waveform which first steps up and then steps
down is provided by the circuit shown in Figure 49. An input
pulse generator provides the pulses which cause the output
to step up or down depending on the conduction of the
clamp transistor, 01. When this is ON, the "down" cur·
HI
1.11.
IIIIC
O.O,plT
2M
R4
HZ
1M
UK
.JL
RESET
PUlSE
SIOK
ONUMOTw/
INPUT COMPARATOR
Rl
1.211
v+
TLlH/7383-55
FIGURE 48. A Free Running Stalrca8e Generator
-
IIOWII
INPUT PULSES
INtI.
RIIZ
" > - " " ' - - _ 0 OUTPUT
RI
PULSE
GENERATOR
"='
SCltMm·TIU6GER
TL/HI7383-56
FIGURE 49. An Up-down Staircase Generator
191
8.0 DesignhigPha.se-Locked Loops
and Voltage Controlled Oscillators,
time to ramp down 'from VH to Vl corresponds to ohe-half
the period (T) of the output frequency and can be found by
starting with the basic eqLlation: of the Integrator
The LM3900 ca,n be connected to ptovlOe a lOW' frequency
(f < 10kHz) phase~locked loop (PL2). This is a useful cireuit
for many control applications. Tracking filterS,' frequency to
DC converters, FM modulators and demOdulators are applications of a pL2.
,)
Vo
=1
-.,.. ,I, dt
8.1 VOLTAGE CONTROLLED OSCILLATORS (VCO)
The heart of a PL2 is the voltage controlled oscillator (VCO).
As the PL2 can be used for many functions, the required
linearity of the transfer characteristic (frequency out VB. DC
voltage in) depend$ upon the application. For low distortion
demodulation of an FM signal, a high degree of linearity is
necessary whereas a tracking filter application would not
require this performance in the veo.
A veo circuit is shown in Figure 50. Only two amplifiers are
required, one is used to integrate the DC Input control voltage, Ve, and the other is connected as ,a Schmitt-trigger
which monitors the output of the integrator. The trigger circuit is used to control the clamp transistor,
When
is
conducting, the input current, 12, is shunted to ground. During this one-half cycle the input current, I" causes the output voltage of the Integrator to ramp down. At the minimum
point of the triangle waveform (output 1), the Schmitt circuit
changes state and transistor
goes OFF. The current, 12,
is exactly twice the value of I, (R2 = R,/2) such that a
charge current (which is equal to the magnitude of the discharge current) is drawn through the capaCitor, p, to provide
the increasing portion of the triangular waveform (output 1).
The output frequency for a given DC input control voltage
depends on the trip voltages of the Schmitt circuit (VH and
VO and the components R, and C, (as R2 = R,/2). The
a,.
C
1,=
,
CONTROL
INPUT
vi:; -
R,
Vee
(2)
,'11
11 Vo = - - (I1t)
,C,
or
•
,11
Vo
'
I,
A't=-C
(3)
Now the time, I1t, to sweep from VH to VL becomes
,
(VH -'- Vt.)C ,.
I1t, =
,I,' : : or
-
.
T = 2 (VH - Vd C and
I,
f=.!.='
I,
(4)
2(VH - VdC
Therefore, once VH, Vlo R, and C are fIXed in value, the
output frequency, f, is a linear function of I, (as desired for a
VCO).
T
,
'
c
12·11
+---11
"d-7'--v
(12·11)
H
/
RI
+Vc
(1)
equation (1) simplifies to
a,
11
,
as I, Is a consta!)t (for a given v!llu~ Of 'Ie) which,ls given by
a,
-
f' ,
-
>---",-00 OUTPUT 1
12
R2
-~--VL
tOUT
RJ
R4
OUTPUT 2
0-------...:.+-4...-<
....JV""-O
~Sl.S
v+
four
TIJH/7383-S7
FIGURE 50. A Voltage Controlled Oscillator
192
c
RI
Yc
Yc
R2
R4
TLlHI7383-58
TLlH/7383-59
FIGURE 51. Adding Input Common-niode
Biasing Resistors
The Circuit shown in ·Flf}urB 50 will require Vc > VeE to
osCillate. A value of Vc = 0 provides fOUT = 0, which may
or may not be desired. Two common-mode input biasing
resistors can be added as shown in Flf}ure 51 to allow
fOUT = fMIN for Vi; = O. In general, if these resistors are a
factor of 10 larger than their corresponding resistor (Rl or
R2l a iarge control frequency ratiO can be realized. Actually,
Vc could range outside the supply voltage limit of V+ and
this circuit will still functiOn properly.
The outPut frequency of this circuit can be increased by
reducing the peak-1o-peak excursion of .the triangle waveform (output 1) by design of the trip points of the Schmi.tt
circuit. A limit is reached when the triangular sweep output
waveform exceeds the slew rate limit of the LM3900 (0.5 VI
p.S). Note that the output of the Schmitt circuit has to move
up only one VeE to bring the clamp transistor, 010 ON, and
therefore output slew rate of this circuit is not a limit.
FIGURE 52. Reducing Temperature Drift
To improve the temperature stability of the veo, a PNP
emitter follower can be used to giVe approximate compensation for the VeE'S at the inputs to the amplifier (see Figure
52). Finally to improve the mark to space ratio accuracy
over temperature and at low control voltages, an additional
amplifier can be added such that both reference currents
are applied to the same type of (inverting) inputs of the
LM3900. The circuit to. accomplish this is shown within dotted lines in Figure 53..
8.2 PHASE COMPARATOR
A basic phase comparator is shown in Figure 54. This circuit
provides a pulse-width modulated output voltage waveform,
VOl, which must be filtered to provide a DC output voltage
(this filter can be the same as the one needed in the PL2).
The resistor R2 is made smaller than Rl so the (+) input
serves to inhibit the (-) input signal. The center of the
RI
:------'-----l
I
Yc
D,OQI"f
1M
ll1K
t-9""'VV'~
v,
I
I
I
I
~MRZ~I~
L ________ ~ __ .-J
TLlH/7383-80
FIGURE 53. Improving Mark/Spece Ratio
193
creased to Improve the frequency lock range. With Inverting
gain, the input to the VCO could go to zero volts. This will
cause the output of the VCO to gq high (V+) and will latch if
applied to the (+) input of the phase comparator. Therefore
apply the VCO signal to the (-) input of the phase comparator or add the common-mode biasing resistors of Figure
51.
dynamic range is indicated by the waveforms shown on the
figure (90" phase difference between fiN and fvco).
••
+--rnnr'
I
.' 0
RI,
I
PULSE·WIDTH MODULATION
8.4 CONCLUSIONS
'!
'
"
'
One LM3900 package (4 amplifiers) can provide all of the
operations necessa\'y to make a phaSEHocked loop. In addition, a VCO is a generally useful component for other system applications.
FILTER
RANGE OF voce
v+
T';vooc';v+
fvco;LrlSl
9.0 Designing Digital and Switching
Circuits
V01~
PHASE DIAGRAM
The amplifiers of the LM3900 Can ,be over-driven and used
to provide a large number of .low spefid digital and switching
circuit applicatio",s for control systems which ope",tE! off of
single power supply voltages larger than the standard
+ 5 Voc digital limit. the large voltage swing i1ndslower
speed are both advantages for most industrial control systems. Each amplifier of the LM3900 can be thought of as "a
super transistor" with a fJ of'l MO,OOO (25 nA Input current
and 25 rnA output current) and with a non-inverting input
feature. I" addition, the actiVe 'pull-up and'pull-Q~n which
exists at the output will supply larger currenf:s than thl!' simple resistor pull-ups which are used in digital logic gates.
Finally, 'the low, input currents allow timing circuits which
minimize the capacitor values as large impedance levelli
can be used with the LM3900.
Tl/HI7383-BI
FIGURE 54. Phase Comparator
The filtered DC output voltage will center at 3V+ 14 and can
range from V+ 12 to V+ as the phase error ranges from 0
degrees to 180 degrees.
8.3 A COMPLETE PHASE·LOCKED LOOP
A phase-locked loop can be realized with three of theaniplifiers as shown in Figure 55. This has a center frequenCY of
approximately 3 kHz. To increase the lock range, DC gain
can be added at the input to the VCO by using the fourth
amplifier of the LM3900. If the gain is inverting, the limited
DC dynamic range out of the phase detector can be In-
:nr
f'N
30K
TUH/73BS-52
FIGURE 55. A Phase-locked Loop
194
(similar to DTL) is recommended as shown ,In Figure 58.
Interchange the inputs for a NAND gate.
9.1 AN "OR" GATE
An OR gate can be realized by the circuit shown in Figuf'8
56. A resistor (150 kO) from V+ to the (-) input keeps the
output of the amplifier in a low. voltage saturated state for all
inputs A, B, and C at OV. If any one of the input signals were
to go high (a! V +) the current flow through the 75 kG input
resistor will cause the amplifier to switch to the positive out·
put saturation state (VO ... V+). The current loss through
the other input resistors (which have an input in the low
voltage state) represents an insignificant amount of the total
input current which is provided by the, at least one, high
voltage Input. More than three inputs can be OR'ed if desired.
y'".
0-""".",
A
B o--1~-.
0-..........--1M-.....
C
150K
D
JfiK
A
0-"".-.
Eo-..........
o--W\I-...
JSK
CRJ
JSK
C o--W\I-"
f
II
= A+B+C
I
I
TLlHI7383-63
All Diodes 1 N914 or Equlv.
FIGURE 56. An "OR" Gate
9.3 A BI-5TABLE MULTIVIBRATOR
A bi-stable multivibrator (as asynchronous RS flip-flop) can
be realized as shown in F/{Juf'8 59. Positive feedback is provided by resistorR 4 which causes the latching. A positive
pulse at tlie "set" Input causes the output to go high and a
"reset" positive pulse will return the output to essentially
OVoc· .
9.2 AN "AND" GATE
A three input AND gate is shown in F/{Juf'8 57. This gate
requires all three inputs to be high in order to have sufficient
current entering the (+) input to cause the output of the
amplifier to switch high. The addition of R2 causes a smaller
current to enter the (+) input when only two of the inputs
are high. (A two input AND gate would not require a resistor
, v'
R1
J5K
RZ
J50K
v· o--w"'""....
RESET
24K
O--.M_......
on
.n
Z4K
Ao--W",""""I
TLlHI7363-65
FIGURE 58. A Large Fan-In "AND" Gate
The "fan-out" or logical drive capability is large (50 gates if
each gate input has a 75 kG resistor) due to the 10 mA
output current capability of the LM3900. A NOR gate Can be
obtained by interchanging the inputs to the LM3900.
RZ
UK
R3
JIIK
>-tHOVo
SETo-....J\NIt"'""". .~
Z4K
Co--w",""~
TLlH/J363-B4
TL/HI7383-66
FIGURE 57. An "AND" Gate
as R2). More than three inputs becomes difficult with this
resistor summing approach as the (+) input is too close to
having the necessary current to switch just prior to the last
input going high. For a larger fan-in an input diode network
FIGURE 59. A BI-stable Multlvlbrator
195
to be coupled to the (-) input which causes the output to
switch to the low voltage state.
A second trigger flip flop can bemede which consists of twc
amplifiers and also provides a complementary output This
connection is shown in Figure 61.
9.4 TRIGGER FLIP FLOPS
Trigger flip flops are useful to divide an input frequency
each input pulse will cause the output of a trigger flip flop to
change state. Again, due to the absence of a clocking signal
input, this is for an asynchronous logic application. A circuit
which uses only one amplifier is shown in Ff{/U19 60. Steering of the differentiated positive input trigger is provided by
the diode CA2. For a low output voltage state, CA2 shunts
the trigger away from the (-) input and resistor A3 couples
this positive input trigger to the (+) input· terminal. This
causes the output to switch high. The high voltage output
state now keeps CA2 OFF and the smaller value of (A5 +
AS> compared with. A3 causes a larger positive input trigger
as
9.5 MONOSTABLE MULTIVIBRATORS (ONE-8HOTS)
Monostable multlvibrators can be made using one or two of
the amplHiers of the LM3900. In addition, the output can be
designed to be either high or low in the quiescent state.
Further, to increase the u$8fuln!*ls, a one-shot can be designed which triggers at a particular DC input voltage level
to serve the dual role of providing first a comparator and
then a pulse generator.
v+
RI
R3
2IOK
CI
lOOpF
V,N
10
I.
o-f
1M
Re
--~
51
1-. ....".W\r-. ....".VVK".-4....
.CR2
I.
f'N
TLlH/7383-87
FIGURE 60. A Trigger Flip Flop
O.OOI"F
-<
>-"'-0 OUTPUT 2
OUTPUT I 0-...
f'N
l'
TLlH/7383-68
FIGURE 61. A Two-ampllfler Trigger Flip Flop
196
..
RI
Rl
1M
+-;uv"u-__- .
RI
1.. .
• Speeds Recovery
V'
TL/H/7383-69
FIGURE 82. A One-ahot MulUvlbrator
9.5.1 A TWO-AMPLIFIER ONE-SHOT
9.5.2 A COMBINATION ONE-8HOT/COMPARATOR
CIRCUIT
In many applications a pulse Is required If a DC input signal
A circuit for a two-amplifier one·shot is shown in F/{/ure 62.
As the resistor, R2, from V+ to the (-) input is smaller than
Rs (from V+ to the (+) input), amplifier 2 will be biased to a
low·voltage output in the quiescent state. As a result, no
current is supplied to the (-) input of amplifier 1 (via R3)
which causes the output of this amplifier to be in the high
voltage state. Capacitor Cl therefore has essentially the full
V+ supply voltage across it (V+ -2 VeS. Now when a dlf·
ferentiated trigger (due to C2) causes amplifier 1 to be driv·
en ON (output voltage drops to essentially zero volts) this
negative transient Is coupled (via Cl) to the (-) input of
amplifier 2 which causes the output of this amplifier to be
driven high (to positive saturation). This condition remains
while Cl discherges via (Rl) from approximately V+ to approximately V+ /2. This time Interval Is the pulse width
(PW). After Cl no longer diverts suffiCient current of R2
away from the (-) input of amplifier 2 (i.e., Cl is discharged
to approximately V+ /2 V) the stable DC state is restoredamplifier 2 output low and amplifier 1 output high.
This circuit can be rapidly re·triggered due to the action of
the diode, CR1. This re·charges Cl as amplifier 1 drives full
output current capability (approximately 10 mAl through Cl,
CRl and into the saturated (-) Input of amplifier 2 to
ground. The only time limit Is the 10 mA available from am·
pllfier 1 and the value of Cl. If a rapid reset is not required,
CAl can be omitted.
exceeds a predetermined value. This exists in free·running
oscillators where after a particular output level has been
reached a reset pulse must be generated to recycle the
oscillator. This double function is provided with the circuit of
Figure 63. The resistors Rs and R6 of amplifier 1 provide the
inputs to a comparator and, as shown, an input signal, VIN,
is compared with the supply voltage, V+. The output volt·
age of amplifier 1 is normally in a high voltage state and will
fall and initiate the generation of the output pulse when VIN
is R6/RS V+ or approximately 80% of V+. To keep VIN
from disturbing the pulse generation it Is required that VIN
fall to less than the trip voltage prior to the termination of
the output pulse. This is the case when this circuit is used to
generate a reset pulse and therefore this causes no problems.
9.5.3 A ONE-AMPLIFIER ONE-8HOT (POSITIVE PULSE)
A one·shot circuit can be realized using only one amplifier
as shown in F/{/IJftJ 64.
The resistor R2 keeps the output In the low voltage state. A
differentiated positive trigger causes the output to switch to
the high voltage state and resistor Rs latches this state. The
capacitor, Cl, charges from essentially ground to approxi·
mately V+ /4 where the circuit latches back to the quiescent
state. The diode, CR1, is used to allow a rapid re-triggering.
y+
Cl
III"
Rl
I.IM
,.
Rl
113
1M
Rl
1M
ORI
:--fL
> " , - 0 OUTPUT
RI
1M
TRI8GER.........J f--Wll-.....-.".".,.,.----'
,.PUr .......
C2
v,.
'''''
Trips At V,N ... 0.8 v+
V,N must fall < 0.8 V+ prior to t2
TLlHI7363-70
FIGURE 83. A On_hot MulUvtbrator'
wHh an Input Comparator
197
TL/HI7S83-71
FIGURE 84. A One-ampllfler One-ahot (Poaltlve Output)
~
w::-
~
r-----------------------------------------------------------------------------,
9.5.4 A ONE-AMPLIFIER ONE-8HOT (NEGATIVE PULSE)
VBE,but there is no upper limit as long as the input resistor
is large enough. to guarantee that the input current will not
,exceed 200 pA
A one-amplifier one-shot multivibrator which has Ii qu~s
cent state with the output high and which falls to zero volts
for the pulse duration is shown in Figure 65.
9.6.2 ACOMPARATOR FOR NEGATIVE
CRI
INPUT VOLTAGI!S
At!ding a commo~mode,biasing network to the comparator
in,'!="1gUf8 66 makes it possible to compare voltages between
zero ,and one,volt as well as the comparison of rather large
;negative voltages, FlfJure 67. When working with negative
voltages, the current supplied by the common-mode network must be large enough to satisfy both the current drain
demands of the input voltages and the bias current requirement of the amplifier:' "
RI
1M
CI
I.DIIMT
OUTPUT
At
TRIGGER
INPUT
I'"
~ I-JoIIfV-.J
No Negative
Voltage UmH
If f'r9per1y "
cz
loa,F
Biased
TLlH/7388~72
I.IM
FIGURE 65. A One-AmplHler One-8hot
,,(Negative, Output) ,
i.IM
III.
The sum of the currents through Rz and Ra keeps the (-)
input at essentially ground. This causes Vo to be in the high
voit8ge state. A differentiated negative 'trigger' waveform
causes the output to switch to'the low voltage state. The
large voltage across C1
provides: input current via R1 to
keep the outpUt low' until C1 is discharged to approximately
V+ /10~ At thiS'time the outJjutswitches to the stable high
voltage state. ,
' ,
,
>---"OV~.
now
"
TlYHt7383-74
FIGURE 67. A Non-inyertlngLow-yoltage ComparatoJ."
9.6~3A,qwERCOMPARATOI!I:
r:, ':'
Whlln used in conjunction withan,externaHr8nsi~r,:this
~er cOmpaiator wiD- drive loads, Which require more, current than the, IC amplifier is capable 'Of supplying., FlfJure 6iJ
IiIhoYiS a non-inverting comparatqr which i,s capable, of driv,ing a ,12Y, 40 mA pal)EilI lamp"
If the R4CZ n$Yorkls moved to, the (,;.,.) inpUt terminaj; the
circuit will trigger on a differe",tiated positive trigger WaVE!form.
" "':'
..
,"",
9.6 COMPARATORS
V'
The voltage comparator is a function required for most system operations and can easily be performed by the LM3900.
Both an inverting and a non-inverting, comparator can be
',
'
,
obtained.
LAMP
~ CONIPARATOR FO~ POSITIVE ,
INPUT VOLTAGES
The circuit in FigtJr8 66 is an inverting comparator. To insure
proper operation, the reference voltage must be larger than
9.6.1
~".~IM,
- ...
+V...
,
" ,
,
TL/H/7383~75
FIGURE 68. A Non-Inyertlng Power Comparator
"vo',
9.6.4 A MORE PRECISE COMPARATOR
1M
+
No,PositIve
A more precise comparator can be designed by using a second amplifier such that the Input voltag$J of the same type
of inputs are comparEid. The (-) input voltages of two amplifiers are naturally more closely matched initially and track
well with temperatur~'chang!ls.The,com~rator of Figure
69 uses this concept.
'
Vollage Umit
TLlHI7383-73
FIGURE 66. An Inverting Voltage Comparator
q.
198
The lower switch point for the inverting Schmitt-Trigger is
determined by the amount of current flowing into the positive input
the output voltage low. When the input current, Is, drops below the level required by the current mirror,
the output will switch to the high limit. With Vo high, the
current demanded by the mirror is increased by a fixed
amount, 12. As a result, the Is required to switch the output
increasE!s this same amount. Therefore, the switch points
are determined by selecting resistors which will establish
the required currents at the desired input voltages. Reference current (11) and feedback current (12) are set by the
following equation.
V+ -
with
lOOK
1M
L---------~~~----------_9~
11=--RB
1M
...-+--0 ....
0,'",
I,
!
.2
~+Ytc/2
R3
2111<
&OK
'S
+Vcc/2
TL/H/7385-17
(a)
••
.00.
3'
~---'WII---",J\I\I'v--o
.',
+v,.
."
+V,./2
TUH/7385-18
(b)
FIGURE 17. Voltage Controlled Oscillator
218
flow through resistor R2 to ground. If the value of R2 is
chosen as R1/2 a current equal to the capacitor discharge
current can be made to flow out of C1 charging it at the
same rate as it was discharged. By making R2 = R1 /2,
current 12 will equal twice 11. This is the control circuitry
which guararantees a constant 50% duty cycle oscillation
independent of frequency or temperature. As capacitor C1
charges, the output of comparator 1 will ramp up until it trips
comparator 2 to its high state (Vsa = + Vcc) and the cycle
will repeat.
The circuit shown in Figuf'8 17a uses a + 30V supply and
gives a triangle wave of 1.5V peak-to-peak. With a timing
capacitor, C1 equal to 500 pF, a frequency range from approximately 115 kHz down to approximately 670 Hz was
obtained with a control voltage ranging from 50V down to
250 mV. By reducing the hysteresis around comparator 2
down to ± 150 mV (Rf = 100 kO, Rs = 1 kO) and reducing
the compensating capacitor C2 down to .001 ,...F, frequencies up to 1 MHz may be obtained. For lower frequencies (fa
:s; 1 Hz) the timing capacitor, C1, should be increased up to
approximately 1 ,...F to insure that the charging currents, 11
and 12, are much larger than the input bias currents of comparator 1.
Figuf'8 17b shows another interesting approach to provide
the hysteresis for comparator 2. Two identical Zener diodes,
Z1 and Z2, are.used to set the trip points of comparator 2.
When the triangle wave is less than the value required to
Zener one of the diodes, the resistive network, R1 and R2,
provides enough feedback to keep the comparator in its
proper state, (the input would otherwise be floating). The
advantage of this circuit is that the trip points of comparator
2 will be completely independent of supply voltage fluctuations. The disadvantage is that Zeners with less than one
volt breakdown voltage are not obtainable. This limits the
maximum upper frequency obtainable because of the larger
amplitude of the triangle wave. If a regulated supply is available, F/{/ure 17a is preferable simply because of less parts
count and lower cost.
Both circuits provide good control over at least two decades
in frequency with a temperature coefficient largely dependent on the TC of the external timing resistors and capacitors. Remember that good circuit layout is essential along
with the 0.01 ,...F compensation capaCitor at the output of
comparator 1 and the series 100, resistor and 0.1 ,...F capacitor between its inputs, for proper operation. Comparator
1 is a high gain amplifier used closed loop as an Integrator
so long leads and loose layout should be avoided.
DIGITAL AND SWITCHING CIRCUITS
The LM139 lends itself well to low speed « 1 MHz) high
level logic circuits. They have the advantage of operating
with high signal levels, giving high noise immunity, which is
highly desirable for industrial applications. The output signal
level can be selected by setting the Vee to which the pull-up
resistor is connected to any desired level.
AND/NAND GATES
A three input AND gate is shown in Figuf'8 18. Operation of
this gate is as follows: resistor divider R1 and R2 establishes
a reference voltage at the inverting input to the comparator.
The non-inverting input is the sum of the voltages at the
inputs divided by the voltage dividers comprised of R3, R4,
+Vc:r:- 11V
............
AI
31.
315mV
A3
1II1II(
R4
'GIll<
...
VOUT
,.5
Hl"
"... 1
TL/H17385-19
FIGURE 18. Three Input AND Gate
Rs and Re. The output will go high only when all three inputs
are high, causing the voltage at the non-inverting input to go
above that at inverting input. The circuit values shown work
for a "0" equal to ground and a "1" equal + 15V. The resistor values can be altered if different logic levels are desired.
If more inputs are required, diodes are recommended to
improve the voltage margin when all but one of the inputs
are the "1" state. This circuit with increased fan-in is shown
in F/{/uf'8 19.
To convert these AND gates to NAND gates simply interchange the inverting and non-inverting inputs to the comparator. HysteresiS can be added to speed up output transitions if low speed input signals are used.
A'
II.
'
'6V
..:.J--DV
¥'
~=r
.... ",.
= A· B. C
.,
You,
••
Vour
= A. B • C •
0
I
ALL DIODES
lm4
TUH/7385-20
FIGURE 19. AND Gate with Large Fan-In
219
ORf.NOR GATES
The three input OR gate (positive logic) shown in Figure 20
is achieved from, the basic AND gate simply by increasing
R1 thereby reducing the reference voltage. A logic "1" at
any of the inputs will produce a logic "1" at the output.
Again a NOR gate may be implemented by simply reversing
the comparator inputs. Resistor R6 may be added for the
OR or NOR function at the expense of noise immunity if so
desired. .
. '
1
~
,.
VOUT
Jl.:..Va:
.
~
..; -f
-f"'.._.
.t=--+VlZll-~
FIGURE 23. One Shot Multlvlbrator
put pulse width is set by tlie values of C2 and R4 (with
R4> 10 Rs to avoid loading the.output). The magnitude of
the input trigger pulse required is determined by the resistive divider R1 and R2' Temperature stability can be
achieved by balancing the tempeniture coeffiCients of A4
and C2 or by usil)g components 'with very low iC. In addition, the TC of resistors R1 and R2 should be matched so as
to maintain a fixed reference voltage of +Vee!2. Diode 02
provides a rapid discharge' path for capacitor C2 to reset the
one shot at the end of its pulse. It also 'prevents the non-Inverting input from being driven below ground. The output
pulse width is relatively independent of the magnitude of the
supply voltage and will change less than 2% for a five volt
change in +Vee.
The one shot multivibrator "hown in Flflure 24 has several
characteristiCs which make it superior to that shown In Figure 23. First, the pulse width Is independent of the magnitude of the power supply voltage because the charging voltage and the intercept voltage are a fixed percentage' of
+ Vee· In addition this one-shot is capable of 99% duty
cycle and exhibits input trigger lock-out to insure that the
circuit will not re-trigger before the output pulse has been
completed. The trigger level is the voltage required at the
input to'raise the voltage at pOint A higher than the voltage
at pOint'B, and is set by the resistive divider R4 and R10 and
the network Rl,. R2 andRs. When the multlvibrator has
been triggered, the output of comparator 2 is high causing
the reference voltage at the non-inverting input of comparator 1 to go'to + Vee. This prevents any additional input
pulses from disturbing the circuit until the output pulse has
been completed.
The value of the timing capaCitor, C1, must be kept small
enough to allow comparator 1 to completely discharge C1
,before the feedback signal from comparator 2 (through R10)
switches comparator 1 OFF and allows C1 to start an exponential charge. Proper circuit action depends on rapidly discharging C1 to a value set by Rs and R9 at which time
comparator 2 latches comparator 1 OFF. Prior to the establishment of this OFF state, C1 will have been completely
discharged by comparator 1 in the ON state. The time delay,
'which sets the output pulse width, results from C1 recharging to the reference voltage set by R6 and R9. When the
, voltage across C1 charges beyond this reference, the output' pulse returns to ground and the input is again reset to
accept a trigger.
.3
11101C
.,.
TLlH/7385-24
"
Ao-"'R4~"
'v,.
.
-..
2G1IK
,M
.. 0-4 ~--:-...--;
+Vcc ·'5V
.,
.,
C1
'01"
=A+ B+e
.1
''''
TLlH/73B6-21
FIGURE 20. Three Input OR Gate
.v'"
TLlH/73B6-22
FIGURE 21. Output Strobing U81ng a DI8crete Translator
OUTPUT STROBING
The output of the LM139 may be disabled by adding a
clamp transistor as .shown in Figure 21. A strobe control
voltage at the base of 01 will clamp the comparator output
to ground, making it immune to any input changes.
If the LM139 is being used in a digital system the output may
be strobed using any other type of gate having an uncommitted collector output (such as National's DM5401!
DM7401). In addition another comparator of the LM139
could also be used for output'strobing. replacing 01 in FI{Jure 21. if desired. (See Figure 22.)
.'"
;:.........- - - 0 ...
I.IIBICSATEmi
1I4lM138
BISTABLE MULTIVIBRATOR
Figure 25 is the circuit of one comparator of the LM139
used as a bistable multivibrator. A reference voltage is provided at the inverting input by a voltage divider comprised of
R2 and Rs: A pulse applied to the SET terminal will switch
the output high. Resistor divider network R1. R4. and Rs
TL/HI7385-23
FIGURE 22. Output Strobing with TTL Gate
ONE SHOT MULTIVIBRATORS
A simple one shot multivibrator can be realized using one
comparator of the LM139 as shown in Figure 23. The out-
220
R.
R4
1M
A
1M
"-
Rl
lOOK
VIN
111
Ii80K
R5
10M
Rl
15K
o-.IV\"'""""'-H - .........
R2
lOOK
~
B +
-=-
~
C
i~~O'F
..sL~vcc
~
>-+-0 V...,
COMPARATOJIl
-y-+VCC
POINT C
I
0
to
COMPAftATOJI2
RIO
62K
1\8
HI
10M
2401(
.",.
TUHI7385-25
FIGURE 24. Multlvlbrator with Input Lock-Out
03
IDOl<
.,
l-l~_;'.
-!'
V
10K
SET
O.
,.K
04
51.
~.
02
o---YY
10K...........
RESET
I
I
'9 L-t~"
~:':oK
'Voe
9
~:K
lIl1LM13~D
t----I+ ",,,,,,,
"iiL
~~:Ok
:
V
S
~
TLIHI7385-2S
FIGURE 25. Bistable Multlvlbrator
now clamps the non-inverting input to a voltage greater than
the reference voltage. A pulse now applied to the RESET
Input will pull the output low. If both Q and ti outputs are
needed, another comparator can be added as shown
dashed in F/{/ure 25.
Figure 26 shows the output saturation voltage of the LM139
comparator versus the amount of current being passed to
ground. The end point of 1 mV at zero current along with an
RSAT of 600 shows why the LM139 so easily adapts itself
to oscillator and digital switching circuits by allowing the DC
output voltage to go practicelly to ground while in the ON
state.
TIME DELAY GENERATOR
The final circuit to be presented "Digital and Switching Circuits" is a time delay generator (or sequence generator) as
shown in Figure 27.
This timer will provide output signals at prescribed time intervals from a time reference to and will automatically reset
when the input Signal returns to ground. For circuit evaluation, first consider the quiescent state (YIN = 0) where the
output of comparator 4 is ON which keeps the voltage
across C1 at zero volts. This keeps the outputs of comparators 1, 2 and 3 In their ON state (Your = GND). When an
input signal is applied, comparator 4 turns OFF allowing C1
to charge at an exponential rate through R1. As this voltage
rises past the present trip points VA, Ve, and Vc of comparators 1, 2 and 3 respectively, the output voltage of each of
these comparators will switch to the high state (Your =
+ Vee). A small amount of hysteresis has been provided to
insure fast switching for the case where the Rc time constant has been chosen large to give long delay times. It is
not necessary that all comparator outputs be low in the quiescent state. Several or all may be reversed as desired simply by reversing the inverting and non-inverting input connections. Hysteresis again is optional.
1400 r-r-r..,"-.---Tlrr-,-..,
1200
1000
i
j
800
800
400
200
1v I
f:I I
I
son
/
II
l.o'~to\v
1mY.
jf
2
8
I' .u
T" -noc
10
14
II
'SINK(mA)
TUHI7385-27
FIGURE 26. Typical Output Saturation Characterlatlca
221
~r-----------------------------------------------------------------~
~
v+
AI
15K
10K
A2
200K
3K
, 18K
'Ie
3K
A3
51K
V.,
10K
V.
3K
111M
11K
vv:ffi[-----------------,;.--t
Vel
I
'
Vz .-
10K
V,
8
to
-...
~
,.
to
C!IMI'AIIA~I.
51K
TL/HI7385-28
FIGURE 27. Time Delay Generator
LOWFREQUENCYOPERATIONALAMPLIFIERS,,'The LM139, like other comparators, is not internally fraThe LM139 comparator can be used as an operational amquency compensated and does not have internal provisions
plifier in DC and very low frequency AC applications
for compensation by external components. Therefore, com(OS: 100 Hz). An interesting combination is to use one of the
pensation must be applied at either the inputs or output of
comparators as an op amp to provide a DC reference voltthe device. FIflUI'9 28 shows an output compensation
age for the other three comparators in the same package.
scheme which utilizes the output collector pull-up resistor
working with a Single compensation capacitor to form a
Another useful application of an LM139 has the interesting
feature that the input common mode voltage range includes'
dominant pole. The feedback network, R1 and R2 sets the
ground even though the amplifier is biased from a single
closed loop gain at 1 + R1/R2 or 101 (40 dB). Figul'929
supply and ground. The!l,eop amps are also low power drain
shows the output sWing'limitations versus frequency, The
dSVices and will not drive large load currents unless current
.
boosted with an exterrial NPN transistor. The largest application limitation comes from a relatively slow slew rate
whichrestricts.·the power bandwidth and the output voltage
rasJ'Onse time..
J.
rrrnmrrnmllr'T1'1T111T''!I'T1l.......!'O!!I
. +Vcc
.---e-..
'I'
R3
15K
10
>-,,-oVOUT
100
lk
10k
lOOk
FREQUENCY
".
. '.
TLlH/7385-30
FIGURE 29. Larg~ Signal Frequency Response
output currerit capabUily of this amplifier is limited by the
relatively large pull-up resistor (15 kO) .. SO the output is
shown boosted with an external NPN transistor in Figu1'930.
The frequency response Is greatly extended by the use of
the new compensation ~heme also shown in FIflUI'9 30.
The DC level shift due to. the VeE of 01 ailows the output
voltage to Swing from ground to approximately one volt less
than + Vee. A voltage offset adjustment can be added as
shown in Figu1'931.
RC
A2
lK..
',::,
A., = 1
+~=101
lOOK
CI
'T~"F
'TLlH/7385-29
R2
FIGURE 28. Non-Inverting Amplifier
222
slowly moving input signals. It may be omitted if not needed,
bringing the total parts count down to one pull-up resistor.
+Vee
The MOS clock driver shown in Figure 16 uses dual supplies
to properly drive the MM0025 clock driver.
", -100
+V"o--"--I
The square wave generator shown in Figure 13 can be used
with dual supplies giving an output that swings symmetrically above and below ground (see Figure 33). Operation is
identical to the single supply oscillator with only change being in the lower trip point.
C3
o.t"F
+Vee
...--_~""",.".....- - -...-o Vou<
Rl
lOOK
Rl
lK
Ft'ULL_UP
R4
TL/HI738S-31
FIGURE 30. Improved Operational Amplifier
Cl
~
.vc:c
OFFSET
AOJUST
R4
1M
R3
R&
R5
I
r+Vcc
L..J
-Vee
>",_OVOUT
RZ
15K
1M
1M
.,
lOOK
+V"'o-+---~
VOUT
-Va:
TL/HI73B5-34
FIGURE 33. Squarewave Generator Using Dual Supplies
Figure 34 shows an LM139 connected as an op amp using
dual supplies. Biasing is actually Simpler if full output swing
at low gain settings is required by biasing the inverting input
from ground rather than from a resistive divider to some
voltage between +Vcc and ground.
RZ
Rl
110K
TU,'F
Cl
lK
A., '" 100
All the applications shown will work equally well biased with
dual supplies. If the total voltage across the device is increased from that shown, the output pull-up resistor should
be increased to prevent the output transistor from being
pulled out of saturation by drawing excessive current, thereby preventing the output low state from gOing all the way to
TL/H/738S-32
FIGURE 31. Input Offset Null Adjustment
DUAL SUPPLY OPERATION
The applications presented here have been shown biased
typically between + Vee and ground for simplicity. The
LM139, however, works equally well from dual (plus and
minus) supplies commonly used with most industry standard
op amps and comparators, with some applications actually
requiring fewer parts than the Single supply equivalent.
The zero crossing detector shown in Figure 10 can be implemented with fewer parts as shown in Figure 32. Hysteresis has been added to insure fast transitions if used with
-Vee·
+Vcc
R,uu.-UP
±v,.
>-...-oV
+Vcc
OUT
R'ULL_UP
15K
>-"_OVOUT
RZ
1M
TLlHI7385-35
FIGURE 34. Non-Inverting Amplifier Using Dual Supplies
TL/H17385-33
FIGURE 32. Zero Crossing Detector Using Dual Supplies
223
+ 1SOOC. When this temperature sensor is connected as
shown in Figure 35 ifcan be used to indicate an alarm condition of either too high or too Iowa temperature excursion.
Resistors Ra and R4 $,et the trip pOint reference voltage, VB,
with switching occuringwhen VA = VB. Resistor R5 is used
to bias up 01 at some low value of current $imply to keep
quiescent power dissipation to a minimum. A'1IQ' near 10 "A
is acceptable.
Using one LM139, four separate senSEi pointS are available.
The ou~uts of the four comparators can be I,Ised to indicate
four separate alarm conditions or the outputs can be OR'ed
together to indicate an alarm condition' atilny one of the
sensors. For the circuit shown the ou~ut will-go HIGH when
the temperature of the sensor goes above the preset level.
This could easily be inverted by simply reversing the input
leads. For operation over a narrow temperature range, the
resistor ratio R2/R1 should be-large to make the alarm more
sensitive to temperature variations. To vary the trip points a
potentiometer can be substituted for Ra and R4' By the addition of a single feedback resistor to the non-inverting input
to provide a slight amount of hysteresis, the sensor could
function as a thermostat. For driving' loads greater than
15 mA, an ou~ut current booster transiste.: could be used.
MISCELLANEOUS APPLICATIONS
The following is a collection of various applications intended
primarily to turthershow the wide versatility thatthe -LM139
quad comparator has to offer. No new modes of operation
are presented here so all of the previous formulas and oircuit descriptions will ./lold true. It is hoped .~hat aU of the
circuits presented in this application· note will suggest to the
user a few of the many areas in which the LM139 can be
utilized.
REMOTETEMPERATURESENSOR/ALARM
The circuit shown in F/{/ure 35 shows a temperature overrange limit sensor. The 2N930 is a National process 07 silicon NPN transistor connected to produce a voltage reference equal to a multiple of its base emitter voltage along
with temperature coefficient equal to a multiple of 2.2 mV1°C.
That multiple is determined by the ratio of R1 to R2. The
theory of operation is as follows:. with transistor 01 biased
up, its base to emitter voltage will appear across resistor R1.
Assuming a reasonably high beta (fJ :2: 100) the base current can be neglected so that the current that flows through
resistor R1 must also be flowing through. R2. The voltage
drop across resistor R2 will be given by:
.
IR1 = IR2
FOUR INDEPENDENTLY VARIABLE, TEMPERATURE
COMPENSATED, REFERENCE SUPPLIES
The circuit shown in Figure 36 provides four independently
variable voltages that could be used for low current supplies
for powering additional equiplTIE!nt or for generating the reference voltages needed in some of the previous comparator applications. If the proper Zener diode is chosen, these
four voltages will, have a neal: zero temperature coefficient.
For industry standard Zeners, this will be somewhere between 5.0 and 5.4V at a Zener current of approximately
10 mAo An alternative solution is offered to reduce this 50
mW quiescent power drain. Experimental data has shown
.that any of National's process 21 transistors which have
been selected for low rev~rse beta (fJR <.25) can be used
and
so
VR2
= 11;12 R2 = IR1 R2 = Vbe
.
R2
-R
1
(31)
As stated previously this base-emitter voltage is strongly
temperature dependent, minus 2.2 mVloC.for a silicon tran. sistor. This temperature coefficient is also multiplied by the
resistor ratio R1/R2'
This provides a highly linear, -variable temperature coefficient reference which is ideal for use as a temperature sensor over a temperature range of approximately - 65°C to
.vee
v·
v·
R5
R3
Q1
REMOTE
SENSOR
2N93D
TLlHI7386-38
FIGURE 35. Temperature AlII~'"
224
.
:.
z
....
I
+Va:
~
+Va:
+Vcc
VI
VOUT2
01
'::"
+Va:
+ Va:
'::"
TLlHI7385-37
FIGURE 36. Four Variable Reference Supplies
quite s~tisfactorily as a zero T.G. Zener. When connected
as shown in Figure 37, thE! T.G. of the base-emitter Zener
voltage is exactly cancelled by the T.G. of tbe forward biased base-collector junction if biased at 1.5 mAo The diode
can be properly biased from any supply by adjusting Rs to
set Iq equal to 1.5 mAo The outpllts of any of the reference
supplies can be current boosted by using the circuit shown
in Figure 30.
+5V
R4
5K
R3
1M
y'
R2
10K
Rs
lfAVEBASE
lfAOOPEN
TLlH/73B5-39
!1,=1.5mA
Q1
FIGURE 38. MagnetiC Tape Reader with TTL Output
= National Process 21
'6Y
Selected for !.ow
Reversa{J
TL/HI73B5-38
FIGURE 37. Zero T.e. Zener
DIGITAL TAPE READER
Two circuits are presented here-a tape reader for both
magnetiC tape and punched paper tape. The circuit shown
in Figure 38, the magnetic tape· reader, is the same as Figure12with a few resistor values changed. With a 5V supply,
to make the output TTL compatible, and a 1 MO feedback
resistor, ± 5 mV of hysteresis is provided to insure fast
switching and higher noise immunity. Using one LM139, four
tape channels can be read simultaneously.
TLlH/7385-40
FIGURE 39. Paper Tape Reader With TTL Output
225
The paper tape reader shown in Figure 39 is essentially the
same circuit as FlfJure 38 with the only change being in the
type of transducer uSed. A photo-diode is now used to
sense the presence or absence of light passing through
holes in the tape. Again a 1 MO feedback resistor gives
± 5 mV of hysteresis to insure rapid switching and noise
immunity.
PULSE WIDTH MODULATOR
Figure 40 shows the circuit for a simpie pulse'width modulator circuit. It is essentially the same as that shown in Figure
13 with the addition of an input control voltage. With the
input control voltage equal to -+- Vee/2, operation is basically the same as that described previously. If the input C-j....- ..- O
VOUT
R3
lOOK
-Vee
":' Tel
TlIHI7385-44
FIGURE 43. Negative Peak Detector
TlIHI73B5-41
FIGURE 40. Pulse Width Modulator
R2
lOOK
.Vee
.Vee
.Vee
R4
lOOK
VA
Rc
10K
VA =
R3
lOOK
~PPER
TRIP POINT
va
= LOWER TRIP POINT
TLlH17385-42
FIGURE 41. Simplified Circuit For
Calculating Trip Points of FIgure 40
For the negative peak detector, a low impedance current
sink is required and the output transistor of the LM 139
works quite well for this. Again the only discharge path will
be the 1 MO reSistor ,and any load, impedanCE! used. Decay
time is changed by varying the 1 MO resistor.
CONCLUSION
The LM139 is ari extremely versatile comparator package
offering reasonably high speed while operating at power lev-'
els in the low mW region. By offering four independent comparators in one package, many logic and other functions
can now be performed at substantial savings in circuit complexity, parts count, overall physical dimensions, and power
consumption.
For limited temperature range application, the LM239 or
LM339 may be used in place of the LM139.
It is hoped that this application note will provide the user
with a guide for using the LM139 and also offer some new
application ideas.
226
National Semiconductor
Applicatiori Note 79
IC Preamplifier Challenges
Choppers on Drift
Since the introduction of monolithic IC amplifiers there has
resistors. The drift is independent of the value of the nulling
been a continual improvement in DC accuracy. Bias curnetwork so it can be used over a wide range of operating
rents have been decreased by 5 orders of magnitude over
currents while retaining low drift. The operating current can
be chosen to optimize bias current, gain, speed, or noise
the past 5 years. Low offset voltage drift is also necessary in
a high accuracy circuits. This is evidenced by the popularity . while still retaining the low drift. Further, since the drift is
of low drift amplifier types as well as the requests for selectindependent of the match between external and internal reed low-drift op amps. However, until now the chopper stabisistors when the offset is nulled, lower and more predictable
drifts can be expected in actual use. The input is fully differlized amplifier offered the lowest drift. A new monolithic IC
preamplifier designed for use with general purpose op amps , ential, overcoming many of the problems with single ended
improves DC accuracy to where the drift is lower than many
chOpper-amps. The device also has enough common mode
chopper stabilized amplifiers.
rejection ratio to allow the low drift' to be fully utilized.
INTRODUCTION
Chopper amplifiers have long been known to offer the lowest possible DC drift. They are not without problems, however. Most chopper amps can be used only as inverting amplifiers, limiting their applications. Chopping can introduce
noise and spikes into the signal. Mechanical choppers need
replacement as well as being shock sensitive. Further,
chopper amplifiers are designed to operate over a limited
power supply, limited tE!mperature range.
Previous low-drift op amps do not provide optimum performance either. 'Selected devices may only meet their specified
voltage drift under restrictive conditions. For example, if a
741 device is selected without offset nulling, the addition of
a offset null pot can drastically change the drift. Low drift op
amps designed for offset balancing have another problem.
The resistor network used in the null circuit is designed to
null the drift when the offset voltage is nulled. The mechanism to achieve nulled drift depends on the difference, in
temperature coefficient between the intemal resistors and
the external null pot. Since the internal resistors have a nonlinear temperature coeffICient and may vary device to device
as well as between manufacturers, it can only approximately
null offset drift. The problem gets worse if the external null
pot has a TC other than zero.
A new IC preamplifier is now available which can give drifts
as low as 0.2 p.VI"C. It is used with conventional op amps
and eliminates the problems associated with older devices.
As well as improving the DC input characteristics of the op
amp, loop-gain is increased when an LM121 is used. This
further improves overall accuracy sinCE! DC gain error is decreased.
The LM121 preamp is designed to give zero drift when the
offset voltage is nulled to zero. The operating current of the
LM121 is programmable by the value of the null network
CIRCUIT DESCRIPTION
The LM121 is a well. matched differential amplifier utilizing
super-gain transistors as the input devices. A schematic is
shown in Figure 1. The input signal is applied to the bases of
Qs and Q4 through protection resistors R1 and R2. Qs and
Q4 have two emitters to allow offset balancing which will be
explained later. The operating current for the differential amplifier is supplied by current sources QlO and Q11. The operating current is externally programmed by resistors connected from the emitters of Q10 and Q11 to the negative supply.
Input transistors Qs and Q4 are cascoded by transistors Qs
and Q6 to keep the collector base voltage on the input
stage eq'ual to zero. This eliminates leakage at high operating temperatures and keeps the common mode input voltage from appearing across the low breakdown super-gain
input transistors. Additionally, the cascade improves the
common mode rejection of the differential amplifier. Q1 and
Q2 protect the input against large differential voltages.
The ouput signal is developed across resistive loads Rs and
R4. The total collector current of the input is then applied to
the base of a fixed gain PNP, Q7. The collector current of
~ sets the operating current of Q8, Q12, and Q1S. These
transistors are used to set the operating voltage of the cascode, Qs .and Q6. By operating the cascode biasing transistors at the same operating current as the input stage, it is
, possible to keep collector base voltage at zero; and therefore, COllector-base leakage remains low over a wide current range. Further, this minimizes the effects of VeE variations and finite transistor current gain. At high operating c.urrents the collector base voltage of the input stage is increased by about 100 mV due to the drop across R1S and
R16. This prevents the input transistors from saturating under worst case conditions of high current. and high operating
temperature.
227
CI)
zroo-
C
v+
I
R4
10K
RI
SOK
RI
SOK
OUTPUT I
OUTPUT •
RI
,IIDK
RIS
IK
RIG
IK
RI
IIIPUT 2 ID8
R2
IIIPUT I
~T~·
~T
ID8
RIa
l&OK
__________________
.r
RI
AI
IK
II'
_I______________~--------~
RII
3U
y.
RII
IK
...
RI.
~--------------~--------------. .---t--~t---~--~~----. .---t--~
TLlH17987 -1
·Pln connectlor:- shown on diagram and typical applications are for TO·5 pack4ga.
FIGURE 1. SchematiC Diagram of the LM121
The rest of the devices comprise the turn-on and regulator
circuitry. TranSistors a14, a15, and a16 form a 1.2V regulator for the bases of the Input stage current source. By fixing
the bases of the current sources at 1.2V, their ouput current
changes proportional to absolute temperature. This compensates for the temperature sensitivity of the input stage
, trsnsconductance. Temperature compensating the traris'conductance makes the preamp more useful in some applications such as an instrumentation amplifier and minimizes
bandwidth variations with temperature. The regulator Is
started by 018 and its operating current Is supplied by a17'
and Og, Fl{Juf9 2 shows the LM121 Chip.
, the LM121 depends only upon the highly predictable emitter
base voltages of transistors to achieve low drift.' Devices
like the LM725 depend on the match between internal resistor temperature coefficient and the external null pot as well
as the input stage trsnsistors characteristics 'for drift compensation.
The input stage'of the LM121 is actually two differential
',amplifiers connected in parsllel, each having a' fixed offset.
The offset is due to different areas for the transistor emitters. The offset for each pair is given by:
kT Al
4VSE=-lnq A2
where k is Boltzmann's constant T is absolute temperature,
OFFSET BALANCING
The LM121 was designed to operate with an offset balancing network connected to the current source transistors.
The method of balancing the offset also minimizes the drift
of the preamp. Unlike earlier devices such as the LM725,
228
using integrated circuits a minimum of three metals are
found: copper, solder, and kovar (lead material of the Ie).
Nominally, most parts of a circuit are at the same temperature. However, a small temperature gradient can exist
across even a few inches - and this is a big problem with
low level signals. Only a few degrees' gradient can cause
hundreds of microvolts of error. The two places this shows
up, generally are the package-to printed circuit board interface and temperature gradients across resistors. Keeping
package leads short and the two input leads close together
help greatly.
For example, a very low drift amplifier was constructed and
the output monitored over a 1 minute period. During the 1
minute it appeared to have input referred offset variations of
± 5 /JoV. Shielding the circuit from air currents reduced this
to ±0.5 /JoV. The 10 /JoV error was due to thermal gradients
across the circuit from air currents.
Resistor choice as well as physical placement is important
for minimizing thermocouple effects. Carbon, oxide film and
some metal film resistors can cause large thermocouple errors. Wirewound resistors of evenohm or managanin are
best since they only generate about 2 /JoVloe referenced to
copper. Of course, keeping the resistor ends at the same
temperature is important. Generally, shielding a low drift
stage electrically and thermally will yield good results.
Resistors can cause other errors besides gradient generated voltages. If the gain setting resistors do not track with
temperature a gain error will result. For example a gain of
1000 amplifier with a constant 10 mV input will have a 10V
output. If the resistors mistrack by 0.5% over the operating
temperature range, the error at the output is 50 mV. Referred to input, this Is a 50 p.V error. Most precision resistors
use different material for different ranges of resistor values.
It Is not unexpected that resistors differing by a factor of
1000, do not track perfecUy with temperature. For best results insure that the gain fixing resistors are of the same
material or have tracking temperature coefficients.
Testing low drift amplifiers is also difficult. Standard drift
testing techniques such as heating the device in an oven
and having the leads available through a connector, thermoprobe, or the soldering iron method - do not work. Thermal
gradients cause much greater errors than the amplifier drift.
Coupling microvolt signals through connectors is especially
bad since the temperature difference across the connector
can be 500e or more. The device under test along with the
gain setting resistor should be isothermal. The circuit in FigUrB 3 will yield' good results If well constructed.
TL/H/73B7 -2
FIGURE 2. LM121 Chip
q is the charge on an electron, and A1 and A2 are emitter
areas. Because of the offset, each pair has a fixed drift.
When the pairs are connected in parallel, if they match, the
offsets and drift cancel. However, since matching is not perfect, the emitters of .the pairs are not connected in parallel,
but connected to independent current sources to allow offset balancing. The offset and drift effect of each pair is proportional to its operating current, so varying the ratio of the
current from current sources will vary both the offset and
drift. When the offset is nulled to zero, the drift is nulled to
below 1 p.v/oe.
The offset balancing method used in the LM121 has several
advantages over conventional balancing schemes. Firstly,
as mentioned earlier, it theoretically zeros the drift and offset simultaneously. Secondly, since'the maximum balancing
range is fixed by transistor areas.. the effect of null network
variations on offset voltage is minimized. Resistor shifts of
one percent only cause a 30 p.V shift in offset voltage on
the LM121, while a one percent shift in collector resistors on
a standard diff amp causes a 300 p.V offset change. Finally,
it allows the value of the null network to set the operating
current.
11K
CONNECTOR
ACHIEVING LOW DRIFT
A very low drift amplifier poses some uncommon application
and testing problems. Many sources of error can cause the
apparent circuit drift to be much higher than would be predicted. In many cases, the low drift of the op amp is completely swamped by external effects while the amplifier is
blamed for the high drift.
Thermocouple effects caused by temJ?8rature gradient
across dissimilar metals are perhaps the worst offenders.
Whenever dissimilar metals are joined, a thermocouple results. The voltage generated by the thermocouple is proportional to the temperature difference between the junction
and the measurement end of the metal. This voltage can
range between essentially zero and hundred of microvolts
per degree, depending on the metals used. In, any system
>--
100
Vas X 1100
10K
OVEN
AMBIENT
TLlH/7387 -3
'Op amp shown in FtgIKB 9.
FIGURE 3. Drift Mea.suremen! Circuit
229
offs~t For example,lIthe offset is nulled to 100 /LV, aboot
0.4 /LVrC will res\llt - or twice the typlcaily expected drift.
This drift is qllite predict$le and COuld even: be used to
cancel the drift elsewhere in,a system. Figure 6 shows drift
as a function of offSet voltage. For critical applications selected devices can achieve,O.2 /LVI·C.'
,,'
"
PERFORMANCE
It is somewhat difficult to specify the performance ot the
LM121 since it is programmable over a wide range of operating currents. Changing the operating current varies gain,
bias current,' and offset current - three critical parameters
in a high accuracy system. However, offset voltage and drift
are virtually independent of the operating current
Typical performance at an operating current of 20p.A is
shown in Table I. Figures 4 and 5 show how the bias current, offset current, and gain change as a function 'of'programming current Drift is guaranteed at 1 /LVrC independent of the operating current.
Figures '7 and 8 show the biaS cUrrent, offset current, and
gain variation over a - 55'C to + 125'6 templ;.rature range.
These performance characteristics do not tell the whole story. ,Since the LM121 is used with an operational, amplifier,
the,op amp characteristics must be considered for over..all
amplifier, performance.
'"
5 ...--,-...,..,.--,---r-....,
TABLE I. Typical Performance at an Operating
Current of 10 p.A Per Side
Offset Voltage
Nulled
Bias Current
;
,Ii;
7nA
III
0.3/LVI"C
125dB
~
Supply Voltage Rejection Ratio
Common Mode Range
125dB
±13V
Gain
Supply Current
20VN
z
'":!:...
1
0
/'
V
,Vo "lfl5V
"
.2
u,
.&
.4
••
1.0
TLlH17387-8
FIGURE 6. Drift VB Offset Voltage
~
·.A/SIDE~
l00~m
I'
..
V
OFFSET VOLTAGE (mV)
lDO".~m'
10
V
./
2
0.5mA
a:
a:
'"u
'"o.!!!
V
co
0.5nA
....
3
a:
Offset Current
Offset Voltage Drift
Common Mode Rejection Ratio
1
4
lo..
..
I .
.1
'I~~ ;Z~'C
I 1111111
3
5
10
30 51
100
2
SET CURREJIITISIDE ("A)
.1 Lo-.L--'--'-....L.......L.-L......L--I......I
TLlHI7387 -4
-55 -3& -15 &' 25 4& 85 IS 185 12&
, FIGURE 4. BlaB and Offset Current VB Set Current
TEMPERATURE ('C)
'TLlHI7387~ 7
FIGURE 7. BlaB and Offset Current VB Temperature
z
C
...
CD
10•
...
'"~
co
...
>
:!
..
...
III
a:
......
is 1.3
N
::;
c
3D
Ii
a:
co
1.
1.2
..
1.1
...'"
1.0
co
••
!!
/
C
Vo· ~15V
,0108'Hz
is
2
1
Z
5
10
zo
&0
'"~
'~
c
10D
>
COLLECTOR CURRENT/SIOE ("A)
TLlH/7387 -5
FIGURE 5. Gain VB Set Current
i.,...-
",
"" ""
,
V. -,.I&V
'-300Hz
.1 J--"'-...L--..............-'--'---'---I--I
-55 -35 -15 5 25 45 85 85 105 12&
TEMPERATURE ('C)
Over a temperature range of - 55'C to + 125'C the LM121
has less than 1 /LV I'C offset voltage drift when nulled. It is
important that the offset voltage is accurately nulled to
achieve this low drift. The drift is directly related to the offset
voltage with 3.8 /LV I'C drift resulting from every millivolt of
"
TLlHI7387-8
FIGURE 8. Gain VB Temperature for the, LM121
230
~-------------------------------------------------------------------------.~
OP AMP EFFECTS
amp will cause a drift of about 0.14 p.vrc. With the system
nulled the drift due to op amp will cause a drift of about
0.15 p.VloC. With the system nulled the drift due to op amp
offset can be expressed as:
The LM121 is nominally used with a standard type of operational amplifier. The op amp functions as the second and
ensuing stages of the amplifying system. When the LM121
is connected to an op amp, the two devices may be treated
(and used) just as a single op amp. The inputs of the combination are the inputs of the LM121 and the output is from
the op amp. Feedback, as with any op amp, is applied back
to the inputs. Figure 9 shows the general configuration of an
amplifier using the LM121.
drift ( VrC) = op amp Offset. (mV) (3.6 V10C).
P.
LM121 gain
p.
In actual operation, drift due to op amp offsets will usually
be better than predicted. This is because offset voltage and
drift are not independent. With the LM121 there is a strong,
predictable, correlation between offset and drift. Also, there
is a correlation with op amps, but it is not as strong. The drift
of the op amp tends to cancel the drift induced in the LM121
when the system is nulled.
In the pr~vious example the drift due to the op amp offset
was 0.15 p.vrc. If the op amp has a drift of 3.6 p.VloC per
millivolt of offset (like the LM121) it will have a drift of
7.2 p.V/oC. This drift is reduced by the gain of the LM121
(Av = 50) to 0.14 p.V
This 0.14 p.VloC will cancel the
0.14 p.VloC drift due to balancing the LM121. Since op
amps do not always have a strong correlation between offset and drift, the cancellation of drifts is not total. Once
again, high gain for the LM121 and a low offset op amp
helps achieve low drifts.
The offset voltage and drift of the op amp used have an
effect on overall performance and must be conSidered. (The
bias and offset currents of today's op amp are low enough
to be ignored.) Although the exact effects of the op amp
stage are difficult and tedious to calculate, a fewapproxima.tions will show the sources of drift.
Op amp drift is perhaps the most important source of error.
Drift of the op amp is directly reduced by the gain of the
LM121. The drift referred to the input is given by:
.
.
op amp drift
Inputdnft = LM121 gain
rc.
.
+ LM121 dnft.
rc
If the op amp has a drift of 10 P.V
and the LM 121 is
operated at a gain of Av = 50, there will be a 0.2 p.VloC
component of the total drift due to the op amp. It is therefore important that the LM121 be operated at relatively high
gain to minimize the effects of op amp drift. Lower gains for
the LM121 will give proportionately less reduction in op amp
drift. Of course, a moderately low drift op amp such as the
LM108A eases the problem.
Op amp offset voltage also has an effect on total drift. For
purpose of analysis assume the LM121 to be perfect with
no offset or drift of its own. Then any offset seen when the
LM121 is connected to an op amp is due to the op amp
alone. The offset is equal to:
op amp offset
offset voltage = LM121 gain
FREQUENCY COMPENSATION
The additional gain of the LM121 preamplifier when used
with an operational amplifier usually necessitates additional
frequency compensation. This is because the additional
gain introduced by the LM121 must be rolled-off before the
phase shift through the LM121 and op amp reaches 180".
The additional compensation depends on the gain of the
LM121 as well as the closed loop gain of the system. Two
frequency compensation techniques are shown here that
will operate with any op amp that is unity gain stable.
When the closed loop gain of the op amp with the LM121 is
less than the gain of the LM121 alone, more compensation
is needed. The worst case situation is when there is 100%
feedback - such as a voltage follower or integrator - and
the gain of the LM121 is high. When high closed loop gains
are used - for example Av = 1000 - and only an additional gain of 100 is inserted by the LM121, the frequency compensation of the op amp will usually suffice.
or the offset.is reduced by the gain of the LM121. For example, with a gain of 50 for the LM121, 2 mV of offset on thE!
op amp appears as 40 p.V of offset at the LM121 input.
Unlike offset due to a mismatch in the LM121, this 40 p.Vof
offset does not cause any drift. However, when the system
is nulled so the offset at the input of the LM 121 is zero, 40
p.V of imbalance has been inserted into the LM121. The
imbalance caused by nulling the offset induced by the op
The basic circuit of the LM121 in Agure 9 shows two compensation capacitors connected to the op amp (disregarding the 30 pF frequency compensation for the op
231
~
'"I
I ..............
....
I
..............
I
....... .......
I
.......
ICc.·
I
-INPUT _...L_~
> ..--------~--OUTPUT
>
+ INPUT ---1~~
I
I RIITt
I
NULL
I NULL POT
I 0.2 IlsET
I
I
V'"
'Frequency compenilallon see IBxt for values '
600
tlSET (pAl z RSET (kill
",
.y-
FIGURE 9. General Purpose AmplHler Using the LM121
An alternate compensation scheme was developed for applications requiring more predictable and srnoother roll off.
This is useful where the amplifier's gain is changed over a
wide range. In this
Ccl' is made large and connected
to V+ rather than ground. The output of the UA121 is reno
dered single ended by a 0.01 ,.F bypass capacitor to V+.
Overall frequency compensation then is achieved by an In·
tegrating capacitor around the op amp:
amp alone). The capacitor from pin 6 to pin 2 around the op
amp acts as an integrating capaCitor to roll off the gain.
Sinee the output of the LM121 is d~erential, a second ca·
pacitor is needed to roll off pin 3 of the op amp. These
capacitors are Ccl and Cc2 in Figure 9.
With capaCitors equal, the circuit retains good AC power
supply rejection. The approximate value of the compensa·
tion capacitprs is given by:
,
Cc
'case
Ban~dth
at unity gain .... 2 ~2 c·
.
1T SET.
8
= 1()6 AcLRsET farads
where RSET is the current set resistor from each current
source and where AcL is closed loop gain. Table II shows
typical capacitor values.
for O.S MHz bandwidth C = 106
TABLE II. Typical compensation capecltora tor various
operating curranta and closed loop gain•• Value. given
apply to LM101A, LM108, and LM741 type amplifiers.
Closed
Loop
Gain
Av=
Av=
Av =
Av =
Av =
Av =
Av =
1
S
10
SO
100
SOO
1000
Currant Set R....tor
120kO
6OkO
30kO
12kO
akO
68pF
1SpF
10pF
1 pF
130pF
27pF
1SpF
3pF
1 pF
270pF
SOpF
27pF
SpF
3pF
1 pF
680pF
130pF
68pF
1SpF
SpF
1 pF
1300 pF
270pF
130pF
27pF
10pF
3pF
232
~SET
ing circuitry. A reasonable value for external resistors is
50 kO.
The external resistors should be of high quality and low drift,
such as wirewound resistors, since they will affect drift if
they do not track well with temperature: A 20 ppm/oC difference in external resistor temperature coefficient will introduce an additional 0.3 J.l.v/°C drift..
An unusually simple gain of 1000 instrumentation amplifier
can be made using the LM121. The amplifier has a floating,
full differential, high impedance input. Linearity is better than
1%, depending upon input signal level with maximum error
at maximum input. Gain stability, as shown in Figure 10, is
about ± 2% over a - 55"C to + 125°C temperature range.
Finally, the amplifier has very low drift and high CMRR.
For use with higher frequency op amps such as the LM118
the bandwidth may be increased to about 2 MHz. If closed
loop gain is greater than unity "C" may be decreased to:
C=
4
1()6 ACL RSET
APPLICATIONS
No attempt will be made to include preCision op amp applications as they are well covered in other literature. The previous sections detail frequency compensation and drift
problems encountered in using very low drift op amps. The
circuit shown in Figure 9 will yield good results in almost any
op amp application. However, it is important to choose the
operating current ·properly. From the curves given it is relatively easy to see the effects of current changes. High currents increase gain and reduce op amp effects on drift. Bias
and offset current also increase at high current. When the
operating source resistance is relatively high, errors due to
high bias and offset current can swamp offset voltage drift
errors. Therefore, with high source impedances it may be
advantageous to operate at lower currents.
Another important consideration is output common mode
voltage. This is the voltage between the outputs of the
LM121 and the positive power supply. Firstly, the output
common mode voltage must be within the operating common mode range of the output op amp. At currents above
10 /J.A there is no problems with the LM108, LM101, and
LM741 type devices. Higher currents are needed for devices with more limited common mode range, such as the
LM118. As the operating current is increased, the positive
common mode limit for the LM121 is decreased. This is
because there is more voltage drop across the internal SOk
load resistors. The output common mode voltage and positive common mode limits are about equal and given by:
1.04
'--T""",.-..,.--r-.--.-r-,-,
§ 1.02
f--I-+--+-+-t-f-t--t;;o..,
!c
I-+-++~'£..t""-I-+-+-I
s
i
1.00
",.
co
...
~CI
.98
V
1/
/'1'"
Va =.,5V
I<-t--I--+-+-+-+ f =300 Hz
>
-56 -35 -15 5 25 46 65 85 105 125
. TEMPERATURE ('CI
TL/H/7387-10
FIGURE 10. Instrumentation Amplifier
Gain vs Temperatura
Figure 11 shows a schematic of the instrumentation amplifier. The LM121 is used as the input stage and operated
open-loop. It converts an input voltage to a differential output current at pins 1 and 8 to drive an op amp. The op amp
acts as a current to voltage converter and has a single-ended output.
ReSistors R, and R2 with null pot R3 set the operating current of the LM121 and provide offset adjustment. R4 is a
fine trim to set the gain at 1000. There is very little interaction between the gain and null pots.
Ol,ltput common
( 0 . 6 5 X 50 kO)
mode voltage positive ~ V+ - 0.6V+
R
common mode limit
SET
If it is necessary to increase the common mode output voltage (or limit), external resistors can be connected in parallel
with the internal 50 kO resistors. This should only be done
at high operating currents (80 J.l.A) since it reduces gain and
diverts part of the input stage current from the internal bias-
R6
3M
1%
z~.
Z
+INPUT
LMI21
8
8
R5 3
~,..... J:-~~~~_=IOUTPUT
-......!.
5
S:~.
1% •
~ RZ
~
R3
..'0K
=
•• ~ 3M
50K
1%
~
-=J:'
1%
L
.•'
CI
30 pF
v-
·Offset adjust
tGain trim
*Better than 1% linaarlty for Input
signals up to ± 10 mV gain stability
typical ±2% from - 55'C to
+ 125"'C CMRR 110 dB.
TUH17387 -11
FIGURE 11. Gain of 1000 Instrumentation Amplifier
233
This instrumentation amplifier is IimHed to a maximum input
signal of ± 10 mV for good linearity. At high signal levels the
transfer characteristic of the LM121 .becomes rapidly nonlinear, as wHh any differential amplifier. Therefore,it Is most
useful as a high galn amplifier.
.
Since feedback is not applied around the LM121, CMRR is
not dependent on resistor matching. This eliminates the
need. for precisely mat9hed resistor as wHh conventional
instrumentation amplifiers. Although the linearity and galn
stabHitY are not as good as conventional schemes, this amplifier will find wide application where low drift and high
CMRR. are necessary.
A precision reference using a standard cell is shown in Figurs 12. The low drift and low Input current of the LMU1A
allow the reference amplifier to buffer the standard cell with
high accuracy. Typical long term drift for the LM121 operat-
ing at constant temperature is less than 2 p.V per 1000
hours.
To minimize temperature gradient errors, this circuit should
be shielded from alr currents. Good single-point wiring
should also be used. When power is not applied, His necessary to disconnect the standard cell from the Input of the
LM121 or it will discharge through the intemal protection
diodes.
CONCLUSIONS
A new preamplifier for operationS! amplifiers has been described. It can achieve voltage drifts as low as many chopper amplifiers without the problems associated with chopping. Operating current is programmable over a wid" range
so the input characteristics can be optimized for the particular application. Further, using a preamp and a conventional
op amp allows more flexibility than a single low-drift op amp.
r-----------------~---v+
11K
LM121
10K
D.1"
'STD +
CELL
OUTPUTS
.....~...........-+_-...........-v-
IUK
0.1"
TlfHf7387-12
FIGURE 12. 10V Reference
234
LM125
Precision Dual
Tracking Regulator
National Semiconductor
Application Note 82
INTRODUCTION
CIRCUIT DESCRIPTION
F/{JurB 1 shows a block diagram of the basic dual tracking
regulator. A voltage reference establishes a fixed dc level,
independent of supply or temperature variations, at the noninverting input to the negative regulator Error Amplifier. The
Error Amplifier drives the Output Control Circuit which includes the high current output transistors, current limiting,
and thermal shutdown circuitry.
The negative regulator output voltage is established by
comparing the Voltage Reference against a fraction of the
output as set by RA and Re. To achieve the desired tracking
action of the positive regulator, a voltage established between the positive and negative regulator outputs by resistors Rc and Ro is compared to ground by the positive regulator Error Amplifier. This insures that the positive regulator
output voltage will always equal the negative regulator output voltage multiplied by the unity ratio of Rc to RD. The
positive regulator Output Control Circuit is essentially the
same as that in the negative regulator.
The current limit and thermal shutdown circuitry sense the
output load current and cjie temperature respectively and
The lM125 is a precision, dual, tracking, monolithic voltage
regulator. It provides separate positive and negative regulated outputs, thus simplifying dual power supply designs. Operation requires few or no external components depending
on the application. Internal settings provide fixed output
voltages at ± 15V.
Each regulator is protected from excessive internal power
dissipation by a thermal shutdown circuit which turns off the
regulator whenever the chip reaches a preset maximum
temperature. Other features include both internal and external current limit sensing for device protection while operating with or without external current boost For applications
requiring more current than the internal current limit will allow, boosted operation is possible with the addition of a one
NPN pass transistor per regulator. External resistors sense
load current for controlling the limiting circuitry. Internal frequency compensation is provided on both positive and negative regulators. The internal. voltage reference pins is
brought out to facilitate noise filtering when desired.
POSITIVE
UNREGULATED
INPUT
---,
r--:-------I
I
I
POSITIVE
OUTPUT ....CONTROL
CIRCUIT
I
POSITIVE
. .- _ - 0 REGULATED
OUTPUT
lie
I
I
I
I
~
RD
I
I
NEGATIVE
Ht-;"--I-O REGULATED
OUTPUT
L-=- _______ _
_ _ _ .J
NEGATIVE
UNREGULATED
INPUT
FIGURE 1. Block Diagram for the Basic Dual Tracking Regulator
235
TLlHI7390-1
;r-----------------------------------------------------~
z
II(
~I'
RI3
RII
+
FIGURE ,2, Simplified Negative Regu"t~r
switch off all output drive capability upon reaching their predetermined limits.
Figuf'9 2 gives a mo~e detailed picture of the negative regulator circuitry. The temperature compensated reference
voltage appears at the non-inverting input of the differential
amplifier, 019 and 020, while an error signal proportion.1
TLlHI7390-2
in the positive regulator output will create an error signal at
the base of 010 which will be amplified and sent to the
voltage follower" Q4 and 05, forcing the output voltage to
track the input voltage. Here the loop gain is on the order of
66 dB so a compensating capacitor of approximately 20 pF
is used to ensure amplifier stability.
The circuitry used for regulator start up, blasing, temperature sensing, and thermal shutdown is shown in Figuf'9 4.
The' field effect transistor 028, is initially ON allowing the
negative input voltage to force current through zener diode
034. When 'enough current flows to fully establish the zener
voltage, transistor 029 .. 030 and,031 tum on and bias up all
current sources. The zener voltage also decreases the gate
to source voltage of the FET, pinching it off to a lower current value to reduce quiescent power dissipation.
The thermal sEinsing and shutdown circuitry is comprised of
034,029,035,032,037,038; R27,R29,R30, R31,and
R33. The voltage divider made up of R29 and R30 provides
a relatively fixed bias voltage VI at the bases of 035 and
036, holding them in the OFF state. When the chip temperature increases to a maximum permissible level, the base to
emitter voltage of 035 and/or 036 will have decreasedsufficiently so that V1 is now high enough to tum them ON. This
causes a voltage drop across R27 sufficient to tum on 032
which switches 037 and 038 to a conducting state shunting
all output drive current to - VIN. The regulator output voltages are then clamped to zero. Transistors 035 and 036
are located on the chip near the regulator output devices so
they will' see the maximum temperatures reached on the
chip, ensuring that neither regulator will ever see more than
this preset !!laximum temperature. The collectors of 035
and 036 are tied together so that if either regulator reaches
the ,thermal shutdown temperature, both regulators will
shutdown. This ensures that the device can never be destroyed because of excessive internal power dissipation in
either regulator.
Figuf'9 5 shows the current limiting circuitry used in the positive regulator; the negative regulator current limiter is identical. The internal current limiter is comprised of 08 and R5;
the external current limiter is comprised of 011 and an external resistor RCL. Both operate in a similar manner. As the
+VOUT '
-VOUT
TL/HI7390-3
FIGURE 3. Simplified Positive Regulator'
to any change In output voltage is applied to the otl1er input.
This error signal is amplified by the diff"rential' amplifier,
019 and 020, and by the triple Darlington 021, Q22, 023 to
produce a current change through R13 and R17 which
brings the output voltage back to its original value. Loop
gain is high, typically 88 dB at low output currents, so a
30 pF compensating capacitor is used to guarantee stability.
Since -VOUT is the output of a high gain feedback amplifier, high supply rejection is ensured.
Aguf'9 3 shows the basic positive regulator. This is actually
an inverting operational amplifier. The negative regulated
voltage (-VOUT) is applied to the current summing input
through R14 while the output (+VOUT) is fed-back via R9.
Then +VOUT is simply - (R9/R14) (-VOUT). Any ch(lrlge
236
+YIN
0-....--------,
-V,. 0-"--4'-----1""----""-"'--"'--"'-"'"
TLlH/7390-4
FIGURE 4. Start-up, BIasing and Thermal Shutdown Circuitry
output current through 05 increases. the voltage drop
across resistor R5 eventually turns ON
and shunts all
base drive away from the output devices. Q4 and 05. The
maximum load current available with this circuit is approximately 250 mA at Tj = 25°C (see Figure 9).
switched away from the output devices 04 and 05. This
externally set current limit Is particularly valuable when used
with an external current boosting pass transistor where the
current limit could be set to protect that transistor from excessive power dissipation.
The constant voltage reference circuit is shown in F/{Jure 6.
Zener diode Zl has a positive temperature coefficient of
known value. VeE of 018 (negative temperature coefficient)
is multiplied by the ratio of R18 and R19 and added to the
positive TC of Zl to produce a near zero TC voltage refer·
ence. Current source 12 is used only during start-up.
as
The external current limiting circuit works in a similar manner. Here the output current is sensed across the external
resistor RCL. When the voltage drop across RCL is sufficient.
to turn ON transistor all. the output drive current is
tV",
EXTERtliAL PASS
...--1....----0V.EF
TRANSl$TOR FOR
Boomo OPERATION
HI
RI
RaL
EXTERNAL
-V..
SENSE
TLlHI7390-6
TLlHI7390-5
FIGURE 6. Voltage Reference Circuitry
FIGURE 5. Positive Regulator Current Limiting Circuitry
237
N
i
F/fJure 7 shows the complete schematic of the LM125 dual
APPLICATIONS
regulator. Diodes 012 and 017 protect the output transistors, plus any external pass devices used, from breakdown
in the event the positive and negative regulated outputs become shorted. Transistors 06 and 07 offer full differential
voltage gain with the convenience of single ended output.
Transistors 013 and 033 insure that operation with ±30V
input is possible. 024 and 026 in the negative regl,llator
amplifier provide single ended output from a differential Input with no loss in gain.
The basic dual regulator is shown connected in Figure 8.
The only connections required other than plus and minus
inputs, outputs, and ground are to complete the output current paths from +RCL to +VOUT and from -RCL to -VIN.
These may be a direct shorts if the internal preset current
limit is desired, or resistors may be used to set the maximum
current at some level less than the internal current limit. The
internal 3000 resistors from pins 3 to 1 and pins 8 to 6
should be shorted as shown when no external pass transistors are used. To improve line ripple rejection and transient
response, filter capacitors may be added to the inputs, out-
r-----------~------------1f~--------------------~----1r--_,~4-o+VM
HS
us
L-___..._-+-=3:..o +BOOST
1----------------4-....---------1....:-0
-
+SENSE
-BOOST
, R3.
R30
.,5
L---~--~--~~~~--~~~~--~~~--~..._----------------------~-v.
Note: Pin numbets apply to metal can package only.
FIGURE 7. LM125
238
TLiH/7390-7
r--------------------------------------------------------------------,~
puts, or both, depending on the unregulated input available.
If a very low noise output voltage is desired, a capacitor may
be connected from the reference voltage pin to ground.
Thus shunting nOise generated by the reference zener. FI{IUfB 9 shows the internal current limiting characteristics for
the basic regulator circuit of FtgUfB 8.
HIGH CURRENT REGULATOR
For applications requiring more supply current than can be
delivered by the basic regulator, an external NPN pass tran·
sistor may be added to each regulator. This will increase the
maximum output current by a factor of the external transistor beta. The circuit for current boosted operation is shown
in FigUfB 10.
In the boosted mode, current limiting is often a necessary
requirement to insure that the extemal pass device is not
overheated or destroyed. Experience shows this to be the
usual cause of Ie regulator failure. If the regulator output is
grounded the p~ device may fail and short, destroying the
regulator. To limit the maximum output current, a series resistor (RCL in FtgUfB 1{]J is used to sense load current. The
regulator will current limit when the voltage drop across RCL
TL/HI7390-B
Note: Pin numbers for metal can package only.
FIGURE 8. Basic Dual Regulator
...
1.10
~~
T," -lii'C
S~
...
2!iC
......
\
...
.
~=
:B£i
...
T,"+12i'C
mill
....
IDO
T,"+ISC
0...
ILOAO-+mA
TUHI73BO-9
T," -!i&'C
V
I ]'"
II:
300
280
f1" I I I
I I II
T,"+I&II'C
...
T,"+IIII'C
t11 I I I
0
T,"+2rc
,..
:0 ..
'":0
I I I T1"
~
IIII
I III
1\
:;
,.. .. ....
T," +25'C
..91
Iii!:
II:
...
=!
!is
11111
:1;
:l!S
.....
UI
TN.JT
I I Ir'l
CD
•
I I TiIIII
lOG
200
ILOAO-+mA
(a)
(b)
FIGURE 9. Internal Current Limiting Characteristics
'---_-,..-0
...
LMI21
-v..
TANTALUM~
TUH/7390-11
FIGURE 10. Boosted High Current Regulator
239
TL/H/7390-10
J;
II.)
,I
~ r-----------------------------------------------------------------------------~
cp
~
equals the current limit sense voltage found in Figuf'8 J 1.
Figuf'8 12 shows the extemal:current .limiting characteristics
unboosted and Figul'8 ,13 showS'the external current limiting
The 2N3055 pass device is low in 'cost and maintains a
reasonably high beta !It collector 'currents up to several
amps. The devices 2N30S5 may be of either planar or alloy
junction constructiOn. The' planar creviCes, have a high for
providing more stable operation due to low p"ase shift. The
alloy devices, with for typically less than 1.0 MHz; may require additional .compensation to guarantee stability. The
simplest of compensation for the slower devices ,is to use
output filter capacitor values greater than 50 p.F (tantalum).
An alternative is to' use an RC filter to create a leading
phase response to ca(1cel some of the phase lag of the
devices. The stability problem with slower pass trimsistors,
if it occurs at all, is usually seen only on the negatIVe regulator. This is because the positiye regulator O~PLlt stage is a
conventional Darlington while the. negativEi output stage
contains three crevices: in a modified triple Darlington connection giving slightly more,. internal phjilse $hift. Additional
compensation may be added to the nagative regulator by
connecting a small capaCitor in the 100 pl;. range from the
negative boost terminal to the internal referepce. Since the
positive regulator uses the negative regulator output for a
reference, this also offers some additonal indirect compensation to the positive regulator.
characteristics in the boosted mode",
To ansum 'Circuit stability at high currents in this' configu;a..
tion, it may be necesSarY to bypass each inp\.1twith low
inductance, tantalum capacitors, to ,~event forming reso"
ne,nt circ,l,Iits with long, ,,,,put IElads. .A C :?; 1 p.F is recomniended:The same 'prOblem can also OCcur at th~ regulator
ol!lPut where a C :?;' 10 p.F te:nt8:l~m wiUe~sure stability and
increa~ rippl~rejectjon.
"
E G.IHIO
...~ O.BOO
...
I,
.
~,tI..?OO
1. 600
0:
""- "
i'v
~~OSITIVE REGULATOR
SENSE VOLTAGE f--
'"",
"
'
~ 0.500
... OADO
...::1z 0.300
'.,
,
r--..
,
r....
~
"
,"
I'
rN GAjlVE REGULATO~.,...
::0
SENSE VOLTAGE
~
.. '0;200
-50 -2~ 0 2&' &0 71 110 125 150 17&
7 AMP REGULATOR
In Figuf'8 14 tluil single'
~xternal p~ss tflinsistor has been
replaced by a conventional Darlington using a 2N3715 and
JUNCTION TEMPERATURE rCI
TLlH17390-12
FIGURE 11. Current Umlt Sense Voltage for a 0.1 %
c.hII~e In Regulated Outpu~ ,VOltage
1.0
0.1
E
w
a: ....
B.iI
.. ;:!:
!C ...
0.7
......
... ::0
a: ....
0.5
~i
0••.
I. :1\"\
,1.0
. I'
f-\
T.· -55°C
1
T.·+~ot
~. 0.9
r-
a:'"
c~!
...
::0>
.....
T,c+12&"C
T, = +150°C
OA
~~
.a:
a..
>::0
~;
0.3
......a:
c'"
...
>
0.2
2!g
2~
0.1
0
......
;::
,
'- Ret + = 1120
10
30
20
.
~~
...a:....
*0' 50" 60
ILOAD (mA)
70
0.8
0.7
0.6
0.5
,I
,
1
l"""
T',=+2&OC,
T, = +125·C
,-to
T, =+150'C
OA
0.3
0.1 f- Re~ 10
30
20
...
e~
0.•
:s::0>..
0.7
0.6
.
0.5
......
"'::0
:::1;
::
......
I
T, = -.55°C ....
T,' +25"C ....
T,=+125"C,
T,=+ISOoC,
0.3
...a:
0.2
50
80
,
70
TLlHI7390-14
(b)
, '".......... ,
-::-,.
1.0
~
a:'"
i'
0.8
0.7
0.6
,.~~
,8.5
.
...
I!:
>::0
;::
c'"
...
>
:I.f~
......a:
0.20 0.40 0.60 0.80 I.O~, 1.20 1:40
ILOAD (AMPS)
G.9
ce~
...
S
..
... >
0.1 t-I'I~L + • 0i611
0
40
ILOAD(mA)
TL/HI7390-13
'"
0.4
ill>
co-
.... !C...
I
\
\
f
FIGURE 12. External Current Umltlng Charecterl8tlcs-U~boosted
1.0
0.9
T
- 112r!
(a)
~
a:'"
\
\
\
0.2
0
,"
.;.!
TJ = -55°C
I
,
T, =+25°C
TJ • +12&OC .....
TJ "+I50°C,
t'o
\
OA
0.3
0.2
0.1 ~RCf"~60
0
TLlHI7390-15
I
T, - _&&OC
\
\
1
,
(b)
FIGURE 13. External Current Limiting Charecterlstlcs-Boosted
240
1
0.20 OAO 0.80 0.80 1.00 1.20 lAO
ILOAD (AMPS)
(a)
\
\
TLlHI7390-16
TLlHI7390-17
FIGURE 14. High Current Regulator Using a Darlington Pair for Pass Elements
a 2N3772. With this configuration the output current can
reach values to 10A with very good stability. The external
Darlington stage increases the minimum input·output voltage differential to 4.5V. When current limit protection resistoris used, as in Figure 14, the maximum output current is
limited by power dissipation of the 2N3772 (150W at 25"C).
During normal operation this is (VIN - VOUT) lOUT (W), but it
increases to V IN Isc (W) under short circuit conditions. The
short circuit output current is then:
avoiding the need for larger heat sink. Figure 15 !lhows a
fcildback current limiting circuit on both positive and negative regulators.
"
The foldback current limiting, a fraction of the output voltage
must be used to oppose the voltage across the current limit
sense resistor. Current limiting does not occur until the voltage across the sense resistor is higher than this opposing
voltage by the amount shown in Figure 11. When the output
is grounded, the opposing voltage is no longer present so
current limiting occurs at a lower level. This is accomplished
in Figure 15 by using a programmable current source to give
a constant voltage'drop across A5 for the negative regula·
tor, and by a simple resistor divider for the positive regulator. The reason for the difference between the two is that
the negative regulator current limiting circuit is located between the output pass transistor and the unregulated input
while the positive regulator current limiter is between the
output pass transistor and the regulated output.
The operation of the positive foldback circuit is similar to
that described in NSC application note AN-23. A voltage
divider A1 and A2 from VE to ground creates a fixed voltage
drop across A1 opposite in polarity to the drop across
ACL + . When the load current increases to the point where
the drop across ACL + is equal to the drop across A1 plus
the current limit sense voltage given in Figure ", the positive regulator will begin to current limit. As the positIVe output begins to drop, the voltage across R1 will also decrease
so that it now requires less load current to produce the cur-
PMAX (TC = 25"C)
Isc = -"'''-''-'-'-:-''---VIN
=
150W = 7.5A max.
20V(min)
IL could be increased to 10A or more only if IsC < IL. A
foldback current limit circuit will accomplish this. The typical
load regulation is 40 mV trom no load to a full load. (Tj =
25"C; pulsed load with 20 ms toN and 250 ms toFF)'
FOLDBACK CURRENT LIMITING
In many regulator applications, the normal operation power
dissipation in the pass device can easily be multiplied by a
factor of ten or more when the output is shorted. This may
destroy the pass device, and possibly the regulator, unless
the heat sink is oversized to handle this fault condition. A
foldback current limiting circuit reduces short circuit output
current to a fraction of the full load output current thus
241
-+---+v'N
. . _ - - - - -...--"""'1....
~~~)_---~~-~~-------~+V~
R3
Uk
AI
3GB
+13
' - - _......-
. .--"""'1...- - - . -VIN
C4
IpF
TANTALUM
-r.-:If
112-03: 2N284D
TlIH/7390-18
FIGURE 15. Foldback Current Umltlng Circuit
rent limit sense voltage. With the regulator outpl!t ~ully shorted to ground (+ VOUT = 0) the current limit will be set by
the value of + RCL alone.
If
Note: The current from the internal 3000 resistor is V3-11
3OOQ. but V3-1 =. VBE + VRCL -VSENSE+ assuming VBE
::: VSENSE+ at the foldback pOint. V3-1 ::: VRCL + = IFB
RCL+'
.
Design example: 2 amp regulator LM125 positive foldback
current limiting (see Ftgure 15).
Given:
IFB~5
Isc
.
then the following equations can be used for calculating the
positive regulator foldback current limiting resistors.
RCL + = VSENSE
Isc
when~ VSENSE is from Ftgure 11.
At the maximum load current fol\1back point:
VRCL + = IFB RCL +
VRI = VRCL + - VSENSE
VRI = IFB RCL + - VSENSE
Then
IFOL.DBACK = 2.0A
ISHORT-CIRCUIT = 500 mA
VSENSE (See FiguitJ 11)
+VIN = 25V
+VOUT = 15V
/3PASS DEVICE = 70
6JA = 15O"CIW
fA = 5O"C
With a
of 70 in the pass device and amaxi,num output
current of 2.0A the regulator must deliver:
(1)
(2)
(3)
(4)
beta
(5)
2A=2A=29mA
/3
70
The LM125 power dissipation will be calculated ignoring any
negative output current for this example.
PLM125 = (VIN - VOUT) lOUT
=(25 - 15) 29mA
= 290mW
TRISE@ 6JA = 15O"C/W = 150"C x 0.29 = 44°C
TJ = TA + TRISE = 50"C + 44°C = 94°C
and
R2= +VOUT + VSENSE
(6)
11
The only point of caution is to ensure that the total current
(11) through R2 is much greater than the current contribution
from the internal 3000 resistor. This can be checked by:
. IFE! RCL +
300
<< I
(7)
1
242
For calculating the maximum full load current with the output still in regulation. current 12
From Figuf6 11:
VSENSE @ (TJ = 94°C) = 520 mW
From equation (1)
I - VOUT - VBEQI
2R3
RCL + = VSENSE = 520mV "" 10
Isc
500mA
From equation (2)
At the point of maximum load current. IFB. where the regulator should start folding back:
(10)
VRCL + = IFB RCL + = (2A)(10) = 2V
From equation (3)
and
(11)
VRI = VRCL + - VSENSE
VRI = 2V - 520 mV = 1.480V
A value for 11 can now be found from equation (7)
IFB RCL +
300
=
=
2A x 10
3000
6.6
The current through 02 (and 03) will have increased from 12
by the amount of 14 due to the voltage VI increasing above
its no-load quiescent value. Since the voltage across 02 is
simply the diode drop of a base-emitter junction:
A
m
14 =
6.6 mA = 66 mA
From equations (S) and (6)
So set 11
= 10 x
I - IFB RCL - - VBE
4 R4
R = +VOUT + VSENSE = 1S + 0.520 '" 240
2
11
66mA
0
14
12
...
10
~
co
>
•.0
I;
6.0
co
4.0
I!:
::>
2.0
'II
'II
I
TI =+125"
1L
ITI - 55"C_ r - -
II
r-- 0.5
26"C -
1.0
lOUT
VSUPPLV • ±lOV
1.5
2.0
Is = 15 + 16 - 17
The drop across RS is found from:
(14)
I - IFB RCL - - VSENSE
sRS
2.&
(AMPS)
(16)
Summing the currents through 03 is now possible assuming
the base-emitter drop of the 2N30S5 pass device can be
given by VBE :::: VSENSE:
TL/HI7390-19
FIGURE 16. Positive Regulator Foldback
Current Limiting Characteristics
I - Vs - V2
The negative regulator foldback current limiting works essentially the same way as the positive side. 01 forces a
constant current. 12. determined by -VOUT and R3. through
02. Transistors 02 and 03 are matched so a current identical to Is will flow through 03. With the output short-circuited
(-VOUT = 0). 01 will be OFF. setting 12 = O. The load
current will be limited when VI increases sufficiently due to
load current to make V2 higher than -V'N by the current
limit sense voltage.
The short circuit current is:
I
'" VSENSE
SC
RCL-
(13)
VI - V2 = IFB RCL - - VSENSE
(1S)
Since VSENSE is the base to emitter voltage drop of the
intemallimiter transistor. the VSENSE in equation (1S) very
nearly equals the VBE in equation (12). Therefore the drop
across RS approximately equals the drop across R4. The
current through R5. Is. can now be determined as:
"L,
'II
I
Is = 12 + 14
and the current through 03 is:
VI - V2 = (-V'N + IFB RCL -) - [VSENSE + (-V,N)l;
simplifying.
1'1
II
II
_
(12)
IFB RCL - - VBE
3000
The current through 02 is now
The foldback limiting characteristics are shown in Figuf6 16
for the values calculated above at various operating temperatures.
16
......
[VI - (-V,N)] - VBe
R4
Substituting in equation (10) gives:
R1 = VRI = 1.480V "" 220
11
66mA
~
(9)
6
---aiiil"
(17)
where Va = VI + VBE :::: VI + VSENSE
I - VI + VSENSE - V2
6 300
Substituting in equation (1S)
I = IFB RCL6
300
I - V2 - (-V'N) _ VSENSE
7 R6
-1'iS"
(8)
243
(18)
,.
Equating equation (1S) with equation (14) and inserting resistor values shown in Figuf8 15,
12 + 14 = 15 + Is - 17
I + IFB RCL - - VSENSE
2
SOO
,.
...
.
CD
~
(19)
>
8.D
..
8.0
5
~
Canceling, we find:
::>
(20)
I
o
r~
I
,
IT ~
.,
7
I
I
II
4.0
Z.o
T~is is the key to the negative foldback circuit Current
source 01 forces current 12 to flow through resistor R5. The
voltage· drop across R5 opposes the normal current limit
sense voltage so that the regulator will not current limit until
the drop across RCL - due to load current, equals the controlled drop across R5 plus VSENSE (given in FlfJuf8 11).
This can be written as:
-
I - - Tj -+1ZS"C
12 I - - I-.T.-+Z&oc r;.;:..
I - - .T. = -&l·C·
I--
~
I + IFB RCL - ~ VSENSE
5
SOO
SOO
12 = 15
~
14
7
~
1"
I'
V,N =±Z5V
o
O.S
1.0
1.& Z.O
IQUT(A)
2.S
3.0
TUHI7390-20
FIGURE 17. Negative Regulator Foldback
Current Umltlng Characteristics
A design example is now offered:
FlfJuf8 16 and 17 show the measured foldbeck characteristics for the values derived in the design examples. The value of RS is set low so that the magnitude of 15 for foldback is'
greater than 14 through 16. This reduces the foldback point
sensitivity to the TC 6f the internal soon resistor and any
mismatch in the TC of 02, OS or the pass device.
Given:
RS can be computed from equation (18):
I
FB=
VSENSE + 12 R5
RCL-
(21)
I
VSENSE + 2001 2
FB=
RCL-
RS = VSENSE- = VSENSE17
15+16-13
combining (1S) and (20).
IFOLDBACK = 2.5A
ISHORT.CIRCUIT = 750 mA
VSENSE (See Figuf8 11)
RS = VSENSE16 -14
-VIN = 25V
-VOUT = -15V
/JPASS DEVICE = 90
8JA = 150"C/W
(22)
1
')
VBE
IFB RCL - ( SOO - R4 +
'R4
TA = 25°C
Setting VBE '" VSENSE and R4 = SOO to match the internal
soon (22) becomes:
The same calculations are used here to figure VSENSE as
with the positive regulator foldback example maximum regulator output current Is calculated from:
lOUT =
2.SA
90 =
RS= R4
Also setting
28mA
PLM12S = (VIN - Vo) lOUT
= 10V x 28mA
Is
S
-+ A5 = 200
A 10 AMP REGULATOR
FigUf8 18 Illustrates the complete schematic of a 10A regulator with fold beck current limiting. The design approach Is
similar to that of the 2A regulator. However. in this deSign,
the current contribution from the internal soon resistor is
greater due to the 2 VBE drop across the Darlington pair.
Expression (7) becomes:
= 280mW
T RISE = 1S0°C/W
~= ~
x 0.28W = 42°C
TJ = TA + TRISE = 25°C + 42"C = 67"C
From Figuf8 11:
VSEN.SE = 500 mV
IFB RCL + + VBE
SOO
From equation (8):
500mV
RCL - = 750 mA = 0.68n
<< .
1,.
(2S)
and. for the negative regulator. expreSsion (22) becomes:
RS =
From equation (21):
VSENSE-
.
-.!..] + VBE [_'_
+ -.!..]
SOO
R4
IFB RCL - [_'_ SOO
R4
I = IFB RCL - - VSENSE = SOmA
2
200n
.
From equation (9):
RS = VOUT - VBEQ1
12
RS""~=2
k
S.OmA
.4
244
(24)
+ I~F
-=!="
TANTALUM
4
R2
120
.....-+-------:-0...
R3
0() VOUT
900
~+-~-------------t_-_4~--~~-VO~
Q4
2SOilF
2N2890
TANTALUM
'Ji
300
!.Ok
12! ~
&
- -
~ I.
5
I.
LM125
V2
I.
R5
200
R&
~ 13
130
17~
13!
ReL
L - -...- - -. .- - - -. .--~t_--+-V,N
TLfHI7390-22
FIGURE 18. 10A Regulator with Foldback Current Limiting
The disagreement between the theoretical and experimental values for the negative regulator is not alarming. In fact
RCl was based on equation (8), which is correct if for zero
VOUT, 15 Is zero as well. This implies:
VSENSE (at SC) =
VSEQ~ ;
150
TA
R
25°C
Y,N -ZZV
120
f-- POSlTIV~IOE
VSEQ5 (at SC)
90
r-
VOUT E!!15V
I Fa -lOA
1..,-=2.9A
Isc' -2.9A
.¥r
which is a first order approximation.
Figure 19 illustrates the power dissipation in the external
power transistor for both sides. Maximum power diSSipation
occurs between full load and short circuit so the heat sink
for the 2N3772 must be designed accordingly, remembering
that the 2N3772 must be derated according to O.86WI"C
above 2SoC. This corresponds to a thermal resistance junction to case of 1.17"C/W.
60 jiiI'~ NEGATIVE SIDE
30
5.0
10
15
VOUT
TLfHf7390-21
FIGURE 19. Power Dissipation In the
External Pass Transistor (Q5, Q7)
245
Example
Positive Side
IFB = lOA
ISC = 2.5A
1125 = 13mA
IFB = 9.8A
Isc = 2.9A
PLM125 =:= 150 mW
RCL+ = 0.260
Rl = '210
VIN = 22V
VOUT = 15V
~ = ~1 ~2 = 15
TA = 25°C
x 50 =
Experimental Resulta
Theoretical Value
750 min
Negative Side
RCL + = 0.280
R1: adjusted to 200
, R2: adjusted to 1200
R2 = 1300
VSENSE+ = 650 mV ,
Theoretical Value
IFB = 10A
Isc = 2.5A
VIN = 22V
RcL - = 0.220
R4 = 3000
R5 = 2000
VOUT = 15V
~ = 800
R6 = 1500
R3 = 1.6kO
TA = 25°
VSENSE- = 550 mV
experimental Resulta
IFB = 10A
Isc = 2.9A
RCL: adjusted to 0.30
R6: adjusted to 1300
R3: adjusted 9000
~=~
15
3
Note: For this example. in designing each aida, the power dissip8tion of the opposite ,aida has not been taken into'the aocount.
The following design equations may be used:
POSITIVE CURRENT DEPENDENT SIMULTANEOUS
CURRENT LIMITING
The LM 125 uses the negative output as a reference for the
positive regulator. As a consequence, whenever the negative output current limits, the positive output follows tracks
to within 200-800 mV of ground. If, however, the positive
regulator should current limit the negative output will remain
in full regulation. This imbalance in output voltages could be
a problem in some supply applications.
'
As a solution to this problem, a simultaneous limiting
scheme, dependent on the positive regulator output current,
is presented in Ftguf'82O. The output current causes an I-R
drop across R 1 which brings transistor 01 into conduction.
As the 'Positive load current increases 11 increases until the
voltage drop across R2 equals the negative current limit
sense voltage. The negative regulator will then current limit,
and positive side will closely follow the, negative output
down to level of 700-800 mY. For VOUT+ to drop the
final 700-800 mV with small output current change, RCL +
should be adjusted so that the positive current limit is slightly larger than the simLlltaneous limiting. Ftguf'821 illustrates
the simUltaneous, cUrrent limiting of bOth sides. '
R1 ICL + = R311 + VBEQl
11 = VSENSER2
Combining (25) and (26),
R3
R2 VSENSE- + VBEQl
ICL + = ----=R:7
1- - -
(25)
(26)
(27)
with
R + - VSENSE+
CL - 1.11CL +
(28)
The negative current limit (independent of ICL +) can be set
at any desired level.
I - - VSENSE- + VOIOOE
CL "'RCL-
a
(29)
Transistor 02 turns off tI;1e negative :pass ~risistor during
,,
simultaneous current limiting. '
246
+
l~f
~TANTALUM
Al
4
V,
+VIN
+BOOST
!I,
+RCL
300
+SENSE
+
lD
GNO
+VOUT
I~F
TTANTALUM
-=
-VOUT
-BOOST
300
-RcL
LM126
'¥'
I~F
TANTALUM
-V'N
TLIH/7390-23
FIGURE 20. Positive Current Dependent SlmuHaneous Current Umltlng
16
"
14
~
12
CD
10
...
=:...
'"...
:>
Tj = + 12SoC--
'-
8.0
::I
8.0
'"
4.0
I!:
::I
used. The simplest is to insert a relay, a saturated bipolar
device, or some other type switch in series with either the
regulator inputs or outputs. The switch must be able to open
and close under maximum load current which, may be several amps.
As an alternate solution, the internal reference voltage of
the regulator may be shorted to ground. This will force the
positive and negative outputs to approximately + 700 mV
and + 300 mV respectively. Both outputs are fully active so
the full output current can still be supplied into a low impedance load. If this is unacceptable, another solution must be
found.
±vw = ±3OV
RCL + - D.58n
Rl = l.On
j=
+25"&--
Tj=
55"C-
2.0
0.&
1.0
1.5
2.0
The circuit in Ftgure 22 provides complete electronic shutdown of both regulators. The shutdown control Signal is TTL
compatible but by adjusting A8 and A9 the regulator may be
shutdown at any desired level above 2 VeE. calculated as
follows:
2.5
POSITIVE OUTPUT CURRENT (AMPS)
Tl/H/7390-24
FIGURE 21. Positive Current Dependent
Simultaneous Shutdown
vT ""
ELECTRONIC SHUTDOWN
In some regulated supply applications it is desirable to shut·
down the regulated outputs (±Vo = 0) without having to
shutdown the unregulated inputs (which may be powering
additional equipment). Various shutdown methods may be
[R8~ 04 +
A3
A9]
R3 VeE
+ 2 VeE
(30)
Positive and negative shutdown operations are similar.
When a shutdown signal VT is applied, 04 draws current
through A3 and 02 establishing a voltage VR which starts
247
YIN
IpF
+
TANTALU,M~
,
RI
R3
70
10
4
10
YT SHUTDOWN
teJV\I\I_:l CONTROL
INPUT
RI
70
FOR VT >2.IV"
6'
'--+----...---.-----O-YOUT --I&Y
RIZ
2&0
-Y,N --3DV
+EL_
I,..F
TANTALUM
'For higher values of Cl increu.. R6 to IimH the 'peak current through Q5 to ~ safe value,
FIGURE 2;2. Electronic, Shutdown for the B~osted Regulator
248
TL/H/7390-25
tor 04. Also using Figure 23 the diode Dl in Figure 22 may
be omitted. The shutdown characteristics of Figure 22 are
shown in Figure 24.
the current sources Ql and Q2. Assuming that Ql and Q2
are:matched, and making Rl = R2 = R3, the currents I"
12, 13 are equal and both sides of the regulator shutdown
simultaneously.
The current 13 creates a drop across R5, which equals or
exceeds the limit sense voltage of the positive regulator,
causing it to shutdown. Since 13 has no path to ground except through the load, a fixed load is provided by Q5, which
is turned on by the variable current source Q4, Cl also dIscharges through Q5 and current limiting resistor RS. ResIstor R4 prevents Q3 tum on during shutdown, which could
otherwise occur due to the drop across R5 plus the internal
300n resistor. Diode D3 prevents 13 from being shunted
through RCL.
C2 discharges through the load. Q7 shares the total supply
voltage withQ2, thus limiting power dissipation of Q2. Another power dissipation problem may occur when the design
is done for VT .= 2.0V for example, and VT is increased
above the preset threshold value. 1, is increased and Q4
has to diSSipate (VIN - 3 VeE - VT) 1, (W). The simplest
solution is to increase R8. If this is insufficient, a set of diodes may be added between nodes A and B to clamp, 1, to'
a reasonable value. This is illustrated in FlfJure 23:
15
~
J.,
5.0
1.0
RI
-.;HI
R7
I
VA9
1
1
.....0
=R9"'"
3.0
4.0
5.0
TLIH/7390-27
FIGURE 24. Electronic Shutdown Characteristics
The normal current limiting current is set by equation (31)
ICL = VSENSE + VOIOOE
(31)
RCL
The same approach is used with the unboosted regulator
shown in Figuf'fJ25. In this case the voltage sense resistor is
the internal 300n one. Since output capacitors are no longer required Q3 is just used as a current sink and its emitter
load has been removed .
!I,
OA
2.0
VT(Vl
I = VR9 ~ VT - VeE - IVT - 2 VeE] = VeE
1
R9 R9
R9
......
.......
..... .....
Tj =+125·C
10
POWER DISSIPATION
The power dissipation of the LM125 is:
HI
2.2k
VT
VT - VBE - (VT - 2 VBE)
VBE
R9
R9
Pd = (VIN+ - VOUT+) IOUT+ + (VIN- VOUT-) IOUT- + VIN+ Is+ + VIN- Iswhere Is is the standby current.
Ex: ± 1A regulator using 2N3055 pass transistors. Assuming a f3 = 100, and ±25V supply,
TLlHI7390-26
Pd = 400mW.
The temperature rise for the TO-5 package will be:
FIGURE 23
So 11 is made independent of VT and by setting a minimum
value of 10 mA (R9 = 70n). The regulator will shutdown at
any desired level above 3 VeE, without overheating transis-
TRISE = 0.4 X 1500C/W = 6O'C
Therefore the maximum ambient temperature is TAMAX =
TjMAX - T RISE = 900C. If the device is to operate at TA
above 900C then the TO-5 package must have a heat sink.
T RISE in this case will be:
TRISE = Pd (BJ.C
249
+ Bc-s + Bs.M·
N
C!p
r-----~----------------~~--------------------------------------------~
~
Y,N =27V
01
iN914
VOUT -15V,
2
VT
--.r
10
8
REF
-
100
-VOUT --15V
8
5
LM125
-V'N ~-27V
11'F
~ANTALUM
l
TUHI7390-28
FIGURE 25. Electronic Shutdown for the Basic Regulator
250
~
National Semiconductor
AppUcation Note 87
Interface
Development Group
Comparing the High Speed
: Comparators
INTRODUCTION
Several integrated circuit voltage comparators exist which
were designed with high speed and complementary TTL
outputs as the main objectives. The more common applications for these devices are high speed analog to digital (A to
D) converters, tape and disk-file read channels, fast zerocrossing detectors, and high speed differential line reeeivers. This note compares the National Semiconductor devices to similar devices from other manufacturers.
The product philosophy at National was to create pin-for-pin
replacement circuits that could be considered as secondsources to the other comparators, while simultaneously
containing the improvements necessary to make a more op-
timum device for the intended usage. Optimized parameters
include speed, input accuracy and impedance, supply voltage range, fanout, and reliability. The LM160/LM2601
LM360 are replacement devices for the pA760, while the
LM161/LM261/LM361 replace the SE/NE529. Tables I and
II compare the critical parameters of the National commercial range devices to their respective counterparts.
SPEED
Throughout the universe the subject of speed must be approached with caution; the same holds true here. Speed
(propagation delay time) is a function of the measurement
TABLE I. LM360/I'A760CComparilOnO"C";; TA";; +70"C, V+
Parameter
=
+5.0V, V-
=
-5.0V
LM360
I'A76OC
Input Offset Voltage
5.0
6.0
Units
mVmex
Input Offset Current
3.0
7.5
I'Amex
Input Bias Current
20
60
pAmex
Input CapaCitance
4.0
8.0
Input Impedance
17
5.0
pFtyp
kG typ
@
1 MHz 25°C
Differential Voltage Range
±5.0
±5.0
v,typ
Common Mode Voltage Range
±4.0
±4.0
Vtyp
Gain
3.0
3.0
VlmVtyp25°
Fanout
4.0
2.0
74 Series TTL Loads
Propagation Delays:
(1) 30 mVp-p 10 MHz Sinewave in
25
30
nsmex25"
(2) 2.0 Vp-p 10 MHz Sinewave in
20
25
ns mex 25°
(3) 100 mV Step + 5.0 mV Overdrive
14
22
nstyp 25°
TABLE II. LM261/NE529 ComparilOn O"C ,,;; TA";; +70"C, V+
Parameter
=
+10V, V-
=
-10V, Vee
=
+5.0V
LM261
NE529
Input Offset Voltage
3.0
10
mVmex
Input Offset Current
3.0
15
I'Amex
Input Bias Current
20
50
Input Impedance
17
5.0
Units
pAmex
kG typ
@
1 MHz 25"C
Differential Voltage Range
±5.0
±5.0·
Common Mode Voltage Range
±6.0
±6.0
Gain
3.0
4.0
VlmVtyp25°
Fanout
4.0
6.0
74 Series TTL Loads
Propagation Delay - 50 mV Overdrive
20
22
nsmex25°
251
Vtyp
Vtyp
~ r-----~----------------------------------------------------------------------~
,',:~Chntque. The earlier "standard" of using a 100 mV input
Jarge, result\ng.in a complete switch of inpulbias current as
Step With 5.0 mV overdrive has given way to seemingly endtile Input signal. traverses the reference voltage level. This
"I~ss,variations. To be meaningful, speed comparll!Ons must
effect can give rise to redl.!ced gain and threshold inaccura, 'be made with identical conditions. It ,is for this reason that
cy, dependent on input source impedances arid comparator
the speed conditions specified for the National parts are the
input bias currents. Tables I and II show that the National
parts have a substantially lower maximum bias current to
same as those of the parts replaced.
ease this problem. This was done without resorting to DarProbably the most impressive speed characteristic of the six
lington input stages whose price is higher offset voltages
National parts is the fact that propagation delay is essentialand longer delay times., The lower bias currents also raise
ly independent of input oVliIrdrive (Figure 1); a I)ighly desirinput resisJance in the threshold region. Lower input capaciT! 2~~J~III
I I 11111
~nce and higher input resistance result in higher input im-i-pedance at high frequencies.
'
Vee
-+6V
]
LOAO-2.0kn
Even ,~ith low source impedances, input accur~cy, is still
>
c
TO Vee +I,&pF TOTAL
dependent on offset voltage. Since none of the devices under discussion has internal offset null capability, ultimate ac14
curacy was improved by designing and specifying lower
maximum offset voltage. Refer to Figure 3 for typical offset
~
CII
'voltage drift with temperature~
I"
:f IZ
i
I. I.
.........
'"
...
1.0
10
S
..!
1.0
,3.0
10
30
300,
100
...
...;:!:...>
Iii......
......
..
1000
CD
DIFFERENTIAL INPUT OVERDRIVE (mV)
TLlHf7407-1
FIGURE 1. Delay V8 Overdrive
able characteristic in A to 0 applications. Their delay typically varies only 3 ns for overdrive, variations of 5.0 mV to 500
mV, whereas the other parts have a corresponding delay
variation of two to one. As can be seen in Tables I and II,
the National parts have an improved maximum delay specification. Further, the 20 ns maximum delay is meaningful
since it is sPecified with a representative load: a 2.0 kO
resistor to + 5.0V and 15 pF total load capacitance. Figure
2 shows typical delay variation with temperature.
:1
>
c
.
.....
......
5!
'"
!C
.1uJ
24
V~
20
LoAD-2.oka
TO Vee +15 pF TOTAL
VIN •• 50 mV PULSE
16
:f
12
8.0
-&&
..... .....
--16
,I
1
,
I
:0
0.6
OA
V
0.2
0
-D.2
-0.4
...... '"
i!! -0.6,
-D••
-65
-16
V
/
V
66
2&
12&
TA ('C)
TL/H/7407-3
FIGURE 3. Offset Temperature CoeffiCient
/
,
,
D••
OTttER PERFORMANCE AREAS
In the case of the LM160/LM260/LM360, fanout was doubled over the previous device. For the LM1611LM2611
LM361 , operating supply voltage range was extended to
J
/t"o,- ,.T
7.0 1Ir-r-:lO~~~~~~
tpdO-= I,..o!
I
26
TA
6&
12&
('CI
TL/Hf7407-2
FIGURE 2. Delay V8 Temperature
INPUT PARAMETERS
The A to 0, level detector, and line receiver applications of
these devices re,quire good input accuracy and impedance.
In all these cases the differential input voltage is relatively
1.0
•.0
y+
,11
13
, 15
OR V- (tVI
TLlH/7407-4
FIGURE 4. LM161 Common Mode Range
± 15V op amp supplies which are often readily available
where such a comparator is used. Figure' 4 reveals the common mode range of the latter device.
252
The performance improvements previously mentioned were
a result of circuit design (Figures 5 and 6) and device processing. Schottky clamping, which can give rise to reliability
problems, was not used. Gold doping, which results in processing dependent speeds and low transistor beta, was not
used. Instead a non-gold-doped process with high breakdown voltage, high beta, and high fT (:::: 1.5 GHz) was se-
lected which produced remarkably consistent performance
independent of normal process variation. The higher breakdown voltage allows the LM161/LM261/LM361 to operate
on ± 15V supplies and results in lower transistor capacitance; higher beta provides lower input bias currents; and
higher fT helps reduce propagation time.
r---------------------~f_~~ROBEI
r-----------~~~------f_--~--------_t--~v~
.--------~--o() OUTPUT 1
L---~--------~--OGNO
r-----------------------e---OSTROBE2
..--+-----t--() OUTPUT 2
+ INPUT 1
-INPUT2~----_+----~
v-o---~.-------~~~------~--------------------~--~
FIGURE 5. LM161 Schematic Diagram
253
TLlHI7407-5
.1.
,'" "
NON·
...-----~ INVERTING
OUTPUT 1
L...-4~-----O() 8NO
+INPUT 1
-INPUTZ 0 - - -.....- - . . 1
v-o---~------~~~----~~----------------~--~
Tl/HI7407-6
FIGURE 8. LM180 Schematic Diagram
tended for interfacing to TIL Iogic~ direct connection may
. be made to EeL logic from the LM161 by the technique
shewn in Figure 9. When used this way the common mode
range is shifted from that of the TIL configuration. Finally
level detectors or line receivers may be implemented with
hysteresis in the transfer characteristic as seen in F/(Jure 10.
APPLICATIONS
Typical applications have been mentioned previously. The
LMl60 and LM161 may be combined as in F/(Jure 7to ere·
ate a fast, accurate peak detector for use in tape and diskfile read channels: A 3-bit Ato 0 converter with 21 ns typical
conversion time is shown in Figure 8. Although primarily in-
254
v," 0-------1
INPUT IVINI--.....~-+-+-I---"'---
V'No-. .----I/~----~
VOUT - - - - - - ;
TLlHI7407-7
FIGURE 7. Peak Detector
~--------~+~+~------,
"
R2
BCD
.J
••
A:~~: o-+----ir--I
:-...:......- - -.....--++----+----oMSI OUTPUTS
.5
LSB
.B
.J
50
.,
..
TL/HI7407-B
FIGURE 8. High Speed 3·blt A to D Converter
255
~ r-------------------------~------------------------------------------------~
~
iCC
-&.2
-10V
TLlHI7407-9
FIGURE 9. Direct Interfacing to EeL
Rl
+
v·l
R4
C-HR(lJ2\r-t-f
TLlHI7407-10
,
, VLT
=
VOL
(R2)
R1 -
VOH
(R4)
R3
FIGURE 10. Level Detector with Hysteresis
256
National Semiconductor
Application Note 88
CMOS Linear Applications
PNP and NPN bipolar transistors have been used for many
years in "complementary" type of amplifier circuits. Now,
with the arrival of CMOS technology, complementary
P·channellN-channel MOS transistors are available in
monolithic form. The MM74C04 incorporates a P-channel
MOS transistor and an N-channel MOS transistor connected in complementary fashion to function as an inverter.
Due to the symmetry of the P- and N-channel transistors,
negative feedback around the complementary pair will
cause the pair to self bias itself to approximately 1/2 of the
supply voltage. F/{JIJre 1 shows an idealized voltage transfer
characteristic curve of the CMOS inverter connected with
negative feedback. Under these conditions the inverter is
biased for operation about the midpoint in the linear segment on the steep transition of the voltage transfer characteristics as shown in Figure 1.
Rl
TL/F/6020-2
FIGURE 2. A 74CMOS Inverter Biased for
Linear Mode Operation
istics. If the input Signal approaches the supply voltages, the
P- or N-channel transistors become saturated and supply
current is reduced to essentially zero and the device behaves like the classical digital inverter.
15
15
:. 12.5
>=
I-
r
...c
.......
...'">
......
'"'"
w
7.5.-----~------I
I--
10
:::t1\
s&Oe
S5°e
I
7.5 - 1 2 )
/
.~
:>
5.0
2.5
"'" /s5°e
\
/
12soe
•
Vee = 15V
2.5
15
5.0
"- "
7.5
"
10
12.5
15
INPUT VOLTAGE - VI.
INPUT VOLTAGE - VII
TUF/6020-3
TL/F/S020-1
FIGURE 1. Idealized Voltage Transfer
Characteristics of an MM74C04lnverter
FIGURE 3. Voltage Transfer Characteristics for an
Inverter Connected as a linear Amplifier
Under AC Conditions, a positive going input will cause the
output to swing negative and a negative going input will
have an inverse effect. Figure 2 shows 1/6 of a MM74C04
inverter package connected as an AC amplifier.
Figure 3 shows typical voltage characteristics of each inverter at several values of the Vee. The shape of these
transfer curves are relatively constant with temperature.
Temperature affects for the self-biased inverter with supply
voltage is shown in Figure 4. When the amplifier is operating
at 3 volts, the supply current changes drastically as a function of supply voltage because the MOS transistors are operating in the proximity of their gate-source threShold voltages.
The power supply current is constant during dynamic operation since the inverter is biased for Class A operation. When
the input signal swings near the supply, the output Signal will
become distorted because the P-N channel devices are
driven into the non-linear regions of their transfer character-
257
t:
i-.
I
.
1.
........._______-'-.,.-_......__......_-,
Poat AmplifIer for Op .Amps,
for a Post Amplifier has several advantages. The operatiQnai amplifier essentially sees no load condition since the input impedance to the Inverter is very high. Secondly, the
CMOS inverters will swing to within millivolts of either supply. This gives the designer the advantage of operating the
operational amplifier !lnder no load conditions yet, having
the full supply.~ng capability on thEi output. Shown,in Figure 7 is the LM4250 micropower Op Amp used with a.74C04
inverter for increased output capability while maintaining the
low power advantage of both device~.
, 'II!
B
~
1.0
~
"
j
=
. ".
f.. standard operationai ~mplifier used with a CMOS inverter
o.t,-::_=-_-=-_-!:-_-=_~:---:!~~!-:-~
-15
-SO
-26
25
611
15
loa
126
TEMPERATURE
+UV
+UV
TL/F/6020-4
FIGURE 4. Normalized Amplifier Supply Current
Versus Ambient Temperature Characteristics
Figure 5 shows typical curves of voltage gain as a funCtion
of operating frequency for various supply voltages.
Output voltages can swing within millivolts 'of the supplies
with either a single or a dual supply.
v,,-uv
50
-i
1M
TUF/6020-7
,
Po
I
:::
~
= 500nW
FIGURE 7. MM74C041nverter Used as a Post
Amplifier for a Battery Operated Op Amp
vee= ,ov
30
The MM74C04 can also be used with single supply amplifier
such as the LM324. With the circuit shown in FlfJure 8, the
open loop gain is approximately 160 dB. The LM324 has 4
amplifiers in a package and the MM74C04 has 6 amplifiers
per package.
'
20
10
+12 V
1.1
10
10'
10'
OPERATING FREGUENCY - H.
TL/F/6020-5
VI.
FIGURE 5. Typical Voltage Gain Versus Frequency
Characteristics for Amplifier Shown In Figure 2
APPLICATIONS
Cascading Amplifiers for Higher Gain
By cascacling the basic amplifier block shown in Figure 2 a
high gain amplifier can be aChieved. The gain will be multiplied by the number of stages used. If more than (me inverter is used inside the feedback loop c~....-yOUT
T= RC
. 114
1IM14CDZ
TL/F/6020-11
1/4
MMl4CDZ
-u V
I.K
Square Wave Oscillator
lOUT ::::
50 rnA
VOUT :::: 6.0 Vpp
TL/F/6020-9
C
FIGURE 9. MM74COO and MM74C02 Used as a Post
AmplHler to Provide Increased Current Drive
1=_1_
1.4RC
Other Applications
Shown in Figure 10 is a variety of applications utilizing
CMOS devices. Shown is a linear phase shift oscillator and
an integrator which use the CMOS devices in the linear
mode as well as a few circuit ideas for clocks and one
shots.
TUF/6020-12
One Shot
+Vcc
Conclusion
Careful study of CMOS characteristics show that CMOS devices used in a system design can be used for linear building blocks as well as digital blocks.
Utilization of these new devices will decrease package
count and reduce supply requirements. The circuit designer
now can do both digital and linear designs with the same
type of device.
INPUT
T=I.4RC
TL/F/6020-13
Staircase Generator
CLOCK
TL/F/6020-14
FIGURE 10. Variety of Circuit Ideas
Using CMOS Devices
259
~
r-------------------------------------------------------------------------,
~ Versatile Timer Operates
National Semiconductor
Application Note 97
from Microseconds to
Hours
"PA
'~
INTRODUCTION
TIming functions, until recently, have been somewhat neglected by integrated circuit manufacturers. The primary
reason was the extremely wide range of input and output
signals currently incorporated in discrete designs. In addition, power supply voltages varied over a ten to one range
and timing periods were as short as microseconds and as
long as hours.
The LM122 timer has been designed to operate over a very
wide range of input/output signal levels, supply voltages,
and timing periods. It will replace most discrete designs with
improved performance and reliability. This new timer overcomes many of the problems incurred in discrete or early IC
designs.
First, it locks out trigger signals during the timing period to
guarantee a precise output regardless of trigger levelwhile maintaining the ability to be retriggered almost Immediately following the end of the timing pulse. (Duty cycles up
to 99.9% can be achieved.) Secondly, the timing period is
free from jitter caused by supply fluctuations because the
timing components are driven from an internal regulated
source. Supply voltage for the timer can vary from 4.5V to
40V even during the timing periodl An additional feature is
the ± 40V excursion allowed on the trigger input and the
40V150 mA drive capability of the output transistor. These
two specifications allow the LM122 to interface directly to
present designs without level shift or power boosting problems. Finally, the LM122 will generate stable timing periods
from several microseconds to hours--a useful range of
eight decades. Worst case guarantees on comparator bias
current and threshold level allow the user to easily select
timing components for maximum accuracy.
CIRCUIT DESCRIPTION
The LM 122 cirCUitry can be divided into five separate sections: output stage, bias network, vciltage regulator, comparator, and logic. These sections are grouped on the schematic in Figure 1 to simplify understanding of the timer.
gain for the regulator. It is buffered by the series pass transistor, 024. 02S, 026, R25, and R26 are included for start·
ing purposes and do not affect operation once current is
flowing in the regulator section.
The function of the comparator is to cause an output
change of state when the timing capacitor has charged to
one RC time constant. 011 through 017 perform this function. 014, 01S, 016, and 017 are a Darlington differential
stage driving an active load formed by 012 and 013. 011 is
a second stage operating as a common emitter amplifier
with R14 as its load resistor. For long timing intervals, the
Darlington is run with no bleed current from 030. Operating
current for 015 and 016 is about 5 p.A per side. The specially processed lateral PNP's have hFE'S of about 200, so
operating current for 014 and 017 i!i\ typically 25 nA. At
these current levels, the substrate PNP's have hFE'S of 80,
giving comparator input currents of 300 pAlOne side of the
comparator is tied to a divider (R16 and R17) which is set at
63.2% of the reference, voltage - one RC time cO,nstant.
The other side is connected ,to the external: timing ,r~sistor
and capacitor.
'
The logic section of the LM 122 performs four functions:
first, it provides a latching action to make the circuitry immune to retriggering during the timing interval; second, it
simulates the action of an exclusive OR gate to generate a
logic reverse function; additionally, it translates the low level
output from the comparator to the high level swing needed
to drive the floating transistor output; and finally, it drives the
discharge transistor to reset the timing capacitor. 02 and
03 makeup the TIL compatible trigger input to the logic
section. 03 is a lateral PNP with 60V reverse emitter-base'
breakdown voltage, allOwing negative inputs are high as .
- 40V without harm to the chip. RS is an epitaxial resistor
which pinches off at 30V and has a breakdown of 80V. This
allows positive input voltages of up to 40V on the trigger
terminal even when operating the timer from a supply voltage of only S.OV. Typical current drawn by the trigger termiform a
nal is 40 p.A at 2.0V and 600 p.A at 40V. Q4 and
latch which self-limits at about 400 p.A and can be turned off
by 02. 05 and 07 interface the latch to the comparator so
that the comparator can fire the latch at the end of the
timing period. 08, 09, and 010 perform the level shifting
required to drive the output transistor and double as an exclusive OR gate, with the emitters of 08 and 09 as one
input and the collectors of 05 and 011 as the second input.
Grounding the 08 and Q9 emitters reverses the effect of a
signal appearing at the collector of 011.
as
The floating transistor output stage of the LM 122 consists of
032 through 036. 036 is the actual output transistor and is
driven by emitter follower, 033. 034 and 035 are antisaturation clamps to reduce stored charge in 036 and to limit
current through 033. 032 acts as a current limiter with the
limit set at about 120 mAo
The regulator built into the LM122 is a VBE/aVBEo type with
a typical output voltage of 3.1fiV at up to 5.0 mA load current. 018 and 019 generate a 100 p.A current through 019
which has a positive temperature coefficient of 0.33%I"C.
This generates 1.2V and .+ 4 mV1°C TC across R21. When
added to the base emitter diode voltages of 020 and 021, a
2.4V, zero TC reference is established at the base of 021.
R18 and R19 form a divider to raise the regulated voltage to
3.15V. (This particular voltage was chosen because it can
be operated off a single 5.0V supply and because one RC
time constant is exactly 2.0V out of 3.1SV.) 023 buffers 021
from supply fluctuations and sets up the currents for the
bias section of the timer. 020 is a single stage of voltage
Biasing for the various circuits in the timer is generated by a
string of PNP current sources consisting of 027 through
031. Current levels are established by the constant current
source, 023, driving diode connected 028. The current from
023 is 400 p.A, setting the drop across the emitter resistor,
R28 plus R29, at 200 mV. 029 delivers 10 p.A to the comparator and 031 supplies a total of 100 p.A to the output
transistor and logic circuitry. Part of 029's collector is returned to 027 to avoid having to use a large value resistor
for R30. 030 is completely off when using the timer for long
timing periods. Shorting the boost terminal of V+ adds
'See AN-42, "On card Regulator for logic Circuits"
260
COLLECTIR
y+
OUTPUT
BOOST
EMITTER
OUTPUT
VREF
l
RID
~
~
RIC
25k
!~k
I
R7
2.Ok
III
RI1
Uk
Rl
&.Ok
117
GNO'
' "
TRIGGER
•
LOGIC
•
•
••
••
•
VADJ
TLlHI7408-1
FIGURE 1. Schematic Diagram
l6-NY
~~~~;.:,;~-
~ r-------------------------~--------------~--------------~--------~--~~~_,
c:p
~
about 5 pA. bleed current at the emitters of Q14 and Q17.
This extra current is needed to slew the emitters of the comparator for timing periods less than 1 ms.
DESCRIPTION OF PIN FUNCTIONS
One of the main features of the LM122 is its greet versstility.
Since this device is unique, a description of the functions
and limitations of each pin is in order. This will make it much
easier to fOllow the discussion of the various applications
presented in this note.
V+ is the positive 'supply terminal of the LM122. When using a Single supply, this terminal may be driven by any voltage between 4.5V and 40V. The effect of supply variations
on timing period is less than O.OOS%/V, so supplies with
high ripple content may be used without causing pulse width
changes. Supply bypassing on V+ is not generally needed
but may be necessary when driving highly reactive loads.
Quiescent current drawn from the V + terminal is typically
2.5 mA, independent of the supply voltage. Of course, addi-'
tional current will be drawn if the reference is externally
loaded.
The VREF pin is the output of a 3.15V series regulator referenced to the ground pin. Up to 5.0 mA can be drawn from
this pin for driving external networks. In most applications
the timing resistor is tied to VREF, but it need not be in
situations where a more linear charging cl,ln'ent is required.
The regulated voltage is Nery useful in applications where
the LM122 is not used as a timer; such as switching regulators, variable reference comparators, and temperature controllers. Typical temperature drift of the reference is less
than 0.01 %/oC.
.
.
The trigger terminal is used to stl!rt timing. Threshold .is typical,y 1.6V at + 25"C and. has a temperature dependence of
-5.0 mVI"C. Current drawn from the trigger source is typically 20 pA. at threshold, rising to 600 pA. at 30V, then leveling off due to FET action of the series resistor, R5. For
negative input trigger voltages, the only current drawn is
leakage in the nA region.
If the trigger terminal is held high as the timing period end&,
the output pulse will appear normally, but the timing capacitor will not be discharged. This is a necessary circuit action
to prevent repetitive cycles when the trigger is held high.
After the timing period, the capacitor is discharged when the
trigger decreases below the threshold, without affecting the
output.
The RIC pin is tied to the'uncommitted side of the comparator and to the collector of the capacitor discharge transistor.
Timing ends .whan the voit8ge o,n this pin reaches 2.0V
(1 RC time constant referenced to the 3.15V regulator). The
internal discharge transistor turns on only if the trigger voltage has dropped below threshold. In comparator or regula,tor applications of the timer,the trigger is held permanently
high and the RIC pin acts Just like the Input to an ordinary
comparator. The maximum voltages which can be applied to
this pin are +5.5V and -0.7V.lnput current to the R/C'pln
is typically 300 pA when the voltage is negative with respect
to the VADJ terminal. For higher voltages, the current drops
to leakage levels. In the boosted mode, input current is
30 nA. Gain of the comparator is very high, 200,000 or more
depending on th& state of the logic reverse pin and the connection of the output transistor.
The ground pin of the LM122 need not necessarily be tied
to system ground. It can be connected to any positive or
negative voltage as long as the supply is negative with respect to the V+ terminal. Level shifting may be necessary
262
for the input trigger if the trigger voltage is referred to system ground. This can be done by capacitive coupling or by
actual resistive or active level, shifting. One point must be
kept in mind; the emitter output must not be held above the
ground terminal with a low SOurce impedance. This could
occur, for instance, if the emitter were grounded when the
ground pin of the LM122 was tied to a negative supply.
The' terminallabel~ VAD.J is tied to'one side of the comparator and to a voltage divider betw~n VREF and ground. The
divider voltage is set at 63.2% of VREF with respect to
ground-8xactly one RC time constant. The impedance of
the divider is increased to about 30k with a series resistor to
present a mh,imum load on external signals 'tied to VADJ.
This resistor is a pinched type with a typical variation in
absolute value of ± 100% and a TC of' 0.7%I"C. For this
reason, external signals (typically a pot between VREF and
ground) ~nnected to VAOJ shoul~ have a source resistance
as low as possible. For small changes in VADJ, up to several
kO is all right, but for large variations 2500 or less should
be maintained. This can be a~inplished with a 1.0k pot,
since the maximum impedance from :the wiper is 2500. If a
voltage is forced on VAoj from a hard source, voltage
should be limited to -0.5, and + 5.0V, or current limited to
± 1.0 mAo This includes capaciilvely coupled signals because even small values of capacitors contain'enough energy to degrade the input stage if the capacitor is driven with a
large, fast slewing signal. The VADJ pin may be used to
·abort the timing cycle. Grounding this pin during the timing
period causes the timer to react just as if the capaCitor voltage had reached its normal RC trigger point; the capacitor
discharges and the output charges state. An exception to
this occurs if the trigger pin is held high when the VADJ pin is
grounded~ In this case, the output changes state, but the
capacitor does not discharge. If the trigger drops with VADJ
is being held low, diScharge will occur immediately and the
cycle will be over. If the trigger is still high when VADJ is
released, the output mayor may not change state, depending the voltage across the timing capacitor. For voltages
below 2.0V across the timing capaCitor, the output will
change state immediately, then once more as the voltage
rises past 2.0V. For voltages above 2.0V, no change will
occur in the output.
In noisy environments or in comparator-type applications, a
!;Iypass capac~or on .the VADJ terminal may be needed to
eliminate spurious outputs because it is high impedance
point. Th' size of the cap will depend on the trequency and
energy content of the nolse. A 0.1 ,...Fwill generally suffice
for spike suppression, but several:,...F may be used if the
timer is subjected to high level 60 Hz EMI.
The emitter al1d the collector outputs of the timer can be
treated Just as If 'they were an ordinary transistor with 40V
minimum collector-emltter breakdown voltage. Normally, the
emitter is tied to the ground pin and the signal is taken from
the collector, or the collector is tied to V;+ and the signal is
taken from the emitter. Variatiol1s"on thase basic connections as possible. The collector can be tied to any positive
voltage up to ,40V when the signal is taken from the emitter.
However, the emitter will not be pulled higher than the supply voltage on the V+ pin. Connecting the collector to a
voltage less than t~!I V+ voltage is allowed. The emitter
should not be cOnnected to a hard Source other than that to
which the ground pin is tied. The transistor has bUDt-in current limiting with a typical knee current of 120 mAo Temporary short circtiits are allowed; even with collector-emitter
voltages up to 40V. The power time product, however, must
voltage in the comparator. The LM122 is specified to have a
timing ratio from 0.626 to 0.638 at + 25°C, giving a ± 1.8%
worst case contribution to initial timing period error. Over
temperature, the worst case figures doubles to ± 3.6%. If
the initial error is trimmed out externally however, timing er'
rordrift due to timing ratio will generally be less than ±0.5%
over temperature.
not exceed 15 watt-seconds for power levels above the
maximum rating of the package. A short to 30V, for instance, can not be held for more than 4 seconds. These
levels are based on a 40"C maximum initial chip temperature. When driving inductive loads, always use a clamp diode to protect the transistor from inductive kick-back.
A boost pin is provided on the LM122 to increase the speed
of the internal comparator. The comparator is normally operated at low current levels for lowest possible input current.
For short time intervals where low input current is not needed, comparator operating current can be increased several
orders of magnitude for fast operation. Shorting the boost
terminal to V+ increases the emitter current of the vertical
PNP drivers in the differential stage from 25 nA to 5.0 pA
With the timer in the unboosted state, timing periods are
accurate down to about 1 ms. In the boosted mode, loss of
accuracy due to comparator speed is only about 800 ns, so
timing periodS of several microseconds can be used.
Adding all the contributions to timing error from the LM 122
itself will usually give a figure in the 2% to 3% range at
+ 25°C. External timing components (Rt and Ct) will normally contribute much more error than this unless selected
components are used. ± 5% tolerance on Rt and Ct will
increase the worst case error to 12% to 13%. By trimming
out initial component errors, an exact initial timing period
can be obtained, but temperature drift then becomes the
limiting factor. For most applications, the contributions to
timing period drift due to the LM122 itself will be in the
0.005%rC to 0.02%/OC range.
If accurate timing over temperature is required, low drift
components must be used for Rt and Ct. Capacitors are
available with temperature coeffiCients of 100 to 200
ppm/oC. Resistors, at least in the lower ranges, are available with TC's much better than this. Above 1 MO, however,
care must be used in the selection of a low TC resistor.
Units are available up to 100 MO with less than 100 ppmrC
drift.
CapaCitor saturation voltage is the voltage still remaining on
the timing capaCitor after it has been reset to as near
ground as the internal discharge transistor can drive it. For
timing resistors 1 MO or greater, this remaining voltage is
typically 2.5 mV. For smaller timing resistors, the capacitor
saturation voltage can be calculated by the following:
formula:
The "LogiC" pin is used to reverse the signal appearing at
the output transistor. An open or "high" condition on the
logic pin programs the output transistor to be "off" during
the timing period and "on" all other times. Grounding the
logic pin reverses the sequence to make the transistor "on"
during the timing period. Threshold for the logic is typically
150 mV with 150 p.A flowing out of the terminal. If an active
drive to the logic pin is desired, a saturated transistor drive
is recommended, either with a discrete transistor or the
open collector output of integrated logic. A maximum VSAT
of 15 mV of 200 p.A is required. A typical example of active
drive to the logic pin is the pulse width discriminator shown
in Flguf8 16.
CALCULATING WORST CASE TIMING ERROR
Timing errors for the LM122 come from the following sources:
1. Timing ratio error
Vc ::::: 2.5 mV + (VREF)* (800)
Rt
'VREF
2. Capacitor saturation voltage
3. Internal switching delays
= 3.15V
The effect of Vc on timing period is linear at 0.03%/mV.
Temperature dependence of Vc is typically +0.2%/oC for
At"; 300 kO, riSing to 0.4%rCfor Rt = 10 kO. This gives a
typical temperature coefficient of timing error due to VC of
(0.002) (2.5 mV) (0.03%/mV) = 0.0015%rC for Rt :2:
1 MO and (0.004) (24 mV) (0.03%/mV) ::::: 0.003%rC for
Rt = 10 kO. Since most applications can use timing resistors in the range of 100 kO and up, error from capacitor
saturation voltage rarely exceeds 0.15% initially, with
± 0.05% variation over the full temperature range.
Internal switching delays cause errors which tend to be a
fixed time rather than a percentage of the timing period. In
the boosted mode this delay is typically 800 ns, and with the
boost off; the delay is about 25 p.s. These times can be
4. Comparator bias current
5. External reSistor and capacitor tolerance
6. Capacitor and board leakage
In general, errors 1 and 5 are the most Significant, so they
will be treated first.
For most applications, the major contribution to timing error
from the LM122 itself is variation in timing ratio, which is the
ratio of the comparator threshold voltage (typically 2.0V) to
the voltage at the VREF pin. A 1% error in this ratio results in
a 1.8% initial timing error. Timing ratio error comes from
variations in the internal divider ratio and from offset
263
~~--~------~~----------------------------------------~
~
added directly to the calcillated timing' period fOr 'worst case
TRIGGER _,'_ _.;.....,
analysis. For timing' periods longer 'than 25 ms, the 25 II-s
INPUT
delay gives an $rror, of 0.1 % or less. In the range of 1 or 25
~
ms, error due to delays is 0.1 % or less for the, boosted
mode, riSing to a m8liimum of 4.0% 1n the'unboosted mode.
At T -= 10 'II-s, delay is the major contribution to timing 'error
(:::: S%).
';:."
' ,
TRIGGER,
'LOGIC
Comparator bias current contributes a negligible timing error
for aU but very'long time timing periods. Error can be calculafed with a simple formula:
,Error (%)"=' -'50
BOOST
v+
COLLECTOR .....--.....1
. - - -................. VREF
x Rt X Ib (Note sign) ,
ib '= Comparator eias Current
, Rt = Timing Resistor '
Lo.y,"""'_-I
.. ,
R1
For Rt == 100 MO and Ib = 0.3 nA (typical) a 1.S% reduction In timing period is incurred. For worst.case calculations
at +25'0, an Ib'of 1 nA maximum is specified,in the un·
boosted mode and 100 nA in the boosted'mode. At tem'per·
atures below + 25'C, these n\lmbers stili hold. At 125'C,
Ib increases due to llilakage to a maximum of ± 5 nA unboosted. For worst case calculations below + 125'C the
leakage error (5 nA) can be assumeCjl to halve for each; O"C
drop below +125·C. At +95'C for instance, tl'l$·leakage
component o( Ib would be (5 nAlS) ,:::: 0.6 nA (or a total Ib of
1.6 nA worst case. For the commercial LM3~,ar)d LM3905,
worst case Ib is 2 nA at + 75'C, and for the LM2eOS Ib is
2" !)A, r'(1aximum at, + S5~C. For, temPElrlltures b,eIWeen
-;1,5°C and +S5°C, the TC of Ii> IstypiC~lIy S pAloC in the
unboosted mode and, 100 pAloC in .the boosted mode. For
a 100 MO Rt, this 5 pArC contributes :-;0~025%/OC to timing' p'''riod C J r i f t . , : ' ,
"
' , ,
\.Ok
RIC
vADJ
EMITTER ~-......~
GNO
VOUT
+
,,6tfor(%iOC) =;: (-50)
(A~/AT)(Rtl
.;.
,
,,
"
,"
TUHI7408~2
FIGU~E 2. EII,mlnating Inltlal'TlIlI!ng Cycle
USING ELECTROLYTIC 'IMINGCAPACITORS ", ~,
Electrolytic dilpacitors8re not usually recommeridEKIfur tlm~
ing beciluseof their unstable capacitance:and higfl'leakage.
For long timing'periods (>" 10 seconds) at mOderate tem~
peratures (O"C to 50"C) however, an electrolytiC maybe attractive because of itS low cOst per microfarad. 'Solid tanta·
lum capacitorS such a~ the Kemet" C series T310 (molded
epoxy) or T110 (hermetiC) are recommended. These units
have long term ,stabilities 01-2% to 3,% and a.temperature
coefficient of + O~%/~C. Selected ~nits are' available for
timing use with vety low' leakage, ' ,
. " "
,
For worst case calculations a Alb/AT (-25 s: TA :s;:
+S5°C) of 12 pArClJlay be used for the LM122/LM222
and 20 pArC for the LM322 and LM2905/LM3905.
RESET TIME
External leakage paths may cause timing errors for large
The timing capacitor used with the LM122 is res9t'with an
internal transistor which has a collector offset voltage of 2.5
mV @ 1 JI.A with approximately SOO of collector resistance.
The time required to reset this capaCitor determines the
minimum time between timing .. pulses. An, approximate formula for reset time is:
~alues ,of Rt and high boar
I
DISCIIET
TRAISISTOR
OR LOGIC
DATE
~
TLlH/7408-5
FIGURE 4. Cycle Interrupt
The output of the timer can be wire ORed with a discrete
transistor or an open collector logic gate output. This allows
overriding of the timer output, but does not cause the timer
to be reset until its normal cycle time has elapsed.
TLlHI7408-3
(A)
D'
'.'7
TRIGGER
v'
USING THE LM122 AS A COMPARATOR
'"'"
A built-in reference and zero volt common mode limit make
the LM122 very useful as a comparator. Threshold may be
adjusted from zero to three volts by driving the VADJ terminal with a divider tied to VREF. Stability of the refrence voltage is typically ± 1% over a temperature range of - SsoC to
+ 12SoC. Offset voltage drift in the comparator is typically
2S p'vrc in the boosted mode and SO p'vrc unboosted. A
resistor can be inserted in series with the input to allow
overdrives up to ± SOV as shown in Figure 5. There is actually no limit on input voltage as long as current is limited to
.
aDO/.,*"
DZ
11457
.
RlT
C2
D.bf
v....
."
EMlnEn
....
NOJl.t.VERTIIiO
IIVERTtllII
TLlHI7408-4
(8)
....,
FIGURE 3. Maximum Noise Immunity
you.
.....,--"T-.. .
av~~!-"N"""--I-I
ABORTING A TIMING CYCLE (Figure 4)
The LM122 does not have an input specifically allocated to
a stop-timing function. If such a function is desired, it may be
accomplished several ways:
• Ground VADJ
• Raise RIC more positive than VADJ
• Wire "OR" the output
Grounding VADJ will end the timing cycle just as if the timing
capaCitor had reached its normal discharge point. A new
timing cycle can be started by the trigger terminal as soon
as the ground is released. A switching transistor is best for
driving VADJ to as near ground as possible. Worst case sink
current is about 300 pA
A timing cycle may be also ended by a positive pulse to a
resistor (R s: Rllt 00) in series with the timing capacitor.
Tl/HI7408-6
'TImer Protected Against Damage for Up to ± 50Y
FIGURE 5. Comparator with 0 Volts to
3.0 Volts Threshold
± 1 mAo The resistor shown contributes a worst case of S
mV to initial offset. In.the unboosted mode, the error drops
to 0.2S mV maximum. The capability of operating off a single SV supply should make this comparator very useful.
26S
USING DUAL SUPPLIES '
APPLICATIONS
The LM122 can be operated off dual supplies as shown in
Figure 6. The only limitation is that the emitter terminal carinot be tied to ground, it must either drive a load referred to
V-'or be actually tied to V- as shown. Altholigh capacitive
coupling is shown for the trigger input (to allow 5V triggering), a resistor can be substituted for Cl. R2 must be chosen to give proper level shifting between the trigger signal
and the trigger pin of the timer. Worst case "10" on the
and worst case
trigger pin (with respect to V-) is
"high" is 2.5V. R2 may be calculated from the divider equation with Rl to give these levels.
BASIC TIMERS
Figure 7 is a basic timer using the collector output RI and Ct
set the time interval with RL as the load. During the timing
interval the output may be either high or low depending on
the connection of the logic pin. Timing waveforms are
shown in the sketch alongside Figure 7.
TRIGGER
INPUT
o.av,
,RI••ER--'lNlr-l
'....ERUTI
--.J 1--+1_ _ _ _-,
ALTERNATE
AZ·
roum;;---,
---.J LOGIC nED TO VR•• L
1---(11,1 (C,l---j
,
OUT
V
I ••
1"::~~~:-1
C!
'."J,1F
V"IF
=
--.
+11V
OUT1'UT
r
,I'RIGGERI---l
INPUT
VOUT
COLLECTOR
(:t11¥)
R,
Tl/H/74D8-9
FIGURE 7. Basic Tlmer-COllector Output
and TimIng Chart
EMmER
RIC
Rgure 8 is again a basic timer, but with the output taken
'--_-----_-__<_-1&V
from the emitter of the output transistor. As with the collector output, either a high or low condition may be obtained
during the timing period.
'Select For Proper Level Shift
TLlHI7~B-7
Emitter Terminal Or Emitter Load Must Be Tied To GND' Pin Of Timer.
,
TRIGGER
INPUT
FIGURE 6. Operating Off Dual Suppllea
+Vee
LINEARIZING THE CHARGING SWEEP
In some applications (such as a linear pulse width modulator) it may be desirable to have the timing capacitor charge
from a constant current source. A simple way to accomplish
this is shown in the accompanying sketch.
Y'
VOUT
r.~;;;'---l
---.J
113
ftl
INPUT
L---L
TL/HI74D8-IO
.2
FIGURE 8_ Basic Tlme....Emltter Output and TIming Chart
.1
Figure 9 shows the timer interfacing 5V logic to a high voltage relay. Although the V+ terminal could be tied to the
+ 28V supply, this would be an unnecessary waste of power
lIZ
..n
in the IC. In any case, the threshold for the trigger is 1.6V
regardless of where V+ is tied.
t - - ':'
-_ _ _ !~~:I~N
TRIGGER
INPUT
+2IV
TLlHI74D8-B
Ql converts the current through Rl'to a current source independent of the voltage across Ct. R2, R3, Dl, and D2 arEi
added to make the current through Rl independent of supply variations and temperature changes. (D2 is a low TC
type) D2 and R3 can be omitted if the V+ supply is stable
and Dl and R2 can be omitted also if temperature stability if
not critical. With Dl and R2 omitted, the curren1 through Rl
will change about 0.015%'"C with a 15V supply and
0.1 %I"C with a 5.0V supply.
TLlHI74D8-11
FIGURE 9. 5 Volt Logic Supply Driving 28 Volt Relay
266
.--------------------------------------------------------------------.~
some time. The relay remains de-energized for Rt Ct seconds after Vee is applied, then closes and stays energized
until Vee is turned off. Figure 12 is a similar circuit except
that the relay is energized as soon as Vee is applied. Rt Ct
seconds later, the relay is de-energized and stays off until
the Vee supply is recycled.
Figure 10 indicates the ability of the timer to interface to
digital logic when operating off a high supply voltage. VOUT
swings between + 5V and ground with a minimum fanout of
5 for medium speed TTL.
TRIBGER
IlIPUr
+i.GV
I---"'-VOUT
c,
RELAY
COIL
TL/HI7408-12
FIGURE 10_ 30 Volt Supply Interfacing to 5 Volt Logic
Figure 11 is an application where the LM122 is used to simulate a thermal delay relay which prevents power from being
applied to other circuitry until the supply has been on for
TL/HI7408-14
FIGURE 12. Time Out on Power Up (Relay Energized
UntflRtCt. Seconds After Vee Is Applied)
Figure 13 is a more advanced application of the LM122 as a
proportioning temperature controller with optical isolation
and synchronized zero crossing features. The timing function is not used. Instead the trigger terminal is held high and
the LM122 is used as a high gain comparator with a built in
reference. R 1 is a thermistor with a - 4 % fOe temperature
coefficient used as the sensor. R2 is used to set the temperature to be controlled by R1. R3 through R8 set up the
proportioning action. R3 raises the impedance of the R1/R2
divider so that R5 sees a relatively constant impedance independent of the set point temperature. R6 and R8 reduce
the VADJ impedance so that internal variations in divider
impedance do not affect proportioning action. R5 and R7
RELAY
COIL
t--4~t---'
to
TLlHI7408-13
FIGURE 11. Time Out on Power Up (Relay Energized
RtCt Seconds After Vee Is Applied)
U7V
At
,.............
.......
ZiV
..IV
UNREGULATED
R1!
'Rl-Thannistor (-4%/'C)
Ql-optical coupler, minimum gain = % at 1.0 mA
(01-03)--1 N459
Q2-Sensltlve gate SCR, 1.0 mA or less
....
AI
IK
TLlH/7408-15
FIGURE 13. Proportioning Temperature Controller with Synchronized Zero-Crossing
267
~
~
~
cc
r-----------------------------------------------------------------------------,
set the actual width of the proportioning band and can be
scaled as necessary to alter the width of the band. Larger
resistors make the band narrower. The values shown give
approximately a 1°C band. R4 and Cl determine the proportioning frequency which is about 1 . Hz with the values
shown. Cl or R4 can change to alter frequency, but R4
should be between SOk and SOOk, and Cl must be a low
leakage type to prevent temperature shifts. 01 prevents
supply voltage fluctuations from affecting set point or proportioning band. Any unregulated supply between 6V and
lSV is satisfactory.
'V"
01
2N3811
FAST
RECOVERY
al is an optical isolator with a minimum gain of O.S. With the
values shown for R9, Rl0, and Rll, al is over-driven by at
least 3 to 1 to insure deep saturation for reliable tum off of
the SCA. a2 must be a sensitive gate device with a worst
case gate firing current of O.S mA. R12, R13, and 02 implement the synchronized zero-crossing feature by preventing
al from turning off after the voltage across a2 has climbed
above 2.SV. 03, RIO, and C2 provide a source of semifiltered dc current must have a minimum breakdown of 200V.
'No.
Figure 14 shows the LM122 connected as a one hour timer
with manual controls for start, reset, and cycle end. S 1
starts timing, but has no effect after timing has started. S2 is
a center off switch which can either end the cycle prema-
START
TRIGGER
LOUIC
S1
Wire Wound On Molybdenum Permalloy Core
TLlH/7408-17
FIGURE 15.5 Volt SWitching Regulator with 1.0 Amp
Output and 5.5 Volt Minimum Input
ance must be connected between VREF and ground with its
tap point tied to VADJ.
By driving the logic terminal of the LM122 simultaneous to
the trigger input, a Simple, accurate pulse width detector can
be made (Figure 16).
'Vee
ClOSETO~
~
BOOST
V+
TIMING
nL
. . .- - -....-fVREF
COLLECTOR
t~:~~"""'1""''''''-------'''
PULSE
VOUT
R,
END CYCLE
INPUT
15M
82:-_0-,.",.".......-1
RESET
~T'---=T:.....I
'Dearborn Electronics LP9A1A476K Polycatbonate
TL/HI74D8-16
FIGURE 14. One Hour Timer with Reset
and Manual Cycle End
turely with the appropriate change in output state and discharging of Ct, or cause Ct to be reset to OV without a
change in output. In the latter case, a new timing period
starts as soon as S2 is released. The average charging current through Rt is about 30 nA, so some attention must be
paid to parts layout to prevent stray leakage paths. The suggested timing capacitor has a typical self time constant of
300 hours and a guaranteed minimum of 2S hours at
+ 2SoC. Other capacitor types may be used if sufficient data
is available on their leakage characteristics.
'VOUT
= 0 For W < R, Ct
= W - R, Ct For W > R, Ct
TLlHI7408-18
Pulse Out
FIGURE 16. Pulse Width Oetector
In this application the logic terminal is normally held high by
R3, When a trigger pulse is received, al is tumed on, driving the logic terminal to ground. The result of triggering the
timer and reversing the logic at the same time is that the
output does not change from its initial low condition. The
only time the output will change states is when the trigger
input stays high longer than one time period set by Rt and
Ct. The output pulse width is equal to the input trigger width
minus Rt • Ct. C2 insures no output pulse for short « RC)
trigger pulses by prematurely resetting the timing capacitor
when the trigger pulse drops. CL filters the narrow spikes
which would occur at the output due to Interval delays during switching.
Figure 15 is another application where the LM122 does not
use its timing function. A switching regulator is made using
the intemal reference and comparator to drive a PNP switch
transistor. Features of this circuit include a S.SV minimum
input voltage at 1A output current, low part count, and good
efficiency (> 7S%) for input voltages to 10V. Line and load
regulation are less than O.S% and output ripple at the
switching frequency is only 30 mV. al is an inexpensive
plastic device which does not need a 'heatsink for ambient
temperature up to SO"C. 01 should be a fast switching diode. Output voltage can be adjusted between 1V and 30V
by choosing proper values for R2, R3, R4, and RS. For outputs less than 2V, a divider with 2S00 the Thevinin resist-
The LM122 can be used as a two terminal time delay switch
if an "on" voltage drop of 2V to 3V can be tolerated. In
268
'V~
II'
R'
..,.
.,
C'
"'SY
LOGIC
!.
TRIGGER--1I-"'_-it-_~_""
INPUT,
3.0 .A ··OFf"
II'
).~..
.
RIC
VREF
COllECTOR
R,
.
R,
TLlHI7408-21
TL/HI7408-19
FIGURE 19. Zero Power DIssipation
Between Timing Intervals
FIGURE 17. Two-Terminal Time Delay Switch
Figure 17, the timer is used to drive a relay "on" Rt Ct sec-
received, the LM122 output transistor and 01 latch for the
duration of the timing period. 01 prevents coupling back into
the trigger signal from the dc load created by the trigger
input. If the trigger input is a short pulse, C1 and R2 may be
eliminated. RL must have a minimum value of
(Vccl/(2.5 mAl.
The LM122 can be made into a self-starting oscillator by
feeding the output back to the trigger input through a capac-
onds after application of power "off" current of the switch is
4 mA maximum, and "on" current can be as high as 50 mAo
An accurate frequency to voltage converter can be made
with the LM122 by averaging output pulses with a simple
one pole filter as shown in Figure 18. Pulse width is adjusted
with R2 to provide initial calibration at 10kHz. The collector
of the output transistor is tied to VREF, giving constant amplitude pulses equal to VREF at the emitter output. R4 and
C1 filter the pulses to give a dc output equal to, (Rt> (Ctl
(VREF) (t). Linearity is about 0.2% for a OV to 1V output. If
better linearity is deSired R5 can be tied to the summing
node of an op amp which has the filter in the feedback path.
If a low output impedance is desired, a unity gain buffer
such as the LM110 can be tied to the output. An analog
meter can be driven directly by placing it in series with R5 to
ground. A series RC network across the meter to provide
damping will improve response at very low frequencies.
II'
D1
1N4&7
R'
3.0..
...
1--....- .....0 vou•
I I I
.- "'-2-..
.--...._.V'"
I
OUTPUT
i
iI WAVEFORM
f.
..
'01'
C,
.00"'"
R'
1.1.
'SeeChart
DC OUTPUT
1.1V/KHz
,.
.
R,C,
TL/HI7408-22
17
11
,..
"""
'OY
~ I.,
oS
....,
, .1V
TLlHI7408-20
• ..,ILII
FIGURE 18. Frequency to Voltage Converter
(Tachometer) Output Independent of Supply Voltage
In some applications it is desirable to reduce supply drain to
zero between timing cycles. In Figure 19 this is accomplished by using an external PNP as a latch to drive the V+
pin of the timer.
L1
.. '"")
1.D
I.
,.
TLlHI740B-23
FIGURE 20. Oscillator
itor as shown in Rgure 20. Operating frequency is 1/(Rt Ctl.
The output is a narrow negative pulse whose width is approximately 2R2 Ct. For optimum frequency stability, Ct
should be as small as possible. The minimum value is determined by the time required to discharge Ct through the internal discharge transistor. A conservative value for Cr can be
Between timing periods 01 is off and no supply current is
drawn. When a trigger pulse of 5V minimum amplitude is
269
chosen from the graph included with FlfJure 20. For frequencies below 1 kHz, the frequency error introduced by Cj is a
few tenths of one percent or less for Rt > 500k.
Although the LM122 is triggered by a positi)le going trigger
signal, a differentiator tied to a normally "high" trigger will
result in negative edge triggering. In Figure 21, R1 serves
the dual purpose of holding the trigger pin normally high and
differentiating the input trigger pulse coupled through C1.
The timing diagram included with Figure 21 shows that triggering actually occurs a short time after the negative going
trigger, while positive going triggers have no effect. The delay time between a negative trigger signal and actual starts
of timing is approximately 0.5 to 1.5 R1 C1 depending on
the trigger amplitude, or about 2.5 to 7.5 p.s with the values
shown. This time will have to be increased for Ct larger than
0.01 p.F because Ct is charged to VREF whenever the trigger pin is kept high and must reset itself during the short
time that the trigger pin voltage is low. A conservative value
for C1 is:
CI
D.I"
••,•••• --.J 1-....._.......,
INPUT.
+Vcc
~
.,
I
I
I
.,
I
VREP
COLLECTOR
C1
Ct
:<>:
10
The LM122 can be connected as a chain of timers quite
easily with no interface required. In Figure 22A and 228, two
possible connections are shown. In both cases, the output
of the timer is low during the timing period so that the positive going signal at the end of timing period can trigger the
next timer. There is no limitation on the timing period of one
timer with respect to any other timer before or after it, because the trigger input to any timer can be high or low when
that timer ends its timing period.
c,
TLlH/740B-24
FIGURE 21. Timer Triggered by
Negative Edge of Input Pulse
VDUTIII
V0UTt1l
Tl/HI74OB-25
(A)
VOUT!tl
----,
TRIGGER
INPUT
I
r...1--..L-, I
t--+
r-l
I
I
I I
I
I I
"-I
........
i l
I
I
I
.
VREf
RIC
t
COLLECTOR
EMITTER
-I
t- ~- Your..
L."""--r.J ~
.-L
I
u
I
~
Lr
OUTPUT 1
TRI•• ERINPUT
nL__';""__
TLlHI74OB-28
(8)
FIGURE 22. Chain of Tliners
270
Typical Performance Characteristics
Comparator Bias Current
IA
I I I
i
a.z
1
~R:6;E~:'~"
i
Ii -11.2
-DA
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a..
a
"
=•
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§
2.5
1..
2..
1.5
a
2.5
2.5
',,--HOC
iii
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T
C
.!!
.n·cl
i
.:=
;
r.·US"C
2.0
1.1
o
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I
11
24
~ 2J1
0.1
..
IIA
..~
i!!
>
3Z
I.a
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V
O
D
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a.s
~~"47,.,.,:--:;11IIIIIIIII
2.D
.II1II
w
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CD
I;-21
CD
I
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L~
-15
D
.....
~nc_
~
TA - _HOC
~ -II
II
24
3Z
co
Short Output Pulse
II
T.·zrC .............
1.0
V' (VI
1111<
!! ....
TA ·125~C
-1.
••
1.
g
........
Reference Regulation
TIMING RESISTOR Inl
J
:J
II ~
;
I.OM
115
~
Reference Regulation
11.
II
-15
I
a: -5.0
!!
... ~/'-1J',/L......UJ.._I.I..-:I_...u:
2.&
..
I I
I
w
1.5
i" t--.
WORST CASE "0'
/1;
1.0
SATURATION VOLTADE (VI
!
15
I
1.'
~
!
....-
_ _ lIImIIIICI
~
•
...... -....L
TEMHAATUAE rCI
/:1 /
..
~=:::;i~
:=.
,.-=""I : y '/.A'I'~,
I
I
..... J ......
I.D
-55
CD
Timing Error Due to
Comparator Bias Current
II
..I.
',,-1H C
///
40
32
2.5
WOAST CASE "I"
~
~
TAlaBEAVOLTAOE (VI
T.- -In
/.
24
11
2.1
............. TYPlJC~~
a
'"
Ii ·
1.1
;:
t.2
Collector Output Saturation
Characteristics at High Current
i·1I
r---
;:
D.I
y< IVI
liD
......
1.0
il
1.1
I.D
Trigger Threshold
~
./
,...
D.OS
COMPARATOA INPUT VOLTAGE IVI
c.a Supply Current
1
a
COMPARATOR INPUT VOLTAGE IVI
C_ARATOR INPUT VOLTAaE (VI
3.D
• r- TIEO TO V"
11
5.•
I"0.5
I--
~GGER"HI'
fl
I
I
a
·n"c
T
21 I-To '1!i"C
. ,.
!
...
TRISDER "La"
l-T,,';UID"C I
T.·'ZI"C :\ --; TRIGGER "HI"
G.I
.J/. T.·un
Ii
2.0
1.5
n
2A
- •.1
-1.1
-2.4
Bias Current
To'-srC
\
~
3D Comparator
4.1
4.1
3.2
iii.
T,,-,ore
fl
:I
Comparator Bias Current
5.B
' .. --HoC
.......
I,m
I••
i.
8.1
I.IM
i
=
::;
CD
I
..
i
10M
'.01
U01~
100M
8.1
~~:~~~:C~'~~~:AJE
~i
.. !::
. ~t =
4.'
2.0
>
:=~
I-
4.0
"w 2.'
!i
f--'-
=F~f-
T. '121"':
T.-25'C. =
T"-55'C - ~
"'-I.DY
AI =1.
c,-mpF
COLLECTOR OUTPUT RL • Hln
D_••
-2.1
I
Z.I
c.a
IJI
au"'" CURRENT IIIIAI
u
1Il10
11M
1.0
TIME_I
100
2JI
11
SJI
TIME 1..1
TUHn408-27
271
N~tional Semiconductor .
Application Note 103
George Cleveland
LM340 Series Three
Terminal Positive
Regulators
INTRODUCTION
The LMS40-XX are three terminal 1.0A positive voltage regulators, with preset output voltages of 5.0V or 15V. The
LMS40 regulators are complete S-terminal regulators requiring no external components for normal operation. However,
by adding a few parts, one may improve the transient response, provide for a variable output voltage, or increase
the output current. Included on the chip are all of the functional blocks required of a high stability voltage regulator;
these appear in Figure 1.
~IC02
~--------------~~Vocrr
-VIN
-
Isoo
(1-1)
COMMON
TL/HI7413~i
FIGURE 1. Functional Block 01 the LM340
The error amplifier is internally compensated; the voltage
reference is especially designed for low noise and high predictability; and, as the pass element is included, the regulator contains fixed current limiting and thermal. protection.
The LM340 is available in either metal can TO-3 or plastic
T0-220 package.
1. CIRCUIT DESIGN
Voltage Relerence
(1-2)
In Figure 3 the voltage reference includes R1-:RS and Q1Q5. QSaiso acts as an error amplifier and Q6 as a buffer
between QS and the current source. If the output drops, this
drop is fed back, through R4, R5, Q4, Q5, to the bllse of QS.
Q7 then conducts more current re-establishing the output
given by:
R4 + R5
VOUT=VREF~
Usually Ie voltage regulators' use temperature-compensated zeners as references. Such zeners exhibit BV > 6.0V
which sets the minimum supply voltage somewhat above
6.0V. Additionally they tend to be noisy, thus a large bypass
capaCitor is required.
272
Complete Circuit of the LM340 (Figure 4)
Here (J02. J03) > (JQ4. Jos) and a positive TC ~VBE appears across RS. This is amplified by 17. (R6/R6 = 17) and
is temperature compensated by the VeE of QS. Q7.
to
develop the reference voltage. R17 is changed to get the
various fixed output voltages.
as
Short Circuit Protection
A) VIN-VOUT < S.OV: There is no current through 02 and
the maximum output current will be given by:
r - - - - - t - - 4 I I -...~VOUT
R5
lOUT MAX =
VeE014
Fi1EI
"" 2.2A (Tj =
2S"C)
(1 -4)
B) VIN-VOUT > 6.0V: To keep Q16 operating within its
maximum power rating the output current limit must decrease as VIN-VOUT increases. Here 02 conducts and
the drop across R16 is less than VeE to turn on Q14. In
this case lOUT maximum is:
lOUT MAX =
f R~S
( VeE014 -
[(VIN - VOUT) - VZD2 - VBE01~ R14)
R13
.
R4
= 0.077 [37.2 - (VIN - VOUT)] (A)
atTj = 25"C
TllH/7413-3
FIGURE 3. LM340 Simplified
. - -...._ - - - -....- - - - -....-_...,:..INPUT
RIB
0.3
...-----+-----...
..;..UUTPUT
R17
tRI
3Dk
RIB
Uk
GNU
3
"Series pass element
TllH/7413-4
tStarilng up reSistor
FIGURE 4. Complete Circuit of the LM340
273
(1-S)
~
~ r-----------~~------------------------------------------------~~------------------~
o
Thermal Shut Down
In Figure 4 the VeE of Q1'3 is clamped to 0.4V. When the die
temperature reaches approximately + 175"C the VeE to turn
an Q13 is 0.4V. When Q13- tums on it removes all base
drive from Q15 which turns off the regulator thus preventing
a further increase in die temperature.
load impedance of 0 to 850. Using the following definitions
and the notation shown on F/{Jllre 5, ZOUT and lOUT are:
QccN = Quiescent current change per volt of inpuUoutput (pin 1 topin 2) voltage change of the LM340
L,N = Une regulation per volt: the change in the LM340
output voltage per volt of input! ouJput voltage
change at a given lOUT.
.
L,N
alOUT = (Qcc/V)aVOUT + Fi1aVOUT
(2-1)
Power Dlsalpatlon
The maximum power dissipation of the LM340 is given by:
Po MAX = (VIN MAX - VOUT) lOUT MAX
+ V IN MAX IQ (W)
aVOUT
ZOUT = - alOUT
(1-6)
The maximum junction temperature (assuming that there is
no thermal protection) is given by:
ZOUT =
TjM = 36 - 13 lOUT MAX ...:. (YIN - VOUT) + 25°C (1-7)
..
0.Q655
.
Example:
VINMAX = 23V,IOUTMAX = 1.0A; LM340T-15.
Equation (1-7) yields: TjM = 200"C.So the Tj max of 150"C
specified in the data sheet should be the limiting temperature.
From (1-6) Po "" 8.1 W. The thermal resistance of the heat
sink can be estimated from:
(2-2)
aVOUT
(L,/V)
(Qcc/V)aVOUT + """"fj1avOUT
1
ZOUT=----IV)
+ (L,/V)
Q
(
cc
R1
(2-3)
(2-4)
(1-8)
The LM340-5.0 data sheet lists maximum quiescent current
change of 1.0 rnA for a 7.0V to 25V change in input voltage;
and a line regulation (interpolated for lOUT = 200 mAl of
35 mV maximum for a 7.0V to 25V change in input voltage:
1.0 rnA
QccN = 15V" = 55 p.AN
(2-5)
The thermal resistance 8;.c Ounction to case) of the TO-220
package is 6°C/W, and assuming a 8e-s (case to heat sink)
of 0.4, equation (1-8) yields:
8s-a = 8.4°C/W
L,N = 35 mV "" 2 mVN
(2-6)
18V
The worst case change in the 200 mA output current for a
1.0V change in output or input voltage using equation 2-1 is:
2. CURRENT SOURCE
The circuit shown on Figure 5 provides a constant 'output
current (equal to VOUT/R1 or 200 mAl for a variable
alOUT = 55 p.A + 2 mV = 135 p.A
(2-7)
1.0V
250
and the output impedance for a 0 to 850 change In ZL using
equation 2-4 is:
1
(2-8)
ZOUT =
2mV = 7.4kO
8s-a =
TIMAX - TA
P
- (8 j·e
o
.
+ 8e-s)(OC/W)
IRIG
1-
VIN ·15V
RI
25
I.OW
....L.CI·
-,-o.u,.F
lOUT
_mA
55p.A
250
Typical measured values of ZOUT varied from 10-12.3 kO,
or 81-100 f)-AIV change input or output (approximately
O.05%/V).
tI
3. HIGH CURRENT REGULATOR WITH SHORT CIRCUIT
CURRENT LIMIT
The 15V regulator circuit of Figure 6 includes an external
boost transistor to increase output current capability to
5.0A. Unlike the normal boosting methods, it maintains the
LM340's ability to provide short circuit current limiting and
thermal shut-down without use of additional active components. The extension of these safety features to the external pass transistor Q1 is based on a current sharing scheme
I
I
I
OS;Za. S;85!l
TLlHf7413-5
"Required
+
nregulator is located far from pOwer supply filter
FIGURE 5. Current Source
274
I
RI
0,25
4
QI
....~•
4
2
O~~~-~5_1-'
__~I~~-e~__~z~.~i-__~S~I~
______-,
I
R3 \ .
-A 10
R2
I
1.0
SI_4.OW
1
I
.....
'5 1--1
V'N -IUV TO 25V
lM34QT.15 I
II'"---r-::--.....P
13
-.!.
VOUT = 15V
AT 5 AMP
~CZ·
~II..F
I
SINGLE
POINT GNO
TlIH17413-6
'Solid tantalum
Note 1: Current sharing between the LM340 and 01 allows the extension of short
circuH currenllimit, safe operating area protection, and (assuming QI'S heal slnk
has four or more times the capacity 01 the LM340 head sink) thermal shutdown
protection.
Note 2: ISHORT CIRCUIT is approximately 5.5 amp.
Note 3: loUT MAX at VOUT = 15V is approximately 9.5 amp.
FIGURE 6. 15V 5.0A Regulator with Short Circuit Current Limit
using R1, R2, and 01. Assuming the base-to-emitter voltage
of 01 and the voltage drop across 01 are equal, the voltage
drops across R1 and R2 are equal. The currents through R1
and R2 will then be inversely proportional to their resistances. For the example shown on Figure 6, resistor R1 will
have four times the current flow of R2. For reasonable values of 01 beta, the current through R1 is approximately
equal to the collector current of 01; and the current through
R2 is equal to the current flowing through the LM340.
Therefore, under overload or short circuit conditions the
protection cirCUitry of the LM340 will limit its own output
current and, because of the R1/R2 current sharing scheme,
the output current of 01 as well. Thermal overload protection also extends 01 when its heat sink has four or more
times the capacity of the LM340 heat sink. This follows from
the fact that both devices have approximately the same input!output voltage and share the load current in a ratio of
four to one.
'
The circuit shown on Figure 6 normally operates at up to
5.0A of output current. This means up to 1.0A of current
flows through the LM340 and up to 4.0A flows through 01.
For short term overload conditions the curve of Figure 7
shows the maximum instantaneous output current versus
temperature for the boosted regulator. This curve reflects
the approximately 2.0A current limit of the LM340 causing
an 8.0A current limit in the pass transistor, or lOA, total.
I_
iI
ia:
8
rg
Under continuous short Circuit conditions the LM340 will
heat up and limit to a steady total state short circuit current
of 4.0A to 6.0A as shown in Figure 8. This curve was taken
using a Wakefield 680-75 heat sink (approximately
7.5'C/W) at a 25'C ambient temperature.
10
F-~:::t~:::¥;+::::J::;d
l-
c
5.0
I-+-t-+--+--t-+--l
~
~
0
w m
~
Q
~
H
6.0
:;
4.0
u
--
a:
,..c:;a:
.'"
e>
2.0
o
L-~_~~_~~~
19
20
21
22
23
24
25
INPUT VOLTAGE (V)
Tt/H17413-8
FIGURE 8. Continuous Short Circuit
Current vs Input Voltage
For optimum current sharing over temperature between the
LM340 and 01, the diode 01 should be physically located
close to the pass transistor on the heat sink in such a manner as to keep it at the same temperature as that of 01. If
the LM340 and 01 are mounted on the same heat sink the
. LM340 should be electrically isolated from the heat sink
since its case (pin 3) is at ground potential and the case of
01 (its qollector) is at the output potential of the regulator.
Capacitors C1 and C2 are required to prevent oscillations
and improve the output impedance respectively. Resistor
R3 provides a path to unload excessive base charge from
the base of 01 when the regulator goes suddenly from full
load to no load. The single point ground system shown on
Figure 6 allows the sense. pins (2 and 3) of the LM340 to
monitor the voltage directly at the load rather than at some
point along a (possibly) resistive ground return line carrying
up to 5.0A of load current. Figure 9 shows the typical variation of load regulation versus load current for the boosted
regulator. The insertion of the external pass transistor increases the input!output differential voltage from 2.0V to
!
!
a:
TA =+25°C
LM340K·I5 HEAT SINK:
WAKEFIELD NO. 680-75
1.5°CIW
,..u'"
e>
!
8.0
15
a:
15~~~~~~~~
I-+-i-+--+-V'N =21V10
I,..
,---r--..---,---r--.,--..
~
JUNCTION TEMPERATURE (OC)
TLlH/7413-7
FIGURE 7. Maximum Instsntaneous
Current vs Junction Temperature
275
s..Z•
CC
approximately 4.5V. For an output current less than 5.0A,
the R2/R1 ratio can be set lower than 4:1. Therefore, a less
expensive PNP transistor may be used.
1.25
...
e
i
IOVERLOAD = 5.0A
ILED = 4Q mA (light intensity of 16 moo)
VIN - 2.65
I
LED
VLED = 1.75, R5 '"
V,N ·21V
TI =+25'C
1.0
0.75
<>
!!
0.5
:II
0.25
L
...
V
/
1.0
~
V'
z.o
4.1
3.0
(4-1)
5. ADJUSTABLE OUTPUT VOLTAGE REGULATOR FOR
INTERMEDIATE OUTPUT VOLTAGES
The addition of two resistors to an LM340 circuit allows a
non-standard output voltage while maintaining the limiting
features built into IC. The example shown in Fl{lure 11 provides a 10V output using an LM340K-5.0 by raising the reference (pin number 3) of the regulator by 5.0V.
/
<>
~
Example:
5.0
LOAD CURRENT (AMPS)
TLlH17413-9
FIGURE 9. Load Regulation
1
4. S.OV, S.OA VOLTAGE REGULATOR FOR TTL
The high current 5.0V regulator for TTL shown in Fl{lure 10
uses a relatively inexpensive NPN pass transistor with a
lower power PNP device to replace the single, higher cost,
power PNP shown in FIgure 6. This circuit provides a 5.0V
output at up to 5.0A of load current with a typical load regulation of 1.B% from no load to full load. The peak instantaneous output current observed was 10.4A at a 25'C junction
temperature (pulsed load with a'1.0 ms ON and a 200 ms
OFF period) and B.4A for a continuous short circuit. The
typical line regulation is 0.02% of input voltage change
(lOUT = 0).
One can easily add an overload indicator using the National's new NSL5027 LED. This is shown with dotted lines in
Fl{lure 10. With this configuration R2 is not only a current
sharing resistor but also an overload sensor. R5 will determine the current through the LED; the diode 02 has been
added to match the drop across 01. Once the load current
exceeds 5.0A (1.0A through the LM340 assuming perfect
current sharing and VD1 = V 02) 03 turns ON and the overload indicator lights up.
...1-Cl
..,.... 0.221
R2. and the effects of Ala in response to input voltage
changes. The change in output voltage is:
AV
= (LlV) AV
OUT
r
IN
Qcel A = Quiescent current change per amp of load current
change
+ (L,- IV) AVIN R2
R1
AVOUT = (Z340) AIL
(5·1)
(Lr/V) (1 +
:~) +
(Qce/V) R2
L,-IV = 50 mV :::: 3 mVIV
18V
1.0 rnA
""""i8V =
(5·2)
55 p.AIV
AVOUT
(1R
2)
ZOUT=--=Z340
+AIL
R1
<
(5·3)
The LM340·5.0 data sheet gives a maximum load regulation
Lr = 50 mV and Ala = 1.0 mA for a 1.0A load change.
(5·4)
50mV
Z340 = 1.0A = 0.050
(5-9)
1 mA
Qcc /A = 1.0A = 100 p.AlA
(5-10)
This gives a worst case dc output impedance (ac output
Impedance being a function of C2) for the 10V regulator
using equation 5-8 of:
AVOUT = 3 VIV (1 + 3100)
1.0V
m
3000
+ (55 p.AIV) 3100
(5-5)
6 mVIV + 17 mVIV = 23 mVIV
(5-6)
3100 )
ZOUT = 0.050 ( 1 + 3000
+ (100 p.A/A) 3100
This represents a worst case line regulation value of
0.23%1V.
The load regulation Is the sum of the LM340 voltage regula·
tion. Its effect on the current through R2. and the effect of
Ala In response to changes in load current. Using the fol·
lowing definitions and the notation shown on Figure 11
AVOUTis:
ZOUT = Regulator output impedance: the change in output
voltage per amp of load current change.
V,N
(5-8)
+(Qce/ A)R2
The worst case at line regulation for the circuit of Figure 11
calculated by equation 5·2. lOUT = 500 rnA and R2
3100 is:
A:~~T =
(5·7)
and the total output impedance is:
The LM340·5.0 data sheet lists AVOUT < 50 mV and Ala
1.0 mA for AVIN = 18V at lOUT = 500 mA. This is:
QcclV =
(Z340)
+ ~ AIL R2
+ (Qcc/A) AIL R2
giving a total line regulation of:
A:~,:: =
Z
•
.....
Z340 = LM340 output impedance
• 25V o-...-
...~
(5-11)
ZOUT = 0.100 + 0.0310 = 0.130
or a worst case change of approximately 1.5% for a 1.0A
load change. Typical measured values are about one-third
of the worst case value.
6. VARIABLE OUTPUT REGULATOR
In Figure 12 the ground terminal of the regulator is "lifted"
by an amount equal to the voltage applied to the non-inverting input of the operational amplifier LM101A. The output
1-=-------....----411-4:>
VOUT
-1-C2"
-,-O.2M
-Required Wthe regulator is located far from tho power supply finer
"Solid tantalum
FIGURE 12. Variable Output Regulator
277
TUH17413-12
S
If the LM324 is used instead of the LM101A, R3 can be
omitted since its common mode voltage range includes the
ground, and then the output will be adjustable from S to a
certain upper value defined by the parameters of the system.
The circuit exhibits the short,circuit protection and thermal
shutdown properties of the LM340' over the full output
range.
The load regulation can be predicted as:
voltage of the regulator is therefore raised to a level set by
the value of the resistive divider R1, R2, R3 and limited by
the input voltage. With the resistor values shown in Figure
12, the output voltage is variable from 7.0V to 23V and the
maximum output current (pulsed load) varies from 1.2A to
2.0A (TJ = 2S°C) as shown in FlfJure 13.
2.5
,
Y'N
=25V
iii
1.5
'"
'"
l!
:t
~
T:=I+M
1---
A
PULSED LOAD
2.0
... i'
IN
- R1
OUT -
·tLmrc
~
~
0.5
13
15
17 19
21
(6·1)
340
7. VARIABLE OUTPUT REGULATOR O.SV-29V
When a negative supply is available an approach equivalent
to that outlined in section 6 may be used to lower the mini·
mum output voltage of the regulator below the nominal volt·
age that of the LM340 regulator device. In Figure 14 the
voltage VG at the ground pin of the regulator is determined
by the drop across R1 and the gain of the amplifier. The
current I may be determined by the following relation:
o ~~~~~~~~~
7.0 9.0 11
R1
where 11V340 is the load regulation of the d~ice givE!n in the
data sheet. To insure that the regulator will start up l!nder
full load a reverse biased small signal germanium diode,
1N91, can be added between pins 2 and 3.
'"
1.0
+ R2 + R3 IN
23
Your (V)
TL/H17413-13
FIGURE 13. Maximum Output Current
Since the LM101A is operated with a single supply (the neg·
ative supply pin is grounded). The common mode voltage
Va must be at least at a 2.0 VSE + VSAT above ground. R3
has been added to insure this when R2 = O. Furthermore
the bias current Is of the operational amplifier should be
negligible compared to the current flowing through the resistive divider.
Example:
VIN = 2SV
I = V340 R2 RS - R3 R4 + VINR1 R4 (R2 + R3)
R1
or if R2 + R3 = R4 + RS = R
V340 R2
1
I = R1 R4 + R1 2.0.00 is higher than indicated on th~ chart. The
graph of Figurs 5 can ~e used to find spot NF if en and Rgan
BJ:e known, or to find en If NF and Rgan are known. It can
also be used to find max Rgen allowed for a given max NF
when en is known. In any case, values are only valid if in
a,;
ROPT =;-
(7)
In
This has bean arrived at by differentiating Equation 4 with
respect to Rgen and equating it to zero (see Appendix). Note
that this does not mean loW8$t noise.
For example, using Flgurs2 to calculate ROPT at say 600
HZ,
1QnV
ROPT = - - = 14kO
.o.7pA
TABLE I. Noise CalculaUons for Example 2
SUMx~f
50-1.0.0 .
100-3.0.0 .
300,..10.0.0
1.Qk-1Qk
5.0-1.0,.0.0.0
5.0
2.0.0
7.oQ
900.0
995.0
Total eN = J2,626,QQQ
(2.0)2 = 4.0.0
(13)2 ;= 169
(1.0)2 = 1.0.0
(9)2 = 81
eR2 = (5.3)2 = 28 .
(8.7 x 2.Qk)2
(8 x 2.Qk)2
(7 x 2.Qk)2
(6x2.Qk)2
= 162.0 nV = 1.62 ""V
'The unils are as follows: (20 ~VlJHzi2
(8.7pA1v'FiiX2.0kO)2
= 400 (nV)2iHz
= (17.4nAlJHi')2 = 302 (nV)2/Hz
Sum =' 702 (nV)2/Hz x 50 Hz = 35,000 (nV)2
286
3.02
256
196
144
7.02· x5Q
425 x 2.0.0
296 x 7.0.0 .
225 x 9.000
28 x 995.0
(nV2)
35,00.0
85,00.0
2.07,000
2,.02.0,.000
279,.000
Then note in FlflurB 3. that eN is in the neighborhood of
20 nVl,fHz for Rgen of 14k. while eN = 10 nV/,fHz for
1. Choose sectional bandwidths of 1 octave each. these are
listed in the following table.
2. Read en from Figure 2 as average for each octave and
enter in the table.
3. Read in from Figure 2 as average for each octave and
enter in the table.
4. Read eA for the Rgen = 13S00 from Figure 4 and enter
in the table.
S. Determine the values of Zgen at the midpoint of each
octave and enter in the table.
6. Determine the amount of eA which reaches the amplifier
input; this is
_
R1
eA
R1 + Zgen
7. Read the noise contribution e47k of R1 = 47k from Fig-
Rgen = 0-100ft STOPI Do not pass GO. Do not be fooled.
Using Rgen = RoPT does not guarantee lowest noise UNLESS eslr/: = kRgen as in the case of transformer coupling.
When eslg2 > kRgen • as is the case where signal level is
proportional to Rgen (eslg = kRgen>. it makes sense to use
the highest practical value of Rgen. When eslg2 < kRgen• it
makes sense to use a value of Rgen < ROPT. These conclusions are verified in the Appendix.
This all means that It does not make sense to tamper with
the Rgen of existing signal sources in an attempt to make
Rgen = ROPT. Especially. do not add series resistance to a
source for this purpose. It does make sense to adjust Rgen
in transformer coupled circuits by manipulating turns ratio or
to design Rgen of a magnetic pick-up to operate with preamps where ROPT is known. It does make sense to increase
the design resistance of signal sources to match or exceed
ROPT so long as the signal voltage increases with Rgen in at
least the ratio 8sit/ ex: Rgen. It does not necessarily make
sense to select an amplifier with ROPT to match Rgen because one amplifier operating at Rgen = ROPT may produce
lower SIN than another (quieter) amplifier operating with
Rgen oF ROPT.
With some amplifiers it is possible to adjust ROPT over a
limited range by adjusting the first stage operating current
(the National LM121 and LM381 for example). With these.
one might increase operating current. varying ROPT. to find
a condition of minimum SIN. Increasing input stage current
decreases ROPT as en is decreased and in is simultaneously
increased.
Let us consider one additional case of a fairly complex nature just as a practical example which will point up some
factors often overlooked.
J:xample 4: Determine the SIN apparent to th9 eat of the
amplifier of Flflure 2 operating over SO-12.800 Hz when driven by a phonograph cartridge exhibiting Rgen = 13S00.
Lgen = O.SH. and average esig = 4.0 mVrms. The cartridge
is to be loaded by 47k as in Figure 6. This is equivalent to
using a Shure V1S. Type 3 for average level recorded music.
r----,
I
I
I
I
I
I
I
L...
0.5H
SlfURE VRI5111
I
L~~T~E.J
ure4.
8. Determine the amount of e47K which reaches the amplifier input; this is
_
Zgen
e47k R1 + Zgen
24
II
20
16
12
8.0
z 4.11
~
0
iil -4.0
a: -8.0
-12
-16
RI~\
"-ll
i
IX
-
,
r-
-20
-24
HF BOOST,
1.
WEIGHTINo'CURV
A FOR LOW LEVELS
(ASASOUND
MEASUREMENTSI
lao
10k
FREQUENCY (Hzl
TL/H17414-7
FIGURE 7. Relative Gain for RIAA,
ASA Weighting A, and H-F Boost Curves
r------------,
I
L _
FREQUENCY
SHAPING
CURVES
PREAMPLIFIER, CURVE SHAPING, TONE CONTROL.
~N.!!!!E~S~M~W!!!H~I!!SE!!.;.
_
I
.J
• RECOMMENDED LOAD
TL/H17414-6
FIGURE 6. Phono Preamp Noise Sources
287
......
•
0
Z
CC
13: Assume a tone control high frequency ·boost of 10 dB at
10kHz frOm r/(/UffJ 7. Again'determlne-'relative response
of octave midpoInts.
9. Determine the effective noise contributed· by in floWing
through the parallel combination of R1 and Zgeri' T-hlils
, Zgen R1
In
Zgen + R1
1D. Square all nOise voltage values resulting from stEiPS 2, 6,
8 and 9; and sum the squares.
14. Multiply all relative gain vaiiies of steps 11-13,"arid
" sqiJ$I'e tlie resUlt. .. . . .
,
'i 5. Multiply the sum of ,the ~uared "alues from stJP 10 by
the resuit8.nt relative gain of step 14".11!1 by
width in each octave. . '
oc:.
11. Determine the relative gain at the midpoint of each
tave from the RIAA playback response curve of F/gUffJ
7.
,
\
the, Qancj,
~"
16. Sum all the values resultant.from steP ,15, and find the
square root ,of the sl,lm, :rh~ Is the, totlll. audible rl'(1!J
. noise apparent in ~he band. ,
'
same
12. Determine the relative gain at these:.
midpoints
from the A weighted response curve of F/guffJ 7 for
sound level meters (this roughly accounts· for variations
in human hearing).
17. DMde. eai~ =
69.4 dB. ,! •
.4
·mv by the tot!l!i~: to..flnd SIr;.! =
"
';1
,'."
, ill'
~
STEPS FOR EXAMPLE
5
11
12
13
14
4
Frequency Band (Hz)
Bandwidth, B (Hz)
Bandcenter, f (Hz)
Zgen atf (0)
Zgen R1 (0)
Zgen/R1 + Zgen>
R1/(R1 + Zgen)
RIAA Gain, ARIM
Corr for Hearing, AA
H-F Boost, Aboost
Product of Gains, A
A2
9R (nV/.'Ri)
50-100 . 100-200
100'
50
150
75
1355
1425
1300
1360
0.028·
0.030
0.97
0.97
5.6
3.1
0.08
0.18
1
0.45
0.55
0.204
0.304
4.74
4.74
200-400
200
300
1665
1600
0.034
0.97·
2.0
0.45
1
0.9
0.81
400-800
·400'
600
2400
2270
0.485
0.95
1.4
0.80
4.74
4.74
1.12
1.26
800-1600 1.6-3.2k., 3.2-6.4k
600
1600
3200
1200
2400
4800
. '81.00
' 4220
16k
11.9k
6900
3900
0.082
0.145
0,255
0.92
0.74
0.8E!
1
0.45
Q;7
,1.
1.26
1.12
1.46
2.3
1.12
i'1.28
1.03
1.26
1.65
1.06
4)4
4.74
'4.74
6.4-12;6k
6400
9600
32k
19k "
0.400
0.6<>.
D.316"
.,0.5
3.1
0.49,
,0.241
4.74
7
947k (nVl.'Ri)
29
29
29
29
29
29
29
29
3
in (pA/.'Ri)
0.85
0.80
0.77
0.72
0.65
0.62
0.6q
0.60
2
en (nVl.'Ri)
19
14
11
10
9.5
9
9
6
8
10
1.1
1.09
e1 = in (Zgen R1)
·4.35
4.35
92 = 9R R1/(R1 + Zgen)
0.81
0.87
93 = 847k Zgan/ (Rl + Zgan>
e n2
360
195
1.21
1.2
e12 (from in)
e22 (from eR)
19
19
0.65
0.76
e32 (from e47kl
l:en2 (n\l2/Hz)
381
216
BA2(Hz)
10.2
30ABA2l:Ei2 (nV2j
3880
6550
l:re;;j2 + e1 j2 + e2 j2 + 83j2l BjAj2 = 1,815,930 nV2
1.23
4.35
0.98
121
1.5
19
0.96
142
162
23000
1.63.
4.25 .
1.4
100
2.65
18
2
122
504
61500
2.55
,4.15
2.4
90
6.5
17
5.8
120
1010
121000
4.3
3.86
4.2
81
18.5
15
18
.133
2640
350000
15
16
eN
17
= .J! =
1.337 p.V
SIN = 20 log (4.0 mVll.337 p.V) = 69.4 dB
288
,9
7.1
3.33
7.4
81
50
11
55
147
3400
670000
9
11.4
2.7
11.6
81
150
7.2
135
373
1550
580000
CONCLUSIONS
The main points in selecting low noise preamplifiers are:
1. Don't pad the signal source; live with the existing Rgen.
2. Select on the basis of low values of en and especially in if
Rgen is over about a thousand o.
3. Don't select on the basis of NF or ROPT in most cases.
NF specs are all right so long as you know preCisely how
to use them and so long as they are valid over the frequency band for the Rgen or Zgen with which you must
work.
4. Be sure to (root) sum all the noise sources en, in and eA
in your system over appropriate bandwidth.
5. The higher frequencies are often the most important unless there is low frequency boost or high frequency attenuation in the system.
8. Don't forget the filtering effect of the human ear in audio
systems. Know the eventual frequency emphasis or filtering to be employed.
Note the significant contributions of in and the 47k resistor,
especially at high frequencies. Note also that there will be a
difference between calculated noise and that noise measured on broadband meters because of the A curve employed in the example. If it were not for the A curve attenuation at low frequencies, the en would add a very important
contribution below 200 Hz. This would be due to the RIAA
boost at low frequency. As it stands, 97% of the 1.35 p.V
would occur in the 800-12.8 kHz band alone, principally
because of the high frequency boost and the A measurement curve. If the measurement were made without either
the high frequency boost or the A curve, the en would be
1.25 p.V. In this case, 76% of the total noise would arise in
the 50 Hz-400 Hz band alone. If the A curve were used, but
the high-frequency boost were deleted, en would be
0.91 p.V; and 94% would arise in the 800-12,800 Hz band
alone.
The three different methods of measuring would only produce a difference of + 3.5 dB in overall SIN, however the
prime sources of the largest part of the noise and the frequency charscter of the noise can vary greatly with the test
or measurement conditions. It is, then, quite important to
know the method of measurement in order to know which
individual noise sources in FIflUf9 6 must be reduced in order to significantly improve SIN.
APPENDIX I
Derivation of ROPT:
eA2 + en2 + in2 Rgen2
NF = 10 log -"'--~==-';':'-''''':':';~
eA2
10 log (1
+8,;2 + 1;;2 Rgen2)
eA2
_8N_F = 0.435 4 kTRB (2R 1;;2) - (8,;2 + 1;;2 R2)4 kTB
8R
(4 kTRB)2
1 + (en2 + in2 R2)/4 kTRB
where: R = Rgen
Set this = 0, and
4 kTRB(2R 1;;2) = 4 kTB (en2
+ r,;2 R2)
2 in2 R2 = en2 + in2R2
r,;2 R2
= en2
R2 = en2/r,;2
en
ROPT=,
In
APPENDIX II
Selecting Rgen for highest SIN.
SIN
=
B(8R2
es~
+ en2 + in2 R2)
For SIN to increase with R,
8S/N > 0
8R
8SIN = 2eslg (8esig/8R) (9fj2
SR
+ 8,;2 + 1;;2 R2) - eSig2 (4 kT + 21;;2R)
+ en2 + in2 R2)2
B(eA2
289
~
__
~
APPENDIX" (Continued)
If we set> 0, then
2 (8e8ig/8 R)(eR2 + en? + ~ R2) > esig (4 kT .-+' 2 in2 R)
For esig
rn
k1
= k1 vR,
8esig/8R = 2.JR
(2 k1/2.JR)(eR2 + en2 + I;;2 R2) > k1.JR (4 kT + 2 r;;2 R)
eR2 + en2 + In2 R2 > 4 kTR + 2,1;;2 R2
en2 > I;;2 R2
Therefore SIN increases with Rgen so long as Rgen ~ ROPT
For esig = k1 R,8esig/8R ;" k1
2 k1
reR2 +
en? + I;;2 R2) > k1 R (4 kT + 2 I;;2 R)
2eR2 + 2 en2 + 2I;;2R2 > 4 kTR + 2 in2 R2
eR2+ 2en2 >0
Then SIN incresses with Rgen for any amplifier.
For any esig
< k1 .JR, an optimum Rgen may be determined. Take, for example, esig = k1 RO.4, 8esig/8R = 0.4k1 R-O.6
(0.8 k1/RO.6) (eR2 + en2 + in2 R2) > k1 ROA (4 kT + 2 in? R)
0.8 eR2 + 0.8 en2 + 0.8 in2 R2 > 4 kTR + 2 in2 R2
0.8 en2 > 0.2 eR2 + 1.2 I;;2 R2
Then SIN incresses with Rgeri until
0.25 eR2 + 1.5 in2 R2 = en2
290
Fast Ie Power Transistor
with Thermal Protection
~•
-
National Semiconductor
Application Note 110
INTRODUCTION
Overload protection is perhaps most necessary in power
circuitry. This is shown by recent trends in power transistor
technology. Safe-area, voltage and current handling capability have been increased to limits far in excess of package
power dissipation. In RF transistors, devices are now available and able to withstand badly mismatched loads without
destruction. However, for anyone working with power transistors, they are still easily destroyed.
Since power circuitry, in many cases, drives other low level
circuitry-such as a voltage regulator-protection is doubly
important. Overloads that cause power transistor failure can
result in the destruction of the entire circuit. This is because
the common failure mode for power transistors is a short
from collector to emitter-applying full voltage to the load.
In the case of a voltage regulator, the raw supply voltage
would be applied to the low level circuitry.
A new monolithic power transistor provides virtually absolute protection against any type of overload. Included on the
chip are current limiting, safe area protection and thermal
limiting. Current limiting controls the peak current through
the chip to a safe level below the fuzing current of the aluminum metalization. At high collector to emitter voltage the
safe area limiting reduces the peak current to further protect
the power transistor. If, under prolonged overload, power
dissipation causes chip temperature to rise toward destructive levels, thermal limiting turns off the device keeping the
devices at a safe temperature. The inclusion of thermal limitlng, a feature not easily available in discrete circuitry
makes this device especially attractive in applications where
normal protective schemes are ineffective.
The device's high gain and fast response further reduce
requirements of surrounding circuitry. As well as being used
in linear applications, the IC can interface transistor-transistor logiC or complementary-MOS logic to power loads without extemal devices. In fact, the input-current requirement
of 3 microamperes is small enough for one CMOS' gate to
drive over 400 LM195's.
Besides high dc current gain, the IC has low input capacitance so it can be easily driven from high impedance sources--even at high frequencies. In a standard TO-3 power
package, the monolithic structure ties the emitter, rather
than the collector, to the case effectively boot-strapping the
base-to-package capaCitance. Additionally, connecting the
emitter to the package is especially convenient for grounded emitter circuits.
The device is fully protected against any overload condition
when it is used below the maximum voltage rating. The current-limiting circuitry restricts the power dissipation to 35
watts, 1.8 amperes are available at collector-to-emitter volt-
o
age of 17V decreasing to about 0.8 amperes at 40V. In reality, however, like standard transistors, power dissipation in
actual use is limited by the size of the external heat sink.
Switching time is fast also. At 40V 25 Ohm load can be
switched on or off in a relatively fast 500 ns. The internal
planar double diffused monolithic transistors have an fl of
200 MHz to 400 MHz. The limiting factor on overall speed is
the protective and biasing circuitry around the output transistors. An important performance pOint is that no more than
the normal 3 p.A base current is needed for fast switching.
To the deSigner, the LM195 acts like an ordinary power transistor, and its operation is almost identical to that of a standard power device. However, it provides almost absolute
protection against any type of overload. And, since it is manufactured with standard seven-mask IC technology, the device is produceable in large quantities at reasonable cost.
CIRCUIT DESIGN
Besides the protective features, the monolithic power transistor should function as closely to a discrete transistor as
possible. Of course, due to the circuitry on the chip, there
will be some differences.
Figure 1 shows a simplified schematic of the power transistor. A power NPN Darlington is driven by an input PNP. The
PNP and output NPN's are biased by internal current source
11. The composite three transistors yield a total current gain
in excess of 106 making it easy to drive the power transistors from high impedance sources. Unlike normal power
tranSistors, the base current is negative, flowing out of the
PNP. However, in most cases this is not a prOblem.
I
---,
I
I
BASE I
I
I
I
I
I
.-------
I
I
I
I
I
I
I
I
IL _ _ _ _ _ _ _ _ _
TL/H17418-1
FIGURE 1. Simplified Circuit of the LM195
291
o
........
~
r-----------------------------------------------------------------------------~
straight line decrease in Qutput current as input voltage increases.
Trarjsistor 013 thermally limits the device by removing the
base drive at high temperatUre. The actual temperature
sensing is done by 011 and 012 with 010 regulating the
voltage across the sensors so thermal limit temperature remains independent of supply. As temperature increases, the
collector current of 011 increases while the VeE of 012
decreases. At about 17O"C the 012 turns'on 013 removing
the base drive from the output transistors. Finally, Cl, 02
and 03 boost operating currents during switching to obtain
faster response time and 017 and 018 compensate for ~e
variations in the power devices.
The Input PNP transistor is made with standard IC processing and has a reverse base-emitter breakdown, voltage in
excess of 40V. This allows the power transistor to be driven
\ trom a stiff voltage source without damage due to excessive
base current. At input voltages in excess of about 1V the
input PNP becomes reverse biased and no current is drawn
from the base lead. In fact it is possible for the base of the
monolithic transistor to be driven with up to 40V even
though the collector to emitter voltage is low. Further, the
input PNP isolates the base drive from the protective circuitry insuring that even with high base drive the device will be
protected. When the device is turned off current 11 is shunted from the base of the NPN transistor by the PNP and
appears at the emitter terminal. This sets the minimum load
current to about 2 mA, not a severe restriction fo~ a power
transistor. Because of the PNP and 11, the power transistor
turns "on" rather than "off" if the base is opened; however,
most power circuits already include a base-emitter resistor
to absorb leakage currents in present power transistors.
A schematic of the LM195 is shown in Fl(}ure 2. The circuitry
is biased by four current sources comprised of 04, 07, 08
and 09. The operating current is set by 05 and 06 and is
relatively independent of, supply voltage. FET 01 and R2
insure reliable starting of the bias circuitry while 01 clamps
the output of the FET limiting the starting current at high
supply voltage.
The output transistors 019 and 020 are driven from input
PNP 014. Current limiting independent of temperature
changes is provided by 021,016, and 015. At high collector to emitter voltages the current limit decreases due to the
voltage across R21 from 03, 04 and R20. The double emitter structure used on 021 allows the power limiting to more
closely approximate constant power curve rather than a
PERFORMANCE
The ,new power transistor is packaged in a,standard TO-3
transistor package making it compatible with standard power tranSistors. An ac;lc;led advantage of the monolithic struqture is that the emitter is tied ,to tl:le case rather than the
collector. This,allows the device to be connected directly to
ground in collector output applications.
A photomicrograph of the LM195 is shown in Figure 3. More
than half of the die area is needed for the output power
transistor (020). Actually, the power transistor is many individual small transistors connected in parallel with a common
colleCtor. Partitioning the power device into small discrete
areas improves power handling over a Single large device.
Firstly, the power device has ten base sections spread
across ,the chip. Between the base diffusion are N + collector contacts. Each section has its own emitter ballasting
resistor to insure current sharing between sections. One of
these resistors is used to sense the output current for current limiting.
COLLECTOR
RU
1.1
EMInER
R21
30
BASE
TLlH/7418-2
FIGURE 2. Schematic Diagram of the LM195
292
r--------------------------------------------------------------------------.
voltage drop from debiasing a section of the stripe at high
operating currents. All current in the stripe flows out through
the small ballasting resistor where it is summed with the
currents from the other stripes in the section. The partitioning in conjunction with the emitter resistor gives a power
transistor with large safe-area and good power handling capability.
APPLICATIONS
With the full protection and high gain offered by this monolithic power transistor, circuit design is considerably simplified. The inclusion of thermal limiting, not normally available
in discrete design allows the use of smaller heat sinks than
with conventional protection circuitry. Further, circuits where
protection of the power device is difficult-if not impossible-now cause no problems.
TL/H1741 B-3
FIGURE 3. LM195 Chip
For example, with only current limiting, the power transistor
heat sink must be designed to dissipate worst case overload power dissipation at maximum ambient temperature.
When the power transistor is thermally limited, only normal
power need be dissipated by the heat sink. During overload,
the device is allowed to heat up and thermally limit, drastically reducing the size of the heat sink needed.
TABLE I. Typical Performance
Collector to Emitter Voltage
Base to Emitter Voltage (max.)
Peak Collector Current (intemally limited)
42V
42V
1.8 amps
Reverse Base Emitter Voltage
20V
Base to Emitter Voltage (Ie = 1.0 amp)
0.9V
Base Current
3/LA
Saturation Voltage
Switching circuits such as lamp drivers, solenoid drivers or
switching regulators do not diSsipate much power during
normal operation and usually no heat sink is necessary.
However, during overload, the full supply voltage times the
maximum output current must be dissipated. Without a large
heat sink standard power transistors are quickly destroyed.
2V
Switching Time (turn on or turn off)
Power Dissipation (internally limited)
Thermal Limit Temperature
Maximum Operating Temperature
Thermal Resistance (Junction to Case)
SOO ns
3Swatts
16SoC
USing this new device is easier than standard power transistors but a few precautions should be observed. About the
only way the device can be destroyed is excessive collector
to emitter voltage or improper power supply polarity. Sometimes when used as an emitter follower, low level high frequency oscillations can occur. These are easily cured inserting a 5k-10k resistor in series with the base lead. The
resistor will eliminate the oscillation without effecting speed
or performance. Good power supply bypasSing should also
be used since this is a high frequency device.
1SO"C
2.3°C/W
A detail of one of the base sections is shown in Figure 4. An
interdigitated structure is used with alternating base contacts and emitter stripes. Integrated into each emitter is an
individual emitter ballasting resistor to insure equal current
sharing between emitters in each section. Aluminum metalization runs the length of the emitter stripe to prevent lateral
P
DIFFUSION
TL/H/741B-4
FIGURE 4. Detailed Structure of one Section of the Power Transistor
293
~
::r:
....
....
Q
........
C) ~------------------------------------------------------------------------------------~
~-1~-------------'
z
38V.
c(
11"
-
L...'I/\""'+__ =
"tJUTPUT
~-.r'1' "'. " - + - + - + - 4 . 6 V -30V
Rl
Dl
LMI03
3.9V
R6
lk
LM105
R2
390k
+
R8
2k
R3.
4
2k
'Sixty turns wound on arnold type A·083081·2 core.
··Four devices in parallel.
tSolid tantalum.
TL/H17418-5
FIGURE 5. 6 Amp Variable Output Switching Regulator
Figure 5 shows a 6 amp, variable output switching regulator
LMI96
for general purpose applications. An LM10S positive regulator is used as the amplifier-reference for the switching regulator. Positive feedback to induce switching is obtained from
the LM10S at pin 1 through an LM103 diode. The positive
feedback is applied to the internal amplifier at pin S and is
independent of supply voltage. This forces .the LM105 to
drive the pass devices either "on" or "off," rather than linearly controlling their conduction. Negative feedback, delayed by L1 and the output capacitor, G2, causes the regulator to switch with the duty cycle automatically adjusting to
provide a constant output. Four LM19S's are used in parallel
to obtain a 6 amp output since each device can only supply
about 2 amps. Note that no ballasting resistors are needed
for current sharing. When 01 turns "on" all bases are pulled
up to V+ and no base current flows in the LM19S transistors since the input PNP's are reverse biased.
+
~.
..
TLlH17418-6
FIGURE 6. Two Tennl~ Current Umlter
The low base current make this power device suitable for
many unique applications. Ftgure 7 shows a time delay circuit. Upon application of power or 81 closing, the load is
energized. capacitor C1 slowly charges toward V- through
A1. When the voltage across A1 decreases below about 0.8
volts the load is de-energized. Long delays can be obtained
with small capacitor values since a high reSistance can be
used.
A two terminal current/power limiter is shown in Figure 6.
The base and collector are Shorted-turning the power transistor on. If the load cu~rent exceeds 2 amps, the device
current limits protecting the load. If the overload remains on,
the device will thermal limit, further protecting itself and the
load. In normal operation, 'only 2V appear across the device
so high efficiency is realized and no heat sink is needed •.
Another method of protection would be to place the mo'nolithic power transistor on a common heat sink with the devices to be protected. Overheating will then cause the
LM195 to thermal limit protecting the rest of the circuitry.
-
....--~..... +15V
01
LM196
CI
llIpF
TL/HI7418-7
. FIGURE 7. TIme Delay Circuit
294
........~
o
YIN
3BY
TLlHn418-B
FIGURE 8. 1 Amp Positive Voltage Regulator
AI
6k
R8
2k
NC
10.,t
l-~------t---t----O~~~
1A
R2
Uk
~------------~-------YTLlHn418-9
FIGURE 9. 1 Amp Negative Regulator
F/fIUf9S 8 and 9 show how the LM195 can be used with
from the collector to base. Less than 20 p.A from the diode
is needed to turn the LM195 fully on.
standard IC's to make positive or negative voltage regulators. Since the current gain of the LM195 is so high, both
regulators have better than 2 mV load regulation. They are
both fully overload protected and will operate with only 2V
input-to-output voltage differential.
An optically isolated power transistor is shown in Figure 10.
01 and 02 are almost any standard optical isolator. With no
drive, R1 absorbs the base current of 01 holding it off.
When power Is applied to the LED, 02 allows current to flow
d~
q------
An alternate connection for better ac response is to return
the cathode of 02 to separate positive supply rather than
the collector of 01, as shown in Figuf9 11, eliminating the
added collector to base capacitance of the diode. With this
circuit a 40V 1 amp load can be switched in 500 ns. Of
course, any photosensitive diode can be used instead of the
opto-isolator to make a light activated switch.
a~
...---....---+
g-----
Q1
LMIII
....-----t--y+
O~~
R1
lOOk
-
....- - - 4 I - - v TL/Hn418-11
FIGURE 11. Fast Optically Isolated SWitch
TLlH/7418-10
FIGURE 10. Optically Isolated Power Transistor
295
Q~--------------------------------------------------~
~
i
Ifv-1~----------------~
HI
5k'
HI
&1_
...- -....- - EMITTER
BASE --JWIr-'t--t
HZ
SOD,,··
lillie
02
LMI85
"""""Ive
111\13
R3
'Protects against
baSe drive.
"Needed fot stability. '..
BULB
471t
' - - -....- - COLLECTOR
TUH17418-13
FIGURE 13. PttP Configuration for LM195
FIGURE 12. 1 Amp Lamp Flasher TL/H17418-12
+15V
R.
IIIGk
R2
10k
LI
R4
5.lk
22TUHNS
ONRB
OUTPUT
RI
RS
IUk
10k
INPUT .....'W"'"". .
HI
"V'\,..,._...
I
2W
02
LM\9&
• Adjust for 50 rnA quiescent current.
tSolid tantalum.
-I&V
.FIGURE 14. Power Op Amp,
A power lamp flasher is shown in Figure 12. It is designed to
flash a 12V bulb at about a on.;:e-per second rate. The re-.
vE!l'Se base current of 02 provides biasing for 01 eliminating
the need for a resistor. Typically,"a cold bulb can draw 8
times its normal.operating current. Since,the LM195 is current limitad, high peak currents to the bulb are not experienced during turn-on. This prolongs bulb life as well as easing the load on the power supply.
Since no PNP equivalent of this device is available. it is
advantsgeous to use theLM195 in a quasi-complementary
configuration to simulate a power PNP. Figure 13 shows a
quasi PNP mada'wHh an LM195. A low current PNP is used
to drive the LM195 as the power output device"Resistor R1
protects againSt overdrive destroying the PNP and, in conjunction with C1, ftequency compensates the loop against
oscillations. Resistor R2 sets'the operating current for the
PNP and limits the collector current.
Flf}u~ 14 shows a power op amp wi,th a quasi-complementary power output stage. 01 and 02 form the equivalent of a
power PNP. The circuit is simply an op amp with a power
output stage. As shown, the circuit is stable for almost any
load. Better bandwidth can be obtained by decreasing C1 to
15 pF (to obtain 150 kHz full output response), but capaci-
TUH17418-14
tive loads can cause oscillation. If due to layout, the quasi-'
complimentary ·Ioop oscillates, collector to base capaci-'
tance on 01 will stabilize it. A Simpler power'op amp for up
to 300 Hz operation is shown in Figure 15.
One of the more difficult circuit types to protect is a current
regulator. Since the current is already fixed, normal protec"
tion doesn't work. Circuits to limit the voltage'across the
current regulator may allow exceSsive' current to flow
through the load. About the only protection method that protects both the regulator and',the driven circuit is thermal limiting.
.".
A 100 mA, two terminal regulator is shown in Figure 16. The
circuit has low temperature' coefficient and 'operates down
to 3V. Once again, the reverSe base current of the LM195 to
bias the operating Circuitry.
A 2N2222 is used to control the voltage across a current
sensing resistor, R2 and diode 01, and therefore the current
through it. rhe voltage across the sense network is the VeE
of thE! 2N2222 plu!l,1.• 2V.,from the L~,l-\3. In the sense network R2 sets the current while 01 compensates for the VeE
of the transistor. Resistor R1 sets the current through the
LM113 to 0.6 mAo
296
$...
...
C)
r-------------+---+
RF
15v
10k
Cl
15pF
lis
-y,.,.,...-...
10k
INPUT
_~
L---------~~---15V
C5t
+:;!:O
I".F
TUH17418-15
FIGURE 15. 1 Amp Voltage Follower
+
Cl
50 pF
TUH17418-16
FIGURE 16. Two Terminal 100 mA Current Regulator
seven mask IC technology making it produceable in large
quantities at reasonable prices. Finally. in addition to the
protection features, it has high gain Simplifying surrounding
circuitry.
CONCLUSIONS
A new IC power transistor has been developed that significantly improves power circuitry reliability. The device is virtually impossible to destroy through abuse. Further it has high
gain and fast response. It Is manufactured with standard
297
........
z011( Use the LM158/LM2581
co
~
National Semiconductor
Application Note 116
LM358 Dual, Single Supply
OpAmp
INTRODUCTION
Use the LM158/LM258/LM358 dual op amp with a single
supply in place of the LM1458/LM1558 wHh split supply and
reap the profits In terms of:
In many applications the LM158/LM258/LM358 can also
be used directly in place of LM1558 for split supply operation.
a. Input and output voltage range down to the negative
(ground) rail
SINGLE SUPPLY OPERATION
b. Single supply operation
c. Lower standby power dissipation
d. Higher output voltage swing
e. Lower input offset current
f. Generally similar performance otherwise
The main advantage, of course, is that you can eliminate the
negative supply in many applications and stili retain equivalent op amp performance. Additionally, and In some cases
more importantly, the Input and output levels are permitted
to swing down to ground (negative rail) potential. Table I
shows the relative performance of the two in terms of guaranteed and/or typical specifications.
The LM1458/LM1558 or similar op amps exhibit several important limitations when operated from a single positive (or
negative) supply. Chief among these is that input and output
signal swing is severely limited for a given supply as shown
in F/fJurB 1. For linear operation, the input voltage must not
reach within 3 volts of ground or of the supply, and output
range is similarly limited to within 3-5 volts of ground or
supply. This means that operation with a +12V supply
could be limited as low as 2 Vp-p output swing. The LM358
however, allows a 10.5 Vp-p output swing for the same 12V
supply. Admittedly these are worst case specification limits,
but they serve to illustrate the problem.
TABLE I. Comparison of Dual Op Amps LM1458 and LM358
CharaCteristic
LM1458
LM358
VIO
6mVMax
7mVMax
CMVI
24Vp-p'
0-28.5V·
110
200nA
50nA
loa
500nA.
-500nA
CMRR
60 dB Min @ 100 Hz
90dBTyp
85 dB Typ @DC
en @ 1 kHz, RGEN 10 kO
45 nVlJHzTyp
40 nV/JHzTyp"
ZIN
200 MO Typ
Typ 100MO
AVOL
20kMin
100kTyp
100kTyp
fe
1.1 MHzTyp
1 MHz Typ"
Paw
14 kHzTyp
11 kHz Typ"
dVo/dt
0.8V1 pos Typ
0.5V/ pos Typ"
24/20Vp-p'
28.5Vp-p
IsC
20mATyp
Source 20 mA Min (40 Typ) .
10 mA Min (20 Typ)
Sink
PSRR@DC
37 dB Min
90 dB Typ
100dBTyp
= 00)
8mAMax
2mAMax
V o @ flL
10 (RL
= 10k/2k
*From laboratory measurement
'Based on Vs = 30V on LM358 only. or Vs = ± 15V
"From data sheet typical curves
.'
~
....
....•
+I2V
+IZV
G)
TLlH17424-1
TLlH17424-2
FIGURE 1. Worst ease Signal Levels with
V,.
+ 12V Supply
o-f t-'W~""
I.
R
Vo= 10;t.5V
R
+2OV
0-01\1"""''''--+-1
TLlHI7424-3
TLlH17424-4
FIGURE 2. Operating with AC Signals
ACGAIN
For AC signals the input can be capacitor coupled. The in·
put common mode and quiescent output voltages are fixed
at one-half the supply voltage by a resistive divider at the
non-inverting input as shown in Figure 2. This quiescent out·
put could be set at a lower voltage to minimize power dissipation in the LM358, if desired, so long as Va ~ V,N pk. For
the LM1458 the quiescent output must be higher, Va ~ 3V
+ V,N pk thus, for small signals, power dissipation is much
greater with the LM1458. Example: RequiredVo = Va ±1V
pk into 2k, VSUPPLY = as required. Find quiescent dissipation in load and amplifier for LM1458 and LM358.
The LM1458 requires over twice the supply voltage and
nearly 10 times the supply power of the LM358 in this application.
INVERTING DC GAIN
Connections and biasing for DC inverting gain are essential·
Iy the same as for the AC coupled case. Note, of course,
that the output cannot SWing negative when operated from a
single positive supply. Figure 3 shows the connections and
signal limitations.
NON-INVERTING DC GAIN
The non·inverting gain connection does not require the Va
biasing as before; the inverting input can be returned to
ground in the usual manner for gains greater than unity, (see
Ftgure 4). A tremendous advantage of the LM358 in this
connection is that input signals and output may extend all
the way to ground; therefore DC Signals in the low-millivolt
range can be handled. The LM1458 still requires that
V,N = 3-17V. Therefore maximum gain is limited to Av =
(Vo-3)/3, or Av max = 5.4 for a 20V supply.
There is no similar limitation for the LM358.
LM1458
LM358
Va=+1V
Va=4V
VSUPPLY= +3.5V
EL2
1
PLOAO=-= -=0.5 mW
RL 2k
VSUPPLy=8V
Po=Vsl~+(Vs-Va>IL
PO=P/1+ (Vs-Va) IL
4V
=22mW+(8- 4
42
PLOAO=2k =8mW
l2k
=3.5VXO.7 mA+(3.5-1)1V
2k
PO= 2.45 + 1.25=3.7 mW
Po=22+8=30mW
PrOTAL =3.7+0.5=4.2 mW
PrOTAL =30+8=38 mW
"From typical characteristics
"From typical characteristics
299
....
....
U) r-------------------------------------------------------------------------------------~
ZERO T.C.INPUT BIAS CURRENT
BALANCED SUPPLY OPERATION
~
The LM358 will operate satisfactorily in balanced supplyoperation so long as a load is maintained from output to the
negative supply.
An interesting and unusual characteristic is that liN has a
zero temperature coefficient. This means that matched resistance is not required at the input, allowing omission of
one resistor per op amp from the circuit in most cases.
Yo' 8-18.5Y
+2av o-J\lV\r"'--"'~
TUHI7424-5
TUH17424-6
FIGURE 3. Typical DC Coupled Inverting Gain
> ....-0 Vo· 0-1I.5V
10k
YIN = 8-18.5"
,
'RI = 00 forAy = +1
Ay ,;; 5.4 for 20V Supply
0--'\1""'..----1
'RI = 00 forAy = +1
Ay not limited
TUH/7424-7
FIGURE 4. Typical DC Coupled Non-Inverting Gain
>-4-0Vo
, Crossover (distortion) occurs alVo =
Ys':' R RFR
'
L+ F
FIGURE 5. Split Supply Operation of LM358
300
TL/HI7424-9
10k
TUHI7424-8
The output load to negative supply forces the amplifier to
source some minimum current at all times, thus eliminating
crossover distortion. Crossover distortion without this load
would be more severe than that expected with the normal
op amp. Since the Single supply design took notice of this
normal load connection to ground, a class AS output stage
was not included. Where ground referenced feedback resistors are used as in Figure 5, the required load to the negative supply depends upon the peak negative output signal
level desired without exhibiting crossover distortion. RL to
the negative rail should be chosen small enough that the
voltage divider formed by RF and RL will permit Vo to swing
negative to the desired point according to the equation:
RL = RF Vs ~ Vo.
RL could also be returned to the positive supply with the
advantage that Vo max would never exceed (ys+ - 1.5V).
Then with ±15V supplies RL MIN would be 0.12 RF. The
disadvantage would be that the LM358 can source twice as
much current as it can sink, therefore RL to negative supply
can be one-half the value of RL to positive supply.
The need for single or split supply is based on system requirements which may be other than op amp oriented. However if the only need for balanced supplies is to simplify the
biasing of op amps, there are many systems which can find
a cost effective benefit in operating LM358's from single
supplies rather than standard op amps from balanced supplies. Of the usual op amp circuits, Table II shows those few
which have limited function with single supply operation.
Most are based on the premise that to operate from a single
supply, a reference Va at about one-half the supply be available for bias or (zero) Signal reference. The basic circuits
are those listed In AN-20.
TABLE II. Conventional Op Amp Circuits
Suitable for Single Supply Operation
Application
AC Coupled amp:!:
Inverting amp
Non-inverting amp
Unity gain buffer
Summing amp
Difference amp
Differentiator
Integrator
LP Filter
I-V Connector
PE Cell Amp
I Source
I sink
Volt Ref
FWRectifier
Sine wave osc
Triangle generator
Threshold detector
Tracking, regulator PS
Programmable PS
Peak Detector
Limitations
Va·
Va
OK·
OK
Va
Va
Va
Va
Va
Va
OK
1.5
10 MIN = OK
R1
OK
Va or modified circuit
Va
Va
OK
Not practical
OK
OKtoVIN = 0
*See AN20 lor conventional circuits
'va denotes need for a reference voltage. usually at about
~•
.....
.....
G)
~
OK means no reference voltage required
II
I'
301
National Semiconductor
Application Note '1 'Z1
LM 143 Monolithic'
High Voltage
Operational Amplifier
Applications
~
..
INTRODUCTION
The LM143 is a general purpose, high voltage opera~ional
amplifier featuring ± 40V maximum supply voltage operation, output swing to ±37V, ±38V input common-mode
range, input overvoltage protection up to ± 40V and slew
rate greater than 2V1p,s·. Offset null capability plus low input bias and offset currents (8 nA and 1 nA respectively)
minimize errors in both high and low source impedance applications. Due to isothermal symmetry of the chip layout,
gain,is constant for loads;., 2 k!l at output levels to ±37V.
Because of these features, the LM 143 offers advantages
not found in other general purpose op amps. The LM143
may, in fact, be used as an improved performance, plug-in
replacement for the LM741 in most applications.
This paper desdribes the operation of the LM143 and presents applications which take advantage of its. unique, high
voltage capabilities. Obviously, other applications 'exist
where the low input current and high slew rate of the LM143
are useful. (See AN-29 on the LM108.) Application tips are
included in the appendix to guide the user toward reliable,
trouble-free operation.
'
CIRCUIT DESCRIPTION
A simplified schematic of the LM143, shown in Figure 1,
illustrates the basic circuit operation. The super-,8 input
transistors(1), 01 and 02, are used as emitter followers to
achieve low input bias currents. Although these devices exhibit,8 = 2000-5000, they inherently have a low collectorbase breakdown voltage of about 4V. Therefore, active voltage clamps 03 and Q4 protect 01 and 02 under all input
conditipns including common-mode and differential overvoltage. Other NPNs in the circuit are representative of
those found in standard IC op amps (,8 :::: 200, LVCEO =
50-70V).
The input stage differential amplifier 07 and 08 with large
base width exhibit LVCEO == 90V to 110V and high BVEBO
so readily withstand input overvoltages. The total input
stage collector current (11 ~ 80 p,A) is made higher than in
most op amps to improve slew rate. Emitter degeneration
resistors, R10 and R11, reduce transconductance(2) to, limit
small signal bandwidth at 1 MHz for a phase margin of 75'.
016 and 017 function as active collector loads for 07 and
08.and provide differential to single-ended current conversion with full differential gain.
One of the highest breakdown voltages available in standard planar NPN processing is the collector-base, BVCBO
which is typically 90V to 120V. To make use of this high
voltage capability in the active region, the second stage
consists of a cascode (common emitter-common base pair)
connection of 021 and 023. The internal voltage bias VB1,
shunts avalanche-induced leakage current away from the
base of .021, avoiding ,8 multiplication as found in the
LVCEO mode. 023 and emitter follower 022 are internally
biased at a low voltage so the BVCEO mode is impossible.
Frequency compensation is achieved with an intemal, high
voltage capacitor, Cc.
• An externally compensated version Of the LM143,Ihe LMI44, offers even
higher slew rale In moat appllca1lons. The LM144 Is pln·for·pln competible
with the LM101A,
-IN
R28
3.
vTL/HI7432-1
FIGURE 1. LM143 Simplified Schematic
302
The second stage drives a complementary class AB output
stage. A cascade connectiOn of 032 and 034 is again employed for high breakdown voltage. The associated voltage
bias, VB2, is internally derived. A Darlington PNP pair, 039
and 040 with BVCEO = 100V, provides the active pulldown.
HIGH VOLTAGE APPLICATIONS
The following applications make use of the high voltage capabilities of the LM143. As with most general purpose op
amps, the power supplies should be adequately bypassed
to ground with 0.1 ",F capacitors.
R3
Ilik
v-· -3IV 0-_ _- - -..
130 Vp-p Drive to a Floating Load
R4
IIOk
A circuit diagram using two LM143's to drive up to 130V
peak-to-peak is given in Figure 2.
V2
A non-Inverting voltage amplifier, with a gain of Av = 1 +
(R2/R1), is followed by a unity gain inverter. The load is
applied across the outputs of A 1 and A2. Therefore,
VOUT = V1 - V2 = V1 - (-V1) = 2Vl. If V1 = 65 Vp-p,
then 2V1 = 130 Vp-p.
All resistors are 1%, 1/4W
TUHI7432-2
FIGURE 2. 130V Drive Across a Floating Load
signals since voltages V1 and V2 are in phase, and no current flow is developed through R1, R2 and R3. The second
stage is simply an op amp connected as a simple differential
amplifier of gain, AV2 = (R5/R4), where R5 = R7 and
R4 = R6. The total gain of the instrumentation amplifier is
The above circuit was breadboarded and the results are as
follows:
i) Maximum output voltage: 138 Vp-p unclipped into 10 kO
load
ii ) Slew rate: 6VI "'s
± 34V Common-Mode Range Instrumentation AmplHler
An instrumentation amplifier with ±34V common-mode
range, high input impedance and a gain of X1000 is shown
in Figure 3.
Av = (1
+ 2R~1)
(::) = (1
+ 2 2~.~~~k)(\~~)
= 1000
R7 may be adjusted to take up the resistance tolerances of
R4, R5 and R6 for best common-mode rejection (CMR).
Also, R2 may be made adjustable to vary the gain of the
instrumentation amplifier without degrading the CMR.
For a differential input signal, VIN, A1 and A2 act as non-inverting amplifiers of gain AVl = 1 + (2R1/R2), where
R1 = R3. However, the gain is unity for common-mode
... ........
........................
........
.;:IV1
10k
....
"
05
1.I1M
01
lOOk
All resistors are 1%,
y.w
'A2 may be adiustable to trim the gain.
"A7 may be adjusted to compensate for the
for best CMA.
TLfHI7432-3
FIGURE 3. Wide Common·Mode Range Instrumentation Amplifier
303
resistance tolerance of A4-A7
The non~invElrting input of the ·op amp senses the currEilnt
through R4.,to establish an, output current. !o proportiol1~to
the input voltage. The expressiOn fOr,lo,is
Laboratory evaluation of this circuit revealed noise and
CMR data as follows:
.', .
i) Frequency response with 10k load and Av = 1000:
-3.0 dB at 8.9 kHz
ii) CMR measurements (common-mode signal of ±34
Vp-pJ Figuh14
iii) Noise measurements in Fl{li.ire 5 '.;
"ENR2
0'.1rnA
-~=
--tiN'
A1 R4
V
.
10=
h,
100
!
10M~=
I" I
"- ~I
----
..,1"- r--.,RS = 10k
10
Xll111 .
~
70
,,"v
•1
o
'
100
,r
-
~
300
400
.
TL/H/Z432-4
1444V2 '.
orRl = 680mW ~ 2.1 ktl
FIGURE 4. Common-Mode Rejection Measurements
...
CD
.:
0oJ
,.70
co
60
...
!!
~~
"",
'!!~
Hence. load reSistances less than 2k will cause excessive
power diSSipation.
100
·co
>
.
c
.
~.'
Simple Po~er Boost Circuit
For loads less than 2 ktl. a power boost cirCUit should be
added. The simple booster shown in Figure 7 has the allvantage of minimal parts count. but crossover distortion is
notic;:eable and there is no sh()rt. circuit protection; hel1l,e.
either the LM143 or the boost transistors may fail under
short' cirCUit conditions.
30'
0--
......z
El2 '(38V)2
= -.Rl'
Rl
PMAX =. 680 mW = -
I (Hz)
.
,
CURRENT BOOSTED APPLICATIONS
Because of the high voltagecapalSiliiy of the LM143. some
thought'must be given for the selection of the'minimum load
reSistance. At an ambient temperature' of 25"C; the LM143
can dissipate 680 mW. Worst case dissipation arisas,when
the load resistance Rl is connected to one supply' and
Vo = O. Then the amplifier sources 10 = (38V/RLl witt)
38V internal voltage drop. During this condition •
Yo
200
as
±3.SmAatEIN":'±35V . '
RoUT = 2. Mn at lOUT = ±2.0 rnA,
..... ~ r--.. RS=O
RS"k i" ~ II~
BO
!..
R3 keeps the circuit stable under, any ,\(~Iue of load resistance. Measured circuit performance is
follows: .
.'
'20
>
;;
...1
d
I."
10
10
100
!.Ok
10k
I (Hz)
TL/HI7432-5
FIGURE 5. Noise Measurements
High Complisnce Current Source
A current source with a compliance of ± 28V is shown in
Figure 6.
R2
Uk
+38V
TL/HI7432-7
Heal'slnk Is ~ Thermalloy No. 2230·5 or equivalent
All
IJISisIors I!I"" 10%. 1w.
FIGURE 7. Simple, Power Booat Circuit
.
TLlHI7432-8
AU resIsIora 1% metal film, Y.W unless oth8l'Wlse specified.
FIGURE 6. High-Compilance Current Source
304
"
100 mA Current Boost Circuit
With the addition 014 diodes, a resistor and a capacitor, the
booster circuit can be short circuit protected at 100 rnA as
shown in Figure 8.,
R1 protects the LM143 by limiting the maximum drive current to (38V13.0k)'" 12.5 mA, thereby keeping safely within
the device dissipation limit of 880 mW. 01-04 in conjuction
with R2 and R3 protect the output transistors 01 and 02 by
shunting the output drive current if the voltage drop across
R2 or R3 exceeds O.7V.
"3av
Breadboard Data:
i) Frequency Response: Limited by LM143 frequency response and slew rate.
ii) Step response for unity gain, voltage follower configuration: Less than 10% overshoot for 1.0V step with 0.01
",F capacitive load, 50% overshoot with 0.47 ",F capacitive load. The circuit is unconditionally stable for capacitive loads.
iii) Output Voltage: ±33 Vp-p into 4000 load
al
IN1i336
H.S.
RI
al
8.8
02
04
1.0 Amp Class AB Current Booster
CI
0.005
lOOV
MYLAR
If crossover distortion is objectionable and currents of up to
1.0A are needed, the circuit in Figure 9 should be
used.
R3
6.8
The output of the LM143 drives a class AB complementary
output stage. The quiescent current for the output stage is
set by the current flow through R4, R5 and diodes 01-04.
The diodes 01-04 are on a common heat sink with the
output transistors 03 and 04 so that the voltage drops
across the diodes and base-emitter junctions of the output
-38V
TLlHI7432-8
Heat sink is a Thermalloy No. 2230-5 or equivalent.
All diodes are 1N914.
All resistors are YoW. 10%.
FIGURE 8. 100 mA Current Boost Circuit
v+ '" +38V
Rn
lOOk
1%
~-~~lJf
TCERAMIC
R4
2210
,
RIO
Ilk
I"
R2
Uk
IW,
2~1
~
LMI43
...... Olt
..... 2N3II8&
'Olt
"
fo'
:.:.. ~.
t ...
II
VOUT
Ic~
3y4
"
fo'03t
RI
R8
0.88
I.OW
... R6
lOD
fo° 2
6
V" D3t
.... 2N5919 .
R1
lID
o.oV
~
R9
0.68
D.!"
I.OW
.... ....
10k
R3. ,
:~k_ ~ D4t
~
JM
04t
..... 2N5918
~Q2t
2N4D33
R6
12k
D.I!!- ' CERAMlcT
V-· -31V
TLlHI7432-9
tPut on common heat sink. Thermalloy BOOSe or equivalent.
All diodes are 1N3193.
All resistors are 10%. V.Wexoept as noted.
FIGURE 9_ 1 Amp Class AB Current Booster with Short Circuit Protection
305
transistors will track with temperature. Normally. R4 and R5
supply the current drive for .the output Oarlingtons. 01. 03
and 02. 04. but if additional' drive 'is needed. the LM143
.upplies the remainder through R2and R3. For: short circuited load; the drive current is bypassed around the output
transistors through 01. 05 and OS during, the positive half
cycle and through 04. 07 and OS during the negative half
cycle. Orive current bypassing. or output current limiting. 0ccurS ·whenever R8 or R9 sees mdre than one diode drop
("" 0.7V). An expression for the maximum output current is
I'
,
MAX"
1.2
...
.
l
i!!
Hc -400
Ay-11
>
D.I
D.I
IA
D.2
102113041&810
0.7V
Vo 1>P (V)
o:68ii
TL/HI7432-10
IMAX so 1.0A
FIGURE 10. Harmonic Distort/on Measurements
Capacitor C1 stabilizes the circuit under most feedback and
load conditions and' C3 and C4 bypass the pOwer supply.
Measured performance is ,as follows:.
i) Mlildmum output voltage with RL = 400: + 29.SV. - 28V
with Vs = ±38 Vee.
ii) Harmonic distortion'measurements of Figure 10 were
measured with a closed loop gain of 10.
Very High Current Booster with HlghCompllance
If very high peak drive current is required in atjdltion to a
capability for the output swing to within 4.0V of tll9 supplies
under full load. the circuit in Figure 11 should be used.
09
2Nl666
R13
5&
Dl
IN3938
H18
22
3.OW
RIO
0.30
3W
AS
1110
VOUT
RI4
02
~ VII
5&
IN3938
Rn
22
CI
T0.0
5pf
010
2N4033
RI
RII
I.Ok
100
04
lN3938
C4
tOn common heat sink, Thermalloy 60068 or equivalent.
All resIstora ere V.W, 5% unless _
noted.
-JIV
·TD.047~F
TLlHI7432-lI
All capacitors are 20%, 100V, ceramic disc unless otherwise noted.
ttOutput current limit adjust
FIGURE 11. Very High Current Booster with High Compliance
306
Excluding the LM 143, the current booster has three stages.
The first stage is made up of 01 and 02 which level shifts
and boosts the current output of the LM 143 to about
100 mAo 03 and 04 further boost the output of 01 and 02
to about 1.0A. 05 and 06 then have adequate drive to
source and sink at least lOA. There is no quiescent current
path when the output voltage is zero since 01 and 02 are
biased off.
The short circuit protection circuit is made up of 07 and 09
on the positive side and as and 010 on the negative side.
09 or 010 turns on as soon as VBE "" 0.7V appears across
Rl0 when the output terminal is shorted to ground. Then 07
or 08 bypass the drive to the output devices, 05 and
Since Rl0 is 0.3.0., current limiting under short circuited output occurs at 2.3A and is relatively independent of the current limit adjustment resistor, Rll. An expression for the
maximum output current, lOUT MAX, with VOUT and Rll as
variables is
All measurements taken with a 4.0. load and ± 38V supplies
unless otherwise stated:
i) Maximum power out: 144 Wrms
ii ) Frequency response:
a) -3.0 dB at 10 kHz at full power
b) -3.0 dB at 11.5 kHz at 10 Vp-p out
iii) Maximum output voltage: ±34V
iv) Maximum capacitive load: 10 p.F with 10% overshoot
for a small signal step response
v) DC deadband: 20 p.V
vi) Ouiescent current: 12.7 mA (positive supply), 2.1 mA
(negative supply)
vii) Input impedance: 1 M.o.
viii) Voltage gain: 21
as.
HIGH POWER APPLICATIONS
90 Wrms Audio Power Amplifier
(IVOUTI- VOl) R13 + V
Rll + R12 + R13
BE9
IIOUTMAXI '" - - - - - - - - Rl0
A circuit diagram of an audio power amplifier which is capable of 90 Wrms into a 4.0. speaker or 70 Wrrns into an 8.0.
speaker is given in Figure 13. The circuit features safe area,
short circuit and overload protection, harmonic distortion
less than 0.1 % at 1.0 kHz, and an all NPN output stage.
(IVOUTI - 0.7) 56.0. + 0.7V
Rll + 526.0.
"'-,;;.:,.:,,;,,,...-::,...,:.,,...---0.3.0.
The output of the LM143 drives a quasi-complementary output stage made up of 01, 02, 03 and 04. This quasi-complementary circuit, which makes possible an all NPN output,
was chosen over the complementary output circuit due to
the lack of low cost high voltage power PNP transistors.
The equation is valid for both output polarities. The plot in
F/{Jure 12 superimposes the above equation on the maximum operating area curve for the 2N3773 and illustrates the
safe area protection feature.
16
Safe area current limiting occurs whenever the output current is
12
(IVOUTI - Voa) R11 + V
R11 + R13
BE5
IIOUTMAXI = -----::A:-:1-=-2----
5
S<
c 8.•
where Rl1 = R15 = 330.0.,
~
co
+i
A13 = R14 = 3.9k,
R12 = R16 = 0.25.0. and
4.0
VBE5 ... VBE6 "'" Voa ""V04 "" 0.7V.
If the output is shorted, the above equation simplifies to
12
24
VBE5
0.7V
IOUTMAX = R12 "" 0.25.0. = 2.8A
36
±Vo(V)
If the output voltage is 30V,
TL/HI7432-12
FIGURE 12. Maximum Output Current
asa Function of R11 and VOUT
(30V-0.7V) 330
7V
4.23k
+0. _2.3+0.7V
IOUTMAX
The diodes, 01 and 02, are in the circuit to keep the baseemitter junctions of 09 and 010 from being reversed biased
during the opposite polarity output voltage swings. Cl, C2,
ca, CS, C7 and C9 are judiciously inserted in the circuit to
prevent oscillation. R17, R18, C8 and L1 are used in the
circuit to maintain stability under all load conditions. Diodes
03 and 04 provide protection for inductive loads.
307
0.25.0.
0.25
12A
r---------------------------------------------------------------------------------,
C'I
,..
~
RI
2M
Z
c
*"
~-+.wO_~....~._....................~~~........~........~
1M
1.111
CI
l'O
0.1",F
CERAMIC
OS'
IN3I2I
RIZ
LIB
2.IW
Lt'
Ia.H
RII
RII
1.25
2.IIW
22
2.M
RII
22
1IW
C1
TLD"'F
R3
I ....
DI
,.3131
Rl
1.711
AI
1.111
tPut on common heat sink, Thermalloy 60068 or
equivalent.
'Tum. of No. 20 wire on a %' form.
RI
I.
All resistors YaW. 5% except as noted.
All capacitors 100 Voe WV exospt as noted.
CI
0.1",F
TCERAMIC
V-'-uv
TLlHI7432-'3
FIGURE 13. 90W Audio Power Amplifier
Figure 15 shows a plot of distortion at 50 mW versus quiescent current. C2,and C3 are connected between the output
and the A4, AS and A7, AS junctions, to provide a "bootstrapped" drive potential for the output stage during output
voltage swings near the power supply potentials. The absolute magnitudes of the voltages at these junctions exceed
the power supply voltages during the high outputs swings so
that adequate current drives to Q4 and Q1 are available. C1
and C4 are used for compensating the output stage. C5 and
C6 are used for power supply bypassing. A18, C7, A19 and
L1 are Included In the circuit to keep the amplifier stable
under all load conditions. 05 and 06 provide protection for
Inductive loads. '
The maximum output current, IO(MAX), versus Vo is plotted
in Figure 14. D4 and 03 are in the circuit to keep Q5 off
during the negative half of the output voltage cycle and Q6
off during the positive half cycle.
11
lZ
~
/'
./
1.0
,/
+;
4.0
V
V
'"
1.2
12
31
PO~5D:.w
1.1
,VOIV)
\
0.1
TLlHI7432-'4
FIGURE 14. Output Current Limiting as a
Function of Output Voltage
..
i!:
Rl-4n
\
f'"kH~- ;--
0.1
\
OA
The output stage is biased Into class AB operation by using
the resistor string A4, A5, A7 and A8 to set the voltage
drops across A6, 01 and 02, which then determine the quiescent current through the output transistors. These diodes
are thermally coupled to the output devices to track their
base-emitter junction voltages with temperature. Low distortion at low power levels is achieved by adjusting A6 to set
the quiescent current through Q3 and Q2 to about 100 mAo
'=I.8kH,
0.2
I'
41
10
120
110
lalmA)
TLlHI7432-15
FIGURE 15. Quiescent Current vs Distortion
308
pass element within 40V, standard three termin~1 voltage
regulators such as the LM340, LM120, etc. may be used as
pass elements and significantly decrease parts count and
circuit complexity. Circuits using this approach are given in
the LMS40 application note (see AN-10S).
The input impedance of the audio amplifier is simply the
value of RS. To keep the output offset voltages to a minimum, RS .. R1 R2. The voltage gain is
II
R1
2.0M
Av = 1 + R2 = 1 + 100k = 21
A Tracking ± 65V Supply with 500 rnA Output
The following data was taken with Vs = ±SSV:
A tracking power supply circuit can be made by modifying
the circuit for the 130 Vp-p driver circuit. The modified circuit
is given in Agurs 18.
i) Maximum power output before visible clipping:
a) 90 Wrms at 1.0 kHz into 40 load
b) 70 Wrms at 1.0 kHz into SO load
A 2N4275 is used as a stable zener voltage reference of
about 6.5V. Its output is amplified from one to about 10
times by the circuitry associated with IC1. The output of IC1
is applied through R 10 to the Darlington connected transistors, 02 and 03. The feedback resistor, R5, one end of
which Is connected to the V+ output node, is made variable
so that the V+ output voltage will vary from 6.5V to about
+65V. The V+ output is applied to a unity gain inverting
power amplifier to generate the V- output voltage. The output circuit of the unity gain inverter uses a compOSite PNP,
Q4 and 05, to provide the current boost.
ii) Distortion measurement: distortion versus frequency and
power is plotted in Figures 16 and 17.
iii) Maximum capacitive load: 20 ,...F
iv) Output nOise, 10Hz to 20 kHz: 100 ,...Vrms
v) Frequency response:
a) Small Signal (1.0 Vrms into 4.00): -S.O dB at 40 kHz
b) Power (90W into 40): -3.0 dB at 29 kHz
c) Power (70W into SO): -3.0 dB at 30 kHz
0.6
Since the input terminals of A2 are at ground potential, the
positive supply lead cannot be grounded; instead, it is connected to the output of a 4.7V zener diode, OS, to keep
within tile input common-mode range.
llUJW,
RL =4!l
0.5
DA
1/
C1, C3 and C4 are used for decreasing the power supply
noise. C2 is used in bypassing most of the noise generated
by the reference voltage and C5 and C6 are used to reduce
the voltage output noise. Short circuit protection is provided
by 01,02,03, R10 and R14 on the positive side and by 04,
05, R 11 and R15 on the negative side. The short circuit
protection circuit is the same as the one used in the 1.0A
current booster circuit.
illr
0.2
(.
J
0.1
D
10
11111
100
1.Dk
10k ZOk
The short circuit current is given by
I (Hz)
VeE
VeE
IMAX '"' R14 '" R15
TUHf7432-16
FIGURE 16. Distortion V8 Frequency, RL = 40
D.S
0.7
"" 0.56 = 1.25A
JLIJ~~III
OA
~
0.3
'"j!!
U
Po
"r
r
where VeE = voltage drop across a diode.
± 65V, 1.0A Power Supply with Continuously Variable
Output Current and Voltage
If a continuously variable output current as well as output
voltage supply is needed, a power supply circuit given in
Figure 19 will do the job. It has an output range from 7.1 V to
65V with an adjustable output current range of 0 to 1.0A.
~
0.1
o
ID
100
I.Ok
Basically, the power supply circuit is a non-ideal voltage
source in series with a non-ideal current source. A reference
voltage of approximately 6.5V is obtained by zenering the
base-emitter junction of the 2N4275. The positive temperature coefficient of the zenering voltage is compensated by
the negative temperature coefficient of the forward biased
base-collector junction. The output of the voltage reference
goes to the variable gain power amplifier made up of IC2,
06, 07 and their associated components and to a reference
current source made up of 02, 01 and components around
them. The variable gain power amplifier multiplies the reference voltage from one to ten times due to the variable feedback resistor, R17. since the maximum current output of IC2
is at most 20 mA, the Darlington connected 06 and 07 are
used to boost the available output current to 500 mAo
10k 2Dk
I(Hz)
TL/Hf7432-17
FIGURE 17. Distortion vs Frequency, RL = ao
POWER SUPPLY CIRCUITS
The ability of the LM143 to withstand up to SOV can be
exploited fully in the design of regulated power supplies.
The circuits to be described use a zener reference voltage,
an IC voltage amplifier, and a discrete power transistor pass
element. If care is taken to keep the voltage drop across the
309
.........~•
N
r--...;.--....- - - - - - -....--::C::',-1----1...+-C3
......-1~ ;~~GUlATED
"'16
-=ERAM'CT
I.
::I:OUTPUT VOLlAGE
ADJU!:ENT
01
22k
"""
10 pF
..J.. 1011V
Cl +
10",..,...
lOY .~
...-=--------41,--4-~. U~~~GULA1EO
CO
:F~::
tPut on oommon heat sink, Thermalloy 60068 or 'equiv8lent.
All resistors are
TUHI7432-18
'hW, 5%, except as noted. '
FIGURE 18. Tracking 65V, 1A Power Supply with ~hort Circuit Protection
..
...
r - - -....- -...----1~_1-----------_
01
m
3...
011
'5.310
1%
+CO
..,...'0.'
~ 'lOYal:
0+lIVIU.OE.)
01'
...
3.GW
Oil
+
Cl
10,.'
&IIVDC~
RZ
•
..
0\3
11k
OZ
03
1N1114 ,.,.
1.510
22k 1."
02+
10.' ..,...
I&VOC ~
,IREF
011
I.
V• ..,
022
1."
Dl
2IM21fi
Dl.
'::'
lNI14
"1Ii-1....M-+----1""O·· VOUT
L.o\oM+l\II;~
D3
+
INSI"
C&
..,....\....
110 ~OC
?
co
1l.017,.F
..,... lD1VDC
CERAMIC DIIe.
?
TUHI7432-19
tPut on oommon heat sink, Thermalloy 60068 or equivalent.
All resistors 'hW, 10% unless otherwise noted.
All capacitors 20%.
FIGURE 19. 1A, 65V Power Supply with Variable Currant Limit
310
Breadboard Data for the Tracking 65V Power Supply
VIN.= ±7SV, lOUT = ±SOO rnA, Tj = 2SoC, TA = 2SoC, VOUT = ±40V, unless otherwise specified.
Parameter
Measured
Data
Conditions
Load Regulation
o ~ lOUT ~ SOOmA
Line Regulation
l±sovl~vIN~I±sovl
lOUT = ±100mA
lOUT = ± SOO rnA
Ouiescent Current
lOUT = 0
~
f
~
Output Noise Voltage"
10Hz
Ripple Rejection
lOUT = ±20 rnA,
f = 120 Hz
+VOUT
-VOUT
.0.SmV
1.0mV
17SmV
169mV
176mV
173mV
Pos.Supply
2S.22rnA
Neg. Supply
6.SSmA
0.12S mV
0.13S mV
-72.SdB
-63.4 dB
3.3SmVI"C
3.43 mV/oC
100kHz
Output Voltage Drift"
'The output noise and drift are due primarily to the zener reference.
Measured Performance of the lA, 65V Power Supply
VIN = +76V, lOUT = SOO rnA, Tj = 2SoC, VOUT = +40V unless otherwise specified
Parameter
Conditions
Load Regulation
o ~ lOUT ~ SOO rnA
(Pulsed Load)
Line Regulation
46V ~ VIN ~ 76V
lOUT = 100 rnA
lOUT = SOOmA
(de Loads)
Maximum Output
Voltage
Messured
Data
S.OmV
297mV
2S6mV
68.6V
dcLoad
Ouiescent Current
21.4 rnA
Output Noise Voltage"
10Hz ~ f ~ 100kHz
Ripple Rejection
lOUT = 20 rnA
f = 120Hz
A Vs = 3.0 Vp-p
A Vo = 6.0 mVp-p
0.2S0mV
66.6 dB
200 ,""S Pulse Every 200 ms
Loads are Pulsed Loads
'The output noise ,. due primarily to zener reference
The power current source is an op amp used as a differential amplifier which senses the voltage drop across RS and
maintains this same voltage across R14. Hence, the maximum output current is
RS
1.0k
lOUT = R14 X IREF ~ s.on
able from the power current source. Because the positive
supply terminal of IC2 is tied to the collectors of 04 and OS,
IC2 will supply just enough current drive to
and 07 to
keep itself on. Hence, a current limiting resistor is unnecessary for IC2. A 10k current limiting resistor, R13, is present
since the total unregulated power supply voltage is available
for IC1. R6 is used to stay within the input common-mode
voltage range of IC1.
IREF is derived from the 6.SV reference source, 01, by using
02 in a current solirce configuration. R22 is made adjustable so that IREF can be set for S.O rnA.
as
x S.OmA = 1.0A.
Since the output load under most conditions will not demand what the power current source can deliver, 04 and
OS will remain in saturation during normal operation. When
Q4 and OS are pulled out of saturation, the output load voltage will drop until the load current just equals what is avail-
311
CONCLUSION
The LM143 is a high performance 'operational amplifier suited for applications requiring supply voltages up to"±40V.
The LM143, Is especially useful In power supply circuits
where the unregulated voltages are as high ,as ± 40V and in
amplifier circuits where output voltages greater than' ±30V
peak are needed. The LM143 is internally compensated and
Is pin-for-pin compatible with the LM741. eoniPar'ed with the
LM741. the LM143 exhibits an order of magnitude lower
Input bias currents. better than five times the slew rate and
twice the output voltage swing.
by the collector FET 041. The gat8i'Char:mel junction of Q41
exhibits 100V breakdown as source and drain are lightly
doped NPN collector and substrate material., The collector
current of Q18 biases current sources Q25 throUgh Q30 and
sets the supply current at nearly, zero TC.
Q19 furnishes a bias voltage. 5V above the negative supply.
for the collectors of Q15. Q20 and Q22. The low Impedance
2V reference (VBl in Figure 1) for the base of Q21 appears
at the emitter of Q20 and has the correct TC to insure that
Q23 never saturates. Should this occur. the low resistance
of Q23 would cause premature LVCEO breakdown of Q21.
The Input transistors. Q1 and Q2. are biased by Q13 and
Q14 which have a breakdown voltage essentially equal to
BVCBO by virtue of the high emitter impedance. R18 and
R19. relative to the low dynamic Impedance of 04. In a similar way. Q18 and Q19 stand off essentially the full supply
voltage. These devices have a high ,output impedance
caused by series feedback and so hold the supply current
nearly constant to prevent excessive power dissipation at
high supply voltages.
APPENDIX
Toward the goal of trouble-free applications. this appendix
details some of the more Subtle features of the LM143 and
reviews application hints pertinent both to op amps in general and the LM143 in particular. The complete schematic of
the LM143 is shown in Figure 2Q.
',
The circuit starts drawing supply current. ~t supply voltages
of ±4V. when current is provided to a 7.5V zener diode 05
v'
7
012
ZD
....--t":'OOUTPUT
013
27
05
R2'
1.1"
R25
19k'
"
~~~------~~~-------+~~-1---+----~--+-~~~~-1~. v, 'S'
OFFSET
OFFSET
,NULL
NtlLL'
TUHI7432-20
FIGURE ZO. Complete Schematic of the LM143
312
~---------------------------------------------------------------. ~
While the simple voltage clamping scheme, 03 and Q4 in
Figure' "1, is adequate, it is prone to oscillation when built
with high P PNPs. The more elaborate scheme of Figure 20
prevents instability. This clamping method is similar to that
used in the LM108, but allows large differential inputs to
exist with complete input overvoltage protection. 09 and
010, which withstand the high input common·mode voltage,
have a BVCBO·type breakdown due to the low impedance
diodes seen from the base leads and the high impedance of
01 and 02 (enhanced by 100% series feedback) in the
emitter leads. Input overvoltage protection also holds up un·
der high·level transient input voltages.
With a large negative-going step input, es could occur in the
unity·gain voltage follower configuration, diode-connected
Q6 turns "ON", protecting the emitter·bese junction of 02
from zener breakdown and subsequent long·term fj degra.
dation. At the same time, stray capacitance at the collector
of 02 is discharged by 02 through Q4 and 012. This holds
010 in a true BVCBO mode (emitter open·circuited) and
clamps the voltage across 02 to 3 VBE.
With a large positive-going step input, stray capacitance at
the collectors of 02 and 012 is charged by the forward·bi·
ased collector junction of 02. As before, with 02 conduct·
ing, 010 is again in the BVCBO breakdown mode. Since the
inverting input can be subject to the same transients, 01 is
afforded the same protection.
Distributed capacitence associated with R10 and R11, together with the collector·base capacitance of 026, cause a
high frequency transmission pole ( the "tail" pole(2» which
can degrade pHase margin. This is avoided by adding a
small lead capacitor, C1, which provides an alternative low·
impedance signal path, thus bypassing the tail pole.
The offset null resistors, R21 and R23, are made larger than
that strictly necessary to null the offset voltage. This reduc·
es the transconductance of 017 and, therefore, the noise
gain of the active loads into R10 and R11. By this simple
expedient, broadband input noise voltage is substantially reo
dUced.
The voltage reference for the output stage (VB2 in Figure 1)
is realized by actively simulating a 4·diode stack. The volt·
age across 033, given by (1 + R8/R9) VBE, is about 3.5V.
Biased at 400 !IA from 030, the circuit presents a low im·
pedance, less than 500, to the base of 032. Since the TC
of the reference is negative, 034 is designed to always remain out of saturation under worst·case conditions of high
temperature and high output current. This avoids potential
destructive breakdown of 032.
Current limiting for 032 and 034 is provided by diode-con·
nected 037 and resistor R12. When the voltage drop across
R12 turns on 037, It removes base drive from 034. In a
similar fashion, current limiting in the negative direction is
initiated when the voltage drop across R13 causes 038 to
conduct. This current is limited in 021 by R20 to about 1
mAo When this occurs, base drive is removed from 039.
Although output short circuits to ground or either supply can
be sustained indefinitely at supply voltages lower than
±22V, short circuits should be of limited duration when op·
erating at higher supply voltages. Units can be destroyed by
any combination of high ambient temperature, high supply
voltages, and high power dissipation which results in excessive die temperature. This is also true when driving low im·
pedance or reactive loads or loads that can revert to low
impedance; for example, the LM143 can drive most general
purpose op amps outside of their maximum input voltage
range, causing heavy current to flow and possibly destroy·
ing both devices.
Precautions should be taken to insure that the power sup.
plies never become reversed in polarity-even under tran·
sient conditions. With reverse voltage, the IC will conduct
excessive current, fuSing the internal aluminum intercon·
nects. As with alilC op amps, voltage reversal between the
power supplies will almost always result in a destroyed unit.
Finally, caution should be exercised in high voltage applications as electrical shock hazards are present. Since the
negative supply is connected to the case, users may inadvertently contact voltages equal to those across the power
supplies.
REFERENCES
1. R. J. Widlar, "Super Gain TransiStors forICs", National
Semiconductor TP-11, March 1969.
2. J. E. Solomon, "The Monolithic Op Amp: A Tutorial
Study", IEEE Journal of Solid-State Circuits, Vol. SC-9,
No.6, December 1974.
313
~
.-
~
FM Rel110teSpeaker
System
National Semiconductor
Application Note 146
' ""
.
INTRODUCTION
A high qllality, noise free; wireless FM transmitter/receiver
may be made using t/'ie LM566 VCO and LM565 PLLDetector. The LM566 veo is used to convert the program material into FM format, which is then transformer coupled to standard power lines. At the receiver .end the material is detected from the power lines and demodulated by the LM565.
The important differenCe between this carrier system and
otherS is· its excellent . quality and freedom from noise.
IIiIhereas the ordinary wireless intercom uses an AM carrier
and exhibits a poor Signal-to-noise ratio (SIN), the system
described here uses an FM carrier for inhereht freedom
from noise and a PLL detection system for additional noise
.
rejection:
of the veo is ± 0.15V peak. A reduction due to the Summlllg network brings the required input to about 0.2V rms for
±10% modulation of fe, based on nominal outPut levels
from stereo receivers. Input potentiometer R1 is provided·tci
set the required level. The output at pin #3 of the LM566,
being a frequency modulated square wave of approximately
6V pk-pk amplitude, is amplified by a single transistor 01
and coupled to the AO line via the tuned transformer T 1.
Because T 1 is tuned to fe, it appears as a high impedance
collector load, so Qlneed not have additional current limiting. The collector signal may be as nuch as 40'-50V,pk-pk.
Coupling capacitor Os isolates' the transfomer from the line
at 60 Hz.
The complete system is suitable for high-quality transmission of speech or music, and 'Will operate from any AC outlet
anywhere on a one-acre homesite. Frequency response is
20-·20,000 Hz andTHD is under %% for speech and music
program material.
.
A Voltage regulator provides necessary supply rejection for
the veo. The power transformer is sized for peak secondary voltage somewhat belOW the regulator breakdown voltage spec (35V) with a 125V line.
Transmission diStance along a. power line is at least adequate to include a:11 outlets in and ~rOund a suburban home
and yard. Whereas many carrier systems operate satisfactorily only when transmitter and receiver are plugged into the
same side of the 120-2401V power service line, this system
operates ecjually well with the receiver on either side of the
line.
'
The receiver amplifies, limits, and demodulatEls the .received
FM signal in the presence of line transient interference
sometimes as high as several hundred volts peak. In addition, it provides audio mute in the absence of carrier and
2.5W output to a speaker.
'
.
The transmitter is plugged into the AC line at a radio or
stereo system source. The signal for the transmitter is ideally taken from the MONITOR or TAPE OUT connectors provided on component system Hi-Fi receivers. If these outputs
are not available, the signal could be taken from the main or
extra speaker terminals, although the remote volume would
then be under control of, the local gain control. The carrier
system receiver need only be plugged into the AC line at the
remote listening location. The design includes a 2.5W power
amplifier to drive a speaker directly.
TRANSMITTER
Two input terminals are provided so that both LEFT and
RIGHT signals of a stereo set may be combined for mono
transmission to a single remote speaker if desired.
The input signal level is adjustable by R1 to prevent overmodulation of the carrier. Adding C2 across each input resistor R7 and Rs improves the frequency response to
20 kHz as shown in Figure 5. Although casual listening does
not demand such performance, it could be desired in some
circumstances.
The veo free-running frequency, or carrier frequency fe, determined by R4 and C4 is set at 200 kHz which is high
enough to be effectively coupled to the AC line. veo sensitivity under the selected bias conditions with Vs = 12V is
about ±0.66 felV. For minimum distortion, the deviation
should be limited to ± 10%; thus maximum Input at pin #5
RECEIVER
The carrier signal is capacitively coupled from the line to the
tuned transfQrmer T 1.·Loaded 0 of the secondary tank T lC2
is decreased by shunt resistor Rl to enable acceptance of
the ± 10% modulated carrier, and to prevent excessive tank
circuit ringing on noise spikes. The secondary of T 1 is
tapped to match the base input impedance of 01A. Recovered carrier at the secondary of T 1 may be anywhere from
0.2 to 45V pop; the base of 01A may see pk-to-pk signal
levels of from 12 my' 'to 2.6V.
.
01A-01DOperates'as a two-stage limiter amplifier whose
output is a symmetrical square wave of about 7V pk-pk with
rise and fall times of 100 ns.
The output of the limiting amplifier is applied directly to the
mute peak detector, but is reduced to lV pk-pk for driving
the PLL detector.
The PLL detector operates as a narrow band tracking filter
which tracks the input signal and provides a low-distortion
demodulated audio output with high SIN. The oscillator
within the PLL is set to free-run at or near the carrier frequency of 200 kHz. The free-run frequency is fo ~ 1/(3.7
R16Cla). Since the PLL will lock to a carrier near its free-run
frequency, an adjustment of R 16 is not strictly necessary;
R16 could be fixed at 4700 or 5100.0. Actually, the PLL with
the indicated value of Cl1 can lock on a carrier within about
±40 kHz of its center frequency. However, rejection of impulse noise in difficult circumstances can be maximized by
carefully adjusting fo to the carrier frequency fo- Adding
314
RI
10K
INPUTS
R1BHT
~
11K
R3
UK
LEFT
I!'.!ff-CZL
Rll0K
c.'
~
C3
I!I!tE-CZR
R,
10K
(LINI
-=
C,
U.F
IBID
RZ
lllK
-=
CAl'AClTORVALUES I••F
RESISTOR VALUES IN n
tsELECT FOR CARR1ER FREo.
'. .
ZOOkHz
100kHz
C4
C!
IZ
181
lD111
_
TL/H/7442-1
FIGURE 1. Carrier System Transmitter
.DZ
TZ
r-----'\
II
,..--1,,_--.
zu
I,'AVCT
03
r-----------------------------------------------------~
~~~'N=au~
I
CAPACITOR VAlUES.N PF
RESISTOR VALUES IN Sl
"SELECT FOR CARRIER FREo.
f.
Cz Cn
ZOOkHz I . 381
10UHz _
IZI
TLlHI7442-2
FIGURE 2. Carrier System Receiver
315
Cl0 = 100 pF will reduce the carrier level fed to the power
amplifier. Even though the listener cannot hear the carrier,
the audio amplifier could overload due to carrier signal power.
A mute circuit is included to quiet the receiver in the absence of a carrier. Otherwise, when the transmitter is'turned
OFF, an excessive noise level would result· as the PLL attempts to lock on noise. The mute detect,or consists of a
voltage doubling peak detector Dl02C7. The peak detector
shunts the 1-2 mA bias away from 01 E without loading the
limiter amplifier. When no carrier is present, the +4V line
biases OlE ON via Rl0 and Rll; and the audio signal is
shorted to ground. When a carrier is present, the 7V square
wave from the limiter amplifier is peak detected·~ and 'the
resultant negative output is integrated by R9C7, averaged by
Rl0 across C7, and further integrated by RllCe. The resultant output of about - 4V subtracts from the + 4V bias supply, thus depriving 01 E of base current. Peak detector integration and averaging prevents noise spikes from deactivat-
ing the mute in the absence of a carrier when the limiter
amplifier output is a series of narrow 7V spikes.
The LM380 supplies 2.5W of audio power to an 80 load.
Although this is adequate for casual listening in the kitchen
or garage, for hi-fi listening, a larger amplifier may be direct.
CONSTRUCTION
PC board layout and stuffing diagrams are shown in Ftgures
3 & 4. After the'receiver board has been loaded and
checked, the power transformer is mounted to the foil side
of the. board With a piece of fish-paper or electrical insulating
cloth between board and transformer. Insulating washers of
1f.a-% inch thickness can be used to advantage in holding
the transformer away from" the foil. The board is laid out so
that the volume. control potentiometer may be mounted on
either side of the board depending on the desired mounting
to a panel.
The line coupling coils are available in production quantities
from TaKa AMERICA, INC. 1250 Feehanville Drive, Mount
Prospect, IL 60056. TEL: (312) 297-0070
TLIHI7442-3
FIGURE 3. Carrier System Transmitter PC Layout and Loading Diagram (Not Full Scale)
. TLlHI7442-4
FIGURE 4. Carrier System Receiver PC Layout and Loading Diagram (Not Full Scale)
316
~---------------------------------------------------------------.~
ADJUSTMENT
Adjustments are few and extremely simple. Transmitter carrier frequency fc is fixed near 200 kHz by R4 and C4; the
exact frequency is unimportant. T 1 for both transmitter and
receiver are tuned for maximum coupling to and from the
AC line. Plug in both receiver and transmitter; no carrier
modulation is necessary. Insure that both units are operative. Observe or measure with an AC VTVM the waveform at
T 1 secondary in the receiver. Tune T 1 of the transmitter for
maximum observed signal amplitude. Then tune T 1 of the
receiver for a further maximum. Repeat on the transmitter,
th.en the receiver. Tuning is now complete for the line coupling transformers and should not have to be repeated for
either. If the receiver is located some distance from the
transmitter in use, or on the opposite side of the t 10-220V
service line, a re-adjustment of the receiver Tl may be
made to maximize rejection of SCR dimmer noise. The receiver PLL free-running frequency is adjusted by R16. Set
Rt6 near the center of its range. Rotate slowly in either
direction uniilthe PLL loses lock (evidenced by a sharp increase in noise and a distorted output). Note the position
and then repeat, rotating in the other direction. Note the
new position and then center R16 between the two noted
pOSitions. A fine adjustment may be made for minimum
noise with an SCR dimmer in operation. The final adjustment is for modulation amplitude at the transmitter. Connect
the audio signal to the transmitter input and adjust the input
potentiometer Rt for a signal maximum of about 0.1 V rms at
the input to the LM566. Adjustment is now complete for
both transmitter and receiver and need not be repeated.
A STEREO SYSTEM
If full stereo or the two rear channels of a quadraphonic
system are to be transmitted, both transmitter and receiver
must be duplicated with differing carriers. Omit Re and include R7 & C2 on the transmitter if desired. Carriers could
be set to 100 and 200 kHz for the two channels. Actually,
they need only be set a distance of 40 kHz apart.
PERFORMANCE
Overall SIN is about 65 dB. Distortion is below about %%
at low frequencies, and in actual program material it should
not exceed 1f2% as very little signal power occurs in music
above about 1 kHz.
317
z•
...
~
o
-1
WITHOUT
C2 ON XMTR
-2
-3
i>'\
111111
111111
111111
10
100
lk
10k
lOOk
FREQUENCY (Hz)
TL/H17442-5
FIGURE 5. Overall System Performance
Transmitter Input to Input ot Receiver Power Amplltler
The 2.5W audio amplifier provides an adequate sound level
for casual listening. The LM380 has a fixed gain of 50.
Therefore for a 2.5W max output, the input must be 89 mY.
This is slightly less than the ± 10% deviation level so we are
within design requirements. Average program level would
run a good 10 dB below this level at 28 mV input.
Noise rejection is more than adequate to suppress line
noise due to fluorescent lamps and normal line transients.
Appliance motors on the same side of the 110-220V line
may produce some noise. Even SCR dimmers produce only
a background of impulse noise depending upon the relative
location of receiver and SCR. Otherwise, performance is
noise-free anywhere in the home. Satisfactory operation
was observed in a factory building so long as transmitter
and receiver were connected to the same phase of the
three-phase service line.
APPLICATIONS
Additional applications other than home music systems are
possible. Intercoms are one possibility, with a separate
transmitter and receiver located at each station. A microphone can serve as the source material and the system can
act as a monitor for a nursery room. Background music may
be added to existing buildings without the expense of running new wiring.
~r-----------~~~--~--~------~----------------------------~
~
z"
c(
"D
3~ andSk timing resistors through the emilt~~ of <;)1. Tllis
current wil,l be amplified by aQout 3 by Q2 and passed to the
base, of Q3. Q3 will then conduct, pUlling down on the base
of Q4 and hence the base of Q1. This is a negative feedback
since i~ will redllce timing resistor current and current to the
power transistor's base until,a balance is reached. This will
occur with the collector of Qa. at about 0.5V, the base,ofQ4
at about 1V, alld a very Small voltage (rom pin ~ to ground.
The, difference between these two voltage,s is the baseemitte~ drop of Ql and 2/3 the, base-emitter drop of Q4 as
set by the high resistance divider from its base to emitter.
Note that negative, feedback voltage is attenuated by at
least 2 due to the divider of two 4000 resistors. Now considering the capacitor, its positive feedback is initially unity.
Therefore the DC bias condition and the temporary excess
positive feedback conditions are met and the circuit must
oscillate:
The waveform pin 8 of the above oscillator' is shown below. The waveform at pin 2, the power transistor collector, is
almost a rectangle; It extends froin a -saturation voltage of
0.1 V or less to within about 0.1 V of the supply voltage. The
"on" period of course coincides with the negative pulses at
pin 8. Other circuit voltages can easily be inferred from the
two waveforms in Figure B.
INTRODUCTION
Most Iinea~,integratedcjrcuitsarE! designE!d to operate with
power supplies of 4.5 to 40V. Practically no battery/portable
equipmentiS provided with indicator: ,lights due to unacceptable power' drain: Even LEOs (solid 'state lamps) won't light
from a 1.5V battery,and drain the common 9V radio battery
in a few hours.
The LM3909 changes all this. Obtaining long life from a single 1.5V cell, it opens a whole new area of applications for
,linear integrated circuits. Sufficient voltage for flashing a
light emitting diode is generated with cell voltage down to
1.1 V. In such' low duty' cycle applications batteries will last
for months to years of continuous operation., Such flasher
circuits then become practical,for marking location of flashlights; emergency equipment, and boat mooring floats in the
dark.
The LM3909 is simple in design, easy to use, and includes
extra resistors to' minimize external 'circuitry and the size of
the completed flasher or oscillator.
at
CIRCUIT OPERATION
The ~ircuit below in Figure A is the LM3909 c(lnnected' as
the simplest type of oscillator. Ignoring the capacitor for a
moment, and assuming 1.5V on pin 5,currE1nt win flow in the
+
5
,a
II
,~
National Semiconductor
Applroation Note 154
1.3V Ie Flasher, O,scillator,
Trigger or Alarm
NEGATIVE
Ilz - - ]
a[+'·
~1 ~OLTIOROPI
JUST BEFORE til
CONoum
28k
11011
6k
3k
Ilz~----------------J
PWR. TRANSISTOR
TL/C17213-1
FIGURE A
+1.2
+.•
~
+.4
co 0
> -.2
-.6
-1.1
I,
•
10
MILLISECONDS
11
12
13
14
1&
TL/C17213-2
FIGUREB
318
l>
The simplicity of LED and incandescent pilot lamp flashers
is illustrated below in Figure 1. In the LED flasher, the
LM3909 uses the single capacitor for both timing and voltage boostirlg.
With the accent on the practical, a brief circuit description
will be given followed by circuits in the following application
areas:
Flasher & Indicator Applications
The LM3909, although designed as a LED flasher, is ideal
for other applications such as high current, trigger pulse for
SCRs and "Triacs." The frequency of oscillation adjusts
from under 1 Hz to hundreds of kHz. Waveshape can be set
from pulses a few /Jos wide to approximately a square wave.
Thus the LM3909 can perform as a sound effects generator,
an audible alarm, or audible continuity checker. Finally it can
be a radio (detector/amplifier), low power one-way intercom, two-way telegraph set, or part of II "mini-strobe" light
flashing up to 7 times per. second.
Audio & Oscillator Applications
Trigger & Other Applications
For those who want to modify or design their own circuits
using the LM3909, application hints will be covered near the
end of this note.
CIRCUIT DESCRIPTION
The circuit of Figure 2 again shows the typical 1.5V LED
flasher, but with the internal circuitry of the IC illustrated.
The flasher achieves minimum power usage in two ways.
Operated as above, the LED receives current only about
1 % of the time. The rest of the time, all transistors but 04
are off. The 20k resistor from Q4'S emitter to supply-common draws only about 50 /JoA. The 300 /JoF capacitor is
charged through the two 4000 resistors connected to pin 5
and through the 3k resistor connected to pin 1 of the circuit.
Operating with only a 1.5V battery as a supply gives the
LM3909 several rather unique characteristics. First, no
known connection can cause immediate destruction of the
IC. Its internal feedback loop insures self-starting of properly
loaded oscillator circuits. Experimenters can safely explore
the possibilities of the LM3909 as an AC amplifier, one-shot,
latch circuit, resistance limit detector, multi-tone oscillator,
heat detector, or high frequency oscillator.
1.5V Flasher
Incandescent Bulb Flasher
NSL5021
+6V
+
LM3909
1/41
I.&V
LM3909
4
-=Note: Nominal Flash Rate: 1 Hz.
TUCf7213-3
Note: Flash Rate: 1.5 Hz.
FIGURE 1. Two Simple Flashers
NSL5021
5
r
Rt
I
I
I
I
I 6k
I
I
I
I
IrAST
~
- i20--
SLOW
4000
3k
- -300I'F
--
v.1
I
I
I
I
I
I
I
I
I
I
+
1.5 V
v-...J
+
TLfCf7213-4
FIGURE 2. Circuit Operation
319
...•
z
i!
~r-------------------~--------~----~------------------------------~
....
II)
~
APPLICATIONS:'FLASHER a: INDICATOR "
Differing uses and supj:)ly voltages will rsqulrEi' adjustment of
flashing rates. Often it is convenient to leave the capaCitor
the same value to minimize Its size. or to fix the ptily'enikgy to the LED. FirSt, the,internal RC resistors can· be uliedto
obtain Sk. 6k, or 9k by:l1ooking to or shorting the appropriate
pins. Further'adJustment methods are shown In the two
parts of Figure '3 below.
In Figure
it can be seen that the intemal'RO resistors aie
shunted by an exiemaI1kbetweenpins8an~.4.Thls will
give a'~little over S times the flashing rate of the typlcat 1.5V
flasher of Figure 1. .
," ,
Transistors 01 through 03 remain off until the capacitor becomes charged to about 1V. This voltage is determined by
the junction drop of 04. its base-emitter voltage divider. and
the junction drop of 01. When voltage at pin 1 becomes a
volt more negative than. that at pin 5 (supply positive terminal) 01 begins to conduct. This then tums' on 02 and 03.
The LMS909 then supplies a pulse of high current to the
LED. Ourrent amplification of 02 and 03 is 6etween 2<.>0 and
1000. 03 can' handle over 100 mA and rapidly pulls pin 2
close to supply common (pin 4). Since the capacitor is
charged. its other terminal at pin 1 goes be/ow the supply
common. The voltage at the LED is then higher than battery
voltage. and the 120 resistor between pins 5 and 6 limits
the LED current.
Many of the other,oscillator.circuits work in a similar fashion.
If voltage boost is not neElded (with or without current limiting) loads can be hooked between pins 2 and 6 or pins 2
and 5.
3s.
The S.9k resistor in Figu,s' 3b con~ected frompln 1.tothe
6V supply raises voltage at the bott9m of the 6k RC r8s!stor:
Charging current through that resistor is' greatly readced.
bringing flashing rate down to about that of the 1.5V circuit
(1 Hz). As will be explained later. this biasin!! method alsq
insures starting of oscillation even under unfavOrable conditions.·
, , '
5
r
- i2n-- v+\
I
I
400n
I
I
SLOW
RC
I
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I
I
I
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I
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Uk
I
+
1.5V
I
I
I
I~AST
~
I
OUT
;-----r"3----
-- -+
V-..J
4
300~F
Ik·
TL/C17213-5
FIGURE 3a. Fast Blinker
r
I
SLOW
RC
I
I
I
I
I
I
I
I
Uk
3k
20 k
I~AST
~
TL/C17213-6
FIGURE 3b. 6 Volt Flasher
320
High frequency operation requires addition of two external
resistors, typicelly of the same value. One, of course, shunts
the high internal timing resistors. If only this one were used,
the capacitor charging current would have to pass through
the two 4000 resistors internally connected between pin 5
and the collector of Q3. Oscillation at a slower rate and
lower duty cycle than desired would occur, and oscillation
might cease altogether before the battery was fully discharged. The second 680 resistor shunting the two 4000
resistors eliminates these problems.
Two precautions are taken for circuit reliability. The added
750 series resistor for the LED keeps current peaks within
safe limits for the diode and IC. Also, in operation above a
3V supply, the electrolytic capacitor sees momentary voltage reversals. It should be rated for periodic reversals of
1.5V.
.
A continuously appearing indicator light can also be powered from a single 1.5V cell as shown in Figure 4. Duty cycle
and frequency of the current pulses to the LED are increased until the average energy supplied provides sufficient light. At frequencies above 2 kHz, even the fastest
movement of the light source or the observer's head will not
produce significant flicker.
The circuit in Figure 5 is a relaxation type oscillator flashing
2 LEOs sequentially. With a 12 VOC supply, repetition rate is
2.5 Hz. C2, the timing and storage capacitor, alternately
charges through the upper LED and is discharged through
the other by the IC's power transistor, Q3.
Since this indicator powering circuit uses the smallest capacitor that will reliably provide full output voltage, its operating frequency is well above the 2 kHz point. The indicator
is not, however, intended as a long life system, since battery
drain is about 12 mAo
If a red/green flasher is desired, the green LED should have
its anode or plus lead toward pin 5 (like the lower LED). A
shorter but higher voltage pulse is available in this position.
NSL5057
r
-iifi--
SLOW
RC
I
I
I
I
I 6k
I
I
I
I
IrAST
L!!!= - - - 211F
+
5
v+l
I
I
I
I
I
I
I
4000
OUT
2-sa~--r3----
+1.5V
sao
3V
TL/C17213-7
FIGURE 4. "Continuous" 1.5V Indicator
3000
+~Dd5~~~'-6-10-O-+--C-'-'OO--II-F--------~+I~~~'----------e----~
4.3k
6V
8_ _ _ _ - '
r
,
I
1000'
~
____
~
___ _
120
SLOW
RC
"'---'\Nv--"
S
V+"'"
I
I
I
I
I
4000
,
I
I
I
I
I
I
I
I
I.
I
I
,rAST
V-...J
~
4
TL/CI7213-B
FIGURE 5. Alternating Flasher
321
Indication Of monitoring of a high voltage power supply at a
remote location can be done much more safely than with
neon lamps. If the dropping resistor (43k as in Figure 6) is
located at the source end, all other voltages on ·the line, the
Ie, and the LED will be limited to less than 7V, above
ground.
The timing capaeitor is charged through the dropping resistor and the two 4000 Collector loads betw~n ,pins 2· and 5
of the Ie. When capacitor voltage reaches about 5V, thefe
is enough voltage across the 1k· resistor (to pin 8) to turn on
010 and hence trigger on the whole Ie to discharge the capacitor through the LED.
· +85ZOOVDC
43k
lW
lk
8_ _ _ _
r
J
~
____
SLOW
I
I
6 - i20- _
""'-...J>,JV'v'-'"
RC
5
v+1
I
I
I
I
I +
I
I
I
I
I
I
I
180"F
8V
I
I
I:AST
~
4
1 VOLT LIMIT
TLlC17213-9
FIGURE 6. Safe, High Voltage Flasher
OFF
+ 4OO"F
3V
ON
2.2.
8____
r
I
"RATE"
+
3 V-=-
6 - ;'20- _
RC
I
I
ik
..J ~ ____
SLOW
I
I
I
1181
LAMP
6.
I
I
I
I:AST
~
TLlC17213-10
FIGURE 7. "Mlni-5trobe" Variable Flasher
322
There are many other LED applications and variations of
circuits. A chart outlining operation of the circuit of Figure 6
at various voltages appears on the LM3909 data sheet. Also
shown are circuits for adjusting the flash rate, flashing 4
LEOs in parallel, and details for building a blinking locator
light into an ordinary flashlight.
A "mini-strobe" Circuit was tested in a Lantern Flashlight
with a large reflector. In a dark room, the flashes were almost fast enough to stop a person's motion. As a toy, the
fast setting can mimic the strobes at rock concerts or the
flicker of old-time movies.
Figure 8 below shows a higher power application such as
would use an automotive storage battery for power. It provides about a 1 Hz flash rate and powers, a lamp drawing a
nominal 600 mAo
A particular advantage of this circuit is that it has only 2
external wires and thus may be hooked up in either of the
two ways shown below in Figure 9. Further, no circuit failure
can cause a battery drain greater than that of the bulb itself,
continuously lit.
In the circuit of Figure 8, the 3300 ,..F capacitor performs a
number of other functions. It makes the LM3909 immune to
supply spikes, and provides the means of limiting the IC's
supply voltage. Since the LM3909 can only operate with
Incandescent bulbs can also be flashed, as already illustrated in Figure 1. However, most such bulbs draw more than
the 150 mA that the LM3909 can switch. The two following
circuits therefore use an added power transistor rated at 1A
or more. In each circuit, an NPN transistor is used, so the
power transistor's base drive is obtained from the common
or ground pin of the flasher IC.
The 3V "mini-strobe" of Figure 1 may be used as a variable
rate warning light or for advertising or special effects. The
rate control is so wide range that it adjusts from no flashes
at all to continuously on. Chosen for rapid response, the
miniature 1767 lamp can be flashed several times a second.
+12t.14VOC
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TUCI7213-11
FIGURE 8. 12 Volt Flasher (2 Wire)
POSITIVE
POSITIVE
+
2WIRE
FLASHER
+
2WIRE
FLASHER
-=-12 V
lZV
COM
SHELL
(NEG. GND SYSTEM)
Not.: If flasher case insulated, it will
operate in positive or negative
ground systems.
TUC/7213-12
FIGURE 9. 2 Wire Flasher Usage
323
7:5V or less on pin 5 (in this circuit) the 2000/1.3k divider
attached to pin 8 of the IC causes it'to tum fully on at 7V or
less on pin 5. Then the LM3909 diScharges the timing capacitor (its own supply voltage) to 4V or less, whereupon it
turns off. The capacitor discharge current comes out of pin
4 oHhe IC, turning on the NSD U01 transistor. It is tne large
size of the timing capacitor that allows it to store all the
needed energy for turning on the power transistor. This in
turn permits the whole flasher circuit to operate as a 2 wire
device.
Many other flasher possibilities exist. LEO flash rate can be
varied from 0 to 20 Hz, or a number of LEOs may be flashed
in parallel. With a 3V supply, yellow and green LEOs may be
flashed. A 6V incandescent "emergency lantern" can be
made and its PR-13 bulb may be made to give continuous
light or flash by switch selection. This .is a more reliable,
longer lived system, than a lantern with a second thermal
flasher bulb. The NSL4944 Current Regulated LED makes
possible flashing many LEOs in parallel or with high voltages without series resistors.
tween a 10,resistor and a 10 inductor can be heard. Quick
checks for shorts and opens in transformers and motors
can therefore be made.
Oarkro.oms, laundry rooms; laboratories,' and cellar workshops can 'often suffer damage from spills or water seepage
ruining lumber, chemicals, fertilizer, bags' of dry concrete,
etc. The circuit of Figure 11 is safe on potentially damp
floors. since there is no connection to the power line. FurthE:lr, its standby battery drain cif 100 p.A yields a battery life
close to (or, according to some experiments, exceeding)
shelf life.
Without moisture, multivibrator transistor Qa is' completely
off, and its collector load (6.2k) provides enough current to
hold pin 8 of the LM3909 above 0.75V where it cannot oscillate. When the sense electrodes pass about 0.25 p.A, due to
moisture, Qa starts turning on, and since Qb is already partially biased on, positive feedback now occurs. Qa and Qb
are now an astable multivibrator which starts at about 1 Hz
and oscillates faster as more leakage passes across the
sense electrodes.
This "multi" then acts as both an amplifier and a modulator.
The pulse waveform at the collector of Qa varies the timing
current through the 3.9k resistor to pin 8 of the LM3909
resulting in a distinctively modulated tone output.
The sensor should be part of the base of the box the alarm
circuitry is packaged in,'lt consists of two electrodes six or
eight inches long spaced about Va inch apart. Two strips of
stainless steel on insulators, or the appropriate zig-zag path
cut in the copper cladding of a circuit board will work well.
The bare circuit board between the copper sensing areas
should be coated with warm wax so that moisture on the
floor, not that absorbed by the board, will be detected. The
circuit and sensor can be tested by just touching a damp
finger to the electrode gap.
Minimum cost, SimpliCity, and very Jow power drain are the
aims of the Morse Code set of Figure 12. One oscillator
simultaneously drives speakers at both sending and receiv-
APPLICATIONS: Audio" Oscillator
Very economical continuity checkers, tone generators, and
alarms may be made from the LM3909. No matching transformer is needed because the 150 mA capability of the
LM3909 output can drive many standard permanent magnet
(transistor radio) loudspeakers directly. The 1.5V battery
used in most applications is both lower in cost and longer
lasting than the conventional 9V battery.
In the continuity checker of Figure 10, a short, up to about
1000, across the test probes provides enough power for
audible oscillation. By probing 2 values in quick Succession,
small differences such as between a short and 50 can be
detected by differences in tone.
A novel· use of this circuit is found In setting the timing of
certain types of motorcyles. This is due to the difference in
tone that can be heard from the tester depending whether
there is a short or not across the low resistance primary of
the 'cycle's ignition coil. In other words, the difference be-
tr,120RI8n~~M_.~__EA_K_E_R____________________________~____~.
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TLlC17213-13
FIGURE 10. "Buzz Box" Contll)ulty and Coli Checker
324
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SENSE ELECTRODES
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ALL CAPACITORS 1 pF
TL/C17213-14
FIGURE 11. Water Seepage Alarm
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TUC17213-15
FIGURE 12. Morse Code Set
325
;z
....
:z•
cc
ing ends. Calculations and actual use tes1s indicate life of a
single alkaline penlight cell to be 3 months to over a year
depending 'on ,usage. "Buzzer" type se1s use two or more
batteries with. much shorter life.
Commonly available, low cost 8.0 speakers are effectively in
series to better match LM3909 characteristics. The three
wire system and parallel telegraph keys allow beginners and
children to use the set without having to understand use of a
"send-receive" switch:
slide in and out like a piston. The box was stiffened with thin
layers of pressed wood, etc. Minimum volume with the piston in was about.. 10 in.S: Speaker, cirCUit, battery, and all
were mounted on the sliding end with the speaker facing out
through a 2Y4 in. hole. A tube was provided (2% in. long, 0/16
in. 10) to bleed air in and out as the piston was'moved while
not affecting resonant frequency.
"Slide tones" can be generated, or a tune can be played by
properly positioning the piston part and working the push
button. Position and direetion of the' pi$ton are rather intuitive, so it is not difficult to playa reasonable semblance of a
tune after a few tries.
The two resistors are added to obtain a suitable average
power output and electrically force the oscillator toward the
desired 50% duty cycle. Acoustically, both speakers are operated at resonance (about 400 Hz in the prototype) for
maximum pleasing tone with minimum power drain. Each of
the two speaker enclosures has holes added to augment
this resonance. For each different type or brand of speaker
and size of box, hole and capacitor sizes wil, have to be
determined by experiment for the most stable resonant tone
over the expected battery voltage variation.
Experiments with the above circuit led to development of
circuit in FiglJf"8 13. It is optimized to oscillate at any acoustie load frequency of resonance! With just a'speaker, oscillation occurs at the speaker cone "free-air" resonance. If the
speaker is in an enclosure with a higher resonant frequency
. . . this becomes the frequency at which the circuit oscillates.
The 120 resistor in series with pin 2 (output transistor 03'S
collector) and the speaker, decouples voltages generated
by the resonating speaker system from the low impedance
switching action of 03. The 100 j.LF feedback capaCitor
would normally set a low or even sub-audio oscillation frequency. Therefore, the major positive feedback voltage to
pin 8 is the resonant motion generated voltage from the
speaker voice coil. Therefore the LM3909 will continue to
drive the speaker at the resonance with the highest combined amplitude and frequency.
It can be seen already that the LM3909, having direct
speaker drive and resonance following capability, can do
things that are a lot less practical with older timer and unijunction circuitry. Two final "sound effect" type of circui1s
are illustrated in Figure 14.
An educational audio demonstration device, or simply an
enjoyable toy, has been fabricated as follows. A roughly cubical box of about 64 in.3 was made with one end able to
N.D.
PUSH BUTTON
~
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TUC17213-18
FIGURE 13_ ElectroniC "Trombone"
326
Th!l siren of Figure 148 produces a rapidly rising wail upon
pressing the button, and a slower "coasting down" upon
release. If it is desirable to have the tone stop sometime
after the button is released, an 18k resistor may be placed
between pins 8 and 6 of the IC. The sound is then much like
that of a motor driven siren.
In this circuit, the oscillation must not be influenced by
acoustic resonances. The 1 ",F capacitor and 2000 resistor
determine a pulse to the speaker that is wider than that for
flashing LEOs, but much narrower than is used in the tuned
systems of F/{/ures 12 and 13. The repetition rate of speaker pulses is determined by the 2.7k resistor, and the charge
on the 500 ",F capacitor. Discharging this capacitor with
the pushbutton increases current in the 2.7k resistor causing a rapid upshift in tone.
The "whooper" of Figure 14b sounds somewhat like the
electronic sirens used on city police cars, ambulances, and
airport "crash wagons." The rapid modulation makes the
tone seem louder for the same amount of power input.
The tone generator is the same as in the previous siren.
Instead of a pushbutton, a rapidly rising and falling modulating voltage is generated by a second LM3909 and its associated 400 ",F capacitor. The 2N1304 transistor is used as a
low voltage (germanium) diode. This transistor along with
the large feedback resistor (5.1 k to pin 8) forces the ramp
generator, LM3909 into an unusual mode of operation hav-
OFF
ON
8_ _ _ _
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TL/C17213-17
FIGURE 14a. Fire Siren
Y'V"no
+11
1':F
200n
8 17 1&
9k NC RL
TOP
5 VIEW
9k NC RL V+
8171&
5
V+
: 5.1k
LM3909
3.9k
3k OUT Ne
11
12
13
v-
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VIEW
4
...,~ 1.5V
LM3909
3k OUT Ne
v-
2 13
4
11
~4~0:F
TONE GENERATOR
300n
~1304
RAMP GENERATOR
TLlC/7213-18
FIGURE 14b. Whooper Siren
327
occurs. From this example; it ean,be seen that,other,input
resistors or bias dividers, can be calculated to gate the
LM3909 triac trigger from other logic levels.
A useful electronic lab 'device is a preciSion squsrewave
generator/calibrator. If the output is held a~ a ,~ew' tenths
percent of 1V, peak-to-peak, it is useful in calibrating oscilloscopes and adjusting, 'scope probes. Many.lower cost ~
battery-portable oscilloscopes do not have thiS feature bwlt
in. Also it is useful in checking gain and transient response
of various amplifiers including "hi-fi" power amplifiers. '"
Battery powered equipment is free from both the inconvenience ofa line cord, and from same of the noise and hum
effects of equipment attached to the power line; Operation
for over five hundred hours from a single flashlight "0" cell
is the bonus provided by the circuit of FlfJure 16. The lowest
reference voltage regulator available, the lM113, is used in
conjunction with a current source, and the voltage boost
characteristic of the lM3909. ,
Output is a clean rectangular wa~e which can be adju~ed to
exactly a 1V amplitude. A rectangular wave of approximately 1.5 ms "on" and 5.5 ms "off" was chos~n ~or ~irc~it simplicity and low battery drain. Waveform clipping IS Virtually
flat due to complete tum-off of the current switch 02 and
the typical "on" impedance of 0.20 provided by the lM113.
The 0.01 % temperatura.coefficient of the lM113 at room
temperature allows negligible drift of the waveform amplitude under laboratory conditions. loading by a 'scope probe
will also be insignificant.
The circuit will work properly down to battery voltages of
1.2V. This is because the 100 ",F electrolytic capacitor
drives the emitter of 02 below the supply minus terminal. At
a battery voltage of 1.2V, the collector of 02 can still swing
more than 1.6V. 01 uses the "off" periods of the lM3909 to
insure that the 100 "F capacitor is charged to almost the
ing longer "on" periods than "off" periods. This raises the
average tone of the tone generator and makes the modula·
t!ons"seem 'lJ,Ipre even.
APPLICATioNS: Trigger & Other
With its high, pulse current capability, 11)" lM3909 is a good
pulse-transformer driver. I=urther, it uses fewer parts and
operateS more succeSsfully from lOw voltage supplies than
do the equivalc:lnt unijunction circuits. The "'Triac" trigger of
Figure 15 operates from a 5V logic supply and provides gate
trigger pulses of up to 200 mAo
,
With n~gate input, or aTIllQgic high inp,:,t, the LM3909is
biaSed off since pin 1 is tied tQ V+. With ,a logic low at the
gate in,' the IC provides 1Ci "S pulses at about a 7kC rate. A
TIL gate loaded only by this circuit is assumed since otherwise worst-case voltage swing may be insufficient. This trigger is not of the "Synchronized Zero Crossing" type since ,
the first trigger pulse after gating on could occur at any time.
However, the repetition rate IS such that after the first cycle,
a triac is triggered within 8V of zero with a resistive load and
a 115 VAC line.
The standard Sprague PC mounting transformer provides a
2:1 current step-up, and suitable isolati,on between the low
voltage circuitry and power lines up to 240 VAC. Resistor
Rg, which includes transformer winding resistance, can be
as little as 3 or 40 for high current triacs. low current types
may need excessive "holding" current ~ith such I~ Rg, so
it may be raised to as ,much as 1000 with a senSitIVe gate
triac.
Oscillation of the lM3909 will start When the oC bias at pin
8 is between 1.6 and 3.9V. In Figure 15, pin 8 is connected
between the 10k input resistor and a 11k resistor to
5V. With 3.8V in, pin 8 is at 4.5V so there is no oscillation.
With 1V, or less, in, pin 8 is at 3.5Vor below and oscillation
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10k
TLlC17213-19
FIGURE 15. Triac Trigger
328
UZk
1%
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TL/C17213-20
FIGUFJE 16. 'Scope Calibrator
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2"----r;---TUC17213-21
FIGURE 17. R.F. Oscillator
entire battery voltage. Thus when the LM3909 turns on and
pin 2 drives almost to the minus supply voltage, the negative
side of the capacitor is driven 0.9 to 1.2V below this termi·
nal. Low battery voltage cannot lead to an undetected error
in the 1V squarewave. This is because the waveform be·
comes distorted rather than just decreasing in amplitude as
battery voltage becomes too low.
Taking advantage of the versatility and the indestructability
of the LM3909 by a 1.5V battery, the IC can become an
ideal teaching means, or experimental device for the young
electronic hobbyist. As well as the circuits already present·
ed, the LM3909 can be made to work as amplifier, radio,
and even logic type circuits. The ideas of negative and posi·
tive feedback can be presented. The circuits presented in
Figuf6s 17 through 21 are intended as illustrations or demo
onstrations of circuitry concepts such as would be used in
an experimenter's kit. They are not meant to be used as
parts of finished commercial products with specific p~rform·
ance specifications. In other words, working circuits have
been breadboarded, but no measurements of performance
such as frequency range and distortion have been attempt·
ed.
Both tuned circuits of Figuf6s 17 and 18 use standard AM
radio ferrite antenna coils (loopsticks) with a tap 40% of the
. turns up from one end. The oscillator works up to 800 kHz
or so, and the radio tunes the regular AM broadcast band.
Both also use standard (360 pF) AM radio tuning capacitors.
The oscillator has the normai' capaCitive positive feedback
used with LM3909 circuits, but with frequency determined
by the tuned circuit loading the output circuit. Detailed operating deSCriptions of these experimenter's circuits will not
be attempted in or'der to keep down the length of this note.
Near the end, a discussion of the IC's general theory of
operation will be given, which should help in understanding
.
the individual circuits.
329
In the radio circuit of Flf1UrB 18, the LM3909 acts as a detector amplifier. It does not oscillate because there is no positive feedback path from pin 2 to pin 8. The tuning ability is
only as good as simple. "crystal set," but a local radio station can provide listenable volume with an efficient inch
loudspeaker. Extremely low power drain allows a month of
continuous radio operation from a single "0" flashlight cell.
Antennae for the radio circuit can be short (10 to 20 feet)
and connected directly to the end of the antenna coil as
illustrated. Longer antennae (30 to 100 feet) work better if
attached to the previously mentioned tap on the cOil ... also
illustrated.
Switches on both the above circuits are momentary types.
In each case a small charge or impulse affects the circuit's
state. The circuit of AgUrB 19 sWitches to and holds its condition whenever the switch changes sides, even if contact Is
made only very briefly. The circuit· of F/{JurB 20 delivers
about a % second flash from the LED every time its push.button makes contact, whether b~efly or for a much longer
period of time. Such circuits are used with keyboards, limit
switches, and other mechanical contaCts that must feed
data into electronic digital systems.
e
By again leaving out the positive feedback capacitor, the
LM3909 can become a low power amplifier. This little audio
amplifier can be used as a one-way intercom or for "listening in" on various situations. Operating current is only 12 to
15mA. It can hear fairly faint. sounds, and someone speaking directly into the microphone generates a full 1.4V peakto-peak at the loudspeaker.
The following two circuits are examples of logic or computer
type functions. They use 3V power supplies (2 cells) be·
cause the LM3909 was designed not to have any stable or
"latching" states with a 1.5V supply.
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TLlCI7213-22
FIGURE 18. Radio
·ON" '" D.3 VOLTS
·0"" tl! 2.1 VOLTS
l001l
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TLlCI7213-23
FIGURE 19. Latch Circuit
330
NSL5051
470
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8_ _ _ _
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TUC172i3-24
FIGURE 20. IndlcaHng One-Shot
rr140n
L\JSPKR.
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---
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TUC17213-25
FIGURE 21. Mini-Power Amplifier
331
.. r---------------------------------------------------------------------------------,
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APPLICATION HINTS
With 1.5V supplies, certain problems can occur to stop oscillation or flashing. Due to the way gain is achieved and the
type of feedback, too heavy a load may stop an LM3909
from oscillating. 200 of pure resistive load will sometimes
do it. Strangely enough, lamp filaments, probably because
of some inductance, don't seem to follow this rule. Also in
flasher circuits, an LED with leakage or conductivity between 0.9 and 1.2V will stop the LM3909. Maybe ·1 % of
LEOs will have this defect because they are not often tested
for it.
Greater frequency stability was not one of the design aims
of the LM3909. In LED flasher circuits it is better than might
be expected because the negative temperature coefficient
of the LED partially compensates the IC. We planned it this
way. Simple oscillators, without the LED, ani uncompensated for temperature. This is due to using 1 % of a silicon
junction drop as the on-off trip pOint and the use of the
integrated timing resistors with their positive temperature
coefficient. Further, most capaCitors of 1 jA>F or over, shown
in the circuits, will usually be electrolytics for size reasons.
These, however, are not particularly stable with temperature
and their initial tolerances vary greatly with type of capaCitor.
In most of the oscillator circuits, frequency is also proportional to battery voltage. This must be considered when
starting with a completely unused cell at 1.54V or so and
deciding what the "end-of-life" voltage is to be. This can be
in the range of 1.1 to 0.9V, a drastic change. It helps to
remember how bright flashlights are with a fresh set of batteries, and how dim they are when the batteries are finally
changed.
Flashers and tone generators for alarms are not, however,
demanding for stability. Flash rate changes of 50% or tone
shifts of 'h an octave are not particularly annoying or even
too noticeable.
One interesting point is that the low operating power of
most of the circuits presented allows them to be powered by
solar cells as well as regular batteries. In bright sunlight, 3 to
4 cells in series will be needed. In dimmer light, 4 to 6 cells
will do the job. Current from cells way under an inch in area
generally will be suffiCient, but circuits drawing a high pulse
current (such as SCR triggers) will need a surge storage
capaCitor across the solar cell array.
The LM3909 was designed to be inherently self-starting as
an oscillator, and LED flasher circuits are, at any voltage,
because the load is nonlinear. A load with sufficient self
inductance will always self-start, although possibly at a higher than expected frequency. There is an exception for largely resistive loads on an oscillator operating with a supply
larger than 2 or 2.5V. A stable state exists with
turned
completely "on" and the timing resistors from pin 8 to the
supply minus still drawing current. A reliable solution is to
bias pin 8 (for instance with a resistor to V + ) so that its DC
voltage is one half V less than half the supply voltage.
The duty cycle of the basic LED flasher is inherently low
since the timing capacitor is also driving the very low LED
"on" impedance. For other oscillators the "on" duty cycle
can be stretched by adding resistance in series with the
timing capacitor. Additionally, nonlinear resistance can be
. used as timing resistance. (See Figure 14b)
as
CONCLUSION
Applications covered in this note range in use from toys to
the laboratory, and in frequency from DC to RF. The
LM3909 can be used to amuse, teach, or even upon occasion to save a life. As a practical cost consideration the
LM3909 IC can often replace a circuit having a number of
transistors, associated parts, and high assembly cost.
Further, the LM3909 demonstrates the practicality of very
low voltage electronic circuits. They can work at high efficiencies if ingenuity is used to design around transistor junction drops. In such circuits stresses on parts are so low that
extremely, long life can be predicted. Often transistors, capacitors,' etc. that would be rejects at higher voltages can be
used. Voltage dividers, protective diodes, etc. often needed
at higher voltages can be left out of deSigns. Power drains
are so low that circuits can be made that will last months to
years on a single cell.
A single cell is more reliable and has a higher energy density then multiple cells. This is due to lack of cell interconnections and insulation as well as elimination of packaging to
hold multiple cells in place.
332
Specifying AID and DIA
Converters
National Semiconductor
Application Note 156
The specification or selection of analog-to-digital (AID) or
digital-to-analog (01 A) converters can be a chancey thing
unless the specifications are understood by the person
making the selection. Of course, you know you want an accurate converter of specific resolution; but how do you ensure that you get what you want? For example, 12 switches,
12 arbitrarily valued resistors, and a reference will produce a
12-bit OAC exhibiting 12 quantum steps of output voltage. In
all probability, the user wants something better than the expected performance of such a OAC. Specifying a 12-bit
OAC or an AOC must be made with a full understanding of
accuracy, linearity, differential linearity, monotonicity, scale,
gain, offset, and hysteresis errors.
Accuracy is sometimes considered to be a non-specific
term when applied to 01 A or AID converters. A linearity
spec is generally considered as more descriptive. An accuracy specification describes the worst case deviation of the
OAC output voltage from a straight line drawn between zero
and full scale; it includes all errors. A 12-bit OAC could not
have a conversion accuracy better than ± % lSB or ± 1
part in 212+1 (±0.0122% of full scale) due to finite resolution. This would be the case in Figure 1 if there were no
errors. Actually, ± 0.0122% FS represents a deviation from
100% accuracy; therefore accuracy should be specified as
99.9878%. However, convention would dictate 0.0122% as
being an accuracy spec rather than an inaccuracy (tolerance or error) spec.
This note explains the meanings of and the relationships
between the various specifications encountered in AID and
01 A converter descriptions. It is intended that the meanings
be presented in the simplest and clearest practical terms.
Included are transfer curves showing the several types of
errors discussed. Timing and control signals and several binary codes are described as they relate to AID and 01A
converters.
MEANING OF PERFORMANCE SPECS
Resolution describes the smallest standard incremental
change in output voltage of a OAC or the amount of input
voltage change required to increment the output of an AOC
between one code change and the next adjacent code
change. A converter with n switches can resolve 1 part in
2". The least significant increment is then 2-", or one least
significant bit (lSB). In contrast, the most significant bit
(MSB) carries a weight of 2 -1. Resolution applies to OACs
and AOCs, and may be expressed in percent of full scale or
in binary bits. For example, an ADC with 12-bit resolution
could resolve 1 part in 212 (1 part in 4096) or 0.0244% of
full scale. A converter with 10V full scale could resolve a
2.44mV input change. Likewise, a 12-bit OAC would exhibit'
an output voltage change of 0.0244% of full scale when the
binary input code is incremented one binary bit (1 lSB).
Resolution is a design parameter rather than a performance
specification; it says nothing about accuracy or linearity.
333
Accuracy as applied to an AOC would describe the difference between the actual input voltage and the full-scale
weighted equivalent of the binary output code; included are
quantizing and all other errors. If a 12-bit AOC is stated to be
± 1 lSB accurate, this is equivalent to ±0.0245% or twice
the minimum possible quantizing error of 0.0122%. An accuracy spec describes the maximum sum of all errors including quantizing error, but is rarely provided on data
sheets as the several errors are listed separately.
fS
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D~--------------DOD 101 010 011 100 101 111 111
OIGITAL CODE
TL/H/5612-1
FIGURE 1. Linear DAC Transfer Curve Showing
Minimum Resolution Error and Best Possible Accuracy
Quantizing Error is the maximum deviation from a straight
line transfer function of a perfect ADC. As, by its very nature, an ADC quantizes the analog input into a finite number
'. of output codes, only an infinite resolution ADC would exhibit zero quantizing error. A perfect ADC, suitably offset %
LSB at zero scale as shown in Figure 2, exhibits only ± %
LSB maximum output error. If not offset, the error will be :;:
FS
IDEAL SLOPE ~ / '" '" '"
..~
I.SB as shown i.n Figure 3. For example, a perfect 12-bit
ADC will show a ±% LSB error of ±O.0122% while the
quantizing error of an a-bit ADC is ± % part in 28 or
±O.195% of full scale. QUantizing error is not strictly applicable to a DAC; the equivalent Elffect is more properly a
resolution error.
/}
1 LSB
/
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..
i
6
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o~--------------GIll 10' 01' ." 'DO 'I' ". 111
DIGITAL CDDE
TLlH/5612-3
FIGURE 4. Linear, 1 LSB Scale Error
111
111
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Gain Error is essentially the same as scale error for an
ADC. In the case of a DAC with current and voltage mode
outputs, the current output could be to scale while the voltage output could exhibit a gain error. The amplifier feedback
resistorS would be trimmed to correct the gain error.
Offset Error (zero error) is the output voltage of a DAC with
zero code input, or it is the required mean value of input
voltage of an ADC to set zero code out. (See Figure 5.)
Offset error is usually caused by amplifier or comparator
input offset voltage or current; it can usually be trimmed to
zero with an offset zero adjust potentiometer external to the
DAC or ADC. Offset error may be expressed in % FS or in
fractional LSB.
,ui
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FS
ANALOG INPUT
FIGURE 2. ADC Transfer Curve, % LSB Offset at Zero
FS
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DIGITAL CODE
.
TL/H/5G12-4
FIGURE 5. DAC Transfer Curve, % LSB Offset at Zero
TLlH/56'2-2
Hysteresis Error in an ADC causes the voltage at which a
code transition occurs to be dependent upon the direCtion
from which the transition is approached. This is usually
caused by hysteresis in the comparator inside an ADC. Excessive hysteresis may be reduced by design; however,
some slight hysteresis is inevitable and may be objectionable in converters if hysteresis approaches % LSB.
Linearity, or, more accurately, non-linearity specifications
describe the departure from a linear transfer curve for either
an ADC or a DAC. Unearity error does not include quantizing, zero, or scale errors. Thus, a specification of ± % LSB
FIGURE 3. ADC Transfer Curve, No Offset
Scale Error (full scale error) is the departure from design
output voltage of a DAC for a given input code, usually fullscale code. (See Figure 4.) In an ADC it is the departure of
actual input voltage from design input voltage for a full-scale
output code. Scale errors can be caused by errors in reference voltage, ladder resistor values, or amplifier gain, at s/.
(See Temperature Coefficient.) Scale errors may be corrected by adjusting output amplifier gain or reference voltage. If the transfer curve resembles that of Figure 7, a scale
adjustment at % scale could improve the overall ± accuracy compared to an adjustment at full scale.
334
linearity implies error in addition to the inherent ± 'Iz LSB
quantizing or resolution error. In reference to Figure 2,
showing no errors other than quantizing error, a linearity
error allows for one or more of the steps being greater or
less than the ideal shown.
Differential Non-Linearity indicates the difference between actual analog voltage change and the ideal (1 LSB)
voltage change at any code change of a DAC. For example,
a DAC with a 1.5 LSB step at a code change would be said
to exhibit 'Iz LSB differential non-linearity (see Figures 6 and
7). Differential non-linearity may be expressed in fractional
bits or in % FS.
Figure 6 shows a 3-bit DAC transfer curve with no more
than ± 'Iz LSB non-linearity, yet one step shown is of zero
amplitude. This is within the specification, as the maximum
deviation from the ideal straight line is ± 1 LSB (1/2 LSB
resolution error plus 'Iz LSB non-linearity). With any linearity
error, there is a differential non-linearity (see below). A ± 'Iz
LSB linearity spec guarantees monotonicity (see below) and
~ ± 1 LSB differential non-linearity (see below). In the example of Figure 6, the code transition from 100 to 101 is the
worst possible non-linearity, being the transition from 1 LSB
high at code 100 to 1 LSB low at 110. Any fractional non-linearity beyond ± 'Iz LSB will allow for a non-monotonic transfer curve. F/{/ure 1 shows a typical non-linear curve; non-linearity is 1% LSB yet the curve is smooth and monotonic.
Differential linearity specs are just as important as linearity
specs because the apparent quality of a converter curve
can be significantly affected by differential non-linearity
even though the linearity spec is good. F/{/ure 6 shows a
curve with a ± 'Iz LSB linearity and ± 1 LSB differential nonlinearity while Figure 1 shows a curve with + 1% LSB linearity and ± 'Iz LSB differential non-linearity. In many user applications, the curve of Figure lwould be preferred over that
of Figure 6 because the curve is smoother. The differential
non-linearity spec describes the smoothness of a curve;
therefore it is of great importance to the user. A gross example of differential non-linearity is shown in Figure 8 where
the linearity spec is ± 1 LSB and the differential linearity
spec is ±2 LSB. The effect is to allow a transfer curve with
grossly degraded resolution; the normal a-step curve is reduced to 3 steps in Figure 8. Similarly, a 16-step curve (4-bit
converter) with only 2 LSB differential non-linearity could be
reduced to 6 steps (a 2.6-bit converter?). The real message
is, "Beware of the specs." Do not ignore or omit differential
linearity characteristics on a converter unless the linearity
spec is tight enough to guarantee the desired differential
linearity. As this characteristic is impractical to measure on
a production basis, it is rarely, if ever, specified, and linearity
is the primary specified parameter. Differential non-linearity
can always be as much as twice the non-linearity, but no
more.
FS
1
1 LSI DIFF
NON.L1NEA
II LSI DIFF
NON·L1NEAR
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8BO 801 011 011 110 101 110 '"
DIGITAL CODE
FIGURE 6. ±'Iz LSB Non-Linearity (Implies 1 LSB
Possible Error), 1 LSB Differential Non-Linearity
(Implies Monotonlclty)
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DIGITAL CODE
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TLlH/5612-6
____________
FIGURE 8. ± 1 LSB Linear,
± 2 LSB Differential Non-Linear
800 801 010 011 100 101 110 '"
DIGITAL CODE
TLlH/5612-5
Monotoniclty. A monotonic curve has no change in sign of
the slope; thus all incremental elements of a monotonically
increasing curve will have positive or zero, but never negative slope. The converse is true for decreasing curves. The
transfer curve of a monotonic CAC will contain steps of only
positive or zero height, and no negative steps. Thus a
smooth line connecting all output voltage points will contain
no peaks or dips. The transfer function of a monotonic ACC
will provide no decreasing output code for increasing input
voltage.
FIGURE 7.1% LSB Non-Linear,
'Iz LSB Differential Non-Linearity
Linearity specs refer to either ACCs or to DACs, and do not
include quantizing, gain, offset, or scale errors. Linearity errors are of prime importance along with differential linearity
in either ACC or CAC specs, as all other errors (except
quantizing, and temperature and long-term drifts) may be
adjusted to zero. Linearity errors may be expressed in % FS
or fractional LSB.
335
Figure 9 shows a non·monotonic DAC transfer curve. For
the curve to be non-monotonic, the linearity erro~ ,must exceed ± % LSB no matter by how little. The greater the linearity error, the more significant the negative step might be.
A non-monotonic curve may not be'a ·special disadvantage
is some systems;· however, it is' a ,disaster in closed·loop
servo systems of any type (Including a DAC·controlied
ADC). A ± % LSB maximum linearity spec on an n-bit converter guarantees monotonicity to n bits. A converter exhib·.
iting more than ± % LSB non·linearity may be monotonic,
but is not necessarily monotonic. For example, a 12·bit DAC
with ± % bit linearity to 10 bits (not ± % LSB) will be mono·
tonic at 10 bits but mayor may not be monotonic at 12 bits
unless tested and guaranteed to be 12·bit monotonic.
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10mVlDIV
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SETTLING TIME
001 OlD 011 100 101 110 111
DIGITAL CDDE
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TL/W5612-7
TLlH/5612-8
FIGURE 9. Non-Monotonic
(Must be > ± % LSB Non-Linear)
Settling Time is the elapsed time after a code transition for
DAC output to reach final value within specified limits, usual~
Iy ± % LSB. (See also Conversion Rate below.) Settling
time is often listed along with a slew rate specification; if so,
it may not include slew time. If no slew rate spec is included,
the settling time spec must be expected to include slew
time. Settling time is usually summed with slew time to ob·
tain total elapsed time for the output to settle to final value.
Figure 10 delinjlates that part of the total elapsed time
which is considered to be slew and that part which is settling
time. It is apparent from this figure that the total time is
greater for a major than for a minor code change due to
amplifier slew limitations, but settling time may also be dif·
ferent depending upon amplifier overload recovery characteristics.
.
Slew Rate is an inherent limitation of the output amplifier in
a DAC which limits the, rate of change of output voltage after
code transitions. Slew rate is usually anywhere from 0.2 to
several hundred volts/ '""S. Delay in reaching final value of
DAC output voltage is the sum of slew time and settling time
as s~own in F/flure 10.
Overahoot and Glltche. occur whenever a code transition
occurs in a DAC. There are two causes. The current output
of a DAC contains switching glitches due to possible asyn·
chronous SWitching of the bit currents (expected to be worst
at half-scale transition when all bits are switched). These
(b) 1 LSB Step
FIGURE 10. DAC Slew and Settling Time
glitches are normally of extremely short duration but could
be of % scale amplitude. The current switching glitches are
generally somewhat attenuated at the voltage output of the
DAC because 'the output amplifier Is unable to slew at a very
high rate; they are, however, partially coupled around the
amplifier via the amplifier feedback network and seen at the
output. The output amplifier introduces overshoot and some
non-critically damped ringing which may' be minimized but
not entirely eliminated except at the expense of slew rate
and settling time.
Temperature Coefficient of the various components of a
DAC or ADC can produce or increase any of the several
errors as the operating temperature varies. Zero scale offset error can change due to the TC of the amplifier and
comparator input offset voltages and currents. Scale error
can occur due to shifts in the reference, changes in ladder
resistance or non-compensating AC product shifts in dual·
slope ADCs, changes in beta or reference current In current
switches, changes In amplifier bias current, or drift in amplifier gain-set resistors. Linearity and· monctoniclty of the DAC
can be affected by differ~tial temperature drifts. of the ladder resistors and switches. Overshoot, settling time, and
slew rate can be affected by temperature due to Internal
change. In amplifier gain and bandwidth. In short, every
specification except resolution. and quantizing error can be .
affected by temperature changes,
336
Long-Term Drift, due mainly to resistor and semiconductor
aging can affect all those characteristics which temperature
change can affect. Characteristics most commonly affected
are linearity, monotonicity, scale, and offset. Scale change
due to reference aging is usually the most important
change.
Supply Rejection relates to the ability of a DAC or ADC to
maintain scale, offset, TC, slew rate, and linearity when the
supply voltage is varied. The reference must, of course, remain constant unless considering a multiplying DAC. Most
affected are current sources (affecting linearity and scale)
and amplifiers or comparators (affecting offset and slew
rate). Supply rejection is usually specified only as a % FS
change at or near full scale at 2S'C.
Conversion Rate is the speed at which an ADC or DAC can
make repetitive data conversions. It is affected by propagation delay in counting circuits, ladder switches and comparators; ladder RC and amplifier settling times; amplifier and
comparator slew rates; and integrating time of dual-slope
converters. Conversion rate is specified as a number of conversions per second, or conversion time is specified as a
number of microseconds to complete one conversion (including the effects of settling time). Sometimes, conversion
rate is specified for less than full resolution, thus showing a
misleading (high) rate.
Clock Rate is the minimum or maximum pulse rate at which
ADC counters may be driven. There is a fixed relationship
between the minimum conversion rate and the clock rate
depending upon the converter accuracy and type. All factors which affect conversion rate of an ADC limit the clock
rate.
Input Impedance of an ADC describes the load placed on
the analog source.
Output Drive Capability describes the digital load driving
capability of an ADC or the analog load driving capacity of a
DAC; it is usually given as a current level or a voltage output
into a given load.
CODES
Several types of DAC input or ADC output codes are in
common use. Each has its advantages depending upon the
system interfacing the converter. Most codes are binary in
form; each is described and compared below.
Natural Binary (or simply Binary) is the usual 2" code with
2, 4, 8, 16, ... , 2" progression. An input or output high or
"1" is considered a Signal, whereas a "0" is considered an
absence of signal. This is a positive true binary signal. Zero
scale is then all "zeros" while full scale is all "ones."
Complementary Binary (or Inverted Binary) is the negative
true binary system. It is identical to the binary code except
that all binary bits are inverted. Thus, zero scale is all
"ones" while full scale is all "zeros."
Binary Coded Decimal (BCD) is the representation of decimal numbers in binary form. It is useful in ADC systems
intended to drive decimal displays. Its advantage over decimal is that only 4 lines are needed to represent 10 digits.
The disadvantage of coding DACs or ADCs in BCD is that a
full 4 bits could represent 16 digits while only 10 are represented in BCD. The full-scale resolution of a BCD coded
system is less than that of a binary coded system. For
337
example, a 12-bit BCD system has a resolution of only 1
part in 1000 compared to 1 part in 4096 for a binary system.
This represents a loss in resolution of over 4: 1.
Offset Binary is a natural binary code except that it is offset
(usually Yz scale) in order to represent negative and positive
values. Maximum negative scale is represented to be all
"zeros" while maximum positive scale is represented as all
"ones." Zero scale (actually center scale) is then represented as a leading "one" and all remaining "zeros." The comparison with binary is shown in Figure 11.
Two's Complement Binary is an altemate and more widely
used code to represent negative values. With this' code,
zero and positive values are represented as in natural binary
while all negative values are represented in a twos complement form. That is, the twos complement of a number represents a negative value so that interface to a computer or
microprocessor is simplified. The twos complement is
formed by complementing each bit and then adding a 1; any
overflow is neglected. The decimal number -8 is represented in twos complement as follows: start with binary code of
decimal 8 (off scale for ± representation In 4 bits so not a
valid code in the ± scale of 4 bits) which is 1000; complement it to 0111; add 0001 to get 1000. The comparison with
offset binary is shown in Figure 11. Note that the offset
binary representation of the ± scale differs from the twos
complement representation only in that the MSB is complemented. The conversion from offset binary to twos complement only requires that the MSB be inverted.
111
110
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8 tOG
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5
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DOl
1
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ANALOG SCALE
(a) Zero to
+ Full-scale
011 011 111
DID DID 110
DOl DOl 101
: : DOD 100
1-....
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101 111 011
110 110
010
", 101 DOl
100 DOD
f f t..OFFSET BINARY
I TWOS COMPLEMENT BINARY
SIGN + MAGNITUDE
TLlH/5612-Q
(b) ± Full-Scale
FIGURE 11. ADC Codes
Sign Plus Magnitude coding contains polarity information
in the MSB (MSB = 1 indicates a negative sign); all other
bits represent magnitude only. This code is compared to
offset binary and twos complement in Flflure 11. Note that
one code is used up in providing a double code for zero.
Sign plus magnitude code is used in certain instrument and
audio· systems; its advantage is that only one bit need be
changed for small scale changes in the vicinity of zero, and
plus and minus scales are symmetrical. A DVM might be an
example of its use.
CONT,ROL
Each ADC must accept and/or provide digital control signals telling it and/or the external system what to do and
when to do it. Control signals should be compatible with one
or more types of logic in common use. Control signal timing
must be such that the converter or connected system will
accept the signals. Common control sig'nals are listed below.
Start Conversion (SC) is a digital signal to an ADC which
initiates a single conversion cycle. Typically, an SC signal
must be present at the fall (or rise) of the clock waveform to
initiate the cycle. A DAC needs no SC signal; however, such
could be provided to gate digital inputs to a DAC.
End of Conversion (EOC) is a digital signal from an ADC
which informs the external system that the digital output
data is valid. Typically, an EOC output can be connected to
an SC input to cause the ADC to operate in continuous
conversion mode. In non-continuous conversicm systems,
the SC signal is a command from the system to the ADC. A
DAC does not supply an EOC signal.
Clock signals are required or must be generated within an
ADC to control counting or successive approximation registers. The cloqk controls the conversion speed within the
limitations of the ADC. DACs do not require clock signals.
CONCLUSION
Once the user has a working knowledge of DAC or ADC
characteristics and specifications, he should be able to select a converter to suit a specific system need. The likelihood of overspecification, and therefore an unnecessarily
high cost, is likewise reduced. The user will also be aware
that specific paramelers, test conditions, test circuits,and
even definitions may vary from manufacturer to manufacturer. For practical production reasons, parameters may not be
tested in the same manner for all converter types, even
those supplied by the same manufacturer. USing information
in this note, the user should, however, be able to sort out
and understand those specifications (from any/manufacturer) pertinent to his needs.
338
r------------------------------------------------------------,~
Ie Voltage Reference has
National Semiconductor
Application Note 161
1 ppm per Degree Drift
A new linear IC now provides the ultimate in highly stable
voltage references. Now, a new monolithic IC the LM199,
out-performs zeners and can provide a 6.9V reference with
a temperature drift of less than 1 ppmI' and excellent long
term stability. This new IC, uses a unique subsurface zener
to achieve low noise and a highly stable breakdown. Included is an on-chip temperature stabilizer which holds the chip
temperature at go·C, eliminating the effects of ambient temperature changes on reference voltage.
~~
SUB SURFACE ZENER IMPROVES STABILITY
Previously, breakdown references made in monolithic IC's
usually used the emitter-base junction of an NPN transistor
as a zener diode. Unfortunately, this junction breaks down
at the surface of the silicon and is therefore susceptible to
surface effects. The breakdown is noisy, and cannot give
long-term stabilities much better than about 0.3%. Further,
a surface zener is especially sensitive to contamination in
the oxide or charge on the surface of the oxide which can
cause short-term instability or turn-on drift.
The new zener moves the breakdown below the surface of
the silicon into the bulk yielding a zener that is stable with
time and exhibits very low noise. Because the new zener is
made with well-controlled diffusions in a planar structure, it
is extremely reproducible with an initial 2% tolerance on
breakdown voltage.
A cut-away view of the new zener is shown in Figure 1. First
a small deep P+ diffusion is made into the surface of the
c;ilicon. This is then covered by the standard base diffusion.
The N + emitter diffusion is then made completely covering
the P+ diffusion. The diode then breaks down where the
dopant concentration is greatest, that is, between the P +
and N +. Since the P + is completely covered by N + the
breakdown is below the surface and at about 6.3V. One
connection to the diode is to the N + and the other is to the
P base diffusion. The current flows laterally through the
base to the P+ or cathode of the zener. Surface breakdown
does not occur since the base P to N+ breakdown voltage
is greater than the breakdown of the buried device. The
buried zener has been in volume production since 1973 as
the reference in the LX5600 temperature transducer.
The planar monolithic IC offers superior performance compared to conventional reference diodes. For example, active
circuitry buffers the reverse current to the zener giving a
dynamic impedance of 0.50. and allows the LM199 to operate over a 0.5 mA to 10 mA current range with no change in
performance. The low dynamic impedance, coupled with
low operating current significantly simplifies the current
drive circuitry needed for operation. Since the temperature
coefficient is independent of operating current, usually a resistor is all that is needed.
Previously, the task of providing a stable, low temperature
coefficient reference voltage was left to a discrete zener
diode. However, these diodes often presented significant
problems. For example, ordinary zeners can show many millivolts change if there is a temperature gradient across the
package due to the zener and temperature compensation
diode not being at the same temperature. A 1·C difference
may cause a 2 mV shift in reference voltage. Because the
on-chip temperature stabilizer maintains constant die temperature, the IC reference is free of voltage shifts due to
temperature gradients. Further, the temperature stabilizer,
as well as eliminating drift, allows exceptionally fast warmup over conventional diodes. Also, the LM199 is insensitive
to stress on the leads-another source of error with ordinary glass diodes. Finally, the LM199 shows virtually no hysteresis in reference voltage when subject to temperature
cycling over a wide temperature range. Temperature cycling
the LM199 between 25·C, 150·C and back to 25"C causes
less than 50 /J-V change in reference voltage. Standard reference diodes exhibit shifts of 1 mV to 5 mV under the same
conditions.
CIRCUIT DESCRIPTION
The block diagram of the LM199 is shown in Figure 2. Two
electrically independent circuits are included on the same
chip-a temperature stabilizer and a floating active zener.
The only electrical connection between the two circuits
7 Q
N'
EMITTER
IUFFUSION
ZENER
CATHODE
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SUBSURFACE
BREAKDOWN
ISOLATION
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BURIED LAYER
TUH/5613-1
FIGURE 1. Subsurface Zener Construction
339
FIGURE 2. Functional Block
Diagram
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cc
is the isolation diode inherent in any junction-isolated integrated circuit. The zener may be used with or without the
temperature stabilizer powered. The only operating restric. tion is that the isolation diode must never become forward
biased and the zener must not be biased above the 40V
breakdown of the isolation diode.
The actual circuit is shown in Figure 3. The temperature
stabilizer is composed of 01 through 09. FET Q9 provides
. current to zener 02 and
Current through
turns a loop
consisting of 01, 05, 06, 07, R1 and R2. Abou1 5V is applied to the top of R1 from the base of 07. This causes 400
p.A to flow through the divider R1, R2. Transistor 07 has a
controlled gain of 0.3 giving 07 a total emitter current of
about 500 !LA. This flows through the emitter of
and
drives another controlled gain PNP transistor 05. The gain
of 05 is abou1 0.4 so 01 is driven with about 200 p.A. Once
is reverse biased and the loop
current flows through 05,
is self-sustaining. This circuitry ensures start-up.
oa.
as base drive to a Darlington composed of 01 and 02. The
Darlington is connected across the supply and initially draws
140 mA (set by current limit transistor 03). As the chip
heats, the turn on voltage for 04 decreases and 04 starts to
conduct. At about 90"C the current through 04 appreciably
increases and less drive is applied to 01 and 02. Power
dissipation decreases to whatever is necessary to hold the
chip at the stabilization temperature. In this manner, the
chip temperature is regulated to better than 2"C for a 100"C
temperature range.
oa
The zener section is relatively straight-forward. A buried zener 03 breaks down biasing the base of transistor 013.
Transistor 013 drives two buffers 012 and 011. External
current changes through the circuit are fully absorbed by the
buffer transistors rather than 03. Current through 03 is held
constant at 250 p.A by a 2k resistor across the emitter base
of 013 while the emitter-base voltage of 013 nominally temperature compensates the reference voltage.
as
oa
The other components, 014, 015 and 016 set the operatIng current of 013. Frequency compensation is accomplished with two junction capacitors.
The resistor divider applies 400 mV to the base of 04 while
07 supplies 120 !LA to its collector. At temperatures below
the stabilization point, 400 mV is insufficient to cause 04 to
conduct. Thus, all the collector current from 07 is provided
111
4.2
~--------4---4---~--~~----4----e----t,.
v-
D3
B.3V
3D,f
1l1li
211
2.6k
zTL/H/5613-2
FIGURE 3. Schematic Diagram of LM199 Precision Reference
-
340
'PERFORMANCE
A polysulfone thermal shield, shown in Figure 4, is supplied
with the LM199 to minimize power dissipation and improve
temperature regulation. Using a thermal shield as well as
the small, high thermal resistance TO-46 package allows
operation at low power levels without the problems of special IC packages with built-in thermal isolation. Since the
LM199 is made on a standard IC assembly line with standard assembly techniques, cost is significantly lower than if
special techniques were used. For temperature stabilization
only 300 mW are required at 25'C and 660 mWat -55'C.
200
~ 150
1\
!
..~
~
IGO
-
STABILIZED ITt' sO"C)_
\..
Tt"25'C
50
10
lOG
"
1l1li
101lle
FREQUENCY IH~
FIGURE 5. Wldeband Noise of the LM199 Reference
D.OI H.~I"I H.
STABILIZED
IT, - 9O"C)
TL/H/5613-3
10
FIGURE 4. Polysulfone Thermal Shield
TIME IMINUTES)
TLlH/5613-4
Temperature stabilizing the device at 90'C virtually eliminates temperature drift at ambient temperatures less than
90'C. The reference is nominally temperature compensated
and the thermal regulator further decreases the temperature
drift. Drift is typically only 0.3 ppml'C. Stabilizing the temperature at 90'C rather than 12S'C significantly reduces
power dissipation but still provides very low drift over a major portion of the operating temperature range. Above 90'C
ambient, the temperature. coefficient is only 15 ppm/'C.
FIGURE 6, Low Frequency NOise Voltage
Because the planar structure does not exhibit hysteresis
with temperature cycling, long-term stability is not impaired
if the device is switched on and off.
The temperature stabilizer heats the small thermal mass of
the LM199 to 90'C very quickly. Warm-up time at 25'C and
- 55'C is shown in Figure 7. This fast warm-up is significantly less than the several minutes needed by ordinary diodes
to reach equilibrium. Typical specifications are shown in Table I.
A low drift reference would be virtually useless without
equivalent performance in long term stability and low noise.
The subsurface breakdown technology yields both of these.
Wideband and low frequency noise are both exceptionally
low. Wideband noise is shown in Figure 5 and low frequency
noise is shown over a 10 minute period in the photograph of
Figure 6. Peak to peak noise over a 0.01 Hz to 1 Hz bandwidth is only about 0.7 /J-V.
.l
TA zl•c
i
~
o
Long term stability is perhaps one of the most difficult measurements to make. However, conditions for long-term stability measurements on the LM199 are considerably more
realistic than for commercially available certified zeners.
Standard zeners are measured in ± 0.05'C temperature
controlled both at an operating current of 7.5 mA ±O.OS /J-A.
Further, the standard devices must have stress-free contacts on the leads and the test must not be interrupted during the measurement interval. In contrast, the LM199 is
measured in still air of 25'C to 28'C at a reverse current of
1 mA ± 0.5%. This is more typical of actual operating conditions in instruments.
When a group of 10 devices were monitored for long-term
stability, the variations all correlated, which indicates changes in the measurement system (limitation of 20 ppm) rather
than the LM199.
-I
-2
-3
/ , ,~:. -5~C
,
I
I
,,
VH-'&V
IZ
II
HEATER ON TIME -ISEC)
211
TL/H/5613-5
FIGURE 7. Fast Warmup Time 01 the LM199
Table I. Typical Specifications for the LM199
Reverse Breakdown Voltage
6.9SV
O.S mA to 10 mA
Operating Current
Temperature Coefficient
Dynamic Impedance
RMS Noise (10Hz to 10kHz)
Long-Term Stability
Temperature Stabilizer Operating Voltage
Temperature Stabilizer Power Dissipation
(25'C)
Warm-up Time
341
0.3ppm/'C
0.50
7/J-V
";20 ppm
9Vto 40V
300mW
3 Seconds
_ r-------------------------------------------------------------------~
-~
co
APPLICATIONS
The LM199 is easier to use than standard- zeners, but the
temperature stability is so good-even better than precision
resistors-that care must be taken to prevent e~emal circuitry from limiting performance. Basic operation only requires energizing the temperature stabilizer from a 9V to
40V power source and biasing the reference with between
0.5 mA to 10 mA of current. The low dynamic impedance
minimizes the current regulation required compared to ordinary zeners.
The only restriction on biasing the zener is the bias applied
to the isolation diode. Firstly, the isolation diode must not be
forward biased. This restricts the voltage at either terminal
of the zener to a voltage equal to or greater than the V - .
A dc return is needed blltween the zener and heater to insure the voltage limitation
the isolation diodes are not
exceeded. Figure 8 shows the basic biasing of the LM199.
The active circuitry in the reference section of the LM 199
reduces the dynamic impedance of the zllnerto about 0.50.
This is especially useful in biasing the reference. For example, a standard reference-diode such as a 1N829 operates
at 7.5 mA and has Ii dynamic impedance of 150. A 1%
change in current (75 p.A) changes the reference voltage by
1.1 mY. Operating the LM199 at 1 m.6: with the same 1%
change in operating current (10 p.A) results in a reference
change. of only 5 p.V. Figure 9 shows reverse voltage
change with current.
Biasing current for the referenc;e can by anywhere from 0.5
mA to 10 mA with little change in performance. This wide
current range allows direct replacement of most zener types
with no other circuit changes besides the temperature stabilizer connection. Since the dynamic impedance is constant
with current changes regulation is better than discrete zeners. For optimum regulation, lower operating currents are
10
REVERSE CURRENT fmA)
TL/H/5613-6
FIGURE 9. The LM199 Shows Excellent Regulation
Against Current Ch~nges
preferred since the ratio- of source resistance to zener impedance is higher, and the attenuation of input changes is
greater. Further, at low currents, the voltage drop in the
wiring is minimized.
Mounting is an important consideration for optimum performance. Although the thermal shield minimizes the heat
low, the LM199 should not be exposed to a direct air flow
such as from a cooling fan. This can cause as much as a
100% increase in power dissipation degrading the thermal
regulation and increasing the drift. Normal conviction currents do not degrade performance.
Printed circuit board layout is also important. Firstly, four
wire sensing should be us~d to eliminate ohmic drops in pc
traces. Although the voltage drops ar",. small the temperature coefficient of the voltage developed along a copper
trace can add significantly to the drift. For example, a trace
with 10 resistance and 2 mA current flow will develop 2 mV
drop. The TC of copper is 0.004%'OC so the 2 mV drop will
change at 8 p.V,oC, this is an additional 1 ppm drift error. Of
course, the effects of voltage drops in the printed circuit
traces are eliminated with 4-wire operation. The heater current also should not be allowed to flow through the voltage
reference traces. Over a -55"C to + 125°C temperature
on
.,50-__--.......,
10 TO 4 0 0 - _ - - - _
AS
TEMPERATURE
STABILIZER
U50
-fSV
-IV TO
-33V
.,50--.----+-----...---.
Ito
Uk
lOY
TLlH/5613-7
FIGURE 8. BasiC Biasing of the LM199
342
range the heater current will change from about 1 mA to
over 40 mA. These magnitudes of current flowing reference
leads or reference ground can cause huge errors compared
to the drift of the LM199.
regulation on the input supply is adequate contributing less
than 10 P.V of error to the output. Feedback resistors
around the LM308 scale the output to 10V.
Although the absolute values of the resistors are not extremely important, tracking of temperature coeffiCients is vital. The 1 ppm/DC drift of the LM199 is easily exceeded by
the temperature coefficient of most resistors. Tracking to
better than 1 ppm is also not easy to obtain. Wirewound
types made of Evenohm or Mangamin are good and also
have low thermoelectric effects. Film types such as Vishay
resistors are also good. Most potentiometers do not track
fixed reSistors so it is a good idea to minimize the adjustment range and therefore minimize their effects on the output TC. Overall temperature coefficient of the circuit shown
in Figure 10 is worst case 3 ppm/DC. About 1 ppm is due to
the reference, 1 ppm due to the resistors and 1 ppm due to
the op amp.
Thermocouple effects can also use errors. The kovar leads
from the LM199 package from a thermocouple with copper
printed circuit board traces. Since the package of the 199 is
heated, there is a heat flow along the leads of the LM199
package. If the leads terminate into unequal sizes of copper
on the p.c. board greater heat will be absorbed by the larger
copper trace and a temperature difference will develop. A
temperature diff8r8f1Ce of 1°C between the two leads of the
reference will generate about 30 p.A. Therefore, the copper
traces to the zener should be equal in size. This will generally keep the errors due to thermocouple effects under about
15 p.V.
The LM199 should be mounted flush on the p.c. board with
a minimum of space between the thermal shield and the
boards. This minimizes air flow across the kovar leads on
the board surface which also can cause thermocouple voltages. Air currents across the leads usually appear as ultralow frequency noise of about 10 p.V to 20 p.Vamplitude.
Figure 11 shows a standard cell replacement with a 1.01V
output. A LM321 and LM308 are used to minimize op amp
drift to less than 1 p.VfOC. Note the adjustment connection
which minimizes the TC effects of the pot. Set-up for this
circuit requires nulling the offset of the op amp first and then
adjusting for proper output voltage.
It is usually necessary to scale and buffer the output of any
reference to some calibrated voltage. Figure 10 shows a
simple buffered reference with a 10V output. The reference
is applied to the non-inverting input of the LM108A. An RC
rolloff can be inserted in series with the input to the LM108A
to roll-off the high frequency noise. The zener heater" and op
amp are all powered from a Single 15V supply. About 1 %
The drift of the LM321 is very predictable and can be used
to eliminate overall drift of the system. The drift changes at
3.6 p.VfOC per millivolt of offset so 1 mV to 2 mV of offset
can be introduced to minimize the overall TC.
---9--------,
.
.. & V - -....
lBV
FIGURE 10. Buffered 10V Reference
15V ....._--~,...._-----------_ _- - - - - - - - - J.5V
uv
OUTPUT
LM1U
Tl/H/5613-B
FIGURE 11. Standard Cell Replacement
343
earlier. A ten-tum pot will adjust the output from +,yz to
- Vz contifluously. For negative output the op amp operates
as an inverter while for positive outputs it operates as.a noninverting connection.
Op amp choice is important for this circuit. A lo~ drift device
such as the LM108A or a LM108-LM121 combination will
provide excellent performance. The pot should be a precision wire wound 10 tum type. It should be noted that the
output ot this circuit is not linear.
For circuits with a ·wide. input voltage range, the reference
carl, be power"d from the ootput of the buffer as is shown in
Figure 12. The op 'amp supplies regulated voltage to the
resistor biasing the reference minimizing changes due to
input variation. There is SQme change due to v~ation of· the
temperature stabilizer vpltage so extremely wide range operaticln is not reC9mmen!led for highest preciSion. An additional res.istor (shown 60 kO) is .. added to the unregulated
input to insure the circuit lltarts up properly at tJ:Ie application of power.
.
Aprecision power supply is shown in F/{/ure 13. The output
of the op amp is buffered by an 10 power transistor the
LM395. The LM395 operates as an NPN power device but
requires only 5 'jIA base current. Full overload protection
inherent in the LM395 includes current limit, safe-area protection, and thermal limit.
A reference which can supply either a positive or a negatiVe
continuously variable output is shown in Figure 14. The reference is biased from the ± 15 input supplies as was shown
CONCLUSIONS
A new monolithic reference which exceeds the performance
of convEintional zeners has been. developed.. In facit, the
LM199 performance is· limited more !;Iy external components
than by reference drift itself. Further, .m~lny of the problems
associated with conventional zeners such as hysteresis,
.stress sensitivity .and temperature gradient sensitivity tiave
also been eliminated. Finally, long-te~m stability ~,rid nOise
are equal of the drift performance Of tl)e new deviCe.
'avTO ..V....--~....---------,
...
OUTPUT
FIGURE 12. Wide Range Input Voltage Reference
"VT.@V---~----t------------1~-----'
..
LI't151
TtMPERATURE
ITABILIZEA
1J5V
lM1.
-5V
FIGURE 13. Precision Power Supply
.15V---....- - - - .
..
,
OUTPUT1:I.IV
lIMPERATURE
STABILIZER
'.m
.. ~--:.t.
-'iV
lM,n
3Ipf,
-IIiV
TLlH/5613-9
FIGURE 14. Bipolar Output Reference
344
National Semiconductor
Application Note 162
LM2907 Tachometer/Speed
Switch Building Block
Applications
INTRODUCTION
Frequency to voltage converters are available in a number
of forms from a number of sources, but invariably require
significant additional components before they can be put to
use in a given situation. The LM2907, LM2917 series of
devices was developed to overcome these objections. Both
input and output interface circuitry is included on chip so
that a minimum number of additional components is required to complete the function. In keeping with the systems
building block concept, these devices provide an output
voltage which is proportional to input frequency and provide
zero output at zero frequency. In addition, the input may be
referred to ground. The devices are designed to operate
from a single supply VOltage, which makes them particularly
suitable for battery operation:
PART 1--GENERAL OPERATION PRINCIPLES
Circuit Description
Referring to Figure 1, the family of devices all include three
basic components: an input amplifier with built-in hysteresis;
a charge pump frequency to voltage converter; and a versatile op amp/comparator with an uncommitted output transistor. LM2917 incorporates an active zener regulator on-chip.
LM2907 deletes this option. Both versions ere obtainable in
14-pin and in B-pin dual-in-line molded packages, and to
special order in other packages.
LM2907N-8
LM2917N-8
v'
4
TlIHI7451-1
TL/H17451-2
LM2907N
Nt
LM2917N
Nt
Nt
Nt
Nt
v,
Nt
Nt
Nt
TlIH17451-4
TL/H/7451-3
FIGURE 1. Block Diagrams
345
.
~ r-~,~,-.--,-,--------------------------------------------------------------~
....
, Inp!,!t Hysteresis Amplifier
~The equivalent schematic diagram is shown in Fi{JIJre2. 01
through·011 comprise the input hysteresis amplifier. 01
t~rOugh 04 comprise an input differential amplifier which, by
virtue of PNP level shifting, enables the circuit to operate
with signals referenced to ground. 07, 08, 04, and 05 comprise an active load with positive feedback. This load behaves as a bi-stable flip-flop which may be set or reset depending upon the currents supplied from 02 and 03. Con; sider the situation where 02 and 03 are conducting equally,
i.e. the input differential voltage is zero. Assuming 07 to be
conducting, it will be noted that the, current f~om 03 will be
drawn by 07 and 08 will be in the "OFF" state. This allows
the current from 02 to drive 07 in parallel with D4 and a
small resistor. 04 and 07 are identical geometry devices, so
that the resistor causes 07 to be biased at a higher level
than 04. Thus 07 will be able to conduct more current than
03 provides. In order to reverse the state ·of 07 and 08, it
will be necessary.to reduce the current from 02 below that
provided by 03 by an amount which is established by R1. It
can be shown that this requires a differential input to 01 and
04, of approximately 15mV. Since the circuit is symmetrical,
the threshold voltage to reverse the state is 15 mV in the
other direction. Thus the input amplifier has built-in hysteresis at ± 15 mY. This provides clean switching where noise
maybe present on the input signal, and allows total rejection of noise below this .amplitude where there is no, input
si,gnal.
I
'
required ,to return the capacitot on pin 2 ,to the high level
voltage is duplicated and used to charge tlie caPaCitor connected to pin 3. Thus in one cycle qf input, the capacitor on
pin 3 gets charged twice with a charge of CV.'
.
Thus the total charge pumped into the capacitor on pin 3
per cycle is:
'
(2)
0= 2CV
Now, since V = Vee/2
(3)
ttlen
0= CVee
A resistor connected between pin 3 'and ground causes a
discharge of the capacitor on pin 3, where the total chl!rge
drained per cycle of input signal is equal to:
V3-T
01 =-R-'
where
V3 = the average voltage on pin '3
, T = period of input signal
R = resistor connected to pin 3
In equilibrium 0 = 01
.
'
v3-i
I.e., CVee = -R-
(4)
and
(5)
or
V3 = Vee-R-C-f
where f = input frequency
(6)
Charge Pump
Op Amp/Comparator
The charge pump is composed of 012 through 032. R4, R5,
and R6 provide reference voltages equal to 1/4 and 3/4 of
supply voltage to 012 and 013. When 010 turns "ON" or
"OFF," the base voltage ilt 016 ch,anges by an amount
equal to the voltage across R5, that is 1/2 Vee. A capacitor
connected between Pin 2 and ground is either charged by
021 or discharged by 022 until its voltage matches that on
the base of 016. When the voltage on 016 base goes low,
016 turns "ON," which results in 018 and 026 turning on,
which causes the current, sourced by 019 and 020, to be
shunted to ground. Thus 021 is unable to charge pin 2.
Meanwhile, 027 and 030 are turned off permitting the
200 /l-A sourced by 028 and 029 to enter the emitters of
031 and 032 respectively. The current from 031 is mirrored
by 022 thrQugh 024 resulting .in a 200 /l-A discharge current
through pin 2. The external capacitor on pin 2 is thus discharged at a constant rate until it reaches the new base
voltage on 016. The time taken for this discharge to occur is
given by:
Again referring to F1[Jure 2, the opamp/comparator includes
035 through 045. A PNP input stage again provides input
common-mode voltages down to zero, and if pin 8 is connected to Vee and the output taken
pin 5, the circuit
behaves as a conventional, unity-gain-compenliated operational amplifier. However, by allowing alternate connections
of 045 the circuit' may be used as a comparator in which
loads to either Vee or ground may be switched. 045 is capable of sinking 50 mAo Input bias current is typically 50 nA,
and voltage gain is typically 200 V(mV. Unity gain slew rate
is 0.2 V/ /l-s. When operated as a comparator 045 emitter
will switch at the slew rate, or the collector 01'045 will
switch at that rate multiplied by the voltage gain of 045,
which is user selectable.
CV
t=-
I
where
from
Active Zener Regulator
The optional active zener regulator is also shown ,in F1[JUf8
2. 08 provides the voltage reference in conjunction with
033. As t/Je supply voltage rises, 08 conducts and the base
voltage on 033 starts to rise. When C33 has sufficient base
voltage to be turned "ON," it in tum causes 034 to conduct
current from the power source. This reduces the current
available for 08 and the negative feedback loop is thereby
completed. The reference voltage is therefore the zener
voltage on 08 plus the emitter base voltage of 033. This
results in a low temperature coefficient voltage.,
(1)
C = capacitor on pin 2
V = change in voltageon 016 base
I = current in 022
During this time, 032 sources an identical current into pin 3.
A capacitor connected to pin 3 will thus be charged by the
same current for the same amount of time as pin 2. When
the, base voltage on 016 goes high, 018 and 026 are
turned off while 027 and 030 are:turned "ON." In these
'conditions, 021 and 025 provide the currents to charge the
capacitors on pins 2 and 3 respectively. Thus the charge
Input Levels and Protection
In 8-pin versions of the LM2907, LM2917, the non-Inverting
inpulof the op amp/comparator is connected to the output
of the charge pump. Also, one inpuUo the input hYsteresis
amplifier is connected to ground. The other input (pin 1) is
then protected from transients by, first a 10kO series resis-
346
.----,
I
rn-------------..,
it
I
liAS
O' AMP COMPARATOR
II
I
I
,
,
'"
"
I
I
I
I
I
I
I
I
I
l-
~
D121
D131
I
I
I
I
ZlOI
.A
I
'-----"0 I
L __________ j
"Note: This connection made on lM2907-8 and lM2917-8 only.
_____
~
____
I
~
CHARGE PUMP
""Note: This connection made on lM2917 and lM2917-8 only.
TLlH17451-5
Not.: Pin numbers refer to 14-pin package.
FIGURE 2. Equivalent Schematic Diagram
~9~·NV
-----
----,
-
""""".. ~-,-~..::-.....-,..~-.---
--
-~-~--~----~~'... .cM _ _ ~
....~
z•
c(
tor, R3 (Figure 2) which is located in a floating isolation
pocket, and secondly by clamp diode D1. Since the voltage
swing on the base of 01 is thus restricted, the only restriction on the allowable voltage on pin 1 is the breakdown
voltage of the 10 kl} resistor. This allows input swings to
± 28V. In 14-pin versions the link to D1 is opened in order to
allow the base of 01 to be biased at some higher voltage.
Second, if R1 is too large, it can become a significant fraction of the output impedance at pin 3 which degrades linearity. Finally, ripple voltage must be considered, and the size
of C2 is affected by R 1. An expression that describes the
ripple content on pin 3 for a single R1, C2 combination is:
VRIPPLE =
05 clamps the negative swing on the base of 01 to about
300 mV. This prevents substrate injection ·in the region of
01 which might otherwise cause false switching or erroneous discharge of one of the timing capacitors.
The differential input options (LM2907-14, LM291,7-14), give
the user the option of setting his own input switching level
and still having the hysteresis around that level for excellent
noise rejection in any application.
Vee
C1 (
""2 e C2
1-
vccellNeC1)
12
pop
It appears R1 can be chosen independent of ripple, however response time, or the time it takes VOUT to stabilize at a
new frequency increases as the size 01 C2 increases, so a
compromise between ripple, response time, and linearity
must be cosen carefully. R1 should be selected according
to the following relationship:
C is seleCted according to:
C1 =
V3 Full Scale
R1 e Vee e IFULLseALE
Next decide on the maximum ripple which can be accepted
and plug into the following equation to determine C2:
HOW TO USE IT
BasiC f to V Converter
The operation of the LM2907, LM2917 series is best understood by observing the basic converter shown in Figure 3. In
this configuration, a frequency signal is applied to the input
of the charge pump at pin 1. The voltage appearing at pin 2
will swing between two values which are approximately 1/4
(Vee> - VBE and 3/4 (Vee> - VBE. The voltage at pin 3 will
have a value equal to Vee e fiN e C1 e R1 e K, where K is
the gain constant (normally 1.0).
The emitter output (pin 4) is connected to the inverting input
01 the op amp so that pin 4 will follow rin 3 and provide a
low impedance output voltage proportional to input frequency. The linearity of this voltage is typically better than 0.3%
of full scale.
C2 =
2
VRIPPLE
R112
The kind of capacitor used for timing capacitor C1 will determine the accuracy of the unit over the temperature range.
Figure 15 illustrates the tachometer output as a function of
temperature for the two devices. Note th!lt the LM2907 operating from a fixed external supply has negative temperature coefficient which enables the device to be used with
capacitors which have a positive temperature coefficient·
and thus obtain overall stabililty. In the case of the LM2917
the' internal zener supply voltage has a positive coefficient
which causes the overall tachometer output to have a very
low temperature coefficient and requires that the capaCitor
temperature coefficient be balanced by the temperature coefficient of R 1.
a:
Choosing R1. C1 and C2
There are some limitations on the choice of R1, C1 and C2
(Figure 3) which should be considered for optimum performance. C1 also provides internal compensation for the
charge pump and should be kept larger than 100 pF. Smaller values can cause an error current on R1, especially at
low temperatures. Three considerations must be met when
choosing R1.
Using Zener Regulated Options (LM2917)
For those applications where an output voltage or current
must be obtained independently of the supply voltage variations, the LM2917 is offered. Th!l reference typically has an
11 I} source resistance. In choosing a dropping resistor from
the unregulated supply to the device note that the tachometer and op amp Circuitry alone require about 3 mA at the
voltage level provided by the zener. At low supply voltages,
First, the output current at pin 3 is internally fixed and therelore V3 max, divided by R1, must be less than or equal to
this value.
:. R1
Veee~ (1 -~)
~ V3max
ISMIN
where V3 max is the full scale output voltage required
lSMIN Is determined from the data sheet (150 pA)
Vee
+VOUT
HZ
10k
TUHI7451-6
FIGURE 3. Basic f to VConverter
348
Input Interface Circuits
there must be some current flowing in the resistor above the
3 mA circuit current to operate the regulator. As an example, if the raw supply varies from 9V to 16V, a resistance of
4700 will minimize these zener voltage variations to 160
mV. If the resistor goes under 4000 or over 6000 the zener
variation quickly rises above 200 mV for the same input variation. Take care also that the power dissipation of the Ie is
not exceeded at higher supply voltages. Figure 4 shows
suitable dropping resistor values.
"
The ground referenced input capability of the LM2907-8 allows direct coupling to transformer inputs, or variable reluctance pickups. Figure 5(8) illustrates this connection. In
many cases, the frequency signal must be obtained from
another circuit whose output may not go below ground. This
may be remedied by using ac coupling to the input of the
LM2907 as illustrated in Figure 5(b). This approach is very
suitable for use with phototransistors for optical pickups.
Noisy signal sources may be coupled as shown in Figure
5(c). The signal is bandpass filtered. This can be used, for
example, for tachometers operating from breakerpoints on a
conventional Kettering ignition system. Remember that the
minimum input signal required by the LM2907 is only 30
mVp-p, but this signal must be able to swing at least 15 mV
on either side of the inverting input. The maximum signal
which can be applied to the LM2907 input, is ±28V. The
input bias current is a typically 100 nA. A path to ground
must be provided for this current through the source or by
other means as illustrated. With 14-pin package versions of
LM2907, LM2917, it is possible to bias the inverting input to
the tachometer as illustrated in Rgure 5(d). This enables the
circuit to operate with input signals that do not go to ground,
but are referenced at higher voltages. Alternatively, this
method increases the noise immunity where large signal
~7n~~~~~~---'
38
~
32
e'"..,..
21
>-
..
2D
:I
18
...
~
24
8~~~
12
I DO
&00
lk
Uk
2k
Uk
POWER SUPPL Y DROPPING RESISTOR - (OHMS)
TLfH17451-7
FIGURE 4. Zener Regular Bias Resistor Range
TL/H17451-8
(a) Ground Referenced Inputs
TLfH17451-9
(b) AC Coupled Input
TL/H17451-10
(c) Bandpass Filtered Input
Reduces Noise
+
+
'IN
TL/H17451-11
TLfH17451-12
(d) Above Ground Sensing
(e) High Common-Mode Rejection Input Circuit
FIGURE 5. Tachometer Input Configurations
349
levels are available but large noise 'signals on ground are
also present. To take full, advantage ,of the common-mode
rejection of the input djfferElntia! stage, a ba,lanced bias oonfiguration must be prC)vidE!d. One such circuit is illustrated in
Figure 5(e). With this arrangement, the effective, cQm(nonmode rejection roay be virtually infinite" ow,ing to the input
hysteresis.'
'
placed in series with the output to protect the LED and the
output transistor.
This circuit has no 'hysteresis in it, i.e., the turn "ON" and
turn "OFF"'spe8dvoltBgesare essentially equal. In cases
where speed may be fluctuating at a high rate and a flashing
tED would beobjdonable, it is possible to incorporate
hystereSiS so that the switch-ori speed is above the switchoff speed by a oontrolled amount. Such Ii configuration is
illustrated in Figure 6(b). Figure 6(c) shows how a grounded
load can also be switched by the circuit. In this case, the
current limiting resistor is placed in the collector of the power transistor. The base current of th!il output transistor (Q45)
is limited by a 5 kO base resistor (see Figure 2). This raises
the output resistance so that the output swing will be reduced at fuli load.
"
The op amp/comparator is internally compensated for unity
gain feedback configurations as in Figure 6(d). By directly
connecting the emitter output to the non-inverting input, the
op amp may be operated as a voltage follower. Note that a
load resistor is required externally. The op amp can also be
operated, of course, as an amplifier, integrator, active filter,
or in any other normal operational amplifier configuration.
Output Configurations
LM2907, LM2917se'ries deVices inoorporate an unusually
flexil;lle op amp/ comparator deviCe on-chip for iriter.facing
with a wide variety of loads. This flexibilitY results from the
availability of bo~ the collector and emitter of 'the output
transistor which is capable of c!riving ,UP to 50 inA of load
current. When the non-inverting input is higher than the inverting input, ihis output transistor is turned "ON". It may be
used to drive loads to either the positive or the negative
supply, with thl' emitter or collector respectively connected
to th,e other supply. ,For example, FiQure 6(a), a simple
speed switch can be oonstrll,cted in which lhe spe,ed signal
derived from the frequency to voltage converter is compared to a reference derived simply by a resistive divider
from the power supply. When the speed signal exceeds the
reference, the output transistor turns on the light emitting .
diode'ln the load. A small currenJ limiting resistor sh~uld be
One unique configuration which is not available with standard operational amplifiers, is shown in Figure 6(e). Here
the col\ector of the outpUt transistor is used: to drive a load
Vee
TLlH/7451-13
(a) Switching an LED
TL/H/7451-14
(b) Adding Hysteresis
to LED Switch
TLlH/7451-15
(c) Switching a Grounded Load
Vee
Vee
vee
Vs o-""'YVv"'-"'U"--t--t
...-
..... ,OUT·VS
...-
..... VOUT
Vs
TL/HI7451-16
, (d) Voltage Follower
TLlH17451-17
(e) Voltage to Current Conl/erter
FIGURE 6. Output Configurations
350
TL/H17451-18
(f) Integrator
~-------------------------------------------------------------------,>
with a current which is proportional to the input voltage. In
other words, the circuit is operating as a voltage to current
converter. This is ideal for driving remote signal sensors and
moving coil galvanometers. Figure 6(t) shows how an active
integrator can be used to provide an output which falls with
increasing speed.
Figure 7 illustrates methods for protecting against these and
other transients. Figure 7(a) shows a typical situation in
which the power supply to the LM2907 can be provided
through a dropping resistor and regulated by an external
zener diode 21, but the output drive is required to operate
from the full available supply voltage. In this case, a separate protection zener 22 must be provided if the voltage on
the power line is expected to exceed the maximum rated
voltage of the LM2907.
In Figure 7(b) and Figure 7(e), the output transistor is required only to drive a simple resistive load and no secondary protection circuits are required. (Note that the dropping
resistor to the zener also has to supply current to the output
circuit). With the foregoing circuits, reverse supply protection is supplied by the forward biased zener diode. This device should be a low forward resistance unit in order to limit
the maximum reverse voltage applied to the integrated circuit. Excessive reverse voltage on the Ie can cause high
currents to be conducted by the substrate diodes with consequent danger of permanent damage. Up to 1V negative
can generally be tolerated. Versions with internal zeners
may be self-protecting depending on the size of dropping
resistor used. In applications where large negative voltage
These are the basic configurations obtainable with the op
amp/comparator. Further combinations can be seen in the
applications shown in Part" of this application note.
Transient Protection
Many application areas use unregulated power supplies
which tend to expose the electronics to potentially damaging transients on the power supply line. This is particularly
true in the case of automotive applications where two such
transients are common. 1 First is the load dump transient.
This occurs when a dead battery is being charged at a high
current and the battery cable comes loose, so that the current in the alternator inductance produces a positive transient on the line in the order of 60V to 120V. The second
transient is called field decay. This occurs when the ignition
is turned "OFF" and the energy stored in the field winding
of the alternator causes a negative 75V transient on the
ignition line.
.
TL/H17451-20
TL/HI7451-19
(8)
(b)
r-----------~----~~~~OVB
Dl
TLlHI7451-22
TLlHI7451-21
(c)
(d)
FIGURE 7. Transient Protection Schemes
351
z
•
....
en
N
translentsinay be anticipated, a blocking diode may be con·
nected in the power supply line to the IC lis illustrated in
Figure 7(d). During these negative transients, the diode 01
will be reverse biased and prevent reverse currents flowing
in the IC. If these transients are short and the capacitor Cl
is'large enough, then the power to the IC can be sustained.
This is useful to prevent change of state or change of
charge in in systems connected' to' it.
The concept of building blocks ,requires that a function be
performed in the same way as it cIIn be mathematically de·
fined. In other words, a frequency to voltage converter will
prOvide an output voltage proportional to frequency which is
independent of the input voltage or other input parameters;
except the frequency. In the same way, the output voltage
will be zero when the input frequency is zero.' These fea·
tures are built into the LM2907.
Applications 'for the device range from, simple speed switCh
for anti'pollution control device functions in automobiles, to
motor speed controls in industrial applications. The applica'
tions circuits which follow are designed to illustrate some of
the capabilities of the LM2907. In most' cases,' altarmitiile
input or output configurations can be mixed and matched at
will and other variations can be determined from the description in Part I of this application note. For complete
specifications, refer to the data sheet:
Temperature J:tanges and Packaging conSld~ratlons
The LM2907, LM2917 ~riesdevices are specified for oper·
ation over the temperature range -40"C to +85°C.
The devices are normally packaged in molded epoxy, dual·
in·line packages. Other temperature ranges and other pack·
ages are availabe to special order. For reliability require.
ments beyond those of normal commercial application
where the cost of military qualification is not bearable" other
programs are available such as B + .
Speed Switches
PART II-APPLICATIONS
Perhaps the most natural application of the LM2907 is in
interfacing with magnetic pickups, such as the one iIIustrat·
ed in Figure 8 to perform speed switching functions. AS'an
example, New York taxies are required to change the inten·
sity of the warning horn above and below 45 mph. Other
examples include an over·speed warning, where a driver
may set the desired maximum speed and have an audible
INTRODUCTION
The LM 2907, LM2917 series devices were designed not
only to perform the basic frequency to voltage function reo
quired in many systems, but also to provide the input and
output interface so often needed, so that low cost imple·
mentations of complete functions are available.
"
PERMANENT MAGNET
o
TL/H17451-23
FIGURE 8. Typical Magnetic Pickup
RZ
1l1li
Rl
10k
FULL·SCALE FREQUENCY (Hz!
10 kHz
10
..
...
I kHz
~ 1.0
Rl'=SI..
...
z
~
..
D.I'
I=;:
~
I
0.01
0.001 V
100".
MAGNETIC
PICK·UP
-
100Hz
SOOk
lOOk.
200k I IV i7"
[;i>'" V
//
I/' I/'
./ /'
"1M
10Hz
t':,'
7
,
./
/' /'
Ims
10m.
lOOms
FUll-SCALE TIME PERIOD
TlIH17451-25
TL/H17451-24
FIGURE 9. Simple Speed Switch Load Is Energized
1
when fiN> 2C1R1
FIGURE 10. RC Selection Chart
352
the output current is conducted along the supply line so that
a local current sensing device in the supply line can be used
to get a direct reading of the frequency at the remote location where the electronics may also be situated. The small
zero speed offset due to the device quiescent current may
be compensated by offsetting the zero on the display device. This also permits one display device to be shared between several inputs.
or visual warning of speeds in excess of that level. Many
anti-pollution devices included on several recent automobile
models have included a speed switch to disable the vacuum
advance function until a certain speed is attained2. A circuit
which will perform these kind of functions is shown in Figure
9. A typical magnetic pickup for automotive applications will
provide a thousand pulses per mile so that at 60' mph the
incoming frequency will be 16.6 Hz. If the reference level on
the comparator is set by two equal resistors R1 and R2 then
the desired value of C1 and R1 can be determined from the
simple relationship:
V~c =
v+
RS
Vee. C1 • R1 • f.
C1R1f = 0.5
or
and hence
C1R,1 = 0.03
From the RC selection chart in Figure 10 we can choose
suitable values for R1 and C1. Examples are 100 kO and
0.3 p.F. The circuit will then switch at approximately 60 mph
with the stated input frequency relationship to speed. To
determine the ripple voltage refer back to the equation for
ripple voltage (under "Choosing R1, C1 and C2"). From this
we can determine that there will be about 10 mV of ripple at
the switching level. To prevent this from causing chattering
of the load a certain amount of hysteresis is added by including R3. This will provide typically 1 % of supply as a
hysteresis or 1.2 mph in the example. Note that since the
reference to the comparator is a function of supply voltage
as is the output from the charge pump there is no need to
regulate the power supply. The frequency at which switching occurs is independeDt of supply voltage.
.....- -...-.VO
TUH17451-26
In some industrial applications it is useful to have an indication of past speed excesses, for example in notifying the
need for checking of bearings. The lM2907 can be made to
latch until the power supply is turned "OFF" in the case
where the frequency exceeds a certain limit, by simply connecting the output tranSistor emitter back to the non-inverting input of the comparator as shown in Figure 11. It can
also serve to shut off a tape recorder or editing machine at
the end of a rewind cycle. When the speed suddenly increases, the device will sense the condition and shut down
the motor.
Vo
t
'IN
SETPOINT
TLlH17451-27
Vo
~ FINV + Rl Cl
SETPOINT ~ V
Analog Displays
+
RD
RS
+
}
RA
Latchup occurs when
RS
1
FIN ~ RA + RS R1 C1
Indepandent of V + I
The lM2907, lM2917 series devices are particularly useful
for analog display of frequency inputs. In situations where
the display device is a moving coil instrument the advantages of the uncommitted output transistor can be realized
by providing a current drive to the meter. This avoids temperature tracking problems with the varying meter resistance and enables high resistance instruments to be driven
accurately with relatively large voltages as illustrated in Figure 12. The lM2917 version is employed here to provide a
regulated current to the instrument. The onboard 7.6V zener
is compatible with car and boat batteries and enables the
moving coil instrument to employ the full battery voltage for
its deflection. This enables high torque meters to be used.
This is particularly useful in high vibration environments
such as boats and motorcycles. In the case of boats, the
most common speed pickup for the knot meter employs a
rotating propeller driving a magnetic pickup device. Meteorologists employ a large number of anemometer~ for measuring wind velocities and these are frequently coupled by a
magnetic pickup. In examples like these, where there is frequently a large distance between the display device and the
sensor, the configuration of Figure 13 can be usefully employed to cut down on the number of wires needed. Here
FIGURE 11. Overspeed Latch
CAL.
AOJUST
RZ
TUH17451-28
FIGURE 12. Analog Display of Frequency
353
»
z
.....•
~
Automotive Tachometer
Not all inputs are derived from variable reluctance magnetic
pickups; for example. in spark ignition engines the tachometer is generally driven from the spark coil. An inte~ace circuit for this situation is shown in Figure 14. This tachometer
can be set up for any number of 'cylinders by linking the
appropriate timing resistor as illustrated. A 5000 trim resistor can be used to set up final calibration. A protection circuit composed of a 100 resistor and a zener diode is also
shown as a safety precaution against the transients which
are to be found in automobiles:
'
10
-
O---TOOTHER
rll~o--SENSORS
Motor Speed Controls
DC motors with or without brushes can be purchased with
ac tachometer outputs already provided by the manufacturerS. With these motors in combination with the
1.110
~ 1.008
GO
FREQUENCY· 2110 Hz
1.008
-- ...
~ 1.004
[11m
GI.DOD
TLlHI7451-29
.=....
;!: OJaR
........
_I LM2917(4700)
:::;0J84
I
I
10.112
'"o.no
-3& -1&
&
LM2I07
"
/
21
4&
I'..
II
II
TEMPERATUftE rC)
10
TL/HI7461-32
FIGURE 15. Normalized Tachometer
Output vs. Temperature
TUH17451-30
FIGURE 13. Two Wire Remote Speed Sensor
II-MV
PROTECTION
ZENER'
10
'=' 4Cyt • CYL
LlIKTO
SELECT
1110. OF
CYLINDERS
Y
acYL
'='
TL/HI7461-31
FIGURE 14. Gasoline Engine Tachometer
354
LM2907, a very low cost speed control can be constructed.
In Figure 16 the most simple version Is illustrated where the
tachometer drives the non-inverting input of the comparator
up towards the preset reference level. When that level is
reached, the output is turned off and the power is removed
from the motor. As the motor slows down, the voltage from
the charge pump output falls and power is restored. Thus
speed is maintained by operating the motor in a switching
mode. Hysteresis can be provided to control the rate of
switching. An alternative approach which gives proportional
control is shown in Figure 17. Here the charge pump integrator is shown in a feedback connection around the operational amplifier. The output voltage for zero speed is equal
to the reference voltage set up on the potentiometer on
the non-inverting input. As speed increases,the charge
pump puts charge into capacitor C2 and ~uses the output
Your to fall in proportion to speed. The output current of the
op amp transistor is used to provide an analog drive to the
motor. Thus as the motor speed approac;hes the reference
levef, the current is proportionately reduced to the motor so
that the motor gradually comes up to, speed and is maintained without operating the motor in ,a switching mode. This
is particularly useful in situations where the electrical noise
generated by the switching mode operation is objectionable.
This circuit has one primary disadvantage in that it has poor
load regulation. A third configuration is shown in Figure 18.
This employs an LM2907-8 acting as a shunt mode regulator. It also features an LED to indicate when the device is in
regulation.
r-----~----~-<>v+
TL/HI7451-33
FIGURE 16. Motor Speed Control
r-----.-------~-ov+
TL/HI7451-34
FIGURE 17. Motor Speed Control with Proportional Drive
355
...
~
:i:
c,
The output of the tachometer is proportional to the product
of supply voltage, input frequency, a capacitor and a resistor. Anyone of these may be used as the input variable or
they may be used in'combination to produce multiplication.
An example of a capacitive transducer is illustrated in Figure
20, where a fixed 'input frequency is employed either from
the 60 Hz line as a convenient source or from a stable oscillator. The capaCitor is a variable element mechanically coupled· to the system whose position is to be sensed. The
output is proportional to the capacitance value, which can
be arranged to have any desired relationship to the mechanical input by suitable shaping of the capacitor electrodes.
Position Sensing
In addition to their use to complete tachometer feedback
loops, used in position transducer circuitS, the LM2907,
LM2917 devic~s can also beu8ed as Position transducers.
For example, the timing resistor can be removed from pin 3
so that the output current produces a staircase instead of a
fixed dc level. If the magnetic pickup senses passing notches or items, a staircase signal is generated which can then
be compared with a reference to initiate a switching action
when a specified count is reached. For example, Figure 19
shows a circuit which will count up a hundred input pulses
and then switch on the output stage. Examples of this application can be found in automated packaging operations or
in line printers.
r-____~--------__-4~OV+
(U-ZlVI
TLlHf7451-35
FIGURE 18. Motor Speed Control
Vcc
..---oIC
V3
Ie
100
TL/Hf7451-36
NO.
OF CYCLES
TLlHf7451-37
FIGURE 19. Staircase Counter
356
Soak
L..--4.....-0VOUT - C1
-
TLlH/7451-38
FIGURE 20. Capacitive Transducer
Analog Systems Building Block
The linearity of voltage controlled oscillators can be improved by employing the LM2907 as a feedback control element converting the frequency back to voltage and comparing with the input voltage. This can often be a lower cost
solution to linearizing the veo than by working directly on
the veo itself in the open loop mode. The arrangement is
illustrated in Figure 22.
The LM2907, LM2917 series characterize systems building
block applications by the feature that the output from the
device is proportional only to externally programmed inputs.
Any or all of these inputs may be controlled inputs to provide the deSired output. For example, in Figure 20 the capaCitance transducer can be operated as a multiplier. In
flow measurement indicators, the input frequency can be a
variable depending on the flow rate, such as a Signal generated from a paddle wheel, propeller or vortex sensor4. The
capaCitor can be an indication of orifice size or aperture
size, such as in a throttle body. The product of these two will
indicate volume flow. A thermistor could be added to R1 to
convert the volume flow to mass flow. So a combination of
these inputs, including control voltage on the supply, can be
used to provide complex multiplicative analog functions with
independent control of the variables.
Phase-locked loops (PLL) are popular today now that low
cost monolithic implementations are available off the shelf.
One of their limitations is the narrow capture range and
hold-in range. The LM2907 can be employed as a PLL helper. The configuration is l?hown in Figure 21. The LM2907
here serves the function of a frequency-to-voltage converter
which puts the veo initially at approximately the right frequency to match the input frequency. The phase detector is
then used to close the gap between veo and input frequency by exerting a control on the summing point. In this way,
given proper tracking between the frequency-to-voltage
converter and the veo, (which is a voltage-ta-frequency
converter), a wide-range phase loop can be developed.
-----+1
'IN 0-...
'OUT
'-+---1
VCONTRDL
TL/HI7451-40
FIGURE 22. Feedback Controlled VCO
Digital Interface
A growing proportion of the complex control systems today
are being controlled by microprocessors and other digital
devices. Frequently they require inputs to indicate position
or time from some mechanical input. The LM2907 can be
used to provide zero crossing datum to a digital system using the circuits illustrated in Figure 23. At each zero crossing
of the input signal the charge pump changes the state of
capaCitor e1 and provides a one-shot pulse into the zener
diode at pin 3. The width of this pulse is controlled by the
internal current of pin 2 and the size of capaCitor C1 as well
as by the supply voltage. Since a pulse is generated by each
zero crossing of the input signal we call this a "two-shot"
instead of a "one-shot" device and this can be used for
doubling the frequency that is presented to the microprocessor control system. If frequency doubling is not required
and a square wave output is preferred, the circuit of Figure
24 can be employed. In this case, the output swing is the
same as the swing on pin 2 which is a swing of half supply
voltage starting at 1 VeE below one quarter of supply and
going to 1 VeE below three-quarters of supply. This can be
increased up to the full output swing capability by reducing
or removing the negative feedback around the op amp.
. . . . . . . . 'OUT
TLlH/7451-39
FIGURE 21. Phase-Locked Loop Helper
Added f to V Greatly Increases Capture and Hold Range
357
N
....
~
'CD
r---------------------------------------------------------------------------------,
The staircase generator shown in Figure 19 can be used as
an A-O converter. A suitable configuration is shown in Figure 25. To start a convert cycle the processor generates a
reset pulse to discharge the integrating capacitor C2. Each
complete clock cycle generates a charge and discharge cycle on C1. This results in two steps per cycle being added to
C2. As the voltage on C2 increases, clock pulses are re-
turned to the processor. When the voltage on C2 steps
above the analog input voltage the data line is clamped and
C2 ceases to charge. The processor, by counting the number of clock pulses received after the reset pulse, is thus
loaded with a digital measure of the input voltage. By making C2/C1 = 1024 an 8-bit A-O is obtained.
p'
VCC
YIN~
•
I
YTH-
VARIABLE
RELUCTANCE
MAGNETIC
PICKUP
n n"
L.+~--+-=----1I-::---+_:_'
1
fo) ...1--.........J
~
-
Input can be ±20 mV to ±28V
. .-
VIN
. . . . VOUT
TUHI7451-42
Pulse width
10k
-
= vee x ~
2
12
TUHI7451-41
OutpUt frequency equal twice Input frequency.
Pulse width
= Vee x ~
2
12
Pulse height
= VZENER
FIGURE 23. "Two-Shot" Zero Crossing Detector
VCC
\
"---"YOUT
;-
~~I
TUHI7451-44
TUHI7451-43
FIGURE 24. Zero Crossing Detector and Line Drivers
ANALOG VOLTAGE
INPUT VA
CLOCK
CLOCK
DATA
RESET
DIGITAL
PROCESSOR
1f1flMnflIll1Il
-11_________
RESET
DATA
...IlI111JUL-
-
• PULSES
TUHI7451-45
FIGURE 25. A-D Converter
358
TL/HI7451-46
amp/comparator is connected with negative feedback with
a diode in the loop so that the amplifier can only pull down
on the load and not pull up. In this way, the outputs from the
two devices can be joined together and the output will be
the lower of the two input speeds. In Figure 27 the output
emitter of the onboard op amp provides the pullup required
to provide a. select-high situation where the output is equal
to the higher of two speeds. The select average circuit in
Figure 28 saves components by allowing the two charge
pumps to operate into a single RC network. One of the amplifiers is needed then to buffer the output and provide a low
impedance output which is the average of the two input frequencies. The second amplifier is available for other applications.
Antl-stdd Circuit Functions
Motor Vehicle Standards 121 place certain stopping requirements on heavy vehicles which require the use of electronic
anti-skid control devices. 5 These devices generally use variable reluctance magnetic pickup sensors on the wheels to
provide inputs to a control module. One of the questions
which the systems deSigner must answer is whether to use
the average from each of the two wheels on a given axle or
to use the lower of the two speeds or to use the higher of
the two speeds. Each of the three functions can be generated by a single pair of LM2907-8 as illustrated in Figures 2628. In Figure 26 the input frequency from each wheel sensor
is converted to a voltage in the normal manner. The op
vcco-------------------------.-----------------------------,
WHEEL INPUT
NO.1
0--------------+-----.. . .
WHEEL INPUT o-----~I_-~
NO.2
RLOAD
1k
1k
TLlH/7451-47
VOUT is proportional to the lower of the
two input wheel speeds
WHEEL SPEED
Tl/HI7451-48
FIGURE 26. "Select-Low" Circuit
359
vcc~--------------------------~------------------------~~~~
'WIIEEL INPUT
NO.1
WIIEEL INPUT
NO.2
0-------""'---"""---+------"""",,
.',
~------t_-...,
T
'::' 10k -
~-Jvv~~~------------~----------~~------------.+
VOUT .
.
-!-~
TLIHI7451-49
VOUT
VOUT is proportional to the" higher of the
two input wheel Speeds ,
WHEEL SPEED
TLIHI7451-50
FIGURE 27. "Select-High" Circuit
VCCo-----------------------~~--------------------------__,
110------------+----__,
12 o----~-....,
R
+ ~----------.....
VOUT·
VCCRC(II +121
TLlH17451-51
FIGURE 28. "Select-Average" Circuit
360
".
.----------------------------------------------------------------..
Transmission and Clutch Control Functions
CONCLUSION
....z•
Electric clutches can be added to automotive transmissions
The applications' presented in this note indicate that the
G)
LM2907, LM2917 series devices offer a wide variety of uses
ranging from very simple low cost frequency to voltage conversion to complex systems building blocks. It is hoped that
the ideas contained here have given suggestions which may
help provide new solutions to old problems. Additional applications ideas are included in the data sheet, which should
be referred to for all speCifications and characteristics.
to eliminate the 6% slip which typically occurs during cruise
and which ~esults in a 6% loss in fuel economy. These devices could be operated by a pair of LM2907's as illustrated
in Figure 29. Magnetic pickups are connected to input and
output shafts of the transmission respectively and provide
frequency inputs fl and f 2 to the circuit. Frequency, f2' being the output shaft speed, is also a measure of vehicle road
speed. Thus the LM2907-8 No.2 provides a voltage proportional to road speed at pin 3. This is buffered by the op amp
in LM2907-8 No.1 to provide a speed output VOUT1 on pin
4. The input shaft provides charge pulses at the rate of 2f1
into the inverting node of op amp 2. This node has the integrating network R 1, C3 going back to the output of the op
amp so that the charge pulses are integrated an(j provide
an inverted output voltage proportional to the input speed.
Thus the output VOUT2 is proportional to the difference between the two input frequencies. With these two signalsthe road speed and the difference between road speed and
input shaft speed-it is possible to develop a number of
control functions including the electroniC clutch and a complete electronic transmission control. (In the configuration
shown, it is not possible for VOUT2 to go below zero so that
there is a limitation to the output swing in this direction. This
may be overcome by returning R3 to a negative bias supply
instead of to ground.)
OUTPUT
SHAFT
REFERENCES
1. Sociey of Automotive Engineers: Preliminary Recommended Environmental Practices for Electronic Equipment Design. October 1974.
2. See for example: Pollution Control Installers HandbookCalifornia Bureau of Automotive Repair No. BAR H-OOI §
5.5.4 NOX control systems.
3. TRW Globe Motors, 2275 Stanley Avenue, Dayton, Ohio
45404.
4. S.A.E. Paper"" 760018 Air Flow Measurement for Engine
Control-Robert D. Joy.
5. Code of Federal Regulations. Title 49 Transportation;
Chapter V-National Highway Traffic Safety Administration, Dept. of Transportation; Part 571-Federal Motor
Vehicle Safety Standards; Standard No. 12~.
INPUT
SHAFT .
LM2101-8 #2
LMZ801-8 #1
r-1~OV-
f1
I
I'
Cl
~
C3
Rl
+
R3
L-------------~------------~--_<)VCC
VOUTZ
R4
VOUT1
VOUT2
= Vee C2 A2 12
= Vee (C2 A2f2 - Cl AI
N
VOUTI
11)
TL/H/7451-52
FIGURE 29_ Transmission or Clutch Control Functions
361
~
'7
z
c(
Ie Zener Eases Reference
Design
DESCRIPTION
A new IC zener with low dynamic impedance and wide operating current range significantly simplifies reference or regulator circuit design. The low dynamic impedance provides
better regulation against operating current 'changes, easing
the requirements of the biasing'supply. Further, the temperature coefficient is independent of operating current, so that
the' LM129 can be used at any convenient current level.
Other characteristics such as temperature coefficient, noise
and long term stability are equal to or better than good quality discrete zeners.
The LM129 uses a new subsurface breakdown IC zener
combined with a buffer circuit to lower dynamic impedance.
The new subsurface zener has low noise and excellent long
term stability since the breakdown is in the bulk of the silicon. Circuitry around the zener supplies internal biasing currents and buffers external current changes from the zener.
The overall breakdown is about 6.9V with devices selected
for temperature coefficients.
The zener is relatively straightforward. A buried zener 01
breaks down biasing the base of transistor 01. Transistor
01 drives two buffers 02 a:nd 03. External current changes
through the circuit are fully absorbed by the buffer transistors rather than by 01. Current through 01 is held constant
at 250 /LA by a 2k resistor across the emitter base of 01
while the emitter-base voltage of 01 nominally temperature
compensates the reference voltage.
National Semiconductor
Application Note 173
The other, components, 04, 05 and as, set the operating
current of 01. Frequency compensation is accomplished
with two junction capacitors.
All that is needed for biasing In most applications'is a resistor as shown in Figuf9 2. Biesing current can be anywhere
from 0.6 mA to 15 mA with little change in performance.
Optimally, however, the biasing current should be as low as
possible for the best regulation. The dynamic'impedance of
the LM129 is about 1 {} and is independent of current.
Therefore, the regulation of the LM 129 against voltage
changes is 1/Rs.
Lower currents or higher Rs give better regulation. For example, with a 15V supply and 1 mA operating current, the
reference change for a 10% change in the 15V supply is
1BO /LV. If the LM129 is run at 5 mA, the change is 900 /LV
or 5 times worse. By comparison, a standard, I,NB21 zener
will change about 17 mV. All discrete zeners have about the
same regulation since their dynamic impedance' is inversely
proportional to operating current.
If the zener does not have to be grounded, a bridge compensating circuit can be used to get virtually perfect regulation, as shown in Figuf9 3. A small compensating voltage is
generated across R1, which matches the dynamic impedance of the LM129. Since the dynamic impedance of the
LM129 is linear with current, this circuit will work even with
large changes in the unregulated input voltage.
01
V+
uv
~. ,~
~
TL/H/5614-1
FIGURE 1_IC Reference Zener
FIGURE 2. BasiC Biasing
362
Other output voltages are easily obtained with the simple
op-amp circuit shown in Fl{Jure 4. A simple non-inverting
amplifier is used to boost and buffer the zener to 10V. The
reference is run directly from the input power, rather than the
output of the op-amp. When the zener is powered ,from the
op-amp,. special starting circuitry is sometimes n~ary to
insure the output comes up in the, right polarity•. For outputs
lower than lhe breakdown of the LM129 a divider can bl!
connected across the zener to drive the op-amp.
An AC square wave or bipolarity output reference can easily
be made with an op-amp andFET switch as shown in Figure
5. When 01 is "ON", the LM108 functions as a normal inverting op-amp with a gain of -1 and an output of -6.9V.
With 01 "OFF" the op-amp acts as a giving 6.9 V at the
output. Some non-symmetry will occur from loading change
on the LM129 in the different states and mismatch of R1
and R2. Trimming either R1 or R2 can make the output
exactly symmetrical around ground.
V.--....---.,
>"'---IDV
VOUT
FIGURE 4. 10 Volt Buffered Output Reference
FIGURE 3. Bridge Compensation for Line Changes
15V
t-"....- -...- - OUTPUT IOV
HZ
lOOk
TLlH/5614-2
FIGURE 6. High Stability 10 V Regulator
FIGURE 5. Bipolar Output Reference
363
~•
....
.....
w
By combining theLM129 With an LM1'17 three-terminal regulator a high. stability power' regulator can be made. This' is
shown in F/gUfB 6. ResistorR1 biases the LM-1'29 at about 1
mA-from thel,25V reference in the1.Ml17. The voltage of
the LM129 is 'added to,the 1;25V ofthetM1 17 to make a
total reference voltage of B.W. The; output voltage is then
set at 10V by R2 and R3:Since the,internal refllrence'Of the
LMl17 contributes only about 200/0 ,of the total reference
voltage, regulation and drift are essentially thosEl of the external zener. The regulator has 0.20/0 load and line regulation and if a low drift zener such as the LM129A is used
overall temperature coefficient is less than 0.0020/0/oC.
The new zener can bEl used as the reference far conventional IC voltage regulators for entlanced performance.
Noise is lower, time stability is better, and temperature coefficient can be better depending on the device selElcted. Further, the output voltage is independent of power chllnges in
the regulator.
.'
Figure 7 shows an LM723 using an external LM129 reference. The internal 7V reference is riot used and a single
resistor biases the LM129 as the refe(ence. The 5k resistor
chosen provides sufficient operating current for the zener
over the 10V to 40V input voltage range of the LM723.
Since the dynamic impedance of the LM129 is so low, the
reference regulation against line phanges is onlyO.020/01V.
This is small compared to the regulation of 0.1 O/ON for the
LM723; however, the resistor can be replaced by almA to
5 mA FET used as a constant current source for improved
regulation. When the FET is used reference regulation is
easily 0.001 O/ON. Output voltage is set in the standard man·
ner except that. for low outp\:rt voltages sufficient current
must be run through the zener to power the voltage divider
supplying the rEJferenceto the LM723.
Ah oiIertoad protecte'tl' pbwEir'shunt regulator is shown in
F"1flur8 0: ThEloutPut voltage is about 1.BV - the 7V breakdown' of the LM129 plus the O.BV emitter-baae iioltage of
the LM395.The LM395 is an IC, 1.5 A power transistor With
complete overload protection on the chip. Included on the
chip are current limiting and thermal limiting, making the davice virtually blowout-proof. Further, the base current is only
5 p.A, making it easy to drive as a shunt regulator. As the
input voltage riseS, more drive is applied to the base of the
LM395, turning it on harder and, dropping more voltage accross the series resistance. Should. the input voltage rise
too high, the LM395 will current limit or thermal I.imit, protecting itself.
The new IC zeiler can .rep!ace existing. zeners in just about
any application with improved performance and simpler external circuitry. As with any zener reference, devices are
selected for temperature coefficient and operating temperature range. Since the devices are made by a standard integrated circuit process, cost is low and good reproducibility is
obtai.ned in volume production. •
Finally, since the device is actually an IC, it is packaged in a
rugged T0-46 metal can package or a 3-lead plastiC transistor package.
V+
Ik
LM723
.......-oM_....
VIN
1011
--'VI/Ir-....- - -....---VOUT
-VOUT
LMIZI
+-----INI
v-
RI
LM1Zt
, ,
!aD
TLlH/5614-3
FIGURE 7. External Reference For Ie
FIGURE 8. Power Shunt Regulator
364
~---------------------------------------------------------------.~
~~
Applications for an
Adjustable Ie Power
Regulator
National Semiconductor
Application Note 178
A new 3-terminal adjustable IC power regulator solves many
of the problems associated with older, fixed regulators. The
LM117, a 1.5A IC regulator is adjustable from 1.2V to 40V
with only 2 external resistors. Further, improvements are
made in performance over older regulators. Load and line
regulation are a factor of 10 better than previous regulators.
Input voltage range is increased to 40V and output characteristics are fully specified for load of 1.5A. Reliability is improved by new overload protection circuitry as well as 100%
bum-in of all parts. The table below summarizes the typical
performance of the LM117.
+ 1500C temperature range, the current limit only shifts
about 10"10.
TABLE I
Since the LM117 is a floating voltage regulator, it sees only
the input-to-output voltage differential. This is of benefit, especiallyat high output voltage. For example, a 30V regulator
nominally operating with a 3BV input can have 70V input
transient before the 40V input-to-output rating of the LM117
is exceeded.
Output Voltage Range
1.25V-40V
0.01 "ioN
Line Regulation
Load Regulati<;>n IL = 1.5A
0.1"10
Reference Voltage
1.25V
Adjustment Pin Currrent
Minimum Load Current (QUiescent Current)
50llA
3.5 rnA
0.01 "Iorc
Temperature Stability
2.2A
Current Limit
Ripple Rejection
BOdS
The overload protection circuitry on the LM117 includes current limiting, safe-area protection for the internal power transistor and thermal limiting. The current limit is set at 2.2A
and, unlike presently available positive regulators, remains
relatively constant with temperature. Over a - 55°C to
At high input-to-output voltage differentials the safe-area
protection decreases the current limit. With the LM 117, full
output current is available to 15V differential and, even at
40V, about 400 rnA is available. With some regulators, the
output will shut completely off when the input-to-output differential goes above 30V, possibly causing start-up problems. Finally, the thermal limiting is always active and will
protect the device even if the adjustment terminal should
become aCCidentally disconnected.
BASIC OPERATION
The operation of how a 3-terminal regulator is adjusted can
be easily understood by referring to Fl{Jure 1, which shows a
functional circuit. An op amp, connected as a unity gain
buffer, drives a power Darlington. The op amp and biasing
circuitry for the regulator is arranged so that all the quiescent current is delivered to the regulator output (rather than
ground) eliminating the need for a separate ground terminal.
Further, all the cirCUitry is designed to operate over the 2V
to 40V input-to-output differential of the regulator.
INPUT
0.2
OUTPUT
TLlHI7334-1
FIGURE 1. Functional Schematic of the LM117
365
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!
II
I
:e
....
A 'l.2V reference voltage appears, inSElrted between the
z,non-inverting input of the op amp and the adjustment termic(
,nal. ~bout 50 /LA is needed to bias the reference and this
";\\\,Irrept comes ,out of the adjustment terminal. In operation,
the output of the regulator is the voltage of the adjustment
terminal plus 1.2V. If the adjustment terminal is grounded,
the device acts as a 1.2V regulator. For higher output voltages, a divider R1 and R2 is connected from the output to
ground 'as Is shown in Figure 2. The 1.2V reference across
resistor R1 forces 10 mA of current to flow. This 10 mA then
flows through'R2, increasing the voltage at the adjustment
terminal and therefore the output ,\loltage. The output voltage is given by,:,
, X (R
VOUT = 1.2V
1 +2
R1 )
The program~ing curr!:lFt is constan, andean be used to
bias other circuitry, While the regulator is used as the' power
supply for the ily~tpm:"n Fffiure 3, the,LMl17 is ~S$d as a
15V regulator while the programming current 'powerS an
LM127 zener reference. The LM129 is an lG,zener with less
than 10 dynamic impedance and can operate over II range
of 0.5 mA to 15 mA with virtually no change in performance.
Another example of using the programming current is
shown in Figure 4 where the' output' setting resistor is
tapped to provide multiple outpUt voltage to opeamp'buffers.
An additional transistor is included as part cif the :overtoad
protection. When any
the' outputs are shorted, the op
amp will current limit and a voltage will be developed across
its inputs. Thf~,
turn "ON" the transistor and pull down
the adjustment terminal of the LMl17, causing all outputs to
decrease, minimizing possible damage to the rest of the
circllitry.
'
''
of
will
+ 50 p.A R2"
The 5<1 /LA biasinQ,c4rrent is small compared to ,5 mA and
causes only a small error in actual, output voltages. Further,
it is extremely well regulated agalnst line voltage or load
current changes so that it contributes virtually no error to
dynamic regulatiO'n. Of course, programming currents other
than 10 mA can be uSed depending upon the application.
Sirce the regulator is floatin\l, aU the quiescent curren( must
be absorbed by the load. With too light of a load, regulation
is impaired. Usually, a 5 mA programming current is sufficient; however, worst case minimum load for commercial
grade parts requires a minimum load of 10 mA. The minimum load cl.\rren! can be compared to the quiescent current
of standard regulators.
'APPLICATIONS'
An adj~stable lali regulator using, the LMl17 is shown in
Figure 2 and has at.2V to 25V' output range. A 10 mA
program current is set'by R1 while the oUtput voltage is set
by R2. Capacitor C1 is optional to' improve ripple rejeqtlon
so that a<1, dB is obtained at any output voltage~ The ctiode,
although not necessary iri this circuit Since the output is
limited to 25V, is needed with outputs over 25V to protect
against the capacitors discharging through low current
, nodes in the LMl17 when the input or output is shorted.
, , Ordinary 3-terminal regulators are not eSPiSlcially attra9lfve
for use as precision current regulators. Firstly, the quiescent
current can be as high as 10 mA, giving at least 1% error at
1A output currents, and more error at lower currents. Secondly, at least 7V is needed to operate the device. With the
LM 117, the only error current is 50 p.A from the adjustment
terminal, and only 4.2V is needed for operation at 1.5A or
3.2V at 0.5A. A simple 2-terminal current regulator is shown
in Figure 5 and is usable anywhere from 10 mA t9 1.5A.
Figure 6 shows, an adjustable current regula~o~ in ,cOnjunction with the voltage regulator from Figure 2 to make constant voltage/constant current ,'lab-type supply. Current
sensing is done across R1, a 10 resistor, while R2 sets the
, current limit point. When the wiper of R2 is connected, the
10 sense, resistor current is regulated at 1.2A. As R2 is
adjusted, a portion of the 1.'2V reference of the LM 117 is
cancelled by the drop across the pot, decreasing the current
limit point. At low output currentS, current regulation is degraded since the voltage across thai 0 sensing'resistor
, becomes quite low. Forexample, witti' 50 mA output current,
only 50 mV is dropped across the sense resistor and the
supply rejection of the LM 117 will limit the current regulation
.......- - 4 - VOUT
01
lN40D2
Tl/HI7334-2
Tl/HI7S34-3
FIGURE 3_ 'Regulator and Voltage Reference
FIGURE 2. Basic Voltage Regulator
366
.--------------------------------------------------------------------.~
off the 10 mA is an LM10B and an LM129 zener. The zener
provides a common-mode voltage for operation of the
LM108 as well as a 6.9V reference, if needed. Input signals
are impressed across R3, and the curent through R3 is delivered to the output of the regulator by 01 and 02. For a
250 resistor, this gives a 40 mA current change for a 1V
input. This circuit can be used in 4 mA to 20 mA applications, but the LM 117 must be selected for low quiescent
current. Minimum operating voltage is about 12V.
to about 3% for a 40V change across the device. An alternate current regulator is shown in Figure 7 using an additional LM 117 to provide the reference, rather than an
LM113 diode. Both current regulators need a negative supply to operate down to ground.
Figure 8 shows a 2-wire current transmitter with 10 mA to
50 mA output current for a 1V input. An LM117 is biased as
a 10 mA current source to set the minimum current and
provide operating current for the control circuitry. Operating
V,N
~__----------------~------~--------~---------15V
Rl
120
R2
3811
>~-+-----_ll1V
R3
500
5V
R4
5011
TLlHI7334-4
FIGURE 4. Regulator with Multiple Outputs
I
OUT
1.25V
="""ii1
10 mA ,s; lOUT ,s; 1.5A
TL/H17334-5
FIGURE 5. 2-Termlnal Current Regulator
....~--~~ ~.V8lo 25V
i.-....,;-'-....II
02
lN4002
R4
3k
TLlH/7334-6
FIGURE 6. AdJustable Regulator. Constant Voltage/Constant Current, 10 mA to 1.2A
367
....~
c;:
=r-------------------------------------------------------------------------,
.....
-~
LM117
V-5VTO -IOV
TL/HI7334-7 .
FIGURE 7. Adjustable Current Regulator
+
+
VIN ~ISV
SINK CURRENT
10TO SOmA
R3
25
1%
DI
6.BV
IW
TL/HI7334-8
FIGURE 8. 10 mA to 50 mA 2-Wlre Current Transmitter
388
......$
National Semiconductor
Application Note 181
3·Terminal Regulator
is Adjustable
CD
INTRODUCTION
Until now, all of the 3-terminal power Ie voltage regulators
have a fixed output voltage. In spite of this limitation, their
ease of use, low cost, and full on-chip overload protection
.have generated wide acceptance. Now, with the introduction of the LM117, it is possible to use a single regulator for
any output voltage from 1.2V to 37V at 1.5A. Selecting
close-tolerance output voltage parts or designing discrete
regulators for particular applications is no longer necessary
since the output voltage can be adjusted. Further, only one
regulator type need be stocked for a wide range of applications. Additionally, an adjustable regulator is more versatile,
lending itself to many applications not suitable for fixed output devices.
In addition to adjustability, the new regulator features performance a factor of 10 better than fixed output regulators.
Line regulation is o.ot %N and load regulation is only 0.1 %.
It is packaged in standard TO-3 transistor packages so that
heat sinking is easily accomplished with standard heat
sinks. Besides higher performance, overload protection circuitry is improved, increasing reliability.
ADJUSTABLE REGULATOR CIRCUIT
The adjustment of a 3-terminal regulator can be easily understood by referring to Figure 1, which shows a functional
circuit. An op amp, connected as a unity gain buffer, drives a
power Darlington. The op amp and biasing circuitry for the
regulator are arranged so that all the quiescent current is
delivered to the regulator output (rather than ground) eliminating the need for a separate ground terminal. Further, all
the circuitry is designed to operate over the 2V to 40V input
to output differential of the regulator.
A 1.2V reference voltage appears inserted between the
non-inverting input of the op amp and the adjustment terminal. About 50 /JoA is needed to bias the reference and this
current comes out of the adjustment terminal. In operation,
the output of the regulator is the voltage of the adjustment
terminal plus 1.2V. If the adjustment terminal is grounded,
the device acts as a 1.2V regulator. For higher output voltages, a divider R1 and R2 is connected from the output to
ground as is shown in Figure 2. The 1.2V reference across
resistor R1 forces 5 mA of current to flow. This 5 mA then
flows through R2, increasing the voltage at the adjustment
terminal and therefore the output voltage. The output voltage is given by:
VOUT = 1.2V (1
+ :~) + 50 IJoA R2
The 50 /JoA biasing current is small compared to 5 rnA and
causes only a small error in actual output voltages. Further,
it is extremely well regulated against line voltage or load
current changes so that is' contributes virtually no error to
dynamic regulation. Of course, programming currents other
than 5 mA can be used depending upon the application.
Since the regulator is floating, all the quiescent current must
be absorbed by the load. With too light of a load, regulation
is impaired. Usually the 5 mA programming current is sufficient; however, worst case minimum load for commercial
grade parts requires a, minimum load of 10 mA. The minimum load current can be compared to the quiescent current
of standard regulators.
Dl*
lN4002
t Solid tantalum
0.2
"Discharges Cl If output Is shorted to ground
ADJUSTMENT
OUTPUT
FIGURE 2. Adjustable Regulator with
Improved Ripple Rejection
TL/H/1532-1
FIGURE 1. Functional SchematiC of the LM117
369
TL/H/1532-2
~ r-------------------------------------------------------------------------~--------------~
co
....
~
diodes as discUSSlild later, to prevent the capacitor frOm discharging through internal low current paths in the LM117
and damaging the device. '
OVIi!RLOAD PROTECTION CIRCUITRY
'An important advancement in the LM117 is,improved cur, ,rent limit Circuitry. Current limit is set internally at about 2.2A
and the' ,current limit remains constant with temperature.
Older devices such as the LM309 or LM7800 regulators use
the turn-on of an emitter-base junction of a transistor to set
the current limit. This causes current limit to typically change
by a factor of 2 over a - 55·C to + 15O"C temperature
range. Further, to insure adequate output current at 150"C
the current limit is relatively high at 25·C, which can cause
problems by overloading the input supply.
Although the LM117 is stable with no output capaCitors, like
any feedback circuit, certain values of external capacitance
can cause excessive ringing. This occurs with values between 500 pF and 5000 pF. A 1 ",F solid tantalum (or 25 ",F
aluminum electrolytic)on the output swamps this effect and
insures stability. When ,external capaCitors are used with
any IC regulator, it is sometimes, necessary to add protection diodes to prevent the capaCitors from discharging
through low current points into the regulator. Most 10 ",F
capacitors have low enough internal series resistance to deliver 20A spikes when shorted. Although the surge is short,
there is enough energy to damage parts of the IC.
Also included is safe-area protection for the pass transistor
to decrease the current limit as input-ta-output voltage differential increases. The' safe area protection circuit in the
LM117 allows full output current at 15V differential and does
not allow the current limit to drop to zero at high input-tooutput differential voltages, thus preventing start up problems with high input voltages; Figure 3 compares the current
limit of the LM117 to an LM340 regulator.
When an output capaCitor is connected to a regulator and
the input is shorted, the output capaCitor will discharge into
the output of the regulator. The discharge current depends
on the value of the capaCitor, the output voltage ofthe regulator, and the rate of decrease of VIN. In the LM117, this
discharge path is through a large, junction that is abl!l to
sustain a 20A surge with no problem. This is not true of
, other types of positive regulators. For output capacitors of
25 ",F or less, there is no need to use diodes.
- - - POSITIVE REGULATOR
f - - LM117
... Tj =I-Sloe
I
_ --'
I I -
:::-~,
The bypass' capacitor on the adjustment terminal (C2) can
discharge through a low current junction. Discharge occurs
when either the input or output is shorted. Internal to the
LM117 is a 50n resistor which limits the peak discharge
current. No protection is needed for output voltages of 25V
and less than 10 ",F capacitance. F/{Jure 4 shows an LM117
with protection diodes inCluded for use with outputs greater
than 25V and high values of output capacitance.
~ ~~ k-- T,=2S"C
-, ...
'. ," ~"
T,-"I"I1"
~
'.
~
~:-
ZI
II
3D
40
INPUT.OUTPUT DIFFERENTIAL (VI
Dl
lN40DZ
TLlHII532-3
FIGURE 3_ Comparison of LM117 Current
Limit with Older Positive Regulator
Thermal overload protection, included on the chip, turns the
regulator OFF when the chip temperature exceeds about
170·C, preventing destruction due to excessive heating.
Previously, the thermal limit circuitry required about 7V to
operate. The LM117 has a new design that is operative
down to about 2V. Further, the thermal limit and current limit
circuitry in the LM117 are functional, even if the adjustment
terminal should be accidentally disconnected.,
~__--~----~,--VDUT
Cl
OPERATING THE LM117
The basic regulator connection for the LM117, as shown in
Figure 2, 'only requires the addition of 2 resistors and a standard input bypass capacitor. Resistor R2 sets the output
voltage while R1 provides the 5 mA programming current.
The 2 capacitors on the adjustment and output terminals
are optional for improved performance.
TLlH11532-4
VOUT - 1.25V (1
+~) +R2.IA~
01 protacts against Cl Vnput shorts)
D2 protacts against C2 (output shorts)
FIGURE 4. Regulator with Protection Diodes
Against CapaCitor Discharge
Bypassing the adjustment terminal to ground improves ripple rejection. This bypass capacitor prevents ripple from being amplified as the output voltage is increased. With a
10 ,..,F bypass capacitor, 80 dB ripple rejection is obtainable
at any output level. Increases over 10 ",F do not appreciably
improve the ripple rejection at 120 Hz. If a bypass capaCitor
is used, it is sometimes necessary to include protection
Some care should be taken in making connection to the
LM117 to achieve the best load regulation. Series resistance between the output of the regulator and programming
resistor R1 should be minimized. Any voltage drop due to
load current through this series resistance appears as a
change in the reference voltage and degrades regulation. If
possible, 2 wires should be connected to the output-1 for
load current and 1 for resistor R 1. The ground of R2 can
370
be returned near the ground of the load to provide remote
sensing and improve load regulation.
This can cause operating speed differences in digital circuitry, interfacing problems or decrease noise margins.
Figure 7 shows a method of adjusting multiple on-card regulators so that all outputs track within ± 100 mV. The adjustment terminals of all devices are tied together and a single
divider is used to set the outputs. Programming current is
set at 10 mA to minimize the effects of the 50 /LA biasing
current of the regulators and should further be increased if
many .LM117's are used. Diodes connected across each
regulator insure that all outputs will decrease if 1 regulator is
shorted.
Two terminal current regulators can be made with fixed-output regulators; however, their high output voltage and high
quiescent current limit their accuracy. With the LM117 as
shown in Figure 8, a high performance current source useful
from 10 mA to 1.5A can be made. Current regulation is typically 0.01 %IV even at low currents since the quiescent current does not cause an error. Minimum operating voltage is
less than 4V, so it is also useful as an in-line adjustable
current limiter for protection of other circuitry.
Low cost adjustable switching regulators can be made using
an LM317 as the control element. Figure 9 shows the simplest configuration. A power PNP is used as the switch driving an L-C filter. Positive feedback for hysteresis is applied
to the LM317 through R6. When the PNP switches, a small
square wave is generated across R5. This is level shifted
and applied to the adjustment terminal of the regulator by
R4 and C2, causing it to switch ON or OFF. Negative
APPLICATIONS
Figure 5 shows a OV to 25V general purpose lab supply.
Operatiqn of the LM317 down to OV output requires the
addition of a negative supply so that the adjustment terminal
can be driven to -1.2V. An LM329 6.9V reference is used
to provide a regulated -1.2V reference to the bottom of
adjustment pot R2. The LM329 is an IC zener which has
exceptionally low dynamic impedance so the negative supply need not be well regulated. Note that a 10 mA programming current is used since lab supplies are often used with
no-load, and the LM317 requires a worst-case minimum
load of 10 mAo
The. 1.2V minimum output of the LM117 makes it e~y to
design power supplies with electrical shut-clown. At 1.2V,
m?St circuits draw only a small fraction of their normal operating current. In Figure 6 a TTL input Signal causes Q1 to
ground the adjustment terminal decreasing the output to
1.2V. If true zero output is desired, the adjustment can be
driven to -1.2V; however, this does require a separate negative supply.
.
When fixed output voltage r'i'gulators are used as on-card
regulatQr for multiple cards, the normal output voltage tolerance of ±5% between regulators can cause as much as
10% difference in operating voltage between cards.
RI
120
1_2
+
f...4....~.... ~9UT
OUTPUT
L-...",.::....~
O-JOV
C2
D.1~F
I.
........JV.IA.-TTL
5&0
'Min output:::: 1.2V
TL/H/1532-6
-12VTO -Iav
FIGURE 6. SV Logic Regulator
with Electronic Shutdown'
TLlH/1532-5
FIGURE S. General Purpose 0-30V Power Supply
t-",-,,-VOUT
L--_~+-----'
____""'_. __ .__ __ +---1
'All outputs within ± 100 mV
tMinimum load -10 mA
TL/H/1532-7
FIGURE 7. Adjusting Multiple On-Card Regulators with Single Control'
371
_
CD
~
r-------------------------------------------------------------------------------~
12
........JVI""'....- lOUT = AI *
TlIHI1532-8
'O.81l ,;: Rl ,;: 1201l
FIGURE 8. Precision Current Umlter
feedback is taken from the output through R3, making the
circuit os<:illate. CapaCitor C3 acts as a speed·up, increasing
switching speed, while R2 limits the peak drive current to
01.
The circuit in Figure 9 provides no protection for 01 in case
ot an overload. A blow-out proof. switching regulator is
shown in Figure 10. The PNP transistor has been replaced
by a PNP-NPN combination with LM395's used as the NPN
transistors. The LM395 Is an IC which acts as an NPN transistor with overload protection: Included on the LM395 is
current limiting, safEHlrea protection and thermal overload
protection making the device virtually immune to any type of
overload.
Efficiency for the regulators ranges from 65% to 85%, de·
pending on output voltage. At low output' voltages, fixed
power losses are a greater percentage of the total output
power so efficiency is lowest. Operating frequency is about
30 kHz and ripple is about 150 mV, depending upon input
voltage. Load regulation is about 50 mV and line regulation
about 1% for a 10V input change.
One of, the more unique applications for these switching
regulators is as a tracking pre-regulator. The only DC connection to ground on either regulator is through the 100n
resistor (R5 or R8) that sets the hysteresis. Instead of tying
this resistor to ground, it can be connected to the output of
IV-35V ....""""'W\O-....
a linear regulator so that the switching regulator maintains a
constant input-to·output differential 'on the linear regulator,
The switching regulator would typically be set to hold the
input voltage to the linear regulator about 3V higher than the
output.
Battery charQing is another application uniq~elY suited for
the LM117. Since battery voltage is dependent on electro- "
chemical reactions, the charger must be designed specifically for the battery type ancj number, of ~lIs. Ni-Cads are,
easily charged with the constant current sources Shown previously. For float chargers 'on lead'·acid tYpe batteries all '
that is necessary is to set the output Of the LM117 at the
float voltage and connect it to the battery. An adjustable
regulator is mandatory since, for long battery life the float
voltage must be preCisely, controlled. The output voltage
temperature coefficient can' 'be matched to the battery by
inserting diodes in series with the adjustment resistor for the
regula~r and coupling the diodes to the battery.
A high performance charger for gelled electrolite lead·acid
batteries is shown in Figure 11. This charger is designEjld to
quickly recharge a battery and shut off at full charge.
Initially, the charging current is limited to 2A by the internal
current limit of the LM117. As the battery voltage rises, current to the battery decreases and when the current has de·
creased to 150 mA, the charger sWitches to a lower float
voltage preventing' overcharge. With a discharged batterY;
the start switch is not needed since the Charger will start by
itself; however, it is included to allow topping off even slight·
Iy discharged batteries.
When the start switch is pushed, the output of the charger
goes to 14.5V set by R1, R2 and R3. Output current is
sensed across R6 and compared to a fraction of the 1.2V
---
1-".,..".,.. .-+-----+-1.8VTO 32V
+
Dl
lN311D
tSolid tantalum
'Core-Amold A·254168·2 60 turns
FIGURE 9. Low Cost SA Switching Regulat~r
372
TLIHI1532-8
;a:.
Z
•
....
....
3-LM391i IN PARALLEL
C»
~290&-,..._ _ _ _ _r.._~_:~:::~\i:~0~",""
...-_.,..,.2N
RI
R4
30
2.5
a-~~~~~~--~
+ CI
~IOllltFt
RS
16k
C2
IOOpF
---
~LIJ"~6~01llt~H!*~"""'-~~~h 32V
RS
240
+
DI
IN3aao
C4
10llltFt
tSolid tantalum
TL/H/15S2-10
'Cor&-Arnold A·254168-2 60 turns
FIGURE 10. 4A Switching Reguletor with OVerload Protection
500
+
T012V
BATTERY
TLlH/1532-11
FIGURE 11. 12V Battery Charger
373
.-co
.z•
cc
r---------------------------~--------------------------------------------------~
reference (across R2) by an LM301A op amp. As the voltCONCLUSIONS
age across R6 decreases below the voltage across R2, the
A new' IC power voltage regulator has been developed
output of the LM101A goes low shunting R1 with R4. This
which is significantly more versatile than older devices. The
decreases the output voltage from 14.SV to about 12.SV
outpqt voltage is adjustable,'in ·addition to improved regulaterminating the charging. Transistor 01 then lights the LED , tion specHications. Further, reliability is increased in 2 fashas a visual indication of full charge.
ions~ Overload protection circuitry has been improved to
The LM117 can even be used as a peak clipping,AC'voltage , make the device' less susceptable to fault conditions and
regulator. Two regulators are used, 1 for each polarity of the
under short cil"Quit conditions, minimum stress is transmitted
input as shown in FlfJure 12. Internal to the LM117 is a diode
back to the input power supply. Secondly, the device is
from input-ta-output which conducts the current 'around the ; 100% burned-in under short circuit conditions at the time of
manufacture. Finally, the LM117 is made with a standard IC
device when the opposite regulator is active. Since each
regulator is operating independently, the positive'and negaproduction process and packaged In a standard TO-3 power
tive peaks must be set separately for a symmetrical output.
package, keeping costs low.
,
LM311
VI.
VOUT1
AOJ
'1
~120
, ~
,
&Vp""
lA
lZVP1I
f\;
410
•
• 480
T".-'
~
121
AOJ
I
VOUTIH~"'--
VI.
c,
LM311
TL/H/1532-12
FIGURE 12. AC Voltage Regulator
','
\,'
374
Improving Power Supply
Reliability with Ie Power
Regulators
National Semiconductor
Application Note 182
Three-terminallC power regulators include on-chip overload
protection against virtually any normal fault condition. Current limiting protects against short circuits fusing the aluminum interconnects on the chip. Safe-area protection decreases the available output current at high input voltages
to insure that the internal power transistor operates within
its safe area. Finally, thermal overload protection turns off
the regulator at chip temperatures of about 170"C, preventing destruction due to excessive heating. Even though the
IC is fully protected against normal overloads, careful design must be used to insure reliable operation in the system.
decrease is linear, and at input-output voltages of about 30V
the output current can decrease to zero. Normally this causes no problem since, when the regulator is initially powered,
the output increases as the input increases. If such a regulator is running with, for example, 30V input and 15V output
and the output is momentarily shorted, the input-output differential increases to 30V and available output current is
zero. Then the output of the regulator stays at zero even if
the short is removed. Of course, if the input is turned OFF,
then ON, the regulator will come up to operating voltage
again. The LM117 is the only regulator which is designed
with a new safe-area protection circuit so output current
does not decrease to zero, even at 40V differential.
This type of start-up problem is particularly load dependent.
Loads to a separate negative supply or constant-current devices are among the worst. Another, usually overlooked,
load is pilot lights. Incandescent bulbs draw 8 times as
much current when cold as when operating. This severely
adds to the load on a regulator, and may prevent turn-on.
About the only solutions are to use an LM 117 type device,
or bypass the regulator with a resistor from input to output to
supply some start-up current to the load. Resistor bypassing
will not degrade regulation if, under worst-case conditions of
maximum input voltage and minimum load current, the regulator is still delivering output current rather than absorbing
current from the resistor. Figure 1 shows the output current
of several different regulators as a function of output voltage and temperature.
SHORT CIRCUITS CAN OVERLOAD THE INPUT
The IC is protected against short circuits, but the value of
the on-chip current limit can overload the input rectifiers or
transformer. The on-Chip current limit is usually set by the
manufacturer so that with worst-case production variations
and operating temperature the device will still provide rated
output current Older types of regulators, such as the
LM309, LM340 or LM7800 can have current limits of 3 times
their rated output current.
The current limit cirCUitry in these devices uses the turn-on
voltage of an emitter-base junction of a transistor to set the
current limit. The temperature coefficient of this junction
,combined with the temperature coefficient of the internal
resistors gives the current limit a - 0.5%I'C temperature
coefficient. Since devices must operate and provide rated
current at 150'C, the 25'C current limit is 120% higher than
typical. Production variations will add another ± 20% to initial current limit tolerance so a typical 1A part may have a
3A current limit at 25·C. This magnitude of overload current
can blow the input transformer or rectifiers if not considered
in the initial design---even though it does not damage the IC.
One way around this problem (other than fuses) is by the
use of minimum size heat sinks. The heat sink is deSigned
for only normal operation. Under overload conditions, the
device (and heat sink) are allowed to heat up to the thermal
shut-down temperature. When the device shuts down, loading on the input is reduced.
Newer regulators have improved current limiting circuitry.
Devices like the LM117 adjustable regulator, LM123, 3A, 5V
logic regulator or the LM120 negative regulators have a relatively temperature-stable current limit. Typically these devices hold the current limit within ± 10% over the full - 55'C
to + 150"C operating range. A device rated for 1.5A output
will typically have a 2.2A current limit, greatly easing the
problem of input overloads.
Many of the older IC regulators can oscillate when in current
limit. This does not hurt the regulator and is mostly dependent upon input bypassing capaCitors. Since there is a large
variability between regulator types and manufacturers, there
is no single solution to eliminating oscillations. Generally, if
oscillations cause other circuit problems, either a solid tantalum input capaCitor or a solid tantalum in series with 5n to
'10n will cure the problem. If one doesn't work, try the other.
Start-up problems can occur from the current limit circuitry
too. At high input-ouput differentials, the current limit is decreased by the safe-area protection. In most regulators the
375
3.5
3
~
....
z
2.5
a:
2
...a:
.....
- - - POSITIVE REGULATOR
LMI17, LM1r
...
I I
I- --' Ti = -55'C
_~
e>
I
.....~vLMI17
--, ~ ~, ~ ~
" ,
" ~,
~Tj'25'C
::0
....
::0
....
::0
I
r---
1.5
1
0.5
, l"-
Ti=150'C',
0
0
10
20
LM120
.
~
30
40
INPUT·OUTPUT DIFFERENTIAL (V)
TL/HI7458-1
FIGURE 1_ Comparison of LM117 Current
Limit with Older Positive Regulator
When a poSitive regulator (except for the LM117) is loaded
to a negative supply, the problem of start-up can be doubly
bad. First, there is the problem of the safe-area protection
as mentioned earlier. Secondly, the internal circuitry cannot
supply much output current when the output pin is driven
more' negative than the ground pin of the regulator. Even
with low input voltages, some positive regulators will not
start when loaded by 50 mA to a negative supply. Clamping
the output to ground with a germanium or Schottky diode
usually solves this problem. Negative regulators, because of
different internal circuitry, do not suffer from this problem.
, ,DIODES PROTECT AGAINST CAPACITOR DISCHARGE
It is well recognized that improper connections to a 3-terminal 'tilgulator will cause its destruction. Wrong polarity inputs
or driving current Into the output (such as a short between a
5V and 15V supply) can force high currents through small
area junctions in the IC, destroying them. However, Improper polarities can be applied accidently under many normal
operatir:'lg conditions, and the transient condition is often
gone before it is recognized.
, '
'
Perhaps the most likely sources of transients are external
capaCitors used with regulators. Figure 2 shows the, discharge path for different capacitors used with a pOi$itiv8 regulator. Input capaCitance, C1, will not cause a problem'under any conditions. Capacitance on the ground pin (or adjustment pin is the case of the LM117) can discharge
'thr:ough 2 paths which have low current junctions.
If the output is shorted, C2 will discharge through the ground
pin, possibly damaging the regulator. A reverse-biased diode, D2, diverts the current around the regulator, protecting
it. If the input is shorted, C3 can discharge through the output pin, again damaging the regulator. Diode D1 protects
against C3, preventing damage. Also, with tiothD1 and D2,
in the circuit, when the input is shorted, C2 is discharged
through both diodes, rather th!!n the ground pin.
In general, these protective diodes are a good idea on all
positive regulators. At higher output voltages, they become
more important since the energy stored in the capaCitors is
larger. With negative regulators ,and the LM117, there 'is an
,inernal diode in parallel with D1 "from output-to-input, eliminating the' need for an external diode if the'output capacitor
is less than 25 p.F.
Another transient condition which has been shown to' cause
problems is momentary loss of the ground connection. This
charges, the dutput capacitor to the unregulated input \/oltage minus a 1-2V drop across the regulator.'lf the ground
is then connected, the output capaCitor, C3, discharges
through the regulator output to the ground pin, destroying it.
In most cases, this problem occurs when a regulator (or
card) is plugged into a powered system and the input pin is
connected before the ground. eo"trol of the connector configuration, such as using 2 ground pins';'to insure ,ground is
connected first, is the best way of preventing this' Pfoblem.
EleCtrical protection is cumbersome. About the 'only way to
protect the regulator electrically is to 'make 02 a power zener 1V to 2V above the regulator voltage and Include 100 to
500 in the ground lead to limit the current.
,LOW OPERATJI'--oEOC
, j.
',SiXTEEN __+~
: ANALOG'
INPUTS=:::j~:
INI-~I-""
MUX
DECODE
IIIR
A
LATCH
ENABLE
+V",
TL/HI7207-1
FIGURE 1. ADC0816/MM74C948 Block Diagram
382
r--------------------------------------------------------------------.~
Figure 2 shows a typical application employing the
ADC0816 for use in a microprocessor-based environmental
control system. In this system the microprocessor can select a channel. monitor a particular sensor reading. convert
that signal to a digital word. and make a system decision
based upon that input. Many other areas of process control.
machine control. or multi-input analog system can utilize this
basic configuration.
The bottom resistor and the top resistor of the ladder network in Figure 4 are not the same value as the remainder of
the network. The difference in these resistors causes the
output characteristic to be symmetrical with the zero and
full-scale pOints of the transfer curve. The first output transition occurs when the analog signal has reached + 1/2
LSB and succeeding output transitions occur every 1 LSB
later up to full-scale.
The successive approximation register (SAR) performs
eight iterations to approximate the input voltage. For any
SAR-type converter. n iterations are required for an n-bit
converter. Figure 4 shows a typical example of a 3-bit converter with an input voltage of 1/4 full-scale. Since the initial
approximation at 7/16 of full-scale is too high. a zero is
posted for the most significant bit (MSB). The second approximation is too low. therefore a one is posted for the
second bit. The final approximation is determined to be too
high. so a zero is posted for the least significant bit (LSB). In
the ADCOB16/MM74C94B the approximation technique is
extended to eight bits using the 256R network.
The most important section of the AID converter is the
comparator. It is this section which is responsible for the
ultimate accuracy of the entire converter. It is also the comparator drift which has the greatest influence on the respectability of the device. A chopper stabilized comparator
provides the most effective method of satisfying all the converter requirements.
THE CONVERTER
The heart of this single-chip data acquisition system is its
8-bit analog-to-digital converter. The converter is designed
to give fast. accurate. and repeatable conversions over a
wide range of temperatures. The converter is partitioned
into three major sections: the 256R ladder network. the successive approximation register. and the comparator.
The 256R ladder network approach was chosen over the
conventional R/2R ladder because of its inherent monotonicity. Monotonicity is particularly important in closed-loop
feedback control systems. A non-monotonic relationship
can cause oscillations that could be catastrophic. Additionally. the 256R network does not cause load variations on
the reference voltage.
Figure 3 shows a comparison of the output characteristic for
the two approaches with a variation in the ladder resistance.
In the 256R approach with unequal or shorted resistors the
slope of the output transfer function cannot be different
from the slope of the analog input. For the R/2R ladder
network. mismatches in the resistor values can cause the .
slope of the output digital code to be different from the analog input signal.
DATA
SENSORS
TEMP
COMP
REFERENCE
HEAT
LIGHT
PRESSURE
FLUID LEVEL
HUMIDITY
AIR VELOCITY
ETC.
SIGNAL
CONDITIONERS
SIXTEEN
ANALOG
INPUTS
LINE
DRIVERS
DATA
ACQUISITION
SYSTEM
74C948
o
~
J-_. ._~AP
PARALLEL
FRONT
tl~~
o
TO PROCESSOR
REMOTE
SITE
TRANSCEIVER
FROM PROCESSOR
R
T
CONTROL
START
CONV.
END
CDNV.
FRDNTEND
CONTROL
CONTROL
SOLENOIDS
VALVES
START
STOP
ACTUATORS
ENVIRONMENT
CONTROL
DISPLAY
CONTROLLER
FRONT END
DATA BUS
TUH/7207-2
FIGURE 2. Remote Environmental Control System
383
Z
•
....
CD
W
~ .-------------------~------------------------------------------------------------~
Q)
.-
~
The chopper stabilized comparator converts the DC input
signal Into an AC signal. This signal is then fed through a
high gain AC amplifier and has the DC level restored. This
technique limits the drift component of the amplifier since
the drift Is a DC component. which is not passed by the AC
amplifier. This makes the entire AID converter extremely
insensitive to temperature, long-term drift, and input offset
errors.
The design of this AID converter has been optimized by
·Incorporatlng the most desirable aspects of several cOnversion techniques. The ADC0816 offers high speed, high·accuracy, low temperature,dependence, excellent long-term
accuracy and repeatability, and consumes 'mlnlmal' power.
These features make this device ideally suited to applications such as process control, industrial contrOl, and machine control.
r---~~-------o-Vm
---000
.--+-....
+v..t·
2R+1I
+V..,
"""M_.
_-\N\r-...IIt/\,."....
-V,of
2R
R
00
01
VOUT
R
-v..,
Voo
VOl
VIt
V,O
OUTPUT VOLTAGE
01
00
It
10
INPUT CODE
I.
11
TUHn207-3
FIGURE 3. 2"R and R2R Ladder Transfer Curves. In a 2"R ladder the most unequal resistors can do Is cause a
nonuniform voltage step. Since a single voltage is across the ladder it must be monotoniC. In a R2R ladder unequal
resistors may cause a sign change in the transfer curve, causing It to be nonmonotonic.
+V..,
NORMALIZED INPUT RANGE
+VIef
I
FULL-SCALE
1&/18
:t
.:
11,
" .; . . --- "'CD ___
I%R
13/18
R
. 11/18
R.
R
7/1
R
R
311 8
R
%R
••" }
\
_."
\.START
•
SlI8
,......
I
8/1.
.If
,. ..........L
t·#'
~
101
010
INPUT
010
1
.J
./
1111 ~4'
000
OIl
100
OUTPUT CODE
lDI
111
--'"
111
TUHn207-4
FIGURE 4. Offset-Adjusted 8R Ladder gives ± % LSB quantizing error of 3 bits with
three comparisons. The output code Is derived by posting a one when upward arrows
are followed and a zero when downward arrows are followed to the Input voltage.
384
CMOS AID Converter Chips
Easily Interface to 8080A
Microprocessor Systems
National Semiconductor
Application Note 200
SUMMARY
Single or multiple channel monitoring of physical variables
can be achieved with high accuracy despite the lack of complexity and low overall cost.
This paper describes techniques for interfacing National
Semiconductor's new ADC3511 and ADC3711 microprocessor compatible analog-to-digital converter chips to 8080A
microprocessor systems. The hardware interface and the
software interrupt service routine will be described for single
and multiple AID converter data acquisition systems.
AID CONVERSION
A" AID converters in this family operate from a single 5V
supply and convert inputs from 0 to ± 2V. The converters
use a pulse-width modulation technique which requires no
precision components and exhibits low offset, low drift, high
linearity and no rollover error. An additional advantage is
that the voltage reference is of the same polarity as the
supply.
Two resolutions are offered: the 3 VI-digit types divide the
input into 2,000 counts plus sign, while the 3 %-digit types
provide 4,000 counts plus sign which is roughly equivalent
to the resolution of a 12-bit plus sign binary converter. The 3
VI-digit converters require 200 ms per conversion; 3 %-digit
types require 400 ms.
The converters handle negative inputs by internally switching the inputs and forcing the sign bit low. While this teChnique allows conversion of positive and negative inputs with
only a Single supply, the supply must be isolated from the
inputs. Without an isolated supply, only positive voltages
may be converted.
The basic converter is shown in Figure 1. The actual conversion technique is described in Appendix A.
INTRODUCTION
The recent introduction of monolithic digital voltmeter chips
has encouraged designers to consider their use as analogto-digital converters in data acquisition systems. While the
high accuracy afforded at low cost was attractive, certain
difficulties in applying these devices in digital systems were
encountered. Most of these difficulties were due to the DVM
chip's output structure being oriented towards driving 7-segment displays with internally generated digit scanning rates.
National Semiconductor has recently introduced a family of
monolithic CMOS AID converters-2 of these devices are
directed towards LED display DPM and DVM applications
(ADD3501 3 VI-digit DPM and ADD3701 3 %-digit DPM)
while the other 2 (ADC3511 3 VI-digit AID and ADC3711 3
%-digit AID) have addressable BCD outputs. These last 2
devices allow easy interface to microprocessor and calculator-oriented (COPS) systems.
23
z2
tJ
If-
Vee IV
vee
,t
ANALOG Vee
,'f--
~"
"
ADC3lnee
(ADel71ICC'
OVERFLOW
CONVERSION
COMPLETE
START
CONVERSION
SION
Ul~fV'N(_I
YINI·)
'"
'to
21 2' 01 DOOLE
..
Otl---
OLE
fOUT
fO.
YFILTER
~
. ., I.b
~':"F
VREf
VAEF 2.DDDV
SWt~
VIII-!
YINI+}
r
Vss
awl
ANALOG
GROUND
r-...;,...
...
.ND
VFB
t...
~Ul'F
TL/H/5616-1
FIGURE 1. Baalc AID Convarter
385
BCD OUTPUT DESCRIPTION
. The ADC3511 and ADC3711 present the output data in
BCD form on a single 4-line output port, plus a separate sign
output. The desired digit is selected by a 2-bit address
which is latched by a high level at the Digit Latch Enable
input (OLE); a low level at DLE allows flow thru ,operation.
Since the output is BCD, it is compatible with many standard
instruments and can easily be converted into binary by the
processor if this format should be desired. Overrange inputs
are indicated by a hexidecimal "EEEE" plus an Overflow
output.
One reference can be uSed for manY AID's. The values of
the upper series resistor R1 depends on the number'of con'
verters used.
A SINGLE CHANNEL CONVERTER
A complete AID port is seen in Figures 3 and 4. Figure 3
shows a Dual Polarity converter and Figure 4 a Positive Only
Polarity converter. Each port contains an AID converter,
TRI-STATE<8> bus driver, and 2 gates to control 110. This
AID port is easily used in single or multi-channel systems.
In multichannel systems a converter is used on every channel allOwing digital multiplexing of the outputs.
A new conversion is begun by a positive pulse or high level
at the Start Conversion (SC) input. The analog section of
the converter continuously tracks the analog input. The
Start Conversion command controls only the transfer of
new data to the output latches, consequently the delay from
the SC pulse to the Conversion Complete (CC) signal may
vary from several milliseconds to several hundred milliseconds. In interrupt driven systems the delay is no problem,
since the processor does not execute delay instructions
while waiting for the data. However, if in-line or program 110
is used where the program waits for the data to be ready,
the maximum delay between SC and CC must be programmed into the wait routine. This type of 110 is therefore
not as efficient as interrupt 110.
Data from the AID converter in a single channel system is
easily processed using an OUT command to start a conversion and IN commands to read the data after the microprocessor has been interrupted by a Conversion Complete.
As seen in Figure 5, a single channel AID port uses a 6-bit
bus comparator to decode its assigned peripheral address
from the lower address bits of the 8080A address bus.
When an interrupt is received, the present status of the
processor is stored on the stack memory by a series of push
commands. The interrupt is serviced by reading digit 4
(MSD) into the processor and checldng the overflOw bit. If
the overflow bit is high, the converter input has exceeded its
range and an error signal is generated, indicating that scaling must be done to attenuate the input signal. If the OFL is
low, the sign bit is then checked to determine the polarity of
the conversion. If the sign bit is low, a "1" is,added to the
MSB of digit 4. Since this bit would normally be low, (maximum converter range allows MSB S; 3 or 0011) a "1" in this
pOSition is used to denote a negative input voltage. The 4
bits of digit 4 which now include the sign are shifted into the
upper half of the first byte and the 4 bits of digit 3 are
packed into the lower half. Similarly, digits 2 and 1 are
packed into the second byte and both bytes stored in memory.
The CC output goes low immediately after the SC pulse. At
the end of a conversion, CC goes high and remains high
until a new conversion is initiated. Continuous conversion
operation is obtained by tying the SC input to Vee.
REFERENCE VOLTAGE
The 2.000V reference is derived from the LM336, a recently
announced monolithic reference which provides 2.5V with
low drift at low' cost. This active reference is adjusted for
minimum thermal drift of about 20 ppml"C by using a third
terminal on the device to adjust its output to 2.490V.
Total reference current consumption is low, as the LM336
requires only 1 mA of bias current, and the resistor divider
about 2 mA. The reference circuit is shown in Figure 2.
Figure 6 and routine 1 are the flow chart and assembly language routine used to implement this action.
8-CHANNEL AID WITH SOFTWARE PRIORITY
The basic AID port can easily be expanded to multiple
channel systems. An 8-channel system is seen in Figure 7.
This system interrupts the processor when one of the Conversion Complete outputs goes high. The processor saves
the current status and reads the status word of the AID
system. The status word is then compared to a priority table.
Each level in the table corresponds to a priority level with
high priority converters which are first in the table. If 2 or
more converters have the same priority and are ready at the
same time, the converter with the highest number gets serviced first.
Vee
..
...--+---o!m.Ef
, " ,.
'---_--o:::~:
•
_
R - (2N
2.49V
+
TUH/5616-2
_
The program determines which service routine to use by the
bit position of "1's" in the status word. The routine loads the
address pOinter to digit 4 of the selected converter. The
1) mA N - 1,2 ...8
FIGURE 2. AID Converter Reference. The 10k Pot Is
Adjusted to a Voltage of 2.49V on the Output; at this
Voltage Minimum Drift Occurs. The Reference can
Supply up to 8 AID Converters.
386
program then calls a subroutine which goes through the process of checking overflow, sign and packs 4 BCD digits into
2 bytes. These 2 bytes are then stored in a table in the
memory directly above the converter addresses. After a
UIV
211
21
channel is serviced, the original processor status is restored
and the interrupt enabled. If additional channels need service, they immediately interrupt so the new status word is
then read and a new priority established.
lit
AIOREF~
FULL.scAlE
. ADJUST
aMlllaS
VRl'
AVec
....
OFl
OI.
SIGI
Oil
.'
083
.
AIN:2111
(AOC31'111
OU
•1
Oil
,.
000
at
OLE
Q
ITART
CC
1I.47p'
~
co
DI
DO
:::~:: o-~~-+---I
'-------'
FIGURE 3. Dual Polarity AID Requires that Inputs are Isolated from
t!1e Supply. Input Range Is ± 1.999V.
UIV
232
ID
111
"D'''~''''
ADJUST
DMiDLIII
VAE'
+
D"
SIGN
Oil
D83
z3
AVec
....
OFl
.
D12
D81
•1
ADC3511
IADCJ711) .
.
DID
at
OLE
V,.
Q
'"
START
~
co
GA7p'
.::::~ o-_~""'
01
__-I
'-------'
TL/H/5816-3
FIGURE 4. Positive Polarity AID Operating from 5V Supply.
Input Range Is + 1.999V.
387
~------------~mm
~------------~mM
01
0....
c
t'!DU
Oil
011
II
I----=~--_f~-a__l.,
F~I--o-,'
r-
CONY COMnnl
ANALOG Vee
..,.
H>o-"
~.,
DECOR
~
7
ROM
ICD
,
DECOR
;::::=
I
I
I
'D'
'DO
-
;i
'--
fREOOUT"'-
11-4
MUX
- H>o-,a
1'-7'
I
0
SWI
+
U~II
~D
I .... I
_
r;:!' \
L:-.J
r
I~-
~
-VAIF
I
TLlH~5818-9
FIGURE A2. ADC3511 3Ya-Dlglt AID (0 ADC3711 3 3/4-Dlglt AID) Block Diagram
J
394
National Semiconductor
Application Note 202
A Digital Multimeter
Using the ADD3501
INTRODUCTION
National Semiconductor's ADD3501 is a monolithic CMOS
IC designed for use as a 3 Va-digit digital voltmeter. The IC
makes use of a pulse-modulation analog-te-digital conversion scheme that operates from a 2V reference voltage,
functions with inputs between OV and ± 1.999V and operates from a single supply.
The conversion rate is set by an external resistorI capacitor
combination, which controls the frequency of an on-chip oscillator. The ADD3501 directly drives 7-segment multiplexed
LED displays, aided only by segment resistors and external
digit buffers. The ADD3501 blanks the most significant digit
whenever the MSD is zero; and, during overrange conditions, the display will read either +OFL or -OFL (depending on the polarity of the input.)
These characteristics make the ADD3501 suitable for use in
low-cost instrumentation. An example of such use is the
inexpensive, accurate, digital multimeter (DMM) presented
here-an instrument that measures AC and DC voltages
and currents, and resistance.
CIRCUIT DESCRIPTION
Figure 1 shows the circuit diagram of the ADD3501-based
DMM, and Table I summarizes its measurement capabilities.
Since the accuracy of the ADD3501 is ±O.050/0, the DMM's
performance is mainly determined by the choice of discrete
components.
Supporting the ADD3501 is a DS75492 digit driver, an
NSB5388 LED display, and an LM340 regulator for the Vee
supply. A 2V reference voltage-10Mn
2OVT02kVRANGE,10Mn
Note 2: All resistors are Yo watt unless _
Note 5: All diodes are lN914.
specified.
Note 3: All capacitors are ±10%.
,,...
2V, 20V, 2OOV, 2 kV
(40 TO 5 kHz SINEWAVE)
-
.....
< ± 1% ACCURACY
DC AMPS
RANGES
'M
200 !lA, 2mA, 20 rnA, 200 mA, 2A
< ± 1% ACCURACY
rnA, 20 mA, 200 mA, 2 A
< ± 1% ACCURACY
ACRMSAMPS
RANGES
200 !lA, 2
OHMS
RANGES
200 n, 2 kn, ?O kn, 200 kn, 2 Mn
>>----,
.MB
LIS
IAn=>~_+!f
,...
.......,
.......'"
Co)
3!
Note 4: All op amps have a 0.1 "F capacitor connected across
the V + and V - supplies.
< ± 1% ACCURACY
ACRMSVOLTS
RANGES
2 ..
Note 1: All Vcr; connections should use 8 single Vcr; point and all ground/
analog ground connections should use 8 single ground/analog ground point
.... x •
..~~r~L~
YOLlI
+
I-
VILli
~"==i-----~--~-+
22MB
~
+-_'~.~W~_~_-==9~
~~
U,,... UJ',.F
II
..,.
-
Vee
..,.
..,.
FIGURE 1. ADD3501 Low Cost Digital Multimeter
LI,.F
TLIH/5617-1
AC Current Measurement. AC current measurements are
Note that VREF is derived from the LM336-a precision voltage source. Equation (1) shows, then, that (all else remaining constant) VI varies directly with changes in Vee; i.e., VI
tracks Vee. The Al/0l pair thus establishes a voltage
across R2 that floats, independent of changes in the
ground-referenced potentials (Vee and VREF) that define it.
Now look at the A2/02 Circuitry. The closed-loop operation
of A2 tries to maintain a zero differential voltage between its
input terminals. A2's non-inverting input is held at VI; thus,
A2's inverting input is driven to VI. The current through RL
(02's emitter current) is therefore (Vee-V1)RL' Since VI
tracks Vee, then (Vcc-Vl) - the voltage drop across RLis constant, thus producing 'SOURCE (Figure 3)-the constant source current needed for the resistance measurement.
made in a way similar to DC current measurements. The
DMM is switched to its AMPS and AC settings. The in-circuit
current is again measured by a drop across the DMM's current-sensing resistor, but now the AC voltage developed
across this resistor is processed by A3, A4, and A5-exactly
as described for AC voltage measurements-before being
transferred to the ADD3501. Again, the DMM displays an
rms value appropriate for the AC signal current being measured.
Resistance Measurement. This DMM measures resistance
in the same way as do most multi meter: it measures the
voltage drop developed across the unknown resis~nce by
forcing a known, constant-current through it. Suitable scale
calibration translates the voltage drop to a resistance value.
The resistance measurement requires the generation of a
constant-current source that is independent of changes in
VCC' using the 2V, ground-referred reference voltage. The
circuit of Figure 3 accomplishes this.
Note, that varying Rx will not affect 'SOURCE so long as the
voltage drop across Rx is less than (Vl-VSE2)' Should VRX
exceed (Vl-VSE2), 02 would saturate, invalidating the
measurement. The ADD3501 eliminates this worry, however, because as soon as the drop across Rx equals or exceeds the 2V full-scale input voltage the ADD3501 will display an OFL condition.
In Figure 3, AI establishes a constant-current sink by forcing node A to VREF, the voltage level at AI's non-inverting
input. With node A held constant at VREF (2.000V), current
through R2 is also fixed-since 01's collector current is determined by the alE product-thus establishing VI as
VI =VCC-a(VREF/Rl)R2
Finally, SWI (Figure 3) is required as part of the VOLTS/
AMPS/OHMS mode selection circuitry; in the VOLTS/
AMPS position it prevents 02's base-emitter junction pulling
the V - supply to ground through A2.
(1)
TABLE I. DMM PERFORMANCE
Measurement
Mode
DC Volts
ACVoits
DC Amps
ACAmps
Ohms
Range
0.2
2
2
Frequency
200
2000
Accuracy
-
-
,;;
V
V
V
V
VRMS
YAMS
VRMS
VAMS 40 Hz to 5 kHz ,;;
,;;
rnA
mA
rnA
rnA
rnA
mARMS mARMS mAAMS mARMS mARMS 40 Hzt05kHz ,;;
,;;
kO
kO
kO
kO
kO
-
-
OVerrange
Display
Response
I%F.S.
I%F.S.
I%F.S.
1% F.S.
I%F.S.
± OFLO
+ OFLO
± OFLO
+ OFLO
+ OFLO
TL/H/5617 -2
FIGURE 2. AC/DC Converter
397
VCC
>-.....f-1H......
RL
- ,"".--(RESISTANCE
RANGE SELECT)
A2
20k
_~...._~VIN+
VOLTSIAMPS
(ADD3601)
,0
SWI
OHMS
TLlHI5617 -3
FIGURE 3. Constant-Current Source
CALIBRATION
baSic circuit of FigufB 1 are possible in the following areas:
Calibrate the DMM according to the following sequence of
operations:
1; Adjust P1 until the cathode voltage of
the reference diode, LM336, equals
2.49V. This reduces the diode's temperature coefficient to its minimum value.
DC Volts 2V
2. Short the (+ ) and (-) probe inputs of
Range
the ADD3501 and adjust P2 until the
display reads 0000.
DCVolts2V
3. Apply 1.995 volts across the (+) and
(-) probe inputs and adjust P3 until
Range
the display reads 1.995.
Ohms2MO
4. Select a precision resistor with a value
Range
near full-scale or the 2 MO range, and
adjust P4 until the appropriate value is
displayed.
AC Volts 2V
5. Apply a known 1.995Vrms sinewave
Range
Signal to the DMM and adjust P5 until
the display reads the same.
1. Expand the VOLTS mode to include a 200 mV full-scale
range;
2. Decrease the full-scale current-measurement loading
voltage from 2V to 200 mY; and,
3.. Provide a true-rms measurement capability.
4. Increase resolution by substituting the ADD3701-3 %digit DVM chip-which is interchangeable and provides a
maximum display count of 3.999.
The first 2 improvements involve a dividing down of the
ADD3501 feedback loop by a ratio of 10:1, which reduces
the 2V full-scale input requirement to 200 mY. This not only
allows a 200 mV Signal between the ADD3501's VIN+ and
VIN- inputs to display a full-scale reading, but implies that
the maximum voltage dropped across the current-measuring-mode resistance.also will be 200 mY. Note, though, that
the values of the current-measurement resistors must be
scaled down by a factor of ten.
Additionally, a 200 mV full-scale input implies a resolution of
100 /LV/LSD. At such low input levels, the DMM may require some clever circuitry to eliminate the gain and linearity
distortions that can arise from the offset currents in the ACto-DC converter.
PC BOARD LAYOUT
It is imperative to have only one, single-point, analog signal
ground connection for the entire system. In a multi-ground
layout, the presence of ground-loop resistances will cause
the op amps' offset currents and AC response to have a
devastating effect on system gain, linearity, and display LSD
flicker. Similar precautions must also be taken in the layout
of the analog and high-switching-current (digital) paths of
the ADD3501.
The third possible improvement-the reading of true-rms
values--can be implemented by replacing the AC-to-DC
converter of FigufB 2 with National's LH0091, a true-rms-toDC converter, and appropriate interface circuitry.
REFERENCES:
A FINAL NOTE
1. ADD3501 Data Sheet.
4. Application Note AN-20.
The digital multimeter described in this note was developed
with the goals of accuracy and low cost. For the high-end
DMM market segments, however, improvements to the
2. LH0091 Data Sheet.
5. ADD3701 Data Sheet.
3. LM336 Data Sheet.
398
New Phase-locked-Loops
Have Advantages as
Frequency to Voltage
Converters (and more)
National Semiconductor
Application Note 210
Robert Pease
A phase-locked-loop (PLL) is a servo system, or, in other
words, a feedback loop that operates with frequencies and
phases. PLL's are well known to be quite useful (powerful,
in fact) in communications systems, where they can pluck
tiny signals out of large noises. Here, however, we will discuss a new kind of PLL which cannot work with low-level
Signals immersed in noise, but has a new set of advantages,
instead. It does require a clean noise-free input frequency
such as a square wave or pulse train.
This PLL can operate over a wide frequency range, not just
1 or 2 octaves but over 1 or 2 or 3 decades. It naturally
provides a voltage output which responds quickly to frequency changes, yet does not have any inherent ripple.
Thus, it can be used as a frequency-to-voltage (F-to-V)
converter which does not have any of the classical limitations or compromises of (large ripple) vs (slow response),
which most F-to-V converters have. 1 The linearity of this Fto-V converter wni be as good as the linearity of the V-to-F
converter used, and this linearity can easily be better than
0.01%. Other advantages will be apparent as we study the
circuit further.
The basic circuit shown in Figure 1 has all the functional
blocks of a standard PLL. The frequency and phase detection do not consist of a quadrature detector, but of a standard dual-D flip-flop. When the frequency input is larger than
F2, Ql will be forced high a majority of the time, and provide
a positive error signal (via CR3, 4, 5, and 6) to the integrator.
FREOUENCY. PHASE DETECTOR
~----~--i4t--------1~~~~-------------WS
FINPUT-+-_~
lSOUARE WAVE
OR PULSE TRAINI
VI
MM74CI83
CD4II4G
OR SIMILAR
OPTIONAL
OffSET ADJUST
RZ
12l1li
1II1II
ERROR
INTEGRATOR
-VS
IN
'OUTPUT
-+-----'
V·TO·F CONVERTER
ZZk
RI'
Uk
LM331
-lOY fULL SCALE
TL/H/5618-1
FIGURE 1. Basic Wide-Range Phase-Locked Loop
1. Appendix C, "VlF Converter IG. Handle Frequency-Io-Voltage Needs," National Semiconduc1or Uneer Applications book.
399
output voltage V~ can be used as the output of an ultralinear F-to~ V coiwerter: However during the brief, pulses when
the flip-flop is CLEARing itself, there will be small ,glitches
found on the output of A1. The RMS value ot'thls noise may
be very small, typically 0.5 to 51j1V, but the peak amplitude,
sometimes 10 to 100mV, can be annoying hi Sortie systems.
And, no additional filtering can be added in the, mllin loop's
path, for any further delay in the route to the "Fe would
cause loop instability. Instead, the output may be obtained
from a separate filter and buffer which operates on a branch
path. A2 proVides a simple 2-pole active filter (as discussed
in Reference 1) which cuts the steady-state ripple and noise
down below 1mV peak-to-peak an excellent level for such a
quick F-toN (as we shall see).
What is not obvious about A2 is that its output can settle
(within a specified error-band such as ± 10 millivolts from
the final DC value) earlier and more quickly than A1's output. the waveforms in Figure 2 show FIN stepping up instantly from 5 kHz to 10kHz; it also shows F2 stepping up
very quickly. The error signal at 01 is also shown. The critical waveforms are shown in Figure 3, the outputs of A 1 and
A2; While A1 puts out large spikes (caused by 11 flowing
through R3), these large spikes cause the V-to-F converter
to jump from 5 kHz to 10KHz without any delay. There is, as
shown in Figure 2, a significant phase error between FIN
and F2, but an inspection of these frequencies shows that
frequency lock has been substantially instantaneous. Not
one cycle has been lost The phase lock and settling takes
longer to achieve. Still, we know that if the frequency out of
the VFCis 10kHz, its input voltage must be -10 VDC. If
there is noise on it, all we have to do is filter it in A2. Figure 3
shows that A2 settles very quickly - actually, in 2.0 milliseconds, which is just 20 cycles of the new frequency. A2's
,output has settled (i.e., the frequency has settled). while
'A 1's output error (which is indicative of phase error being
servo'ed out) continues to settle out for another 12 ms.
Thus, this filter permits its output voltage to settle faster
than its input, and it is responsible for the remarkable quickness of this circuit as an F-to-V converter. The waveforms of
If F Input and F2 are the same,but the riSing' edges of F
input lead the rising edges of F2, the duty cycle of 01 = HI
will be proportional to the phase error. Thus, the error signal
fed to the Integrator will decrease to nearly zero~ when the
loop has achieved phase-lock, and the phase error between
FIN and F2 is zero. Actually, in this condition, 01 will put out
30 nanosecond positive pulses, at the same time that 02
puts out 30 nanosecond negative pulses, and the net effect
as seen by the integrator is zero net charge. The 30 nanosecond pulses at 01 and 02 enable both flip-flops to be
CLEARED, and prepared for the next cycle. This phase-detector action is substantially the same as that of an MC4044
Phase-Detector, but the MM74C74 is cheaper and uses less
power.. It is fast enough for frequencies below 1 MHz. (At
higher frequencies, a DM74S74 can be used similarly, with
very low delays.)
The error integrator takes in the current from R1 or R2, as
gated by the 01 and Q2 outputs of the flip-flop. For example, when FIN is higher, and 01 is HIGH, 11 will flow through
CR4, 5, and 6 and cause the integrator's output to go more
negative. This is the direction to make the V-to-F converter
run faster, and bring F2 up to F input. Note that A 1 does not
merely integrate this current in C1 (a mistake which many
amateur PLL designers make). The resistor R3 in series with
C1 makes a phase lead in the loop response, which is essential to loop stability. The small capacitor'C2 across R3 is
not essential, but has been observed to offer improved settling at the voltage output.
'
The output of the integrator, V1, is fed to a voltage-to-frequency (V-to-F) converter. The example shown here utilizes
a LM331. This converter runs on a single supply, and responds quickly with nonlinearity better than 0.05% (even
though an op-amp is not used nor needed). The output of
the VFC is fed back to F2, as a feedback freq~ency, either
directly or through an (optional) frequency divider. Any number of standard frequency dividers such as MM74C193,
CD4029, or CD4018, can be used, subject to reasonable
limits. A divider of 2, 3, 10, or 16 is often used. The output
voltage of the integrator will be proportional to the F input,
as linearly as the V-to-F can make it. Thus, the integrator's
Verllcalsensitlvlty= 10 V/DIV (CMOS logic levels)
Horizontalsenslllvity = 0.5 ms/DIV
Vert = 10 V/DIV, Horlz=0.5 ms/DIV
TL/H/5618-2
TL/H/5618-3
FIGURE 2a. F output steps up from 5 kHz to 10 kHz,
as quickly as the Input, ,never missing a beat.
Top Trace = Input "FIN" to PLL.
Bottom Trace = output "FOUT" from PLL
FIGURE 2b. Error Signal. Top Trace = error signal
at 01. Bottom Trace = output "FOUT" from PLL.
400
Figure 3 can be compared to the response (shown in Figure
4) of a conventional F-to-V converter. The upper trace is the
output of a conventional FVC after a 4-pole filter2, and
the lower trace is the output of the circuit of Figure 1. The
phase-locked-loop F-to-V converter is quicker yet quieter.
2. AN·207, V·to·F and F·to-V Converter Applications.
Vert = 2 V/DIV, Horiz = 2 ma/DIV
Vert
= 2 VlDIV, Horlz = 0.5 ma/DIV
d
TL/H/5618-5
TUH/5618-4
FIGURE 3a. Settling waveforms, as F,N goes from 5 kHz
to 10 kHz and back again, ualng circuit of Figure t. Top
Trace = output of Integrator (V1). Bottom Trace =
output of filter (VOUT).
FIGURE 3b. PLL Settling Waveforms.
The same waveform aa In Figure 38, but time base la
expanded to 0.5 ms/DIV to show fine detail of aeWlng.
Vert = 2 V/DIV, Horlz "" 20 ms/DIV
p 1<,,;
~
Vert
""
~~ :)' ~ ... ~ :i>:"
= 2 V/DIV, Horlz = 20 ms/DIV
piV" i.
~ "
,
.. 'j
t
»e"j
d
2
;
J"
';~l;:t:,~,~ '>,1:,
;
pd
TUH/561S-6
TUH/5618-7
FIGURE 4a. FVC Response va PLL Response. The PLL
can settle rather more quickly than a conventional F-toV converter. Top Trace = conventional F-to-V
converter with 4-pole active filter, responding to a 5
kHz to 10 kHz atep. Bottom Trace = PLL FVC, with the
same input, circuit of Figure 1.
FIGURE 4b. FVC Step Response.
FIGURE 4b. This waveform la similar to that In Figure 411
but the frequency change covers a 10:1 ratio, from 10
kHz to 1 kHz and back to 10 kHz. For this waveform, the
adaptive current sources of Figure 5 connect to Figure
t (whereas for Figure 4a R1 = R2 = 120k).
Vert
pM
=
2 VIDIV, Horiz
Of,'"
5 ms/DIV
q
" ' , ~ ~?"'I.
2, ..""-"" r> """1"""'"
, '
=
.' .
'~
d
TL/H/5618-9
TLlH/561S-S
FIGURE 4c. FVC Response. The same as Figure 4b, but
time base expanded to 5 ms/DIV, to show detail of rise
time. Top Trace = conventional FVC. Bottom Trace =
PLLFVC.
FIGURE 4d. FVC Response The same as Figure 4b, but
expanded to 5 ms/DIV to show details of fall time. Top
Trace = conventional FVC. Bottom Trace = PLL FVC.
401
Yert
= 0.2 VlDIY/, Horlz = 50 ma/DIY
to F, it is easy to generate current sources 11' and 12' which
are proportional to F. The circuit of Figure 5 can be connected to the basic PLL, instead of Rl and R2, and provides
good, quick loop stability over a 30:1 frequency range, from
330 Hz to 10kHz. For best results over a 30: 1 frequency
range, change R3, the damping resistor in Figure 1, from
47k to lOOk. However, if the frequency range is smaller
(such as 2:1 or 3:1), constant resistors for Rl and R2 or
very simple current sources may give adequate response in
many systems. (To cover wider frequency ranges than 30.1
with optimum response, the circuits in the precision phaselocked-loop, below, are much more suitable.)
Often a frequency multiplier is needed, to provide an output
frequency 2 or 3 or 10 or n times higher than the input, By
inserting a + n frequency divider in the feedback loop, this is
easily accomplished. [Of course, a + m frequency divider
can be inserted ahead of the frequency input, to provide
correct scaling, and the output frequency then will be
FIN(n/m).]
TLfHf5618-10
FIGURE 4e. PLL Settling Waveforma at Low
Frequencies. The 88me Idea aa.ln Rgul'fl4b, but 10 x
alower, from 1.0 kHz to 100 Hz (and back). The aettllng
to 1 kHz la atlll dlatlnctly faater for the PLL, but at 100
Hz, it ia a bit alower. Stili, the PLL la faater than the FVC
at allapeeda from 200 Hz to 10 kHz.
To obtain good loop stability in a frequency multiplier with n
= 2, remember that a 20 kHz V-to-F converter followed' by
a + 2 circuit has exactly the same loop response and stability needs as a 10 kHz V-to-F converter, because it is a 10
kHz V-to-F converter, even though it provides a useful 20
kHz output. Thus, the frequency of the F2 (minimum and
maximum) will determine what loop gains and loop damping
components are needed.
So far we have shown a PLL which operates nicely over a
frequency range of about 3:1. If the frequency is decreased
below 3 kHz, the loop gain becomes excessive, and the
currents 11 and 12 are large enough to cause loop instability.
The loop gain increases at lower frequencies, because a
given initial phase error will cause the fixed current from Rl
or R2 to be integrated for a longer time, causing a larger
output change at the integrator's output, and a larger
change of frequency. When the frequency is thus corrected,
and the period of one cycle is changed, at a low frequency it
may be over-corrected, and the phase error on the next
cycle may be as large as (or larger than) the initial phase
error; but with reversed sign.3 To avoid this and to maintain
loop stability at lower frequencies, e.g. 0.5 to 1 kHz, Rl and
R2 can be simply raised to 1.5 M.o.. However, response to a
step will be proportionally slower. To achieve a wide frequency range (20:1), and optimum quickness at all frequencies, it is necessary to servo 11 and 12 to be proportional to
the frequency. Fortunately, as Vl is normally proportional
To accommodate a 1 kHz V-to-F loop, simply make Cl and
C2 10 times bigger than the values of Figure 1; treat
C4,
C5 and Ct similarly is used. To accommodate a 100 Hz V-toF, increase them by another factor of 10.
ca,
If the PLL is to be used primarily as a frequency multiplier, it
may be necessary to use stable, low-temperature-coefficient components, because the accuracy of VOUT will not
be important. The parts cost can be cut considerably. (Make
sure that the VFC does not run out of range to handle all
frequencies of interest.) On the other hand, the damping
components will be chosen quite a bit differently if slow,
stable jitter-free response is needed or if quick response is
required. The circuits shown are just a starting place, to start
optimizing your own circuit.
r------.....
--1P"--+ys
4lk
CURRENTSOURCEl1'
f~':iWlfow,
CURRENT SOURCE 12'
CONNEcnQlli)
INSTEAD Of RI
A3 - LF351, LM741 OR ANY
NPN TRANSISTOR - 2N3904, 2N2222 OR ANY SILICON NPN
PNP TRANSISTOR - 2N3906, 2N2907 OR ANY SILICON PNP
ALL RESISTORS ±10%
ALL DIODES 1N914 OR 1N4148 OR SIMILAR
L . . . - -.....- -.....-
.....--ys
FIGURE 5. Proportional Current Source for Baalc PLL
3. Optimize phase-lock loops to meet your needs or determine why you
can~. Andrzej B. Przedpelskl, Electronic Design, September 13, 1978.
402
TLlHf5618-11
~
A Single-Supply PLL
The single-supply PLL is shown in Figure 6 as an example
of a simple circuit which is effective when battery operation
or single-supply operation is necessary. This circuit will
function accurately over a 10:1 frequency range from 1 kHz
to 10kHz, but will not respond as quickly as the basic PLL
of Figure 1. The reason is the use of the CD4046 frequency
detector. When an fiN edge occurs ahead of a f feedback
pulse, pin 13 of the CD4046 pulls up on C1 via R1 = 1 kn.
This current cannot be controlled or manipulated over as
wide a range as "11" in Figure 1. As a consequence, the
response of this PLL is never as smooth nor fast-settling as
the basic PLL, but it is still better behaved than most f-to-V
converters. As with the basic PLL, the detector feeds a cur-
rent to be integrated in C1 (and R2 provides the necessary
"Iead"). A 1 acts simply as a buffer for the R1, C1 integrator.
A3, optional, can provide a nicely filtered output. And A2
servos Q1 , drawing a current out of C6 which is proportional
to V2. Here the LM331 acts as a current-to-frequency converter, and f output is precisely proportional to the collector
current of Q1. As with the basic circuit, this PLL can be used
as a quick and/or quiet f-to-V converter, or as a frequency
multiplier. One of the most important uses of an f-to-V is to
demodulate the frequency of a V-to-f converter, which may
be situated at a high common-mode voltage, isolated by
photoisolators, or to recover a telemetered signal. An f-to-V
converter of this sort can provide good bandwidth for demodulating such a signal.
-Vs
INPUT
fREDUENCY
11
1
fiN _ _ _ _ _ _....l:14•••
V2
+I VOLTS
fULL SCALE
r - - -...- -....----_"""'-~~~LTS
fULL SCALE
-
c&
~{l'TALUIl
•••..._-.l~22IIM,.......- - -..
OUT
40.211
1'"
Tn
fREDUENCY
DIVIDER
IN
IOUTPUT
fULL::rl-...- -....I----.::j
L..-_........_ - J
NOTES:
- Ql
~
2N3565 OR 2N3904 HIGH BETA NPN
-Al,A2,A3
-
~
TLlH/5618-12
Y.LM324
ON CD4046, PINS I, 2, 4, 6, 7,10,11,12 ARE
NO CONNECTION
-
USE STABLE, LOW·T.C. PARTS FOR COM·
PONENTS MARKED'
-+vs
~
+7TO +15VDC
FIGURE 6. Single Supply Phase Locked Loop
403
z
N
....
C)
• The V-to-F converter uses A2 as an op-amp integrator, to get better than 0.01 % nonlinearity (max).
• G2 is recommended as an inverter, to invert the signal on the LM331's pin 3, avoid a delay, and improve
loop stability. (However, we never found any real improvement in loop stability, despite theories that insist
it must be there. Comments are invited.)
The precision PLL in Figure 7 acts very much the same as
the basic PLL, with refinements in various places.
• The flip-flops ·in the detector have a gate G1 to
CLEAR them, for quicker response.
• The currents which A 1 integrates are steered through
01, 02 and 03, 04 because transistors are quicker
then diodes, yet have much Ipwer leakage.
R2
lZ0k
""''''''''''"",--+VS
FREQUENCV AND
PHASE DETECTOR
ERROR INTEGRATOR
F INPUT--+-.I
SQUARE WAVE
OR PULSE TRAIN
.VS-_+....-
....
rI
I
I
OPTIONAL
Ik
ZZk
FREOURENCY
DIVIDER
-VS
FOUT
10kH,
FULL
SCALE
LM331
5k"
)
Zk"
RS
GAIN
ADJUST
+Vs
RIN
lOOk"
+Vs
11Il10
~
OPTIONAL
t-""''''''~''''¥<'''''+-·f 60k m~~
ll11n
-VS
~:T~~~'~~~:~~;:;!i~ NUTEO
ALL RESISTORS ARE ±111!1
ALL DIODES ARE lN914 OR lNtla
ALL NPN'S ARE SILICON. ZN3804 OR SIMILAR
ALL PNP'S ARE SILICON. ZN31111 OR SIMILAR
"/4 MMJ4CII OR C04011
A3.Al· LF3Il;11Z LF313.0R SIMILAR
AI' LF3111. LM3IIIA. OR SIMILAR
At- LF3Il. LMJ41C. OR ANV
.VB - +IZTO +11 VDC
-VS' -14T0 -IIVOC
Do-
TUHf6618-13
FIGURE 7. Precision PLL
404
~
This PLL has been widely used in testing of VFCs, as it can
force the LM331 to run at a crystal-controlled frequency (established as the F input), and the output voltage at VOUT is
promptly measured by a 6-digit (1 ppm nonlinearity, max)
digital voltmeter, with much greater speed and precision
than can be obtained by forcing a voltage and trying to read
a frequency. While at 10kHz, the advantages are clearcut;
at 50 Hz it is even more obvious. Measuring a 50 Hz signal
with ± 0.01 Hz resolution cannot be done (even with the
most powerful computing counter-timer) as accurately,
quickly, and conveniently as the PLL's voltage output
settles.
• A4 is included as an (optional) limiter, to prevent V1 from
ever going positive. This will facilitate quick startup and
recovery from overdrive conditions.
Also, in Figure 8, the wide-range current pump for the precision PLL is a "semiprecision" circuit, and provides an output
current proportional to - V1, give or take 10 or 15%, over a
3-decade range. The 22 MO resistors prevent the current
from shutting off in case - V becomes positive (probably
unnecessary if A4 is used). For best results over a full 3decade range (11 kHz to 9 Hz), do use A4, delete the four
22 MO resistors, and insert the (diode parallel to the 470
kO) in series with the RG as shown. This will give good
stability at all frequencies (although stability cannot be extended below 1/1500 of full scale without extra efforts).
r-----_-
100 atlc = 1 ",A and appear to match better than
their NPN counterparts. Current gain is less affected by temperature, resulting in a fairly flat bias current over temperature (Figure 9). At elevated temperature the sharp decrease
in bias current for VCM > V- is caused by the same substrate leakage that affects bi-FET op amps.
Protective resistors have been included in the input leads so
that currant does not become excessive when the inputs
are forced below the negative supply, forward biasing the
base tubs of the lateral PNPs.
5
Rl
~.
~
TL/HI7200-4
Figure 4. Op amp offset adJuatment
This complementary emitter follower arrangement provides
the necessary current gain without requiring the extra bias
voltage of the Darlington connection.
Base drive for the NPN oulputtransistor is initially supplied
by 012, but a boost circuit has also been added to increase
the available drive as a function of load current. This is accomplished by 024 in conjunction with a current inverter.
Drive for the PNP half of the output is somewhat more complicated. Again, a compound buffer, 015 and 016, is used,
although to maintain circuit balance rather than for current
gain. The signal proceeds through two inverters, 017 and
019, to obtain the correct phase relationship and DC level
shift before it is fed to the PNP oulputtransislor, 028.
This path has three common-emitter stages and, potentially,
much higher gain than the NPN side. The gain is equalized,
however, by the shunting action of 018-R19 and 021-R22
as well as negative feedback through 023.
When the output PNP saturates, 020 serves to limit its base
overdrive with a feedback path to the base of 017. As will
be seen, 020 is also important to floating-mode operation in
that it disables the PNP drive circuitry when the op-amp
output is shorted to V + .
Offset nulling is accomplished by connecting the balance
terminal to a variable voltage derived from the reference
output, as shown in Figure 4. Both the input stage collector
voltage and the reference are well regulated and have a low
temperature drift. The resistance of the adjustment potentiometer can be made very much lower than the resistance
looking back into the balance pin. Therefore, no matching of
temperature coefficients is required and offset nulling will
tend to produce a minimum-drift condition.
With 200 mV on the balance control, the balance range is
asymmetrical. Standard parts are trimmed to bring them into
the -1 mV to 8 mV adjustment range. Null sensitivity can
be reduced for low-offset premium parts by adding a resistor
on the top end of R1.
Proceeding through the circuit, the input stage is buffered by
vertical PNP followers, 03 and 04. From here, the differential signal is converted to single ended and fed to the base
of the second stage amplifier, 07.
This configuration is not inherently balanced in that the
emitter-base voltage of the PNP transistors is required to
match that of the NPNs. The final design includes circuitry
to correct for the expected variations.
15
-r--,...
~
0
...z>-
..,'"'"'"
...!!!'">-
the reference
A simplified version of the reference circuitry and internal
current regulator is shown in Figure 5. The design of the
band-gap reference is unconventional both in its configuration and because it compensates for the second-order nonlinearities in the emitter-base voltage as well as those introduced by resistor drift. Thus, the bowed characteristic of
conventional designs is eliminated, with better temperature
stability resulting.
VCM=V-.~
r-- r--.
The reference element iself is formed by 040 and 041, with
the output on the emitter of 041. The VeE component of the
output is developed across R30, while the ~ VeE component
is obtained by operating 041 at a much lower current density than 040. The output is made less sensitive to variations
in biasing current by the action of R29. Curvature correction
results from the different temperature coefficients of bias
current for the two transistors.
BIAL -
~CM~-
"'"
Vs = .20V
-15
0.6
l - t-0
-50 -25
OFFSET
I
0
25
50
75
~
100
6
The 200 mV reference voltage is fed to both the reference
amplifier and the internal current regulator. The reference
amplifier design is straight-forward, consisting of two stages
with an emitter follower output. Unlike the op amp, the output can only swing within 0.8V of the positive supply. This
should be kept in mind when deSigning low-voltage circuitry.
125
TEMI'fRATURE ('C)
TL/HI7200-3
Figure 3. Variation of Input current with temperature
From the collector of 07, the signal splits, driving separate
halves of the complementary class-B oUlput stage. The
NPN output transistor, 025, is driven through 013 and 014.
409
AN·211
'1-
REFERENCE
AMPLIfiER
",7
T
BIAS
BUSS
L
t
t t
REFERENCE
·1·
l_ l_
l_
r~~~
rm
(Oi3
(042
l
RZ&
20k
(ni2
·1
CURRENT
REGULATOR
L
l=
·1
alAS AND
STARTUP
~~
~R43
2Gk
1lA':AL I
~
I
......
Q54
L•
R44
I 1
880k
REFERENCE
OUTPUT
R39
~
Uk
o
r
052
R31
m
R34
4Ik
v-
4
1.
1
~
~
~
•
R32
2.~
I.
REFERENCE
FEEDBACK
I I
1 1 1 1
~=
1
R37~
4Ik
I
~R41
21k
~~ I
~::.
w
R3B
3Ik
TUH/7200-5
Figure 5. Simplified schematic of the reference and Internal current regulator
A minimal sink current (- 20 /LA) is supplied by 034. And
since the reference is not included in the thermal protection
control loop, conventional current limit is included on the
final circuit to limit maximum output current to about 3 mA.
and once in the linear region, the maximum change of terminal voltage is 0.15/ /Ls. This is illustrated in the plots of Figures 8 and 9. In general, high accuracy cannot be obtained
with switch frequencies above 100 Hz.
Hysteresis can be provided as shown in Figure 6 by feedback to the balance terminal. About 1 mV of hysteresis is
obtained for a 5V output swing. However, this disappears
near 10Hz operating frequency because of gain loss.
Figure 10 shows a flame detector that can drive digital circuitry directly. The platinum-rhodium thermocouple gives an
8 mV output at 800"C. This threshold is established by connecting the balance pin to the reference otuput.
The current regulator is also relatively uncomplicated. A
control loop drives the current source bias bus so that the
output of one current source (051) is proportional to the
reference voltage. The remaining current sources are
slaved into regulation by virtue of matching.
The remaining circuitry generates a trickle current for startup and biases internal Circuitry.
An analysis of the complete circuit would serve only to bring
into focus a multitude of detail such as second-order DC
compensation terms, minor-loop frequency stabilization,
clamps, overload protection, etc. Although necessary, these
particulars tend to obscure the principles being put forward.
So, having gained some insight into circuit operation, it is
appropriate to proceed to some of the novel applications
made possible with this new IC.
linear operstlon
The IC can also operate linearly in the floating mode. The
simplest examples of this are the shunt voltage regulator in
Figure 11 and the current regulator in Figure 12. The voltage
regulator is straightforward, but the current regulator is a bit
unusual in that the supply current of the IC flows through the
sense resistor and does not affect accuracy as long as it is
less than the desired output current.
It is also possible to use remote amplifiers with two-wire
signal transmission, as was done with the comparators. Remote sensors can be particularly troublesome when low-level analog signals are involved. Transmission problems include induced noise, ground currents, shunting from cable
capacitance, resistance drops and thermoelectric potentials. These problems can be largely eliminated by amplifying the signal at the source and altering impedances to levels more suitable for transmission.
floating comparators
The light-level detector in Figure 6 illustrates floating-mode
operation of the IC. Shorting the op-amp ouM to V + disables the PNP half of the class-B output stage, as mentioned earlier. Thus, with a positive input signal, neither half
of the output conducts and the current between the supply
terminals is equal to the quiescent supply current. With negative input Signals, the NPN portion of the output begins to
tum on, reaching the short circuit current for a few hundred
microvolts overdrive. This is shown in Figure 7.
Figure 7 also shows the terminal characteristics for the case
where the output is shorted to V- so that only the PNP side
can be activated. This mode of operation has not been so
thoroughly investigated, but it gives a slightly lower ON voltage at moderate currents and the gain is generally higher
below 70"C. With ON currents less than about 1 mA, the
terminal voltage drops low enough to disrupt the internal
regulators and the reference, producing some hysteresiS.
Further, there is a tendency to oscillate over about a 50 /LV
range of input voltage in the linear region of comparator
operation.
The above is not intended to preclude operation with the
output connected to V -, if there is a good reason for dOing
so. It is meant only to draw attention to the problems that
might be encountered.
Figure 13 is an example of a remote amplifier. It boosts the
output of a high-impedance crystal transducer and provides
a low impedance output. No extra wires are needed because DC power is fed in on the signal line.
Figure 14 is a remote Signal conditioner that operates in the
current mode. A modification of the current source in Figure
12, it delivers an output current inversely proportional to
sensor resistance. The output can be transmitted over a
twisted pair for maximum noise immunity or over a single
line with common ground if the signal is slow enough "that
sufficient noise bypass can be put on the line.
A current-mode Signal conditioner for a thermocouple is
shown in Figure 15. A thermocouple is in reality a two-junction affair that measures temperature differential. Absolute
temperature measurements are made by controlling the
temperature of one junction, usually by immersing it in an
ice bath. This complication can be avoided with cold-junction compensation, which is an absolute thermometer that
measures cold-junction temperature and corrects for any
deviation from the calibration temperature.
In Figure 6, the internal reference supplies the bias that determines the transition threshold. At crossover, the voltage
across the photodiode is equal to the offset voltage of the
op amp, so leakage is negligible. The circuit can directly
drive such loads as logiC circuits or silicon controlled rectifiers. The IC can be located remotely with the sensor, with
the output transmitted along a twisted-pair line. Alternatively, a common ground can be used if there is sufficient noise
immunity; and the signal can be transmitted on a single line.
It should be remembered that this particular design is fully
compensated as a feedback amplifier. As such it is not particularly fast in comparator applications. With low-level signals, delays a few hundred microseconds can be expected;
In Figure 15, the IC temperature sensor (81) generates an
output proportional to absolute temperature. This current
flows through R2, which is chosen so that its voltage drop
has the same temperature coefficient as the thermocouple.
Thus, changes in COld-junction temperature will not affect
calibration as long as it is at the same temperature as Sl.
In addition to powering Sl, the reference is used to generate an offset voltage such that the output current is within
411
r---.-+
100
...s tL F~Vlilllm ....
10
15
~.
::>
-
u.
....
::>
...
'"
V~~T = V·
----VOUT=V-
1.0
!;
i=±= f=
VIN
i
-50
-0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1A I .• 1.8
V+ -5V
v- =0
TAj o2fC
100
CD
CD
>
1\
\
I
;"'. 10050
i
10mV
\
Ismv_ I-
J
...
TUHI7200-7
Figure 7. Terminal Characteristics above and below
threshold
I
VOD=50mV
1110
10
1.0
ll-
I I'
-60
-0.2 0 0.2 OA 0.6 0.8 1.0 1.2 1.4 1.6 1.8
TIME (ml)
TIME (m.)
TUH/7200-B
TUHI7200-9
Figure 8. Comparator response times for various '.Input
overdrives
Figure 9. Comparator response times for various Input
overdrives
V+
5V
,J
PLATINUM*
RHODIUM
-'f;
P~OBE
TO MOS OR
TTL LOGIC
RI ,
200
'SOD C threshold Is establlshsd by connecting balanas to VREF.
TUHI7200-10
Figure 10. Flame detector
r---.... +
CI*
O.OlpF
..-.J\M.,--...- - - 4.... +VOUT =( I + ~ )
VREF
HI
I
_ (R2 + R3) VREF
OUTR1R3
RI
R2
R3
'required for capacitive loading
TUH17200-11
TUH/7200-12
Figure 11. Shunt voltage regulator
Figure 12. Current regulator
412
RZ
10M
operating limits for temperatures of interest. It is important
that the reference be stable because drift will show up as
signal.
The indicated output-current range was chosen because it
is one of the standards for two-wire transmission. With the
new IC, the dynamic range can be increased by a factor of
five in some cases (0.8 mA-20 mA) because the supply
current is low. This could be used to advantage with a unidirectional signal where zero must be preserved: the less the
offset required to put zero on scale, the less the offset-drift
error.
V'
t4
X
R3
1M
RI
1.1M
The circuit in Figure 16 is the same thermocouple amplifier
operating in the voltage mode. The output voltage range
was chosen arbitrarily in that there are no set standards for
voltage-mode transmission.
TLIH17200-13
Figure 13. Remote amplifier
The choice between voltage- and current-mode operation
will depend on the peculiarities of the application, although
+
V'
_-1
RI
715
1%
1--'~
RL
RI
RZ
TLIHI7200-14
Figure 14. Two-wire transmHter for variable-resistance
sensor
4V " VOUT " 20V
100
R4
RS
Zk
1%
1%
200"C " Tp " 700"C
-
r---------------~~--------._+
tapan trim
;Ieve/-shift trim
lOUT
SI
LMI34
'cold-Junctlon 111m
RI
1%
+
ALUMEL
PROBE
TLIH17200-16
With voltage-mode operation, the line resistance can cause
error because the DC current that powers the amplifier and
sensor circuitry must flow through it. Ground potentials, if
they cannot be swamped out with signal swing, would require that twisted pair lines be used. This is not so with
current mode.
An important consideration is that cable capaCitance does
not affect the loop stability of the current-mode amplifier.
However, large-amplitude noise appearing across the output can give problems. Figure 17 shows the noise rejections
of the LM10. The negative supply rejection applies in current-mode operations with the output connected to V+. The
rejection in this mode Is not overly impressive, but transmission can be reduced by bypassing the load resistor. This
done, noise slew limiting is the restricting factor in that excessive slew can give rise to a DC error. The maximum
200"C " Tp " 700"C
lmA,,10UT,,5mA
tgainlrim
1%
Figure 16. Voltage transmitter for thermocouple,lncludIng cold Junction compensation
current mode seems to be favored overall. If there is sufficient supply voltage, the dynamic range of both approaches
is about equal, provided the transmitter is capable of working at both low voltage and current. This situation could be
modified by the voltage and current requirements of the
sensor or conditioning circuitry.
715
CHROMEL
RZ*
IZO
RZ
100
1%
COLD
JUNCTION
COMP
R3
50
H&t
6.67
1%
TUHI7200-15
Figure 15. Current transmitter for thermocouple Including cold Junction compensation
413
~ r-------~--------------------------------------------------------------------------------_,
~
~
cc
With bridge sensors, these techniques not only reduce
noise problems but only require two leads to both power the
bridge and retrieve the signal.
noise 'amplitude that can be tol,erated for a 100 p.V input-referred DC error is plolled in Figure tB.These limits are not
to be pushed as error increases rapidly above them.
r-."-r--,,.--,..,--,---r----.
140·
The relevant circuit is shown in Figurs'19. The op amp is
wired for a high-im~ance differential 'input so as not to
load the bridge. The reference supplies the offset to put the
amplifier in the center of its operating range when the bridge
is balanced. It alsO: powers the bridge. The low voltage available from the reference regulator is ideal for driving wire
strain gauges that usually ~ave low resistances .
Another form of remote signal processing is shown in Figurs
20. A logarithmic conversion is made on the output current
of a photodiode to compress a four-decade, light-intensity
variation into a standard transmission range. The circuit is
balanced at mid-range, where R3 should be chosen so that
the current through it equals the photodiOde current. The
log-conversion slope is temperature compensated with R6.
Selling the reference output to 1.22V gives a current
through R2 that is proportional to absolute temperature, because of D1, so that this level-shift voltage matches the
temperature coefficient of R6. C1 has been added so that
large area photodiodes with high capacitance do not cause
frequency instabilities.
Figurs 2t shows a setup that optically measures the temperature of an incandescent body. It makes use of the shift
in the emission spectrum of a black body toward shorter
wavelengths as temperature is increased. Optical filters are
used to split- the emission spectrum, with one photodiode
being illuminated by short wavelengths (visible light) and the
other by long (infrared). The photocurrents are converted to
logarithms by 01 and 02. These are subtracted to generate
an output that varies as the log of the ratio of the illumination intensities. Thus, the circuit is sensitive to changes in
spectral distribution, but not intensity. Otherwise, the circuit
is quite Similar to that in Figure 20.
120
ii
3
z
100
.
80
fi
~
II:
!
''''!
60
40
10
100
Ik
10k
lOOk
1M
FREOUENCY (Hz)
TLlHI7200-17
Figure 17. Nolae rejection for the varloua elements of
the circuit
...
100
CMRR
PSRR+
~
co
c
!:;
.
..
10
&Vos IV
RIO
Zk
1%
I
R6
ZO
1%
TUH172DO-22
Figure 22, Precision thermocouple amplifier/transmitter
415
~ r-----------------------------------~----------------------------~----------------------_,
~
~
cc
F/{Jure 22 shows how a low-drift preamplifier can be added
to improve the measurement resolution of a thermocouple.
The preamp is powered from the reference regulator, and,
bridge feedback is used to bias the preamp input within its
common-mode range. COld-jllnction compensation is provided with the offset voltage set into A 1, it being directly
proportional to absolute temperature.
It Is also possible to make a negative regulator with this
device, as can be seEm from F/{JUre 24. A discrete transistor
is used to leve( shift the reference current. This increases
the minimum operating voltage to about 1.8V.
Output voltage cannot be reduced below 0.85V because of
the common-mode limit of the op amp. The minimum inputoutput differential is equal to the voltage across R1 plus the
• saturation voltage of 01, about 400 mY.
The maximum drift specification for the preamp is
0.2 ",VI"C. For this particular circuit, an equal drift component would result for 0.004 %I"C on the reference,
0.001 %I"C mismatch on the bridged-feedback resistors
(R2-R4) or 3 p.VI"C on the op amp offset voltage. The op
amp drift might be desensitized by raising the preamp gain
(lowering R7-R9), but this would require raising the output
voltage of the reference regulator and the minimum terminal
voltage.
It is necessary that 01 have a high current gain, or line
regulation and thermal drift will be degraded. For example,
with a nominal current gain of 100, a 1% drift will be introduced between - 55°C and 125°C. With the device specified, drift contribution should be less than 0.3% over the
. same range; but operation is limited to 30V on the input.
Floating-mode operation can also be useful in regulator applications. In Figure 25, the op amp controls the tum-on
voltage of the pass transistor in such a way that it does not
see either the output voltage or the supply voltage. Therefore, maximum voltages are limited only by the external
transistors.
In this application, the preamp is run at a lower voltage than
standard parts are tested with, and the maximum supply
current specified is high. However, there should be no problem with the voltage; and a lower, maximum supply current
can be expected at the lower voltage. Even so, some testing may be in order.
A three-stage emitter follower is used for the pass transistor
primarily to insure adequate/:llas voltage for the IC under
worst-case, high-temperature conditions. With lower output
currents 02 and R4 could be replaced with a diode.
regulators
The op amp and voltage reference are combined in Figure
23 to make a positive voltage regulator. The output can be
set between 0.2V and the breakdown voltage of the IC by
selecting an appropriate value for R2. The circuit regulates
for input voltages within a saturation drop of the output (typically 0.4V @ 20 mA and ().15V @ 5 mAl. The regulator is
protected from shorts or overloads by current limiting and
thermal shutdown.
_----+-----...
-GROUNO
> ...-+- VOUT' -10V
Typical regulation is about 0.05% load and 0.003%1V line.
A substantial improvement in regulation can be effected by
connecting the op amp as a follower and setting the reference to the desired output voltage. This has the disadvantage that the minimum input-output differential is increased
to a little more than a diode drop. If the op amp were connected for a gain of 2, the output could again saturate. But
this requires an additional pair of precision resistors.
'electrolytic
The regulator in F/{Jure 23 could be made adjustable to zero
by connecting the op amp to a potentiometer on the reference output. This has the disadvantage that the regulation
at the lower voltage settings is not as good as it might otherwise be.
OUT •
(1 + Rl~ )'Y
'"
1-. . .- - - - - VIN ,,;-ID.5V
TLlH/7200-24
Figure 24. Negative regulator
Load regulation is better than 0.Q1 %. Worst-case line regulation is better than ± 0.1 % for a ± 1OV change in input
voltage. If the op amp output were buffered with a discrete
PNP, load and line regulation could be made essentiallyiJerfect, except for thermal drift.
C2
O.01J.1F
V
.
HI
2k
Current limiting, although not shown, could easily be provided by the addition of a sense resistor and an NPN transistor.
A foldback characteristic could be obtained with two more
resistors.
REf
A fully adjustable voltage and current regulator is shown in
Cl*
25.F
Figure 26. A second IC (A2) is added to provide regulation in
the current-limit mode. Both the regulated voltage and the
current can be adjusted close to zero.
'electrolytic
The circuit has a tendency to overshoot when a short circuit
is removed. This is suppressed with 02, R5 and C3, which
limit the rate at which the output cl\O rise. Low-level oscillations at the dropout threshold are eliminated with C2 and
R4.
':"
TL/HI7200-23
Figure 23. A~iustable positive regulator
The current-limit amplifier takes about 100 p.s to respond to
a shorted output. Therefore, 06 has been added to limit the
peak current during this interval.
416
~
N
....
r--...- -....- -...- V IN
....
..-------4_-~
~-+---
....
VOUT =50
R2
250k
1%
~--~---------------. . . GROUNO
TLlHI7200-25
Figure 25. Bootstrapped regulator
. . . - - - - - - - - -. . .- -. . . .- -. . .-
VIN
RIO
3.3k
C2
0.01 "F
R4
RS
47k
390
D2
lN457
R7
0.1
R2
10k
Cl
0.001 "F
Dl
~--~-----e-----~~-----Vo~
IN457
C3
O.022"F
R3*
SOOk
O-SOV
0-IA
C4
50"F
..--------..---------------------------------..
~--t--e------'VOUT = 10- 4 R3
-------COM
Figure 26. Detailed schematic of an adjustable Yoltage and current regulator
417
TLlH17200-27
With high-voltage regulators, powering the IC through the
drive resistor for the pass transistors can become quite inefficient. This is avoided with the circuit in Figure 27. The supply current for the IC is derived from Q1. This allows R4 to
be increased by an order of magnitude without affecting the
dropout voltage.
Rgure 28 shows a more detailed circuit for a high-voltage
regulator. Foldback current limiting has been added to proteet the pass transistors from blowout caused by excessive
heating or secondary breakdown. This limiting must be fairly
precise to obtain reasonable start-up characteristics while
conforming to worst case specifications for the transistors.
This accounts for the complexity of the circuit.
Selection of the output transistors will depend on voltage
requirements. For output voltages above 200V, it may be
more economical to cascade lower-voltage transistors.
. . - - -...- - _....-V'N >204V
VOUT=~VREF
R1
...-------VruT·200V
L-_~--~----
C2
+
10~F
L-----_~--------------~---------COMMON
TL/HI7200-26
Figure 27. High-voltage regulator
r--------------..
..
---_~----
--2&OV~V'N S3&OV
05
IN4DD2
O'IN4002
L-__~---e_----e_----+_----..----------_._----..---VO~·2&oV
6mA~louT S l&OmA
R3
2k
1%
+
C2
1000pF
C1
200pF
C3
2~F
RZ
2.5M
I"
TLlHI7200-29
Figure 28. High voltage regulator with foldback current limit
418
r-----------------------------------------------------------~~
The output current is sensed across R8. This is delivered to
the current limit amplifier through R7, across which the foldback potential is developed by R6 with a threshold determined by 04. The values given limit the peak power below
20W and shut off the pass transistors when the voltage
across them exceeds 310V. With unregulated input voltages
above this value, start-up is initiated solely by the current
through R5. 04 is added to provide some control on current
before A2 has time to react.
The design could be considered overly conservative, but
this may not be inappropriate considering the start of the art
for high-voltage power transistors. Their maximum operating
current is in the tens of milliamperes at maximum voltage.
Cutting off the power transistor before the maximum inputoutput voltage differential is reached can cause start-up
problems, depending on the nature of the load (those that
tend toward a constant-current characteristic being worst).
If a tighter design is' required for start-up, the values of R6
and 04 can be altered. In addition, R5 can be lowered, although it may be necessary to add a PNP buffer to A2 in
place of 03.
The leakage current of 03 can be more than several milliamperes. That is why a hard turn-off is provided with 02.
The circuit is stable with an output capaCitor greater than
about 2 p.F. Spurious oscillations in current limit are suppressed by C2 and R4, while a strange, latch-mode oscillation coming out of current limit is killed with C1 and R1.
Switching regulators operating directly from the power lines
are seeing increased usage not only because of the reduced weight and size when compared to a 60 Hz transformer but also because they operate over a wide voltage
range giving a regulated output with reasonable efficiency.
Electrical isolation of the load is generally required in these
applications for reasons Qf safety. Therefore, if precise regulation is needed on the secondary, there must be some
way of transmitting the error signal back to the primary.
Figure 29 shows a design that provides this function. The IC
serves as a reference and error amplifier, transmitting the
error Signal through an optical coupler. The .Ioop gain may
be controlled by the addition of R1, and C1 and R5 may be
added to develop the phase lead that is helpful in frequency
stabilizing the feedback.
voltage level indicators
In battery-powered circuitry, there is some advantage to
having an indicator to show when the battery voltage is high
enough for proper circuit operation. This is especially true
for instruments that can produce erroneous data.
The battery status indicator drawn in Figure 30 is designed
for a 9V source. It begins dimming noticeably below 7V and
extinguishes at 6V. If the warning of incipient battery failure
is not desired, R3 can be removed and the value of R1
halved.
A second circuit that also regulates the current through the
light-emitting diode is shown in Figure 31. This is important
so that adequate current is available at minimum voltage,
but excessive current is not drawn at maximum voltage.
Current regulation is accomplished by using the voltage on
the balance pin (5) as a reference for the op amp. This is
controlled at apprOximately 23 mV, independent of temperature, by an internal regulator. When the voltage on the reference-feedback terminal (8) drops below 200 mV, the reference output (1) rises to supply the feedback voltage to the
op amp through 02, so the LED current drops to zero.
The minimum threshold voltage for these circuits is basically
limited by the bias voltage for the LEOs. Typically, this is
1.7V for red, 2V for green and 2.5V for yellow. These two
circuits can be made to operate satisfactorily for threshold
voltages as low as 2V if a red diode is used. However, the
circuit in Figure 31 is preferred in that difficulties caused by
voltage change across the diode biasing resistor are eliminated.
.._---..----1P-- +
RI
660k
R6
51<
R2
47.8k
1%
R4
1.5k
R3
680k
TL/HI7200-30
Figure 30. Battery status Indicator
r---.----+
DC I
FEEDBACK TO
SWITCH
CONTROLLER
R2
HOk
RE::~"ED ~'''''''''''''''
OUTPUT
01
R4
/1/
1.8"
I"
tcontrols "loop gain"
R3
10k
TLlH/7200-28
'optionallrequency shaping
Figure 29. Isolated sensor for an off·llne switching
regulator
RI
4.7
TLlHI7200-31
Figure 31. Battery level Indicator with regulated LED
current
419
N
::::
.... r------------------------------------------------------------------------------------------,
When operating with a single cell, it is necessary to incorpor----~----~---v+
~
~
cc
rate switc;hing circuitry to develop sufficient voltage to drive
the LED. A circuit that accomplishes this is drawn in Figure
32. Basically, it is a voltage-controlled asymmetrical multivibrator with a minimum operating threshold given by
R4(R1 + R2)
(1)
VTH = R1 (R3 + R4) VREF
VTH' =·15V
01
Cl
20~F
Above this threshold, the flash frequency increases with
voltage. This is a far more noticeable indication of a deteriorating battery than merely dimming the LED. In addition, the
indicator can be made visible with considerably less power
drain. With the values shown, the flash rate is 1.4 sec- 1 at
1.2V with a 300 IJ-A drain and 5.5 sec- 1 at 1.55V with
800 p.A drain. Equivalent visibility for continuous operation
would require more than 5 mA drain.
The maximum threshold voltage of this circuit is limited because the LED can be tumed on directly through R5. Once
this happens, the full supply voltage is not delivered to R2,
which is how the threshold is determined. This problem can
be overcome with the circuit illustrated in Figure 33. This
design repositions the indicator diode, requiring an input
voltage somewhat greater than the diode bias voltaged
needed.
above 6V and
belowl5V
TUHI7200-33
Figure 33. Doubl_nded voltage monitor
This circuit has the added feature that it can sense an overvoltage condition. The lower activation threshold is given by
equation (1), but above a threshold,
,_
R4 (R1 + R2) VREF
(2)
VTH - R1 (R3 + R4) - R3 (R1 + R2)'
oscillation again ceases. (Below VTH the op amp output is
saturated negative while above VTH' it is saturated positive.)
The flash rate approaches zero near either limit.
The minimum/maximum limits possible with this circuit
along with the possibility of estimating the proximity to the
limit and the low power drain (- 500 /LA) make it attractive
for a variety of simple, low-cost test equipment. This could
include everything from the measurement of power-line voltage to in-circuit testers for digital equipment.
H2
62011
meter circuits
One obvious application for this IC is a meter amplifier. Accuracy can be maintained over a 15°C to 55°C range for a
full-scale sensitivity of 10 mV and 100 nA using the design
in Figure 34. In fact, initial tests indicate negligible zero drift
with1 mVand 10 nA sensitivities, although balancing Is troublesome with low-cost potentiometers. Offset voltage error
is nulled with R5, and the bias current can be balanced out
with R4. The zeroing circuits operates from the reference
output and are essentially unaffected by changes in battery
voltage, so frequent adjustments should not be necessary.
flashes about 1.2V
rate increases with
voltage
TUHI7200-S2
Figure 32. Undervoltagelndlcator for single call
R2
HI
lOOk
1%
INPUT
flash rate Increases
HI
11011
r-----"'--V+
10mV.l00nA
~=6V
8.6M
1%
---t----.. .
FULL·SCALE .......
01
lN457
02
lN457
H5
+
BJ~
~--...-
....--<'r:Sl
Figure 34. Meter amplifier
420
81
1.5V
TUHI7200-34
r--------------------------------------------------------------------.~
Under overload conditions, the current delivered to the meter is kept well in hand by the limited output swing of the op
amp. The same is true for polarity reversals. Input clamp
diodes protect the circuit from gross overloads.
Total current drain is under 0.5 mA, giving an approximate
life of 3-6 months with an "AA" cell and over a year with a
"0" cell. With these lifetimes an ON/OFF switch may be
unnecessary. A test switch that converts to a battery-test
mode may be of greater value.
reference veltage. This done, temperature compensation
cen be obtained by making the resistor in series with the
meter a copper wire-wound unit
If this design is to be used for photography, it is important to
remember that silicon photodiodes are sensitive to near infrared, whereas ordinary film is not. Therefore, an infraredstop filter is called for. A blue-enhanced photodiode or an
appropriate correction filter would also give best results.
An electronic thermometer deSign, useful in the range of
-55°C to 150"C, is shown in Figure 36. The sensor, 81,
develops a current that is proportional to absolute temperature. This is given the required offset and range expansion
by the reference and op amp, resulting in a direct readout in
either °C or of.
If the meter amplifier is used in building a multimeter, the
internal reference can also be used in measuring resistance. This would make the usual frequent recalibration with
falling cell voltage unnecessary.
A portable light-level meter with a five-decade dynamic
range is shown in Figure 35. The circuit is calibrated at midrange with the appropriate illumination by adjusting R2 such
that the amplifier output equals the reference and the meter
is at center scale. The emitter-base voltage of Q2 will vary
with supply voltage; so R4 is included to minimize the effect
on circuit balance. If photocurrents less than 50 nA are to
be measured, it is necessary to compensate the bias current of the op amp.
The logging slope is not temperature compensated. With a
five-decade response, the error at the scale extremes will
be about 40% (a half stop in photography) for a ± 18°C
temperature change.
If temperature compensation is desired, it is best to use a
center-zero meter to introduce the offset, rather than the
r_--------....-----
V'>IV
51
LMI34
'trim for span
ttrim for zero
R3*
R2t
Uk
1%
732
1%
R4
Uk
TLlHI7200-36
Figure 36. ElectroniC thermometer
1"""4t--....- - . - -
~
+ I.1VS v' S2V
Dl
TLlHI7200-35
Figure 35. Logarithmic light-level meter
421
Z
N
....
....
..-
i
r------------------------------------------------------------------------------------------,
Although it can operate down to 1V with better than 0.5°C
accuracy, the LM134 is not tested below 1.5V. Maverick
units were observed to develop a 1°C error going from 1.5V
to 1.2V. This should be kept in mind for high-accuracy applications.
The thermocouple transmitter in F/{/ure 15 can easily be
modified to work with a meter if a broader temperature
range is of interest. It would likewise be no great problem
adapting resistance or thermistor sensors to this function.
This is' illustrated with ·the microphone amplifier shown in
Figure 38. The reference, with a 500 kHz unity-gainbendwidth, is used as a preamplifier with a gain of 100. Its output
is fed through a gain-control potentiometer to the opamp
which is connected for a gain of 10. The combination gives
a 60 dB gain with a 10kHz bandwidth, unloaded, and 5 kHz
loaded at 500.0.. Input impedance is 10 k.o..
Potentially, using the reference as a preamplifier in this
fashion can cause excess noise. However, because the reference voltage is low, the noise contribution, which adds
root-mean-square, is likewise low. The input noise voltage in
this connection is 40-50,nV 1.JHz, about equal to that of the
op amp.
One point to observe with this connection is that the signal
swing at the reference output is strictly limited. It cannot
swing much below 150 mV nor closer than 800 mV to the
supply. Further, the bias current at the refer!ilnce feedback
terminal lowers the output quiescent level and generates an
uncertainty in this level. These facts limit. the maximum
feedback resistance (A5) and require that A6 be used to
optimize the quiescent operating voltage on the output.
Even so, the fact that limited swing on the preamplifier can
reduce maximum output power. with low settings on the gain
control must be considered.
In this deSign, no DC current flows in the gain control. This
is perhaps an arbitrary rule, designed to insure long life with
noise-free operation. If violations of this rule are acceptable,
A5 can be used as the gain control with only the bias current for the reference amplifier «75 nA) flowing through the
wiper. This Simplifies the circuit and gives more leeway on
getting sufficient output swing from the preamplifier.
The circuit in F/{/ure 38 can also be modified to provide twowire transmission for a microphone output.
audio circuits
As mentioned earlier, the frequency response of the LM10
is not as good as might be desired. The frequency-response
curve in Figure 37 shows that only moderate gains can be
realized in the audio range. However, considering the reference, there are two independent amplifiers available, so
that reasonable overall performance can be obtained.
140
120
iii
3
z
......;;;:
...;:!:
...
co
100
80
TA = 25"C
- ~ GAI~
.......
zo
>
P·T~ "'"-
=
-20
200
:
40
"
J'
i
"'\
...........
..
PI
:I:
!
......
60
260
'"
a
150
I
'"
m
,~
100
~
-40
50
0.1
1.0
10
100
lk
10k lOOk 1M
FREQUENCY (Hz)
TLlHI7200-37
Figure 37. Open loop frequency response
_ _ _":':'_ _ _ _,..VS
...
R9
I.5V
1M
loUT - 68011
85kHz
Rl
6.2M
R7" C3
10k 0.47 JAr
R2
.}
6.2M
GAIN
-
·maxgain trim
-
-
Figure 38. Microphone amplHler
422
Av" lk
11 - 100 Hz
12 - 5kHz
RL - 500
TLlHI7200-38
r----------------------------------------------------------------.~
conclusions
The applications described here show that some truly
unique functions can be performed by the LM10 because of
the low-voltage capability and floating mode operation.
Among these are accurate, two-terminal comparators that
interface directly with most logic forms. They can also drive
SCRs in control circuits using low-level sensors like photodiodes or thermocouples, although this was not explored
here.
Two-wire transmitters for analog signals were shown to
work with a variety of transducers, even to the extent of
remotely performing computational functions. These might
be used for anything from a microphone preamplifier to a
strain gauge measuring stress at some remote location in
an aircraft. The power requirements of this IC are modest
enough to insure a wide dynamic range and permit operation with lower-voltage supplies.
The IC also proves to be quite useful in regulator circuits, as
might be expected from a combined op amp and voltage
reference. It makes an efficient series regulator at low voltages. And as a low-level, on-card regulator, it offers greater
precision than existing devices. It is also easily applied as a
shunt regulator or current regulator.
transistors, because the control circuit sees, at most, a couple volts. Therefore, output voltages of several hundred
volts are entirely practical.
A few examples were given of amplifiers and signal conditioners for portable instruments. Emphasis was placed on
single-cell operation as this gives the longest life at lowest
cost from the smallest power source. The IC is well suited to
single-supply operation, where it can be used in any number
of standard applications. This can be put to use in digital
systems where some linear functions must be performed.
The availability of a reference allows precise level shifting or
comparisons even when the supply is poorly regulated. The
reference can also be used to create an elevated pseudoground so that split-supply techniques can be used.
Even when split supplies are available, the increased output
capability (40V @ 20 mAl coupled with lower power consumption could well recommend the LM10. This is com. bined with the more satisfactory fault protection provided by
thermal limiting.
In the floating mode, it operates with the precision required
acknowledgement
The authors would like to thank Dick Wong for his assistance in building and checking out the applications described
here.
of laboratory supplies, as either a voltage or current regula-
references
tor. Maximum output voltage is limited only by discrete pass
1. R. J. Widlar, "Low Voltage Techniques," IEEE J. SolidState Circuits, Dec. 1978.
*See Addendum that follows
this Application Note.
423
Z
~
.....
.....
National Semiconductor
Technical Paper 14
Low Voltage Techniques*
Robert J. Widlart
Apartado Postal 541
Puerto Vallarta, Jalisco
Mexico
Abstract. A mlcropower operationsl smplifier is d8SCribBd
thst will operate from s total supply voltsge of 1. 1V. The
complementary Clsss-S output can swing within 10 mVof
the supplies or deliver ±20 mA with O.4V ssturation. Common-mode. range includes V-, fscilitsting single-supply 0peration. Otherwise, DC performsncs comperes fsvorably
with thet of the LM108. An sdjustable-output voltage referencs is slso presented that uses s new technique to eliminate the bow ususlly found in the temperature chsracteristics of the bsnd-gsp reference. Minimum supply is 1 V. snd
typicsl drift is 0.002%/°C.
introduction
The intrinsic operating voltage limit of bipolar ICs is only
100-200 mV greater than the emitter-base voltage of the
transistors. To date, this limit has been pushed only with
digital circuitry and relatively simple linear devices. This paper will deal with techniques for fabricating such devices as
operational amplifiers, comparators, regulators and voltage
references that work from a voltage as low as that supplied
by a single nickel-cadmium cell.
Field-effect transistors have been considered for low-voltage applications because their operating voltage can theoretically be made less than that of bipolar transistors. Although their transconductance equals .that of bipolar devices at very-low currents, it is considerably less even at moderate current densities. This limits FETs to such functions as
input stages where the operating current is relatively low
and well controlled.
A combined op amp, voltage reference and reference amplifier was chosen as a design example. A functional diagram
is given in Figure 1. This configuration will serve to demonstrate that the usefulness of low-voltage operation goes beyond battery-powered equipment. It can be used in a floating mode, independent of fixed supplies. This is illustrated
both by the floating voltage regulator in Figure 2, where the
IC operates from the drive voltage to the pass transistors,
and the remote comparator in Figure 3, where the IC functions as a 2-terminal device, driving TTL logic directly. A
wide range of similar applications have been developed and
are discussed elsewhere. 1
BALANCE
OUTPUT
REFERENCE
FEEDBACK
r---~-----+~----~~~
1
REFERENCE
OUTPUT
REFERENCE
1.-._______....._ _. . ......;::_
v-
TUH/872S-1
Figure 1_ Functional diagram of the design example
'Reprinted from IEEE Jcumal of Sofid.SIate CIrcuits, December, 1978.
...--....-
.....- vlN >53V
~--t---~--------~---+-Vmrr=s~
Rl
2k
R2
SOOk
+
Cl
1
25
TUH/8723-2
Figure 2. High voltage regulator with bootstrapped control amplifier
v+
Dl
~
A
HI
2DDk
-i"
BAlE
am
H2
4711
TL/H/8723-S
Figure 3. Light level detector driving TTL dlreclly over
2-wire line
Some small advantage might be gained by limiting operation
to low voltages. This is overshadowed by the benefits of
making a general-purpose IC. Therefore, it was decided to
use standard proceSSing with maximum operating voltages
limited only by the BVCEO of the transistors (50V-60V).
lon-implanted resistors were ·incorporated to obtain the necessary high values for micropower operation. They also
have the advantage that, with proper deSign, the speed/
power tradeoffs can be determined at the final stages of
processing by varying the implant dose. However, the advisability of doing this on a production basis has yet to be
established.
operational amplifier design
A simplified schematic of the op amp is given in Figure 4.
Lateral PNP transistors are used on the input because this
is the easiest way to secure operation at common-mode
voltages equal to the negative supply voltage. Processing
that yields typical PNP current gains greater than 100 at low
tThls work was performed under conlrae! 10 National Semiconductor Corporation, Sente Clara, CalHornia.
424
currents has been in production for nearly 10 years. These
lateral transistors also have relatively constant current gain
over temperature, giving lower bias-current drift than NPNs.
amplifier is connected as a follower, this prevents false outputs when the common-mode limit is exceeded. in normal
operation, the low-level leakage from the auxiliary collector
is evenly divided between the input-stage collectors because the voltage drop across R4 is small.
An extra emitter on 02 working with 018 performs a similar
function when the negative common-mode limit is exceeded
on the inverting input, insuring that the output will be in positive saturation. The non-inverting input is also arranged to
give a proper output when the input is driven belOW V-.
Protective resistors have been included in the input leads so
that current does not become excessive when the inputs
are forced below the negative supplies, fonvard biasing the
base tubs.
Offset nulling is accomplished by connecting' the balance'
terminal to a variable voltage derived from the reference
output. Both the input-stage current and the reference are
tightly regulated over temperature, and the resistance of the
adjustment potentiometer ,can be 'made very much lower
than the resistance looking back into the balance pin.
Therefore. offset nulling can produce a mini ll1 !Jm-drift condition.
Proceeding through the circuit, the input stage is buffered by
vertical PNP followers, 03 ,and 04. This differential signal is
converted to single ended by 05 and 06 and fed to the
base of the second-stage amplifier 07.
As mentioned earlier, the optimum collector current of 013
will depend on the VeE difference between NPN and PNP
transistors (09-010 and 07-013), This is compensated by
generating a similar difference current with 021 and 022
then processing it with 019, 017 and'015 to generate the
required complement in the collector circuit of 013.
The output stage has been designed to deliver a minimum
output current of ± 20 mA with a typical saturation voltage
of ±0.4V. Conventional' current limiting cannot be used
without significantly increasing the saturation voltage. Since
the current gain of lateral PNPs falls off severely at high
current and high temperature, it is only necessary to limit the
driver current. This is done with R42 and R43, with 044
insuring that supply current does not become excessive if
the BVCEO of 045 is exceeded on supply transients.
Current limit for the NPN side is done with 051, 053 and
'associated circuitry. In addition, 049 and 052 have been
added to limit the over boost, should It become larger than
,can be handled by 035.
This configuration is not inherently balanced in that the
emitter-base voltage of the vertical PNPs is required to
match that of the NPNs. As will be seen, the final circuit
does include circuitry to correct for the expected variations.
From the collector of 07, the signal splits, driving separate
halves of the complementary Class-B output stage. The
NPN output transistor, 025, is driven through 0,13 and 014.
This complementary emitter follower arrangement provides
the necessary curr'i!nt gain wit!:lout requiring the extra bias
voltage of a Darlington connection. This is essential in real-'
izing minimum-voltage operation.
Base drive for the NPN output transistor, is initially supplied
by 012, but a boos~ circuit has been added to increase the
available drive as a function of load current. This is accomplished with 024 in conjunction with a current inverter. The
inclusion of R23 prevents gros$ over boosting.
The maximum operating voltage and output current of this
device are high enough that current limiting cannot be expect8d to prevent excessive die temperature, especially
with worst-case conditions. Therefore, thermal overload
protection has been provided., Die temperature is sensed
with 025, and 026 introduces hystereSis into the limiting
characteristic. The cut out temperature is designed to be
165°C, with operation resuming when the die cools to
155°C. The NPN and PNP halves are shut off by 027 and
,029, respectively.
Output stage quiescent current is determined by the voltage
across R16 and various device geometries. The current is
stabilized for varying supply voltage by connecting 033 in
cascode with 030 and by the addition of 031 and 032,
which tend to compensate for the collector voltage sensitivi'
ty of emitter-base voltage.
The boost amounts to controlled positive feedback. It does
tend to reduce dead zone and Unearize gain. Excess boost
current is absorbed by 014, which presents a low enough
drive impedance sp that the vQltage transfer fUnction from
its base does not exhibit a negative-gain characteristic.
Considerable experience With this and similar boost circuits
shows that they do not unfavorably alter frequency re:
sponse, at least below a few megahertz.
Drive for the PNP half of the output is somewhat more complicated. Again, a compound buffer, 015 and 016, is used,
although to maintain circuit balance rather than for current
gain. The signal proceeds through two inverters, 017 and
019, to obtain the correct phase relationship and DC level
shift, before it is fed to the PNP output transistor, 028.
At temperatures approaching thermal limit, 040 must operate beyond the threshold of saturation. The addition of 039,
.which is actually a lateral PNP collector ring surrounding the
base of 040, produces a voltage drop across R34 to compensate for the drop across R35 caused by excess base
current.
This path has three common-emitter stages; and, potentially, much higher gain than the NPN side. The gain is equalized, however, by the shunting action of 018-R19 and 021R22 as well as negative feedback through 023.
frequency compensation
With feedback amplifiers,the ability to frequency compensate a particular design is generally the bottom line in determining its usefulness. Considering the number of stages involved and the fact that the drive paths for the PNP and
NPN output transistors are entirely different, one might rightly conclude that frequency compensation would be difficult.
As much of the frequency compensation network as can be
explained in a straightforward manner is shown in the simplified schematic of Figure 4. Overall compensation is provided by a MOS capacitor, C2, between the output and the
collector of an input transistor. Within this loop, a diffused
capaCitor, C1, rolls off the gain of 07, breaking back out
where Xcl = R6.
When the output PNP saturates, 020 serves to limit its base
overdrive with a feedback path to the base of 017. This is
also important to the floating-mode operation of Figures 2 '
and 3 in that it disables the PNP drive circuitry when the op
,
amp output is connected to V+. ' "
The complete schematic of the operational amplifier in Figure 5 shows the remaining deSign featutes. The lower.' collector on 01 is outside the normal collector. Its current is
quite low until the positive common-mode limit is exceeded,
saturating the normal collector of 01. The auxiliary collector
picks up the re-injected current in saturation, which is routed
through Q4 to the collector of 03. When, for example, the
425
Addendum to AN·211
,
,
"
,
"
,,7y+
R22
Rll
2tk
~
t:f WI
~
2.5k
.... ". I
t:f ....
....
:~~
UZZ " .
H2O
2tk
i.5pA
~
t
5pA
+
t 5pA
+10pA
+5pA
__-+--+--..,r.
Rl
4k
':J
.I
•
R7
15k
•
I
'I
I:Q28
P
OUTPUT
I [" Q15
RID
10K
INPUTS· R2
4k
I
+40pA
RS.
ll111k
BALANCE
&
&.
&
&
&
Cl
&
1
&.
I
1
&.
I
I
I
I
I
' 1 ' • v-
.108
TLlHl8723-5
Figure 4. EI8entIaI detaIIa of the op-amp
T
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427
8
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al
I
A tally of the compensation capacitance for the entire circuit
gives a total value of 1000 pF. Nearly all of this is diffused
emitter-isolation capacitance (-1 pF/mil2), and most is diffused into the isolation walls, requiring no extra die area.
The reverse;bias on diffused capacitors is less than a diode
drop, minimizing the' effect of soft junctions. This is but one
of the advantages of a design where most of the circuit sees
only low voltage.
Referring again to the complete schematic, it can be seen
that things are not really that simiple. The function of the
feed-forward capacitors, C7 and C9, seems obvious. But
remaining compensation components were lidded as a result of breadboard tests which checked the circuit over temperature with full range of load currents and operating voltages, while varying the resistive and reactive components of
load impedance.
.
A detailed theoretical analysis of the compensation seems,
overly complicated, considering the number of minor feedback loops involved. This conclusion is ~upported by' the
fact that impedance levels in portions of the circu,it vary considerably with load current and so does the effect of the
frequency-shaping circuits.
Results show the circuit to be stable. For one, no '$ignificant
differences were found between the breadboard and the IC.
This is not overly surprising considering tile frequericies involved. Further, varying the sheet resistance of the il'11plant
resistors over a 5:1 range showed only that higher resistors
made slower amplifiers. Varying NPN curren1gain over a 4:,
range had little effect on AC characteristics.
Figure 6 is a plot of the open-loop frequency-phase plot of
the amplifier. It can be seen that the response does ncit
exactly follow a 6 dB/octave curve. In voltage follower applications, the excess phase shift, will cause about :3 dB
peaking around 35 kHz. This is of little consequence in that
the circuit is not intended 'for operation above the audio
range. What is important is that there are'rio stability problems for capacitive loads in excess of 1000 pF over the'
entire operating range of the device. This is n1ustrated by
, '
the plot in Rgure 7 . "
140
I
120
;;;
:a
z
..
80
C
60
co
40
co
2G
~
f-
1110
~ .....GAI~
;l!
!
2lIO
:
i
~ Lr( ,
-20
~,
"
.......
1.0
10
100
lk
li
lliG
.,!;
i
1110
il
Drift-curvature correction is obtained by maintaining the collector current of 071 nearly constant while that of 072 varies directly as temperature. This makes the reference output
rise at a rllte increasing with temperature. Resistor drift and
emitter-base voltage non:linearities have the opposite effect. Near-exact cancellation can, be obtained with the proper tap on R64/R66.
.'"
50
-40
0.1
The collector curren~ of 072 is essentially the output current
of the top'60llector on 068 less the current through the
R62-R~4-R66 divider. If the current-source current (068) is
invariant with temperature and the divider current varies as
, emitter-base voltage, the collector current of 072 can be
made proportional to absolute temperature. This done, the
value of R61 can be set so that the voltage on the collector
of 072 does r:Jot change appreCiably for small changes in
current-source current.
2&0
'
F= .!T~
Ignoring the voltage drop across R61 for the moment, the
,r;eference voltage developed at the emitter of 071 is equal
to the voltage drop' across R62 .plus the difference in the
emitter-base voltages of 071 and 072. The former component is proportional to the emitter-base voltage of 072 and
has Ii negative temperature coefficient while the latter has a
positive temperature coefficient. First order temperature
compensation can be obtained by adding these voltages in
the proper proportions.
TA -25·C
~
>
reference and Internal regulators
The reference and the internal biasing circuitry are shown in
Figure 8. The deSign of the band gap reference2 (using 071
a'nd 072) is unconventional in its configuration and because
it compenslltes for the second-order nonlinearities In the
emitter-base voltage as well as, those introduced by the
temperture drift of the resistors. Thus, the uncompensatable
bow in the thermal characteristics of standard devices can
be miliimizap and better temperature stability obtained.
10k lOOk 1M
The reference amplifier is pretty much a conventional design using a PNP pair (066-069) for the input, with a NPN
current inverter (067-070) supplying gain and converting to
single ended operatlon~ Additional gain is supplied by 064,
and its output is buffered by 062 and 056. Frequency rolloff
is providSd with C12 and R60, with a lead established by
feed-forward through C13 and R59.
FREQUENCY (Hz)
TLlH/S723-S
Figure 6. Open loop frequency response
o~
,he op amp ..
10-6 1":"':.,...,:-=...,.-;:::;--_ _ __
~10-7U;~~~~~1I~~
~
The quiescent level of the Class..A output stage is set by
057. The output current is, primarily limited by the current
gain of 056. Current limiting' is added with 058, 061 and
R54 to control the short circuit current for supply voltages
above BVCEO. This was considered necessary because the
thermal limiting does not operate on the reference amplifier.
I
~ 10-'
I
~
~~~~M~'~'
E
1 0,1 ",0,01
-1
-100'
10-9
10-"
1110 10
A clamp, 059, has been added to insure that the emitterbase junctior'l of 056 does not break over if the reference
output is' shorted to V + .
Precise regulation of the op amp input stage current is required
minimize 'drift when the recommended offset balancing scheme is used. It also turns out to be of considerable value in normalizing overall operation over the 40: 1
range of supply voltage specified for the device.
LOAD CURRENTJniA)
TL/H/S723-7
to
Figure 7. Plot of capacitive loading required to produce
excessive transient ringing the op,amp
in
428
V+.?
I
I
R55
5le
~R56
15k
~R57
~::s Q73~
20le
~R67
J~.
15.&le
~:
R74
8.7k
V-
BIAS
BUSS
. 11&8
4
~I
R54
100
REFERENCE
OUTPUT
rbf. (t-1'
I
Q62
Q5B
.!
IQU~
I -~
f II.!
rf~t~!
I 1 ~~QA~.;!f]lf~~~~~_.
+IJ
1•
o.s( raor I
I l:.~ I:
l' t
+C1&
t
v-
R71
19.1k
t
25
I
I
R75
4IIk
I
I
R81
1
R66
30k
Uk
R65
2k
V
•
•
•
RIHRENCE
1&
•
FEEDBACK
TVH/8723-8
Figure 8. Complete schematic of the reference and internal regulators
~ ~~·NY
01 wnpuappy
.... r-------------------------------------------------------------------------------------,
~
~
~
E
:=I
-g
CD
!
Regulation is obtained with another feedback amplifier that
maintains the output current of one of the current sources
(083) at a level where the voltage drop across R7S is equal
to the basic reference voltage. The differential input stage
(077-080) is buffered by vertical PNPs (076-082) more for
DC level shift than increased current gain. 078 serves as a
current inverter, delivering a single-ended 9utput to a, QOmpound buffer (074-075) that drives the bias bus. The only
unusual feature is' 073. It is a tranSistor formed using the
isolation diffusion as the base. This makes the intrinsic emitter-base voltage more than 100 mV higher than a standard
NPN. With this high emitter-base voltage, it can be used as
a clamp on the bias bus, limiting peak cu,",nt-sourge ,cur~
rent under transient conditions.
Tabla II_ Typical Peformance of the Reference at 25"C
Parameter
Conditions
Une R~ulation
1.2 V $ Vs $ 40V
Load: Regulati0fl.:' "
0$lo$1mA
Feedback Sense
'"
Voltage'
Input Offset Current
0.25nA
Offset Current Drift -SsoC
s; TA $
Input Bias Current
E: 1.6 I=~-+--il-+--+--I
.!I
i
ii
1.~
s:
Bias Current Drift
-SsoC $ TA
V- ,$ VOM $ V+ -0.8SV
TliIH/8723-9
Figure 9. Plot defining minimum supply voltage for the
. op .amp at various load currer;rts
1.0
0.6
!E:s:
I
1.2V $ Vs ,$ 40V
Unloaded Voltage
Gain
Vs
Va
Loaded Voltage
Gain
,
0.1
~~:-IT"--r-r==--=:-:::I
t:Z2!];J~~3:d
1=~'::J"HI~"Iii''''-
...
'0.02 =-~~~
r-!!!!*~~t::t
I!!
0.002
0.001 L-..J.....-..I..L.L-....I....-L---I
-0.3 -u -0.1 0 11.1 0.2 0.3
OFFSET VOLTAGE CHANGE (mY)
102 dB
TL/H/8723-10
. Figure 10. Saturation characteristics of the op amp
.,
96 dB
= ±20V,
400Vlm\i
= ±19.97V,lo = 0
Vs = ±20V, Va = ±19.6V,
1aOVlm\i
RL = 9800
•
, ,l.2V $ Vs $ 40V
0;2 MHz
1.2V $ Vs $ 40V
0.15V/p.s
..
0.2
0.05
::Ii
0.01
~ 0.005
"
Supply-Voltage
Rejection
~~~~~~~~;J
0.3.,.0.2 0.1 0 -0.1 -0.2 -0.3
OFfSET VOLTAGE CH~E (mY)
6OpAloC
+125°C',
1.0
D•• L-....J.....-L__L-....J.....-L---I
10nA
Common-Mode
Rejection
2'lOp.A
.-:-----:::::=,"--,-..,.,---.---,
1.8
,2pAloC
+12SoC
75V/mV
,,'
"
0.3mV
2 p.VloC
Slew Rate
0.2V"S; Va $ 15V
"\',
Mini!Tlum oper!l,ting vqltage for the 9P a!llP.depends on 19ad
current and allowable gain error as'indicated in FlfJure 9.
The typical saturation voltage of the'output stage is shown
in FlfJu(e 10. The voltage "i'Quired to power the reference is
p,lotted in Figur,J ~.1.
'
Value
Input Offset Voltage
:'20nA
Total Supply Current ,l.2V $ Vs $ 40V
TlJItle I_ Typical performance of the operation amplifier
at25"C
" ,
Offset Voltage Drift -5SoC $ TA $ +125"C
+125°C 0.0020/0/oC
,
_ 1.2,
Conditions
s; TA $
"
, Amplifier Gain
The characteristics of the op amp are outlined in Table I.
Tile standard specifications compare favorably with the
best of the ~polar ICs available today. The output-voltage
Mng, output-saturation voltage, output current, commonmode range and supply-voltage range are indeed unusual.
These are indicated by the measurement conditions of relevant parameters.
Unity-Gain
Bandwidth
-'-SsoC
Current
p8rformance
Parameter
"
"
Feedback Bias
To avoid these obscure problems, a collector FET and implant resistor (088-R82) have been added to insure reliable
operation. Once the circuit is going, 087 disconnects the
start-up circuitry, leaving Q84 to supply current to the bias
bus.
"
0.010/0
200mV
Temperature Drift"
A high sensitivity start-up circuit is used that will activate on
leakage currents alone (08S-088). However, worst-case '
analysis of any start up based on leakage currents, especially at low temperatures and low voltages, becQmas an
exercise in the unknown.
Value
0.001 O/ON
,
E:
~
1.2
i.
1.0
§j
~
D.• L-..;O;;"'_.......~.....J.--Jc...:311
-50 -25 0 26 50 '. ,7& 100 126
TEMPERATURE (CO)
The typical specifications of the reference are given in Till/Ie
II. Again it is clear that performance has not been sacrificei:l
to realize low-voltage operation.
'
TLlH/8723-11
Figure 11. Minimum supply voltage of the reference aa
a function of temperature
430
As can be seen from Figure 12, the input-stage currentsource, 01, has been made with about 3 times the base
width of the other current-source transistors. This serves
both to give it the same emitter-base voltage at roughly half
the current density and to make it less sensitive to changes
in collector-base voltage. The latter contributes directly to
improved common-mode rejection.
To save space, several lateral PNP current-sources have
been built with a combination of linear emitter and emitter
on a radius. 068 in Figure 12 is an example of this. The
current density at circular emitters is higher than linear emitters for a given bias voltage. This must be accounted for in
deSign.
The total supply current for the complete IC is typically
270 "A This is impressive only considering the performance and complexity of the circuit. This current might be
reduced by a factor of 4, at the expense of speed, by raising
the sheet resistance of the implanted resistors.
general
Except for the inclusion of implanted resistors, processing is
essentially the same as that developed in 1968 for the
LM101A. The high sheet resistivities obtained with implanted resistors strongly recommend them for micropower devices, especially at high levels of complexity. But implanted
resistors have a lower breakdown voltage than their diffused
counterparts (40V vs 100V). This is caused by the reduced
radius of curvature at the junction edges. With higher sheet
resistivities, a signijicant voltage coefficient of resistivity will
be observed (resulting in a carrier depletion of about 1012
cm- 2 at the BVCEO of the NPN tranSistors). These factors
recommended that caution be used when operating implant
resistors at higher voltages or that they be operated at low
voltages where possible. In the circuit under discussion,
none of the implant-resistor junctions see the full supply
voltage.
A consequence of this low voltage design is that most of the
low-level circuitry is operating at junction biases of little
more than a diode drop. At this voltage, junctions are not
greatly affected by minor defects. Further, in this Circuit,
most areas that see fuli supply voltage can tolerate several
microamperes of leakage before operation is affected in the
least. This can be expected to increase both reliability and
manufacturing yield. The overall yield will also be improved
because there is a substantial market for devices that will
work only at low voltages.
The complete IC is built on a 97 x 105 mil die, shown in
Figure 12. This is definitely large for an op amp, even when
combined with a reference. But with 3-inch wafers and modern processing, die size is not the prime determinant of seiling price, as long as reasonable yields are maintained. This
is evidenced by the low cost of regulators having equal die
area and encapsulated in more expensive power packages.
As mentioned earlier, operating biases in several places are
determined by the difference in the emitter-base voltage between NPN and PNP transistors. Hence, a knowledge of
these differences is essential to avoid production problems.
Since the output transistors of the op amp can diSSipate
considerable power, thermal gradients are potentially a
problem. The effects of this dissipation have been measured and the results plotted in Figure 13. It is evident that
the thermal gradients are well in hand even with 400 mW
dissipation. The thermal gradient feed-through into the reference is also plotted in Figure 14. Clearly it will be insignificant at the power levels encountered in practical designs.
Thermal gradient isolation is primarily the result of careful
layout, Since many points within the circuit are sensitive.
The difficulties are, of course, mitigated by the large die
size.
I ........
1/
-0.1
~
'- PNP
Vs±20V
- ~ur
IoUT=2OmAl I
=, 0
I
L...JL-L--,--,--,--,--'-...J...~-I
-20
20
40
TIME (ma)
60
80
TL/H/8723-13
Figure 13. Effect of a pulsed load on the offset voltage
of the op amp showing electrical change and
that caused by thermal gradients
C3
0.05
g
054
I "
III
~
~
-0.05
~-'
I I I
loUT = 0
PNP
0.05
I
NPH
bur = -20mA-
loUT
V
-0.05
-20
= 20 mA
'"
o
f-
r1
Vs ±2OV
YouT = 0
20
40
60
80
TIME (ms)
TL/H/8723-12
TUH/8723-14
Figure 12. Photomicrograph of the IC
Figure 14. Cross-coupllng from the op amp to the reference caused by thermal gradients
431
~ ~--------------------------------------------~-------------------------------------------,
applications
cOnclusions
~
i
o·
E
::I
'a
Ii
!
There are many obvious uses for precision functions such
as op amps, voltage comparators and voltage references
that are capable of operating at low voltages·with,a small
power drain. These include a variety of portable Instruments, remote telemetry and even implanted medical devices.
With this battery powered equipment, there is a decided advantage in reducing operating voltage to that of single cell ..
The power source will be more simple, lesS costly and have
a higher energy content for a given size and weight. In many
respects, current requirements for a given appHcation do
not decrease linearly with available supply voltage, giving an
even greater advantage to single-ce" operation. The resulting increase in the capacity of the power source coupled
with the low drain of the electronics could eliminate the
need for ON/OFF switches in certain applications.
The control circuits described earlier (F/{/ures 2 and 3) that
operate from residual voltages independent of fIXed supplies suggest an entirely new range of equipment-design
possibilities, even with line-operated power supplies. In general, the usefulness of this approach suffers greatly if minimum operating voltage is much above a volt. low idling
current is also an important consideration.
It has been shown here that high-performance linear circuits
oan be deSigned to operate with little more than a volt of
supply voltage. This precludes many standard design methods that require more than two diode drops of bias. Notable
among these is the Darlington connection. Alternate techniques can result In a significant increase in complexity.
However, this is not a serious problem with modem manufacturing methods, providing that reasonable yield can be
a
maintained~
Although the 2.70 p.A power drain of the example used is nOt
overly impressive in the realm of mjcropOwer, it shOuld be
remembered that it is a fairly complex function deSlQ.ned for
- 55·C to + 125·C operation and capable of delivering
more than 20 mA of output current. A more specialized davice could be built witl:! less than a tenth the drain, especially if the ma,ximum operating temperature cbuld be restricted
to 85·C. At elevated temperatures and low currents, the
emitter-base voltage of a transistor approaches the saturation offset voltage, creating circuit problems.
In general, feedback amplifiers with more complicated signal paths become more difficult to frequency compensate.
The benefrts to be gained (i.e., saturating outputs and extended common-mode range) are probably justified only in
low-voltage clrc!lits. The isolation-wall capecitorsintroduced
here ease the compensation problem some. A typ~1 integrated circuit (lM1 08) has.over1 000 pF of this caPacitance
avaUable with no area penalty. Nonetheless, stabilizing
some designs requires perseverance.
. .
It is difficult to evaluate the impact of these new approaches
mainly because they seerr to represent a step change In
how things can be done at the equipment-design level. But
considering that low-voltage operation can be realized with
no sacrifice in performance, it would seem that there are
few restraints on investigating the new methods.
As a practical matter, the IC described here can also be
used in a variety of ordinary applications providing significant performance advantages when cOmpared to existing
ICs. Because of this they might be expected to become an
"industry standard". This is important considering the volume-related economies that strongly influence pricing in the
semiconductor business. The general availability of the part
can be expected to have a strong influence on the investigation of the new design methods advocated here and elsewhere. 1
acknowledgement
Special thanks are due to Mineo Yamatake and Bob Dobkin
at National Semiconductor Corporation for' Invaluable assistance in frequency compensating the op amp and other
contributions to the final design.
references
1. R. J. Widlar, "New Op Amp Ideas", (to be published).
2. R. J. WIdlar, "New Developments in IC Voltage Regulators", IEEE J. of Solid-Stata Circuits, Vol. SC-6, No.1,
pp. 2-7, February 1971.
432
Super Matched Bipolar
Transistor Pair Sets New
Standards for Drift and
Noise
National Semiconductor
Application Note 222
Matched bipolar transistor pairs are a very powerful design
tool, yet have received less and less attention over the last
few years. This is primarily due to the proliferation of highperformance monolithic circuits which are replacing many
designs previously implemented with discrete components.
State-of-the-art circuitry, however, is still the realm of the
discrete component, especially because of recent improvements in the components themselves.
It has become clear in the past few years that ultimate performance in monolithic transistor pairs was being limited by
statistical fluctuations in the material itself and in the processing environment. This led to a matched transistor pair
fabricated from many different individual transistors physically located in a manner which tended to average out any
residual process or material gradients. At the same time, the
large number of parallel devices would reduce random fluctuations by the square root of the number of devices.
The LMl94 Is the end result. It is a monolithic. bipolar
matched transistor pair which offers an order-of-magnitude
improvement in matqhing properties and parasitic base and
emitter resistance over conventional transistor pairs. This
was accomplished without compromising breakdown voltage or current gain. The LM194 is specified at 40V minimum
collector-to-emitter breakdown voltage and has a minimum
hFE of 500 at 1 mA collector current. Maximum offset voltage is 50 p.V over a collector current range of 1 p.A to 1 mA.
Maximum hFE mismatch is 2%. Common mode rejection of
offset voltage (dVos/dVce) is 124 dB minimum. An added
benefit of paralleling many transistors is the resultant drop
in overalllbb and ree, which are 400 and 0.40 respectively.
This makes the logarithmic conformity of emitter-base voltage to collector current excellent even at higher current levels where other devices become non-theoretical. In addition, broadband noise is extremely low, espeCially at higher
operating currents.
The key to the success of the LM194 is the nearlyone-toone correlation between measured parameters and those
predicted by a theoretical bipolar transistor model. The relationship between emitter-base voltage and collector current,
for instance, is perfectly logarithmic over an extremely wide
range of collector currents, deviating in the pA range because of leakage currents and above several milliamperes
due to the finite 0.40 emitter resistance. This gives the
LM194 a distinct advantage in non-linear designs where
true logarithmiC behavior is essential to circuit accurac.y. Of
equal importance is the absolute nature of the logarithmic
constant, both between the two halves of the device and
from unit to unit. The relationship can be expressed as:
dependent only on Boltzman's constant (k), absolute temperature (T), and the charge on the electron (q). Since these
values are independent of processing, there is virtually no
variation from unit to unit at a fixed temperature. Lab measurements indicate that the logarithmiC constant measured
at a 10: 1 collector current ratio does not vary more than
± 0.5% from its theoretical value. Applications such as logarithmic converters, multipliers, thermometers, voltage references, and voltage-controlled amplifiers can take advantage of this inherent accurac.y to provide adjustment-free
precision Circuits.
VeE 1
Ve~2 =
kT In
q
APPROACHING THEORETICAL NOISE
In many low-level amplifier applications, the limiting factor
on performance is noise. With bipolar transistors, the theoretical value for emitter-base voltage noise is a function only
of absolute temperature and collector current.
en = kT.Jtc
Volts/~
This formula indicates that voltage noise can be reduced to
low levels by simply raising collector current. In fact, that is
exactly what happens until collector current reaches a level
where parasitic transistor noise limits any further reduction.
This "noise floor" is usually created by and modeled as an
equivalent resistor (rbb') in series with the base of the transistor. Low parasitic base resistance is therefore an important factor in ultra-low-noise applications· where collector
·current is pushed to the limits. The 400 equivalent rbb' of
the LM194 is considerably lower than that of other smallsignal transistors. In addition, this device has no excess
noise at lower current levels and coincides almost exactly
with the predicted values. A low-noise deSign can be done
on paper with a minimum of bench testing.
Another noise component in bipolar transistors is base current noise. For any finite source impedance, current noise
must be considered as a quadrature addition to voltage
noise.
(~)
IC2
This relationship holds true both within a single transistor
where IC1 and IC2 represent two different operating currents
and between the two halves of the LMl94 where collector
currents are unbalanced. Of particular importance is the fact
that the kT/q logarithmic constant is an absolute quantity
433
in~~~~=~:~~~ = eN = 4en2 + (in e rsl2Volts/~
where rs is the source impedance
In the LM 194, base current noise is a well-defined function
of collector current and can be expressed as:
.In __
~2q e Ic
Amps/~
hFE
To find the collector current which yields the minimum overall equivalent input noise with a given source impedance,
the total noise formula can be differentiated with respect to
Ic and set equal to zero for finding a minimum.
eN2 = en2 + (in2 ers2) + 4 kT e ra
(4 kT e rs = noise2 of rsl
2k2e T2
= ---
qelC
+
2qelcers2
hFE
+ 4kTers
1
.1
d(VN 2)
--=
d(lc)
-2k2 • T2
q • le2
2q. rs2 ,
Inductive ,source into h,igh impedance:
kT'
,"
+--=0
hFE
,
v'fiFE
Ie (optimum) = kT •
q
'i,,\ I
Pf&ll2
\
\
,
~
~
1
o
'.
OF 4DII
10 80
100 SOD
lk
3k
\
"
'.
n
1
I\.
.........
....
LM194
~ ........'.
i0l8EFl8UR~~
I
OPTIMUM
COLLECTOR
"CURII!NT
'.
'.
.J
'\
;
;
I
i
I\.
1
"
'"
10k 30k lOOk 8DOk 1M
SOURCE IMPEDANCE (III
TL/L/6922-1
FIGURE 1. Noise Figure va Source Impedance
source impedance for the LM194 and a very low noise junction FET (PF5102). Collector current for the LM194 is optimized for each source impedance and is also plotted on the
_graph using the right side scale. The PF5102 is operated at
a constant 1 mA.lt is obvious that the bipolar device gives
significantly better noise figures for low source impedances
and/or low frequencies. FETs are particularly poor at very
low frequencies « 10 Hz) and offer advantages only for
very high source impedances.
C3'
.... ---It---...
I
vTLlL/6922-2
FIGURE 2. High Frequency Power Supply Rejection
BANDWIDTH CONSIDERATIONS
Because of its large area, the LM194 has capaCitance-limited bandwidth. The hIs • f product is roughly 0.08 MHz per
microampere of collector current, yieldihg an ft of 80 MHz at
Ie = 1 mA and 800 kHz at Ie = 10,u.A.
ev'fiFE • 4fH • fl
Collector-base CapaCitance on the LM194 is somewhat
higher than ordinary small-signal transistors due to the large
device geometry. Cob is 17 pF at VeE = 5V. For high:gain
stages with finite source impedance, the Millering effect of
, Cob will usually be the limiting factor on voltage gain band-
Capacitive source into summing junction:
kT v'fiFE
x-x
q
, II
'Cl=C2+C3 '
Capacitive source into high impedance:
Ie (opt) =
(~~~~) where Rl is the lo~d resisto;
. - - -.....-V+
REACTIVE SOURCES
Calculations may also be done to derive an optimum collector current when the Signal source is reactive. In this case,
upper and lower frequencies (fH and fu must be specified.
Also, optimum current is different for an amplifier with a
summing junction input (ZIN = 0) as compared to a high
impedance input (ZIN :> Xe, Xu. The formulas below give
optimum collector current for noise within the frequency
band fl to fH. For audio applications, lowest "perceived"
noise may be somewha~ different because of the variation in
sensitivity of the ear to frequencies in the audio range
(Fletcher-Munson effect).
kT
Ie (opt) = - . C • 21T
q
,
'
Noise injected from power supplies is an often 'overlooked
problem in low noise designs. This is probably in part due to
the use of IC op amps with their high power supply rejection
ratio and differential inputs. Many low-noiSe designs are single-ended and do not Elnjoy the inherent supply rejection of
differential designs. For a singlE;l-ended amplifier with its
load resistor tied directly to the power SuPPlY, nqise on the
supply must be no higher than (Rl. Ie. VN)/(3kT/q) or
noise performance win be degraded. For a differential stage
(see Figure 2) with the common emitter resiStor tied to the
negative supply and the collector resistors tied to the positive supply, supply noise is' not generally a problem, at least
at low frequencies. For this to be true at higher frequencies,
the capaCitance at the collector nodes must be kept low
and balanced. In an unbalanced Situation, noise from either
supply will feed through unattenuated at higher frequencies
where the reactance of the capacitor is much lower than the
collector resistance.
100'"'
\t=kHZ \\
;
\
Av =
;
~.
\
: Pf&101
",'
'
"
fl2 + fH2 tfL.fH
,
.
Keep in mind that the simple formula for total input-referred
noise, though accurate in itself, does not take into account
the effects of noise created in additional stages or noise
injected from supply lines. In most cases voltage gain of the
LM194 stage will be sufficient to swamp out.second stage
effects. For' this to be true, first stage gain' must be at least
3. Vn2/vN, where vn2 is the voltage nOise,of the second
stage and vN is the desired totai input referred voltage
noise. A simple formula for voltage gain of an LM194 stage,
assuming no seeond stage loading, is given by:
1
@
10Hz
','
~':3
Ie (opt) = - - 21T· L
rs
For very low source impedances, the 400. rbb' of the LM194
should be added to rs in this calculation. A plot of noise
figure versus collector current (see curve) shows that the
formula does indeed predict the optimum value. The curves
are very shallow, however, and actual current can be varied
by 3:1 without losing more than 1 dB noise figure in,most
cases. This may be a worthwhile tradeoff if low bias current
(Ie < I~pt) or wide bandwidth (Ie > lopt) is also important
Figure 1 is a plot of best obtainable noise figure versus
\
q.v'fiFE~
RI
434
width. At Ie = 100 p.A and RL = 50 kO, for instance, DC
voltage gain will be (Ru(lc)f(kT/q) = 200, but bandwidth
will be limited to
FREQUENCY
(Hz)
kT/q
f3W = (21T)(Ru(lc)(RS>(Cobl = 50 kHz
, TOTAL HARMONIC DISTORTION
"
20
<0.002 <0.002 <0.002 <0.002 <0.002
100
<0.002 <0.002 <0.002 <0.002 <0.002
for a ~urce impedance (RS> of 1, kO.
lk
<0.002 <0.002 <0.002 <0.002 <0.002
LOW NOISE APPLICATIONS
FlIJures 3 and 4 represent two different approaches to low
noise designs. In FlIJure 3, the LMl94 is used to replace the
input stage of an LMl18 high speed operational amplifier to
create an ultra-low-distortion, low-noise RIM-equalized
phono preamplifier. The internal input stage of the LMl18 is
shut off by tying the unused inputs to the negative supply.
This allows the LMl94 to be used in place of the internal
input stage, avoiding the loop stability problems created
when extra stages are added. The stability prOblem'is especially critical in an RIM circuit where 100% feedback is
used' at high frequencies. Performance of this circuit exceeds the ability of most test equipment to measure it. As
shown in the accompanying chart, FllJUre 3, harmonic distortion is below the measurable 0.002% level over most of
the operating frequenCy, and amplitude range. 'Noise referred to a 10 mV inpUt signal is 90 dB doWn, measuring
0.55 P.VRMS arid 70 pARMS ina 20 kHz bandwidth. More
importantly, the noise figure is less than 2 dB when the amplifier is used with standard phono cartridges, which have an
equivalent wideband (20 kHz) noise of 0.7 p.V1. Further improvements in amplifier noise characteriStics woald be of
little use because of the noise generated by the cartridge
itself.
A special test was performed to check for "Transient Intermodulation Distortion'~2. 10 kHz and 11 kHz were mixed 1:1
at the input to give an RMS output voltage of 2V (input =
200 mV). The resulting 1 kHz intermodulation product measured at the output was 80 iN. This calculates to 0.004%
distortion, an incredibly low level considering that the 1 kHz
has 14 dB (5:1) gain with respect to the 10 kHz signal in an
RIM circuit. Of special interest ,also.,is the use of all DC
coupling. This eliminates the overload recovery problems
associated with coupling and bypass capaCitors. Worst case
10k'
<0.002 <0.002 <0.002 0.0025 <0.003
20k
<0.002 <0.002 0.004
0.004
0.007
O.t
1.0
5.0
0.03
0.3,
OUTPUT AMPLITUDE (V) RMS
FIGURE 3. Ultra Low Noise RIM Phono Preamplifier
..... _ _ .... +IV
l:t_J
C3J..+
Z5.FT
~
?
.. -
-
+-""'""1~-"" +9V
~5
Uk
~3
III"
1111
"SELECT FOR I'tIOPER IMPEllANCE MATCH,
TUU6922-4
FIGURE 4. Ultra Low Noise Preamplifier
DC output offset voltage is about 1V with a cartridge having
1 kO DC resistance.
The single-ended amplifier shown in Figure 4 was designed
for source impedances below 2500. At this level, the
LMl94 should be biased at 2.5 mA (or higher) collector current. UnfortunatelY, Ibb', even at 400, is the limiting factor
on noise at these current levels. To achieve better performance, the: two halves of the LMl94 are paralleled to reduce
Ibb' to 200. Total input voltage noise for this design is given
by:
eN = .J4kT(lbb' + R3) + en2
+ 0.096 = 0.775 nViFz
= .;0.504
The current noise is 1.2 pA/Fz, and when this flOWS
through a 2500 source,resistance, it causes an ad!litional
0.30 nVlFz. Since the Johnson noise of a 2500 resistor is
2.0 nV/Fz, the noise figure is:
,
.,1(2 nV)2
NF = 20109
2nV
,
= 0.74 dB
Several unique features of this circuit should be pointed out.
FII'St, it has only one internal capaCitor which functions as an
AC',bypass for both stages. Second, no input stage load
resistor bypassing is used, yet the circuit achieves 56 dB
supply rejection referred to input. The optional supply filter
shown in dotted lines inTproves this by an additional 50 dB
and'is necessary only if supply ,noise exceeds 20 nV/Fz.
Finally; the problem of AC coupling'the 100 feedback impedance is eliminated by using a DC biasing scheme which
biases both stages simultaneously without relying on feedback from the output.
NOTE: Carj(ldge is BSSIImed to have less Ihan 5 kil Dc ..-mnce, Do nol
capacItOr couple the cartridge. R1. R2. and Ra Stiould b8 lOw noise malal
film
+ (0.3 nV)2 + (0.775 nV)2
resistOrs.
435
Harmonic distortion is very low for a '''simple'' two $tage
design. At ~OO: mV aUfpl,lt, total harmonic distortiori" mea}sl,lr~ 0.Q16%. For n_~rmal signal levels of 50. my a,nd bel.ow,
'distortion was lost:in. the·noise floor. Small-signal bandwidth
is 3 MHz.
1.5 JA.S to 0.1 %, and 5 JA.s to 0.01 %. Distortion with 10 Vp•p
outpl,lt Is virtually unmeasurable (<, 0.002%) a,t lOY{ frlilquencies, rising to 0.1 % at 50 kHz, and 1% at 200 kHz.
LOW DRIFT DESIGNS
Offset voltage drive In the LM194 quite closely follows the
theoretical value derived by differentiating the 109!1rithmic
formula. In other words it is a' function only of the original
offset voltage. If Vos is the original room temperature offset
voltage, drift of offset as given by differemiatiQn yields:
An ideal. application for this ~plifie~is as ~ head pre-amp
for moving-coil phono cartridges.. These cartridges have
very low oujput impeda!,!ce « 500 at lOW frequencies) and
have a full-outPut signal below 1 mY. Obviously, the. preamp
used for such a low signal level must have superb noise
properties. The amplifier' shown has a total RMS input noise
.of 0.11 JA.V in a 20 kHz bandwidth, yielding a signal-to-noise
ratio of 70 dB when used .with a 490 source impedance at a
0.5 mV signal level;.' .
d(V6s> .
d=r=
e~)
kT/q In
dT'
= Vos
LOW-NOISE, LOW-DRIFT INSTRUMENTATION
AMPLIFIER HAS WIDE BANDWIDTH
T
At room temperature (T= 297"K), 1 mV of offset voitage
will generate 1 mV/297"K = 3.37 JA.V/oC drift. The LM194
with a maximum offset voltage of 50 JA.V could be expected
to have a maximum offSEjt voltage drift of 0.17 JA.Vrc. !,.ab
measurements indicate that it does not deviate from this
theoretical drift by more than 0.1 JA.Vrc. This means the
LM194 can be specified at 0.3.JA. V1°C drift without an individual drift test on each device. In additiQn, if initial offsetvollage is zeroed out, maximum drift will be le~ than 0.1 JA.VI
DC. The zeroing, of course, must.1ie done.ln a wa~ tha~ theoretically zeroes drift•. This iii! best done .as lIhow!,!,.n FIgure 6
with a small trlmpot used to unbalance collector load resistors. (See National~s Application Note AN-.3.)
The circuit in Figure 5 is a high-performance instrumentation
amplifier for low-noise, low-drift, wide-bandwidth applications. Input noise voltage is 2 nVl.JHZ up to 20 kHz, rising
Cl
0.001
(d
R1
It
v.1\
R7
1110D
C4
tlpF
+O-----~----~~--~-1~
Ro·
01
1• .,4
III
SklI
::~
R12
&Ie
:r:.w.',
.. • 1MHz • 8=10
lMI=hllC
DRIVER
15=111
11=114
TLlLl6922-5
FIGURE 5. Low Drift-low Noise Instrumentation
Amplifier
to 3.5 nV/.JHZ at 100 kHz. Bandwidth at a gain of 50 is 1
MHz arid gain can be varied over the range of 10-100
Simply by changing the value of R3
Re. Input offset
voltage drift is determined by the LM194 and the tracking of
the (R1-R2>. (R3-Re>. and (R4-RS) pairs. 20 ppm/oC mismatch on all. pairs will generate 1.1 JA.VloC referred to input,
dominating the drift due to the LM 194. Resistor pairs which
track to 5 ppm/oC or better are recommended for very' low
drift applications. Input bias current is abOut 1 JA.A, rather
high for general purpose use, but necessary in·this case to
achieve wide bandwidth and ·Iow noise. The tight matching
of the LM 194, however. re!luces input offset current to
20 hA, and input offset currsilt drift to 0.5 nA/·C.-lnput bias
current drift is under 10 nArC. In terms of source Impedance. total. input referred voltage drift .will be degraded 1
JA.V1°C for each 1000 of unbalanced source. resistance and
0 ..05 JA.V/oC for each.1000 of balanced source resistance.
DC common mode rejection of this amplifier is. extremely
good, depending mostly on the match of. the ratio of R3/R4
to Rs/Re.· 0.1 % matching gives better than 90 dB. Rejection
will Improve with tighter matching and is not limited by .the
LM194 until CMRR approaches 120 dB. High frequency
CMRR is also very good. measuring 80 dB.at 20kHz and
60 dB at 100 kHz. Settling time for a 10V output step is
TL/Ll8922-8
and
FIGURE 6. Zeroing Offnt and Drift
To obtain optimum performance from such a low-drift device. strict attention must be paid to sources of drift external
to the device itself•. These include thl?rmocouple effects.
mismatch in load-resistor temperature coefficients, secondstage loadlng~ collector leakage. and finite source impedance.
Thermocouple effects in ultra-Iow-drift amplifiers are often
the limiting factor in. performance. The copper-to-Kovar
(LM194 leads) thermocouple will generate 35 JA.V/oC. This
sounds extremely high. but is not a problem if all input leads
on the LM194 are at the same temperatl,ll'e. For optimum
drift performance. the differential lead temperature where
copper connects to. Kovar should not exceed 0.5 millidsgreas per degree change in ambient. If the LM194 is mounted on a p~nted circuit boardl emitter and base lea.ds should
be solderSd to identical size pads and the package qrienl/ltion should place eri-litter and base leads on isothermal lines
if any significant power is being dissipated on the board.
The board should be kept in a still-air environment to minimize the effects of circulating air currents. "Still" air is particularly important when the LM194 leads are soldered di-
436
rectly to wires and when low « 10 Hz) noise is critical.
Individual wires in air can easily generate a differential end
temperature of 10 millidegrees in an ordinary room ambient,
even with the wires twisted together. This can cause up to 1
,.,.Vp_p fluctuation in offset voltage. The 0.001 Hz to 10 Hz
noise of the LM 194 operating differentially at 100 ,.,.A is typically 40 nVp_p (see Figure 7), so the thermally generated
signal represents a 25: 1 degradation of low frequency
noise.
The amplifier used in conjunction with the LM194 may contribute significantly to drift if its own drift characteristics are
poor. An LM194 operated with 2.5 VDC across its load resistors has a voltagfil gain of approximately 100. If the second
stage amplifier has a voltage drift of 20
(normal for
an amplifier with Vas = 6 mY) the drift referred to the
LM194 inputs will be 0.2
a significant degradation in
drift. Amplifiers with low drift ,such as the LM10SA or
LM30SA (5 ,.,.V/oC max) are recommended.
,.,.vrc
,.,.vrc,
For the ultimate in low drift applications, the residual drift of
the LM194 can be zeroed out. This is particularly easy because of the known relationship between a change in roomtemperature offset and the resultant change in offset drift.
The zeroing technique involves only one oven test to establish initial drift. The drift can then be reduced to below
0.03 ,.,.V/oC with a simple room-temperature adjustment.
The procedure is as follows: (See Figu/'9 8.)
1. Zero the offset voltage at room temperature (TAl.
2. Raise oven temperature to desired level (TH) and meas!Jre offset voltage.
3. Bring circuit back to room temperature and adjust offset
voltage to (Vas at TH). (TA)/(TH - TAl. (T is in OK.)
TL/LI6922-7
4. Re-adjust offset voltage to zero with an external reference source by summing the two signals. (Do not re-adjust the offset of the LM194.)
FIGURE 7. Low Frequency NOise of Differential Pair.
Unit must be In stili air environment so that differential
lead temperature is held to less than O.0003°C.
If the load resistors used to bias the LM194 do not have
identical temperature coefficients, they will contribute to offset voltage drift. A 1 ppmrC mismatch in resistor drift will
generate 0.026
drift in the LM194. Resistors with 10
ppmrC differential drift will seriously degrade the drift of an
otherwise perfect circuit design. Resistors specified to track
better than 2 ppm/oC are available from severai manufacturers including Vishay, Julie, RCL;TRW, and Tel Labs.
This technique can be extended to include drift correction
for source-generated drift as well since the basic correcting
mechanism is independent of the source of drift.
,.,.vrc
(USED AS TC TRIM)
ZERO
Source impedance must be considered in a low-drift amplifier since voltage drift at the output can result from drift of the
base currents of the LM 194. Base current changes at about
-o.S%rc. This is equal to 2 nAloC at a collector current of
100 ,.,.A and an hFE of 400. If drift error caused by the
changing base current is to be kept to less than 0.05 ,.,.Vre,
source unbalance cannot exceed 250 in this example. If a
balanced condition exists, source impedance is still limited
by the base current mismatch of the LM194. Worst case
offset in the base current is 2%, and this offset can'have a
temperature drift of up to 2%rC, yielding a change in offset
current of up to
RD
2nd
STABLE
STAGE POSITIVE
INPUT
'SELECT FOR
REQUIRED RANGE.
L--1~--' .,....I-....M."--T~~:..
-=-
STABLE
NEGATiVE
VOLTAGE
TI.II.I6922-8
FIGURE 8. Correcting for Residual or Source Generated
Drift
(2%)(100,.,.A)(2%/OC)/hFE = 0.1 nArC
VOLTAGE REFERENCE
Voltage references utilizing the bandgap voltage of silicon
were first used 8 years ago, and have since gained wide
acceptance in such circuits as the LM109, LM113, LM340,
LM117, ,.,.A7S00, AD5S0, and REF 01. The theory has been
well publiciz~d and is not reiterated here.
The circuit in Figure 9 is a mlcropower version of a bandgap
technique first used by Analog Devices. It operates off a
single 2.5V to 6V supply and draws only 25 ,.,.A idling current. Two AA penlight cells will power the reference for over
a year of continuous operation. Maximum output current is
0.5 mA, with an output resistance of 0.20. Line regulation is
-0.01%/V and output noise is 20 ""VRMS over a 10 kHz
bandwidth. Temperature drift is less than ±50 ppmrC
when the output is trimmed to 1.21V. Much lower drift can
be, obtained by adjusting the output of each reference to the
at a collector current of 100 ,.,.A. This limits balanced source
impedances to 5000 at collector currents of 100 ,.,.A if drift
error is to be kept under 0.05 ,.,.V
For higher source
impedances, collector current must be reduced, or drift trimming must be used.
Collector-leakage effects on drift are generally very low for
temperatures below 500C. At higher temperatures, leakage
can be a factor, espeCially at low collector currents. At 700C,
total collector leakage (to base and substrate) is typically
2 nA, increasing at 0.2 nArC. Assuming a 10% mismatch
between collector leakages, input-referred drift will be 0.05
at a collector current of 10 ,.,.A, and 0.005 ,.,.V/oC at
100 ,.,.A. At 125°C, Input referred drift will be 1.5 ,.,.V
and
0.15 ,.,.V/oC respectively.
rc.
,.,.vrc
----_-V+
vg~~:~ .....
rc
437
,N r-----------------------------------------------------------------------------~
+ 1V to + 10V common mode range, a full scale input of
optimum value. A 1% shift in output voltage changes drift 33
~
20 mV (1 mV to 100 mV is possible) and fully' balanced
~- ppm/~C. Temperature range is -25"C to +-100"C.
inputs with a differential input impedance> 10 MO. ComThe LM194is the entire referenceln this design, Slipplying
mon mode input impedance Is 100 MO. Common mode reboth- Vee and IJ.Vee portions of the referE!nce. one half
jection ratio is 120 dB at 60 Hz, 11'4 dB at 1 kHz, and 94 dB
lMl14 delivers a constant bias cUrrent to ft1e LM4250. "the
at 1() kHz referred to input. Power supply rejection at DC is
other half, 'in conjunction with the 2N4250 PNP, ensures
114 dB on_the V+ supply and 108 dB on the V- supply.
startup of -the circuit under worst cast (2.4k) load current.
Small signal bandwidth is > 50 kHz and slew rate Is 0.1
R1...;R2 and R4-R5 should track
50 ppm/·C. Re should
V / ,...s. Gain error is determined by the accuracy of Rs, Rs.
have a TC of under 250 ppm/·c. The circuit is stable 'for
~, and R3. For ,the values shown, gElin is 500. R3 can be
capacitive loads up to 0.047,...F. ~ is optional, for improved
varied to set gain,as desired from 25~(8000) to 10,000
ripple rejection.
(200). Gain,non-linearityis·< 0.05% for a-l0V butput and <
STRAIN GAUGE ~MPLIFIER
0.012%-,for 5V-ou~y.t)._.R7 is a +0.3%repositive-temperatunM;oefficient wirewound resistor for compensation of
The instrumentation amplifier shown in F/(/UfB 10 is an,
ample of an ultra-low-drift design specifically optimized for
gain with te!TIPElrature. Without this resistor, gain change
strain-gauge applications. A typical strain-gauge bridge has
with temper:atureis 0.007%I"C.-lf R7 is omitted, replace Rg
with 12.4 kO.
one end grounded and the other driven by a 3-to-l0 volt
precision voltage reference. The diff~ential output Signal of
Input offset voltage drift isdeterrnined primarily by resistor
the bridge has a 1.5 to 5 volt common-mode level and a
mismatohes ~een R1/Fl2 and R5/Re. If either of these
typical full-seale differential signalleV81 of 5-50 mV. Source
ratios driftS by 5 ppm/·C, an input offset voltage drift of
impedance is in the range of 1000 to
with an imped0.15 ,...VI·C will be created. Other resistor drifts contribute to
ance imbalance of less than 2%~ This amplifier has been
gain error only. R12 is used to adjust room temperature offspecifically optimized for these types of signals. It has a
set voltage to zero.
to
a
ex-
soon,
(U < Vln
Vas
k ICI
--=-=-IndT
T
qlC2
IC2
q-a
(a = thermocouple output in V,OC)
The circuit is basically a non-inverting amplifier with the gain
set to give 10 mVirF or 0c) at the output. This output sensitivity is arbitrary and can be set higher or lower. Cold-junction compensation is achieved by deliberately unbelancing
the collector currents of the LM 194 so that the resulting
input offset voltage drift is just equal to the thermocouple
output (a) at room temperature. By combining the formulas
for offset voltage versus current imbalance and offset voltage drift, the required ratio of collector currents is obtained.
ICI
ICI
IC2
-=e--
In-=---=--
r-----.....-------+
15V
OUTPUT
10mV/oC
+15V
R12
12k
R4
250k
R3
5012
CERMET
Rl
590k
R6
50k
THERMOCOUPlE
R2
I.DBk
R5
13k
TLlLf6922-11
1. Select R9 - 300 kn
2. Set'Al0 equal to A9 •• -4(1.18 x 1(4)
E= Gain error alloWed for ("'2.5%)
T 1 = T8!l1peralure In 'K at which H is desired to
3. RB'- 200k
4. Select R4 In the range 50 kO to 250 kO
5. RS _
(R4)(Tl)(a)
S(TI - Tal - a(Tl)
have the gain control
9. R7
= (R9/Rl0)(R2)
10. AS = At/l0
give proper output at T2 (gain adjust).
which the desired
S= Aequlred output scale factor. Use
vrc
even though actual output may be in 'F
[(R2).:~~ a(Tt!) (0.95)
.. Set oven to T 1 end adjust A6 to givaproper
output (zero adjust).
b. Raise (or lower) oven to T2 and adjust R3 to
at
zero
S-a
8 R3 _ (E)(R2)
.
50
the
temperature scale ("C or 'F)' is equal to
(S_a)[Rs_ a (R4)]
7. AI _
not interact with
zero control
To= Temperature in 'K
6 R2 = a(A4J(R5)(1 - E'l1oo)
.
CALIBRATION:'
Vz= Zener reference voHege
c.
Raturn to room temperalure end short thermocouple and 01 to ground. Adjust Rl1 to
give proper output (room ambient) In 'K or·R.
For 10 mVrc. this is 2.98V
@
T A = 25"C.
For 10 mVrF. this Is 5.37V
@I
TA = 77'F.
d. Aemove shorts and re-adjust R6 H necessary
to zero output.
a = Thermocouple output in Vrc
Values shown on schematic ere for 10 mVrc.
Ses below for 10 mVrF values ualng a Chromel·
Alurnel thermocouple with room temperalure
forTI·
Note: Steps C and 0 can be eliminated ~ exact
cold junction compensation Is not required. RII
is simply shorted out. Compensation will be withIn ± 5% wHhout adjustment ('; O.OS'C/'C).
AI = 3671<. A2 = 6290, A3 = O. A4 = 250k.
'Thermocouple only In
A5
= 4.0Bk. R6 = 5Dk, R7
= lk. RIO
= 191k
FIGURE 11. Thermocouple Amplifier with Cold.Junction Compenaatlon
439
oven.
N,r-------------------------------------------------------------~
~
'~'
for low thermocouple effects (resistors do generate thermocouple voltages if their-ends are at different temperatures)
and should have low temperature'coefficients. Rg and R10
should track to 10 ppm/oC. Rs,R6,and Rll' should not have
a TO higher than 250 ppml"O. Rh:R2, and R4 sl:lo\lld track
to 20 ppml"O. 02 can be added to 'reduee spikes 8.l!1d noise
from long thermocouple lines.'
Input impedance for this circuit is > 10Q MO,: so high thermocouple impfadance will not affea! ,sC(lle faator. "Zero
shift" due to input bias current is apPtoxirnately 1°0 for each
4000 of thermocouple lead, resistance with,a 40 p.VI"O
thermocouple.
No provision is made for correction of thermocouple non-Nnearity. This could be accomplished with a slight nonlinearity
introduced' into R4' with additional r!!Sistors and diodes.Another poSSibility is to digitize the output and correct the nonlinearity digitally with a ROM prOgrammed for a specific thermocouple type.
,. .-
only and can be inverted if ilegmive.. A nice.feaMe. af'ttl'lS
design is that all gain errors ean be trimmed to!Z8ro at bne
point. RS,is Pllralleledwith 2.4 MO,tp,drqp itsnqmi~lval~
2%. Rs then, gives a ±2% 91l!l"l:trim to accountf0r errorJI)o
Rlo R2. Rs. R7. and any offset in .O.l.9r 02. forverylqw level
ir:!puts. offset voltage in the LM30ssmay cr~ate large percentage,:errors referred to input. A simplEillClheme for offSE!tting any of.t,he !-M3~s ,to ,~ero i!l,shown in .dotted)in~; tl)9
+ input of the approprillte, LM308 ~ sJmply ,tilld to ~lt in,stead of ,ground for zel"QingO' The, sl,lmming "1oge of operatiOI) on all inputs allows e~sy scallng on anY or all, inputS.
$imp~ set the inpufre$jst0r, equal to (VIN(max»i(2oo"JiA).
VOUT is equal to:,
' "
'.,
' ,,'
,;,:
"
.vOUT =
,,
(AiX,) (Y)
R; (Rs)
Z:
'
" ~7
". "
I " ,
"
Input voltages above the supply v:oltage are allowed because of the summing mode of operl!-tion. Several inputs
may be summed at uX", lIy," or uZ."
Proper scaling will improve accuracy bY. preventing large
current imbalances in 01 and 02. and..by creating the largest possible output swing. Keep in mind that any multiplier
scheme must have a reference and this circuit is no differ-,
ent. For a simple (X) • (Y) or (X)/Z function, the unused
input must be tied' to a reference voltage. Perturbations in
thi,~ r~erencewill be seen at the output as scale factor
: changes. so a stable reference is necessary for precision
work. For less critical applications. the unused input may be
" tied tl)'the positive supply voltage, with R = V+ /200 p.A.
POWER METER
The power meter in Figure 12 is ~ good e~m~~ of mi~i
mum-parts-count deSign.. It uses orn)'one transistor pair ,to
provide the complete (X) • (V) function. The circuit is intended for 117 VAC ± 50 VAC operation, but can be easily modified for higher or lower voltages. It measures true (non-reactive) power being delivered to the load arid requires no external power supply. Idling power drain is only O.5W. Load
current sensing voltage is only 10 mY, keeping load voltage
loss to 0.01 %. Rejection of reactive load currents is better
than 100: 1 for linear loads. Nonlinearity is about 1% full
scale when using a 50 p.A meter movement. Temperature
correction for gain is accomplished by using a copper shunt
(+0.32%1"0) for load-current sensing. This Circuit measures power on negative cycles only, and so 'Cannot' be
used 01) rectifying loads.
.,
LOW COST MATHEMATICAL FUNCTIONS
Many analog circuits require a mathematical function to be
perform!l
~ -DA
~
~
~
~ -D .•
z
~
-1.2
-\.&
-2.0
s
_T
~~
~
r'" ~
K
/J
/ I
IT
s
J
o
10
20
30
40
50
60
70
TEMPERATURE ("CI
TUHI7471-2
FIGURE 2. Thermocouple Nonlinearity
Of course, increased error results if, due to component inaccuracies, the compensation circuit does not produce the
ideal output. The LM335 is very linear with respect to absolute, temperature and introduces little error. However, the
complete circuit must contain resistors and a voltage reference in order to obtain the proper offset and scaling. Initial
tolerances can be trimmed out, but the temperature coefficient of these external components is usually the limiting
factor (unless this drift is measured and trimmed out).
I!
840, or CIS series 360)sholJld be consi~ered as good Candidates"for high'resolutitin trim applications. competing with
the more obvious (but,slightly more expensive) multi-turn
trim pots socii Allen Bradley type RT or MTO'Weston type
850, or similar.
'
With a room temperature adjustment, drift error will be only
± WC at 70"C and ± WC at O"C. Thermocouple:nonlinearity results in additional compensation error. The chromell
alumel (type K) thermocouple is the most linear. With this
type, a compensation accuracy of ±o/4°C can be obtained
over a O°C-70"C range. Performance with an iron-constantan thermocouple is almost as good. To keep the error sinall
for the less linear S and T type thermocOuples, the ambient
temperature must be kept within' a more limited range, such
as 15'0 to 50"C. Of course, more accurate,compensation
over a' narrower temperature range can be obtained with
any thermocouple type by the proper adjustment of voltage
TC and offset.
Standard metal-film' resistors cost substantially less than
precision types and may be' substituted with a reduction in
accuracy or temperature range. Using 50 ppm/oC resistors,
the circuit can achieve Yz°C error over a 1O"C range. Switching to 25 ppm resistors will I)alve this error. Tin oxide resistors should be avoided since they generate a thermal emf of
20 p.V for 1°C temperature difference in lead temperature as
opposed to 2 p.WOC for nichrome or 4.3 p.V/oC for cermet
types. ResiStor netw~rks, ~xhiblt good tracking, with
50 ppm/oC obtainable for thick film and 5 ppml"C for,thin
film. In order to obtain the large resiStor ratios needed, one
can use series and parallel connections of resistors on'one
or more substrates.
CIRCUIT DESCRIPTION
A single-supply circuit is shown in Figure So R3 and R4 diVide down the 10 mV/oK output of the LM335 to match the
SeellEl.ck coefficient of the thermocouple. The LM329B and
its asSociated voltage divider provide a voltage to buck out
the O°C output of the LM335. To calibrate, adjust R1 so that
V1 = ex: T, where ex: is the Seebeck coefficient· and T is
the ambient temperature in degrees KBMn. Then, adjust R2
so that V1-V2 is equal to the thermocouple output voltage
at the known ambient temperature.
To achieve maximum performance from this circuit the resistors must be carefully chosen. R3 through R6 should be
precision wirewounds, Vishay bulk metal or precision metal
film types with a 1% tolerance and a temperature coefficient
of ± 5 ppm/oC or better. In addition to having a low TCR,
these resistors exhibit low thermal emf when the leads are
at different temperatures, ranging from 3 p.V/oC for the
TRW MAR to only 0.3 p,V/oC 'for the Vishay types. This is
especially important when using S or R type thermocouples
that output only 6 p.V/oC. R7 should have a temperature
coefficient of ±25 ppm/oC or better and a 1% tolerance.
Note that the potentiometers are placed where their absolute resistance is not important so that their TCR is not critical. However, the trim pots should be of a stable cermet
type. While mUlti-turn pots are usually considered to have
the best resolution, many modern Single-turn pots are just
as easy to set to within ±0.1 % of the desired value as the
multi-turn pots. '
Also single-turn pots usually have superior stabil,ty of setting, versus shock or vibration. Thus, good single-turn cermet pots (such as Allen Bradley type E, Weston series
'See Appendix A lor calculation of Seebeck ooeffIoient.
as
l&Y
R3*
200k
Al
LM33&
TCADJ
l&Y
--
THERMOCOUPLE
A---iK 10k'
-
ThermcIcoupie ,CoerIIctent
Type
: } OUTPUT
R5*
200k
A7t
,
1M'
choose,R4
/
V2
~
R4
(II)
R6
(II)
(,.Yrc)
52.3
1050 385
42.8
T
856 '315
K
40.8
816 300
S
6.4
1.28 46.3
°R3 Ihru R6 are, 1 %, 5 ppmrC. (to' ppmrC tracking.)
tR7 i91%, 26,ppmrc.
a
chOose R6 =
A6*
choose R7
TL/Hf7471-3
'
= ,10 mvrc·' R3
*.
-T
eel
~
(0.9R5)
,
= 5. ,R5
where To is absolute zero (- 273.16'0)
, Vz is the ~renca voltage (6.95V lor
FIGURE 3. Thermocouple Cold-Junctlon Compensation Using Single Power Supply
444
LM~29B)
A circuit for use with grounded thermocouples is shown in
Agure 4. If dual supplies are available, this circuit is preferable to that of Figure 3 since it achieves similar performance
with fewer low TC resistors. To trim, short out the LM329B
and adjust R5 so that Vo = -4H. VOUT'" IOmvrc
All fIXed resistors ± 1 %, 25 ppmrC
unless otherwise indicated.
AI should be a low drift type such
+
as LM306A or LHOO44C. See text
-..
FIGURE 5. Centigrade Thermometer with Cold-Junctlon Compeneatlon
445
TL/H/7471-5
~,r,~~~--~--------------~~------~--~----------------------------------,
~,
~
a
The'error oiler O"C to 1300·C'range tlue,to,thermocowple
noriHnearity is only 2.5% maximum. Table l'shoWS'the error
due to thermocouple nonlinearity as ~ function of temperature. This erroHs under 1·C for O"C to 300·C but is as high
17"C over the' entire range, This inay be corrected with' a
nonlihear shaping network. If the output is digitized; correc:tion factors can be stored iil a ROM and added in via' hardware or'software.
The major cause of temperature drift will be theinputoff8et
voltage drift 'of the op amp. The LM30BA haS a specified
maidmum OffSet Voltage drift of 5 )J.VI·C which will result in a
1·C error for every B·C change in ambient. Substitution of an
LH0044C with its 1 P.V I·C maximum offset voltage drift will
reduce this error to 1·C per 40"C. If desired, this temperature drift can be trimmed out with only one temperature cycle by following thepr~cedure detailed in App~ndix B.
,,
as
"',
-0.3
-0.4
-0.4
-0.4
-0.3
-0.2
O'
0.2
0.4
'"0.6
O.B
0.9
0.9
0.9
O.B
0.7
0.5
0.3
0.1
I,
""'I
'
,L":'';''CU
-,
TR,EF
TL/H17471~6
FIGURE Sa
,..---,
TREF
CHROMEL
I
----.---~
ALUMEL
ALUMEL
I
~
LC
IL ___ JI
TL/H17471-7
'Has no effect on measurement
FIGURESb
FIGURE 6_ Methods tor Sensing Temperature of
Reference Junction
TABLE I. Nonllnearlty'Error of Thermometer Using
Type K Thermocouple (Scale Factor 25.47"C/p.V)
Error ("C)
.. ,
'I, I '
ALUMEL
The LM335 must be held isothermal with the thermocouple
reference junction for proper compensation. Either of the
techniques of Figures 6a or 6b may be used.
Hermetic ICs use Kovar leads which outpUt 35 p.VI"C referenced to copper. In the circuit of Figure 5, the low level
thermocouple output is connected directly to the,op amp
input. To avoid this causing a problem, both input leads of
the op amp must be maintained at the same temperature.
This is easily achieved by terminating both leads to identically sized copper pads and keeping them away from thermal gradients caused by'components that generate significant heat.
10
20
30
40
50
60
70
BO
90
100
110'
120
130
140
150
160
170
1BO
190
',
'112'
'+'
':; I ,,','
LM336 '
CONSTRUCTION HINTS
·C
7""' cu'
C~OME.L r
·C
"
",:
446
200
210
220
240
260
2BO
300
350
400
500
600
700
BOO
900
1000 "'.
1100
1200,
1300
Error ("C)
I'
-0.1
-0.2
-0.4,
-0.6
-O.!;i,'
-0.4
":"0.1,
"1.2 '
2.B,
7.1
11·B
15.7
17.6
17.1
14.0
, B.3
-'0.3
-13
,
,
.--------------------------------------------------------------------.~
On a graph, the error of the line approximation is easily
viSible as the vertical distance between the line and the
nonlinear function. Thermocouple nonlinearity is not so
gross, so that a numerical error calculation is better than the
graphical approach.
Most thermocouple functions have positive curvature, so
that a linear approximation with minimum mean-square error
will intersect the function at two pOints. As a first cut, one
can pick these pOints at the % and % points across the
ambient temperature range. Then calculate the difference
between the linear approximation and the thermocouple. t
This error will usually then be a maximum at the midpoint
and endpoints of the temperature range. If the error becomes too large at either temperature extreme, one can
modify the slope or the intercept of the line. Once the linear
approximation is found that minimizes error over the temperature range, use its slope as the Seebeck coefficient value when designing a cold-junction compensator.
An example of this procedure for a type S thermocouple is
shown in Table II. Note that picking the two intercepts (zero
error points) close together results in less error over a narrower temperature range.
Before trimming, all components should be stabilized. A 24hour bake at 85·C is usually sufficient. Care should be taken
when trimming to maintain the temperature of the LM335
constant, as body heat nearby can introduce significant errors. One should either keep the circuit in moving air or
house it in a box, leaving holes for the trimpots.
CONCLUSION
Two circuits using the LM335 for thermocouple cold-junction compensation have been described. With a single room
temperature calibration, these circuits are accurate to
±%·C over a O·C to 70"C temperature range using J or K
type thermocouples. In addition, a thermocouple amplifier
using an LM335 for cold-junction compensation has been
described for which worst case error can be as low as 1·C
per 40"C change in ambient.
APPENDIX A
DETERMINATION OF SEEBECK COEFFICIENT
Because of the nonlinear relation of output voltage vs. temperature for a thermocouple, there is no unique value of its
Seebeck coefficient oc. Instead, one must approximate the
thermocouple function with a straight line and determine ex:
from the line's slope for the temperature range of interest.
t A collection of thermocouple tables useful for this purpose is found In the
Omega Temperature Measurement Handbook published by Omega Engineering, Stamford, Connecticut.
TABLE II. Linear Approximations to Type S Thermocouple
Centigrade
Temperature
0"
5·
10"
15·
20"
25·
30"
35·
40"
45·
50"
55·
60"
65·
70"
TypeS
Thermocouple
Output (/LV)
0
27
55
84
113
142
173
203
235
266
299
331
365
398
432
Approximation 'iF 1
Zero Error
at 25·C and 60"C
Linear
Approx.
Approximation 'iF 2
Zero Error
at 30"C and 50·e
/LV
·C
Linear
Approx.
-17
-12
-9
-6
-3
0
1
3
3
4
2
2
0
-1
-3
-2.7"
-1.9"
-1.4·
-0.9"
-0.5"
0
0.2·
0.5·
0.5·
0.6"
0.3·
0.3·
0
-0.2"
-0.5·
-16
16
47
78
110
142
173
204
236
268
299
330
362
394
425
Error
-17
15
46
78
110
142
174
206
238
270
301
333
365
397
429
oc =
6.4 /LV/·C
O.6"C error for
20"C < T < 70"C
Error
oc =
/LV
·C
-16
-11
-8
-6
-3
-1
0
1
1
2
0
-1
-3
-4
-7
-2.8·
-1.7·
-1.3·
-0.9·
-0.5·
-0.2·
0
0.2"
0.2·
0.3·
0
-0.2"
-0.5·
-0.6·
-1.1·
6.3 /LV/·C
0.3·C error for
25·C < T < 50"C
Note: Error is the difference between linear approximation and actual thermocouple output in ",V. To convert error to 'C, divide by Seebeck coefficient
447
z
~
en
~ r---~--------------------~----------~--------------------------------~
APPENDIXB
This procedure compensates for all sources of 'drift, includ- '
;
TECHNIQUE FOR TRIMMING OUT OFFSET DRIFT
ing resistor TO; reference drift ,( ± 20 ppml"C rriaximum for
Short out the thel'mOCO,uple input and measure the circuit : the LM329B) aM op amp offset drift; Perfoonance will be
limited only by TC nonlinearitias aM measurement accuraoutput volflige at i!5°C 'and "at 70"C. C8lculatethe outPut
cy.
voltage temperature coefficient, /3 as shown:' ":
/3
= VOur l70'C) - VOut!25"C) in mVl~K '
45°K
,
'
"
Next, short out the LM329B and adjust thl! TC ADJ POt so,'
that VOUT = (20 mVloK - /3) x 298°K .t 25°C. Nowr&move the short across the LM329B aJ:1d adjust the ZERO
ADJUST pot so that VOUT = 246 mV at 25"C (246 times the
25°C output of an ic;e-point-referenced thermocouple).
REFERENCES
R. C. Dobkin, "Low Drift Amplifiers," National SemicoMue- "
tor LB-22, JUne ,1973.
' ""
Carl T. NelsOn, "SuPer Matched Bipolar Transistor Pair 'Sets '
New Standards for Drift and Noise," National Seriticondu(:.'
tor AN-222, February 1979.
"
448
~
National Semiconductor
Application Note 227
Applications of Wide-Band
Buffer Amplifiers
v·
INTRODUCTION
The LHOOO2, LHOO33 and LH0063 are wide-band, high current, unity gain buffer amplifiers. They are intended for use
alone or in closed-loop combination with op amps to drive
co-axial cables and capacitive or other high-current loads.
Features and characteristics of these buffers are summarized in Table I. All are active trimmed for low unadjusted
output offset voltege and uniform performance. Good thermal coupling between dice is achieved by hybrid thick-film
construction on ceramic substrates.
Part I analyzes the AC and DC equivalent circuits.
Part II is a comprehensive guide to applications techniques
and shows how to get optimum performance under a variety
of circumstances.
Finally, Part III illustrates these techniques in some specific
applications including drivers, sample-aod-hold amplifiers
and active filters.
"""
~OUTPUT
INPUT 0-
~~
v-
TLlH/8725-1
FIGURE 1_ LHOOO2 Simplified Output Stage
~
vc·
I
2
I. OIRCUIT DESCRIPTIONS
General
The three buffer amplifiers share a similar class AB emitterfQllower output stage as shown in FtgtJr6 1. The symmetrical
class AB amplifier output provides current sourcing or sinking and relatively constant low impedance to the, load during
positive and negative output swing. The input stage of the
LH0002 consists of a complementary bipolar emitter-follower. The LH0033 and LH0063 employ junCtion FETs configured as source-followers, thereby achieving several orders
of magnitude improvement in DC input resistance over the
LHOO02. In each case, the output stage collectors are uncommitted to allow the use of current limiting resistors in
series with either or both output collectors.
RI
5k
~113
t
3
~E3
R3
2
B
4
INPUT~
~OUTPUT
R4
2
6
~02
LHOOO2 Low Frequency Operation
The LH0002 circuit shown in Figure 2 is a compound emitter-follower with small-signal current gain of approximately
40,000 (product of first and second stage betas).
~E4
~04
R2
iii!
.....
I--
v-
7
6
vc-
TL/H/8725-2
FIGURE 2. LHOO02 Schematic Diagram
,TABLE I. Buffer Amplifier Typical Characteristics
LHOOO2
LHOO33
LHOO63
Unite
DC Output Current Continuous
±100
±100
±250
mA
Peak Output Current
±200
±250
±500
rnA
200
1500
6000
V/p.s
50
100
160
MHz
0.97
0.98
0.96
VIV
±10
±5
±10
mV
6 p.A
50pA
100pA
6
6
1
Parameter
Slew Rate
CondlUona
RL
= 1 kO, Rs = 500
Bandwidth, 3 dB
Voltage Gain
Output Offset Voltage
Input Bias Current
= 1V@ 1 kHz, RL = 1k
To = 25°C, Rs = 100 kO
(Rs = 3000 for LHOOO2)
To = 25"C
Y,N
Output ReSistance
,449
0
Ope~atiomiS
symmetrical, and ihe circuit .may be analyzed
If Vs= ± 15V, tl1eLH0002 can tl)eoretically;.d,eliver, about
500 'mA peak ihtO shorted load (in practice, only 400 mA
peak can be realized, for the current densi\}':ln the, output
transistors limits the beta to about 150) or'1'80 mA peak into
500. Current limiting may be employed for short circuit protection (see section on Current Limiting).
by cOr'1sidering only the upper or the lower half of the circuit
a
80S r8drawn in Figure 3. Input stage operating current is dei~rmined by R1 in conjunction with supply and input voltages. For VIN = 0 and Vs = ±15V, first stage quiescent
'
current is typically:
Ie =
Vs - VBE - VIN
15 - 0.6S - 0
R1
=
50000
= 2.88 mA
The voltage gain of the LH0002 is slightly less than unity
and is a function of load lis with any emitter-follower. It is
dominated' by the finite output resistance. of the output
stage. Hence, the gain analysis for all three buffers can utiliie the 'hybrid '1r model as shown in Figure 4. Note that. re3
is the emitter dynamic resistance 'of
and is '1oad-cilrrent
dependent. The gain' expression written as a function of
load resistance and input voltage is: '
(1)
The normal production variation of Ie is ±5%.
The emitter-base junction of the first and second stages
appear in series between input and output terminals, therefore the output offset voltage for VIN = 0 is the difference in
base-emitter junction voltages of a PNP and an NPN transistor. This is true for both upper and lower halves of the
circuit, so there is no conflict between the two circuit halves.
Output stage quiescent current will equal that of the input
stage if the transistors are matched and at equal temperatures. This establishes a class AB bias in the output stage
sci there is no class B crossover distortion in the output.
Resistors RS and 84 inserted in the outpUt emitter circuits
minimize the effect of 'unmatched upper and lower circuit
halves and limit the potential for thermal runaway due to
input and output stage temperature differences. There is no
thermal runaway it operation is confined within data sheet
limits.
as
Av'"
R3
0.026)
Vo + o.oaSRl
,"
(
0.026)
RS+Rl1+-VIN 'VIN > O.1V
Voltage gain could range from 0.996 for Fi l = 1 kO to 0.978
for Rl = 1000 at 10V input. ·In contrast. the saine loads
would yield gains of 0.97S to 0.956, respectively, for an input of 1V because re3 would be somewhat larger:
Because of the inherent current-mode feed~ack, initial offset error is typically 10 mV with a finite (SOOO) series, input
resistance: Even with unsymmetrical supplies, Vos increases only an additional S mV Per volt of supply differential.
Usually tliis error component may be ignored. as it is relatively small compared to the large-signal error' predicted by
equation (S) when driving heavy It:lad~. '
Vs - VBE3 - loRS - Vo
,
RlI,83
'
Vs - VBE3
Vs - 0.7
R1/,83 + RS + Rl "" SO + Rl
+ Rl ( 1 +
(S)
Maximum output current is dependent on the supply voltage, R1, OS current gain, and the output voltage. Maximum
current is available when VIN rises sufficiently above VOUT
that 01 is cut off. Unde~ this condition, the 5k resistor supplies base current to OS, and the maximum output current
is:
IO(MAX) =
Rl
,Rl + RS + re3
(2)
where,83 "" 200.
V+
R3+ '.3
VIN
VOUT
-r,0
VIN
RL,
TLlH/8725-4
Where: '.3
~
0.026/10
FIGURE 4. Equivalent Model of LH0002
";'
VOUT
• TL/H/8725-3
FIGURE 3. LHOOO2 Half Circuit
450
LHOO02 High Frequency Operation
R2
) (
.B3Rl
)
(
eo(s) .
.B3Rl + rout
ein(S) = [1+ s (R211Rsl C' CBll [1+ s (routll.B3RLl CcB3l
'R2'+'Rs
The high frequency response is limited primarily by internal
circuit capacitances; most significant are the junction capacitances shown in Figure 5.
(4)
'"
Av (low frequency)
(1 + s RsCcBl) (1 + s reI CCB3)
To illustrate, for Rs = 300.0, the primary pole il! predicted to
occur at about 60 MHz, a close correlation to the real value,
while the output pole is well beyond 1 GHz. The implication
of this analysis is quite significant-the fundamental bandwidth of the LHOO02 is a function of the input source resistance within a reasonable range of 500 to 3000. For the
case of Rs = 500, the resulting bandwidth is well above
100 MHz.
Since the base-emitter junction capacitances of emitter-followers see little effective junction voltage change, they may
be neglected in the following first-order analysis. For the
transistors used we may also assume that the transistor delay and transit time effects are over-shadowed by the RC
effect. We can then simplify the half-circuit to that of Figure
6: a single transistor emitter-follower plus an equivalent load
reflected from the output stage.
Evaluation of the transfer function of equation (4) as derived
from Figure 6b indicates that the input pole dominates for
finite source resistance.
YOUT
YTl/H/8725-S
FIGURE 5. LHOO02 High Frequency Circuit
y+
RI
'IN~.
" -. .--oO°OUT
CCsIT lR2
RS
-
'OUT
m
'\.,02
~RL
TCCB3
- - -- --
Ccea'"SpF
Whe,e: 'oUT '" (,.,
R2
Tl/H/872S-8
FIGURE 6a. LH0002 Simplified Mirror-Helf Input Stege
+ ~)
= ~, ('., +
Rl
TL/H/872S-7
IIRI
I ~3 RLl
FIGURE 6b. Hybrid '7T Model
451
OUT
.l'F
.lIre'
I TA=25"C
RsbRL=504
2V
8.. ••• . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INPUT~
2V
11
II
\.~-;o....-1
10···· ••••••..
I
IOns
IOns
2V
.TLlH/8725-9
a. Negative Pulse Response
.... .... ............ .... .....
INPUT
OUTPUT
b. Positive Pulse Response
l
II .
1\
.... ....
.. ..
90···· ••••••••
INPUT
I
r+~-r-+--~T--H-+~~+-1
OUTPUT
~
I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
~IJ~
I""*"'..,..'W+OO.......~\.~..~....;..-""I
J
\:'!o .......... ..
I ..........................
J
IOns
2V
.J TA=25"C
I,!JO--+---+-+--+-I---+- Rs=50D:, ~=1 KA
k+1~~w.+-~+-f-t"'l+iJI~.-r-~
,
.l
2V
I TA=25"C
Rs=50Jt, RL=IKA
2V
•• ".
OUTPUT i<--V-,.t.--+--+-+-r-+---t--"'oo;l:
TLlH/8725-8
.lIF
~,'
INPUT r+1J/'t';:.
'·1····· ..................................... .
2V
• '0' ~ •••.' ."
~~~~~:'t.\;Oo~.--r.,."'.. M
.
OUTPUT loIoi""t:""'Io-~"""+~~+tlf!!l'l"""''',~:,"'''!'f
TA=25CC
~s=RL=500
~...
~
I
II
I.
.
90' • •• •••• •••• •••• ••••
IOns
2V
TLl1j/8725-10
TLlH/8725-11
c. Negative Pulse Response
d. Positive Pulse Response
FIGURE 7. LH0002 Pulse Response
LHOO02 Large Signal Pulse Response
is drawn from the output, 01 and 02 will drift at slightly
different rates as 101 will no longer equal 102 by the differ·
ence in output stage base current. Resistor R2 is trimmed to
establish the drain current of current·source transistor 02 at
10 mA, and R1 is trimmed for zero offset.
Figure 7 shows the typical large signal pulse response of
the LH0002.
LHOO33 Low Frequency Operation
The LHOO33 circuit can be described in simplified form, Fig·
ure 8, as a source-follower plus a balanced emitter·follower.
The complete circuit is shown in F/{/ure 9.
v,
y+
12
1
y+
YOUT
OUTPUT
Y-
TL/H/8725-12
R2
100
FIGURE 8. LHOO~3 Simplified Circuit
When 01 and 02 are well matched, offset voltage and drift
will be low because the gate-source voltage of 02, VGS2, is
set "'2 VeE, thus forCing VGS1 = VGS2 due to the matching
when operating at equal currents. However, as load current
Y-
10
TLlH/8725-13
FIGURE 9. Complete LH0033 Schematic Diagram
452
The same current flowing through 02 also flows through 01
and R1, causing a gate-source voltage of approximately
1.6V. The 10 mA flowing through R1 plus 03's VeE of 0.6V
causes VOUT = 0 for VIN = O. The output stage current is
established to be approximately equal to that of the input
stage by 03 and 04.
Voltage gain is predicted to be 0.995 for a 1 kO load, and
0.95 for a 500 load at 10V output.
LHOO33 HIgh Frequency OperatIon
Low frequency performance is modified at high frequencies
by the increasing effect of transistor junction capacitance.
Transistors 03, Q4 and the output emitter-follower pair contribute only minor incremental effect on the first-order high
frequency equivalent circuit so they may be omitted to yield
the simplified model appearing in Figure 11. Modeling of
transistor 01 reduces the circuit to that of Figure 12.
Voltage gain of the LH0033 is the product of the 1st and
2nd stage gains taken independently. The analysis of each
is shown in Figure 10. We can write the total amplifier gain
expression as:
1
~=
1 + 2/RL
where'/35 "" 200.
~
+ 1671/35RL + 0.261V1N
YI--
TL/H/8725-15
Avl
ROlllsRL
= ROJJIlsRL + l/l11al
1
+ Rl
1
YOUT
+ 167/RO + 167/1lsRL
for. lllal .. 0.015 mho
RO '"
~ (I + 9fa2R2) = 125 kIl
IIos2
TL/H/8725-16
Av2=
TL/H/8725-14
RL
a. HybrId 1T Model of FET Source-Follower IncludIng Effect of Output Load
+
RL
Re
+ r8S
1
1
+ Re/RL + 0.0261VI
b. Output Stage GaIn wIth the Effect
of EmItter DynamIc ResIstance
FIGURE 10. Voltage GaIn AnalysIs of the LHOO33
TLlH/8725-18
Where: RI'- = Rl + lIg181
RL = RoIIllsRL
~ = GGD2 + Gess
+ CC86
FIGURE 12. LHOO33 HIgh Frequency CIrcuit Model
TLlH/8725-17
FIGURE 11. LH0033 SImplifIed CIrcuIt
453
where· I is ·the _input stage current available to .-charge the
circuit- capacitance C:;L.·'
With the I::Ho.o.33, the positive slew i&'2-3 times greater
than the" negative slew. ,The' pulse response in FigUriJ 13
Illustrates this. The reason is 'that during pOsitive sl$vi;'the
peak charging current is limited by the value of·Rl·plus Rs
when the FET gate-source junction is forward biased. This
could be ·3o. mA-40'mA peak, allowing a typical.slew rate of
3,000. VI p.s.
The LHo.o.33 negative-going slew is limited by its input stage
quiescent current of 10. mA established by the FET current
source. As the inpUt transi$tqr tends to shut off, the 'circuit
capacitance discharges into'the current source (si(1k) at a
rate of 10. mA. Therefore, the slew rate is computed to be:
dv 1o.mA
dt = 9.5pF = 1,o.5o.V/p.~
Capacitors GeB5 and CcB6 are collector-base juncti!;ln capacitances of 05 and 06,typically 3 pF each. eG01 and
CGD2 are the gate-drain capacitances of the FETs, iypic;ally
3.5 pF each. The frequency-dependent' transfer furit:lion of
,.
the circuit is: .
, eo(s)
.. "RL/(Rl. +'R1)
'~ln(S) = [1 + s RsCGD1U1 +s(R,..IIRL,) GLl
(6)
Notice that unlike ,the LHo.o.o.2, the output pole (s =
11R",CL,). dominates the prilj18ry frequency,resPQnse roll-pff
occurri(1g at about, 10.0. MHZ with an input source-fesi~nce
Rs = 50.0. The user is cautioned that as Rs increases, the
secondary (input) pole will begin to take effect. To illustrate,
for Rs = 30.0.0, the secondary pole will have moved from
900 MHz at Rs = 50.0 to about 150. MHz.
LHOO33 Slew Rate
The slew rate of the buffer is predicted by equation (7),
elv
=-.!...
dt
CL
(7)
.l
.l'I'"
J.
2V
TA=~5CC
'r-I--t--I---t----1I---I----11- Rs=RL=SOIl
90••••••••••••••••••••••••••••• ,
eo
.
T
TA=15oc
~ Rs=RL=500
'II '
~UTPUT ","\~-+-O+-+--i~I~
1.......j.o.-.j.o.'.
.~,;
.
'., .' ~
.:,' :.
456
''",.-:.'-
Power Disspatlon and Device Rating
The load-related power is the average power dissipated in
the output stage. It may be estimated as the product of
average current delivered to the load and the average voltage across the output stage. Because of the high-current
capability of the buffers, it is essential to observe the device
dissipation limits. Safe operating areas for each buffer are
presentlld in FlfJure 18. A note of caution: these plots are
valid only for. 25°C ambient. Additional power derating
based on the power derating curves of Figure 17 is mandatory for operation at higher ambient temperature.
Each data sheet· specifies the conditions for safe operating
power dissipation. These limits must be observed for both
continuous and pulsed conditions. Figure 17 shows the
power dissipation limits versus temperature for each device,
both with and without heat sinks. To compute total power
dissipation, the standby power must be addEl~ to the loadrelated power.
The standby power drain is computed from the device DC
operating current and its operating voltage:
Pstandby = (Vs+ - Vs-)Is
(10)
LHOOO2 Maximum Power
Dissipation
1.8
u
i
1.2
i
1.0
'"'
I .•
CI
II<:
0.8
i
0.4
1
I
1
2.0
I
T\
I'
AMBIENT ~
6JA j'2,Cj
0.2
1
25
z
CI
;::
1.5
§
1.0
~
CI
II<:
\.
N
;
2
LH0063 Power Dissipation
,
r-- ~
i
CASE8J -15" CIW
1
1
LHOO33 Power Dissipation
I
C1SE
"\.
.........
AMBIE~
6JA·'00"CIW
0.5
CASE
~C-"'CIW-
OJ~ • 15·JIW
~
AMBI~NT6J~ .~CIW
"
""
r-.....
\
........
~
1
25
50 15 100 125 150 11& 200
50
15
In
TEMPERATURE r C)
TEMPERATURE ('e)
a.
b.
125
150
Z5
50
75
101
TEMI'ERATURE
125
1&0
rc)
TL/H/8725-27
c.
.FIGURE 17. Device Power Dissipation
LHOOO2 Sate Operating Area
LHOO33 Safe Operating Area
150
1
!i
c
.s...
50
~
'00
c
.s
50
!; -50
...~~ -100
0:
0:
,.
-50
,.I!:co
-'00
-150 L....-'-_-'---l_...L._.L..........
-15 -10 -5
10
15
OUTPUT VOLTAGE (V)
I--+-~FI+H
'00
5
.
.
,.
zoo
15
0:
0:
0:
,....
,.I!:co
LH0063 Safe Operating Area
~ r-~--~~~~~~
'iD
-'00
co
-150 L....-'-_-'-......_...L._.L....-I
10
15
-'5 -10 -6
-zoo
-300 L....-'-_.1.........._...L._.L....-1
-'5 -10 -5
'I
15
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TUH/8725-28
a.
c.
b.
IIllJ DC BREAKDOWN
mil CASE POWER DISSIPATIDN
III AMBIENT POWER DISSIPATION
Tl/H/8725-29
FIGURE 18. Safe Operating Areas at 25°C and Vs = ± 15V
457
~r---------------------------------------------------------~
N
~
III(
Peak Power DI88lpat1on
An often overlooked power dissipation factor exists when
driving a reactive load. Consider the LH()()()2 with a possible
400 mA peak current drive capability when driving 10V
square pulses into 1000 pF. At the rising edge, the upper
device transistor charges the capacitor at its limiting current
The charging waveform is not linear, in fact it approaches a
logarithmic curve beCause the resistor R11P3 appears as
the principal value of charging resistance [see equation (2)].
The instantaneous power dissipation is simply the product
of V+ and 10(MAX)' or 6W, with occurrences at the positive
and negative leading edges. Once the load capacitor is
charged, the negative leading edge instantaneous peak
power is somewhat greater because the power dissipated in
the lower output transistor is (Vo - V-) 10 = 2510. The
PNP pull-down transistor has slightly lower p, limiting peak
current to less than 400 rnA, therefore the peak negative
edge power is just under 10W in this instance.
Figure 19 indicates the output voltage and current relationships as well as the power dissipation versus time for the
pulse waveform into a capacitive load.
Obviously, the average power dissipation under peak current drive conditions is dependent upon the pulse repetition
frequency, and becomes increasingly dominant as the PRF
increases.
Because each of the buffer amplifiers may be operated on
dissimilar supply voltages fqr input and output stages; device power dissipation is reduced. by lowering the output
stage supply vo~s while retaining the input stage su~
plies at a higher level for best current driving capability. The
limiting factor is, of course, a reduced output voltage swing.
Current Umltlng
Current limiting may be provided in either of two ;.Yays: by
adding series resistors at the collectors of the output stage,
or by a single series resistor at the buffer output The first
method (FIgUre 20) is preferred as there is little effect on
output resistance and peak current drive. However, the output voltage swing is reduced by the voltage drop across
these resistors. Their value is determined as follows:
V+
VRLIM = - - - (11)
18C+' Iscwhere Isc = 100 mA for LH0002 and LHOO33, and 250 rnA
for LH0063.
TLlH/8725-30
PEAK POWER
Pto
= (15V -
0v) (0.4A)
=6WPEAK
Pl1 = [10V - (-15V)J (0.411)
TLlH/8725-31
= 10WPEAK
.LH0033 and LHOO63 only
FIGURE 19. Peak Power DI88lpatlon
Into Pure Capacitive Load
FIGURE 20. Current UmlUng using Collector ReaI8tora
458
The output collectors should be bypassed with 0.01 jl.F capacitors in addition to the normal supply bypassing, as
shown in Figure 20. The 0.01 jl.F capaCitors will allow full
output voltage and current on an instantaneous basis for
transient pulses yet at the same time prevent output stage
resonant oscillation.
Alternate active current limit techniques .that retain almost
the full DC output swing are shown in F/{JUre 21. In these
circuits, the current sources are saturated during normal operation and thus apply nearly full supply voltage to the load.
Under fault conditions, the voltage decreases as determined by the overload.
For applications where the buffers are inside the feedback
loop of an op amp such as LH0032, LH0024, LHooS2 or
LM118, a single current limiting resistor may be placed inside the feedback loop at the buffer output as shown in
FtgUf6 22. Its value is also computed as RUM = V + lise.
Heat Sinking
In order to utilize the full drive capabilities of these devices,
low thermal resistance heet sinks should be used. The cases of all three devices are isolated from the circuit and may
be connected to system ground or to the buffer output as
desired. The following list gives thermal reistance of various
heat sinks available for the buffers.
For Figure 21a, the limit-set resistor is set for SO rnA.
TABLE II. Heat Sinks For LH0033 and LH0063
LHOO33
LHOO63
RLIM = VBE/lse = O.SV/O.OSA = 100
In Figure 21b, the current limit has been set to 200 mAo
Thermalloy 2240A, 33°C/W
Wakefield 215CB, 300C/W
IERC UP-T08-48CB,
15°C/W
VBe
O.SV
RUM ISC = 0.2A = 3.00
ThermalloyS002B-19, SOC/W
IERC LAIC3V4BC
IERC HP1-T03-33CB
7"C/W
INPUT
TLlH/8725-33
TLlH/8725-32
b.
a.
'LHOO33 and LH00S3 only
FIGURE 21. Current Umltlng using Current Sources
459
~ r-----------------~------~--~--------------------------------------------------~
~
~
CapaCItive Loads
is accomplished with a 2000 variable resistor inserted, batween V- and pin 7 of the LH0033 or pin 6 of the LH0063. It
is good practice to insert a 200 resistor in series with the
variable resistor to limit excessive ,power dissipation at the
input stage when the pot is at minimum value. The offset
adjustment range is typically ±400 mV.
All three devices are capable of driving relatiVely high'capacitive loads. Because capacitive loacis on emitter-followers are reflected to the input as negative resistan~, it is
necessary to add seime series compensating positive real
resistance; 500-3000 is usually sufficient. An alternative is
to insert the current limiting resistor at the output as ahown
in Figure 22. This will isolate the, capacitive load from the
buffer.
'
When a buffer amplifier is used as a current booster in conjunction with an operational amplifier, as in Fl{}ure 22, there
is usually no need for output offset adjustment, since the
offset is reduced by the open-loop to closed-loop gain ratio.
The total offset of the closed-loop circuit is:
Any of the buffers can drive twist~ pair, shielded or cOalQal
cables, or other reactive Ipads. For all practical, purposes,
an unterrninated coaxial cable presents a capacitive ,load ,to
the driver. On the other hand, terminated coaxial cables appear as resistive loads; and therefore may not. require the
compensation for'capacitive loads. Don't fOrget consideration of peak power dissipation when drMng cable loads,
since they may represent capacitive lOads' (see sectiorion
Peak Power Dissipation).
'
VOS(TOTAL)= V,OS ± Voos AcL
(12)
AoL
where: V,OS = input offset voltage.
Voos = buffer offset voltage.
Slew Rate
Slew rate is the rate of change of output voltage for largesignal step input changes. For resistive load, slew rate is
limited by internal circuit capacitance and operating current.
Figure 23 shows the slew capabilities of the buffers under
large-signal input conditions.
Offset Voltage and Adjustment
Offsat voltage Is measured with V,N = O. As V,N and IL are
increased, the, apparent offset voltage will change. This is
due primarily to a gain which is less than unity (inherent in
an emitter-follower). The effect of this is discussed in detail
in the section on Circuit Description. Both the LH0033 and
LH0063 have provisions for, offset voltage adjustment.
When not required, the OFFSET ADJUST pins of these two
devices should be shprted. When adjustment is desired,
they should be open-circuited, and the external adjustment
However, when driving capacitive load, the slew rate may
be limited by available peak output current according to the
following expression.
dv/dt = Ipk/CL
(13)
L_ "
~>-IVI&~IV-"'~>"""'I\ojR'IoLlI\oM~~ODUTPUT
I --'/
,
INPUTo-1+ - . , - ; / '
~OOO2. LH0033. DR LHOO63
V
TL/H/8725-34
FIGURE 22. Current Limiting Inside an Amplifier/Buffer Loop
l .I
5V
1.
TA=25"C
lj1o, -t--+-+--+--f--t-Rs=SOD:, RL=1 KA
10···· ....
90....
1-..':-+-/7"I--+--I-4--I--+--+--+--I
FALL
J.
'SV
TA=25"C
lr-t--+-+--+-.f--+-+Rs=RL=SOKA
"
.. . . . . . . . . . .
J
RISE
lJ
RISE
1····
........... .
I
:~~~~~~~~~~
T
Sns
_./
\.
10. . . . . . . . . . . . . .~~ .. ..
I
2ns
TLlH/8725-S5
TLlH/8725-38
a. LHOO33 Slew Response
b. LHOO63 Slew Response
FIGURE 23. Positive and Negative Slew of Each Buffer
460
Note that the peak current available to the load decreases
as CL changes [see equation (2)]. Figure 24 illustrates the
effect of the load capacitance on slew rate for the three
buffers. Slew rate tests are secified for resistance and/or
very small capaCitance load, otherwise the slew rate test
would be a measure of the available output current For
highest slew rate, it is obvious that stray load capacitance
should be minimized.
distortion. The LH0063 may exhibit a small amount of crossover distortion in some circumstances due to the relatively
low 1 mA output stage bias. The heavy local feedback inherent in emitter-follower or source-follower operation provides
a very low distortion output. The remaining distortion
«0.1%) is primarily due to the modulation effect of nonconstant VeE as the output voltage changes.
Closed-Loop Feedback Operation
Any of the buffer amplifiers may be used inside an op amp
feedback loop. When this is done, the additional phase lag
introduced by the buffer must be included in loop stability
consideration. With most op amps, the bandwidth of these
buffers is so great that the op amp totally controls the loop
stability. However, when using very wide-band op amps
such as the LH0024, LHOO32, and LHOO62, the small additional phase lag of the buffers should be taken into consideration. F/{/Ute 25 presents the Bode plots of gain and
phase for the three buffers. The phase margin and open
loop frequency response is altered by the additional pole(s)
contributed by the buffer. The buffer phase shift is algebraically summed with the op amp phase shift, and may cause a
stable op amp loop to become marginaily stable depending
upon the relative positions of the op amp and buffer poles.
In general, the buffer bandwidth should significantly exceed
that of the op amp, so that the loop performance will be
determined solely by the op amp.
1000
~...
!C
oc
!I
......
100
10
'"
0.1 .........................WIIII..........................
0.1
10
100
1000
CAPACITANCE (nF)
TUHf8725-37
FIGURE 24. Slew Rate V8 Load Capacitance
Distortion
The output stage of the three buffer amplifiers are biased at
1 mA to 10 mA to remove any possibility of crossover
LH0033 Frequency Response
40
r Ys·flIY
RS-1iOn
RL -&10
r YIN -I.OVrn
LHOO02 Frequency Response
-411
1.0
~
'c"'
...
c
...,..co
....... ~
0.8
0••
..
./
...a"'
-I. ..."'
-8
1.0
:c'CD"'
0.8
CD
0.8
./
Z..
5.0 10.0 ZO.O
50.0 100
DA
"'"'
1.0
U
&.0
10.' 20.0
CD
,..co
220
1111
Ay
\
.8
!1
.8
2111
180
1111 ~
140 ~
lZ8
III
80
A
80
.z
i-'"
180
10
..
..
£
am
011
m
;;
41
(>
II
o
1
III
TUHf8725-39
III
i!
...
&0
FREQUENCY (MHz)
LH0063 Frequency Response
!!
cCD
011
;;"'
/
Ie
TLfHf8725-38
~
Z5
I.
A
°
r-
---j
20
FREQUENCY (MHz)
I.'
..'"
I,.
.... J
.
I I. a.."'
I
:10
,/
1.0
Ay
8.Z
011
4>
~
...
i!
...,..co
-Z4 ~
/
0.2
...:z:
lIi
J
OA
u
-3Z
'"
YIN - I YRMS, RL -&lID,
Ys- tlZ•• Y, TA _Z5° C
CD
CD
Ay
~
3S
30
20
D
I.
FREQUENCY (MHz)
FIGURE 25. Phaae-Galn Relatlonshlpa of Buffers
461
TUHf8725~40
load {II about half what it wouJd,be without, the near end
tennination. '"
The LH0033and LHOO63 areaseful in high spe8lhampleand-hold or peak detector circuits because of their very high
speed and :Iow-bias'current FET input stages. The bigh
speed peak detector circuit shoWn in, Figtn 27 cOuld be
ohanged to II samplEl"and-hOld circuit simply by removing
the detector diode and the reset circuitry. For best accuracy,
the circuit offset may be trimm!ld with the ,1 0 kO offset ad·
justment pot ,ShoWn. The C!tcuit has 'a typical acquisition
time of 900 ns, to '0;1% ,~ fln~1 value for 10V input step
signal, and a droop rate of 100 p.Vlms. Even faster acquisi·
tion time caR be achieVed bY'reducing the hold capacitor
value.
'
"",
III. APPUCATIONS CIRCUITS
Because of their high current drive capability. the LHOO02,
LHOO33 'and LHOO6S buffer amplifiers are suitable for driv·
ing terminated or untermlliated coaxial cables, and high cur·
rent or reaCtive loads. CUrrent limiting resistors should' be
used to prcjtect the deviCe from excessive peak load cur·
rents or accidental short circuit There is no current limiting
built into the devices other than that imposed by the limited
beta of the output transistors, Figtn 26 shows ,a coaxial
cable 'drive Circuit. The 430 resistor matches the driving
source to the cable; however. 'its inclusion
rarely result In
Visible improvement in pulse response into a terminated ca·
ble. If the 430 resistor is inCluded, th9 output voltaQe to the
will
-FOr. LH0002, RUM = loon.lw
LH0033, RUM = loon, lW
LHOO63, ~UM =, ~n, 5W ,
,
--Jumper for LH0033 and LH00S3 only.
TUH/8725-41
FIGURE 26. CoaxIal cable DrIve CIrcuit
11V
TUH/8725-42
FIGURE 27. HIgh Speed Peak Dete~ with Hold andR. Control.
462
The LH0033 may be used as a cable-shield driver as shown
in FI{J/Jre 28. The adVantage is that the source driver is not
required to charge the line capacitance of the unterminated
coaxial cable, and indeed does not need to match its line
impedance; therefore, high speed data transmission is permitted.
The buffers may be used with a single supply without special considerations. A typical application Is shown in Figure
29. The input is DC biased to mid-operating point and is AC
coupled. Its input impedance is approximately 500 kG at low
frequencies. Note that for DC loads referenced to ground,
the quiescent current is increased by the load current set at
the input DC bias voltage.
r
The high input impedance of the LH0033 and LH0063 are
suitable for active filter applications. A basic two pole, high
pass filter is diagrammed in FI{JIJf'9 30 using the LH0033.
The circuit provides a 10 MHz cutoff frequency. One consideration of the filter is its apparent gain change due to the
finite output impedance of the amplifier, which affects the
overall gain and the damping factor of the filter stage. Resistor R3 ensures that the input capaCitance of the amplifier
does not interact with the filter response at the frequency of
interest.
An equivalent low pass filter is similarly obtained by capacitance and resistance transformation.
Vcc= lZ.0V
OUTPUT
IUNTERMINATEDI
y+
D.lpF
-
IN'UTOO. .- -.....
TLfH/8725-44
FIGURE 29. Single Supply
AC Buffer AmplHler
VTLfH/8725-43
FIGURE 28. High Speed Shleld/Une Driver
HI
79.&
Cl
l00pF
INPUT~
>':':"-~"'ODUTPUT
--
VTLlH/8725-45
FIGURE 30_ Wide Band Two Pole High Pasa Filter
463
The most common use of the buffers is inside an op amp'
feedback'ioop as shown in Rgure31. Theci1artln the figure.
shows the ideal match of the buffer family to most popular,
operational amplifiers.
REFERENCES "
"Application of' the LHO002. Current Amplifier.," ,National .
SemiCOnductor Corporation•. AN-13; September 1968.
B. Siegel and 'L: Van Der Gaag. "Applications For'a New .
Ultra-High Speed Buffer;" National Semiconductor Corpora- •
tion. AN-48. August 1971.
George S..MoschYtz. "Unear Integrate~Ne~o,rks Design,"
Ch. 3•. Active Filter Building Blocks.
O.Ii1
15V
Af'
INPuro-...,.v.,.......
. lise
>...-JW\t-. .OOUTPUT
-l&V
1t.IH/8725-47
Recommended
OpAmp
Buffer
LMIOI, LMI08, LM741, LF151
LHOOO2
LH0022, LH0042, LH0052
LFI55, LFI56, LFI57, LH0024, LHOO32
LHOO33
LH0024, LH0032
LH0083
Vs
Rso-
ISO
. ,FIGURE 31. Using Voltage Follower 8S Output Buffer '
464
The AID Easily Allows
Many Unusual Applications
National Semiconductor
Application Note 233
Accommodation of Arbitrary Analog Inputs
Note that when the input signal, VIN, equals VIN MIN the
"differential input" to the AID is zero volts and therefore a
digitel output code of zero is obtained. When VIN equals
VIN MAX, the "differential input" to the AID is equal to the
"span" (for reference applications convenience, there is an
internal gain of two to the voltage which is applied to pin 9,
the VREF/2 input), therefore the AID will provide a digital
full scale. In this way a wide range of analog input voltages
can be easily accommodated.
An example of the usefulness of this feature is when operating with ratiometric transducers which do not output the
complete supply voltage range. Some, for example, may
output 15% of the supply voltage for a zero reading and
85% of the supply for a full .scale reading. For this case,
15% of the supply should be applied to the VIN(-) pin and
the VREF/2 pin should be biased at one-half of the span,
which is Yz (85%-15%) or 35% of the supply. This properly
shifts the zero and adjusts the full scale for this application.
The' VIN( _) input can be provided by a resistive divider
which is driven by the power supply voltage and the VREF/2
pin should be driven by an op amp. 1his op amp can be a
unity-gain voltage follower which also obtains an input voltage from a resistive divider. These can be combined as
shown in Rgure 2.
This application can allow obtaining the resolution of a
greater than 8-bit AID. For example, 9-bit performance with
the 8-bit converter is possible if the span of the analog input
voltage should only use one-half of the available OV to 5V
span. This would be a span of approximately 2.5V which
could start anywhere over the range of OV to 2.5Voo
The RC network on the output of the op amp of Figure 2 is
used to isolate the transient displacement current demands
of the VREF/2 input from the op amp.
Two design features of the ADC0801 series of AID converters provide for easy solutions to many system design problems. The combination of differential analog voltage inputs
and a voltage reference input which can range from near
zero to 5Voc are key to these application advantages.
In many systems the analog signal which has to be converted does not range clear to ground (0.00 Voc) nor does it
reach up to the full supply or reference voltege value. This
presents two problems: 1) a "zero-offset" prOVision is needed-and. this may be volts, instead of the few millivolts
which are usually provided; and 2) the "full scale" needs to
be adjusted to accommodate this reduced span. ("Span" is
the actual range of the analog input signal, from VII'I MIN to
VIN MAX.) This is easily handled with the converter as shown
in Figure t.
_o----_~+
ADC0801
'VIN
VREF/2
"SMN"
+VIN MIN
'VIN MIN .0;; VIN
.0;;
VIN MAX
-2-
SMN
II
VMAX - VMIN
TLlH/5619-1
FIGURE 1. Providing Arbitrary Zero
and Span Accommodation
VCC =5VDC
VCC
UK
ADC08D1
35% OF VCC
lK
1----------------+ 15% OF VCC
75012
TL/H/5619-2
FIGURE 2. Operating with a Ratlometrlc Transducer which Outputs 15% to 85% of Vee
465
Llmlta of VREF/2 Voltage Magnitude
A question arises as to how small in value the span can be
made. An ADC0801 part is shown In FIgure 3 where the
VflEF/2 voltage is reduced in steps: from A), 2.5V (for a full
scale reading of 5V); to B), O.625V (for a full scale reading of
1.25V-this corresponds to the resolution of a 10-bit converter over this restricted range); to C), O.15625V (for a full
scale reading of O.3125V-which corresponds to the resolution of a 12-bit converter). Note that at 12 bits the linearity
error has increased to Yz LSB.
.For these reduced reference applications the offset voltage
of the AID has to be adjusted as the voltage value of the
LSB changes from 20 mV to 5 mV and finaHy to 1.25 mV as
. we go from A) to B) to C). This offset adjustment is easily
combined with the setting of the VIN MIN value at the VIN( - I
pin.
Operation with reduced VREF/2 voltages Increases the requirement for good Initial tolerance of the reference voltage
(or requires an adjustment) and also the allowed changes in
the VREF/2 voltage over temperature are reduced.
An interesting application of this reduced reference feature
is to directly digitize the forward voltage drop of a silicon
diode as'a simple digital temperature sensor.
"
•
,<,
"
Note that the VREF/2 pin of the converter is supplied with
·1/8 VREF so each of the f04r spans which are enCOded will
be:
.
.
In actual implementation of this circuit, the switch would be
replaced by an analog multiplexer (such as the CD4066
quad bilateral switch) and a microprocessor would be programmed to do· a binary search for the two MS bits. These
two bits plus the 8 LSBs provided by the AID give the 10-bit
data. For a particular application; this basic Idea can be simplified to a 1-bit ladder to cover a particular range of analog
input voltages with increased resolution. Further, there may
exit a priori knowledge by the CPU which could locate the
analog signal to within the 1 or 2 MSBs without requiring a
search algorithm.
A Mlcroproceuor Controlled Voltage Comparator
In applications where set points (or "pick points") are set up
by analog voltages, the AID can be. used as a comparator
to determine whether an analog input is greater than or less
than a reference DC vallie. This is accomplished by simply
grounding the VREF/2 pin (to provide I'l)aximum resolution)
and applying the reference DC value to the VIN(-I input.
Now with the analog signal applied to the VIN(+I input, an
all zeros code will be output for VIN( + I less than the reference voltage and an all ones code for VIN(+I greater
A 10-811 AppllcaUon
This analog flexibility can be used to increase the resolution
of the 8-bit converter to 10 bits. The heart of the Idea is
shown in Figure 4. The two extra bits are provided by the 2bit external DAC (resistor string) and the analog switch, SW1.
I_VI-~-l
(1 LSI = 20 MVI
+1LSI
t'"'..._I-""""....j--+_+-....-I--+_+-A_I..FU_LL...St-CAL"""*E=..
l-
I
.... 1
1
+1LSI[
~
i
...
II FULLSCALE = 1.2IIV
(1 LSI=5M¥)
-1 LSI
I
.... 1
[I
-1 LSI
+1.LSI
t
1""- 1.1
I .... 1
f"¥"1
4"4""-
=
CI FULL SCALE O.I12n
(1 LS8=1.22I1VI
-.-~~
a~
..'
-1 LSI
ANALOG INPUT
FIGURE 3. Linearity Error for Reduced Analog Input Spana
466
TLlH/6619-3
than the reference voltage. This reduces the computatiOnal
loading of the CPU. Further, using analog switches, a single
AID can encode some analog input channels in the "normal" way and can provide this comparator operation, under
microprocessor control, for other analog input channels.
and other set point values in the system. This Is a major
application area for the new generetion converter products.
Control Temperature CoeffIcients with Cqnvertara
The performance of many systems can be improved if voltages within the system can be caused to change properly
with changes in ambient temperature. This can be accomplished by making use of low cost 8-bit digital to analog
converters (DACs) which are used to introduce a "dither" or
small change about the normal operating values of DC p0wer supplies or other voltages within the system. Now, a single measurement of the ambient temperature and one AID
converter with a MUX can be used by the microprocessor to
establish proper voltage values for a given amblent temperature. This approach easily provides non-linear temperature
compensation and generally reduces the cost and improves
the performance of the complete system.
DACtI Mllltiply and AIDs Divide
Computation pan be directly done with convertar components to either increase the speed or reduce the loading on
a CPU. It is rether well known that DACs multiply-end for
this reason many are actually called "MDACs" to signify
"multiplying DAC.'! An analog product voltage is provided as
an output Signal from a DAC for a hybrid pair of input slgnals--one is analog (the VREF input) and the other is digital.
The AID provides a digital quotien~ output for two analog
input signals. The numerator or the dividend is the normal
analog input voltage to the AID and the denominator or the
divisor is the VREF input voltage.
High speed computation can be provided external to the
CPU by either or both of these converter products. DACs
are available which provide 4-quadrant multiplications (the
MDACs and MICRO-DACsTM), but AIDs are usually limited
to only one quadrant
Save an Op Amp
In applications where an analog signal voltage which is to
be converted may only range from, for example, OVoc to
500 mVoc. an op amp with a closed-loop gain of 10 is required to allow making use of the full dynamic range (OVoc
to 5Vocl of the AID converter. An alternative circuit approach is shown in F/gur9 5. Here we, instead, attenuate the
magnitude of the reference voltage by 10:1 and apply the 0
to 500 mV signal directly to the AID converter. The VIN(-)
input is now used for a Vos adjust, and due to the "sampled-data" operation of the AID there is essentially no Vos
drift with temperature changes.
Combine Analog Self-Teet with Your Digital Routlnae
A new innovation is the digital self-test and diagnostic routines which are being used in equipment. If an 8-bit AID
converter and an analog multiplexer are added, these testing routines can then check all power supply voltage levels
VIII(+)
AIICGIIII1
VllEF/2
TUH/~19-4
FIGURE 4. 10-BIt AID Using the 8-BIt ADC801
467
As shown in FIgUre. 5"all zeros will be output by the AID .for,
an inpulvoltage (aHheV'N(+) input) of OVocand all ones
will be output by the AID fQr a500mVOC Input signal. Operation of tIi'Ei AiD In thishigh'se;;sitiVity rriodecanbe useful
in many loW cost system applications.
".
DlglUzlng a Current Flow .
In $ystem applications there are many requirements to monitor the current drawn by a PC card or a high current load
del/ice. This typically, is done, by sampling the .load current
flow with a small valued resistor. U[lforlunately, it is. usually
desired that this resistor, be placed in series with the Vee
line. The problem is to remove the large common-mode DC
voltage, amplify the differential signal, and then present the
ground referenced .voltage to an AID converter.
All of ttJese. functions can bE! handled by the AID using the
circuit shown in FIgUre. 6., Here we
making use of the
differential input featurlil and the common-mode rejection 01
the AID to directly encode the voltage drop aQl'oss the load,
current sampling resistor. A[I offset voltage adjustment is
provided and the VREF/2 voltage is r\3duced to 50 mV to
accommodate the input voltage span 01100 mV. Ifdesil'Eid,
a multiplexer can be used to allow switching the V'N(-l input among many loads.
are
ConclusIOns
At first glance It may ,appear ,that the AID convertlilrs were
mainly designed for an easy digital interface to the microproceS$Or. This is true, but the analog interface has also
been given attE!ntion in the design and a very useful converter product has resulted from this ,combinatiOn of features.
FIGURE 6, Directly Encoding a Low Level Signal
--!!:..
O.ID
Vee
(IAMAX)
(+IVDC)o---1~+-W~""-----------"""
loomV
MAX
10D ~ .._v~oa:::ADoI
__~
AID
IK
, FIGU~E 8,' ~lglttZlng a Curr.~t Flow
468
TLlH/1l818-5
National Semiconductor
Application Note 236
An Introduction to the
Sampling Theorem
An Introduction to the Sampling Theorem
With rapid advancement in data acquistion technology (i.e.
analog-to-digital and digital-to-analog converters) and the
explosive introduction of micro-computers, selected complex linear and nonlinear functions currently implemented
with analog circuitry are being alternately implemented with
sample data systems.
Though more costly than their analog counterpart, these
sampled data systems feature programmability. Additionally,
many of the algorithms employed are a result of developments made in the area of signal processing and are in
some cases capable of functions unrealizable by current
analog techniques.
With increased usage a proportional demand has evolved to
understand the theoretical basis required in interfacing
these sampled data-systems to the analog world.
This article attempts to address the demand by presenting
the concepts of aliasing and the sampling theorem in a
manner, hopefully, easily understood by those making their
first attempt at signal proceSSing. Additionally discussed are
some of the unobvious hardware effects that one might encounter when applying the sampled theorem.
With this ... let us begin.
I. An Intuitive Development
The sampling theorem by C.E. Shannon in 1949 places restrictions on the frequency content of the time function signal, fIt), and can be simply stated as follows:
In order to recover the signal function f(t) exactly, it is
necessary to sample f(t) at a rate greater than twice
its highest frequency component.
Practically speaking for example, to sample an analog signal having a maximum frequency of 2Kc requires sampling
at greater than 4Kc to preserve and recover the waveform
exactly.
The consequences of sampling a signal at a rate below its
highest frequency component results In a phenomenon
known as aliasing. This concept results in a frequency mistakenly taking on the identity of an entirely different frequency when recovered. In an attempt to clarify this, envision the
Ideal sampler of Figure 1(s), with a sample period of T
shown In (b), sampling the waveform f(t) as pictured in (c).
The sampled data points of f'(t) are shown in (d) and can be
defined as the sample set of the continuous function fIt).
Note In Figure 1(9) that another frequency component, a'(t),
can be found that has the same sample set of data points
as f'(t) in (d). Because of this it Is difficult to determine which
frequency a'(t), is truly being observed. This effect is similar
to that observed in western movies when watching the
469
_.~I_)
_-",x
I'(I)SAMPLED DATA
(.)
.j t t t t 1:T4
T
t.
I
213T4T5T6T71
(b)
f
D
T
V
a2TQiT\V5TV6T'U
1\ I\f.
I
1\4T
(e)
I'(I)SAMPLED DATA
1
·1
T•
1
T
• 1 .I
(d)
.r-I'(I)SAMPLED DATA
r'
..•. , ,".
.\
".~',.\
'.. ,\U,
~:~EDJ"";
SAMPLED DATA
"
~'''-'''/''''
;'r\\j··.
• -\l.j
I' _-',VI..
.....
\,
(I)
TL/H/5820-1
FIGURE 1. When eampllng, many algnala may be found
to have the eame eat of data point•• The.. are called
alla.e. of each other.
spoked wheels of a rapidly moving stagecoach rotate ~aek
wards at a slow rate. The effect is a result of each individual
frame of film resembling a discrete strobed sampling operation flashing at a rate slightly faster than that of the rotating
wheel. Each observed sample point or frame catches the
spoked wheel slightly displaced from its previous pOSition
giving the effective appearance of a wheel rotating backwards. Again, aliasing is evidenced and in this example it
becomes difficult to determine which is the true rotational
frequency being observed.
IDEAL
ANTIALIASIN8 FILTER IlESPOIISE
ALI.O*8LE SAMPUNS FII8IUENCIES
o
Ie
2Ic
FII8IUENCY -
TLIH/5620-2
FIGURE 2. Shown In the shaded area .. an Ideal, low pass, antl-allaalng filter response.
Signal. passed through the flilar are bandllmlted to frequencle. no greater than the
cutoff frequency, fc. In accordanes with the sampling theorem, to recover the
bandllmltecl signal exactly the sampling rate must be chosen to be greater than 2fc.
On the surface it is easily said that anti-aliasing designs can
be achieved by sampling at a rate greater than twice the
maximum frequency found within the signal to be sampled.
In the real world. however. most signals contaln the entire
spectrum of frequency components; from the desired to
those present in white noise. To recover such information
accurately the system would require an unrealizably high
sample rate.
This difficulty can be easily overcome by preconditioning the
input signal. the means of which would be a band-limiting or
frequency filtering function perfonned prior to the sample
data input The prefilter. typically called anti-aliasing filter
guarantees. for example in the low pess filter case. that the
sampled data system recelves analog signals having a
spectral content no greater than those frequencies allowed
by the filter. As illustrated in FtgUf8 2. it thus becomes a
simple matter to sample at greater than twica the maximum
frequency content of a given signal.
A parallel analog of band-limiting can be made to the world
of perception when considering the spectrum of white light
It Can be realized that the study of violet light wavelengths
generated from a white light source would be vasUy simplified if initial band-limiting were performed through the use of
a prism or white light filter.
Theorem: If the Fourier transform F(CII) of a signal function
fIt) is zero for all frequencies above 1CIII ~ CIIc.
then fIt) can be uniquely determined from its
sampled values
In = ,fInn
(1)
These values are a sequence of equidistant sam-
11_ The Sampling Theorem
To solidify some of the intuitive thoughts presented In the
previous section. the sampling theorem will be presented
applying the rigor of mathematics supported by an illustrative proof. This should hopefully leave the reader with a
comfortable understanding of the sampling theorem.
fn = f( n
ple points spaced 211 = Tc = T apart. fIt) is thus
c 2
given by
00
~ f(nn sin CIIC (t - nn
fIt) =
n
~
(2)
CIIc(t-nn
=-00
Proof: USing the inverse Fourier transform'formula:
fIt) = - 1
2".
Joo
.
F(CII)E 101t dCII
(3)
-00
the band limited function. fIt). takes the form. Flf/uf8 as.
fIt) =
...!... fOlC
2".
F(CII)E jOlt dCII
(4)
-OIC
:J
is then given as .
(5)
See F/{/Uf8 3c and B.
Exprilssing F(CII) as a Fourier series in the interval - CIIc
s: CIIc we have
L
s: CII
00
F(CII)=
n ==-00
470
(6)
Where,
H(CII) = 1
and
H(CII) = 0
then as pictured in Figures 4b, d, and f,
(7)
Further manipulating eq. (7)
(6)
L
n =-00
~
n=
n...
- fnE
CIIc
-IOI;;;C
2~ J~:e
=
co
'/I'
...!... JOIe
f(t) =
CIIc
Substituting eq. (9) into eq. (6) gives the periodic Fourier
Transform
L
L
oo
-00
n=
co
L
F(CII)E
(14)
1011 dCII
~~
[H(CII)
-(IIc
2'/1'
(10)
of F/{/Ure 3f. Using Poisson's sum formula1 F(CII) can be
stated more clearly as
F(CII) =
-I"!!!
'/I'
-fnE"e
CIIc
Solving for f(t) the inverse Fourier transform eq (3) is applied
to eq (14)
as
~=~~
Fp(CII) =
(13)
co
F(CII) = H(CII). Fp(CII) = H(CII)
en can be written
(12)
~
n=
1
fn
2 -
(3)
fnE _j(ll : ; ]
CIIc
d
Q)
I(II(I-~)
(II
JOIe
jCllt
E
-00
E
dCII
-l.IJc
CIIe
-00
1Poisson's sum formula
F(CII - 2nCllc)
(11)
~
n =-00
L
n=
Interestingly for the interval - CIIc ,;; CII ,;; CIIc the periodic
function Fp(CII) and Figure 3f. equals F(CII) and Figure 3b.
respectively. Analogously if Fp(CII) were multiplied by a rectangular pulse defined,
t
~ and fs is the sampling frequency
Ie,
-Ie
(b)
.
I
·1
I I·, ..
1--2Ic--l
t
(el
(d)
...
In
,VI
I
J
• J
J
I
,
I
I
I
,
\
.......
.....
.......
.....
, ,
• 11.
-
-j(llnT
f(nT)E
n=-oo
-00
where T =
II)
.t
F(CII - nClla) =
JL
Jl •••• -ll-z1c
L
co
I
•
I
I
I
I
'- ,
I
J
J
•
\
I
"
,I
-Ie
Ie
... ....
.....
••
I
, ,.
I
I
I
I
,
\
" ,I
•
•
\
"
ro
~
TLIH/5620-3
FIGURE 3. Fourier transform of a sampled IIgnal•.
471
'n
,
-
I
....
....
,
....
"",
,,-,
,
''''I
I
o /
:,I
I
/
/
I
I
I
\
"
,I
I
/
\
,I
"-Ie.J ~Ie
.la,
11\
(1'
/
I
I
I
,
/
1
'/"'1
I
I
\
"
,I
I
\
~c
0
0
"
(b)
-
.
.,..
lin I
-"'""
. ..
.....
,,-,,
"'"
,''''
/
I
. ..
IFPI.,)
~
. /""'...
-Ie
JL.
Ie
(d)
j[
-fc
I
.,
'.
...
It· f
(I)
(I'
TLlH/5620-4
FIGURE 4. R~very of a signal f(t) from sampled data Information.·'
ledl ~ ede, are non·overlapping. On the other hand Figure 5
illustrates spectral folding, ov~rl~pping or aliasing of the
spectrum images into the original signal spectrum. This aliasing effect is, in faet, a result of unciersampling and further
causes the information of the original signal to be indistinguishable from its images (i.e. Figure tel. From Figure 6 one
can readily see that the signal is thus considerad non-recoverable.
The frequency Ifcl of Flflure 3f and 4b is exactly one half the
sampling frequency, fc=fs/2, and is defined as the Nyquist
frequency (after Harry Nyquist of. Be/I Laboratories). It is
also often called the aliasing fr,equencv or folding frequency
'for the reasons discussed alloVe. From this we can say that
in order to prevent aliasing in sanipled~data system the
sampling frequency should be chosen to be greater than
twice the highest frequency component fe of the signal being sampled.
giving
(15)
Eq (15) is equivalent to eq (2) as is illustrated in Figure 48
and Figure 3a respectively.
As observed In Flflures 3 and 4, each step of the sampling
theorem proof was al$O illustrated with its Fourier transform
pair. This was done to present alternate iIIuli!lrative proofs.
Recalling the convolution2 theorem, the convolution of
F(ed), Figure 3b, with a set 'of equidistant impulses, Fldure
3d, yields the same periodic frequency function Fp(ed), Figure at, as did the Fourier transform of fn, Figure 38, the
product of f(t), Flflure 3a, and its equidistant sample impulses, Flflure 3c.
In the same light the original time function f(t), Figure 48,
could have been recovered from its sampled waveform by
convolving fn, Flflure 48, with h(t)~ Figure
rather thl!n
multiplying Fp(ed), Figure 4b, by the rectangular function
H(ed), Figure 4d, to get F(ed), Flflure 4(, and finally inverse
transforming to achieve f(t), Figure 48, as done ·in the .matti.
ematic p r o o f . "
a
By definition
fs ~ 2fe
(16)
" Note, however, that no mention has been made to sample
at precisely the Nyquist rate sillce in actual practice it is
2 The convolution theorem allows one' to· m8thematically convolve in the
4c.
time domain by sImPly multiplying in the ~cy domain, The! Is, Hf(t) hes
Ihefourler transform F(..), and x(1) hes 11\8 f;QurIer transform X(..), lhen the
comiolution f(I)'x(1) h88 lhe Fourier \IlIhsform FtO»oX(..).
m. Some Observations and Definitions
f(t) • x(t) f(t) • x(t) -
If Figures 3f or 4b are re-examined it can be noted that the
original spectrum Fp(ed), ledl s: ede, anc;l its images Fp(ed),
~,
.'
472
F(ed). X(ed)
F(ed)' X(ed)
. f\J1Jt\M. ·.·MlRAll··
-Ie
111
-111
(I)
111
(I)
Fp(.,)
.-
..
-Ie
-111
(b)
Ie
(b)
TlIH/5820-5
TlIH/5620-6
FIGURE 5. Spectral folding or allallng cauaed by:
(a) under sampling
(b) exaggerated under sampling.
FIGURE 6. Allaaed spectral envelope (a) and (b) of
Flguraa 58 and 5b rupectlvely.
TlIH/5620-7
FIGURE 7. Generalized lingle channel sample data system.
impossible to sample at fs = 2fe unless one can guarantee
there are absolutely no signal components above fe. This
Can only be achieved by filtering the signal prior to sampling
with a filter having infinite rolloff .•• a physical impossibilitY,
see Figure 2.
To this point no mention has been made concerning the
sample and hold circuit block depicted in Rgure 7. In general the analog-to-d!gital converter can operate as a. stand
alone unit. In many high speed operations however, the
converter speed is insufficient and thus requires the assistance of a sample arid hold circuit. This will be discusSed in
detail further in the article.
.
IV. The Sampling Theorem and Ita Hardwara
Implications
Though there are numerous sophisticated techniques of implementstion, It is appropriate to re-emphasize that the intent of this article is to give the first time user a basic and
fundamental approach toward the deSign of it sampled-data
system. The method with which to achieve this goal will be
to .introduce a few of the common perils encountered when
implementing such a system. We begin by considering the
generalized block diagram of Figure 7.
As shown in FtgUf8 7, prior to any Signal processing manipulation the analog input signal must be preconditioned to prevent aliasing and thereafter digitized to logic Signals usable
by the logic function block. The antialiasing and digitizing
functions are perlormed by an input filter and analog-to-digital converter respectively. Once digitized the signal can then
be altered or processed and upon completion, reconstructed beck to a continuous anfilog signal via a digital-to-analog
converter followed by a smoothing filter.
A. The Antlallaslng Input Filter
As indicated earlier in the text, the antialiasing filter should
band-limit the input signal's spectrum to frequencies no
greater than the Nyquist frequency. In the real world however, filters are non-ideal and have typical attenuation or bandlimiting and phase characteristics as shown in Figure 8. 3 It
must also be realized that true band-limiting of a specific
frequency spectrum is not possible. In the sample data system band-limiting is achieved by attenuating those frequencies greater than the Nyquist frequency to a level undetectable or invisible to the system analog-to-digital (AID) converter. This level would typically be less than the rms quantization" noise level defined by the specific converter being
used.
31n order net to disrupt the flow 01 the discussion a list 01 filter terms has
been presented In Appendix A.
4For an explanation 01 quantization mer to section IV. 8. of this article.
473
frequency. Similar to the flat pass-band consideration, if the
phase shift of the filter is not exactly proportional to the
frequency, the output of the, filter will be a )Vaveform In
which the summation of all frequencY cOmponents has been
altered by shifts in their relative phase. Figure Db further
indicates that contrary to the roll 'off rate, the higher the filter
order the more non-ideal the delay becomes (Increased delay) and the result Is a diStorted output signal. '
A final and complex consideration to understand is the effects of sampling. When a signal Is sampled the end effect
is the multiplication of the signal by a unit sampling pulse
train as recalled from Figure
C and 6. The resultant
waveform has a spectrum that is the convolution of the signal spectrum and the spectrum of the unit sample pulse
train, i.e. Figure 3b, d, and f. If the unit sample pulse has the
classical sin XIX spectrum5 of a rectangular pulse, see Flgure 13, then the convolution of the pulse spectrum with the
signal spectrum would produce the non~ideal sampled signal spectrum shown in Figure tOB, b, and c.
It should be realized that because of the band-limiting or
filtering and delay respqnse of the Sin XIX function combined with the effects of the non~ideal antialiasing filter (i.e.
non-flat pass-band and phase shift) certain of the sum and
difference frequency components may fall within the desired signal spectrum thereby creating aliasing errors, FI{Iure 10e.
When designing antial!asing filters it will be found that the
closer the filter response approaches tI1e ideal the more
complex the filter becomes. Along with thls an Increase in
delay aocl pass-band ripple combine to distort and alias the
input Signal. In the final analysis the design will involve trade
ofts made between filter complexity, sampling speed and
thus system bandwidth.
'
As an example of how an antialiasing filter would be applied,
assume a sample data system having within it an Sobit AID
converter. Eight bitS, translates to 2n:=28=256 levels of
resolution. If 2.56 volt reference were used each quantization level, q, would represent the equivalent of 2.56 voltsl
256:= 10 millivolts. Realizing this the antiallasing filter would
be designed suCh that frequencies in the stopband were
attenuated to less than the rms quantization noise level of
q/2.J3 and thus appearing invisible to the system. More specifically
V full scale
-2010g10
"" -59 dB = AMIN
a
sa,
Vq/2~
It can be seen, for example in the Butterworth filter case
(characterized as having a maximally flat pass-band) of Figure 9s that any order of filter may be used to achieve the
-59 dB attenuation level, howeve", the higher the order,
the faster the roll off rate and the closer the filter magnitude
response will approach the ideal.
Referring back to FltJure Sit is observed that those frequencies greater than OIa are not recognized by the AID converter and thus the sampling frequency of the sample data system would be defined as CIIs ~ 2C11a. Additionally, the frequencies present within the filtered input signal would be
those less than CIIa. Note however, that the portion of the
signal frequencies least distorted are those between CII = 0
and ClIp and thOSE! within. the transition band are distort~ to
a substantial degrea, though it was originally desired to limit
the signal to frequencies less than the cutoff ClIp, because of
the non-ideal frequency response the true Nyquist frequency occurred at OIa. We see then that the sampled-data system could at most be accurate for those frequencies within
the antialiasing filter passband.'
,'
'
From the above example, the design of an antialiasing filter
appears to be quite straight forward. Recall however, that all
waveforms ere composed of the sums and differences of
various frequency components and as a result, if the response of the filter passband were not flat for the desired
signal frequency spectrum; the recovered signal would be
an inaccurate summation of all frequency components altered by their relative attenuations in the pasS-band.
Additionally the antialiasing filter design should not neglect
the effects of delay. As illustrated in FigureS and 9b, delay
time corresponds to a specific phase shift at a particular
PASSBAND
, B. The Analog-to-Dlgllal Convertar
, Following'the antiall.sing filter is the AID converter which
performs the operations of quantizing and coding the input
Signal in some finite amount of time. Figure 11 shows the
quantization process of converting a continuous analog input signal into a set of discrete output levels. A quantizatIOn,
q, 'is thus defined as the smallest 'step used in the dlgiiaJ
5ThIs will be explained more clearly in Section IV. Of this article.
STOPBAND
:M:t~'________________~~
i!
III
I
OIl
"p
FREQUENCY..
FREQUENCY"
TLIH/5620-8
FIGURE 8. TypiCal filter magnitude and phase versus frequency response.
474
0.1
0.2
0.3
0.4
0.5 0.6 0.7 0.8 0.9 1
5
6
7 8
TLIH/5620-9
a) Attenuation characterlatlca of a normalized Butterworth filter aa a function of degree n.
3
/""I
2
I ~
1
/r
~\
VI \'
10
i
l..---
!
I
~
--
-
II!
~
1\\ \
1\' ~\
I,......- Va , / /
. / -...... \ .'\\~
~ --7 / '
'\ .~ ~
/
Y
/ " ,/"
~ /"
.'\ ~ ~
.....
~ V .................
0 ~ ~ t--...
....... ....
-l
.......... ~
~~~
2
1=10
!!
V
V '1/
- --
./
~ /
~
"
- ---- "' -- s:::
&
-
1
0.1
0.2
0.3
0.4
0.5
0.&
~
i--
0.7
0.8
0.9
1.0
1.1
I""---
1.2
1.3
~ t:::' I'oo.=""
i""--
1.4
1.5
~
1.8
1.7
~
t:5=:
1.8
1.1
TLIH/5620-10
b) Group delay performances of normalized Butterworth lowpass filters aa a function of degree n.
FIGURE 9
475
L I~
III
I
Ibl
.........•
........•.
.'
•••••••••••••••_•••_••_.
_.;...-_ _ _-'_II1I:I_ _......;__•••_••••••••••••••••••
lei
TL/H/5820-11
FIGURE 10. (c) equall the convolution of (I) with (b).
representation of fq(n) where fen) Is the sample set of an
input signal f(t) and Is expressed by a finite number of bits
giving the sequence fq(n). Digitally speaking q is the value of
the least significant code bit. The difference signal E(n)
shown In FIgure 111s called quantization noise or error and
can be defined as E(n) = fen) - fq(n). This error Is an Irreducible one and is a function of the quantizing process. Its
error amplitude Is dependent on the number of quantization
levels or quantizer resolution and as shown, the maximum
quantization error is Iq/21.
Generally E(n) Is treated as a random error when described
in terms of its probability density function, that is, all values
of E(n) between q/2 and -q/2 are equally probable, then
for the averaie value E(n)avg =0 and for the rrns value
E(n)rma == q/2~.
As a side note It Is appropriate at this point to emphasize
that all analog signals have some form of noise corruption.
If for example an Input signal has a finite signal-to-noise
ratio of 40dB It would be superfluous to select an AID converter with a high number of bits. It may be 'realized that the
use of a large number of bits does not give the digitized
signal a higher signal-to-nolse ratio than that of the original
analog input Signal. As a supportive argument one may say
that though the quantization steps q are very small with re~
spect to the peak input signal the lower order bits of the
AID converter merely provide a more accurate representation of the noise inherent in the analog input signal.
Returning to our discussion, we define the converaion time
as the time taken by the AID converter to convert the analog input Signal to Its equivalent quantization or digital code.
The conversion speed required In any particular application
depends upon the time variation of the signal to be converted and the amount of resolution or bits, n, required. Though
the antlallaslng filter helps to control the Input Signal time
rate of change by band-limiting Its frequency spectrum, a
finite amount of time is stili required to make a measurement or conversion. This time Is generally called the aperture time and as Illustrated In FIgure 12 produces amplitude
measurement uncertainty errors. The maximum rate of
change detectable by an AID converter can simply be statedas
V full scale
-dvl
dt maximum resolvable
rate of change
2nTconversion time
~n
,
If for example V full scale = 10.24 volts, T conversion time
= 10 ms, and n = 10 or 1024 bits of resolution then the
maximum rate of change resolvable by the AID converter
would be 1 volt! sec. If the Input signal has a faster rate of
chenge than 1 volt!sec, 1 LSB changes cannot be resolved
within the sampling period.
In many Instances a sample-and-hold circuit may be used to
reduce the amplitude uncertainty error by measuring the input signal with a smaller aperture time than the conversion
time aperture of the AID converter. In this case the
416
DIGITAL
OUTPUT
15~ ~
I I I I
o '"
0
01 0 1
o 1 00
VFULL SCALE
&ci
'ii'
'6
5q
4q
00 1 1
3q
001 0
2q
0001
o0 0 0
lq
0
~_..L-""""_I..-.....L.......JL...--'-
_ _ _ __
q/2 3q/25q/27q/2 9q/2 • . .
INPUT SIBNAl ~.)=~QI
I(n)
l=nT
TLlH/5820-12
FIGURE 11. Quantization error.
.t
t
;
!:i
=
TLlH/5820-13
I>.v: AMPLITUDE UNCERTAINTY ERROR
Ia: APERTURE TIME
I>.1a: APERTURE TIME UNCERTAINTY
FIGURE 12. Amplitude uncertainty a8 a function of
(a) a nonvarylng aperture and
(b) aperture time uncertainty.
maximum rate of change resolvable by the sample-and-hold
would be
V full scale
(18)
taperture
dt
maximum resolvable
It is appropriate to recall the earlier discussion that the
spectrum of a sampled signal Is one In which the resultant
spectrum is the product obtain by convolving the input signal spectrum with the sin X/X spectrum of the sampling
waveform. Figure 13 Illustrates the frequency spectrum plotted from the Fourier transform
. edT
~I
rate of change
Note also that the actual calculated rate of change may be
limited by the slew rate speCification fo the sample-and-hold
in the track mode. Additionally it is very important to clarify
that this does not imply violating the sampling theorem in
lieu of the increased ability to more accurately sample signals having a fast time rate of change.
An ideal sample-and-hold effectively takes a sample in zero
time and with perfect accuracy holds the value of the sample indefinitely. This type of sampler is also known as a zero
order hold circuit and its effect on a sample data system
warrants some discussion.
sin
2"
F(ed) = AT-;;;r
(19)
2
of a rectangular pulse. The sin X/X form occurs frequently in
modern communication theory and is commonly called the
sampling function.
The magnitude and phase of a typical zero order hold sampler spectrum
sined'T .1
]
H(ed) = A [ ' T - - + I-(cosed-l)
(20)
ed'T
ed
477
limits the amount of il'lformation resolvable by the sample
data system. On the, Ot~er hand a narrow sampler pulse, width or aperture window has a broader main lobe or bandwidth and thus when convolved with the analog input signal
produces the least amount of distortion. Understandably
then the effect ,of the sampler's spectral phase and main
lobe width must be considered when developing a sampling
system so that no unexpected aliasing occurs from its convolution with the input signal spectrum.
1(1)
A
-T/2
T/2
II)
(I)
(b)
TUH/5620-14
FIGURE 13. The Fourier transform of the rectsngular
pulse (a) Is shown In (b).
is shown in Figure 14 and F/{/ure 15 illustrates the spectra of
various sampler pulse-widths. The purpose of presenting
this illustrative information is to give insight at to what effects cause the aliasing described inFigure 10. From Figure
15 it is realized that the main lobe of the sin XIX function
varies inversely proportional with the sampler pulse-width.
In other words a wide pulse-width, or i,n this case the aperture window. acts as a low pass filtering function and
TUH/5620-16
FIGURE 15_ Pulse width and how It effects the sin XIX
envelop spectrum (normalized amplltudes)_
c. The Dlgltal-to-Analog Converter and
(I)
Smoothing Filter
~,""""
.
. .'
,
,
, Attar a signal has been digitally conditioned by the signal
processing unit of Figure 7, a O/A converter Is used to convert the sampled binary information back in to an, analog
signal. The conversion is called a zero order hold type
where each output sample level is a function of its binary
weight value and is held until the next sample arrives, see
Figure 16. As a result of the 01A converter step function
response it is apparent that a large amOunt of unde~irable
high frequency energy Is present. To eliminate this the O/A
converter IS usually follow!KI by a srnoothing filter,l'Iaving a
cutoff frequency no greater than half t~!I sampling frequency. As its nanie suggestS the ,fil~r output produces a
smoothed version of the 01 A converter output which in fact
is a CohVolved function. More simply said, the spectrum of
the resulting signal is the product of a step function sin XIX
spectrum and the 'band-limitad analog filter spectrum. Analogousto the input sampling problem, the smoothed output
may have aliasing effects resulting from the phase and attenuatiol'l relations of the signal recovery system (defined as
the 01 A converter and smoothing tilter combination).
\.
'
<:
Ib)
i'~'
1-' , '
,',',
(e)
TUH/5620~15
FIGURE 14. Sampling Pulse (a), Its Magnitude (b) and
Phase Response (e).
478
As a final note, the attenuation due to the 0/ A converter sin
X/X spectrum shape may in some cases be compensated
for in the signal processing unit by pre-processing using a
digital filter with an inverse response X/sin X prior to 0/A
conversion. This allows an overall flat magnitude signal response to be smoothed by the final filter.
There are basically five types of filters used to pass or reject
such signals and they are defined as follows:
1. A low-pass filter passes a band of frequencies called the
passband, ranging from zero frequency or DC to a certain
cutoff frequency, "'c', and in addition has a maximum
attenuation or ripple level of AMAX within the passband.
See Figure 1.
'Recall thai the radian frequency .,=2,,1.
(II
(bl
TL/H/5620-18
FIGURE 1. Common Low Pass Filter Response
Frequencies beyond the "'c may have an attenuation
greater than AMAX but beyond a specific frequency
defined as the stopband frequency, a minimum attenuation of AMIN must prevail. The band of frequencies higher
than "'8 and maintaining attenuation greater than or equal
to AMIN is called the stopband. The transition region or
transition band is that band of frequencies between "'c
and "'s.
2. A high-pass filter allows frequencies above the passband
frequency, "'c, to pass and rejects frequencies below this
point. AMAX must be maintained in the passband and frequencies equal to and below the stopband frequency, "'s,
must have a minimum attenuation of AMIN. See Rgure 2.
"'8
TL/H/5620-17
FIGURE 16. (a) Proceaaed signal data polnta
(b) output of D/A converter
(c) output of smoothing filter.
V. A FInal Note
This article began by presenting an intuitive development of
the sampling theorem supported by a mathematical and illustrative proof. Following the theoretical development were
a few of the unobvious and troublesome results that develop when trying to put the sampling theorem into practice.
The purpose of presenting these thought provoking perilS
was to perhaps give the beginning designer some inSight or
guidelines for consideration when developing a sample data
system's interface.
-
VI. Acknowledgementa
The author wishes to thank James Moyer and Barry Siegel
for their encouragement and the time they allocated for the
writing of this article.
·L1111
I
APPENDIX A
Basic Filter Concepts
A filter is a network used for separating Signal waves on the
basis of their frequency and is usually composed of passive,
reactive and active elements such as resistors, capacitors,
inductors, and amplifiers, or combinations thereof.
TL/H/5620-19
FIGURE 2. Common High Pass Filter Response
479
3. A bandpass fHter performs the function oi passing a specific band of frequencies while rejecting those freqUencies above and below Cilc2 and lower. Cilc1,cutoff frequ/ilncy limits. See 'Figure 3.,
-
4. A bil.'rid.:rejectfllt~ or notch filter' allows all, but a specific
band of frequencies to pass.' As shown in Figure 4. ,those
frequencies between Cilsi' arid' wsi,are filtered· ' out and
those frequencies above and below Cilc2and Cilc1 respec- ,
tlvely .ate' 'passed. The attenuation requirements of the
stopband AMIN and passbar:ld AMAX mUst stili hold.'
5. An all-pass or phase shift filter allows all frequ~ncies to
pass without any appreciable attenuation. It further introduces a predictable phase shift to all frequencies passed.
though not restri~ing the entire range of frequencies to a
specific phase shift (\.e;. a phase shift may be imposed
upon a selected band of frequenci~s BlJd'appear invisible
' ,
to all others).
APPENDIXB
UIII
ARTICLE REFERENCES
!
TLlH/562D-20
Figure 3. Common Band-pass Filter Response
As in the previous two cases the passband is required to
sustain an attenuation of AMAX. and the stopband of frequencies above and below Cils2 and Cils2 respectively.
must have a minimum attenuation of AMIN.
S.D. Stearns. Digitsl Signal Analysis. Hayden. 1975.
S.A. Tretter. Introduction to Discrete- TiITlB Signal Processing. Wiley. 1976.
W.O. Stanley. Digital signsl Processing. Reston, 1975.
A. Papoulis. The Fourier Int8[Jral and its Applications. McGraw-Hill.1962.
E.A. Robinson. M. T. Silvia. Digitsl Signal Processing and
TiITlB Series Analysis. Holden-Day. 1978.
C.E Shannon. "Communication in the Presence of Noise."
Proceedings IRE, Vol. 37. pp. 10-21. Jan. 1949.
M. Schwartz. L. Shaw. Signal Processing: Discrete Spectral
Analysis, Detection and EstilTlBtion, McGraw-Hili, 1975.
L.R. Rabiner, B. Gold, Theory and Apj:)/ication of DiU/tsl Signal Processing. Prentice-Hail. 1975.
W.H. Hayt. J.E Kemmerly. Enginsering Circuit Analysis.
McGraw-Hili. 3rd edition. 1978.
EO. Brigham. The Fast Fourier Transform. Prentice-Hail.
1974.
J. Sherwin. Spedifying AID
D/A eonV6(t6fS. National
Semiconductor Corp .• Application Note AN-156.
Analog-Digital Conversion Notes. Analog Devices Inc.•
1974.
A.I. Zverev; Handbook ofFilter Synthesis. Wiley. 1967.
,and
TLlH/562D-21
Figure 4. Commo" Band-Reject Filter Responss
480';
r----------------------------------------------------------------,~
National Semiconductor
Application Note 237
CONVOLUTION: Digital
Signal Processing
~~
Introduction
As digital signal processing continues to emerge as a major
discipline in the field of electrical engineering, an even
greater demand has evolved to understand the basic theoretical concepts involved in the development of varied and
diverse signal processing systems. The most fundamental
concepts employed are (not necessarily listed in the order
of importance) the sampling theorem[l), Fourier transforms
(2) (3), convolution, covariance, etc.
Decreasing the pulse width while increasing the pulse
height to allow the area under the pulse to remain constant,
Figuf9 1e, shows from eq(l) and eq(2) the bandwidth or
spectral-frequency content of the pulse to have increased,
Figure 1d.
Further altering the pulse to that of Figuf9 1e provides for an
even broader bandwidth, Figuf9 1f. If the pulse is finally altered to the limit, i.e., the pulsewidth being infinitely narrow
and its amplitude adjusted to still maintain an area of unity
under the pulse, it is found in 1g and 1h the unit impulse
produces a constant, or "flat" spectrum equal to 1 at all
frequencies. Note that if AT = 1 (unit area), we get, by definition, the unit impulse function in time.
The intent of this article will be to address the concept of
convolution and to present it in an introductory manner
hopefully easily understood by those entering the field of
digital signal processing.
It may be appropriate to note that this article is Part II (Part I
is titled "An Introduction to the sampling Theorem") of a
series of articles to be written that deal with the fundamental
concepts of digital signal processing.
Since this time function contains equal frequency components at all frequencies, applying it or a good approximation
of it to the input of a linear network would be the equivalent
of simultaneously impressing upon the system an array of
oscillators inclusive of all possible frequencies, all of equal
amplitude and phase. The frequencies could thus be determined from this one input time function. Again, variations in
amplitude and phase at the system output would be due to
the system itself.
Let us proceed ....
Part II Convolution
Perhaps the easiest way to understand the concept of convolution would be an approach that initially clarifies a subject relating to the frequency spectrum of linear networks.
Determining the frequency spectrum or frequency transfer
function of a linear network provides one with the knowledge of how a network will respond to or alter an input
signal. Conventional methods used to determine this entail
the use of spectrum analyzers which use either sweep generators or variable-frequency oscillators to impress upon a
network all possible frequencies of equal amplitude and
equal phase.
The response of a network to all frequencies can thus be
determined. Any amplitude and phase variations at tlie output of a network are due to the network itself and as a result
define the frequency transfer function.
Another means of obtaining this same information would be
to apply an impulse function to the input of a network and
then analyze the network impulse-response for its spectualfrequency content. Comparison of the network-frequency
transfer function obtained by the two techniques would yield
the same information.
Empirically speaking the frequency spectrum or the network
frequency transfer function can thus be determined by applying an impulse at the input and using, for example, a
spectrum analyzer at the network output. At this pOint, it is
important to emphasize that the above discussion holds
true for only linear networks or systems since the superposition principle (The response to a sum of excitations is equal
to the sum of the responses to the excitations acting separately), and its analytical techniques break down in non-lin, ear networks.
Since an impulse response provides information of a net,work frequency spectrum or transfer function, it additionally
provides a means of determining the network response to
any other time function input. This will become evident in
the following development.
The output of the network G(t
(6b)
Footnote:
1. It is important to note that the convolution integral is commutative. This implies the reversability of the fIt) and hIt)
terms in the definition.
g(t) =
(4)
482
f:
f:
00
fIT) hIt - T) dT = F-1 [F(Ol). H(lII))
00
fIt - T) hIT) dT = F-1 [H(CIl) • F(lII»)
.--------------------------------------------------------------------,
F("'....f
H "b(.,' r-.8(,,'
"II."
put excitation function, multiplying the two transforms and
finally computing the inverse FFT of the product.
Moving averages and smoothing operations can further be
characterized as lowpass filtering functions and can additionally be implemented using convolution. The above are
just a few of the many operations convolution performs and
the remainder of this discussion will focus on how convolution is realized.
To start with, an illustrative analysis will be performed assuming continuous functions followed by one performed in
discrete form similar to that realized in computer aided sampled-data systems techniques.
As an example, if it were desired to determine the response
of a network to the excitation pulse fIt) shown in Figure 3a,
knowing the network impulse ha(t), Figure 3b, the impulse
response of an RC network, would allow one to determine
the output g(t) using the convolution integral, eq(3).
TL/H/5621-2
H(..)~Ha(")· Hb("')
G(...) ~ H( )
F(...)
..
FIGURE 2. Block diagram of a network transfer function
the following identity can be made
Jof(T) hIt - T) dT =
f~ fIT) hIt -
T) u(t - T) dT
(7)
Rewriting eq(5) as
FU(t) • hIt)] =
f~ cj..t f~ fIT) hIt -
T) (l(t - T) dTdt (8)
The convolution of fIt) and halt)
and letting x = t - T so that
f(t) = 10[u(t)-(u(t-Toll
ha(t)=c 8t
(9)
eq(8) finally becomes
F[f(t)' hIt)] =
=
could be obtained by first substituting the dummy variable
t - T for t in halt) so that
f~ f~ fIT) h(x) u(x) cj..tcj..xdTdx
f~ h(x) u(x) °E-j..
F[f(t)Oh(t)] =H(CIJ). F(CIJ)
X
dx
(13)
ha(t-T)=c8(t-,.)
f~ fIT) cj..,. dT
(15)
By definition g(t) = fIt)
(10)
0
halt) thus becomes
f:f(T)ha(t-T)dT= Jo10[u(t)-u(t-Tol]c 8(t-,.) dT
(16)
which is the equivalent of eq(4).
In essence the above proof describes one of the most important and powerful tools. used in signal processing .•..
the convolution theorm. In words,
111--------,
Convolution Theorem:
The convolution theorem allows one to matheml!-tically convolve in the time domain by simply multiplying in the frequency domain. That is, if fIt) has
the Fourier transform F(CIJ) and x(t) has the Fourier
transform X(CIJ), then the convolution fIt) • x(t) has
the Fourier transform F(CIJ) • X(CIJ).
.
For the time convolution
F(CIJ). X(CIJ)
fIt) 0 x(t) _
(11)
T.
TL/H/5821-3
l(t)~10[u(t)-u(t
-Toll
(a)
and the dual frequency convolution is
f(t). x(t) F(CIJ)' X(CIJ)
(12)
Convolutions are fundamental to time series sampled data
analysis. First of all, as described earlier all linear networks
can be completely characterized by their impulse response
functions and furthermore the response to any input is given
by its (the input function) convolution with the network impulse response function. Digit filters being linear systems
accomplish the filtering task using convolutions. A network
or filter transfer function for example can be represented by
its inpulse response in the form of a Fourier series. A filtered
input excitation response can then be found by convolving
the input time function with the network Fourier series or
impulse response. With the aid of a high speed computer
the same result could be obtained by storing the FFT (Fast
Fourier Transform) of the network impulse response into
memory, performing an FFT on the sampled continuous in-
TL/H/5821-4
h8(t)~.-at
(b)
FIGURE 3. (a) rectangular pulse excitation
(b) Impulse response of a single RC network
483
~
z
~
!:S
~ r-----------------------------------------------------------------~
CO)
~
a(l)
c
18(1-.-11)
I
I
10.-1I(.'T, -1)
I
'V ~
T.
TLlH/5621-5
(e)
FIGURE 3. (c) output or convolution of the network (b) excited by (a)
Since the piecewise nature of the excitation makes it convenient to calculate the response in corresponding pieces the
output is found to be
O 0 however as. the present time t varies, the
impulse response ha(t-T) scans the excitation function f(T),
always producing a weighted sum of past inputs and weighing most heavily those values off(T) closet to the present.
As seen In Figures 46 through 4", the reSponse or output of
the network at anytime t is the integral of the functions or
calculated shaded area under the curves. In terms of the
superposition prinCiple the filter response g(t) may be interpreted as being the weighted superposition of past input f( T)
values weighted or multiplied by hs(t-T).
An extension of the continuous convolution to its numerical
discrete form is made and shown in Figure 5. Again the
excitation and impulse response of Figure 3 are used and
are further represented as two finite duration sequences f(n)
T) dT
(18)
The output response g(t) is plotted In Figure 3c and is clearly what might be expected from a simple RC network excited by a rectangular pulse.
Though Simplistic in its nature, the analysis of the above
example quickly becomes unrealistically cumbersome when
complex excitation and impulse response functions are
used. Turning to a numerical evaluation of the convolution
integral may perhaps be the most desirable method of realization. Prior to a numerical development however, an intuitive graphical illustration of convolution will be presented
which should make discrete numeric convolution easily understood.
The convolution integral -
fa
f(T) hs(t - T) dT
IMPULSE RESPONSE
EXCITATION
~~.
o
.
T O T
(I)
(b)
TL/H/5621-6
FIGURE 4. a) ha(T): network Impulse response
b) f(T): excitation function
484
----1t:
JIII!.-
o
T
(d)
(e)
THE PRODUCT: f(tlh6ll- TI
THE AREA = I(TIOh""l = 0(11
0(1) =~(T)h.,(I-TldT
o
-Ix 0
('1
(II
~THE
PRESENT INSTANT, NOW.
-~
I--FUTURE
011
PAST-I
(al
o
(hI
L
o
Ib
(II
o
I
III
Ie
T
(k)
(I)
tL
o
Id
I
(nl
(ml
TL/H/56.21-7
FIGURE 4. cont'd c) ha( - 1'): halT) folded about the ordinate
d) halt - 1'): ha(r) folded and shifted
e) through n) the output response g(t) of the network whose
Impulse response halT) Is excited by a funcUon f(T).
Or the convolution, f(T)"ha(t), of f(t) with halt).
485
"""~
CO)
EXCITATION
IMPULSE RESPONSE
i
~
.Nb=,'
0
L
Na=7
.
n
D
D
(II
(bl
.
..,
~-.;--
• =4
THE AIIEA:g(nIT =T.!.flll/Id(l-:-11
m
II
0
4
0
n
n
(el
(dl
LL
n
D
0
n
8
~
ffl
!,
13
(ul
(II)
TLlH/5621-8
FIGURE 5. illustrative description of discrete convolution
and ha(n) respectively, Figures 58 and b.
It is observed additionally that the duration 01 fen) is Na = 7
samples [fen) is nonzero for the interval 0 s: n .s: Na -1 and
the duration of hs(n) is Nb = 8 samples [hs(n) is nonzero for
the interval 0 s: n s: Nb -1]. The 13equence g(n), a discrete
convolution, can thus be defined as
If fen) and hs(n) were nl1Jd considered to be periodic se·
quences and a convolutl,on was desired using either shifting
techniques or .performing an FFT on the excitation and impulse response sequences and finally inverse FFT trans·
forming to achieve the qulput response, some care must be
tsken when preparing the convolving sequences. From Fig·
ure 5h it is observed ttlat the convolution is completed in a
Na + Nb -1 point sequence. To acquire the nonoverlapping
or nondistorted periodic sequence of Figure 6c the convolution thus requires fen) and ha(n) to be Na+Nb-1 point se·
quences. This is. achieved by appending ttle appropriate
number of zero valued samples, also known as zero filling,
to fen) and ha(n) to make them both Na + Nb -1 pOint se·
quences. The undistorted and correct convolution can now
be performed using tI1e zero filled sequences F/(Jure 6a and
6b to achieve6c.
n
g(n) =
L
f(x) ha(n - x)
(21)
x=o
having a finite duration sequence of Na + Nb -1 samples,
Figure 5h. The convolution using numeriCal integration (area
under the curve) can be defined as
n
g(n)T = T
L
f(x) ha(n - x)
(22)
x=o
where T is the sampling interval used to obtain the sampled
dats sequences.
486
.--------------------------------------------------------------------.~
:;p:
N
L. .
L.
Co)
.....
belln)
PERIODIC
Itn)
PERIODIC
(b)
1111111 "
IlIIm '"
1111111
b
110-1
(e)
NI+Nb-1
TUH/5821-9
FIGURE 6. Linear periodic discrete convolution of I(n) and ha(n), I(n)*ha(n).
A Final Note
This article attempted to simplify the not-so-obvious concept of convolution by first developing the readers knowledge and feel for the implications of the impulse function
and its effect upon linear networks. This was followed by a
short discussion of network transfer functions and their relative spectrum. Having set the stage, the convolution integral
and therorem were introduced and supported with an analytical and illustrative example. This example showed how
the response of a simple RC network excited by a rectangular pulse could be determined using the convolution integral.
Finally, two examples of discrete convolution were presented. The first example dealt with finite duration sequences
and the second dealt with periodic sequences. Additionally,
precautions in the selection on n-point sequences was discussed in the second example to alleviate distorting or
spectually overlapping the excitation and impulse response
functions during the convolution process.
487
~ r-~--~~~--------~------------------------------------------------------~
Appendix A
Z
1. Carson Chen, An Introduction to the sa",pling Theorem,
12. S. A. Tretter, Introduction to Discrete-nme Signsl Pr0National Semiconductor Corporation.
cessing, John-Wiley, 1976.
2. A. Papoulis, The Fourier Integral and Its Applications,
13. A: Papoulis, Signsl Anslysis, McGraw-Hili, 1977.
McGraw-Hili, 1962.
14. M. Schwartz, L Shaw, Signal Processing: Discrete,
'. Spectral AnsIysis. Detection, and Estimation, McGraw3. E. O. Brigham, The Fast Fourier Transform, Prentice-Hall,
1979.
Hill,1975.
4. L. Enochson, R. K. Otnes, Applif!d TIfTIS Series Anslysis, . 15. W. D. Stanley, Digitsl Signs! Processing, 1975.
John Wiley, 1978.
. .
16. D. F. Tuttle, Jr., Circuits, McGraw-Hili, 1977.
5. B. Gold, C. M. Rader, Digitsl Processing of Signsls,
n,.F!; C. Agawal,
S. Burrus, Number Theoretical TransMcGraw-HiII,1969.
forms to !mplemenl Fast Digital Convolution, Proc.
6. F. F. Kuo, Network Ans/ysis and Synthesis, JohnWiley,
IEEE, Vol. 63, pp. 550-560, April 1975.
1968.
18. J.W. Cooley, P; A. W. Lewis, P. D. Welch, Application of
7. R. W. Hamming, Qigitsl Rhers, Prentice-Hall, 1977.
the Fast Fourier Transform to Computstlon of Fourier
Integrsls, Fourier Series, and Convolution Integrals,
8. B. Gold, L. R. Rabiner, Theory and Application of Digits!
IEEE Trans, Audio EI&ctroaccoustics, Vo. AU-15, pp.
Signal Processing, Prentice-Hall, 1975.
79-84, June 1967.
9. M. Schwartz, Information Transmission. Moduliltlon, and
Noise, McGraw-Hili, 1970.
Acknowledgements
10. S. D. Stearns, Digitsl Signsl Analysis, Haysen, 1975.
.Jhe author wishes to thank James Moyer and Barry Siegel
for their guidance and constructive criticisms.
11. E. Kreyszig, Advanced Engifl99ling MatJiemstics, .JohnWiley, 1979.
~
cc
e.
488
:r>
Wide-Rang~. Current-to-
Does an analog-to-digital converter cost you a lot if you
need Il)any bits of accuracy and dynamic range? Absolute
accuracy better than 0.1 % is likely to be expensive. But a
capability ~or wide dynamic range can be quite inexpensive.
Voltage-to-frequency (V-to-F) converters are becoming popular as a low-cost form of A-to-D conversion because they
!lan handle a wide dynamic range of signals with good accu. racy.
f "" VIN x..!..
RINQ
When VIN covers a wide dynamic range, the Ves and Ib of
the op amp must be conSidered, as they greatly affect the
usable accuracy' when the input signal is very small. For
example, when the full-scale input is 1UV, a signal which is
100 dB below full-scale will be only 100 ",V. If the op amp
has an offset drift of ± 100 '" V, (whether caused by time or
temperature), that would cause a ± 100% error at this signal level. However, a current-to-frequency converter can
easily cover a 120 dB range because the voltage offset
problem is not significant when the input signal is actually a
current source. Let's study the architecture and design of a
current-to-frequency converter, to see where we can take
advantage of this.
(Figure 1). This current is integrated by an op amp, and a
charge dispenser acts as the feedback path, to balance out
the average input current. When an amount of charge
Q=leT (or Q=CeV) per cycle is dispensed by the circuit,
then the frequency will be:
b.
~
When VIN is large:
Most voltage-to-frequency (V-to-F) converters actually operate with an input current which is proportional to the voltage
input:
+ I .)
I.
N
Application Note 240
Robert A. Pease .
Frequency Converters
f = (VIN - Ves
RIN
z
National Semiconductor
x ..!.
Q'
Uk
"'~M_"'----
'OUT
RI
-YIN
RIN ~
Fi~---~~--~~----~~------.
SCALE
TUH/5622-1
FIGURE 1. Typical Voltage-to-Frequency Converter
489
"When the Input signal is a current, the use of a low-voltage:: driff op amp becomes of no advantage, and low bias current
" is the'prlme specification. A low-cost BI-FETTM op amp such
as the LF351 A has Ib <100 pA, and temperature coefficient
of Iii less than 10 pA/·C, at room temperature. In a typical
circuit such as FII/ure 2, the leakage of the charge dispenser
is important, too. The LM331 is only specified at 10 nA max
at room temperature, because that is the smallest current
which can be measured economically on high-speed test
equipment. The leakage of the LM331's current-source output at pin 1 is usually 2 pA to 4 pA, and is always less than
the 100 pA mentioned above, at 25°C.
The feedback capaCitor ~ should be of a low-leakage type,
such as polypropylene or polystyrene: (At any temperature
above 35°C, mylar's leakage may be excessive.) Also, lowleakage diodes are recommended to protect the circuit's
input from any possible fault conditions at ~e input. (A
1N914 may leak 106 pA even With only 1 millivoH across it,
and is unsuitable.)
,
After trimmi~g this ~ircuit for'a low offset when liN is 1 nA,
the circuit will operate with an input range of 120 dB, from
200 p.A to 100 pA, and an accuracy or linearity error well
below (0:02% of the signal plus 0.0001 % of full-scale).
The zero-offset drift will be below 5 or 10 pA/oC, so when
, , the inP4t is 100 dB down frolT! full-scale, the zero drift will be
less than 2% of signal, for a ±SoC temperature range. Another way of Indicating this performance Is to realize that
when the input is 1/1000 of full-scale, zero drift will be less
than 1% of that small signal, for a O"C to 700c temperature
range.
CURRENT
OFFSET
ADJUST
1M
y+
v+
yUk
~
___.....
FREQUENCY
~::::T
FULL-SCALE
"N
zoallA
-
FULL·
SCALE
IDa TO 10k
D3
y-
--
IN4002
01, 02= 1N457, 1N484, or similar !ow-leakage planar diode
FIGURE 2. Practical Wide-Range Current·to-Frequency Converter
490
TLlH/5622-2
What if this isn't good enough? You could get a better op
amp. For example, an LHOO22C has 10 pA max lb. But it is
silly to pay for such a good op amp, with low V offset errors,
when only a low input current specification is needed. The
circuit of Figuf'8 sa shows the simple scheme of using FET
followers ahead of a conventional op amp. An LF351 type is
suitable because it is a cheap, quick amplifier,well suited for
this work. The 2N5909s have a maximum Ib of 1.0 pA, and
at room temperature it will drift only 0.1 pA/·C. Typical drift
is 0.02 pArCo
The voltage offset adjust pot is used to bring the summing
point within a millivolt of ground. With an input signal big
enough to cause fOUT= 1 second per cycle, trim the Voffset adjust pot so that closing the test switch makes no
effect on the output frequency (or, output period). Then adjust the Input current offset pot, to get fOUT = 1/1000 of fullscale when liN is 111000 of full-scale. When liN covers the
140 dB range, from 200 p.A to 20 pA, the output will be
stable, with very good zero offset stability, for a limited temperature range around room temperature. Note these precautions and special procedures:
1. Run the LM331 on 5V to BV to keep leakage down and
to cut the dissipation and temperature rise, too.
2. Run the FETs with a 6V drain supply.
3. Guard all summing point wiring away from all other
voltages.
IV
1.1,.
±I"
CURRENT
OFFSET
ADJUST
V-
~-----"-'OUT
1.311
v+
"N
-
ZDlpA
FULL-SCALE
- .. -"
,,,
,
'II
"
Ql • 2N5909 or stmllar
lG<1 pA
waFfSET
ADJUJr
ULTRA·LOW
LEAKAGE
Opgp
I
L-- ".
"
Q2 - 2N930
or 2N3565
vTLIH/5822-3
FiGURE 3a. Very-Wide-Range Current·to-Frequency COnverter
491
An alternate approach, shown in Figure 3b, uses an LM11 C
as the input pre-amplifier. The LM1'1C has much better voltage drift than-any of the other amplifiers shown here (normally -jess than 2 p.VlOC) and excellent current drift, less
than1pAI"C by, itself, and typically 0.2 pAI"C when
trimmed with the 2N3904 bias current compensation- circuit
as shown. Of course, the LM331's leakage of1 pAloC will
still double every 10"C, ,$0 that hEWing an amplifier with excellent Ib characteristics does not-solve the whole problem,
when trying to get good accuracy with a 100 pA signal. For
that job, even thE! leakage of the LM331- must be guarded
out!
What if even lower ranges of input current must be accepted? While it might be possible to use a current-to-voltage
converter ahead of a V-to-F converter, offset voltage drifts
would hurt dynamic range badly. Response and zero-drift of
such an I-V will be disappointing. Also, it is not feasible to
starve the LM331 to an arbitrary extent.
For example, while its lOUT (full-scale) of 280 p.A DC can be
cut to 10 p.A or 28 p.A, it cannot be cut to 1 p.A or 2.8 p.A
with good accuracy at 10kHz, because the internal
switches in the integrated circuit will not operate with best
speed and precision at such low currents.
Instead, the output current from pin 1 of the LM331 can be
fed-through a current attenuator circuit, as shown in.F/{Jure
4. The LM334 (temperature-to-current converter IC) causes
-120 mV bias to appear at the- base of 02. When a current
flaws-out of pin 1 of the LM331, 1/100 6f thec;:urrent will
flow out of 01's collector, and the rest will go out of 02's
collector. As theLM334's current is linearly proportional to
Kelvin temperature, the -120 mV at 02'8 base will change
linearly with temperature so that the 01/02 current divider
stays at 1:100, invariant of temperature, according to'the
equation:
i
r
1 '2 ='e
q(Vb1 - Vb2}
kT,
This current attenuator will work stably and accurately, even
at high speeds, such as for 4 p.S current pulses. Thus, the
output of 01 is a charge pump which puts out only 10 picocoulombs per pulse, with surprisingly good accuracy. Note
also that the LM331's leakage is substantially attenuated
also, by a factor of 100 or more, so that source of error
IV
1II1II
I.
un1%
LM331
1.01",
POLYmRENE
~
Io=------=--~'OUT
!.IVDe
10l1li
Ulk
1%
Uk
aI, 2N3904 or any silicon NPN
02, 2N930 or 2N3565
1114002
TL/H/5622-4
FIGURE 3b. Very-Wlde-Range I-to-F Converter with Low Voltage Drift
492
virtually disappears. When Q1 is off, it is really OFF. and its
leakage is typically 0.01 pA if the summing point is within a
millivolt or two of ground.
Now, with an input current of 1 p.A, the full-seele output
frequency will be 100kHz. At a 1 nA input, the output frequency will be 100 Hz. And, when the input current is 1 pA,
the output frequency will drop to 1 cycle per 10 seconds or
100 mHz. When the input current drops to zero, frequencies
as small as 500 "Hz have been observed, at 25°C and also
as warm as 35"C. Here is a 'wide-range data converter
whose zero drift is well below 1 ppm per 10"CI (Rather more
like 0.001 ppm per"C.) The usable dynamic range is better
than 140 dB, with excellent accuracy at inputs between
100% and 1% and 0.Q1 % and 0.0001 % of full-scale.
To do justice to this low leakage of the VFC, the op amp
should be made with MOSFETs for Q3 and 04, such as the
Intersil3N165 or 3N190 dual MOSFET (with no gate-protection dodes). When MOSFETs have relatively poor offset
voltage, offset voltage drift, and voltage noise, this circuit
does not care much about these characteristics, but instead
takes advantage of the MOSFET's superior current leakage
and current drift.
IIV
IDak
I....
....I~F
lit
I.Ilk
Ilk
III
IN'UT
Ct
ZERO
ADjUST
~'=' 33G,F
..L
LM331
v·
111Hz
f.--=~----"'-. SCALE
FULL·
1II1II
Ik
1M ~-Yi"",""",Jt,fo.""''''
OUTPUT
..,
Ik
>111
III
%III
III
.111
Uk
'='
IDa
'1"
Uk
' - - - -......._ - ' -...... -IIVI
11"
IIV
VDFFIET
ADjUST
IN
1111
I~
-
Ilk
.111
FULL·
SCALE
Ilk
I·. .r.-I.,o"
~-I
. . . '1IP110IAL
LtJW.LEAIME
..
I
_T
IIFFER
I
'.11
Q1 • 2N4250 or 2N3906
- - -...- ..... v-
Q2, Q3, Q4. 2~904 or 2N3686
I
""':,
FIGURE 5. C\Irrent·to-Frequency Converter For P08ltlve Signals
"';'
'='
~,
'
494
TUH/5622-8
National Semiconductor
Application Note 241
Working with High
Impedance Op Amps
Robert J. Widlar
Apartado Postal 541
Puerto Vallarta, Jalisco
Mexico
Abstract New developfTl8nts have dramatically redUC8d
the error currents of Ie op amps, 8Sp8Cially at high temperatures. The basic techniques used to obtain this peformance
are briefly described. SOfTI8 of the problems associated with
working at the high impedance levels that take advantage of
these low error cUffents are discussed along with the;r solutions. The areas involved are printed-circuit board leakage,
cable leakage and noise generation, semiconductor-switch
leakages, large-value resistors and capaCitor limitations.
Introduction
A new, low cost op amp reduces dc error terms to where the
amplifier may no longer be the limiting factor in many practical circuits. FET bias currents are equalled at room temperature; but unlike FETs, the bias current is relatively stable
even over a - 55°C to 125°C temperature range. Offset voltage and drift are low because bipolar inputs and on-wafer
trimming are used. The 100 p.V offset voltage and 25 pA
bias current are expected to advance the state of the art for
high impedance sensors and signal conditioners.
bias currents
There has been a continual effort to reduce the bias current
of IC op amps ever since the p.A709 was introduced in
1965. The LM101A, announced in 1968, dropped this current by an order of magnitude through improved processing
that 'gave better transistor current gain at low operating curIDOnA
...z
...
..
...5
II:
II:
:::0
LMIOIA
.."
lUnA
V
InA ~
- 10,A
-
1.1
i...
V r--.
to- r-
i
0
50
TEMPERATURE
100
OA
1.2
co
0
-8.2
Ie
~
-DA
-D.•
...;=
/
D.6
II
!:;
~ K. r--.. LM11 .,
v 11 ioS ~
r~ ~
I,A
-50
This low bias current has not been obtained at the expense
of offset voltage or drift. Typical offset voltage is under a
millivolt and provision is made for on-water trimming to get it
below 100 p.V. The low drift exhibited inRgure 2 indicates
that the circuit is inherently balanced for exceptionally low
drift, typically 1 p.VloC below 100"C.
0.8
/LF155
~LMI08
:l
ii 108 pA
r
rents. In 1969, super-gain transistors (see appendix) were
applied in the LM108 to beat FET performance when temperatures above 85"C were involved.
In 1974 FETs were integrated with bipolar devices to give
the first FET op amp produced in volume, the LF155. These
devices were faster than general purpose bipolar op amps
and had lower bias current below 70"C. But FETs exhibit
higher offset voltage and drift than bipolars. Long-term stability is also about an order of magnitude worse. Typically,
this drift is 100 p.Vlyear, but a small percentage could be as
bad as 1 mV. Laser trimming and other process improvements have lowered initial offset but have not eliminated the
drift problem.
The new IC is an extension of super-gain bipolar techniques. As can be seen from Figure 1, it provides low bias
currents over a - 55°C to 125°C temperature range. The
offset current is so low as to be lost in the noise. This level
of performance has previously been unavailable for either
low-cost industrial designs or high reliability military/space
applications.
\.
\
-0.8
-1.0
-sa
150
rei
0
50
180
150
TEMPERATURE (OC)
TLlH17478-1
TLlH17478-2
Figure 1. Comparison ot typical bias currents for various types of IC op amps. New bipolar device
not only has lower blss current over practical
temperature ranges but also lower drift. Offset
current Is unusually low with the new design.
Figure 2. Bipolar transistors have Inherently low offset
voltage and drift. The low drift of the LM11
over a wide temperature range shows that
there are no design problems degrading pe....
formance.
495
_
~
r-------------------------------------------------------------------~
:'Jw.,i;I,e)'V op amp
With the LM11, both voltage and ,current related dc errors
have been reduced to the 'point where overall circuit performance could w,ell be noise limited, particularly ir;l limited
temperature range applications.
..,
,
he LM11 is, in essence, a refinement of thet:M108. A
~ <4'modifi~
Darlington input stage has been added to reduce
"-!:lias currents. With a standard Darlington, one transistor is
biased with the base current of the other. This degrades dc
amplifier performance because base current is noisy, subject to wide variation and generally unpredictable.
211
~
Supplying a bleed current greater than the base current, as
shown in Figuf'8 3, removes this objection. The 60 nA provided is considerably in excess of the 1 nA base current.
The.bleet;! current is made to vary as absolute temperature
to' maintain eoristant impedance at the 'emltt!il\'S of 01, and
02. This stabilizes frequency response and, also redu99s
the thermal variation cif bias current. ParasitiC, capacitances
of the currerit generator have been bootstrapped SO that the
0.3 VI p.s slew rate of the basic ampntier is unaffected..
III
1",.. -1 H.
lis-lanD
TA -Zi·e
10
~co
>
'~~
~
co
I
5...'"' -1.
n..... ~ If' WI lJ.
'.
!!
-20
OUTPUTS
a
IGO
ZGO
""
300
~
400
TIME lsi
:rLIH17478-4
Figure 4. Lower operating currents increase nOise, but
low frequency n,olse is stili slightly lower than
Ie FET amplifiers. Lorig-Jerm stability is much
Impr,oved.,
'.
reliability
The reliability of the LM 11 is' not expected to be substantialIydlfferent than the LM1 os, which has beeh usEid extensively in military and space applications. The only significant
, difference is the input stage. The low current nodes introduced here might possibly be a problem were they not bootstrapped, biased and guarded to be virtually unaffected by
both bulk and surface leakages. This qpinion Is substantiat.' ,
ed' by preliminary life-test data.
This IC could, in fact, be expected to improve reliability
when used to replace discrete or hybrid amplifiers thatuse
selected components lijnd have been trimmed and tweaked
to give the required performance.
From an equipment standpOint, reliability analysiS of Insulating mate,rials, sl,!rface contamination, cleaning procedures,
surface coating and potting are at least as important as the
IC and other components. These factors become more important as Impedance levels are raised. But this should not
discourage designers. If poor Insulation and contamination
cause a problem when Impedance levels are raised by an
order of magnitude, It is best found out and fixed.
v--.....- -...
TL/H/7478-3
Figure 3. Modifying Darlington with tileed current reduces offset voltage, drift 'and noise. Unique
Circuitry provides well-controlled current with
minimal stray capaCitance so that speed of the
basic amplifier is unaffected.'
Results to date suggest that the base currents of this modified Darlington input are better matched than the simple
differential amplifier. In fact, offset current is so low as to be
unmeasurable on production test systems. Therefore, guaranteed limits are determined Ily the test equipment rather
~han the IC.
noise
Operating trahsistors' at' very low' currents does increase
nOise. Thus, the LM11 is about a faetor of four noisier than
''the LM10S; But the low frequency noise, plotted in Figuf'84,
is still slightly less than that of FET ampfifiers. Long-term
measurements indicate that the offset voltage shift Is under
10 p.V.
In contrast to the noise voltage, low frequency noise current
is subject to greater unit-to-unit variation. Generally, it is below 1 pA, peak-to-peak, about the same magnitude as the
offset current.
Even so, It may not be advisable to take advantage of the
full potential of the LM11 in all cases, especially when hostile environments are involved. For example, there should
be no great difficulty in finding an LM11 with offset current
less than 5 pA over a - 55·C to 125·C temperature range.
But anyone designing high-reliability equipment that Is going
to be in trouble if combined leakages are greater than 10 pA
at 125·C had best know what he is about. '
electrical guarding .
Thlil effects of bQard I$akage can be minimized using an old
" trick known as guarding.
the Input circuitry Is surround," ed by' a conductive trace that is conneCted to a low Im!'edance point at the same potential as the inputs. The electrical connection of the guard for the basic op amp COnfigurations Is shown In F/{Juf'8 5. The guard absorbs the leakage
from other points on the board, drastically reducing that
reaching the Input circuitry.
Here
496
To be completely effective, there should be a guard ring on
both sides of the printed-circuit board. It is still recommended for single-sided boards, but what happens on the. unguarded side is difficult to analyze unless Teflon inserts are
used on the input leads. Further, although surface leakage
can be virtually eliminated, the reduction in bulk leakage is
much less. The reduction in bulk leakage for double-sided
guarding is about an order of magnitude, but .this depends
on board thickness and the width of the guard ring. If there
are bulk leakage problems, Teflon inserts on the through
holes and Teflon or kel-F standoffs for terminations can be
used. These two materials have excellent surface properties
without surface treatment even in high-humidity environments.
,;
BALANCE
I~
'8~
OUTPUT, 6
,
COMPENSATION
HI
H2
INPUT -I\I\".,....---"""'IN~--....,
0
1
5
.
I
----..
4
v-
TLlHI747S-S
BoHomVlew
Figure 6. Input guarding can 'drastically reduce surface
leakage. Layout· for metal can Is shown here.
Guarding both sides of board is required. Bulk
leakage reduction Is less and depends on
guard ring width.
OUTPUT
H3
signal cables
It is advisable to locate high impedance amplifiers as close
as possible to the signal source. But sometimes connE!Cling.
lines cannot be avoided. Coaxially shielded cables with
good insulation are recommended. Polyethelene or virgin
(not reconstituted) Teflon is best for critical applications.
In addition to potential insulation-problems, even short cable
runs can ·reduce bandwidth unacceptably with high source
resistances. These problems can be largely' avoided by
bootstrapping the cable shield. This is shown for the follower connection in Figure 7. In a way, bootstrapping is pOSitive
feedback; but instability can be avoided with a small capacitor on the input.
Cable Bootstrapping
TLlHI747S-5
a. Inverting amplifier
OUTPUT
TL/HI747S-6
b.follower
RZ
R3
OUTPUT
INPUT
OUTPUT
RI
-
TLlHI747S-9
INPUT
TL/H/747S-7
c. non-inverting amplifier
Figure 5. Input guarding for various op amp connections. The guard should be connected to a .
point at the same potential as the inputs with a
low enough Impedance to absorb board leakage without Introducing excessive offset.
An example of a guarded layout for the metal-can package
is shown in Figure 6. Ceramic and plastic ,dual-in-line packag9$ are avaHable for critical applications with guard pins
adjacent to the inputs both to facilitate board layout and to
reduce package leakage. These guard pins are not internally connected.
497·
Figure 7. Bootstrapping input shield for a follower reduces cable capacitance, leakage and spurious voltages from cable flexing. Instability can
be avoide~ with small capaCitor on input.
With the summing amplifier, the cable shield is simply
grounded, with the summing node at virtual ground. A small
feedback capacitor may be required to insure stability with
the added cable capacitance. This is shown in Figure 8.
~ ~----------------------------------------------------------------------------------~
;
~
OUTPUT
Tl/H17478-10
Figure 8. With summing amplifier, summing node Is at
virtual ground so Input shield Is best grounded. Small feedback capacitor Inaures stability.
An inverting amplifier with gain may require a separate follower to drive the cable shield if the influence of the capacitance, between shield and ground, on the feedback network
cannot be accounted for.
High impedance circuits are also prone to mechanical noise
(microphonics) generated by variable stray capacitances. A
capacitance variation will generate a noise voltage given by
"
aC
en
=CV,
where V is the dc bias on the capacitor. Therefore, the wiring and components connected to sensitive nodes should
be mechanically rigid.
This is also a problem with flexible cables, in that bending
the cable can cause a capacitance change. Bootstrapping
the shield nearly eliminates dc bias on the cable, minimizing
the voltage generated. Another problem is electrostatic
charge created by friction. Graphite lubricated Teflon cable
will reduce this.
switch leakage
Semiconductor switches with"leakage currents as low as the
bias current of the LM11 are not generally available when
operation much above 50"C is involved. The sample-andhold circuit in Figure 9 shows a way around this problem. It
is arranged so that switch leakage does not reach the storage capacitor.
Isolating leakage current requires that two switches be connected in series. The leakage of the first, 01, is absorbed by
R1 so that the second, 02, only has the offset voltage of the
op amp across its junctions. This can be expected to reduce
leakage by at least two orders of magnitude. Adjusting the
op amp offset to zero at the maximum operating temperature will give the ultimate leakage reduction, but this is not
usually required with the LM11.
MOS switches with gate-protection diodes are preferred in
production situations as they are less sensitive to damage
from static charges in handling. If used, 01 and R2 should
be included to remove bias from the protection diode during
hold. This may not be required in all cases but is advised
since leakage from the protection diode depends on the
internal geometry of the switch, something the designer
does not normally control.
A junction FET could be used for 01 but not 02 because
there is no equivalent to the enhancement mode MOSFET.
The gate of a JFET must be reverse biased to turn it off, and
leakage on its output cannot be avoided.
high-value resistors
Using op amps at very high impedance levels can require
unusually large resistor values. Standard precision resistors
are available up to 10 MO. Resistors up to 1 GO can be
obtained at a significant cost premium. Larger values are
quite expensive, physically large and require careful handling to avoid contamination. Accuracy is also a problem.
There are techniques for raising effective resistor values in
op amp circuits. In theory, performance is degraded; in practice, this may not be the case.
With a buffer amplifier, it is sometimes desirable to put a
resistor to ground on the input to keep the output under
control when the signal source is disconnected. Otherwise it
will saturate. Since this resistor should not load the source,
very large values can be required in high-impedance circuits.
F/{Jure 10 shows a voltage follower with a 1 GO input resistance built using standard resistor values. With the input disconnected, the input offset voltage is multiplied by the same
factor as R2; but the added error is small because the offset
voltage of the LM11 is so low. When the input is connected
to a source less than 1 GO, this error is reduced. For an accoupled input, a second 10 MO resistor could be connected
in series with the inverting input to. virtually eliminate bias
current error; bypassing it would give minimal noise.
v+
Rl
11k
INPUT
SAMPLE ~t--f.-"'~'N~~I---""'"
OUTPUT
Lr
TLlH17478-11
Figure 9. Switch leakage In this sample and hold does not reach storl\g~"capaCltOr.1f Q21)88 an Internal gate-protection diode, D1 and R2 must be Included to remove bias t~om its Junction during hold.
498
!
RI
III
-
TLlH17478-12
figure 10. Follower Input resistance Is 1 GO. With the
Input open, offset voltage Is multiplied by
100, but the added error Is not great because
the op amp Offael Is IoVi.
The voltage-to-current converter in rtgUre 11 uaes a similar
method to obtain the equivalent of a 10 GO feedback resistor. Output offset is reduced because the error can be made
dependent on offset curlent rather than bias current. This
would not be practical with'largevall$ resistors because of
cost, particularly, for matched resistors, and because the
summing node would be offset several hundred millivolts
from ground. In Figure 11, this offset is limited to several
millivolts. In addition, th~ output can be nulled with the usual
balance potentiometer. Further, gain trimming is easily
done.
R88I8tanc:e Mumpllcatlon
I.
quency shaping and charge measuring circuits require control of the capacitor tolerance, temperature drift and stability _
with temperature ,cycling. For smaller values, NPO ceramic ...
is best while a polystyrene-polycarbonate combination gives
good results for larger values over a -10"C to 85·C range.
Dielectric absorption can also be a problem. It C8Uaes a
capacitor that has been quick-charged to drift back toward
its previous state over many milliseconds. The effect is most
noticeable in sample-and-hold circuits. Polystyrene, Teflon
and NPO ceramic capacitors are most satisfactory in this
regard. Choice depends mainly on capacitance and temperature range.
Insulation resistance can clearly become a problem with
high-impedance circuitry. Best performer is Teflon, with
polystyrene being a good substitute below 8SOC. Mylar capacitors should be avoided, especially where higher temperatures are involved.
Temperature changes can also alter the terminal voltage of
a capacitor. Because thermal time constants are long, this
is only a problem when holding intervals are several minutes
or so. The effect is reported to be as high as 10 mVrc, but
Teflon capacitors that hold it to 0.5 mVrc are available'.
An op amp with lower bias current can ease capacitor problems, primarily by reducing size. This is obvious with a sam- '
ple-and-hold because the capacitor value is determined by
the hold interval and the amplifier bias current. The circuit in
Figure 12 is another example. An RC time constant of more
than a quarter hour is obtainE\d with standard component
values. Even when such long Jlme constants are not required, redUCing capacitor size to where NPO ceramics can
be used is a great aid in prec~on work. '
....M*
RZ
1%
1%
R3
-
liN
I.
,1II1II
RI
OUTPUT
H2'
1111
INPUT-~""'''''~W'--'''-.:f
VaUT
T
CI
=
!!!.£
(R2 + R3)
R3
T''':V =~(I
R2+Vosl
R3
B
":'
OUT
RI
TLlH17478-14
IOIIM
t
1%
":'
figure 12.
NULL
1000 "conds and provides low output 1mpedanca. Cost Is lowered because of .....
duced realstor and capacitor values.
v+
TLlH/7478-13
Figure 11. Equivalent feedback resistance Is 10 GO, but
only standard resistors are used. Evan
though the offset voltage Is mumplled by
100, output offset Is actually reduced because error Is dependent on offset current
rather than bias current. Voltage on summing
Junction Is less than 5 mV.
This circuit would benefit from lower offset current than can
be tested and guaranteed with automatic test equipment.
But thera should be no problem in selecting a device for
critical applications.
capacitors
Op amp circuits impose added requirements on capacitors,
and this is compounded with high-impedance Circuitry. Fre-
This cIrcUit multIpHes RC time constant to
concIuelons
A low cost IC op amp has been described that not only has
low offset voltage but also advances the state of the art in
reducing input current error, particularly at elevated temperatures. Designers of industrial as well as military/space
equipment can now work more freely at high impedance
levels.
Although high-impedance circuitry is more sensitive to
board leakages, wiring capacitances, stray pick-up and leakage in other components, it has been shown how input
guarding, bootstrapping, shielding and leakage isolation can
largely eliminate these problems.
499
-Component R _ Co., Inc., Santa Monica, CeIifomIa.
,
_
r-------------------------------------------------------------------------------~
~:
~
ackn_ledgmant
The authOr would like 10 acknawledgethe asSistance of the
staff at National Semiconductor In irriplementing this design
and sorting'out the application problems. DiscusSions with
Bob Dobkin, Bob Pease, earl Nelson and Mineo Yamatake
have been most helpful.
appendix "
super-gain techniques
Super-gain 'transistors are not new, having been developed
for the LM102/LM110 .voltagefollowers in 1967 and latar
used on the LM108 general-purpose op amp. They are similar to reglliar transistprs, except that they: are diffused for
high current gains (2,oo0-10,OQO) at .the expense of breakd9wn v<;lltage. Acurva-tracer display Of. a typical device is
shown in Figure A 1. In an IC,. super-gain transisto,rs Can be
made simultaneously with standard transistors by including
a second, light base predeposition that is. diffused less
deeply.···
:.,
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40
,150A
'(
4
I.A:
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II:
Super-gain transistors ean·be connected in ·cB$COde with
regular transistors to form a composite device with both
high gain and high breakdown. The simplified schematic of
the LM108 i(iput stage in FlgureA2shows hOw it is done. A
commoF,l bas~ pair, Q3 and 04, is bootstrapped to the input
transistors, Q1 and Q2, So that the latter are operated at
nearly zero collector-base voltage, no matter what tbeinput
common-mode. The regular' NPN transistors: are distinguished by drawing them with wider base regiol'\s.
Operating the input transistors at very low collector-base
voltage has the added advantage of drastically reducing collector-base leakage. In this configuration bipolar transistors
are affected little by the leakage currents that limit perform- ,
ance of FET amplifiers.
2,
••
TLlH17478-18
Figure A2. A bootatrapped Input stage
COLLECTOR EMITTER VOLTAGE (V)
TLlH17478-15
Figure A 1. curve tracer display of a
super-galn translator '
*See .Addendum at the End
of Application Note 242.
500
National Semiconductor
Application Note 242
Applying a New
Precision Op Amp
Robert J. Widlar
Apartado Postal 541
Puerto Vallarta, Jalisco
Mexico
Bob Pease and Mineo Yamatake
National Semiconductor Corporation
Santa Clara, California
U.S.A.
Abstract: A new bipolar op amp design has advanced the
state of the art by reducing offset voltage and bias current
errors. Its characteristics are described here, indicating an
ultimate input resolution of 10 p. Vand 1 pA under laboratory
conditions. Practical circuits for making voltmeters, ammeters, differential instrumentation amplifiers and a variety of
other designs that can benefit from the improved performance are covered in detail Methods of coupling the new
device to existing fast amplifiers to take advantage of the
best characteristics of both, even in follower applications,
are explored.
Transistors with typical current gains of 5000 have been
used in the manufacture of the LM 11. The input stage employs a Darlington connection that has been modified so
that offset voltage and drift are not degraded. The typical
input currents, plotted in Figure 1, demonstrate the value of
the approach.
88
i...
...
The essential details of the design .along with an introduction to the peculiarities of high-impedance circuits have
been presented elsewhere.· This will be expanded here.
Practical circuitry that reduces effective bias current for
those applications where performance cannot be made dependent on offset current are described. In addition, circuits
combining the DC characteristics of the new part with the
AC performance of existing fast amplifiers will be shown.
This will be capped with a number of practical designs to
provide some perspective into what might be done.
de errors
Barring the use of chopper or reset stabilization, the best
offset voltage, drift and long-term stability are obtained using bipolar transistors for the op amp input stage. This has
been done with the LM11. On-wafer trimming further improves performance. Typically, a 100 /J-V offset with
1 p.V I"C drift results.
::0
i...
I
I
BIAS""
u
10-
"'-
.- -
r--. k'
~ I-- !OFFSET
--41
-10
-10
II
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TEIIP£RATURE rei
II
'11
,
TL/H17479-1 I
Figure 1. Below 100"C, bias current varies almost linearly, with temperature•. Thls means that simple
circuitry can be used for compensation. Offset
current Is unusually low.
The offset current of this op amp is so low that it cannot be
measured on existing prod,uction test equipment. Therefore,
it probably cannot be specified tighter than 10 pA. For critical applications, the user should have little difficulty in selecting to a tighter limit.
The bias current of the LM11 equals that of monolithic FET
amplifier at 25°C. Unlike FETs, it does not double every
10"C. In fact, the drift over a - 55°C to + 125°C temperature
range is about the same as that of a FET op amp during
normal warm up.
Other characteristics are summarize.d in Table I. It can be
seen that the common-mode rejection, supply-voltage rejection and voltage gain are high enough to take full advantage of the low offset voltage. The unspectacular 0.3V/ p.S
slew rate is balanced by the 300 p.A current drain.
'R. J. Wldlar, "Working with High Impedance Op Amps", National Samiconductor AN·241.
501
"""'",-
a:
a:
Introduction
A low cost, mass·produced op ,amp with electrometer-type
input currents combined with low offset voltage and drift is
now available. DeSignated the LMt1, this IC can minimize
production problems by providing accuracy without adjustments, even in high-impedance Circuitry. On the other hand,
if pushed to its full potential, what has been impossible in
the past becomes entirely practical.
Significantly, the LM11 is not restricted to commercial and
industrial use. Devices can be completely specified over a
- 55°C to + 125°C range. Preliminary data indicates that
reliability is the same as standard ICs qualified for military
and space applications.
'
411
.Tablel. Typical characterlatlca of the
LM11forTJ = 25"Cand Vs = ±15V.Operatlonls
.
specified down to Vs = ± 2.5V.
paramet.r
Conditions
Value
. Input Offset Voltage
100 p.V
Input Offset Current
500 fA
Input Bias Current
25pA
8 p.Vpp
Input Noise Voltage 0.01 Hz :s: f :s: 10Hz
Input Noise Current 0.01 Hz :s: f :s: 10Hz
1 pApp
Long Term Stability Tj = 25°C
10 p.V
1 p.VloC
Offset Voltage Drift -55°C:s: Tj :s: 125°C
Offset Current Drift -55°C:s: Tj :s: 125°C
20fAI"C
Bias Current Drift
-55°C:S: Tj:S: 125"C 5OOfA/oC
Voltage Gain
VOUT = ±12V,
1,200V/mV
lOUT = ± 0.5 mA
300VlmV
VOUT = ±12V,
lOUT = ±2mA.
Common-Mode
-12.5V:S: VCM:S: 14V 130 dB
Rejection
Supply-Voltage
±2.5V:S: Vs:S: ±20V
118dB
Rejection
Slew Rate
0.3V/p.S
Supply Current
300 p.A
all circuits. Examples are in~egrators, sample and holds, logarithmic converters and signal'lionditioning amplifierS. And
even though the LM1.1 bi~. ourrent is. low,. there will be
those applications wh8re it needs to be lower. .
.
Referring back to Figure 1, it can be seen that the bias
current drift is essentially linear over a ...:. 50"C to + 100"C
range. This is a deliberate consequence of the input stege
design. Because of it, relatively simple circuitry can be used
to develop a compensating current
As might be expected, the low bias currents were obtained
with some secrifice in noise. But the low frequency noise
voltage is still a bit iess t~ a FET amplifier and probably
more predictable. The latter is important because this noise
cannot be tested in production. Long term measurements
have not indicated any drift in excess of the noise. This is
not the case for FETs;
.
It is worthwhile noting that the drift of offset voltage and
current is low enough that DC accuracy is noise limited in
room·temperature applications.
Figure 2. Th. LM11 operata8 from MO sourc. reslstanc.s with IIHIe DC .rror. With equallOurce reslatancas, accuracy Is ....ntlally limited by
low frequency current noise.
Bias current compensation is not new, but making it effective with even limited temperature excUrsions has been a
problem. An early circuit' suggested for bipolar ICs is shown
in Figure Ss. The comperisating current is determined by the
diode voltage. This does not vary as rapidly with temperature as bias current nor does it match the usual non-linearities.
With the improved circuit in Figure 3b, the temperature coefficieirt can be increased by using a transistor and including
R2. The drop across R2 is nearly constant with temperature.
The voltage delivered to the potentiometer has a 2.2 mV1°C
drift while its magnitude is determined by R2. Thus, as long
as the bias current varies linearly with temperature, a value
for R2 can be found to effect compensation.
1
III
~
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...,.
100
58
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ZO
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ONE.
INPUY
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1.5
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187
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k':"80TH
'. IN.P~TS_
108
108
1.1.
SOURCE RESISTANCE en!
TLfHI7479-2
bias current companeatlon
The LM11 can operate from MO source resistances with
little increase in the equivalent offset voltage, as can be
seen in FIgUre 2. This is impressive considering the low initial offset voltage. The Situation is much iinproved if the design can be configured so that the op amp sees equal resist·
anCe on the two i~puts. However, this cannot be done with
15V
HI
1.5.
15V
11
1!G1l
Dl
IN457
l:k
--""""RN3~-I
41'
3IIIIk
TUH17479-3
TUH17479-4
a. original Circuit
b.lmproved veralon
figura 3. Blas-currant companeatlon. With the Improved varslon, the temperature coefficient of the compeneatlng
current can be varied with A2. It Is effective only If bias current has linear, negative temperature coefficient.
502
r--------------------------------------------------------------------,~
In production, altering resistors based on temperature testing is to be avoided if at all possible. Therefore, the results
that can be obtained with simple nulling at room temperature and a fixed value for R2 are of interest. Figure 4 gives
this data for a range of parts with different initial bias currents. This was obtained from pre-production and initial-production runs. The bias current variations were the result of
both hFE variations and changes in internal operating currents and represent the worst as well as best obtained.
They are therefore considered a realistic estimate of what
would be encountered among various production lots.
20
~
z
....'"
..'"
..•'"
One disadvantage of the new circuit is that it is more sensitive to supply variations than the old. This is no problem if
the supplies are regulated to 1%. But with worst regulation it
suffers because, with R2, the transistor no longer functions
as a regulator and because much tighter compensation is
obtained.
The circuit in Figure 5 uses pre-regulation to solve this problem. The added reference diode has a low breakdown so
that the minimum operating voltage of the op amp is unrestricted. Because of the low breakdown, the drop across R3
can no longer be considered constant. But it will vary linearly with temperature, so this is of no consequence. The fact
that this reference can be used for other functions should
not be overlooked because a regulated voltage is frequently
required in designs using op amps.
.....
DO\
0-
lIJ
Little comment need be made on these results, except that
the method is sufficiently predictable that another factor of
five reduction in worst case bias current could be made by
aHering R2 based on the results of a single temperature run.
10
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,
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ii
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~
i
-20
-50
I
40000000a0000o
In Figure 5, a divider is used so that the resistor feeding the
compensating current to the op amp can be reduced. There
will be an error current developed for any offset voltage
change across R6. This should not be a problem with the
LM11 because of its low offset voltage. But for tight compensation, mismatch in the temperature characteristics of
R4 and R5 must be considered.
~i
:i
15--100
50
150
TEMPERATURE ('C)
TL/Hf7479-5
Figure 4. Compel188ted bias current for five representative units with a range of Initial bias currents.
The circuit in FIgure 3b was used with balancIng at 2S·C. High drift devices could be Improved further by altering R2.
R2
68k
R3
30k
01
lM385
1.2V
2N2484
Ql
INPUT
R4
1.3M
Cl
R6
100M
R5
lOOk >."-~",,"-4""--"I
OUTPUT
TLlHf7479-6
Figure 5. Bias current compensation for use with unregulated supplies..
Reference voltage Is available for other circuitry.
503
:r:
...
N
N
Nr---------------------------------------------------~
~
Z
c(
e~has limited valUe. However, the bootstrapped'ioput stage
of the LM11 reduces this to about 2 pA for a ± 20V common-mode swing, gMng a2 x 10130 common-mode Input
resistance.' '. . . . ,
. . : , ...
Bias ,current compensation is more difficult for non-inverting
amplifiers because the common-mode voltage varies. With
a voltage follower, everything can be bootstrapped to the
output 'and powered by a regulated' current source, ·as
shown in Figure 6.. The' LM334 is a· \e!llpe~atu.re !!8nsor. It
reguilites against voltage changes and i~ output varies,linearly ~It temperature, so it fits the bill. . .
."
Although the LM334 can accommodate voltage cha~ges
fast erwugh to work with the LM11, it is not fast enough for
the high-speed circuits to be deSCribed. But compensation
can still 'be obtained by \Ising the zener diode pre-regulator
bootstrapped to the output and powered by eittter a resiStor
or FET cjJrrent source•. The LM385 fits ,well here,becau~
both the breakdown voltage and IT!ini~um operating current
are low.
.,
.
,
With ordina~ op amps, the collector base voHage of, the
input· transistors varies with' the cammon-mode voltage. A
50%· change in bias current over the common-mode range
is not unusual, so compensating the bias current of a follow-
A precision oCamplifier, although sloW; can
used to ~~~
bilize th.e offset voltage of a .I~, preqiSEl- fliSt amplifillr. As
shown, In Fl{}ure 7, thl! slow a~plif\er ,senses thE! voltage
across, the input terminals and suppl,es a co,rrection. signal
to the balance terminals of the fast amplifier. The LM11 Is
particularly interesting in this respect as it dOes not degrade
the input bias current of the composite even when the fast
amplifier has a FET input.
SurpriSingly, with ti)e LM11, this Will, work for both inverting
and non-inverting connections because its common-mode
slew recove~ is a lot faster than that of the main loop. This
was accomplished, even, wHh' circul~ running under
100 nA, by proper clamping and by bootstrapping of internal
stray capacitances.
6e
115
240
+-..........,1---......;::.,
INPUTS
OUTPUT
~UTPUT
INPUT-"'--~=.f
TlIH/7479-8
Tl/H11479-7
Figure 6. This circuit ilhow~ how bias current compensation can be used on a voltage fOllower.
Figure 7. A' slow amplifier can be used to null the offset
of a fast amplifier.
504
An optimized circuit for the inverting amplifier connection is
shown in Figure 8. The LM11 is DC coupled to the input and
drives the balance terminals of the fast amplifier. The fast
amplifier is AC.coupled to the input and drives the output.
This isolates FET leakage from the input circuitry.
Measurements indicate that the slew rate of the fast amplifier is unimpaired, as is the settling time to 1 mV for a 20V
output excursion. If the composite amplifier is overdriven so
that the output saturates, there will be an added recovery
delay because the coupling capacitor to the fast amplifier
takes on a charge with the summing node off ground.
Therefore,. C1 should be made as· small as possible. But
going below the values given may introduce gain error.
If the bias current of the fast amplifier meets circuit requirements, it can be direct-coupled to the input. In this case,
offset voltage is improved, not bias current. But overload
recovery can be reduced. The AC coupling to the fast-amplifier input might best be eliminated for limited-temperaturerange operation.
This connection also increases the open-loop gain beyond
that of the LM11, perticularly since two-pole compensation
can be effected to reduce AC gain error at moderate frequencies. The DC gains measured showed something in
excess of 140 dB.
As can be seen, the method of coupling into the balance
terminals will vary depending on the internal configuration of
the fast amplifier. If the quiescent voltage on the balance
terminals is beyond the output swing of the LM11, a differential coupling must be used, as in Figure 88. A lead capacitor, C2, reduces the AC swing required at the LM11 output.
The clamp diode, 01, insures that the LM11 does not overdrive the fast amplifier in slew.
If the quiescent voltage on the balance terminals is such
that the LM11 can drive directly, the circuit in Figure 8b can
be used. A clamp diode from the other balance terminal to
internal circuitry of the LM11 keeps the output from swinging too far from the null value, and a resistor may be required in series with its output to insure stability.
R2
10k
R5
10k
Rl
10k
Rl
10k
INPUT-~I\o-+--.:t
INPUT
R2
24k
Cl
li8pF
Cl
500pF
C2
OA7.F
R4
1M
>-+----4~DUTPUT
R3
1M
Dl
lN457
OUTPUT
C3
3DpF
TL/H/7479-9
TlIH/7479-10
b. with fast hybrid
a. with standard BI-FET
Figure 8. These Inverters· have bias current and offset voltage of LM11 along with speed of the FET op amps. Open
loop gain Is about 140 dB and settling time to 1 mY about 8 jIos. Excess overload-recovery delay can be
eliminated by directly coupling the FET amplifier to summing node.
505
~
~
c(
,---------------------------------------------------------------------------------,
A voltage-follower connection is given in Figure 9. The coupling circuitry is similar, except that. A5 was addEld to eliminate glitches in sleW. Overload involves driving the fast amplifier outside its common-mode range and should be avoided by limiting the input. Thus, AC coupling the fast amplifier
is less a problem. But the repetition frequency of the input
signal must also be limited to 10kHz for ± 10V swing. Higher frequencies produce a DC error, believed to resulUrom
r!ilctification of the input sign~1I by the voltage sensitive input
capacitance of the FET amplifier u~d. A fast bipolar amplifer like the LM 118 should work out better in thi~, respect. To
avoid confusion, it should be emphasized that this problem
is related to repetiti,on frequency rather than rise time.
input terminals. However, when the inputs are shorted, the
output state is indeterminate 'because of offset voltage.
Adding degeneration"as shown in Figure 11 takes care of
this problem. Here, A2 is tne feedback resistor for the most
sensitive range, while A1 is chosen to get the metet deflectic;>n out of the noise with, a shorted input. Adding the range
resistor, as shown, does not affect the degeneration, so that
there is minimal drop across the input for full-scale an an
ranges.
R4
1l1li
Rl
2k
CNPUT ....iV\jIlor-+---+-=!
AI
10k
INPUT~""~"""""",,;~
CI
5CIIpF
OUTPUT
C2
CI
3,F
O.OZjlf
TUHI7479-12
DI
Figure 10. This 100X amplifier has small a"d large signal
bandwidth of 1 MHz. The LM11 greatly reduce. offset voltag~, bias cUmlnt and gain error.
Eliminating long recovery delay for greater
than 100% overload requires direct coupling
of A2 to Input.
IN457
RANGE
R2
TL/H17479-11
Figure 9. Follower has 10 p.s settling to 1 mY, but signal
repetition frequency should not exceed 10
kHz if the FET alTlpllfler is AC coupled t,o Input.
The cirCUit does not behave well if commonmode range is exceeded.
A precision DC amplifier with a 100 MHz gain-bandwidth
product is shown in Figure 10. It has reasonable recovery
(-7 ,""s) from a 100% overload; but beyond that, AC coupling to the fast amplifier causes problems. Alone, the gain
error and thermal feedback of the LHOO32 are about 20 mV,
input referred, for ± 10V output swing. Adding the LM11 reduces this to microvolts.
AI
INPUT - -.....I\J'\I\o,............
y+
TUHI7479-13
picoammeter
Ideally, an ammeter should read zero with no input current
and have no voltage drop across its inputs even with fullscale deflection. Neither should spurious indications nor inaccuracy result from connecting it to a low impedance.
Meeting all these requirements calls for a DC amplifier, and
one in which both bias current and offset voltage are controlled.
The summing amplifier connection is best for measuring
current, because it minimizes the voltage drop across the
Figure 11. An ammeter that has constant voltage drop
across Its input at full-scale, no matter what
the range. It can have a rea80nably-behaved
output even with shorted Inputs, yet a maximum drop of ten times the op amp noise voltage.
506
r--------------------------------------------------------------------..
The complete meter circuit in Figure 12 uses a different
scheme. A floating supply is available so that the power
ground and the signal ground can be separated with R12. At
full-scale. the meter current plus the measured current flow
through this resistor. establishing the degeneration. This
method has the advantage of allowing even-value range resistors on 'the lower ranges but increases degeneration as
the measured current approaches the meter current.
Bias-current compensation is used to increase the meter
sensitivity so there are two zeroing adjustments; current balancing. that is best done on the most sensitive range where
it is needed. and voltage balancing that should be done with
the inputs shorted on a range below 100 p.A. where the
degeneration is minimal.
With separate grounds. error could be made dependent on
offset current. This would eliminate bias-current compensation at the expense of more complicated range switching.
The op amp input has internal. back-to-back diodes across
it. so R6 is added to limit current with overloads. This type of
protection does not affect operation and is recommended
whenever more than 10 mA is available to the inputs. The
output buffers are added so that input overloads cannot
drag down the op amp output on the least-sensitive range.
giving a false meter indication. These would not be required
if the maximum input current did not approach the output
current limit of the op amp.
332
3.3Zk
3Uk
v+
33Zk
HI
ZOk
Z.3Zk
1M
111M
100M
lG
lk
H5
lG
v+
R6
10k
INPUTt
03x
RIZ
0.8
DZ
D3
lN07
1.67
TUH17479-14
Flgur.12. Current meter ranges from 100 pA to 3 mA, full-scale. Voltage across Input Is 100 p.V at lower ranges rising
to 3 mV at 3 mA. Buffers on op amp are to remove ambiguity with high-current overload. Output can also
drive DVM or DPM.
507
...f
N
millivoltmeter
R3
An idea] voltmeter has requirements analogous to those discussedf6r the ammeter, and Figure 13 shows a circuit that
will satisfy them. III the, most-sensitive position, the range
resistor is zero and the input resistance equals R1. As voltage measurement is desensitized by increasing the range
resistor, the input resistance is also increased, giving the
maximum input resistance consistent with zero stability with
the input 'open. Thus, aHull-scale, the 'source will be loaded
by whatever multiple of the noise current is required to give
the desired open-input zero stability.
INPUT--...- -......- -...
RI
This technique is incorporated into' the voltmeter circuit in
Figure 14 to give a 100 MO input resistance on the 1 mV
scale rising to 300 GO on the 3V scale. The separation of
power and signal grounds has been used here to simplify
bias-current compensation. Otherwise, a separate op amp
would be required to bootstrap the compensation to the input.
RANGE
TUH17479-15
Figure 13. This voltmeter has constant full-scale loading Independent of range. This can be only
ten times the noise current, yet the output
will be reasonably behaved for open Input.
Rl
lOk
.....--.,
y+---~
RI6
Uk
T
Bl
9V
I
...L
01
lM385
l.lY
RI7
Uk
M (
~ATTERIES..L~IA,
NOK
y+
VBAl
R7
100M
T O~OFF
H20
T
B2
I
R16
lk
BV
_1V-
Rll
l~
3x
'I x scale callbrale
Rll
1.17
1,%
ttincludes reversing switch
0
1•
RIO
R9
750
1%
RI
75
1%
t3 x scale calibrate
SCALE
Uk
1%
01
lN451
R14*
15k
Rlst
1.25k
RANGE
ImY
10mV
100mV
IV
TUHI7479-18
Figure 14. High input Impedance millivoltmeter. Input current is proportional to input voltage, about 10 pA at full-scale_
Reference could be used to make direct reading linear ohmmeter.
508
current sources
The input resistor, R6, serves two functions. First, it protects
the op amp input in the event of overload. Second, it insures
that an overload will not give a false meter indication until it
exceeds a couple hundred volts.
The classical op amp circuit for vOltage-to-current conversion is shown in Figure 15. It is presented here because the
output resistance is determined by both the matching and
the value of the feedback resistors. With the LM 11, these
resistors can be raised while preserving DC stability.
Since the reference is bootstrapped to the input, this circuit
is easily converted into a linear, direct-reading ohmmeter. A
resistor from the top of 01 to the input establishes the measurement current so that the voltage drop is proportional to
the resistance connected across the input.
RI
While the circuit in Figure 15 can provide bipolar operation,
better performance can be obtained with fewer problems if
a unipolar output is acceptable. A complete, battery-powered current source suitable for laboratory use is given in
Agure 16 to illustrate this approach. The op amp regulates
the voltage across the range resistors at a level determined
by the voltage on the arm of the calibrated potentiometer,
R3. The voltage on the range resistors is established by the
current through 02 and 03, which is delivered to the output.
The reference diode, 01, determines basic accuracy. 01 is
included to insure that the LM11 inputs are kept within the
common-mode range with diminishing battery voltage. A
light-emitting diode, 02, is used to indicate output saturation. However, this indication cannot be relied upon for output-current settings below about 20 nA unless the value of
R6 is increased. The reason is that very low currents can be
supplied to the range resistors through R6 without developing enough voltage drop to turn on the diode.
R2
10M
20M
1%
'"
Rl
= R3;R2 = R4
I
_ R2VIN
oUT - Rl R5
R5
2K
'"
If the LED illuminates with the output open, there is sufficient battery voltage to operate the circuit. But a battery-test
switch is also provided. It is connected to the base of the op
amp output stage and forces the output toward V+.
TL/HI7479-17
Figure 15. Output resistance of this voltage/current
converter depends both on high value feedback resistors and their matching.
ON/OFF
REVERSE
,TEST
LBATTERY
R&
IOIlM
CI
100 pF
BI -
BV
(>SAV)
I
I
R4
B.lk
R8
100
t-________~~__-----t~~'''~--~~R-A~NG-E_o'omA
R9
Ik
1%
ImA
R5
RI4
1.5k
·calibrate range
100M
1%
L..#.v,...--o
tselect for lcao ,;; 100 pA
IOnA
TUH17479-18
Figure 16. Precision current source has 10 nA to 10 mA ranges with output compliance of 30V to -5V. Output current
is fully adjustable on each range with a calibrated, ten-turn potentiometer. Error light indicates output
saturation.
509
Bias current compensation is not used because low-range
,1!.C3Curacy is limited .I;IY the leakage cllrrents of 02 and 03.
As it is, these parts must be s~lected for low leakage. This
,should not be difficult because the leakage specified is determined by t!lSt equipment rather than device chantcteristics. It should be noted in making substitutions that 02 was
selected for low pinch-off voltage and that 03 may havet9
dissiPate 300 mWon the high-current range. Hea~ing Q3 :on
the high range could increase leakage to where the circuit
will not function for while when switched to tlie low range.
light meter
This logging circuit is 'adapted to a battery-poWered light
meter in Figure f8. An LMiO, combined op amp'and reference, is used for the second amplifier anti to provide the
regulated voltage for ~ffsettingthelogging circuit and powlIring the 'bias current compensation; Since a meter is the
output indicator, there is no need ,to optimize frequency
compensation. Low-cost single transistors are used for logging since the temperature range is,,limited. The meter is
protected from overloads by clamp diodes 02 and 03.
Silicon photodiodes are mO,re sensitive to infrared than visible light, so an appropriate ,finer must be used for photography. Altemately, gallium-arsenide-phosphide diodes with
suppressed IR resPonse are becoming 'Ilvliilable.
a
logarithmic converter
A logarithmic amplifier that can operate over an eight-decade range is shown in Figure 17. Naturally,'bias current
compensation must be used to pick up the low' end of this
range. Leakage of the logging transistors Is not a problem
as long as 01A Is operated at. ,zero collector-base voltage.
In the worst case, this may require balancing the offset voltage of A 1. Non-standard frequency compensation is used
on A 1 to obtain fairly uniform response time, at least at the
high end of the range. The low end might be improved by
optimizing C1. Otherwise, the circuit is standard:
differential amplifiers
Many instrumentation appliCations require the measurements of low-level signals in the presence of considerable
ground noise. This can be accomplished with a differential
amplifier becauSe it responds to the voltage between the
inputs and rejects Signals between the inputs and ground.
C2
470pF
.,"
--
l1V,
,
RI1
I.m
'"
813
l40k
'"
liN
A8
~--~~--~~
lUk
10pA-l rnA
'"
YOUT '
A5
2k
330 ppmrC. Type 0209
available from Tel Labs, Inc.,
Manchester, N.H.
T
--
a.
C3
IL01
/AF
--
= 1000nA
= 100 p.A
4V at liN = 10 pA
set RII for VOUT - 0 at liN
b. set RS for VOUT =, 3Vat liN
c.
set R3 for Vour =
, Tl/Hn479-19
Figure 17. Unusual frequency compensation gives this logarithmic converter a 100 p.allme constant ,from 1 mA down
to 100 nA, Increasing from 200 fJo8 to ZOO ms from 10 nA to 10 pA. C»tlcmal bias current compensation can
give 10 pA resolution from -55"C to + 100"C. Scale factor Is 1V/decade and tamperature ~pensatad.
,
.,'
,~
,
.
510
C2
O.OO22IJF
RI4
12k
R6
Uk
R9
":'
91
Rill
1M
R1
OJ
180
RZ
30k
ZN4250
v--,.,.".,......- ...
RI1
RI6*"
3.6k
150
R15*
5.6k
0-100pA
VI
VI
• Ml
.. Ml
03
IN451
-
O@I'N - 100 nA
-0.24V@I'N - 10 pA
O@I'N - 10pA
f .•. @I'N - 1 mA
TUHI7479-20
Figure 18. Light meter has eight-decade range. Bias current compensation can give input current resolution of better
than ±2 pA over 15"C to 55"C.
&1
Figu/'8 19 shows the classic op amp differential amplifier
connection. It is not widely used because the input resistance is much lower than alternate methods. But when the
input common-mode voltage exceeds the supply voltage for
the op amp, this cannot be avoided. At least with the LM11,
large feedback resistors can be used to reduce loading
without affecting DC accuracy. The impedances looking into
the two inputs are not always the same. The values given
equalize them for common-mode signals because they are
usually larger. With single-ended inputs, the input resistance
on the inverting input is R1, while that on the non-inverting
input is the sum of R2, R4 and R5.
Provision is made to trim the circuit for maximum DC and AC
common-mode rejection. This is advised because well
matched high-value resistors are hard to come by and because unbalanced stray capaCitances can cause severe deterioration of AC rejection with such large values. Particular
attention should be paid to resistor tracking over temperature as this is more of a problem with high-value resistors. If
higher gain or gain trim is required, R6 and R7 can be added.
5pf
Vs -
±15V
RS
Ik
1%
4._
R3
Rl
111M
11\
INPIITS
±2IDVMAX
1-+-~I\r-"'--1~"'"
'"
R1
11k
"'
OUTPUT
RZ
llJGM
"'&N
10pF
A _~(A6+A7)
V AI
A6
Rst
&&
ttrim for DC CMAA
*trim for AC CMAA
TUH/7479-21
Figure 19. This differential amplifier handles high Input
voltages. Resistor mismatches and stray capacitances should be bslanced out for best
common-mode rejection.
511
~ ~------------------------------------------------------------------------------------~
i
The simplest connection for making a high-input-impedance
differential amplifier using op amps is shown in Figure 20. Its
main disadvantage is that the common-mode signal on the
inverting input is delayed by the response of A1 before being delivered to A2. for cancellation. A selected capacitor
across R1 will compensate for this, but AC common-mode
rejection will deteriorate as tlie characteristics of A 1 vary
with temperature.
R5"
Uk
1%
Rl'
1M
'"
R2
••",
,.PUTS
I.
R3
R4
1%
1M
1%
When slowly varying differential Signals are of interest, the
response of A2 can be rolled off with C2 to reduce the sensitivity of the circuit to high frequency common-mode signals. If Single-resistor gain setting is desired, R5 can be added. Otherwise, it is unnecessary.
A fUll-blown differential amplifier with extremely high input
impedance is shown in Figure 21. Gain is fixed at 1000, but
it can be varied with R10. Differential offset balancing is
prOvided, on both input amplifiers by R18.
The AG. common-mode rejection is dependent on how well
the frequency characteristics of A2 and A3 match. This is a
far bette, situation than encountered with the previous circuit. When AC rejection must be optimized, amplifier differences as well as the effects of unbalanced stray capacitances can be compensated for with a capacitor across R13
or R14, depending on which side is slower. Alternately, C1
can tie added to control the differential bandwidth and make
AC common-mode rejection less dependent on amplifier
matching. The value shown gives approximately 100 Hz differential bandwidth, although it will vary with gain setting.
, A separate amplifier is used to drive the shields of the input
cables. This reduces cable leakage currents and spurious
signals g!lnerated from cable flexing. It may also be required
to neutralize cable capaCitance. Even short cables can attenuate low-frequency signals with high enough source resistance. Another balance potentiometer, RB, is included so
that resistor mismatches in the drive to the bootstrapping
amplifier can be neutralized. Adding the bootstrapping am,plifier also provides a, connection pOint, as shown, for biascurrent compensation if the ultimate in performance is required.
12'" 10Hz
'gain set
ttrim for DC CMRR
TL/HI7479-22
Figure 20. Two-op-amp Instrumentation amplifier has
poor AC common-mode reJection. This can
be Improved at the expense of differential
bandwidth with C2.'
R13
I.
1%
R15
1l1li.
.%
c.
INPUTS
0.8'' ' ,
R14
1ft
.%
tt9Ufl'8nt zero
tvaltage balance
·gain
tDCCMRF!
"ACCMRR
TLlH,17479,-23
Figure 21. Hig,h gain differential Instrumentation amplifier Includes Input guarding, cable, bootatrapplng and bias cu~
, rent compensation. Differential bandwidth Is reduced by C1 which also makes common-mode rejection less
dependent on matching of Input amplifiers.
512
r--------------------------------------------------------------------.~
As can be seen in Figure 22, connecting the input amplifiers
as followers simplifies the circui~ considerably. But single
resistor gain control is no longer available and maximum
bandwidth is less with all the gain developed by A3. Resistor
matching is more critical for a given common-mode rejection, but AC matching of the input amplifier is less a problem. Another method of trimming AC common-mode rejection is shown here.
:r:
Cl'
~
N
INPUT ...IIN\r-"'~
OUTPUT
Integrator reset
When pursuing the ultimate in performance with the LMll, it
becomes evident that components other than the op amp
can limit performance. This can be the case when semiconductor switches are used. Their leakage easily exceeds the
bias current when elevated temperatures are involved.
Rl
2k
The integrator with electrical reset in Figure 23 gives a solution to this problem. Two switches in series are used to
shunt the integrating capacitor. In tlie off state, one switch,
Q2, disconnects the output while the other, Ql, isolates. the
leakage of the first. This leakage is absorbed by R3. Only
the op amp offset appears across the junctions of Ql, so'its
leakage is reduced by two orders of magnitude.
A junction FET could be used for Ql but not for Q2 because
there is no equivalent to the,enhancement mode MOSFET.
The gate of a JFET must be reverse biased to turn it off and
leakage on its output cannot be avoided.
MOS switches with gate-protection diodes are preferred in
production situations as they are less sensitive to damage
from static charges in handling. If used, 01 and R2 should
be inlcuded to remove bias from the internal protection diode when the switch is off.
'polystyrene recommended
.....--4~RESET
trequired il protected-
gate switch is used
TL/H17479-25
Figure 23. Reset Is provided for this Inegrator and
switch leakage Is isolated from the summing
Junction. Greater precision can be provided if
blas-current compensation Is Included.
Rl
R2
1011
1M
"'
1"
INPUT
OUTPUT
+
Cl
10pF
Rl - R3; R2 - R4
--
R2
AV-ii1
ttrim for DC CMRR
*set for AC CMRR
TUH17479-24
Figure 22. For moderate-gain Instrumentation amplifiers, input amplifiers can be connected as followers. This simplifies circuitry, but A3 must also have low drfft.
513
peak detector
The peak detector in Figure,24 expands upon this idea. Isolation is used on both the peak-detecting diode and the reset switch. This particular circuit is designed for a long hold
interval so acquisition is not quick. As might be expected
from an examination of the figure, frequency compensation
of an op amp peak deteC!0r is not exactly straightforward.
oven controller
The LM11 is quite useful with slow servo systems because
impedance levels can be raised to where reasonable capacitor values can be used to effect loop stabilization without
affecting accuracty. An example of this is shown in Figure
25. This is a true proportional controller for a cryStal oven.
RI
ZOIc
01
IN914
CZ
SOpF
OUTPUT
INPUT
300 ,.. min single pulse
200 ,.s min repetitive pulse
300 Hz max sine wave error
<
5 mV
RESET_......-.......
trequlred If QI has gateprotec1lon diode
'polystyrene or Teilon
TLlH/7479-ZO
Figure 24. A peak detector designed for extended hold. Leakage currents of peak-detecting diodes and reset switch
are absorbed before reaching storage capaCitor.
IIV .. v+ .. 2OV
SI*
LM335Z
R4
22M
RS
RZ
120.
,%
22M
01
LM331
Z.SV
R3
20.
,TEMP
SET (IS·C)
--
'solid tantalum
tmylar
TLlHI7478-27
*close thermal coupling between sensor and oven shell Is recommended.
FIGURE 25. Proportional control crystal oven heater uses lead/Jag compensation for fast settling. Time constant Is
changed with R4 and compensating resistor RS. If Q2 Is inside oven, a regulated supply Is recommended
for O.1·C control.
514
Temperature sensing is done with a bridge, one leg of which
is formed by an IC temperature sensor, S1, and a reference
diode, 01. Frequency stabilization is done with C2 providing
a lag that is finally broken out by C1. If the control transistor,
02, is put inside the oven for maximum heating efficiency,
some level of regulation is suggested for the heater supply
when precise control is required. With 02 in the oven, abrupt supply changes will alter heating, which must be compensated for by the loop. This takes time, causing a small
temperature transient.
Because the input bias current of the LM11 does not increase with temperature, it can be installed inside the oven
for best performance. In fact, when an oven is available in a
pieca of equipment, it would be a good idea to put all critical
LM11s inside the oven if the temperature is lesS than 100"C.
this increases the ouput offset because the op amp offset
voltage is multiplied by the resistance boost.
But when conventional resistor values are used, it is practical to include R5 to eliminate bias-current error. This gives
less output offset than if a single, large resistor were used.
C1 is included to reduce noise.
standard cell butter
The accuracy and lifetime of a standard cell deteriorate with
loading. Further, with even a moderate load transient, recovery is measured in minutes, hours or even days. The
circuit in Figure 27 not only buffers the standard cell but also
disconnects it in the event of malfunction.
The fault threshold is determined by the gate tum-on voltage of. 01. As the voltage on the gate approaches the
threshold either because of low battery voltage or excessive
output loading, the MOS switch will begin to tum off. At the'
tum' off threshold, the output voltage can rise because of
amplifier bias current flowing through the increasing switch
resistance. Therefore, a LED indicator is included that extin-
ac amplifier
FlfJure 26 shows an op amp used as an AC amplifier. It is
unusual in that DC bootstrapping is used to obtain high input
resistance without requiring high-value resistors. In theory,
OUTPUT
R4 •
182k
1%
R2) A _ R2 + RS + R4
RIN=Rl ( 1+Fi3; vR2+R3
--
TLlH/7479-28
Figure 26. A high Input Impedance AC amplifier for a piezoelectric transducer. Input resistance of 860 MO and gain of
10 Is obtained.
r---~--"------~-------1~--~--~+
Rl
+
STANDARD
CELL
OUTPUT
R2
42.2k
+
T
I
Cl
II'F L..._';;;;;;"
Bl
BV
...!....
R3
3.6k
R4
Zk
TLlHI7479-29
'cannot have gate protection diode; VTH > VOUT
Figure 27. Battery powered buffer amplifier for standard cell has negligible loading and disconnects cell for low
supply voltage or overload on output. Indicator diode extinguishes as disconnect circuitry Is activated.
515
~ ~--~----------------------------------------------------------------------~
;
guishes as the fault condition is· approach9d. The MOS
An assortment of measurement and computational circuits
making use of the unique capabilities of this IC were preZ
threshold should be higher than the buffer output so that he
CC
disconnect and error indicator operates· before the output· sented. These circuits have been checked out and the resaturates.
sults should be of some value to those working· with high .
impedances. These applications are by no meims ali-incluconclusloiis
sive, but they do show that an amplifier with low input cur. Although the LM11 does not provide the ultimate in perrent can be used in a wide variety of circuits.
formance in either offset voltage or bias current for nominal
Although· emphasis was oli high-performance circuits ·requirroom temperature applications, the combination offered is
ing adjustments, the LM11 will see widest usage in less detruly noteworthy. With significant temperature excursions,
manding applications where its low initial offset votlage and
the results presented here are much more impressive. With
bias current 'Can eliminate adjustments.
full-temperature-range operation, this device does represent
the state of the art when high-impedance circuitry is. inacknowledgement
volved.
The authors would like to thank Dick Wong for his assistCombining this new amplifier with fast op amps to obtain the
best features of both is also interesting, particularly' since
the composite .works well in both the inverting and non-inverting modes. However, making I:tigh-impedance circuits
fast is no simple task. If higher temperatures are not involved, using the LM 11 to reduce the offset voltage of a
FET op amp without Significantly increasing bias current
may be all that is required.
ance in building and checking out the applications described
here.
*See AddendurrI that follows
this Application Note.
516
National Semiconductor
Technical Paper 15
Reducing DC Errors
inOpAmps
Robert J. Widlar
Apartado Postal 541
Puerto Vallarta, Jalisco
Mexico
Abstract. An IC op amp design that reduces bias currents
below 100 pA over a -SS"C to + 12S"C tempersture rsnge
is discussed. Super-gain bipolar trsnsistors with on-wafer
trimming are used, providing low offset voltage and drift.
The key to low bias current is the control of high tempersture leakage currents along with the development of reasonably accurste nanoampere current sources with low parasitic capaCitance.
Introduction
A bipolar replacement for the LM108 (1) drastically reduces
offset voltage, bias current and temperature drift. This design, the LM11, does not depend on new technology. Instead, the improvements result from a better understanding
of tranSistor behavior, new circuit techniques and the application of proven offset trimming methods. Table I summarizes the results obtained. The combination of low offset
voltage and low bias current is unique to IC op amps, while
the performance at elevated temperatures represents an
advance in the state of the art.
TABLE I. Input error terms of the LM11 show an Improvement over FET op amps even at room temperature. There Is little degradation In performance from
-55"C to 125"C. Other Important speclflcetlons are
somewhat better than LM108A.
Parameter
Input Offset Voltage
Input Offset Current
Input Bias Current
Offset Voltage prift
Offset Current Drift
Bias Current Drift
TJ = 25"C
-55"C:S:TJ
:s: +125"C
Units
Typ
Max
Max
0.1
0.5
25
1
20
0.5
0.3
10
50
0.6
30
150
3
",V/"C
0.5
fAloC
pArC
mV
pA
pA
does with bipolars. FETs are also sensitive to mechanical
strains and subject to offset shifts during assembly or with
temperature cycling.
Typically, long term stability is about 100 ",V/year, although
this can go to 1 mVIyear with no prior warning in early life.
This contrasts to a 10 P. VIyear long term stability for bipolar
pairs.
Lastly, although the input current of FETs is low at room
temperature, it doubles for every ,1 O"C increase. This, coupled with high offset voltage drift, makes FETs much less
attractive as operating temperature is increased.
MOSFETs
Field effect transistors, with a metal gate and oxide insulation, give the ultimate in low input current. Practically, this
advantage disappears when diodes are included to protect
the gate from static charges encountered' in normal handling. Further, the offset voltage problems of JFETs go double for MaS FETs. They are also subject to offset shifts due
to contamination.
Interesting designs are on the horizon for various chopperstabilized complementary MaS ICs. These solve most offset voltage problems, but not that of input leakage current.
Even at moderate temperatures, this input current will seriously degrade the low offset voltage and drift even with relatively low source resistances. Chopper-stabilized amplifiers
have added problems with overload recovery and noise, especially with high source impedances. These problems have
limited solutions, but chopper stabilization is not usually suitable for general purpose applications.
bipolar op amps
Offset voltage, its drift or long term stability has not been a
serious problem with bipolar-input op amps. Such techniques as cross-coupling or zener-zap trimming have reduced offset voltage to 25 p.V in production. The real problem has been bias current. The LM108, introduced in 1968,
has represented the, state of the art in low bias currents for
standard bipolar devices. At 3 nA, maximum over temperature, the bias current is lower than FETs above 85"C.
Junction FETs
At first glarice, field effect tranSistors seem to be the ideal
,input stage for an op amp, mainly because they have a low
gate current, independent of their operating current. Practically, they do provide an attractive combination of performance characteristics in a relatively simple deSign. But there
are serious shortcomings.
A Dariington version of the LM108, the LM216, provided
bias currents in the 50 pA range; bilt this design was seriously marred by high offset voltage, drift, excessive low frequency noise and anomalous leakage currents at higher
temperatures.
Improvements in this design were thwarted by the inability
to provide nanoampere bleed currents to stabilize the Darlington input and the erroneous belief that uncontrollable
surface states created the anomalous leakage.
For one, FETs do not match as well as bipolar devices: the
offset voltage is at least an order of magnitude worse. Laser
trimming can compensate for this to some extent. But with
FETs, low offset voltage does not guarantee low drift, as it
517
N
~
~
...,..
~
~o
...
,
~
C
j
r-----------------------------------------------------------------------------,
,'a~ew deSign
a nanoampere current source
,
50'
A circuit that generatEis the
nA bieed current is shown in
Figure 2. A super-gain transistor ope~a:ted in the forward
mode is used to bias a standard' transistor in the reverse
mode. The reverse connection is used because the capacitance of an ordinary collector tub would reduce the common-mode slew rate from 2 VI p.s t6 0.02 VI p.s. '
"With bipolar transistors, there is a tradeoff between current
gain' and preakdown voltage. Super-gain transistors are de, ,viCes that have been diffused for maximum current gain at
the expense of breakdown voltage (which is typically a couple volts for a current gain of 5000). These low voltage transistors can be operated in a cascade connection with standard transistors to give a compOSite device with both high
gain and breakdown voltage.
III
+'O"A
Figure 1 shows a modified Darlington input stage for a super-gain op amp. Common base standard transistors (05
, and 06, drawn with a wider base) are bootstrapped to the
super-gain input transistors so that the latter'are operated at
near zero collector base voltage. In addition to permitting
the use of super-gain Inputs, this connection also isolates
the input transistors from common-mode variations, increasing common-mode ~liIjection.
_ - -...---t.....--v+
HZ
TUH/8722-2
ZIk
Figure 2. Forming a nanoampere current source' with
low parasitic capaCitance. Design takes advantage of predictable VSE difference betwee,n atandard:' and super-gain trenslators
and"fact that VBE of' a translator la the same
when operated In forward or reverse mode.
..--II---} OUT~UT
,At first look; this biasing scheme would seem 'to be subject
, to ~, number of process vanattanl!. This is not so. For one,
the Vee of a transistor d~pends on the ,bllSIl Gummel number(Qellie), the number of majority carrieI'!! per unit area
divided by their effective mobility. Since the Gumme! number and the effective area lire un~hlll)ged when thlil collector and emitter are interchanged, the VeE'WiIi be the, same in
either connection, provided ~hat base rec6mbination is not
exceS$ive. In stal'!~ard IC transistorS, reversE! hfe is about
30, indicating that recombination is not a significant factor.
Measured reverse hje is much lower, but this is th~r'esul1 of
a parasitic PNP that does not affect VeE or aE, the common
base current gain.
The bleed current depends also on the ratio of super-gain to
standard transistor hje, as indicated by the equation in Figure 2. Intuition suggests that super-gain hfe will increase
much faster than standard transistor hfe with increaSing
emitter diffl!sion time, giving lower ~Ieed current with higher
Super-gain hfe. However, measurements with. vllriances of
standard LM 108 processing indicate that' tl'\e' bleed current
,
'remains within 25% of design center. '
INPUT{~
,
zapA
,-";---+-1
..........-v-,
TLlH/8722-1
As shown in Figure 2, higher cu~rent ratios can bEl obtained
Figure 1. Bootstrapped Input stage using super-galn
transistors In modified-Darlington connection.
The objectionable characteristics of the Darlington are virtually eliminated by, operating
tile Input transistors at a much larger current
than 'he base 'current of the transistors ,they
are drlvln$ll"
by increasing the area of 01 relative to 02 ,or. by including
R1. The equation in Figure 2 assumes that I, varies' as absolute temperature. If thevolll\ge drop.acr9ss ,R1 is equal to
kT/q, ,changes in the VeE of 01 withsmall.changes in I,will
be cancelled by changes, in the voltage' drQP across R1.
This 'makes input bias current essentially unaff~cted by variations in supply or common-mode voltage' as. lorig as I, is
'
reasonably well controlled.
The usual problems with the Darlington connection are
avoided by providing a blelld current that operates t~ input
transistors. 01 and 02, lit, a current much higher than the
base current of the transistors they are driving, 03 and 04.
This is necessary 'because, the base currel!ts are ROt that
well matched, especially over temperature, and have excess low frequency noise.
518
junction capacitances on low current nodes under transient
conditions. This minimizes recovery delays.
leakage currents
The input leakage currents of bipolar op amps can be kept
under control because small geometry devices are satisfactory and because the collector-base junction can be operated at an arbitrarily low voltage if bootstrapping is used.
The clamp circuitry is shown in Figure 5. Emitters are added
on the input transistors and cross-coupled to limit the differential input voltage. Another transistor, 05, has been added
to limit voltage on the input transistors if the inputs are driven belowV-.
Simple theory predicts that bulk leakage saturates for reverse biases above 2kT/q. But generation in the depletion
zone dominates below 125°C. Because the depletion width
varies with reverse bias, so does leakage. The characteristics of a high quality junction plotted in Figure 3 show that
leakage current can be reduced with lower bias.
OUTPUT
Ik
TJ= 125°C
C
.9
Iii
...
.....'"
.......'"
II:
II:
V
100
c
c
/
10
10
100
TUH/8722-5
REVERSE VOLTAGE IV)
Figure 5. Separate clamps are used for differential and
common-mode overloads_ Leakage currents,
ICES of forward and reverse connected transistors, cancel.
TLlH/8722-3
Figure 3. Voltage sensitivity of collector base leakage
Indicates that generation in the depletion zone
dominates even at 125"C.
The differential clamp transitors do contribute to input current because Vca > 0, so collector current is not zero for
VBE "" 0 (ICES'" 100 pA at 125°C). The common-mode
input clamp, 05, is also operated at VeE = 0 and VCB > 0,
although in the inverted mode. The resulting error is diffusion current, dependent only on the characteristic VBE of
the transistors. Thus, the current contributed by the differential clamp transistors is cancelled, within a couple percent,
by that from the common-mode clamp.
When more than one junction is involved, minimum leakage
is not necessarily obtained for zero bias. This is illustrated in
Figure 4. a plot of ICBO for a junction isolated NPN transistor. A parasitic PNP is formed between the base and the
isolation as diagrammed in the inset. Zero leakage is obtained when VCB is set so that the PNP diffusion current
equals ICBO of the NPN.
Ik ~~~~~~=====F.~
bias current
C
IUU
Figure 6 shows some results of the design approach described here. A room temperature bias current of 25 pA is
obtained, and this his held to 60 pA over a -55°C to 125°C
temperature range. The figure also shows the results of
.9
...
Iii
....'"
II:
II:
10
-
811
:l
C
80
. ".. -.:'!- ~ t:::,
...
...
...
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:l
iii
......
.9
0.1
o
0.1
D.2
D.3
OA
40
,LMI1
II:
II:
0.&
COLLECTOR·BASE VOLTAGE (VI
TL/H/8722-4
Figure 4. Plot above explains "anomalous" leakage of
NPN transistors in ICe. As collector base bias
Is reduced, base current reverses then increases exponentially. This excess current Is
the forward diffusion current of parasitic PNP
to substrata (see Inset).
.
'"
!!
20
0148
-20
--40
-50
50
1\
100
ISO
TEMPERATURE (OCI
TLlH/8722-8
Input protection
Figure 6. Input bias current of the LM11 remains low
over military temperature range. Improvements In development give even beHer results
(074B). Offset current Is usually below 1 pA.
The input clamps perform a dual function. Most important,
they protect the emitter base junction of the input transistors
from damage by in-circuit overloads or static charges in
handling. Secondly. they limit the voltage change across
519
Some Improvements in development that have reduced'bias
current to 20 pACiver the full operating temperature range.
when operating from higher source resistances, op amp
noillS'is obSCIJred by resistor noise, as, shown in F"1fJl!re B.
Low frequency' noise is not" as 'easilyaccolmted for as
broadband 'noise, but, lower operating currents inorease
noise in much the same fashion. The low frequency noise of
the LM11, shown in Figure 9, is a bit less than FETs but
greater than, that ,of the LM108 when it is operated from
source resistances less than 500 kO.
Figure 6 shows that bias current is very neatly a linear func:.
tion of temperature, at least from - 55"C to + 1OO"C. This,
coupled with the fact that bias current.is Virtually unaffected
by'changes in common-mode or supply voltage; suggests
that bias current compensation can be provided, for critical
applications. An appropriate circuit is shown in Figure 7. Details are given in reference [2], but properly set up it should
be possible to hold bias currents to less than 20 pA over a
- 5,5°C to + 1000C temperature range or 5 pA over a 15°C
to 55"C range with' a simple room temperature adjustment.
>
;;
'20 ...-............."""T--.r-T"""-r--r---.
'MAX = 1 Hz
H, = 100 kn
TJ=Z5°C
+--+-I-+--+-f
101--'-t--I'-+-+-t-+-+--t
co
15V
~
co
>
AI
!..
1.5M
5
!i
A2
-10
30Ic
o
'
R4
300
400
TL/H/B722-9
Figure 9. Low frequency noise of LM11 Is high compared to other bipolar devices but somewhat
less then FETs.lt Is equal to LM108 operating
from 500 kO source resistances.
ZN2414
-
ZOO
TIME (,)
f~ ~~~. . .I-'IV\o':~,·-~:~I~G NODE
~
100
TLlH/8722-7
complete circuit
Figure 7. Bias current of LM11 varies linearly with temperature sq It can be effectively compensated
with this circuit. Bias currents less than 5 p~
over 15"C to 55"C r:ange or 20 pA over -55"C
to + 100"C are practical.
A schematic diagram of an IC op amp using the techniques
described is shown in Figure 10. Other ~han ~e input stage,
the circuitry is much like the LM112,a CQ,mpensated versi~
of the LM108 that includes ,o~t balancing.
'
One significant ohange has'been the inclusion of wafer level
trimming for offset voltage. This is done using zener'zap
trimming across portions of the input stage collector load
resistors, R4 and R5. This kind of zener is ,simply the emitter
base junction of an NPN transistor. When pulsed with a
large reverse current at wafer sort, the junction is destroyed
by the formation of a low reSistance filament between the
emitter and base contact beneath the protective oxide. This
shorts out a portion of the collector load, resistoi. The process is repeated on binary Weighted segments until the offset voltage has been minimized.
Offset voltage of the LM'11 ,is' conservatively specified at
300 p.V. Although low enough for most applicatiqns, offset
voltage trimming is, provided for fine adi,ustment. Balance
range is determined by the resistance of the balance potentiometer, varying from ±5 mVat 100 kO to ±400 p.V at
1 kO. Incidentally, when nulling offset VOltages of 300 p.V,
the thermal matching of balance-pot resistance to the internal resistors is not a 'significant factor.'
noise
The broadband noise of a bipolar transistor is given by'
en ,= kT.l2~f/qlc."
(1)
Therefore, operating the input transistOR! at low collector
current does increase noise. Because the noise of most op
amps is greater than the theoretical noise voltage of the
input transistors, the noise increase from low current input
buffers is not as great as might be expected. In addition,
lk~m
/
~MI1
The actual balancing is done on the emitters of lateral PNP
tranSistors, 09 and 010, that imbatancethe collector loads
of,the input stage. This'partlcular arrangementW&s used so
that
damage would result from accidentall:onnection of
the balance pIns to Voltages outside either supply. Not obvious is that a balance pin voltage' 15V more: negative than
V+ can effectively short these PNP transistorS with a parallel P-channel MOS transistor, forcing the output ~o onE! limit
or another..
10 '----'-..............- - ' - - -....
10k
lOOk
1M
10M
10IIII
rio
RESISTANCE (CI)
TL/H/8722-8
Figure 8. Increased noise ot LM11 Is consequence ot
, low collector current In Input trenslstors. But
In' high Impedance applications, op amp nOise
Is maiked by the thermal nOise ot souree reslstanee given above.
520
~
__
~~
__
~
________________
COMPEMSATION CLAMP
~
______
~5~-.
____- .____
~--
______
~
____
~
__
~7 ~
01
45
'--__+-__,.::.5 OUTPUT
R12
R14
'--____~--~--------4_~~5-~---7-00_+----_+--------~----4
~
TL/H/B722-10
Figure 10. Complete schematic of the LM11. Except for the Input stage, circuit Is much like the LMl12, a compensated version ·of the LM108 that Includes offset balancing.
Although the LMll is specified to a lower voltage than the
LM1OS, the minimum common·mode voltage is a diode drop
further from V- becau~ the bleed current generator, Q12
and Q13, has been added.
The output stage is a complementary class-B design with
current Iimiting"Biasing has been altered so that the guaran·
teed .output current is twice the LM10a. A zener diode, 01,
limits output voltage swing to prevent stressing the MOS
capacitor to the point of catastrophiC failure in the event of
gross supply transients.
Proceeding from the input stage, the second stage amplifier
is a differential pair of lateral PNPs, Q7 and Qa. These feed
a current mirror, Q25 and Q26, which drive a super-gain
follower, Q27. The collector base voltage of Q26 is kept
near zero by including Q2a. The current mirror is bootstrapped to the output so that second stage gain error depends only on how well Q7 and Qa match with changes in
output voltage. This gives a gain of 120 dB in a two stage
amplifier. Frequency compensation is provided by MOS capacitor C1.
The main bias current generator design (Q20-Q23) is due
to Dobkin [3]. It is powered by Q19, a collector FET. The
circuit is auto-compensated so that output current of Q14
and Q21 varies as absolute temperature and changes by
less than 1% for a 100: 1 shift in Q19 current.
521
~
~.'
~
,...
;
S
E
:s
r----------------------------------------------------------------------------,
speed
With a unity gain bandwidth of 500 kHz and a 0.3 VI p's slew '
rate the LM11 is not faSt. But it is no slower than might be
expected for a supply current of only 300 p.A.
If the precision of the LM 11 is required along with greater
speed, the circuit in Ftgure 11 might be used. Here, the
LM11 senses input voltage and makes appropriate adjustments to the balance terminals of a fast FEi amplifiet:. The
main signal path is through the fast amplifier.
conC!iusions
A, new IC op amp has been described that can not only
increase the performance of existing 'equipment but also
creates new design possibilities. Op amp error h8s been
reduced to, the point where other problems can dominate.
Many of the practical difficulties encountered in high impedance circuitry are discussed in reference (4) along with solutions. A number of tested designs using these techniques
are given in reference (2).
The LM11 is not the result of any breakthrough in processing technology. It is simply a modification of ICs that have
been in volume production for over 10 years. The improvements have resulted primarily from an understanding of
strange b9hallior observed on the earlier ICs and taking advantage of certain inherent characteristics of bipolar transistors that were not fully appreciated.
~
~
+--~--~--------~
INPUTS
OUTPUT
As users of the LM11 may have discovered, the offset voltase and bias current specifications are quite conservative. It
seems possible to offer 50 p.V offset voltage and perhaps
1 p.V1°C drift even on low cost parts. Taking full advantage
of 5 pA bias current would require guarded 10-pin T0-5
packages or 14-pin DIP packages. Further, the feasibility of
reducing low frequency noise to 2 p.V and 0.1 pA, peak to
peak, has been demonstrated on prototype parts.
acknowledgement
TL/H/8722-11
Figure 11. The LM11 can zero offaet of fast FET op amp
In eHher Inverting or non-lilvertlng configurations. Speed 18 that of fast amplifier. FEt amplifier can be capacltlvely coupled to critical
Input to, eliminate Its Iquge current.
The author would like to acknowledge the contributions of
Dennis Foltz for solving the rather formidable production
test problems of the LM11.
references
(1) R.J. Widlar, "IC op amp beats FETs on input current",
National Semiconductor AN-29, December 1969.
(2) R.J. Widlar, R. Pease and M. Yamatake, "Applying ,a
new precision op amp", National Semiconductor AN242, April 1980.
Surprisingly, this connection will work even as a voltage follower. The common-mode slew recovery of the LM11 is
about 10 p.s to 1 mY, even for 30V excursions. This was
accomplished by minimizing or bootstrapping stray capacitances and providing clamping to limit the voltage excursion
across the strays.
(3) R. Dobkin, U.S. patentno. 3930172.
(4) R.J. Widlar, "Working with high impedance op amps",
National Semiconductor AN-241" February 1980.
When bias current is an important consideration, it will be
advisable to ac couple the FET op amp to the critical input.
Reference (2) discusses this and other practical aspects of
fast operation with the LM 11.
522
Application of the ADC 121 0
CMOS AID Converter
National Semiconductor
Application Note 245
INTRODUCTION
THEORY OF OPERATION
The ADC1210 is the answer to a need for analog to digital
conversion in applications requiring low power, medium
speed, or medium to high accuracy for low cost. The versa. tile input configurations aliow many different input scale
ranges and output logic formats.
Uke most successive approximation A to D's, the ADC1210
consists of a successive approximation register (SAR), a 0
to A converter, and a comparator to test the SAR's output
against the unknown analog input. In the case of the
ADC1210, these elements are connected to allow unusual
versatility in matching performance to the user's applications.
The. SAR is a specialized shift register programmed such
that a start pulse applies a logical low to the most significant
bit (MSB) and logical highs to all other bits, thus applying a
half scale digital signal to the OAC. If the comparator finds
that the unknown analog input is below half scale, the low is
shifted to the second bit to test for quarter scale. If, on the
other hand, the comparator finds that the analog input is
above half scale, the "low" state is not only shifted to the
second bit, but also retained in the MSB, thus forming the
digital code for three quarters scale. Upon completing the
quarter (or thrae-quarter) sacle test, the next clock pulse
sets the SAR to test either Ye, %, %, or % full scale, depending on the input and the previous decisions. This suc·
cessive half-the-previous-scale approximation sequence
continues for the remaining lower order bits. The thirteenth
clock pulse shifts the test bit off the end of the working
register and into the conversion complete output. F1!JUf9 1
shows the schematic diagram of the device.
The wide supply voltage range of 5V to 15V readily adapts
the device to many applications. The very low power dissipation yields ramar:kable co~rsion linearity over the full
operating temperature range. Table I below summarizes the
typical performance of the ADC1210.
TABLE I. ADC1210 Performance Characteristics
Resolution
Unearity Error, TA = 25°C
Over Temperature
12 bits
±0.0183% FS MAX
±0.0366 % FS MAX
Full Scale Error, T A = 25D C
Zero Scale Error, T A = 25"C
0.2% FSMAX
0.2% FSMAX
Quantization Error
±1jzLSBMAX
200 p.s MAX
Conversion Time
This note expands the scope of application configurations
and techniques beyond those shown in the data sheet. The
firat section discusses the theory of operation. The remaining sections are devoted to applications that extract the optimum potential from the AOC1210.
OPERATING CONFIGURATIONS
Figures 2 through 5 show four operating configurations in
addition to those presented in the data sheet.
CUltJI ~t,
START
C"v!~SIOH
COMPLETE
GND
~ff
o!!-c
"
i:C
a"
, CMOS SAR CONTROL LOGIC
..
0"
1
a.
Do
A,
Do
o.
0,
0,
a.
...
o.
D~
l
12 MSI
1
ID
•
.L-
7
OlQITAL
OUTPUTS
•
W 70~7
,...
LSB
....
'1Ok
.OOk
lOOk
lOOk
2DOk
R·tft lADDER
.".
....
R2I
11
200k
u,
'8
it it 1
!Ok
15
2011
16
17
K
"
10k
+
23
_TOR
OUTPUT
10
vTLlH17185-1
FIGURE 1. Schematic Drawing
523
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rDCiiio
,"AoCJ211 -
~~
241
Cp
,JC
DIA AND SAR LOGIC
+
MSB
~:=
R26
2R
1"
L-
-----
R28
,/'"
R27
15
V'
.":",
2- 1
DIGITAL
OUTPUTS
'
1
COMPARATOR
OUTPUT
1
I
__ ":....J
20
.,
~lt
~
2- 12
"
,',
I. ii- 17 Ie
1!!lP2:1234 6 8 7 8 9 011 12
"
I
I
123
COMP
LSI
1
1
'I
I
~,
~
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"
20k
13 '
14,
"
"
-----------------------.
- --
I
I
I
CLOCK PULSE
START
CONVERSION
COMPLETE
,.'
~;
ANALOG
INPUT
+5V" VIEf" +15V
0" ViN" -VIIEf
LOGICAL "1" "O.5V
LOGICAL "0" .. ¥REf
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RA
2Il0l<
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,
C.
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.
lk
-=TL/HI7185-2
FIGURE 2. Complementary Logic, DV to - VREF Input
"
"
V+ (VIlEF)
4.1,5
r(~
~~m~DCim--~-------------------------1
I '
I
1
I
I
1
CLOCK PULSE
START
CONVERSION
COMPLETE
20k
241
13
"
Cp
14
CC
0.:;+---1 SC
I
DIA AND SAR LOGIC
X .
""--
MS8
'
21r, ~ ~ ~ S'~ ~'~
'111
~
R28' R26
2R
2R
R2I
111u----- '1.- ii- 17"
2- 12
V'
_
,-
I
1."15--
20
I
2- 1
NC
OIllITAL
OUTPUTS
+5V" VREI' "+15V
-IVRjFl" ViN "+IVIIEFI
LOGICA "1"" D.!iV'
LOGICAL "0" "VII£F
.....
I
, ...JI
___
R27
~
..
I
123
COMP .......
.>---t""'"'1t-"O gg~RATOR
'.'
lLSB
I
I
1- .....
R
II ":'
L.G!!!
./
I
ANALOG
INPUT
" ).
NC
R.
200k
NC
~--------~t~
0,1%
20k
0,1%'
, 100pF
~=
10k
TLlHI7185-3
FIGURE 3. Complementary Logic, Bipolar - VREF to
524
+ VREF Input
f
V+ (VwEF)
....
P,tt"
~
en
i c,m.Aoc"i1- - -- -----------------------,I
22
AO
I
I
I
CLOCK PULSE
START
CONVERSION
COMPLETE
241
13
14
20k
01 A AND SAR LOGIC
a
I
y'
Cp
It
~
R
LSI
R28
2R
"LI!!o
1-
-----
11 2 3 4 5 6 7 8 9
,
011 12
R25
2R
-
19
R2B
II
17
16
V'
15
20
4.7~
+"
2-'
Ol6lTAL
OU1PUTS
COMPARATOR
OUTPUT
I
I
___ ..JI
V
R27
J
-:2-. 2
123
COMP
+
MSI
I
I
I
I
I
-:
+5V"VREF" +15
+VIIff
LDGlCAL "I" .. VREf
LOGICAL "0" " 0.5V
o "VIfj"
ANALOG
INPUT
-:
iIA
200k
"
-IV ~
v- ~-15V
'"
Rs
lk
100pF
-=
TLlHI7185-4
FIGURE 4. PoslUve True LogiC, OV to
+ VREF Input
Y+ (YIIEF)
Ht"
+~
22
IAoCi21o. ADc12;; - - - -
I
I
I
I
CLOCK PULSE
START
CONVERSION
COMPLETE
24!
13
14
CP
It
cc
I
-----------------------~
I
I
2Dk
I
I
I
LSB
'1
R26
2R
L~
R25
2R
21 1 2 3 4 5 6 7 8 9 10 1 1 1 2 - - - - - \;9- lB
"
V'
2-12
DIGITAL
OUTPUTS
"'
R28
17
R27
NC
4.7"
+
H.
20D
':,F
-IV
+5V " v"EF" + 15V
-IVREFI " VIN " + IVRm
LOGICAL "I" .. YREF
LOGICAL "0" " 0.5Y
ANALOG
COMPARATOR
OUTPUT
\;6- ii"--- 20
NC
2-1
123
I
I
____ JI
Msa
1-
I
I
~
COMp .......
t;/"'"
XR
OIA SAR LOGIC
~
V-
0.1"
2Dk
~
-15V
C":-,'PF
INPUT
II
0.1"
28k
Hs
lk
0.1"
lDk
VREf
-=
TL/H17185-5
FIGURE 5. Positive True logic, Bipolar - VREF to
525
+ VREF Input
DESIGN CONSIDERATIONS
To Complement, or Not to Complement
Of the two recommended logic configurations, the complementary version is preferred. It provides greater accuracy'
than the straight binary version. The reason for that is that
with the complem4[lntary logic configuration, a reference
voltage is fixed at the non-inverting input of the comparator.
Consequently, the comparator operates at this fixed threshold independent of the input voltage. For the straight binary
configuration, the analog input drives the non-inverting input
of the comparator so tllat the ,common mode voltage on the
comparator input varies with the analog input. This adds a '
non-linear offset voltage of less than 1ft LSB. ,
Regardless which configuration is used, the comparator in~' ,
put common mOde range must not be exceeded. In fact; the
voltage at either comparator input must be no less than 0.5
volts from the negative supply and 2.0 volts from the paBl-,
tive supply. Therefore, for applications r&quinng common
mode range to ground, simply connect a negative supply
(-2V to -15V) to pin 20.
'
Layout CQlllllderations
Highresolutlori'D/A and AID converter circuits may have
their entire error budget blown if any digital noise is allowed
to enter the analog oircuit.
Exercising 'care' in the layout is certain 'to' minimize frustrations. Single point analog grounding is a good place to start.
All analog ground connections and supply bypassing should
,be returned to this pOint. fact, in critical applications, the
ADC1210 GND pin showld be made" "the" reference node.
Furthermore, one should separate the analog ground from
tHe digital ground. Any excursion ofswitchlng'spikes generated in the digital circuit is, to some degree, decoupled from
the analog cirquitry~ Figure 6 illustrates 'this. Of course,
these two ,p~ints !ll"e eventually tied together at the power
supply/cihassis ---+---+-----If-----iANALOG IN
21
14
T
Vee
24
CLOCK
13,
mlIf
',0
APC
lIlIO 1210
Cp
LS8
lC'
MM74C902 ".'
TLlH17185-6
FIGURE ~. Grounding ~.Ideratlons of Interf.ce Circuits'
526
The recommended technique is to apply a slight amount of
AC hysteresis (50 mV) at the beginning of the decision cycle, but let it decay away to an acceptable accuracy before
the decision is actually recorded in the SAR. The approximate decay time is (5) x (10k + 1k) x (100 pF), or 5.5 ""S
(see Figure 2).
Power Supply Bypassing
The supply input only provides power to the digital logic, it is
also a reference voltage to the resistor ladder network of
the ADC1210. This voltage must be a very stable source. A
precision reference device such as the LH0070 or LH0071
is ideal for the ADC121 O. However, the internal CMOS Successive Approximation Register (SAR) invariably generates
current spikes (10-20 mA peak) in the supply pin as the
logic circuit switches past the linear region. COnsequently, if
a reference device such as the LH0070 is used, the current
spike tends to cause excursions in the reference voltage,
thus threatening conversion accuracy. To preserve the 12bit accuracy, bypass the supply pin with a 4.7 ""F tantalum
capacitor. In high noise environments, a 22 ""F capaCitor
shunted by a 0.1 ""F ceramic disc capacitor is desirable.
For those applications using supply voltage other than 10V,
say 5V, and if 50 mV initial hysteresis is to be maintained,
the 200 kO (RA> resistor in Figure 2 should be changed to
100 kO based on the relationship:
Rs
-R
R VREF = 50mV
A
+ s
Where: Rs = 1 kO
High Speed Conversion Technique
It pin 20 is connected to a negative supply, it too should be
bypassed to prevent voltage fluctuations from affecting the
comparator operation.
By using one IC, one discrete NPN transistor, and a resistor,
the ADC1210 can be made to run at up to 500 kHz clock
frequency, or 12-bit conversion time of 26 ""s. The circuit is
shown in Figure 7. The idea is to clamp the comparator
output low until the SAR is ready to strobe in the data at the
riSing edge of the conversion clock. Comparator oscillation
is suppressed and kept from influencing the conversion decisions. This technique eliminates the need for the AC hysteresis circuit.
Output Drive capability
The digital outputs of the ADC121 0 and the outputs of the
SAR, through which the resistor ladder is referenced, are
one and the same. Any excessive load current
the digital
output lines will degrade conversion accuracy. For this reason, the ADC121 0 must interface with CMOS logic. However, the three most significant bits (pins 10, 11, and 12) are
buffered from the R-2R ladder and are capable of driving
light loads without degrading linearity. This could prove useful in 2's complement applications where an inverter is necessary in the MSB; one might construct this inverter with a
discrete NPN transistor and two resistors. The bit most sensitive to output loading is the fourth most Significant (pin 9).
An error voltage at this pin gets divided down by a factor of
16 before being applied to the comparator, so if we wish to
limit the error due to output loading to say, Yz LSB, or
1.25 mV at the comparator, we can tolerate 20 mV at pin 9.
If all lower bits will have the same output load, the error
must be limited to 10 mY. Since all of the digital outputs
have a maximum ON resistance of 3500 at 10V VREF in
both high and low states, the maximum allowable load current is 10 mVl3500 = 29 ""A. This current requirement is
easily satisfied with an MM74C914 or MM74C901 thru
MM74C902 level translators for interface with logic levels
different than VREF.
on
To implement the idea, a complementary phased clock is
required. The positive phase is used to clock the converter
SAR as is normally the case. The inverted clock, generated
from the same clock Signal, is inverted by the transistor. The
open collector is wire-ORed to the output of the comparator.
During the first half of the clock cycle (50% duty cycle), the
comparator output is clamped and disabled, though its internal operation is still in working order. During the last half
cycle, the comparator output is unclamped. Thus, the output
is permitted to slew to the final logic state just before the
decision is logged into the SAR. The MM74C906 buffer (or
with two inverting buffers) provides adequate propagation
delay such that the comparator output data is held long
enough to resolve any intemal logic set-up time requirements.
The 500 kHz clock implies that the absolute minimum
amount of time required for the comparator output to be
unclamped is 1 ""s. Therefore, for applications with clock
period must be
signal other than 50% duty cycle, this 1
observed.
""S
Comparator Hysteresis
Vap
Even an ideal comparator can be expected to oscillate due
to stray capacitive feedback if biased in the linear region. It
is the normal operation of the SAR feedback loop to do just
that ... at least at or toward the end of the conversion cycle. For most applications, this oscillation is only a, minor
bother, as the SAR register would have locked out the converted data from further changes at the end of conversion. If
that is still undesirable, the Conversion Complete (CC) Signal may be used to drive an open-collector gate (such as
the MM74C906) with the output wire-ORed to the comparator output. In this way, the comparator is always clamped to
the low state at the end of conversion. Normal operation
resumes upon restart of a new conversion cycle.
122
v+
CLOCK _ _- - - - - - - - - - . . : 2 : : 4t C,
ADC
1210
i'-.
....
MM74C986
In normal operation, however, if we want to preserve 12-bit
accuracy, the comparator oscillation should be suppressed.
10k
r -_ _~23=_1ICOUT
~N39D4
~t------'I
-!ii
TUHI7185-7
FIGURE 7. High Speed Conversion Circuit
527
Testing 'has demonstrated reliable performance from this
circuit beyond the recommended device operating ,frequency of, 65 kHz. However, the AC hysteresis .circuit is still e
very ,reliable technique below this clock ,frequency and,
therefore, should be used. 'Only 'in applications,where the
required clock frequency Is above 65 kHz should the abovementioned technique be ~d?pted.
" ..
The circuit operates as follows: initially the latch is in, the
RESET state, and the converter is in the end-of-conversion
lltat!!, (CO putpu~ at logic low). The S'TAFfi" signal
the
latch lind, on the ,next positivecloc~ tr~sitionj initial~e~ all
internal registers il! the cpnverter. The CO output Is se(to
logic high, presetting the exterl1al latch. the latch Is held in
the "RESET" state d,uring,the'entire con\lel'$ionperio~, effectlvely, preventing a neYf SiAFfT signal from interrqptlng
the conversion;
, '
sets
Synchronlzlne Com.ralan Start Signal
It is recommended that the"START CONVE~T input be synchronized to the CLOCK input. This avoids the possibility of
the comparator making,an error on the first (MSB) decision
when the analog input is near Yz scale. There is a chance
that energy can be coupled to the comparator from the rising edge of the 'STAR'i' Signal. If this occurs just before the
rising edge of the clock, a wrong MSS' decision can be
made if time is not' allowed for the charge ,to dissipate. The
synchronization circuit in F/{Jure 8 effectively prevents this
from occurring.
Serial Output
The cOmparator output does contain the 'stream of serially
converted data with the most significant bit first. However;
recognIZing the danger of comparator piIClliatlon, there is, 'a
potential for the external serial data registE!r to latch a data
bit different from that recorded in the SAR due to different
logiC set-up time requirements. If the ADC1210 accepts an
error in anyone data bit, the subsequent lower order bits
tend to correct for it. On the other hand, an external serial
register has no provision for error correction. All sull,sequent
bits following a bit in error ,will not be valid dllta.
'
The 12 bits of information can', be shifted out seri~IIY by' using an MM74Q15P.digital multiplexer: The cir~uit is shoV!n in
F/{Jure 9. This scheme permits valid, data to be available at
the serial.output port as f~ as haif a. clock cycle after the
most current decision. The data are thus synchfonized to
the converter clock ,(here the $E!ri.1 data are synchronized at
the falling edge of the syste!l1 CLOCK, to avoid ciock skew).
Obyiously, a nlJmber of variations can be made to this baSic
circuit for use with different handshake protocols: .'
--:==::'-----.. . - .....-.·v,,' .
r-.....
START-'---r~
4:7,..,
CLDCK--+------i-'''-i
LSe
.
'
'. "
Msa
'
TL/1:I17185-8
FIGURE. 8. Synchronlzl!'lg START CONVERT Signal
ANALOG iN ---::::=::::"'--~--:==:---,
m1if---r_
CLOCK
--t..::;;;:=:::;...-....
AHA
AOC121D
12 11 10
%MM74CIIO
9
8
Msa
1
6
5
4
3
2
1
LSa
t-:1:;;,.O_-_-~
SERIAL OUT
......++--_---+--11-+--11---~------- DATA VAUD
.....----oOICLR
L..----.....;~CLK
TL/H17185-9
FIGURE 9. 12·Blt AID Converter with Serial Output
528
swing, well within the 15 ,.S converter clock period. Thus,
the ranging circuit is designed to work off the same clOCk.
APPLICATIONS
Long TIme Sample and Hold
The circuit in Figure 10 is a particularly simple realization of
an infinite sample and hold. This scheme requires two lowcost analog sample-and-hold amplifiers to complete the circuit.
The idea is to utilize the digital-loop feedback mechanism of
the.ADC1210 which, in the normal conversion mode, replicates the analog input voltage at the output of the SAR/Dto-A converter.
The circuit is designed such that the auto-ranging function is
transparent to the user. All command signals into and out of
the system are identical to those of an ADC1210 operating
alone. The only exception is that the system requires one
and one-half clock cycle (mandatory auto range cycle), plus
however many ranges it has to scale to (each·scale requires
onll clock period, 7 possible range switching in all) in addition to the basic 13 conversion cycle required by the
ADC1210. Therefore, in the best case where no ranging is
necessary, the. circuit adds 22.5 ,.s to the conversion time;
and in the worst case, an additional 128 ,.s..
The operation of the circuit may be described as follows:
During the normal "hold" mode, the replicated analog voltage is buffered straight through the SI H amplifier to the
output. Upon an issuance of a ~ signal, this S/H
am~lifier is placed in the hold mode, holding the voltage
until the new analog voltage is valid. The same ~
signal triggers an update to the input sample-and-hold amplifier. The most current analog voltage is captured and held
!or conversion. This way, the previously determined voltage
IS held stable at the output during the conversion cycle while
the SAR/D-to-A continuously adjust to replicate the new input voltage. At the end of the conversion, the output sample-and-hold amplifier is once again placed in the track
mode. The new analog voltage is then regenerated.
In the quiescent state where the ADC1210 is in the nonconversion mode, the auto-ranging circuit is free to function
normally. Upon an issuance of a START Signal, the next
clock rising edge puts the circuit in the final auto range cycle
before conversion begins. If the need for up-range or downrange is detected, the circuit remains in the auto range
mode until all necessary scaling is completed. The control
circuit then issues a start conversion signal to the ADC121 o.
Half a clock cycle later, the ADC1210 begins conversion
and suspends the auto-ranging operation until the conversion is completed. At which time the 12-bit converter data
plus the 3-bit range data are valid for further processing.
This design is suitable for applications in data-acquisition
systems or portable instruments, particularly where low
power is an important consideration. Other variations from
this basic scheme can be realized depending on the user's
requirements.
.
An Auto-Ranging Gain-Programmed AID Converter
The circuit in Figure 11 shows one possible circuit of an
auto-ranging AID converter. The circuit has a total of 8 gain
ranges, with the ranging done in the LHOO86 Programmable
Gain Amplifier (for differential input, use the LH0084 with
ranges of 1, 2, 5, 10 digitally programmed, or pin strap programmed for multiplying factors of 1, 4, and 10). The gain
~anges are: 1, 2, 5, 10, 20, 50, 100, and 200. It effectively
Improves the AID resolution from 12 bits to an equivalent of
19 bits, a dynamic range of better than 100 dB.
SUMMARY
The ADC1210 is a low-cost, medium-speed CMOS analogto-digital converter with 12-bit resolution and linearity. It has
wide supply range and flexible configuration to allow varied
applications such as field instruments and sampled data
systems.
The circuit has relatively high speed ranging due to the very
fast settling time of the LH0086, typically 5 ,.S for 1OV
,
!-D
~C~
e
¥lE,
%MM741:74
at---
22
ADCI21D, ADCI211
DI-•
~~
24
CLOCK
A
%MM~D4
14
~
Sl:
C~
~
'/
ee
8
ANALOG IN
£4.7""
I-Va..
3
pg:
23
I"""P""'P""'V ........
20Ok
GND
21
,. 19 15 16 17
20
4
LF1~
.:
VB,,:,
&
.~.
3
'4MM74CDB ::: c.
-.
-
"
l00pF
-15V
5
"-.
4
• lk
..;..
ANALOG
OUT
C,
"""
TL/H/7185-1D
FIGURE 10. InfInite Sample and Hold Amplifier
529
"
+15V
-15V
2lI0'
I"'---_'MSB
ANALOG
'N
1·10 24aV
DATA
LSB '
CLOCK
CONVERSION
COMPlETE
l~~=~~~===~~======~~~====~~~~~~E~~t:t==~Ao
A1 DATA,
, A, RAN6E
TLlH17185-11
FIGURE ~ 1. Auto Gain Ranging AID Converter
530
National Semiconductor
Application Note 247
Larry Wakeman
Using the ADC08081
ADC08098-Bit JLP
'Compatible AID Converters
with 8-Channel Analog
Multiplexer
INTRODUCTiON
The ADC0808/ ADC0809 Data Acquisition Devices (DAD)
implement on a single chip most the elements cif the standard data acquisition system. They contain an 8-bit AID
converter, 8-channel multiplexer with an ad,!iFess input latch,
and associated control logic. These devices provide most of
the logic to interface to a variew of microprocessors with
the addi~on of a minimum number of parts.
'
The second function block. the successive approximation
AID converter, transforms the analog output of the multiplexer to an 8-bit digital word. The output of the multiplexer
goeS to' one of two comparator inputs. The other input is
derived from a 256R resistor ladder, which is tapped by a
MOSFET transistor switch tree. The converter control logic
controls the switch tree, funneling a particular tap voltage to
the comparator. Based on the result of this comparison, the
control logic and the successive approximation register
(SAR) will decide whether the next tap to be: selected
should be higher or lower than the present tap on the resistor ladder. This algotithm is executed 8 times per conversion, once every 8 clock periods, yielding a total conversion
time of 64 clock periods.
These circuits are implemented using a standard metal-gate
CMOS process. This process is particularly suitable to applications where botl:! analog and digital functions must be implementlld on the same chip.
These two converters, the ADC0808and ADC0809, are
functionally identical except that the ADC0808 has a total
unadjusted error of ± % LSB and the ADC0809 has an
unadjusted error of ± 1 LSB. Ihey are also related to their
big brothers, the ADC0816 and ADC0817 exp~dable 16
channel' converters. All four converters will typically do a
conversion'in -100 p.s when using a 640 kHz:clock, but
can convert a single input in
little as - 50 p.s.
When the conversion cycle is complete the resulting data is
loaded into the TRI-STATEGDoutputlatch. The data in the
output latch can then be read by the host system any time
before the end of the next conversion. The TAl-STATE capability of the latch allows easy interface to bus oriented
systems.
'
as
1.0 FUNCTIONAL DESCRIPTION
The ADC0808/ADC0809, shown in Figure 1, can be functionally divided into 2, besic subcircuits. These two subcircuits are an analog multiplexer and an AID converter. The
multiplexer uses 8 standard CMOS analog switches to provide for up to 8 analog inputs. The switches are selectively
turned on, depending on the data latched into a 3"bit multiplexer address register.
r-----------__.--CLOCK
ALE---..,
A
The operation of these converters by a microprocessor or
some control logic is very simple. The contrOlling device first
,selects the desired input channel. To do this, a 3-bit channel
address is placed on the A, B, C input pins; and the ALE
input is pulsed positively, clocking the address into the multiplexer address register. To begin the conversion, the
START pin is pulsed. On the rising edge of this pulse the
internal registers are cleared and on'the failing edge the
start ~nversion is initiated. '
,
1+------ START
......T"---:---~---.....,r---....t------... ~:~ERRUm
CONTROL
LOGIC
OUTPUT ENAILE
(DEI
07
INO
INI
01
1M2
IN3
UI
IN4
IN5
INI
03
04
D3
01
DO
IN?
REF (+I--'W~~M...JII."""....W~~
TUH/5823-1
FIGURE 1. ADC080S/ADCOS09 Functional Block Diagram
531
As ·me~tioned earlier, there are B clock periods per approxi,: ,·.matiori::'Even though there is no conversion in "rogress the
·ADCOBOB}ADC0809 is still internally cycling through these
.~ Clock, periods. A start pulse can occur any time during this
.' cyCle but the conversion will not actually begin until the converter internally cycles to the beginning of the next B clock
period sequence. As long as the start pin is held high no
conversion begins, but when the start pin is taken low the
conversion will start within B clock periods.
The EOC output is triggered on the rising edge of the start
pulse. It, too, is controlled by the B clock period cycle, so it
will go low within B clock periods of the rising edge of the
start pulse,. One can see that it is: entirely possible for EOC
to go·IQW before the conversion starts internally, but this is
.not important, since the positive transition of EOC, which
occurs at the end of a conversion, is what the control logic
is looking for.
Once EOG does go high this signals the interface logic that
the data resulting from the conversion· is ready to be read.
The output enable (OE) is then raised high. This enables the
TRI-STATE outputs, allowing the data to be read. FIgure 2
shows the timing diagram.
full-scale is of great importance. For exampll!, ~e potentiometric displacement transducers of FJj;ure 3 have this
feature. When the wiper is at midscale, the output voltage is
Vo = VF x (Wiper Displacement) == VF X 0.5. This enables thl! use of much I~ accurate and less expensive
references. The important consideration for this' reference is
noise. T.~ reference must be "glitch free" because a voltage spike during a cOnversion cycle could cause conversion
inaccuracies.
+V
IV
H~""---"REFI+}
)-4HI----I1II
~~-..... INI
AOCHDII
AOcena
FROM
ANALoa
TRANSDUCERS
2.0 ANALOG INPUTS
2.1 Ratiornetrlc Inputs
The arrangement of the REF( +) and REF( -) inputs is intended to· enable easy design of ratiometric converter systems. The REF inputs are located at either end of the 256R
resistor ladder and by proper choice of the input voltages
several applications can be easily implemented.
Figure 3 shows a typical inPut cOnnection for ratiometric
transducers. A ratiometric transducer is a conversion device
whose output is proportional to some arbitrary full-scale value. In otherwords, the transducer's absolute output value is
of no particular concern but the ratio of the output to the
TO C'U OR
CONTROL LODIC
L------.--1REFH
FIGURE 3. Ratlometrlc Converter
with separate Reference
CLOCK
.
--J
~L
ALE
START
\
,...........,
II
I
IN'UT
OUTPUT
ENAILE
Eoe
I
I- -~-
:!.t~ CLOCK 'ERIODS}
:
/--IC
DATA
OUT,UTS
~
STAiLE:
J 1r..
TRI.SfATE
-----------------~------------
•
L
OATAVALIO
TLIH/5623-2
FIGURE 2. ADC08081 ADC0809 Timing Diagram
532
are shown in Figures 5 and 6. The magnitude of the reference voltage, VREF = REF( +) - REF( -), can be varied
from about -O.5V to Vee, but the center voltage must be
maintained within ± O.1V of Vcc/2. This constraint is due to
the deSign of the transistor switch tree, which could malfunction if the offset from center scale becomes excessive.
V~riation of the reference voltage can sometimes eliminate
the need for external gain blocks to scale the input voltage
to a full-scale range of 5V.
Since highly accurate references aren't required it is possible to use the system power supply as a reference, as
shown in Figure 4. If the power supply Is to be used in this
manner supply noise must be kept to a minimum to preserve conversion accuracy. If possible the supply should be
well bypassed and separate reference and supply PC board
traces, Originating as close as possible to the power supply
or regulator, should be used. This is illustrated in Figure 4.
External accessibility of both ends of the resistor ladder enables several variations on these basic connections, and
~
________________________-e______
POWER
SUPPLY
.~~~~~~R
VCC
~---""--""~~----~REF {+I
)o ....-t----tREF I-I
A_I
ABeDI.
TB CPU BR
CONTROL LBGIC
IV
> ....--~--tREFI-I
GNB
TLlH/5623-4
FIGURE 6. Mld-8upply Centered Reference Using Buffered Resistors
Figure 5 shows a center referencing technique, using two
equal resistors to symmetrically offset an LM336 2.SV reference, from both supplies. The offset from either supply is:
Vee - VREF
.
VOFF =
'2
= 1.2SV
As. the reference voltage decreases, system noise will become more Significant so greater precaution should be enforced at lower voltages to compensate for system noise;
i.e., adequate supply and reference bypassing, and physical
as well as electrical isolation of the inputs.
These resistors should be chosen so that they limit current
through the LM336 to a reasonable value, say S mAo The
total resistor current is:
IR = IREF + ILADDER + ITRAN
where ILADDER is the 256R ladder current, ITRAN is the current through all the transducers, and IREF is the current
through the reference. R1 and R2 should be well matched
and track each other over temperature.
For odd values of reference voltage, the reference could be
replaced by a resistor, but due to loading and temperatUre
problems, these resistors should be buffered to the REF( + )
and REF(-) inputs, Figure 6. The power supply must be
well bypassed as supply glitches would otherwise be
passed to the reference inputs. The reference voltage magnitude is:
. 2.2 AbsOlute Analog Inputs
The ADC0808! ADC0809 may have been designed to easily
utilize ratiometric transducers, but this does not preclude
the use of non-ratiometrlc inputs. A second type of input is
the absolute Input. This is one which is independent of the
reference. This Implies that its absolute numerical voltage
value is very critical, and to accurately measure this voltage
the accuracy of the reference voltage becomes equally critical. The previous designs can be modified to accommodate
aPsolute input signals by using a more accurate reference.
In F/f/ure 4 the power supply reference could be replaced by
LM33s:.S.0 r¢erence. R1 and,R2 of Figure 6, and R1 and
R3 of Figure 7 mey have to be made more accurately equal.
In some small systems It is possible to use the precision
reference as the, poWer supply as shown in FIgure 7. An
unregulated supply voltage> SV is required, but the LM336S.O functions as both a regulator and reference. The dropping resistor R must bti choser! so that, for the whole range
of supply currents needed by the system, the LM336-S.0 will
stay in regulation. As in 'FlfJUre '4 separate supply and reference traces should be used to maintain a noiseless supply.
If the system requires more power, an op amp can be used
as shown in F/f/!Jf8 8 to isolate the reference and boost the
supply current capabilities. Here again, a single unregulated
supply is required.
VREF = VDD
(2R1~ R2) ForR3 =
R1
There are several op amps that can be used for buffering
this ladder. Without adding another supply, an LM3S8 could
be used if the REF( + ) input is not to be set above 3.SV. The
LM10 can swing closer to the positive supply and can be
used if a higher VREF( +) voltage is needed.
As the REF( + ) to REF( -) voltage decreases the incremental voltage step size decreases. At SV one LSB represents
-20 mV, but at 1V, one LSB represents -4 mV.
S34
2.3 Differential Inputs
Differential measurements can be obtained by playing a little software trick. This simply involves sequentially converting two channels then subtracting the two results. For example, if the difference voltage between channel 1 and 2 is
required, merely convert channel 1 and read the result.
Then convert channel 2, input the result, and subtract it
from the first result. (See Figure 9.) When using this procedure, both input signals must be stable throughout both conversion times or the end result will be incorrect. One way to
get around this is to use two sample/holds which are sampled at the same time.
'V
VCC
.....-----1
VCC
'V -JV.~-4-""':=-----I REF ,.)
REF ,.)
INO
INO
INI
INI
IN2
FRDM
TRANSDUCERS
IN3
1M
ADC08DIJ
ADCOI09
TD CPU DR
CDNTRDL LDDIC
FRDM
ANALDG
TRANSDUCERS
ADCDlDII
ADCDlOI
TD CPU DR
CDNTRDL LDGIC
•.1'"
~----~REFH
GND
....- - - - - - i R E F H
---+~~R~~~isR
- - - - - - - -....
..
A
GND
'---------
FIGURE 7. Precision Reference used as a Power Supply
---.~~~~~~
FIGURE 8. Precision Reference Buffered
for Power Supply
5V
TO
REFERENCE
CHANNEL I
CHANNEL 2
TO CPU DR
CDNTROL
LDGIC
CHANNEL 3
CHANNEL 4
TD
REFERENCE
TL/H/5623-5
FIGURE 9. Software Controlled Differential Converter
535
parallel data acquisition scheme. Figu/11 11 shows this circuit. in which all the input channels are connected in pairs
through LF998 monolithic sample/holds. Under normaloparation a sample/hold iI~ a~essed through.an MM74C42
which wiD pulse an MM74C221, generating a sample pulse.
After a sample/hold is done sampling.the signal, the appropriate channel is started. If this process is alternated between two converters the sample rate can be doubled.
A second method is to use two chips to convert a differential channel, Figu/11 10. Typically·each channel 1 would be
connected to opPOsite sides of the differential. input. Both
converters are started simultaneously, When both. converters' EOC outputs go high the output of the AND gate will go
high indicating that the data is ready to be read.' .
The circuit in Figu/11 10 can be slightly modified to provide
increased data throughput by using two converters in a
TO
'
REFERENC~~ ~
REF (+)
INO'
CHANNEL 1
,
~
CHANNELZ
INI
CHANNEL 3
INZ
CHANNEL 4
CHANNEL 5
IN3 AOCD808I EOC
AOC0809
IN4
START
CHANNEL 6
IN5
ALE
IN8
CLOCK
CHANNEL 7
CHANNEL 8
-
DE
-
REFH
-
MM74C08
IN7
P""" I-
,.}
DATA OUTPUTS
00-07
A,B,C
-
D},
..t
r
-
',-
1-TO CPiJ'OR
CONTROL
LOGIC
REF (+)
INa
00-07
INI
IN2
EOC
START
AOC08081
114 AOC080a ,/ILE
~
I-
IN3
IN5
CLOCK
IN6
DE
IN7
TO
REFERENCE
REFH
~
....
A
A,B,C
'1
Tl/H/5823-8
FIGURE 10. Dual Converter Differential Circuit
596
2.4 Analog Input Considerations
Analog inputs into the ADC0808/ ADC0809 can handle any
input signal that is maintained within the supply limits, but
some careful consideration must be given to the output 1m·
padanee of the transducer or buffer. Using transducers with
large source impedances can cause errors due to compara·
tor input currents.
5V
VCC
REF(.'
CHANNEL I
IN
LF311
OUT 1 - - - - - - - - - - . . . 0 4
HOLD CAP
TIIIIO'F
TO CPU
OR CONTROL
LOGIC
IV
IV
lilt
lilt
IV
VCC
0
. . .-----} ::r::
C
•
A
MM74C4Z
TO
OTHER
TO CPU
OR CONTROL
LOGIC
II1II744:221
G21------~=t~
10
GND
TUH/5623-7
FIGURE 11. Parallel Data Acquisition with sample/Holds
537
.....
"II'
N
.,
Z
oi(
many TTL circuits. The data outputs' of the ADCOB081
ADC0809 are capable of 'driving one standard TTL load
which is adequate :for most small systems. but for larger
systems extra buffering may be rtecessary. The EOC output
is not quite as powerful as the data outputs, but normally it is
not bussed like the data outputs.
The converter inputs are standard CMOS compatible inputs.
When TTL outputs are connected to any of the digital inputs
a pull-up resistor should be tied from the TTL output to Vee,
· - 5 kO. This will ensure that the TTL will pull-up above
'3.5V.
.
.
To understand the nature of these currents a short discussion of comparator operation is required.·F/fluf9 12 shows a
simplified model of the comparator and multiplexer. This
comparator alternately samples the input voltage and the
ladder voltage. As it samples the input, Cc and. Cp are
charged up to the input voltage. It then samples the ladder
and discharges the capacitor. The net charge' difference is.
determined by a modified inverter chain and results in a 1 or·
o state at the output.
. . . '.
Eight samples are made per conversion, resulting in eight
spikes of varying magnitude on th~ input.
If the source resistance is Ia:rge, it 'adds to the RC time constant of the switched capaCitor which will inhibit th~ input'·,
from settling properly, causing errQrs, As one might expect,
the maximum source resistance allowable ·for accurate conversions is inversely proportional to ·clock frequency. This
resistance should be :s: 1 kO at 1.2 MHz 8I'Id:S:2 kO at 640
kHz. If a potentiometer-type ratiometric transducer is used·it
should be :S:5 kO at 1.2 MHz and :S:10 kO.at640 kHz.
Usually the converter clock will be derived from the micro·processor system clock. Some slower microprocessor
clocks can be used directly, but at worst a few divider
· stages may be necessary to divide microprocessor clock
frequencies above 1.2 MHz to a usable value.
The timing of the START and ALE pulses relative to channel
selection and signal stability can be critical. The simplest
approach to microprocessor interfaces usually ties START
and ALE together. When these lines are strobed the address is strobed into the address register and the conversion is started. The propagation delay from ALE to comparator input of the selected input signal is about - 3.0 p.s
Onput source r~sistance < < 1 kO). If tl:!e start pulse is very
short the comparator can sample the analog input before it
is stable. When using a slow clock :s: 500 kHz the sample
period of the comparator input is long enough to allow this
delay to settle out.
If the ADC08081ADC0809 clock is > 500 kHz, a delay between the START and ALE pulses is required. There are
·three basic methods to accomplish this. The first possibility
is to design the microprocessor interface so that the START
and ALE inputs are separately accessible. This is simple if
·some extra address decoding is available. Separate accessibility of the START and ALE pins allows the microprocessor, via software, to set the delay time between the START
and ALE pulses.
If extra decoding is not available, then START and ALE
could be tied together. To obtain the proper delay, the microprocessor would cause STARTI ALE to be strobed twice
by executing the load and start instruction twice. The first
time this instruction is executed, the new channel address is
loaded and the conversion is started. The second execution
of this instruction will reload the same channel address and
restart the conversion. But since the multiplexer address
register contents are unchanged the selected analog input
will have already settled by the time the second instruction
is issued. Actual implementations of these ideas are shown
in following sections.
If large source impedances are unavoidable (~2 kO at 640
kHz), the transient errors can be reduced by placing a bypass capaCitor ~ 0.1 p.F from the analog inputs to ground.
This will reduce the spikes to a smllil average current which
will cause some error as well, but this can be much less
than the error otherwise incurred. The maximum voltage error for a potentiometer input with a bypass capaCitor added
is:
_ [RPOT
Ck]
VERR - -5- (liN) 640 kHz V
where RpOT = total potentiometer resistanqe; liN = maxi-.
mum input current at 640 kHz, 2 pA; and Ck = clock frequency.
.
For standard buffer source impedance the maximum error·
is:
where Rs = buffer source resistance; liN = the maximum
input current at 640 kHz, 2 p.A; and Ck = clock frequency.
3.0 MICROPROCESSOR INTERFACING
The ADC08081 ADC0809 converterswer&designed to interface to most standard microprocessors witll very little external logic, but there are a few general requirements which
must be considered to ensure proper converter operation.
Most microprocessors are designed to be TTL compatible
and, due- to speed and drive requirements, incorporate
UHR'S BUFFER
ANALOG MUX
COMPARATOR FRONT END
~--T---T-----------'
I
I
I
1....._-....,-
}
~~NTROL
LOGIC
TLiH/5823-8
FIGURE 12. Analog Multiplexer and Comparator Input Model
538
A third possibility when ALE and START are tied together is
to stretch the. microprocessor derived ALE 1START pulse by
inserting a one-shot at these inputs and creating a positive
pulse > 3 p.s. Since ALE loads the multiplexer register on
the positive going edge of the pulse and START begins the
conversion on the falling edge, the width of the pulse sets
the ALE to START delay time.
Most microprocessor interfaces' would be designed such
that a START pulse is issued by a memory or 1/0 write
instruction, although a memory or 1/0 read can be used.
The ALE strobe on the other hand, requires a write by the
CPU when A, B, and C are connected to the data bus, and
could use a read instruction if A, B, .and C are connected to
the address bus, but the software could get confusing. The
logic to derive the OE strobe must be connected to the
microprocessor so that a memory or 1/0 read instruction will
cause OE to be pulsed. A read is required since the
AOC0808/ AOC0809 data must be read.
3.1 Imerfacll1g to the 80BO
The simplest Interlace wquld contain no address decoding,
which may seem unreasonable; but if the system ports are
110 mapped, up to 8 of them can be connected to the CPU
with no decoding. Each of the 8 110 address lines would
serVe as a simple port enable line which would be gated
with read and write strobes to select a particular port. This
scheme is shown in Fl{lure 13. A7 is the address line used
and, whenever it is zero and an 110 read or write is low, the
port is accessed. This implementation shows A, B, C connected to DO, 01, 02 causing the information' on the data
bus to select the channel, but A, B, and C could be connected to the address bus, with a loss of only 3 ports. Both
decoding schemes are tabulated in Figure 14. (Remember
A, B, C inputs are only valid when selecting a channel to
convert, and are not used to read data.)
SV
VCC
REF f+)
TO REFERENCE
TRANSDUCERS
FROM!
01
01
DI
06
05
04
OS
IND
INI
03
02
IN2
IN3
01
DO
104
INS
IN&
INTlloaOI .
EOC
ADCIIIOI/
ADCOm
r
5v"--,
RESETTABLE INTERRUPT
-SV - - -
I
I
I
I
I
I
I
DC
03
02
01
DO
5V
INT
I
I
100
I
L ______ :::._...J
50
IN1
l7iiIi
DE
50
to REFERENCE
REFH
START
ALE
L::;t"t"---c2 are gated together and, for a write R/W
is inverted.
is the 6800 phase 2 system clock. Also natice that the 6800 IRT interrupt input is active lov,;. Tt;i~ enables a standard wired-OR open collector design to be imp·lemented.
Both the decoder and the bus comparator methods of address decoding have their own advantages. Bus comparators will more completely decode addresses but are capable
of only a limited number of port strobes. Decoders, on the
other hand, provide less decoding but more port strobes.
There is a trade off for minimum parts systems as far as
which route to go, and it will depend on the CPU and type of
system.
"'2
Ftgure 20 illustrates some typical 6800 software utility rou-
tines for eith/lr polled or interrupt interfaces. Again notice
double start instructions.
3.2 InterfaCing to ,the 6800
The ADC0808/ ADCo809 easily interface to more than one
microprocessor. The 6800 can also be used to t;:Ontrpl the
converter. The 6800 tias no separate I/O address space so
all I/O transfers must be memory mapped. In general more
address decoding logic is required to ensure that the I/O
ports don't overlap existing memory. For small systems a
partial address decoding scheme is .shown in Ftgure 18.
Generally, if several ports are deSired, a 'small. block of
zao
3.3
Interface
InterfaCing the Z80 to the ADC0808 is much the same as
interfacing to an 8080/8224/8228 CPU group. CPU instruction timing is very similar, except'the read/write 'control signals are slightly different. Instead of the IlOW write strobe
there is thelmE<:i and ii\7F{ and instead of IlOR, 10Rm
and RD are supplied.
5V
TO
REFERENCE
5.
REF (+1
i7iiR
I1I!W
DE
5.
OM1~LS02
5V
START
OUT
5V
IND..
i
ALE
GNO
5V
5V
Al
FROM
TRANSDUCERS
AOCOBOBI
AOCDBD9
A6
AS
A4
A3
EOC .....---1---1
TO BOlD
INTH
"A3
,11-:----------------A.....---------~--------
TO
REFERENCE
REF I~)
A2
AI
...
':
CLOCK .....- - - i H
BDBO CLOCK
+,(2MH.)
5V
5V
TUH/5623-11
FIGURE 17. Interrupt-Type aoa0/8224/8228 Interface Using 6-Blt Bus Comparator
542
REfEREN~~
REf (+)
INO
INI
IN2
OE
FROM
TRAN$OUCERS
IN3
ADC'SOBI
AOCIJ808
5V
IN4
5k
IN5
ALE
START
.,
A2
AD
TO
REfERENCE
ALEISTART Port - DOOOH-DOO7H
Data Read Port - DOOOH
FIGURE 18. Typical 6800 Interface with Partial Address Decoding
sv
DMII3I
STROBE
5V
TO
REfERENCE
REfH
DE 1--41---<:><
G21-t+-- EOC STATUS BIT
MASK BITS 1-7
IF A = 0 THEN CONVERTER DONE, '
EXECUTE MISC PROGRAM
·CONTINUOUS POLLING OF EOC (FIGURE 19)
POLLIT '
':, LDAA
ANDA'
BNE
READYLDAA
,
EOCIN
,CHANN2
POLL IT
DATA
LOAD Eob STATUS
MASK MSBs
ITAG(>,oO NOT READY, LOOP
ELsE READ DATA
' '
CONTINUE PROGRAM
FIGURE 20. Typical 110 Routines for AD(:080SIA!)COS09 and 8800 Interface
, ','
544
,~,
'
.--------------------------------------------------------------------. z
~
4.0 CONCLUSION
Both the ADCOBOB and the ADCOB09 can be easily used in
microprocesSor controlled environments. Many sophisticated medium throughput applications can be handled with a
minimum of extra hardware, but additional hardware can increase flexibility and simplify software. Putting both the multiplexer and AID on the same chip frees the designer from
matching multiplexers and AIDs to implement a 7 or 8-bit
accurate system. Design time and overall system cost can
be reduced by using these low cost converters.
Figurs 21 shows a very simple Z80 interface, which is similar to the INS8080 interface of Figurs 13, except that the
interrupt flip-flop design is closer to the 6800 designs. This
is because the Z80 iJiIT is active low as is the 6800, but the
INS8080 INT Is active high.
Figurs 22 shows a fully decoded bus comparator design
where the DM8131 decodes 5 address bits and the 10I'iE0
1/0 request strobe. Two NOR gates gate the FfI5 and WR
strobes for ALE, START and OE inputs.
5V
5V
..-----TNT
5V 112MM14C14
VCC
TO
D
II
CK
fimi
EOC
REFERENCE
01 ~---_i-----------~-------D1
08 ~---~r_-------------------D8
D5 ~----~r_-------------------D5
D4 ~-----_+------------------------04
D3 ~------~~--------------------D3
D2 ~~---~r_---~-------------02
INO
~~~-~r_-------------------Dl
~r1_t--~----------------------DO
5k
5V
ANALOG
INPUTS
ADC08081
ADC0809
A
5V
~-4----~ analog
converters and buffered amplifiers.
TUH17313-2
FIGURE 2. Complete LHOO32 Schematic Diagram
lk
TUH/7313-3
FIGURE 3. High Speed Sample and Hold Circuit
548
A High Speed S/H Circuit
High Speed sample-and-hold circuits require high slew rate
and fast settling amplifiers. The LH0032 is ideal for these
applications. An example is shown in Figure 3.
The complementary emitter-follower 03 and 04 sources or
sinks large Reak current to rapidly charge or discharge the
hold capaCitor during step changes, thus e~ectively b.uffering thE! FET switch, 01, whose rD(ON) would otherwise slow
the charge time. The LH0033 FET-input amplifier buffers the
output signal, providing 100 mA drive capability.
The circuit exhibits a 10V acquisition time of 900 ns to 0.1 %
accuracy and a droop rate of only 100 p.V/ms at 25°C ambient condition. An even faster acquisition time can be obtained using a smaller value hold-capacitor. By decreasing
the value from 1000 pF to 220 pF, the acquisition time improves to 500 Ils for a 10V step. However, droop rate increases to 500 p.V/ms.
100 mAo The circuit can be easily modified to operate from a
single + 15V power supply. The only requirement is that the
amplifier must be biased within the input common mode
range.
The receiver circuit uses an LH0032 configured as a transimpedance amplifier. A photodiode with 0.5 amp per watt
responsivity such as the Hewlett-Packard type HP50824220, generates 50 mV signal at the receiver output for
1 p.W of light input.
Expectedly, the bandwidth of the entire optical link rests on
the receiver circuit. Therefore, if the response time is to be
optimized, one should reverse bias the photodiode to minimize junction capacitanCe. As a result, rise time improves
more than 2 orders of magnitude. Next, the feedback resistor value should be chosen to be as large as possible in
order to maximize sensitivity within the limits of allowable
bandwidth degradation. Using 100 kO feedback resistor, the
maximum system bandwidth is 3.5 MHz.
Fiber OptiC Transmitter-Receiver Applications
Many fiber optiC applications require analog drivers ·and receiverS operating in the megahertz region where many socalled wide-band op amps simply run out of steam. Packed
with 70 MHz gain-bandwidth product (unity gain compensated), the LH0032 is quite suitable for optical communication
appHcations up to 3.5 MHz. Figure 4 demonstrates a complete analog transmission system using this device.
The transmitter incorporates the LF356 to drive the light
emitter. The LED is normally biased at 50 mA operating
current. The input is capacitively C9upled and ranges from
OV to 5V, modulating the LED current from 0 mA to
Fast Settling .12-BIT 01 A Converter
A high resolution, fast-settling DAC can be constructed using the LH0032. Its low input bias current causes no significant DC error in conversion accuracy. Great care must be
exercised in circuit layout to assure highest performance. A
single point analog ground shOUld be used with the digital
ground separated. A complete circuit with 12-bit resolution
is shown in Figure 5. The converter typically settles to
1,4 LSB in 800 ns for a 10V full-scale swing. Similarly, 10-bit
or 8-b,t resolution DACs may be constructed using the
DAC1020 or DAC0808, respectively.
·+11V
1.241<
VOUT
....·U..+-...-+1&V
"':"
-15V
.-11V
"':"
TL/H17313-4
FIGURE 4. Fiber Optic Link
100
MSI
~u..._..... OV " VOUT " +1OV
-15V -IIW\--,......:::::=-t
TUH/7313-5
FIGURE 5. Fast Settling OAC
549
Buffered AmpiHIer"
WheneVer higher outpUt current is required, a buffer amplifimay be added to the loop as shown 'in F/fJuf9 6. The
LH0033 boosts the output drive capability to ± 100 mA con'
tinuous and ±400 mA peak.
DESIGN CONSIDERATIONS
dptlmlzlngLH0024/32 Performaripe ,
The LH0024 and ,LH0032 all~w cOnsiderable fle!dbillty i,l'!designing high performance circuits if care is taken iri the way
they are used and implelilent8d. Inde8d, 'the printed CirCUit
board layout in' high f~equency circuits is as important as the
design Of the hYbrid devices themselves. • ' "
,
It ,Is good praCti~'to uSe grouiid planlJ POI;)Oard de'iilgn. It
provides a low ~esistance, loW in~uctance Path~ a,xi r",duces stray signal coupling to sensitive circuitry. Adouble-sided
ground plane is usually better and should be consider8cJ.
In addition, ~ignal trace conh~O~s should be kept ~ sho~
, and Wide as possible. Avoid closely-sPaced p~lelsig"'al
traces as signal cross-coupling may occur. Circuit' elements
should be placed cloSe to the amplifier, PBl1lcularlycritieal
camponents that directly affect the amplifier's freQuenC)'response, such as compensation capecitors. If at all possible,
one should maintain single point ground, throughout the circuitto,minimize signal phase d e l a y . ,
Examples .of single-Sided PC layouts for the LH0024 and
LH0032 are shown in 'Figuf9 7 and Figuf9 8, respectively.
The layouts include a settling' time test circuit, optional inverting or nonlnvertiog mode. Note' that the summing junction side of the feedback resistor is kept very close to:tlle
device pin" thus minimizing lead capacitance., The, power
supply, decoupling capaCitors shquld al8.C\ be kept close to
the device pins, prefe~bly % of an inch.
c
er
HpF
>~""'''''cOUTPUT
'-1IV
,-IIV
TLlH17313-6
FIGURE 6. Wide Band Amplifier
with 100 rnA OUtput capability
Despite its 100' MHz bandwidth, the '(HOOS3 introduces
about 15 degrees of phase lag at the LH0032 unity-gain
frequency of 70 MHz. As a result, phase margin is degraded
by the same amount. Slight overcompensation may be required in order to restore adequate phase margin. One way
is to Increase the feedback capacitor from 5 pF to a slightly
larger value, 6 to 6 pF Should be sufficient: If the load is
predominantly capaCitive, the total phase shift of the buffer
stage may exceed 180" and appear as negallve impedance
seen looking into the input of the buffer. the 510 reSistor
restores some real resistance to alleviate this condition and
prevents potential oscillation. In cases where the load capacitance is relatively large, up to 1000 'may be nece~
to compensate for it.
c
Input Guarding 'and Baot!lb'applng
In applications where input leakage currents are important,
trace guarding, such as \lsed in sample ,and hold circuits,
can improve performance at no additional cost.
TUH/7313-7
CllMI'OIIENT SIDE
.
"
,
FIGURE 7. Slngle-5lded Sample PC Layout tor LH0024
550
TLlH/7313-8
.
r--------------------------------------------------------------------.~
Z
N
U'I
W
TUH17313-9
COMPONENT SIDE
TLlH/7313-12
FIGURE 8. Single-5ided Sample PC Layout for LH0032
The guard conductor serves to intercept leakage currents
from inputs to the surrounding circuit. It is most effective
when it is driven to the same potential as the guarded circuit. Figures 9 and 10 show how the technique is implemented in inverting and non-inverting configurations, respectively.
One other benefit of input guarding is the reduction of input
stray capacitance effects. A comprehensive discussion of
this technique is described in Application Note AN-63.
Input Capacitance Cancellation
The intrinsic input capacitance of the amplifier cannot be
totally eliminated by the input guarding technique. This input
capacitance introduces a pole in the amplifier response at
the frequency given by:
fp = 2'ITR: C,N
.
(3)
This pole may become extremely important as, for example,
a C,N of 5 pF (typical input capacitance of the LH0024 and
LH0032) with a 500n effective source resistance creates a
pole at about 64 MHz-well before the amplifier's natural
frequency response rolls off to unity gain at 70 MHz. If
closed-loop gain is unity, more than 1350 total phase lag is
introduced even before the crossover frequency is reached
and will destroy phase margin. Oscillation is certain to occur. The solution is to cancel its effect. As shown in Figure
11, the lead capacitor C1 across the feedback resistor is
used to introduce a zero in the loop response such that it
exactly cancels the pole caused by the input RC network.
INPUT ~W"""'.....,R---=t
OUTPUT
Cl'
TL/H17313-10
2-8pF
FIGURE 9. Guarding Inverting Figure Amplifier
INPUT --Wlr-t-....
OUTPUT
'Cl=B C,N
OUTPUT
TUH17313-13
FIGURE 11_ Compensating Amplifier Input Capacitance
TL/H/7313-11
FIGURE 10. Guarding Non-Inverting
Unity Gain Amplifier
551
~ ~----~--------------------------------------------------------------------------,
~
c
Ideally, the ratio of input capacitance CIN to lead capacitor.
C1 should equal the cloSed-loop gain of the amplifier. Under
this condition, exact pole-zero cancellation is realized.
Note that Equation (3) dictates the use of source resistance
values less than 1 kO in circuits operating at or near unity
gain to keep fp greater than 70 MHz.
5pF
INPUT -Wlr-+-t-=I
OUTPUT
Frequency CompensaUon
High-performance wideband op ampil such as the LHOO24
and LH0032 require extemal frequenCy compensation, depending on the closed-loop gain. Optimum AC performance
will be affected by a given circuit :and its layout. Several
compensation techniques are recommended and the best
should be selected according to the particular application.
Each is discussed in the following sections.
-15V
TLlH17313-15
FIGURE 13. Input RC Lag Compensation Circuit
CompenaaUng the LHOO32
With the LHOO32, two compensation schemes may be used,
depending on the designer's llpeCific needs.
The first technique is shown in Figure 14. It offers the best
0.1 % settling time for a ± 10V square wave input. The compensation capacitors Cc and CA should be selected from
'. Figure 15 for various closed-loop gains. Figure 16 shows
how the LHOO32 frequency response is modified for different value compensation capacitors.
Although this approach offers the shortest settling time, the
falling edge exhibits overshoot up to 30% lasting 200 to
300 ns. Figure 17 shows the typical pulse response.
Compensating the LHOO24
Table II provides a guide to compensate the LH0024 at several values of closed-loop gain. Figure 12 shows the basic
scheme.
+15V
112
INPUT
....- OUTPUT
>=~
1-,\-I\Rl,.,...-=-t
R3
R2
TLlH/7313-14
FIGURE 12. LHOO24 Frequency Compensation Circuit
When operating with closed-loop gain of -1, C3 is required
and may need slight adjustment to completely cancel the
input capaCitance of tlie device, typically 5 pF.·
INPUT
1'_~R-I\I,....~
OUTPUT
-15'
TABLE II
Closed-Loop Gain
C1
C2
C3
100
0
0
0
20
0
0
0
10
0
20pF
1 pF
1
30pF
30pF
5pF
TLlH17313-16
FIGURE 14. LHOO32 Frequency Compensation Circuit
,
I
~
1/
An altemate technique for compensation at a closed-loop
gain of 1 is to use an input RC lag compensation network as
shown in Figure 13.
With 1 kO resistor values in the circuit, Rc and Cc should be
820 and 0.047 p.F, respectively. The difficulty in using this
compensation is its involved calculation and. experimenting
required in order to find the optimumRc and Cc values if
resistors other than 1 kO.are used when the above Rc and
Cc values are no longer valid .and must be redetermined.
For this reason, optimum compensation is almost always
determined empirically,. as were the values given.
10
I
I
5
I-
['\Cc
I-
C
I
o
1
10
100
CLOSED LOOP GAIN
TLlH17313-17
FIGURE 15. Recommended Value of
Compensation' Capacitor VI- Closed-Loop
Gain for .O~mum setulng nme
552
10
i
60
!z
.
.
(
40
-45
:!:
c 20
-til
C
!:l
co
-1311
-20
101<
1M
II10lc
10M
I
8
t
4
z
2
I..
..i
I
IiE
!
-110
100M
1\
\
'cc
CA
1
I
o
1
FREQUENCY (Hz)
10
100
CUllED LOOP BAlN
TL/H17313-18
TUHI7313-20
FIGURE 16. The Effect of Various
Compensation Capacitors on LHOO32
Open Loop Frequency Response
FIGURE 18. Recommended Value of
Compenaatlon capacitor va. Closed-Loop
Gain for Optimum Slew Rate
lOY
lOY
\..\ ....... .
/
!I...... .
F·····
~
lOY
\
v
lOOns
lOY
TUH17313-19
SOns
TUH/7313-21
FIGURE 17. LH0032 Unity Gain Non-Inverting
Large Signal Pulse Response:
TA = 2S"C,Cc = 10pF,CA = 100pF
FIGURE 19. LHOO32 Unity Gain Non-Inverting
Large Signal Pulae Response:
Cc = SpF,CA = 1000pF
If obtaining minimum ringing at the falling edge is the primary objective, a slight modification to the above is recommended. It is based on the same circuit as that of Figure 14.
schematic, in which a 2700 resistor and a 0.01 /LF capaCitor
are shunted across the inputs of the device. This lag compensation introduces a zero in the loop modifying the response such that adequate phase margin is preserved at
unity gain crossover frequency. Note that the circuit requires
no additional compensation.
The values of the unity gain compensation capacitors Cc
and CA should be modified to 5 pF and 1000 pF, respectively. Figure 18 shows the suitable capacitance to use for various closed-loop gains. The resulting unity gain pulse response waveform is shown in Figure 19. The settling time to
1% final value is actually superior to the first method of
compensation. However, the LH0032 suffers slow settling
thereafter to 0.1 % accuracy at the falling edge, and nearly
four times as much at the rising edge, compared to the previous scheme. Note, however, that the falling edge ringing is
considerably reduced. Furthermore, the slew rate is consistently superior using this compensation because of the
smaller value of Miller capaCitance Cc required. Typical improvement is as much as 50%. A more detailed discussion
of this effect is provided in the Slew Response section of
this Application Note.
lk
>''+.....-OUTPUT
0.01""
TUH17313-22
FIGURE 20. LHOO32 Non-Compenaated
Unity Gain Campenaatlon
The second compensation scheme works well with both inverting or non-inverting modes. Figure 20 shows the circuit
553
Power DIssipation
Output Drive Capabl!lty
The LHOOl!4 and LH0032.op amps' are deliignedto deliver,
but not to exceed, ± 100 mA peak outp.ut c,Urrent for dura·
tions under 1 ,...s at duty cycles under .1 'lb.
.
A simple design rule that is often bent, if not broken, is that
relating to power dissipation. The limits for the LH0024 and
LHOO32 are shown in F/{Jure 23. Under no circumstances
should these guidelines be exceeded within the temperature
range specified. The total' power dissipation can be easily
calculated from the following equation:
The output drive' /l8pability of these QP amps is limited pri·
marily by device power dissipation. F/{Jure 21 shows the
maximum drive capabilities under various conditions. These
limits should be observed: Furthermore".the open loop gain
decreases slightly as a result of increased output loading.
For this reason, continuous output cL!rrent should be kept
under 50 mAo
.
LH0024
60
PTotal = Po + POut
(4)
Where: Po = the quiescent power at a given supply
voltage and currimt as specified by the data
sheet, and,
.
POut = the drive power dissipated in the device
output stage, computed as the net rrns collsetor-emitter voltage of the output transistor times
the load current.
Determining power dissipation 'when driving a capacitive
load is more involved. The peak power required to charge or
discharge the load capacitor is:
TA= + 25 'C.
'1 ==16V
III
IIY
I- TA= +la'c,
vs==l!Y.....~) TJ\=+70'C,
i-'"
f-
o
o1
wr
=rtLu
PPeak = CdaV)2
.
t
TJ\= +86'C,
t = Ipeak charging time into Cl.
Over a full charge and discharge cycle, the power is directly
roportional to the frequency of the input pulse waveform. As
the pulse repetition frequency increases, so does power dissipation.
.
LHOO24
2 3 4 5 • 7 • B 10 11 12
OUTPUT VOLTAII£ (VI
TLlHI7313-23
LHOO32
60
50
Iii
Ii
i
I
1'0..
TUJ,l,
~I-~ =±ltV ",;I
140
.
au
.....
N
f-
10
lo--'" 10--
'1
"" CASE
A_lEI
~II
'1= +125'C,
o
o
I'..
f'....
1.1
~
(5)
Where: aV = the change in voltage across Cl.
I"1"-.
I.
Irrn-
1 2 3 4 5 • 7 8 9 10 11 12
"-
P"-.
"
I
•
OU7PUT VIJ!,TAGE(VI
25
50
75 lID 125
TEMPERATURE rCI
TL/HI7313-24
151
TLlH/7313-28
FIGURE 21. Continuous Output Drive CapabllHy
LH0032
Capacitive Load Compensation
2.5
Capacitive loads cause increased phase shifts in such a
way that phase margin decreases toward an unstable state
and OSCillating may result. The cure is to overcompensate
the op amp and to isolate the load with a series resistor
(100 to 2000) as shown in F/{Jure 22. For example, an un·
terminated coaxial cable presents a capacitive load. Slight
overcompensation may be required to maintain stability.
i
I
I'.. GASEI
2.0
1
.,.0
15
.
,
~
=70 LCIW t - -
~
'"
-
I
I
AMBlEIIT ' "
-9.i =1~'C/WI
0.5
2&
I
I
I
I
60
7&
......
'"
100
125
150
TEMPERATURE ('CI
TLlH17313-27
FIGURE 23. Maximum Power Dissipation
TLlH17313-25
FIGURE 22. Output Protection
when Driving Capacitive Load
554
Short Circuit Protection
Adjustment of OHset Voltages
Since the LH0024 and LH0032 have no internal short circuit
protection, their relatively high drive capability can sustain
current levels sufficient to destroy the devices if high frequency OSCillation is induced. This can occur with a large
capacitance load. To design in protection, a current limiting
resistor Rsc should be inserted at the output of the amplifier
inside the feedback loop as shown in Figure 22. The value
of Rsc can be determined from the following equation:
V+
Rsc = (6)
Isc
Where: V+ is the power supply voltage.
When required, the offset voltage of the operational amplifiers may be nulled using a balance potentiomater as shown
in F/{/UrB 24. The 1000. series resistors prevent any adverse
oscillation or malfunction when the pot is shorted to either
end of the adjustment range.
+111V
+IIY
Heat SInking Considerations
Under severe environmental and electrical operating conditions, a low thermal resistance heat sink should be used to
assure safe operation. The following is a list of heat sinks
from various sources recommended for the TO-8 case style:
Thermalloy 2240A, ssoC/W
Wakefield 215CB, 30"C/W
IERC, UP-TO 8-48CB, 15°C/W
Heat sinks for the TO-5 case style ere readily available from
many manufacturers. A reasonably priced clip-on unit from
Thermalloy, Model 2228B, offers modest thermal resistance
of 35°C/W.
-15V
-15Y
TVI.f/7313-28
FIGURE 24. Offset Voltage Adjustment
Slew Reaponselmprovement
Slew rate is the internally limited maximum rate of rise, or
fall, at maximum amplifier output swing when driven by a
large Signal step input. It is primarily limited by the operating
current of the input stage. When overdriven by a step fuction, the input stage operating current charges or discharges the effective circuit capaCitance of the second stage.
The rate of charge is:
C_ Grounding
dV = Iinput Stage
dt
CNode
Grounding the case of the device offers improved immunity
from circuit cross-talk, but it compromises additional stray
capacitance to every device pin (usually 1-2 pF). In the rare
situation where case grounding is required, slight recompensation may be necessary. However, most applications are
not demanding enough to warrant its uSe.
There are several ways to strap, or ground the case. For the
LH0032, the best approach is to solder a small metal washer or a small piece of wire between the base of the device
metal can and the base of an unassigned lead post. Dedicating pin 7 of the LH0032 for this purpose is recommanded, although any other "no connection" pin is acceptable.
High tempereture solder should be used to avoid solder'reflow during normal assembly operations.
The LH0024 has no unused pins available, and thus is not
readily adaptable to case strapping. An alternative approach
is to use an electrically conductive heatsink with a PC
board-mountable option, such as Thermalloy type 2230C-5.
In all uses of case grounding, be on the lookout for groundinduced noise into the signal path. In short, be sure the
ground is a quist ground.
(7)
In the case of the LHOO32, where Miller Compensation is
used, the external capacitance adds to the internal circuit
capacitance, resulting in reduced slew rate. Ftgure 25 illustrates this effect as a function of the capacitance value.
1_
'.
DIll
~
\
i7llO
e._
¥S=:t15V
TA=25°C
\
~
~
i-
S:
- -"-
100
•
G
5
10
15 20 25 3D
COMPENSAnOfl CAPACITANCE CC (pF)
TVHI7313-29
FIGURE 25. LHOO32 Slew Rate vs. Frequency
Compensation Capacitance
Power Supply Bypau
Power supply pins must be bypassed in all cases to prevent
oscillation. A 0.01 ",F to 0.1 ",F disc or monolithic ceramic
capacitor at each supply pin to ground is adequate. The
capacitors should be placed no more than Yz inch from the
device pins.
555
26. 27, and 28 demonstrate the rising and falling
slew ca~bilities of the LHOO24 and LH0032.Notice the im"
proved slew rate peformance .of the LHOO32 using the .alternative compensation technique in F/{/IJrB ?8 colI)pared to
Fl{}u/'f127. The difference is due to the smaller MiIIliIr capacitance used in the former.
The LH0024 does not use Miller Compensatiqn. so slew
rate is not compromised. Consequently. large, signet frequency response Is significantly higher than that of the
LH0032.
.
Finally. power supply voltage affects slew rate. As the volt"
age deqreases,. input stage operating current decreases .aqcqrdlngly. The net effect is. a reduction in the slew rate as
the available charging current drops off. Figure 29 shows
the typical slew response of each op amp, as a function of
supply voltage.
FI{}Uf9S
SV
/
•••••••••••••••••••••••••••• ~-.~ FALL
1 ns
10nl
TLlHI7313-30
TL/H/7313-31
FIGURE 26. LHOO24 Slew RespOnse,
Unity Gain Inverting Mode
FIGURE 27. LH0032 Slew Response, .
Unity Gain Inverting Mode, Standard Compenaatlon
(Cc = 10 pF, CA = 100 pF)
5V
I..-.;t.-...t.-...t.-"/j.;;;..
:+.;::
.. ~
.. :;;;
.. :;;;
..
F..:;;;.. ~..;;j.. RISE
;;$.;::
•.•
I'
)'
~V,
71"
tE'-l/-+--+--+-~~-+--+-::~Jo-.~-"'---t
............ .... "yv. ............ . FALL
10nl
FIGURE 28. LH0032 Slew Reaponse, Unity Gain
Inverting Mode, Improved Compensation
.
(Cc = 5 pF, CA = 1000 pF)
1.
LH0024
lIIIO
lIIIO
1
--
7110
e.1IIO
5:
I.
LH0032
.....
.----r--r---r--r---r---.
9110 1-+--I--I--+~:1-~
1•
Av=I_ 1
RL=1kQ
'!A=Z5°C
lIIIO
e. 1IIO t--+--t--+--t--+---I
i&IIOr-+-~-r-+~~
5:
280
1110
o
'!A=21°C
1 700 1-+--11--1---+-+-''-1
~I==~F==I-I~
2801-+--11--1---+-+-'-1
5
1.
1110 I--+-t--+-t--+--I
16
o~~~~~~-~~
20
5
SUPPLY VDLTAIIE (:l:V)
10
15
20
SUPPLY VOLTAGE (:l:Vl
TL/H/7313-33
TL/H/7313-34
FIGURE 29. Slew Rate Response as a Function of Supply Voltages
556
plying these high performance op amps. The ultimate capabilities that can be extracted are a direct function of careful
engineering. With prudence, these devices are harmless indeed.
Settling Time
Settling time Is the time between the start of a step input to
the time it takes the output to settle to within a specified
error band of the final voltage. This parameter is heavily
influenced by the frequency compensation of the amplifier
(degree of damping). Undercompensation results in excessive phase shift, overshoot and ringing, and therefore, a
long settling time. Equally poor performance results from
overcompensation, which yields an overdamped system,
slow decay and, again, a long settling time.
Application of these high performance amplifiers requires an
understanding of compensation and layout technique. With
the information presented in this note, the designer should
be able to enjoy the benefits of their superior capabilities.
REFERENCES
1. National Semiconductor Special Functions Databook.
Expectedly, settling time is affected by the loop gain of the
amplifier. Figure 30 illustrates this effect for these two devices.
2. R. K. Underwood, "New Design Techniques for FET Op
Amps" National Semiconductor AN-63, March 1972.
3. J. Wong, J. Sherwin, "Applications of Wide-Band Buffer
Amplifiers" National Semiconductor AN-227, October
1979.
One of the most demanding applications is driving a capacitive load in a circuit such as a high speed sample-and-hold,
where accuracy and fast settling time are both important.
Because of the additional phase shift introduced by driving
the sampling capacitor, the LH0032 must be recompensat·
ed. Figure 31 presents the optimum compensation to obtain
fastest settling time under these conditions.
4. "LH0082 Optical Communication Receiver" Data Sheet,
National Semiconductor Corp.
5. E. Miller, "Introduction to Practical Fiber Optics" National
Semiconductor AN-244, May 1980.
CONCLUSION
At first glance, the LH0024 and LH0032 seem harmless
enough. A more in-depth look reveals tha challenges in apo
1_
LH0024
.....
Vs=",'1V
TA=U"C
i
'1
.,,.
~
210 f'11 f-
I III
,
780
I: Jf
a
•,
1.'"
111111
o
" =21"C
I-
..,,.
~
Vs-:t15V
100
800
400
I
II.
LHOO32
'01
CI.OIEII LOOP IIAIII (ViVI
I
-llli~"
,.
I.
,ao
'ODO
CUI8EII LOOP IAIIt (VI¥)
Tl/H/7313-35
TLlHI7313-36
FIGURE 30. Settling Time va. Cloeed-Loop Gain
i"'
Vs';'-';'IV
fA =21"c
F
AV-+'
F
a
I
r-
'0
'01
, . '0••
UIAD CAPACITAIICE (pFJ
TLlH/7313-37
FIGURE 31. Frequency Compensation va. Load CapaCitance
557
National Semiconductor
Application Note 255'
P,owetSpec.traEstimation,
,".
. ..~,
1.0 INTRODUCTION
;;.
Perhaps one 'of the thore linportant application areElS' of digital signal prOcessing (DSP) 'is the power Spectralestimlltion
of peiiOdicf and random signals.' Speech recognition prob· .
lems use spectrum analysis as a preliminary meaS!>!ref!'1en~ ,
to perform speee!:! bandwidth reduction and further aeoustip
processing.. Sonar' systems' use sophisticated spectruth
analysis to lOcate' submarirles and surface vli$seIS. Spectral
measurements iii rader are used to obt81n target location
and velOCity information. The vast variety of measllrements
spectrum'analysis encompasses Is perhaps.llmHiess III1d,it
will thus be the intent of this article to provide a brief and
ful)dam!IDta! introduction to theconce~ of pqwer spectral .
estimation.
, '<.'
. '1-:' _
.\
"
Since the'listimation of power speetra'is statiiltieally:based
and covers a' variety of digital signal processing conceptS, .
this article attempts ·to·· proVide sufficient baGkgr6uiid'
throughilts contents and'appendiCes'to allow the discUssion'
to flow void of discontirltlities.· For'fh6se familiar with,the
preliminary.· background ,and seeking a quick introduction
into spectral estimation; skipping to SectionS' 6.0.through
11.0 should suffice to fill their need. Finally, engineers seek·
ing a mor~·:rigorol!!I de.1(ElloPlJ1ept.and newer..tec~niques of
measllring pOl!/er sP~1lI should consult .the excellent refe.r-. '.
ences li,~ec! .in, .4.ppe'1d1x Pan,dpurrent technical. society
publiclltlJ)nS.... "";'
",
As a brie#:summary and quick lookup, refer to tile Table. of
Contents ·of this article.
TABLE OF CONTENT:S
SectIon
Description
1.0 Introduction
2.0 What is a Spectrum? .'
3.0 Energy and PoWer...
4.0 RandOm'Signal$ .
5.0 Fundamentlll Princlples of ~StImatiori Tl1eory
6.0 The Periodogram' .
.. '.
.
7.0 Spectral 'E~~ticin by Averaging Periodograms
8.0 Windows..
."
.. ...} :."
1.0 Spectral !:stimatio!) by U!SIng Windovis to
Smooth a 'Single Periodogram
10.0 Spectral EStImation by Averag1n9
Modified Periodograms
11.0 Procedures for Power Spectral Density Estimates
12.0 Resolution
13.0 Chi-Square Distributions
14.0 Conclusion
15.0 Acknowledgements
Appendix A
. o.serlptlon
A.O Concepts of Probability, Random Variables and
Stochastic Processes
A.1 Definitions of Probailility
A.2 Joint Proba\:iHity'
A.3 Conditional Fir9bability ..
A.4 Probability Density FU!19tion(pdf}
A.5 Cumulative Distribution FunCtion (edt)
A.6 Mean Values; Varianct$ and .St8ndard Deviation
A.7 Functions of Two Jointly DIstritiiJtedRandom
Variables ,';' ,
." .' .' ,'..
., ,
A.8 Joint Cumula~:o!,e Dist~ibI,Jti9~ F~~i:,tIon
A.I Joint Probability Density Function
A.10 Statisticallndependilnce
A.11 'Marginal Distribution and Marginal Density Functions
A.1~
Oete'rlniniStlc, Stationary, Ergodic
A.13 Joint Moments
H . C9rTeiation Functions
ApPend.l~s
B. .Interchanging Time Integration and Expectations
.. 'C. .ConvQluti~n
D. Referen,ce$
'. TerrnihdloQY:
:A.
558
~--------------------------------------------I~
2.0 WHAT IS A SPECTRUM?
A spectrum is a relationship typically represented by a plot
of the magnitude or relative value of some parameter
against frequency. Every physical phenomenon, whether it
be an electromagnetic, thermal, mechanical, hydraulic or
any other system, has a unique spectrum associated with it.
In electronics, the phenomena are dealt with in terms of
signals, represented as fixed or varying electrical quantities
of voltage, current and power. These quantities are typically
described in the time domain and for every function of time,
f(t), an equivalent frequency domain function F(ed) can be
found that specifically describes the frequency-component
content (frequency spectrum) required to generate fIt). A
study of relationships between the time domain and its corresponding frequency domain representation is the subject
of Fourier analysis and Fourier transforms.
The forward Fourier transform, time to frequency domain, of
the function x(t) is defined
FIx(t)] =
f:
00
x(t)ci Cllt dt = X(ed)
and the inverse Fourier transform, frequency to time damain, of X(ed) is
F-1[X(ed)] = - 1
211"
foo
X(ed)eiClltded = x(t)
(2)
-00
(For an in-depth study of the Fourier integral see reference
19.) Though these expressions are in themselves self-explanatory, a short illustrative example will be presented to
aid in relating the two domains.
If an arbitrary time function representation of a periodic
electrical signal, f(t), were plotted versus time as shown in
Figure 1, its Fourier transform would indicate a spectral content consisting of a DC component, a fundamental frequency component edo, a fifth harmonic component 5edo and a
ninth harmonic component 9edo (see F/{/UrB 2). It is illustratively seen in Figure 3 that the superposition of these frequency components, in fact, yields the original time function
fIt).
(1)
,\
\
,,
....
\ SPECTRAL ENVELOPf
TL/H/8712-2
FIGURE 2. Spectral Composition or
Spectrum F(ed) or f(t)
FIGURE 1. An Electrical Signal fIt)
:=
E
j
TL/H/8712-3
FIGURE 3. Combined Time Domain and Frequency Domain Plota
559
f
U'I
U'I
U)r---------------------------------------------------------------------------------~
In
~
4(
3.0 ENERGY -AND POWER
This is only true, however, assutning that the signal itlthe
~em,is impressed acros$,a·10 resil\tOl'. It Is r~aI~ed. for
~xl1inPle. that if fIt) is: a voltage (current) signal applied
acrQSs!l system resi$tan~ R, it!' true insta(ltaneOIl,s power
Would be, expressed as [f(t»)2/R (or fpr.c;:urrent [f(t)12R)
thuS; U(t)Jl!, il! the true povier, only if R ,;" 1O.
In the previous section, time and frequency domain siiinal
functions were related through the use of Foufier transforms. Again, the'same i'elationship Will I>Eimilde in this sectic;m ~ut t,l:le emphas~ will pertain to,~illnl!'~r and!,(l~rgy.
'
"
'"
"
'
So for the ge~ral C!lse, power is always proportional to the
Parseval~s theorem relates the repr8se~tio~ ,of
CII(t), in the time domain to the frequliIllCY, d<1main, by thii
statement
,
'
energy:
, CII(t) =
f~00~1(~)f~(t)dt~J~)1'(f)F2(f)df,
square of the signal a,ntpljtude varied, ~ ,a proJ?Ol1ioilaiity
CQnstant R, the impedance, level in a circuit. In practice,
however, it is, url(,esirabl~' to Carry e)dra constantii)n tt,e
colTJPutation and .customarily for signal analysis, o~' as.
sumes signal measurement across: a 10 resistor..This allOWS' units of power to be, expresSed as
$Quare of the
signal amplitudes .and ,the units 'of energy measured
vQIts2~second (~peres2~second). "
For periodic Signals, equation (5) can be used ,to'
the
average power, PaV9, over a time,interval t2 to t1 by integrating [f(t))2 from t1 to t2 and then obtaining the average ,after,
dividing the result by t2 - t1 or
(3)
where fIt) is an arbitrary signal varying·as a funQtion of time
and F(t) its equivalent Fourier transform reprasentation in,
the frequency domain.'
,
,tbe
The proof of this is simply
J:oo
f:oo
f1(t)f2(t)dt =
define
f1(t)f2(t)dt
(4a)
f'
Letting F 1(f) be the Fourier transform of f 1(t)
f:
00 f1(t)f2(t) dt =
=
f:
,
1
2
Pavg = - f2(t) dt
t2 - t1 11
00 [ f : 00 F1(f)Ei27rlt df ]f2(t) dt (4b)
f:oo
[F1(f)
iis
f:oo
.!. rr f2(t) dt
=
TJo
d27rltdf]f2(t)dt (4c)
(6a)
(Bb)
where T is the period of the signal.
Rearranging the integrand gives
Having established the definitions of this section, energy
can now be expressed in terms of ppwer, P(t);, '
f:oof1(t)f2(t)dt = f:ooF1(f)[f:""f2(t)El2..1tdd df (4d)
CII(t) =
and the factor in the bracketS Is seen to'be F2(";f) (where
F2(-f) = F2" (f) the conjugate of F2(f) so that ',!
f:oof1(t)f2(t)dt
=: f:oo F1(~F2(-f)df
=
!
=
f:
00 f2(t) dt
=
=
f:
f:
00 F(f)F"(f) :df
(58)
00 IF(f)12 df
(5b)
Jo
capacitor
0>(1)
di
= L iii
= (T vidt =
i=
0 dt
-
0
Udt - !L12
2,
c!!
= (T Yidt =
Jo
fT L~ldt fl
"" '
dt
fT YC~dt
0
dt
=
(7b)
pet) = dCII(t)
,
dt
(8)
It was made apparent in previous sections that the use of
Fourier transforms for analysis of linear systems is widespread and frequently leads to a saving in labor.
In view of using frequency domain methods for system analysis, it is natural to ask if the same methods are still applicable when considering a random signal system input. As will
be seen shortly, with some modification, they will Still be
useful and the modified methods offer essentially the same
advantages in dealing w~h random signals as with nonrandom Signals,' ,
','
It is I1Ppropriateto ask if the Fourier transform may be used
for" the analysis .~, anyrandpm sample function. Without
proof. two reasons can lie diScussed which make the transform equations (1) and (2) invalid.
tRecall the energy storage elements
0l(1)
pet) dt
4.0 RANDOM SIGNALS "
In many electrical engineering applications, the instantaneous signal power is desired and is generally assumed to
be equal to the square of the signal amplitudes i.e., f2(t).
v
f:oo
(7a)
As a final clarifying note; again, IF(f)12 and P(t), as used in
equations (7b) and (8), are ~mmonly called throughout the
technical literature, energy density, spectral density. or powef spectral density functiohs, PSD. Further, psb may be
interpreted as the average power associated with a bandwidth of one hertz centered at f hertz.
This simply says that the total energyt In a signal fIt) is
equal to the area under the square of the magnitude of its
Fourier transform. IF(f)12 is typically called the energy density. spectral density, or power spectral density function and
IF(f)I2df describes the density of signal energy contained in
the differential frequency band from f to f + dF.
Inductor
00 [f(t)J2 dt
with power being the time rate of change of enerln'
(4e)
A corollary to this theorem is the condition f1 (t) = f2(t) then
F(-f) = F·(f),the complex conjugate of F(f), and
CII(t)
f:
fV0 cvdv = !ey2"
2
560
and for an ergodic process approaches the mean-square
value of the process as T approaches infinity.
Firstly, X(CII) is a random variable since, for any fixed CII,
each sample would be represented by a different value of
the ensemble of possible sample functions. Hence, it is not
a frequency representation of the process but only of one
member of the process. It might still be possible, however,
to use this function by finding its mean or expected value
over the ensemble except that the second reason netages
this approach. The second reason for not using the X(CII) of
equations (1) and (2) is that, for stationary processes, it almost never exists.. As a matter of fact, one of the conditions
for a time function to be Fourier transformable is that it be
integrable so that,
J:co Ix(t)ldt
<
At this particular point, however, the limit as T approaches
infinity cannot be taken since Xr(f) is non-existent in the
limit. Recall, though, that X,-(f) is a rar:ldom variable with
respect to the ensemble of sample functions from which x(t)
was taken. The limit of the expected value of
2~ IXr(f)12
can be reasonably assumed to exist since its integral, equation (15), is always positive and certainly does exist. If the
expectations E { I, of both sides of equation (15) are taken
(9)
00
E
A sample from a stationary random process can never satisfy this condition (with the exception of generalized functions
inclusive of impulses and so forth) by the argument that if a
signal has nonzero power, then it has infinite energy and if it
has finite energy then it has zero power (average power).
Shortly, it will be seen that the class of functions having no
Fourier integral, due to equation (9), but whose average
power is finite can be described by statistical means.
< ;2 (t) >
2
(12)
(13)
00
The Fourier transform pair of the truncated function xr(t)
can thus be taken USing equations (1) and (2). Since x(t) is a
power signal, there must be a power spectral density function associated with it and the total area under this density
must be the average power despite the fact that x(t) is nonFourier transformable.
Restating equation (5) using the truncated function xr(t)
J : co
x~(t) dt =
J : )Xr(f)12 df
IT Jco
-00
x~(t) dt =
IT Jco
2-00
IXr(f)12 df
(t) = Joo lim
ElI Xr(f)12} df
_ooT-oo
2T
S(f) = lim
E(Xr(f)12}
T_oo. 2T
(18)
(19)
(20)
Recall that letting T - 00 is not possible before taking the
expectation.
Similar to the argument in Section III, the physical interpretation of power spectral density can be thought of in terms
of average power. If x(t) is a voltage (current) associated
with a 1{} resistance, X2(t) is just the average power dissipated in that resistor and S(f) can be interpreted as the
average power associated with a. bandwidth of one hertz
".
..
.
centered at f hertz.
S(f) has the units volts2-second and its integral, equation
(19), leads to the mean square value hence,
(14)
and dividing both sides by 2T
2
ElIxr(f)12} df
2T
The integrand of the right side of equation (19), similar. to
equation (5b), is called the energy density spectrum or power spectral density function of a random process and will be
.
.designated by S(f) where
but that
<
oo
For stationary processes, the time average of the meansquare value is equal to the mean-square value so that
equation (18) can be restated as
x
J:colxr(t)1 dt
= Jco lim
_co T _
where x2 (t) is defined as the mean-square value ( denotes ensemble averaging and < > denotes time I!veraging).
This truncated function is defined so that the Fourier transform of xr(t) can be taken. If x(t) is a power signal, then
recall that the transform of such a signal is not defined
00
(17)
1T Jco E IIxr(f)12} df
-co
(11)
J:co lx(t)1 dt not less than
oo
2
and
x(t) = lim xr(t)
T_oo
(16)
results in
(10)
>T
..!..Jco 2
_lim
2T -cox (t)dt- T _
lim
T_oo
Assuming x(t) to be a sample function from a stochastic
process, a truncated version of the function xr(t) is defined
as
It I ,,; T
It I
{2~ J:oo X~(t)dt} = E L~ J:co Ixr(f)12 df }
then interchanging the integratipn and expectation and at
the same time taking the limit as T _ 00
(15)
gives the left side of equation (15) the physical significance
of being proportional to the average power of the sample
function in the time interval - T to T. This assumes xr(t) is a
voltage (current) associated with a resistance. More precisely, it is the square of the effective value of xr(t)
;2 (t)
561
= J : 00 S(f) df
(21)
For the stationary process, ,the autocorrelation function is
independent of time and therefore
=
N
L
~m-+.oo 2N ~ 1
xn
(34)
n =-N
then for each sample sequence
N
We see then that the special density is the Fouriertransform
of the time average of the autocorrelation function. The relationship of equation (29) is valid for a nonstationary process.
m - < ( » - lim
_1_
xn
-N-+co2N+1
~
£.J
.
n=-N
x(n)
(35)
Since equation (35) is a precise representation of the mean
value in the limit as N approaches infinity then
•
1 N~1
.'
m= N £.J x(n)
n=O
562
(36)
may be regarded as a fairly accurate estimate of m for sufficiently large N. The caret (A) placed above a parameter is
representative of an estimate. The area of statistics that
pertains to the above situations is called estimationthtiory.
Having discussed an elementary statistical estimate,:a few
common properties used to characterize the estimator will
next be defined. These properties are bias, variance and
=
~2 [N{E[X~1l
1
= - E[X~J
consistency.
N
Bias
The difference between the mean or expected value E[~J of
an estimate .q and its true value '1'/ is 'called the bias.
bias = B.q= '1'/ - E[~r
+
(:t (!
E[xJ)
1-
,
0
EbqJ)
](45)
1=0
;""1
N-1
+ {m,J2--
(46)
N
thus allowing the variance to be stated as
0'~ =
x
(37)
(47)
E[(rT!,J2J - {E[mx]}2
=
-E[x:;J
1
,
+ (m2x)N-- - {E[rnx]}2
=
NE[x:;J
1
2
2
+ {mx)-N-m.
The variance of an estimator effectively measures the width
of the probability density"{Appendix A.4) and 'is defined as
=
N (E[xnJ - mx)
(50)
O'~E = [(~ - E[~1l2 ]
=
O'~
(51)
Thus, if the mean of an estimate is equal to the true value, It
is considered to be unbiased and having a bias valve equal
to zero.
"
1
2
N
2
N
N
1
(48)
(49)
Variance
(38)
(~ -, 'I'/}2] = O'~ + B~
2
2
N
This says that as the ,number of observations N increase,
the variance of the sample mean decreases, and since the
bias is zero, the sample mean is a consistent estimator.
'If the variance is to be estimated and the mean value is a
known then
N- 1
A good estimator should have a small variance in addition to
having a small bias suggesting that the probability density
function is concentrated about its mean value. The mean
square error associated with this estimator is defined as
mean square error = E[
1
(39)
1
A2
O'x = N
Consistency
If the bias and variance both tend to zero as the limit tends
to infinity or the n4mber of observations become large, the
estimator is said to be consistent. Thus,
lim
O'~=O
N-+ 00 "/
2
(52)
N-l
(4O)
A2
0'. =
~m-+
00
B.q = 0
,
mx =
1
(41)
; =0
A
m,J2
(53)
N"-l
N~l
N £.. X;
'2
1 ~
E[O'x] = N
(42)
£..
,
(E[x;] - E[rnx])2
(54)
;= 0
;= 0
the mean square value is computed as
I I
~
N £..
{X; 1
;= 0
again ~ i!l the sample mean.
The only difference' between the two cases is that equation
(52) uses the true value of the mean, whereas equation (53)
usas the estimate of the mean. Since equation (53) uses an
estimator the bias can be examined by computing the expected value of ~~ therefore,
'
This implies that the estimator converges in probability to
the true value of the quantity bEling estimated as N becomes
infinite.
In using estimates the mean value estimate of 1TIx, for a
Gaussian random process is the sample mean defined as
=
m,J
this estimator is consistent.
If" further, the mean and the variance are to be estimated
then the sample variance is defined as
and
E[m~J ~2
~
£..{X;
;=0
(55)
E[x;XjJ
(43)
J= 0
Z
~~,[ E~+ ~ ~E~.E~ ].~l
(56)
N-1N-l
I~I
E[x;Xj]
563
)
+
~2 ~ ~ E[x;x~
"' r---------------------------------------------------------------------------------,
~
the expected value
N~1 2, 2 (N~1 2
= N """ EIxI],- N2
""" E(Xd + ,
1
1= 0
1=0
I I
1=0
EIXI]eE1Xj])
j=o
~2(I
+
I+j
ij (NeElxf1) -
(57)
+ N(N -
+ ~2 [NeElxf] + N(N -
= .!. (NeElxf1 )
1)m:]
1)0,: ]
L
(59)
=
ij (NeElxfl) -
~(Elxfl) -
SNxx(f) =
=
1
N
(N -
RNxx(k) d",kT
(71)
(60)
This assumes that x(n) is a discrete time random process
with an autocorrelation function RNxx(k).
For a finite sequence of data
(61)
(72)
(
{ Xn forn = 0,1, ... , N-1
X n) = 0 elsewhere
called a rectangular data window, the sample autocorrelation function (sampled form of equation A.14-9)
(62)
L
2(NN- 1) m:
1) m2
IN·
2
1
2
(N - 1) 2
Elxd) - N(Elxd) - - N - m.
(70)
k= - ...
+ .!. Elx2] + (N N
(EIx~12 ]
S.OTHE PERIODOGRAM
The first method defines the sampled version of the WienerKhintchine relation, equations (31) and (32), where the power spectral density estimate SNxx(f) is the discrete Fourier
transform of the autocorre~tion estimate RNxx(k) or
-1) m2
N2
•
I
(69)
mators. '
(58)
+ ~EIx?] + N(N
N2
(68)
Re-examining equations (63) and (70) as N becomes large
clearly Indicates that the sample variance is a consistent
estimate. Qualitatively speaking,' the accuracy of this estimate depends upon the number of samples considered in
the estimate. Note also that the procedures employed
above typify the style of analysis used to characterize esti-
_ 2N (EIxfl) _ 2N(N - 1) m2
N2
N2·
N
ij [EIx~] -
=
Z'~EIx~eEIxjl)
:2 [NeEIxf]
= EIx~
varl~~] = ElIjI21 - (ElljIl)2
1=0
Elxfl '+
=
ElljI]
so finally
:
00
= (N
~ 1) (Elxfl) _ (N ~ 1) m:
RN,cx(k) =
ij
x(n)x(n
+ k)
(73)
n==-oo
(N - 1) 2
=-N-O'·
can be substituted into equation (71) to give the spectral
density estimate
(63)
It Is apparent from equation (63) that the mean value of the
sample variance does not equal the variance and Is thus
biased. Note, however, for large N the mean of the sample
variance asymptotically approaches' the variance and the
estimate 'virtually becomes unbiased. Next, to check for
consistency, we ,will procead to determine the varlancfl of
the estimate sample variance. For ease of understanding,
assume that the process is zero mean, then letting
N-1
A2
1 ~ 2
(64)
'II = 0'. = N """ XI
(74)
called the perlodogram.
( Note: IX~f)12 = XN(f):N.(f) = JlnT cit>lnT
SNXX(t) =
~ C%00
k
~ 00
From equation (82) it is observed that RNxx(k) is a biased
estimator. It is also considered to be asymptotically unbiased since the term
(77)
x(n)Eit>lnT
N
x(n + k) clt>l(n
approaches 1 as N becomes large. From these observations RNxx(k) can be classified as a good estimator of R(k).
+ k)T)
In addition to having a small bias, a good estimator should
also have a small variance. The variance of the sample autocorrelation function can thus be computed as
and allowing the variable IT' = n + k
SN (t)
xx
= .!.N XN(t)XN'(t) = .!.IXN(t)12
N
(78)
var[RNxx(k)] = E[R~",(k)] - E2[RNxx(k))
in which the Fourier transform of the signal is
XN(t) =
L
(79)
x(n) clt>lnT
:~, ~ E{[ij' I "'-" I.,1
~m"m I.I']} ~
n = - 00
The current discussion leads one to believe that the periodogram is an excellent estimator of the true power spectral
density S(t) as N becomes large. This conclusion is false
and. shortly it will be verified that the periodogram is, in fact,
a poor estimate of Set). To do this, both the expected value
and variance of SNxx(t) will be checked for consistency as N
becomes large. As a side comment it is generally faster to
determine tile power spectral denSity, SNXl\(t), of the random process using equation (74) and then Inverse Fourier
transforming to find RNl\X(k) than to obtain RNxx(k) directly.
Further, since the perioaogram is seen to be the magnitude
squared of the Fourier transformed data divided by N, the
power spectral density of the random process is unrelated
to the angle of the complex Fourier transform XN(f) of a
typical realization.
+
[(£".
1 (N - 1 -Ikl
=N2
+
N - 1 -Ikl
L L
n=O
E[x(n)x(n + Ikl)x(m)x(m + Ikl)] )
E[X1X2Xsl<.!l = E[X1 X2l E[Xsl<.i] + E[X1Xs] E[X2l<.!l
+ E[X1X4l E[X2X3l (87)
(80)
= [ E[x(n) x(n + Ikl)l E[x(m) x(m + Iklll
x(O)x(k)+ x(1)x(lkl+ 1)+ ... +x(N-1-lkl)x(N-1)
+
E[x(n)x(m))E[x(n + Ikl)x(m + Ikll
N
+
E[x(n) x(m + Ikl)) E[x(n + Ikl) x(m))
=~
N-l-Ikl
L
x(n)x(n+lkll
(81)
n=O
k = 0, ±1, ±2, ... , ±N - 1
which averages together all possible products of samples
separated by a lag of k, then, the mean value of the estimate is related to the true autocorrelation function by
E[RNxx(k)] =
(
~
k
N-l-Ikl
)
E[x(n)x(n+ Ikl)]
(82)
= N -lkIR(k)
N
where the true autocorrelation function R(k) is defined as
(the sample equivalent of equation A.14-8)
R(k) = E[x(n)x(n + k))
(86)
m=O
If the statistical assumption that x(n) is a zero-mean Gaussian process, then the zero-mean, jointly Gaussian, random
variables symbolized as Xl, X2, X3 and l<.i of equation (86)
can be described as [Ref. (30)].
Prior to checking for the conSistency of SNl\X(t), the sample
autocorrelation must initially be found consistent Proceeding, since the sample autocorrelation estimate
RNxx(k) =
(84)
Examining the E[RNlQI(k)) term of equation (84), substituting
the estimate of equation (81) and replacing n with m, it fol-
(83)
565
] (88)
:p:
N
UI
UI
where the lag term n· - m- was obtained from the lag dlffer~
ence between T = n - m = ,In +k) - (m + k) In· the
second term of equation (88). The lag term'n - k + m and
n - k - m was obtained by referencing the third term in
equation (88) to n, therefore for
E[x(n) x(m + Iki>]
(91)
the lag term T = n -:- (m + Ikl> so
'
E[x(n).x(m + Ikl>] ... RNlQ(n - m .t- .Ikl)
(92)
and for
(9a)
E[x(n + Ikl) X(II1)]"
first let n - m then add Ikl so T = n - m + Ikl and
E[x(n + Ikl) X(m)] = .RNxx(n - m + ,Ikl)
(941
Recall that a sufficient condition fer an e!ltimatot to be consistent is that its bias and variance both converge to zero.
N becomes infinite. This essentially says that an estimator is
consistent if it converges in probability to the true value of
the quantity being estimated as N approaches infinity.
Re;examining equation (90), the, variance of RN (k), and
equation (82), the expected value of RNlQ(k), it is ~und that
both equations tend toward zero for large N and therefore
RNxx(k) is considered as a consistent estimator of R(k) for
fixea finite k in practical applications.
Having established that the autocorrelation estimate Is consistent, we return to the questiqn of the periodogram c0nSistency.
At first glance, It might s,eem ,obvious that SNlQ(f) should
inherit the asymptotically unbiased and consistent properties of RNlQ(k), of which it Is a Fouriertransfonn. Unfortunately, however, It will be shown that SNlQ(mdoes not' p0ssess these nice statistical properites.
Going back to the power sPectral densitY of equation (71).
Note from equation (98) that thEi periodogram mean is the
discrete Fourier transform of a product of the true autacorrelation function and a triangular window functi9ll. This
frequency function can be expt'essed e!1tirely in the frequency domain by the convolution integral. From equation (98),
then, the convolution expression for the mean power spectral density Is' thus,
'
,
E[SNxx(f)] =
A(f)
f
"
RNxx(k) E-jOlkT
sil, ~2'111)2
['
N]2
: (2'111)
=: N
(100)
81n2-
~~ 00 var[SNioc(f)] =
S2(f) ,
'
U01)
aP-
E[RNlQ(k)] dOlkT
(95)
the substitution of equation (82) into eqUation (95) yields the
mean value estimate
. ': .
N
L
. (99)
More clearly, if the ratio of mean ,to st8nd~ devia~n' is
used as a kind of signal-ta-noise ratio, i.e.
,E[SNxx(f)]
"" S(f) = 1
(102)
Ivar[SNxx(f)ll Yo S(f).
it can be seen, that the true signal spectrum is only as large
as the noise or uncertainty in SNxx(f) for increasing N. In
addition, the variance of equation (101), which also 'is
proximately flPplicable for non-Gaussian sequences, indicates that calculations using different sets of N samples
from the same x(n) process will yield vastly different values
of SNlCl!.(f) even when N becomes I~e. Unfortunately, since
the vanance of SN (f) does not decrease to zero as N approaches infinity, tli'e periodogr~ is thus an inconsistent
estimate of the power spectral density and cannot be used
for spectrum analysis in its present form.
. k=-co
E[SNlQ(f)] =
~ ,.,) d1J
RlHxanilning equatfon (98) or (96) it can be Said that 'equation (71) or (74) gives an asYmptotically unbiased estimate
of' SIt) with the distorting effects of a(k) ,vaniShing as N
tends'toward infinity. At this Point equation (98) still8PPearS
as a good estimate of'the poWer spectral density funCtIon.
For the 'variance var [SNlQ(f)] however, it can be shown
[Ref: (10)]' that If the data sequence x(n) comes from a
Gaussian PI'C!C8SS then the varianCe of SNxX(t) approaches
the squere of the true spectrum, 82(f); at each frequency f.
Helice; the vllriance Is not small for increasing N, '
and determining Its expected value
E[SNlcc(f)] =
1
,
=-aD
k
.
y. S(,.,)A(f
-y.
where the general frequency expr,ession for the transformed
triangular window function A(f) Is
'
co
L
SN~(f) =
f
R(k) ( 1 -
I~I) cjOlkT
" ..
7.0 SPECTRAL ESTIMATION BY
AVERAGING PERIODOGRAMS
It was shoWn'in the last section that the periodogram was
(96)
K= -N
not a consistent estimate of the power spectral density
term of equation (96) can be interpreted as a(k), th$ triangular window resulting from the autocorrelation of' finite-sequence rectangular-data window ",(k) of equation (72).
Thus,'
'
a(k) = {
Ikl,
1
Ikl < N - 1 (97a)
elsewhere (97b)
-oN'
and the expected value of the periodogram can be 'written
as the finite sum
00
E[SNxx(f)] =
L
k=
RNxx(k) a(k) cjOlkT
(98)
-00
586
function. A technique introduced by Bartlett, however, allows the use of the periodogram and, in fact, produces a
consistent spectral estimation by averaging periodograms.
In short, Bartlett's approach reduces the variance of the
estimates by averaging together several independent periodograms. If, for example XI, X2, X3, ... , XL are uncorrelated
random variables having an expected value E[x] and a variance (72, then the arithmetic mean
A
+ X2 + X3 + ... + XL
XI
where A(f) is the Fourier transformed triangular window
function of equation (100). Though the averaged estimate is
no different than before, its variance, however, is smaller.
Recall that the variance of the average of L identical independent random variables is IlL of the individual variances,
equation (51). Thus, for L statistically independent periodograms, the variance of the averaged estimate is
L
A few notes are next in order. First, the L fold variance
reduction or (L) Va signal-to-noise ratio improvement of equation (102) is not precisely accurate since there is some dependence between the subsidiary periodograms. The adjacent samples will correlated unless the process being analyzed is white.
o
+t
{o
s: n s: M ls:ts:L
M _ M)
1 (104)
However, as indicated in equation (110), such a dependence will be small when there are many sample intervals
per periodogram so that the reduced variance is still a good
where the superscript t specifies the segment or interval of
data being observed, the subscript M represents the number of data points or samples per segment and depending
upon the choice of Land M, we have N ;;;, LM. For the
computation of L periodograms
S~(f) i~
=
II
x~(n)
i
Ci",nT 2 1 s:
n=O
t
s:L
approximation. Secondly, the bias of
(105)
gram estimator S~(f) computed from L individual periodograms of length M is thus defined
L
A/I""
l £.J
f L E[S~(f)]
Prior to looking at other techniques of spectrum estimation,
we find that to this point the subject of spectral windows has
been brought up several times during the course of our discussion. No elaboration, however, has been spent explaining their spectral effects and meaning. It is thus appropriate
at this juncture to diverge for a short while to develop a
fundamental understanding of windows and their spectral
implications prior to the discussion of Sections 9 and 10 (for
an in depth study of windows see Windows, Harmonic Analysis and the Discrete Fourier Transform; Frederic J. Harris;
submitted to IEEE Proceedings, August 1976).
(106)
(107)
I = I
= E[S~(f)]
(106),
8.0 WINDOWS
I
SM(f)
I = I
Since the L subsidiary estimates are identically distributed
periodograms, the averaged spectral estimate will have the
same mean or expected value as any of the subsidiary estimates so
L
E[S~(f)] =
S~(f), equation
is greater than S~ (f), equation (105), since the main lobe of
the spectral window is larger for the former. For this situation, then,. the bias can be thought of as effecting spectral
resolution. It is seen that increasing the number of periodograms for a fixed record length N decreases not only the
variance but, the samples per periodograms M decrease
also. This decreases the spectral resolution. Thus when using the Bartlett procedure the actual choice of M and N will
typically be selected from prior knowledge of a Signal or
data sequence under consideration. The tradeoff, however,
will be between the spectral resolution of bias and the variance of the estimate.
If the autocorrelation function RN (m) becomes negligible
for m large relative to M, m > M, t~n it can be said that the
periodograms of the separate sections are virtually independent of one another. The corresponding averaged p8riodo-
SM(f) =
(110)
(98) and (99) S~(f) is asymptotically unbiased, S~(f) can be
said to be a consistent estimate of the true spectrum.
To be more speCific, dividing.an N pOint data sequence x(n),
s: n s: N - I, into L segments of M samples each the
segments X~(n) are formed. Thus,
x(n
l1 var[SNxx(f)] '"' l1 [S(f)]2
So, again, the averaging of L periodograms results in approximately a factor of L reduction in power spectral density
estimation variance. Since the variance of equation (110)
tends to zero as L approaches infinity and through equation
has the expected value E[x] and a variance of (72/L. This
fact suggests that a spectral estimator can have its variance
reduced by a factor of L over the periodogram. The procedure requires the observed process, an N point data sequence, to be split up into L nonoverlapping M point sections and then averaging the periodograms of each individual section.
x~(f) =
I
var[SM(f)] =
(103)
(108)
In most applications it is desirable to taper a finite length
data sequence at each end to enhance certain characteristics of the spectral estimate. The process of terminating a
sequence after a finite number of terms can be thought of
as multiplying an infinite length, i.e., impulse response sequence by a finite width window function. In other words, the
window function determines how much of the original impulse sequence can be observed through this window,
From this, the expected value of the Bartlett estimate can
be said to be the convolution of the true spectral density
with the Fourier transform of the triangular window function
corresponding to the M sample periodogram where M s: NIL
equations (98) or (99) we see that
(109)
567
see F/fJUrBS 48, 4b, and 4c. This tapering by mulitiplying the
sequence by a data window is thus analoQous. to multiplying
the correlation function by a lag window. In addition, since
multiplication in the time domain is equivalent to convolution
in the frequency domain then it is also analogous'to convolving ,tl1le ' Fourier'transform of a, finite-length-seqUence
with the Fourier transform of the window function, FlfJUrBS
4d, 49, and 4f. Note also that the Fourier transform of the
rectangular window function exhibits significant oscillations
and poor high frequency convergence, Figure 49. Thus,
when convolving this spectrum with a desired amplitude
function, poor convergence of the rElsulting amplitude response may occur. This calls for investigating the use of
other possible window functions that minimize some of the
difficulties encountared with rectangular function.
(a)
(d)
(b)
(e)
Ji-,
main lobe, the maximum side lobe' level' should be as small
as possible. Unfortunately, however, both conditions cannot
be simultaneously optimized so that, 'in practice, usable window, functions represent a suitable' compromise betWeen
the' two criteria. A window function in ,which minimization' of
the main iobe width is the primary objective, fields a finer
frequency resolution but suffers from some oscillations, I.e.,
the spectrum pessband and substantial ripple in the spectrum stopband. Coversely, a window function in which minimization of the side lobe level is of primary concern tends to
have a, smoother amplitude response and, very low ripple in
the stopband but, yields a much poorer ffequeilcy resolution. Examining Figure 5 assume a hypothetical impulse response, FlfJUre sa, whose spectrum is Figure 5b. Multiplying
the impulse response by ther~Ctangular window, Figure 4b,
yields the windowed impulse response, FigurS 50, implYIng
the convolution of the windOw spectrum, FiiJure 49, With the
Impulse response spectrum, F/fJure 5b. The result of this
convolution is seen in Figui'B 5d and is a distorted version of
the ideal spectrum, F/fJure 5b, having passband oscillations
and stopband ripple. Selecting another window, i.e., Figure
9 with more, desirable spectral characteristics, we see the
appropriatelY modified windowed data"F/fJure 59, results in
a very good approximation of Figure 5b.
This chllracteristically provides ,a smoother passband and
lower stopband ripple lev,elbul sacrifices the sharpness of
the roll.oft rate inherent in the use of a rectangular window
(compara' FlgiJrBS 5d and 5f). Concluding this brief discussion, a few common window functions will next be ,considered.
"
A(tJ*.(tJ
,(c)
TLlH/8712-5
FIGURE 4
In order for the spectrum of a window function to have minimal effeqts upon the desired amplitude response, resulting
from cO'nvoMng two functions, it is necessary that the window spectrum approximate an impulse function. This implies ti:1at as much of its energy as possible should be concentrated at the center of the spectrum. Clearly,' an ideal
impulse spectrum is not feasible since this ~uiresan infinitely long window.
"
'
In general terms, the spectrum of a window function typically con'sists of a main lobe, representing the center of the
spectrum, and various side lobes; located on either side of
the main lobe (see Figures 6 thru 9). It is deSired that the
window function satisfy two criteria; (1) that the rnilin lobe
should be 'as narrow' as possible and (2) relatil(e to the
(c)
(eI)
(e)
(f)
TLlH/8712-4
FIGURE 5. (a)(b) UnmodlfledOata Sequence
(c)(d) Rectangular Windowed Data Sequence
(e)(f) Hamming Windowed Data Sequence
568
Rectangular window: Figure 6
N -1
w(n) = 1
(111)
Inl < - 2 -
=0
otherwise
Bartlett or triangular window: Figure 7
21nl
N- 1
w(n) = 1 - Inl < - N
2
=0
otherwise
Hann window: Figure 8
(112)
+ 0.5 cos (2~n)
(113)
w(n) = 0.5
=0
Again the reference previously cited should provide a more
detailed window selection. Nevertheless, the final window
choice will be a compromise between spectral. resolution
and passband (stopband) distortion.
Inl < N - 1
2
otherwise
9.0 SPECTRAL ESTIMATION BY USING WINDOWS TO
SMOOTH A SINGLE PERIODOGRAM
It was seen in a previous section that the variance of a
power spectral density estimate based on an N point data
sequence could be reduced by chopping the data into Shorter segments and then averaging the periodograms of the
individual segments. This reduced variance was acquired at
the expense of increased bias and. decreased spectral resolution. We will cover in this section an alternate way of computing a reduced variance estimate using a smoothing operation on the single periodogram obtained from the entire N
point data sequence. In effect, the periodogram is
smoothed by convolving it with an appropriate spectral window. Hence if Sxx(f) denotes the smooth periodogram then,
Hamming window: Figure 9
w(n) = 0.54
2'11'n)
+ 0.46 cos ( iii
=0
N-1
Inl <-2-
(114)
otherwise
Swxx(f)=
f'll
-y.
SNXX(") W(f-,,) d,,=SNXX(")"W(,,) (115)
",In)
N-l
T
"'(.,
N-l
W(1l
TUH/S712-S
TL/H/S712-6
FIGURE 8. Hann Window
FIGURE 6. Rectangular Window
wen)
...en)
~
N-l
T
A
I-I
o
W(f)
I-I
T
N-l
WIf)
TUH/S712-7
TUH/S712-9
FIGURE 7. Bartlett or Triangular Window
FIGURE 9. Hamming Window
569
~ r-------------------------------------------------------------------------~
Bartlett or triangular window
N
where W(f - '1/) Is the spectral window and 'denotes con-
!;
....
volutlon. Since the periodogram is equivalent to the Fourier
transform of the autocorrelation function RNxx(k) then, using
the frequency convolution theorem
:= X(f) 'V('I/ -
,F(x(t)y(t)}
f)
Iml
w(m) = 1 - M i m i :s;; M - 1
= 0
(116)
=I1
otherwise
Hannwindow
where F ( } denotes a Fourier transform, Sxx(f) Is the Fourier transform of the product of RNxx(k) and the inverse Fourier transform of W(f). Therefore for a finite duration window
.
sequence of length 2K. - 1,
Swxx(f)
+ 0.5 cos (M1I"~ 1)
w(m) = 0.5
Rlllxx(k)w(k)c/OIkT
i
w(k) =
=0
(117)
otherwise
w(m) = 0.54
W(f) E/OIkT df
1f'lo
-'10
~
£."
1
= f'lo
-'10
m = -(M -1)
'Assumes M
1
(121)
M-
1
3N
2M[ (0.5)2
~
(0.5)2]
2M[ (0.54)2
~
(0.46)2]
M
311"
M
>
1
segments of M samples each as defined in equation (104),
the L modified or windowed periodogram can be defined as
I~(f) = u~
Rectangular window
Iml :s;;
2M
Welch [Ref. (36)(37») suggests a method for measuring
power spectra which is effectively a modified form of Bartlett's method covered in Section 7. This method, however,
applies the window wIn) directly to the data segments before computing their individual periodograms. If the data sequence is sectioned into
Smoothing is like a low pass filtering effect, and so, causes
a reduction in frequency resolution. Further, the width of the
window main lobe, defined as the symmetric interval between the first positive and negative frequencies at which
W(f) = 0, in effect determines the bandwidth of the
smoothed spectrum. Examining Table I for the follOwing defined windows;
= 0
411"
10.0 SPECTRAL ESTIMATION BY AVERAGING
MODIFIED PERIODOGRAMS
Therefore, it is the adjusting of the length and shape of the
window that allows the variance of Sw (f) to be reduced
xx
over the periodogram.
w(m) = 1
-N
311"
Hamming
(120)
2M
M
M
Hann
W2(f) df
Variance Ratio'
(approximate)
211"
Bartlett
Continuing from equation (119), it is seen that a satisfactory
estimate of the. periodogram re~ulres the variance of
Swxx(f) to be small compared to SNxx so that
/3 <
Width of
Main Lobe'
(approximate)
Rectangular
W2(f)df
w2(m)
otherwise
Window
Function
where N is the record length and 2M - 1 is the total window
width. Note that the energy of the window function can be
found in equation (119) as
=
Iml:s;; M - 1 (125)
TABLE I
L
EOI
M -1
= 0
References (10)(16)(21) proceed further with a dei/elopment to show that the smoothed single windowed periodogram is a consistent estimate of the power spectral density
function. The highlights of the development, however, show
that a smoothed or windowed spectral estimate, Sw (f),
can be made to have a smaller variance than that orthe
stralght periodogram, SNxx(f), by /3 the variance ratio relationship
M-1
Q = var [Swxx(f») ___
1
I'
w2(m)
var [SNxx(f»)
N
m= -(M-1)
(119)
N
+ 0.46 cos (~)
We see once again, as in the averaging technique of spectral estimation (Section 7), the smoothed periodogram technique of this discussion also makes a trade-off between variance and resolution for a fIXed N. A small variance requires
a small M while high resolution requires a large M.
(118)
-'10
= -
Iml :s;; M - 1 (124)
Hamming window
k= -(K -1)
where'
(123)
IL x~(n)
M
-
1
n=O
(122)
otherwise
570
I
wen) cjOlnT 2 1 :s;; I :s;; L (126)
B. 1. Compute the Fourier transform of the data sequence
where U. the energy in the window is
x(n)
M=1
U =ij
L
x(n) X(f)
2. Multiply X(f) by its conjugate to obtain the power spectral density SNlCX(f)
1
SNlCX(f) = NIX(f)12
(74)
(127)
w2(n)
"=0
Note the similarity between equations (126) and (105) and
that equation (126) is equal to equation (105) modified by
functions of the data window wen).
The spectral estimate
is defined as
3. Convolve
W(f)
i'
L
1 ~ I
,M(t) =L ~ ,M(t)
AI
S~(f)
with an appropriate window function
SwlCX(f) = S~(f) • W(f)
(115)
C. 1. Compute the Fourier transform of the data sequence
x(n)
(128)
I = 1
x(n) X(f)
2. Multiply X(f) by its conjugate to obtain the power spectral density S~(f)
and its expected value is given by
~(f) = ~ IX(f)12
where
W(f) =
U~
IL
M
= 1
I
wen) ci.,>nT 2
3. Inverse Fourier transform S~(f) to get R~(k)
4. Multiply R~(k) by an appropriate window function
wen)
5. Compute the Fourier transform of the product to obtain
SwlCX(f)
SwlCX(f) R~(k).w(n)
(117)
Averaging periodograms [Ref. (32)(37)(38)1
A. 1. Divide the data sequence x(n) into L S; N/M segments,
x,(n)
2. Multiply a segment by an appropriate window
3. Take the Fourier transform of the product
4. Multiply procedure 3 by its conjugate to obtain the
spectral density of the segment
5. Repeat procedures 2 through 4 for each segment so
that the averege of these periodogram estimates produce the power spectral density 'estimate. equation
(128)
(130)
" =,0
The nor"lalizing factor U is required' so that Athe spectral
estimate I ~(t). of the modified periodogram. I ~(f). will be
asymptotically unbiased [Ref. (34)1. If the intervals of x(n)
were to be nonoverlapping. then Welch [Ref. (37)] indicates
that
AI
1
1
var[ (f)1 "" car [8NlCX(t)1 '" L [8(t)1 2
(131)
'm
which is similar to that of equation (110). Also considered is
a case where the data segments overlap. As the overlap
increases the correlation between the Individual periodograms also increase. We see further that the number of M
point data segments that can be formed increases. These
two effects counteract each other when considering the variance I~(f). With a good data window. however. the increased number of segments has the stronger effect until
the overlap becomes too large. Welch has suggested that a
50 percent overlap is a reasonable choice for reducing the
variance when N if fixed and cannot be made arbitrarily
large. Thus. along with windowing the data segments prior
to computing their periodograms. achieves a variance reduction over the Bartlett technique and at the same time
smooths the spectrum at the cost of reducing its resolution.
This trade-off between variance and spectral resolution or
bias is an inherent property of spectrum estimetors.
12.0 RESOLUTION
In analog bandpass filters. resolution is defined by the filter
bandwidth. AfBW. measured at the passband half power
points. Similarly. in the measurement of power spectral density functions it is importsnt to be aware of the resolution
capabilities of the sampled data system. For such a system
resolution is defined as
1
AfBW = NT
(132)
and for;
Correlation resolution
1
AfBW=--
11.0 PROCEDURES FOR POWER SPECTRAL
DENSITY ESTIMATES
Smoothed single periodograms [Ref. (21 )(27)(32)]
A. 1. Determine the sample autocorrelation R~(k) of the
data sequence x(n)
2. Multiply RNlCX(k) by an appropriate window function
wen)
3. Compute the Fourier transform of the product
RNxx(k) wen) -
SwlCX(t)
(74)
'"max
(71)
571
"max' = mT. where m
is the maximum value
allowed to produce
the maximum lag
term in the correlation
computation
'"max.
(133)
Fourier transform (FFT} reSolUtion
1
m
1
where P is the record length,
afBW = PL = NT = LT N, the number of data points
and m, the samples within
each L segment,>
N
L =
ij'
Figure 10 shows the probability density function for several
n values and it is important to note that as n becomes large
the chi-square distribution' approximates a Gaussian distribution. We use this X~ distribution in our analysis to discuss
the variability of power spectral densities. If len has a zero
mean and N samples ,of it are used to compute the power
spectral density estimate Set)' then, the probability that the
true spectral density, S(t), lies between the limits
A ~ S(t) ~ B ,
(140)
is
P = (1 - a) = probability
(141)
(134)
Note t!lat ,the above afBW'S can be ,s",bstantially poorer depending upon the choice of the data window. A IQsS in degrees of freedom (Section 13) and statistical accuracy occurs when a data sequence is windowed. That is, data at
each end of Ii record length are given leSs weight than the
data at the middle for anything other than the rectangular
window. This loss in degrees of freedom shows up as a loss
in resolution beceuse the main lobe of the spectral window
is widened in the frequency domain.
Finally, the limits of a sampled data system can be described in terms of the maximum frequency range and minimum frequency resolution. The maximum frequency range
is the Nyquist or folding frequency, f~,
'
fs
1
fe = - = (135)
2 2Ts
where fs is the sampling frequency and Ts the sampling
period. And, secondly, the resolution limit can be described
in terms of a (AfBW) NT product where
1
AIBW ;;, NT
(136)
f(~1
TLlH/8712-10
FIGURE 10
The lower A and upper B limits are defined as
or
(AfBW)NT ;;, 1
(137)
13.0 CHI-SQUARE DISTRIBUTIONS
Statistical error is the uncertainty in power, spectral density
measurements due to the amount of data, gathered, the probabilistic nature of the data and the method used'in dariving
the desired parameter. Under reasonable conditions the
spectral density estimates approximately follow a chisquare, x~, distribution. X~ is defined as the sum of the
squares of Xn' 1 ~ n ~ N, independent Gaussian variables
each with a zero mean and ,unit variance such that
X~ =
,
L X~
N
and
where
2n/2r(~)
[
B';"~
X ;l-i
(143)
respectiVely. X~;" is defined by
X~" =
[v sothat
I ~ f(X~dX~]';'
a
(144)
see
'.
Figure f 1 and the interval A toB is referred to as a
confidenc,e intEjrval. From Otnes and Enrochson [Ref. (35)
pg. 217] the degrees of freedom can be described ~ ,
n = 2(AfBW)NT = 2(AfBW) PL
(145)
(138)
n = 1,'
'1
(142)
n
,
The number n is called the degrees pflreedom and the X~
probability density function is
f(X~ =
A=$
Xn;i
n-2] ~
(X~)T
E 2
(139)
r(~) is the statisticel gamma function (Ref. (14)].
TLlH/8712-11
FIGURE 11
572
and that for large n i.e., n ~ 30 the X~ distribution approaches a Gaussian distribution so that the standard deviation or standard error, EO' can be given by
1
There is thus a 95 % confidence level that the true s~ectral
density funClion S(1) lies within the interval 0.5853 S(1) s;
S(1) S; 2.08 S(1).
As a second example using equation (148) let T = 1 ms,
N = 4000 and it is desired to have (.Msw) desired = 10Hz.
(146)
Then,
NT=4
The degrees of freedom and associated standard error for
the correlation and Fourier transform are as follows:
correlation: n =
~
Eo =
FFT: n = 2M
EO =
~
~
(147)
1
fe = 2T = 500 Hz
(148)
EO
where M is the number of IX(1)12 values
and we thus have a 95% confidence level that the true
spectral density S(1) lies within the limits
0.75 5(1)
l!.fsW = _n_ = 00125 Hz
2NT
.
If it is so desired to have a 95% confidence level of the
spectral density estimate then
P = (1 - a)
X 20; 0.975
A=~=~
15.0 ACKNOWLEDGEMENTS
X 20; 0.025
9.59
34.17
so that
0.5853 S(f)
S;
S;
S(1)
205(1)
9.59
S;
1.395(1)
The author wishes to thank James Moyer and Barry Siegel
for their support and encouragement in the writing of this
article.
yield from Table II
S(1)
S;
14.0 CONCLUSION
B=~=~
S;
S(1)
This article attempted to introduce to the reader a conceptual overview of power spectral estimation. In doing so a wide
variety of subjects were covered and it is hoped that this
approach left the reader with a sufficient base of "tools" to
indulge in the mounds of technical literature available on the
subject.
0.95 = 1 - a
a = 1 - 0.95 = 0.05
205(1)
34.17
S;
It is important to note that the above examples assume
Gaussian and white data. In practical situations the data is
typically colored or correlated and effectively results in reducing number of degrees of freedom. It is best, then, to use
the white noise confidence levels as guidelines when planning power spectral density estimates.
so
X~; 0.975 =
X~O; 0.025 =
= 5.75
X~;o.o25 = 106.63
n = 2(NT) (l!.fsw)
X n; a/2
0.158
a = 1 - P = 0.05
X~;0.975
Choosing T = 100 ms, N = 8000 samples and n = 20
degrees of freedom then
1
fe = 2T = 5Hz
X n; 1 - a/2
~ = ~·N-T-(-l!.-fs7~-)d-es-i-re-d =
N = 2M = 2NT (l!.fSW)deslred = 80
If it is again desired to have a 95% confidence level of the
spectral density estimate then
(149)
M = NT (l!.fSW)desired
and m is the maximum lag value.
An example will perhaps clarify the usage of this information.
the limits
=
2.08 5(1)
573
,'c
TABLE II: Percentage Points of the ChI-Square Dlatrlbutlon
"
n
.
0.010
0.005
5.02
8.63
7.38 ' 9.21
11.34
9.35
11.14
13.28
15.09
12.83
7.88
.. 10.60
12.84
14.86
16.75
.1.24
1.69 ,
2.18
2.70
3.25
1.64
2.17
2.73
3.33
3.94
12.59
14.07
15.51
16.92
18.31
14.45
16.01
17.53
19.02
2Q.48
16.81
18.48
20.09
"21.67
23.21
18.55
20.28
,21.96
23.59
25.19
3.05
3.57
4.11
4.66
5.23
3.82
4.40
5.01
5.63
6.26
4.57
5.23
5.89
6.57
7.26
19.68
21.03
22.36
23.68
25.00
21.92
23.34
24.74
26.12
27.49
24.72
26.22
27.69
29.14
30.58
26.76
28.30
29.82
31.32
32.80
'5;81
6.41.,
7.01
:,7.63
8.26
6;91
7.56
,8.23
8.91
9.59,
7.96
8.67
9.39
10.12
10.85
26.30
27.59
28.87
31.41
28.85
30.19
31.53
,32.85,
34.17
10.,28
10.98
11.69
12.40
13.12
11.59
12.34
13.09
13.85
14.61
32.67
33.92
35.17
36.42
37.65
35.48
36.78
38.08
39.36
40.65 '
38.93
40.29
41.84
42.98
44.31
41.40
42.80
44.18
45.56
46.93
13.84
14.57
15.31
16.05
16.79
15.38
16.15
16.93
17.71
18.49
38.89
40.11
41.34
42.56
43.77
41.92
43.19
44.46
45.72
48.98
45.64
46.96
'48.28
49.59
50.89
48.29
49.64
50.99
52,34
53.67
1
2
3
4
5
0.000039
0.0100
0.0717
0.207
0.412
0.00016
0.0201
0.115
0.297
0.554 '
6
8
9
10
0.68
0.99
1.34
1.73
2.Hi
0.87
1,.24
1.65
2.09
2.56'
11
12
13
14
15
2.60
3.07
3.57
4.07
4.60
16 5.14 :
17 5.70
18 6.26
19 ,6.84
20 7.43
21
2~
23
,24
25
,0.975"., 0.950
.'
8,90,
9:~4
10.20,
10.86
1·1.52,
8.03
8.64
9.26
,9.89
10.52
a
3.84
5.99
7.81
9.49
11.07
0.990
"
'
0.0039
0.1030
0.352
0.711
1.150
0."5
?
..
'.
0:00098
0.050Er
0.216
0.484
0;,831'
0.050
30.1~
0.025
32.00
34.27
33.41
35.72
34.81
37.16
36.19
3M8
37.57 ,40.00
29
30
1M6,
13.12
13.79
12,,20
12.88
13.56
14.26
14.95
40
50
60
70
80
20.71
27.99
35.53
43.28
51.17
22.16
29.71
37.48
45.44
53.54
24.43
32.36
40.48
48.76
57.15
26.51
34.76
43.19
51.74
60.39
55.76
67.50
79.08
90.53
101.88
59.34
71.42
83.80
95.02
106.63
63.69
76.15
88.38
10Q.43
112.33
66.77
79.49
91.95
104.22
116.32
90
100
59.20
67.33
61.75
70.06
65.65
74.22
69.13
77.93
113.14
124.34
118.14
129.56
124.12
135.81
128.30
140.17
26
11.16
,'??
11.81
2~
,
,
574
~
APPENDIX A
Similarly, an event that is absolutely certain to occur has a
probability of one and an impossible event has a probability
of zero.
In summary:
A.O CONCEPTS OF PROBABILITY, RANDOM
VARIABLES AND STOCHASTIC PROCESSES
In many physical phenomena the outcome of an experiment
may result in fluctuations that are random and cannot be
precisely predicted. It is impossible, for example, to determine whether a coin tossed into the air will land with its
head side or tail side up. Performing the same experiment
over a long period of time would yield data sufficient to indicate that on the average it is equally likely that a head or tail
will turn up. Studying this average behavior of events allows
one to determine the frequency of occurrence of the outcome (i.e., heads or tails) and is defined as the notion of
probability.
1.0~P(A)~1
2. P(Al) + P(A2) + P(A3) + ... + PIAn) = 1, for an
entire set of events that are mutually exclusive
3. PIA) = 0 represents an impossible event
4. PIA) = 1 represents an absolutely certain event
A.2 JOINT PROBABILTY
If more than one event at a time occurs (i.e., events A and B
are not mutually excusive) the frequency of occurrence of
the two or more events at the same time is called the joint
probability, P(AB). If nAB is the number of times that event A
and B occur together in N performances of an experiment,
then
Associated with the concept of probability are probability
density functions and cumulative distribution functions
which find their use in determining the outcome of a large
number of events. A result of analyzing and studying these
functions may indicate regularities enabling certain laws to
be determined relating to the experiment and its outcomes;
this is essentially known as statistics.
PIA,B) = N_oo
lim
[nAB]
N
A.3 CONDITIONAL PROBABILITY
The probability of event B occurring given that another
event A has already occurred is called conditional probability. The dependence of the second, B, of the two events on
the first, A, will be deSignated by the symbol p(B)IA) or
A.1 DEFINITIONS OF PROBABILITY
If nA is the number of times that an event A occurs in N
performances of an experiment, the frequency of occurrence of event A is thus the ratio nA/N. Formally, the probability, P(A), of event A occurring is defined as
P(A)=~_oo [r;.:]
p(BIA) = nAB
(A3-1)
nA
where nAB is the number of joint occurrences of A and B
and NA represents the number of occurrences of A with or
without B. By dividing both the numerator and denominator
of equation (A.3-1) by N, conditional probability p(BIA) can
be related to joint probability, equation (A.2-1), and the probability of a single event, equation (A1-1)
(A1-1)
Where it is seen that the ratio nA/N (or fraction of times that
an event occurs) asymptotically approaches some mean
value (or will show little deviation from the exact probability)
as the number of experiments performed, N, increases
(more data).
ij)
Assigning a number,
p(BIA) = (nAB) (
nA
~
N
Analogously
to an event is a measure of how likely or probable the event.
Since nA and N are both positive and real numbers and 0 ~
nA ~ N; it follows that the probability of a given event cannot be less than zero or greater than unity. Furthermore, if
the occurrence of anyone event excludes the occurrence of
any others (i.e., a head excludes the occurrence of a tail in a
coin toss experiment), the possible events are said to be
mutually exclusive. If a complete set of possible events Al
to An are included then
nAl
nA2
nA3
(A.1-2)
"'N+"'N+"'N+
+ P(A2l + P(A3) + ... + PIAn)
= P(A,B)
PIA)
p(AIB) = P(A,B)
PIA)
and combining equations (A6) and (A 7)
p(AIB) P(B) = PIA, B) = p(BIA) PIA)
(A.3-2)
(A.3-3)
(A.3-4)
results in Bayes' theorem
P( IB) = PIA) p(BIA)
~
P(B)
or
P(Al)
(A2-1)
= 1 (A1-3)
575
(A.3-5)
Z
~
en
en
USing Bayes' theorem, it is realized that.if P(A) and P(B) are
statistically Ind8(J8ndent events, implying thet the probability
of event A does not depend upon whether or not event B
has occurred, then p(AIB) = P(A), p(BIA) "" P(B) and
hence the joint probability of events A and B is the 'produCt
of their indMdual probabilities or
P(A,B) = P(A) P(B)
(A,3·S)
More precisely, two random events are statistic811y indepen.
.
dent only if equation (A.3-6) is true.
..
'xCxl
TOTALAREyAi
fxlx""-1
"X2
AREA·
f
C\
'xlxldx
xI
PROIAIILlTY OF OCCURRENCE
IN THE INTERVAL xf TO x2
xI x2
A.4 PROBABILITY DENSITY FUNCTIONS
A formula, table, histogram, or graphical representation of
the probability or possible frequencY of occurrence of en
event associat$d with variable X, is defined as fx(x), the
probability density function (pdf) or probability distJibution
function. As an example, a function corresponding to height
histograms of men might have the probability distribution
function depicted in Figure A.4.1.
0""-
4'
a'
5'
7'
d.'
TL/H/8712-13
,
"
FIGURE A.4.2
Contil1l,liog, since the total ,of all probabilities, of the random
variabl~ X must equal unity and fx(x} dx Is the probability
that Xlies within a specified Interval '
'xlxl
(x -
~)and (x - ~) ,
then,
(A.4-2)
It is important to point out that the density function fx(x) is in
fact a mathematical description of a curve and is not a prob·
ability; it is therefore not restricted to values less than unity
but can have any non-negative value. Note however, that in
practical application, the integral is normalized such that the
entire area under the probability density curve equates to
unity.
.
TLlH/8712-12
FIGURE A.4.1
The probability BlBment, fx(x) dx, describes the prObability
of the event that the random variable X lies within a range of
possible values between '
To summarize, a few properties of fx(x) are listed below.
1. ,fx(x) ~ 0 for all values of x or ~ co· < X <: co
(x-~)and(x+ ~x)
2.
i.e., the area betw~n ,the two points 5'5" and 5'7" shown
in Figure A.4.2 repreSents the probability that a man's height
will be found in that range. More clearly,
3. Prob [(x -
x+-
J, x-"2~fx(X)dx
J
5'7"
Ax
x
+"2 fx(x)dx
Ax
x-2
A.S CUMULATIVE DISTRIBUTION FUNCTION
If the entire set of probabilities for arandoin variable event
X are known, then since the probability element, fx(x) dx,
describes the probability that event X will occur, the accu·
mulation of these probabilities from x = - co to x = co is
unity or an absolutely certain event. Hence,
or
Prob [5'5" s; X s; 5'7") =
~x) s; X s; (x + ~) ]
=J
Ax
(x-~) s;Xs; (x+~x)] =
= 1
,
(A.4-1)
prob[
J:oo fx(x)dx
fx(x) dx
5'5"
Fx(x) J:~ fx(x)dx = 1
576
(A.5-1)
Re-examining Figure A.5.1 does indeed show that the pdf,
fx(x), is a plot of the differential change in slope of the cdf'
Fx(x).
where Fx(x) is defined as the cumulative distribution function (edt) or distribution function and fx(x) is the pdf of random variable X. Illustratively, Figures A.5.1a and A.5.1b
show the probability density function and cumulative distribution function respectively.
Fx(x) and a summary of its properties.
1.0S;Fx(x)S;1
-oo0
00
(A. 10-3)
Fx(x)Fy(y) = Fxy(x, y)
again implies this independence.
(A. 10-4)
1. Fxv(x,y) = Fx(x) Fy(y)
reversible
2. fxv(x,y) = fx(x) fy(y)
3. E[XY] = E[X] E[y]
reversible
non-reversible
When dealing with two or more random variables that are
jOintly distributed, the distribution of each random variable is
called the marginal distribution. It can be shown that the
marginal distribution defined in terms of a jOint distribution
can be manipulated to yield the distribution of each random
variable considered by itself. Hence, the marginal distribution functions Fx(x) and Fy{y) in terms of FXY(x, y) are
(A.11-1)
Fx(x) = Fxv(x, 00)
(A.9-3)
2'
respectively, where the Joint density function fxy(x, y) has
been normalized so that the volume under the curve is unity.
A few properties of the joint probability density functions are
listed below.
1. fxv(x,y)
Fxv(x, y) = Fx(x)Fy(y)
A.11 MARGINAL DISTRIBUTION AND MARGINAL DEN·
SITY FUNCTIONS
analogous to Section A.5. Again fxy(x, y) dxdy represents
the probability that X and Y will jointly be found in the ranges
dx
dy
x ±
and y ±
2
(A. 10-2)
but, the converse is not true Since random variables can be
uncorrelated but not necessarily independent.
In summary
(A.9-2)
J J:
fx(x) fy{y) = fxv(x,y)
It is important to note that for the case of the expected
value E[XY], statistical independence of random variables X
and Y implies
E[XY] = E[XJ E[Y]
(A.10-5)
It is noted that the double integral of the Joint pdf is in fact
the cumulative distribution function
Fxv(x, y) =
(A.10-1)
and
Prob[x1 ~ X ~ x2, Y1 ~ Y ~ Y2] =
YI
fxy(x,y) = fx(x) fy(y)
imply statistical independence of the random variables X
and Y. In the same respect the joint cdf
Xv
XI
Ixv(x,y) dxdy
and
Recall that the pdf is a density function and must be integrated to find a probability. As an example, to liM the probability that (X, y) is within a rectangle of dimension (Xl ~ X
~
and (Y1 ~ Y ~ Y2), the pdf of the joint or two-dimensional random variable must be integrated over both ranges
as follows,
Y2
00
If. the kn.owledge of one variable gives no information $ut
the value of the other, the two random variables are said to
be statistically independent. In terms of the joint pdf .
The probability of occurrence
increases as· either· x or y, or
both increase
A.9 JOINT PROBABILITY DENSITY FUNCTION
X2
00
A.10 STATISTICAL INDEPENDENCE
Similar to the single random variable probability. density
function (pdf) of sections A.4 and A.5, the joint probability
density function fxy(x, y) is defined as the partial derivative
of the jOint cumulative distribution function Fxv(x, y). More
clearly,
d2
fXY(x,y) = dx dy Fxv(x,y)
(A.9-1)
JJ
J~ J~
and
Fy(y) = Fxv( 00 ,y)
respectively.
For all values ofx and y or - 00 < x <
00 and - 00 < y < 00, respectively
fxy(x,y) dxdy = 1
580
(A.11-2)
r---------------------------------------------------------------.~
The marginal density functions 'xIx) and fy(x) in relation to
the joint density fXY(x, y) is represented as
fx(x) =
and
fy(x) =
f: 00
f: 00
fxv(x,y) dy
(A."-3)
fxv(x,y) dx
(A."-4)
A.13 JOINT MOMENTS
In this section, the concept of joint statistics of two continuous dependent variables and a particular measure of this
dependency will be discussed.
The joint moments mil of the two random variables X and Y
are defined as
mii = E[XIYil =
respectively.
where i
A.12 TERMINOLOGY
Before continuing into the follOwing sections it is appropriate to provide a few definitions of the terminology used
hereafter. Admittedly, the definitions presented are by no
means complete but are adequate and essential to the continuity of the discussion.
Determlnl.tlc .nd Nondetermlnl.tlc Random Proc.....
as: A random process for which its future values cannot be
exac\ly predicted from the observed past values is said to
be nondeterministic. A random process for which the future
values of any sample function can be exactly predicted from
a knowledge of all past values, however, is said to be a
deterministic process.
Stationary and Nonatatlonary Random Proca....: If the
marginal and jOint density functions of an event do not depend upon the choice of i.e., time origin, the process is said
to be stationatY. This implies that the mean values and moments of the process are constants and are not dependent
upon the absolute value of time. If on the other hand the
probability density functions do change with the choice of
time origin, the process is defined nonstatlonary. For this
case one or more of the mean values or moments are also
time dependent. In the stri,ctest sense, the stochastic process x(1) is stationary if its statistics are not affected by the
shift in time origin i.e., the process x(1) and x(t + T) have the
same statistics for any T.
Ergodic and Nonergodlc Random Procesae.: If every
member of the ensemble in a stationary random process
exhibits the same statistiCal behavior that the entire ensemble has, it is possible to determine the process statistical
behavior by examining only one typical sample function.
This is defined as an ergodic process and its mean value
and moments can be determined by time averages as well
as by ensemble averages. Further ergodicity implies a stationary process and any process not possessing this property is nonergodic.
Mathematically speaking, any random process or, i.e., wave
shape x(t) for which
I·1m
T-
00
r1m
xm = T
-
1 fT/2
00
T
-T/2
x(t) dt
f:oo f :00 xlyi fxv(x,y) dx
dy (A.13-1)
+ j is the order of the moment.
The second moment represented as 1-'-11 or CTXV serves as
a measure of the dependence of two random variables and
Is given a special name called the covsriancs of X and Y.
Thus
1-'-11 = CTxv = E[(X - X) (Y -
f f: 00
y)]
=
(A.13-2)
(X - i)(y -
y) fxv(x,y) dx dy
= E[XYl - E[XJ E[Y)
(A.13-3)
= m11 - xy
(A.13-4)
or
If the two random variables are independent, their covariance function 1-'-11 is equal to zero and m11, the average of
the product, becomes the product of the indMdual averages
hence.
1-'-11 = 0
(A.13-5)
implies
(A.13-6)
m11 = E[(X - i)(y - Yll = E[X - Xl E[Y - Yl
Note, however, the converse of this statement in general is
not true but does have validity for two random variables
possessing a joint (two dimensional) Gaussian distribution.
In some texts the name cross-covariance is used instead of
covariance, regardless of the name used they both describe
processes of two random variables ea(:h of. which comes
from a separate random source. If, however, the two random variables come from the same source it is instead
called the autovariance or auto-covariance.
It is now appropriate to define a normalized quantity called
the correlation COfIfficient, p, which serves as a numerical
measure of the dependence between two random variables.
This coefficient is the covariance normalized, namely
p=
covar[X,Yl = E{[X - E[Xl] [Y - E[Ylll(A.13_7)
4VartX] vartvl
~CT~ CT~
=2:1L
= E[x(t)l
CTx CTy
holds true is said to be an ergodic process. This simply says
that as the averaging time, T, is increased to the limit
T - 00, time averages equal ensemble averages (the BXpected value of the function).
581
(A. 13-8)
;e
U'I
U'I
DlJe to this time origin indepel'ldence. T'can be set equal·to
-t1. T = -t1o and,substltutlon irito equations (A.14-5a. b)
Rxx(t1.t2) = RXXl
(A.14-11)
would equal the mean square value or total power (AC plus
DC) of the process. Further. for values oUler than l' = O.
Rx!1') re~nts a ..measure of the similarity IMitween its
waveforms x(t) and x(t + 1').
= E(X(t1) x(t21 - X(t1) EIx(t2l1 - EIx(t1)1 x(t21
+ EIx(t1)1 EIx(t2l] I
= EIx(t1)X(t2l1 .:.. EIx(t1)] EIx(t2)]
- EIx(t1)1 EIx(t2l]
'.
+ E[x(t1)] EIx(~) . '. ,
(A.14-3)
or
The autoc:orrelation function ~ defined il) equation (A.14-1)
is valid for both stationary and nonstation8ry processeS. If
x(t) Is stationary then all its ensemble avefages are independent of the time origin and accordingly
(A.14-5a)
Rxx(t1.t2). = Rxx(t1 + T. t2 + T)
(A.14-5b)
= EIx(t1 +
X(t2 +. T)]
n.
582
APPENDIXB
In the same respect as the previous discussion, two random
variables from two different jointly stationary random processes x(t) and yet) have for the random variables
B_O INTERCHANGING TIME INTEGRATION
AND EXPECTATIONS
xl = X(tl)
Y2 = y(tl + T)
the crosscomJlation function
Rxy(T) = E{X(tl)y(tl+T)]
=
f f:
00
If f(t) is a nonrandom time function and aCt) a sample function from a random process then,
[
f ]
(A.14-12)
f::
=
~~)
E [aCt)] f(t) dt
This is true under the condition
x1Y2 f x1Y2 (Xl,Y2) dXl dY2
a)
The crosscorrelation function is simply a measure of how
much these two variables depend upon one another.
Since it was assumed that both random processes were
jointly stationary, the crosscorrelation is thus only dependent upon the time difference T and, therefore
Rxy(T) = Ryx(T)
:~ aCt) f(t) dt
E
f
12 E[ja(t)11If(t)1 dt
11
< 00
(B.0-2)
b) aCt) is bounded by the interval tl to t2. [tland t2 may be
infinite and aCt) may be either stationary or nonstation-
aryl
APPENDIXC
(A. 14-13)
C.O CONVOLUTION
where
This appendix defines convolution and presents a short
proof without elaborate explanation. For complete definition
of convolution refer to National Semiconductor Application
Note AN-237.
For the til7l9 convolution if
f(t)-F(CIl)
(C.O-1)
Yl = y(tl)
x2 = X(tl + T)
and
Ryx(T) = E{y(tl) X(tl +T)l
=
f
(A.14-14)
x(t)-X(CIl)
f:ooY1X2fY1X2(Yl,X2ldyldX2
The time crosscorrelation functions are defined as before by
lim
1 fT/2
Rxy(T)=t_oo-
T
-T/2
x(t)y(t+T)dt
(A.14-15)
yet) =
and
r
Ryx(T) = tl~
1 fT/2
yet) x(t + T) dt
T -T/2
00 -
(C.O-2)
then
f:
(C.O-3)
00
X(T) f(t - T) dT -
Y(cIl) = X(cIl) • F(CIl)
or
(A.14-16)
yet) = x(t) • f(t) proof:
and finally
Rxy(T} = Rxy(T}
(A.14-17)
Ryx(T} = Ryx(T}
(A.14-18)
Y(cIl)
= X(cIl) • F(CIl)
(C.O-4)
Taking the Fourier transform, F[ 1, of yet)
for the case of Jointly ergodic random processes.
F[y(t)]
f: f:
f: f:
Y(cIl) =
00
00
x(T) [
and lettingk = t -
583
[
= Y(cIl) =
T,
00
00
(C.0-5)
]
X(T) f(t - T) dT .,-JOII dt
f(t - T)-JOII dt] dT
then, dk = dtandt = k +
T.
(C.O-6)
Thus,
Y(~)
,=
=
f: [f
00
XC;)
APPENDIXD
:00
f(k; E-
j~(k +,1') dkl d~: (c.o-?)
D;OREFE~ENeES
1. Brigham, E. Oran, The Fast FouriBr Transform, PrenticeHall,1974.
2. Chen, Carson, An Introduction to the Sampling ThBofBm, National Semiconductor Corporation AppliCation
Note AN-236, January 1980.
3. Chen, Carson, Convolution: Digital Signal ProCBssing,
National Semiconductor CO('poration Application Note
AN-237, January 1980.
'
4. Conners, ER., Noise.
5. Cooper, George R.; McGillen, Clare D., Methods of Signal and SystBl71 Analysis, Holt; Rinehart and Winston,
Incorporated, 1967.
.
6. Enochson, L, Digital TechniquBS in' Data Analysis,
Noise Control Engineering, November-December 1977.
7. Gabel, Robert A.; Roberts, Richard A., Signals and LinBBl'SystBms.
8. Harris, F.J. Windo~, Harmonic Analysis and thB DisCfBtB FouriBr Transform, submitted to IEEE Proceedings, August 1976.
9. Hayt, William H., Jr.; Kemmerly, Jack E., EngiflBBling
circuit AnsIysIs, McGraw-Hili, 1962~
10. Jenkins, G.M.; Watts, D.G., 8pBctraJ Analysis and Its Applications, Holden-Day, 1968.
11. Kuo, Franklin F" Network Analysis and·Synthesis, John
Wiley and Sons, Incorporated, 1962.
12. Lathi, B.P.,' Signals, SystBms and CommuniCations,
John Wiley and Sons, Incorporated, 1965.
13. Liu, C.L.; Liu, Jane W.S., Unsar Systems Analysis.
14. Meyor, Paul L., Introductory Probability and Statistical
Applications, Addison-Wesley Publishing Company,
1970.
15. Mix, Dwight F., Random Signal Analysis, Addison-WBSley Publishing Company, 1969.
16. Oppenheim, A. V.; Schafer, R. W., 'Digital Signal Processing, Prentice-Hall, 1975.
17. Otnes, Robert K.; Enochson, Loran, Applied Time BeriBs
Analysis, John Wiley and Sons, Incorporated, 1978.
18. Otnes, Robert K.; Enochson, Loran, Digital Time SeriBs
Analysis, John Wiley and Sons, Incorporated, 1972.
19. Papoulis, Athanasios, The FouriBr Integral and Its Applications. McGraw-Hili, 1962.
20. Papoulis, Athanasios, Probability, Random VariBb/es,
and Stochastic Processes, McGraw-Hili, 1965.
21. Papoulis, Athanasios, Signal Analysis, McGraw-Hili,
1977.
22. Rabiner, Lawrence R.; Gold, Bernard, Theory and Applicstion of Digital Signal Processing, Prentice-Hall, 1975.
f:oo*)ciO>1'dT
f
:00
(C.O-8)
f(k) ci";k dk
Y(CII) = X(CII) e F(CII)
(C.O-9)
F!lf .the frequency convolution of
f(t)-F(CII)
x(t)-X(CII)
then
H(CII) =
..!..
f
27T
00
-00
(C.O-tO)
(C.0-11)
F(v) X(CII - v) dv -
h(t) = f(t) e x(t)
, ,
.
(C.0-12)
or ..
1
H(CII) = - F(CII) • X(CII) h(t) = f(t) e x(t)
(C.0-13)
27T
proof:
Taking the inverse Fourier transform F -1 [ ] of equation
(C.0-13)
h(t) = F-1 [X(CII)2::(CII)]
f
[..!.. f
1
00
27T
-00
27T
=
(C.0-14)
00
-00
(..!..)2
f
.27T
F(v)(CII - v) dV] Eio>1 dCII
00
-~
F(v)
f
X(CII - v) Eio>1 dCII dv
00
-00
(C.0-15)
and letting g
Thus,
= CII -
v, then dg = dOl and CII
= g + v.
F-1 X(CII) • F(CII)
27T
(C.0-16)
h(t) =
h(t) =
(..!..)2
f
27T
..!..
f
27T
00
-00
h(t) = f(t) e x(t)
00
-00
F(v)
f
00
-00
X(g) Ei(g +
F(v) Eivt dvef 00
v)1 dg dv
X(g) Eigt dg (C.0-17)
-00
(C.0-18)
584
23. Rabiner, L.A.; Schafer, A.W.; Dlugos, D., Periodogram
, 'Method for Power Spectrum Estimation, Programs for
Digital Signal Processing, IEEE Press, 1979.
24. Raemer" Harold R., Statistical Communications ThsoIy
and AfipHcations, Prentice-Hall EE Series.
25. Roden, Martin S., Analog and Digital Communications
Systems, Prentice-Hall, 1979.
26. Schwartz, Mischa, Information Transmission Modulation, and Noise, McGraw-Hili, 1959, 1970.
27. Schwartz, Mischa; Shaw, Leonard, Signal Processing:
DIscrete Spectral Analysis, Detection, and Estimation,
McGraw-Hili, 1975.,
32. Steams, Samuel D., ,Digital Signal Analysis, Hayden
Book Company Incorporated, 1975.'
33. Taub, Herbert; Schilling, Donald L, PrincipltJs of Communication Systems, McGraw-Hili, 1971.
34. Tretter, Steven A., Discrst6-Tims 'Signal ProceSSiniJ,
John Wiley and Sons, Incorporated, 1976.
35. Turkey, J.W.; Blackman, A.B., The MlfJSsuremsnt of
Power Spectra, Dover Publications Incorporated, 1959.
36. Welch, P.O., On t//tJ Variance of Tima and Frequency
Averages Over Modifiad Psriodograms, IBM Watscn
Research Center, Yorktown Heights, N.Y. 10598.
37. Welch, P.O., The Use of Fast Fourier Transforms for the
28.' Silvia, Manuel T.; Robinson, Enders A., Digitel Signal
Processing and Time Series Analysis, Holden-Day Inc.,
1978.
Estimation of Power Spectra: A Method BaSed on Tims
AlltJfS{Jing Over Short Psriodograms, IEEE Transactions
29. Sloane, EA, Comparison of linearly and Quadratically
Modifiad Spectral Estimates of Gaussian Signals, IEEE
Translations on AudiO and Electroacoustics Vol. Au-17,
No.2, June 1969.
38. Programs for Digital Signal ProCessing, Digital Signal
Processing Commiff6e, IEEE Press, 1979.
30. Smith" Ralph J., Circuits, Devices, and SysttJlTlS, John
Wiley and Sons, Incorporated, 1962.
31. Stanley, William D., Digital Signal Processing, Reston
Publishing Company, 1975.
585
on Audio and Electroacaustics, June 1967.
39. Bendat, J.S.; Piersol, A.G., Random Data: Analysis and
MlfJSsuremsnt Procedures, Wiley-Interscience, 1971.
~
::
CircuitrY for Inexpensive
Relative Humidity
Measurement
National Semiconductor'
Application Note 256
Of all common environmental parameters, humidify is per-
reveals a cl6se expOnential relationship between the sensor
and relative humidity spanning almost 4 decades of resistance. Linearization of.this curve may be accomplished by
taking the logarithm of the resistance value and utilizing
breakpoint approximation techniques to minimize the residual non-linearities. A further consideration in signal conditioning is that the manufacturer specifies that no Significant DC
current component may pass through the sensor. This device must be excited with an unbiased AC waveform to preclude detrimental electrochemical niigra~ori . .In. addition, it
has .a 0.36 RH uniVOC positive temperature coefficient. The
sensor is a chemically treated styrene copolymer' which has
a surface layer whose resistivity varies with relative humidity. Because the humidity sensitive portion of the sensor is at
its surface, time response is reasonably rapid and is on the
order of seconds.
A block diagram of the concept chosen to instrument the
sensor appears in Ftgure 2. An amplitude stabilized square
wave which is symmetrical about zero volts is used to provide a precision alternating current through the sensor, satisfying the requirement for a zero DC component drive. The
current through the sensor is fed into a current sensitive
(e.g. the input is at virtual ground) logarithmic amplifier,
which linearizes sensor response. The output of the logarithmic amplifier is scaled, rectified and filtered to provide a
DC output which represents relative humidity. Residual nonlinearity due to the sensors non-logarithmic response below
RH = 40% is compensated by breakpoint techniques in
this final stage.
haps the least understood and most difficult to measure.
The most common electronic humidity detection methods,
albeit highly accurate,· are not obvious and tend to be expensive and complex (See Box). Accurate humidity mea~
surement is vital to a number of diverse areas, including
fooclprocessing, paper and lumber production, pollution
monitoring and chemical manufacturing. Desplte,these and
other applications, little deSign oriented matelial. has appeared on circuitry to measure humidity.. This is primarily
due to the small nlimber of transducers available and a generally accapted notion that they are difficult and expensive
to signal condition.
AHhough not as accurate as other methods, the sensor described by the response curve (Figure 1) is inexpensive and
provides a direct readout of relative humidity. The curve
100M
.....
§
'"
1I11III
z
5...
II:
1'-
I.
1M
lINe
J
I
o
10 20 30 40 50 60 70 BI 10 100
RELATIVE HUMIDITY '")
TL/H/8713-1
FIGURE 1_ Phys-Chemlcal Research Corp_
Model PeRC-55 Humidity Sensor
PRECISE
SYMMETRICAL
SOUAREWAVE
RH
SENSOR
CURRENT
SENSITIVE
LOGARITHMIC
AMPLIFIER
SCALING
RECTIFIER
AND FILTER
I....-
ADDITIONAL
LINEARIZING
CIRCUITRY
OUTPUT
rTLlH/8713-2
FIGURE 2
586
~--------------------------------------------------------------.~
The detailed circuitry appears in Figure 3. It is worth noting
that the entire funtion described in Figure 2 requires a small
number of inexpensive ICs. This is accomplished by novel
circuitry approaches, especially in the design of the logarithmic amplifier. The stabilized symmetrical square wave is
generated by A1, ~ of an LF347 quad amplifier. A1 is set up
in a positive feedback configuration, causing It to oscillate.
The output of A 1 is current limited and clamped to ground
for either polarity output by the LM334 current source diode
bridge combination. The LM334 is programmed by the 150
resistor to current limit at about 5 mAo This forces the voltage across the 1200-1.5 kO reSistor string to stabilize at
about ± 8V. Each time A1's output changes state the charging current into the 0.002 p.F capacitor reverses, causing
the amplifier to switch again when the capaCitor reaches a
threshold established by the 1200-1.5 kO divider (waveforms, Figure 4). This circuit's output is buffered by the A1
follower. The amplitude stability of the waveform is dependent upon the +0.33%'OC temperature coefficient of the
LM334. This T.C. has been intentionally designed into the
LM334 so that it may be used in temperature sensing and
compensation applications. Here, the negative 0.3%I"C
temperature dependence of the humidity sensor is reduced
by more than an order of magnitude by the LM334's T.C.
and thermally induced inaccuracy in the humidity sensor's
response drops out as an error term. In practice, the LM334
should be mounted in proximity to the humidity sensor. The
residual -0.03%'OC temperature coefiicient is negligibly
small compared to the sensors ± 1% accuracy specification.
The output square wave is used to drive current through the
sensor and into the summing junction of another ~ of A1,
which is connected as a logarithmic amplifier. On negative
cycles of the input waveform the transistor (Q1) in the feedback loop provides logarithmic response, due to the well
known relationship between VeE and collector current in
transistors. During positive excursions of the input waveform
the diode provides feedback to the amplifier's summing
junction. In this manner the summing junction always remains at virtual ground while the input current is expressed
in logarithmic form by the negative going square wave at the
transistor emitter. Since the summing junction is always at
ground potential the sensor sees the required symmetrical
drive (waveforms, Figure ~.
,.
_RNTRIM
OUTPUT
011-,_
DV-'IVRNTRIM
'oak
SENSOR
1k
,.vo-..IItI.",....-
........._ -.....
'Ilk
=
Sansor PCRC55 - Phys-Chsmlcal Research Corporallon
AI LF347
A2=LF353
LF347 and lF3&3 run on ± '5V supply.
01, 02, Q3 ar. on lM389 chip.
=
.. =1% Molal Film
.. =IN4148
TVH/8713-3
FIGURE 3
587
;
\
The output of this stage is fed ·to another % of A 1. This
amplifier is used to sum in the 40% RH trim and provide
adjustable gain to set the 100% RH trim. The output is filtered to DC and routed to one -half of A2, an lF3S3, which
unloads the filter and provides additional gain and the final
output.
The other Yz of A2 is used to compensate'the sensor departure from logarithmic conformity below 40% RH (Figure 1):
This is accomplished by changing the gain of the' output
amplifier for RH readings below 40%. The input to,the output amplifier is sensed by the breakpoint amplifier. When
this.input goes below RH= 40% (about 0.36V at the output
amplifiers "+.. terminal) the breakpoint amplifier swings
positive. This turns on the 2N2222A, causing the required
gain change to occur at the output amplifier. For RH values
above 40% the transistor is off and the circuits linearizing
function is determined solely by the logarithmic amplifier.
2m./D1V
FIGURE 4
In logarithmic configurations such as this, Ql's DC operating point will vary wildly with tempEirature and the circuit
normally requires careful attention to temperature compensation, resulting in the expense associated with logarithmic
amplifiers. Here, A3, an LM389 audio amplifier IC which also
contains three discrete transistors, is used in an unorthodox
configuration to eliminate all temperature compensation requirements. In addition, the cost of the log function is reduced by an order of magnitude compared to available ICs
and modules. Q3 functions as a chip temperature sensor
while Q2 serves as a heater. The amplifier senses thetemperature dependent VeE of Q3 and drives Q2 to s,ervo the
chip temperature to the set-point established by the 10 kO1 kO divider string.' The LM329 reference ensures power
supply independence of the temperature control. Q1 operates in this tightly COntrolled thermal environment (typically
SO'C) and is immune to ambient temperature shifts. The
LM340L 12V regulator en!!ures safe operation of the
LM389, a 12V device~ The zener at the base of Q2 prevents
servo lock-up during circuit start-up. Because of the' small
size of the chip, warm-up is quick and power consumption
low. Figure 8 shows the th,ermal servo's' performance for a
step function of 7,·C change in set-point. The step is shown
in trace A while the LM389 output appears in trace B. The '
output responds almost instantaneously and complete settling to the new set-point occurs within 100 ms.
I,. .,....................................
10V/D1V 9!lf=;;;j;;;;;;;;;;!;;--\-t--r-=l;=FT-t---i
(50UH) I---t--t--t-+-+-+-'--t--t--+-t
~::t:::h;4:~~$~::::j:~=::j:=I
10 mV/DIY
'~,'--~-+--+--+--4-~--~--~~~
f'"
2ms/D1V
TL/H/8713-5
FIGURE 5
101>....
~--+--+--~~r-~--~-+--+--+--;
LM389
+INPUT
To adjust this circuit,-ground the base of Q2, apply circuit
power and measure the collector potential of Q3, at known
room temperature. Next, calculate what Q3's collector potential will be at SO'C, allOwing -2.2 mVl·C. Select the lk
value to yield a voltage close to the calculated SO·C potential at the LM389's negative input. This can be a fairly loose
trim, as the exact chip temperature is unimportant so long
as it is stable. Finally, unground Q2's base and the circuit
will servo. This may be functionally checked by reading Q3's
collector voltage and noting stability within 100 P,V (O.OS·C)
while blowing on A3.
To calibrate the circuit for RH, place a 35 kO resistor in the
sensor position and trim the 150 kO pot for an output of
10V. Next, substitute an Ii MO resistor for the sensor and
trim the 10k potentiometer for an output of 4V. Repeat this
procedure until the adjustments do not interfere with each
other. Finally, substitute a 60 MO resistor for the sensor and
select the nominal 40 kO value in the breakpOint amplifier
for a reading of RH = 24%. It may be necessary to select
the 1.5 MO value to minimize "hop" at the circuit output
when the breakpoint is activated. The circuit is now calibrated and will read ambient relative humidity when the PCRC55 sensor is connected.
~'....J.~t=t=t:::t::t::::j=t::j::::1
~_
I
1-500mV/DIV~~9F~~~r-+-~~~~
LM3~9
OUTPUT Ip--+--+--~~r-+--~-+--+--+--;
t-~
.....
TLlH/8713-6
FIGURE 6
588
~
HUMIDITY
Humidity is simply water gas. In air the humidity may vary
from zero percent for 9O"F dry air to as much as 4.5 percent
for heavily water laden air at 9O"F. The amount of water air
will hold is dependent upon temperature. RBlBtive humidity
is an expression denoting the ratio of water vapor in the air
to the amount possible in saturated air at the same temperature.
Some of the more common ways of expressing humidity
related information include wet bulb temperature, dew point
and frost point. Wet bulb temperature refers to the minimum
temperature reached by a wetted thermometer bulb in a
stream of air. The dew pOint is the point at which water
saturation occurs in air. It is evidenced by water condensation. When temperatures below O"C are required to produce
this phenomenon it is called the frost pOint.
589
Other measurements and ways of expressing humidity exist
and are useful in a variety of applications. For additional
information consult the bibliography.
BIBLIOGRAPHY
1. "Humidity Sensors"-brochure describing Models
PCRC-11 and PCRC-55 Relative Humidity Sensors. Phys:
Chemical Research Corp.; New York.
2. "Humidity Measurement"-Instrumentation TBChn%gy;
reprint P. R. Wiederhold. Available from General Eastern
Corp.; Watertown, Mass.
3. "Handbook of Transducers for Electronic Measuring Systems"-Norton, Harry N.; Prentice Hall, Inc.; 1969.
4. "Electric Hygrometers"-Wexler, A.; NBS Circular 586;
NBS Washington, D.C. 1957.
5. "An elegant 6-IC circuit gauges relative humidity"-WiIIiams; James M.; EDN Msgazlne, June 5,1980.
~
no
g:
the"
Data Acquisition: Uiln'CI'
ADC0816 arid ADC0817
8.-BitA/D,CQl)verter', ,,<,
with On-Chip 16Ch~nnel
Multipl~xer '"
National Semiconductor
Application,Note 258
Larry Wakeman '" .' . "'. ,.[
,""
.".~
"D
.'
,i [
••
.
,
';
',J.
•
',,1
it
',',',".
I. 'IntrQductlon.
The ADCOS16 and AOCOSn, CMOS,H~-Channel Da~ Ac,
quisition devices are selectable multi·input .S-bit I\fq!lonverters. In add.ition to a standard 8-,bit successive approximationtype AID cohVerter;. thes, d~' C ....--IREF{-)
Tt1H/5624-8
FIGURE 9. Supply-Centered Reference Using Buffered Resistor Divider
595
IV
I
vec
-
TO
REFERENCE
+1 -
CDIII'
REF( + I
MUXOUT
EXlW(SION
-=
=
---1=-
1N2
TO
REFERENCE
AOCII1I
AOCll17
IN6
IN7
INI
INI
IN10
INll
IN12
IN13
IN14
1 - IN15
-
os
02
01
II
CUI
o
C
•
•
A
INO
-IV
vec
cUe
l
C
A
+\V
J. ~
-
IG
IG
I""" 4D
•
A
.
~
'- 1
va. 110
~
-IV'
-
T
veC.
1- 7
u-
If-Af--1- 5
T01IMIDUCEM ! - 4 CD4DIIII
(CIWIIIELI IWIl 1 - 3
INH.
1-'
1-1
I-I
110
1- •
_VII
1Df1Gf-
r-
.INH
VeE
vec
40 f - :: MM74C174:: f--10
10
CLEAR
IV
CUI
C04II518
1- 2
TO"
III1IRFACE
E
0
C
*'r
,-
07
01
01
04
EC-
REF(-I
:-7
-I
-5
TO , - 4
TIAIIIOIICEIII
(CHANNELl 1"141 . - 3
STAIIT
ALE
DE
07
01
01
04
03
02
01
00
INS
1114
TO
TRAIISDUCERS
(CHANNELl 11-111
!DC
EOC
START
ALE
DE
INO
INl
INI
1/
,
ri
--
I--
;;
.t.J
TLfHf58l!4-7
FIGURE 10. Simple 32-Channel AID Converter
596
F. Differential Analog Inputs
An easy, and sometimes overlooked method for implementing a differential input scheme is shown in Figure 11. This
approach actually implements the differential in software. All
16 channels are paired into positive and negative inputs.
Then the controlling logic or microprocessor will convert
each channel of a differential pair, load each result, and
then subtract the two results. This method requires two single ended conversions to do one differential conversion,
hence the effective differential conversion time is twice that
of a single channel or a little over 200 p.S (Ck = 640 kHz).
The differential inputs should be stable throughout both of
the conversions to produce accurate results.
TO
REFERENCE
CHANNEl 1
I
CHANNElzl
CHANNJiL 3\
CHANNEL 4\
CHANNJiL6\
CHANNEl 8 \
CHANNEl 7 \
CHANNEl 8 \
the comparator input to settle. Using the LF353 op amp, this
delay should be about 5 p.s.
G. Input Signal Buffering
There are three basic ranges of input signal levels that can
occur when interfaCing the ADC08161 ADC0817 to the "real
world". These are: a) signals which exceed Vee and/or go
below ground; b) signals whose input ranges are less than
Vcc and Ground, but are different than the reference range;
c) and signals that have an input range that is equal to the
reference range. Each of these situations require different
buffering.
The last situation, case "c" is usually trivial. No buffering is
required unless the source impedance of the input signal is
very high. I! this is the case a buffer may be added between
the multiplexer output and comparator input pins. I! a high
input impedance op amp is used, the input leakage looking
from the multiplexer input can be greatly reduced. This circuit is shown in Figure 13. Using a buffer like this eliminates
the necessity for large capacitors on the multiplexer inputs
(explained later), but these buffers usually require two supplies and can contribute their own conversion errors.
VCc
REF(+1
INO
INI
INZ
IN3
IN4
INS
IN&
IN7
IN8
IN9
IN10
INl1
IN12
IN13
IN14
IN15
I! the input Signal is within the supply, but the reference
cannot be manipulated to conform to the full input range,
the unity gain buffer of Figure 13 can be replaced by another op amp as shown in the Figure 13 inset. This type of
amplifier will provide gain and lor offset control to create a
full scale range equal to the reference.
The third case, c, where the input range exceeds Vee andl
or goes below ground, the input signals must be level shifted before they can go to the multiplexer with the only exception being when the magnitude of the input voltage
range.is within 5V, but outside the 0-5V supply range. In this
case the supply for the entire chip could be shifted to the
analog input range, and the digital signals level shifted to
the system's 5V supply.
A typical example would be bipolar inputs from - 2.5V to
+2.5. I! the ADC0816/ADC0817 have their supply and ref. erence derived as shown in Figure 14, then the ±2.5V logic
outputs need only to be level shifted to 0 and 5V logic levels, Figure 15.
AIICII818
ADC0817
lrftfRFACE
TO
REFERENCE
TUH/56l!4-8
FIGURE 11. Simple 8-Dlfferentlal Channel Converter
A 16 channel differential system can be realized by modifying Figure 10. This is accomplished by changing the
CD4051's addressing and adding a differential amplifier in
between the multiplexer outputs and the comparator input.
The select logic for the CD4051's has been modIfied to enable the switches to be selected in parallel with the
ADC0816/ADC0817. The outputs of the three multiplexers
are connected to a differential amplifier, composed of 2 inverting amplifiers with gain and offset trimmers. A dual op
amp configuration of inverting amplifiers can more easily be
trimmed and has less stringent feed-back resistor matching
requirements, as compared to a single op amp design. The
transfer equation for the dual op amp amplifier shown in
Figure 12 is:
H. Digital Data Acquisition
The ADC0816/ADC0817 make good analog data acquisition subsystems, but there are many instances where these
converters are good digital data acquisition systems as well.
I! a system has unused channels, digitsl inputs can be connected to these channels instead of being separately buffered into the system. In the case of a microprocessor system this could eliminate an I/O port and associated logic.
The speed at which this Input is accessed is one conversion
cycle, but many times this will be fast enough. These inputs
can be used as input switches, power supply indicator devices, or other system status flags. The microprocessor
converts the digital input channel and reads it. Software
then decides whether the input is high enough or low
enough to cause a particular action.
Propagation delay through the op amps should be considered to provide sufficient time between the analog switch
selection and start conversion to allow the analog signal at
597
..
5V
.I
:!'
.
CHANNEL iiI-
;';;'1-
.. I-
lOOK12(I~1
I/O
7
6
-~J
CHANNEL 12
RZ
VCc
CHANNEL II
5
4 C04051B INH
3
C-Z
-1
-0
A-
,,•
VSS VEE
-
-.-
JJE
I/O
111-
5
~
4
3 C04051B INH
1- z
e
I- I
A
1- 0
~
•
~5V
TO
INPUT
INa
INI
IN2
IN3
IN4
IN5
5t
=JVCC
INPUT
ClEAR
DISABLE
,..:0..,
~
t...
rl-
4D MM74C173 4D
3D ~
30
2D
20
lQ
lD IUND eLK
IKQ
COMP
EDC.
START
AlE
DE
ADctII1&
ADC0817
D7
06
05
D4
TO
INTERFACE
LOGIC
03
D2
1111-
INl1
INI2
INI3
INI4
IN15
l-
+sv-
''''.t."
MUX OUT
1l - INe
1- IN7
1- INI
i - IN9
1- IN10
REFEREN~~-
l~'
VCe
REFEREN~~-
DlFF.
V
*
1
r-
4IKRrn'I~Q
.
r--
VSs VEE
1-
.1.
H3
lOOK12 (1%)
-=-
VCC
1- 7
;- 6
. '" lF353
50KQ
~
- 5V
TO
OIFF.
INPUT
1 ~.
'. 1
HI
lOOK12(I%)
01
00
D
C
REF(-)
•A
EXPANSION
GNO
4:.
TlIH/6824-9
FIGURE 12. Differential 16-Channel AID Converter
598
COMPARATOR
INPUT
MULTIPLEXER
OUTPUT
+v
+5V
R
t-----------t
+5
TO
TRANSDUCERS
_-------1
EXIMSION
INO
INI
IN2
IN3
INC
INS
INI
IN7
IN8
IN9
IN10
INll
IN12
IN13
IN14
IN15
UNITY SAIN
AMPLIFIER
MUX OUT
REF(+)
COMP~M_-';';"''''
ADC0811
ADC0817
REF(-)
FIGURE 13. Single Input Ampllfler Buffering
+Y~~~+----------~RU(+)
20 K2 1%
ANAL~I
TRANSDUCERS
2OIIQ1%
INa
INI
IN2
IN3
INC
INS
INI
IN7
IN8
IN9
IN10
INll
IN12
IN13
INI.
IN15
Vec
EDC
MUX OUT
AOC0811
ADC0817
D7
DI
D5
DC
03
D2
Dl
DO '--~ ____ -'~
SHIFTER
Tl/H/5624-10
FIGURE 14.
±2.5V Input Range Data AcqulaHlon
599
IV
~u
. IOKs:!
TO
i '.
.
"
RIO..
. ADCOIIII
.. AIICtII17 . .
IV
MICIOPROCESIOR
OR CONTROL LOGIC
-2.1
MM74C811&
~
II' MM74CIU
+1
+2.5'
fIIIIM·
TO
MICIIDPIIIICE8IOR '
OR CON7IOL LII8IC
ADCDI111ADC0I17
-uv
1-'
FI'GURE 1S. Input/OulpUI Level Shifters
I. Input Considerations
In most instances interfacing analog circuitry is very
straightforward, but there are some constraintS that should
be observed if a reliable accurate syStem design is to result.
One major consideration, input source Impec;lance is actually more complicated than it appears. One would expect that
the input current would be a small D.C. current, but due to
the nature of the comparator, It is not. The A/D's comparator is a capacitor sampling comparator whose input current
is a series of spikes. Figuffl 16 shows a simplified model of
the 'comparator input.
When determining a single bit value during a conversion, 51
will close causing Cc and Cp to charge to the input voltage.
Then 51 is opened and 52 is closed sampling the ladder.
The input current is an AC tranSient charging curr~nt whose
magnitude and duration is dependent on the values of Ce ,
Cp, As, Am and AL. The duration of the transient must be
shorter than the input sample period, and the sample period is dependent on the converter's clock frequency. Thus
the maximum source impedance is dependent on the clock
period. At a clock frequency of 1 MHz, As s: 1k; lind' at
640 kHz, As s: 2k. The source Impedance of potentiometric
transducers vary as a function of wiper positipn. Thus min&.
ducers with a value of s: 10k at a frequency of 640 kHz and
s; 5k at 1 MHz are suilable.
'
.
When a sample-and-hold or SQme othe.r active device is:ln~
serted between the multiplexer and comparator pins, the
output impedance of the ,transducers, are no longer as, re- .
stricted and depend more on the particular Sample/Hold or
op amp chosen. The critical parameter now.isthe source
impedance of the buffer which should,be s; 3k at a clock
frequency of 1 MHz and s; 5 kO with'the clock equal to 640
kHz."
'::'
.If higher impedances are unavoidable; AC charging errors
. can be reduced to an average current error by placing a
.. capacitor= 1 p.F, from the multiplexer input to ground. Add.ing this capacitor will average the transient current spikes
and cause a small DC current IIrror which for a potentiomet. ric transducer is:
VERR =
aAp (liN>. 640CkkHz Volts
where Ap=total potentiometer resistance; IIN=2 p.A (maximum input current at 640 kHz); and Ck=clock frequency.
For a standard buffer source impedance the voltage error is:
Ck
, VER~ = IIN(Asl 640 kHz Volts
where As=buffer source impedance; IIN=2 p.A (maximum
average input current.llt 640 kHz); and Ck=ciock frequency.
In addition, whenever analog signals are present in a digital
system, several prec8\ltions should be exercised to reduce
noise on the analog inputs. The analog Input signals and the
reference input should be kept physically isolated from the
digital signals and a, !lingle point analog ground should be
employed.
J. Protecting the Analog Inputa Against OVer Voltages
be added to limit these currents as shown in Figure 17b, but
this value resistor must be no greater than the values speci·
fied in the previous section.
During normal operation, it is important to keep the analog
input voltages to the multiplexer or comparator between
Vee and Ground to ensure proper operation. There may be
some occasions where over or under voltages cannot be
avoided. Protecting the analog inputs, due to their unique
nature, can be more difficult than digital inputs. The most
effective method is to use extemal Schottky diodes as
shown in Figure 17a. Since the Schottky knee voltage is 0.4
volts the IN5166 diodes of Figure 17a will safely shunt cur·
rents up to several milliamps. To shunt possible currents
larger than several milliamps some series resistance may
ANALOG
SIGNAL SOURCE
A less expensive solution would be to replace the Schottky
diode with some standard switching diodes, Figure 17b, but
since these diodes could only partially shunt the input current from the intemal clamp diodes, some series resistor
should be used as in Ftgure 17c. If the extemal diode must
shunt a large amount of current the two series resistors of
Figure 17d should be used. If the input design is such that
the input can exceed only one supply the diode going to the
other supply can be omitted.
MULTIPUXER
"ON" CHANNEL
COMPARATOR INPUT
Cc
RS
TO
COMP
~CP
FROM SWITCH
TREE
FROM MULTII'lEXER
ADDRESS LllBIC
FROMCOiiTRDL
LOGIC
FIGURE 16. Simplified Multiplexer/Comparator Equivalent Circuit
+5V
+5Y
IN5166
CDNVERTERI
MULTIPLEXER
INPUT
BUFFER
OUTPUT
BUFFER
OUTPUT
IN5166
lKg
CDNVERTERI
MULTIPLEXER
INPUT
IN5166
1N5166
(II
":'
(bl
":'
+5V
+5V
INII4
IN914
lKg
BUFFER
OUTPUT
CONVERTERI
MULTIPLEXER
INPUT
BUFFER
OUTPUT
1"914
50Dg
Hog
CDNVERTERI
MULTIPLEXER
INPUT
IN914
":'
(01
":'
FIGURE 17. Analog Input Protection Circuitry
601
(dl
TUH/5624-12
IV. Signal Conditioning
There are many applications where. it is desirable to add
some signal processing circuitry to improve circuit performance. Typical additions would be filter circuits, sample!
holds, gain controlled amplifiers, and others.• Here again tile
external accessibility of the multiplexer outpUt and comparator input pins can greatly reduce the amount of circuitry required by enabling the use of only one·circuit required by all
16 outputs instead of 1 for each input.
This will switch a resistor in and out of the feedback loop. If
these resistors, R2N: are of different values, different gains
are· realized. These gains are given by:
A microprocessor or some control logic would select a gain
by latching the channel address into a MM74C173. It is important to ensure the output of the LF3568 does not ex~
the power supply, so before a new channel is selected the
gain of the op amp should be reduced to a safe value. The
1k resistor on the output of the LF356 is to help protect the
comparator inputs from accidental over or under voltages.
Two back biased diodes placed from the input to Vee and
Ground (IN914 or Schottky) will offer further protection.
A. Gain Control
Previous examples of gain manipulation have dealt with one
fixed gain for all 16 channels, but there are occ!1sions where
variable gain or selectable gain· may improve accuracy and
simplify hardware and/or softWare.
Figure 18 shows a typical method for gain control. Th!il
CD4051, analog multiplexer, is placed in the feedback loop
of a simple non-inverting op amp. The gain of this op amp is
controlled by selecting one of the CD4051's analog
switches.
+5Y
+5
TO","
INTERFACE
TO
REfERENCE
REF{+1
INO
INI
IN2
IN3
IN4
IN5
IN6
IN7
IN8
INI
INID
INll
IN12
IN13
IN14
INll
EOC
START
ALE
OE
ADCG816
ADC0817
07
De
OS
04
D3
02
01
De
I:T'FACE
0
C
B
REF(-l
A
TL/tj/5624-13
FIGURE 18. Microprocessor Controlled Gain
602
B. Sample/Holds
The only major data acquisition element not included on the
ADC0816 is a sample/hold circuit. If the input signals are
fast moving then a S/H should be used to quickly acquire
the signal and then hold it while the ADC0816/ADC0817
converts it. This circuit can be easily implemented by inserting it between the multiplexer output and the comparator
input.
ADC0817. This is easily accomplished by using the LF398
monolithic sample/hold, as shown in Figure 20. The acquisition time for this part is typically 4 /loS to 0.1 %, and the
droop rate is 20 /loV /converson. This circuit has its own hold
control thus the expansion control is free to be used normally.
The choice of the hold capacitor is critical to the performance of the sample/hold circuit. Some capacitors are composed of dielectrics that will have an initial droop after the
hold is strobed. This is due to dielectric absorption. Polypropylene and polystyrene dielectrics have very little dielectric
absorption and thus make excellent sample/hold capacitors. Such materials as mylar polyethylene have higher absorption properties and should not be used.
The simplest solution is to tie a capacitor on the multiplexer
output and then tie this pin to the comparator input pin. The
expansion control pin is used as a sample control. When
this pin is high one switch is on and the capaCitor voltage
will follow the input. However, when the expansion control
pin is pulled low, all switches are turned off and the capacitor holds its last value, almost. The input bias to the comparator is about 2 /loA (worst case with Ck = 640 kHz). Thus the
droop rate for a 1000 pF is approximately 2000 V /S or
about 0.2 V/conversion. This is totally impractical. If a 0.01
/loF capacitor is used instead then the droop rate is 20 mV,
which may be satisfactory. Unfortunately, the acquisition
time is on the order 100 /loS, or about the length of a conversion.
The problem is that the comparator input leakage is too high
for this sample and hold. To eliminate this, the input can be
buffered by using an LM356B. Figure 19. The leakage, now
due mostly to multiplexer leakages, is reduced to approximately 100 nA. The droop per conversion is typically less
than 1.0 mV per conversion when using a 1000 pF capacitor
and the acquisition time is approximately 20 /loS.
A more accurate solution would be to isolate the capaCitor
from both the multiplexer comparator pins of the ADC0816/
C. Filtering Analog Inputs
Under some conditions the analog input may have come
from a noisy environment and to recapture the original signal some filtering may be required. Typically high frequency
noise must be filtered. The ADC0816/ADC0817 can easily
accommodate the addition of many standard low pass filters. Another useful filter is a 50 Hz or 60 Hz notch filter to
eliminate the noise contributed to the circuit by A.C. power
lines.
It is particularly easy to place a Single passive filter between
the multiplexer output and comparator input pins, but passive filters must be carefully designed to reduce input loading. The filter capacitor will tend to average the comparator
sampling current as mentioned in the Input Considerations
section. To eliminate this, the passive filter can be buffered
by an op amp or an active filter could be used.
REF( +)
COMP
EXPANO
INO
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN1D
1N11
IN12
IN13
IN14
IN15
TO
REFERENCE
SAMPLElIIlIIli
EOC
START
ALE
DE
AOC0816
ADC0817
D7
D6
D5
D4
D3
TOjd'
INTERFACE
D2
D1
DO
D
C
B
A
REF(-)
GND
CK
'::"'
TUH/5624-14
FIGURE 19. Op Amp Sample Hold Circuit
603
~ r-------------------------------------------------------------------------~
i
O~TPUT
+IV
VCc
.MUX OUT
SAMPLE
. COMP I----..;;.-"'M---..J
TO MALaS
TRANSDUCERS
ADC0818
ADC0817
07
06
05
D4
03
02
01
00
TO REFERENCE
TO ",08
CONTROL LOIIC
0
C
8
A
TLlH/5624-15
FIGURE 20. Sample/Hold Converter Using LF398
V. Microprocessor Interface
The interface requirements for the ADCOB16/ADCOB17 interconnection to various microprocessors are essentially
the same as the ADCOBOB/ADC0809 requirements. The davices can be connected to the CPU so that it looks either
like a memory location or I/O port. The data transfers can
be initiated by either an interrupt to the CPU or the CPU can
periodically interrogate the A/D. When trying to implement
an absolute minimum components count system, the I/O
port (as opposed to memory) addressing will usually require
fewer components.
There are several design considerations that apply to most
microprocessor systems when interfacing the ADC0816/
ADC0817. Even though the actual timing of CPU read and
write cycles vary, in general, a microprocessor will output
the address and data (If write operation) onto its busses. A
certain time later the Read or Write strobes will go active. for
a specified time. The interface logic must detect the state of
the address and data busses and initiate the specified action. For the AOC0816/AOC0817 these actions are: 1) load
channel address, 2) start conversion, 3) detect end of conversion and 4) read resultant data. These actions are performed by decoding the read/write strobes, address, and
data information to form the and ALE and START pulses,
then detect EOC, and finally read the data.
For the most part the decoding and strobe generation is
straight forward. The START, ALE, and OE strobes will generally be of the same duration as the CPU read/write
strobes and positive going (ALE can be negative going).
One subtle choice is where to derive the A, B, C, and D
channel select address. These lines can be connected to .
either the address bus or the data bus. The advantage of
connecting them to the data bus is that in minimum systems, more I/O address lines are available for simple decoding. When the A, B, C, and 0 inputs are connected to the
address bus each analog channel becomes a separate I/O
port.
In most designs it is very tempting to tie START andA.LE
together, enabling one pulse to both write the channel address and then start the conversion. However, it is very im:
portant that the signal on the comparator input be stable
before the conversion starts, otherwise the first and most
Important successive approximation could be in error. Usually the START and ALE pulses are the same length as the
CPU read and write strobes which are normally between 0.2
to 1./J-S long. Thus the conversion may start within 1 /J-S of
the address select latching. (Remember the channel Is selected on the rising edge of ALE and the conversion begins
within 8 clock periods of the falling edge of START.) For
converter clocks greater than 500 kHz, 1 /J-S may not be
enough time to allow the analog input signal to propagate
through the multiplexer and any additional signal conditioning circuitry such as buffers, S/H's, etc. There are, however,
a couple of easy fixes that can correct this possible problem. First, the START/ALE pulse could be stretched to the
proper length by using a one-shot (MM74C221 or similar) to
generate a pulse as long as the total delay from multiplexer
input to comparator input. Secondly, the problem can be
circumvented by "double pulsing" the converter. This can
be easily accomplished in software by writing to the
START/ALE address twice. The first pulse latches the desired channel address and starts the conversion. The second pulse must again load the same channel address,
which will not change the multiplexer'S state, and will then
restart the conversion. Of course, the second pulse must
occur after the comparator input has settled.
Even thOugh thil hardware to interface the AOC0816!
ADC0817 to various microprocessors will differ and the system software will vary, the basic routines to operate the
ADC0816/AOC0817 are usually similar. There are many
variations, but Ftguf'8s 21 & 22 illustrate flow charts that
typify these routines. The ADC0816/ ADC0817 is tied directly
604
to the address and data bus (as opposed to using a peripheral controller). Generally, the hardware to create START
and ALE pulses. This does not necessarily have to be true,
but write instructions are conceptually easier and little is
gained by designing the logic such that read instructions
intiate these pulses. The OE pulse must be created by an
I/O or memory read as the converter's data must be read.
A. Interfacing to INS8080
Interfacing the ADC0816/ADC0817to an INSB080 system
is extremely simple, because the INS80801lNS8224/
INS8228 CPU group have separate I/O read (17Ol'I) and I/O
write (!lOW) strobes which imply that the INSB080 has separate I/O addressing. In small systems this means that very
little or no address decoding is necessary. Figure 23 shows
a very simple interface which uses two NOR gates to gate
the I/O strobes with the most significant address bit A7. The
INS8080 has 8 bits of port address which will yield a maximum of 4 I/O ports if inputs A, B, C, and 0 are connected to
the address bus. A MM74C74 flip-flop is used as a divideby-2 to generate a converter clock of 1 MHz. If the INS8080
system clock is ,;; 1 MHz this flip-flop is unnecessary.
The major design consideration is whether EOC should be
polled by the microprocessor or whether EOC should cause
an interrupt. This decision is system dependent, however
the following applications illustrate both methods.
r---- ----.,
I Fr:d1JfMM~\\ I
'----'~---~
......
~'"
.-'"
IS
........ NO
SERVICE
<......
IT ADC0B16/ADC0B17>--+ OTHER
••
~~
DEVICES
........
",'"
YES
OUTPUT ADDRESS
TO A, I, cao INPUTS
AND
PULSE ALE
(LOAD ADDRESSI
OUTPUT AODRESS
TO A. I. C. 0 INPUTS
AND
PULSE ALE
(LOAD ADDRESS)
r---iiEsn---'
I IN~~~UPT I
L---- T-----'
r----:!:----,
I,-__RE-EN;;~ CPU__-,I
!!!'!!RR~..!
r----.----,
I
WAIT FDR
EDC TO ao LOW
I
I
I
'-----T-----'
r----~----,
ENABLE
I
I
L
INTERRUPTS
--=~----
~UTE PRODIIAM
-
...1
I
·THESE lLOCU UIED ONLY WHEN EDC
TIED DIRECTLY TO CPU INTERRUPT INPUT
··THEBE BLOCU UIED ONLY WHEN
MULTIPLE INTERRUPTI ARE
WlRE-DRED TOIETHER
···THII lLOCK UIED WHEN INTERRUPT
FLIP-FLOP Mun IE RElET
IY SOFTWARE
•..·INTERRUPTS MAY IE ENAlLED ANY
nME AFTER DEVICE INTERRUPT 18 RESET
TL/H/56.24-16
FIGURE 21. Flow Chart for Interrupt Control
of ADC0816/ADC0817
FIGURE 22. Flow Chart to Control ADC0816/ADC0817
In a Polled I/O Mode
605
+IV
MUXOUT
COMP
, TO
IlU£RENCE
REI'l+ I
- .....--17DW
_..r---
- .....--'--17lI1I
ADC0818'
ADC0817
A7
D7 I~::::===== DUl7
UI
D5~~~~~~~
D4
D3
D2
~
DO
D4
D3
D2
os
IN8101D
DATA BUI
~
DO
~
REfEREN~
AI} IN8BDBD
B~=====: ~A01 =:usa
A I-
~ (,YITEM CLOCK." ." 2 MHII'
Va 74C74
TLlH/5624-17
FIGURE 23. Simple INS8080/8224/8228 to ADC08161ADC0817 Interface
Typical software would first write the channel address to the
converter and start it. As mentioned before, two start pulses
should be sent to the ADC08161 ADC0817 to allow the comparator input to settle. After the second start pulse the CPU
could execute other program segments until it is interrupted
by EOC going high. Depending on the interrupt structure,
program control would then be given to the interrupt handler
which reads the converter's data.
data is read which may seem unusual, but can actually be
useful if the converter is to be continually restarted upon
completion of the previous conversion. Address bit A6 Is
used to derive a strobe which will place EOC on the data
bus to be read by the CPU.
F/{/ure 26 uses a 6 bit comparator to decode A4-A7 and
iOREO. Two NOR gates are used to gate the ALE/START
and OE pulses. This design functions the same as F/{/ure 23
except that the DM8131 provides much more decoding.
The second interface circuit, Figure 24 utilizes a DM74LS139
dual 2-4 decoder in which one-half of the chip is used to
create read pulses and the other half write pulses. The
START and OE inputs are inverted to provide the correct
pulse polarity. This interface partially decodes A6 and A7 to
provide more 1/0 capabilities than before. This circuit also
implements a simple polled 110 structure. The EOC output
Is placed on the data bus by a TRI-STATE inverter when the
inverter is enabled by an INS8080 read.
C. Interfacing to the NSCSOO
The NSC800 interface is actually very similar to the
INS8080 110 interface, even though their timing is very different. The NScaOO multiplexes the lower 8 address bits on
the data bus at thjl beginning of each cycle. When accessing memory, AO-A7 must be latched out at the beginning of
a read or wri~ cycle, but for 110 accessing; the NScaoO
duplicates the!l bit 110 addresses on A8-A15 address lines
and latches are not necessary since these lines aren't multiplexed. The 110 read and write strobes are derived from a
RD (read) and WR (write) line and the 10/tJ signal.
B. Interfacing to the Z80 11D
The Z80, even though architecturally similar to the INS8080,
uses slightly different control lines to perform I/O reads and
writes. In Figure 25 a NOR gate approach similar to FIgure
22 is shown to interface the Z80 to the ADC0816/
ADC0817. Instead of l70R and flOW strobes the Z80 has
Frn (read) and WFi (write) strobes which are gated with
KmEO (110 request). In the Z80 interface, to show a slight
variation, START is connected to OE instead of ALE. This
will cause a new conversion to be started whenever the
F/{/Ure 27 shows a design using a dual 2-4 line decoder
which decodes A15, and A14 and is enabled by the read/
write strobes. TRI-STATE Inverters are used to implement a
scheme similar to FIgure 24. This scheme has START and
ALE accessed separately so that "double pulsing" isn't required.
606
):.
Z
•
+5V
N
OM74LS139
7D SIGNAL
PROCESSING
TO
REFERENCE
TO
TRANSDUCERS
I
VCC
MUX OUT
EXPANSION
EOC
CI'I
CD
IIOW
COMP
REF(+)
IIOR
A7
AB
START
INO
INI
IN2
IN3
IN4
IN5
INB
IN7
IN8
IN9
IN10
INll
IN12
IN13
IN14
IN15
DE
AOC0816
AOC0817
07
06
05
04 INS8080
03 DATA BUS
02
01
00
07
06
05
04
03
02
01
DO
0
C
B
A
TO
REFERENCE
A3 OR
A2 DR
Al DR
AD DR
1
03 INS8080
02 DATA DR ADDRESS
01 BUS
DO
cf>2(SYSTEM CLOCK 0 ,; cf> ,; 4 MHz
NOTE: PULL·UP RESISTORS SHOULD BE
ADDED 7D CMOS INPUTS TO IMPROVE TTL COMPATIBILITY
FIGURE 24. Partial Addre•• Decoding INS8080/8224/8228 to ADC08161 ADC0817
+5V
Vec
MUX OUT
EXPANSION
EOC
OM74LSI25
A6
ALE
iDREG
REF(+)
WI!
START
RD
DE
AOC0816
AoeOB17
A7
MM74C12 OR OM74LS12
07
07
06
05
04
03
02
01
DO
os
05
04
03
02
01
DO
0
C
B
A
7D
REFERENCE
ZlO
DATA BUS
A30R03\
A2 DR 02 ADDRESS DR
Al DR 01 DATA BUS
AD DR DO
MM74C74 OR OM74LS74
4I2(Z80 CLOCK 0 " 41" 4 MHz)
NOTE: PULL·UP RESISTORS SHOULD BE
ADDED TO CMOS INPUTS 7D IMPROVE
TTL COMPATIBILIlY
TL/H/5624-18
FIGURE 25. Simple Z80 Inter1ace to ADC0816/ADC0817
607
+5
+5V
TO
REFERENCE
REF( +)
OUT
ADC0816
AOC0817
07
D6
D6
TO
TRANSDUCERS
TO
REFERENCE
117
06
05
04
04
03
02
01
DO
03
02
'="
D1
00
0
C
I
A
REfI-)
IND
ZI8
DATA BUS
IND
:jADORESS
AI 8US
AD
NDTE: PUU.-UP RESISTORS SHOULD IE
ADIIEII TO CMOS INPUTS TO IMPROVE
TTLCOMPAnllUlY
FIGURE 26. Decoded zao Interface
+8
74LS166
lYO
lYl
In
1YS
2Y0
2Yl
2YS
m
ADC0816'
AOCOI17 '
07,"========= A06
A07
08'"
os
ADI
04
A04
03
A03
02
01
AD2
ADI
DO
Cl
B2 I---"",,RD'
C2 ......---....&...-10/.
snECT I 1-'::"'-All'NSC81111
ADUIIES. IU8
SELECT A I-~_ A14
NSCBOO
DATA IUS
ADO
oC
A11
AID OR
OR ADS!
AD2 :mESS IUS
:
TO
REFERENCE
'1 1----.
:: : :O~
DATA BUS
DM74L874
NDTE: PULL-UP RESISTORS INOULD IE
ADDED TO CMOS INPUTS TO IMPROVE
TTL COMPATIBILITY
TLlH/5B24-19
FIGURE 27. PartlaUy Decoded NSCIOO to ADC0816/ADC0817 Interface
608
starting a new conversion. Since EOC is directly tied to the
interrupt input, the controlling software must not re-enable
interrupts until 8 converter clock periods after the START
pulse when EOC is low.
The next design, Figure 28, uses the same simple NOR
gating scheme as Figure 23, except the NSC800 control
signals are Slightly different. A Simple interrupt scheme for
EOC is employed using an MM74C74. When E09 goes high
the flip-flop is set and j]\J'ffj goes low. When the NSC800
acknowledges the interrupt by lowering iNfA, the flip-flop
will reset. If more than one interrupt can occur simultaneously either mTA should be gated with EOC, or some
other signal instead of INTA must be used. This is required
since it is possible for the NSC800 to detect another interrupt and clear the ADC0816/ADC0817 interrupt before it's
detected.
The memory control signals are very different from the
INS8080 type CPU's. One line indicates whether the operation is a read or write, R/W instead of separate read/write
outputs on the INS8080/Z80INSC800. This signal along
with VMA indicates a valid read/write operation.
Figure 30 is slightly more complex, but provides more I/O
port strobes. A NAND gate and inverter are used to decode
the addresses, VMA and <1>2 clock. The I/O addresses are
located at 1111 OXXXXXAABBBB (Binary); where X = don't
care; A = 00 (Binary) for ALE write or IREO resetlEOC read
and A=01 for START write or Data read; and B=channel
select address if A, B. C and D are connected to the address bus and ALE is accessed. A dual 2-4 line decoder is
used to generate these strobes and inverters are used to
create the correct logic levels.
D.lnterfaclng to the 6800
The 6800 has no separate I/O addressing capabilities, so
the system 110 must be addressed as thouQh it is memory.
As mentioned before, memory mapping can require more
address decoding in order to separate memory from I/O,
but in small systems very minimal parts count is still attainable.
The 6800 supports only a wired-OR interrupt structure. In a
multi-interrupt environment only one interrupt is received
and the interrupt handler routine must determine which device has caused the interrupt and service that device. (Although the INS8080/Z80INScaOO can implement a similar
structure, hardware interrupt controllers can also be used
which will automatically vector the ",p to the correct service
routine.) To do this EOC is brought out to the data bus so
the CPU can check It.
F/{/ure 29 illustretes an interface which uses a DM8131
comparator to partially decode the A 12, A 13, A 14, and A 15
address lines with the <1>2 clock and Valid Memory Address
(VMA). to provide an address decode pulse for the two NOR
gates which in tum generate the START/ALE Pulse and the
output enable signal. This design will locate the AID in one
4k byte block.
This design tied EOC to 1RE<:i interrupt through an inverter.
This is only usable in single interrUpt systems since
the 6800 has no way of resetting this interrupt except by
+5V
10/.
ill
iii
A15
ADC0818
AIIC08I7
TO
TRANSDUCERS
5~~~
f:::
02",,=====
03
011-
DDi--------
TO
IIEFEIIENCE
ig~~~~~~~ E: J
L...-""""""Il-ia
NGTE: PULI.-IIP RESISTORB IHDULD BE
ADDED TO CMOS INPUTB TO IMPROVE
AD7
AD8
AD8
AIM
AD3
AD2
AD1
ADD
ex
NICIDD
DATA BUB
ADDREI.IUB
Y,·.M74C74
II
m caMMTIBIUlY
TLlH/5624-20
FIGURE 28. Minimal N$C8oo to ADC0816/ADC0817 Interface
609
iJiaI
+1iV
+1
1=
EXl'MSION
":'
RlW
EGC
+IY
ALE
IND
INI
INZ
INa
IN4
~
07
ADCD817
ADC0818
1~7
04
IN8
IN9
INID
~§§§~~~ D8DB
07
"""=::::==
:l=====
:~:;,;;,;;;;=:
IN12
IN13
IN14
IN15
VIM
OUT
oa
021-
IN11
TO
REfERENCE
.,
OE
IN5
INI
TO
TRANSDUCERS
All
A14 \ &lIOII
A13 ADDRESS IUS
A12
START
DC
OS
DZ
01
DO
":'
IIOD DATA IUS
0\------
REF(-I
ClK
a
a
NOTE: PUll·UP RESISTORS SHOULO IE
ADDED TO CMOS INMS TO IMPROVE
TTL COMMnllUTY
AI
All
~
1880
AODREIS IUS
CK
.z (18GO CLOCK 0" . " 1MHzI
0
FIGURE 29. 6800 to ADC0816/ADC0817 Interface
5V
COMP
TO,
REFERENCE
TO
TRANSDUCERS
TO
IW'ERENCE
Al1
ALE
REF(+I
INa
INI
IN2
IN3
INC
INI
INI
IN7
IHI
INI
INID
INl1
IN12
IN13
IN14
IN15
START
DE
ADCDB11
ADCDB17
07
07
DB
D8
05
04
OS
02
01
DO
D8
DC
OS
02
01
DO
0
C
I
A
REF(-I
CLK
I8GO
DATA IUS
AI DR 031'
AlDRDZ =OR
AI DR 01 ADDRESS IUS
AI DR !III
.'
'IIMM74C74
.z (IIOD CLOCK 0"." 1 MHzl
NOTE: PULL·UP RESISTORS SHOULO BE
ADDED TO CMOS INPUTS TO IMPROVE
nL COMMTlIIUTY
TUH/5624-21
FIGURE 30. Partially Decoded 6800 to ADC0816/ADC0817 Interface
610
F. Parallel Interface Circuits
In some cases p.P support chips can be used to interface
the ADC0816/ADC0817 to microprocessors. Most parallel
1/0 chips can be used, and provide enough flexibility to enable all functions to be under software control. Typical parallel 1/0 chips that could be used are INS8255, 6820, Z80PIO and others. Typically these support IC's would be connected directly to the data and control pins and the software
would manipulate the START and ALE pins via the interface
chip. In some cases the chips provide handshaking andlor
interrupt capabilities which can ease the converter interface.
In some cases, the interface circuits will not provide a clock,
and therefore must be provided externally.
While use of parallel 110 circuits simplify designs and increase versatility, they are more expensive than the 1 or 2
611
SSI or MSI circuits that they would replace, and thus not
always the best choice.
VI. Conclusion
The ADC0816/ADC0817 are easy to use general purpose
AID converters with the additional benefit of a 16 channel
analog multiplexer. The IC's can become a simple standard
8-bit data acquisition circuit or the basis of a more powerful
data acquisition system. Both integrated circuits provide
features to enable easy microprocessor interface, yet also
allow hardwired control logic to be used. In those applications which require less accuracy, the less expensive
ADC0817 can be used to reduce overall system cost.
C)
~ A 20-Bit (1 ppm) Linear
cc Slope-Integrating AID
Converter
By combining an "inferior", 20 year old AID conversion
technique with a microprocessor, a developmental AID
convener achieves 1 part-per-million (20-bit) linearity. The
absolute accuracy of the cor'IVerter is prilllarily limited by the
voltage reference available. The precision achieved by the
unlikely combination of technologies surpasses conventional approaches by more than an order of magnitude. The
approach used points the way towards a generation of
"smart" converters, which would feature medium to high
resolution (12 bits and above) with high accuracy over extended temperature range. The conversion technique employed, while slow speed, suits transducer based measurement systems which require high resolution over widely
varying conditions of time and temperature. In addition, extensions of the basic converter have achieved 15-bit digitization of signal inputs of only 30 mV full-scale with no sacrifice in linearity or stability. This offers the prospect of an
"instrumentation converter" which could interface directly
with low level analog signals.
One of the many AID techniques utilized in the late 50's and
early 60's was the single-slope-integrating converter. One
form of this circuit compares a linear reference ramp to the
unknown voltage input (see About Integrating Converters
and CapaCitors). When the ramp potential crosses the unknown input voltage a comparator changes state. The
length of time between the start of the ramp and the comparator changing state is proportional to the input voltage.
This length of time is measured digitally and presented as
the converter output. The inherent strengths of this type of
converter are simplicity and high linearity. Although singleslope-integrators were used In early AIDs and voltmeters
their dependence on an integrating capaCitor for stability
was considered an intolerable weakness. The advent of the
dual-slope converter (see About Integrating Converters and
Capacitors) solved the problem of integrating capaCitor drift
with time and temperature by error cancellation techniques.
In a dual-slope converter the output represents the ratio of
the time required to integrate the unknown voltage for a
fixed time and then, using a reference voltage of oppOSing
polarity, measures the amount of time required to get back
to the Original starting pOint (see About integrating Converters and Capacitors). The technique eliminates capaCitor
drift as an error term.
Umltatlons of Dual-5lope Converters
The dual-slope converter, and variants on it, have been refined to a point where 16 and 17-bit resolution units are
available. A primary detriment to linearity in these converters is a parasitic effect in capaCitors called dielectric absorption. Dielectric absorption can be conceptualized as a
slight hysteresis of response by the capaCitor to charging
and discharging. It is influenced by the recent history of cur-
National Semiconductor
Application Note 260
rent flow in the capaCitor, including the magnitude, duration
and direction of current flow (see About Integrating Converters and CapaCitors).
.
The nature of operation of dual-slope and related converters requires the instantaneous reversal of current in the integrating capaCitor.. This puts a substantial burde.n on the
dieleCtric absorption characteristics of the capaCitor. Although dual-slope and related techniques go far to cancel
zero and full-scale drifts, residual non-linearity exists due to
the effects of dielectric absorption. In addition to non-linearity, dielectric absorption can also cause the converter to give
different outputs with a fixed input as the conversion rate is
varied over any significant range. Various compensation arrangements are employed to partially offset these effects in
present converters. What is really needed for high precision,
however, is a conversion scheme which inherently acts to
cancel the effects of dielectric absorption, while simultaneously correcting for zero and full-scale drifts.
Overcoming Dual-5lope Limitations
Figure 1 diagrams a converter which meets the requirement
noted previously. In this arrangement a microprocessor is
used to sequentially switch zero, full-scale reference and EX
signals into one input of a comparator. The other comparator input is driven from the ramp output of an operational
amplifier integrator. With no convert command applied to
the microprocessor, the circuit is at quiescence. In this state
the microprocessor sends a continuous, regularly spaced
signal to the integrator reset switch. This results in a relatively fixed frequency, period and height ramp at the amplifier's output. This relationship never changes, regardless of
the converter's operating state. In addition, the time between ramps is lengthy, resulting in an effective and repeatable reset for the capacitor. When a convert command is
applied, the microprocessor switches the comparator input
to the zero position, waits for the next available ramp and
then measures the amount of time required for the ramp to
cross zero volts. This information is stored in memory. The
microprocessor then repeats this procedure for the fullscale reference and EX switch positions. With all this information, and the assumption that the integrator ramps are
highly linear, the absolute value of EX is determined by the
processor according to the following equation.
EX =
[CEl( - CZEROl
X K /LV
[CFULL-SCALE - CZERO]
where C = count obtained
and K = a constant, typically 107
After this equation is solved and the answer presented as
the converter's output, the conversion is complete and the
microprocessor is ready to receive the next convert command.
612
-y
WIDTH OUTPUT
€)ANALDD
INPUT
MULTIPLEXER
CONTROL
+Yo-"""fIt-.
ImORATOR
REBET
DIGITAL OUTPUT
CONVERT COMMAND
TUHf5625-1
FIGURE 1
The converter arrangement shares many of the characteristics of a dual-slope type and also provides some significant
advantages. The key operating features are as follows:
1. It continuously corrects for zero and full-scale drift in all
components in the AID circuit, regardless of changes in
time or temperature. The primary limitation on accuracy is
the stability of the MI-scale reference. The zero Signal is
derived through conventional high quality grounding technique. These features are similar to a dual-slope converter.
FIlling Out the Blocks
The detailed schematic diagram of the prototype 20-bit linear AID conveter is shown in Figure 2. For clarity, the details of the INS8070 microprocessor and its associated logic
are shown in block from. Note that the entire analog section
of the converter is fully floating from the digital section to
eliminate noise due to digital current spiking and clock
noise. The analog and digital circuits communicate via optoisolators. The full-scale reference for the converter is provided by the LM199A-20-LM10SA combination. This circuit,
using the components specified, will typically deliver 0.25
ppml"C performance with drift of several ppm per year. The
accuracy to which this reference can be maintained is the
primary limitation on absolute accuracy in this converter.
The output of this reference is fed to an FET-switched multiplexer which also receives the EX and zero signals. Because all these sources are at low impedance, and only one
is switched on at a time, the leakage and ON resistances do
not contribute significant error. The A4 combination provides a low bias current unity gain follower with greater than
1,000,00:1 (120 dB) of CMRR, preserving converter linearity. Drifts in this follower are not significant because they will
be cancelled out by the microprocessor's calibration cycle.
The microprocessor's digital commands to the FET
switches are received by the 4N28 opta-isolators. The
LM148 quad op-amp (A5) is used to generate the voltage
swing necessary to control the FET switches. The discrete
components at each amplifier output are used to generate
one-way time delays to give the FET switches break-beforemake action. This prevents cross talk between the zero, fullscale reference and EX sources.
2. Because the integrating capacitor is always charged in a
continuous pattern and in the same direction, the dielectric absorption induced error will be relatively small, constant, and will appear as an offsetterrn. This offset term
will be removed during the microprocessor's calibration
cycle. This feature is unique to this converter and is the
key to high linearity.
3. The comparator always sees the ramp voltage approaching the trip point from the same direction and at the same
slew rate, regardless of operating conditions. This helps
maintain repeatability at the trip pOint in the face of noise
and gain-bandwidth limitations in the comparator.
3. Unlike a dual-slope, this converter has no inherent noise
rejection capability. The EX input signal is directly coupled to the comparator input with no filtering. This is a
decided disadvantage because most "real world" signals
require some smoothing. If a filter was placed at the input
substantial time lag due to settling requirements would
occur. This is unacceptable because the converter relies
on short time intervals between multiplexer states to effectively cancel drift. The solution is to use the microprocessor to filter the signal digitally, using averaging techniques.
613
iC"I
1111<
I,
-16V
Z
cC
5Dk
lID
} INTEGRATOR
RESET
4.0k*
LM329
WIDTH OUT
15V
3.3k
2.7k
22k
10k
':"
llV
4.7k'
A4
FULL-SCALE
(REFERENCEI
""r
-IIV--"""'M.....
llV
llV
-IIV
lie,
-15V
15V
-16V
o-J\I<.,.,.
laD
Fiiii::SCAi:E
EX
,ZERO
Notes
~il
it.
=; 2N4393
± 15V for analog clrcullry Is fully Iloaling
"·Vlohay 8-102 precision 18.lolor
" Melal film realslor-RN6OC
t Tefion-COIT)ponenl Research Corp.
+!- =IN4148
TLlH/5826-2
FIGURE 2
The requirement for a cOmparator with 1 ppm (1 L~Bat20
bits;" 1 ppm) of ~p pOint noise cannot ~'met 'by any standard device., At 10V full-scale this is only a 10 p,V LSB. The
50 ms-10V ramp's relatively slow ,slew rate me&rls that the
gain-bandwidth and noise cilaracteristlc$ of a standard differential, input comparator 'will', i:aU8EI ,~nsidei'a~!e I,Incertainty at .the, trip point. Also, as the common-mode voltage at which the ramp vs EX crossing occurs changes,
the trip point of the comparator will shift, introducing
overall non-linearity.
Another FET is used to reset the, integrator and is biased by
it "brute-force" level shifting-edge speed-up network
formed by the 2N2222-2N2369 pair. A 4N28 opto-isolator
biases this' network when it receives the reset signal
from the INSS070 'processor. A1, an LF356, has its "+"
input biased at about negative 1\t, ensuring that
the ramp will start far enough below ground to determine a
true zero signal.
614
These problems are addressed by the A2-A3 configuration,
which forms a high precision comparator. A4's negative output is resistively summed with the positive output of the A 1
ramp at A2. A2 normally operates at a low gain due to the
diode bounding in its feedback loop. When the currents produced by the ramp potential and A4's output very nearly
balance the potential at A2's summing junction will go low
enough so that A2 comes out of bound and operates at a
gain determined by the 499k feedback resistor (about 100).
A2 remains in this high-gain state as long as the ramp and
A4 output caused currents are nearly equal. As the ramp
continues in its positive going direction the current into A2's
summing junction will go to zero and then move pOSitive
until the A2 output bounds negative. The output of A2 drives
A3, an LM311 comparator which is set up as a zero crossing
detector. The components in the positive feedback path at
A3 insure a sharp transition. Fl{Jure 3 shows the waveforms
of operation. The ramp (a) is shown in highly expanded
form. The A2 output (b) can be seen to come cleanly out of
diode-bound just before the ramp balances A4's output and
then return to bound after the crOSSing occurs. Waveform
(c) is A3's output. The A2 pre-amplifier makes the A3 comparator's job much easier in a number of ways. It amplifies
the voltage difference of the two Signals to be compared by
a factor of 100. This knocks down the effect of A3's input
uncertainties. It also produces an apparent 100 fold increase in the ramp slew rate at the trip point. This means A3
spends that much less time with its inputs nearly balanced
in an uncertain and noise sensitive condition. Finally, A2
presents the difference Signal as a single ended zero crossing signal. This eliminates errors due to changing commonmode voltages that a differential comparator's input would
face. Such errors would manifest themselves as overall
converter non-linearity.
Converter Performance and Testing
FI{JIJf9 4 shows the convert at work. A complete conversion
cycle is captured in the photograph. Waveform (a) is the
integrator reset out of the INS8070. (b) is the ramp at A 1's
output. Waveform (c) is the multiplexer output at A4, showing the zero, full-scale reference and EX states. For each
state ample time is allowed before the ramp begins. The
width output is shown in waveform (d).
(II = 10V(olV
(II)-1oY/DIV
(c)-aVIDIV
(d),-10v/DIV
HDRIZ· &0 IIIIDIII (UNCALIBRATED)
TL/H/5825-4
FIGURE 4
The converter was tested with the arrangement shown in
Figure 5. The Kelvin-Varley voltage divider, a primary standard type, has a guaranteed linearity of within 1 ppm. The
LM11 op amp provides a low bias current, low drift follower
to unload the Kelvin divider's output impedance. Because
the LM11 gives greater than 120 dB common-mode rejection, its voltage output should track the linearity of the Kelvin
divider. To test this the LM11 was adjusted for offset null
and a battery-powered p.V meter connected between its inputs. 20-bit linear (1 ppm) transfer characteristics were verified by running the Kelvin divider through its range and noting less than 10 p.V (1 LSB at 10V full-scale) shift under all
conditions. Then, the converter reference was used to drive
the Kelvin divider input and the LM11 output to the EX input
of the AID converter.
HDRIZ =200 ~sJDIV
TLlH/5625-3
FIGURE 3
The output of the A3 comparator feeds a 2N2369 transistor,
which functions as a level shifter-gate. This transistor gates
out that portion of the width output pulse which would be
due to the length of the integrator reset pulse. The 2N2369,
a low storage capaCitance device, provides high speed,
even in the relatively slow common emitter configuration.
The HP-2602 high speed opto-coupler transmits the width
information to the digital circuitry.
TL/H/5625-5
FIGURE 5
615
A typical output on the Hewlett-Packard 2644A' GRT tenninal display is shown in Figure 6. For. each corw,,m,command
to the INSS070 ,the number of cou~ of zero, ,full-!lCaie ref~
erence and EX are shown along with the final compl!t~
answer. Note that the final,C9unt is computed tq, Qn~ part in
ten million and th~ last digit is insignificant Note also, that
the 4. final counts are all, within ±, 1, ppm , ' _d~ the ,fact
that they were individually spaced almost 1 hour apart in a
varym9 thermai environment. Unearity of the converter over
a 10V range was verified at 10 points ,by varying the MSB of
thl[lK~I\rir'i diyiper. Although llie prototype converter takes
300 rTl$ to complete a cyclE!, "fa$tElr ~d is attainable by
incriiasir1g the 2QMl'iz oleiC\< rate: Perhij!s ntore practically,
hiOher,conv8I'l\ionspeedsat,lower res~i~hsareeasily attainable'by simply,shonening'tl;le ramI' time. ,The converter
output Word lenglt\
oonve..siori time may be varied over
a wide dynamiM~ngeby.jl!Qglingc~k s~ed and ramp
tini&. '~:'
" , J : : " " " ,';" ; , :,"
bridge output for a given bridge drive level. In this manner,
ellen if the bridge drilte varies, the gain of the system ra-.
mains calibrated by ratiometric error cancellation. The zero
signal is derived by shorting both amplifier inputs to the
common-mode voltage at the- bridge output. This system
has been built and has maintained 15-bit accuracy over a
75'F temperature range.
Prospective constructors of this converter are advised that
construction technique is extremely critical. In orde; for the
converter to operate properly, the greatest care must be
taken in grounding, guarding and shielding techniques. Use, ful sources of information are listed in the References
References
1. "Grounding and Shielding Techniques in Instrumentation", R. Morrison; Wiley Interscience.
2. "Designing sensitive Circuits? Don't Take Grounds for
Grantedl", A. P. Brokaw; EON, October 5,1975.
3, "Input Connection Practices for Differential Amplifiers",
J. H. Hueckel; Neff Inst. C o r p ' ,
4. "Prevent Low Level Amplifier PrOblems", ~. Williams;
Electronic Design, February 15, 1975.
5. "Signal Conditioning", Gould Inc., Brush Insts. Div.,
Cleveland, Ohio.
6. "On Computing Errors of an Integrator", T. Miura,et. al;
Proc. 2nd ALCA Conf. Strllsbourg, France. 1958. Presses Academiques Europeennes, Brussels.
7, "Comparator I.C. Forms 10-Bit AID Converter", J: Williams: Electronics, April 17, 1975.
8, "Low Cost, Unear AID Conversion Uses Singla-.Slope
Teehniques",J. Williams:,EDN, August 5,1978.
9. Component Research Corp.-Catalog JB.
10. "The Secret Ufe of Capacitors", ECD Corp., Cambridge,
Massachusetts.
'
11. "An Analysis of Errors in Single Slope Integrators", R. A.
Eckhardt;'S. B. Thesis, M.tT., 1974.
'
12. "Characterization, Measurement and Compensation of
Errors in Capacitors ..• a compendium of stu crOSsing. Bandwidth is in
excess of 50 MHz to ensure no bandwidth-induced distortion.
Another commonly used technique is a pseudo-class B output stage found in many integrated power op amps, (see
Figure 2). In this configuration, the limited output swing
problem of class AB amplifiers is eliminated. The output
swings to within one or two volts of either supply.
limit sense to protect the output stage. Current sense resistors connected between the supply pins and the SC pins
program the limit threshold. In operation, an approximate
0.6V differential turns ON either transistor
or 09, which
in tum drives 012 and Q4 respectively, starving any excess
base current from driving the output beyond the preset limit.
The buffer stage output is current limited by transistors 07
and
to no more than 50 mA. However, the power stage
transistors 01 and 02 are designed to tum ON as the load
current reaches about 25 mAo Any additional current demanded is sustained by these two output transistors right up
to the rat!ld output limit. Thus, the reserve drive of the buffer
stage is used only to "smooth" the turn-on delay of the
output Darlington transistors.
as
as and 09 base-to-emitter junctions are used as current
as
The obvious problem with this type of circuit is that it has
significant crossover distortion. Distortion occurs when both
output transistors are biased completely OFF during zero
crossing, thus exhibiting. relatively high reSistance at the amplifier output. In addition, the minor loop feedback between
the base drive of the transistors and the output almost always induces an abrupt change in the response. This further aggravates the amplifier distortion.
v+
+
INPUT
>~w..-+-
OUTPut
vTLlH/6B85-2
FIGURE 2. Class B Output Stage
TLlH/6866-3
FIGURE 3. LH0101 Complete Schematic
619
....~
.-
~
~
,---------------------------------------------------------------------------------,
RESULT
The performance of the LH01 01 is best demonstrated in the
following photographs. Figure 4 shows the large signal slew
response of the LH0101 into a 100 load. No crossover distortion is evident.
DESIGN PRECAUTIONS
Circuit Layout Considerations
In high power applications, one must pay close attention to
the trace connections in which high current is ~rried. Critical connections should be short to minimize line drop. For
example, a 10 mO PC trace carrying 2 amps develops
20 mV of error voltage. It is important to be aware of where
this error is generated and how it impacts accuracy.
Ground connections are probably the most important, if not
the most troublesome. Not only can they contribute to circuit error, but in many situations the circuit can become unstable if the layout induces excessive phase error. F/{/ure 7
shows one correct technique for circuit grounding. The
heavy lines represent high current paths. The analog signal
ground is returned to the supply common.
Output Current Umlt
As described in the previous section, current sense resistors may be inserted between the supply pins and the SC
pins to limit excessive load currents. A voltage of 0.6V developed across the sense resistor triggers the limiting circuit. Figure 8 illustrates the usage.
TLfHf6865-4
FIGURE 4. Large Signal Pulse Response, 100 Load
Generally, crossover distortion occurs within a small region
near zero crossing. In order to amplify its effect, a signal of
small amplitude is used. Figures 5 and 6 show a signal amplitude of 2 volts peak, and loads of 100 and 10 respectively. Notice that a slight distortion is observed in F/{/ure 6, but
only under the extreme condition imposed by the 10 loadl
In cases where the chosen RSC is small « 10), the contact
resistances from solder connections and socket ohmic contacts become important and must not be overlooked. A
good solder joint typically exhibits 5 mO of resistance and
socket contacts have about 10 mO. Even interconnecting
traces will become significant if they are long.
Consider the circuit in Figure 8; a pair of good solder joints
on the 0.30 current sense resistors corrlribute more than
3% error. Also, one can expact the current sense transistor
threshold to vary as much as 10% from device to device.
Furthermore, this threshold has a temperature coefficient of
-2 mVI"C. In summary, the expected accuracy is on the
order of 20% to 25% under all operating conditions.
When designing the current limit,. the threshold should not
be set too close to the worst case peak current under any
normal operating conditions. Signal distortion will occur
even if the threshold is intermittently exceeded for a very
short duration. In the worst instance, the circuit can trigger
spurious oscillation, such as in the case of driving a capacitive load during transient conditions. These occurrences are
very real in nearly all op amps having similar current sense
circuits. Although the current limit circuit has high enough
gain to produce a sharp response, it is a good idea to allow
a 20% margin above the worst case operating condition.
TLfHf6865-5
FIGURE 5. Small Signal Response, 100 Load
Safe Operating Conditions
In order to preserve the reliable performance of the
LHOI 01, the device must not operate beyond the boundary
defined in the Safe Operating Area curve in the data sheet.
Because of its importance, it has been reproduced in Figure
9.
TLfHf6865-6
FIGURE 6. Small Signal Triangular
Wave Response, 10 Load
620
Power Dissipation Considerations
Probably the single most important gauge of reliability is the
operating temperature of this device. The derating curve,
which has again been reproduced in Figure 10, must be
followed faithfully. Similar to the Safe Operating Area curve,
under no circumstances should the boundary be exceeded.
tion temperature of 150"C. Thus, the sum of all the thermal
resistance represents the thermal efficiency of the mechanical design. The lower the sum, the more efficient the thermal conductivity.
In a typical deSign, first and foremost is to calculate the
maximum power dissipation that the device is designed to
handle. There are two components, which are related by the
following equation:
(2)
POISS = Po + Po
The curves relate operating and junction temperature, power dissipation and thermal resistance. The general relationship is expresed as follows.
POISS =
where:
TJ(MAX) - TA(MAX)
RSJC+ Rscs+ RSSA
The first part of the equation is the quiescent power at
which the device operates under no load. The second term
is the power dissipated by the output transistors due to the
load. This is calculated as the average voltage difference
between the supply voltage and the output voltage multiplied by the maximum rms load current the amplifier is required to deliver.
(1)
POISS = the power dissipated by the device in
watts.
TJ(MAX) = the maximum junction temperature allowed, for the LH0101, TJ(MAX) =
150"C.
Once the power dissipation is calculated, the next step is to
determine the maximum ambient temperature in which the
device must operate.
TA(MAX) = the maximum ambient temperature in ·C
under which the device must operate.
To complete the thermal design, all contributions of thermal
resistances must be summed per equation (1) above. First,
the junction-to-case thermal resistance for the LH0101 is
given in the data sheet; it is typically 2.5·C/W.
The metal case of the LH0101 is electrically connected to
the output of the amplifier. Unless the application permits
direct mounting to a heat sink, a sheet of insulation should
be sandwiched between the case and the mounting surface
for isolation purposes. Many types of insulators are available. The most popular of these is mica film. Its thermal
resistance is listed in Table II along with other types.
RSJC = thermal resistance from the junction to
case in ·C/W, for the LH01 01, RSJC =
2.5·C/W.
Rscs = thermal resistance from case to surface
of heat sink in ·C/W.
ReSA = thermal resistance from heat sink to free
air ambient in ·C/W.
In simple terms, the expression is a measure of how well the
internally generated heat is removed such that the power
dissipated will not give rise to a maximum permissible juncH2
Y+
INPUTS
OUTPUT
Rac= 0.6
ISC
vTL/H/B65S-8
TLlH/6668-7
FIGURE 8. Current Limit Protection
FIGURE 7. Proper Supply Connection
g
i..
=
u
100
90
~ 80
Ii 78
80
~ 50
40
VS· ..,5Y .•,\'SII"
4
TA.~\~ ~ INFlN"" HUT SINK
3
II"'"
I
il»
2
.\'l
i
W
NO HEAT 8111K
1
0
~ -1
co -2
S -3
-4
-s
~
NO HEAT SINK
I
.... ~
I
~'1
~
INFINITE HEAT IINIIA !-'''"
-15
A'"
-10
-5
•
+5
8JC-ZOCIW
8JA-25"C1W
+1. +15
~
INFIN.le !--!--
....... HEAT SNK
1'.
ao
20
10 f-1-- f- NO HEAT sINK f- f-~
• 0
25
50
7S
100
126
TEMPERATURE ('I:)
Yo, OUTPUT VOLTAIIE (VI
TLlH/6668- 10
TL/H/6866-Q
FIGURE 10. Power Derating Curve
FIGURE 9. Safe Operating Area
621
TABLE II. Thermal Resistance (Note 1)
Insulator
Material
Type
W/OThermal W/Thermal
Joint
Joint
Compound Compound
y+
y-
y-
Sources
1.3°C/W@
0.003" thick
1.2"C/W@
0.002" thick
0.25"C/W
Thermalloy Inc.
0.33"C/W
Thermalfilm 12 1.5°C/W@
0.002" thick
1.00C/W@
Aluminum
Oxide2
0.062"C
Beryllium
0.6°C/W@
Oxide2-3
0.062" thick
Insul-Cote2
0.5°C/W@
0.002" thick
0.52"C/W
Keystone
Electronics
Mod; #4658
Thermalloy Inc.
Mica
y+
O.3"C/W
. TUH/6865-11
FIGURE 11. Back EMF Suppression Technique
0.15°C/W
1k
y+
Thermalloy Inc.
Nate 1: Mountfng bolts torqued 10 6 oz.·ln.
Nate 2: ConsuH manufacturer on availability for 8-Iaad TO-3 pacl of about 25°C/W. Consequently, a heat sink is almost always required in applications
invoMng significant power. Most heat sink manufacturers
specify the mounting-surface to ambient thermal resistance
RI/SA. In a nutshell, the heat sink is selected such that the
right hand side of equation (1) is equal to or greater than the
left hand side, or total power dissipation. It is good engineering practice to allow at least a 10% safety margin.
INDUCTOR
LOAD .
.
.
.
TUH/~-12
FIGURE 12. RC Damping to Compensate Inductor Load
In some applications where It is desirable to prevent poweron surges from actuating the "Ioad, for example a motor
valve actuator or a disk drive read/write head servo loop,
the same RC damping qircult provides an alternate conductive path to suppress surge current.
Design Considerations Driving CapaCitor Load
Capacitive loads tend to create an unwanted pole at the tail
end of the frequency response where the open loop gain
approaches unity gain frequency. The effect is a net reduction of phase margin. For example, a 500 pF load capacitor
reduces the phase margin of the amplifier from a no load of
58" to 45°. A 1000 pF capacitor pushes it down to 400. With
a large 0.01 p.F capaCitor, the amplifier has a mere 22"
phase margin. The latter cases are susceptible to oscillation. Figure 13 shows a compensation technique to restore
stability. The value of the lead capaoltor C1 should be such
that the capacitive reactance is one-fifth the resistance of
R2 at the unlty-gain crossover frequency of the amplifier, or
4 MHz.
It is interesting to note that there is a critical value for the
load capaCitor abo:.'e which oscillation cannot occur. That
value is approximately 0..1 p.F. Under such a condition, the
time constant is so large that the heavy dampitlg effectively
suppresses any chance for the circuit to oliciHate.
DesIgn Conalderatlon Driving Inductive Load
The LH0101 is suitable for driving most inductive loads including voice-coils and motors. However, in many situations
the device should be protected from the harmful effects of
enargy stored in the inductor. Such a condition exists when
power is removed from the circuit at an Instant when a high
current is flowing through the inductor. A back-emf may
have energy high enough to forward bias internal junctions
at a current density level sufficient to destroy the device.
Figure 11 illustrates a simple way to prevent this.
Theoretically, an inductive load does not cause amplifier
loop instability. Howaver, if the circuit Q is high enough and
stray capacitances are within a critical range, the load circuit
can break out into oscillation. A series RC damping circuit of
100 and a 0.01 p.F capacitor across the inductor as shown
in Figure 12 usually alleviates the problem.
622
R2
INPUT
200mV/cm
IL
aO ..VI.... lGOmA/em
81
INPUT
1812
OUTPUT
~CL
Cl· .. hc~t
TLlH/6865-16
FIGURE 18. 20 kHz Current Drive Waveform of
CRT Deflection Coil
511Q
Servo Motor Amplifier .
A typical motor driver circuit is shown in Figure 17. The amplifier will deliver the rated current into the motor. Again,
care should be taken to keep power dissipation within the
permitted level.
A variation of the same servo design is shown in FIgure 18.
This precision speed regulation circuit employs rate feedback for constant motor current at a given input voltage.
yTL/H/6865-13
FIGURE 13. Compensation for Capacitance Load
TYPICAL APPLICATIONS
CRT Yoke Driver
One of the most natural applications for the LH0101 op amp
is the deflection yoke driver for high resolution CRTs. The
low distortion characteristics allow virtually unrestricted use
in any circuit configuration. A typical design is shown in Fig-
R2
ure 14.
v+
INPUT-~",,"-=-I
TL/H/6665-17
2.311
FIGURE 17. Servo Motor Amplifier
ROAMP
10012
TLlH/6865-14
·Coil Current IL Measured with
Tek1ronix CUrrent Probe Model P6042.
FIGURE 14. CRT Yoke Driver Circuit
A 500 mV peak-to-peak triangular waveform about ground is
input to the amplifier, giving rise to a 100 mA peak current to
the inductor. As shown in Figures 15 and 16, the responses
were recorded at 60 Hz and 20 kHz respectively. At higher
frequencies, ROAMP becomes important. The value should
be selected to yield the cleanest waveform.
INPUT
2OOm"o..
TL/H/6665- 1B
IL
50 ..V/eRI ,. 100 IllA/om
FIGURE 18. Rate Feedback Servo Motor Amplifier
TL/H/6665-15
FIGURE 15.60 Hz Current Drive Waveform of
CRT Deflection Coli
623
The result is an impressive set of specifications summarized
in Table III. Although not earth-shaking, 0.14% total harmonic distortion at the rated 40W output, within the full audio frequency spectrum, is very respectable.
Digitally Programmable Power Source
Designing, preci$ion c:volt«Q& and, current sources is made
simple 1J$ing~l-HQtO~ AddiOg a digital-ta-analog converte~prdvid~. trerri~~O~i~/!IOlint'Of flexibility in speed
and C9ntrol: ,A,p.p~~titiii$(tangff ,frOm DC precision power
suppllll' to,S'l>Phi$tiCated.;pI'Qgrsinmable waveform generators. the ~ei!gn~Ofl~e'vg~e,source is relatively straightforwa(d;wtie~aii;.~,pro!irar1jJriabl~ current source is a bit
more inY~IVed.' SUch',~. £Ii~,ns shown in' Figure 19. The
DAC is.:configured'U> operate hi a bipolar mode with an output range of ±10.000V. With 12 bits, the DAC outputs an
equivalent of.4.88'mV per bit-weight. ConsequentlY, the resolution at the current source is 0.488 /lA/bit.
Transient slew rate of greater than 1OVI p.S extends the full
power bandWidth to beyond 200 kHz,and the distortion response is plotted over the entire audio spectrum in FIgure
22. This would satisfy all but a handful of audio purists.
About the only difficulty .encountered was finding Ii'heat sink
that was good enough for convection cooling. By following
the previous section on Power. Dissipation Considerations,
the heat sink thermal resistance required is a maximum of
3.5°C/W at an ambient temperature of 25"C. The calculation included the use of mica insulator and liberal use of
thermal-coat compound. As it tumed out, a large extruded
heat sink with fins similar to the Thermalloy type 6141 did an
excellent. job of keepinll the junction~ cool. .
The output sources and sinks current only to ground referenced . loads. A negative full-scale code (all digital inputs
low) effectil
negative (Souri:8r'1 amp current output. A
zero scale (MSB low and all' other bits high) gives zero current. And' positive' full sciilEl' code (all digital inputs high)
forces a poSitive (sink) 1 amp current at the o\itPui.
a
a
TABLE III. Bridge Audio Ampl"le, SpecHlcatlona
The versatility pf this circuit configuration is riot without limi~
tation.' Because the output voltage is dependeitt upon the
ground referred load; one' must be aware of the potentially
destructive power dissipation level the LH0101 must sustain. For example, 1A current into a 50 grounded load generates 10W of power in the amplifier. This level is high
enough to destroy the device \lnle~ an appropriate heat
sink is used to keep the device Junction temperature from
exceeding the 150"C lim.it.
AV (Voltage Gain)
ZIN (Input Impedance)
Iq(Quiescerit Current)
Po (Output ~ower)
'.
-AMI) Continuous. 20. Hz-20 kHz
Full Power Bandwidth
THO (Total Harmonic Distortion)
1W 20-20,000 Hz
40W 20-20,000 Hz
IMD (Intermodulation Distortion)
1W 60 Hz/100 kHz 4:1
40W 60 Hz/100 kHz 4:1
Peak Output Current'
Supply Voltage
Maximum Output Voltage Swing
CoaxIal Cable Driver
The I.:H0101 makes'an ideal cable driver of any type. It has
adequate bandwidth fpr most aUdio and sub-video applications. The high current, distortiOn free output can easily interface any termination required: Large ,line' capaCitance
does hOt preSjtnt a problem fo~ the LH01 O~. It has adequate
reserve current capability to charge the capaCitance without
seriously degrading bandwidth. However, current limit pratection against cable shorts is recommended. A typical interface circuit is shown in Figure '20. The op amp can drive
up to 6 coaxial lines without the use of a heat sink.
3
10 kG
60 mA
40 Watts i.nto f;l0
28 Watts into 160
DC to > 100 kHz
<0.8%
<0.15%
<0.01%
<0.002%
3.125Aint080
±18V
21.2Vrms
30VPeak
REFERENCES
1. National Semiconductor, Special Functions Daf8book.
2. National Semiconductor, UflBBr Applications Handbook.
3. J. Wong, J. Sherwin, "Applications of Wide-Band Buffer
Amplifier", National Semiconductor AN-227, October
1979.
.'
, "
' ,
Low Distortion Audio AmpUfler
At this juncture, it would be .of great interest to see how well
the LH0101 performs in the audio high fidelity arena The
intent here is not to set a new standard but merely to use
the stringent requirements of the audio specifications as an
ideal yardstick for comparison.
The complete design is illustrated in F1f}ure 21. The circuit is
configured as a bridge amplifier to maximize available output power for a given set of supply voltages.
4. NatIOnal Semiconductor' "LH0101 Pawer Operational
AmplifiGr" data sheet
!""
:j'
- ,<.
624
,'"
LSI
MSI
+15V
-1~_'::Z2:.t
HI
10k. 0.111
-15V -I1-1-~
H2
I k. 0.111
~':-_..... VI
+5Y-t-t-....'"I
+15V
':'
+15V
-15V
20k
H6
HI. D.III
2W
+IIV~-I5V F.S. ADJ.
OFFSET ADJ.
R3
10k. 0.111
10 __ R2Vl
RI R6
':'
-IIV
H4
10911. III
R5
lOUT
481,.A/BIT
200"
lOT
TL/H/6885-19
FIGURE 19. Digitally Programmable Current Sourea
lk
.,51
....'
~ .... '
H&-58
50g
':'
~
50"
RD-58
1k
50g
RG-58
50"
':'
~~'
-15V
50"
':'
TLlH/6865-20
FIGURE 20. Multl·Llne Coaxial Cable Driver
625
~
.i
r-----------------------------------------------------------------------------------------------,
R5
!'O'CASE=+-_~+
IHPIlT
>---+
OUTPUT
TL/H/6865-21
Rl-R4
R5
RS
R7-Rl0
Current UmH Resislor
Feedback Resistor
Feedback Resistor
Input Resistors
Cl-04
C5-06
O6-CI2
Bypass Capacitors
Bypass Cepacitors
BypassCapacitors
0.151l.2W
5 kll
15 kll
10 kll
47 ,..F. 25V Electrolytic
10,..F.25VTentelum
0.1 ,..F.25VCeramic
FIGURE 21. LH0101 Bridge Audio Power Amplifier
TL/H/6865-22
FIGURE 22. Total Harmonic Distortion vs Frequency
of Bridge Power AmplHler
626
Applying Dual and Quad
FETOpAmps
National Semiconductor
Application Note 262
The availability of dual and quad packaged FET op amps
offers the designer all the traditional capabilities of FET op
amps, including low bias current and speed, and some additional advantages. The cost-per-amplifier is lower because
of reduced package costs. This means that more amplifiers
are available to implement a function at a given cost, making design easier. At the same time, the availability of more
amplifiers-per-dollar means that relatively self contained
and sophisticated functions can be designed around a single FET dual or quad package. In addition, duals and quads
require less board space, fewer bypass capacitors and less
power supply bussing. An inventive designer can capitalize
on all of these advantages to produce complex circuit functions at low cost. An example is shown in Figure 1.
direction ultimately limited by the diode feedback-bound.
Another diode provides bias at A2's .. + .. Input to compensate the bound diode and A2's output settles very near zero
volts. When the positive output pulse from A 1 ends, the
positive current into A2's summing junction ceases and A2's
output ramps linearly until the next reset pulse.
A3 functions as a current summing servo-amplifier which
compares the currents derived from the LM 135 temperature
sensor and the LM129 reference. In this example A3 operates at a gain of 1000 with a 1 j.LF capacitor providing 0.1 Hz
servo response. A3's output represents the amplified difference between the LM135's temperature and the desired
control setpoint, which may be varied by altering the 21.6k
value. In this circuit the 21.6k resistor provides a setpoint of
49"C. A3's output is compared to the ramp output of A2 and
A4, which is set up as a comparator. A4's output will only be
high during the time A3's output is greater than the ramp
voltage. The ramp reset pulse is diode-summed with the
ramp output (Trace C, Figure 2) at A4 to prevent A4's output
from going high during the period of the reset pulse. A4's
output biases the LM395 power transistor which switches
power to the heater (Trace 0, Figure 2). If the LM135 sensor
is tightly coupled to the heater and the oven is well insulated, this controller will easily hold O.05°C over wide excurSions of ambient temperature.
HIGH EFFICIENCY PRECISION OVEN TEMPERATURE
CONTROLLER
In this circuit, a complete, high efficiency pulse width modulating temperature controller is built around a single LF347
package. In Figure 1, A 1 functions as an oscillator whose
output (Trace A. FlfJure 2) periodically resets the A2 integrator output (Trace B, Figure 2) back to ,zero volts. Each time
A 1's output goes high, a large positive current is forced into
A2's summing junction, overcoming the negative current
that flows through the 100 kO resistor into the LM129 reference. This forces A2's output to head in a negative-golng
lZ111
All diodes = 1N4148
03
4.711
• = Low TC. metal·film 1ypes
= LF347 quad
A 1·A4
,
1l1li
II1Of1
15V'o-+"""II""'_..~
-15V
SERVO
CONTROL
SETPOINT
15Vo-Y\j~"
+ ___________________________
THERMAL FEEDIACK ..1
TL/H/8932-1
FIGURE 1. Connecting appropriate components to an LF347 quad FET op amp IC produces
a high efficiency prec;lslon oven temperature controller. This design can hold
, a temperature w,lthln O.OS"C despite wide ambient temperatura fluctuations.
627
N
~
C
r-----------------------------------------------------------------------------~
PLATINUM RTD HIGH TEMPERATURE TI;IERMOMETER
.
WITH ANALOG AND DIGITAL OUTPUTS
Another temperature related circuit appears in' Figure 3. In
this circuit an LF347 is used to signal condition a Platinum
RTD and provide simultaneous analog and frequency outputs. These outputs are accurate to ± 1°C over a range of
300"C-600"C (572"F-1112"F). Although the circuit maintains linearity over a much wider range the non-linear response of the RTD over wide range is the limitation to accurate, wide range operation (see graph, Figure 4).
A
B
c
A 1 functions as a negative gain inverter to drive a constant
current through the platinum sensor. The LM129 and the
5.1 k resistor provide the current reference. Because A 1 operates at negative gain the voltage across the sensor is
extremely low and self-heating induced errors are eliminated. A1's output potential, which varies with the platinum
sensor's temperature, is fed to A2. A2 provides scaled gain
and offsetting so that Its output will swing from 3.00V to
6.00V for a 300"C to 600"C temperature swing at the platinum sensor.
A3 and A4 form a voltage-to-frequency converter which
generates a 300 Hz to 600 Hz output from A2's 3V to 6V
analog output. A3 integrates in a negative-going direction at
a slope which is linearly dependent upon A2's output voltage. A4 compares A3's negative ramp to the LM129's positive reference voltage by current summing in the 10 kG resistors. When the negative value of the ramp just 'exceeds
the LM129 voltage A4's output goes positive, turning on the
2N4393 FET and resetting the A3 integrator. AC feedback
at A4 causes it to "hang up" In the positive state long
enough to completely discharge the integrator capaCitor.
D
TLlH/8932-2
Trace Vertical Horizontal
A
B
C
0
20V/Div
10V/Div 50,""s/Div
10VlDiv
20V/Div
FIGURE 2. Oven-controller waveforms from Figure 1's
circuit show A1's oscillator output (Trace A) and A2's
Integrator output (8) as the laHer resets periodically to
OV. Trace C displays A4's ramp Input, and (D) Indicates
the LM395's power Input to the oven heater.
RpLATINUM
IO~F
IIV
r---~~+--.
_.
~--------------------------~--~~~
lilk
ZERO TRIM
13OO'C)
ANALOG
OUTPUT
I3V-8V - 38O'C-IIII"C)
RPLATINUM
=
Rosemount 118 MG
= 214.20 at 300'0 (572'F)
= 318.20 at 600'0 (1112'F)
All diodes = 1N4148
AI·M - LF347 quad
• = Low TO, meta)·fllm types
FREIIUENCY
OUTPUT TRIM
ZOOk
1.1M"
FREIIUENCY
OUTPUT
1380 Hz - 310'C,
III Hz-IIO"C)
TLlH/6932-3
FIGURE 3. Generate simultaneous analog level a!Hi frequency outputs using one LF347 package
by signal-conditioning a platinum RTD sensor. You can calibrate this high temperature (30o-C to BOO-C)
measuring circuit to ± 1°C by using three trimming pots.
628
.--------------------------------------------------------------------.>
z
To calibrate this circuit, substitute a high quality decade box
,,
(e.g., General Radio #1432-K) for the sensor. Alternately
...
~
I0Il
elOD
1 400
I:
R~~U
TlllMB /
adjust the zero (300"C) and full-scale (6OO"C) potentiometers for the resistance values noted in Figure 4 until A2's
output is calibrated. Next, adjust the 200 kO frequency out·
put trim so the frequency output corresponds to the analog
value at A2's output.
V
Sf.SOR RESPOWSf
J
~~
1111
l#
a
IDEAL
VOLTAGE CONTROLLED SINE WAVE OSCILLATOR
LjEARyY-
Figure 5 diagrams a very high performance voltage controlled Sine wave oscillator which uses a Single LF347 package. For a OV-10V input the circuit produces sine wave
outputs of 1 Hz to 20 kHz with better than 0.2% linearity. In
addition, distortion is about 0.4% and the sine wave output
frequency and amplitude settle instantaneously to a step
input change. The circuit's sine wave output is achieved by
non-linearly shaping the triangle wave output of a voltageto-frequency converter.
II 1.. 1&1 2111 ZIG 3ID 310
RESIITANCE (Ill
TL/H/6932-4
Temperature("C) Reslstance(O)
600
500
400
300
200
100
0
318.2
284.7
249.8
219.2
177.3
139.2
100.0
Assume the 2N4393 FET is on and A1's output has just
gone low. With the FET on, A1's "+ .. input is grounded and
A1 functions as a unity gain inverter. In this state its output
will be equal to - EIN (Trace A, Figure 6). This negative
voltage is applied to the A2 integrator which responds by
ramping in a positive direction (Trade B, Figure 6). This positive-going ramp is compared by A3 to the LM329 7V reference which is contained within its symmetrically bounded
positive feedback loop. The paralleled diodes compensate
the diodes in the bridge. When the positive-going ramp voltage just nulls out the -7V produced by the LM329, diode
FIGURE 4. A platinum RTD sensor's reslstanca
decreases linearly from 60erC to 300"C. Then, from
30erC to erc, the sensor's resistance deviates from a
straight line slope and degrades the Figure 3 circuit's
accuracy beyond ± 1°C.
LOW FREOUENCV
DISTORTION TRIM
ZERO TRIM
.Ok
m
·'5V
"V
"V
liV
2Ok'
2M
UII
D.D#F
33k U
10lpF
tDpF
',.
·liV
• = 1 % metal·lllm resistors
.. = Match
to 0.1%
All diodes = 1 N4148
A1-A4 - LF347 quad
.I
1&V
SINE WAVE
OUTPUT
m
SYMMET~ ......,.,.,-+----i
TRIM
-11V
200
-'IiV
TUH/6932-5
FIGURE 5. An LF347-based voltage-controlled sine wave oscillator combines high performance with versatility. For OV
to 10V Inputs, this circuit generates 1 Hz to 20 kHz outputs with better than 0.2% linearity and only 0.4% distortion.
629
N
bound A3's output goes positive (Trace D, F/{/ure 6). The
100 pF capacitor provides a frequency adaptive trim to A3's
trip point, aiding VlF linearity at high frequencies by ,compensating A3's relatively slow response time when used as
a comparator. The 10 pF capacitor provides ACpositive
fsedback to A3's positive input (Trace C, Figure 6) . .The positive output of A3 is inverted by the 2N2369, transistor which
also has the effect of further shortening A3's response time.
It does this by using a heavy feed-forward capaCitor In its
base drive line. This allows the transistor to complete
switching just barely after the A3 output has begun to movel
(Trace E, Figure 6). The 2N2369's negative output turns off
the 2N4393 FET. This lifts A 1's .. + .. input from ground and
causes A 1 to become a unity gain follower. This forces A1's
output to immediately slew to the value of EIN. This causes
the A2 integrator to reverse in direction, forming a triangle
wave. When A2 ramps far enough negative A3 will again
switch and the entire cycle will repeat. The triangle output at
A2 is fed to the discrete transistors which form a sine shaper. This configuration uses the logarithmic relationship between collector current and VSE in,transistors to smooth the
triangle wave. The last amplifier in the quad package provides gain and buffering and furnishes the sine wave output
(Trace F, Figure 6).
To calibrate the circuit apply 1OV to the input and adjust the
wave shape trim and symmetry trim for minimum distortion
on a distortion analyzer. Next, adjust the input voltage for an
output frequency of 10Hz arid trim the low frequency distortion potentiometer for,minimum'indication on the distortion
analyzer. Finally, alternately adjust the zero and full-scale
potentiometers so that inputs of 500 p.V and 10V yield respective outputs of 1 Hz and 20 kHz. Distortion products are
shown in Trace G, Figure 6.
This circuit provides an unusually clean and wide ranging
response to rapidly changing inputs, something most sine
wave oscillators cannot do. Figure 7 shows the circuit's respOnse to a 10V ramp applied to the input. The output is
Singularly clean, with no untl;lward dynamics, even during or
following the high speed reset of the ramp.
A
B
c
o
1ms/DIV
TL/H/6932-7
E
FIGURE 7. Applying a 10V ramp Input (top trace) to the
Flgure5 circuit's Input produces an extremely clean
output (bottom trace) with ~o glitches, ringing or
overshoot, even during or after the ramp's
high speed reset.
F
G
SINE WAVE VOLTAGE REFERENCE
TLlH/6932-6
Figure 8 depicts a simple and economical sine wave circuit
Trace
Vertical
A
B
C
D
E
20V/Div
20VlDiv
10V/Div
20VlDiv
50VlDiv
F
G
0.2VDiv
Horizontal
, which provides a fixed 1 kHz output with a precise 2.50
Vrms amplitude. The circuit may ba used as inexpensive AC
calibration source or anywhere an amplitude stabilized AC
source is required. 01 is set up in a phase shift oscillator
configuration and oscillates at 1 kHz. The sine wave at 01's
collector is AC coupled to A 1, which has a closed loop gain
of about 5. A1's output, which is the circuit's output, is halfwave rectified by the diode and a DC potential appears
across the 1 p.F capacitor.
This positive voltage is compared by A2 to a voltage derived
from the LM329 reference. The diode in the potentiometer
wiper arm compensates the rectifying diode. The diode in
A2's feedback loop prevents negative voltages from baing
applied to 01 (and the feedback capacitor, an electrolytic)
on start-up. A2 amplifies the difference of the reference and
output signals at a gain of 10. The output of A2 is used to
provide collector bias for 01, completing an amplitude stabilizing feedback loop around the oscillator. The 2 p.F electrolytic provides stable loop compensation. The 5 kG potentiometer is adjusted so that the circuit output is exactly 2.50V.
This output will show less than 1 mV shift for ±5V variation
'in either supply. Drift is typically 250 p.V1°C and distortion is
inside 1 %.
' ,
20 p.s/Div
2V/Div
FIGURE 6. Waveforms from the oscillator shown In
Figure 5 show that upon receiving A 1's negative
voltage (Trace A), A2 ramps In a positive direction (B).
This ramp Joins the AC feedback delivered to A3's
positive Input (C); Trace D depicts A3's posltlve-golng
outpU1. This output In tum lalnverted by the 2N2369
translator (E), which turns off the 2N4393 and drives
A 1's positive Input above ground. A2's triangle output
also connects to four sln_hapar transistors and A4
and finally emerges as the circuit's sine wave output (F).
A distortion analyzer's output (G) shows the circuit's
minimum distortion products attar trimming.
630
0.02
>-4~--"'-------O SINE WAVE OUTPUT
12.50Vrmsl
lOOk
-15V
L----I2N2222A
Ql
I.2k
2k
lOOk'
1M
5k
REFERENCE
TRIM
LM329
03
All diodes
~
I N4148
02
lOOk'
All capacilors in ,.F
•
~
I%
AI. A2
meta~film
~
types
LF353 dual
TL/H/6932-8
FIGURE 8. Reduce parts count and save money by basing this precision sine wave voltage reference on an LF353 dual
FET op amp IC. This circuit generates a 1 kHz sine wave at 2.50 Vrms. The 2N2222A transistor functions as a phaseshift oscillator. The A 1, A2 combination amplifies and amplitude stabilizes the circuit's sine wave output.
ANALOG-TO-DIGITAL CONVERTER
and a new conversion cycle starts. False data at the converter output is prevented during the time A 1 is high by resistor. diode gating at the 2N3904 base.
An extremely versatile integrating analog-to-digital co~vert
er appears in Figure 9. A Single LF347 quad implements the
AID converter which can be either intemally or externally
triggered. As shown. the converter provides a 10-bit serial
output word with a 10 ms full-scale conversion time.
Normally, a ± 1 count uncertainty at the output will be introduced because the 100 kHz clock runs asynchronously with
the conversion cycle. This problem is eliminated by the diode and 4.7k resistor which run between A1's output and
the A3 negative input These components force the oscillator to synchronize to the conversion cycle at each falling
edge of A 1's output. The length of time between conversions in the "free run with delay" mode is adjustable by
varying the RC combination associated with this switch position. The converter may be triggered externally by any
source with a greater than 2V amplitude. In the "free run"
mode the converter self triggers immediately after A4 goes
high. Thus, the conversion time will vary with the input voltage.
To understand this circuit assume the mode select switch is
in the "free run with delay" position and the 2N4393 FET
has Just been turned off. The A2 integrator, biased from the
LM129 reference, begins to ramp in a negative-going direction (Trace B, Ff9Ure 10): The 2N2222A transistor provides
a -0.6V or a + 7V feedback output bound for A4, keeping
its output from saturatin9 and aiding high speed response.
AC positive feedback assures clean transitions. A3 is set up
as a 100 kHz oscillator. The LM329 and the diodes provide
a temperature compensated bipolar switching threshold reference for the oscillator. During the time A4 is low the pulses from A3's output are passed by the 2N3904 transistor.
When A4 goes high the 2N3904 is biased on and no more
pulses appear (Trace D, Figure 10). Since A2's output ramp
is linear the length of time A4 spends low is directly proportional to the value of EIN. The number of pulses at the
2N3904 output provides a digital indication of this information. A2'.s ramp continues to run after A4 g~s high and the
actual conversion ends. When the time constant associated
with the "free run with delay" mode charges to 2V A 1's
output goes high (Trace A, Fl{lure 10), turning on the
2N4393 FET, which resets the integrator. A 1 stays high until
the AC feedback provided by the 150 pF capacitor decays
below 2V. At this point A1 goes low, A2 begins to ramp
This is graphically illustrated in the photo of Figure 11. Here,
a positive biased sine wave (Trace B, Figure 11) is fed into
the AID input. Because the AID resets and self triggers
immediately after converting, the A2 ramp output shapes a
ramp constructed envelope of the input signal (Trace C, Figure 11). Trace A shows this in time expanded form. Note
that the -120 ppm/DC temperature coefficients of the Polystyrene capaCitors in the integrator and oscillator will tend to
track, aiding drift performance in this circuit. From 15°C to
35°C this circuit achieves 10-bit absolute accuracy. To calibrate this circuit apply 1O.OOV to the input and adjust the FS
trim for 1000 pulses out per conversion. Next, apply 0.05V
and adjust zero trim for 5 pulses out per conversion. Repeat
this procedure until the adjustments converge.
631
;
Nr-----------------------------------------------------~
All diodes = 1N4148
... = 2 kG 10,20 MG typ for delays up 10 20 sec
.. = Polystyrene types
• = Metal-film types
A1-A4 ,= LF347 quad
2k'
4.7k
Ik
lB01.f-1'
'1II1I1I
fULL·SCALE
TRIM
2.2k
Isvo-~iv-.....~M....._"I,M...._t
18"*
1ft
11k"
liV
TTL
OUTPUT
16V
U.
4.lk
4.7k
TLlH/6932-9
FIGURE 9_ Three mode select switch positions offer a choice of Intemator external trigger
, conditions for this Integrating AID cohverter. Over 15"C to 35"C, this trimmable converter
provides a 10·blt serial output, converts In 10 ms and accepts OV to 10V Inputs_
TL/H/6932-10
Trace
Vertical
A
5V/Oiv
10V/Oiv
10VlOlv
5V/Oiv
B
C
0
TLlH/6932-11
Horlzontsl
1 ms/OiY
Trace
Vertical
Horlzontsl
A
B
C
W/Oiv
5V/Ow,'
2 ma/Div
20 ms/Ow
5V1Dw
2Oms/Div
FIGURE 11.lIIu8tratlngthe AID cOnverter'8 operation In
the "free run" mode, Trace B ShOW8 a poslth(ely, biased
sine wave Inpllt. J;lecauSe reset and ",If trigger occur
'In8tantly after converSion: A2'8 output proclucu a'
ramp-constructed envelope of the Input (Trace C).
Trace A ShOW8 a time expanded form of the envelope
waveform. '
FIGURE 10, Depicting the operation of Flgure,9's AID
circuit In "free run with dela,y" mode" Trace'A shows
A 1's output low_ In thla stste, integrator A2 atarta to
ramp In a negatlve;.golng direction (Trace B). When A2's
, ramp potential barely exceeds the input voltage'8"
riegatlve value, A4'8 output gos8hlgh (C). Thl8
tranaltlon turns on the 2N3904 transi8tor, which shuts
off the TTL output pulse train (D).
632
packages permit ±40 mA of output current. The series, RC
damper prevents oscillations. The circuit of Figure 13 issimilar but features a gain of 10 and output to a floating load.
A 1 amplifies the signal and A2 helps it drive the load. A3
operates as a unity gain inverter and A4 helps it to drive the
load. This circuit will easily drive a 20000. floating load to
±20V.
HIGH OUTPUT CURRENT AMPLIFIER
Figure 12 shoWs,. scheme for obtaining high output current
into a load by using all 4 amplifiers in an LF347 to supply
output power. It operates on the principle that all the amplifiers have to supply the same current as A 1, whether that
current is plus, minus or zero. A single LF347 can be used
to drive a 6000. load to ± 11V in this fashion. Two LF347
41
41
41
..
~----~----+------+------4+
I
TO ADDITIONAL
LF3471FOR
IIORE._R
LOAD
A1-A4
= LF347 quad
TLlH/6932-12
FIGURE 12. Utilizing current-amplifying capabilities, one LF,347 can drive a 6000. ioad to ± 11Y.
For additional power, two LF347's can aupply an output current of ± 40 mAo
10k
LOAD
51
20110
ZOk"
'=
••
1% types
A1-A4 = LF347 quad
TLlH/6932-13
FIGURE 13. Configured as a high output current amplifier with a gain
of 10, this LF347 circuit can drive a 2000. floating load to ±20Y.
633
National Semiconductor
Application Note 263
Sine Wave Generation
Techniques
Producing and manipulating the sine wave function is a
shift configuration and oscillates at about 12 kHz. The recommon problem encountered by circuit designers. Sine
maining circuitry provides amplitude stability. The high imwave circuits pose a significant design challenge because
pedance output at 02's collector is fed to the input of the
they represent a constantly controlled linear oscillator. Sine
LM386 via the 10 ,..,F-1 M series network. The 1M resistor in
wave circuitry is required in a number of diverse. areas, incombination with the internal 50 kO unit in the LM386 dicluding audio testing, calibration eqUipment, transducer
vides 02's output by 20. This is necessary because the
drives, power conditioning and automatic test equipment . LM386 has a fixed gain of 20. In this manner the amplifier
(ATE). Control of frequency, amplitude or distortion level is
functions a~ a unity gain current buffer which will drive an
often required and all threa parameters must be simulta80 load. The positive peaks at the amplifier output are rectin~usly controlled in many applications.
fied and stored in the 5 ,..,F capacitor. This potential is fed to
the base of 03. 03's collector current will vary with the difA number of techniques utilizing both analog and digital apference between its base and emitter voltages. Since the
proaches are available for a variety of applications. Each
emitter voltage is fixed by the LM313 1.2V reference, 03
individual circuit approach has inherent strengths and we~
performs a comparison function and its collector current
nesses which must be matched against any given applicamodulates 01's base voltage. 01, an emitter follower, protion (see table).
vides servo controlled drive to the 02 oscillator. If the emitPHASE SHIFT OSCILLATOR
.ter of 02 is opened uP. and driven by a control voltage, the
A simple inexpensive amplitude stabilized phase shift sine
amplitude of the circuit output may bEi varied. The LM386
output will drive 5V (1.75 Vrms) peak-to-peak into 80 with
wave oscillator which requires one IC package, three transistors and runs off a single supply appears in FlfJure 1.02,
about 2% distortion. A ± 3V power supply variation causes
in combination with the RC network comprises a phase
less than ± 0.1 dB amplitude shift at the output.
1M
":"
":"
lM386
+
10~F
lN914
+
lOOk
8
LOAD
5~F
":"
2k
01-03 2N3904
TL/HI7483-1
FIGURE 1. Phase-shift sine wave oscillators combine simplicity with versatility.
This 12 kHz design can deliver 5 Vp-p to the ao load with about 2% distortion.
634 .
Sine-Wave-Generation Techniques
Typical
Amplitude
Stability
(%)
Typical
Frequency
Range
Typical
Distortion
(%)
Phase Shift
10Hz-1 MHz
1-3
3 (Tighter
with Servo
Control)
WelnBrldge
1 Hz-1 MHz
0.01
1
Extremely low distortion. Excellent for high-grade
instrumentation and audio applications. Relatively
difficult to tune-requires dual variable resistor with
good tracking. Take considerable time to settle after
a step change in frequency or amplitude.
LC
Negative
Resistance
1 kHz-10MHz
1-3
3
Difficult to tune over wide ranges. Higher Q than RC
types. Quick starting and easy to operate in high
frequency ranges.
Tuning Fork
60Hz-3kHz
0.25
0.01
Crystal
30 kHz-200 MHz
0.1
1
Highest frequency stability. Only slight (ppm) tuning
possible. Fragile.
TriangleDriven Break·
Point Shaper
< 1 Hz-500 kHz
1-2
1
Wide tuning range possible with quick settling to new
frequency or al\1plitude.
TriangleDriven
LogarHhmlc
Shaper
< 1 Hz-500 kHz
0.3
0.25
Wide tuning range possible with quick settling to new
frequency or amplitude. Triangle and square wave also
available. Excellent choice for general-purpose
requirements needing frequency-sweep capability with
low-distortion output.
DAC·Drlven
logarithmic
Shaper
< 1 Hz-500 kHz
0.3
0.25
Similar to above but DAC-generated triangle wave
generally easier to amplitude-stabilize or vary. Also,
DAC can be addressed by counters synchronized to a
master system clock.
ROM·Drlven
DAC
1 Hz-20MHz
0.1
0.01
Powertul digital technique that yields fast amplitude
and frequency slewing with little dynamiC error. Chief
detriments are requirements for high-speed clock (e.g.,
8-bit DAC requires a clock that is 256 x output sine
wave frequency) and DAC glitching and settling, which
will introduce significant distortion as output
frequency increases.
Type
LOW DISTORTION OSCILLATION
Comments
Simple, inexpensive technique. Easily amplitude servo
controlled. Resistively tunable over 2: 1 range with
little trouble. Good choice for cost-sensitive, moderateperformance applications. Quick starting and settling.
Frequency-stable over wide ranges of temperature and
supply voltage. Relatively unaffected by severe shock
or vibration. Basically untunable.
iting action of the positive temperature coefficient bulb in
combination with the near ideal characteristics of the Wein
network allow very high performance. The photo of Figure 3
shows the output of the circuit of Figure 2a. The upper trace
is the oscillator output. The middle trace is the downward
slope of the waveform shown greatly expanded. The slight
aberration is due to crossever distortion in the FET-input
LF155. This crossover distortion is almost totally responsible for the sum of the measured 0.01 % distortion in this
In many applications the distortion levels of a phase shift
oscillator are unacceptable. Very low distortion levels are
provided by Wein bridge techniques. In a Wein bridge stable
oscillation can only occur if the loop gain is maintained at
unity at the oscillation frequency. In Figure 2a this is
achieved by using the positive temperature coefficient of a
small lamp to regulate gain as the output attempts to vary.
This is a classic technique and has been used by numerous
circuit designers" to achieve low distortion. The smooth lim-
'Including William Hewlett and David Packard who built a few of these type circults In a Palo AltO garage about forty years ago.
635
oscillator. The output of the distortion analyzer is shown in
the bottom trace. In the circuit of F/{/ure 2b, an electronic
equivalent of the light bulb Is used to control loop gain. The
zener diode determines the output amplitude and the loop
time constant is set by the 1M-2.2 "F combination.
loop. The LM3900 Norton amplifiers comprise a 1 kHz amplitude controllable oscillator. The LHoo02 buffer provides
low impedance drive to the LS-52 audio transformer. A voltage gain of 100 is achieved by driving the secondary of the
transformer and taking the output from the primary. A current-sensitive negative absolute value amplifier composed
of two amplifiers of an LF347 quad generates.a negative
rectified feedback signal. This is compared to the LM329
DC reference at the third LF347 which amplifies the difference at a gain of 100. The 10 "F feedback papacitor is used
to set the frequency response of the loop. The outpu~ of this
amplifier controls the amplitude of the LM3900 osoillalqr
thereby closing the loop. As shown the circuit oscillates at 1
kHz with under 0.1 % distortion for a 100 Vrms (285 Vp-p)
output. If the summing resistors from the LM329 are replaced with a potentiometer the loop is stable for output
settings ranging from 3 Vrms to 190 Vrms (542 Vp-p!) with
no change in frequency. If the DAC1280 D/A converter
shoWn In dashed lines replaces the LM329 reference, the
AC output voltage can be controlled by the digital code input
with 3 digit calibrated accuracy.
.
The 2N3819 FET, biased by the voltage across the 2.2 "F
capacitor, is used to control the AC loop gain by shunting
the feedback path. This circuit is more complex than Figure
2a but offers a way to control the loop time constant while
maintaining distortion performance almost as good as in
Figure2a.
HIGH VOLTAGE AC CALIBRATOR
Another dimension in sine wave oscillator design is stable
control of amplitude. In this circuit, not only is the amplitude
stabilized by servo control but voltage gain is included within
the servo loop.
A 100 Vrms output stabilized to 0.025% is achieved by the
circuit of Figure 4. Although complex in appearance this circuit requires just 3 IC packages. Here, a transformer is used
to provide voltage gain within a tightly controlled servo
O.068~F
430
>-+--0 SINE·WAVE
0.068
OUTPUT
~F
>-+-0 SINE·WAVE
OUTPUT
TYPE
lN457
O.Ol~F
327
LAMP
1N755
(7.SV)
SOOk
lOOk
TL/HI7483-2
TL/HI7483-3
(a)
(b)
FIGURE 2. A baalc Weln bridge design (a) employs a lamp's positive temperature cosfflclent
to achieve amplitude stability. A more complex version (b) provides
the 88me 'eature with the additional advantage 0' loop time-constant control.
11\ ,
1\ 11\ 1\ 1\ 1\ 11\
VIV.' VV VV.
.........
r--...
~V
~I\ 11\ ~I\
IV
~V
IV
Trace
.........
"-
.......
A
r-....
Vertical
Horizontal
Top
10VlDIV 10ms/DIV.
Middle lv/DIV 500ns/DIV
Bottom 0~5V/DIV 500ns/DIV
~
~~
\~
TLlHI7483-4
The
FIGURE 3. Low-dlstortlon output (top trace) Is a Weln bridge 08clllator 'eature;
very
low crossover distortion level (middle) re8Ults 'rom the LF155's output stage. A distortion
analyzer's output signal (bottom) Indicates this design's 0.01 % distortion level.
636
lOOk
.--~"""'015V
BINARY INPIITS
A 1-A3 =
V. LM3900
A4 = LH0002
= V. LF347
= UTC LS-52
A!I diodes = lN914
• = low-TC, metal-film types
AS-A7
T1
TLlHI7483-5
FIGURE 4_ Generate high-voltage sine wsves using IC-baaed circuits by driving a transformer In a step-up mode. You
can realize digital amplitude control by replacing the LM329 voltage reference with the DAC1287.
matched pair accomplish a voltage·to·current conversion
that decreases 03's base current when its collector voltage
rises. This negative resistance characteristic permits oscilla·
tion. The frequency of operation is determined by the LC in
the 03·05 collector line. The LF353 FET amplifier provides
gain and buffering. Power supply dependence is eliminated
by the zener diode and the LF353 unity gain follower. This
circuit starts quickly and distortion is inside 1.5%.
NEGATIVE RESISTANCE OSCILLATOR
All of the preceding circuits rely on RC time constants to
achieve resonance. LC combinations can also be used and
offer good frequency stability, high 0 and fast starting.
In Figure 5 a negative resistance configuration is used to
generate the sine wave. The 01-02 pair provides a 15 p.A
current source. 02's collector current sets 03's peak collector current. The 300 kO resistor and the Q4-05 LM394
1.8k
.-----._----~.---------._~~--015V
S.ak
180k
180k
lmH
2x2N3810
V,LF353
Uk
LM329
VtLF353
SINE·
>-11"""""-0 WAVE
5.1k
OUTPUT
910
TLlHI7483-6
FIGURE 5. LC sine wave sources offer high stability and reasonable distortion levels. Transistors 01 through 05
implement a negative-resistance amplifier. The LM329, LF353 combination eliminates powe....upply dependence.
637
RESONANT ELEMENT OSCILLATOR-TUNING FORK
All of the above oscillators rely on combinations of passive
components to achieve resonance at the oscillation frequency. Some circuits utilize inherently resonant elements'
to achieve very high frequency stability. In Figure 6 a tuning
fork is used in a feedback loop to achieve a stable 1 kHz
output. Tuning fork oscillators will generate stable low frequency sine' outputs under high mechanical ',shock condi~'
tions whiCh would fracture a quartz crystal.
'
Because of their excellent frequency stability, small size and
low power requir~ments, 'they have been used in airborne
applications, remote instrumentation and even watches.
The low frequencies achievable with tuning forks are not
lk
available from crystals. In Figure 6, a 1 kHz fork is used in a
feedback configuration with 02, one transistor of an
LM3045 array. 01 provides zener drive to the oscillator circUit. The need for amplitude stabilization' is eliminated by
allowing the oscillator to go into limit. This is a conVentional
technique in fork oscillator design. 03 and 04 provide edge
speed-up and a 5V output for TIL compatibility. Emitter follower 05 is used to drive an LC filter which provides a sine
wave output. Figure 68, trace A shows thEi square wave
, output while, trl!,ce B depicts the sine wave output. The 0.7%
distortion in the sine wave output is shown in trace C, which
is the output of a distortion analyzer.
10k
10k
10k
220
lk
SINE.
01-05 = LM3045 array
VI =1 kHz tuning fork,
Fork Standards lne.
'-~"""'Y'I"Y'\",-o WAVE
'OUTPUT
All capaCitors In ,.F
TUHI7483-7
FIGURE 6. Tuning fork based OSCillators don't Inherently produce sinusOidal outputs. But when you do use
them for this purpoae, you achieve maximum stability when the oscillator stage (01, 02) limits.
03 and 04 provide a TTL compatible Signal, which 05 then converts to • sine wave.
-
10-
......;
1-
J"
J "\J ~7 '"
~l
\, ~ I \,
v
'V;
"\J
\
1\
1)
r\
~
-
"
\I \
It r\ .It
Trace
\J IJ'\
Vertical
Horizontal
Top
5V1DIV
Middle 50VlDIV 500p.s/DIV
Bottom O.2V/DIV
Tl/HI7483-8
FIGURE 6a. Various output levels are provided by the tuning fork OSCillator shown In FIgure 6.
This design easily produces a TTL c~mpatlble signal (top trace) because the oscillator is allowed
to limit. Low-pass filtering this square wave generates a sine wave (middle). The OSCillator's
0.7% distortion level Is Indicated (bottom) by an analyzer's output
638
crystal. The varactor is biased by a temperature dependent
voltage from a circuit which could be very similar to Rgure
7b without the output transistor. As ambient temperature
varies the circuit changes the voltage across the varactor,
which in turn changes its capacitance. This shift in capacitance trims the oscillator frequency.
RESONANT ELEMENT OSCILLATOR-QUARTZ
CRYSTAL
Quartz crystals allow high frequency stability in the face of
changing power supply and temperature parameters. Figure
7a shows a simple 100 kHz crystal oscillator. This Colpitts
class circuit usas a JFET for low loading of the crystal, aiding stability. Regulation will eliminate the small effects (- 5
ppm for 20% shift) that supply variation has on this circuit.
Shunting the crystal with a small amount of capacitance allows very fine trimming of frequency. Crystals typically drift
less than 1 ppml"C and temperature controlled ovens can
be used to eliminate this term (Figure 7b). The RC feedback
values will depend upon the thermal time constants of the
oven used. The values shown are typical. The temperature
of the oven should be set so that it coincides with the crystal's zero temperature coefficient or "turning pOint" temperature which is manufacturer specified. An alternative to temperature control uses a varactor diode placed across the
APPROXIMATION METHODS
All of the preceding circuits are inherent sine wave generators. Their normal mode of operation supports and maintains a sinusoidal characteristic. Another class of oscillator
is made up of circuits which approximate the sine function
through a variety of techniques. This approach is usually
more complex but offers increased flexibility in contrOlling
amplitude and frequency of oscillation. The capability of this
type of circuit for a digitally controlled interface has markedly increased the popularity of the approach.
15V~--f-------------------------'
4.7k
4.7k
O.~~FT ~":"1
OPTIONAL I~
VARACTOR
=
n
CONTROL
O.OOll'f
10k
E---o
18.6k
Y,
0--+-*",,"-+1
-15V~------__- _ . J
LM335
2N3823
~
I
I
I
Y1 = 100 kHz crystal
I
........""'''-0("1
3k
-15V
LM328
":"
THERMAL FEEDBACK
~--------------------------~
TLlH/7483-9
TL/HI7483-10
(a)
(b)
lOOk
Ao--AIII'--'~-Ol CONTROL
VCC.I600
OUTPUT
6~YSTAL
COOl
TL/HI7483-11
(c)
FIGURE 7. Stable quartz-crystal OSCillators can operate with a single active device (a). You can achieve
maximum frequency stablll.y by mounting the oscillator In an oven and using a temperature-controlling
circuit (b). A varactor network (c) can also accomplish crystal fine tuning. Here, the varector replacas the
oven and retunes the crystal by changing Its load capacitances.
639
SINE APPROXIMA1'ION-BREAKPOINT SHAPER
Figure 8 diagrams a circuit' which will "shape" .a 20 Vp-p
wave input into'a sine wave output. The amplifiers serve to
establish stable bias pOtentials for the diode shaping network. the shailer operateS by having indiVidual diooes tum
on or off depending upon the amplitude of the input triangle.
This changes the gain of the output amplifier, aod gives the
circuit its characteristic non-linear, shaped output response.
The values of the resistors associated with the diodes determine the shaped waveform's appearance. h,dividual diodes
in the DC bias circuitry provide first order temperature coinpensation for. the shaper diodes. Figure 9 sl)ows the circuit's
performance. Trace A is the filtered 'output (note 1000 pF
capacitor across the output amplifier). Trace B shOWS the
waveform with no. filtering (1000pF capacitor. removed) and
trace C i~ the output of a distortion analyzer. In trace· B the
breakpoint action is. just detectable at the top and bottom of
the waveform, but all the breakpoints are clearly identifiable
in the distortion analyzer output of trace C. In this circuit, if
tile ,amplitUde or symmetry of the input triangle wave shifts,
the output waveform will degrade badly. Typically, a D/A
cqnverter will be, used to provide input drive. Distortion in
this circuit is IjlBs than 1.5% for a filtered output. If no filter is
used, this, figure rises to about 2.7%.
.
15V
LM313
10k
1.3k
6.81k
l.96k
1M
~:g~~~.-7~.8~7~k~__+-~-+~4.0~2~k~~____~
1M
QAC
10 ~F
7.32k
15k
SINE-
>""'-0 WAVE
OUTPUT
All diodes = 1 N4148
All op amps = % LF347
-15V
TLIH/7483-12
FIGURE 8. Breakpoint shaping networks employ dlo~es that conduct In direct proportion to an Input triangle wave's
amplitude. This action changes the output amplifier'S gain to produce the sine function.
Trace
A
B
C
Vertical
HoriZontal
5V1DIV
5V1DIV 20 ,,"s/DIV
0.5V1DIV
TLlHI7483-13
FIGURE 9. A clean sine wave results (trace A) when FIgure 8'. circuit's output Includes a 1000 pF capacitor.
When the capaCitor isn't used, the diode network's breakpoint action becomes apparent (trace B).
The distortion analyzer's output (trace C) clesrly shows all the breakpoints.
640
SINE APPROXIMATION-LOGARITHMIC SHAPING
Figure 10 shows a complete sine wave oscillator which may
be tuned from 1 Hz to 10 kHz with a single variable resistor.
Amplitude stability is inside 0.02%/OC and distortion is
0.35%. In addition, desired frequency shifts occur instantaneously because no control loop time constants are employed. The circuit works by placing an integrator inside the
positive feedback loop of a comparator. The LM311 drives
symmetrical, temperature-compensated clamp arrangement The output of the clamp biases the LF356 integrator.
The LF356 integrates this current into a linear ramp at its
output. This ramp is summed with the clamp output at the
LM311 input. When the ramp voltage nulls out the bound
voltage, the comparator changes state and the integrator
output reverses. The resultant, repetitive triangle waveform
is applied to the sille shaper configuration. The sine shaper
utilizes the non-linear, logarithmic relationship between Vbe
and collector current in transistors to smooth the triangle
wave. The LM394 dual.transistor is used to generate the
actual shaping while the 2N381 0 provides current drive. The
LF351 allows adjustable, low impedance, output amplitude
control. Waveforms of operation are shown in Figure 11.
1.2k
lSV 0---.1'.111'----.
SpF
lOOk
1.2k
7Sk
10k
Sk
Sk
WAVE·SHAPE
TRIM
LM329
lSV
SYMMa::!..
2S_k..N..,...._
ADJUST
7Sk
AMPLITUDE
-lSV
10k
All diodes = 1N4148
Adjust symmetry and waV&o
100
shape controls for minimum distortion
SINE·
>--41-0 WAVE
OUTPUT
·LM311 Ground Pin (Pin 1) at -15V
200
47
47
15k
'----4_-.JI>I\I'--Q-15V
TUHI7483-14
FIGURE 108. logarithmic shaping schemes produce a sine wave OSCillator that you can
tune from 1 Hz to 10 kHz with a single control. Additionally. you can shift frequencies rapidly
because the circuit contains no control-loop time constants.
641
~ r-------------------------------------------------------------------------------------~
i
SINE APPROXIMATION-VOLTAGE CONTROLLED
SINE OSCILLATOR
FigUI8 10b details a modified but extremely powerful version
of F/{Jure 10. Here, the input voltage to the LF356 integrator
is furnished from a control vciitage input instead of the zener
diode bridge. The control input'is inverted by the LF351. The
two complementary voltages are each gated by the ~N4393
FET switches, which are controlled by the LM311 output.
The frequency
of oscillation
will now vary in direct propor,
,
tion to the control input. In addition, because the amplitude
of this circuit is controlled by limiting, rather than a servo
loop, response to, a control step or ramp input Is almost
instantaneous. For a OV -1 OV input the output will run over 1
Hz to 30 kHz with less than 0.4"10 distortion, In addition,
linearity of control voltage vs output frequency will ba within
0.25"10. F/{Jure 10e shows the response of this circuit (waveform B) to a 10V ramp (waveform A).
ZERO-FREQUENCY
TRIM
15V o--.NIIMI'--.o - 15V
CONTROL·
VO~~~~~~
__________-t~
(()'10V)
1M
10k
~~-.Nv_6---------------~~1.2~kl'--~15V
Adjust distortion for
minimum at 1 Hz to 10 Hz
Adjust full-scale for 30 kHz
at 10V Input
All diodes
= 1N4148
TLlHI7483-15
'Match to 0.1'"
FIGURE 10b. A voltage-tunable OSCillator results when Flgurtl 11h1's design Is modified to Il1cIude Ilgnal-levelcontrolled feedback. Here, FI:TI switch the Integrator'llnput 10 that the resulting lummlng-Junctlon currant II a
function of the Input control voltage. Thll scheme realizes a frequency range of 1 Hz to 30 kHz for a OV to 10V Input.
TLlHI7483-16
FIGURE 1Gc. Rapid frequency sweeping II an Inherent
festure of Figurtl 1Ob~ voltage-controlled sine wave
oscillator. You can Iweep this VCO from 1 Hz to 30 kHz
with a 10V Input Ilgnali the output lettles quickly.
642
SINE APPROXIMATION-DIGITAL METHODS
nated and the sine wave output taken directly from the
LF357. This constitutes an extremely powerful digital tech·
nique for generating sine waves. The amplitude may be volt·
age controlled by driving the reference terminal of the DAC.
The frequency is again established by the clock speed used
and both may be varied at high rates of speed without introducing significant lag or distortion. Distortion is low and is
related to the number of bits of resolution used. At the 8·bit
level only 0.50/0 distortion is seen (waveforms, F/{/ure 13;
graph, Figure 14) and filtering will drop this below 0.10/0. In
the photo of Figure 13 the ROM directed steps are clearly
visible in the sine waveform and the DAC levels and glitch·
ing show up in the distortion analyzer output Filtering at the
output amplifier does an effective job of reducing distortion
by taking out these high frequency components.
Digital methods may be used to approximate sine wave op·
eration and offer the greatest flexibility at some increase in
complexity. Figure 12 shows a 10·bit IC D/A converter driv·
en from up/down counters to produce an amplitude·stable
triangle current into the LF357 FET amplifier. The LF357 is
used to drive a shaper circuit of the type shown in Figure 10.
The output amplitude of the sine wave is stable and the
frequency is solely dependent on the clock used to drive the
counters. If the clock is crystal controlled, the output sine
wave will reflect the high frequency stability of the crystal. In
this example, 10 binary bits are used to drive the DAC so
the output frequency will be 1 /1024 of the clock frequency.
If a sine coded read-only·memory is placed between the
counter outputs and the DAC, the sine shaper may be elimi·
A
B~
C
r--.....
oV
E
\"
;...
r- ~.
.~
~
:--.... .........
.........
"'-
I - i--
"...
........
.......... r-..,... ~
-'"
r- ~
,/
V
V
V
- "'"
Trace
Vertical
A
B
C
D
E
20VlDIV
20V/DIV
10V/DIV
10V/DIV
0.5V/DIV
Horizontal
20 p.S/DIV
'\..
'\
TLIHI7483-17
FIGURE 11. logarithmic shapers can utilize a variety of circuit waveforms. The Input to the LF356 Integrator (Figure 10j
appears here as trace A. The LM311's Input (trace B) Is the summed result of the Integrator's triangle output (e) and the
LM329's clamped waveform. After passing through the 2N3810/LM394 shaper stage, the resulting sine wave Is
amplified by the LF351 (D). A distortion analyzer's output (E) representa a 0.350/0 total harmonic dlstortton.
643
LSB
WAVE-SHAPE
TRI",
15V
DAC-10z0
25k
75k
SYMMETRY Qo-.NIMI---K...
TRIM
-15V
-15V
MM74COO
MM74C32
MM74C74
MM74193
= NAND
= OR
= D flip-flop
= counters
TL/HI7483-18
FIGURE 12. Digital techniques produce triangular waveforms that methods employed In FlgulYl 1Da can then
easily convert to sine waves. This digital approach divides the Input clock frequency by 1024 and uses the
resultant 10 bits to drive a DAC. The DAC's triangular output_mplifled by the LF357-c:Jrives the log shaper
stage. You could also eliminate the log shaper and place a slne-coded ROM between the counters' outputs
and the DAC, then recover the sine wave at point A.
/
V'
- 'I\.
,
":\.
Trace
Vertical
Horizontal
Sine Wave W/DIV
200J.l.s/DIV
Analyzer O.2V/DIV
/.
~V
'-I"
TLlHI7483-19
FIGURE 13. An 8-blt sine coded ROM version of FlgUIYl 12'. circuit produces a distortion level less than 0.5%. Filtering
the sine output_hown here with a ,distortion analyzer's trace-can reduce the distortion to below 0.1 %.
644
20
16
,
I
10
8
6
5
4
~
Z
0
j::
II:
i
,
3
I
I
2
/
,.
I
1.0
0.8
0.6
0.5
0.4
0.3
I
.
I
/
/
/
/
I
I
/
/
,,.
,,I
SLOPE = 6 dB/BIT
WITHOUT FILTERING
I
I
0.2
0·~'=:0--J9~""""*8-~7--J6r---.t5--+4-""'3t-----
RESOLUTION (BITS)
TL/HI7483-20
FIGURE 14. Distortion levels decrease with Increasing
digital word length. Although additional filtering can
considerably Improve the distortion levels (to 0.1 % from
0.5% for the 8-bit case), you're better off using a long digital word.
645
An Electronic Watt-WattHour Meter
National Semiconductor
Application Note 265
The continued emphasis on energy conservation has forced
designers to consider the power consumption and efficiency
of their products. While equipment for the industrial market
must be designed with attention towards these factors, the
consumer area is even more critical. The high cost of electricity has promoted a great deal of interest in the expense
of powering various appliances. The watt-watt-hour meter
outlined in Figure 1 allows the designer to easily determine
power consumption of any 115V AC powered device. The
extremely wide dynamic range of the design allows measurement of loads ranging from 0.1 W to 2000W.
input. Switchable gain at the current amplifier allows decade
setting of instrument sensitivity. The instantaneQus power
product (E X I) drawn by the load is represented by the multiplier output. Because the multiplier is a 4-quadrant type, its
output will be a true reflection of load power consumption,
regardless of the phase relationship between voltage and
current in the load. Because the multiplier and Its associated
amplifiers ara connected directly to the AC line, they must
be driven from a floating ROWer supply. In addition, their
outputs cannot be safely monitored with grounded test
equipment, such as strip chart recorders. For this reason,
the multiplier output drives an isolation amplifier which operates at unity'gain but has no galvanic connection between
its input and output terminals.
Conceptually, the instrument is quite straightforward (Figure
1). The device to be monitored is plugged into a standard
110V AC outlet which is mounted on the front panel of the
instrument. The AC line voltage across the monitored load
is divided down and fed via an op amp to one input of a 4quadrant analog multiplier. The current through the load is
determined by the voltage across a low resistance shunt.
Even at 20A the shunt "steals" only 133 mV, eliminating the
inaccuracies a high resistance current shunt would. contribute. This single shunt is used for all ranges, eliminating the
need to switch in high impedance shunts to obtain adequate
signal levels on the high sensitivity scales.
This provision is made possible by loW uncertainty in the
current amplifier, whose output feeds the' other multiplier
This feature is accomplished through pulse amplitude modulation techniques in conjunction with a small transformer,
which provides isolation. The isolated amplifier output is
ground referenced and may safely be connected to any
piece of test equipment. This output Is filtered to provide a
strip chart output and drive the readout meter, both of which
indicate load power consumption. The isolation amplifier
output also biases a voltage-to-frequency converter which
combines with digital cOunters to form a digital integrator.
ThiS allows power Over time (watt-hours) to be integrated
and displayed. Varying the divide ratio of the counters produces ranging Of the watt-hour function.
VOLTAGE
CURREIl
CURRENT
SHUNT
DIGITAL
WATT AND POWER
DISPLAY
DIGITAL
DIVIDER
CHAIII
VDLTAGE·TD·
FREDUENCY
CONVERTU
TL/H/5626-1
FIGURE 1
646
In
-
1IVO
•
ISV
FLOATINO
1II1II
ACQ
STANCOR
CIIUI. . .AI
,
r
plL-...~"N"·Ir-.-+14.,
I.II.F
TRWfC.IIII.3Z
PRIMARYSHGWI
IIEEFI8UREZHOR
IECONOARY COINEcnONS)
I"
II.
RLOAO
ft
4AII"
I.&M
JpF
"
1111
•
RANOE
SCALE
ACLINE
1-
1M
~
i~::~
III
1111
I. .
IIIV
1111
....
....
I"
ISV
h1Nnl5
~I'
~A
•
~_R
;:::;,.
1ft
-IIV
1111
Note 1: All diodes 1N4148.
Note 2: ,/, floating ground connected to neutral side of 110 VAC line.
Nole 3: R # ~ G.E. current shunt 5O-14OO34NDAA.
1-
1111
Note 4: Circuit power from ± 15V fIosting supply shown in schemstic.
Note 5: 'Resistors are 1% metal film types.
-15V
TLfHf5826-2
FIGURE 2a. Roatlng Half of Circuit is Connected Directly to the AC Une. Always Use Caution when Working with this Circuitry.
S9~·NV
~ r---------------------------------------------------------------------------------~
~
I.V
Z
4
1M
HART
~
ADJUST
IGV·5VI
SECONDARY OF
TRW TC-BSO-3Z
'ill
CHART
DUTFUT
_
"'----...,....------0
,II1II*
15Vo-....--"f
INSTANT
ANALOG
OUTPUT
LM331'
V/f
CONVERTER
.~a.DlIP"',
511*
r---....;;;.----.. . . . ..y,,.,,....
1111
-o15V
DIGITAL· ,
DIVIDER
CHAIN
,I._II
TUH/5626-3
Note 1: 'Resistors are 1% metal film types.
Note 2: "Polystyrene capacitor.
..ote 3: DO NOT cennect (...) ground of this hall of ,cIrcu~ to (m) ground of F/gur9 28.
Note 4: ± 15V p~ must ceme frem a source other than floating supply of FIfJUI'6 28.
Note S: Figute 2s and Figute 2b must be electrically IsolBtaiI frOm each other.
FIGURE 2b. Grounded Side of Circuit. This Circuit can Safely Be Connected to a 'Ch~rt
Recorder or ComPuter Due to Isolation Provided by TRW Transformer.
Figures 2aand 2b show the detailed schematic, with Figure
ranges. The 1N1195 diodes and the 20A fuses protect A1
and the shunt in the event a short appears across the load
test socket. The voltage and current signals are multiplied
by a multiplier configuration comprised of amplifiers A3, C
and 0, and the LM394 dual transistors. The multiplier Is of
the variable transconductance type and works by using one
input to vary the gain of an amplifier whose output is the
other input of the multiplier.
3 giving the waveforms of operation. The AC line is divided
down by the 1OO:'kG -4.4 kG resistor string. % of A2 (amplifier A) serves as a buffer and feeds one input of an analog
multiplier configuration. A1 monitors the voltage across the
current ,shunt,at a fixed gain of 100. The other half of A2 (B)
provides additional gain and calibrated switching of wattage
sensitivities from 2W to 2000W full-scale over four decade
648
The output of the multiplier (Figure 3, Trace A) represents
the instantaneous power consumed by the load. This information is used to bias a pulse amplitude modulating isolation amplifier. The isolation amplifier is made up of AS (A
and B) and the discrete transistors. The AS (A) oscillator
output (Figure 3, Trace B) biases the 01-02 switch, which
drives a pulse transformer. AS (B) measures the amplitude
of the pulses at the transformer and servo controls them to
be the same amplitude as its "+ .. input, which is biased
from the multiplier output. OS provides current drive capability and completes the feedback path for AS (B). Figure 3,
Trace 0 shows the pulses applied to the transformer. Note
that the amplitude of the pulses applied to the transformer
forms an envelope whose amplitude equals the multiplier
output. Figure 3, Trace C shows OS's emitter voltage changing to meet the requirements of the servo loop.
The amplitude modulated pulses appear at the transformer's secondary, which is referenced to instrument ground.
The amplitude of each pulse is sampled by AS, a samplehold amplifier. The sample command is generated by A4.
The output of AS is lightly filtered by the 1S kll - 0.02 ,.F
combination and represents a sampled version of the instantaneous power consumed in the load (FiI-
=lN4148
"* = Photodlode, RCA type
LATCHED
ALARM
OUTPUT
~708
Tl/H/5627-1
FIGURE 1. FIber ~pUc link eavesdroppIng aHempta are Immediately detactad by thla desIgn. WorkIng on a pul....bypulse comparison basis, A3 samples each Input pulse and holds Ita output amplitude value at a DC level. AnythIng
that disturbs the next Input's amplitude causes a Jump In this level; because A4 Is an AC-coupled amplifier, the
comparetor and latch then actIvate.
651
'( 's8mp/e-hOid control pulse to AS, which insures that AS's
OutpiJt III, sampled well after its OlltpUt. has settled. Under
,normal conditions, the pulse-ta-pulse amplitude variations at
As's output will be negligible, and the output of AS will be at
'a DC level. A4 is AC coupled and its output will be zero.
During an intrusion attempt, energy will be removed from
the line and AS's output will shift, causing AS to jump to a
new DC level. This shift will ~ AC amplified by A4 and the
A5 comparator will trip, activating the latch circuitry.
Note that the circuit is not affected by slow drifts in circuit
components over time and temperature because it is only
sensitive to AC disturbances 'on the line. In addition, the
frequency and pulse widths of the data may vary over wide
ranges. The photo of Ftgure 2 shows the circuit in operation.
Trace Ais AS's output. Trace 8 is the sample-hold control
pin at AS and Trace C is the latch-alarm output. In' ,this figure, a disturbance on the fiber optic line has occurred just
past the midpoint of the photo. This is reflected by the reduced amplitude of AS's output at this point. The latchalarm output goes high just after the sample command rises, due to the sample-hold amplifier jumping to the new
value at AS's output. In the photo, the disturbance has been
made large (""10%) for viewing purposes. In practice, the
circuit will detect an energy removal as small as 0.1 % from
the line.
TI.IH/5827-2
TRACE VERTICAL HORIZONTAL
A
B
C
10VlDIV
10V/DIV
10V/DIV
1 mSEC/DIV
1 mSEC/DIV
1 mSEC/DIV
FIGURE 2. An Intrusion attempt occurring Just past the
midpoint of Trace A Is Immediately detected by Figure
1'8 circuit. The photodetector's amplifier output (A)
shows a slight amplitude drop. The next time the S-H
amplifier samples this signal (B), the alarm latch sets
(C).
Proportional Pulse Stretcher
The circuit of Figure 3 allows high accuracy measurement of
short width pulse durations. The pulses may be either
HO.F
ISVo-.....- -....-"'I,.,.....-t
Uk
10k
-f>f-
= 1N4148
"* =Photodlode, RCA type C-30708
LMI29
NPN =2N2369
PNP = 2N2907A
LF347 = Quad op amp
TLlH/5827 -3
FIGURE 3. Pulse width measurement accuracy Is enhancei:l by this pulse stretChing circuit. A sllort Input 'pulse triggers
the 74121 ontHt1ot and (via 01) discharges the 100 pF capaCitor while concurrently turning on the recharging current
source, 03,'So long as the Input pulse Is' present, the capaCitor chargeS;' when the pulse ends, the capaCitor's voltage Is
proportional to the pulse's width. SoH amplifier A2 samples this voltage, and:'the resultant DC level controls the ON
duration of the A4/A5 pulse width modulator.
S52
repetitive or single-shot events. Using digital techniques, a
1 % width measurement of a 1 p.s event requires a 100 MHz
clock. This circuit gets around this requirement by linearly
amplifying the width of the input pulse with a time multiplying
factor of 1000 or more. Thus, a 1 p.s input event will yield a
1 ms output pulse which is easy to measure to 1 %. This
measurement capability is useful in high energy physics and
nuclear instrumentation work, where short pulse width signals are common.
ceives its sample-hold command from A3 (Figure 4, Trace
E-note horizontal scale change at this point). A3 is fed
from a delay network which is driven by A 1's inverting output. The output of A2 is a DC voltage, which represents the
width of the most recently applied pulse to the circuit's input. This DC potential is applied to A4, which along with A5
comprises a voltage controlled pulse width modulator. A5
ramps positive (Figure 4, Trace G) until it is reset by a pulse
from A6, which goes high for a short period (Figure 4, Trace
F) each time A3's output (Figure 4, Trace E) goes low. The
ramps at A6's output are compared to A2's output voltage
by A4, which goes high for a period linearly dependent on
A2's output value (Figure 4, Trace H). This pulse is the circuit's output.
In this particular circuit, the time amplification factor is about
2000 with a 1 p.s full-scale width giving a 1.4 ms output
pulse. Absolute accuracy of the time expansion is 1% (10
ns) referred to input with resolution down to 2 ns. The 50 ns
DM74121 reset pulse limits the minimum pulse width the
circuit can measure.
Figure 4, Trace A shows a 350 ns input pulse applied to the
circuit of Figure 3. The A 1 comparator output goes low (Figure 4, Trace B), triggering the DM74121 one shot, which
resets the 100 pF capacitor to OV via 01 with a 50 ns pulse
(Trace C). Concurrently, 02 is turned off, allowing the A3
current source to charge the 100 pF capacitor in a linear
fashion (Figure 4, Trace C). This charging continues until the
circuit input pulse ends, causing A 1's output to return high
and cutting off the current source. The voltage across the
100 pF capacitor at this point in time is directly proportional
to the width of the circuit input pulse. This voltage is sampled by the LF398 sample-hold amplifier (A2) which re-
A
8
C
D
F
Q
H
TLlH/5627 -4
TRACE VERTICAL HORIZONTAL
A
B
C
0
E
F
G
H
10VlDIV
5V1DIV
5V/DIV
5V/DIV
50VlDIV
50V/DIV
20VlDIV
100V/DIV
100 nSEC/DIV
100 nSEC/DIV
100 nSEC/DIV
100 nSEC/DIV
500 p.SEC/DIV
500 p.SEC/DIV
500 p.SEC/DIV
500 p.SEC/DIV
FIGURE 4. A sequence of. events In Figure 3's circuit
stretches a 350 ns Input pulse (A) by a factor of 2000.
When triggered, comparator A 1 goes low (B). This action
starts the recharging of a capaCitor (C) after Its previously stored charge has been dumped (D). When the input
pulse ends, the capacitor's voltage Is sampled under control of a delayed pulse (E) derived from the input amplifier's Inverting output (F). The sampled and held voltage
then turns off a voltage controlled pulse width modulator
(G), and a stretched output pulse results (H).
653
ControJled Amplitude Pulser
SimultaneouslY,the A1 sample-hold amplifier is placed in
the sample mode. When the pulse ends, A1~soutput'is ata
DC level equal to the amplitude of the' output pulse. This
level is compared tothe"amplitude set DC reference by A2:,
whose output drives 01. 01's emitter provides the DC supply level to the 02-03 switch. This servo action forces the
amplitude of the output pulse'toba the same as the'DC
potential at the amplitude set potentiometer wiper, regardless of 03 switch losses or loading. In Figure 6, Trace A Is
the circuit'output. Traces Band C detall the, rising and f,alllng
edges of the output (note h(l[izolltal sweep time change for
B and C) with clean 50 ns transitiOnS into the 200 load.,
FIgIH8 5 depicts a circuit which converts an input pulse traln
into an amplitude stabilized pulse output which will drive a
200 load:The ouljlut pulse amplitude is adjustable from OV
to' 1OV and is stable over time, temperature and load changes, This circuit function is useful in automatic test equipment
'
and general laboratory applications.
The circuit works by storing thEi sampled amplitude of the
output pulse as a DC level, and supplying this information to
a feedba<;k loop which controls the vol~ge applied to the
output switch. Each time a pulse is applied at the circuit input, th,e 02-03 combination turns on and drives the ioad.
470F
TANTALUM
IIV
r-~----~------~~
III
',=,
Ik
-IIV o-"V\~....-..,
It
IIIe
IIPUT
, COITROL
INPUT
~\
.
~o.ol~f
.'
'
, "
TUH/5627-5
FIGURE 5. Pulse amplitude control results whe11 this circuit samples an output pulse's amplitude and compares It with a
preset reference level. When the output exceeds this reference, A2 readJUiIts switching transistor Q3's supply voltage
to the correct level.
TRACE VERTICAL HORIZONTAL
A
A
8
8
C
10VlDIV
10V/DIV
10VlDIV
1 mSEC/DIV
100 nSEC/DIV
100 nSEC/DIV
c
Tl/H/5627-Q
FIGURE 6. A 10V, O.5A pulse (A) Is amplitude stabilized by the S-H technique dePicted In F/gurtI5. Note the clean 50 ns
rise (8) and fall (C) times.
' '
"
'
""
654
Isolated Input Signal Conditioning Amplifier
Figure 1 is a logical and very powerful extension of the controlled amplitude pulser shown in Figure 5. This circuit permits measurement of a small amplitude signal, e.g., thermocouples, in the presence of common-mode noise or voltages as high as 500V. This is a common requirement in
industrial control systems. Despite the fact that the input
terminals are fully galvanically isolated from the output, a
transfer accuracy of 0.1 % may be expected. With the optionallow-Ievel pre-amplifier shown, inputs as low as 10 mV
full-scale may be measured.
signal value. This pulse train drives a transformer which provides total galvanic isolation of the input circuitry from
ground. The transformer output is then demodulated back
to a DC level to provide the circuit's system ground referenced output. The amplitude of the pulse train which drives
the transformer is controlled by a loop very similar to the
one described in Figure 5. The amplitude set potentiometer
has been deleted, and the servo amplifier's" + .. input becomes the circuit input. A1, a low drift X1000 amplifier, may
be employed for boosting low-level inputs. The pulse train is
supplied by A2, which is set up as an oscillator (A2 output
shown in Figure 8, Trace A). The feedback to the pulse
amplitude stabilizing loop is taken from an isolated
The circuit works by converting the input Signal into a pulse
train whose amplitude is linearly dependent on the input
.
OUTPUT
• = 1% RN60C film resistor
-i>I- =IN4148
~ = Circuit and system ground
,J.
Floating ground
11
=
=TRW TC-8S0-32
CR = 0.33 pF typical
TUH/5627-7
FIGURE 7. Obtain input signal Isolation using this circuit's dual SoH scheme. Analog Input slgnala amplitude modulate a
pulse train using a technique similar to that employed In Flgurtl5'a dealgn. Thla modulated data la transformer coupled,
and thereby Isolated, to a DC filter atage, where It la resampled and reconatructed.
A
TRACE VERTICAL HORIZONTAL
A
B
B
C
C
D
E
D
50VlDIV
W/DIV
50VlDIV
10VlDIV
5V/DIV
100 ",SEC/DIV
100 p.SEC/DIV
100 ",SEC/DIV
100 ",SEC/DIV
100 ",SEC/DIV
E
TL/H/5627 -6
FIGURE 8. Figure 7's In-clrcult oscillator (A2) generates both the sampling pulse (A) and the switching transistor'a
drIVe. Modulated by the analog input aignal, Q2'a (and therefore n'a) output (8) la demodulated by SoH amplifier A7.
AS'a output (C) and A6's input (D) and output (E) provide a delayed sample command.
655
secondary of the transformer, which insures high accuracy
amplitude information transfer. The amplitude coded ,information at the transformer's,secondary (Figure 8, Trace B) is
demodulated back to a DC level by sample-hold amplifier,
A7; ,A5 (output, Figure 8, Trace C) and A6(" +'~ ihput, FI{Jure,8, Trace D; output, Figure 8, Trace E) provide a delayed
sample command to A7, ensuring accurate acquisition of
the transformer's output pulse ampHtude. A8 provides gain
trimming and filtering capability.
hold amplifier) and Trace D is A7's output. Trace E shows
Ihe.filter's output at A8.
PreCision, H'lgh efficiency Temperlitunt cOntroller
The sample-\)old amplifier:in Fl{Jure 10 is used to provide
very high stability in ,an oven temperature control circui~. 'In
this circuit, the output signal ,of the pulse driven thermistorbridge is ten times greater than,thE! usual DC driven bridge.
In thermistor-bridges, power dissipation in the resistors and
thermistor is the limiting factor.!n how muc,h DC bridge drive
may be used. However, if the bridge drive is applied in the
form of high voltage pulses at very low duty cycle, average
power dissipation will be low arid a high bridge output !lignal
will result.
Figure 9 provides very' graphic evidence of the circuit al
work. Hera, a DC biased sine wave (Fiqure 9, Trace A) is fed
into the circuit input. Trace B is the clock froin A2's output.
Trace C is the transformer secondarY (irlp~ of A7 sample-
A
"
B
TRACE VERTICAL HORIZONTAL
5V/DIV
100 mSEC/DIV
100VlDIV
5V/DIV
5V/DIV
5V/DIV
A
8
c
C
D
D
E
E
TL/H/5627-9
FIGURE 9. Completely Input·to-outpl,lt isolated, FllI.urtl 7's circuit's analog input signal (A) is sampled by a clock pulse
(8) and converted to a pulse amplitude modulated format ,(C). After tllterlng and resampllng, the reconstructed signal
(D) Is available smoothed (E).
'
15k
.-15V
••
..01pF
2.n
15V
ISV
15k
'5
HEATER
I.
Uk-'"
~~~~~.
I
I
I
I
I
I
I
I
m
01, Q2 z LM395
• = TRW 1% MAf1.8 resislor
Transformer = P8394 (Slanco!)
-#= lN4148
R Thermisler Yeliow Springs
'::"
'::"
'::" I
I
I
"
L. _ _ _ _ _ _ _ _ ':"'~,..'--,_------~---...;-------"------~
=
Insl. CO',144014 " ,
, " , '
'
,
'
; ,,'
TUH/56l!7-10
F,IGURE 10. T!ght temperature ,col1trol !'8l!ults, wilen hlg'" voltage pulses sy~hronously drive a themllstor-brldge-re
trick that Increases slgnalleve!-,and are t~en sampled and used to control apulse width, modillated heater driver"
656
In Figure 10, this operation is implemented by having,the A1
oscillator drive 01 to energize a common 24V transformer
used "backwards". The transformer's floated output is a
100V pulse which is applied directly across the thermistorbridge. With one side of the bridge output grounded, the
bridge drive with respect to ground appears as complementary 50V pulses (Figure 11, Traces A and B). A2 provides
amplification of the bridge's pulsed output (Figure 11, Trace
C). A3, a sample-hold amplifier, samples the middle of A2's
output pulses and has a DC output equal to the amplitude of
these pulses. Proper timing for A3's sample command (Figure 11, Trace D) is provided by the A4-A5 pair and their
associated RC networks. The DC output of A3 is low-pass
filtered and fed to AS, which combines with A7 to form a
simple pulse width modulator. The output of A7 is a ramp
(Figure 11, Trace F-note horizontal scale change) which is
periodically reset by A5's output (Figure 11, Trace E). This
ramp is compared at AS to AS's output, and the resultant
pulse at AS's output (Figure 11, Trace G) is used to drive the
02 heater control switch. In this fashion, the ON time of the
pulse applied to the heater will be proportional to the
sensed offset at the thermistor-bridge. Thermal feedback
from the heater to the thermistor completes a loop around
the circuit. The 5 MO potentiometer is used to adjust the
time constant of this loop, and the 2.5k potentiometer at A2
sets the gain.
In operation, with the thermistor and heater tightly coupled,
the time constant of the loop is adjusted by applying small
step changes in the temperaturesetpoint. This is done by
alternately opening and closing a switch across a 1000 resistor in series with one of the bridge resistors. For the
thermistor shown, this represents a 0.02'C step. The response of the loop to these steps can be monitored at A3's
output. With the loop time constant and gain properly adjusted, AS's output will settle in a minimum amount of time in
response to the steps. Figure 12 shows settling for both
" +" and "-" steps, with settling inside 2 seconds for either polarity step.
A
B
TRACE VERTICAL HORIZONTAL
c
A
B
C
D
E
F
G
D
E
F
100V/DIV
100VlDIV
5V/DIV
10V/DIV
5V/DIV
10V/biV
50V/DIV
200 ",SEC/DIV
200 ",SEC/DIV
200 ",SEC/DIV
200 ",SEC/DIV
1 mSEC/DIV
1 mSEC/DIV
1 mSEC/DIV
G
TL/H/5627 -11
FIGURE 11. Driving a thermistor-bridge with complementary high voltage pulses (A and B) permlta high gain amplification without drift problems (C). Driven by a delayed sample command (D), a SoH amplifier converts the bridge's error
signal to a DC level (E) that controls a pulse width modulated heater driver (F and G).
1 SEC/DIY
FIGURE 12. Tight heater to thermistor coupling and careful calibration can provide rapid temperature restablllzation. Here the controlled oven recovers within 2 seconds
after ± O.OO2'C steps.
S57
TUH/5627 -12
Dynamic Sampling Error: The error introduced into the
Once adjusted, and drivihg a welt insulated and designed
oven, the circuit's control stability can be monitored. The
high' output signal' !evels from the bridge, in combination
with the gain provided by A2, yield extremely good performance.
held output due to a changing analog input at the time the
hold command is given. Error is expressed in mV with a
given hold capacitor value and input slew rate. Note that
this error term occurs even for long sample times.
Gain Error: The ratio of output voltage swing to input volt-
Sample-Hold Amplifier Terms '
Acquisition Time: ThE! time required to acquire a new ana-
age swing in the sample mode expressed as a percent dif-'
ference.
.
log input voltage with an output step of 10V. Note that acquisition time is not just the time required for the output to
setUe, but also includes .the time required for all intemal
nodes to settle so tiiat the output assumes the proper value
when switched to the hold mode.
Hold Settling Time: The time required for the output' to
settle within 1 mV of final value after 'the hold logic command.
Hold Step: The voltage step at the output of the samplehold when switching from sample mode to hold mode with a
steady (DC) analog input voltage. Logic Swing is specified,
usually 5V.
Aperture Time: The delay required between hold command
and an input linalog transition, so that the transition does
not affect· the held output.
POWER PINS
> ....._____....;;..5-0. OUTPUT
INPUT
ANALOG
DIFFERENTIAL
..
LOGiC PINS .
(PIN 11YPICALLY GROUND£D)
TUH/5627 -13
FIGURE 13. Typical Sample-Hold Ie Amplifier
658
Circuit Applications of
Multiplying CMOS 0 to A
Converters
National Semiconductor
Application Note 269
The 4-quadrant multiplying CMOS 0 to A converter (DAC) is
among the most useful components available to the circuit
designer. Because CMOS DACs allow a digital word to operate on an analog input, or vice versa, the output can represent a sophisticated function. Unlike most DAC units,
CMOS types permit true bipolar analog signals to be applied
to the reference input of the DAC (see shaded area for
CMOS DAC details).
This feature is one of the keys to the CMOS DAC's versatility. Although 0 to A converters are usually thought of as
system data converters, they can also be used as circuit
elements to achieve complex functions. Some CMOS
DACs contain internal logic which makes interface with microprocessors and digital systems easy. In circuit oriented
applications, however, the "bare bones" DACs will usually
suffice. As an example, Rgure 1 shows a 0 kHz-30 kHz
variable frequency sine wave generator which has essentially instantaneous response to digital commands to
change frequency. This capability is valuable in automatic
test equipment and instrumentation applications and is not
readily achievable with normal sine wave generation techniques. The linearity of output frequency to digital code input
is within 0.1 % for each of the 1024 discrete output frequencies the 10-bit DAC can generate.
REFERENCE
INPUT
(ANALOGI
r----
-----------------------,I
R
R.
R
R
2R
2R
,
,,
,
I
I
2R
I SWITCHES EXERCISED
I BY EXTERNAL
, DIGITAL COMMAND
R~E.!!!'~'!- _ _ _ _ _
J
Details (Simplified) of CMOS DAC1020-Last 5 Bits Shown
Other CMOS DACs are similar in the nature of operation but also include internal logic for ease of interface 10 microprocessor based systems. Typical is the
DAC1000 shown below.
'II-IIT
INPUT
LATCH
•
•
•
•
DAC
REGISTER
•
•
••
r---l-~--OVREf
'.IIT
1--f--oIOUT I
MULTIPL VlNO
DAC
r-i1--t--oIOUTZ
~_ _ _!:::t--r-ORFEEDIACK
CHIP
SELECT
WRITE'
WRITE:2
659
XFER
BYTE 11
BYTE 2
TLlH/5628-1
TO FEEDBACK RESISTOR
OIOI'C
.........-o'fiV
5k
WAVE SHAPE ADJ
'5V
OFFSET":
II
-'liV
16k
280
-!>I-=1 N4148
,. = 1% film resistor
TL/H/5628-2
FIGURE 1
To understand this circuit, assume A2's output is negative.
This means that its zener bounded output applies -7V to
the DAC's reference input. Under these conditions. the DAC
pulls a current from A1's summing junction which is directly
proportional to the digital code applied to the DAC. A1, an
integrator, responds by ramping in the positive direction.
When A 1 ramps far enough so that the pOtential at A2's
.. +" input just goes positive, A2's output changes state and
the potential at the DAC's reference input becomes + 7V.
The DAC output current reverses and the A1 integrator is
forced to move in the negative direction. When the negative-going output of A1 becomes large enough to pull A2's
.. +" input slightly, negative A2's output changes state and
the process repeats. The resultant amplitude stabilized triangle wave at A1's output will have a frequency which is
dependent on the digital word at the DAC. The 20 pF capacitor provides a slight leading response at high operating frequencies to offset the 80 ns response time of A2, aiding
overall circuit linearity. The triangle wave Is applied to the
Q1-Q2 shaper network, which furnishes a sine wave output. The shaper works by utilizing the well known logarithmic relationship between VeE and collector current in a transistor to smooth the triangle wave.
To adjust this circuit, set all DAC digital inputs high and trim
the 25k pot for 30 kHz output. Next, connect a distortion
analyzer to the circuit output and adjust the 5k and 75k
potentiometers associated with the shaper network for minimum distortion. The output amplifier may .be adjusted with
its potentiometer to provide the desired output amplitude.
This circuit permits rapid switching of output frequency
which is not possible with other methods. Figure 2 shows
the clean, almost instantaneous response when the digital
word is changed. Note that the output frequency shifts immediately by more than an order of magnitude with no untoward dynamics or delays. If operation over temperature is
required, the absolute change in resistance in the DAC's
internal ladder network may cause unacceptable errors.
This can be corrected by reversing A2's inputs and inserting
an amplifier (dashed lines in schematic) between the DAC
and A1. Because this amplifier uses the DAC's internal
feedback resistor, the temperature error in the ladder is cancelled and more stable operation results.
ZIOI/O'V
liVlDlV
liV/DIV
TL/H/5628-3
FIGURE 2
660
>-4~rol TIL OUT
20k
FULL·SCALE
CALIBRATE
TL/H/5628-4
FIGURE 3
ative until it bounds against the diode in its feedback loop.
During the time the clock pulse is high, the current through
the 2.7k diode path forces A2's output low. When the clock
pulse goes low, A2's output goes high and remains high
until the A 1 integrator output amplitude exceeds the trip
point. To calibrate this circuit set all DAC bits high and adjust the "full-scale calibrate" potentiometer for the desired
full-seele pulse width. Next, set only the DAC LSB high and
adjust the A 1 offset potentiometer for the appropriate length
pulse, e.g., 1/1024 of the full-scale value for a 10-bit DAC. If
the 2.2mV
drift of the clamp diode in A 1's feedback loop
is objectionable it can be replaced with an FET switch.
Digitally Programmable Pulse Width Modulator
The circuit of Figure 3 allows the DAC inputs to control a
pulse width. This capability has been used in automatic testing of secondary breakdown limits in switching transistors.
The high resolution of control the DAC exercises over the
pulse width is useful anywhere wide range, precision pulse
width modulation is necessary. In this circuit, the length of
time the A 1 integrator requires to charge to a reference level is determined by the current coming out of the DAC. The
DAC output current is directly proportional to the digital input code. Both the DAC analog Input and the reference trjp
point are derived from the LM329 voltage reference. During
the time the integrator output (Figure 4, Trace A) is below
the trip point, the A2 comparator output remains high (Figure 4, Trace B). When the trip point Is exceeded, A2's output goes low. In this fashion, the DAC input code can vary
the output pulse width over a range determined by the DAC
resolution. Traces C, D and E show the fine detail- of the
resetting sequence (note expanded horizontal scale for
these traces). Trace C is the 5 IJ-s clock pulse. When this
pulse rises, the A 1 integrator output (Trace D) is forced neg-
rc
Digitally Controlled Scale Factor Logarithmic Amplifier
Wide dynamic measurement range is required in many applications, such as photometry. LogarithmiC amplifiers are
commonly employed in these applications to achieve wide
measurement range. In such applications it is often required
to be able to set the seele factor of the logarithmiC amplifier.
A DAC controlled circuit permits this to be done under digital
control. Figure 5 shows a typical logarithmic amplifier circuIt.
Ql is the actual logarithmiC converter transistor, while Q2
and the 1 kO resistor provide temperature compensation.
The logarithmic amplifier output is taken at A3. The digital
code applied to the DAC will determine the overall scale
factor of the input voltage (or current) to output voltage ratio.
TRACES A AND 8 -IDD .oIOlV
TRACES C, D AND E - I ""DIV
lOVlDlV
Digitally Programmable Gain Amplifier
ZOVIDIV
Figure 6 shows how a CMOS DAC can be used to form a
digitally programmable amplifier which will handle bipolar input signals. In this circuit, the input is applied to the amplifier
via the DAC's feedback resistor. The digital code selected
at the DAC determines the ratio between the fixed DAC
feedback resistor and the impedance the DAC ladder presents to the op amp feedback path. If no digital code (aU
zeros) is applied to the DAC, there will be no feedback and
the amplifier output will saturate. If this condition is objectionable, a large value (e.g. 22 MOl resistor can be shunted
across the DAC feedback path with minimal effect at lower
gains. It is worth noting that the gain accuracy of this circuit
is directly dependent on the open loop gain of the amplifier
employed.
5VIDIV
lOVlD1V
Iv/DIV
TL/H/5628-5
FIGURE 4
661
LHIOJI
lay
FIGURE 5
.>-....fOl0UTPUT
TL/H/5628-7
FIGURE 6
Digitally COntrolled Filter
In FIgure 7 the DAC is used to control the cutoff frl1Quency
of a filJer. The equation given in the figure governs the'cu~ff
frequency'of the circuit. ,In this circuit, the DAC allows high
resolution digital c,ontrol of frequency response by effeCtively varying the time constant of the A3 integrator. Figure 8
dramatically demonstrates this. Here, the circuit is driven
from the test circuit shown in Fit1ure 7.
As each input square wave is presented to the filter the oneof-ten decoder sequentially shifts a "one", to the next DAC
digital input line. Trace A is the input waveform, while Trace
B is the Vl/aveform at A1'" output (the reference input of the
DAC). The circuit output at A3 appears as Trace C. It is
clearly evident that as the decoder shifts the "one" towards
the lower order CAe inputs the circuit's cutoff frequency
decays rapidiiy.'
'.
.
662 '
Test Circuit
ru-L.fl.n ....
'NPUT.
OUTPUT
R3
10k
'NPUT (OI--'l.M_U~
~"'.....ra\ OUTPUT
TLlH/562B-B
FIGURE 7
TL/H/562B-9
FIGURE 8
663
Applying the New CMOS
MICRO-DACTM
National Semiconductor
Application Note 271
Tim Regan
Most microprocessor based systems designers will find that
the new CMOS MICRO-DAC are among the most interesting and versatile devices they will include in their system.
The availability of these devices opens a vast new area 'of
applications where the microprocessor can provide an, intelligent contrOlling function in the analog world. Traditional
analog control devices, primarily potentiometers and
switches which require, a time-consuming and often erroneous human interface, can often be replaced by a processor
and DACs to perform precise and automatic controls. A little
creative thinking can easily generate several functions that
could be better performed automatically. The purpose of
this note is to stimulate this thought and to illustrate' the
versatility of CMOS DACs to achieve results.
The use of CMOS processing in the fabrication of the MICRO-DAC offers several important features. The primary
advantage is that the current switching R-2R ladder network, used for the actual D to A conversion, can conduct
current in both directions (sourcing or sinking current at its
analog output) to control either a positive or negative fixed
voltage reference or an AC signal. In addition, all of the
necessary digital input conditioning circuitry to permit a, direct microprocessor interface with, no additional logic devices needed is included with minimal device power require- '
menls. All of the MICRO-DAC can be, contr~lIedJr0m an 8bit data bus regardless of the number of digital inputs for a
particular device. The operation of the R-2R ladder and the
digital interface signal requirements are explained in detail
on the actual device data sheets,
..
In the application circuits that follow, the connections for the
control pins for the actual digital interface are omitted for
simplicity. Several methods of configuring the DAC to accept its inputs from a processor exist and are described on
the data sheets. The actual method used depends on the
overall system provisions and requirements. The digital input code is referred to as D and represents the decimal
equivalent of the binary input. For example, D would range
from 0 to 4095 in steps of 1 to describe the full range of
digital inputs for a 12-bit MICRO-DAC. Any of the MICRODAC can be used in any of the circuits shown, depending on
apcuracy and/or, resolution requirements.
THE DIGITAL POTENTIOMETER
The most common and basic application of a DAC is generating discrete voltage output levels within a given span, and
serving in essence as an attenuator (Figure 2). The applied
digital input word multiplies the applied reference voltage,
and the output voltage is this product normalized to the
DAC's resolution. The op amp shown is used to convert the
output current from the CAC to a voltage via a feedback
resistor included in the DAC (RIB)' This output current
ranges from a near zero output leakage (on the order of 10
. nA)10r an'~pplied code of all zeros (D = 0), to a full-scale
value (D = 2n ~ 1, where n is the CAC's bits of resolution) of
VREF divided by the R value of the internal R-2R ladder
network (nominally 15 kG). The current at lOUT 2 is equal to
that c,aused by the one's complement of the applied digital
input, so while lOUT 1 is at full-scale, lOUT 2 will be zero.
Note that the output voltage is the opPOSite polarity of the
Resolution and linearity are the ~rist importa~t characteriSapplied reference voltage, but since CMOS DACs can actics of the analog output of any D to A. Uneatity is important
cept bipolar reference voltages, if a positive output is needto insure that each and every analog output' quantity is preed, a negative reference can be applied. To preserve the
dictable within a given tolerance (specjfied as a percent of .. linearity' of the output, the two current output pins of the
the full-scale range) for any applied digital word., Resolution, ' CAC must be as close to OV as possible, which requires the
defines the number of possible analog output' quantities , input offset voltage of the op amp to be nulled. The amount
available within a given range. Higher resolution in a DAC
of linearity error degradation is approximately Ves + VREF.
serves to minimize the gaps in the analog output inherent in
For AC signal attenuation, in audio applications for example,
digitally-based controls. The new line of MICRO-DAC offers
the CAC's linearity over the full range of the applied refera wide variety of converters to fit the accuracy and resoluence voltage, even as it passes through zero, is sufficiently
tion requirements of a great number of applications. The
good enough to distort a 10V peak sine wave by only
device part numbers are summarized in Figure 1.
0.004%.
Resolution
Linearity Error
(% of Full-scale)
8 Bits
10 Bits
12 Bits
256 Output 1024 Output 4096 Output
Steps
Steps
Steps
±0.012%
DAC1208,
DAC1230
±0.024%
DAC1209,
CAC1231
±0.05%
DAC0830
DAC1000,
CAC1006
±0.1%
DAC0831
CAC1001,
DAC1007
±0.2%
DAC0832
DAC1002,
DAC1008
FIGURE 1. The MICRO-DAC Family
664
CAC1210,
CAC1232
The feedback capacitor shown in Figure 2 is added to improve the settling time of the output as the input code is
changed. With no compensation, a fair amount of overshoot
and ringing appears at the output due to a feedback pole
formed by the feedback resistor, and the output capacitance of the DAC, which appears fram the (-) input of the
op amp ground.
It is most desirable to select an op amp for use with the
MICRO-DAC which combines good DC characteristics, primarily low Vas and low Vas drift, with fast AC characteristics such. as slew rate, settling time and bandwidth. Such a
combination is difficult to find in a single op amp for use with
the higher accuracy 12-bit DACs. Figure 3 shows an op amp
configuration which combines the excellent DC input characteristics of the LM 11 with the fast response of an LF351
BI-FETTM op amp.
The low cost, high resolution, and stability with time and
temperature of the MICRO-DAC allow precise output levels
that rival the capability of the best multiple turn potentiometers, and can automatically be adjusted, as required, by a
controlling microprocessor.
LEVEL SHIFTING THE OUTPUT RANGE
As shown in Figure 4, the zero code output of the DAC can
be shifted, .if deslred, to any level by summing a fixed current to the DAC's current output terminal, offsetting the output voltage of the op amp. The applied reference voltage
now serves as the output span controller and is fractionally
added to the output as a function of the applied code.
VOUT
vOUT=~
-VREFD
forO';; 0,;; 255
FIGURE 2. The Digital Pot
ISk
-IVV
REFERENCE
....--.4H.-o-ISV
~---""'-oVOUT
Settling time '" BpS
for a zero to full·
47k
scale transition
FIGURE 3. Composite Amplifier for Good DC Characteristics and Fast Output Response
RI
7&11
-IVV
REFERENCE
ISV
TL/H/5629-1
FIGURE 4. Level Shifted Output
665
VOUT
=
.E...]
-VREF [AlB +
AI
256
;
-r-------------------------------------~
SINGLE SUPPLY OPERATION
The R-2R ladder can be operated as a voltage switching
network to circumvent the output voltage inversion inherent
in the current switching mode. This allows single supply operation. In Figure 5, the reference voltage is applie~ to the
lOUT 1 terminal, and is attElnuated by the R-2R ladder in
proportion to the applied code, and output to the VREF terminal with no phase inversion. To insure linear operation in
this mode, the applied reference voltage must be kept less
than 3V for the 1O-bit DACs or less than 5V for the a-bit
DACs. The applied supply voltage to the DAC must be at
least 1OV more positive tHan the reference voltage to insure
that the CMOS ladder switches have enough voltage overdrive to fUlly turn on. An extemal op amp can be added to
provide gain to the DAC output voltage for a wide overall
output span.
linearity can be obtained in this circuit with the 8 and 1O-bit
MICRO-DAC, but is difficult because of the very low value
reference required with the 12-bit parts. The resistance to
ground of the VREF terminal is nominally 15 kG, indepen.
dent of the digital input code.
.
BIPOLAR OUTPUT FROM A FIXED REFERENCE
VOLTAGE
The use of a second op amp in the analog output circuitry
can provide a bipolar output swing from a fixed reference
lioltage. This, in effect, gives sign significance to the MSB of
the digital input word to allow 2-quadrant multiplication of
the reference yoltage. The polarity of the reference can still
be reversed or be an AC signal to realize full' 4-quadrant
multiplication. This circuit is shown in Figure 6.
Only the input offset voltage of amplifier OA 1 needs to be
nulled to preserve the linearity of the DAC. The offset of OA
2 will affect only absolute accuracy of the output voltage.
The zero code output voltage is limited by the low level
output saturation voltage of the op amp. The 2 kO load
resistor helps to minimize this voltage. Specified DAC
15V
....---IVcc
151<
OAC1000
Vour
Zk
vour =
+VREF
[~l
1024
FIGURE 5. Single Supply Operation
ZA'
10k
A'
5k
A,B
±VREF
OACDl30
TUH/5629-2
vour = VREF (0 -
128)
128
'These resistors are available from
Beckman Ins1ruments, Inc. as their
part no. 694-3-Al0K-O
1 LSB = IVREFI
128
Input Code
IdealVOUT
MSB ••• LSB
+VREF
-VREF
1 1 1 1 1 1 1 1
1 1 0 0 p 0 0 0
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
VREF -: 1 LSB
VREF/2
-IVREFI + 1 LSB
-IVREFI/2
0
0
-1 LSB
+1 LSB
0 0 1 1 1 1 1 1 JVREFI_ 1 LSB
2
0 0 0 0 0 0 0 0
-IVREFI
FIGURE 6. Bipolar Output from a Fixed Reference Voltage
666
IVREFI + 1 LSB
2
+IVREFI
DAC CONTROLLED AMPLIFIER
CAPACITANCE MULTIPLIER
In the circuit of Figure 7, the OAe is used as the feedback
element for an inverting amplifier configuration. The R-2R
ladder digitally adjusts the amount of output signal fed back
to the amplifier'summing junction. The feedback resistance
can be thought of as varying from eo 15 kO to 00 as the
input. code changes from full-scale to zero. The internal RIB
is used as the amplifier's input resistor. It is important to
note that when the input code is all zeros the feedback loop
is opened and the op amp output will saturate.
The OAe controlled amplifier can be used in a capacitance
multiplier circuit to give a processor control of a system's
time or frequency domain response. The circuit in Figure 8
uses the OAe to adjust the gain of a stage with a fixed
capacitive feedback, creating a Miller equivalent input capacitance of the fixed capacitance times 1 + the amplifier's
gain. The voltage across the equivalent input capacitance to
ground is limited to the maximum output voltage of op amp
A 1, divided by 1 + 2"/0, where n is the OAe's bits of
resolution.
15V
RIB
OAC10ao
15V
>------...
-oVOUT
VOUT = -VIlIi(1024)
o
FIGURE 7. DAC Controlled Ampllfer
RIB
15V
OACOl30
TLlH/5629-3
CECUIV = Cl (1 +
FIGURE 8. CapaCitance Multiplier
667
2~)
.. r------------------------------------------------------------------------------------------,
.....
The output current of these circuits is limited to that of the
HIGH VOLTAGE OUTPUT
C'I
~
LM143, typically 20 mAo If higher voltage and/or higher outMany DAC'applications iiwolve the generation of high voltput current is needed, a discrete power stage can be used,
age levels to be used for deflection plate driving, high voltas shpwn in Figure 10.
age motor speed, or position control. All of. the MICRO-DAC
can, control 'as, much as ± 25V applied to the reference terTo inSl:Jre accuracy with these high voltage circuits, concern
for the power dissipation and temperature coefficients of
minal, but guaranteed performance is specified at no more
than ± tOV. Since the output amplifier serves as a currentthe resistors used to increase the output voltage is necesto-voltage converter, increasing the effective feedback resary. The .I-network configuration shown in Figure 10 reducsistance directly increases the amplifier's output voltage for
es the dependence Of the output voltage to temperature
a given DAC output current. Use of a high voltage op amp,
changes by reducing the significance of the tracking requirethe LM143 with 80V supply capability for example, can acments of the external resistors to the internal RIB resistor.
Using two resistors with similar temperature coefficients for
commodate this increased gain and allow the use of referR1 and R2, and making their ratio dominant in setting the
ence voltage within the DAC's specified limits. Figure g illustrates how higher voltage outputs can be obtained for both
overall gain provide the most stable results.
unipolar and bipolar requirements.
a) Unipolar Output
BOV
HIB
ltV
VCC
DAC1001
-lOY
VHEF
-VRO
VOUT = 1024 (RfB
VHEF
+ Rll
0,;; VOUT';; 50V
":'
b) Bipolar Outpu~
8A
IDk
IIV
llV
H
1011
DACI.
10V
REFERENCE
~±3fIV
"""""'--""'~OUTPUT
VREF
SWING
":'
-4f1V
v
_ (0 -
OUT -
512)3VR
512
FIGURE 9. Unipolar and Bipolar Voltage Bo08tlng
.---1--.....Jt.IIIY....
1k
---oIZDV
llV
RIB
llV
-lOY
REFERENCE
Rl
Uk
-VREFO [
R2
R2]
VOUT=-- 1 +--+4096
RIB Rl
TL/H/5629-4
FIGURE 10. High Voltage Power DAC
668
):.
HIGH CURRENT CONTROLLER
The entire circuit "floats" by operating at whatever ground
reference potential is required by the total loop resistance
and loop current. To insure proper operation, the voltage
differential between the input and output terminals must be
kept in the range of 16V to 55V, and the digital inputs to the
DAC must be electrically isolated from the ground potential
of the controlling processor. This isolation can best be
achieved with opto-isolators switching the digital inputs to
the ground potential of the DAC for a logic low level.
The MICRO-DAC can also be used to linearly control current flow useful in applications such as automatic test systems, stepper-motor torque compensation, and heater controls. Figure 11 illustrates the use of a DAC1230 controlling
a OA to 1A current sink. The largest source of nonlinearity in
this circuit is the stability of the current sensing resistance
with changes in its power dissipation. To minimize this effect, the sensing resistance should be kept as low as possible. To maintain the output current range, the reference
voltage to the DAC must be reduced. The flexible reference
requirements of the MICRO-DAC permit the application of a
lower reference with no degradation in linearity. A triple Darlington is used to minimize the base current term flowing
through the sense resistor, but not into the collector terminal.
In a non-microprocessor based system where the loop controlling information comes from thumbwheel switches, the
digital input data for the DAC can be derived from BCD to
binary CMOS logic circuitry, which is ground referenced to
the ground potential of the DAC. The total supply current
requirements of all circuits used must, of course, be less
than 4 mA, and the value of R1 could be adjusted accordingly.
4 rna to 20 rnA CURRENT LOOP CONTROLLER
TARE COMPENSATIONI AUTO-ZEROING
The standard 4 mA - 20 rnA industrial process current loop
controller is an application where automatic, microprocessor directed operation is often required, and is a natural
application for D to A converters. The low power requirements of the CMOS MICRO-DAC allow the design cif a controller that is powered directly from the loop it is controlling.
Figure 12 illustrates a 2-terminal floating 4 mA to 20 mA
controller.
Probably the most popular application of D to A converters
is in auto-zeroing or auto-referencing. In these systems the
DAC is called upon to hold an output voltage used to offset
the analog input range of an A to D converter. This is done
to reserve the full input range of the A to D for analog voltages starting from reference potential to a full-scale value
relative to that reference voltage. A common example of
this is Tare Compensation in a weighing system where the
weight of the scale platform, and possibly a container, is
subtracted automatically from the total weight being measured. This, in effect, expands the range of weight that
could be measured by preventing a premature full-scale
reading, and allows an automatic indication of the actual
unknown quantity.
In this circuit, the output transistor will conduct whatever
current is necessary to keep the voltage across R3 equal to
the voltage across R2. This voltage, and therefore the total
loop current, is directly proportional to the output current
from the DAC. the net resistance of R1 is used to set the
zero code loop current to 4 mA, and R2 is adjusted to provide the 16 mA output span with a full-scale DAC code.
5V.... 50V
LOAD
t5V
-tV
REFERENCE
RIB
I
I
I
IL __ _
I = lA(D)
o
4096
TLlH/5629-5
FIGURE 11. High Current Controller
669
Z
.....,.•
N
F/{Jure 13 illustrates this basic technique. In this system1he
DAC Would initially be given a zero code and the system's
input would be set'to some reference quantity. Aconversion
of this input would be performed, then the corresponding
code would be applied to the DAC. The output of the DAC
will be equal to and of the opposite polarity as the input
voltage to force the amplifier's output, and therefore the
AID's input, to zero. The DAC's ootput is held constant $0
that any $Ubsequent Al9 conversions 'i\'ill yi~ld a v/lIUll relative in magnill!de to the, ir:'itial refer~nce quantity. To insure
that th~ outpl,lt code from the A to D generatl!,s the proper
DAC output, voltage, the two devices should be driven from
the same referen~ voltage. '
INPUT
IN4801
Ilk
1l1li
DACII830
LM3290
GNO ONO
3
LM3290
10
R3
10
~'-i\M'-JVVY.I--"'! 4.AS lOUT $ZO ",A
10k
lOUT - VREF [~+ 2:RiB] [1
+~]
FIGURE 12. Two-Terminal 4 mA - 20 mA Current Loop Controller
r----------------------------~----------------~-oVREF
INPUT
1
PROCESSOR
DATA BUS
15V
VREF
OACOB30
IIV
>;.:.;.......~TOAID
&.;;;;'----.... FROM 0/10
ACCOMMODATING DIFFERENTIAL SIGNALS
TLlH/5629-6
FIGURE 13. Basic Tare Compensation
670
For differential input signals, an instrumentation amplifier
such as the LM363 can be used. The output reference pin
of this amplifier can be driven directly by the DAC's v/ded by the thermal time constant of V2 and the 10 MO-1
Jl.F delay in the LF311 inp!!t line. Figure 13 shows the response of this amplifier booster at a gain. of about 25 .. With a
15V input pulse (Trace A), the output (Trace B) goes to
350V in 1 Jl.s, and settles within 5 Jl.s. The falling edge slews
equally fast and settling occurs within 4 .",s.
Figure 14 is a table which summarizes the information in this
article and will help you to pick the right booster for your
particular appliCation.
immune \to load shorts and reverse voltages. A solid state
output requires substantial protection against these conditions. Although the circuit shown has a -350V limit, tubes
(~member them?) with higher plate voltage ratings can extend the output capacity to several kilovolts. In tl)is circu~,
our thermionic friends are arranged in a common cathode
(V2B) loeded-cathode-follower .(V2A) output, driv~n from a
common cathode gain stage (V1). The booster output is fed
back to the LF357 via the 1 MO resistor. Local feedback is
used to stabilize the LF357, while the'pF-1 MO pair rolls off
the loop at 1 MHz. Because the V1 stage inverts, the feedback summing junction is placed at the LF357 positive input.
The parall~t diodes at the summing junction prevent high
voltage from destroying the amplifier during circuit start-up
and slew rate limiting. Tubes are inherently much more toleraAt of loa.d'·shorts IiJ1d reverse voltages. tliantransistors,
and are much easier to protect. In this circuit, an LM335
temperature . sensor is in. contact with V2. This
. A· aoYJDIV.
a-IIIIVIDIV
HORIZOIITAL· z·;..m,y
TL/H/S630-11
FIGURE 13
Figure
Voltage Gain
Current Gain
Bandwidth
1
No
Yes-200mA
Depends on
op amp. Typical 1 MHz
3
No
Yes-200mA
Full output to
5MHz-3dB.
Point at
11 MHz.
Ultra fast. 750VI fIos. Full bipolar output. Inverting
operation only.
5
Yes-24V swing
No
Depends on
opamp.
Requires that load float from ground.
6
Yes-±100V
Yes-50mA
50 kHz typical.
8
Yes-±30V
Yes-3A
50kHz
Full" + " and" -" output swing. Allows inverting
. or non-inverting operation.
9
Yes-70V Swing
Yes-3A
100 kHz
Output extremely rugged. Well suited for driving
difficult loads in lab. Set-ups. Full bipolar output.
AConly.
10
Yes-1000V
Yes-300mA
50Hz
High voltage at high current. Switched mode
operation allows operation from ± 15V supplies
with good efficiency. Limited bandwidth with
asymmetrical slewing. Positive outputs only.
12
Yes-350V
No
500kHz
Output very rugged. Good speed. Positive outputs only.
FIGURE 14
680
Comments
Full" + " and" -" output swing. Stable into
, 500-10,000 pF load. Inverting or non-inverting
operation. Simple.
FiJll .. + " and" -" output swing. Allows inverting
or non-inverting operation. Simplified version
( ideal for CRT deflection plate driving. More complex version drives full200V swing into 2 kO and
1000 pF.
CMOS AID Converter
Interfaces Easily with
Many Microprocessors
National Semiconductor
Application Note 274
With a span accommodation down to 180 mil, this 8-bit unit
can also replace a 12-bit analog-ta-digitsl device in some
applications.
ing I/O selection to increase the width of the read and write
strobe Signals. This eases interface requirements considerably, since slower I/O devices can operate with much faster
microprocessor units. The automatic wait state for I/O devices will loom larger in importance as the next generation
of higher speed microprocessors evolves.
To help meet the rising demand for easier interfacing between analog-to-digital converters and microprocessors, the
complementary MOS, 8-bit ADC0801-05 has been designed
to accommodate almost all of today's popular microprocessors. It requires only a single 5V supply and is low power to
boot.
Housed in a 20-pin dual-in-line package, the successive approximation device includes a Schmitt trigger circuit that allows it to be driven from a system clock, as well as an external RC network. At a clock frequency of 640 kHz, conversion time is 100 /ls. What's more, its guaranteed linearity
error of ± 1,4 least significant bit (typically ± 1,1,6 LSB) can
encode an analog signal span as small as 180 mV-a performance that allows it to replace 9, 10, and even 12-bit
converters in many applications.
Constantly decreasing converter prices raise the comparative cost· of the interface electronics and increase the demand for simplicity of interfacing. The growing emphasis on
simpler systems for higher levels of reliability has also
pushed this demand, as has a trend toward lower levels of
power dissipation. And with the success of the 5V power
supply standard of logic circuits, linear circuits have been
pressed for 5V operation. Supporting the ADC0801-05 AID
converter are such special operational amplifiers as the
LM358 dual and the LM324 and LM3900 quad op amps that
run off 5V supplies; also useful are voltage comparators
such as the LM393 dual and LM339 quad devices. Perhaps
the most versatile of such 5V linear devices is the LM392,
comprising an op amp and a comparator.
MORE COMPLICATIONS
Complicating the interfacing are the ever higher levels of
resolution in monolithic converters, with 8 and 10-bit types
readily available and 12-bit devices ready to emerge soon.
Yet, despite their greater resolution, 10 and 12-bit monolithic AID converters are not only more expensive than 8-bit
designs, but also require more careful attention to system
noise problems and management of grounding.
For simple interfacing, an AID converter must operate directly with the signals available on a microprocessor control
bus. The converter is generally given an address that can
be mapped into memory or input/output space, depending
on the type of microprocessor employed. On 6800 microprocessors and their derivatives, no special input/ output addressing or strobes are available, so the converter must appear as a memory location to these processors. Z80 11D microprocessors, on the other hand, not only provide special
I/O interfacing, but also automatically insert a wait state dur-
COMPATIBILITY CRITERIA DIFFER
Microprocessor compatibility has a wide range of meanings-at least according to the various converter data
sheets. True compatibility, however, involves meeting electrical specifications like proper logic voltage levels with adequate loading capability. For example, true TTL compatibility
means the ability to maintain a 0.4V low potential (or less) at
the AID converter logic outputs while sinking 1.6 mA of current. And the high state must be maintained at a minimum of
2.4V while supplying at least 360 1JoA.
Furthermore, all interface protocols must be met. This not
only means operating with the proper signals, but also
meeting all necessary timing requirements, so the converter
must have valid data on the microprocessor bus within the
access time of the memory system with which it happens to
be working.
The protocols for interfacing are not at all standardized.
Some A/D converters make use of the standard chip select
signal (CS) to start a conversion. But decoding· voltage
glitches can cause an A/D converter to begin conversion
when it is not desirable. Both the standard CS signal and a
write strobe signal (WR) must therefore be used, so that the
former signal qualifies the latter and prevents unwanted
conversions due to address decoding glitches. Care must
also be taken when using some A/D converters that are
designed to act as bus controllers; problems can arise when
the central processor is not in control of the bus.
DIFFERENT STANDARDS
The 8080 and 6800 microprocessors (and their derivatives)
use different control bus standards. Microprocessors based
on the 8080, for example, make use of read and write strobe
signals to specify the operation (read or write) requested.
Working with these microprocessors, AID converters start
the conversion cycle upon the microprocessor's issuance of
a chip select signal (decoded from the address bus) and a
write strobe signal. At the end of conversion (EOC), the converter issues an EOC Signal. When dealing with older AID
converters where the EOC signal is typically low during the
conversion process and high at the end of it, microprocessors have difficulty because the EOC signal is not available
on the data bus. Furthermore, the EOC signal does not reset when the converter is serviced by the central processing
unit (that is, when data has been read).
681
...~
Z
C
converter's negative input lead to a 0..5 VDC offs~tvoltage
and supplying ia refer-ence voltage' that is equal to half the
3V span. This application provides the DO. output code for
VIN = 0.:5 VDC and the FF output code for VIN = 3.5 VDC.
In many applications (such as wfilighing cans on ,8 production line), 14, or even 16-bit converters are often called
upon for the needed high levels of resolution. For those
reduced-span applications, an 8-bit A/D converter can be
used instea~t oonsiderblesavings.
COl'T!plicatlOns can also occur wh!ln,'microprocellSOrs interface WIth older AID devices during read operations. For
,.: proper lJ1,te(facing, such converters must have valid data on
't~~ bus,~thin the memory access time.
h;terfaCing'requirements differ for 68CC-type microprocessors, like the 650.2 and 680.0.0., which use read/write (R/Wj
control lines instead of read and write strobe signals and
obtain timing, informa~ion from the system clo~k signal. In
addition, they include a valid memory address signal to qualify the address that is placed on the bus. Such features
make interfacing for 'these micrClprocessors' different from
.
'
that for earfier 80.80. types.'
A SAMPLED-DATA INPUT
The ADC08D1-D5 makes use of a sampled-data comparator. Sampled-data circuits cancel the offset voltage, provide
essentially temperature-independent performance, and cancel low frequency MOS 1/f noise. They do, however, provide some differences in application, since there is an input
stray capacitance to ground, as shown in Figure 1.
For an AID converter to be most u$eful. in a microprocessor-based system, it must have such desirable analog features as differential inputs, and it shOUld adjust to :abcommodate various analog input signal ranges.. The ADC08C1-C5
offers differential analog' inputs, but .it, is ,the' converter's
span aC(Xlmmodation that allows many unusual and useful
analog applications.
When switch S1 is clqsed, stray input capacitance, CIN, is
charged to the input analog potential, VANALOG. Note that
with a stray capaCitance of approximately 12 pF and a 5 kG
MOS switch resistance, the time constant, T, is only 60. ns.
Thus, elN becomes charged to the necessary accuracy level (within ± 1f4 LSB) in 6.9T, or about 0..4
Since the input
switches are operating at one eighth the input clock frequency of 640. kHz, there is ample time for CIN to settle, as
comparisons are made only at the end of the clock period.
Note that the switch at the (-) analog input discharges the
stray capacitance; this evellt causes. input displacement
currents ,to flow. '
The availabilitY of differential analog voltage inputs eliminates the problem of poor analog grounds, since both inputs
can be connected directly across the analog signal source.
The negative (normally grounded) analog input lead can be
referenced to any desirea DC offset voltage to accommodate an input signal range that does· not swing down to
ground. A DC' offset can thus be used at this input'\o cause
a digital output of all Cs at any desired input voltage.
FLEXIBLE $PAN
Finally, the ability to accommodate an arbitrary span or input
dynamic voltage range is desirable in an AID converter.
This can easily be achieved in the ADCC8C1-C5 by selecting
the m8gnitude of the converter's reference input.
""S.
,'
An example might be to permit an analog input voltage
range of C.5V to 3.5V. This is accomplished by tying the
RS
A
•
INPUT
1 r---------:k---l
ICH~GE
~~~~~~~---~--~I,'
'YIN(+lj'
SWI
SIGNAL
L _____________ .J
!~
VANALOG
Input bypass capacitors, when placed directly at the analog
,inputs, cause full-scale errors, since they average the current which will flow through the source resistance of the
analog input signal generator. Input capaCitors are not required; but if they are used, a full-scale adjustment will eliminate any system errors.
I
SOURCE
, YIN
I
HI
I
I
r---~-D;.RES'jsTANC~oFl
i '
.A. SAMPLING SWITCH I
IL____________
5k
SW2
I
~J
...--....T-.,.---CIN
-'-UpF
-r- STRAY
I
*
CAPACITANCE
.
,
FIGURE 1_ Equivalent. Because It has a sampled~data comparator Input, the a-bit A,DC0801-05
monolithic analog-to-dlgltal converter looks capacitive to an Input signal source.
The sampling swHches operate at one eighth the rate of the clockf~quency.
\
682
TLlH/8721-1
The ADC0801·05 monolithic 8·bit CMOS AID converter can
be operated with a wide range of VREF/2 voltages that facil·
itates its use in many different circuit applications. Inexpen·'
sive ratiometric transducers, such as potentiometers, can
be tied, across the converter~s' 5V supply voltage with the
wiper f!KI directly to the converter's Y,N + input pin. The
VREF/2 pin, which will now bias at 2.5V, can be tijl,d to a
second potentiometer that is also hooked across the supply
voltage to provide a full·scale adjustment.
over temperature changes. Grounding problems become
more critical and careful grounding Is a must.
The ADC0801·05 can also be used as a logarithmic con·
veiter to extend the Input voltage dynamic range to cover
three decades. Three input logging circuits (Figure 2) are
provided by the NPN trans,istors in the feedback loops of
operational amplifiers. With these at the seme temperature
(all three on a common Chip), there are no thermal problems
with this circuit. To keep costs at their lowest, the three
transistors in the LM389 audio amplifier IC can be used.
When the VREF/2 is grounded, the converter then functions
as a comparator,ylelding a digital output of all 1s when
V,N+ is,greaterthan V'N-, and of all Os when V,N+ is less
than V'N-' The VREF/2 feature is also useful for low level
analog voltage systems where an operational amplifier is
normally used to boost the input signal prior to digitization.
In a circuit with a(1 analog input voltage of 250 mV maxi·
mum, for example, the signal can be fed directly to the AID
device, saving the cost of the amplifier. The VREF/2 pin
would thus be biased at 125 mY.
The fourth operational amplifier in Figure 2 is used to supply
the proper VREF/2 voltage to the AID converter. Its DC
output voltage is half that of the logarithmically compressed
analog input voltage span.
OFFSET ADJUSTING
Yet another application for the ADC0801·05 is in automati·
cally adjusting the offset voltage of an op amp under micro·
processor control. This is useful in transducer bridge net·
works where a pair of amplifiers is normally used to amplify
the differential signal. Such an output signal can be fed di·
rectly to the AID converter's inputs without requiring a more
costly instrumentation amplifier. The bridge network's arms
will thus be biased at approximately VCc/2.
.
CAREFUL GROUNDING
A minor drawback is that this extra analog resolution leaves
the circuit more susceptible to noise, and the VREF/2 volt·
age requires a low initial tolerance and must be stable
5V
R'
-VANALOG _ _IVI""'_-4H
(-0.01 VOC TO -10 Voci
V,N (+)
':'
5V
Note: 01-03 are
matched transistors
j~ the same package
R
-VIN MINIMUM~ _ _JV,II'v_-4H
(0.01 VOC)
ANALOG·
TO:OIGITAL
COIIVERTER
VREF/2
VINH
':'
5V
R
2R
-VIN MAXIMUMi _ _"",RII'v_-4H
HOVOC)
2R
TL/H/8721-2
FIGURE 2. Logarithmic. The ADC0801-GS monolithic AID converter's VREF/2 pin allowa
Ita use as a three-c:lecadelogarlthmlc circuit. The three NPN transiators In the feedback loopa of the operational
amplifiers give better accuracy with changing temperature than the diodes normally used.
683
F/{/ure 3 shows such a circuit, where the microprocessor
amp 1 is referenced to one side of the bridge network in
takes the digital output of the AID device and automatically
order to cancel any common-mode offset voltage effects.
adjusts the ,output, voltage of operational amplifier 2. This
The AID converter acts as a high gain comparator because
amplifier is used to isolate the, bridge !1etwprk from the offa OV VREF/2 is provided by the voltage follower (amplifier 4)
set adjustment circuit. The INS8255 prog~ammable periph,
and switch 1 circuits. This allows the mICroprocessor to pereral interface ,controls the offset voltage adjustment and anform a successive approximation routine to null the offset
alog sWItches 1 and 2. The CMOS buffer provides id~1 anavoltage of the system. Resolution is thus considerably betlog level swings of either OV or 5V to the bina~ resistor , ter than the normal + 1LSB obtainable with a conventional
network. The bin~ resistor network extracts and injects a
AID converter.
current from, and into op amp 3, causing a small voltage
The ADC0801-05 combines linear and digital features'in an
drop acrolls RS. This 90rrects for offset voltage that is intraAID converter that is flexible and easy to tie to microprocesd~ced anywhere in the system.
sor-based systems. The benefits of a sampled-data comAUTO AOJUSTMENT " '
parator and an unusual ladder now make an AID converter
actually easier to fabricate than a digital-to-analog convertElectrically actuated switches 1 and, 2 allow the automatic
er.
adjustment of the offset voltage. It should be noted that op
R~", ~p-------t,
R
IV
CHIPSELECT,Cli0<4l--------------t
2
WRITE,WlIp..I-------.,...-:---....-""""I
'-----'
~-~~
SW2
READ,Ii1Ip..I-----------+-t""""l
p----~
ADCDIDI
AID
CDNVERTER
AID
CDNVERTER
DUTPUT
DATA
,"112&5
PRDGR_llE
PERIPHERAL
INTERFACE
1\,.--.,.------1 PORTI
~-----; PORTC
II
lDGIC lEVEL
IOV DR5Y)
TL/H/8721-3
FIGURE 3. Automatic. Adjusting the offset voltage of a differential amplifier pair In a transcript
bridge network can be done automatiCally. A microprocessor provides this adjustment through a
programmable peripheral Interface and a buffer Integreted circuit.
684,
CMOS 01 A Converters
Match Most
Microprocessors
National Semiconductor
Application Note 275
James B. Cecil
With double buffering, 8, 9, and 10-bit mulUplying units are
useful for microprocessor control of gain and attenuation.
microprocessors. The converters appear to the microprocessor as a memory location or as an input! output port and
require no interfacing logic. Each has two levels of input
buffers-an input latch and a register (Figure 1).
A new family of complementary MOS multiplying digital-toanalog converters has arrived on the scene and promises to
make microprocessor interfacing truly universal. The double-buffered MICRO-OACTM units eliminate many common
problems, bridging the way to a host of new applications
that include microprocessor-controlled gain, attenuation,
and multiplication.
The converter's register holds the digital data undergoing
conversion, while the input latch is kept busy acquiring new
input data. The digital input data is used to update the 01 A
converter. The double buffering feature allows 10 bits of
microprocessor data to be assembled from 2 data bytes. It
also prevents the analog output from changing while the
digital input word is updated.
.
The proliferation of the microprocessor in electronic circuits
has brought with it an equal proliferation of microprocessorcompatible 01 A converters. Many of these converters, however, have shortcomings in that they often require additional
external components to be truly microprocessor-compatible. Furthermore, depending on a converter's resolution and
data format, a deSigner is sometimes forced to adopt additional interfaCing Circuitry for total microprocessor compatibility. Transient output voltage errors can occur during the
updating of a 10-bit 01 A converter from an 8-bit microprocessor bus, when the two words are transferred to the converter. Left-justified (fractional binary) and right-justified (positionally weighted binary) 01 A converter data formats require different interfacing schemes. All of these problems
must be considered in interfaCing a microprocessor and a
O/A unit.
Even when used with l6-bit microprocessors, the double
buffering feature is necessary for the simultaneous updating
of many 01 A converters. Double buffering establishes the
proper conditions for the next test or lets new system parameters be set up at the same time.
Two groups of MICRO-OAC converters are available. The
OAC1000, OAC1001, and OAC1002 are 24-pin units with
10, 9, and 8-bit accuracy fevels, respectively. Each contains
all of the necessary logic functions for interfacing with rightjustified and left-justified microprocessor data. The
OAC1006, OAC1007, and OAC1008 20-pin units are designed for left-justified data at accuracy levels of 10, 9, and
8 bits, respectively.
All the members of this family of multiplying 01 A converters
feature standard chip select (CS) and write (WR) microprocessor control Signals. Data on the microprocessor bus can
be written into the 01 A converter in a standard write cycle.
TWO LEVELS OF BUFFERING
The MICRO-OAC family of multiplying 01 A converters consists of 8, 9, and 10-bit accurate units designed to interface
directly with the 8080, 8048, 8085, Z-80, and other popular
MOST SIGNIFICANT BIT
D
D
BIT7
2·BIT
INPUT
LATCH
D
D
8-BIT
D
rTABUS>
D
D
BITO
LEAST SIGNIFICANT 81T
8·BIT
INPUT
LATCH
Q
o
o
Q
D
Q
18-BIT
DIGITAL·
TO·ANALOG
CONVERTER
REGISTER
TO
CURRENT
SWITCHES
D
D
D
BYTE 1!1VTn
LATCH
ENABLE
CHIP SELECT m
WRITE IVIif
eft
READY
OUTPUT
WIll
TL/H/B715-1
FIGURE 1. Double buffered. The MICRo-DAC family of 8,9, and 1o-blt dlgltal-to-analog converters
has two levels of Input buffers-an Input latch and a register. They are designed to Interface
with 8080-, 8048, 8085, Z-80, and other popular microprocessors, with no interfacing logic.
685
'.
'HANP'~It.i~ THE DIFFERENT DATA FORMATS; ,
of 2 VBE + VTHN,fQ~use,by aU of the 109ic,,input circuits.
Each of thEi'lnput stages has FETs like Q3,. whose source
has the digital input applied to it ,and whose geometry is the
same as that of FET 01. Like 01, 03 also has 60 p.A of
current feeding its drl!-!n. When, the logic 'input lIoltage
equals 2 VBE, 03 conductS, thereby pulling the input of a
standard CMOS inverter to a low level. This 2 VBE threshold
continues to be independent of the Of A converter's supply
voltage. '2 VBE is 'the logiC threshold voltage cif standard TTL
gates. '
'/,
::;t)ifferent data formats exist for many 01'A ·converter prod-
!JetS; '!l11 of:which must be readily handled when .interfacing
" with a. microprocessor. Left-justified (fractional number X
VREF) and right-justified (positional number x VREFf1,024)
are the main ones. Initially, converter manufacturers favored
a left-justffied approach in which the most significant bit was
labeled bit 1. Newer converters have changed to the rightjustified approach match the data format of microproces. sor data buses. Nevertheless, ihe left-justified approach is
. still wideiyused, As previously mentioned, the MICRd-qAC
family can readily handle left- and right-justified data formats
with no additioriai interfacing circuitry.
When a' MICRO-OACconverter uses either an' 8-bit (two
write cycles) or a 16-bii (one ,write ~ycle) data bu~, all .10
locations of the converter's input latch are enabled on the
first wrltl! cycle from the microprocessor. Dependin~ on the
.data format, the next write cycle, if used, overWrites 2 of the
10 locations at the proper data rate.
.
,
."
'Digital data is transferr!'ld 'from the i~put latch to the register
internally in ohe qf three ways: automatically whe.n the second 'write byte occurs; through microprocessor control,
which allows the updating of several OfA converters if this
is necessary; and through the use of an external strobe,
The converter's CMOS logic levels are made' compatible
with those of TTL by a special biasing circuit that uses the
parasitic NPN biPolar transistor available on a CMOS qhip.
The bipcilar transistor supplies a ba~-eniitter voltage (VBE)
that act!! as a reference. for the converter's'digital inputs. It
supplies an ,input threshqld 'voltage of 2 VeE that has the
same amplitude as that of TTL devices,.
.
Details of the biasing circuit are shown in Figuri! 2. Note that
the reference N-chanriel field-effect transistor, 01, is tied. in
a feedback 100'" so
to have its gate voltage biaSed at a
. !evel of VTHN, causing it to conduct,the 60 p.A shown in its
drain circuit. The three NPN transistors in the .loop add a
voltage of 3 VBE to VTHN. The output emitter-follower, 02,
causes a loss of VBE, thus producing a voltage reference
to
A~HIEVING I:tlGH ~CCURACY
The design of the MICRO:O~C's.resistor network is Simple,
even though it provides high. level.s of converter accuracy.
Figure'S shQws the current switching inverted R,217lladder
used, which consists of passiVe componeots.
The operation of the ladder network ,requires 'that all of the
, 2R I!lgs connect to .a .aV,. or ground. level. This means that
the external operational amplifier shown must have,a minimal o11$et voltage. Only 1 mV of offset voltag!'l can introduce a 0.01 % linearity error. into the converter's operation.
Operational amplifiers, like· Nationiil's LM308A series are
available, with low offset voltages, and they require ",0 zero
adjL!I!tments.
'
When ,zero adjustment of the operational amplifier'S offset
voltage is required, a 1 kO resistor can be temporarily
,switched in·between the converter's lOUT 1 tElrminal (which
is tied to the amplifier'S negative input terminal) and ground.
. No DC balancing. resistance should ,be used in the operational amplifier's grounded poSitive inpuUerminal"since it
may create errors. The operational' amplifier, a BI-FETTM
LF356 (made with bipolar and field-effect tranSistors), has a
low input bias current which makes it an ideal choice for use
as a current-to-voltage converter. The amplifier's offset voltage should be adjusted with Ii digital input of aU zeros to
force lOUT 1 ~)f the converter to a zero current level. The
manually switched-in resistor provides a DC gain of about
15 to the offset voltage and makes the zeroing easier to
sense. The converter chip provides the feedback resistor
for good initial matching as well as for tracking over temperature) .
'
as
,.Vee
VTHRESHOLD
TL/H/8715-2
FIGURE 2: ThreshOld. This basic ioglc threShold loop provides the biasing for the MICRo-DAC
family of MOS DIA converters to Interf~ce with TTL voltage levels. This circuit uses the
parasitic bipOlar structure, which dellvets an Input threshold' of ~ VeE to the biasing circllIl
~
,
~
686
I
.~.
= 2
The usefulness of a 01 A converter can be determined by
the magnitude of the linearity errors resulting from changes
in the reference voltage" For applications, like multiplication,
that require small values of reference voltage, small linearity
errors are essential. In the case of the MICRO-OAC converters, reducing the reference voltage from 10V to 1V results in
a worst-case linearity error change of approximately
0.005%.
LOOKING AT THE INSIDE
An examination of the intemal details of the single-pole,
double-throw 'current-mode switches employed in the converters shows that the N-channel FETs' gates are driven
from the 01 A converter's supply voltage. In contrast to a 5V
supply, a 15V level reduces the FETs' on-resistances and
thereby improves the converter's performance.
MICRO-OAC converters are relatively stable in gain and linearity during variations in the t 5V supply voltage. For example, a drop in supply voltage all the way down to 5V results
in a gain error of only -0.1 %. Even smaller is the change in
linearity error for' the same supply voltage swing-just
-0.005%.
Figure 4 shows a typical application of a MICRO-OAC as a
unipolar voltage output device. This circuit inverts the negative reference voltage to a positive output, with a maximum
value of 1,023/1,024 of the reference voltage multiplied by
VREF. The BI-FET operational amplifier used is an LF356
that slews and settles within 3 p.s.
2R
VOUT
TL/H/8715-3
FIGURE 3_ Ladder_ The current-switching, current-mode R-2R resistor ladder of the MICRD-DAC
family of DIA converters Is Simple, yet provides high levels of converter accuracy_ The external
operational amplifier is chosen for minimal offset voltage for the least converter linearity error_
15VDC
CONTROL BUS
BYTE 11iiY'fE1
20 14
VOUT
DAC1006
(FOR lEFT.JUSTIFIED DATA)
15
LSB I---,r.:----r.:---"
VREF
-10.000 VDC
REFERENCE
o ,;: VOUT ,;: 9.990 Voc
TUH/8715-4
FIGURE 4_ Unipolar_In a typical unipolar application, a MICRO-DAC DIA converter Inverts the
negative reference voltage to a positive one_ The positive output Is 1,023/1,024 of the negative reference
voltage multiplied by 9_990 VDC- The output amplifier slews within 3 p.s.
687
Operating the MICRO-DAC'sR-2R resistor ladder in.a voltage switching mode as shown in Figure 5 gives. a faster
slewing and settling time--,1.8 ,""s. The ladder is being used
backwards. The reference voltage that is derived from the
LM336 reference diode is applied to the lOUT 1 pin. An output voltage is produced at the converter's pin 15 where the
reference voltage was previously located in Figure 4. This
output voltage ranges from 0 to (1,023/1,024) (2.49 Vee).
The LF356 operational amplifier used supplias a gain of a
little more than 4 for an overall output voltage ranging from .
to 1 LSB less than 10V (or 9.990 Vocl. The two compensating diodes at the ends of \he full-scale adjustment potentiometer on the LM336 reference' improve the temperaturE! .
stability of the reference voltage.
o
For a bipolar output voltage, the circuit in Fl{}ure 6 may be
used. The bipolar output voltage results from adding or subtracting the reference voltage from the converter's output
voltage.
The output of operational amplifier 1 ranges. from 0 to',
-1,023/1,024 X VREF (or -9.990 Voc). This voltage is
then appliEKI to ope~tional amplifier 2, where a ,gair of. - 2
doubles the voltage range. A -:.10 Voc offset voltage at the
output. of operational amplifier.2 is provided by ad~ing the
conve.rter's reference voltage the IImplifier:'s input..Resistors Rl, R2, and R3 in the circuit of operational amplifier 2,
must s~y matched even during temperature changes for
the circuit of Fig~re 6in order to work properly. .
to
The bipolar converter of Figure 6.is adjusted by first entering,
a digital code composed of all zeros into the 01 A converter..
Next, the offset potentiometer of oPl!raijonal amplifier 1 is .
adjusted for a zero' amplifier output voltage and then th!l
offset potentiometer of operational amplifier 2 is adjusted
for an amplifier output voltage of -10,000 Vee. Finally, a
digital code of all 1s is applied, and the 500n potentiometer,
in series with RIB of the 01 A Conl/erter, is adjusted for an
output voltage of 9:98 Vee. This voltage is VREF - 1 LSB,
where 1 LSB = VREF/512.
CONTROL BUS
m
Blli!
0.11'1'
15VDCo-~t4-+....++-H""""---"""'"IH ~
2.4IIV OC
DACIBDD
(ALL LOGIC FEATURESI
IN914
VOUT
LM336
UV
RE.FERENCE
:
3D.1k
III
IN914
o :!: VOUT :!: 9.990 Vce
TUH/8715-5
FIGURE 5. Volt,ge mOde. Operating the MICR()'OAC 01 A converter's resistor ladder
In a voltag....wltctltng mode provides a faster slewing and settling time (1.8 ,""s) than that
of F/gurtl4. Note that the 01 A converter'S R-2R ladder Is. being used backwards.
ISVOC
R2
CONTROL Bas
1111
0.1%
TImIImI 0 - - - - - - ,
BYTE I l f i m o - - - - - ,
liR (>.- - - - ,
15VOC
1:10---,
RI
MICROPROCESSOR BUS
5k
0.1%
DACIIIDI
VREF
ID.IBDVOC
(FOR
HI
LEFT~aSTIFIED
DATAl
VOUT
13
II
I.
R3
0.1%
-10Voc:!: Vour:!: 9.99Voc
TUH/8715-6
FIGURE 6. Bipolar. By adding and subtracting the MICRo-DAC 01 A converter's reference voltage
from Its output voltage, a bipolar output results. For this circuit to work properly, however,
resistors Rl, R2, and R31n the circuit of op amp 2 must stay matched during temperature changes.
688
MICROPROCESSOR
BUS
RIB
£1,
MULTIPLYING D/A
CONVERTER
VOUT
VOUT ~ -VIN/M
Where M ~ digital Input
(expressed as a fractional binary number) 0 < M < 1
TWH/8715-7
FIGURE 7. Control. A MICRo-OAC 01A converter ean be used for microprocessor control of an
amplifier circuit. Since the converter has 4-quadrant multiplication capability, AC and DC signals
ean be handler. The feedback resistors referred to but not shown Is In the converter.
USING THE MICROPROCESSOR FOR CONTROL
Another way to specify converter linearity is by an end-point
method. For a current output converter, the offset voltage of
the current-to-voltage output amplifier is first adjusted for OV
output. Then the converter is adjusted with a full-scale input
digital code to produce a full-scale output voltage. This simple technique ensures that each of the 10-bit unit's 1,024
steps are within the stated linearity specification. Further, a
pretrimmed output amplifier can be used to eliminate the
zero offset adjustment, leaving only the full-scale adjustment.
The MICRO·OAC multiplying OfA converter can be used in
a microprocessor-controlled amplifier circuit as the feed·
back element for the amplifier (Figure 7). Since the converter has 4-quadrant multiplication capability, both AC and OC
signals can be handled. The feedback resistor (not shown)
is the internal·one on the Of A converter's chip.
The Of A converter in Figure 7 automatically provides an
output voltage that causes the current from the converter's
lOUT 1 terminal to the VREF terminal to equal the input current, VINRfB. Note that when the microprocessor provides
data to the OfA converter with. the LSB set to a 1, a relatively large value of the reference voltage is needed to balance
the input current. This value corresponds to the maXimum
gain of -1,024. The minimuin gain of -1,02411 ,023 is obtained for a Of A converter digital input of all 1s. In all, 1,023
gain steps are provided.
.
The addition of another amplifier in the converter's lOUT 2
leg produces a microprocessor-controlled amplifier and attenuator. Compared with the gain of the circuit that appears
in Figure 7, the gain here is noninverted and ranges from 0
to 1,022.
END POINT VS BEST-sTRAIGHT-LINE
To maximize their product yields, manufacturers of digitalto-analog converters like to use a best-straight-line linearity
guarantee. Unfortunately, this method is based on iteration
of the zero and full-scale converter adjustments, so that errors are optimally split and equidistant from a straight line.
To the converter user, a best-straight-line specification
means that the OfA converter must undergo a sophisticated
adjustment procedure for its linearity to be proven. Furthermore, each OfA converter has a different best-straight-line
fit, making it necessary to adjust every one of them individually.
The differences between the best-straight-line and endpoint specification techniques are shown in the illustration
(below), where a OfA converter with an error of 1 least significant bit is shown failing the end-point linearity test. Note
that by readjusting the converter's full-scale output, the Of A
converter's error is optimally split on either side of the ideal
line in a best-straight-line fit, which is a time-consuming procedure, particularly when done on a large number of individual converters. For many an application where the OfA converter is already mounted on a printed circuit board, the
end-point adjustment of zero and full-scale is much less
time-consuming. Furthermore, this end-point procedure is a
more stringent guarantee of converter linearity than the
best-straight-line approach. The end·point method is used
for OfA converters in the MICROOAC family.
DIGITAL INPUT
TL/H/8715-8
689
National Semiconductor
Application Note 276
SingW.Chin
A New, Low-Cost,
Sampled-Data, 10-Bit
CMOS AID Converter·
"IF IT'S NOT LOW COST,IT'S NOT CRJ;ATIVE"
Cost is the single most important factor in the success of
If the AID converter has an accuracy of ± 1 least significant
any new product. The current emphasis on digital apbit (LSB), this could be expressed as ± 1/1024 or ±0.1% of
full;scale.
proaches to build electronic systems. and the success of
microprocessors have created new, high-volume markets
10 BITS PRESENTS DESIGN PROBLEM
for low cost AID converters. Without this stimulatipn in the
An AID ,converter which provides every possible analog
marketplace, converter products would not have been sevoltage as a tap on a resistor ladder would require 210, or
lected as monolithic components, due .to the relatively low
1024 resistors. A ladder expansion technique has been prevolume usage of the traditional products. The challenge today, therefore; is to find new design solutions which will _ viously developed which has greatly reduced the number of
resistors. This tec~nique has been used to prol(ide an 8-bit
reduce costs of MDs without sacrificing the performance
AID (the ADC0804 family) wf1ich uses. a theoretical minispecifications.
mum of only 7 resistors. (In practice, extra resistors are typiHOW M.ANY BITS ARE NEEDED?
cally used to improve matching by making use of unit resisThe question of how many bits are needed in the AID contors.)
verter for a particular system-is not always easy to answer.
This 8-bit AID design was the starting point for developing
This·is further complicated because of the distinction which
this 10-bit converter. A new idea, which is key to the 10-bit
must .first be made between· resolution and accuracy. For
deSign, is a novel way to, in effect, use the previous 8-bit
example, your digital bathroom scale may have graduations
circuit four times to increase the resolution to 10 bitst. This
which indicate each pound over a range which extends from
was achieved by adding 2 MSBs to the 8-bit design. We will
zero to ·300 pounds maximum. This means you are capable
first., review the 8-bit AID operatipn as a basis for underof "resolving" one ,pound over this complete dynamic range
.
standing the new 100bit design.
or "span." The next question is, "What do I really weigh,
THE
BASIC
8-BIT
DESIGN
say, on my doctor's scale?'.' You may find that his scale
The essential part of the ADC0804 8-bit AID family is a
indicates you are actually three pounds heavier than your
s<;ale indicates: this,i!! the accuracy.problem.
novei, multiple input, voltage comparator. This circuit allows
a new feature for· a comparator: multiple, differential voltA 10-bit AID is capable of resolving 210, or 1024,. minimum
ages rian be accepted as simultaneous inputs to the comvoltage levels over the. range from. 0 to VREF volts. To put
parator, and each differential input can be weighted by scalthis int01he physical world we live in, this degree of resoluing the size of the associated input capacitor. The traditional
tion is capable of differentiating each single sheet of paper,
op amp summing circuit, Agure " is similar, but accepts
which is only 0.004 inches (4 mils) thick in a stack of paper 4
single-ended voltage inputs, and first converts each input
inches high. In any stack of paper up to this maximum limit,
voltage to· an Input current by making use of a scaled or
a· .10-bit AID could be used in an electronic system which
weighted input resistor. These input currents are then algewould sound an alarm if a sheet was added to or removed
braically summed at the "virtual ground" or summing juncfrom the stack. (For Simplicity, this assumes we have a pertion (the (-) input of an op amp which has the (+) input
fect height transducer and perfect analog signal conditiongrounded). The current surplus (or deficiency) is supplied
ing .circuitry between this transducer and the input to the
through the feedback resistor to produce the output voltage.
AID.)
Rl
-.!!-
-V2 o--Y\,""'-_~
V3O--Y\,fIw---4.--I
>--6-000() Vo
DV, THE ''VIRTUAJ,. GROUND"
CURRENT SUMMING REQUIRES:
. . , 1,-IZ+ 13+ IF=O
VOZIF RF
TUH/8716-1
FIGURE 1. The TradItional Op Amp Summing CIrcuIt
tThis dealgn concept was proposed and Implemented by John Connolly.
690
A more useful voltage comparator results from a sampleddata approach, which involves switches and capacitors.
Now, input voltages are converted to input charges by the
use of input capacitors, and the resulting charges are then
algebraically added at a "charge summing".node.
The differential input feature of this comparator has allowed
an unusual resistor ladder to be used for the DAC. Notice
that the top three resistors (each labeled "R") have 1,4 VREF
across them and the lower resistors (each labeled "R/4")
have Yta VREF across them. The comparator, therefore, allows the increased resolution of the 52 selected voltages to
be "fitted into" each section of the upper or $1 selected
voltages. In this way, the first 4 bits of this differential DAC,
or "DDAC," are realized.
This same 4-bit trick is used again via the left side decoding
switches, 53 and 54. These same voltage values provide
charge which is reduced in significance by 16:1, making the
input capacitor for this section a factor of 16 smaller. This
now provides the least significant 4-bit group. The additional
capacitor, C, and the lowennost two resistors (labeled
"R/8") supply a % L5B overall DAC offset voltage. This is
used in AIDs to center the natural ± % L5B quantization
uncertainty of the AID about the integer L5B values of analog input voltage. (This is % L5B voltage is added to the
analog input to cause the OOHEX to 01 HEX code change of
the AID to occur at any analog input voltage value of only
%L5B.)
If we are to use this basic 8-bit design for a 1O-bit converter,
we must make these 8 bits the least significant of the 10-bit
data word. This can easily be done by again scaling the
capacitor sizes. Further, ~ additional M5Bs must be added:
here is where another trick comes in.
A multiple, differential input, sampled-data comparator is
shown in Figure 2 with the switches in the zeroing cycle.
The input-output short, which is accomplished with 5W5
around the inverting gain block (provided by a logic inverter), causes this stage to bias at a fixed DC voltage. For
example, a standard CMOS inverter will bias at approximately one half of the power supply voltage. Notice that at
this time the input switches, 5W2 and 5W4, are precharging
the input capacitors with the ( - ) input voltages of the differentia inputs. These input capacitors will serve as storage
elements to remember both of the (-) input voltages and
the biasing voltage of the gain stage.
These zeroing switches are then opened. The gain stage is
now active and will respond to any deviations in the input
voltage. An input voltage results when the switches 5Wl
and 5W3 are subsequently both closed. As shown in the
figure, t. VI is positive, which inputs a charge, 01, proportional to the value of Cl, (01 = t. VI Cl). If t. V2 is negative,
a charge, 02, will be removed from the charge summing
node. If the charges 01 and 02 are balanced, there is no
net change in the input voltage of the inverting gain block.
These switches are dynamically cycled by a clock and the
system is zeroed prior to each measuring interval. This is
the same operating mode as has been used years ago by
the auto-zeroed or chopper-stabilized op amps. A sufficient
number of these stages are capacitor-coupled to provide an
adequate overall gain for the comparator.
A NOVEL WAY OF ADDING 2 MSBs
The 2 M5Bs of the DAC will control 22, or 4, voltages. If
these are chosen as VREF, ground, % VREF and % VREF
we have an unusually beneficial situation. Notice that the
differential voltage input feature of the sampled-data comparator allows picking up the two intermediate voltages (%
and % VREF) from a resistor divider with only one tap, as
shown in Figure 4. These odd voltage values (% and %
VREF) from this 2 M5B DAC are "cleaned up" simply by
scaling the size of the input capaCitor which is used for this
DAC section by a factor of %. This will, therefore, provide
the 1,4 VREF increments 0, 1,4 VREF, % VREF and % VREF,
which are necessary for the 2 M5Bs. Now the basic 8-bit
circuit can be used a total of 4 times, with each referenced
to one of these 1,4 VREF values. This will cover the analog
input voltage range of 0 to VREF with 10 bits of resolution,
as shown in Figure 5.
MAKING AN 8-BIT AID
This sampled-data comparator was made the heart of an 8bit AID converter, as shown)n Figure 3. The comparator
now has four differential voltage inputs; one for the analog
inputs and three for the DAC. The first 4 M5Bs of the 8-bit
AID are supplied by the DAC switches, 51 and 52. As .
shown, the positions of 51 and 52 correspond to the digital
code, "10 00," for the first 4 bits of the 8-bit word. This
should input VREFJ2 from the DAC. Note that 51 is selecting % VREF and 52 is selecting 1,4 VREF, and these voltages
are the first differential pair which is sampled by 5Wl and
5W2 at the start of a successive approximation search. This
provides (% VREF-1,4 VREF) or % VREF as required from
the DAC.
~
aVl{C>---o'on
U f.-
-;;:
~---ru-~
"-4I--IINVL:~~R
.
'SW2*
{::B
It)
SW3
C2
.-~
'aV2
V
AS
AIN BLOCK
CHARGE
SUMMING
NODE
Vo I
'>4:>---4I-~1
t- _..
TO ADDITIONAL
STAGES
---;n-
H
• Switches are shown in the "zeroing" cycle
SW4*
TLlH/8718-2
FIGURE 2. A Multiple, Differential Input Sampled-Data Comparator or Charge Summing Circuit
691
AIALOG
IIIPUT
VOLTAGE
VREFo--+---+----.
.
"II"
"DI" 2 Milt
''III"
lIe
4MSIt
I14VREF
R/4
''lID''
o--+':I/:":av:'"R-oEF"III"
2 LSIt
R/4
3/11VREF
e
RII
lIZ LSB
....___--tll-_O_F;.;FS;;;;ET~.
R/I
4LSIt
TUH/8716-3
FIGURE 3. Basic DAC Ladder of 8·Blt AID Converter
VREFo-_...- - - -....
1~IN
S1 (MSB) S2 {2nd Bit)
.y l--+ ~gMPARATOR
VOAC
0
0
0
0
1
1
1
0
YaVREF
%VREF
VREF
1
"'"
TUH/8716-4
FIGURE 4. Providing the 2 MSBs of a 10-Blt AID
ZMSIh-
VOAC FROM
ZMSIh
(AS SCALED BYC,N'
00
01
I
I
II4VREF
SEGMENT I
·1I
11
I
I
0
I
\8
I
2/4 VREF
SEGMEIIT2
·1
I
314VREF
SEGMENT3
·1
I
SEGMEIlTe :
.\
I
THE 8-BIT CIRCUIT
IS USED III EACH SEGMEIIT
o
AIIALOG IIIPUT VOLTAGE
VREf
TUH/8716-5
FIGURE 5. How the 2 MSBs Extend the 8-Blt Circuit to 10 Bits
692
This 2 resistor ladder will produce linearity errors in only 2 of
the segments of the overall AID transfer characteristic, because there will be no errors in the first segment (2 MSBs =
0), because VOAC for this code is OV. Similarly, if we assume
that the input capacitors ratio properly, there will be no linearity errors in the last segment, because the full VREF is
sampled (then is weighed to produce % VREF as compared
to the analog h1Put voltage, via CjN)' Any mismatch between
the CjN of the analog differential input voltage and the CjN
of the DACs will cause a full-scale error, not a linearity error.
The, two end segments are therefore both free of linearity
errors and an additional benefit is that any error in the exact
value of the tap voltage on a 2 resistor divider has the natural characteristic that the error is the same magnitude on
the 'h VREF and % VREF voltages, and is simply of opposite
sign. Thus, a linearity trim must provide a single magnitude
of correcting charge, then this same charge is introduced
into the comparator summing mode in one polarity for the
"01" 2 MSB code, and then the opposite polarity for the
"10" code (a correcting charge is not used for the "00" or
"11" codes).
data is left·justified and transferred, most Significant byte
first. This allows a single read cycle to pick up a valid 8-bit
representation (the 8 MSBs) and can save time if this is all
the resolution that is required on a particular analog channel. A second read cycle will pick up the 2 LSBs of the 10·bit
data word. The 6 LSB pOSitions are set to zero in this sec·
ond byte. An internal byte counter keeps track of the byte
sequencing so multiple, double·read cycles can be made, if
desired.
The problem of proparly biasing a 5 VOC reference circuit
when operating from only a single 5 VOC power supply voltage was handled on the 8·bit part by reducing the operating
reference voltage for tile internal DAC to only 2.5 VOC. This
can be deSigned to still provide a 5V full-scale for the AID
by simply doubling the sizes of all of the DAC Input capacitors to the comparator. This technique was also used for
this 10·bit product. The reference voltage can also be further reduced in magnitude to increase the analog resolution
over a reduced analog input voltage span, if desired.
A basic diagram of the DAC and the comparator input sec·
tion of the 10·bit AID are shown in Figure 6. A simplified
schematic representation has been used for the 8 LSB section. This has been shown in more detail in Figure 3 without
the VREF reduction to VREF/2.
To understand the scaling shown for the input capacitors,
keep in mind that it is the input charge which is balanced.
This means that a maximum differential analog input voltage
of 5V would produce an input charge of 5 x 32C or 160C
THE ADC1001, A 1G-SIT AID
In keeping with the similarity to the previous 8-bit AID, a 10bit product was designed to fit in the same 20 pin (0.3"
wide) package and to use the same pinouts. Now a customer can easily interchangll from an 8 to a 10-bit AID. This
allows for a range of performance variation in his end products while using the same PC board.
The problem of getting the 10-bit output of the AID onto an
8-bit data bus is handled by reading two 8·bit bytes. The
A:tr:
l
V'N(+I~J
.---------------11--9---'7'"
VINI~I'~
+Vee
>o---4HI- -
0-....--------.,
R
4R
2R
+VREF/l
0--+--------.
4R
>;;}8C~i--li I ~~
~
~J-f
V<}C&....o
---------II---+-r.....
V< ___
___
,
I
I
t/lLIIOFFIET
L..
VOLTAGE ,
&....01
en
,
Cf4
FlTRIM
VOLTAGE
,
I,
:
~1M=n:.
&....0,
..J
TL/H/8716-6
FIGURE 6. The DAC and Comparator Input Section
693
~ .-----------------------------------------------------------------------------~
~
~
input capacitor Vts smaller in, value ,to properly 'reduce the
significance of the last 4 bits>
cOI,lIombs.lf !he DAC were' forced to a "11 0000 0000" or
300HEX code, the voltage, which is output fron'i:the"2 MSe
section, would; be, VREF/2. This is converted to an input
charge via the 48C capacitor, so this charge; 03I>OHEX, be-.
comes:
FULL-S<:ALE TRIM'
FUII~scal~ (or "gai~ ..j errors arl;' trimmed' bYinko~!lcing",",
add~i(:mal ,corr~ctirlg charge into ttle summing nOde of, the,
comparator. This is done in steptl; for example, no full-scale
con:ection is used ,on the first % of the ~nal!'!l input, yoltage
range (near zero). The next,range {eceiyes 'kof the,to~
FS correcting, ch&J:ge, th~n o/:a, and ,finally the full ol:larg~ is,
introduce" in the last section. This seq\!encing of the FS
is ,achieved by dynamically altej;~g the input"capili«itanc" from no «Bpacitance to Cl~; to Cf4, and 'finally' to
3C/4. This is the reason for the'lIxtra input capacitqrand
tlie added switches; which are shown in the FS tt'inf section
of Fl{}ure 6.'
"
'
,
and as
ihen,
!rim
Q300HEX = 1206
which ratios to the analog fuli-scale
charg~, QAF~ as
,Q300HEX = ~ 20C = o/.i FS
QAFS
160C",
which is the proper weight for the 300HEX code. '
,-,.'
APPLICATIONS,
The standard applications 6f the 8-bit ADC0804 series· can
now easily be extended to 10 bits by simply plugging in the
new ADc1001 10-bit part. In 'addition, a 24 pin product
(ADC1021) is also available, which brings all 10 bits oUt for
a 16-bit data bus application.
Similarly, the "00 10000000" or080HEX code should require '/a (VREF) at the analog input (neglecting the effects of
the '12 LSB off~t voltage shift) to balance. This is the output
of the'8 LSB Section 'with a binary code of "1000'0000"
input to this DAC section. The charge fror'ri tlie analog Input,
QA, which corresponds to an' analog 'input' voltage of Ya
VREF, is given by:
" QA = Ya(VREF) (320)
The, outpu~ vOI~ge of the 8-bit 'DAC~ection for 080HE~
code is '12 (VREF)/2,' so the 'charge input by this DAC, QOAC,
is given by
QOAC =
The ;zero offsetting (by introc:!ucing a DC shifting voltage into
the, VIN(-) pin) can be"used to accommodate analog input
volt!lges whic~ do ,not ,swing togrO\!nd. The VREf{2 input
voltage can also I;>e reduced to accommodate a reduced
span of analog inp,ut yoltages. FinaIlY,$~tem d~signerS can
use the same PC board for ~ither an a;bit,or a 1O~product
to, take advantage of the, $tandard, pinouts used for these,
AID converters.
.,
, '
(VREF)
'h2 -(16C),
CONCLUSIONS
The multiple, input, sampled-data voltage comparator allows many benefits in both the design and application flexibility of monolithic AI.D converters. This revo~ionary concept has reduced the die size of AIDs, alloWs many product
benefits, and appears to be the optimum solution for the
realization of a low cost, high performance; monolithic AID
converter line: '
'For further details see data sheel
and this ratios to the analog input change, QA I, as
QOAC
QA
as expected. The 4
= '12 (VREF/2) (16C) = l'
' Ya (VREF) (32C) ,
LS!3 grouping of this 8-bit DAC uses an
'"
694,
The New MICRO-DACTM
Product Line for
Microprocessor Systems
National Semiconductor
Application Note 277
.James B. Cecil
A second generation of the popular MDAC (or multiplying
DAC) is now available which has been designed to provide
an easy interface to microprocessor systems. These new
MICRO-DAC products are low power drain CMOS converters, which typically require only 0.5 mA supply current (2 mA
max) and draw only approximately 600 p.A from a 10 VOC
reference supply.
ent, it will cause a 0.15% error. This means that all of the
allowable error in a 10-bit DAC will be used up due to this
thermal gradient. From this, it is obvious that the CMOS
DAC, with its combination of a low temperature coefficient
thin-film resistor ladder and an on-chip power dissipation of
30 mW max, will overcome one of the major problems in
bipolar designs.
The basic problems which are inherent in bipolar designs
are not present in this CMOS product. CMOS devices have
nearly infinite current gain, therefore there are no {J or a
errors in the design. Also, there is no analogous term to
offset voltage in these products, rather, an ON CMOS
switch is nothing more than a small resistor which can be
controlled by device geometry. To avoid the temperature
coefficient and piezoresistive problems of diffused resistors,
silicon chromium thin-film resistors are used.
These resistors track within 1 ppm/oC, which insures excellent temperature tracking characteristics. Also, the feedback resistor, which is needed with an external op amp, is
provided on the chip, which insures a low temperature coefficient of the gain or full-scale reading of the DAC.
Bipolar designs in the 10-bit region can have a power, dissipation of 300 mW. Unless extreme care is taken to insure
an almost perfect thermal die layout, it is very possible to
have a 1°C temperature gradient on the die. If a diffused
resistor ladder were to be used in the presence of this gradi-
DATA FORMATS AND DATA BUFFERS
MSB
1
2- 1
1/2
VOUT
0
2- 2
1/4
2- 3
0
2- 4
1/8
1/16
= (fractional binary number)
1
2- 5
1/32
From the digital viewpoint, a DAC seems little more than a
write only memory where the information in the memory is
made available as the analog output voltage. Problems
arise concerning data formatting. Is the data to be left-justified (fractional binary) or right-justified (positionally weighted
binary)? Also, updating a 10-bit DAC from an 8-bit bus can
cause transient output voltage errors until the complete new
word has been transferred.
The data format options are shown in Figure 1. Early converter manufacturers favored fractional binary, and this has
caused the MSB to be labeled as "Bit 1" on DAC products.
As may be expected, this convention has been changed in
the new converter products to match the notation of the bits
on the data bus of p.Ps. People supplying converter products still favor the fractional binary format, but it appears
that the user groups are approximately split on the question
of which to use.
0
2- 6
1/64
2- 7
11128
0
2- 8
1/256
2
2- 9
1/512
LSB
0
2- 10
1/1024
x VREF
a) Left..Justifled Data
MSB
1
29
512
VOUT
LSB
o
27
128
28
256
25
32
= (positionally weighted binary number)
o
o
o
24
16
22
4
20
x VLSB
where VLSB = VREF/l024
b) Right-Justified Data
FIGURE 1. Data Formats for a la-Bit Converter
695
, :Solft (;If these problems go away witt) the addition of flexible
Two product options are offered, 8!1 shown. in th~ IT)atrix of
Figure 3. Each of the 2 functional options is offered in apcuracies of 8, 9 or 10 bi~. The 20 pin 0.3" .wide packages are
used for fixed left-justified data format. The 24 pin part is pin
programmable,for. either right. or left~justi~ied. data.
All of these options make use of the standai-d ,...p control
Signals, such as CS and Wl'i, and the data on the bus can
be read by the converter in a standard write cycle. As expected, the internal CMOS logic is. faster for hig~er' supply
voltages, and this effect on the write strobe width shown
'input digijal data buffers (latches) which allow complete,applications fleXibility (Figure 2). For example, with Iyto levels
,of input buffers (double buffering), the DAC Register has the
. job of' holding the current digital data which is being converted, and the other, the Input Latch, is then available to acquire new digital data which will eventually be used to update the DAC. This allows 10 bits to be assembled with two
data bytes from the p,P and prevents the transient output
'error at updating time. Further, even'with 16--bit ,...Ps, double
buffering is' necessary to allow many DACs to' be, updated
simultaneously. This is useful to establish the proper condi, tions for a next test, or to alloW new system parameterS to
be set up at the same time.
Data formatting is handled by providing flexillilltyin'the way
the digital data is entered into the Input Latch. To allow
operation with either an 8-bit (two write cycles) or a 16-!lit
(Orl8 write,cycle) data,bus, all 1.0 location~ of the,lnput Latch
are enabled ,on the first writecycla frOm the ,...P. Then, depending on the data format, the next write cycle, if ~ed, will
overwrite two Of these locations with the ,proper data.
inFigure4.
. .
is
. The internal transfer of the digital d~ta from the Input L8tch
to' the DAC Register can be controlled in three ways:. 1) automatic transfer when the second byt", occurs, ~). use the
,...p to control the transfer-this signal can update several
DACs, if desired, or 3) use an external strobe to cause the
transfer.
'
TO
CURREIT
SWITC~ES
. . T=I
DATA
IUS
BYTE li19Tn
o-----t-"
mn..~-'
m
.....__"
:~r:~--~------~
TUH/8717-1
FIGURE 2. Double-Buffering the Digital Input Data
500 f-
Part #
l
VINL =O~
VINH =3V TO 5V
J.
Accuracy
Pin Deacrlptlon
(Blta)
DAC1000
10
DAC100l
9
DAC1002
8
DAC1006
10
DAC1007
9
DAC1008
8
24
Has All
Logic
Features
20
For LeftJustified
Data
-
~
~
100
o
~~
Vcc=15V
Vee = 15V
-55-35 -15 5 25 -4....0VOUT
MICRO·OACTM
TUH/8717-7
F.IGURE 9. Adjusting the Vos of the Op Amp
698
END POINT GUARANTEE va BEST-sTRAIGHT-UNE
The internal details of the SPOT current-mode switches are
shown in Figuf9 10l, The N-channel transistors are driven by
the Vee supply voltage which is used for the part. Operation
at 15 Voc reduces the switch ON resistance as compared
to the use of a 5 Voe SUpply and, therefore, improves the
performa(lce of the OAC. The change in galn and linearity
errors as a function of the SUpply voltage are shown in FigUf9 11. These curves are normalized to the performance
with a 15 Voc power supply and show the degradation as
the supply voltage is reduced.
The usefulness of a OAC can be determined by noting the
linearity errors which result as the magnitude of the reference voltage is reduced. This is important for multiplication
applications and other uses which require small values of
reference voltage. In the case of the MICRO-DAC converters, reducing the reference voltage from 10V to 1V results in
a linearity error change of approximately 0.005%.
±VREF e>-
-
-
-
-
-
Suppliers of DACs like to use a Best-Fit Straight-Une linearity guarantee to increase yields. Unfortunately, this, technique is based upon Iterating the zero arid the full"scale
adjustments to optimumly split the errors to be 'equidistant
from a straight line. To the usar, this means that each DAC
has to go through a rather sophisticated adjustment pr0cedure to home in on this best approximation-whlch is different for each part.
,
The alternative specification is called an' End Point Spec.
This means that after a standard zeroing of the Vos of the
op amp (the DAC itself doesn't require a zero adjustment,
so a pre-trimmed low Vos op amp can eliminate this adjustment) and a standard full-scale adjustment, the linearity of
each of ths 1024 stBps Is within specl This Is a large benefit
to the DAC user.
R
R
-JVV\I-....JVV\I-
-
ZR
R·ZR
LADDER
DATA FROM
DAC REGISTER
-
-~-------------------oloun
FIGURE 10. The h . DAC Circuit
0.010
A
LlJEARI~Y E~ROR
~
~
II: -11.025
::-0.050
Ii
i-U15
..::!
V
1/
AGAIIUAAOA
-II.1DO
-0.125
1.
11
Vce - SUPPLY VOLTAGE (Voc)
TlIH18717-9
FIGURE 11. Eftecta of Supply Voltage
on Linearity and Gain Error
699
TLlHI8717-8
The differences between thes.e specification techniqUEIsare, .
shown in Figure, 12. A DAC with an error of 1 LSBandJ!liling
theEll)d point test, i,~,sl;l~wnin Fi{,ure .12. Noiii::eth~t by"
rea~justin!;l tl;l~ f\lllc~c.al~,. th~ errQr,9f this, q~c can pe opt~
mu.mly split to be symmetrically located about ~ &~t-Fit
Straight-Lin~'fJhis search ,for tM' opt!niumendpo,il'lt rlilad.\,,~
justments has to be done, by the 1JSll~, for each individual ..
. DAC.' ThE! end.,pointsp~c, ai"owsstandarcl zero and full, ,
scale adjustment procedures' to be used in PC ,board.,as.-. .
sembly, and no time-con,suming se~ching or special reil-djusiing techniques, ,need to 'be u!,ed, ,Further, it can be ~eeh
that'the end point"spec is a more s~ringer:lt requirement on
, , , .' ",.,' ,
the linearity ,of theDAC, ' , .
.'
:"
, ,
SUMMARY
The CMOS current-switohing DACs have evolved from the
unbuffered MDACs to the "p compatiblil"dOuble-buffered
MICRO-DAC products. Many non-DAC applications have
been generated for tHe' MDACs and we now have the new .
possibility' of "p controlled' gaili, attenuators and multipliers-all of which easily' interface to'a p.P system, THese new'
low cost monolithic DACs will open up manY new applications in the 'modern electronic systems. '
.
"
...
...=>
!;.,
.,~=>
...
c
....,
'"...
CI
~
c
:'l!
DIGITAL INPUT'
DIGITAL INPUT
TL/H/8717-10
FIGURE 12. .,e8toStralght-Llne V8 End Points Specs
,
"
"':
700
:.
z
Designing with a New Super
Fast Dual Norton Amplifier
National Semiconductor
Application Note 278
Timothy T. Regan
WHY ANOTHER NORTON AMPLIFIER?
The current differencing Norton amplifier has been widely
applied over the last 5 years because of the versatility and
availability of quad Norton amplifiers (the LM3900). These
low cost quads are found today in a wide variety of analog
systems, but primarily in medium frequency and single supply AC applications. Today, a brand new dual current differencing amplifier, the LM359, offers spectacular speed improvements which can be used in circuits operating well
beyond the video frequencies.
A NEW HIGH FREQUENCY ACTIVE FILTER
STRUCTURE
Multiple op amp active filter building blocks are very popular
because of their low sensitivities and their tunability. The
basic element of such a filter is the inverting integrator. Usually two inverting integrators are cascaded and a third inverter allows closing the overall loop with the proper phase.
This is the idea behind the state variable and bi-quad filter
structures which today are fully available in low cost hybrid
forms.
How the speed is improved: The speed improvement of
the new Norton amplifier is due to the cascode circuit (Figure 1). Cascode circuits are used in high frequency singleended amplifier designs because there is no Miller effect on
the collector-to-base capacitance of the input transistor.
Also, there is no collector-to-emitter parasitic feedback in
the common base configured transistor, Q2, so the high frequency signal appearing at the output of the cascode does
not reflect back into the input. Furthermore, note that bandlimiting PNP transistors are eliminated from the signal path;
here PNPs are used only for collector loads, so not only is
high speed maintained, but high gain is also obtained without additional amplification stages.
y+
•
N
~
y+
-=-
H
1+1
~
":'
":'
":'
YIIAS
1
TLiHf7490-2
FIGURE 2. Adding a Current Mirror to
Provide Current Differencing Inputs
y+
HINPUT
TLfHI7490-1
FIGURE 1. Basic Cascode Circuit
Adding a mirror to get differential Inputs: To make the
high frequency single-ended amplifier more versatile differential inputs should be provided. An easy way is to add a
current mirror across the negative (inverting) input terminal
(Figure 2). This method provides current differencing, as the
current entering the non-inverting input is extracted from the
inverting input current. The LM359 is then a current differencing, as opposed to a voltage differencing, op amp.
The programmable features extend versatility: An additional feature of the LM359 is the programmability of its
speed, its input impedance, and its output current sinking
capability for line driver applications and for control of overall power consumption (Figure 3). An internal compensation
capacitor is adequate compensation for all inverting applications where the gain is 10 or higher. An additional compensation capaCitor can be added externally to reduce undesired bandwidth or to fit any particular application, as will be
discussed later. The following sections illustrate some new
design ideas using this fast Norton amplifier.
701
OUTPUT
Ho---...."'"-i
1+10--.........
TLiH17490-3
FIGURE 3. A Simplified Schematic of the LM359,
a High Speed, Current Differencing Amplifier.
The Input, Output and Speed CharacteristiCS are
Externally Programmable.
..
, The op ainp count in these filters could,~e re.duced~y .one
.: ,(allowing ,use of a dual op amp instead of i3 op amps .or a
"quad) if a',true non-inverting integrator could be built with a
, ,single op amp. Unfortunately, this cannot be done with stan"dard op.:'amps but is a trivial task with current differencing
amplifiers (Figure 4). Combining a non-inverting integrator
with an inverting one, a, new high ,frequency and I.ow;sensitivity active filter building block can be made (Figure 5). Table I shows the 3 particular filt~r II1ructures, together with
VOl
V02
CI
,.'
;,TABLE I. Analysis and DesIgn Equations
"
Type,
their design ettuations, which are deriyed fr.om Figure.5. The
frequency compensation for the 2 amplifiers, is ilsymmetric
to optimize performance. Also" since the.' !-M369 is a wide
' bandwidth amplifier, high frequency circuit layout is strongly
recommended. The circuit works with a single supply, and
the output DC biasing of each filter type is provided with 2
resistors, R1 and Rb, 'wilich should be ch.osen.according to
, Table II,
' ,
R12.
,fa
fll1
,I
BP
LP
0
,Ri2
00
II
HP
BP
Ci
00
00
f
2'ITRC
Qo'
Ra
R
1
2'ITRC
Aa
R
fZ (Notch)
!"to (LP)
-
R
-Ai2
-
..;
,',
;
III
Notch
or
BandReject
-
"
CI
00
1
2'ITRC
Ril
Type I
Type II
.!. + ...:!... = .!-. R1 ,,= 2R
Type·1II
R
Ra
1
1
Rb' R1
9
C,
"
...lasf -+ 00
C
R
Al aSf "70
-
tl
,',
L~
2
~~
R
VIN(DC)
V,.,.. (R il)
C
,',
~
LM358
VOUT
VIN~~
R'b'
" Ra
RaCi
AC
.
+ R + .0
R = R"";b R1 = 2R
.!.+...!...=..!....!...=
',R
-
-
2 'IT RRiCCi
TABLE II. DC ~iasing Equations for
V01 (DC) "" V02 (DC)'" V""/2
2 VIN (DC)
V"" (R V
I
Ho(HP)
Ra
AI;!
1
Aa
R
:
, Ho(BP)
I
+..!...
'
2R
,~
""~f.~IN dt
Cc (EXTERNAL COMPENSATION
REQUIRED)
TLlH17490-4
FIGURE 4. A True Non-Inverting Integrator
{.
lLI I
Rl
v·
'~jl
elN
,(~,
II'
RQ
..
"
"
111
~~=L'
R
II
12.T
_
'rt1'
:-r"" .IJ_-, ~~;
- "
-,,~z..
II
10pF
- T",'
Rb'
I~
Cj
R
"
,
'
to Figure 5
.
I
v·
,
Table I and Table II relate
:
VOl'
V02'
TLtHI7490-5
,
FIGURE 5. High Performance 2 Amplifier BI-Quad Filter. Half of the LM359 Acta as aNon-Inverting Integrator and the
Other Half Acts as an Inverting One. No Extra Inversion Is Necessary to Provide Proper Phase.
,. 702
The operating range of an active filter can be estimated by
comparing its 0 0 , center frequency product (fo x 0 0 ), with
the gain bandwidth product (GBW) of its active elements.
The fo x 0 0 should be less than the active element GBW
by a factor 01 at least 20; a higher factor will yield less sensitive filters. For instance, with a 5 MHz op amp, the fo x 0 0
product of the filter should not exceed 250 kHz, and in reality should be even less. The filters tested with the LM359
could extend their fo x 0 0 product up to 2 MHz.
The simplest method to dynamically control fe is to vary
ISET IN through a control voltage, Ve, where:
I
=
Ve - VBE
SET IN
RSE":" IN + 500!!"
In this manner, CCOMP should be chosen for the highest
desired corner frequency at maximum ISET IN. Two curves
illustrating the dependence of the corner frequency on
ISET IN for two different compensation capacitors are shown
in Figure 7.
VOLTAGE-CONTROLLED LOW PASS FILTER
A most unique feature of the LM359 is that it provides the
user with complete control of its frequency response over a
very wide range. The combination of both programmable
input stage current and external compensation capability is
the key to this flexibility.
1-+-H.y,..o'l-eeOMP = 110 pF
100
i
~
One of the most simple, yet illustrative, examples of the
usefulness of this capability is the voltage-controlled low
pass filter shown in Figure 6. The corner frequency of this
filter is determined by the closed loop corner frequency of
the inverting, gain of 100 amplifier. This frequency is directly
controlled by the frequency of the dominant pole of the amplifier's open loop response, which can be approximated by
the expression:
f
!l:
:;
i"""
10
eeOMP = 0.0047 I'F"-
I
0.1
tttttt:titit:::t±itt:iittl
0.01
1 1
0.1
10
100
ISETIN (mA)
=
31SETIN
P - 2 7r CeOMP AVOL VT
TUH/7490-7
FIGURE 7. Amplifier Closed Loop Corner
Frequency va ISET IN
It should be noted that as the compensation capacitor is
increased, or ISET IN is decreased, the maximum slew rate
of the amplifier is decreased. To prevent slew rate induced
distortion of sinusoidal input Signals, the following restriction
applies:
where AVOL is the amplifier's DC open loop gain, VT is equal
to KT/q or 0.026V at room temperature, ISET IN is the input
stage programming current, and CeOMP is the total compensation capacitance.
Rl
10k
liN
1~"
Rl
el
(>-1":
100
_
~~
lOk
IlV
ec'
Slew rate max = 3 SET IN;;,
OMP
''"~~
T
'OUT
RSET OUT
lOk
VIDEO AMPLIFIERS
~
The basic principle behind the design of the LM359 is to
provide amplification of high frequency signals with the ease
of using standard operational amplifiers. The most obvious
application area for this amplifier is in the video area where
a fair amount of gain is required at frequencies much higher
than monolithic op amps can provide.
TL/HI7490-6
FIGURE 6. Voltage-Controlled Low Pass Filter. Minimum
Input Frequency Is Determined by C1 and R1.
The closed loop corner frequency, which, as stated is also
the corner frequency of the" filter, is:
fe =
fJ • GBW
=
A specific application is the amplification or buffering of a
composite video signal for a distributed monitor system.
fJ • AVOL • fp
where fJ is the feedback factor, R1/(R1 + R2), and a Single
pole open loop frequency response is assumed. Combining
these two expressions, the corner frequency is:
fe =
Vo peak,
where Vo peak is the peak output voltage of the filter and CJl
is 2 7r fiN, where fiN is the signal frequency. The output
voltage for Signal frequencies less than the corner frequency of the filter (within the passband) should then be restricted to:
ISET
RSETIN
IN I, 5.6k
lMJ59 '):
CJl
3 ISET IN • fJ .
27rCcoMPVT
703
Figure 8 shows a typical connection for a non-inverting video amplifier whose signal source may be either detected
video from a receiver, or possibly a camera signal. The output stage of the lM359 can be progra,mmed, as shown, to
drive a terminated 750 cable to 4 Vp-p for use as a video
line,driver. For color signals, the differential phase error and
differential gain error at 3.58 MHz are desirably low, as noted in Table III.
pulses that can be processed by data separating or decoding circuitry. The two amplifiers in a single lM359 package
can be combined in a variety of ways to provide the basic
blocks of a playback channel.
a)'For very high bit rates and low level signals they can be
cascaded to optimize 'overall 'gain bandwidth product, as
already shown in Figure 9.
b) For single-ended playbac~ signals (non ce.nter-tapped
head), one amplifier can be used as a gain stage and the
other as a differentiating stage, to convert recovered signal peaks into bi-directional zero crossing Signals, and
then properly d~e a comparator with regard to direction
of flux changes on the disc or tape; this simplifies decoding of phase-encoded data.
c) For differential playback Signals (center-tapped head),
one amplifier can be used to provide gain for ea~h output
signal individually to retain the differential Signal, or a single amplifi~r difference amp can perform a differential to
single-ended conversion and the other amplifier' can perform differentiation Of the single-ended signal. For mult~
channel, parallel recorded data, the overall component
count of the playback system can be minimized by using
one amplifier of the lM359 per channel.
TABLE III. Typical Video Amplifier Performance
AV = 20,dB
-3 dB Bandwidth -
2.6 Hz to 25 MHz
Differential Phase Error <1°
Differential Gain Error < 2%
'} at 3.58 MHz
'
Amplifier Output Swing ' := 4 Vp-p Max
For general purpose wideband amplifiers, the availability of
two amplifiers in a single package allows cascading two
gain stages to achieve very high gain bandwidth products as
shown in Figure 9.
'
,
DISC AND MAGNETIC TAPE MEMORY SENSING
In digital data recovery from a magnetic storage medium,
such as a disc or magnetic tape, there exists a need for high
gain bandwidth amplifiers to convert the low level voltage
transients from the output of the playback head (caused by
a magnetiC flux reversal on the tape or disc) to, digital
Combining gain with constant delay filtering: Another
important application of the lM359 in data recovery systems is that of filtering. It is moSt desirable to prevent high
frequency noise spikes from being coupled through the
sensing stage causing erroneous readings, but the low
I pF
Uk
15
Uk
15
Uk
12V
Tl/HI7490-8
FIGURE 8. A Typical Application of this, Fast Norton Amplifier as a High Perfomance Video Amplifier Driving a 750 Line
0.01
r:lOOPF
,"IN
Uk
o--Ll"+~"'..J\N~""-"
>1.;.4+-O.OUT
~"1000
SIN
Circuit BW '" 8 MHz
20k
TUHI7490-9
FIGURE 9_ General Purpose, High Gain, Wldeband Ampllflera Can Be Obtained by
Cascading the 2 Norton Amplifiers Available on a Single Chip
704
pass filter used must not induce time delays to valid data
signals which will be decoded by their time relationship to
each other. This immediately implies a constant group delay
low pass filter or a Bessel filter approximation which, if implemented with active components, can also provide signal
gain. Figure 10 shows a fourth order, 250 kHz, gain of 100
Bessel filter. Here, because of the low 0 0 requirements of
the Bessel filter, a simple (Sallen-Key) filter structure has
been chosen over the previously discussed higher performance structures. Note, however, that constant group delay
filtering and amplification are performed with a single
package.
mirror allows significant improvements of the noise characteristics. For an inverting application where the non-inverting input would only be used for DC biasing purposes, an
alternate biasing scheme, the nVeE biasing, can be used, as
shown in Figure 11. This allows "shutting off" the input current mirror which, in itself, will reduce the input noise by a
.
factor of two.
In addition, the input stage programming current can be increased to further reduce the noise voltage at the expense
of an increase in input noise current and low frequency 1ff
noise, which are not a problem in low input impedance,
wideband amplifiers. The typical effect on noise vs input
stage current is illustrated in Figure 12.
A HANDLE ON INPUT NOISE
The programmability of the amplifier's input stage current
and the ability to "shut off" the non-inverting input current
3.l1li
Uk
20pF
0.1
~
'IN ----,
12pF
I.I1f1
380
12V
I-~M_"'''''''''''''''''''''''''''.:..t
620
1.3k
"ouT = 100
elN
fa = 250 kHz
Time delay = 636 ns
for f :s; 250 kHz
>1;.;.4...._
0 • 0UT
TLlH/7490-10
FIGURE 10. A Fourth Order, 250 kHz Bessel Filter for Data Recovery Systems.
The Filtering Function Is Done with a Single Package.
7.6k
C
'IN <>-I1-..J\j'V\r--+-I
'='FIGURE 11. nVBE Biasing can Reduce Input Noise Voltage
705
TLlHI7490-11
32
40
..
~....
..:
~,
ZI
30
.
25
2D
co
15
co
·,0
...!!!>
.~ 24
>
..s
... 20 \ISET IIf =2 ~A
~
...
ISET 1"1- u.05 ~A
co
...> 12" \ L / ISHIN"O.SmA !!!
35
..
~
co
z
4
-...
~
o
100
lk
10k
lOOk
1M
10M
10
100
Iii
10k
1II1II<
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
TL/HI7490-12
TLlHI7490-18
a) Effect of "Shutting Off" the Input Mirror
b) Nollie Performance of Figure 11
FIGURE 12. Programmability Provides a Handle on Input Noise
MAKING A FAST JFET INPUT OP AMP
The current mirror input stage of ~he LM359 can be used as
an active load for a differential JFET stage to form a super
fast op amp (Figure 13). This circuit combines the high frequency performance and programmability of the LM359 with
the high input impedance and low bias currents of a discrete
JFET input stage. External compensation of the LM359 is
generally required to accommodate any additional phase
shift of the input stage, and the "pole-splitting" configuration shown works quite well. The speed performance is
shown in Table IV. Note that this op amp should be mainly
used for very high speed, single supply AC coupled circuits.
This is because the op amp DC input offset voltage depends mainly on the matching of 2 discrete JFETs.
A HIGH COMMON·MODE INPUT VOLTAGE
DIFFERENCE AMPLIFIER.
An inherent feature of a current differencing input stage is
that the voltages from which the input currents are derived
are limited only by the l11aximum'input current (or mirror current) of the amplifier lind the size of the input resistors. An
application that takes advantage otthis is a high commonmode voltage difference amplifier (Figure 14). In this circuit,
the LM359 will amplify the difference in voltage between
inputs V1 and V2, but both inputs can be riding ona common-mode level as high as approximately 250 Voc without
exceeding the maximum mirror current of 10 mAo
The addition of resistor R1 in Figure 14 allows an adjustment
of the common-mode rejection ratio by adjusting the inverting input bias current, via the programmable input stage current, ISET IN. This bias current error is most significant at
lower common-mode input voltage levels. By making the
bias current directly proportional to the input level, a 20 dB
CMRR improvement is possible by adjusting R1 for maxi. mum CMRR at the maximum input common-mode voltage.
TABLE IV. Typical Amplifier Performance
AV
BW
Sr
Cc
1
40 MHz
60V/p,s
51 pF
10
24 MHz
130Vlp,s
5pF
100
4.5 MHz
150 Vlp,s
2pF
lZV
I-Io--"H
6.1k
vo
'Vos null (VOS is typically
ISlAS
<
< 25 mV)
50 pA
TLlHI7490-13
FIGURE 13. Combining the Norton Amplifier with Discrete
P·Channel JFETs to Make a Fast Voltage Mode Op Amp
706
r-------------~----------------------------------------------------_.~
Z
N
12V
5tIIc
~
12V
MEDIUM FREQUENCY
251c
VlF
VI
.--U....I--o
Vo
25k
V2
RI
Ilk
SQk
fOUT= nf!N
L..--Il,Afv-------4....---Wllw--O I2V
TLlHI7490-15
TLlH17490-14
FIGURE 15. Using a Fast PLL to Make a
High Frequency, Ultra Linear V IF
FIGURE 14. A High Input Common-Mode
Voltage Difference Amplifier
'2V>---9-------~----~-----.--~~--------------------------..,
IN
6.1,*
1Dk*
10k
,....
1001c
'OOk
D.D11AF
FULL-SCALE
ADJUST
V,Oo---""""/\/II____...-I
-5V ) -_____________......__.J
....
1M3"
All diodes lN914
'Metal film,l%
"Polypropylene
·"''''Mylar
Ql-+2N5D38
FUll-scale edjust made with V,N
Zero adjust mede with V,N
~
~
-1 DV
- D.W
lour - &GIl kIIz/IIIILT 0-----....-----<><:1-----....----------.......1-1
27pF
1/1DM7414
TL/H/7490-17
FIGURE 16. Complete Schematic of an Ultra Linear, Two Decade (50 kHz -
707
5 MHz) VCO
BUILDING A FAST AND ULTRA LlNEARV/F
CONVERTER
Linear and fast voltage-to-frequency (V IF) converters are
very difficult to build, especially when standard VIF design
techniques are used. A solution to this problem is the use of
a fllst 'phase locked loop (PLl-) which is driven by a medium
frequency and ultra linear VlF IC (the LM331), Figure 15.
This high frequency operation is obtained via a frequency
divider inserted into the loop, and the linearity of the overall
circuit closely approximates the linearity of the medium frequency input V IF. The high frequency, quasi linear VCO,
and the error amplifier of the PLL are designed by using the
2 sections of the LM359. The output frequency of the VCO,
which is also the output of the system, is divided by 100 and
is compared with the output of the driving V IF via a digital
phase detector. The overall circuit is shown in F/{Jure 16.
Following a zero and a full-scale adjust, the V IF works well
over 2 decades of frequency and its non-linearity is below
0.03%, as shown in Figure 17.
Nortronics Design Digest on Digital Recording, Application
Factors to Consider for Magnetic Heads, 1976.
Pease, R.A., "New Phase-locked-Loops Have Advantages
as Frequency to Voltage Converters (and more),' AN-210,
National Semiconductor Corporation.
0.050
~
50 kHz - 5 MHz veo
TVP LINEARITY ERROR <0.03%,
JITTER (Af.) 0.112%
RESPONSE TIME 50 mllli MHz
0.040
~
II:
~ 0.030
...
;
~
1/
0.020
,
Ii
... 0.010
\
.,
o
10k
lOOk
1M
10M
fO (Hz)
REFERENCES
Fredericksen, T.M.; Howard, W.M.; Sleeth, R.S., "The
LM3900--ANew Current-Differencing Quad of ± Input Amplifiers" AN-72, National Semiconductor Corporation.
TLlH17490-16
FIGURE 17. Typical Performance
708
~--------------------------------------------~====~~
National Semiconductor
Application Note 280
AID Converters Easily
Interface with 70 Series
Microprocessors
AbslrBct: This application note describes techniques for interfacing parallel 110 and serial 110 8-bit AID converters to
the INSB070 series of microprocessors. A detailed hardwal9 and software interface example is provided for each
typsofAID.
As examples, the INSB073 is used to interface with the parallelllO ADC0804, and the INSB072 is used with the serial
110 ADC0833.
INTRODUCTION
The INSB070 series of microprocessors is designed for
compact, low cost control, data acquisition, and processing
applications. Up to 2.Sk-bytes of ROM and 64 bytes of RAM
are available on-Chip. The INSB073 is a programmed version of the INS8072 with a Tiny Basic microinterpreter onchip. The microinterpreter executes source code dire~ly,
,thus avoiding the need to translate the source code Into
machine language. This approach allows users to develop
system software without using a development system and
gives a greater flexibility for deSign changes.
The ADC0801 series, the ADC0808 series,' and the
ADC0816 series are CMOS 8-bit successive approximation
AID converters that inClude TRI-STATEI!> latched outputs
and control logic' for parallel 1/0. These A/Os can be
mapped into memory space or they can be controlled as 1/0
deviCes. The ADC0801 series includes a differential input and
span adjust pin, while the ADC0808 and ADC0816 series
:::====~~
~
'D
include an 8- or Hi-channel multiplexer with"llitched control
logic.
Ihe ADCo831 series, on. the o,ther hand, are CMOS' 8-bit
successive approximation AID converters with serial 1/0. In
addition to the Single' analog input ADC0831 in an B-pin
miniDIP, they ~ffer B, 4, or 2-channel analog multiplexed
inputs. Serial output data, can be selected as either MSB or
LSB first. The channel assignment of the multiplexers is accomplished ,'lNith a 4-bit serial input word preceded by a
leading "1''' start bit.
The ADCQ801, ADCOB02, ADCOB03, ADCOB04 parallel 110
AIDs and the' ADCOB33 serial IIQ AID are designed to
work with a 2.SV fixed reference for a OV to 5V analog input
, 'range. The full 8 bits of resolution ,can l1e encoded over any
smaller analog voltage range by applying one half, of the
desired full-scale analog input voltage value to the, VI1IEF/2
pin.
The ADC080S, ADC080B, ADCOB09, ADC0816, ADC0817
paraile,IJ/O AID converters arid the ADCOB31, ADCOB32,
ADCOB34, and ADC083B serial I/O AID converters are designed to operate ratiometrically with the system transduc;:ers.
A ratiometric transducer is a co,J'1Version device whose outputis proportional to some.aiVitraryfull-scaleyalue. The actual
value of the transducer's output is not important, but the
ratio of this 'output to t.he full-scale reference is important.
Also,' thelie, parts are, designed to use a 5V fixed reference.
__ill-~~~~~~~~
IIN(+lo-....-+~
IINI-Ilo-+-.....-
.....
LATCH 1
__ __
':~::::::::~:>~------~~~==~L::~~~ ~
FIGURE 1. ADC0804 Internal Block Diagram
709
TLlH/5631-1
•
!
location FooO HEX. Tlte read and wrjte stroPE! signals of the
AID and-the prOcesSor aretiedteQ\lther,alldthe lfimi signal of,the AlD}s t~ to the'S~~SE ,B Inp,ut.ot~ .INS8073.
The mici"ointerprefer has built-in I/O routines to serially interface with an RS-23a- fer!llinal. TI:I.'''!~Sl!Q73, F1 flag
should be inverted and buffered to provide an RS-232 level.
Similarly, the INS8073 will accept se"al input data,'huffered
to TTL level without inversion. on,itsSA"inpUl DS14881
081489 quad line driverlreceiver chips are used for TTLI
RS-232 buffering, Baud rate 'can be selected by matching
the two jumpers, J1 and J2, (see Figure 2), with the table
below. A "O'! signifies that the jl,lmper is missing, and a "1"
means that it is installed.
'All Of, theSe AID converters operate from a standard 5V
power Supply, and are available In accuracies over the tern,peratu... i'ange of ±% LSB or ± 1 lSs Including full-scale,
Dro ~. and non-linearity errors.
ADCOeO..IMPLEMENTATION EXAMPLE
Theory Of Operdon
The converter is started
forcing ~ 8nd WR simultaneously I~. This.sets"the BJart flip-flop (F/F) (8841 r1gt.fl'fl1)
which resets the 80blt $hift register, ,resets the II'{TR FIF and
seta FIF1, wlJich is at th8 input erid of the 8-Qit shift regliter.
When;the set Bignal of th8 start F/F 90es low (elther WR or
is high), the 8-blt $hlffregiBter then $hlfts in a "1" from
F/F1, whictl starts theconversio~ prOcess. After the ''1'' is
'CIockeq t.hRx.ghthe 8-bit sbift register; It apPearS .. the
Input to Latch 1. The "1" oUtput from the shift register causes the 8-bit output of the SAR latch to trariStei to .ttie TRISTATE 'output latches. When Littcti 1 is subs8quently' en'abled, the Q ouJput makes a tligh-to-Iow transition which
setsthelNTR F/f. An inverting baffer then supplies the
lNTR output signal. When d8ta Is to be read, the combination of both 'OS and AD tieing lOw will reset the INTR F/F
and will enable the TRI-STATE buffer latch output onto the
8-blt data buB.
1k-byte of exten1aJ RAM Is provided in thit 1NS8073 ~m,
In which the first 256 bYtes
use4 to store the mlcrointerPrete"s ~, stacks
buffers. The ...rilaindilrOf the
RAM "Is used to store data 8nd the lirterface program. The
AID is mappeclinto the 'memory &Pace of the 1NS8073 system at addniss 3000 HEX. eXternal RAMs are lOcated from
1000 HEX to 13FF HEX. A DM74(S138address decoder is
, used to genarate the chip select"agnals for the AiOali~the
RAM. It also ptoVtdes a signal to enable a DM74LS388 TRISTATE HEX buffer Which provides the baud rate settI.ng at
bY
es
Baud Rate
J1
J2
0
0
480Q
0
1
,1200
1
0
300
1
1
110 .
DetaIls ot-both hardware and software interface are given
below and in Figure.2. A Tiny Basic subroutine, along with
an Assembly language' subroutine} are illustrated. The microprocessorstarts'the AID, reads, and 'stores the results
of 16 sucx;esslve conversions. The 16 data bytes are stored
,at location 1300 HEX to ..130F HEX.T~e AssembJy language subroutine can be called tw iSSUing. a "LINK" statement in Tiny Basic. It P,$riorms the ..same fUJilction· as the
,Tiny BasiC; su!lroutine, except it .wlil aXtK:ute faster. l:he Tiny
Basic subroutine takas about 80 ma to execute; .the Assembly Language subroutin~ takes only 96 /JoS (Plus conversion
time).
"d'are
TINY BASIC ,I~RFACE SUBROUTINE
100 REM SUBROUTINE TO START AID AND STORE DATA INTO MEMORY
110 REM C IS THE COUNTER FOR THE NUMBER OF DATA BYTES STORED
120 REM 0 POINTS to THE 1ST DATA ADDRESS
130C=18
1400=#1300
150. #3000=A
:f:'\EM START AID
180 A= STAT AND #20
:REM LOOP UNTIL SENSE B GOES LOW
170 IF A< >0, THEN" 00 TO 180
:REM (CONVERSION COMPLETED)
180.0=. #3000
:REM INPUT CONVERTED DATA
1900=0+1
.
:REM INCREMENT DT ADDRESS
2OOC=C-1,
.
.. :REM. CHECK WHETHER 16 CONVERSIONS
210 IF C>O THEf.! ,GO TO 150
:REM ARE DONE OR NOT
220 RETURN
1NS8072 ASSEMBLY CODE INTERFACE SUBROUTINE·
; THIS SUBROUTINE IS TO BE CALLED BY TINY BASICTHF!OLiGI'I A "LINK" STATEMENT
BEGIN:
. PLI
P2,-13DOH
;P2 POINTS TO A 1ST BYTE ADDRESS
P3,=3000H
;P3 POINTS TO AID
PI-I
A,=OFH
LD
;SET CONVERSION cdUNTER TO 15
, A,COUNT'
;COUNTER ADDFiESS '
ST
,A,O,~ ,
START:'ST
;STARTAID
;WAIT FOR SENSE B INPUT TO GO LOW
WAIT:
',;"LD
A,S
. AND
;(CONVERSION COMPLETED)
A,""2OH
BNZ
WAIT
NOP
LD
A,O,P3
;INPUT CONVERTED DATA
.1,P2
;STORE DATA IN MEMORY
~T
OLD
A, COUNT
;DECREMENT COUNTER. IF NOT DONE,
BP
START
;00 ANOTHER CONVERSION
;RESTORE P2AND P3 FOR TINY BASIC
P3
.. POP
POP
,P2,
RET
;RETURN TO TINY BASIC
710
-
h.li~
14
9
A2
13
12
15
B2 74LS139
ADDRUS lV3 7
~ Al DECODER
......! G1
1 G1
lY2 I
m
~
-~33pf
T
IV
37
NRIT ·A15 9
10k
A14 ~
n
A13
12
A12
13
A11
Ala ~
10k
~3 NHDLD
NBREG
7
~MHZ
:t
AI
AI
A7
AI
AI
A4
A3
A2
Al
AD
XauT
1110k
~
It
II1S81173
'x..
~27pF
~
1 G1 Va: IND Y2
IV
5V'~
I13 • '::"
•I
P 11
?~
~
1~
.flO
,
~
~
4M81
HSI
11 h2 113 114
II .... IIIb IIIIz 1101 Va: GND
CI
MM2n41tx4 RAM
AI AI A7 AI AI A4 A3 A2 Al AD WE'
6 5
J1511611711 12 31 4
~
~
in
I
5VI'~_
• ':"
h2 113 114 (,.
I".... IIIb MM2n41kx4
III1z 1101 Va: GND
RAM
':"
•
CI
I
AI AI A7 AI AI A4 A3 A2 Al AD WE'
.11511111711121314 PIE 15
~
2 Al
n.!.
4 A2
1110pf
.fH·~
10k
5im
1
o.! 'InI(+)
o-! ¥tt( -)
AIICB4
s::o-! ¥mIt
~
lAUD
RATE
HI£CTION
JUMPERS
74LS31i8
HEX IUFfER
t
1'10
~
~
1011
~;' I
.!~~
5V':"
I
,L.
10k
CUI R ~
eLKIN ~
AUD
DGND
DI7 DI8 D85 OM D83 DB2 DG1 DBO WI l1li iIif
.In 112 p3 114 115 p6 117 I!' a 2 5
1011
~
5V
D7!,-"
....
D6~
D6~
D4~
D3~
B2~
D1~
,~
2
(~
l!!!L
oa!!..-
r
NBIIN
IV.!! Va:
.a
iV
1GII
NRD3 4
39
FlM
raND
10k
NWDS I
114081418
1/174D4
1..... 2 2
3
.....
3
SA 38
~
...
.A1
.-
IIS-232
TERMIIlALIIO
JlS..232
TLlH/5631-2 .
FIGURE 2. ADC0804-INS8073 Microprocessor Interface
08~-N\f
accomplished by testing,the carry'bit after each shift and
modifying FI accordingly (see T~bles I and II and Fl(}ure 4).
Once the leading sentinel bit and all four MUX address bits
are clocked in, tlie AlO input is disabled'and 00 is enabled.
One clOCk pulse is required to sync the 'ou~put with the .fall-"
ing clock edge; the falling clock edge is used to clock 'data
out. Each of eight successive ,input loops load the status
register into the accumulator and the, masks to determine
whether the input was a "1" or "0". After ascertaining
which, the result is loaded into the acc!lmulator and the
program successively shifts ,left (for "0"), or shifts left and
adds a "1" (for a "1"). A digitized byte is formed representing the analog,input (see Figures 5 and 6).
ADC0833 IMPLEMENTATION EXAMPLE
Theory of Operation
The three flag outputs (F1. ;F2,' Fa) and a sense input (SA or
S8) are all that is required to interface the ADC08aa and the
70 series family microprof.:9Ssor (see Figure 3). The AND S,
= XX and the OR S, = XX instructions set up the status
register to produce the~pfoper output signals (01, ClK, ~).
The input is derived by IQading the status r~lster Into the '
accumulator and masking all but the necessary bit.
a
The ADC0833 is selected by setting 'CS, ClK, and 01 low.
After setting a counter to account for the 4-bit MUX address
and the start bit, the data is shifted out, serially. This is '
5V
lOOk
5V
-¥t.,..,..-:..: HBRED
NENIN
10k
'NAST, 37
T33#
34
35
36
36
FIGURE 3. A/D COllverslon Ci~uit for Single-Ended MSB First Mode
ClK
01
•
I"
lj
1
I,
0
1
I
-~-SS~ENnT1NINflEl~S~):Nc~ru~~====~M=UX=M~D=R====~-------~-~------~---~~~
DO--~~!·'--~"~~Z~S=TA=J~E------~I
0
0
WD ZERD~FO=R"""-:M::":S::'B"
, MUX SEnl!.
,
~
lSB
," CII lL._"';"""~~_""-~--":"--,,,,,,,,,,_ _ _,,,,,;,,....,...,._,,,,,;,,~_~~_ _ _,,,,
TL/H/5631-3
,.'
FIGURE 4. Exllmple' I/O 'rransactiOn(A/DOutput= 7A; Channel 2, Single-Ended Selected)
712
TABLE I. SINGLE·ENDED MUX MODE
LSB
MSB
SID
Start
1
0
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
Single-Ended
0
1
2
3
+
HEX
Code
13
+
18
+
17
+
IF
3
HEX
Code
-
19
TABLE II. DIFFERENTIAL MUX MODE
LSB
MSB
SID
Start
1
0
0
0
1
1
1
0
0
1
1
0
1
0
1
1
1
1
0
1
0
+
Differential
1
2
-
11
+
-
+
15
-
+
1D
CLQCIC ROunNE
TLlH/5631-4
FIGURE 5. AID Conversion Flow Chart
713
i
~
Z•
START:
c(
lOOP 1:
lOOP 5:
ONE:
ZERO:
CONT:
lOOP 2:
INO:
GO:
PULSE:
AND
lD
ST
lO
ST
lD
JMP
XCH
RRl
XCH
lD
BP
OR
JMP
AND
CAll
OLD
BNZ
lD
CAll
lD
AND
BZ
lD
Sl
ADD
JMP
lD'
Sl
ST
, OLD
BNZ
RET
OR
NOP
AND
RET
S,=OFOH'
A,='5
A,CNTRADDR
A,=O,
A, RESlT ADDR
A,=MUXADDR
lOOPS
,A,E
A
A,E
A,S
ZERO
$,=02
CONT
S,=OFOH
PULSE
A1 CNTRADDR
lOOP 1
A,=08
PULSE
A,S
A,=01
INO
A, RESlT ADDR
A
A,=1
GO
A, RESlT ADDR
A
A, REStT ADDR
A,CNTRADDR
lOOP 2 ,
';SET OS'",; 0, elK';' 0
;SET UP MUX ADDR COUNTER
;CLI:ARS RESULT lOCATION
;lOAD MUX ADDR AND S,ENTINEl BIT
;RESTORE MUX ADDR REMAINDER
;ROTATE SIT 0 INTO CARRY
;SAVE MUX ADDR REMAINDER
;LOAD STATU,S REG
;IF CARRY NOT SET, OUTPUT = "0"
;SET F1 = 1 (01<=,1)
;SET F1 =0 (01';'0)
;PUlSE ClK 0 -+ 1 -+ 0,
;DECR AND lOAD COUNT~R
;BRANCH IFCOUNT=O
;SET UP DATA BIT COUNTER
;PUlSE CLOCK 0 -+ 1 -+ 0
;lOAD STATUS REG
;DETERMINE IF DATA = "1"
;IF ACC= 0, GO TO INO
;lOAD CURRENT RESULT
;SHIFT RESULT lEFT
;ENTER LATEST DATA BIT.
;lOAD RESULT
;SHIFT RESULT lEFT, BIT 0 = 0
;STORE CURRENT RESULT
' ;DECR AND lOAD DATA COUNTER
;IF COUNTER*O, CONT
5,=04
;SETF2=1 (ClK=1)
;DELAY
;SET F2 = 0 (OlK = 0)
S,=OFBH
FIGURE 6. Slngle:.Ended AID Conversion Program
714
Data Acquisition Using
INS8048
National Semiconductor
Application Note 281
Daniel Hagerty
Abstract: This application'note describes techniques for interfacing National Semiconductor's ADC0833 serial I/O,
and ADCOB04 parallel I/O A/D converters to the INSB048
family of microprocessors. A hardware and software interface example is provided for each A/D, along with a brief
theory of operation.
The ADC0804 is a CMOS 8-bit successive-approximation
AID converter with parallel I/O. This AID can be mapped
into memory space or can be controlled as an 1(0 device.
No external logic is needed to interface with the INS8048. A
new differential analog voltage input allows increasing the
common-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage' reference input
can be adjusted to allow encoding smaller voltage spans to
the full 8 bits of resolution.
I""TRODUCTION
Since the INS8048 series microprocessors are single-chip,
multiple I/O line, high speed devices designed as efficient
controllers, the capacity to interface with analog peripherals
is obvious. That the conversion be fast, inexpensive and
easily expanded to accommodate a number of 110 devices
is desirable.
ADC0833 IMPLEMENTATION
Before explaining the system configuration, it is worthwhile
for one to understand the ope,ration of the INSB048 processor's I/O ports. Ports 1 and 2 are quasi-bidirectional; that is,
~hey can be used as inputs or outputs while being statically
latched. If a "1" is written into any port bit, that bit can
function as an input or as a high level output. If a "0" is
written into any port bit, that bit can function only as a low
level output. Outputs are latched until changed and inputs
are unlatched and must be read immediately. When used
with the ANL Pp,A (AND accumulator to port) or the ORL
Pp,A (OR accumulator to port) instructions, these ports provide an efficient means of handling Single line inputs and
outputs. Port expansion;, if ,anticipated, is handled via the
lower four bits of Port 2. These four bits fulfill three distinct
functions:
(1) A quasi-bidirectional static port
The INS8048 is a self-contained, 8-bit processor in a 40-pin
dual-in-line package. It contains its own system timing, control logic and memory. All parts contain RAM (64, 128, 256
bytes) and offer the option of on-board ROM (1 k, 2k, 4k
depending on part). ,It provides extensive bit-handling capabilities, 97 instructions, and offers easy expansion for I/O
and memory.
The ADC0833 AID converter is an 8-bit successive-approximation device with serial 110 and conversion time of 25 /-Ls.
This family of converters offers various configurations of
multiplexed analog inputs which can be software programmed as single-ended, or as differential inPUts, or both.
Single-ended inputs are referenced to a common pili which
is either referred to analog ground or to a fixed reference
voltage. Like the INS8048 family, a single 5V power supply
is all that is needed. The inputs will accep, a OV-5V range.
No zero adjust is necessary. It is compatible with TTL and
MOS at both input and output. The output can be selected
as either MSB or lSB first.
(2) The four high order address bits for external memory
(3) An expander port interface
Only four pins of the processor's Port 1 or Port 2 are needed for physical interfaCing- (see Figure 1). The ANL or ORL
instructions set up the port pins to produce the proper outputs (CS, ClK, and the multiplex address) or to allow for
data input from the AID converter.
5V
5V
Ne
INS8D48
Ne
PI1
P1D
EA
DI
elK
SARS
DO
UP TO 8
ANALOG
INPUTS
BE
lk
Vss
"::"
"::"
5V
TUH/5632-1
FIGURE 1. A/D Conversion Circuit for Single-Ended MSB First Mode
715
;
~
r------------------------------------------------------------------------------------------,
The folloWing description of the' program· can be:,used with
" the listing· or flow chart to understand the prqcedure• .T0
..:·begln colll(ersion, the processor must drive CS low, resetting t1ie'~i)1ultiplex address shift register, the successive-approximation register and the 9-bit shift register. After the
AID converter has been selected, the multiplexer address is
shifted out· serially to the converter. The 4-bit multiplexer
address is always preceded by a start bit, a "1 ~'. The program loads the multiplexer address, start bit and mode bit
into the accumulator as a single byte which is processed
and shifted ouUo the converter. By: shifting this byte into the
carry, each bit is tested and the appropriate,"1" or "0" is
output,to the port. After five such operations, the start bit is
shifted on the rising edge of the clock pulse through the
AID's 5-bit shift register (see Figuf'9s2 and 3, Tables 1 and
2). At this pOint, the digital data input is disabled, and the
digital data output enabled. One more clock pulse is needed
'to synchronize the output on the falling edge of the clock
pulse. On each successive clock pulse, data is shifted serially ·to the processor. The data bits are then shifted, upon
reception, into the accumulator to form the digitized an~og
input.
'
CLK
I !
DI _ _......
1
1
START
~~~~E
W
i I
1
MUX,'ADDR
~
LSI
OO------~~--~Hlw~~Sm~U[rE--------~~:I~!_~~
L£AD ZERO FOR
MUX SETTLING
MSI
csl~__________________________~--~----------------~
FIGURE 2. Ex~mpl. I/O Transaction (AiD
Output = ,7A; Channel 2, Single-Ended
Selected)
,
.
RET
CLOCK ROUTINE
[PULSED CLOCK INPUT
TO AID CONVERTER]
RET
TLlH/5632-2
FIGURE 3. A/D Conversion Flow Chart
716
TABLE I. Single-Ended Mux Mode
LSB
MSB
SID
Start
1
0
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
0
Single-Ended
2
1
HEX
Code
3
+
13
+
1B
+
17
+
1F
3
HEX
Code
TABLE II. Differential Mux Mode
LSB
MSB
SID
Start
0
0
0
1
1
1
0
0
1
1
0
1
0
1
1
1
1
0
1
1
START:
LOOP 1:
ZERO:
ONE:
CONT:
LOOP2:
PULSE:
ANL
MOV
MOV
MOV
RRC
JC
ANL
JMP
ORL
CALL
DJNZ
P1, #OF3H
R2 #5
A, #DATA
R3, #0
A
ONE
P1, #OFEH
CONT
P1, #1
PULSE
R2,LOOP1
MOV
CALL
IN
RRC
RRC
MOV
RLC
MOV
DJNZ
RETR
ORL
NOP
ANL
RET
END
R2, #8
PULSE
A,P1
A
A
A,R3
A
R3,A
R2,LOOP2
P1, #04
P1, #OFBH
0
Differential
2
1
+
-
-
+
11
+
-
19
-
+
10
15
;SELECT AID, SET CSO to 0
;BIT COUNTER - 5
;A - MUXADDR
;CLEARR3
;CY - ADDR BIT
;IFCY = 1 GO TO ONE
;SETDI = 0
;CONTINUE IF.o
;SETDI = 1
;PULSE CLK 0 - 1 - 0, CLK IN DATA
;LOOP, TO SHIFT AND OUTPUT MUX
;ADDR AND SENTINEL
;BIT COUNTER - 8, FOR SERIAL IN
;PULSECLKO - 1 - 0
;A - (DO), BIT SHIFTED TO CARRY
;A - RESULT
;A(O) - CY, SHIFT LEFT
;R1 - RESULT
;LOOP THRU FOR ALL 8 BITS
;CLK ;DELAY
;CLK -
START
FIGURE 4. Single-Ended AID Conversion Routine
717
1
0
Easy expansion, mentioned earlier, has not been.forgotten; .. "." ,,Adlample"'prl5gram is shown in Figure 6. The processor
With the addition of the orle phip' (see Figqrs ,5), ~IiElnumbei'
, .. star\s the AID; reaas and stores lhe result of an analog-toof peripherals can be expanded TEN-FOLDITM INS8243
digital conversi.on through an..interrupt service routine. This
1/0 expander consists of five 4-bit bidirectional poris. One
subroutine starts at.address 30H, and the external interrupt
port provides the interlace wit!!, the' processor, the other four'
vector is located at adl;lress 03H. The converted data word
Is' stored"at on-chip RAM location, 10H. The following is a
provide the 110 expansion., The INS82!13 110 expanper
serves as a direct extension for the resident 110 port of ,the
line by line description' Qf the parallel AID conversion subINSB048 family of processoll!. The INSB048 instruction :set
routine.
., ~EGIN: This is where the 'prpgram starts execution after
provides four instructions $Olely for use with this chip. They
are:
having been reset.· RO 'and R1 are set up with addresses to
MOVD Pp,A-Shift accumulator data to addressed port
point to the AID converter and the address where data is to
MOVD A,Pp-Shift addressed port data to accumulator
be stored.
ANLD Pp,A-ANDing accumulator data to adclressed port" "..AGAIN: Interrupts are enabled to allow the AID to signal
that it has completed its conversion; arbitrary data is written
ORLD Pp,A-ORing accumulat~r data to al;ld~~ss~. 'port'
tO,the ~aviceto, start its conyersion process.
The last two instructions can be used in the same way as
".
..
the ANL and ORL instructions in the first example. It should
LOOP: The processor waits here for an interrupt to occur.
be noted that only one pin can be used in Port since the
The :interrupt servIce roUtine returns with a zero in the accuINSB243, unlike the INS8048. seri4il$, has true bidirectional
mulator to allow the program to continue at CONT.
ports and thus requires that each port be either input or
COI\IT: This is :'Where the anll.log input received earlier is
proceSl!ed.
output. F/{Jurs 5 shows how 10 AID converters could be
connected to allow up to 80 analOg inputs to be monitored'
INDAT~ Upon the occurrence of an interrupt, this routine is
at the expense of only four I/O pins on ,the INS8048 itself.
entered. It reads data from the AID converter (with a MOVX
ADC08041MPLEMENTATION
A,@RO) and puts it into the RAM location pointed to by R1
(MOV @R1, A). The accumulator is cleared in order to pass
The ADC0801/2/3/4/5 AID converters have been delocation LOOP:, (see FigLlrs 6) and control is returned to
signed to directly interface' with processors similar to the
the user's program.
'
INS8048 family. The AID is memory mapped into the exter. Upon' inspection, it can be: seen that each system has its
nal data memory space of'the INS8048 system. The RD,
. ~. 'strengths and limitations,' Because of the need to handle
WR and INTR signals of the AID, and the processor are tied
serial'data with loops for-'!nput and output, the ADC0833 is
directly. In the example circuit" an arbitrarily chosen adapproximately five times slower than the ADC0804. Theredress, EO, is assigned to·the AID, and CS is decoded by a
fore; ,for raw speed, the ADC0804, at 100 p.s conversion
bus comparator, the DM8131. Since the !Iddress and the
,time plus minimal processor service time, is. preferable.
data of the INS8048 processor are lTlultiplexed on the same
F,aster processors can b!iI' ,!Jsed to decrease the response
bus, an inverted ALE Signal from the INS8048 is tied to the
time from any given analog input. All INS8048 series devicstrobed input of the bus comparator' in order to latch the
es are available with clock rates up to 11 MHz. Though
address output from the processof. If 'no other devices are
slow,er, the ADC0833, provides up to eight multiplexed inattached to the INS8048's bus, this decoding can be left off
puts configurable in single-ended or differential modes, and
and the CS input to the ADC0804 is. simply grounded.
uses only four processor I/O pins. In either case, the implementation is not formidable and, with only 2 or 3 chips per
system, not expensive.: '
. ."
i,
PRDO 1---+lPRoG
Expander
Port 4
Port 5
o~tputs
DI
SK
CS1
~2
IN88243
INSl048
P5t-_.....,...;.,
CS3
CS4
es5
_.,1"
CS6
PortS
. ,,',
,t:s.
es7
CS6
eg9
Port 7
es10
DO
eS7-1D
eS3-.
elK PI
•
DO
TLlH/5632-3
FIGURE 5. I/O Expansion
71"8
;TEST ROUTINE FOR INTERFACING INS8048 WITH,ADC0804
;PROGRAM STARTS AT MEMORY LOCATION'lOH
;INTERRUPT SUBROUTINE STARTS AT LOCATION 30H
;DATA WILL BE STORED IN MEMORY LOCATION AT 20H
ADDRESS
OBJECT CODE
0000
0410
0003
0430
0010
0012
0014
0015
0017
0018
OOlA
B8EO
B920
05
23FF
90
9618
00
001B
00
0030,
0031
0032
0033
ORG
JMP
ORG
JMP
ORG
MOV
MOV
ENI
MOV
MOVI
JNZ
NOP
BEGIN:
AGAIN:
LOOP:
CONT:
;PROGRAM STARTS AT 10H
;INTERRUPT VECTOR
;MAIN PROGRAM
;RO POIBTS TO AID
;Rl POINTS TO DATA ADDRESS
;SET THE ACC FOR INTR LOOP
;STARTA/D
;LOOP UNTIL INTR FROM AID
;GO TO USER' S PROGRAM
A. #OFFH
@RO.A
LOOP
;USER' S PROGRAM TO PROCESS
;CONVERTED DATA
NOP
,INDATA:
80
Al
27
93
OH
10H
3H
30H
10H
RO. #OEOH
Rl. #20H
ORG
30H
MOVX
MOV
CLR
RETR
END
A. @RO
@Rl.A
A
;INTERRUPT ROUTINE STARTS
;AT30H
;INPUT CONVERTED DATA
;STORE IN DATA ADDRESS
; CLEAR ACC TO GET OUT OF
;THE INTERRUPT LOOP
FIGURE 6. AID Conversion Routine
ADDRESS DECOQING
(OPTIONAU
AID CONVERTER
5V
lk
5V
Uk
14
T1i
Uk
12
T5
Uk
10
T,4
...
~I
OM8131
-:b-
OUTPUT
~
~
ITRlJIE 81 82 83 84 B5 86
~,
*
IV
6 4 12 8 I
T3 T2 T1 GND
~f20
Vee
MICROPROCESSOR
5V.!! Vee
lk
1 3 5 11 13 15
n
Is 17
9
WiN I + I Vuo I I,VaEF/2
19 10k
CLK R
150 pF
I
I ~
I
ADCDBD4' CLK IN 4
PBO PBl P82PB3P84PB5P86 PB7
18 17 16 15 14 13 12 n
AGNDa
IMINO
1
RDWRIRT
2 3 5
-=
Vee 'leo S'ALE 11
20 pF
INS8D4.
rl~XTALl
H,~
3 XTAL 2
20 pF
HrRmT
I,F
7
EA
-=
080 12
0'1 13
'
,
1-
14
062
0.3::
DB4
DB5 17
IUS
DBS::
DB7
RDB
I'iII 10
lIlT·
~GND
FIGURE 7. AID Conversion Circuit
719
TLlH/5632-4
Single-Supply AppUcatiQriS:
of CMOS MICRODACs
CMOS data acquisition and conversion products are becoming the ideal choice for microprocessor controlled anlllog systems. The use I;)f CMOS allows the addition of more
digital logic functionality on to the same die as the analog
circuitry to minimize external parts'requirements. The inl)~r
ently low power consumption is also a big factor for battery
operation and low heat generation in large scale systelns.
National's MICRODACTM family of 8, 10 and 12~bit D to A
converters all feature on-chip data latches to permit direct
, interface to B or 16-bit data busses. These devices were
designed to', provide the' most versatility from, an analog
standpoint. By utilizing a current switching R-2R ladder network (Ftgure 1), the applied r~erence voltage can be eith,er
a stable DC voltage or an AC voltage within the wide range
of ± 10V. However,' output linearity requires that the two
current output terminals be biased to OV. This is accomplished by using an external op amp to serve as a currentto-voltage converter. Negative feedback via the feedback
resistor included in the DAC keeps the IOUT1 terminal at a
virtual ground potential. A drawback to this technique is that
the output amplifier Inverts and outputs a voltage of the opposite polarity of the applied reference. This then requires
the output amplifier to have a negative supply voltage' if the
reference were positive. To operate with only a single-sop, ply by biasing the ground pin of theDAC and the inputs of
the op amp to % the supply does not work, as the digital
inputs are no longer TTL compatible.
, NatiOnal Semiconductor
Application Note 284
Tim RegaA
All hope is not lost, however, if !'single-supply operation ,is
essential. By taking a somewhat backwards view of the
DA9 ladder network, only a single positive supply is necessarY. In Ftgure 2 the R-2R ladder network is used to switch
voltages rather than currents. 1 By applying the reference to
the normal current output terminal (I0Ui1) and groundirlg
IOUT2 the voltage at the reference terminal will be a fraction
of the reference voltage and a function of the applied digital
input, code.
There are two important considerations when using this
voltage-switching approach. The applied reference voltage'
must be positive since there are internal parasitic diodes
from the lOUT terminals to ground which would turn on if the
refe,rence were to be negative. This, of course, is of no concern with single-supply applications. There is also a depen- '
dence of converter linl;'arity and gain error ,on the voltage
difference between the DAC's Vee supply and the applied
reference voltage. This is a result of the voltage drive requirement of the CMOS ladder switches. To ensure that all
of the switches can tum on sufficiently (so as not to add
signifICant resistance to any leg of the ladder and thereby
introduce additional linearity and gain errol'll) an B-bit DA~
should not have a reterence greater than SV and the
supply should be at least 9V more positive·,than the refer-'
ence. This would keep linearity and gain error degradation '
less than 0.1 %. A 10-bit DAC is a bit more stringent. For a, '
0.005% or less error degradation, the reference should be
less than 3 VOC and Vee should be 10V more pOSitive. The
typical effects of bringing VREF and Vee closer together,
'lee
R
Vo
'oun
N
= Number of bits of resoIuUon
TUH/5633-6
FIGURE 1. The Stan~rd Current-8wltCl'llng R-2R Ladd~r Ne~Ork
2R
I
2R
",'
2R.:
2R
.>
l'
2~
"'i,'
Msa
TL/H/5633-1
FIGURE 2. Operating the Ladder "Backwards" to Serve as a Voltage-8wltchlng Network ",
720
as well as temperature performance, are shown graphically
5 results. This is a single-supply OAC with an adjustable
zero-code output offset. voltage and adjustable output span
to reserve the fOil resolution of the OAO for a range of voltages other than OV to full-scale. An importsnt point to note
is that fQr an all ones code applied, only the voltage at IOUT1
is connected to the ladder and sets the output to 255/256
times the voltage of IOUT1. With an all zeros code applied,
only the voltage at IOUT2 drives the ladder, setting the output to 255/256 times this voltage. This non-interaction of
the two inputs at the end-points makes calibration a breeze.
The incremental analog output steps are automatically set
to (VMAX-VMIN)/256.
The buffers at the two reference inputs in Figure 5 isolate
the code-dependent resistance to ground at IOUT1 and
IOUT2 from the resistive string used to set VMAX an VMIN.
The output responds in accordance to the following expression.
in Rgure 3 for the 8-bit OAC0830 series.
Since. the output is now a voltage rather than a current, an
output op amp is not necessarily required, but the OAC's
output impedance .is. fairly high (equal to its specified reference input resistance of '10k to 20k), so an op amp may be
required' for buffering purposes. Figure 4 shows a singlesupply OAC with an output amplifier providing buffering and
gain for a more useful OV to 10V output from a 2.5V reference. The LM336 reference diode is biased through the internal feedback resistor between the IOUT1 pin and the Rib
pin. The zero-code output voltage is limited by the lower
output saturation voltage of the LM358 op amp. The 2k pulldown load resistor helps to reduce this voltage to 10 mV or
1,4 of an output LSB. Even with a 15V OAC supply, the digital
inputs remain T2L compatible.
Closer inspection of Figure 2 shows that both IOUT1 and
IOUT2 drive the ladder network in an identical manner. Each
leg is connected to either IOUT1 or IOUT2. as controlled by
the logic state of each digital input. If eac~ lOUT terminal is
blased to separate reference potentials, the circuit of Figure
g
I
\
-1 T
F 2.5V
fj -0.2
Vm~5V
VwEf=2.6V
I
E
0.4
VOLTABE MOGE OPEJr~=J ER~oR
0.2
r
I'--- L'
¥tEf=6V
ijERrt-
TA=25'C
-0.4
word.
Gain and Unearlty Error
Variation vs Reference
Voltage
Gain and Unearlty Error
Variation vs Supply Voltage
0.4
(1) VOUT = 0/256 (VMAX - VMIN) + 255/256 VMIN
Where 0 is the decimal equivalent of the 8-bit binary control
'!II!'!
r-VOLTABE
OPERATION I
I
g
0.2 6LINEARITY
ERROR
IE
Vee=1~
.'
I
Gain and Linearity Error
Variation vs Temperature
0.100
I
g
V ~=15V
"..,
I
I
Vee = 15V
r-~1iC=12V"'"'\
0245.1012141.
" Vee, SUPl'Ll VOLTABE (Yael
-0.075
TA=25'C
o
2
~
fj -0.050
ABAIN ERROR
-0.4
~
E
~ C::::= ~
1-0·025
"'"'\
I'
.. -0.2
m E MODE OPERATION I
6LINEARlTY ERROR ..:::::::
Vee = 15V, VR1!F=5V
0;050
Vee=12V, VaEf=2.5V- ;;.c
~~
0.025
",
0.075
J
J
4
•
I
I 1"-
4GAlN ERROR
Vee=15V, VIIfF=5V DR
Vee = 12V, VaEf = %.5V
I I
-0.100
-55-35-15 5 25'45 65 65 105125
TA. AMBIENT TEMPERATURE ('C)
10
VaEF, REfERENCE VOLTABE (Vue)
TUH/5833-2
Note: For these curves, VREF is the voltage applied to the IOUT1 terminal and IOUT2 is grounded.
FIGURE~. The
Effects of Bringing the Vee Supply and VREF Closer Together and Temperature Performance Using the
DAC In the Voltage-Swltchlng Mode
i:
+15V
Hp---o+15V \\:c
LM33I
15
':" +1
OV TO 2.5V
~
..v.AX~
> .........-0 VoUT=oV TO 10V
2k
1---
20k
1Dk
..v.,N
. .
.'
o
30k
COGE (0)
255
TLlH/5833-3
FIGURE 5. A Singie-Supply DAC with Level Shift and
Span Adjustable Output
FIGURE 4. Obtaining OV to 10V Output from a 2.5V
Reference
721
;
~
r---------------------------------------------------------------------------------,
A common requirement of single-~pply systems is that the
outputs of signal-co\lditioning amplifiers must be DO biased,
typically to1jz of the Vee supply, to provide maximum unclipped AC signal swing. The 'circuit of Figure 6 shows,'hQw
this dual-input \loltage"switching DAC configuration can allow the digital input code to centrolthe attenuation of an AC
signal without significantly affecting the DC biasing level. If
the voltage at:lbUT2 is set to the DC level of the voltage at
loun, then the term in equation (1) which is controlled by
the digital input code, D, reduces to just the AC signal at
loun.The DC level at the output is 2551256 times the.DC
level at the input.
amount of current that flows through. the loop,yet receives
its own power from the'very same loop.
Digital aontr.ol and isolation are -provided by a single optoiSOlator and a ,CMOS ,counter. The controlling processor must
generate' a clock and keep track of the. mlniber of, clock
pulses issued to the circuit to know what the loop current is
at any time. On power-up the counter is, resetto lill 'zeros to
give the processor a, starting point, as well as to, inherently
provide a calibration point.When calibrating, potentiometer
P1 would be'set for the zero-code loop current of 4 mAo The
processor would th4[ln issue exactly 255 clock .pulses to the
optc-isolator. Potentiomete,r P2,can then adjust the fullscale current value to 19.92 mA. If one, more clock pulse is
issued, the DAC input code returns to all zeros and the previously set value of 4 mA will flow, as this setting was unaffected by the full-scale adjustment.
The circuit of Figure 7 combines the advantages of low power consumption of the CMOS MICRODACs together with
the non-interactive zero and full-scale, adjustability of, this
voltage-switching technique. This circuit is an isolated 4 mA20 mA current loop controller where the DAC sets the
DACOII3O
FIGURE 6. Single-Supply DAC where,the Dlgltall~piltWOrdAtfecta the Attenuation of
,-
, an AC Signal without Significantly Altering Its DC Biasing Level
• 21!V-55V LOOP sumy
,.v
n,
'-11
I
L,
"
3Dfc
4M
~ii'"
"II
_-1
1III,D711f os QOQ3 Q2 Q1
'2134235&79
-..
1-.....-.",1""
IIACI1I3O
100
Ro
240
Ro
,11<
TlIH/5633-4
FIGURE 1.. ~slly Calibrated. leelated ,4 mA-20 mA Current Loop Controller
722
):.
The NI;'N emitter-follower will con~uct whatever level of ,current necessary to keep the voltage across resistor ~s equal
to the voltage across resistor RX' This voltage is equal to
the 1)utput voltage at the VREF pin of the DAC which can be
determined"from equation (1). The actual loop current is:
(2) ILOOP=VOAcl1/Rs+ 1/Rxl
The seoond LM329 reference diode is used to bias the DAC
Vee supply higher than the voltages at loun and IOUT2 to
preserve linearity.
Finally, what if a D to A function is required, but only a single
5V supply is available and 'minimal supply current is a pi;mary concern (battery powered Instrumentation is a good
example)? The voltage-switching techniques previously de"
scribed are not suitable because not enough voltage is
avail~le to properly bias the DAC. A CMOS DAC is 'still
attractive for its low sUpply' current requiremenfs ~nd it'lt can
be operated in the standard current' switching configuration,
a single 5V supply is sufficient. But.how about thevoltage
inversion and the requi,relTlent for negative supply potential?
,By taking advantage of aFlage-old,t~hnique of ,clooking,a
diode-capacitor network connepled as a DC to DC voltage
inverter, a ,low current negative supply, «an bll generated. In
the circuit of Figure 8, 2 diodes and 2 capacitors are clocked
by a CMOS Schmitt trigger oscillator and connected in such
a fashion as to generate a - 3.8V supply potential. This
negative supply is used only to bias a low c!lrrent LM3852.,5V reference diode to provide the DAC witll a stable neg-
ative reference. Now the inversion of the output current-tovoltage converter will generate a positive' output ranging
from OV to 2.5V as a function of the digital input code.
The amount of ripple that may appear at the reference hiput
is a function of the dy",amic impe!lance of the LM385, the
clock frequency and the size of the switching capacitors.
For the component values shown, the clock frequency is
approximately 1 kHz and the ripple on the reference is 7 mV
peak to peak. This ripple is cleanly filtered by the-bypass
cap around the feedback resistor of the Qutput amplifier.
The Ol4tput op, amp is part of a new low power quad, the
lP324, which is ideal for its ability to common-mode to
ground on the inputs and swing very close to ground at its
output. I,f an extra CMOS Schmitt inverter is not readily available, the oscillator function can be implemented with another of the amplifiers in the op amp package. The total supply
current of this single-supply DAC is on the order of 1.5 rnA
with no output load.
With this technique even the 12-bit DAC1230 can be used
wit/;l no linearity degradation which would be apparent in the
voltage-switching techniques.
REFER,ENCE
,
1. 'Sevastopoulos, N.; Cecil, J.; and Fredericksen, T., ':An
Unusual Circuit Configuration Improves CMOS~MDAC Performance': EDN Mallazine, March 5, 1979, pg. 77.
Your =O-2-5V
TL/H/5633-5
FIGURE 8. Single 5V Supply, 8-81t CMOS DAC
723
~
::
...
~
National Semiconductor
Application Note 285
An ACOustic Transformer
~owered' Super-High
..
Isolation Amplifier
.
,
A number of measurements require an amplifier whose input terminals are galvanically isolated from its output and
power terminals. Such devices, often called parametric or
isolation amplifiers, are employed in situations that call for
measurements in the presence of high common-mode voltages or require complete ground path isolation for safety
reasons. AlthOugh commercial devices are available to
meet these needs, the method of power transfet used to
supply power to the floating input circuitry has limited the
common-mode voltage capability to about 2500V. In addition, leakage currents can run as high as 2 pA.
Present deVices (Figure 1) employ transformers to transmit
power to the floating front end of the amplifier. The output of
the floating amplifier is then modulated onto a carrier which
is transmitted via a transformer or opto-isolator to the output
of the amplifier. Modulation schemes employed inclUde
pulse 'width and pulse amplitude as well as frllQuency and
light intensity coding. The limitation on common~inode voltage breakdown and leakage in this type of device is the
breakdown rating of the transformers employed. Even when
opto-isolators are used to transmit the modulated signal, the
requirement for power to run the floating front end mandates the need for at least one transformer in the amplifier.
ACOUSTIC TRANSFORMERS
A technique which satisfies the aforementioned requirements is available by taking advantage of the piezoelectric
characteristics of certain ceramiC materials. Although piezoelectric materials have long been recognized as electricalto-acoustic or acoustic-to-electrical transducers (e.g., buzzers and microphones) their capability for electrical-to-acoustic-to-electri6a1 energy conversion has not been employed.
This technique, which capitalizes on the non-conducting nature of ceramic materials, is the key to a super-high isolation
electrical transformer. In this device the conventional transformer's transmission medium of magnetic flux and conductive core material is replaced by acoustic waves and a .
INPUI
'
l
'lRANSFORMER .
DRIVE
ClRCUmlY
FLOAnNG
DEMDDUIAIOR
INMS
1---+-oOAMPUFIER
~OUIPUI
TL/H/5634-1
FIGURE 1
724
.
Although other methods of transmitting electrical energy
with, I'ligh isolation are available (e.g., microwaves, solar
cells) they are expensive,.inefficient and impractical. Batteries present and obvious choice but have drawbacks due to
maintenance and reliability. What is really needed to
achieve extremely high «ommon-mode ,capability and low
leakage is a method for transferring electrical energy which
is relatively efficient, easy tp implement and Offers almost
total input-to-input isOlation.
.
non-conducting piezoceramic core. Figure 2 shows a photograph of typical acoustic transformers, fabricated by Channel Industries, Santa Barbara, California. Two physical configurations are shown, although many are possible. In each
case the transformer is constructed by simply bonding a pair
of leads to each end of the piezoceramic material. Insulation
resistance exceeds 101211 and primary-to-secondary capacitance is typically a few pF. The nature of the piezoceramic material employed and the specific physical configuration determines the resonant frequency of the transformer.
Rgure 3 shows a plot of the output of an acoustic transformer driven at resonance. From the data it can be seen that
transfer efficiency can exceed 75%, depending upon loading conditions. Output short circuit current for the device
tested was 35 mAo
primary, while the diodes and capacitor rectify and filter the
secondary's output. Figure 5 shows the collector waveform
at 01 (Trace A) while Trace B, Figure 5 shows the secondary output. Despite the distorted drive waveform the transformer's secondary output is a clean sinusoid because of
the extremely Hi-O of the device. An LM331 V/F converter
is used to convert the amplitude input to a frequency output.
The V IF output drives an LED, whose output is coupled to a
length of fiber-optic cable. Trace A, Figure 6 shows the
LM331's output, while Trace B indicates the current through
the LED. Each time the LM331 output goes low, a short 20
mA current spike is passed through the LED via the 0.01 p.F
capaCitor. Because the duty cycle is low, the average current out of the transformer's secondary is small and power
requirements are minimized. At the amplifier output a photodiode is used to detect the light encoded signal and another
LM331 serves as an FIV converter to demodulate the frequency encoded Signal.
APPLYING THE TRANSFORMER-A 20,OOOY ISOLATION AMPLIFIER
Flflure 4 shows a basic but working design for an isolation
amplifier using the acoustic transformer. This design will
easily stand off common-mode voltages of 20,OOOV and
versions that operate at 100 kV potentials have been constructed. In this design the acoustic transformer's HI-O
characteristics are used to allow it to self resonate in a manner similar to a quartz crystal. This eliminates the requirement to drive the transformer with a stable oscillator.
APPLICAnONS
An excellent application for the high isolation amplifier is
shown in Figure 7. Here, the winding temperature of an
electric utility transformer operating at 10,OOOV is monitored
by the LM135 temperature transducer. The LM135 output
biases the isolation amplifier input and the temperature information comes out at the amplifier output, safely referenced to ground.
The 01 configuration provides excitation to the transformer
TL/H/S634-2
FIGURE 2
lOOk
Yni=3 Vlma
IIN=lOmA/
V
s: 50k
I'
~
~
Iii
~
10k I--_N= 5m
51<
lk
/
'V ~
V
/bN=lmA
o
5
10
15
OUTPUT VOLTAGE (V)
F!GURE3
725
20
TLlH/5634-3
,
...... - - -. .,- - - - - : .-~
':1,
'1'
'
"".'
1iV,
0.01
15V
33k'
-
1II1II'
, Al,A2=LF353duaJ"
1,02
*=1N4148
"
=2N2222A
*1% melal film ,.8Islor,
,b .; Floating common
Amplifier grou~ci
V=
'
..
"
Vau,
'<"
", '
,,/'"
TUH/5634-4
A&V/DIV
B10Y/DIV
TL/H/5634-6
TUH/5634-5
FIGURE 6
FIGURES
ELECTRIC
UTWTY
-3
AMPUF1ElI
TL/H/5634-7
FIGURE 7
726
Figure 8' shows another application where the high common-mode voltage capability allows a 5000V regulated power ,supply to have a fully floating output. Here, a push-pull
type DC-PC converter generates the 5 kV output. The piezo-isolation amplifier provides a ground referenced output
feedback signal to A 1, which controls the transformer drive,
completing a feedback loop.
In Figure 9, the piezo-isolation amplifier is used to provide
complete and fall-safe isolation for the inputs of a piece of
test equipment .to be connected into a CMOS IC production
line. This capability prevents any possibiHty of static discharge damage, even when the equipment may have accumulated a substantial charge.
v+
~-1~--~---'+~u
OUTPUT =
FULLY FLOATING
REGULATED
500DV
AMPLIFIER
r---"::::~ ........._-,r~~~ING
AMPLIFIER
FLOATING
COMMON
FIGURE 8
PRODUCTION UNE
TEST EQUIPMENT
@8
-'\~
o \.J
T.\! !
~
FULLY FLOATING
INPUTSo---t
INPUTS
.....
_--'
TL/H/5634-8
FIGURE 9
727
National Semiconductor ".
Applic,ation Note 286 '.
Applicatio.ns of the LM392"'
Compa~ator
Op·',Amp Ie
". .""1,11···,··'
...,
'.
.,,",
The LM339 quad comparator and the LM324 op amp are
among the most widely used linear ICs today, The combination of low cost, single or dual supply operation and ease of
use has contributed to the wide range of applications for
these devices,
The LM392, a dual which contains a 324-type op amp and a
339-type comp8f8.tciI:, is alsq available: This devica' shares
all the operating features and economy of 339 and 324
types with 'the flexibility of both device types in a ~ngle 8-pin
mini-DIP. This allows applications thatare ~t readilY implemented with other devices but retain.simplicity and low~. '.
F1fJUF9 1 provides an example.'
.
.,
,
..
"
comparator C1 switches, causing 02 to tum off the current
source. At this point the collector voltage of Q4 sits at the .
circuifs input voltage. 01 insures that the comparator will '
not ilelf trigger if the input voltage increases during a "hold"
interval. When a DC biased sine wave is applied to the circuit (Trace 0, FtgUftJ 2) the sampled output (Trace. E, FIgure
2) ·is. available at the circuit's output. The ramping action of,
tha Q4 current source during the "sample" states is just
visible in the oUtput
SAMPLE-HOLD CIRCUIT "
The circuit of FIgure 1 Is an unusual implementation of the
sample-hold function. Although its input-tci-output relationship is similar to standard conflgurationsdts.'operating principle is different. Key' advantages include simplicity, no hold
step, essentially.zero gain error and operation from a single
5V supply. In this circuit the sample-hold command pulse
(Trace A, Figure 2), is applied to 03, which turns on, causing
current source transistor Q4's coliector (Trace B, Figure 2)
to go to ground potential. Amplifier A1 follows 04's collector
voltage and provides the circuit's output (Trace C, Figure 21.
When the sample-hold command pulse falis, Q4's collector
drives a constant current into the 0.01 p.F capacitor. When
the capacitor ramp voltage equals th~ c~it's input voltage,
-
~
B=2V/DW
C=2V/DW
E=2V/DW
E=2V/DIV
~
/"
L
~
I\" /
r\
I\
,., V,
','
','
r
\.... ",
r\ I \
,', ,V ,', V,
','
"
','
r
,', ,V
','
"
A, 8, C HORIZONTAL=20ps/DW
D,E HORIZONTAL=lms/DW
TUHI7493-1
FIGURE 2
INPUT
5V
5V
Uk
Uk,
LM385
1N4148
3.3k·
Ql. Q2. Q3 = 2N2369
Q4 = 2N2907
SAMPI.E COMMAND
INPUT
l-SAMPLE
a-HOLD
FIGURE 1
728
Cl. AI = LM392 ampIllier-comparalllr dual
·1 % metal film resIaIor
TUHI7493-2
"FED-FORWARD" LOW-PASS FILTER
In Figure 3 the LM392 implements a useful solution to a
charge rapidly towards the input value. When the voltage
across the capaci,tor equals the voltage at C1'II positive input, C1'.s output will go high, turning off 01. Now, tl:'le capacItor can only charge through the109k valuEl,and the time
constant will belpng. Waveform B clearly shows this. Th"
pOint at which the filter switches. from short to long time
constant ill adjustable with the 1 k.!l potentiometer. Normally, this is adjusted so that SWitching o~urs at 9O%~98% of
final value, but the photo was taken at a 70% trip point so
circuit operation is easily discernible. A 1 provides a buffered
output. When the input returns to zero the 1N933 diode, a
low. forward drop type, provides rapid discharge for. the capaCitor.
common filtering problem. Thi~ sil)gle supply circuit allows a
signal to be rapidly acquired to final value. but provides a
long filtering constant. This characteristic is useful in moltiplexed data acquisition systems and has been employed in
electronic infant scales where fast, stable readings of infal'lt
weight ~re desired· despite motion on the scale Platform.
When ari input step (Trace A, Figure 4) is applied, C1's negative input will immediately rise to a voltage determined by
the 1k pot-10 k.!l divider. C1's .. + .. input is biased through
the 100 k.!l-O.Ol ,...F time constant and phase lags the input.
Under these conditions C1's output will go low, turning on
01. This causes the capacitor (Waveform B~ Figure 2) to
FILTER L-IN ADJUST
I~
'"
-CI
/Ik
2.2k
5V
+
IDk
Ik
V
,
2N2907
IN933
2~
IDk
lOOk?
~ lO~T'
~
+
~O.OI
,"',
AI. CI
=
TlIHn493-3
lM392 amplifier-comparator dual
. FIGURE 3
-B=1V/DIV r-If"-f_+--f--f_-l--+.!....jl_-I---J.--I
HORIZONTAl=ms/DIV
FIGURE 4
729
VARIABLE RATIO DIGITAL DIVIDER
value to maintain the summing junction at OV. Thissequenl<8 ,is repeated for every input, pul~. DlJring this time
A1's outPut will form the staircase shape shown in Trace B
" the 0.02 ,.,.F feedback capacitor ,is pump8d up by the
charge dispensing action Into A1's suinming junction. When
A1's ,9utput Is great enough to just bias C1's ,,+;; Input
below ground, C1's output (Trace C, F/{/Ure 6) goes low and
resets A1 to OV. Positive feedback to C1's ".+ ", input (Tnu;e
0, F/{/ufe 6) comes through the 300 pF unit, insuring adequate reset time for A1. The, 1 MO potentiometer, by setting
the nl,lmber of stej)S in the ramp required to trip C1, controls
thE! circuit inplJt-output division ratio. Traces E-G expand
the scale to show circuit detail. When the input (Trace E)
goes high, charge i~ deposited into A1's SUmming junction
(Trace F) and the resultant staircase waveform (Trace G)
takes a step.
In Figure 5 the circuit all6ws a digital pIllse input to be divided by any number from 1 to 100 with control provided by'a
single knob. This function is ideal for bench type work where
the rapid set-up and flexibilitY of the division ratio is highly
desirable. When the Circuit input is low, 01 and 03 are off
and 02 is on. This causes the 100 pF capacitor to acCumulate quantity of charge (0) equal to .
O;=CV
'
,
a
where C = 100 pF
andV = ,the LM38!1 potential (1.2V) minus the VCE(SAT}
0102.
When the input goes high (Trace A, F/{/ure 6) 02 goes off
and 01 turns on 03. This causes 03 to displace the 100 pF
capacitor's charge into A1's summing junction. A1's output
responds (Waveform B, F/{/ure 6) by jumping to the required
15V
10k
16k
2.7k
33k
10k
300 pF
5,Ok
220k
1M
DIVISION
RATIO
'*
;IN4148
A1, C1
=LM392 compa,.tor-ampllfler dual
NPN=2N23e9
PNPc2N2907
15V
Tl/Hn493-5
FiGURES
A
8
t\: ~
c
o~
E
F' I,
'":
G
-
.
-
Trace
Vertical
Horizontal
A
10V
500,.,.s
B
1V
500,.,.s
C
50V
5OO,.,.s
0
50V
500,.,.s
.
E
10V
50",s
,
F
10mA
50,.,.s
G
0.1V
50,.,.s
--- ,.. .
-- '- '''\.
~
r--
"'"-
7'", ~
l
:,
TLlH/7493-6
FIGURES
730
EXPONENTIAL V/F CONVERTER FOR ELECTRONIC
MUSIC
02. This causes the entire LM3045 array to be at constant
temperature, eliminating thermal drift probl~ms in 01 's operation. 04 acts as a clamp, preventing servo lock-up during
circuit start-up.
01 's current output is fed into the summing junction of a
charge dispensing ifF converter. C1 's output state is used
to switch the 0.001 J.LF capacitor between a reference voltage and C1 's "-" input. The reference voltage is furnished
by the LM329 zener diode bridge. The comparator's output
pulse width is linimportant as long as, it permits complete
charging and discharging of the capacitor'. In operation, C1
drives the 30 pF-22k combination. This RC provides regenerative feedback which reinforces the direction of C1 's output. When the 30 pF-22k combination decays, the positive
feedback ceases. Thus, any negative going amplifier output
will be fof/owed by a positive' edge after an amount of time
Professional grade electronic music synthesizers require
voltage controlled frequency generators whose output frequencies are exponentially related to the input voltages. Figure 7 diagrams a circuit which performs this function with
0.25% exponential conformity over a range from 20 Hz to
15 :kHz using a single LM392 and an LM3045 transistor array. The exponential function is generated by 01, whose
collector' current will vary exponentially with its base-emitter
voltage in 'accordance with the well known relationship between BE voltage and collector current in bipolar transistors. Normally, this transistor's operating pOint will vary wildly with temperature and elaborate and expensive compensation is required. Here, 01 is part of an LM3045 transistor
array. 02 and 03, located in the array, serve as a heatersensor pair for A1, which servo controls the temperature of
3,3M
15k
15V
15V
0,001
POLYSTYRENE
15V
.or
Uk
SAWTOOTH
1.5k
PULSE
OUTPUT
5k
ZERO
4.7K·
SELECfFOR
1 H,OUTPUT =
OV INPUT
15V
3,Ok
0.05
LM329 '
15V
10k·
2k
> .....--"'J~.......-
......-
lk·
101<
.....~aa - ,
I
I
I
I
I
All N PN = LM3045 array
PNP=2N2907
* = 1 'ttD film resistor
AI, Cl LM392 amplifier·comparator dual
=
+I-
=IN4148
'I
I
I
I
I
I
I
L ________________ -J
FIGURE 7
TLIHI7493-7
731
governed by the 30 pF-22k time 'constant· (Waveforms A
and B, Figure 8); The actual integration capacitor in the circuit Is the 2 p.F electrolytic. This capacitor Is never allowed
to charge beyond 10 mV-15 mV because it is constantly
being.reset by charge dispensed from the switching of the
0.001 p.F capacitor (Waveform C, Figure 8). Whenever the
amplifier's output goes negative,the 0.po1 p.F capacitor
dumps a quantity of charge (Waveform D) into the 2 p.F
capacitor, forcing it to a lower potential. The amplifier's out·
put gOing negative also causes a short pulse to be transferred through the 30 pF capacitor to the U +" input When
this negative pulse decays out so that the U + .. input is higher than the" -" input, the 0.001 p.F capacitor is again able
to receive a charge and the entire process repeats. The rate
at which this sequence occurs is directly related to the current into C1's summing junction from 01. Since this current
is exponentially related to the circuit's input voltage, the
overall ifF transfer function is exponentially related to the
.
A=20V/Dri
LINEARIZED PLATINUM RTD THERMOMETER
In Figure 9 the LM392 is used to provide gain and linearization for a platinum RTD in a single supply thermometer circuit which measures from O'C to 500'C with ± 1'C accura·
cy.01 functions as a current sOurce which is slaved to the
LM103-3.9 reference. The constant current driven platinum
sensor yields a voltage drop which is proportionate to temperature. A 1 amplifies this signal and provides the circuit
. output. Normally the slight nonlinear response of the RTD
would limit accuracy to about ± 3 degrees. C1 compensates
for this error by generating a breakpoint change in A 1's gain
for sensor outputs above 250'C. When the sensor's output
indicates 250'C, C1's "+" input exceeds the potential at
the" -" Input and C1'.soutput goes high. This turns on 02
whose collector resistor shunts A1's 6.19k feedback value,
causing a gain change which compensates for the sensor's
slight loss of gain from 250'C to 500'C. Current through the
,
~
'-;
r
B=10V/Dri 'r
C=10mV/Dri
input voltage. This circuit can lock·up under' several conditions. Any condition which would allow the 2 p.F electrolytic
to charge beyond 10 mV-20 mV (start-up, overdrive at the
input, etc.) will cause the output of the alt!plifiar to. go to t~e
negative rail and stay there. The 2N~907A transist9r pre·
vents this by pulling the U_" input towards -15V. The
10 p.F-33k combination determines when the ·transistor will
come on. When the circuit is running normally, the 2N~7
is biased off and is effectively out of the circuit To calibrate
the circuit, ground the input and adjust the zero potentiometer until oscillations just start. Next,. adjust the full-scale po.
tentiometer so that frequency output exactly doubles for
each volt of input (e.g." 1V per octave for musical purposes).
Repeat these adjustments until botll are fixed. C1 prOvides
a.pulse output while 05 AC amplifies the l\umming junction
ramp for a sawtooth output.
-Ir-
,..-
~
It
D=20mA/Dri
-
HORIZONTAL=20j.iS/Dri
TL/HI7493-8
FIGURE 8
5V
100
LM103-3.9
Uk'
4k'
OUTPUT
>-1_~~)O.1V=O·C
2.6V=500'C
TRIM FOR
O·C=O.100V
OUTPUT
22k'
Sensor
= Rosemount
118 MF-1000-A
10000 atO"C
01 = 2N2907
02 = 2N2222A
A 1, C1
TUHI7493-9
= LM392 amplHier-comparator dual
'metel film resistor
FIGURE 9
732
220k resistor shifts the offset of A 1 so no "hop" occurs at
the circuit output when the breakpoint is activated. A precision decade box is used to calibrate this circuit. With the box
inserted in place of the sensor, adjust ODC for 0.1 OV output
for a value of 1000!l. Next dial in 2846!l (500"C) and adjust
the gain trim for an output of 2.60V. Repeat these adjustments until both zero and full-scale are fixed at these pOints.
TEMPERATURE CONTR"oLLER
Figure 10 details the LM392 in a circuit which will temperatun~-control an oven at 7SDC. This is ideal for most types of
quartz crystals. 5V single supply operation allows the circuit
to be powered directly from TTL-type rails. A 1, operating at
a gain of 100, determines the voltage difference between
the temperature setpoint and the LM33S temperature sensor, which is located inside the oven. The temperature setpoint is established by the LM103-3.9 reference and the 1k-
6.8k divider. A1's output biases C1, which functions as a
pulse width modulator and biases Q1 to deliver switchedmode power to the heater. When power is applied, A 1's
output goes high, causing C1 's output to saturate low. Q1
comes on and delivers DC to the heater. When the oven
warms to the setpoint, A 1's output falls and C1 begins to
pulse width modulate the heater in servo control fashion. In
practice the LM335 should be in good thermal contact with
the heater to prevent servo oscillation.
REFERENCES
1. Transducer Interface Handbook, pp. 220-223; Analog
Devices, Inc.
2. "A New Ultra-Linear Voltage-to-Frequency Converter",
Pease, R. A.; 1973 NEREM Record Volume 1, page 167.
5V
1M
5V
2.7k
1.5k
lOOk
+
10k
lOOk
471'F
SOLID
~TANTALUM
O.ool~
I
I
I
I
I
I
I
IL. _____
A1, Cl
~
lOOk
lOOk
7.511
HEATER
~
_______________ _
-!H~~L.!.E~B~K
LM392 amplHier-comparator dual
TLlH17493-10
FIGURE 10
733
~
National Semiconductor
Application Note 288,
System-Oriented DC-DC
Conversion Techniques
,
In many electronic systems, the need arises' to generate
small amounts ,of power at voltages' other than the main
supply voltage. This is especially the'case in digital,.systems
where a relatively small amount of analog circuitry must be
powered. A number of manufacturers have addressed this
requirement by offering modular DC-DC converters which
are PC mountable, offer good efficiency and are available in
a variety of input and output voltage ranges. These units are
widely applied and, in general, are well engineered for most
applications. The sole problem with these devices is noise,
in the form of high frequency switching spikes which appear
on the output lines. To understand why these spikes occur,
it is necessary to examine the operation of a converter.
A typical DC-DC converter circuit is shown in Figure 1. The
transistors and associated components combine with the
transformer primary to form a self-driven oscillator which
provides drive to the transformer. The transformer secondary is rectified, filtered and regulated to obtain the outputs
required. Typically, the transistors switch in saturated mode
at 20 kHz, providing high efficiency square wave drive
5UO,.H
~~7~F
V
"F
"
to the transformer. The output filter capaCitors are relatively
small compared to sine wave driven transformers an~ overall losses are quite low. The high speed, saturated switching
of the tranSistors does, however;, generate high frequency
noise components. These manifest themselves as short duration current spikes drawn from the converter's input supply and as high speed spikes which appear on the output
lines. In addition, the transformer can radiate noise in RF
fashion. ,Manufacturers have dealt with these problems
through careful converter deSign, including attention to input
filter design, transformer construction 'and package shielding. Figure 2 shows typical output noise of a good quality
commercial DC-DC converter. The spikes are approximately
10 mV-20 mV in amplitude and occur at each transition of
the switching transistors. In many applications this noise
level is acCeptable, but in data acquiSition and other systems which work at 12-bit and higher resolutions, problems
begin to crop up. In these situations, spacial system-oriented DC-DC converter techniques must be employed to insure
against th~ problems outlined above.
INPUT FILTER
SELF-DRIVEN
TRANSFORMER
PRIMARY
15V
}~
OUTPUT AND REGULATORS
T1 = Plco Electronics 1131080
~=lN4935
=
01, 02 2N2219
TUHI7495-1
FIGURE 1
HORIZONTAL = 211 ,.a/DIY
FIGURE 2
734
TL/HI7495-2
BLANK PULSE CONVERTER
(trace A and B) and the blank pulse (trace C) which is issued
at each switching transition. The converter's output noise is
shown in trace D. The blank pulse is used to alert the system that a noise spike is imminent. In this fashion, a critical
AID conversion or sample-hold operation can be delayed
until the converter's noise spike has settled. This technique
is quite effective, because it does not allow the system to
"see" noise spikes during critical periods. This not only insures good system performance, but also means that a relatively simplistic converter design can be employed. The expense associated with low output noise (e.g., shielding, special filtering, etc.) can be eliminated in many cases. Figure 5
details a converter design which uses a different approach
to solving the same problem.
Figure 3 shows a converter which will supply 100 mA at
± 15V from a 5V input. This design attacks the noise problem in two ways. The LM3524 switching regulator chip provides non-overlapping drive to the transistors, eliminating
simultaneous conduction which helps keep input current
spiking down. The LM3524 operates open loop. Its feedback connection (pin 9) is tied high, forcing the chip's outputs to full duty cycle. Internal logic in the LM3524 prevents
the transistors from conducting at the same time. The components at pins 6 and 7 set the switching frequency. The
LM3524's timing ramp biases the LM311 comparator to
generate a blank pulse which "brackets" the output noise
pulse. Figure 4 shows the switching transistor waveforms
5V
5V
4.7k
12
100
0.01
3.3k
4
LM3524
}.-
15k
......._
......--oSV·
.
+
~4.7PF
01, 02 = 2N5023
T1 = Pica Electronics #32165
.,=lN4934
100 mA output-shorl circuit
limit of 150 rnA set by 0.70
resistor at pin 4
FIGURE 3
TL/H17495-3
A=lOV/DIV
8=10V/DIV
C=10Y/DIV
D=5O mY/DIV
HORIZONTAL = 5 pJ£1 DIV
FIGURE 4
735
TL/H17495-4
5V
300pF
~
2Ic
5V
100k
100k
5V
10k
-15V
Ql,Q2=2N2219
T1
= Pico ElectroniC. /131080
Cl-C4
=LM339 quad comparator
~ =lN4934
50 mA output
5V
FIGURE 5
TLlHI7495-5
A=5V/DIV
8=5V/DIV
C=511O mA/DIV
0=20 mY/DIY
HDRIZONTAL = 200 ,a/DIV
TLlHI7495-8
FIGURE 6
.. virt~allydisappears because the output regulators are powIn Figure 5 the system controls the converter, instead of the
erea only by the 100 p.F filter capacitors. The value of these
converter issuing blank commands. ThIs arrangei\lent uses .
. cCap~ltorS'
depend directly on the output load and the
. length of the 'blank pulse. If synchronization to the system is
an LM339 quad comparator to provide the necessary drive
to the converter. C1 functions as a clock' which proVides
.'desi.eild, a system-derived 20 kHz square wave may be apdrive to C2 and
These Cdmparators &ive the'tran$ist9!'S" ....... ~;plied'.atq1~s negative input through 2k, after removing the
.300, pF capacitor and the 100k feedback resistor. The low
(trace B, Figure 6 is Q1's collector. volijige wavetorm, while' .
trace C deijiils its current) to prOvide power to the transnoi~ during t~e blank pulse period affords ideal conditions
'." for sensitive system operations. Although this approach alformer. When a critical syStem operation. muSt.·occur, an
external blank pulse (trace A) is .tlPpliild to··C4. C4's output .
lows great flexibility, the amount of off time is limited by the
goes high, shutting off all transformer drive. Under these··
storage capacity of the output filter capacitors. In most sysconditions, the transformer .current ceases. (note: volUigei
; terns this is' nqt problem, but some cases may require a
ringing on tum-off in trace BLand output noise (trace O)::2i'!f,er WhiCh.s~pPlies low noise outputs at 100% duty
EXTERNALLY STROBED CONVERTER
will
ca.
a
736
SINE WAVE DRIVEN CONVERTER
Figure 7 diagrams a converter which sacrifices the efficient
saturated-switch mode of operation to achieve an inherently
low noise output at a 100% duty cycle. In this converter,
sine wave drive is used to power the transformer. 01 functions as a 20 kHz phase shift oscillator with 02 providing an
emitter-followed output. A1 and A2 are used to drive the
transformer in complementary-bridge fashion (traces A and
B, Figure 8). The high current output capability of the amplifiers, in combination with the transformer's paralleled primaries, results in, a high power transformer drive. The transformer output is rectified, filtered and regulated in the usual
'"
fashion. Because the sine wave drive contains little harmonic content and current spiking, outpu, noise is well below
1 mV (trace C, Figure 8). To adjust this circuit, ground the
wiper arm of the 1k potentiometer and adjust the 100k value
for minimum power supply drain. Next, unground the 1k potentiometer wiper arm and adjust it so that both A1 and A2's
outputs are as large as possible without Clipping. This circLlit
yields a low noise output on a 100% available basis but
efficiency degrades to about 30%. In relatively low power
converters such as this one (e.g., 50 mA output current) this
is often acceptable.
'"
-12VOUT
' 'OUT
1.8.
10Y
'O"F
1:
Tl/H17495-7
FIGURE 7
A=2V/DIV
B=2V/DiV
C=O.DD5V/DIV
HDRlZOtITAL;=50 pI/DIV
TlIH17495-8
FIGURE 8
737
LOW POWER CONVERTER
Figure 9 shows' a 'Converter which operates from very low
power. This circuit will provide 7.5V output froms 1.5V D
cell battery. With 'a 125 p.A load current (typically 20 CMOS
ICs) it will run for 3 months. It may be externally strobed off
during periods where lowest output noise 'Is desired and it
also issues a "converter running" pulse. This circuit is unusual in that the amount of time required for 01 and 02 to
drive the transformer is directly related to the load resistance. The converter's output voltage is sensed by an LM10
op amp reference IC, which compares the· converter output
to its own internal 200 mV reference via the 5.1 M-160k voltage divider. Whenever the converter output is below 7.5V,
the LM10 output goes high, driving the 01-02 pair and the
transformer which form an oscillator. The transformer output is rectified and used to charge the 47 p.F capacitor.
When the capaCitor charges to a high enough value,the
LM10 output goes low and .oscillation ceases. Trace A, Fl{}10,lIhows the collector of 01, whilE! trace,B shCWi!s the
output voltage aqross the 47 p.F capacitor (AC ooupled). It
can be seen that each time thE! output voltage ,falls a bit the
LM10 drives the oscillator, ~orcing the voltage to rise until it
is high enough to switch the LM10 output to its low ~tage.
The frequency of this regulating action is determined by the
load on the converter output. To prevent t/:le converter from
osyillating about the trip point, the 0.1 p.F unit is used to
provide hysteresis of response. Very low loading of the converter will result in almost no on time for the oscillator while
large loads will force,it to run llimost constantly. Loop op~
ating frequencies of 0.1 Hz to 40 Hz are typical. The LM10
output state may be used to alert the system that the converter is running. A pulse applied to the LM 10 negative input
will override normal converter operation for low noise operation during a critical system AID conversion.
UTe
,..---------------<>
"CONVERTER RUNNING"
15k
n...,....-I~-........jr41 7,5V
OUTPUT
....H . .
15k
""'"-,t~
_oCONVERTER STROBE
Tl = Stancor IIPCT·39
01, 02 = 2N2222A
~=lN4148
INPUT
1,5V
"
:'f
TUHI7495-9
FIGURE 9
HORIZONTAL = 10 ms/DIV
TLlHI7495-10
FIGURE 10
738
National Semiconductor
Application Note 292
Applications of the LM3524
Pulse-Width-Modulator
. The LM3524 Regulating Pulse-Width-Modulator is commonly used as the control element in switching regulator power
supplies. This is in keeping with its intended purpose. Engineers closely associate this part with switching power supplies. Nevertheless, the flexible combination of elements
(see box) within the LM3524 also allows it to be used in a
number of other applications outside the power supply area.
Because the device is inexpensive and operates off a single-sided supply, it can considerably reduce component
,cou",t and cirellit complexity in almost any application. The
coiuitant light intensity servo of Figure 1 furnishes a good
example.
CONSTANT LIGHT INTENSITY SERVO
The circuit of Figure 1 uses a photodiode's output to control
the intensity of a small 'light bulb. The constant intensity
output of the light bulb is useful in a number of areas, including opta-electronic 'component evaluation and quality control of photographic film during manufacture. In this circuit,
the photodiode pulls a current out of the LF356 summing
junction, which is directly related to the amount of light that
falls on the photodiode's surface. The LF356 output swings
positive to maintain the summing junction at zero and represents'the photodiode current in amplified voltage form. This
potential is compared at the LM3524 to the voltage coming
from the 2.5k "intensity" potentiometer wiper. A stable voltage for the "intensity" control is taken from the LM3524's
internal five-volt regulator. The difference between the
LF356 output and the "intensity" potentiometer output is
amplified at a gain of about 70 dB, which is set by the 1 M!l
value at pin 9. The LM3524 output transistors are paralleled
and provide drive to the 2N2219 switch transistor. The 5.6k
and .01 ,..F values set the switching frequency at about 30
kHz. Because the LM3524 forms a switched mode feedback loop around the light bulb and photodiode, the average
power delivered to the light bulb will be controlled by the
photodiode output, which is directly proportional to the
lamp's output. Frequency compensation for this feedback
loop is provided by the .001 ,..F capacitor, which rolls off the
loop gain at alms time constant. Figure 2 shows the wave-
31111'10
TlLl7
P11OT01I101IE
-t-
lt
221<
I
I
I
I
t
12V_
8Ul8 ~ ~-4-"""""
11881
14
12
-INPUT I
l1l131iZ1
13
STEP
-AtNIr ~ TEST
""""----YOI'UlSE
IENERAYOR
I
I
I
+ I.PUT 21----~
11
16
2.51<
IITEIISITY
IlGIITROl .".
+15
. FIGURE 1
739
TLlH/6890-1
~
i
r---------------------------------------------------------------------------------,
. forms in the circuit. Trace A is the 2N2219 collector and
trace 'B is the Ac..coupled LF356 output Each time the
. 2N2219 collector goes low, power is driven into the lamp.
, This is reflected in the positive going ramp at the LF356's
output. When the 2N2219 goes off, the lamp cools. This is
shown in the negative going relatively slow ramp in trace B.
It is interesting to note that this indicates the bulb is willing
to accept energy more quickly than it will give it up. Figure
3a elaborates on this. Here, trace A is the output of a pulse
generator applied to the "step test" input and trace B is. the
AC-coupled LF356 output. When the pulse generator is
high, the diode. blocks its output, but when it goes low, current is drawn away from the "intensity" control wiper
through the 22k res.istor. This forces the servo to control
bulb intenSity at a lower value. This photo shows th$t the
bulb servos to a higher output almost threll times as fast as
it takes to go to the lower output state, because the bulb
more readily accepts energy than it gives It up. Surprisingly,
at high intenSity levels, the situation reverses because the
increllsed incandescent state of the bulb makes it a relatively efficient radiator (Figure 3b).
TLlH~6890-2
FIGURE 2
TEMPERATURE-TO-PULSE-WIDTH CONVERTER
B= .ll5VIDIV.
AC-COUPLED
I-VOLT LEVEL
The circuit in Figure 4 uses the LM3524 to convert the output of an LM135 temperature transducer into a pulse width
which can be measured by a digital system, such as a microprocessor-controlled data acquisition system. Although
this example uses the temperature transducer as the input,
the circuit will convert any 0.1 to 5V input applied to the 100
kO resistor into a 0-500 ms output pulse width with 0.1 %
linearity. In this circuit, the LM135's temperature-dependent
output (10 mVI"K) is divided down and applied to A1's positive input. This moves A 1's output high, driving the input to
the LM3524's pulse-width modulation circuitry. The LM3524
pulse-width output is Clipped by the LM185 reference and
integrated by the 1 MO-0.1 p.F combination. The DC level
across the 0.1 p.F capacitor is fed back to A 1's negative
input. This feedback path forces the LM3524's output pulse
TL/H/6890-3
FIGURE3a
TL/H/6890-4
FIGURE3b
'*'l
--------,
II¥
COMPEIIATIOI •
..
+ CL SEllIi
10TE 3
- CL SENSE
IV
'NUlOOWI 10 It
NOTE5~
IV
n n n
14 EMITTER.
L-J L-J L-:; !.::_______-1_~--t..-----------------~3:~~~mR
81D~
7
~
TL/H/8890-9
Note 1: 5V 50 mA regulator available to user.
Note 2: Transconductance diff. input amplifier. Gains from 40-80 dB available by r&siator loading of output. 1.8-S:4V common mode Input range.
Note 3: Over current sense comparator -0.7 to 1V common mode Input range.
Note 4: Output transiators switch out of phase and may be paralleled. Up to 100 mA maximum output currenL
Note 5: Tranaiator may be use.d to strobe LMS524 into an off state at Its outputs.
Note 8: Oscillator typiCally frequency programmable for up to 100kHz.
743
~r---------------------~----------------------------~======~
~ Control Applications of' :III:
oil(
CMOS DACs"
"'National Semiconductor
Application Note 293
The CMOS multiplying cligital-to.anafag cOnverter can be
widely applied in pro~essor-driv,en control appli~tions. Because these devices carl' have' a bipolar reference voltage
their versatility is increased. In some control applIcations the
DAC's output capabilities must be substantially increased to
meet a requirement while others require substantial additional circuitry to drive a transducer or actuator.,A good example of the latter is furnished by F/{/ure 1.
~
SCANNER CONTROL
Biochemists use a p;:O~ure caHed "scanning electrophoresis" to separate cell!! from, each other: In orle form ofthis
process the sample is con~ined within a vertical glass or
quartz tube apprOximately 1 foot in length. When a high voltage potential is applied across the length of the tube the
cells'separ&te along the charge density gradient which runs
along the tube's length. This re~ults in a serie~ of stripes
lk
~=lN4148
~=lN4001
~ = 1% melal film, malch 0.5%
=Molordyne. Inc. 1/1150·1
=LF356
A3, A4 =LF353 dual
Molor
AI, A2
A5, A6 = LM393 dual
FIGURE 1
744
TLIH/5636-1
or bands within the tube as the individual cells, under the
influence of the charge gradient, collect together. When
separation is complete, the tube is mechanically scanned
along its length by a photometer for optical density characteristics of each band. This information yields useful biochemical information to the experimenter. The scanner
must be fully programmable so that it can be run between
any two limits at a variety of speeds. In Figure 1 the two
DAC1020 D/A converters establish the limitS of the scan.
The 5k pick-off potentiometer furnishes scanner location information and the motor drives the scanner (via a geartrain). A5 and AS are comparators, one of whose outputs
goes low when either the high limit (AS and its associated
DAC) or low limit (A5 and itS associated DAC) is exceeded.
A1 and A2 fumish voltage outputs from the current output of
the DACs. A3 and A4 are used to provide suitable reference
voltages for the 5k pick-off potentiometer and the DAC reference inputs.
goes low, setting the DM7474's 0 output too high. This
turns on 02, 05 and 03 resulting in current flow through the
motor from 03 to 02. This forces the scanner to run
towards its high limit. When this limit is reached, AS goes
low and the flip..flop changes state. This turns off the 02,
05, 03 combination and the 04, as, 01 trio come on, forcing current through the motor in the opposite direction via
the 01-04 path. This causes the motor to reverse and proceed toward the lower limit. 07 is driven by a width-modulated pulse train from the processor which is used to control
the scanner's speed via 05 and OS. The diodes across 01,
02, 03 and 04 provide motor spike suppression and the
internal current limiting in the LM395s (02-04) assures
short circuit protection.
HIGH VOLTAGE OUTPUT FOR ATE
Testing high voltage components with automatic test equipment (ATE) is often inconvenient because a source of stable, controllable high voltage is required. Adding this capability to a piece of equipment can be expensive and time
consuming if standard techniques are used. In Figure 2 a
circuit is shown which has been employed in the testing
The DM7474 flip..flop Is configured in a set-reset arrangement which changes output state each time either A5 or AS
goes low. When the lower limit of the scan is reached, A5
-15V
3k
Transformer = TRIAD TV·90
~
lN4006
15V
15V
FIGURE 2
745
TUH/5636-2
of' high voltage transistors and zeners as well all fuse link
blowing in PROMs. In this circuit, a high voltage 'Output is
developed by using a Toroidal DC;DC coriverterwithin a
DAC-controlled pulse-width modulated feedback loop to obtain high voltage. The DAC1020 in conjunCtion with A1 supplies a setpoint to the LM3524 regulating pulse-width modulator. This set point needs to be within the LM3524's common mode input voltage range of 1.8V to 3.5V. The
LM3524's outputs are used to.drive the TV-90 toroid via·01
and 02. The high voltage square-wave transformer output is
rectified and filtered and ,divided down by the 100k-2.7k
string. This potential is fed back to the LM3524, completing
a loop. Loop gain and frequency compensation are set by
the 1000 pF-100k parallel combination, 'and the 10 resistor
at pin 6 of the transformer .is used to sense current for .short
circuit protection. Although the update rate .Into the DAC
can be very fast, the 20 kHz switching of the transformer
and the loop time constants determine the' available bandwidth at the circuit's output. Iii practice, a full output sine
wave s~ing of 100V into'10000 Is available at 250 Hz.
AC signal, typically a ramp. The high voltage plate drive is
furniShed by the 01, 02, 03, 04 configuration which is a
complementary common-base-driven common-emitter 'output stage. BeCause the output current requirements are low,
the usual crossover distortion problems may be avoided by
returning the circuit's output to negative supply via the 120
kO resistor. This eliminates notch comp.ensation circuitry
and results in a simplified design. Because the high voltage
stage inverts, overall negative feedback is achieved by" returning the 1 MO feedback resistor to AS's positive input.
The point now becomes the summing junction for both
DAC-driven inputs and the feedback signal. The output of
this circuit is clean and quick, as shown in Figure 4. In this
figure, 2 complete DAC-driven amplifiers were used to produce the traces. Trace A is the output of A1, while the com'
plementary high voltage Olltputs are shown in Band C.
PLATE-DRIVING DEFLECTION AMPLIFIER.
Another common high voltage requirement involves deflection plate modulation in CRT and electron-optics applications. F/{/ure 3 shows a pair of DAC1218s used to control
both the static (DC) and dynamic (AC) drive to deflection
plates in a piece of electron-optic equipment. In contrast to
the previous high voltage circuit, this one has very little output current capability but greater bandwidth. The deflection
plate load can be modeled as a 50 pF capacitor. In this
application, the output of both DAC-amplifier pairs is
summed at A3. In practice, one DAC will supply a DC level
to the plate (bias) while the other one provides the plate's
8=100v/DIV
C=100v/DIV
HORIZOHTAI.=50 /4/DIV
TUH/5638-3
FIGURE 4
125V
1k
...........-+ .....- ....Icuc
DM7474
~D.DD3
Uk
3.3i1
'---"I\oI\r--05V
= 2N2369
= 2N2907
Cl, C2 = LM311
A1 = LF356
NPN
15V~':5
T.
PNP
PDINTS
-15V
Note: All capacHor values are in "F.
FIGURE 7
used in the circuit. The circuit of Figure 7 greatly reduces
hold step by using an unusual approach to the sample and
hold function. In this circuit sampling is started when the
sample and hold command input goes low (trace A,Figure
8). This action also sets the DM7474 flip-flop low (trace B,
Figure 8). At the same time, C1's output clamps at QS's
emitter potential of -12V (trace C, Figure 8). When the
sample pulse returns high, C1's output floats high and the
O.OOS ,..F capaCitor is linearly charged by current source Q1.
This ramp is followed by A 1, which feeds C2. When the
ramp potential equals the circuit's input voltage, C2's output
(trace 0, Figure 8) goes high, setting the flip-flop high. This
turns on Q2, very quickly cutting off the Q1 current source.
This causes the ramp to stop and sit at the same potential
at the circuit's input. The hold step generated when the circuit goes into hold mode (e.g., when the flip-flop output
goes high) is quite small. Trace E, a greatly enlarged version
of trace C, details this. Note the hold step is less than 10 mV
high and only SO ns in duration. Acquisition time for this
circuit is directly dependent on the input value, at a rate of 5
,..s/V.
753
TL/H/56S7-8
REFERENCE
One Ie Makes Precision Analog Sampler, S. Dendinger;
EON May 20,1977.
A=5V1D1V
B=5V/DIV
C=1V/DIV
D=SVlDlV
E~5Dmv/DIV
A, B, C, D HORIZONTAL .. SJII/DlY
E HORIZONTAL= 100 ../DIV
TLlH/56S7-9
FIGURE 8
A High Performance,
Industrial Weighing System
National Semiconductor
Application Note "295
The continuing ,emphasis on efficiency and waste control in
shows the way the rolls are handled and fed into the coating
machinery. The desired weighing system performance
the industrial environment has opened new applications arspecifications also appear in the figure. Figure 2 shows the
eas for electronic measurement and control systems. Standard electronic techniques can be used to solve many of
specifications for a typical high quality strain gauge load cell
these application problems. In some areas, however, the
transducer. From this information, it can be seen that the
measurement requirements are so demanding that novel . electronic error budget is vanishingly small. The 3 mVIV
and unusual circuit architectures must be employed to
specification on the load cell means that oniy 30 mV of fullscale is available for a typical 10V transducer excitation.
achieve the desired result. In particular, very high preciSion
transducer-based measurements can be achieved by comThe desired 0.01 % resolution means that only 3p.V rebining microprocessor and analog techniques. The performferred-to-input error is allowable. In addition, the gain slope
ance achievable can surpass the best levels obtainable with
tolerance and temperature coefficients of the load cells,
while small, seem to preclude meeting the required specificonventional approaches.
cations. The 0.1 % gain slope tolerance also appears to
An example of a requirement involves high resolution weighmandate the need for manual system recalibration wheneving of 2000 pound rolls of plastic material. In this applicaer load cells must be replaced in the field. Finally, assuming
tion, the rolls must be weighed before they are fed into mathese specifications can be met, an AID converter which
chinery which utilizes the plastic in a coating process. Bewill hold near 15-bit stability over the required temperature
cause the plastic material is relatively expensive, and the
range is required.
number of rolls used over time quite large, it is desirable to
keep close tabs on the amount of material actually used in
The key to achieving the desired performance is in the realization that the system must be designed as an integrated
production. This involves weighing the roll before it is used
and then weighing the amount of material left on the roll
function instead of a group of interconnected signal condicore after it has unwound. In this fashion, the losses accutioning blocks. Traditional approaches which rely on "brute
mulated over hundreds of rolls can be tracked and appropriforce" high stability amplifiers and data converters cannot
ate action taken if the losses are unacceptable. Figure 1
be successfully used to meet the required specifications.
MOVEABLE CHAIN HOIST
MACHINERY
INTO WHICH
ROLL IS FED
TLlH/5638-1
FIGURE 1
FIGURE 2
Desired System Specifications
Typical Load Cell Specifications
Siop~
Accuracy, 0.03%
Gain
Stable Resolution, 0.01 %
Reccmmencled Excitation-l0V
Operating Temperature Range, 1000C Ie 45'C
Gain Tempco-±O.OO08%I'F
Full Load Cell Field Interchangeability
Zero Tempco-±0.OOI5/'F
20,000 Ccunt Display
754
mVIV Excitation ± 0.1 %
The approach utilized is diagrammed in Figure 3. In this arrangement a microprocessor is used to effectively close an
analog loop around the load cells with an instrumentation
amplifier and an AID converter. In this system, four discrete
measurements are continuously performed on each load
cell to determine its error'corrected output. Corrections are
made for zero and gain drift and a first-order temperature
error correction is also ,made. The actual load cell o!Jtput
voltage is read to complete the measurement cycle. The
start of a measurement cycle is initiated by the microprocessor commanding the LF13509 differential input multiplexer
A to position 1 (See Figure 4). In this position, the amplifier
inputs are connected to one side of the transducer bridge.
This determines the electrical, zero in the system at the
common-mode output voltage of the bridge. Physical zero
information (e.g., "tare weight") is fed to the microprocessor
via a pushbutton which is depressed when no load is in the
chain hoist. This operation need only be carried out when
the system is first turned on. The multiplexer is then
switched to position 2.
the string is physically located within the load cell connector. When any such equipped load cell is plugged into the
system, the value of this resistor allows immediate and precise gain slope compensation and eliminates the usual
manual calibration requirements. When this measurement is
completed, the multiplexer is switched to position 3. In this
position the output of strain gage bridge A is connected to
the LM163 instrumentation amplifier. This signal, which represents the transducer output, is amplified by the LM163,
converted by the AID and stored, in memory. The fourth
multiplexer operation is used to read the temperature of the
load cell. In this pOSition, the output of the LM335 temperature sensor, which is located inside the load cell transducer,
is 'determined and stored in memory. The relatively high level LM335 output is resistively divided by 100 so the LM163
does not saturate. Two separate temperature terms, zero
and gain TC, affect the load cell. Although the LM335 provides the absolute cell temperature, the sign of each temperature term in any individual cell will vary. Thus, not only
the cell's temperature but the sign for both zero and gain
terms must be furnished. This is accomplished by a pin
strapping code inside the load cell's connector. This sequence of operations is also performed by multiplexer B for
load cell B. When all the information for both transducers
has been collected, the microprocessor can determine the
actual weight of the roll. The temperature information provides a firSt-order correction for the relatively small effect of
ambient temperature on the load cell's gain and zero terms.
In this position, the LM163 inputs are connected across the
middle resistor in a string of resisto~. The voltage across
this resistor represents the preCise full-scale output voltage
of the load cell transducer. Although the, transducers are
specified for only 0.1 % interchangeability, the preCise value
of gain slope is furnished with eaoh individual device. This
information allows the system to determine the gain slope of
the transducer. In practice, the middle reSistor in
+,
TEMP
OUT
•
A CELL
OUT
MUXA
LF13509
r-~
LM335
INSTRUMENTATION
+
TEMP
OUT
~
::f>-'
......
AID
CONVERTER
LM183
5V
,
B CELL
OUT+--+_",
GAIN
CALIBRATION
MUXB
LF13509
+
I
*
I
II
'Pin strap code
for cell temperature
signs (both A and B)
-
X
, "TARE
waaHT"' ~
BI/TTON ?I
MICROPROCE3SOR
AND ASSOCIATED
L08\C AND MEMORY
f-
I
LOAD"
CELL
FIGURE 3
755
TLiH/5638-2
compensated for by the' closed loop action of the microprocessor. The sole requirement for these components is
that they be linear and have noise limits within the required
measurement precision. In this manner, the zero and gain
drifts of all active electronic components in the system are
eliminated, which considerably simplifies the selection and
design of these components.
A Schematic diagram of the sy$tem appears in Figure 4. For
purposes of clarity only, one load cell and its associated
multiplexer are shown. Details' of the 'microprocessor are
also not included. The LF11509 multiplexer feeds the
LM163 instrumentation amplifier. The LM163's output is
routed to the AID converter section which is composed of a
ramp generator (A1) and a preCision comparator circuit (A2A3). The output of the AID is a pulse width which varies with
the LM163's output amplitude. This pulse width is fed to the
microprocessor which uses it to gate a high speed clock. A
The gail} calibration resistor string inside the load cell allows
complete field interchangeability with no manual field calibration required. In practice, the load cell connector heads
are modified by the addition of the resistor string, temperature sensor and temperature sign pin strapping after the
cells have been purchased from the manufacturer. Connector types with the appropriate extra number of pins are substituted for the originals and the completed modified transducer is furnished as a unit to ,the end user. The stability of
this approach is entirely dependent on the resistors in the
gain calibration string. The voltage drive to the bridge need
not be stable because it is common to the gain calibration
string'and ratiometrically cancels. Low pass filtering of electrical and mechanical noise is achieved by displaying the
digitally-averaged value of a number of measurement cycles. It is worth noting that zero and gain drifts in the instrumentation amplifier and the AID converter are continuously
15¥
15¥
100
15¥
491k'
SYSTEII
SYNC PULSf
Uk
22k
15¥
.. - - - ,
1IODk*
I
"TARE
I
I
I
I
I
I
LOAD CElli
WEIGHT"'
5VO-O-'- '
I
lll3
-
I
I
I
I
MICIIOI'IIOCESSOR
AND SUI't'ORT LOGIC
TOMUX
lk
'I~J_
_
_
T£MPERATURl SIGN'
PIN STRAP INFORIIATIOII
TOM_OIl
TLlH/6~8-3
tTeflon
'Ultronlx 104A ratio match 0.005%.
"Ultronlx 104A, 0.01 % value shown Is Ideal for
precise 30 mV oU1pulload cell and must be
aelecled at load cell test.
FIGURE 4
756
used to turn off a high speed clock (trace F, Figure 5) which
was started at the beginning of the ramp (comparator-ramphigh speed clock detail shown in Figure 6). The waveforms
show that the number of high speed pulses which occur at
each multiplexer state varies with the LM163's output. Because the ramp is highly linear and the comparator very
stable, a direct relationship between the number of high
speed pulses and the LM163 output is assured. The final
computed answer at which the microprocessor controlled
loop arrives will nullify the effects of drift in the AID converter and instrumentation amplifier.
loop is completed by using the microprocessor to control
the LF11509 multiplexer address inputs. Operation of the
system is best understood by referring to Figure 5. Trace A
is a system synchronizing pulse which is generated by the
microprocessor. Trace B is the output of the LM163, which
is connected to the multiplexer. Each time the synchronizing
pulse goes low, the multiplexer advances one state. The
leftmost multiplexer state in the photograph is the zero signal. The next state is the gain calibration, which is followed
by the strain gage bridge output and then the temperature
signal. The next 4 multiplexer states repeat this pattern for
the other load cell. Each time the multiplexer changes state,
the LM 163 output is compared to the A 1 ramp generator
output (trace C) by the A2-A3 comparator. A2 acts as a preamplifier for the A3 comparator, insuring a low noise trip
point. When the ramp is very close to balancing the current
being pulled out of A2's summing junction by the LM163, A2
comes out of diode bound (trace D, Figure 5) and trips A3.
The rapid slewing, high level signal from A2 allows A3 to
have a noise free transition (trace E, Figure 5). This output is
In practice, this system has met specifications in the industrial environment for which it was designed. It furnishes a
good example of the type of intelligence which is becoming
typical in industrial measurement and control apparatus.
The interlocking of analog and digital techniques to solve a
difficult measurement problem will become even more common in future applications.
A=5V1DtV
A= lv/DIV (A2 OUTPUT)
B.1OV/OIV
C=10V/DIV
C=O.lV/DIV (Al DUTPUT)
D=2V/DiV
8=5V/DIV (A3 OUTPUT)
E=5OV/DiV
D=5v/DIV (GATED HIGH
SPEED CLOCK)
F=lDV/DiV
HORIZONTAL .. l pI/DIV
HORIZONTAL .. 1 ms/DtV*
TL/H/5638-5
TL/H/5838-4
'System operation normally occurs al a 2 Hz rate bul has baan sped up for
photographic convenience.
FIGURES
Details of comparalor-ramp-hlgh speed clock interaction:
When A2's outpul comes oul of bound (trace A), lhe A3 comparator responds with a clean, noise-free transltion (trace BJ, causlng the high speed
clock burst to cease (trace OJ. Trace C shows the ramp, greally expanded.
A2·A3 trip poinl occurs just after the ramp pass.. cenler seraen.
FIGURE 6
757
Industrial environments present a formidable challenge to
the electronic system desighEilr. In particular, high electrical
noise levels and often excessive common mode voltages
make safe, precise measurement difficult., One of the best
ways to Clvereome these problems is by the use of isolated
measurement, techniques. TypicallY"these approaches utilize transformers oropto isolators to galvanically isolate the
input terminals of the signal conditioning amplifier from its
output terminal. This breaks the common ground connection and eliminates noise and dangerous common mode
voltages. The conflicting requirements for good accuracy
and total input/output galvanic isolation requires unusual
circuit teChniques. A relatively simple isolated signal conditioner ap~ ,in Figure 1.
'aa,F
....
/
FLun••
llPUT
···rJ
National Semiconductor
Application Note 298
Isolati,onTechniques For'
Signal CQnditioning
-
l heH
points
.Hot"
MGTDI
-, TO .MPLIFIEI
'Iml
11U~.1M1
TO PI.II "HII.
TMaulCIT
TUH/5639-'
, AC,~INE FROM FULL WAVE BRIDGE,
J;IGURE 1A
bandwidth,extendll from1~Hz to~5kHz ± .25dB with the
- 3dB point beyond 85kHz. Risetime is about 10 microseconds: ..,Figu,,! '2 IIhows,the motonYaveiorm at the ground
referenced circuit output., The isolated, wideband response
of the clrcuit,pe~l1Iits safe monitoring of the fast rise SCR
turn-on
~el,a:~'hemojor"s;bIl!Sh nOi,se.
as
-!-
.l1li
OUTPUT=
INPUT +100
& ISOLATED
T1=UTC-#P2
A= .& VOLTIDIV
TL/H/5639~2
TO AC LINE FROM FULL WAVE BRlpGE
FIGURE 1
FLOATING INPUT HIGH VOLTAGE MOTOR MONITOR
In this inexpensive circuit, a wideband audio transformer
permits safe, ground referenced monitoring of a motor
which is powered directly from the 115VAC line. Figure 1A
details the measurement arrangement. The floating amplifier inputs are applied directly across the bruSh-type motor.
The 100k-1 Ok string, in combination with the transformer
ratio, provides a nominal 100:1 division in the observed motor voltage while simultaneously allowing a ground referenced output. The NE-2 bulb suppresses line transients
while the 10k potentiometer trims the circuit for a precise
100:1 scale factor. To calibrate the circuit, apply a 10-volt
RMS 1kHz sine wave to the floating inputs, and adjust the
potentiometer for 100 millivolts RMS output. Full power
IIOIIIZ = 5laJDlV
TL/H/5639-3
FIGURE 2
ISOLATED TEMPERATURE MEASUREMENT
Figure 3 shows a scheme which allows an LM135 temperature sensor to operate in a fully floating fashion. In this circuit, the LM311 puts out a 100 microsecond pulse at about
20Hz. This Signal biases the PNP transistor, whose collector
load is composed of the 1kO unit and the primary of T1. The
voltage that develops across T1 's primary (waveform A, Figure 4) will be directly dependent upon the value that the
LM135 temperature sensor clamps the secondary at. Wave- '
form B, Figure 4 details the transformer primary current.
758
.11i
·15
Uk
470
4J1c
IGII
I MIg
1II1II
-15
LIIIS
TEMI'UATURE IEISOR
T1
= TRWfI PC-SSG-32
*=1N41048
• = Nominal value. selecl at calibration.
":'
TL/H/5639-4
FIGURE 3
tion power in addition to their output signal. Some industrial
measurement situations require that the transducer must be
physically connected to a structure which is floating at a
high common mode voltage. This means that the signal
conditioning circuitry must supply fully floating drive to the
strain gauge bridge, while also providing isolated transducer
output signal amplification. Figure 5 details a way to accomplish this. Here, the strain bridge is excited by a transformer
which generates a pulse of servo-controlled amplitude. The
pulse is generated by storing the sampled amplitude of the
output pulse as a DC level, and supplying this information to
a feedback loop which controls the voltage applied to the
output switch. A2 functions as an oscillator which simultaneously drives 02-03 and the LF398 (A3) sample mode pin.
When A2's output pulse ends, A3's output is a DC level
equal to the amplitude of the output pulse which drives the
strain bridge. The dual secondary of T1 allows accurate
magnetic sampling of the strain bridge output pulse without
sacrificing electrical isolation. A3's output is compared to
the LH0070 10-volt reference by A4, whose output drives
01. 01's emitter provides the DC supply level to the 02-03
switch. This servo action forces the pulses applied to the
strain gauge transducer (waveform A, Figure 6) to be of
constant amplitude and equal to the 10-volt LH0070 reference output. Some amount of the pulse's energy is stored in
the 100"F capacitor and used to power the LM358 dual
(A 1) followers. These devices unload the output of the
transducer bridge and drive the primary of T2. T2's secondary output amplitude (waveform B, Figure 6) represents the
transducer output value. This potential is amplified by A5
and fed to A6, a sample-and-hold circuit. A6's sample command is a shortened version of the A2 oscillator pulse. The
74C221 generates this pulse (waveform C, Figure 6).
This voltage value, of course, varies with the temperature of
the LM135 in accordance with its normal mode of operation.
The LF398 sample-and-hold IC is used to sample the transformer primary voltage and presents the circuit output as a
DC level. The 100 pF-39k-1MO combination presents a trigger pulse (waveform C, Figure 4) to the LF398, so that the
sampling period does not finish until well after the LM135
has settled. The LM340 12-volt regulator provides power
supply rejection for the circuit. To calibrate, replace the
LM135 with an LM336 2.5-volt diode of known breakdown
potential. Next, select the 1kO valve until the circuit output
is the same as the LM336 breakdown voltage. Replace the
LM336 with the LM135 and the circuit is ready for use.
A = IiVIIIV
I = IOiIAIIIIV
C= IiVIIIV
mz • 2IIs4IIIIV
FIGURE 4
TLiH/5639-5
FULLY ISOLATED PRESSURE TRANSDUCER
MEASUREMENT
Strain gauge-based transducers present special difficulties
if total isolation from ground is required. They need excita-
759
FIGURES
760
625) in place of the transducer and dial in the respective
values for zero and full-scale output (which are normally
supplied with the individual transducer). Adjust the circuit
"zero" and "gain" potentiometers until a 0- to 10-volt output
corresponds to a 0 to 1000psi pressure input.
Aa 2GViDIv
• = IIIVIDIV
1.5-VOLT POWERED ISOLATED PRESSURE
MEASUREMENT
Figure 7 diagrams another pressure measurement circuit.
e = 2IIV1DIV
This circuit presents a frequency output which is fully isolated by the transformer indicated. The entire circuit may be
powered from a 1.5-volt supply, which may be derived from
a battery or solar cells. The potentiometer output of the
pressure transducer used is fed to a voltage-to-frequency
converter circuit. In this V-f circuit, an LM10 op amp acts as
an input amplifier, and forces the collector current of 01 to
be linearly proportional to VIN for a range of 0 to +400
millivolts. Likewise, the reference amplifier of the LM10
causes 02's output current to be stable and constant under
all conditions. The transistors 03-010 form a relaxation oscillator, and every time the voltage across C1 reaches
az = 11II,.81D1V
TL/H/5639-7
FIGURE 6
Because the A6 sample command falls during the settled
section of T2's output pulse, A6's output will be a DC representation of the amplified strain gauge pressure transducer
output. The LH0070 output may be used to ratiometrically
reference a monitoring AID converter. To calibrate this circuit, insert a strain bridge substitution box (e.g., BLH model
-I."
+1.&
.....
"'"
1M
.111
.%
II
.....
"
,,•
,,
,
..-:,'
,
.',,
,,
,
"
L_____ '__
,.e.
--f>o = II8MM14C240 '"'"""
QI = Q5 Each 1/5 LM3046
Q8 = Q1' Each 2N3EQ\ or 2N2II07
012 = 2N3904 or any NPN lIIicon
AI.LM1OCLH_apamp
TI = TAWIl f'C.SSO-32
• Praseurelransducer
-...
....,.lit
...,.
••.%
.....IT
~UT
'"
"
'111
.,..
Gianntnicontrols
D-15PS1A-1kn
TLlH/5639-8
FIGURE?
761
O.,S-volt, 06 is comman!l~ to reset,it to zero yolts differential. This basic circuit is not normally considered a 'very accurate technique, because the dead time, while 06 is saturated, will qaLlse a large (1 %) nonlinearity in the V-to-F
transfer curve. However, the addition ,of Rx causes,the reference current flowing through 02 to include a term which is
linearly proportional to the signal, which corrects the trans:
'
fer nonlinearity.
FULLY ISO~TEQ "ZERO POWER" ,COMPLETE AID
CONVERTER
'
AgUf'8 8 shoWs a complete 8-bit AID converter, which has
all input anc! output lines fully f10llting from system ground.
In addition,the AID converter requires no power supply for
operatiori! Circuit operation is initiated by applying a convel1..oommand pulse to the "convert-command" input (trace
A"F/{/uf8 9B).' This pulse simultaneously 'forces the "Data
Output" line low (trace 8, Figuf8 9B)and propagates across
the isolation transformer. The pulse appears at the transformer secondary (Figuf8 9A, trace A)' and charges the 100
p.F ,capacitor to five volts. This potential is used to supply
power to the floating AID cC)Aversion circuitry. The pulse
appearing at the transformer secondary is also used to start
the AID conversion by biasing comparitor A's negative Input
low. This causes comparitor A's output to go low, discharging the .06p.F capacitor (waveform 8, Figuf8 9A). Simultanepusly, the 10ktiz oscillator (AgurB 9A, trace D), formed by
The NSC MM14C240 inverters are employed because this
Ie has the only uncommitted inverters with such a low (0.6
to 0.8V) threshold that they can operate on a supply as low
as 1.2 volts.
The 49.9k resistors which feed into 02'8 emitter act as a
gain tempco trim, as 012's Vbe is used as a tempEjrat\lre
sensor. If the output frequency is 100ppm/C too fast/hot,
you can cut the resistor to 20k. If f is too slow Ihot, add more
resistance in series with the 49.9k. Total current drain for
this circuit is about 1 milliampere.
1I11III
..
INPUT 0- 3 vIm
LMI.
1I11III
1I11III
.&
DATA
OUTPUT
Tranaformer = UTCII ~
A. B. C. 0
= LM339 Quad
All NPN = 2N2222A
TO ALL ".6"
FLOATINS POINTI
-.... =IN4148
TUH/5639-9
FIGURE 8
762
comparator D and its associated components, is forced off
via the 22k diode path. A second diode path also forces
comparator D's output low (Figure 9A, trace E). Note the
cessation of oscillation during the time the convert command pulse is high. When the convert command pulse falls,
the 01-02 current source begins to charge the .06 /A-F capaCitor. During this time, the 10kHz comparator C oscillator
runs, and comparator D's output is a stream of 10 kc clock
pulses. When the ramp (trace B, Figure 9A) across the .06
/A-F capacitor exceeds the circuit input voltage, comparator
B's output goes high (trace C, Figure 9A), forcing comparator D's output low. The number of pulses which appeared at
comparator D's output is directly proportional to the value of
the circuit's input voltage. These pulses are amplified by the
two NPN transistors which are used to modulate the data
pulse stream back across the transformer. The six series
diodes insure that the modulated data does not appear at
comparator A's input and trigger it. The pulses appear at the
primary (Figure 98, trace A) as small amplitude spikes and
are then amplified by the data output transistor, whose collector waveform is trace B or Figure 98. In this example a 0to 3-volt input produces 0- to 300 pulses at the output. The
22k diode path averts a + 1 count uncertainty error by synchronizing the 10kHz clock to the conversion sequence at
the beginning of each conversion. The 500k potentiometer
in the current source adjusts the scale factor. The circuit
drifts less than 1LSB over 25·C ± 20·C and requires 45 milliseconds to complete a full scale 300 count conversion.
COMPLETE, FLOATING MULTIPLEXED THERMOCOUPLE TEMPERATURE MEASUREMENT
Figure 10 shows a complete, fully floating multiplexed thermocouple measurement system. Power to the floating system is supplied via T2, which runs in a self oscillating DC-DC
converter configuration with the 2N2219 transistors. T2's
output is rectified, filtered, and regulated to ± 15 volts. An
eight channel LF13509 multiplexer is used to sequentially
switch 7 inputs and a ground reference into the LMll amplifier. The LMll provides gain and cold junction compensation for the thermocouples. The multiplexer is switched from
the 74C93 counter, which is serially addressed via the 4N28
opto isolator. The ground referenced channel prevents
monitoring instrumentation from losing track of the multiplexer state. The LM11 's output is fed into a unity gain isolation amplifier. Oscillator drive for the isolation amplifier is
derived by dividing down T2's pulsed output, and shaping
the 74C90's output with A4 and its associated components.
This scheme also prevents unwanted interaction between
the T2 DC-DC converter and the isolation amplifier. This
circuit, similar to the servo-controlled amplitude pulser described in Figure 5, puts a pulse across Tl's primary. The
, amplitude of the pulse is directly dependent on the LM11 's
output value. Tl 's secondary receives the pulse and feeds
into an LF398 sample-hold-amplifier. The LF398 is supplied
with a delayed trigger pulse, so that Tl 's output is sampled
well after settling occurs. The LF398 output equals the value of the LM11. In this fashion, the fully floating thermocouple information may be connected to grounded test equipment or computers. Effective cold-junction compensation
results when the thermocouple leads and the LM335 are
held isothermal. To calibrate the circuit, first adjust R3 for an
LMll gain of 245.7. Next, short the "+" input of the LMll
and the LM329 to floating common, and adjust Rl so that
the circuit output is 2.982 volts at 25·C. Then, remove the
short across the LM329 and adjust R2 for a circuit output of
246 millivolts at 25°C. Finally, remove the short at the LM11
input, and the circuit is ready for use.
A = 5VJDIV
B = ZVIOIV
C = 5V1DIV
D= 5VJDlV
E = 5V1DIV
IIOIIZ = 5llal1IIV
l't/H/5639-10
A = lDVIDIV
B = 5V1DIV
IIIIRIZ = l-.1DIV
TL/H/5639-11
FIGURE 9
763
AN-298
-.1
Lf.._
••
.0Il
••
••
..........
~
~
.....
•
.•
,)
~IIZ
•
....
~
_+11
L.1lI
*
" , =FlOAT'NG COMMON
=GROUND
T2 - PlCO ELECTRON'CS 31080
TI- UTe #pc - SSO - 32
*=.N4148
- = 1'!1. RN60 FILM RES.STOR
- = Al-A4 = LF347 QUAD
-15
.11
111fT
~I
S
c:
ca•••11
:a
m
....
CI
...
.-. - r"
...
••
TLlH/5639-12
Audio Applications of
Linear Integrated Circuits
National Semiconductor
Application Note 299
Although operational amplifiers and other linear ICs have
been applied as audio amplifiers, relatively little documentation has appeared for other audio applications. In fact, a
wide variety of studio and industrial audio areas can be
served by existing linear devices. The stringent demands of
audio requirements often mean that unusual circuit configurations must be used to satisfy a requirement. By combining
off-the-shelf linear devices with thoughtful circuit designs,
low cost, high performance solutions are achievable. An example appears in Figure 1.
Although this method works well, it requires careful attention to temperature compensation to achieve good results.
Figure 1 shows a circuit which eliminates all temperature
compensation requirements. In this circuit, the current into
AI's summing junction is exponentially related to the circuit
input voltage because of the logarithmic relationship between 01 's VBE and its collector current. AI's output integrates negatively until the 02-05 pair comes on and resets
Al back to OV. Note that opposing junction tempcos in 02
and 05 provide a temperature compensated switching
threshold with a small (100 ppml'C) drift. The -120
ppm/'C drift of the polystyrene integrating capaCitor effectively cancels this residual term. In this fashion, AI's output
provides the sawtooth frequency output. The LM329 reference stabilizes the 05-02 firing point and also fixes 01 's
collector bias. The 3k reSistor establishes a 20 Hz output
frequency for OV input, while the 10.5k unit trims the gain to
1V in per octave frequency doubling out. Exponential conformity is within 0.25% from 20 Hz to 15 kHz.
EXPONENTIAL V-F CONVERTER
Studio-type music synthesizers require an exponentially responding V-F converter with a typical scale factor of 1V in
per octave of frequency output. Exponential conformity requirements must be within 0.5% from 20 Hz-15 kHz. Almost all existing designs utilize the logarithmic relationship
between VBE and collector current in a transistor.
INPUT
10.5k*
> .........----1k> ) SAWTOOTH OUTPUT
250*
r
3k*
600*
LM329
15Y
15Y
Uk
03"',
10k
330
I
1
1
331
1
1
1
I
'I % rnetallilm resistor
tPolystyrene
= 2N2222A
= 2N2907A
AI, A2 = LF412 dual
01, 03, 04, 06 = LM3046 array
02
05
I
I
~----------+-------~-~
FIGURE 1
765
TL/H17498-1
.'The 1M-1.2k divider at A 1's " +'," input, achieves first order
C9mpensation for Q1 's bulk emitter resistance, aiding expo'nential conformity at high frequencies. A2 and its associated
comPQnel)ts are used to "brute-force" stabilize Q1 's operating' point. Here, Q3, Q4 and A2 form a temperature-control
loop that thermally stabilizes the LM3046 array, of which Q1
is a part. Q4's VBE senses array temperature while Q3 acts
as the chip's heater. A2. provides servo gain, forcing Q4's
VBE'to equal the servo'temperature selpoint established by
the 1Ok-1 k string. Bias stabilization comes from the LM329.
The
clamp and the 330 emitter resistor determine the
maximum power Q3 can dissipate and also prevent servo
lock-up during circuit start-up. Q1, operating in this tightly
controlled environment, is thus immune from effects of ambient temperature shift.
of A3 al9ng with Q1 ,and Q2.,A1 and, A2 provide buffered
inputs. The - 65' dB fa8dthrough figure is' typical ,for this
type of multipli~r: A5 an~ A6 are ,l!,sed to fut1/Jer red,!ce this
feedthrough figure to ~'84dB at 20 kHzby'a nulling technique. Here, the circuit's audio input is inverted by A5 and
then summed at A6 with the main gain control output, which
comes from A4. The RC networks at A5's input provide
phase shift and frequency response characteristios which
are the 'same as the main 'gain cantrol multipliers feedthrough characteristics. The amount of feedthrough compensation Is adjusted with the 50k potentiometer. In this
way, 'the" feedthrough components (and only'the feedthrough-components) are nulled 'out and do not appear at
, A6's output. From 20 Hz to 20 kHz, feedthrough is'less than
-80 dB.. Distortion is inside 0.05%, with a fUll power bandwidth of 60'kHz. To adjuilt this circuit, apply a 20 Vp-p sine
wave at the audio Input and ground the gain control input.
Adjust the 5k coarse feed~hrougll trim for, minimum output at
A4. Next, adjust the 50k fine feedthrough trim for minimum
output at A6. For best performance, this circuit must be rigidly constructed and enclosed in Ii fully shieided box with
attention give to standard low noise grounding 'techniques.
Figure 3 sh,ows the typical temaining feedthrough at 20 kHz
for a 20 Vp-p input. Note that the feedthrough is at least
-80 dB down and' almost' obscured by the citcuit noise
floor.
as
ULTRA-LOW FEEDTHROUGH VOLTAGEoCONTROLLED
AMPLIFIER
A common studio requirement is a voltage-controlled gain
amplifier. For recording purposes, it is desirable that, when
the gain control channel is brought to OV, the signal input
feedthrough be as low as possible. Standard configurations
use analog multipliers to achieve the voltage-controlled gain
function. In Figure 2, A1-A4, along wilh Q1-Q3, comprise
such a multiplier, which achieves about -65 dB of feedthrough suppression at 10kHz. In this' arrangement, A4 single ends a transconductance type multiplier composed
5k
COARSE
15'
FEEDTHROUGH ,TIIIM
3 pF
*lN4148
'1 % film resistor
A1-A2, A3-M, A5-AS = LF412 duals
01-02 = LM394 dual,S
FEEDTHROUUH
COMPENSATION
CIRCUITRY
TLlHI7496-2
FIGURE 2
766
A=1DV/DIV
8=5 mY/DIV
HDRIZDNTAL=50 ,.a/DIV
TL/H/7496-3
FIGURE 3
1.2k
>--....-4_....~~OUTPUT
Frequency
INPUT (Ol~....-f
<0.002
<0.002
<0.002
<0.002
<0.002
100
<0.002
<0.002
<0.002
<0.002
<0.002
1000
<0.002
<0.002
<0.002
<0.002
<0.002
10000
<0.002
<0.002
<0.002
<0.0025
<0.003
20000
<0.002
<0.002
<0.004
<0.004
<0.007
0.03
0.1
0.3
1.0
5.0
Output
Amplitude
(Vrms)
*TRW-MAR-6 resistor
Total Harmonic Distortion
20
-15V
TUH17496-4
FIGURE 4
ULTRA·LOW NOISE RIAA PREAMPLIFIER
than 2 dB when the amplifier is used with standard phono
cartridges, which have an equivalent wideband (20 kHz)
noise of 0.7 J£V. Further improvements in amplifier noise
characteristics would be of little use because of the noise
generated by the cartridge itself. A speCial test was performed to check for tranSient intermodulation distortion.
10kHz and 11 kHz were mixed 1: 1 at the input to give an
rms output voltage of 2V (input = 200 mY). The resulting
1 kHz intermodulation product measured at the output was
80 J£V. This calculates to 0.0004% distortion, quite a low
level, considering that the 1 kHz has 14 dB (5:1) gain with
respect to the 10 kHz signal in an RIAA circuit. Of special
interest also is the use of all DC coupling. This eliminates
the overload recovery problems associated with coupling
and bypass capaCitors. Worst-case DC output offset voltage
is about 1V with a cartridge having 1 kO DC resistance.
In Figure 4, an LM394 is used to replace the input stage of
an LM118 high speed operational amplifier to create an ultra-low distortion, low noise RIAA-equalized phono preamplifier_ The internal input stage of the LM118 is shut off by
tying the unused input to the negative supply_ This allows
the LM394 to be used in place of the internal input stage,
avoiding the loop stability problems created when extra
stages are added_ The stability problem is especially critical
in an RIAA circuit where 100% feedback is used at high
frequencies_ Performance of this circuit exceeds the ability
of most test equipment to measure it. As shown in the accompanying chart, harmonic distortion is below the measurable 0.002% level over most of the operating frequency and
amplitude range. Noise referred to a 10 mV input signal is
-90 dB down, measuring 0.55 J£Vrms and 70 pArms in a
20 kHz bandwidth. More importantly, the noise figure is less
767
MICROPHONE PREAMPLIFIER
Figure 5 shows a microphone preamPlifi~i'~hiCh'\runs from" ,
a single 1.5V cell and can be located right iitthll llj1ic(O"'"
phone. Although the LM10 amplifier,refereneecombirijlfiorl
has relatively slow frequency response; performance can be
considerably improved by cascading ttie artlp.lifierar'td refer·'
enca amplifier together to form a sin!ll~ 6verall audio ampli·
fier. The reference, with a 500 kHz URity-gairibaridwidth, is
used as a preamplifier with a gain of .100. Its output is fed
through a gain control potentiometer to the op amp, which is "
connected for a gain of 10. The co!'ibinatiO~ giv~'a,,60 dB
gain with a 10kHz bandwidth, unloaded, and 5 icHz, loaded '
with 5000. Input impedance is 10k(1.
3M
1.5V
1.SV
8.2M
4.7
+
~OU1PUT
6.2M
1M
R&
0.47
~"""'\f\lOk.,.,.....
111Of1
GAIN
1M
R8
SET
'---"
Lt:n\ MICROPHONE
I
potel)tially, ul!ing the reference as a preamplifier in this
"fashion can cause excess noise. However, because the ref·
etence voltage is low, the noise contribution which adds
root~meail·square, is likewise low. The input noise voltage in
, this, connection is '40 nV - 50 nVI VHz, approximately equal
to ·that of the op amp.
,One. pointtci observe with this connection is that the signal
,sWing at, the·.reference output is strictly limited. It cannot
swing much !;lelow 150 mV, nor closer than 800 mV to the
supply. Further, the bias current at the reference feedback
terllj1in,allow~rs the output quiescent level and generates an
uncertainty' in "this level. These facts limit the maximum
feedback r,esistance (R5) and require that R6 be used to
optimize', tJ;je quiescent operating voltage on the output.
Even so, ona'must consider the fact that limited swing on
the preamplifier can reduce maximum output power with low
settings on the gain control.
In this design, no DC current flows in the gain control. This
is perhaps an arbitrary rule, designed to insure long life with
noise-free operation. If violations of this rule are acceptable,
R5 can be used as the gain control with only the bias cur·
rent for the reference amplifier ( <75 nA) flowing through the
wiper. This siniplifies the circuit and gives rilore leeway in
getting sufficie~t output swing from the preamplifier.
DIGITALLY PROGRAMMABLEPANNER-ATTENUATOR
Figure 6 shows a Simple, effective way to use a multiplying
CMOS D-A converter ,t.o steer or pan an audio signal between two channels. In this circuit, the current outputs of the
DAC1020, which are complementary, each ,feed a current·
to·voltage amplifier. The amplifiers will have complementary
voltage outputs, the amplitude of which will depend upon
'f'INPUT
I
I
I
V
TL/HI7496~5
FIGURES
FEEDBACK
NC
15k*
INPUT
*1% film resistor
A1, A2
= t.F4\2 dual
TL/Hi7496-6
FIGURE 6
768
the address code to the DAC's digital inputs. Figure 7 shows
the amplifier outputs for a ramp-count code applied to the
DAC digital inputs. The 1.5 kHz input appears in complementary amplitude-modulated form at the amplifier outputs.
The normal feedback connection to the DAC is not used in
this circuit. The use of discrete feedback resistors facilitates
gain matching in the output channels, although each amplifier will have a z 300 ppm/DC gain drift due to mismatch
between the internal DAC ladder resistors and the discrete
feedback resistors. In almost all cases, this small error is
acceptable, although two DACs digitally addressed in complementary fashion could be used to totally eliminate gain
error.
is to control cut-off frequency by controlling the gain of the
A3-A6 Integrators, which has the effect of varying the integrators' capacitors. A1-A3 and their associated DAC1020
form a filter whose high-pass output is taken at A 1 and fed
to an identical circuit composed of A4-A6 and another
DAC. The output of A6 is a low-pass function and the final
circuit output. The respective high-pass and low-pass cut-off
frequencies are programmed with the DAC's digital inputs.
For the component values shown, the audio range is covered.
REFERENCES
Application Guide to CMOS Multiplying D-A Converters, Analog Devices, Inc. 1978
DIGITALLY PROGRAMMABLE BANDPASS FILTER
Figure 8 shows a way to construct a digitally programmable
first order bandpass filter. The multiplying DAC's function
A=5V/DIV
8=5V/DIV
HORIZONTAL"l ml/DIV
TL/H/7496-7
FIGURE 7
lOll
INPUT
> ....-f(») DUTPUT
Al, A2
A3, A4
A5, A6
= LF412 dual
= LF412 dual
= LF412 dual
TLlHI7496-8
FIGURE 8
769
~ Simple Circuit Detects l-oss
< of 4-20 rnA Sign~1
z•
Four-to-twenty milliampere current loops are commonly
used in the process control· industry. They take advantage
of the fact that a remote amplifier can be powered by the
same 4-20 rnA current that it controls as its output Signal,
thus using a single pair of wires for Signal and power. Circuits for making 4-20 rnA transmitters are found· in the
LM10, LM163, and LH0045 data sheets.
In general, an expensive isolation amplifier would be required to detect the case of a 4 rnA signal falling out of spec
(e.g., 3.7 rnA) without degrading the isolation of the 4-20 rnA
current loop.
But this new circuit (Figure 1) can detect a loss or degradation of signal below 4 rnA, with simplicity and. low cost. The
LM10 contains a stable reference at pins 1 and 8, 2qo rTiV
positive referred to pin 4. As long as the loop current is
larger than 4 rnA, the I x R drop across the 47.60 resistor,
R4, is sufficient to pull the LM10's amplifier ·input (pin 2)
below pin 3 and keep its output (pin 6) turned OFF.
The 4-20 mA current will flow through the LED in the.optoiso;
1.4 mATO. 20 riI~
,HIGH·.
R2
National Semiconductor
Application Note 300
Robert A. Pease .
lator and provide a LOWoutput at pin 5 of theoptoisolator.
When the current loop falls below 3.7 mA, the LM10's input
at pin 2 will rise and cause the pin 6 output to fall and steal
all the current away from the LED in the optoisolator. Pin 5
of the 4N28 will rise to signify a fault condition. This fault
flag will fly for any loop current between 3.7 rnA and 0.0 rnA
(and also in case of reversal or open-circuit). R1 is used to
trim the threshold point to the desired value. CR2 is added
in series with the LED to make sure it will tum OFF when the
LM10's output goes LOW. (While the LM10 is guaranteed to
saturate to 1.2V, the forward drop of the LED in the 4N28
may be as low as 1.0V, so a diode is added in series with
the LED, to insure that it can be shut off.) Note that most
operational amplifiers will not respond in a reasonable way if
the output pin (6) is connected to the positive supply pin (7),
but the LM10 was specifically designed and Is specified to
perform accurately In this "shunt" mode. (Refer to AN-211
application note,. TP-14 technical paper, and the LM10 data
sheet.).
47k
.
""--'.....~~_y3
2k
1%
OUTPUT
R3
2k
1%
R4
CRI
47.6
1%
II
•
IODDV
ISOLATION
LOW
FLOATING
OUTPUT
FAULT
DETECTOR
DETECTOR
=
CRI 1N4001, opllonal, In case of signal reversal
LM10= NSC LM10CLN or LM10CLH amp/reference
IC2 = 4N28 or sl",lIar, oPlolsolalor
V2 = Normally low; high signifies faull (I < 3.7 mAl
V3 = Normally high; low signifies faull (1<3.7 mAHbuffered Oulpul)
'C1 = 1 .F opllonal, 10 avoid false OUlpul when large AC currenlls superimposed on 4.0 mAo
Dlsconnecllhla capacllor when using wllh circuil of Figure 2.
1/6 MM74C04 or similar, CMOS inverter
.
1>0 =
Tl/H/S640-1
FIGURE 1. Current Loop Fault Detector
770
.-----------------------~----------------------------~>
While you could manually adjust R1 while observing the
status of V3 output, this would be a coarse and awkward
trim procedure. Figure 2 shows an improved test circuit
which servos the current through the detector circuit, forcing
it to be at the threshold value. Then that current can be
monitored continuously, and the circuit can be trimmed easily. If the current through R107 starts out too small, the output of the 4N28 will be HIGH too much of the time, and the
op amp output will integrate upwards until the current is at
the actual threshold of the detector. The integrator's output
will stop at the value where the duty cycle ofthe4N28 out-
put is exactly 50%. This occurs when the current through
R107 is straddling the threshold value.
The positive feedback via R108 assures that the loop oscillates at approximately 50 cycles per second, with a small,
well-controlled sawtooth wave at its output. This mode of
operation was chosen to insure that the loop does not oscillate at some high, uncontrolled frequency, as it would be
difficult in that case to be sure the duty cycle was exactly
50%. This test circuit is advantageous, because you can
measure the trip pOint directly.
15Voc
R1D2
2k
R1D1
2k
r---I
I
R1D5
lOOk
t-....-....,
I
I
I
I
I
':"' I
I
DETECTOR
CIRCUIT
FROM FIGURES
lOR 3
I
L __
II
,
---.J
~LOW;;';"'_-_-_----___+ __ ~~~':E
R1D7
100
1%
15Voc
R111
1.5M
Rl09
10k
1%
Rl0a
150k
R110
10k
1%
Al0l
=LM308 or similar
1>0 = 1/6 MM74C04 or Similar, CMOS Inverter
Ql0l =2N2907 or similar, PNP
FIGURE 2. Test Circuit for Threshold Detector
771
TL/H/5640-2
z
W
g
The test circuit of Figurs 2 is necessary for trimming the
detector in Figurs 3. This circuit does not· have a trim pot,
and thus avoids the problem of someone mis-adjusting the
circuit after .it is once trimmed correctly. It also avoids the
compromises between good but expensive trim pots and
cheap but unreliable, drifty trim pots. By opening one or
more of the links, L1-L4, according to the following procedure, it is easy to trim the threshold I~vel to be within 1% of
3.70 mA (or as desired).
• If ITHRESHOLD is larger than 3.760 mA, open link L3;
-if not, don't
• Then, if ITHRESHOLD is larger than 3.720 mA, open link
L4;-if not, don't
.'
.
,
This procedure provides a circuit trimmed to much better
than 1% of 3.70 mA, without uSing any trim pots. Of course,
this circuit can be used to detect drop-out of regulation of
other floating signals,while maintaining high isolation from
ground, good accuracy, low power dissipation (2 mA x 2.5V
typical)·and low cost.
Other standard values of current loop are 1 mA-5 mA and
10 mA-50 mAo The version shown in Figurs 4 uses higher
resistance values to trip at 0.85 mAo The circuit in Figurs 5
has an additional transistor, to accommodate currents as
large as 50 mA without damage or loss of accuracy, and
provide an 8.5 mA threshold.
• Observe the DC current through R107 in Figurs 2
• If ITHRESHOLD is larger than 3.950 mA, open link L1;
-if not, don't
• If ITHRESHOLD is larger than 3.830 mA, open link L2;
-if not, don't
Ll
R301
75
R302
14 mA-20mA
,HIGH
39
+Va
47k
_-fol'-_~OUTPUT
R305
lk
1%
R306
lk
1%
.
=
=
Al LM10CLN or LM10CLH
IC2 4N28 or Similar, optolsolator
LOW
FLOATING DETECTOR
TL/H/5640-3
FIGURE 3. Fault Detector wHh Low-Cost Trim Scheme
(To be trimmed In the circuit of Figure 2)
I 1 mA-5 mA
, HIGH
Rl
2k
R2
10k
1%
5V
R5
220k
r---f'-NC
_--t-li-..._"'-[>cl_OUTPIIT
R3
10k
1%
.
. VREF R3+R4
ITHRESHOLD = "R4' Rl + R2
ICI = LM10CLN or LM10CLH
IC2 4N27 or 4N28 or similar
= 118 MM74C04 or similar, CMOS Inverter
VREF = 200 mV:I: 5%, pins 1 and 8 referred to pin 4
When trimming this circuit with the circuit of Figure 2,
use Rl01 = Rl02 =8.2 kO
=
1>0
LOW
TL/H/5640-4
FIGURE 4. Current Loop Fault Detector
(lTHRESHOLD = 0.85 mA for 1 mA-5 mA Current Loops)
772
1,0mA-50mA
'HIGH
CRI
IN4001
R2
5V
2k
1%
/-f'I--"'--+-o~-OUTPUT
CH2
IN4oo1
R3
2k
1%
R4
21.0
1%
LOW
VREF
-ITHRESHOLD =
R3+R4
R4". 'Fi1"+R2
ICI = LM10CLH or LM10CLN op amp and reference
VREF=200 mV:t5O/O, plnll andS referred 10 pin 4
IC2 =4N28 or similar, optolsolator
1>0 = 1/6 MM74C04 or Ilmllar, CMOS Inverter
QI - 2N2804 or 2N2807, any Illicon PNP
When trimming this circuit with the circuit of Figure 2,
use RIO! = RI02 = 82011
TL/H/5640-5
FIGURE 5. Current Loop Fault Detector
(ITHRESHOLD = 8.5 mA, for 10 mA-50 mA Current Loops)
773
Signal Conditioning for
Sophisticated Transducers
National Semiconductor
Application Note 301
A substantial amount of information is available on signal
conditioning for common transducers. Fortunately, most of
these devices, which are used to sense common physical
parameters, are relatively easy to signal condition. Further,
most transducer-based measurement requirements are well
served by standard transducers and signal conditioning
techniques.
'
their capabilitie's amI what is required to signal condition
them. The circuits stiown are i~endet1 as iQstructive exampies only, although ,each one has been constructed and
tested: :Every individual transducer application has a set of
speCifications and constraints which will require modification or revision of the circuits presi!nted. Sources of additional information which feature more vigorous treatment
are presented in a reference section at the end of the application note.
'
Some situations, however, require sophisticated "~ransduc- '
tion techniques with their attendant special signal conditipn:
ing requirements. This application note details signalconditioning and applications information for diverse' group of
sophisticated and unusual tranducers. Because ,these devices are unusual or somewhat difficult to. signal condition,
relatively little material has appeared on how to design circuitry for them. Many of these devices permit measurements which cannot be accomplished in any other way. For
this reason it is worthwhile to have a basic familiarity with
a
PHOTOMULTIPLIER TUBE (PMn
Perhaps the most versatile 'ligl1t detector ava;lable is the
photomultiplier tube (PMn. These sensors allow single photon detection, sub-nanosecond':r,se time, pandwidths approaching 1 GHz and linearity of response over a range of
107. In addition, they feature extremely low noise, stable
characteristics and very long life. Figure 1a details a typical
-1000V0L18
ZlV
10k
ImIDIIEI
10M
TYPICAL
IIALIIEB
ll11111pF-_pF
L~
Uk
-15V
LMIIZII
111 LF412
IIIc
01, 02. 04 = 2N3054
03, 05 = 2N2222A
...... =IN4007
R=500k
11IL
">.....-{<») OUTPUT
T1 = Pulse Engineering PE/6197
FIGURE 18
TL/H/5641-1
PMT along with a signal conditioning circuit. The tube is
composed of a photosensitive cathode, an anode, a focusing electrode and ten dynode stages. In operation, the photocathode, which is high voltage biased with respect to the
dynodes, emits photoelectrons when it is struck by light.
These are focused into a beam and directed to the first
dynode stage by the focus electrode. These arriving electrons impinge on the dynode, causing secondary emission
to occur. As a result, a greater number of electrons leave
the dynode and are then directed to the second dynode. In
this fashion, a number (e.g.,10) of dynode stages are used
to achieve overall gains of 1()6 to 108. The electrons from
the final dynode are collected by the anode, which provides
the output current of the tube. In contrast to other vacuum
tubes, the PMT does not use a filament to thermionically
generate electrons. Instead, the photocathode, in combination with incident light, initiates the electrons. The absence
of a filament means there are no degradation, heat or outgassing problems and the life of a PMT is very long.
light produced by an LED. This photo was taken with a high
speed PMT which was terminated directly into a 1 GHz
bandwidth, 50.11 sampling oscilloscope.
Another PMT application exchanges speed for sensitivity in
a nuclear medical instrument, the Gamma camera.
The Gamma camera operates by using the scintillation
properties of special crystals which are placed in front of an
array of PMTs. Small quantities of radioactive isotopes are
introduced into the patient either by oral ingestion or injection. Specific isotopes collect at certain organs within the
body. As the radioactive isotopes decay, gamma rays are
emitted from the isotope concentration area. These rays are
collimated by a lead plate containing many small holes
which forms the front of the camera (Figure 2a). This collimator allows only those rays which are at right angles to
pass through the plate. The rest are absorbed in the lead. In
this fashion the geometric shape of the gamma source is
preserved and is presented to the scintillation crystal. The
array of PMTs is located behind the crystal. The individual
tubes respond to any given scintillation anywhere in the
crystal with a distribution of signal strengths. This distribution is used by a processor to determine the precise point of
scintillation in the crystal. Each of these scantillation locations is recorded on a CRT. After a length of time, this
counting-integration process produces a picture of the organ on the CRT. Figure 2b shows 7 such pictures of a pair
of human lungs, taken 30 seconds apart over a 150 second
period. In photo A, the administered radioactive isotope begins to collect in the lungs. In photo B, the lungs are saturated. During photos C, 0, E, F and G, the isotope progressively decays. Normally, human lungs will clear after 120 seconds. This particular sequence shows evidence of an obstructive pulmonary disease which is most pronounced in
the lower right lung.
Signal conditioning involves generating a stable high voltage supply and accomplishing a low noise current-to-voltage conversion at the anode. In this example, a DC-DC converter is used to supply the dynode potentials to the tube.
The supply is stabilized by the LF412 amplifier which drives
the 03-05 combination to complete a feedback loop around
the 01-02 driven transformer. The LM329 provides a stable
servo reference. In general, the regulation of a PMT supply
should be at least ten times greater than the required measurement gain stability because of the relationship between
a PMT's gain slope and the high voltage applied. The cathode and dynodes are biased from the high voltage supply
via divider resistors. The resistors distribute the dynode potentials in proportion to a ratio which is specified for each
tube type. To prevent non-linear response, the current
through the divider string should be at least ten times the
maximum expected current out of the tube. Some high
speed pulse applications can generate transient high tube
currents which may require the small capacitors shown in
dashed lines. The anode is the tube output and appears as
an almost ideal current source. The LF412 amplifier performs a current-to-voltage conversion with the 1 Mn resistor setting the output scale factor.
OF PMTI
LIGHT
The PMT's combination of high speed and extreme sensitivity suits it to a variety of difficult light measurement chores.
The remarkable photograph of Figure 1b shows the actual
rise and fall time characteristics (inverted) of a fast pulse of
------------
GAMMA RAYS NOT AliGNEO WITH
HOLES ARE BLOCKED
------------
GAMMA RAYS ALIGNED WITH
HOLES GO THROUGH LEAD SHIELD
TLlH/5641-3
FIGURE2a
PYROELECTRIC DETECTOR
The pyroelectric detector represents another class of sophisticated photodatector. These ceramic-based radiation
detectors feature an extraordinary light sensitivity range
from microwatts to watts with excellent linearity. Their bandwidth is flat from the ultraviolet to the far infrared. Response
is sub-nanosecond and the devices may be operated at
room temperature; no cooling is required. A major difficulty
and source of confusion with signal conditioning pyroelectrics is that they do not respond at DC. This limitation, which
is in keeping with all ceramic-based transducers, is surmounted by using a light chopper in front of the detector. In
this fashion, DC light inputs to the detector appear as a
modulated carrier. These devices are used in industrial temperature measurement, spectroscopy and laser power meters. They are also used to measure high speed laser pulse
characteristics.
....
~
;:
II
I
HORIZOHTAl=20 ns/DlV
TL/H/5641-2
FIGURE 1b
775
respo,nse.time much Io,nger than a-few milliseconds, the o,ptical cho,pper pro,vides a mo,dulated.light signal'to, t~ detect!Jr. The amplifier.o,utput may be rectified to recover the DC
co,mponent o,f the signal. Figure 3c ·sho,ws a current mode
signal co,nditio,ning circuit. The o,ptical cho,pper is retained,
but the detecto,r is Io,aded (jirectly into, the summing junctio,n
o,f a Io,w bias o,p amp co,mposed o,f an LF411 and a pair o,f
sub-picoamp bias -FETs. The Io,w. bias current lI11o,ws Io,w
energy light.measur!lment.
For signal co,nditio,ning purposes, pyroelectrics can be mo,deled as e.ither a current source with parallel capacitance o,r a
vo,ltage so,urce with series capaCitance. Because there is no,
resistiveco,mponent, there is no, resistive Jo,hnso,n no,ise.
Figure
sho,ws simple vo,ltage mo,de ~t-up which.can
be used fo,r fast pulses o,f high energy. In this circuit, the
detector is terminated directly into, a high speed 500 o,scillo,scope. In Figure 3b, a slo,wer detector terminateS into, 1 MO
and is unloed~ by. the LH0052 low bias FET amplifier. Fo,r
3a
a
INHAlATION
60 SECONDS·
ISOTOPE OECAY·
3D.SECONDS
SATURATION
128 SECONOS
90 SECONDS
150 SECONDS
FIGURE2b
PYROELECTRIC
omCTOR
LASER PRECISION CORP.
AMPLITUDE MODULATED
CARRIER OUTPUTTO RECTIFIER. A-O CONY, ETC
TEKTRONIX
p<811-+----1
I I~,i
CHOFftR/l;- UDHT INPUT
~
CHOFftR SYNC. SIGNAL
(FOR A-O TRIGGER, ETC.)
"TRW MAR6resis\or, 1%
FIGURE3a
FIGURE3b
,.......-oI5V
31.6k*
31.6k*
LASER PRECISION CORP.
~""-iC»OUTPUT
KT311Q
'TRW MAR 6 resistor,
1"
TLlH/5641-4
FIGURE3c
776
high Q, noise rejection characteristics and fast response of
ultrasonic transducers to accomplish a difficult thermal measurement. This circuit is similar to a type developed to measure high speed temperature shifts in a gas medium.
PIEZOELECTRIC ULTRASONIC RESONATORS
Piezoelectric ultrasonic tranducers are generically related to
pyroelectrics in that they are also ceramic-based. These devices are used for both generation and reception of narrow
band ultrasonic information. The characteristic resonance of
these transducers, in a similar fashion to quartz crystals, is
extremely narrow, allowing high Q, noise rejecting systems
to be built around them. As transmitters, they are often driven very hard by steps several hundred volts high at low duty
cycles. This permits substantial ultrasonic power to be generated and eases the burden of the receiver in the system
(which could be the same transducer as the transmitter).
Ultrasonic resonators are used in a wide variety of applications including liquid level detection, intrusion alarms, automatic camera focusing. cardiac ultrasonic profiling (echocardiography) and distance measuring equipment. Figure 48
shows a signal conditioning circuit which capitalizes on the
1011
lN4141
In contrast to almost all other temperature sensors, it does
not rely on its sensing element to come into thermal equality
with the measurand. Instead, the relationship between the
speed of sound and the temperature of the medium in which
the sound Is propagating is utilized to determine temperature. The speed of response is therefore very fast and the
measurement is also non-invasive. The relationship between the speed of sound in any medium and temperature
may be described by equations. As an example, the relationship in dry air is:
C = 331.5
~ meters/second,
where C = speed of sound.
------+-----+-
1.
TRANSMmER
SAMPlE RATE
IDle
RECEIVER
RECEIVE .
TEST POINT
lav
IDle
IDle
15V
UIII07tI
(10VVIEF)
D1
2M3alD
DUAL
lk
14.7k
lk
110
RAMP TEST POINT
lOG
ZERO
10k
5.•
Ultrasonic transducers
= Massa MK-l09
TLlH/5641-5
FIGURE4a
777
For any given value of C the absolute temperature is:
T
In Figure 58, the transducer looks'directly into the ground
potential summing junction of an -op amp. Because. of this,
there is no voltage difference between the interconnecting
cable center conductor and its shield. This eliminates cable
capaCitance effects on the transducer output and allows
long cable runs. It is advisable to use cable specified for low
triboelectric charge effects for best performance, although
this is usually only a factor with relatively low output devices.
The 1011 0 resistor provides a DC feedback path, while the
variable capaCitor sets the sensitivity of the charge-to-voltage conversion. When the accelerometer shown is mounted
on a hand-held voltmeter and dropped on the floor, the instantaneous acceleration to which the voltmeter is subjected can be determined. In Figure 5b, the stored trace display
=~
C.2
(331.5)2 X .
It is clear that because sound speed and the medium in
which it travels have a predictable relationship, a temperature transducer can beeomposed of the medium itself. If the
characteristics of the medium can be defined(e.g., its make
up) the transmit time of a sonic pulse through it can be used
to determine its temperature. If narrow band ultrasonic
transducers are used, they will reject sonic noise that may
be occurring in the medium.'
A1 periodically generates a short pulse (waveform A, Figure
4b) that drives the 2N3440 into conduction, forcing the ultrasonic 40 kHz transducer to emit a short burst at its resonant
frequency. The 150V pulse amplitude allows substantial ultrasonic energy to be coupled into the medium. As this
pulse is generated, the DM7474 flip-flop is set low (waveform C, Figure 4b). After a length of time, determined by the
distance between the ultrasonic transducers 'and the temperature of the gas, the sonic pulse arrives at the receiving
transducer and is amplified by A3 and A4 (A4's output is
waveform B, Figure 4b). This amplified output triggers AB,
which resets the flip-flop high. During the time the flip-flop
was low, the 2N3810 current source was allowed to charge
the 0.Q1 /LF capacitor (waveform D, Figure 4bj. When the
flip-flop is reset high, 02 comes on and the charging ceases. The A2 follower output sits at the capacitor's DC potential, which is related to the sonic transit time in the gas
stream. The LF398 sample-hold is triggered by the "B"
DM74121 one shot and samples A2's output. The LF398's
output feeds two LH0094 multi-function non-linear converters which are arranged to linearize the speed of sound versus temperature relationship. The output of this configuration is the gas temperature which is displayed on the meter:
Gain and zero trims are provided via the A7 and A8 networks. When A1 issues another pulse, the DM74121 "A"
one shot resets the 0.01 /LF capacitor to OV and the entire
process repeats.
It is worth noting that no bandwidth limiting of any kind is
employed at the A3-A4 receiver despite their compound
gain of 1000. This would seem to invite noise sensitivity
problems in a sonic system, but the high 0 ultrasonic transducer provides almost ideal noise rejection. Figure 4c
shows the amplified output of the received pulse superimposed on the output of a boardband microphone placed in
the sonic path. Boardband noise 100 dB greater than the 40
kHz pulse is pumped into the sonic path. Virtually complete
noise rejection occurs and signal integrity is maintained.
A=3OV/DlV
8=1OV/DIV
C=1OV/DIV
D=2V/DlV
IIORIZONTAL=0.5 pi/DIY
TL/H/5641-6
FIGURE4b
A=5V/DlV
8=5V/DlV
HORIZONTAL =0.5 pI/DIV
TL/H/5641-7
FIGURE4c
PIEZOELECTRIC ACCELEROMETER
Another piezoelectric-based tran.sducer is the piezoelectric
accelerometer. These devices utilize the property of certain
ceramic materials to produce charge when subject to mechanical excitation. These accelerometers use a mass coupled to the piezoelectric element to generate a force on the
element in response to an acceleration's frequency and amplitude. Calibration and sensitivity can be varied by selecting
the piezoelectric materal and altering the configuration and
amount of the mass. The best way to signal condition these
devices is to employ an amplifier configuration that is directly sensitive to their Charge-type output. Charge amplifiers
use low bias current op amps with capacitive feedback. Output voltage will depend upon the charge out of the accelerometer which is related to the applied acceleration.
1 pF-5 pF
P"--tC>J OUTPUT
TLlH/5641-8
FIGURE5a
778
shows an instantaneous force of almost 1000G with smaller
forces generated as the voltmeter bounces 3 times over 60
ms. (It is recommended that this experiment be performed
with a borrowed voltmeter.)
Figure 6b shows a circuit which does this. Waveforms of
operation are given in Figure Be. In this circuit, 01 and its
associated components from a phase shift oscillator which
runs at 2.5 kHz, the manufacturer's specified transducer operating fnsquency. A1A amplifies and buffers 01's ou~ut
and drives the LVDT (waveform A, Figure Be). Since the
transducer's ou~ut will vary with drive level, feedback is
used to stabilize the 2.5 kHz amplitude. A1C and A 10 full
wave rectify a sample of the drive waveform. A1C's filtered
output is applied to A 10, a servo amplifier. A10 compares
A1C's output to the LM329 reference and drives the 01
oscillator to complete an amplitude stabilization loop. The
LVDT's ou~ut is amplified by A2C and fed to A2A. A2A is a
unity gain ampilifer whose sign altemates between" + " and
"- ". Synchronous switching for A2A comes from C1
(wayeform B, Figure 6c), which is driven by the modulation
sine wave ou~ut via a phase shift network. The phase trim
network compensates phase shift in the LVDT and ensures
that C1 switches at the zero crossings relative to A2A's output. When C1's ou~ut is low, the 2N4393 FET is off and
A2A's positive input (waveform C, Agure 6c) receives signal. When the sine wave reverses polarity, C1's output goes
high, turning on the FET, which grounds A2A's "+" input.
Under these conditions A2A is always switching its amplification's sign from" + " to .. -" in synchronism with the sine
wave output from the LVDT. A2A's phase sensitive ou~ut,
in this case positive, appears in trace 0, Agufe 6c. A2B
provides a scaled and filtered DC output. To trim the circuit,
set the LVDT to at least Yz physical displacement and adjust
the phase trim for maximum output indication. Next, adjust
the gain trim for the desired Circuit output at full-scale LVDT
displacement.
HORIZONTAL=1D 1II/01V
TLlH/5641-9
FIGURE5b
LINEAR VARIABLE DIFFERENTIAL
TRANSFORMER (LVDT)
The linear variable differential transformer (LVOn offers
zero-friction position sensing with good precision. Although
potentiometers are easy to signal condition and allow high
precision they cannot match the nearly infinite life and zerofriction of the LVDT approach. LVDTs are available in both
rotary and stroke mechanical configurations. The LVDT is
basically a transformer (Figure 68) with a movable core. The
primary is driven with a sine wave which is usually amplitude '
stabilized. The two matched secondaries are connected in
series-opposed, fashion. When the movable core is positioned in the magnetic (and usually geometric) center of the
transformer, the secondaries' outp~ cancel and no net
secondary voltage appears. This is called the null position.
As the core is moved from nUll, the differential in flux coupled to the two secondaries produces a net voltage difference across ~hem.
PRIMARY
FORCE·BALANCED PENDULOUS ACCELEROMETER
The operating principles of the LVDT are applied in the
force-balanced pendulous accelerometer. Transducers of
this type feature wide dynamic range, high linearity and very
high accuracy. FlfJure 7a shows one form of a conceptual
force-balanced pendulous accelerometer. The device operates by using an LVDT-type pick-off to determine the position of the pendulum. The DC output olthe LVDT is fed to a
servo amplifier which drives the torque coil. The magnetic
output of the torque coil completes a servo loop around the
pendulum, forCing it to become immobile. Because the
torque coil's field can attract only the pendulum, a second
bias coil provides a steady force for the torque coil to work
against. When an input acceleration occurs along the sensitive axis, the servo applies the necessary current to the
torque coil to keep the pendulum from moving. The amount
of current required is directly proportional to the value of the
input acceleration. Because the. pendulum never moves,
transducer linearity and acquracy can be very high. In addition, wide dynamic range is possible. Force-balanced accelerometers are widely applied in aircraft inertial guidance
systems, aerospace applications, seismic monitoring, shOCk
and vibration studies, oil drilling platform stabilization and
similar applications. In recent years these accelerometers
have become available in complete signal conditioned
packages, although there are a number of applications
where it: is desirable to independently Signal condition the
transducer:, FlflIIfe 7b shows a detailed schematic of such
signal conditioning. The pick-off circuitry is similar to the
LVDT shown in Figure 6b and does not require further'comment. The bias coil is driven by the LHOOO2 boosted LF347
(A 1A) which is in a current sensing feedback configuration.
For the accelerometer shown, the manufacturer specifies
OUTPUT
CORE
PICKOFF
t
+
TLlH/5641·10
FIGURE6a '
This is the output of transducer, 'Good transducer performance (e.g., null cancellation characteristics, linearity, etc.)
requires manufacturer attention to winding techniques, magnetic shielding, material choices and other issues. Rectifying
and filtering the output signal will yield only amplitude information. Optimum signal conditioning requires a phase sensitive demodulation scheme. This gives the amplitude and
also polarity information necessary to determine on which
side of null the LVDT core is.
779
....
~
z
C
60 mA of bias coil current. Torque. pulses are applied by
servo amplifier A38, which is biased from the LVOT demod,
ulator output.· The output of the circuit is taken across the
1000 resistor in series'with the torque coil. Servo gain'is set
at A38 while damping for the loop is provided by the 1 p.F
unit in A38's feedback loop. In addition, aCcelerometer
damping is controlled by stabilizing the temperature of the
mechanical assembly. This is accomplished by A3C, which
is· set up as a simple on-off temperature controller. The interior of the accelerometer is filled at manufacture with a liquid
whose viscosity provides appropriate damping characteristics at a specified temperature, in this case 180"F. Accelerometers of th~·type rQUtinely yield 100ppm accuracy from
.
ranges of 20 mG to 1'00G.
TRANSFORIilER DElAil
_YELLOW
RED
.aWE
,tv
+I-=N914
AI
A2
= LF347
= LF347
Cl = LM311
Ql = 2N2222
FIGURE6b
PIVOT
TL/H/5641·12
FIGURE6c
TLlH/5641-1'
FIGURE 7.
780
15V
15V
BIACII
13k
HEATER
IlEMODUIATOR
DC TEST POINT
28k
PENOULOUS ACCElEROMETER
,
...... IftIIIEYWELL _HI
Ik
\
I
I
7111
0.1
"TI
~I
GRES.' .....
~
C
:II
-15V
.;'
T8IIIVII=II8'F TEMP.
WHITE-YELLOW ~':J MONITOR
WlllTE-lLUE
741111180'F
> ....
~121111
is
-- -""
I,.F
l:I:
:1:1
~118
511
-15V
...,
III
<>--"\1\0
6L1nu
tr
-I.IV
Y.,
10k
3k
Uk
TOI.IVY.,
ArLM385
TLlH/5641-13
• Adjust to 60 rnA bias loop
AI, A2, A3 = LF347
current
lOe-NY
----
------------
RATE GYRO
The rate gyro is another form of high performance inertial
measuring transducer. It consists of an electrically driven
gyroscope with a captive spin axis. Normal gyros are free of
restraint and maintain position when moved. The rate gyro
is held captive and forced to move with the physical input.
By measuring the force generated as the gyro opposes its
restraining mechanism, rate-of-angle change information
can be deduced. Figure 8 shows Signal conditioning for a
typical rate gyro. An LVDT-type pick-off is used and synchronous demodulation-type circuitry very similar to Figure
7b is employed. Note the high voltage drive to the gyro motor (26 Vrms) supplied by the boosted LM143. Because of
their long life and high precision rate, gyros are frequently
employed in inertial guidance systems, drilling platformstablllzation systems and other critical applications.
extemal magnetic field and the average permeability of the
material. Since this saturation-ta-saturation transition occurs
twice each excitation period (fundamental), the frequency of
signal out of the pick-up windings is twice the excitation
frequency.
These 'transducers find use in metal detectors, submarine
locating gear, electronic compasses, oil surveys, ,and other
areas where measurement of the 'strength or locally caused
disturbanCe of the earth's magnetic field is of interest. Flux
gate,transducers are capable of measuring variations in the
earth's magnetic field within one gamma (10- 5 oersteds).
Two axis flux gates ,! set the desired passband gain and a
and generating a clock for the proper resonant frequency.
Each 2nd order section can be treated in a modular fashion,
with regard to individual center frequency, a and gain, when
casoading either the two sections within a package or several packages for. very high order filters. This individuality of
se.ctions is important in implementing the various response
characteristics such as Butterworth, Chebyshev, etc.
The follOwing is a general summary of deSign hints common
to all modes of operation.
1) The maximum supply voltage for the MF10 is ± 7V or Just
+ 14V for single supply operation. The minimum supply
to properiy bias the part is 8V.
788
.--------------------------------------------------------------------.~
MODE 1: Notch, Bandpass and Lowpass
With the addition of just one more external resistor, the output dynamics are improved over Mode 1A to allow bandpass designs with a much higher O. The notch output features equal gain above and below the notch frequency.
MODE 1A: Non-Inverting Bandpass, Inverting Bandpass, Lowpass
This is a minimum external component configuration (only 2
resistors) useful for low 0 lowpass and bandpass applications. The non-inverting bandpass output is necessary for
minimum phase filter designs.
Design Equations
Design Equations
f
felK
0=
f = felK or felK
o
100
50
felK
100 or 50
fnotch = fo
0= R3
0= RS
R2
R2
HOlP = -1
R2
HOlP = - R1
RS
HOBPl = - R2
R3
HOBP = - R1
HOBP2 = 1 (non-inverting)
Circuit Dynamics
R2
felK
HON = - R1 aSf-Oandasf-T
HOBPl = -0 (this is the reason for the low 0
recommendation)
Circuit DynamiCS
HOlP (peak) = 0 X HOlP
HaBP = HOlP X O=HON X 0
HOlP (peak) = 0 X HOlP (if the DC gain of the LP output is
too high, a high 0 value could cause clipping at the lowpass
output resulting in gain non-linearity and distortion at the
bandpass output).
MODE1A
SAil
~6
y+
MODE 1
RI
SAil
~6
y+
Tl/H/5035-5
789
11=
~
.....
~ r---------------------------------------------------------------------------------~
~
~
MODE 2: Notch (with .In ,;; 'o),Bandpass and I.;dwpass
This configuration allows tuning of the clock to center frequenCy ratio to values greater than 100 to 1 or 50 to 1. The
notch output is useful for designing elliptic highpass filters
because the frequency of the required complex zeros
(fnotch) is less than the frequency of the complex poles (fo).
Design Equations
f = fClK ~1
o
100
+ R2 or fCLK ~1 + R2
R4
50
MODE 3: Hlghpaaa, Bandpaaaand Lowpass
This configuration is the classical state variable filter (the
circuit of Ftguf9 1) implemented with only 4 external resistors. This: is· the most versatile mode of ope(ation, since the
clock to center frequency ratio can becexternally toned either above or below the 100 to 1 or 50 to t values. The
circuit is suitable for multiple stage Chebyshev filters controlled by a single clock.
'. . :'
Design Equations
R4
50
Q
= JR2/R4
Q =
+1
R2
HOHP = - R1
R2/R 3
R2
R1
HOlP=~
1
R3
HOBP = - R1
R4
HOLP = - Rt
+ R4
R3
HOBP = - R1
Circuit Dynamics
R2
HON1(asf -
HOHP = HOlP (::)
R1
0) =~
1
HON2 ( as f -
fR2 fClK fR2
VAA or 50 VAA
fR2 x R3
VAA R2
f = fClK
o
100
f - fClK fClK
n - 100 or
fClK)
2
HOlP (peak) = Q X HOlP
+ R4
HOBP = Q "HOHP X HOlP
HOHP (peak) = Q X HOHP
R2
= - R1
Circuit Dynamics
HOBP = Q ';"'fi"'O-LP"""-'X"THT"O-N-2
= Q "HONl
X H9N2
MODE 2
R4
r---------------------------------------------------------------.~
HON, (as f -
A notch output is created from the circuit of Mode 3 by
summing the highpass and lowpass outputs through an external op amp. The ratio of the summing resistors Rh and R,
adjusts the notch frequency independent of the center frequency. For elliptic filter designs, each stage combines a
complex pole pair (at fo) with a complex zero pair (at fnotch)
and this configuration provides easy tuning of each of these
frequencies for any response type. When cascading several
stages of the MF10 the external op amp is needed only at
the final output stage. The summing junction lor the intermediate stages can be the inverting input of the MF10 internal
op amp.
_ lelK
(R2
(R2 x
'VFi4
_ lelK
Inotch - 100
Ai" X HOlP
felK)
2
Rg
= Rh X HOHP
MODE 4: Allpass, Bandpass and Lowpass
Utilizing the 51A (51 B) terminal as a signal input, an allpass
function can be obtained. An allpass can provide a linear
phase change with frequency which results in a constant
time delay. This configuration restricts the gain at the allpass output to be unity.
Design Equations
I = lelK or lelK
o
100
50
(R2
lelK
or
I z (Irequency 01 complex zero pair) = 10
R3
R2
0= R3
fRh lelK fRh
'V Ai" or 50 'V Ai"
Oz (0 01 complex zero pair)
R2
.
R3
= R1
R2
HOAP = - R1 = -1
R2
HOHP = - R1
R4
HOlP = - R1
HOlP
=-
(:~ + 1) = -2
R3
HOBP = - R1
HOBP
=-
(1
HON (atf = fo) =
~
~
-1OoVFi4 50VR4
0=
0) =
HONh ( asl -
Design Equations
10
Z
Rg
MODE 3A: Hlghpass, Bandpass, Lowpass and Notch
+ R2) R3 = -2 R3
R1
R2
R2
Circuit DynamiCS
I0 (:~ HOlP - :~ HOHP) I
HOBP = HOlP X 0 = (HOAP
+
1)0
MODE3A
R4
BPa
LPa
R1
Sa'i
~.
y-
NOTCH
OUT
MODE 4
R1
V,.
>--""'''''-1
TUH/5035-7
791
~
~
:Z
cc
r---------------------------------------------------------------------------------,
MODE 5: Complex Zeros (C.:!;), Baridpaaa and, Lowpa..
MODE 6A: Single Pole, Hlghpaaa and Lowp...
This mode features an improved allpass design over that of
Mode 4, in that it maintains a more constant amplitude with
frequency at the complex zeros (C.z) output. The frequen·
cies of the pole pair and zero pair' are resistor tunable.
By using only one of the internal integrators, this mode is
useful for creating odd,ordered cascaded filter responses
by providing a real pole that is clock tunable to track the
reSonant frequency of other 2nd order MF10 sections. The
corner frequency is resistor tunable.
Design Equations
Design Equations
fOlK'~
f
\1
=fOlK~1_R1 0 rfOlK~
0= 100
f
z
fCLK ~
iM or 50,,1 + iM
1 '+
100
Q = R3 ~1
R2
R4
50
fe (cut-off frequency) = fOLK (RR2) or fOLK -(RR2)
.
-.
100
3
50
3
R3
HOlP = - R1
_R1
1 R4
R2
HOHP = - R1
+ R2
R4
Qz = R3 ~1 _ R1
R1
R4
HO(o.z)asf -
R2(R4 - R1)
0 = R1(R2 + R4)
HO(o.z)asf -
2
Hosp = R3 (1
R2
+ R2)
fOLK
R4 (R2
HOlP = R1 R2
R2
= R1
R1
+ R1)
+ R4
MODE 5
MODE6A
R1
SAil \
~6
vTL/H/5035-B
792
MODE 6B: Single Pole Lowpass (Inverting and NonInverting)
split supply operation these pins would be grounded. An
input coupling capacitor is optional, as it Is needed only if
the input Signal is not also biased to Vcc/2. For a two-stage
Butterworth response, both stages have the same corner
frequency, hence the common clock for both sides. The
resistor values shown are the nearest 5% tolerance values
used to set the overall gain of the filter to unity and to set
the required Q of the first stage (side A) to 0.504 and the
second stage (side B) Q to 1.306 for a flat passband response.
This mode utilizes only one of the integrators for a single
pole lowpass, and the input op amp as an inverting amplifier, to provide non-inverting lowpass output. Again, this
mode is useful for designing odd-ordered lowpass filterS.
Design Equations
fc(cut-offfrequency)= fClK
100 (R2)
R3 or fClK (R2)
R3
50
HOlP (inverting output) = -
A unique advantage of the switched capacitor design of the
MF10 is illustrated in Figure 6. Here the MF10 serves double duty in a data acquisition system as an input filter for
simple bandlimiting or anti-aliasing and, as a sample and
hold to allow larger amplitude, higher frequency input signals. By gating OFF the applied clock, the switched capacitor integrators will hold the last sampled voltage value. The
droop rate of the output voltage during the hold time is approximately 0.1 mV per ms.
:~
HOlP (non-inverting output) =
+1
MODE6B
LPA (N.lNY.) VIN
A useful non-filtering application of the MF10 is shown in
Figure 7. In this circuit, the MF10, together with an LM311
comparator, are used as a resonator to generate stable amplitude sine and cosine outputs without using AGe circuitry.
The MF10 operates as a Q of 10 bandpass filter which will
ring at its resonant frequency in response to a step input
change. This ringing signal is fed to the LM311 which creates a square wave input Signal to the bandpass to regenerate the oscillation. The bandpass output is the filtered fundamental frequency of a 50% duty cycle square wave. A 90'
phase shifted signal of the same amplitude is available at
the lowpass output through the second integrator in the
MF10. The frequency of oscillation is set by the center frequency of the filter as controlled by the clock and the
50:1/100: 1 control pin. The output amplitude is set by the
peak to peak swing of the square wave input, which in this
cirCUit is defined by the back to back diode clamps at the
LM311 output.
R3
TLlH/5035-9
SOME SPECIFIC APPLICATION EXAMPLES
For single-supply operation, it is important for several terminals to be biased to half supply. A single-supply design for a
4th order 1 kHz Butterworth lowpass (24 dB/octave or 80
dB/decade rolloff) is shown using Mode 1 in Figure 5. Note
that the analog ground terminal (pin 15), the summer inputs
51 A and 51 B (pins 5 and 16) and the clock switching control
pin (pin 12) are all biased to VCC/2. For symmetrical
13k
OUTPUT
20
LPa
10k
19
r-f1
10k
18
17
ePa NIAPI INVB
HPa
16
SIB
15
14
AGNO Vr
r--
13
12
11
VD - 5OI1ooV CLKa
CL
MF10
NIAPI
LPA
8PA
HPA
INVA
SlA
SA/B
VA+
1
2
3
4
5
6
7
'--C
INPUT--
-H---
22k
12k
VD+
L Sh
8£
CLK.\
10
100 kHz
CLOCK
5V.., ....
22k
7~10V
~
ov-L-I
---T
TLlH/5035-10
FIGURE 5. Only 6 resistors required for this 4th order, 1 kHz Butterworth
lowpass filter. This example also Illustrates single-supply biasing.
793
9.1k
13k
INPUT -IW'It--I
INPUT
AGNDLlf--~
I
..J
AID
DATA
CONVElITER
CLOCK-~-""
y
START CONVERTER
AND PUT FILTER
IN HOLD MODE
TLIH/5035-14
FIGURE 6. An MF10 as an Input Filter and Sample/Hold
11k
51k
" " - ' Va SIN (21" ~~ t)
5.1k
1M
TL/H/5035-11
FIGURE 7. Generating Quadrature Sine Waves from a T2L Clock
794
Construction of this filter on a printed circuit board would
obviously be more compact than an RC active filter approach and much more cost effective for the level of precision required. An even more attractive implementation from
a space savings point of view would be a hybrid circuit approach. A film resistor array connecting to two MF10 die
could produce the entire filter in one package requiring only
7 external connections for input, output, supplies, etc.
Finally, as a graphic illustration of the simplicity of filter implementation using the MF10, Figure 8 is a complete 300
baud, full-duplex modem filter. The filter is an 8th order, 1
dB ripple Chebyshev bandpass which functions as both an
1170 Hz originate filter and a 2125 Hz answer filter. Control
of answer or originate operation is set by the logic level at
the 50/100/CL input so that only one clock frequency is
required. The overall filter gain is 22 dB.
~______________________________________~:ANSWEi
9.1k
ORIGINATE
56k
7k
20
167k
19
10k
18
11.6k
88k
17
2D
19
10k
18
MF10
17
MF10
•
•
lUk
239k
101<
5.9k
~
8.6k
16k
5Y
101<
______________________________________..111.
OUTPUT
_~~:z
47k
INPUT
TUH/5035-12
FIGURE 8_ A Complete Full-Duplex 300 Baud Modem Filter
795
~ r---------------------------------------------------------------------------------~
o
C?
~
THE SWITCHED CAPACITOR INTEGRATOR-HOW IT
WORKS
The effective resistance from VIN to the (-) input is therefore:
The most important feature of the MF10 is that it requires no
external capacitors, yet can implement filters over a wide
range of frequencies. A clock is used to control the time
constant of two non-inverting integrators. To feel comfortable with the operation of the MF10, it is important to understand how this control is accomplished. '
,
R=VIN=_1_,
1 C1 felK
This means that 51, 52 and C1, when clocked in Figure B,
act the same as the resistor in Figure A to yield a clock
tunable time constant of:
It is easiest to discuss an inverting integrator (Figure A) and
how its input resistor can be replaced by 2 switches and a
capacitor (Figure BJ. In Figure A the current which flows
through feedback capacitor C is equal to VIN/R and the
circuit time constant is RC. This time constant accuracy depends on the absolute accuracy of two completely different '
discrete components. In Figure B, switches 51 and 52 are
alternately closed by the clock. When switch 51 is closed
(52 is opened), capacitor C1 charges up to .yIN. At the end
of half a clock period, the charge on C1 (QC1) is equal to
VINxC1. When the clock changes state, 51 opens and 52
closes. During this half of the clock period all of the charge
on C1 gets transferred to the feedback capaCitor C2.
C2
T=--C1 felK
Note that the time constant of the switched capaCitor integrator is dependent on a ratio of two capacitor values,
which, when fabricated on the same die" is very easy to
control. This can provide precise filter resonant frequency
control both from part to part and with changes in temperature.
'
The actual integrators used in the MF10 are non-Inverting,
requiring a slightly more elegant switching scheme, as
shown in Figure C. In this circuit, 51A and 51e are closed
together to charge C1 to VIN. Then 52A and 52e are cloSed
to connect C1 to the summing junction with the capacitor
plates reversed, to provide the non-inverting operation. If
VIN is positive, VOUT will move positive as C2 acquires the
charge from C1.
The amount of charge transferred from the input, VIN, to the
summing junction [the(-) input] of the op amp during one'
complete clock period is VI~1. Recall that electrical current is defined as the amount of charge that passes through
a conduction path during a specific time interval (1 ampere = 1 coulomb per second). For this circuit, thE! current
which flows through C2 to the output is:
aQ VINC1
I=Tt=-r-=VINC1 felK
where r is equal to the clock period.
C
.. ~UT
• r:;.r,¥a
'II'
or:'
FIGURE A
C2
82~ ¥aUT O~t
81
VJN~
-y- *C1-Y-
1Jt~
-QA
+
'II'
FIGUREB
C2
VOUT
TLlH/5035-13
FIGURE C. The Non-Inverting Integrator Used in the MF10
796
Theory and Applications of
Logarithmic Amplifiers
National Semiconductor
Application Note 311
A number of instrumentation applications can benefit from
the use of logarithmic or exponential signal processing techniques. The design and use of logarithmic/exponential circuits are often associated with involved temperature compensation requirements and difficult to stabilize feedback
loops. For these considerations and others, designers tend
to avoid these circuits. Hybrid and modular logarithmic/exponential devices are available commercially, but are quite
expensive and earn very high profits for their manufacturers.
circuit's output is a function of:
The theory and construction of these circuits are actually
readily understood. Figure 1 shows an amplifier which provides a logarithmic output for a linear input current or voltage. For input currents, the circuit will maintain 1% logarithmic conformity over almost 6 decades of operation. This
circuit is based, as are most logarithmic circuits, on the inherent logarithmic relationship between collector current
and VBE in bipolar transistors. 01 A functions as the logging
transistor in this circuit and is enclosed within AlA's feedback loop, which includes the 15.7 kO-l kO divider. The
circuit's input will force AlA's output to achieve whatever
value is required to maintain its summing junction at zero
potential. 8ecause alA's response is dictated by the logarithmic relationship between collector current and VBE, the
output of AlA will be the ·Iogarithm of the circuit input. AI 8
and 018 provide compensation for alA's VBE temperature
dependence. Al 8 servos a18's collector current to equal
the 10 ".A current established by the LM329 reference diode and the 700 kO resistor. Since 01 8's collector current
cannot vary, its VBE is also fixed. Under these conditions
only alA's VBE will be affected by the circuit's input. The
where K = Boltzmon's constant
EOUT =
15.7k + lk
lk
(VBe01B - VBEalA)
For 01 A and 018 operating at different collector currents,
the VBE difference is:
AV
- KT I
ICOIA
BE oge IC01B
q
T=temperature 'K
q = charge of an electron.
If both equations are combined, the circuit output for a voltage input is:
EIN - 700k
E
_ -KT 15.7k + lk
OUT q
lk
loge 6.9V -lOOk
where 6.9V=Vz of LM329
lOOk = input resistor
EIN;;"O.
This confirms that the circuit output voltage is logarithmically related to the circuit's input. Without some form of compensation, the scale factor will change with temperature.
The simplest way to avoid this is to have the 1 kO value vary
with temperature. For the device shown, compensation is
within 1% over - 25'C to + 100'C. The circuit's gain is set
by the 15.7 kO-l kO divider to a factor of tV/decade.
,--1,...---.....I\J""'...->M_15Y
7ODk*
3k
LM329
ru.(o}-_..J
'1 % film resistor
11 kG (±1%) at 25"C, +3500 ppm/'C.
Available from Vishay Ultranl..
Grand Junction, CO, OB1 Series.
FIGURE 1
797
A1A. A1B = LF412 dual
01A. 01B = LM394 dual
TLIH/5045-1
~
~
i
,-----------------------------------------------------------------------------------------------,
. This. circuit may be easily turned around to generate exponentials. In Figure 2, 01 A is driven from the input via the
15." kG divider. 01 8's collector current varies exponentially
with its VSE, and A18 provides a voltage output representation of this action.
These circuits are easy to construct and use if a few considerations are kept in mind. 8ecause of the VSE and scale
factor temperature dependences, it is important that 01 A,
01 8 and the 1 kG resistor be kept at the same temperature.
Since 01 is a dual monolithic device, both halves will track.
The resistor should be mounted as closely as possible to
Uk
01, and these components should be kept away from air
currents or draftS. The KTI q factor for which the resistor
compensates· varies at /lbout ,O.3%/OC, so. a. few dll9rees
difference between 01 and the resistor will intrOduce significant error.
Once the theory and construction techniques are understood, the circuits can be applied. F/{Jure 3 shows a way to
'achieve very precise control ofa rotary pump, used to feed
. a biochemical fermentation process. In this example, the
exponentiator, composed of 01 and A1A, is driven from
10k
10k
15V~W_""W~~--"'1_""""\.
> ....I-tOO)EtiUT
15.7k*
*1'l1lilmresistor
tl kll (± 1%) at 25'C. + 3500 P\1ftI/'C.
Available from Vishay Ullroni ••
Grand Junction. CO. 081 Series.
AlA. AlB ~ LF412 dual
01A. 01B ~ LM394 dual
FIGURE 2
LM329
Uk
69.5k*
+REF-..."V',.,.,........
* 1" film r.sistor
tl kll (± 1%) at 25'C. + 3500 ppm/'C.
Available from Vishay UllrOnix.
Grand Junction. CO. 081 Series.
.....- ~ lN414B
01A. 018 ~ 'LM394 dual
02 - 05 ~ TlPI12 Darlington
AlA. AlB. AIC. AID ~ LF347
TOsTmaI
MOlORANO
PUMP HEAD
TL/H/5045-2
FIGURE 3
, 798
:I>
input amplifier A 1D. 01 B's collector current, instead of biasing a voltage output amplifier as in Figure 2, pulls current
from the A 1B integrator which ramps up (trace A, Figure 4)
until it is reset by level triggered A 1C (A 1C output is trace B,
Figure 4). The 100 pF capacitor provides AC positive feedback to A3C's .. + .. input (trace C, Figure 4). The magnitude
of the current that 01 B's collector pulls from A 1B's summing junction will set the frequency of operation of this oscillator. Note that the operation of the exponentiator is similar to the basic circuit in Figure 3 because A1B's summing
junction is always at virtual ground. A 1C's output drives the
MM74C76 flip-flop to bias the output transistors with 4phase drive for a stepper motor which runs the pump head.
In practice, the exponentiator allows very fine and predictable control for very slow pump rates (e.g., 0.1 rpm-10 rpm
of the stepper motor), aiding tight feedback control of the
fermentation process. When high pump rates are required,
such as during process start-up or when a wide feedback
control error exists, the exponentiator can be voltage directed to the top of its range. To calibrate the circuit, ground VIN
and adjust the 0.1 Hz trim until OSCillation just ceases. Next,
apply 7.SV at VIN and adjust the 600 Hz trim for 600 Hz
output frequency. Figure 5 shows a circuit similar to Figure
3, except that a more accurate V-F converter is used. This
circuit is intended for laboratory and audio studio applications requiring an oscillator whose frequency changes exponentially with an applied input sweep voltage. Applications
include swept distortion measurements (where this circuit's
output is used to drive a sine coded ROM-DAC combination
or analog shaper) and music synthesizers. The V-F converter employed allows better than 0.1S% total conformity over
a range of 10 Hz-30 kHz. The voltage reference used to
drive A1A's input resistor is derived from the LM331A's internal reference and is scaled by A 1B, which also biases the
zero trim setting. The DM74C74 provides a square wave
output for applications requiring a waveform with substantial
fundamental frequency content. The 0.1S% conformity performance achieved by this circuit will meet almost any synthesizer or swept distortion measurement and the scale factor may be easily varied. To trim, apply OV to the input and
adjust zero until oscillation (typically 2 Hz-3 Hz) just starts.
Next, apply -8V and adjust the Sk unit for an output frequency of 30 kHz. For the values given, the K factor of the
exponentiator will yield a precise doubling in frequency for
each volt of input (e.g., 1V in per octave out).
A=5V/DIV
B=2OV/DIV
C=2OV/1IV
HORIlONTAL=200 ,.s/DIV
TUH/5045-3
FIGURE 4
D.DD1
LM331A
3.3k
15V
loUT
10Hz30 kHz
... 5k*
5Ic
••
FULL·
SCALE
10k*
28k*
TRIM
VIM
OVTD -IV
47.
10k
ZERO
lkt
loUT 12 (SQUARE WAVE)
5 Hz-15 kHz
·1 % film reslstor
tl kG (± 1%) a125"C, +3500 ppml'C.
Available from Vlshay Ultranix.
Grand Junction. CO. 081 Series.
AlA. AlB - LF412 dual
01 A. 01 B = LM394 dual
n*
FIGURES
799
TLlH/5045-4
z
•
w
....
....
........
C?
Z
0....
I'SOCKET
r..... ~~
2
3 4 5 6 7 8910
DIE SIZE \kMIL2)
TLlF/5260-B
16-PIN MOLDED IIIP
~ BOARD MOUNT-BnLL AIR
130
90
71
O!I::!.
80 -BOAR
FIGURE 8. Thermal ReSistance vs
Board or Socket Mount
Lead Frame Material
Figure 7 shows the influence of lead frame material (both
die attach and device pins) on thermal resistance. This
graph compares our same 16-pin DIP with a copper lead
frame, a Kovar lead frame, and finally an Alloy 43 type lead
frame-these are lead frame materials commonly used in
the industry. Obviously the thermal conductivity of the lead
frame material has a significant impact in package power
capability. Molded interface circuits from National Semiconductor use the copper lead frame exclusively.
lJi!
"
m~!;>
~
TL/F/5280-6
c~Ji
z ...
~z"'"
1
FIGURE 6. Thermal Resistance vs Ole Size
Ii
~
90
.... .....
2
3 4 5 678910
DIE SIZE IkMILZ)
150
100
60
50
IU
Ii
II!Ji
71
...
80
170
110
IU
50
1
KOVA
AirFlow
When a high power situation exists and the ambient temperature cannot be reduced, the next best thing is to provide air
flow in the viCinity of the package. The graph of Figure 9
illustrates the impact this has on thermal resistance. This
graph plots the relative reduction in thermal resistance normalized to the still air condition for our 16-pin molded DIP.
The thermal ratings on National Semiconductor's interface
circuits data sheets relate to the still air environment.
1
U
1.1
;
1.0
~ 0.9
I
1II1 1
~
MDLOED"frr
~,
... 0.8
I
!
0.7
0, L must be made large enough so that:
DC/DC CONVERSION
The LH1605 operates only in Buck-type DC/DC converters.
A Buck converter produces a positive DC output voltage
which is less than its input voltage. It consists of a switching
regulator, a steering diode, an inductor and a capacitor (Figure 5). During the switch ON time, inductor current, iL,
builds, flowing to both the capacitor and the load. During
toFF, the magnetic energy stored in the inductor draws current through the diode. The capacitor serves to filter the
output voltage by sourcing current while iL is low and sinking
current when iL is high.
Figure 6 illustrates the current waveforms of the paths labeled in Figure 5.
= (VIN - Vol X toN
I
> [VIN(MAX) - Vol
O(MIN)
2L
x t ON
(13)
Equation 14 conveniently expresses the minimum required
inductance as a function of 10(MIN) and the operating frequency, fo.
(~)
VIN(MAX)
L> [VIN(MAX) - Vol
1
(14)
1
x-x--
2fo IO(MIN)
The graph in Figure 8 plots L vs IO(MIN) for some common
converter parameters.
As the load increases, more current must be supplied to
maintain a given output voltage. The switching regulator
senses the drop in Vo and increases switch duty cycle to
raise the average iL. Likewise, a reduction in loading causes
a reduction in switch duty cycle.
The next consideration for inductor design is the choice of
an appropriate magnetic core. The core must provide the
desired inductance without saturating under maximum output conditions. Magnetic core saturation leads to excessive
inductor current which jeopardizes output stability and may
damage both the switching regulator and the load circuitry it
supplies.
TLIK/5496-8
TL/K/5496-6
FIGURE 7. Inductor Current with ~IL > 210
FIGURE 5. Buck-Type Step-Down Voltage Converter
1\
I)
VO=12V,
VINIMAX)=18V
Vo=5V,
VINlMAX)=25V
Vo=5V,
VINIMAX)=l2V
10
b)
~
~
c)
10=50 kHz
o
5
d) tr-~~~~~~~~~~~~~---
50
L(,.H1
~
500
TL/K/5498-9
10
FIGURE 8. Inductance vs Minimum Output Current
a)
TLlK/5498-7
FIGURE 6. Buck Converter Current Waveforms
S09
~
;
:i
r------------------------------------------------------------------------------------------,
Switching converter inductor cores are' normally made of
ferrite or molypermalloy powder to minimize core loss at
high switching frequencies. The core should provide a
closed flux,path to minimize radiated noise due to flux leakage. Toroidal and fully enclosed pot cores are popular for
this reason.
To further reduce flux leakage, the core winding should be a
single layer covering a maximum amount of the winding surface. The number of winding turns necessary for an Inductance, L, is:
ute to the ESR and should be made as short as possible. To
reduce output voltage spikes due to switching transients, a
0.1 jJ.F ceramic capacitor should be used in parallel with an
electrolytic capaCitor. A partial list of manufacturers of low
ESR capacitors is included in Appendix A.
Equation 17 is a convenient expression for determining the
minimum required capaCitance as a function of eO, fO, ESR,
and the inductor ripple current.
C >'IO!MIN) x
1
(17)
4fo
eo - (10 (MIN) x ESR)
Figure 10 plots C vs eo for some common converter parameters.
N = 1000 X ~ L
(15)
Ll000
Core manufacturers specify the nominal inductance,
Ll000 mH per 1000 turns, for a given core as well as the
maximum magnetic energy, L12, that a core can sustain
without saturation. U2 is calculated using L as determined
by equation 14 and I equal to the maxlmum anticipated output current plus 10(MIN).
When using a core with optimum magnetiC performance at
the desired switching frequency, the 12R loss in the winding
will dominate inductor power losses. This loss,
PL = 102 x RLCDC winding resistance)
(16)
can be reduced by using large diameter copper wire for the
core winding.
Many magnetiC core manufacturers offer further information
on inductor design. Some companies now specialize in supplying pre-wound inductors to meet specific switching converter needs. A partial list of core manufacturers and inductor suppliers is included in Appendix A.
I--H..,yHtli~III(lIIII)=O.5A,
",£SR-G.OIID
°
~
If
Ie
" 80
f
f
100
1000
C(pF)
TUKl5496-11
FIGURE 10. CapaCitance vs Output Ripple Voltage
Power loss in a filter capaCitor is almost entirely due to ESA.
This loss is given by:
Pc =
CO!~IN»)2 X ESR
(18)
FEEDBACK
The LHl605 regulates output voltage using a single feedback resistor. The resistor, Rt, forms a voltage divider with a
2 kO internal resistor from pin 3 of the LH 1605 to ground
(Figure 11). A steady state output voltage is reached when
the voltage on pin 3 is approximately equal to the reference
voltage on pin 2, about 2.5V.
rj
iedt
= 0,5 Arms and ESR = 0.111,
1
= 50 mV + Ci"
1 ....
1 ....
11....
111I.......
1....&-..........1.I.UoI
1.....-....
10
CHOOSING AN OUTPUT CAPACITOR
The output filter capaCitor reduces the peak-to-peak output
ripple voltage, eo, by integrating the inductor ripple current
at the output node. To do this, the capacitor may have to
source and sink currents as high as 2A., At these current
levels, the drop across the capacitor's effective series resistance, ESR, could dominate eO. Figure 9 shows an example where no amount of capacitance could achieve less
than 50 mV output ripple.
VT'= ie x ESR +
__P'l...a:l::lttl
r- 1001IlII)-O·5A't
ESR=O.0250
YIN
iedt
TUK/5496-10
FIGURE 9. Effect of ESR on eo
Because the ESR of a large capacitor is generally less than
that of a small capaCitor of similar construction, the easiest
way to reduce ESR is to use a large capacitor. ESR can also
be reduced by using 2 or more capacitors in parallel. Capacitor leads and the PC board traces connecting them contrib-
8
L
~
Ui16D5
2k
CASE
3
lit
7
1
+
/
==c
ill
I
Vo
j
TLlK/5496-12
FIGURE 11. Output Voltage Feedback with LH1605
810
The output voltage can be programmed by selecting a feedback resistor as follows:
R - 2 kn VOUT - 2.5V
12.5V
A 10 p.F capacitor from pin 2 to ground will allow the
LH1605 to recover with a soft start from an over-current
condition. F1[Jure 13 illustrates a typical current limit circuit
for the LH1605 requiring only two transistors and three resistors.
(19)
Figure 12 shows the linear relationship between RI and Vo.
Although this circuit is effective, it has several shortcomings.
The -2.2 mVl'C TC of 01 can cause a 34% drift in the
current limit set point over the - 25'C to + 85'C temperature range, and the relatively large Rs can decrease overall
converter efficiency by as much as 10%. Furthermore, a
short circuit condition draws significant power from the input
supply. Superior performance can be obtained from a foldback current limit with only a slightly higher parts count.
20
16
1/
FOLDBACK CURRENT LIMITING
4
o
o
4
A fold back current limit reduces the current limit threshold
as the converter's load increases from an initial overcurrent
condition to a complete short circuit. Because short circuit
current, Isc, is much less than the initial current limit set
point, ICl' a prolonged short circuit draws very little power
from the input supply.
8 12 18 20 24 28
~IV)
TUKJ5496-13
FIGURE 12. Feedback ReSistance vs Output Voltage
In the circuit of Figure 14, Initial current limit is reached
when the output of 02 reaches 0.6V, VSE(ON) of 01.
CURRENT LIMITING
LH1605 current limiting is best done by pulling down the
reference voltage at pin 2. This reduces the output pulsewidth on a cycle-to-cycle basis. Clamping the reference to
ground inhibits the output switch and can be done with any
general purpose transistor.
+
.
0.6V
This corresponds to VCl = - - where
Av
R2
Av = R1 ,Rl = R3, R2 = R4.
(20)
OUT.8__-r~Lnr,-__. .__-.~~RS~~__-e____ +
IN
10k
LHl605
C
I_ _ _10_~~~~~~1-Ok------~------------~R-l-~
ICl _ O.IV
Rs
Isc-~
Rs
TUKJ5496-14
FIGURE 13. Hard Limiting Circuit for LH1605
LHl605
+
5 IN
OUT 8
Ll
IIA
r
YIN
j
+
Cl
+
Vel
-
Rl
lie
R2
TUK/5496-15
FIGURE 14. Foldback UmlUng for LH1605
811
Power drained from the input supply with the converter output short circuited cannot be easily expressed due to the
nature of the LH160S's control loop while in current limit.
The drain, however, can be minimized by using a foldback
current limit with a low Isc.
VCl is the sum of the voltage drop across Rs and the opposing drop acrossRA. As current limit is reached, Va is
reduced, lowering the voltage across RA. It then requires
less current through Rs to create a VCl sufficient to cause
further current limiting. This action produces the I-V characteristics shown in Agurs 15. As the overll;)ad is removed, the
converter output recovers along the same curve.
Design Example
Design requirements:
VIN(MAX> = 20V
VIN(MIN)
= 10V
VIN(NOM) = 14V
Va
= SV
TlJKl5496~16
FIGURE 15. Vo vslo.wlth Foldback limiting
Because the gain o.f Q2 can be quite large, generally 10 to
20, the sense resistor. Rs. can be made very small, 0.020
to 0.060. This significantly improves overall converter efficiency. Another advantage of amplifier gain is increased
temperature stability. A gain of 10 reduces ICl drift to about
-3.3 mArC with Rs = 0.060
The first step in designing a foldback current limit for the
LH160S is to choose a readily available value for Rs. Then
the amplifier gain ciln be determined as a function of Rs
and the desired short circuit current.
Av=~
~
10(MIN)
= O.SA
= 1A
= 2SkHz
fa
LM.IN = (20V-SV)
The maximum magnetic energy will be:
El = (1S0 ,...H)(SA + 0.SA)2 = 4.S4 mJ.
A toroidal powdered-iron core from Arnold Engineering, part
;IOSG-0800-0320-T, was chosen for this example because
of its high flux density capability. At only 2S kHz switching
frequency, a powdered-iron core has very little hysteresis
power loss and costs far less than a molypermalloy powder
core of comparable flux density capability.
The nominal Inductance of this core Is 32 mH per 1000
turns. The number of turns required for this design is found
using equation 1S:
lie 8.820 I-
28
N = 1000 x
"
18
12
0.040
~
8
-- 0,1j'D
- ....
"'"
1
Capacitor
From equation 17:
lac (A)
TLIK/5496-17
FIGURE 16. Amplifier Gain VI
Short Circuit Current and Rs
The resistors RA and Ra can be found in terms of Va. Rs.
and the amount of current foldback desired.
RA =
x
--voRa
Rs
(lcl -lsC>
1S0,...H
32 mH = 69 turns
A single layer winding of this core requires about S.1 feet of
;10 24 wire which would yield a DC winding resistance of
0.130. In this case, efficiency can be improved significantly
by using a double layer winding of ;10 20 wire with only
O.OSOO.
0
0
c:~) G) CS~HZ) (O.~A)
= 1S0 pH
28
.e
= SA
Inductor
From equation 14:
The relationship between Av. Isc. and Rs is shown in Figure
16. A small capaCitor in parallel with R2 andlor R4 may be
necessary with high amplifier gains to filter switching noise.
24
= SOmV
ICl
Isc
(21)
Isc x Rs
eo
CMIN =
( 0.5A) (
4.
1 ) (.
1
2S kHz
O.OSV - (O.SA
x ESR) V
)
S
O.OS - 0.5 ESR ,...F
Sinqe no capacitor will meet the needs of this application
with ESR > 0.10 at 2S kHz. it is easier in this case to
search for a capaCitor on the basis of ESR rather than capaCitance. Mepco/Electra part ;I0347SGD681M6P3JMBS
has a typical ESR at 2S kHz of about 0.060.
For ESR = 0.060,
(22)
«
The condition Ra
R1 should be maintained to insure accuracy in setting ICl. Typical valuelil for these resistors are:
1kO 50,..F
The complete circuit is shown in Figure 17.
150,.11
I
5 IN
0.05
OUT 8
+
2k
LHl605
80
r'
V\tj
Rt.
0.1 pi
..0 pi
2k
1.2M
1
Yo
j
TLlK/5496-18
FIGURE 17. Complete Buck Converter Using LH1605
L
OUT 8 - - -
_-----_....:5~IN
LHl605
HS
, ,..JII
"'-_--II
TLlK/5496-19
FIGURE 18. Typical Power Supply System
813
TABLE II. TYPical Component Values for Buck Regulators
fO = kHz
eO = SOmV
ESRc·
10 (MIN)
1.0A
Vo
(0)
VIN(MAX)
(V)
(V).
0.02
0.03
0.04
0.05
12
15
25
35
5
5
12
24
O.SA
LMIN
CMIN
LMIN
CMIN
(,...H)
(,...F)
(,...H)
(,...F)
Rt
(0)
59
'67
334
500
1000
117
134
250
302
125
143
167
200
2k
2k
7.6k
17.2k
125
151
Power DI~r\but\on Pre-Regulator
In applications requiring very low output ripple voltage. the
LH1605 can be used as a pre-regulator to improve system
performance and efficiency (Figure 19). By pre-regulating
the input to the linear regulators to 5.8V, line frequency ripple is virtually eliminated from the 5V output. The 25kHz
switching ripple is attenuated70 dB by the LM2931's giving
less than 1 mV total output noise.voltage.
-
DC Motor Speed Controller
Figure 20 shows how an LH1605 can be connected as a
fractional-horsepower, DC motor speed controller. The constant average output voltage of the LH1605 is set with a
single resistor, A" as it is in Buck converter applications.
Current limiting may be required to protect the LH1605 during start-up of motors with low armature resistance..
LM2931
uv
OUTI--t-~-
lDD,.F 'IiVO
WIT.
IlOmA
lIND
LM2931
Dur .......- - DND
1_
LM2931
our .......- - -
RECTIFIERS
·IDD,.F
rANT:.
IiVO·
110 mA
TlIK/5496-20
FIGURE 1.9. Pre-Regulator Power Dletdbutlon Syttem .
5 1/1
o.n ..8;....._ _...._......,
TlIK/5496-21
FIGURE 20. DC Motor Speed Regulation
the Buck converter's output power must be greater than
that of the secondaries. In the circuit of Figure 21, 10 ~ 0.8A
in the 5V primary is necessary in order to have 100 mA
capability in the ± 12V secondaries.
Multiple Outputs
It is possible, as Figure 21 suggests, to obtain any number
of outputs from a single LH 1605 provided there is one primary output in a Buck configuration drawing sufficient output current. During toFF, the voltage across the primary inductance is 1Y0 + Vf}. The voltage across any secondary
windings wound on the same core is Ns/Np (VO + Vf}.
Because Vo is regulated and VI is nearly constant, the voltages on the secondaries are also constant.
REFERENCES
1. National Semiconductor, 1982 Hybrid Products Databook.
2. National Semiconductor, "LH1605 5 Amp, High Efficiency
Switching Regulator" datasheet.
3. Abraham I. Pressman, "Switching and Linear Power Supply, Power Converter Design", Hyden Book Company,
1977.
During toN, the diodes in the secondaries are reverse biased so all secondary power comes from the filter capacitors, C1 and C2. During toFF, the diodes conduct, and the
capacitors are recharged. To ensure stable output voltages,
. . . . . --+
lm... ~
r------------t--~------~----~---+
" ":~ N ~ ""!\~ ~""''''+--+-__I- -~- --l'w.,,....
2
....
.....
.....
...
~----IV~~----~------~---.------+
N2=N3s2.6 Nl
TL/K/5496-22
FIGURE 21. Multiple Output Voltages froms Single LH1605
815
.. r----------------------------------------------------------------------------,
~
~
c(
APPENDIX A
'"
Following is a partial list of sockets, heat diSsipafors, magnetic components and low'ESR-type C41pacitors for use with the .
LH16C5. National Semiconductor Corporation assumes nei, responsibility for their quality or availability.
8·LEAD T0-3 HARDWARE
Socket.
Mfea Washers .
H~tSlnks.
Robinson Nugent .0.0.02011
Azimuth 602& (test socket)
Thermalloy 2266B (35'C/W)
.' IERC LAIC 3e4CB
IE.RC HP1-T03~33CB (7'C/W)
AAVID 5791B " .
'Keystone 4658.
AAVID ENGINEERING
3.0 Cook Court
Laconia, New Hampshire .03246
IERC
135 W. Magnolia Blvd.
Burbank, CA 915.02
ROBINSON NUGENT INC.
(ICe E. 8th St.,:.
.
New Albany, IN 4715.0
AZIMUTH ELECTRONICS
2377 S. EI camino Real
San Clemente, CA 92672
KEYSTONE ELECTRONICS CORP.
49 Bleecker St.
New York, N.Y. 1.0.012
THERMALLOY
P. O. Box 34829
Dallas, Texas 75234
MAGNETIC COMPONENTS MANUFACTURERS
Cor••
ARNOLD ENGINEERING CO.
300WestSt.
Marengo, ILL. 60152
FERROXCUBE
5038 Kings Highway
Saugerties, N.Y. 12477
Pre-Wound Inductor.
GFS MANUFACTURING CO., INC.
6 Progress Drive
Dover, N.H. .0382.0
MAGNETICS
P.O. Box 391
Butler, PA 160.01
FERRONICS, INC.
60 N. Lincoln Rd.
E. Rochester, N.Y. 14445
RENCO ELECTRONICS
6C:Jefryri Boulevard
East D.eer--Park,N.Y.11729
LOW ESR-TYPE CAPACITORS
SPRAGUE
Type 6720 Aluminum Electrolytics
Type 32DR Aluminum Electrolytics
Type 6220 Aluminum Electrolytics
MEPCO/ELECTRA INC.
Series 3428 Aluminum Electrolytics
Series 3191 Aluminum EIEiclrolytiqs ..
Series 312.0 Aluminum Electrolytics
MALLORY
Type TT Aluminum Electrolytics
Types CG/CGS/TCG Aluminum Electrolytics
SANGAMO
Type 3.01 Aluminu';' Electrolytics'
SPRAGUE
481 Marshall St.
North Adams, MA .01247
MEPcO/ELECTRA INC•.
265 Industrial Dr.
Roxboro, NC 27573
816 .
SANGAMO
P.O. Box 128
., Pickens; SC 29671'
\..
MALLORY
P. O. Box 1284
Indianapolis, IN 46206
LF13006/LF13007 Precision
Digital Gain Set
Applications
National Semiconductor
Application Note 344
Some basic circuit configurations for using the LF13006 and
LF13007 are shown in Figures 1 through 4. In each case
only the Digital Gain Set and an op-amp are required, although in some instances the amplifier may need external
compensation in order to maintain stability over wide ranges
of closed loop gain. As shown, inverting and noninverting
configurations are possible with several variations. Nearly
unlimited values of gain can be realized using different combinations of outputs and/or the additional resistors at R1,
Rc, and R2 to modify an amplifier's input or feedback.
~I- ~r- -i- -~-i~-
- -LF131116
,
~------------~En
~------...&....B"",
-1- - -1CI
DATA BUS
lUll
You,
CONTROl
LINES
Note: lR= 15 kll
TL/H/5513-1
FIGURE 1A. LF13006, GAIN = 1 to 128 In Binary Sequence
~I- ~r- -i-
-I:j-J-
LF1311O7
_ - __
-_'-.-EXT
-r-___-__ _
-1- - -1CI
DATA BUS
lUll
CONTROL
LIlIES
Note: lR=15 kll
TLlH/5513-2
FIGURE 1B. LF13007, GAIN = 1 to 100 in "1, 2, 5" Sequence
817
:
CO)
Ohignificant interest are circuits such as in Ftgum3, which
c(
tions can be useful where in-circuit trimming may be needed
: for sm.J~· narrow range adjustments. Also, by cascading two
circuits, high resolution as well as wide gain range can be
realized. For example, by using Figure 4 in conjunction with
Z: . allow gain switching at values near one. These configura-
. i"
YIH
DIGITAL
CONTROL
LF13006.
16
GAIN
ANA
GND
fA, the progr$mmed, gains of 1.2 and 1.7 can be used to "fill
. in" betWeen the binary steps supplied by1A. In audio applications, this particular arrangement. would provide steps of
3 dB or less over a 46 dB range arid slightly larger steps to
57 dB.
=
010 -127
DIGITAL
CONTROL
LFI3006
LF131107
LF13007,
GAIN
=
R
010 -99
2 INPUT
R
14
15
AoUT
TL/H/5513-4
FIGURE 2A. High Input Impedance Inverting Mode
TLlH/5513-3
FIGURE 2. Inverting Mode
GAIN (LF13006)
GAIN (LF13007)
11
9
1.8
3.67
1.83
1.29
1.125
1.059
1.029
1.014
1.007
1.2
1.1
1.048
1.02
1.01
YoU!
16
ANA
INO
15
LFI3006
LFI3007
TLlH/5513-6
INPUT
FIGURE 4. Altered Gain Range
13
DIGITAL
CONTROL
AOUT
12
TLlH/5513-5
FIGURE 3. Variable Gains of Almost 1
818
Circuit operation of the variable low pass is very straightforward. The LF1300S Network along with an LF412 dual opamp form a resistance "multiplier" in which a settable fraction of the input voltage is used to determine the charge or
discharge current though R into Cl. One half of the dual
amplifier (Al) is used to buffer the LF1300S's "output" (Input, pin 2) and provide charging current for Cl, while the
second op-amp (A2) allows the resistor ladder to float on
Cl. In addition, the ratio of the selected time-constants will
be very precise since these will be proportional to the
LF13006's gain accuracy.
To a similar end, a classical capacitance multiplier can be
made programmable with the circuit of Figure 6. The Digital
Gain Set controls what is in effect a high input-impedance
inverting amplifier which is used to drive the lower side of
Cl. The value of the "virtual" capaCitor seen at the circuit's
input will be Cl multiplied by the programmed gain. A drawback of this scl)eme is that the signal swing at Al's output
can be large and may cause amp!ifier saturation. Thus for
high capaCitance multiplication factors, the input swing must
be kept small in order to prevent clipping.
Applications for these devices also include a wide variety-of
circuits besides those which simply switch op-amp gain. A
simple digital "handle" on one or more other circuit parameters can do a great deal to enhance the capabiliti~ of many
analog designs. In circuits such as, filters, precision references, current sources, and countless others, the addition
of programming capability can be invaluable.
One good example of such versatility is shown in a digitally
adjustable low pass filter in Figure 5. Applications for this
function include variable bandwidth front-ends for data acquisition and "smart" filters for DC signals which combine
fast settling with high noise rejection. This can be done by
increasing bandwidth in the presence of a large input-to-output differential at the filter, and then cutting back as the
output gets close to its final level. The corner frequency is
easily set via the 3-bit code input to an LF13006 or i When
using the ,LF13006, time const&nts from RxCl to 128RxCl
can be programmed in binarily weighted steps. The, same
function performed with a conventional CMOS DAC would
need more bits to covar Ute same range and would still not
be able to maintain the precision of setting at its limits of
operation.
TIme Constant t = NRCI
N = Set galn in basic configuration (N
Ceffective = CIN
N = GAIN of Fig 1
= GAIN of Fig 1)
Nota: Output swing at Input op amp is multiplied by
set gain. Signal range
may be limited.
IN
12
AOUT
15
LF131106
LF13007
14
2 INPUT
13
C1
ANA
aND
16
DIGITAl
CONTROL
TL/H/5513-7
FIGURE 5. Variable Time Constant FiRer
TLlH/5S13-8
FIGURE
819
e. Variable Capacitance Multiplier
In Figure 7, an LF13006 is used to switch a single amplifier'S
gain but not quite in the conventional sense in this case.
The LF411 op-amp can be flipped from a' follower to an
inverter using no additional parts· and only the "Dig. In 1"
input (pin 8) of the gain network. This "two part" approach
can be used in preCision rectifier and synchronous modulator/demodulator circuits as well as for polarity inverters in
front of A to 0 converters.
The two extra matched resistors that are provided at R1,
R2, and Rc (pins 13, 14, 15) are used to set the inverter gain
while two of the internal switches are Configured to switch
the op-amp's noninverting input. The 8R resistor (apprOXimately 120K) which exists from the circuit input to ground is
not actually needed but is an unavoidable result of this particular switch connection.
In another example, a precision current source can be given
direct digital control by using the simple Scheme shown in
Figure 8. Here, the current source's reference is "floated"
on the load terminal (lOUr) by using one half of a BI-Fet c;lual
op-amp (LF412, A1) as a buffer for the output. This provides
a current return path for the gain set's resistor ladder and
the circuit's reference (LM385-1.2) which doesn't interfere
with the main output. The other half of the Bi-Fat dual (A2) is
used to supply the output current via the sense resistor, R1.
The current SOurce's output is varied by changing the fraction of the reference voltage which will be forced to appear
across R1. With this scheme, the output current is governed
by the equation; lOUT = VREF/(R1 x Set Gain);
Applications for the above circuit include bias sources for
programmable amplifiers, linear ramp' generatorS, and'variable current limiters. For greater output currents, R1 can be
reduced and an external pass transistor can be added to
A2's output.
A common need in data acquisition systems is for a differ'
entlallnpilt 'amplifier, or instrumentation amplifier, with easily
adjustable precision gains. Normally this can't be done without using several preciSion resistors and switches or employing expensive inodular products that have this capability
already built in. In Figure 9, a differential gain can be varied
~y using one Digital Gain Sat in one version of a three opamp Instrumentation amp circuit: The amplifier's front end
uses an LF412A precision dual op-amp as a follower (A1)
and also
a vanable gain inverter (A2), both which drive
the inputs of a fixed gain cflfference amp (LF411). The instrUmentation amp's common-mOde 'perforrnancewill directly depend on the four' external resistors. For designs
where common-mode rejection is critical, close matching of
resistor pairs R1, R2 and R3, R4 are required, i.e. 60 dB DC
CMRR requires 0.1 % matching. However, reasonable rejection can still be achieved (54 dB typ) if only two external
resistors are used and the gain set's uncommitted resistors
serve as R1 and R2.
as
15V
lOUT -
3Dk
DIGITAL
CONTROL
N
1~~ (~)
= GAIN'of Fig 1
AOUT
LF13006
LF130D7
YouT
LM385·UV
TLlH/5613-9
FIGURE 7. Swltchable Gain of ± 1
TLlH/5613-10
FIGURE 8. Programmable Current Source
820
In Figure 10, the programmable function generator shown
will shift its operating frequency one octave for each LSB
change in the program code. Triangle square-wave and
sinewave outputs are available over an eight octave range.
If an LF13007 were to be used rather than the 13006, the 1,
2, 5 sequence would provide ideal scaling for horizontal
sweep or other scanning circuits.
This particular function generator employs 3,4 of a quad opamp as an integrator, comparator, and buffer. The integrator
(A1) is driven from a controllable source which is simply the
Digital Gain Set used as a passive voltage divider, and buffered by A2. The triangle output from A 1 is used to drive a
sine shaping circuit consisting of the last quarter of the
LF347 (A4) and two dual transistors. Sine distortion can be
reduced to 0.5% by trimming the symmetry and waveshape
adjustments provided. The circuits' frequency range as
shown is from 10 to 1280 Hz.
Note 1: R" R2. Ra. R4 = 15k
Note 2: For 46 dB min CMRR. R,. R2 can be replaced by intemal resistors
in the LF1300617
Note 3: For 60 dB CMRR R,. R2 and Ra. R4 musl match to 0.1%
Note 4: VOUT = N(VA - Ve)
N = GAIN of Fig 1
H1
AoUT
12
HZ
H3
YoUT
DIGITAL
CONTROL
INPUT
VA--------I
112 LF412A
TLlH/5513-11
FIGURE 9. Programmable Instrumentation Amp
10k
16V
rv
SYMMJ~ I;+--'w..~. . _--r
SINE WAVE
OUTI'tJT
TRIMf
-'5V
Note 1: A'-4 LF347
Note 2: Adiust waveshape and symmetry trims for lowest output
distortion on sinewave
Note 3: Range 10 to 1280 HZ
-15V
FIGURE 10. One Octave per Bit Function Generator
821
TLlH/5513-12
~
~
Hlgh-Performaoce Audio'
Applications of TheLM833
National Semiconductor
Application Note 346
Kerry Lacanette .
Designers of quality .audio equipment have long recognized
the value of a low noise gain block with "audiophile performance". The LM833 is such a device: a dual operational amplifier with excellent audio specifications. The LM833 features low input noise voltage (4.5 nV/.JF1z typical), large
gain-bandwidth product (15 MHz), high slew rate
(7V ,,,,,Sec), low THO (0.002% 20 Hz-20 kHz), and unity gain
stability. This Application Note describes some of the ways
in which the LM833 can be used to deliver improved audio
performance.
Figurs 1 shows the standard RIM phono preamplifier amplitude response. Numerical values relative., to the 1 kHz
gain are given in Table I, Note that the gain rolls off at
6 dB/octave rate above 2122 Hz. Most phono preamplifier
circuits in commercially available audio products, as well as
most published circui~, are based on the topology shown in
Figurs 2(a). The network consisting of R1, R2, C1, and C2 is
not unique, and can be replaced by any of several other
networks that give equivalent results. Ro is generally well
under 1k to keep its contribution to the input noise voltage
below that of the cartridge itself. The 47k resistor shunting
the input provides damping for moving-magnet phono cartridges. The input is also shunted by a capacitance equal to
the sum of the input cable caPacitance and Cpo This capacitance resonates with the inductance of the moving magnet
cartridge around 15 kHz to 20 kHz to determine the frequency response of the transducer, so when a moving magnet
pickup is used, Cp should be carefully chOsen so that the
total capaCitance is equal to the recommended load capitance for that particular cartridge.
I_ TWO STAGE RIAA PHONO PREAMPLIFIER
A phono preamplifier's primary task is to provide gain (usually 30 to 40 dB at 1 kHz) and accurate amplitude and phase
equalization to the signal from a moving magnetor a moving
coil cartridge. (A moving coil device's output voltage is typically around 20 dB lower than that of a moving magnet pickup, so this signal is usually amplified by step-up deviceeither an active circuit or a transformer-before being applied to the input of the phono preamplifier). In addition to
the amplification and equalization functions, the phono
preamp must not add significant noise or distortion to the
signal from the cartridge.
a
21
20
i
III
~
15
1.
5
-:
a
I""'"
~
I....
1-10
-15
-II
-21
I~
I"'
20 101ID_.lk 2k 1Ik'0,.fREQUStCY (HzI
TVHI5520-1
FIGURE 1. Standard RIAA phonograph preamplifier frequency response curve.
Gain continues to roll off at a 6 dB/octave rate above 20 kHz.
FREQUENCY (Hz)
20
30
40
50
60
80
100
150
200
300
400
500
Table I. RIAA standard response referred to gain at 1 kHz.
AMPLITUDE (dB)
FREQUENCY (Hz)
+19.3
800
1000
+18.6
+17.8
1500
2000
+17.0
+16.1
3000
+14.5
4000
+13.1
5000
' +10.3
6000
+8.2
8000
+5.5
10000
+3.8
15000
+2.6
20000
822
AMPLITUDE (dB)
+0.7
0.0
-1.4
-2.6
-4.8
-6.6
-8.2
-9.6
-11.9
-13.7
-17.2
-19.6
The circuit of Figure 2(a) has a disadvantage: it cannot accurately follow the curve in Figure 1, no matter what values
are chosen for the feedback resistors and capacitors. This
is because the non-inverting amplifier cannot have a gain of
less than unity, which means that the high frequency gain
cannot roll off continuously above the 2122 Hz breakpoint
as it is supposed to. Instead, a new breakpoint is introduced
at the unity gain frequency.
response curve Since the absolute value of its gain can be
less than unity. The reduced level of ultrasonic information
at its output will sometimes result in lower perceived distortion (depending on the design of the other components in
the audio system). Since there is no voltage swing at the
preamplifier input, distortion will be lower in cases where the
gain block has poor common-mode performance. (The
common-mode distortion of the LM833 is low enough that it
exhibits essentially the same THO figures whether it is used
in the inverting or the non-inverting mode.)
The primary handicap of the inverting configuration is its
noise performance. The 47k resistor in series with the
source adds at least 4 /lo V of noise (20 Hz to 20 kHz) to the
preamplifier's input. In addition to 4 p.V of thermal noise
from the 47k resistor, the high impedance in series with the
preamp input will generally result in a noise increase due to
the preamplifier's input noise current, especially when the
series impedance is made even larger by a moving magnet
cartridge at resonance. In contrast, the 47k damping resistor in Figure 2(a) is in parallel with the source, and is a
significant noise contributor only when the source impedance is high. This will occur near resonance, when the
source is a moving magnet cartridge. Since the step-up devices used with moving coil cartridges present a low, primarily resistive source impedance to the preamplifier input, the
effects of cartridge resonance and input noise current are
virtually eliminated for moving coil sources. Therefore, the
circuit of Figure 2(a) has a noise advantage of about 16 dB
with a moving coil source, and from about 13 dB to about
18 dB (depending on the source impedance and on the input noise current of the amplifier) with a moving magnet
source. Using the component values shown, the circuit in
Figure 2(a) follows the RIAA characteristic with an accuracy
of better than 0.5 dB (20-20 kHz) and has an input-referred
noise voltage equal to 0.33 /loY over the Audio frequency
range.
Even better performance can be obtained by using the twoamplifier approach of Figure 3. The first operational amplifier takes care of the 50 Hz and 500 Hz breakpoints, while
the 2122 Hz rolloff is accomplished by the passive network
R3, Rs, and C3. The second amplifier supplies additional
gain-10 dB in this example. Using two amplifiers results in
accurate conformance to the RIM curve without reverting
to the noisy inverting topology, as well as lower distortion
due to the fact that each amplifier is operating at a lower
gain than would be the case in a single-amplifier design.
Also, the amplifiers are not required to drive capacitive feedback networks with the full preamplifier output voltages, fur-
In addition to the amplitude response errors (which can be
made small through careful design), the lack of a continued
rolloff can cause distortion in later stages of the audio system by allowing high frequency signals from the pickup cartridge to pass through the phono equalizer without sufficient
attenuation. This is generally not a problem with moving
magnet cartridges, since they are usually severely band-limited above 20 kHz due to the electrical resonance of cartridge inductance and preamp input capacitance. Moving
coil cartridges, however, have very low inductance, and can
produce significant output at frequencies as high as
150 kHz. If a subsequent preamplifier stage or power amplifier suffers from distortion caused by slew-rate limitations,
these ultrasonic signals can cause distortion of the audio
signal even though the signals actually causing the distortion are inaudible.
Preamplifers using the topology of Figure 2(a) can suffer
from distortion due to input stage nonlinearities that are not
corrected by the feedback loop. The fact that practical amplifiers have non-infinite common mode rejection ratios
means that the amplifier will have a term in its gain function
that is dependent on the input voltage level. Since most
good operational amplifiers have very high common mode
rejection ratios, this form of distortion is usually quite difficult
to find in opamp-based designs, but it is very common in
discrete amplifiers using two or three transistors since these
circuits generally have poor common mode performance.
Another source of input stage distortion is input impedance
nonlinearity. Since the input impedance of an amplifier can
vary depending on the input voltage, and the signal at the
amplifier input will be more strongly affected by input impedance if the source impedance is high, distortion will generally increase as the source impedance increases. Again, this
problem will typically be significant only when the amplifier
is a simple discrete deSign, and is not generally troublesome
with good op amp deSigns.
The disadvantages of the circuit configuration of Figure 2(a)
have led some designers to consider the use of RIM preamplifiers based on the inverting topology shown in Figure
2(b). This circuit can accurately follow the standard RIAA
VIN - . - -....----1
>-.......-YauT
81
1M
R2
12M
110
390
ca
T
>-~VDUT
'OOpf
w
TLiH/5520-16
TLiH/5520-2
~
FIGURE 2. Two typical operational amplifier-based phonograph preamplifier circuits. (a) Non..Jnverting. (b) Inverting.
823
. '
3.18 X 10-3
4) Calculate Cl =.
R
ther reducing distortion compared to the single-amplifier designs.
The design equatioris for the preamplifier are:
1)
2)
'
Rl = 8.058 RoAl, where Al is the 1 kHz voltage gain
of the ~rst: amplifier.
3.18 x 10-3
Cl =~:....",....:..:....Rl '
R
5)
'
3) R2=-1-RO
9
4)
1
3.18 X 10-3
Exam Ple:,Cl ~ 8.058 x 104 = 0.03946 p.F
If Cl is not a convenient value, choose the nearest
convenient value and calculate a new Rl from
3.18 x 10-3
Rl =.:.:..:.~:--', Cl
Example: New Cl = 0.039 p.F.
, 3.18 X 10-3,
New Rl = 3.9 X 10- 8 = 81.54k
_.
,_s(R3 + Rs) _ 7.5 X 10-S
C3 - 7.5 X 10
R3 RS Rp
1
C4 = -:-:::---::--:2'1rfL (R3 + Rs)
where fL is the low-frequency -3 dB comer of the second stage. For'standard RIAA preamplifiers, fl. should
be kept well below the audible frequency ran!;ie. If the
preamplifier is to follow the IEC recommendation (lEC
Publication 98, Amendment #4), fL should equal
20.2 Hz.
,
Rs
6) AV2= 1 +R4
where AV2 is the voltage gain of the second amplifier.
Use Rl = 80.6k.
5)
Rl
6) Calculate a new value for Ro from Ro = 8.058AVl
8.06 X 104
Example: New Ro = 8.058 x 20 = 498.8.
Use Ro = 499.
7) calculate R2 =
Example: R2 =
1
7) Co:::: 2'1rfoRo
Rl
9"
-
Ro
8.06 X 104
9
- 499 = 8456.56
Use 8.45k.
8)
where fo is the low-frequency - 3 dB corner of the first
amplifier. This should be kept well below the audible
frequency range.
ChOose a convenient value for C3 in the range from
0.01 p.F to 0.05 p.F.
Example: C3 = 0.033 p.F.
7.5 x 10-S
9) Calculate Rp =
Ca
A deSign procedure is shown below with an illustrative example using 1 % tolerance E96 components for close conformance to the ideal RIAA curve. Since 1% tolerance capaCitors are often difficult to find except in 5% or 10% standard values, the design procedure calls for re-calculation of
a few component values so that standard capacitor values
can be used.
7.5 X 10-s
Example: Rp = 3.3 X 10 8 = 2.273k.
10) Choose a standard value for R3 that is slightly larger
than Rp.
Example: R3 = 2.37k.
RIAA PHONO PREAMPLIFIER DESIGN PROCEDURE
11) Calculate Rs from 1/Rs = 1IRp - 1/R3
1)
Example: Rs = 55.36k
Use 54.9k.
Choose Ro. Ro should be small for minimum noise contribution, but not so small that the feedback network
excessively loads the amplifier.
'
12) Calculate C4 for low-frequency rolloff below 1 Hz from
design equation (5).
Example: Choose Ro = 500.
2)
Choose 1 kHz gain, AVl of first amplifier. This will typicaily be around 20 dB to 30 dB.
Example: C4 = 2 p.F. Use a good quality mylar, polystyrene,
or polypropylene.
Example: Choose AVl = 26 dB =:,20.
3) CalculateRl = 8.058RoAvl
Example: Rl = 8.058 X 500 x 20 = 80.58k.
13) Choose gain of second amplifier. '
1&V
1/2LM133
v.~~
__~______~3~~~
>~-'Y\t\r-"'"
R4
2k
H8
Uk
FIGURE 3. Two-amRllfier RIAA phono preamp,!fler with very accurate RIM response.
824
Table 11_ Equivalent Input noise and slgnal-ta-nolse ratiO
for RIAA preamplifier circuit of Flgurtl 3_ Noise levels
are referred to gain at 1 kHz_
Example: The 1 kHz gain up to the input of the second
amplifier is about 26 dB for this example. For an overall 1
kHz gain equal to about 36 dB we choose:
AV2 = 10 dB = 3.16.
NOISE WEIGHTING
14) Choose value for A4'
Example: A4 = 2k.
Noise voltage
CCIR/ARM
"A"
FLAT
0.26 p.V
0.23 p.V
0.37/LV
86dB
87 dB
82 dB
15) Calculate As = (AV2 - 1) A4
Example: As = 4.32k.
Use As = 4.3k
SIN referred to
5 mV input at 1 kHz
16) Calculate Co for low-frequency rolloff below 1 Hz from
design equation (7).
LOUDSPEAKERS
A typical multi-driver loudspeaker system will contain two or
more transducers that are intended to handle different parts
of the audio frequency spectrum. Passive filters are usually
used to split the output of a power amplifier into signals that
are within the usable frequency range of the individual drivers. Since passive crossover networks must drive loudspeaker elements whose impedances are quite low, the capacitors and inductors in the crossovers must be large in
value, meaning that they will very likely be expensive and
physically large. If the capacitors are electrolytiC types or if
the inductors do not have air cores, they can also be significant sources of distortion. Futhermore, many desirable filter
characteristics are either impossible to realize with passive
circuitry, or require so much attenuation to achieve passively that system efficiency is severely reduced.
II. ACTIVE CROSSOVER NETWORK FOR
Example: Co = 200 p.F.
The circuit of Figure 3 has excellent performance: Conformance to the AIAA curve is within 0.1 dB from 20 Hz to 20
kHz, as illustrated in Figure 4 below for a prototype version
of the circuit. THD and noise data are reproduced in Figure
5 and Table II, respectively. If a "perfect" cartridge with
1mV/cm/s sensitivity (higher than average) is used as the
input to this preamplifier, the highest recorded groove velocities available on discs (limited by the cutting equipment) will
fall below the 1V curve except in the 1 kHz to 10kHz region,
where isolated occurances of 2V to 3V levels can be generated by one or two of the "superdiscs". (See reference 4).
The distortion levels at those frequencies and signal levels
are essentially the same as those shown on the 1V curve,
so they are not reproduced separately here. It should be
noted that most real cartridges are very limited in their ability
to track such large velocities, and will not generate preamplifier output levels above 1Vrms even under high groove
velocity conditions.
2.0 r-r-r-r---r-r--r--r--r--,
An alternative approach is to use lOW-level filters to divide
the frequency spectrum, and to follow each of these with a
separate power amplifier for each driver or group of drivers.
A two-way (or "bi-amped") system of this type is shown in
Figure 6. This basic concept can be expanded to any number of frequency bands. For accurate sound reprodUction,
the sum of the filter outputs should be equal to the crossover input (if the transducers are "ideal"). While this seems
to be an obvious requirement, it is very difficult to find a
commercial active' dividing network that meets it. Consider
an active crossover consisting of a pair of 2nd-order Butterworth filters, (one is a low-pass; the other is a high-pass).
The transfer functions of the filters are of the form:
1.• ,,""""H-+--+-+--+--+--+--I
1.0 I-H-+--+-+--+--+--+--I
i 0.5 I-H-t--+-+-+--++--1
-
a 1".ooI~_.-I"""""""ojII!!I
1-0.5 I-H-+--+-+--+--+--+--I
I-H-+--+-+--+--+--+--I
-1.5 I-H-+--+-+--+--+--+--I
-1.8
-2.0
L-L-I---I.--I---L~---L-J...-'
20 50 100 20D 500 lk 2k 5k 10k ZGk
FREQUENCY (~J
TLlH/5520-4
FIGURE 4_ Deviation from Ideal RIAA response for
circuit of Figure 3 using 1% resistors_ The maximum
observed error for the prototype was 0.1 dB_
g
0.1
z
0.05
i
0.02
!
~
0.01
0•0115 1
z
~
and their sum is:
0.002
0.001
-
=
r=llr~~ ~
¥aUT 300 mVrm.
J..-r'[
20 50 100 200 500 lk 2k 5k 10k 20k
FREQUENCY (HI'
WOOfEII
Tl/H/5520-5
TLlH/5520-6
FIGURE 5_ THO of circuit In Figure 3 as a function of
frequency_ The lower curve is for an output level of
300mVrms and the upper curve Is tor an output level of
1Vrms.
FIGURE 6. Block diagram of a twa-way loudspeaker
system using a low level crossover network ahead of
the power amplifiers.
825
tave. The input impedance is equal to R/2, or 12 kO in the
circuit of Figure 9. The LM833 is especially well-suited for
active filter applications because of its high gain-bandwidth
product. The transfer functions of this crossover network
are of the form
The output will therefore never exactly equal the input signal
(exceptin the trivial case of a DC input). Figure 7 shows the
response of this crossover to a square wave input, and the
amplitude and phase response ofthe crossover tOosin!Jsoidal steady state inputs can be seen in Figure 8. Higher-order filters will yield similarly dissatisfying results when this
approach is used.
VL(S) =
Vin(S)
Il3S3
A significant improvement can be made by the use of a
constant voltage crossoverolike the one shown in Figure 9.
The term "constant voltage" means that the outputs of the
high-pass and low-pass sections add up to prooduc9 oan exact replica of the input signal. The rolloff rate is 12' dBI oc-
als + 1
+ a2s2 + als + 1
and
VH(S) =
a3s3 + a2s2
Vin(S)
a3s3 + a2s2 + a,s
+1
t· 1\
I
I
......
II
"
!'-
- --- -
-A
Tc
DME
TL/H/5520-7
FIGURE 7. Response of second-order Butterworth crossover network (high-pass and low-pass outputs summed) to a
square wave input (dashed line) at the crossover frequency. Period is Te = 1Ife.
iii'
:!!.
III
i
225
188
21
20
15
1.
5
•
-5
-10
-1'
-20
~
, .....
131
II
110
41
o
-41
-ID
~
"'"
-1311
-180
'"-,
"
ID
~21
20 50 100 200 8D01k Zk 5k 10k 20k
FRalUENCY (Hzl
TLlH/5520-8
20 88 1DO 200 1IOII1k 2k 5k 10k 20k
FllEllUSiCY (HzI
TLlH/5520-17
(a)
(b)
FIGURE 8. Magnitude (a) and phase (b) response of a second-order. 1 kHz Butterworth
crossover network with the high·pass and low-pass outputs summed. The Individual high-pass
and low-pass outputs are superimposed (dashed lines).
TLlH/5520-9
FIGURE 9. Constant-voltage crossover network with 12 dB/octave slopes.
o
1
The crossover frequency Is equal to 2'ITRC'
826
It is important to remember that even a constant voltage
crossover transfer function does not guarantee an ideal
overall system response, because the transfer functions of
the transducers will also affect the overall response. This
can be minimized to some extent by using drivers that are
"flat" at least two octaves beyond the crossover frequency.
The low-pass and high-pass constant voltage crossover
outputs are plotted in Figure 10. The square-wave response
(not shown) of the summed outputs is simply an inverted
square-wave, and the phase shift (also not shown) is essentially O· to beyond 20 kHz.
21
i
III
28
11
10
5
i -:
-10
-15
-28
-II
III. INFRASONIC AND ULTRASONIC FILTERS
In order to ensure "perfectly flat" amplitude response from
20 Hz to 20 kHz, many audio circuits are designed to have
bandwidths extending far beyond the audio frequency
range. There are many high-fidelity systems, however, that
can be audibly improved by reducing the gain at frequencies
above and below the limits of audibility.
'"
" ",
J
L
The phonograph arm/cartridge/disc combination is the
most significant source of unwanted low-frequency information. Disc warps on 33% rpm records can cause large-amplitude signals at harmonics of 0.556 Hz. Other large lowfrequency signals can be created at the resonance frequency determined by the compliance of the pickup cartridge
and the effective mass of the cartridge/arm combination.
The magnitude of undesireable low-frequency Signals can
be especially large if the cartridge/ arm resonance occurs
28 10100D 1IOII1k Zk Ilk 10k 2tIk
FRBlUENCY (Hzl
TLIH/5520-10
FIGURE 10. Low~pass and high-pass responses of
constant-voltage crossover network In FIgure 9 with
crossover frequency of 1 kHz. For the circuit of
Figure 9, a, = 4, a2 = 4, and a3 = 1. Note that the summed
response (dashed lines) Is perfectly flat.
90.911
0.33
0.33
~1r-
~'_,7--,.-_VOUT
Tl/H/5520-11
FIGURE 11. Filter for rejection of underslreable Infrasonic signals. Filter characteristic Is thlrd-order Butterworth with
- 3 dB fraquency at 15 Hz. Resistor and capacitor values shown ara for 1% tolerance components. 5% tolerance units
can be substituted In less critical applications.
VOUT
TLlH/5520-12
FIGURE 12. Ultrasonic rejection filter wltl1 fourth-order Bessellow-pass characteristic. The filter gain is down 3 dB at
about 40 kHz. As with the Infrasonic filter, 1% tolerance components should be used for accurate response.
827
U) ~~----~--------~------------------~------------~----------------------------,
i
at a warp frequency. InfraSonic signals can sometimes overload amplifiers; and even 'in the absence of amplifier overload can cause,large woofer excursions, .resulting in audible
distortion and even woofer damage. '
Ultrasonic'slgnals tend to Cause problems in 'power amplifiers when the amplifiers exhibit distortion mechanisms due
to slew rate'Umitations and other high frequency ,",onlinearities. The, most troublesome high-frequency signals ,come
principally from moving..poil cartridges a~d sometimes from
tape recorders if their bias oscillator outputs manage to get
into the audio signal path. Like the infrasonic signals, ultrasonic signals can place distortion products in the audio
band even though the offending signals themselves are not
audible.
The circuits in Figures 11 and' 12 attenuate out-of-band signals while having minimal effect on the audio prOgram. The
infrasonic filter in Figure 11 is a third-order Butterworth highpass with its -3 dB frequency at 15 Hz. The attenuation at
5 Hz is over 28 dB, while 20 Hz information is reduced by
only 0.7 dB and 30 Hz information by under 0.1 dB.
The ultrasonic filter in Figure 12 is a fourth-order Bessel
alignment, giving excellent phase characteristic:s. A Bessel
filter approximates a delay line within its passband, so complex in-band signals are passed through the filter with negligible alteration of the phase relationships among the various in-band signal frequencies. The circuit shown is down
0.65 dB at 20 kHz and -3 dB at about 40 kHz. Rise time is
limited to about 8.5 I£Sec.
The high-pass and low-pass filters exhibit extremely ,low
THD, typically under 0.002%. Both circuits must be driven
from low Impedance sources (preferably under 100 ohms).
5% components will often yield satisfactory reSUlts, but 1 %
values will keep the filter responses accurate and minimize
mismatching between the two channels. The amplitude response of the two filters in cascade is shown In Figure 13.
When the two filters are cascaded, the low-pass should precede the high-pass.
10~~~~-r~~~~
5 ~~~~~~~++~
•
i
•
H-~~+-+'t"t'++Ok-H
-1'
~-I+t+++~+iHH-f\I
-5~rft+++~~HH~
5::
1+-It+I+H-H-+t+-H
i ~++~~~~~++~
-21
-:18 H-i1+t+++~+iHHr-H
-35
1-HH-t+++~+iHHr-H
-41 .................................................................
IIOI.,k,01e,D
FREGUENCY (Hz)
Tl/H/5520-13
FIGURE 13. Amplitude response of Infrasonic
and ultrasonic flltera connected In series.
IV. TRANSFORIIjIERLESS MICROPHONE
PREAMPLIFIERS
Microphones used in professional applications encounter
an extremely wide dynamic range of input sound pressure
levels, ranging from about 30 dB SPL (ambient noise in a
quiet room) to over 130 dB SPL. The output voltage of a low
impedance (200 ohm) microphone over this range of SPLs
might typically vary from 20 1£V to 2V rms, while its self-generated output noise would be on the order of 0.25 p.V over a
20 kHz bandwidth. Since the microphone's output dynamic
range il! so large, a preamplifier for microphone signals
should have an adjustable gain so that it can be optimized
fof the Signal levels that will be present in a given situation.
Large signals should be handled without clipping or excessive distortion, and small signals should not be degraded by
preamplifier noise.
R2
2Gk
Ht,
101e
1IIL• •
Z
YauT
HI
1111
":'
TLlH/5520-14
FIGURE 14. Simple transformerleas microphone preamplifier using LM833. R,. R2.
and R3 are 0,1 % tolerance units (or R2 can be trimmed).
828
.--------------------------------------------------------------------.~
For a conservative low noise design, the preamplifier should
contribute no more noise to the output signal than does the
resistive portion of the source impedance. In practical applications, it is often reasonable to allow a higher level of input
noise in the preamplifier since ambient room noise will usually cause a noise voltage at the microphone output terminals that is on the order of 30 dB greater than the microphone's intrinsic (due to source resistance) noise floor.
and .002% at minimum gain. For more critical applications
with lower sensitivity microphones, the circuit of Figure 15
uses LM394s as input devices for the LM833 gain stages.
The equivalent input noise of this circuit is about 2.4
nv/y'Hz, at maximum gain, resulting ,in a 20 Hz to 20 kHz
input noise level of 340 nV, or -129 dB referred to 1V.
In both circuits, potentiometer R4 is used to adjust the circuit gain from about 4 to 270. The maximum gain will be
limited by the minimum resistance of the potentiometer. If
R1, R2, and Rs are all 0.1 % tolerance units, the rejection of
hum and other common-mode noise will typically be about
60 dB, and about 44 dB worst case. If better common-mode
rejection is needed, one of the R2S can be replaced by an
18k resistor and a 5k potentiometer to allow trimming of
CMRR. To prevent radio-frequency interference from getting into the preamplifier inputs, it may be helpful to place
470 pF capacitors between the inputs and ground.
When long cables are used with a microphone, its output
signal is susceptable to contamination by external magnetic
fields-especially power line hum. To minimize this problem,
the outputs of most professional microphones are balanced,
driving a pair of twisted wires with signals of opposite polarity. Ideally, magnetic fields will induce equal voltages on
each of the two wires, which can then be cancelled if the
signals are applied to a transformer or differential amplifier
at the preamplifier input.
The circuits in Figures 14 and 15 are transformerless differential input microphone preamplifiers. Avoiding transformers has several advantages, including lower cost, smaller
physical size, and reduced distortion. The circuit of Figure
14 is the simpler of the two, with two LM833s amplifying the
input signal before the common-mode noise is cancelled in
the differential amplifier. The equivalent input noise is about
760 nV over a 20 Hz to 20 kHz frequency band (-122 dB
referred to 1V), which is over 26 dB lower than a typical
microphone's output from the 30 dB SPL ambient noise level In a quiet room. THO is under .01 % at maximum gain,
References:
1) S. P. Lipshitz, J. Audio Eng. Soc., "On RIAA Equalization
Networks", June 1979.
2) P. J. Baxandall, J. Audio Eng. Soc., Letter, pp47-52, Jan
1981.
3) Ashley and Kaminsky, J. Audio Eng. Soc., "Active and
Passive Filters as Loudspeaker Crossover Networks", June
1971.
4) T. Holman, Audio, "Dynamic Range Requirements of
Phonographic Preamplifiers", July 1977.
11V
Uk
I8tI
1180
1/2LM183
2
TLlH/5520-15
FIGURE 15. Transformerless microphone preamplifier similar to that of Figure 14,
but using LM394s aslow·nolse input stages.
829
z
W
~
(ix) is equivalent to design equation (3) on page three.
Combining (vjand (ix), '
APPENDIX I: DERIVATION OF RIAA'PHONO'PREAMPLI"
FIERQESIGN EQUATIONS (1), (2), Ato!D (3).
The flrsfthre& design equations 'on the third page are derived here. The derivations of the others should'be apparent
by observatiOn. The purpose of thepreamplifier's'first stage
is to produce tile transfer function: ' "
, ' '
, '(3.18X 10- 4 + 1) "
(i)
Av(s) "" Av(dc) (3.18 x 10 3 + 1)
~v(dC)=
Ro +,~' + R2 =Ad 1 + 1/9)"
(x)
,
Ro,
Ro
Finally, solving forR, and using Av(dc) = 8.9535Av (1 kHz)
yields:
RoAv(dc)'
"
,
R, =~=0.9RoAV B or Dolby C type noise reduction. A scant few have different systems such as dbx or Hi-Com. The universal appeal of compandors to n.r. system designers is the amount of noise
reduction they can offer, yet one of the major reasons the
Dolby B system gained dominance in the consumer marketplace is because it offered only a limited degree of noise
reduction - just 10 dB. This was sufficient to push cassette
tape noise down to the level where it became acceptable in
good-quality applications, yet wasn't enough that undecoded playback on machines not equipped with a Dolby B system was unsatisfactory - quite the contrary, in fact. The h.f.
boost on Dolby B encoded tapes when reproduced on systems with modest speakers was frequently preferred. Since
companding systems are so popular, it is not unreasonable
to ask, "why do we need another noise reduction system?"
For many of the available audio sources today, compandors
are not a solution for audio noise. When the source material
is not encoded in any way and has perceptible noise, complementary noise reduction is not possible. This includes
radio and television broadcasts, the majority of video tapes
and of course, older audio tape recordings and discs. The
DNRTM single-ended n.r. system has been developed specifically to reduce noise in such sources. A single-ended
system, able to provide noise reduction where non previously existed, and which avoids compatability restraints or the
imposition of yet another recording standard for consumer
equipment, is therefore attractive.
The DNR system can be implemented by either of two Integrated circuits, the LM1894 or the LM832, both of which can
offer between 10 and 14 dB noise reduction in stereo pro-
gram material. Although differing in some details (the
LM832 is designed for low-signal, low-supply voltage applications) the operation of the integrated circuits is essentially
the same. Two basic principles are involved; that the noise
output is proportional to the system bandwidth, and that the
desired program material is capable of "masking" the noise
when the signal-to-noise ratio is sufficiently high. DNR automatically and continuously changes the system bandwidth
in response to the amplitude and frequency content of the
program. Restricting the signal bandwidth to less than 1 kHz
reduces the audible noise and a special spectral weighting
filter in the control path ensures that the audio bandwidth in
the signal path, is always increased sufficiently to pass any
music that may be present. Because of this ability to dynamically analyze the auditory masking qualities of the program
material, DNR does not require the source to be encoded in
any special way for noise reduction to be obtained. This
paper deals with the design and operating characteristics of
the LM1894. For a more complete description of the principles behind the DNR system, refer to AN384.
THE DNR SYSTEM FORMAT
A block diagram showing the basic format of the LM1894 is
shown in Fl9uf8 1. This is a stereo system with the left and
right channel audio Signals each being processed by a controlled cut-off frequency (L3 dB) low-pass filter. The filter
cut-off frequency can be continuously and automatically adjusted between 800 Hz and 35 kHz by a signal developed in
. the control path. Both audio inputs contribute to the control
path signal and are used to activate a peak detector which,
in turn, changes the audio filters' cut·off frequency. The audio path filters are controlled by the same. signal for equally
matched bandwidths in order to maintain a stable stereo
image.
AUDIO CONTROLL£D
LOW PASS FILTER
LEfT
AUDIO 0-...- -.....- - - - - 1
INPUT
1 - - - -.....- - - - 0
LEfT
AUDIO
OUTPUT
CONtROL SIGNAL
D£lECTOR
FILTER
CONtROL SIGNAL
1----....----00
RIGHT
AUDIO 0-....- -....- - - -....
INPUT
AUDIO CONTROUEO
LOW PASS FILTER
FIGURE 1. Stereo Noise Reduction System (DNR)
837
RIGHT
AUDIO
OUTPUT
TLIH/8395-1
I.---~------.--,
R
I
I
I
R
,:':'
!>i5 0
TUH/8395-2
(a) V.,-Iable Lowpass Filter
CLOSED LOOP GAIN
.......
.~
>
OPEN LOOP GAIN
fREQUENCY (F)
TUH/8395-14
(e) Closed Loop Response
flo'
o~----------~~~
FREQUENCY (F)
,TUH/8395-13
(b) Open Loop Response
FIGU,R!1:2
A more detailed schematic is given in Figure 3 and shows
the resistors Rf and Ri which provide dc feedback around
the circuit for unity closed-loop gain (i.e. 'at frequencies below ful. The transconductance stage conSists of a differential pilir T1 and T2 with current mirrors replacing the more
conventional load resistors. The output current 10 to the Integrator stage is the difference between T1 and T2 collector
currents.
For a differential pair, as long as the input differential voltage is small - a few millivolts - the gm is dependent on
the tail current IT and can be· written·
VARIABLE CUT-OFF LOW DISTOIlTION FILTERS
By low distortion we mean a filter .that has a flat response
below the cut-off frequency, a smooth, constant attenuation
slope above the cut-off frequency and does not peak at the
cut-off frequency as this frequency is changed.
The circuit topology is shown in Figure 2 (a) and is, In fact,
very similar to the pole-splitting frequency compensation
technique used on many integrated circuit operational amplifiers (see pp. 24-26 of "Intuitive IIC Op Amps" 'by T. M.
Fredericksen). A variable transconductance (gml stage
drives an amplifier configured as an integrator. The transconductance stage output current 10 is given by
q
gm = kT
10 = gm Yin
(1)
and if the second amplifier is considered ideal, then the voltage VOu! is the result of 10 flowing through the capaCitative
reactance of C. Therefore we can write
10
VOu!=21TtC
For frequencies below the cut-off frequency, the amplifier is
operating closed loop, and the de feedback via Rf will keep
the input differential voltage very small. However, as the
input signal frequency approaches cut-off, the loop gain decreases and larger differential voltages will start to appear
across the bases of T 1 and T2. When this happens, the gm
is no longer line~y dependent on the tail current IT and
signal distortion will occur. To prevent this, two diodes D1
, anQ D2 biased by. current sources are added to the input
stage. Now the signal current is converted to a logarithmically related voltage at the input to the differential pair T 1
and T2. Since the diodes and the transistors have identical
geometries and temperature excursions, this conversion will
exactly compensate for the eXJ?Onential relationship. be, tween the input voltage to T1 and T2 and the output collec. tor currents. As long as the signal current is less than the
current available to the diodes, the transconductance amplifier will have a linear characteristic with very low distortIon.
(2)
VOu! _
(3)
At some frequency, the open loop gain will fall to unity
(f=ful given by
•
.
. .
fu=~
21TC
(5)
where..9.. = _1_@25°C
kT
26mV
Combining (1) and (2) we have
gm
Yin - 21TfC
,.
x '2
IT
(4)
For a fixed value of capacitance, when the transconductance changes, then the unity gain fraquency will change
correspondingly as shown in Figure 2 (b).
If we put dc feedback around both stages for unity closed
loop gain, the amplitude response will be flat (or unity gain)
until fu is reached, and then will follow the open loop gain
curve which is falling at 6 dB/octave. Since WE! .contr91 gm,
we can make fu any frequency we desire and therefore have .
a controlled cut-off frequency low pass filter.
838
140J.'A
1
C
O.OO33J.'F
CURRENT
MIRROR _ _....,,.....
v~o---~~----~--~¥r------------------~
%Olen.
20 len.
TUH/8395-3
FIGURE 3. Variable Lowpass Filter with DIstortion Correcting Diodes and Control Voltage Offset Compensation
INPUT o-"WHH
'r
(FROII DETECTOR)
150kA
10pF
FEEDBACI<
TUH/8395-4
FIGURE 4. The OP AMP Output Stage of the LM1894
For the entire circuit, if Ri = Rt = R and the diode dynamic
resistance is re, we can write the transfer characteristic as
VOu! =
-1
(
4".tCK26 x 10-3)
1+
IT
whereK =
In operation, the transconductance stage current IT for the
LM1894 will vary between the levels given above in response to the control path detected voltage. Notice that
with the circuit values given in Figure 3 the maximum output
voltage swing at the cut-off frequency is about IVrms (use
equation 2 and put 10 = IT = 33 /LA) and this is specified in
the LM1894 data sheet as the input voltage for 3% THO.
This is, of course, the condition for minimum bandwidth
when noise only is normally present at the input. When signals are simultaneously present causing the audio bandwidth to increase out to 35 kHz, the transconductance stage
current is over 1 mA, allowing signal swings at 1 kHz (theoretically) of over 34 Vrrns. Practically, at maximum bandwidth the output swing is determined by the output stage
saturation voltages which are dependent on the supply volt-
(6)
(2 +~)
2re
Therefore the pole frequency for C = 0.0033 /LF is
fu = IT/4"IT 26 X 10 -3 CK = IT X 33.2 X 106
for fu = 1 kHz, IT = 33.2 /LA
forfu = 35 kHz, IT = 1.1 mA
839
CD
~
•
~
RIGHT INPUT
lDTlI'UT
15
v.
~
20114
20114
111 ...
STAGE
1114
IIk4
~KDE1ECIOR
7004
~
. O.1~F
lk4
O.ooI,.r
0.047 "r
"
GAINS£T
TLlH/B395-5
FIGURE 5. Control Path Amplifiers and Filters
age (see Fl{Jure 4). With a 15 Voc supply, the LM1894 can
handle well over 4 Vrms.
of the human ear sO that audible signal distortion or unmasking d~5 not occur.
While there are other circuit topologies that can be used to
obtain a variable cut-off low pass filter, this design has certain advantages, especially when it comes to avoiding control feedthrough. Control feedthrough is the name given to
voltage offsets that can occur in the audio path as the transconductance stage current changes. The audible effect is a
low level "bacon frying" noise or pops as the bandwidth
changes. To prevent such voltage offsets occurring, the differential stage T 1 and T 2, the current mirrors and the diodes
are arranged to provide good tracking over the entire range
of the bandwidth control current IT. E\ecause the transconductance stage is driving the inverting input to an operational amplifier - a virtual ground - there will be no voltage
swing at this node. This eliminates possible offset voltages
from output impedance changes in the current mirror and T 1
collector caused by different operating currents. Last, but
not least, a source of offset voltages are the base currents
of T1 and T 2. Because the transistors have a finite current
gain, when the tail current IT is increased, these base cur:
rents must increase slightly. T 1 base current is provided by
the referE1nce voltage (V +/2), but T2 base current must
come via the feedback resistor Rt. This current is not normally available from D2 because the feedback loop is holding T 1 and T2 base voltages equal. By adding the resistor
Rb in series with T 1 base, a compensating offset voltage is
produced across the inpUt diodes. This reduces the current
in D1 slightly and increases the current in D2 correspondingIy,allowing it to supply the increased base current requirement ofT2.
Figure 5 shows a block diagram of the control path including
the external components. A straight-forward summing amplifier combines the left and right channel inputs and acts as
a, buffer amplifier for 'the gain control. Because the noise
level for signal sources can be different - cassette tapes
are between -50 dB and -65 dB (depending on whether
Dolby B encoding is employed) and FM broadcast noise is
around -45 dB to over -75 dB (depending on signal
strength) - the control path gain is adjusted such that a
noise input is capable of just increasing the audio bandwidth
from its minimum value. This ensures that any program material above the noise level increases the audio bandwidth
so that the material is passed without distortion. Setting the
potentiometer (or an equivalent pair of resistors) will be described in more detail later.
The gain control potentiometer is also part of the DNR filter
characteristic derived from auditory masking considerations
- see AN384. Combined with a 0.1 ",F coupling capaCitor,
the total resistance of the potentiometer will cause a signal
attenuation below 1.6 kHz.
1
i.e. f1' 2'11'RC
1
2'11' x 103 X 0.1 x 10 6
1.6 kHz
This helps to prevent signals with 'a high amplitude 'but 'no
high frequency content above 1 kHz - such as a tiass drum
- from activating the control path detector and unnecessarily opening the audio bandwidth. For signals that do have
a significant high frequency content (predominantly harmonics), the control path sensitivity is 'increased at a 12 dB/octave rate. This rapid gain in sensitivity is important since the
harmonic content of' program material typically falls off
quickly with increasing frequency. The 12 dB/octave slope
is provided by cascading two RC high pass filters composed
of the coupling capaCitors to the control path gain stage and
detector stage and the internal input resistors to these
stages. Individual corner frequencies of 5.3 kHz and 4.8 kHz
respectively are used, with a combined corner frequency
around 6 kHz. Above 6 kHz the gain can be allowed to
THE CONTROL PATH
The purpose of the control path is to ensure that the audio
bandwidth is a!wavs suffiCiently wide to pass the desired
signal, yet in the absence of this signal will decrease rapidly
enough ,that the noise also present does not become audible. In order to do this, the control path must recognize the
masking qualities of the signal source and the detector
stage must be able to take advantage of the characteristics
840
a pulse or transient input signal, the rise time is 200 p.s to
90% of the final detected voltage level. Actual rise-times will
normally be longer with the detector tracking the envelope
of the combined left and right channel signals after they
have passed through the control path filter.
80
illl 111111111 11111
70
!
IWintoUT MiD CIRCUIT
10
~
~ 50
I
40
30
20
r-
10
f-
o
1
1111
An interesting difference to compandor performance can be
demonstrated with a 10 kHz tone burst. Since the LM1894
detector responds only to negative signal peaks, it will take
about four input cycles to reach 90% of the final voltage on
the detector capacitor (this is the 500 P.s time constant
called out in the data sheet). After the first two cycles the
audio bandwidth will have already increased past 10kHz
and a comparison of the input and output tone bursts will
show only a slight loss in amplitude in these initial cycles. A
compandor, however, usually cannot afford a fast detector
time constant since the rapid changes in system gain that
occur when a transient signal is processed can easily cause
modulation products to be developed which may not be
treated complementarily on playback, Therefore there is a
time lag before the system can change gain, which may be
to the maximum signal compression (as much as 30 dB
depending on the compandor type). Failure to compress immediately at the start of the tone burst means that an overshoot is present in the signal which can be up to 30 dB
higher than the final amplitude. To prevent this overshoot
from causing subsequent amplifier overload (which can last
for several times the period of the overshoot), clippers are
required in the signal path, limiting the dynamic range of the
system. Obviously, the LM1894 does not need clippers
since no Signal overshoots in the audio path are possible.
~
A ••1mH
r~l\( - •..g~.s.:J:
100
IK
10K
FREQUENCY (HI)
lOOK
TUH/8395-6
FIGURE 6. Control Path Frequency Response
decrease again since the signal energy content between
1 kHz and 6 kHz (the critical masking frequency range) will
have already caused the audio bandwidth to extend beyond
30 kHz, allowing passage of any ·high frequency components in the audio path.
Under some circumstances, not normal to music or speech,
the source can contain relatively high level, high frequency
comp.onents which are not necessarily accompanied by
large levels of low freqllency signal energy providing noise
masking. These are spurious components such as the line
scan frequency in a television receiver (15.734 kHz) or subcarrier signals such as the 19 kHz pilot tone in FM stereo
broadcasting. Although both these components should be
low enough to be inaudible in the audio path, their presence
in the control path could cause a change in the minimum
bandwidth and hence the amount of available noise reduction. Since these unwanted components are at .frequencies
higher than the desired control path frequency range, they
are easily accommodated by including a notch filter in the
control path at the specified frequency. A resonant L-G circuit with a Q of 30 will attenuate 19 kHz by·over 28 dB. If a
10% tolerance 0.015p.F capacitor is used, the coil can be a
fixed 4.7 mH inductance. For 15.734 kHz a 0.022 p.F capacitor is needed. When those frequency components are not
present (i.e. in cassette tapes) the L-G circuit is eliminated
and the gain amplifier and detector stage are coupled together with a single 0.047 p.F capacitor.
Apart from providing the proper frequency response the
control path gain must be enough to ensure that the detector threshold can be reached by very low noise input levels.
The summing amplifier has unity gain to the sum of the left
and right channel inputs and the necessary signal gain of 60
dB is split between the following gain amplifier and the detector stage. For the gain amplifier
Ay=33
When the input signal transient decays, the diode in the
detector stage is back biassed and the capacitor discharges
primarily through the feedback resistor and takes about
60 ms to reach 90% of the final value.
T=RG x 2.3=27 X 103 X 1 X 10- 6 X 2.3
=62.1 ms
The decay time constant is required to protect the reverberatory or "ambience" qualities of the music. For material with
a limited high frequency content or a particularly poor SIN
ratio, some benefit can be obtained with a faster decay
time-a resistor shunted across the detector capacitor will
do this. Resistors less than 27 kO should not be used since
very fast decay times will permit the detector to start tracking the signal frequency. For signal amplitudes that are not
producing the full audio bandwidth, this will cause a rapid
and audible modulation of the audio bandwidth.
BYPASSING THE SYSTEM
Sometimes it is necessary or desirable to bypass the n.r.
system. This will allow a direct and instantaneous comparison of the effect that the system is having on the program
material and will assist in arriving at the correct setting for
the control path gain potentiometer. This facility is not practical with compandors unless unencoded passages occur in
the program material. Also, should the action of the compandor becomE! more objectionable than the noise in the
original material, there is no way of switching the n.r. system
off.
One way of bypassing is to simply use a double pole switch
to route the Signals around the LM1894. This physically ensures· complete bypassing but does present a couple of
problems. First, there may be a level change caused by the
different impedances presented to the following audio
stages when switching occurs. Second, the signal now has
to be routed to the front panel where the switch is located,
perhaps calling for shielded cable.
x 103/(re + 103) =26.2
=28.4 dB
For the detector stage, the gain to negative Signal swings is
Ay=27 x 103 1700=38.6=31.7 dB
With over 60 dB gain and typical source input noise levels,
the gain potentiometer will normally be set with the wiper
arm close to the ground terminal.
THE DETECTOR STAGE
The last part of the LM1894 to be described is the detector
stage which includes a negative peak detector and a voltage to current converter. As noted earlier, the input resistance of the detector, together with the input coupling capacitor, forms part of the control path filter. Similarly the output
resistance from the detector and the gain setting feedback
resistor help to determine the detector time constants. With
841
V/1 CONYER1ER
TO gm STAGES
INPUT FROII GAIN AIIP
TLlH/8395-7
FIGURE 7. Peak Detector and Voltage to Current Converter
Input
Peak
Detector
Output
TIME: 20 ms/DIV
TLIH/8395-8
Peak Detector Response, 500 mY/Diy
Input
Output
TLIH/8395-12
TIME: 0.5 ms/DIV
Audio Output Response, 10 kHz Tone Burst
FIGURES
842
The same circuit as Figure 9 can be used for measurements
on the I/C performance but, as with any other n.r. system,
care in intepretation of the results may be necessary. For
example, while the decay time constant for a tone burst
signal is pretty constant, the attack time will depend on the
tone frequency.
A different technique, which avoids these problems, is to
switch the LM1894 permanently into the full audio bandwidth mode. Since this provides a high SIN ratio path and
low distortion the impact on the signal is minimal. Two methods can be used to switch the LM1894 audio bandwidth fully
open, both with a single pole switch that is not in the audio
path. Simply grounding the input of the peak detector amplifier will generate the maximum bandwidth control current
and simultaneously prevent any control signals reaching the
detector. Usually this is more than adequate since the maximum audio bandwidth is 34 kHz, but in some cases the 1 dB
loss at 17 kHz produced by the single pole audio filters may
not be desired. Figure 9 shows a way to increase the audio
bandwidth to 50 kHz (-1 dB at 25 kHz) by pulling up the
detector capacitor to the reference voltage level (V + /2)
through a 1 kG resistor. This method is useful only for higher supply voltage applications. To increase the bandwidth
significantly the detector capaCitor must be pulled up to
around 5V (V + >10V). Although a separate voltage source
other than the reference pin could be used when V + is less
than 1OV, this can cause an internal circuit latch-up if the
voltage on the detector increases faster than the reference
voltage at initial turn-on.
Sometimes separation of the audio path input and the control path is required, particularly when the frequency response or the THO with low input signal levels is being measured. If the audio and control paths are not separated then
a typical audio system measurement of the frequency response will not appear as expected. This is because the
control path frequency response is non-linear, exhibiting low
sensitivity at low frequencies. When a low level input signal
is swept through the audio frequency range, at low frequencies the audio - 3 dB bandwidth will be held at 1 kHz, and
the audio path signal will fall in amplitude as the signal goes
above 1 kHz. As the Signal frequency gets yet higher, the
increasing sensitivity of the control path will allow the detector to be activated and the audio path - 3 dB frequency
starts to overtake the Signal frequency. This causes the output signal amplitude to increase again giving the appearance that there is a dip in the audio frequency response
around 1-2 kHz. It is worth remembering at this point that
the audio path frequency response is always flat below
some corner frequency and rolls off at 6 dB/octave above
this frequency. In normal operation this corner frequency is
the result of the aggregrate control path signals in the 1 kHz
to 6 kHz region and not the result of a single input frequency. To properly measure the frequency response of the audio path at a particular signal input frequency and amplitude,
the control path input is separated by disconnecting Cs from
Pin 5 and injecting the signal through Cs only. Then, a separate swept frequency response measurement can be made
in the audio path. Similarly measurements of THO should
include separation of the audio and control path inputs.
GENERAL SYSTEM MEASUREMENTS AND
PRECAUTIONS
For most applications the external components shown in
Figure 9 will be required. In fact, the only recommended
deviation from these values is the substitution of an equivalent pair of fixed resistors for the galn setting potentiometer.
Location of the LM1894 in the audio path is important and
should be prior to any tone or volume controls. In tape systems, right after the playback head pre-amplifier is the best
place, or at the stereo decoder output (after de-emphaSis
and the multiplex filter) in an FM broadcast receiver. The
LM1894 is designed for a nominal input level of 300 mVrms
and sources with a much lower pre-amplifier output level will
either require an additional galn block or substitution of the
LM832 which is designed for 30 mVrms input levels.
843
AN-386
~
+
@'II-I':"'"+-------,
I sof'
lsof'
O.0033sof'
r-12V
~ ..............tl.... I'--t~--tt
V"
12'1'
RIGHT
OUT
,
13 1
LEFT
IN
+
I SOf'
20kA
20kA
2
+-
RIGHT
IN
I sof
,
14'
27kA
30kA
1.2V~~
t
1.2V
700A
IkA
ON
5
BYPASS
.J!
8
0.1 SOf' t . . - . l . 0 0 1 soF
1,----
'kA
TUH/8395-9
FIGURE 9. Complete Stereo Noise Reduction System
3) Apparent High Frequency Loss:
The ability to instantaneously AlB the source with and
without noise reduction can sometimes exhibit an apparent loss of h.f. Signal content as the DNA system operates. This is most likely to happen with sources having an
SIN ratio of less than 45 dB and is a subjective effect in
that the program material probably does not have any
significant h.f. components. It has been reported several
times elsewhere that adding high frequency noise (hiss)
to a music signal with a limited frequency range will seem
to add to the h.f. content of the music. Trying sources
with a higher SIN ratio that do not demonstrate this effect can re-assure the listener that the DNA system is
operating properly. Alternatively a control path sensitivity
can be used that leaves the audio bandwidth slightly
wider, preserving the "h.f. content" at the expense of
less noise reduction in the absence of music.
4) Sensitivity Setting:
Since this is the only adjustment in the system, it is the
one most likely to cause problems. Improper settings can
cause any of the previously described problems. Factory
pre-sets can (and are) used, but only when the source is
well defined with known noise level. For the user who
intends to noise reduce a variety of sources, the control
path gain potentiometer is required and should be adjusted for each application. A bypass switch is helpful in this
respect since it allows rapid AlB comparison. Another
useful aid is a bandwidth indicator, shown in Figure 10.
This is simply an LED display driver, the LM3915, operating from the voltage on the detector filter capacitor at Pin
10 of the LM1894. The LM3915 will light successive
LEOs for each 3 dB increase in voltage. The resistor values are chosen such that the capaCitor voltage when the
LM1894 is at minimum audio bandwidth, is just able to
light the first LED, and a full audio bandwidth control signal will light the upper LED. Experience will show that
adjusting the sensitivity so that the noise in the source
(no signal is present) is just able to light the second LED,
will produce good results. This display also provides constant reassurance that the system audio bandwidth really
is adequate to process the music. A simpler detector,
using a dual comparator and a couple of LEOs can be
constructed instead, with threshold levels selected to
show the correct sensitivity setting, minimum bandwidth,
maximum bandwidth or some intermediate bandwidth as
desired.
PITFALLS - OR WHAT TO LISTEN FOR
Many people are understandably wary of non-complementary n.r. systems since there is no perfect means for distinguishing between the desired signal and noise. A thorough
understanding of the psycho-acoustic basis for noise masking will go a long way to allaying these fears, but a much
simpler method is to listen to a variety of source material
with a DNA system being switched in and out. Even so,
improper implementation of the LM1894-wrong location in
the audio path changing either the level or frequency response of the source-or incorrect external component values, or the wrong sensitivity setting, can all strongly affect
the audio in an undesired way. Sometimes, unhappily, the
source is really beyond repair and some compromise must
be made. Phonograph discs with bad scratches may require
special treatment (a click and pop remover) and some older
tape recordings may show some or all of the following problems.
1) Pumping:
Incorrect selection of the control path bandwidth external components can result in an audible increase in
noise as the input level changes. This is most likely to
be heard on solo instruments or on speech. Sometimes
the SIN rate is too poor and masking will not be completely effective - i.e., when the bandwidth is wide
enough to pass the program material, the increase in
noise is audible. Cutting down on the pumping will also
affect the program material to some extent and judgement as to which is preferable is required. Sometimes
a shorter decay time constant in the detector circuit
will help, especially for a source which always shows
these characteristics, but for better program material
a return to the recommended detector characteristics
is imperative.
2) High Frequency Loss:
This can be caused by an improper control path gain
setting-perhaps deliberate because of the source SIN
ratio as described above-or incorrect values for the
audio path filter capacitors. Capacitors larger than the
recommended values will seele the operating bandwidth
lower, causing lower -3 dB corner frequencies for a
given control path signal. Aeturn to the correct capacitor values and the appropriate control path gain setting
will always ensure that the h.f. content of the signal
source is preserved.
14
II
13
LM3II&
Ik
F~~~~~~~
____________________
~
__
~
430
110
TL/H/8395-10
FIGURE 10_ Bar Graph Display of Peak Detector Voltage
845
DNR Component Diagram
•.,,~------oVoun
'J~~~
. . .It------oPEAK OETECTOR OUT
........----c. PE,'KDETECTOR III
~'I~ilt-----oGIlD
TlIH/8395-11
FIGURE 11. Prlntad Circuit Layout
846
National Semiconductor
Application Note 390
Martin Giles
Kerry Lacanette
DNRTM Applications
of the LM 1894
INTRODUCTION
In the majority of these applications the circuit used is identical to that shown in Figure 1, and this is the basic stereo
Dynamic Noise Reduction System. Although a split power
supply can be used, a single positive supply voltage is
shown, with ac coupled inputs and outputs common in many
consumer applications. This supply voltage can be between
4.5 Voc and 18 Voc but operation at the higher end of the
range (above 8 Vod is preferred, since this will ensure adequate signal handling capability. The LM1894 is optimized
for a nominal input Signal level of 300 mVrms but with an
8 Voc supply it can handle over 2.5 Vrrns at full audio bandwidth. Smaller nominal signal levels can be processed but
below 100 mVrms there may not be sufficient gain in the
control path to activate the detector with the source noise.
In this instance, and where battery powered operation is
desired, the LM832 is a better choice. The LM832 has identical operating principles and a similar (but not identical) pinout. It is optimized for input levels around 30 mVrms and a
supply voltage range from 1.5 Voc to 9.0 Voc.
The capaCitors connected at Pins 12 and 3 determine the
range of - 3 dB cut off frequencies for the audio path filters.
Increasing the capacitor value scales the range downward the minimum frequency becomes lower and the maximum
or full bandwidth frequency will decrease proportionally.
Similarly, smaller capacitors will raise the range.
The operating principles of a single-ended or non-complementary audio noise reduction system, DNR, have been
covered extensively in a previous application note AN384,
Audio Noise Reduction and Masking. Although the system
was originally implemented with transconductance amplifiers (LM13600) and audio op-amps (LM387), dedicated I/Cs
have since been developed to perform the DNR function.
The LM1894 is designed to accommodate and noise reduce
the line level signals encountered in video recorders, audio
tape recorders, radio and television broadcast receivers,
and automobile radio/cassette receivers. A companion device, the LM832, is designed to handle the lower signallevels available in low voltage portable audio equipment. This
note deals chiefly with the practical aspects of using the
LM1894, but the information given can also be applied to
the LM832.
THE BASIC DNR APPLICATION CIRCUIT
At the time of writing, the LM1894 has already found use in
a large variety of applications. These include:
AUTOMOTIVE RADIOS
TELEVISION RECEIVERS
HOME MUSIC CENTERS
PORTABLE STEREOS (BOOM BOXES)
'-3dB=IT/9.1C(lT=33,..AMIN)
(1)
( = 1.05 mA MAX)
For normal audio applications the recommended value of
0.0033 ,..F should be adhered to, producing a frequency
range from 1 kHz to 35 kHz.
SATELLITE RECEIVERS
AUDIO CASSETTE PLAYERS
AVIONIC ENTERTAINMENT SYSTEMS
HI-FI AUDIO ACCESSORIES
BACKGROUND MUSIC SYSTEMS
ETC.
LEfT
OUTPUT
LEfT
INPUT
TO VOLUME
CONTROL AND
FROM TAPE
PREAMP OR FII
POWER AMPLIFIERS
RIGHT
INPUT
P
O.I:,r
CI.-;r
O.I~
C2
RIGHT
OUTPUT
_
ca-
Rl
o.ool/lor
R2
_
'RI + R2
~
C4
•
I kO total
l/Ior
TL/H/B420-1
FIGURE 1. Complete DNR Application Circuit
847
ft
~
'F
..y~ -f~
0.047 pF
OUT
IN
TLiH/8420-1 B
TLiH/8420-2
(b)
(a)
FIGURE 2. Two Methods of DNR IN/OUT Switching
The two resistors connected at Pin 5 set the overall control
path gain, and hence the system sensitivity. A lower tap
point will decrease the sensitivity for high signal level sourc.es, and a higher tap point will accommodate lower level
sources. For purposes of initial calibration it is best to replace the resistors with a 1 kG potentiometer (the wiper arm
connecting through Ce to Pin 6), and follow the procedures
outlined below. Once the correct adjustment point has been
found, the position of the wiper arm is measured and an
equivalent pair of resistors are used to replace the potentiometer. This, of course, can be done only if ,the source has
a relatively fixed noise floor-the output from an audio cassette tape for example. For an add-on audio aCl)essory the
potentiometer should be retained as a front panel control to
allow adjustment for individual sources. Use of DNR with
multiple source~ is described later.
. Apart from the basic circuit shown in Figure 1, all, applications of the DNR system have another feature in commonthe location of the LM1894 in the signal chain. As Figure 3
shows, the LM1894 is always placed right after the Signal
source pre-amplifier and before any circuit that includes
user adjustable controls for volume or frequency response.
The reasons for this are obvious. If the gain of the Signal
amplifier preceding DNR is changed arbitrarily, the noise
input level 10 the LM1894 will not be at the correct point to
begin activation of the audio path filters. Either reduced
noise reduction will be obtained, or the high frequency content of the program material will be affected. A change in
system gain prior to the LM1894 requires a corresponding
change in the control path threshold sensitivity. Similarly
modifying the frequency response, by, heavy boost or cut of
the mid to high frequencies, will have the same effect of
changing the required threshold setting-apart from modifying the masking qualities of the program material.
SYSTEM CALIBRATION
System calibration can be performed in a number of ways.
With the source connected playa blank but biased section
of the cassette tape. Set the potentiometer so that the wiper
arm, is at ground and then steadily rotate. it until a slight
increase in the output noise level is heard. Alternatively,
with source program material present, set the potentiometer
with the wiper arm connected to the Pin 5 end of the slider
and again rotate until the high frequency content of the program material appears to begin to be attenuated. Then return the potentiometer wiper slightly towards Pin 5 so that
the music is unaffected.
A third method of adjustment can be done with an oscilloscope monitoring the voltage on the control path detector
filter capacitor, Pin 10. This will show a steady dc voltage
around 1V while the wiper arm of the potentiometer is at
ground. As the wiper arm is rotated, this voltage will start to
increase. About 200 mV above the quiescent value will usually be the right point. Note that this. will not be a steady dc
voltage but a random peak, low amplitude sawtooth waveform caused by peak 'detection of the source noise in the
control path.
Whatever method is used to determine the potentiometer
setting, this setting should be confirmed by listening to a
variety of programs and comparing the audio quality while
switching DNR in and out of the circuit. This is easily accomplished by grounding Pin 9 which will disable the control
path and force the audio filters to maximum bandwidth, Figure 2(a). Also shown is a second method of ON/OFF
switching that gives an increased maximum bandwidth over
that obtained in normal operation. Although the switch is not
a required front panel control it can be an important feature.
Unlike compander systems, DNR can be switched out leaving the source completely unproceSsed in any way. With a
switch, the user can always be assured that the noise reduction is not affecting the program material.
HOW MUCH NOISE REDUCTION?
The actual sensitivity setting that is finally used, and the
amount of noise reduction that is obtained, will depend on a
number of factors. As the data sheet for the LM 1894 and
other application notes have explained in some detail, the
noise reduction effect is obtained by audio bandwidth restriction with a pair of matched low-pass filters. A
CCIR/ARM· weighted noise measurement is used so that
the measured improvement obtained with DNR correlates
well to the subjective impression of reduced noise. This is
another way of stating that the source noise spectrum level
versus frequency characteristic can have a large impact on
how "noisy" we judge a source to be-and concomitantly
how much of the "noisiness" can be reduced by decreasing
the audio bandwidth. Fortunately most of the audio noise
sources we deal with are smooth although not necessarily
flat, resembling white noise. The weighting characteristic referred to above generally gives excellent correlation. For
example, if the source - 3 dB upper frequency limit is only
.. 2 kHz (an AM radio), reducing the audio path bandwidth
down to 800 Hz will improve the SIN ratio by only 5 to 7 dB.
On the other hand, if the source bandwidth exceeds at least
8 kHz then from 10 dB to 14 dB noise reduction can be
obtained. Of course, it is always worth remembering that
this is the reduction in the source noise-any noise added in
circuits aftBrthe LM1894 may contribute to the audible output and prevent the full noise reduction effect. To see how
easily this can happen, we will consider the noise levelS at
various points in a typical automotive radio using an IIC
tone and volume control, and an IIC power amplifier, both
with and without noise reduction of the cassette player.
'See pp. 2-9 to 2-10, Audio Handbook, National Semiconductor 1980.
848
TAPE H£AD
AIIPLIFlER
~""K
....
RIM
PREAIIPlIF1ER
FII STEREO
L11ISS.
DECODER
~
---.
TONE
VOLUME
POWER
AIIPS
60dB
I.F. amplifier gain control range
55 dB
True synchronous detector with a Pll
Detector conversion gain
34 dB
Detector output bandwidth
9MHz
Detector differential gain
2%
Detector differential phase
1 degree
Noise averaged AGC system
Internal AGC gated comparator
Reverse tuner AGC output
DC controlled video detection phase
AFC detector
The Signal coming into the receiver has this general format
and the receiver R.F. and I.F. circuits .are designed to handle such a Signal and re.duce it back to the baseband composite video and audio intercarrier. Even where signal
scrambling is used to protect the vide~. modulation from unauthorized detection, the R.F. spectrum must remain within
this format. For satellite broadcasts with frequency modulation of the video Signal, the signal is demodulated and then
remodulated onto a low VHF channel for reception by standard television receivers. In connSction with this, the
lM1823 Pll detector is not suitable for wide-band FM detection-even though the I.F. carrier (70 MHz) is well within
the lM1823 I.F. amplifier frequency capability.
Notice again that the pix carrier is located at one end of the
occupied bandwidth and only the upper sidebands are being
fully transmitted. The lower sidebands are truncated with
only frequencies close to the pix carrier frequency modulating the carrier. This method of conserving the frequency
spectrum is referred to as vestigial sideband transmission.
THE CABLE CONNECTION
Originally introduced many years ago as a means for providing broadcast TV to isolated areas or where the terrain
made direct reception difficult, cable TV had modest growth
in the U.S. and was a stagnating industry until the mid-seventies. lower cost satellite earth stations were the turning
pOint, allowing cable operators access to many varied program sources from any part of the country.
THE R.F. SIGNAL FORMAT
Despite the wide variety of signal sources available to the
home television receiver-broadcast, cable, satellite, video
games etc.-on channel carrier frequencies from
55.25 MHz to 885.25 MHz, the spectral content of each R.F.
channel has been established for many years. In the United
States the channel bandwidth is fixed at 6 MHz with the
picture carrier located 1.25 MHz from the lower end of the
band, and an aural carrier placed 4.5 MHz above the picture
(pix) carrier. Introduction of color television in the early fifties
added another carrier, the chroma sub-carrier, positioned
3.58 MHz above the pix carrier frequency. The pix carrier is
amplitude modulated· by the baseband video signal (which
J----IUHz QWlHEL WIIIH----.j
• A more appropriate term is "negative downward modulation" since any
modulating Signal causes a decrease in the peak carrier amplRude (c0mpared 10 conventional a.m., where the modulating signal altemately increases and decreases the peak carrier level wRh the mean carrier level remaining constant). For television carriers, syncs correspond to peak carrier and
increasing brightness causes decreasing carrier amplitudes.
0.5
TUH/8421-1
FIGURE 1. U.S. Broadcast Channel Spectrum
Broadcast Channel Frequency Allocations
13
54 VHf LOW II
1.71
SUB
BAND
21.75
174
101
Iono -BAND
A-I
14
VHF HIGH 21.
SUPER
BAND
T7
110
Cable Channel Frequency Allocations
410
21.
83
UHF
.'0
W
TUH/8421-2
FIGURE 2. Broadcast and Cable Bands In the U.S.
856
TL/H/8421-3
FIGURE 3. Cable Set·Top Converter Block DIagram
located outside the signal channel. This permits use of the
television receiver in a normal way but does require simultaneous switching of the decoder receiver with channel
changes.
Standard television receivers in the U.S. tune to VHF channels 2 through 13 and UHF channels 14 through 83, and
initially cable operators used the 12 VHF channels for their
program material. With increased sources soon all channels
were occupied on some systems creating significant demands on television tuner and I.F. amplifier strips. More
space yet was needed and rather than using UHF channel
allocations starting at 470 MHz because of cable Signal attenuation (typically 0.8 dB/100 ft. at 300 MHz), operators
tumed to the unused spectrum space between VHF channel
13 and UHF channel 14. Naturally, since standard TV receivers could not tune to these channels, the set-top converter came into being. Each of the new channels could be
converted to a low VHF channel to be received on the standard TV. Television manufacturers responded, and with the
common introduction of varactor tuners were soon able to
offer "cable ready" televisions capable of tuning to all the
new cable frequencies. This meant that customer conveniences such as remote control of channel selection also
became available. Unfortunately it aggravated a problem already confronting the cable operator. Since standard televiSion receivers couldn't tune to the cable channels, operators had been able to offer premium services on some of
these frequencies, paid for by subscribers who rented the
appropriate set-top converter box. This didn't prove very secure since one operator's "free" channel was another operator's "pay" channel, and the introduction of cable-ready
televisions ensured the eventual demise of such systems.
Also, spectrum space must be reserved for each scrambled
channel's data carrier.
A more popular method of scrambling is "in band scrambling" where the data carrier to decode the signal is included inside the transmitted Signal channel, usually within the
aural carrier. Any number of channels can be scrambled
and now different levels of service can easily be added or
deleted without the need to rewire the decoder box. This is
achieved by including time multiplexed binary "tags" along
with the sync information so that special programs can be
identified. Individual subscriber boxes can be similarly addressed and tumed on or off by the cable operator. In these
types of systems, the LM1823 and LM2889 have obvious
applications. The LM1823 is able to provide an excellent
baseband Signal inside the decoder box, which Signal is
then remodulated on a low VHF channel carrier by the
LM2889 for retransmission to the standard television receiver. Clearly, the highest possible performance is desireable
to prevent any noticeable difference between a converted
channel, whether scrambled or not, and a regular off-air
broadcast channel. (For a complete description of the
LM2889 modulator IIC see AN402).
THE RECEIVER FRONT·END
Scrambling the signal, a technique already being used by
over-the-air subscription television, has become common in
the cable service. The degree of scrambling" is limited since
the scrambled signal spectrum must remain within the channel allocation and anything done to the signal must be subsequently undone without noticable degradation of the signal.
The typical receiver front-end consists of a tuner, I.F. amplifier, I.F. filters and a videolsound intercarrier detector stage.
These circuits are designed to provide a number of functions:
Generally for television, scrambling means a pulse or sine
wave suppression of the signal horizontal blanking pulse
interval so that the sync-tips occur between the black and
white levels instead of always below black level. The standard television sync separator does not function well with
this signal and the I.F.ltuner AGC circuits will not work properly, effectively scrambling the displayed picture. Other
techniques include random inversion of the video information to provide an even greater degree of security.
The means used to encode such a scrambled signal gives
rise to the terms "in band scrambling" and "out of band
scrambling". With cable ready television receivers capable
of tuning to the scrambled channel, the decoder can be a
simple broad-band gain switch (to change the signal R.F.
amplitude during horizontal blanking) with a separate receiver tuned to the decoding data carrier frequency, which is
$Other security techniques such as jamming or trapping are used but since
iamming is easy to defeat and trapping requires removal or replacement of
filters in the cable drop to individual subscribers, scrambling the signal is
receiving a lot more attention.
1)
Select (tune) a specific R.F. channel in a band of frequencies.
2)
Provide rejection to adjacent and other channels in the
band.
3)
Amplify low level R.F.lI.F. Signals prior to detection of
the modulation.
4)
Avoid overload on high level R.F. Signals.
5)
Trap or attenuate specific frequencies within the channel bandwidth to ensure a proper detected frequency
response is obtained.
6)
Linearly demodulate all desired modulating frequencies
on the carrier.
7)
Produce a noise-free video signal at the detector.
8)
Provide automatic gain control (AGC) to compensate
for changing signal strength at the receiver input.
9)
Provide automatic frequency control (AFC) to the tuner
local oscillator (L.O.) to maintain the carrier intermediate frequency (I. F.).
N.B. Items 8) and 9) have previously been provided in part by circuits external to the conventional I.F. amplifier. However, these functions are
completely included with the LM1823 leading to overall performance
improvements and reduction in external parts count and cost.
857
.- r------------------------------------------------------------------------------------------,
G)
z'?
TV
CH3
RF
the desired output impedance is 750. and that the major I.F.
amplifier frequency selectivity is determined by a block filter
placed between the tuner output and I.F. amplifier input.
This is consistent with modern practice using surface
acoustic wave filters (SAWF's) and high gain stabilized IIC
amplifiers (LM1823). Even so, as noted in more detail later,
the LM1823 does provide opportunities for more filtering at
the I.F. amplifier output prior to the detector stage.
SP£ClRUM
c(
Dual conversion tuners have been popular for a number of
years and use first L.O. frequencies that are above the input
R.F. bandwidth, avoiding problems with L.O. leakage back
onto the feed cable. The second L.O. and mixer convert the
high first I. F. to a Ch 3 or Ch 4 carrier for reception by the TV
receiver. The addition of PLL's to control the first L.O. and
descrambling networks on the R.F. output have added sufficient complexity to such converters that they are now called
"set-top terminals". Also, since the scrambling techniques
have become more sophisticated the Signal is now frequently converted down to baseband before decoding and remodulation on Ch 3 or Ch 4 carriers. The high first I.F. has
the advantage that image signal rejection is achieved without the switchable filters necessary at the input to the single
conversion tuner. However, the absence of these filters
does mean that care must be exercised to avoid generation
of interrnodulation products that "talk back" onto the cable
(up conversion of the R.F. signal has been proposed as a
way to minimize intermodulation components). Another disadvantage of the dual conversion tuner shown in Figure 6 is
that it typically has a very high Noise Figure, often between
14 dB to 16 dB. This is because the signal is applied directly
to the first mixer which is a passive, double balanced diode
mixer. As discussed in more detail later when we look at
SAWF's between the tuner and the I.F. amplifier, a pre-amp
in front of the mixer can improve the N.F. to 6 dB to 8 dB,
espeCially in a baseband converter where an AGC voltage is
available to help the tuner handle the input signal strength
range.
o
-10
-20
dB
-30
-40
-50
TL/H/B421 -4
FIGURE 4. R.F. Tuning and I.F. Conversion (Note High
Side LO. Reverses the Relative Position of the Picture
Chroma & Sound Carriers. c.f. Figure 1).
Although we are not directly concerned with the tuner design in this application note, it is useful to understand the
design goals and constraints on the tuner for' at least two
reasons. First, since the tuner and I.F. amplifier interact very
closely to obtain and maintain a noise-free picture, we need
to know something about the tuner in order to provide the
correct gain distribution and AGe action. Second, when the
two functions are finally placed together, we need to know
where to look to solve visible problems that may have become apparent. In some instances, either the tuner or the
I.F. amplifier may be atfault, and a good understanding of
the system interaction is' needed to ensure that the appropriate action is taken.
Returning to the single conversion tuner, the major parameters to be considered are as follows:
1) Power gain
2) Noise Figure
TUH/B421-5
FIGURE 5. Typical Single Conversion Tuner
3) Good Cross-Modulation rejection
4)VSWR
Both single conversion and double conversion techniques
are used in cable conv.erter tuners. The Single conversion
type is similar to the conventional TV receiver tuner and
consists essentially of an R.F. stage, mixer stage, and local
oscillator. Usually some input filtering is done to help match
the cable to the input device and provide some rejection to
unwanted signals outside the operating channel. Further rejection to unwanted signals, such as the I.F. frequency radiated back from the I.F. amplifier, is accomplished with interstage filtering between the R.F. amplifier and the mixer, and
finally an output filter matches the mixer output to the cable
feeding the I,F. amplifier. For convenience, we are assuming
5) AGC Range
6) Impedance changes with AGC
7) Overload capability
8) Channel 6 beat rejection
9) Curve tilt (tracking)
10) L.O. drift and radiation
For an I.F. amplifier design, items 1), 2), 7), and 8) are the
most significant, but if the tuner designer has overlooked
the others we may see some problems when the tuner and
I.F. amplifier are hooked together.
TL/H/B421-6
FIGURE 6. Dual Conversion Tuner
858
.--------------------------------------------------------------------.~
Crossmodulation describes the condition wherein the modulation information on an adjacent channel (usually) is transferred on to the desired carrier. A typical specification is the
undesired carrier level with 30% modulation needed to
cause 1 % modulation of the desired carrier level.
frequency, the burst amplitude is increased and the picture
will become harsh with excessive overshoots.
Similar problems can occur on any specific channel simply
due to mis-tuning or L.a. drift. In particular, as the L.a. frequency drifts high and the chroma subcarrier amplitude increases, the sound carrier also increases and chroma/
sound beats will appear in the picture. In the U.S. the chroma/sound carrier beat is at 920 kHz (4.5 MHz-3.58 MHz)
and appears as a herringbone pattern while the audio modulates the sound carrier. This 920 kHz beat can also be
caused by detector non-linearities, and after the video detector by the detected 4.5 MHz sound intercarrier mixing
with the chroma subcarrier in subsequent receiver stages. If
turning down the color level control removes the 920 kHz
beat then a better 4.5 MHz trap is needed at the video detector output.
Crossmodulation is particularly likely to occur in cable systems and is usually observed as sync bars drifting through
the picture: In particularly severe cases the interfering picture can actually be seen. High signal levels at the input of
the mixer are a frequent cause of crossmodulation, particularly when high gain R.F. stages are used to obtain a low
tuner noise figure (N.F.). But when AGC is applied the
crossmodulation source often shifts to the R.F. device.
When overload occurs, (measured as the total harmonic
distortion of a specified modulation frequency), the peaks of
the R.F. carrier waveform become compressed and this will
show up at the video detector as a smaller sync pulse amplitude (sync tip to black level). Since the AGC system oper,
ates on the sync tip level the effective result is that the black
level appears to go blacker than black-i.e. some near
black information will be lost and the picture will appear to
have too much contrast. Alternatively if the subseque"'t receiver circuits have black level restoration the screen brightness increases and picture tube blooming on peak whites
may occur. As overload increases there is a strong chance
that vertical sync will be lost. Generally the tuner mixer device is the first stage to overload, followed by the R.F. stage.
While overload is caused by very strong signal strengths
and therefore may appear to be of limited concern it can
also occur at weak to intermediate signal strengths because
of incorrect AGC threshold settings and this will be discussed in detail later.
These preceding comments are not meant to imply that the
tuner is the root cause of all the nasty phenomenae that can
be observed in the picture display. Overload, Channel 6
beat and video noise are very dependent of the tunerll.F.IAGC interaction. To understand why this is the case,
we need to look at the demands that the input signal field
strength puts on the system.
Z
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IF OUTPUT
•
Lynn IF
AIIPLtFIER
11 AGC
INPUT
21
SPECTRUY
ANALYSER
Lynn YCO
II
TUNE TO
Cit FREa.
0.011'1.
-
n
CONTROL
PIN
TLlH/8421-16
FIGURE 15. Checking the pcb for Excess VCO Pick-up
24
7
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12
5
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;
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8
o
10
100
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20
IK
I
4
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1
10
10K
IF AMP GAIN - 3 dB
20
SUPPLY CURRENT (mA)
RESISTANCE (PIN 3 TO PIN 4)
TL/H/8421-17
TLlH/8421-1 B
FIGURE 16. Fourth I.F. Amplifier Stage
Gain with External Resistor
nected to the 12V power supply can be used, but the maximum value is limited in practice to less than 5000 at intermediate frequencies because of stray p.c.b. capacitance
and the loading of the detector stage input impedance of
3 kO. The stage gain for a total load impedance of Z is given
by Equation (2)
AV = lZ1/48
(2)
SELECTING THE I.F. GAIN
The last part of the I.F. amplifier concerns the power supply
input at Pin 5. This is a shunt regulated input with a nominal
value of 6.3V and the I.F. amplifier current is delivered
through a dropping reSistor from the 12V rail supplying the
remainder of the IIC. The 0.01 /l-F ceramic r.f. decoupling
capaCitor at Pin 5 should be grounded through very short
Clearly the LM1823, with all the gain provided by five I.F.
amplifier stages and with 34 dB detector conversion gain,
has a more than adequate gain margin to provide signal
sensitivity and compensate for interstage filter losses. To
show how this gain may be distributed we can look at a first
cut design example.
FIGURE 17. I.F. Amplifier Voltage
Regulator Current Requirement
leads--preferablyon the copper side of the p.c.b. A nominal
current level into Pin 5 is 32 mA, set by a 1800 resistor. This
current should not exceed 60 mA and the minimum current
is about 20 mA, below which the I.F. amplifier will start to
lose gain as Pin 5 voltage drops below the regulated level.
863
....
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Z'
2)
Hz=I ....
Hz=1IOA
K=1.ot
k . .t
W.=ltX10I RlDS/SEC
W. =2Xlo'RADS/sm
r3d8
="!(H>;
F'3da • +to KHz
TL/H/8421-29
867
-f?
z
c
.-------------------------------------------------------------------~
in the leading edge of a color bar as the VCO belatedly
attempts to track the phase change. For these types of signals it is desirable to increase the loop bandwidth to about
500 kHz-changing R2 to 6800 is an easy fix. The loop
damping factor is kept greater than 1 to avoid ringing on the
phase transients. Larger loop bandwidths will increase the
possibility of luma/sound/chroma crosstalk.
Once the VCO is iocked in phase to the I.F. Signal, the DC
phase shifter Pin 22 is normally around 4 VDC' for peak
detector efficiency. Usually some extra phase lag will be
introduced since a subjectively crisper picture is obtained if
picture transients have an overshoot. Between 12% and
20% overshoot without ringing is desirable, corresponding
to a 400 mV to 800 mV sOift in Pin 22 voltage.
24
20
/
4
o
L
/'
VIDEO DETECTOR POST AMPLIFIER
The response of the video amplifier is rolled off above
9 MHz to minimize the amount of the VCO waveform and its
harmonics appearing in the output at Pin 16. Typical oscillator. products are 40 dB below the desired signal level.
Zener diodes are used in the video amplifiers for level shifting so that the use of PNP transistors Is avoided and the
detector linearity is .preserved. Excellent differential gain
characteristics are obtained-typically less than 3%. Pin 16
is a Darlington NPN emitter follower output. With no detector CW input signal, Pin 16 is at 7.6 VDC, representing zero
carrier level which is slightly higher than peak white
(by 12%%). As the CW input increases, Pin 16 voltage decreases towards black level with the sync pulses produCing
the most negative detector level.
The level reached by the sync tips is determined by the
AGC loop threshold and if the Internal AGC comparator is
used (Pin 16 is directly connected to Pin 17), the sync tips
will be clamped at 4 VOC. This produces a nominal detector
output of 3.2V (p-p) but this IS subject to variations in the
Pin 16 detected zero carrier level. The resistive network
shown connected between Pin 16 and Pin 17 in Figure 30
can be used to change the zero carrier level at Pin 17 for an
adjustable recovered video level. For best performance the
recovered video level should never be less than 1V (p-p) or
greater than 4V (p-p). In suppressed sync systems, the recovered video at Pin 16 is routed to the descrambler for
restoration of the sync amplitude before it is applied to Pin
17. Obviously the signal DC content must be preserved
through the descrambler If proper AGC action is to be maintained.
/
V
\ .. 1/
4.0
4.5
5.0
5.5
AGC Self Gating Comparator (LM1823)
The AGC comparator input has a low pass filter to protect
the AGC loop from noise Interference. Conventional detector systems often use noise gates to prevent the AGC system "backing off" on noise peaks that occur below the sync
tip level. It is difficult to set the noise gate threshold close
enough to the sync tip level for it to provide any benefit
without risking AGC lock-out. For the LM1823 however, syn-
VOLlS (PIN 22)
TLlH/8421-30
FIGURE 28. Signal Overshoot Produced
by Carrier Detection Phase Shift
7IC
115
2K
....-01.
¥IDEO
OUTPUT
TL/H/8421-31
FIGURE 29. LM1823 Detector and Video Amplifier
868
l'
2 leA
12V
2kA
51(1
12V
10kA
17
151eA
51 leA
14
TLIH18421-32
FIGURE 30. LM1823 Selt Gating AGC Comparator
chronous detection allows the noise gate to be eliminated.
Since the noise is random phase, the synchronous detector
will not rectify the noise voltage and the low pass filter can
average out the noise input to the comparator.
Further protection of the AGC comparator is provided by
gating the comparator on only during the sync pulse period.
The gate pulse is obtained from the input video waveform
sync pulses at Pin 16. Essentially an emitter coupled sync
stripper circuit, the slice level is set by an external time con-
stant at Pin 14. During the sync pulse period the capacitor at
Pin 14 is being charged toward ground potential and the
comparator is gated on. Between sync pulses the capacitor
discharges towards the positive supply voltage through the
resistor and the comparator is off. The sync slice level is
determined by the Pin 14 RC time constant and is given in
Equation (3) as the number of millivolts the slice level is
above the sync tip voltage.
V SLICE = 1/2 RC (mV)
(3)
12Y
12Y
F
AGe
15K
AGe
IIIlAY
1-O+I~2OK
I
I
I
I
I
I
I
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151(
0.1.1.
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I
I
I
I
I
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--------------------------------------_.
-
FIGURE 31. RF AGC Amplifier
869
TLIHI8421-33
;
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r------------------------------------------------------------------------------------------,
for Signal amplitude transients at high R.F. signal levels (tuner in gain reduction). AC changes on Pin 13 are coupled to
the threshold level control allowing the I.F. amplifier to gain
reduce (or increase) during the signal transient. This happens only during the signal change, so that the detected
video returns more rapidly to the proper output levels. Once
signal equilibrium is restored, the appropriate gain balance
~een the R.F. and I.F. amplifiers returns.
A typical slice level for a 3V (o-p) video signal is between
100 mVand 250 mV. Different slice levels can be obtained
with other capacitor values (the resistor should be left unchanged). Small capacitors will allow a faster response to a
fluctuating sync tip level but also may cause the consequently deeper slice to include video overshoots.
RE AGC DELAY AND OUTPUT AMPLIFIER
The I.F. amplifier is at full gain below 4 VDC on Pin 13. At
anywhere from 5.5 VDC to 6.5 VDC we will want to shift gain
control into the R.F. stages, and this is accomplished by a
delayed AGC threshold control at Pin 12. When the filter
vol1age on Pin 13 is O.7V above the pre-set level on Pin 12,
the R.F. AGC amplifier at Pin 11 will start to sink current.
The capacitor shown connected between Pins 12 and 13 is
optional and intended to provide an increase in AGC action
.. CONCLUSION
This note has described a high quality video I.F. amplifier!
detector combination that can provide excellent baseband
video signals. A complete schematic of the external components required in such an application is shown in Figure 32,
with a. suitable p.c.b. layout in Figure 33.
12.
31lk
•
...........__-+--oAFC
OUTPUT
10k
12.
180
11M
IF INPUT
12.
&Ok
15k
DE~:~.----------~f+1
2Dk
ADJUST
v
15.
TL/H/8421-34
SAW Filter-MuRata SAF45MC!MA
L1-9 VaT} #22wire
L2-4 VaT
on 3.16" form with
L3-6 VaT
HF core, shielded
All caps in uF unless noted
FIGURE 32, LM1823 External Circuit Components
8t:O
.----------------------------------------------------------------.~
z
~
...
TL/H/B421-35
FIGURE 33. LM 1823 Printed Circuit Board Layout (Component Side)
871
! LM2889 R.F. Modulator
oct
Introduction
T.wo IIC ~F modulators are available that have been espeCially designed to convert a suitable baseband video and
audio signal, up to a low VHF modulated carrier (Channel 2
through 6 in the U.S., and 1 through 3 in Japan). These are
the LM1889 and LM2889. Both IIC's are identical regarding
the R.F. modulation function-including pin-out&-and can
provide either of two R.F. carriers with dc switch selection of
the desired carrier frequency. The LM1889 includes a crystal controlled chroma subcarrier oscillator and balanced
modulators for encoding (A- Y) and (B-Y) or (U) and (V) color
difference signals. A sound intercarrier frequency L-C oscillator is modulated using an external varactor diode. The
LM2889 replaces the chroma subcarrier function of the
LM1889 with a video dc restoration clamp and an internally
frequency modulated sound intercarrier oscillator.
Modulation Parameters
In the U.S., either of two R.F. channels is made available so
that the user can select a vacant channel allocation in his
geographic area, thus avoiding co-channel problems with
National Semiconductor
Application Note 402
Martin Giles
older receivers that have inadequate shielding between the
antenna input and the tuner.
The characteristics of the R.F. signal are loosely regulated
by the FCC under part 15, subpart H. Basically the signal
can occupy the standard T.V. channel bandwidth of 6 MHz,
and any spurious (or otherwise) frequency components
more than 3 MHz away from the channel limits must be
suppressed by more than - 30 dB from the peak carrier
level. The peak carrier power is limited to 3 mVrms in 750
or 6 mVrms in 3000, and the A.F. signal must be hard-wired
to the receiver through a cable. Most receivers are able to
provide noise-free pictures when the antenna signal level
exceeds 1 mVrms and so our goal will be to have an R.F.
output level above 1, mVrms but less than 3 mVrms. Since
the distance from the converter to the receiver is usually
only a few feet, cable attenuation will rarely be a problem
but mis-termination can change both the amplitude and rei:
ative frequency characteristics of the signal.
The standard T.V. channel spectrum has a picture carrier
located 1.25 MHz from the lower band edge. This carrier is
amplitude modulated by the video and sync signal. In the
SOUND
osc
r-----~--~t_--t_--------~~------.-~~---o vcc
MOD
DEPTH
RF
OUTPUTS
VIDEO
AUDIO
~I-4'---I--",
o----{2l---.....I
RF
OSCILLATORS
CHANNEL SELECT
FIGURE 1. The LM2889 Block Diagram With External Components
872
TL/H/8452-1
Modulation Parameters (Continued)
1-----
o
-10
~,I
-20
III
I I
(db)
-30
-40
-----------1
FCC EMISSIONS LIMIT
,.
I'
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I, \
,,
I
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\
\
\
,
,,
I
75% SATURATED
BAR PATTERN
-50
PIX
CARRIER
CHROMA
.1
1--4.5 - - - - - . ,
3.0--~t-1.25+1-3.58
~-----6.0-----_01+--
3.0
FREQUENCY (MHz)
TLIHIB452-2
FIGURE 2. Television Channel R.F. Spectrum
case of a color Signal, a second subcarrier is added
3.58 MHz above the picture carrier. The sound or aural carrier is 4.5 MHz above the picture carrier and is frequency
modulated with the audio signal to a peak deviation of 25
kHz. This audio signal has pre-emphasis above 2.1 kHz (a
75 "'S time constant). Similar modulation methods and standards are used in Japan and Europe.
channel and consists of bandpass and harmoniC filter sections. A broadcast transmitter uses a separate modulator for
the sound carrier and this is added to the picture carrier via
a diplexer before'reaching the transmitting antenna. Close
control is maintained on the picture and SOund carrier frequencies to keep a 4.5 MHz spacing between them. This
tight frequency control is used to advantage by the majority
of television receivers which employ intercarrier sound circuits. The I.F. amplifier processes both the pix and sound
I.F. carriers and detects the 4.5 MHz difference frequency at
the video detector stage. This frequency modulated sound
intercarrier is then stripped of amplitude modulation by a
high gain limiter circuit and a quadrature demodulator recovers the audio.
With the picture carrier located near one end of the channel
bandwidth, most of the available spectrum is used by the
upper sideband modulation components. Only modulating
frequencies within 0.75 MHz of the carrier frequency are
transmitted double sideband and the lower sideband is truncated by'at least - 20 dB compared to the peak carrier level
by the time the lower channel edge is reached. This is referred to as Vestigial Sideband (VSB) modulation and since
most R.F. modulators are double sideband, a VSB filter is
used at the transmitter output. A filter is needed for each
The LM1889 and LM2889 use a slightly different modulation
scheme to that described above for several reasons. For
circuit economy L-C oscillators are used to generate the pix
RF
OSCILlATOR
61.25 MHz
VIDEO
II
61.25
1\
cur
64.83
II )\l
61.25
64.83
65.75
RF
OSCI.LAlOR
65.75 MHz
AUDIO
TLIH/8452-3
FIGURE 3. Broadcast Transmitter Block Diagram
873
1=r@1-~ ~
LI
y---61.25
--~
II " ..
1"65.75
64.83
TL/H/8452-4
FIGURE 4. LM1889/2889 Sound and Video Modulation
-40 I.R.E. is the synchronization portion of the signal. The
usefulness of this scale is that the standard composite video signal will always have a sync amplitude that can be
normalized to 40 I.R.E. Similarly the color burst amplitude is
always 40 I.R.E. For a 1V (p-p) video Signal, an I.R.E. unit is
equivalent to 7.5 mV.
carrier frequencies. The stability of such oscillators is good
enough for the AFT circuits in modern receivers to maintain
picture quality, but if a separate L-C sound carrier oscillator
were used, the relative drift of the two carrier frequencies
would be much too great for intercarrier sound receivers.
For example, ,a typical television sound circuit tuned to
4.5 MHz will generate as much as 3% distortion if the difference between the R.F. carriers changes by 15 kHz. Apart
from the difficulty of setting the initial frequency with sufficient accuracy, it is unlikely tl:lat two L-C oscillators could be
kept within 15 kHz of each other at 60 MHz to 100 MHz
operating frequencies. However, when the audio signal is
modulated onto a 4.5 MHz intercarrier oscillator frequency
and this carrier is used to modulate the picture carrier, we
have only the 4.5 MHz oscillator drift to worry about.
A less obvious problem, but nevertheless significant if good
audio quality is to be obtained, is incidental carrier phase
modulation (ICPM).Even broadcast transmitters cannot
maintain an invariant carrier phase as the modulation depth
changes. Without feedback loops to control ICPM, a broadcast transmitter can produce from 3 degrees to as much as
30 degrees phase change as the carrier mo~ulation decreases from sync tips to peak white. While the separate
sound carrier is unaffected by this ICPM of the pix carrier,
on reception in the intercarrier sound receiver the phase
shift with picture information is transferred onto the 4.5 MHz
sound intercarrier. This results in a phenomenon known as
sound buzz. Even with exceptionally careful p.c.b. layout, an
IIC modulator with L-C oscillators can expect the pix carrier
frequency to change with modulation depth. Fortunately, by
modulating the sound signal as a 4.5 MHz intercarrier onto
the pix carrier, the ICPM occurs equally in both R.F. carriers
and will not be detected by the intercarrier receiver.
Although the video is amplitude modulated on the carrier
waveform, the carrier amplitude only decreases from the
unmodulated level. This contrasts with standard AM where
the carrier level alternately increases and decreases about
the unmodulated level. For a television signal, the peak unmodulated level corresponds to sync tip level and increasing brightness levels cause decreaSing carrier levels. To
prevent complete suppression of the carrier (and consequent loss of the sound intercarrier in the receiver) the peak
white Signal is limited to a maximum modulation depth of
87.5% of the peak carrier. Returning to our I.R.E. scale we
can see that from peak carrier to zero carrier is equivalent to
160 I.R.E. (140/0.875 = 160). One obvious consequence
of this modulation scheme is that the video signal MUST BE
dc coupled to the modulator. AC coupling will cause .the
peak carrier level to change with modulation scene brightness (standard AM) and the sync modulation amplitude will
change. This spells trouble for the receiver sync circuits and
the changing R.F. carrier black level will cause errors in displayed brightness-the picture will "wash out" or disappear
into black.
The LM2889 uses doubly balanced modulator circuits with
an L-C oscillator switching the upper transistor pairs. The
signal is applied across the lower transistor pairs. If the signal input pins 10 and 11 are at the same dc potential, the
100
Video Modulation
IRE
The baseband input to the modulator is in an easily recognized composite format and this is a convenient pOint at
which to introduce the I.R.E. scale. This is an oscilloscope
scale divided into 140 units. The video portion of the signal
representing the scene (picture) brightness levels will occupy the 0 to 100 I.R.E. portion of the scale, with 0 I.R.E. as
black level and 100 I.R.E. as peak white level. From 0 to
SCALE
TL/H/8452-5
FIGURE 5. Video Modulating Signal
(In t.erms of the I.R.E. Scale)
874
Video Modulation (Continued)
be clamped to 5.1 VDC by the dc restorer circuit, pin 10
should be biassed at 5.1V + 2.29V = 7.4 VDC. A look at
the R.F. carrier output will confirm that now the syncs occupy from 100% to 75% of the peak carrier, and that white
modulates the carrier down to 12Yz% of the peak. To maintain the proper modulation depth the clamp at pin 2 will
track with supply voltage changes, allowing the bias at pin
10 to be set with a resistive divider connected between the
supply and ground.
1W
FIGURE 6. LM2889 VIdeo DC Restoration Clamp
If the video signal polarity is reversed with positive syncs,
either a dc coupled signal or an external dc restorer should
be used that places the signal sync tip voltage towards the
upper end of the common-mode input range at pin 11,
which is 9 VDC with a 12V supply. Pin 10 is then offset
below pin 11 voltage by the required amount for proper
modulation. An input level of 2V (p-p) is optimal. Signal amplitudes of less than 1V (p-p) are also useable but internal
offset voltages and the potential for carrier feedthrough or
leakage to the output stage may make it difficult to maintain
good R.F. linearity at peak modulation depths. Signal swings
larger than 3V (pop) shou.ld be avoided since this will produce relatively large AC/DC current ratios in the modulator
and the resulting modulator non-linearities can cause a
carrier is completely suppressed. As the offset voltage between pins 10 & 11 is increased. the carrier output level
increases. With II 750 output load resistor, the conversion
gain of the R.F. modulator is 20 mVrms/volt. A dc restoration circuit at pin 2 of the LM2889 allows the composite
video to be ac coupled from the preceding stages, giving
the designer flexibility in the video processing Circuits (unless an LM1886 is being used as a video source, it is unlikeIy that the composite video dc level will be correct, even
with dc coupled video sources). On a 12V supply, pin 2
clamps the sync tip of the video waveform to 5.1 VDC.
Therefore, if we have a 2V (P-p) signal, one I.R.E. is equivalent to 14.3 mV and 160 I.R.E. is 2.29V. This is the required
offset across the modulator input pins and since pin 11 will
920 kHz beat between the chroma and sound carriers.
Although only one video input is required, the LM2889 has
two balanced R.F. modulators and two R.F. carrier frequency oscillators. Selection of the carrier frequency is by dc
switching the supply voltage to the relevant oscillator tuned
circuit. This automatically shuts off the other oscillator and
modulator circuits. For test purposes when an output R.F.
VSB filter isn't used, or when only one carrier frequency is
needed, the output pins 8 and 9 can be wired together with
a common load resistor. Providing two channel operation
with two independent oscillator/modulator circuits is much
superior to using a single modulator and attempting to
change carrier frequency by switching the tuning components of a single L-C oscillator. The latter method involves·
TUH/8452-6
1W
O---t-------~----------------~~--------..~ ~H
240
75
240
10K
. VIDEO
FIGURE 7. LM2889 R.F. Modulator and Oscillator (one channel)
875
TL/H/8452-7
oscillator differential pair and preventing start~up. The inductor value is chosen to resonate with the capilcitor in series
with the crystal at slightly less than the desired operating
frequency. About 20% less will allow the inductor to be fixed
tuned. Close to its series resonant frequency (normally the
3rd overtone) the Crystal will provide the additional inductive
reactanqe necessary for the circuit to oscillate. The equillalent resistance of the crystal at the operating frequency will
affect the tuned circuit a and hence the peak-ta-peak drille
to the modulator circuit. Smaller capacitors in series with the
crystal (with corresponding changes in the inductor valu,)
will push the operating frequency closer to anti-resonance
and produce large equillalent resistances dropping the osciUator drive level. Larger capacitance values cause the operating frequency to approach 'series resonance and a lower
equivalent resistance (approaching Rs for the crystal, which
is of the order of 400 to 1000 at 60 MHz). This can produce
higher drille levels but risks operation at the lower overtones. to prevent lower frequency oscillation a resistor can
be connected across the crystal. Also a small' resistor in
series with one of the collector leads will form a low pass
filter with the output capacitance and suppress spurious oscillations at higher frequencies. If this is needed, resistor
values less than 300 should be used, so that dc offsets will
not prevent the oscillator from starting. For the circuit of
Figure 8, capacitor values betwE!8n 20 pF and 56 pF, with
the appropriate inductor value, work well with only Slightly
reduced oscillator drive compared to the conventional LIC
circuit.
Video Modulation (Continued)
use of isolating diodes (if unbalanced operation with attendant feed through problems is to be avoided) and expensive
trimmer capacitors for tuning the second carrier frequency.
A further disadvantage is the need to switch the VSB filter at
the R.F. output.
The LM2889 oscillator configuration is the familiar cross
coupled differential amplifier type, with level shifting zener
diodes used to prevent the transistors from saturating with
large oscillator output swings. The oscillator frequency is set
by the tuned circuit components (f = 1/21TV[C), and the
load resistors connected to the supply will set the oscillation
amplitude and drive level to the modulators as well as deter·
mining the circuit working a.
As might be expected, there are conflicting requirements on
the practical range of working a's. A high a is desireSble
from the viewpoint of stability, but higher working a's (set
mainly by larger load resistors) increase the drive level to
the modulator. Above 350 mV (p-p) the modulator will have
attained full conversion gain and the R.F. output levetwill be
determined by the amplitude of. the video input signal. Unfortunately increased drive levels will also increase the carrier frequency second harmonic output from the modulator.
Although a fully balanced design is used, parasitic capacitances on the emitters of the switching transistor pairs will
rectify the oscillator waveform and this produces high levels
of second harmonic. Load resistors much larger than 2400
can produce a level of second harmonic matching the fundamental. Since relatively small load resistors are required
(much smaller than the tuned circuit dynamic reSistance)
the working a will be dominated by these resistors.
Vee
The acceptable degree of frequency stability will depend on
the intended application, but L-C oscillators have proven to
be adequate for most purposes. We can gain an idea of the
frequency stability that' is possible by conSidering the frequency drift produced by changes in the oscillator internal
phase. A change in internal phase shift can be caused either by temperature or supply voltage changes but, as the
LM2889 data sheet shows, the supply voltage dependency
is low. Between 12V and 15V the frequency is essentially
constant and changes by less than 30 kHz over the entire
supply voltage range. With temperature, the internal oscillator phase shift changes by about 2 degrees. over a 50 degree Celcius temperature range. If the tuned circuit a is 15,
then at 61.25 MHz (Ch 3 pix carrier) the oscillator frequency
must change by - 92 kHz to produce a, compensating 2
degree phase shift. If the a is 30, then the frequency would
change by less than -45 kHz etc.
TLlH/II452-8
FIGURE 8. R.F. Crystal 08clliator Circuit
For high circuit a, a large capacitance is desireable, but the
inductor cannot be made too small if it is to, remain the
tuning element. This keeps the practical range of capacitance values to between 50 pF and 100 pF. USing a 75 pF
capacitance, at 67.25 MHz the required inductance is just
under 0.08 ""H and the working a is 15 with 2400 resistors
connected on either side of the tuned circuit to the supply
voltage. Depending on the coil type, the number of turns for
this inductance will be from 1% to 3% giving over 10 MHz
tuning range. This is more than enough to compensate for
component tolerance and variations in overall internal
phase lag from IIC to IIC.
The Sound Carrier Oscillator
Before mOving to the R.F. output and the VSB requirements,
we need to look at anothe~ signal that will be added to the
baseband video-the aural intercarrier. Both the LM1669
and the LM2889 have L-C sound carrier oscillators operating at 4.5 MHz. Frequency modulation of the LM1889 sound
oscillator is achieved by an eXternal varactor diode which
alters the tuning capacitance in response to the amplitude
of the'audio signal. The LM2889 has a similar tuned L-C
oscillator but the frequency deviation is obtained by internally phase shifting the oscillator current. This is done by a low
pass filter connected to the oscillator which provides a lagging phase voltage component of the oscillator waveform at
the input to a differential amplifier. The current output from
If better frequency stability of the carrier frequency over that
provided by an LlC circuit is needed, then crystal control of
the oscillators can be used. It is necessary to retain the
inductor, since a dc short is required across the oscillator
pins to avoid a collector current imbalance off-setting the
876
Sound Modulation
this amplifier is controlled by the audio signal amplitude so
that more or less of the current (now in quadrature to the
original oscillator current) is added back to the tuned circuit
producing the desired shift in the output frequency. Phase
offsets of up to + 12 degrees with increasing audio input
levels will yield very low audio distortion (less than 0.2%).
Also the use of a lagging oscillator waveform component
reduces harmonic levels within the oscillator and a reduced
possibility for undesired signals contaminating the R.F.
waveform.
1~+1~
The tuned circuit operating 0 is important in two respects.
Similar to the R.F. oscillator tuned circuits. the 4.5 MHz
tuned circuit should have a high loaded 0 for stability. but
the circuit bandwidth must also be wide enough to accommodate the FM sidebands produced by the audio modulation. For a maximum frequency deviation (~f) and maximum
modulating frequency f. the minimum bandwidth is given by
Equation (1).
(1)
B-W :?: ~f (2.5 + 411 Af)
The other requirement is that the maximum phase deviation
of the oscillator current is able to produce the maximum
frequency deviation (~f) of the carrier. This is given by
Equation (2).
~f = 4.5 x 106 X 0.12/0
(2)
1~
!
4.5 MHz
OSC1UAlOR
1 AUtlIO
-900
Table I summarizes .the results of calculating the maximum
circuit 0 that satisfies Equations (1) and (2) for the various
monaural sound modulating standards used in the U.S. and
Europe.
TUH/8452-9
FIGURE 9. LM2889 Sound Carrier FM Modulator
TABLE I
Af
Modulation
Bandwidth
25kHz
73kHz
125 kHz
400 kHz
UK
50kHz
200kHz
,;;30
,;;15
Continental
Europe
30kHz
150kHz
,;;36
,;;22
System
USA
Mono
Stereo
Qmax
Modulation
Deviation
,;;36
,;;21
';;12
';;7.4
BIAS
2KA
":"
FIGURE 10. LM2889 4.5 MHz Sound Oscillator and Modulator
877
TL/H/8452-10
cal and other methods to set the oscillator frequency must
be used. Since a crystal will provide the neCessarY temperature and voltage stable reference frequency a PLL is a useful solution (see Figure 11). Either the widelY available 3.58
MHz crystals or a 4.5 MHz crystal can b~ used, but in either
case, the LlC tank circuit frequency I'TII,Ist be divided down
before application to the phase detectpr. This is because
frequency modulation of the sound carrier will'" produce
many radians of phase deviation at the phase detector input-for a modulation frequency of 100 Hz and a peak deviation of 73 kHz the carrier phase change is given by Equation 3.
'
8 = at/fm = 73 x 103/100 = '730rads
(3)
Since the linear input range of most phase detectors is less
than 21Tradians, the modulated canierinput must be divided down by at least 233 to keep the:phase deviation within
this linear range. For 'a 4.5 MHz crystal, tl)~, reference frequency divider M and the sound oscillator divider N are the
same. Available ripple counters such as the 74HC4040 and
74HC4060 can easily divide by 128 (for monaural) or by 256
for stereo. If a 3.58 MHz crystal is used the M:N divider ratio
is 35:44 requiring substantially more packages, and the odd
numbered divider must be followed by ari even divide of 2 or
4 to "square up" the input waveform to the "hase detector.
Also, since the video will include a chroma subcarrier, good
isolation is needed to prevent the reference oscillator beating with the chroma sidebands.
Asuitable I'hase, detector is the 74C932E~cl!Jsive- Or type
with a'sensitivitY of 1.6 volts/radian. ThEi filter at the detector output prevents the input modulation from reaching the
varactor diode and distorting the audio. Even so, the loop
filter must have some ac bandwidth for a reasonable acquisition time and other dynamic characteristics. The components shown in Figure 11 have been chosen such that with
a varactorsensitivity of 100kHz/volt the loop has a hold-in
range of over ± 150 kHz, with a lock-up time of less than 0.5
seconds. The T.H.D. is less than 1% for a 400 Hz modulating frequency producing 25 kHz deviation of the carrier. The
accuracy of the sound car,ier frequency is, of course, that of
, the crystal used for the reference oscillator.
Sound Modulation (Continued)
Cleatly.the deviation phase offset'dominates the circuit a
requirement.
If we choose a a of ar6und 10, then the oscillator drift With
temperature (assuming a 2 degree phase change In 'osoilfs-<
tor current with a 50 degree rise In, temperatui'e)ls of th~
order of '- 9 kHz. A typical receiver will, generate less than
3% distortion at'peak deviations with this much frequency
drift but if better peftormance is required, then the circuit a
can be raised. High modulation linearity Will still be retained
with a a of 20 and the OSCillator maximum frequency drift
will be halved. Alternatively temperature compensated tuning capacitors can be used (between N20 and N75). When
higher circuit ,a's than 20l\l"e employed, increased audio
input levels will, produce the desired peak frequency deviations but with the possibility of increased modulation distortion. The actual operating parameters that are selected can
be balanced, between distortion as a result of modulation;
and distortion in the receiver circuits as a result of oscillator
frequency drift.
To ensure that we have a sufficient 4.5 MHz oscillator level
to provide enough drive to the internal phase shift circuit,
the load impedance at pin 13 should be greater than 3.5 kno'
A second requirement is that we have enough oscillator lev~,
el to generate the desired aural carrier amplitude when
modulated on the picture carrier. This means that load impedances greater than 6 kn are desireable. At 4.5 MHz, a
typical oscillator coil ot'231£H wili have,an unloaded a of 55 '
and tune with '55 pF.For a working Q 'Of 10, the external
damping resistor Is 7.5 kn.
'
Stereo Sound
The introduction in the U.S. of a multiplex stereo sound system (the BTSC system combining the Zenith MCS proposal
with dbx noise reduction in the stereo difference channel)
with peak carrier deviations in excess of 73, kHz puts even
larger constraints on the tank circuit a. Following the same
rules as before, the maximum allowable a for low distortion
is now less than 7.4-with a loaded a of 5 being likely, With
this loaded a, maintaining a carrier center frequency accuracy better than 5 kHz with an L/C circuit becomes impractiI
8
ICt' 74C132
74HC'4040
8
Icz
lea
1i:1
2 3 4
r
8
13
11
10
"- 18
I,
f--;- +258
+M
H~'/£F
3
10 PIN 1
: LM 2889
~F
.. ~ MV1404
~
Vee
Ic2
r
'~,Y
+6V
+N
,
74HC4080,
1501<
I
18
"
lea
.
J
+
1K
",'
t;?1/£F
' 14 --:;:. 218 ':"
12:,11 '
8
~
10
"..'-~fj:O~~
T
XTAL:4.5 MHz
-==
82pF
FROM PIN 13
LM2889
FI~U~E
82pF
TL/H/8452-11
11. 4,5 MHzCrystalReferen~ ,elre,uJt "
878
Audio Processing For Sound
Carrier Modulation
meter is used, peak levels of + 10 dB are possible while the
meter is indicating OVU. Obviously without processing the
audio to keep it within predetermined limits, the input level
calibration will be somewhat empirical in nature.
If we assume the decrease in spectral energy above 10kHz
is such that overrnodulation peaks above this frequency are
unlikely to occur, then we can allow a signal at 10 kHz to
produce full modulation deviation. Since the amplitude of
most audio signals at 10kHz is at least 6 dB below the
midband frequency level, we can calibrate the audio input
with a -6 dB amplitude, 10 kHz tone to produce 100%
deviation. As we shall see later, a frequency close to 10kHz
will make the measurement of actual peak deviations very
easy indeed. With the standard pre-emphasis network, at
signal frequencies less than 2 kHz, the modulating signal
amplitude at pin 1 will be - 8 dB below the anticipated peak
10 kHz level producing 100% modulation. This corresponds
to a modulator input level of 118/2.2 = 45.4 mVrms. The
With the proper tuned circuit Q (see Table I), a linear increase in the amplitude of the audio signal will produce a
correspondingly linear increase in the frequency deviation.
TeleviSion receiver sound circuits in the U.S. have a 75 p.s
de-emphasis and in Europe frequencies above 3.2 kHz
(SO p.s) are de-emphasized at a 6 dB/octave rate. This is
done to help improve the SIN ratio of FM reception and the
transmitter incorporates the complementary pre-emphasis
characteristic-above 2.1 kHz the audio frequencies are
boosted at a 6 dB/octave rate. The consequence of this
modulation scheme is that if a 0 dB peak signal amplitude at
15 kHz is capable of producing a 25 kHz deviation than a
similar amplitude signal at 400 Hz will produce a peak deviation of only 3 kHz-a loss of some 18 dB in SIN ratio for the
midband frequencies. Broadcasters usually employ compressors to enable high modulation levels to be obtained at
mid-band frequencies without overrnodulating high frequencies. If the audio input to the LM2889 is being sourced from
an original broadcast (a scrambled Signal decoder output for
example) than this audio-without de-emphasis-can be directly applied to pin 1 of the LM2889, and the overall input
level is adjusted so that the modulation limits are not exceeded except for brief intervals (less than 10 instances per
minute). When the audio has not already been processed a
different set of conditions will apply and an audio pre-emphasis network is required at pin 1.
45MHz
I
,,
:..{!
1
.lt - - II....)- ~I
~f~K1Jrfr
15
1
R
l,
LU2UI
20
RELATIVE
AMPLITUDE
(dB) 10
--
~:::I!
S
........:
"
NO MODULATION
~~
-
T s R211"2.1
C=
-'
x 103
0
1./
.......
I+-- 10.4KHz
-l8dS
~=5OUS
V
V
- 1\\
111
J
-
~
100
lK
10K
-
INCREASING MODULATION
TLlH/8452-12
AF=25KHz
FIGURE 12. Audio Pre-emphasis
Since the audio source is likely to be at a relatively low
impedance (a pre-amplifier output), the pre-emphasis network will also be used to attenuate the level of the average
audio input to the LM2889 as well as providing a relative
boost to the higher frequencies. The input sensitivity of the
audio modulator is 150 Hz/mV which means that
118 mVrms will give a peak deviation of 25 kHz.
Next we have to decide what Signal frequency and amplitude to use in calibrating the audio input. Unfortunately the
75 p.s time constant for FM broadcasting was chosen $t a
time when equipment limitations meant there was relatively
low spectral energy at higher frequencies. Today, modern
audio material is not well suited to boosting above 2.1 kHz
since energy peaks at only -6 dB can be obtained at
10kHz. A further complication is the ability of the audio level
meter to predict high energy peaks. If a conventional VU
/
111
--
v
...,J\..., "
-
III
I\,
APPROACHING CARRIER NULL
TL/H/8452-13
FIGURE 13. FM Spectrum with Increasing
Audio Amplitude (t mod = 10.4 kHz) 4.5 MHz
Sound Carrier Level
879
Audio Processing For Sound
Carrier Modulation (Continued)
input resistance at pin 1 is, 1.5 kfl. so Rl = 30 kO, if we
assume an input source level of 1 Vrms at 400 Hz. ,For a 2.,1
kHz breakpoint, C· = 0.0027 /!oF.
carrier. This is conventional AM and a 4.6V (p.p) signal will'
yield sound carrier sidebands at -6 dB r!llative to the ,picture carrier; If we require a ,sound, carrier amplitude at
-17 dB, the signal coupled to pin 10 must be 11 dB below
4.6\1 (p-p), or 1.3V (p..p). This is obtained by using a4.7,kfi
resistor coupled through a O.lp.F capacitor to pin 10, and ,a
second, 2.7 kO resistor. connected to the wiper arm ,of the
potentiometer used to set the video modulation depth. The
effect of the potentiometer,setting on the aural carrier,level
is eliminated by a 0.1 p.F capacitor connected from tha,wiper arm to'ground. However, since the impedance presented
by the potentiometer will, for all practical purposes, be rela'
tively constant, the capacitor could be removed and the parallel resistance of the upper and lower arms of the potentiometer, network used to provide ,the second resistor" of
2.7 kn. If the video input level. is well controlled, it may be,
possible to replace the potentiometer with a fixed divider.
Anyone who has observed the output from an FM circuit
with a spectrum analyzer will know that for a fixed modulating frequency the output spectrum will consist of the carrier
frequency component and sidebands spaced by the modulating'frequency from the carrier: As the modulation amplitude is increased (the modulation index rn becomes larger),
the carrier decreases to a null and then increases again.
The modulation indices for which carrier: nulls occur can be
calculated and for our purposes it is important to know that
the first carrier null occurs at m = 2.4048:' FoC' a system
maximum deviation of 25 kHz the modulating frequency f is
given by:
(4)
f '" 25 x lOS/2.4048 = 10.4 kHz
Therefore, if we use an input frequency of 10.4 kHz, as the
input amplitude is increased, the firsf carrier null will indicate
peak deviation. if we continue with our assumption of a
- 6 dB level at 10kHz, calibration consists of adjusting the
audio input so that a -6 dB, 10.4 kHz Signal causes the first
carrier nUll. With the above'pre-emphasis network, this
should correspond to 500 mVrms at 10.4 kHz.
The final part of the design concerns the outPut stage, and
involves' meeting' the constraints applied by any regulatory
agenCy. In the U.S., apart from the need to restrict the peak
carrier output level to less than 3 rhVrms in 750, we have
two Signals prasent in the outpllt whose' level 'will eltceed'
the spurious emission limit of - 30' dB with respect to the
peak carrier level. One of these signals is thEi result of amplitude modulating the 4.5 MHz intercarrier audio on the picture carrier. Apart from the desired -17 dB sound carrier
amplitude (upper sideband) an equal amplitude lower sideband will be present. For channel 3 this is at a frequency of
56.75 MHz-which 'is '250 kHz outside our channel lower
limit. Therefore we need to provide at least 13 dB more
attenuation at this frequency in the output filter. The second
unwanted emission (or emissions) Is the result of carrier frequencyharl1lonics--Specifically the 2nd harmonic level produced by high modulator drive. To suppress, this, from
-18 dB to -30 dB attenuation at 123 MHz is required.
We have already looked at the tuned circuit parameters at
pin 13 in terms of deviation Ih'lElarity and OSCillator stability.
With a working Q of 10, the 'effective load at pin 13 is
6.2 kO. The oscillator current Is 0.45 mA so that the output
amplitude at 4.5 MHz is 3.6V (p-p). Some portion of this
oscillator signal level is coupled over to pin 10 to set the
sound carrier level and this ban be done by splitting the
external 7.5 kO damping resistor into two parts. The picture
carrier level is set by the offset voltage between pins 10 and
11 as described earlier. For a 2V (p-p) video signal this offset is 2.3V. Since the 4.5 MHz signal will be accoupled over
to the bias pin 10, it will amplitude modulate the picture RF
~~--.------o 12V
(vuo L£V£L 'IV (P-P) )
12V
IS
l1Y
12V
10
L112819
-,
Tl/H/8452-14
FIGURE 14. Audio Intercarrler Coupling to the Video 'Modulator R.F. Output anci V.s.s. Filter
880
Audio Processing For Sound
Carrier Modulation (Continued)
With a properly constituted baseband signal modulating the
carrier, these are the only intrinsic unwanted emissions we
are concerned with. Normal video modulation components
appearing in the lower sideband will not have sufficient amplitude and do not extend beyond the lower channel limit.
Even so, the filter requirements are not trivial.
the filter. Since the output of the filter will normally be terminated in 750 to match the cable (and provide triple transit
echo suppression for a SAWF), the best way to choose the
load resistor is to monitor the output to the cable and apply
a dc offset between pin 10 and 11 that is equivalent to the
expected video input. The resistor is then chosen to give the
desired peak carrier level of 2.5 mVrms. The carrier should
be unmodulated since downward modulation will reduce the
mean carrier level by as much as 2-3 dB.
If L-C filters are used, this can be done with three coils per
channel but some alignment procedure will be required. Fortunately SAW filters are available from several sources
which, although more expensive than the equivalent L-C filter, avoid the cost of production alignment. Usually the SAW
filter will have a substantially greater insertion loss, but the
LM2889 has enough output level to compensate for this.
Both Single channel and dual channel filters are available
and in the latter case the LM2889 dual oscillator/modulator
configuration enables easy dc switching between channels.
A coil may be required, connected across the SAWF input,
to tune out the SAWF input capacitance.
I! the offset voltage between pin 10 and 11 is reduced, a
check can be made on the residual carrier level at the output. This residual level is the result of oscillator feedthrough
in the modulators and extemal coupling from the oscillator
tuned circuits. The residual carrier level is normally better
than -26 dB below the peak carrier level, ensuring good
modulation linearity. High levels of residual carrier can be
caused by coupling through ground or power supply leads.
A good technique to minimize the effect of unwanted pickup is to decouple the supply voltage to pin 8 and 9 load
resistors over to ttie output connector shield ground. This
removes at the output any carrier Signal on the supply line to
the load reSistors.
.
The load resistors connected to pins 8 and 9 will set the
LM2889 conversion gain, which for 750 is typically
20 mVrms R.F. carrier per volt offset at the input pins 10
and 11. The actual load will include the input resistance of
12V
cmNND. 3 FILlER
754
.16.
1804
'r'I
U/ 2889
INOUCTORS jdI
CAPACIIORS pF
12V
HI·
10
"r
754
62
-
0---4--...- -...- ......
2004
2004
8
U/ 2889
CHANND. 3 AND 4
TL/H/8452-15
FIGURE 15. Vestigial Sideband FIRers
881
N·r-----------------------------------------------------~
~
Z
500 Hz): Once the band
frequencies have been selected, circuit a; and the values
for the series tuned circuits may be calculated. The following formulae find general use In equalizer design.
Band spaCing Is often measured in units of octaves. An 0ctave covers a frequency ratio of 2: 1, e.g. the frequencies
between 1000 and 2000 Hz constitute an octave as do the
frequencies between, 200 Hz and 400 Hz. The number of
octaves contained between any two frequencies is given by
the equation
(I of octaves = LOG(F2/Fl)/LOG(2)
(1)
where F2 > Fl. Another formula used In conjunction with
equalizer' design Is that which finds the musical center between two frequencies:
center frequency = .JF2f=1
(2)
As an example consider 2 frequencies, 220 Hz and 440 Hz.
These are at an interval of 1 octave. At first glance it might
appear that 330 Hz is halfway between these two, but as far
as the ear can discern, 311 Hz Is eqUidistant from 220 Hz
and 440 Hz. This is because the ear hears logarithmic
changes in pitch equally.
3kI
D~ D~ D~
TUH/8864-2
LEVEL
D5
D4
Da
D2
D1
Do
FLAT
0
0
0
0
0
0
1 dB
1
0
0
0
0
0
2
0
1
0
0
0
0
3
0
0
1
0
0
0
4
0
0
0
1
0
0
5
0
0
0
0
1
0
6
0
1
0
0
1
0
7
1
0
1
0
1
0
8
0
1
0
1
1
0
9
0
0
0
0
0
1
10
1
0
1
0
0
1
11
1
0
1
1
0
1
12
1
0
1
1
1
1
FIGURE 2. Digitally Controlled Variable Rell.tor
The frequency and bandwidth characteristics of each band
are set by the LlC networks (Figure 1) and the value of
each aesociated variable resistor. At resonance, the LlC
network reduces to zero impedance. In the boost mode this
leaves amplifier I with a gain set by the ratio of Re and
Ro+Rv. Conversely, attenuation Is obtained in the cut
mode with amplifier /I buffering the circuit composed of Rc,
Ro and Rv. Off resonance, the series tuned LlC network
presents a high impedance and the gain (or attenuation)
reduces to 1. Since the characteristics of the equalizer are
determined by external LlC networks, the designer can tailor the equalizer circuit to suit his own needs.
Although It may seem that by relocating the switches of
Figure 1 a single bank of resistors could be used for boost
and cut, this has not been done. Unlike mechanical
switches, CMOS switches exhibit a finite ON resistance of
several hundred ohms which unfortunately is not constant
when large signal voltage swings occur acroes the switch.
For a signal source with a nominal 1 Vrms level, with 12 dB
BAND SELECTION
In most consumer equalizers the band frequencies are
equally spaced and centered around 1 kHz. The bands are
related to each other by some factor. For example, 7-band
equalizers with a 1 kHz center frequency use a factor of 2.5.
If 1 kHz is repetitively multiplied and divided by 2.5 the other
band frequencies will be found: multiplying (and rounding)
we find 2.5 kHz, 6.3 kHz and 16 kHz, and dividing yields
400 Hz, 160 Hz and 63 Hz.
884
The formulae for QMAX cause the -3 dB pOints of any two
bands to occur at approximately the same frequency. If this
is not desired, the maximum Q may be set to any value by
appropriately designing the resonant networks. Higher values of Q give greater definition between bands while lower
values of Q gives less ripple response between adjacent
bands.
If the desired control range is defined, the center frequency
can be found with the formula
center band = .JFMAXFMIN
(3)
and the factor
(4)
FMIN represents the lower -3 dB point of the "bottom"
band when it is in full boost and all other bands are flat.
FMAX is the analogous higher -3 dB point of the "top"
band. "d" is the number of bands. These formulae can be
combined as
( FMAJ(!!!..=..2)( FMIN~)
Once the maximum Q has been determined, Land C (from
Figure f) may be calculated:
Ln = 2270QMAX/tIln
(10)
Cn = 1/(tIln2Ln)
(11)
(5)
Note that 22700 is the minimum resistance including the
6800 resistor (Ro), switch resistance and SiChrome resistance (Rv) as shown in Figure f.
A common misconception about equalizers is that the band
frequencies relate to the frequency response of the instrument. This is not true at all-the flat frequency response of
the equalizer is completely independent of the band frequencies. Even so, many equalizer designs have bands extending beyond the normal range of hearing while compromising control at low frequencies.
Using the typical7-band consumer center frequencies (factor = 2.5) and a QMAJ( = 1.05 (from equation 8), the following values are calculated:
Fn =
2d
2d
where "n" is the band number (from 1 to d).
There is no magiC in spacing band frequencies. While equal
spacing can offer control over a wide frequency range, it is
possible to enhance control over a limited range by closely
spacing the bands in one area while spreading out the remaining bands elsewhere. This technique (modified spacing) is especially useful at frequencies below 500 Hz where
speakers and listening environments have pronounced resonances and antiresonances.
Band
Frequency (Hz)
Lo(mH)
Co(nF)
2
3
4
5
6
7
63
160
400
1000
2500
6300
16000
6040
2380
952
381
152
60.4
23.8
1060
416
166
66.5
26.6
10.6
4.16
The inductances required at low frequencies would seem
prohibitive, but there is an easy solution. The LMC835 is
designed for use with series resonant networks. Since the
inductances required are quite large and discrete realizations would be expensive, a simulated inductor, also called
a gyrator, may be used.
SELECTION OF MAXIMUM Q
The maximum desired Q of each band occurs at full boost
or full cut and is set by the values of Ro + Rv, Lo and Co.
Mathematically QMAX is a function of the adjacent band frequencies:
GYRATOR DESIGN
The properties of an Inductor may be simulated by a simple
op amp circuit (often called gyrator) as shown in Figure 3.
The impedance seen at the input terminal is jtllRLROCL and
the inductance is given by the product RLROCL. As shown,
Ro represents a loss resistance in series with the Inductor.
The internal SiChrome resistors are designed to accommodate an Ro of 6800.
(6)
where QMAX is the maximum Q of F2 during full cut or boost,
and Fa and F1 are the adjacent band frequencies. The highest and lowest bands on an equalizer have only one adjacent band. In this case:
QMAX = ABS
( F2~)
- F1
(7)
where F1 is the adjacent band. In terms of a factor:
Q
.JfiCfOr
MAX = factor - 1
(8)
In terms of FMIN and FMAX:
Q
2d4FMAX/FMIN
MAX = d.JFMAX/FMIN
1
(9)
TLlH/S884-3
FIGURE 3. Simulated Inductor
885
U')
q
bility.,'A ,100 pF feedback capacitor compensates most op
amps with little effect on the, audio performance of the
equalizer.
' A t ' high frequencies the impedance of, the 'gyrator should
Z '
approach infinity, but several effects limit the maximum imc(
pedanee. The result is an increase in high frequency gain as
contributed by the boost section, and a decrease in high
frequency gain as contributed by the cut section.
Gyratorinipedance is ultimately limited by the loading effects of RL, especially for smaller inductances since RL necessarily' becomes small. To reduce . loading effects· keep
RL>47 kO. In extreme cases CL and RL can be buffered by
a second op amp as shown in FigurB 4.
The voltage divider action caused by stray capaCitance at
the junction of CL and RL also reduces gyrator impedance.
This effect is minimized by keeping CL>470 pF. Bootstrapping (Figure 5) is Ii viable alternative for reducing the effects
of stray capaCitance.
'
rLM833
TLlH/8664-4
FIGURE 4: BuffereCl Gyrator'
An important' gyretorperformance factor is the gain and
phase of the op amp at high frequencies. An op-amp unitygain bandwidth of at least 10 MHz is recommended since
poor frequency response will reduce the gyrator impedance
at high frequencies. Phase shift through the op amp causes
the gyrator to become capacitive. The LM833 is an excellent choice for a gyrator as its bandwidth is well over 10
MHz, and it is unity gain stable.
Signal path stability and high frequency gain accuracy are
affected by the feedback loop around the first amplifier of
Figure 6. Most op amps cannot tolerate stray capaCitance
on their inverting input since it reduces the phase margin.
This leads to increased gain at high frequency, if notinsta-
TLlH}8664-5
FIGURE 5. Bootstrapped Gyrator
7.3k
1
1
1
'I
3.4/c
1
1
1
1
1
1
II
1
1
1
1
1
,I
1
1
1
TLlH/8664-6
FIGURE 6. AC Coupled Signal Path
'886
SWITCH LEAKAGE
When the CMOS switches are OFF, a small leakage current
of typically 1 nA can flow either into or out of any of the
gyrator connections. This current charges Co until a state of
eqUilibrium is reached. If one of the switches is now closed,
the charge stored on Co will be injected into the signal path
possibly causing an audible "pop" in the output. A 100 kO
resistor is all that is necessary (as shown in Figure 6') to
bleed this charge away and prevent pops. This results in a
gain error or less than 0.2 dB at maximum boost or cut.
sary to provide a DC path around the op amps. Since the
majority of applications require a "popless" configuration,
the internal 7.3 kO resistors have been adjusted to accommodate the effects of the external 100 kO resistors. If DC
coupling is not used, the 100 kO signal path resistors should
be included to insure gain accuracy.
A complete seven-band graphic equalizer circuit is shown in
Figure 7.4700 resistors are used in series with the output
amplifiers to isolate capacitive loads that could cause instability. To increase signal handling capability the input is attenuated 6 dB by two 27 kO resistors and then equally amplified in the output buffer. With this configuration the maximum signal level at the input (with flat equalization) is about
9 Vrms yet the LMC835 sees only one-half of this-less
than its + / -7.5V supply limitation. Clipping is still possible
if, for instance, a 9 Vrms input is boosted 12 dB. There is
sufficient headroom to handle full boost on a 2 Vrms input
signal. Gyrator component values are shown in Figure 8.
Provision is made to convert the equalizer to a + /- 6 dB
control range. The 3.4 kO resistors shown in Figure 6, when
selected, drop the control range to +/-6 dB with approximately 0.5 dB steps. When the 3.4 kO resistors are selected, the resultant changes in the Signal path DC gain can
produce pops. Op amp input offset voltage and bias current
are the root cause; the solution is to AC couple the Signal
path to the LMC835. In addition to the three 47 ,.,.F coupling
capaCitors of Figure 6, two 100 kO resistors are also necesINPUT
CHANNEL
B
DATA
- .••
I
I
I
•
I
••••• •••••
DIGITAL
GROUND
_~.~
_____ •• ~~"ON
RLEAK
Cn lOOk
6.8k
INPUT
CHANNEL
B
TL/H/8664-7
FIGURE 7. Complete 7·Band Graphic Equalizer
887
~ r-------------------------------------------------------------------------~
i
z.,
Zl,8
Z2,9 '
23,10.
. Z4,11
Z5, 12
Z6,13
'Z7,14
fo(Hz)
Co(F)
CL(F)
RL(O)
1,...
470n
150n
68n
22n
IOn
4.7n
lOOn
33n
15n
6.8n
3.3i1
1.Sn
680p
lOOk
lOOk'
lOOk
plished by connecting pin 1 to pin 27 and pin 4 to pin 25.
P,ins 2 and 3 are left. open, a,nd any ul"1l!sed gyrator pinsara
.simply tied off to ground. The ± 6 dB range is selected by
activating only one set of ±6 dB. resistors, and lIith~rset will
do.
In applications requiring .15 to 28 bands a second LMC 835
can'be cascaded as shown in Figure 10. Note that the. output buffer of the first LMC835 is made redundant by the
input amplifier of the second LMC835. Therefore only 3 signal path op amps are requi~ed instead of 4.
RO(O)
'0'
63
. 160
400
lk
2.5k
6.3k
16k
8~J(
82k
62k
47k
680
680
680'
680
680
.. 680
680
FIGURE 8. Gyrator Component Values
PARALLEUNG FOR MORE BANI;)!?
The two halves of an LMC835 can' be paralleled to provide
up to 14 monaural bands. Paralleling (Figure 9) is accom-
, t :t
. 10k
,,..
~
L.
.
;!:
47,...
+
-
28
27
+
26
25
..
"'-
1
3.4k
7.3k
7.3k
3.4k
'~{
TO
BANDS
8-14
)
"
TO
BANDS·
1-.-
3:4k
.7jk
7.3k
1
2
3
3.4k
>
{
~~
4
TLfHf8564-8
.FIGURE· 9. Paralleling for 8 to 14 Banda on One Chip
27
26
Lt.t~35
LIotC835
(14 BANDS)
(14 BANDS)
FIGURE 10
886
25
TLfHf8664-13
PROGRAMMING
addressed. A timing diagram is shown in Figure 11. Note
that bit DO is shifted in first, 07 last. Figure 12 shows the
coding used for band and gain selection. With the maximum
clock rate of 500 kHz, the entire equalizer can be programmed in less than 500 ,",so
Parallel entry of data is possible using a simple word generator circuit as shown in Figure 13. A clock signal is applied
continuously, and DO through 07 are loaded and shifted into
the LMC835 commencing with the positive edge of a start
pulse. CLOCK, DATA and STROBE signals are all automatically generated and sequenced. DO through 07 could be
supplied by a parallel data bus or even toggle switches.
A three wire interface consisting of a DATA, CLOCK and
STROBE line (Figure 7) is provided for programming the
LMC835. DATA bits are shifted in to an internal serial register on positive CLOCK edges. This data is then latched (and
executed) by a low-going pulse on the STROBE pin. A separate digital ground pin is provided to prevent contamination
of the sensitive analog signal path.
Programming is accomplished with two 8-bit words. The first
word selects a band for adjustment and selects either of ± 6
or ± 12 dB control range. The second 8-bit word selects
boost or cut and the desired level for the band previously
u
BAND
~ELECT
'
J11
Lr
~UP
L
DATA
DON1 CARE
CHANNEL A t6/12dB
CHANNEL B :l:6/12dB
I
1 (1)
GAIN CODE
L o=OPEN
~
[1 = CLOSE
1
LDATA
GIIOUP 2(0)
O=CUT
1 = BOOST
RANGE
1 = i6dB 0= :I: 12dB
TVH/8664-9
FIGURE 11. TImIng DIagram
(CH A:BAND I N7, CH B:BAND $N14)
CH A :I: 12 dB RANGE, CH :I: 12 dB RANGE.
CH A :I: 12 dB RANGE, CH :I: 12 dB RANGE,
CH A:I: 12dB RANGE, CH :I: 12dB RANGE,
CH A :I: 12dB RANGE, CH :l:12dB RANGE,
CH A :I: 12 dB RANGE, CH :I: 12 d8 RANGE.
CH A :l:12dB RANGE. CH :l:12dB RANGE.
CH A :I: 12 dB RANGE. CH :I: 12 dB RANGE.
CH A :I: 12 dB RANGE. CH :I: 12 dB RANGE.
CH A :I: 12 dB RANGE. CH :I: 12 dB RANGE.
CH A :I: 12 dB RANGE. CH :I: 12 dB RANGE.
CH A :I: 12 dB RANGE. CH :I: 12 dB RANGE,
CH A :I: 12 dB RANGE. CH :I: 12 dB RANGE.
CH A :t 12 dB RANGE. CH :I: 12 dB RANGE,
CH A :I: 12 dB RANGE. CH :I: 12 dB RANGE.
CH A :I: 12 dB RANGE. CH :I: 12 dB RANGE,
CH A :I: 12 dB RANGE. CH :I: 12 dB RANGE.
CH A :I: 12 dB RANGE. CH :I: 6 dB RANGE.
CH A:I: 6dB RANGE. CH B:I: 12dB RANGE.
CH A:I: 6dB RANGE. CH B:I: 6dB RANGE.
NO BANO SELECTION
BAND 1
BAND 2
BAND 3
BAND 4
BAND 5
BAND 6
BAND 7
BAND B
BAND 9
BAND 10
BAND II
BAND 12
BAND 13
BAND 14
NO BAND SELEtnON
BAND I NI4
BAND INI4
BAND INI4
BAND CODE
CH B :l:6dB/12dB RANGE
CH A :l:6dB/12dB RANGE
DDN1 CARE
DATA I
D7
This is Ihe gain if !he ± 12 dB range is
saiected by DATA I. if Ihe ±6 dB range is
selected, Ihen Ihe values shown must be
approximately halved.
flAT
I dB BOOST
2dB BOOST
3dB BOOST
4d8 BOOST
5dB BOOST
6dB BOOST
7dB BOOST
adB BOOST
9dB BOOST
10dB BOOST
II dB BOOST
12dB BOOST
I d8N12dB CUT
L
L
L
L
L
L
L
L
L
L
L
L
L
L
TVH/8664-10
DATA II (BAND SELECllON)
os D4 D3 D2 DI
X
L
L
L
L
L
H H L
L
L
L
H L
H L
L
L
H L
L
H L
L
H L
L
H L
L
L H
H L
L
L
H L
H L
L
H
H H L
H L
H
H L
H L H H
L
L
H L
L
L
H H L
H L
L
H H L
H H L
H H L
H H H
L
VAUD ABOVE INPUT
D6
LL
L
BOOST/CUT
DATA n
L
L
L
L
L
L
L
L
L
H
H
H
H
GAIN CODE -
FIGURE 12. CodIng InformatIon
889
DO
TVH/8664-11
2 .....- - - -..
v+
V+ 07 06 05 04
OJ
02 01 00
TL/H/8664-12
FIGURE 12. Teat Word Generator
APPLICATIONS
Several distinct advantages are associated with computer
controlled equalizers. Remote control is possible unlike con- .
ventional mechanically controlled equalizers. Since the
LMC835 is programmed by a simple 3-wire interface, hardwired control from a remote location is also possible. This is
useful on stage or in the studio where the equalizer must be
located near the source and the amplifiers and/or speakers,
but the control point is behind the audience or in a control
room. The 3-wire digital interface Is easier to connect than
attempting to route low-level analog signal lines over long
distances between signal source and control point.
Microprocessor storage of various equalization settings is
possible. Specific sellings for different instruments, diverse
890
program material, or perhaps multiple speaker or listening
environments can be accessed as easily as recalling a
pocket calculator memory. If a real time analyzer (RTA) is
included in the equalizer, automatic equalization is possible.
In this application pink noise is played through the amplifierl
speaker system, and a calibrated microphone feeds the resultant spectrum back to the RTA. One band at a time, the
controlling microprocessor adjusts the LMCB35 equalizer
for flat response. Two or three iterations are required since
the adjustments are interactive.
By using analog circuit techniques, the LMC835 is able to
achieve 0.0015% distortion, 114 dB signal to noise ratio and
20 dB headroom relative to a 1 Vrms input signal. This performance is suitable for use with conventional analog audio
sources as well as digital audio formats.
A 150W IC Op Amp
Simplifies Design of
Power Circuits
National Semiconductor
Application Note 446
Robert J. Widlar
Apartado Postal 541
Puerto Vallarta, Jalisco, Mexico
Mineo Yamatake
National Semiconductor Corp.
Santa Clara, California
Abstract: A power op amp capable of driving ± 35V at
± fOA has been fabricated on a single silicon chip. Peak
power ratings to BOOW allow it to handle reactive loads. The
Ie incorporates intemal management circuitry to insure
smooth tum on and automatic protection from a variety of
fault conditions; this includes instantaneous peak-temperature limiting within the power tranSistors. The op amp is described briefly, but emphasis is placed on the practical problems encountered in designing with power amplifiers. Numerous application examples are also given.
Ing shorts to the supplies. Dynamic safe-area protection is
provided by peak-temperature limiting within the power transistor array. The tum-on characteristics are controlled by
keeping the output open-circuited until the total supply voltage reaches 15V. The output is also opened should the
case temperature exceed 150'C or as the supply voltage
approaches the BVCEO of the output transistors. The IC
withstands overvoltages to 100V.
introduction
Advances in IC technology have produced a power amplifier
that is an order of magnitude more powerful than its predecessors. Unlike other IC's, its peak dissipation rating is
many times higher than continuous, as is required for handling reactive loads. Protection circuitry is also more effective. The performance of the new IC, the LM12, puts it in the
same class as discrete and hybrid ·amplifiers. However, it
offers far more effective control of tum on, fault and overload conditions in addition to the economies of monolithic
construction.
In the late 1960's, the availability of low cost IC op amps
prompted their use in rather mundane applications, replacing a few discrete components. This power op amp now
promiSes to extend this to high-power designs. Replacing
single power transistors with an op amp may become costeffective because of improved performance, simplification
of attendant circuitry, vastly improved fault protection, greater reliability and the reduction in design time.
The LM12 is supplied in a steel TO-3 package with four
throug~ leads, plus case. A gOld-eutectic die attach to a
molybdenum interface is used to avoid thermal fatigue problems with power cycling. Two voltage grades are available;
both are specified for either the military or industrial temperature range.
Table I, Some tYpical characteristics of the LM12 for Vs
= ±40VandTC = 25'C.
parameter
input offset voltage
input bias current
voltage gain
output voltage swing
peak output current
continuous dc dissipation
pulse dissipation
Some 'applications are given here to illustrate op amp design principles as they relate to power circuitry. Unusual design problems that have cropped up in using the LM12 in a
wide variety of situations with all sorts of fault conditions are
identified along with solutions.
.
power output
total harmonic distortion
bandwidth
slew rate
supply current
theopamp
conditions
VOM =0
VCM=O
RL=40
lOUT = ±1.5A
±10A
VOUT= 0
Tc= 25'C
100'C
toN = 10ms
1 ms
0.2ms
RL = 40
RL=40
Av = 1
RL=40
lOUT = 0
value
2mV
150nA
50VlmV
±38V
±35V
±13A
90W
55W
120W
240W
600W
150W
0.010/0
.700 kHz
9V/,..s
60mA
general advice
The performance of the LM12 is summarized In Table I. The
input common~mode range extends to within a volt of the
positive supply and to three volts above the negative supply.
No input-polarity reversal is exPerienced should the inputvoltage range be exceeded, and no damage results should
the inputs be driven beyond the supplies.
Power op amps are subject to qlany of the same problems
e)(perienced with general-purpose op amps. Excessive input
or feedback resistance can cause a dc offset voltage on the
output because of bias-current drops, or it can combine with .
stray capacitances to cause oscillations. Improper supply
bypassing and capacitive loading, alone or in combination,
can also result In oscillations. Many hours spent tracking
down incomprehensible design problems could !lave been
saved by monitoring the op amp output with a wide-band
oscilloscope.
The IC is compensated for unity-gain feedback, with a
small-signal bandwidth of 700 kHz. Slew rate is 9V I ,..S, even
as. a follower. This translates to a 60 kHz power bendwidth
'under load with Ii ± 35V output swing. The op amp is stable
. with or without caPacitive loading; the maximum load capac, itance depends upon loop gain. Thereare no spurious output stage oscillations, and a series-RC snubber is not required on the output.
With low impedance loads and current transients above
10A, the inductance and resistance of wire interconnects
can become important in a number of ways. Further, an IC
op amp rated to diSSipate 90W continuously will not do so
unless it is properly mounted to an adequate heat sink.
The IC delivers ± 10A output current at any output voltage
yet is completely protected against output overloads, includ891
can drive the output beyond the supplif.ls. Figure 1 shows
the oVf.lrload respoilse of thf.l LM12 driving ±36V at 49 Hz
into a 40 load in sf.lries will) 24 mH to iIIustratf.l the point.
The IC has internal supply~lamp diodes, but theSe clamps
have a parasitic current that dissipates roughly· half the
clamp current across the total supply voltage. This dissipation cannot be controlled by the internal protection circuitry
and will result in catastrophic failure if sustained. Therefore,
the use of external diodes to clamp the output to the power
supplif.ls is strongly recommended.
The management and protection circuitry of·the LM12 can
_. -alse affect operation. Should thf.l total supply lIoltage ex;,Ceed ratings or drop below 15V, the op amp shuts off com. pletely.Case temperatures above 150·C alse cause complete shut down until the temperature drops to 145·C. This
may take several seconds, depending on the thermal system. Activation of dynamic safe-area protection causes both
the main feedback loop to lose control and a reduction in
output drive current, with possible oscillations.' In ac applications, the dynamic protection will cause waveform distortion.
supply bypassing
All op amps should have their supply leads bypassed with
low-inductance capacitors having shQrt leads and located
close to the package terminals to avoid spurious oscillation
probl~ms. Power op amps require larger bypass capacitors.
.The LM 12 is stable with gopd-quality electrolytic bypass capaCitors greater" than 20 ,...F. Other considerations may· require larger capacitors.
The current in the supply leads is a rectified componem of
the load current. If adequate bypassing is, not provided, -this
distorted signal can be fed back into intemal circuitry. Low
distortion at high frequencies requires that the $uppljes be
bypassed with 470 ,...F or more, at the package'terminals.
3:
£
~
2
~
i
o 8
I
-2
.
-4
-60
0
10
15
20
25
i
liME (mo)
TLlH/8710-27
lead Inductance
With ordinary op amps, lead-inductance problems are usually restricted to supply bypassing. Power op amps·are alse
sensitive to inductance in the output lead, particularly with
heavy capacitive loading. Feedback toth" input should be
taken directly from the output terminal, minimizing common
inductance with the: load. Sensing to a remote load must be
accompanied by a high-frequency feedback path, ,directly
from the output terminal. Lead inductance can alse cause
voltage surges on the supplies. With long leac:ls to the power
seurce, energy stored in the lead inductance when the output is shorted can be dumped back into the supply bypass
capacitors when the short is removed. The magnitude of
this transient is reduced by increasing the size of the bypass
capacitor near the IC. With 20 ,...F -local bypass, these voltage surges are Important only if the lead length exceeds a
couple feet (> 1 ,...H lead inductance). TWisting together the
supply and ground leads minimizes the effect.
Figure 1. Output voltage and current waveforms with
dynamic ute-area protection activated on an
Inductive load. Stored energy In 'the Inductor
drives the output beyond the supplies.
Expf.lrlencf.l has demonstrated that hard~wlre shoftlng the
output to the supplies can induce random failures If these
f.IXIernai clamp diodes are not used. Therefore, it is prudent
to use output clamp diodes. even when the load is not obviously inductive. Failure is particularly violent when operating
from low-impedance supplies: the V+ pin can vaporize, with
a hole being blown through the top of the can. If there are
failures, install diodes before proceeding.
.
Heat sinking of the clamp diodes Is I!sually unimportant in
that they only clamp. current transients. Forward drop with
15A transients is of greater concern. The clamp to the negative .supply can have somewhat reduced effectiveness
should the forward drop exceed O.8V. Mounting this diode
to the op amp heat sink improves the situation. Although the
need has not been demonstrated, including a third diode, D3
In Figure 2, will eliminate any concern 'about the clamp di·
o.des. This diode, however, must be capable of dissipating
continuous power as determined by the negative supply cur·
rent of the op amp.
ground loop.
With fast, high-current circuitry, all sorts of problems can
arise from improper grounding. In general, difficulties can be
avoided by returning all grounds separately to a ·common
pOint. Sometimes this is Impractical. When compromising,
special attention should be paid to the ground returns for
the supply bypasses, load and input signal. Ground planes
also help to provide proper grounding. .
..
Many problems unrelated to system performance dan be
traced to the grounding of line-oPerated test equipment
used for system checkout. Hidden paths are particularly difficult to sort out when .several pieces of test equipment are
used but can be minimized by using current·probes or'the
neVi isolated oscilloscope preamplifiers. Eliminating any ·direc! ground connection between the signal· generator and
the oscilloscope synchronization input solves one common
problem.
.
.
IN
TL/H/8710-6
Figure 2. Output clamp diodes, D1 and D2. dump Indue.
tlve-Ioad current Into the supplies when op
amp g088 Into po.wer limit. A third diode, D30
maY.be required Uthe. forward drop of D2 Is
exce~ve.
.
output clamp diodes
When a Push-pull amplifier goes into PQwer lirnit.whilf,l driving an inductive load, the energy stored in t~ inductance
892
reactive loading
The LM12 is normally stable with resistive, inductive or
smaller capacitive loads. Larger capacitive loads interact
with the open-loop output resistance (about 10) to reduce
the phase margin of the feedback loop, ultimately causing
oscillation. The critical capacitance depends upon the feedback applied around the amplifier; a unity-gain follower can
handle about 0.01 ,...F, while more than 1 ,...F does not cause
problems if the loop gain is ten. With loop gains greater than
unity, a speedup capacitor across the feedback resistor will
aid stability. In all cases, the op amp will behave predictably
only if the supplies are properly bypassed, ground loops are
controlled and high-frequency feedback is derived directly
from the output terminal, as recommended earlier.
So-called capacitive loads are not always capacitive. A
high-Q capacitor in combination with long leads can present
a series-resonant load to the op amp. In practice, this is not
usually a problem; but the situation should be kept in mind.
Large capacitive loads (including series-resonant) can be
accommodated by isolating the feedback amplifier from the
load as shown in Figure 3. The inductor gives low output
impedance at lower frequencies while providing an isolating
impedance at high frequencies. The resistor kills the Q of
series resonant circuits formed by capacitive loads. A low
inductance, carbon-composition resistor is recommended.
Optimum values of Land R depend upon the feedback gain
and expected nature of the load, but are not critical. A 4 ,...H
inductor is obtained with 14 turns of number 18 wire, close
spaced, around a one-inch-diameter form.
A feedback capacitor, C1, is connected directly to the output
pin of the IC. The output capacitor, C2, is connected at the
output terminal with relatively short leads. Single-point
grounding to avoid dc and ac ground loops is advised.
The impedance, Z1, is the wire connecting the op amp output to the load capacitor. About 3 inches of number-18 wire
(70 nH) gives good stability and 18-inches (400 nH) begins
to degrade load-transient response. The minimum load capacitance is 47 ,...F, if a plastic film or solid-tantalum capacitor with an equivalent series resistant (ESR) of 0.10 is used.
Electrolytic capacitors work as well, although capacitance
may have to be increased to 200 ,...F to bring ESR below
0.10.
Loop stability is not the only concern when op amps are
operated with reactive loads. With time-varying signals,
power dissipation can also increase markedly. This is particularly true with the combination of capacitive loads and
high-frequency excitation.
Input compensatfon
The LM12 is prone to low-amplitude oscillation bursts coming out of saturation if the high-frequency loop gain is near
unity. The voltage follower connection is most susceptible.
This glitching can be eliminated at the expense of smail-signal bandwidth using input compensation. Input compensation can also be used in combination with LR load isolation
to improve capacitive load stability.
An example of a voltage follower with input compensation is
shown in Figure 5a. The R2C2 combination across the input
works with R1 to reduce feedback at high frequencies without greatly affecting response below 100 kHz. A lead capacitor, C1, improves phase margin at the unity-gain crossover
frequency. Proper operation requires that the output impedance of the circuitry driving the follower be well under 1 kO
at frequencies up to a few hundred kilohertz.
Extending input compensation to the integrator connection
is shown in Figure 5b. Both the follower and this integrator
will handle 1 ,...F capacitive loading without LR output isolation.
L1
4",
IN
> .....-Jyy.,.
....R1
OUT
4.7
TLlH/S710-7
Figure 3. Isolating capacitive loads with an Inductor.
The non-Inductive r.alstor avoids resonance
problems with load capacltanca by dropplngQ.
OUT
IN~-.JV'.'IY-""'-I
The LM12 can be made stable for all loads with a large
capaCitor on the output, as shown in Figure 4. This compensation gives the lowest possible closed-loop output impedance at high frequencies and the best load·transient response. It is appropriate for such applications as voltage
regulators.
TL/H/S710-9
a)tollower
IN Jt,A1'v1--.....--I
R3
5k
C2
0.22",
OUT
OUT
IN
--------------~~
TLlH/8710-10
TLlH/S710-S
b) Inverter
Figure 4. Using a large output capacitor to stabilize for
all capacitive loada. The Impedance, Zt, la the
wire connecting the Ie output to the load-ca·
pacltor terminal.
Figure 5. Ualng Input compenaatlon to reduce bandwidth and Increaae stability with capacitive
loads a) for a voltage follower and b) tor an
Integrating Inverter.
893
parallel operation.
current drIve
·Load current beyond the· oapability of one· power' amplifier
can be obtained with parallel operation as shOwn in Figute
6. The power op amps, A2 and As are wired as followers
andc::onnected in parallel with the. outputs coupled through
equalization resistors, R4 and Ri;. More output buffers, with
individual equalization resistors, may be added to. meet
even higher drive requirements. A standard, high,vOltlige op
amp is used to prOllide voltage gain. Overall ,feedback compensates for the voltage dropped ac~oss· the equalization
resistors.
The circUit in Figure 8· provides an· output current·proportlon·al to ,the input voltage, Current drive is sometimes preferred
for servo motors because it aids in stabilizing servo loops by
reducing phase lag caused by motor Inductance. In applications requiring high output resistance, such as operational
power supplies running in the·current mode, matching of the
feedback resistors to 0.Q1 percent· or better is required. Alternately, an adjustable resistor, R3, can be used for trimming. Offsetting. R3· from its optimum value will give dacreasing' positive or negative .output resistances ..
The current ·source· input is· actually differential. It can be
driven as shown, or from the bottom of R3· to obtain the
opposite output sense. Both inputs should be connected to
a low source impedance like ground or an op amp output.
Otherwise, the source resistance will imbalance the'feedback, changing output resistance. Alternately, an input can
be driven by· a known source resistance, like a voltage divider, if thi\! resistance is made part of the feedback network.
R4
0.1
IN
OUT
·RS
0.1
RIO·
10k·
I _ R2Vln
out - Rl RS
TL/1iI/8710-12
>-.....W_-,OUT
FIgure 6•. Parallelrng the outputs of two op amps. The
,
power amplifIers. A2 and Aa. are wired ail followera and connected In parallel with the outputa.coupJed ,through equalizatIon reslators.
With parallel operation there will be an increase in unloaded
supply current related to the ·offset voltage of A2 and Aa
across the equalization resistors~ In some cases; ifmay be
desirable to use input compensation on the followe;S for
increased stability. It is important that the source resistance
introduced by inpUt compensation not increase the offset
voltage overmuch.
TL/H/8710-11
Figure 8_ This voltage/current converter requires excellent resistor matchIng or trImming to get
hIgh output r,slstance. BandwIdth can be reduced ·by the Inductance of Ra.
The frequency characteristics of the current source can be
expressed in terms of an equivalent output-load capacitance given by
Amethbd of paralleling op amps that does not require a
separate control·ilmplifier is shawn iii FiglJre 7. The output
buffer, A2, provides load current through R5 equal to' that
supplied by the main amplifier, AI, through R4. Again, more
output buffers can be added.
C
=
eq
Rl + R2
217" foRI Re '
(1)
where I~ is th~ extrapolated unity gain bandwidth oflhe op
amp (in this case aboUt 2 'MHz for the LM12). The equation
is orily valid for ZL > Re. .
This output capacitance can resonate with inductive loads
such as motors, causing some peaking. Inductive loads can
oscillate should the· feedback .network be imbalanced to
give sufficient negative output resistance.
Inductance of the current sense resistor, Re, can affect operation. With a' o. fir resistor, 3' p.H series inductance will
reduce the maximum obtainable bandwidth to 5 kHz. Proper
supply bypassing and connecting R2 directly to the output
pin of the op amp are important" with this circuit.
TLlH/8710-13
FIgure 7. Two power op amps can be paralleled usIng
thIs master/illave arrangement. but hIgh frequency performance suffers..
slngla-supply operation
Although op amps are usually operated from dual supplies,
single-supply dperationJs practical. The ~ridged amplifier in
Figure 9 supplies Ili-directional current drive to a servo motor while operating from a single poSitive supply. One op
amp, AI, is a vQ!tage/current converter with a differential
input. The second is a unity-gain inverter driven from the
output of the first.. It has its non-inverting input referred to
half ,the ,~opply voltages so thiltthe two. ()~,~ SWing symriletri~l1Y abo~ this voltage.·
."
The cross-supply current between the outputs of paralleled
amplifiers can be affected by gain error as the power-bandwidth limit is approached. In the first circuit, the operatingcurrent increase will depend upon· the matching of the highfreql:lency characteristics. In. the second circuit, however,
the entire input error of A2 appears across R4 and R5. The
supply current Increase can cause t.hE! power limiting to be
activated as tile sl.wUmit is approaCl'led. This will not (jilinage the: LM12: It
be avoided in both cases by connecting Al as·
'iriiier'tirig amplifier and restricting bandwidth
.
.
with Cl.
ail
can
894
Either input may be grounded, with bi-directional drive provided to the other. It is also possible to connect one input to
a positive reference, with the signal to the other input varying about this voltage. If this reference voltage is above 5V,
R2 and R3 are not required.
The output is easily converted to voltage drive by shorting
Rs and connecting R7 to the output of A2, rather than Al.
Although not shown, clamp diodes to V + and ground on the
output of both amplifiers are recommended for motor loads.
IN .....JV.>IV-.....-----'IM,...,
TLlH/8710-15
Figure 10. Bridge connection gives differential output
approaching twice the total supply voltage.
Diode bridge clamps outputs to supplies.
bridge amplifier can result in one amplifier saturating while
the output transistor of the second handles the overload at
the full supply voltage. Not all power amplifiers can take this
kind of treatment; the LM12 will.
Figure 10 shows how a bridge-rectifier module can be used
to provide output clamping for both outputs.
+IN -"Iyy-.....---...,.,~.....
The LM12 can be operated in cascode with external transistors to get output swings several times higher than the basic
op amp. The design in Figure 11 drives ± 90V at ± 1OA.
Significantly, the IC provides current and power limiting for
the external transistors.
-IN ...IIJy.".--+----'Vy.".--TUH/8710-14
Figure 9_ The output current of this bridged amplifier Is
proportional to differential input voltage. Although not shown, output clamp diodes are
recommended with a motor load.
The transistors and zener diodes form a simple voltage regulator that is driven at 70 percent of the output swing from
the R7/R9 divider. Thus, the total supply voltage of the IC
stays constant while the voltage to ground swings some
±60V.
high voltage amplifiers
Using two amplifiers in a bridge connection also doubles the
voltage swing delivered to the load. The configuration in
Figure 10 gives good results with split supplies. Oneop amp
is an inverting amplifier while the other is a non-inverting
amplifier with equal gain. A load connected between the
outputs sees twice the swing of either amplifier. Understandably, the output slew rate doubles while the full-power
bandwidth stays the same.
The current limit of two op amps cannot be expected to be
the same. Therefore, a short between the outputs of a
The supply terminals of the LM12 swing both above and
below ground at full output. Therefore, the input terminals
must be bootstrapped to the output to keep them within the
common-mode range. The Rl-R4 bridge does this. The
bridge is unbalanced by Rs to set the gain near 30. Naturally, R4 and Rs can be combined.
O~~~~~-------------i
R13
3.3
Rl
lk
0.1"
TLlH/8710-18
Figure 11. This amplifier cen drive ± 90V at ± 10A, more than twice the output swing of the
LM12, The Ie provides current and power limiting for the discrete transistors.
895
Bootstrapping the power supplies reduces the voltage
swing across the interrial frEkluelicy compensation capacitors of the LM 12. The effectiveH.ess of' the capacitors is in
proportion to the output. swing across them. If the voltage
swing between the output and V~ terminals of the IC is onethird the actual outpUt swing, the sli!lW rate and gain-bandwidth product of the complete amplifier will be three times
that listed for the, IC. The minimum loop gain must be increased accordingly.
Distortion on the bootstrapped s~pplies can show up on the
output because the· op amp lias limited' supply rejection at
high frequencies. If Rs and Rs are· not low enough, these
power followers cannot track high frequency waveforms
and performance will suffer.
This circuit is more sensitive to capacitive loading than the
basic op amp because the supply terminals of the IC cannot
be bypassed' directly to ground. The effects of this can be
mitigated by using an appropriate LR network in the output.
When the IC goes into power limit, current will likewise be
cut back in the external transistors. The voltage on these
external transistors is not necess8rlly regulated, so the discrete transistors must be enough stronger than the IC transistors to handle the extra voltage. The IC cali handle orders of magnitude more power cycling than commercial
power transistors with'soft-solder die attach. Cycling in and
out of power limit at low frequencies could be a problem and
should not be ignored.
The output swing can be Increased using more-conventional Circuitry if floating supplies are available. Figure 12 shows
a bridged amplifier that drives a ground-referred load. A differential input is provided, but one input can be' grounded
and the other driven from a low-impedance source. If the
non·inverting input is ,grounded, R7 and Rs can be replaced
by a single resistor. Operation is like a standard bridge, except that it is a bit more sensitive to capacitive loading. Output .swing is ± 70V at ± 10A.
Cl
200p R2·,
IQk. .
+4OV.
+
. 'IN-¥I~~~iM~HM-f1f-..---+-~"'"
Rl
lk
R6
5k
.... oUT
>_~
TLlH/871D-17
Figure 13. Cascading two oP. amp. doubles ou1pul
swing. Ou1pul may be Increased by any number oIis18ges, buta ilepalllie floating supply
Is required for each,
.
output of A1, from regenerating (this really shows up as capacitive load senSitivity). Like the other designs, an output
LR will help reduce sensitivity to capaCitivE! loading.
audio amplifiers
High quality audio amplifiers are widebllnd, power op amps
with tight distortion specifications. The petformance of the
LM 12 puts it in this class. ,
'
A practlc:al design for an audio power amplifier is shown in
Figu~ 14. Output-clalllP diQdes are mandat!)ry because
loudspeakers are InductiVe loads. qUtpot ~R isolation' is
also used because audio amplifiers are\,isually!!xpected to
handle up to 2 p.F load capacitance: Large, 'supply-bypass
capacitors located close to the Ie are used sO that the rectified load current in the supply leads does. not get back into
the amplifier, incr9/lsing hig/1-freq49ncy distortion. Single~
point grounding for all internlll leads plus the signal source
and load is recommended to .avoid ground loops that can
iricr4*!Se·disto,rtion.
-IH-.....fV¥+----¥l,..,.,
Rl
lk
~+--M....-4~IJViIJ'-"""OUT
R3
lk
R2
1.1k
IN .....t--t
R5
lk
.Rl
lk
common
ground /~-~.++""f-I
R7
lk
point
-=-
TL/H/871D-16
TLlH/871D-25
Figure 12. Bridge amplifier with a single-ended ou1pUI
uses floallng supply. Either Inpul can .be.
grounded.
A final circuit in Figure 13 shOWS hoiN two op amps can be
stacked to double output swing. A third op amp with a gain
of 0.5 added to the output will triple the basiC swing.:Any
number of op amps can be cascaded, adding to the s:;ving,
but a floating supply Is required for each. '.
With two stages, clamp diodes from each amplifier output to
its supply terminals are recommended. With three or more
stages, the diodes are required to avoid su!'ply reversals,
The bandwidth is limited by R4 and C3. This isolation also
prevents load transients on the output; reflected back to the
Figure 14. As an aUdiO a",pllfler, the LM12 has better
.'
dlslortlon, Irsnsient resPonse and saturstlon
recovery than moat power op amps.
The total harmonic distortion measured for this circuit is
plotted in Figure. 15. The increase at high frequencies is due
to crossover distortion of the class-B stage. That at low frequencies is caused ~y thermal feedback within the LM12.
The effect of thermal feedback on the response of the
LM12 is indicated in Figure 16. The offset voltage change is
plotted as a function of time after the application of an output load that diSSipates 50W in the source and sink transistors.
896
With fast motor-driven servos, it is best to make the motor
current proportional to the servo amplifier drive. With current
drive, motor response is basically unaffected by the series
inductance of the motor, windings. At higher frequencies,
current drive can give 90 degrees less phase shift in the
motor transfer function when compared to voltage drive.
Should the servo loop go through unity gain at a frequency
at which motor inductance is unimportant, the advantage of
current drive is lost.
The motor/tachometer speed control shown in Figure 17
gives an example of optimizing performance using a current
drive that is supplied by A2, connected as a voltage/current
converter. The tachometer, on the same shaft as the dc
mQtor, is simply a generator. It ,gives a dc output voltage
proportional to the speed of the motor. A summing amplifier,
Al, controls its output so that the tachometer voltage equals
the input voltage, but of opposite sign.
With current drive to the motor, phase lag to the tachometer
is 90 degrees, before second order effects come in.
Compensation on Al is designed to give less than 90 degrees phase shift over the range of frequencies where the
servo loop goes through unity gain. Should response time
be of less concern, a power op amp could be substituted for
Al to drive the motor directly. Lowering break frequencies of
the compensation WOUld, of course, be necessary.
g
I
TLlH/8710-30
Figure 15. Total harmonic distortion of the circuit in
Figure 14 Is plotted here for both low- and
high-level outputs.
,
s~uJ::-
_-~~t"-
...,.;-
II
-
SINK
II,
0
-1
o
PON:SOW
I '"I
I
20
«l
80
80
The circuit in Figure 17 could also be used as a position
servo. All that is needed is a voltage indicating the sense
and magnitude of the motor shaft displacement from a desired position. This error signal is connected to the input,
and the servo works to make it zero. The tachometer is still
required to develop a phase-correcting rate signal because
the error signal lags the motor drive by 180 degrees.
TIME (mo)
TLlH/8710-31
Figure 16. The offset voltage change after the application of a load that dissipates 50W in each
output tranSistor is, plotted here_ This thermal feedback causes increased distortion
below 100 Hz.
Unlike crossover distortion, the low-frequency distortion can
be virtually eliminated by using the LM12 as a buffer inside
the feedback loop of a low-level op amp. However, the lowfrequency harmonic distortion, being generated thermally, is
slow and does n"ot cause the more objectionable interrnoduiation distortion. The latter measured 0.015 percent with
± 10V into a 40 load under the standard 60 Hz/7 kHz, 4:1
test conditions.
R1
10k
R3
C3
4.7k 0.221'
R5
10k
0.1%
IN """/Ir-""'Wrll-t--.JV';IIr---,
The transient response of the circuit in Figure 14 is clean;
and saturation characteristics are glitch-free even at high
frequencies. In addition, the 9V1 /Ls slew rate of the LM12
virtually eliminates transient intermodulation distortion.
The availability of a low-cost power amplifier that is suitable
as a high-quality audio amplifier can be expected to generate interest in using a separate amplifier to drive each
speaker. Not only does this eliminate high-Ievei crossover
networks and attenuators, but also it prevents overloading
at low frequencies from causing interrnodulation distortion
at high frequencies. With separate amplifiers, such clipping
is far less noticeable.
TL/H/871 0-20
Figure 17. Motor/tachometer servo gives an output
speed proportional to input voltage. Using
current drive to motor reduces loop phase
shift due to motor inductance.
The concept of a rate signal can be understood from a simple example. The problem is to rotate a radar antenna to
acquire a target from a large angle off point. When the motor has limited power and the antenna has mass, the quickest path into point is to run full bore toward point; pick the
correct instant to reverse at full power before getting there;
and shut down in just the right place. In a servo, the rate
signal added to the error signal' is what tells it when to reverse in order to acquire the target without overshooting.
servo amplifiers
When making servo systems with a good power op amp, '
there is a temptation to use it for frequencY shaping to stabilize the servo loop. Sometimes this works; other times there
are better ways; and occasionally it just doesn't fly. Usually
it's a matter of how quickly and to what accuracy the servo
must stabilize. A couple of examples should make the point.
897
!Z•
cr:
With a fixed target, a tachometer on the drive motor will give
the rate signal. If the target is moving across the al)tenna, it
does not: it produces the rate signal plus or minus the angular velocity of the target This disrupts acquisition and generates a pointing error.
The rat~ signal can be obtained by differentiating the error
signal. A design that gives the required error plus rate signal
at the output is shown in Agure 18a. Neither op amp should
saturate under any condition, no matter how far off point or
how fast the error changes. If it saturates,· a proper rate
signal is not developed; and acquisition will be degraded.
This can degenerate to where the servo will oscillate continuously once a certain tracking error is exceeded.
IN
a) generating rate signal electrically
CI
Acquiring from large errors quickly and 10 great accuracy
requires an extremely wide dynamic range: In Figure 18a, it
is necessary to make A, and A3 so low to keep the amplifiers from saturating that chopper stabilization may be required 10 preserve accuracy.
RI
; ' " 160
OJ
Il4
7.5V
7.5V
In Figure 18a, A3 can be raised to any value if back-ta-back
zeners are put across it. The waveform below the clamp
level will be unchanged from the case where A2 h!ls unbounded output swing. Should the clamp levels be large
enough to saturate the motor drive, operation is unimpaired.
This principle is developed further in Figure 18b. It gives
identical response, except that the resistor in series with C,
breaks back the differentiator above the unity gain frequency. Off pOint, the voltage at the junction of A, and A2 should
not get so large that the output of A, cannot saturate A2
without the clamps conducting.
R5
Ik
TUH/B710-21
b) compressing dynamic range
operational power supply
External current limit can be provided for an op amp as
shown in Figure 19. The positive and negative limiting currents can be set precisely and independently down to zero
with potentiometers R3 and A7. Alternately, the limit can be
programmed from a voltage supplied to A2 and As. The
input controls the output when not in current limit. This is
just the set-up required for an operational power supply or
voltage-programmable power source.
Figure 18. When electrical rate signals must be developed with large error signalS .well beyond
saturation of motor drive, a.llnear approach
a) requl.... wide dynamic range and great
preciSion. More practical design b) uses
feedback Clamps to Increase effective dynamic range.
Nota: Supply voltages for
the LM318s are ±15V
RI2
Ik
INI"'VIf\t-....- - - - - - -......- - - - -....- -.....
TUH/8710-19
Figure 19. BI-directionaillmlting currents of the power op amp, A4, are set Independently by
R3 and R7' Fast response is ensured by clamp diodes, 01 and 02'
898
r--------------------------------------------------------------------.~
The power op amp, A4, is connected as an inverting amplifier. Its output current is sensed across RIo. This sense voltage is level shifted to ground by A3, a differential amplifier
that is made insensitive to the op amp output level by trimming Rg.
The output load capaCitor, C2, is part of the op amp frequency compensation. This requires that C, be connected directly at the op amp output and C2 at the ,load, as described
earlier. The reference noise is filtered by Cl, which also
controls the start-up rate. The clamp diode, 02, resets Cl
when the output is shorted and keeps the op amp input from
being driven below V-.
With current below preset levels, the outputs of Al and A2
are clamped by 01 and 02 with 01 and 02 turned off. When
the current threshold is reached, the relevant amplifier will
come out of clamp, saturate the transistor on its output and
take over control of the summing node. The clamp diodes
limit the swing on the outputs of the current-control amplifiers while the transistors disconnect frequency compensation until the summing node is engaged. This ensures fast
activation of current limit. Recovery back to voltage mode is
also fast. The LM318 wideband amplifier is required for Al
through A3.
Oual supplies are not required to use an op amp for a regulator, as can be seen from the 4V to 70V adjustable regulator shown in Figure 21. This regulator also has overvoltage
protection. Should an overvoltage condition exceed the current or power capabilities of the LM12, a comparator will
trigger a SCR, crowbarring the output.
RI
18k
voltage regulators
An op amp can be used as a positive or negative regulator
with equal ease. Unlike most dedicated voltage regulators,
the output can both source or sink current to absorb energy
dumped back into the supply and prevent overvoltage with
certain fault conditions. Output transient response is also
improved, especially overshoots. '
A particular reason for using the LM12 as a regulator is its
exceptional high-voltage capability. This not only gives output voltages to 70V, but also ensures startup under worstcase full-load conditions.
R2
2.7k
Compared to conventionallC regulators, using an op amp
with an external reference has better accuracy: an optimum
reference can be selected and thermally isolated from the
power circuitry. Better regulation, temperature drift and long
term stability result. Remote, output-voltage sensing at the
load to further reduce errors is also practical.
A positive regulator with a 0-70V output range is shown in
Figure 20. The op amp has one input at ground and a reference current drawn from its summing junction. With this arrangement, output voltage is proportional to the setting resistor, R2.
01
LII329
7V
R3
4k
. .-~~~-~~-~~~-~-~~GNO
~-
TLlH/8710-23
Figure 21. This 4V to 70V regulator operates from a single supply. Should the op amp not be able to
control an overvoltage condition, the SCA
will crowbar tl'!e output.
The reference is a low drift zener, 01, powered 'from V+
through Rl. The reference voltage is dropped to 4V and fed
to the non-inverting input of the op amp, AI, with zener
noise attenuated by Cl' Thus, the output will be this 4V plus
a voltage that is proportional to the resistance of Rg. As
before, 02 is a clamp while C2 makes sure the IC input is ac
coupled directly to its output terminal.
With overvoltage, a comparator, A2, fires the SCR through a
buffer, 02, after about a 20 p.s delay from C3 to eliminate
spurious transients. The comparator receives its power from
O-i so that V+ can be increased above the rating of the
LM311. '
y+~ 75V
01
LIot385
L-...;..+-_ _ _ _...... GNO
L.:2o;::.5:..V_W \r--4_ _ _ _ V"=-5V
R3
, 700
TLlH/8710-22
Figure 20. Positive regulator with 0-70V output range.
Output will source or sink current, and startup capability with higher Input voltages Is
superior to standard Ie regulators.
Should the feedback terminal of the op amp rise more than
0.4V above the regulating value for longer'than 2() p.s, the
comparator will provide the signal required to fire the SCR.
Since this can only happen if the considerable current and
energy capabilities of the LM12 are exhausted, nuisance
tripping is unlikely. The output trip threshold will be 0.4V
above nominal as long as it happens quickly enough that
the vQltage across C2 does not change appreciably. For a
slow overvoltage condition, it is 10 percent above nominal.
A negative supply is used to operate the op amp within its
common-mode range, provide zero output with sink current
and power a low-voltage bandgap reference, 01. Current
drawn from this supply is under 150 mA, except when sinkirig load current.
899
...&•
Z
remote sensing
With the current running at 10A, a foot of 0.1-inch-diameter
copper drops 10 mV. Obviously, sizeable voltage drops will
have to be accepted to run this kind of current over any
distance without expensive and cumbersome cables.
Remote sensing, illtistrat6d in Figure 22, can help the situation considerably. It uses a pair of small wires, in addition to
the main pOwer cables, to sense the voltage at the load. A
feedback amplifier can then correct for the 'drop in the main
cables.
-IN
Rl
RS
SK
SDk
R2
+IN
SK
COMC1~
lnT
L~+~~
~
With this type of protection, the power capabilities will depend on case temperature, transistor operating, voltages
and how the dissipation ,varies with time. Figure 24 shows
the amplitude of a power pulse required to activate power
limiting in 100 ms as a function of collector-emitter voltage
on the output transistors for two case temperatures. The
continuous dissipation limit is ab,out 15 percent less than the
100 ms limit.
:c-
..
o'!!.
Ia
8
l'\
4
ZL
111
'
.....
Tc=I00"C
0
R4
0
SDk
--
G.8
0.4
Tc=250C
--'- I
1.6
1.2
nME(mo)
TUH/B710-24
TUH/B710-33
Figure 23. Output short-cIrcuit current Is reduced when
power transistor Junction temperature
reaches 2300C and power limit takes over.
Figure 22. Remote sensing allows the op amp to correct for de drops in cables connecting the
load. Normally, common and one Input are
hooked together at the sending end.
--r-
120
The cables can cause delays in the feedback signal returning from the remote sense. This delay can make the feedback loop unstable u.nless the remote signal is ignored at
higher frequencies. Thus, cable drop can be compensated
but only at a limited rate; transient response suffers most.
Heavy cables, closely spaced (or twisted) to minimize inductance, give fewest problems here.
'
The schematic in Figure 22 shows a differential-input amplifier that has dc feedback from the remotely-sensed load.
The ac 'feedback is directly from the op amp output and the
signal common at the sending end. There is no feedback
from the load at high frequencies. The optimum capacitance
depends upon the cable delay.
For single-ended input, the unused input terminal in the
schematic would be, strapped to the common. Feedback resistors should be reasonably matched to avoid second-order errors and the feedback resistors should be made
enough greater than the sense line resistance to avoid gain
errors.
100
..... ~250C,
g
80
I
60
tc=12~OC r--..
I-
40
I-
20 I-- toN =lOOms
-
Tuw=2.lO"C
oL-L-L-~~~~~~
02040
60
80
COllECTOll-EMmER VOlTAGE (V)
TL/H/B710-34
Figure 24. The power required to activate power limit Is
less at higher voltage, but this Is not so pronounced at higher case temperatures.
The pulse capabilities of the output transistors are shown in
Figure 25. The curves give the amplitude of a constant-power pulse required to activate power limiting in the indicated
time. With pulse widths longer than 1 ms, the pulse capability decreases with collector voltages above 40V as indicated
in Figure 24.
Sometimes provision is made to control the circuit shol,lld
the sense lines be disconnected. With a regulator, an imbalance current could be put into the sense lines to bring the
regulator output to zero should one line go open. With bi-directional op amps, it is not obvious whether limiting the error
with back-Io-back diodes between the power-out and
sense-in is better than having it go open loop.
1 11111 TIJIj =2.lO"C
g
~=25JC'
200 l -
I
power capabilities
The output transistors of the LM 12 will dissipate power until
their' peak junction temperature reaches 230"C (± 15'C).
When this temperature is reached, internal limiting circuitry
takes over to regulate peak temperature. How this works Is
illustrated in Figure 23, which gives the peak output current
waveform with the output instantaneously shorted' to
ground. Conventional current limiting holds the short-circuit
current near 13A for a few hundred microseconds, then
temperature limiting takes over as junction temperature tries
to rise above 230'C. The response time of the temperature
limiter is well under 100 /,-s.
50 '--'..J..JJ1WUL
1111I-l..J..I.UWJI...........1.LUJlI
0.1
toO
10
tOO
nME (mo)
TL/H/871 0-35
Figure 25. The peak-dlsslpatlon capabilities of the power transistor are shown here. For times greater then 100 ma, the external heat sink will determine ratings.
900
10
3:
I
I
5.0
,"'
TC=25°C-- TJ =2000C
700C--,--f-12SOC-
" , '" ......::......
"'~ ~ "
'"~ ~ """I'--..
,
0.3118
~
7
1.0 .......
2.0
TC=25"C
TJ =2OO"C
1.0
0.5
do
./'
./
0
.~
2
o
60
80
VC£=4OV Tc=25O C
58Y---TJ =2000C
78Y--
o
:;;..
~.
I
I'
,..
,
.'
80
COlLECTOR-EIot1l1[R VOLTAGE (Y)
~
o
,...
0.1
{;
1.0
10
100
PULSE WI1llH (ml)
TLIH/8710-37
a) safe area curve
b) dc thermal reslstan,ce
c) pulse thermal resistance
Figure 26. The worst-case power ratings of the output transistors are described by a) a safe area curve,
b) the change In dc thermal resistance with temperature and operating voltage and c) the
pulse thermal resistance.
power ratings
The protection circuitry of the LM12 brings a new dimension
to derating. Such conditions as out-of-spec line voltage or
lack of air circulation cause the equipment to stop working
temporarily; excessive stress or catastrophic failure does
not result. It should be recognized, however, that there are
certain applications where a temporary misfunction can be
the same as a permanent one, definitely recommending derating.
The guaranteed power ratings of the LM12 are based on a
peak junction temperature of 200"C rather than the 230"C
limiting temperature. Test accuracy. guard bands and unitto-unit variations are also taken into account. The result is
that the guaranteed ratings are about 40 percent less than
the power required to activate thermal limit.
The worst-case, safe-area curves for a peak junction temperature of 200"C with a 25°C case temperature are shown
in Figure 268. The guaranteed-maximum, dc thermal resistance is given as a function of collector-emitter voltage in
Figure 26b. It can be seen from this figure that the incre~e
in thermal resistance with voltage is much less at higher
case temperatures. Finally, the equivalent thermal resistance for power pulses is given in Figure 26c. Again, these
are worst-case numbers. The voltage dependency of thermal resistance in Figure 26c is for a 25°C case temperature.
At higher case temperatures this dependency will be moderated as shown in Figure 26b.
Derating also reflects the user's faith in the ability of the
manufactur~r to adequately test the parts. Dynamic safearea protection helps out here. Shouid a die-attach void or
other defect produce hot spots in the power transistor, it will
be rejected during production testing as having reduced dissipation capability, r~ther than being passed on as a reliability risk. This cannot be done with conventional power semiconductors.
No short-term failure mode has been found with modern IC
power transistors even with peak junction temperatures of
300"C. However, power cycling can cause problems. Die-attach failures at:3 x 104 cycles'with a 70"C temperature rise
are possible With power transistors having a soft-solder die
attach. The LM12 avoids this by using a gold-eutectic die
attach to a molybdenum spacer. Even so, metalization failures have been experienced with the LM12 at 106 cycles
from 50"C to power limit at 230"C with 200W dissipation.
The guaranteed power ratings are not established by statistical methods from sample tests. Instead, they are interpolated from actual measurements of power capability into
thermal limit: these are standard production tests.
With ac loading, both power transistors share the dissipation; and the worst-case thermal resistance can drop to
1.9"C/W. However, it is necessary that the frequency be
sufficiently high that the peak ratings of neither output transistor are exceeded.
Thermal derating is more applicable to the control circuitry
of the LM12. Operating the control circuitry above 150"C
can be expected to affect reliability. Fortunately, the control
circuitry is exposed to only a fraction of the temperature rise
in the power transistor. Derating may be based on a thermal
resistance of O,9"C/W independent of operating voltage.
With ac loading, where power is being dissipated in both
power transistors, thi,s thermal resistance drops, finally approaching OJ!'C/W.
thermal derating
It is not unusual to derate the maximum junction temperature of semiconductors below the manufacturer's specified
value in worst-case design. The derating is often dictated by
unpredictable operating conditions and design uncertainties. An equipment manufacturer does not want his product
failing because of some obscure stress that Is not apparent
to the customer.
package mounting
The ratings of the LM12 are based on the case temperature
as measored on the bottom of the TO-3 package near the
cemer. Proper mounting is required to minimize the thermai
resistance betWeen this region and the heat sink.
A good thermal compound such as Wakefield type 120 or
Thermalloy Thermacote should be used when mounting the
package directly' to the heat sink. Without this compound,
thennal resistance will be no better than 0.5°C/W, and possibly much worse. With the compound, thermal resistance
will be 0.2°C/W or less, assuming under 0.005-inch combined flatness run-out for the package and the heat sink.
Proper torquing of the mounting bolts is important. Four to
six inch-pounds is recommended.
Company policies, equipment requirements and individual
preferences vary as to what constitutes appropriate derating. When pressure is on for the best performance at lowest
cost, a 200"C junction temperature for power semiconductors ,has been accepted, although this might well be influenced by whether hermetic or plastic packaging is used.
Continuous operation at 200"C should also be treated differently than infrequent excursions to this temperature. Nonetheless, reducing temperature is a recognized method for
increasing reliability; and ultra-reliable military and space applications have required that maximum junction temperatures be under 125°C.
901
!
<
are not· dominant with. multi-finned .heat sin~, power dissi'pation and temperature rise should char:ecterize performance. Heat sink size can be drastically reduced b,y forced air
cooling, should it be available.
Should·:it be. necessary to isolate V- from the heat sink, an
insulating. washer is' required. ':lard washers like beryllium
oxide, anodized aluminum and mica require the use of thermal compound on both faces. Two-mil mica washers are
most common,' giving about OAoC/W interface resistance
with the cornpound. Silicone-rubber washers are also avail- '
able. A 0.5°C/W thermal resistance is claimed without tilermal compound. Experience has shown that these rubber
washEirs deteriorate and ,must be replaced should the IC be
dismounted.
determining dissipation
It is a simple matter to, establis~ the power that an op amp
must dissipate when driving a resistive load at frequencies
well below 10Hz. Maximum dissipation occurs when the
outPut is at one-half the supply voltage with high-line conditions. The individual output transistors must be able to handle this power continuously at the maximum expected case
temperature.
.
If there is ripple on the supply bus, it is valid, to use the
average vlllue in, ¥,Iorst-case, calculatio(ls
,ong as the
peak rating of the powedransistor is riot exceeded at the
rippie peak. With 120 Hz ripple, the peak rating is 1.5 times
the continuous power rating.
'
Dissipation ,requirements are not so easily esta~lish!ld with
time-varying output Signals, especiallY with reactive loads.
Both peak- and continuous-dlssipation ratings must be taken into account, and these depend on thesignal waveform
a~ well as 1000d characteristics.
With a sine wave output, analysis is fairly, straightfQ/Ward ..
With supply voltages of ±Vs, the maximum average power
di8$ipatlon of ,both output transistorS is
heat sinking
With no heat sink, the internal temperature rise of the LM12
can be as high as 160"C with ± 40V supplies and no load. A
heat sink is required.' Heat sinks are commerciaily available,
with data on their power rating' and temperature'i1se sup-'
plied by the manufacturer. The types most suitable for diSsipation in the order of 50W are made from extruded aluminum channel equipped with multiple fins. It is important that
the heat sink have enough metal under the package t~ conduct heat from the center of the package
to the fins
without eXc8ssive temperature drop. . '
The power rating of a multi-finned heat sink is determined
largely by the surface area Subject. to conVection cooling
and the allowable temperature riSe above ambient: Heat
loss due to radiation can also be important with simple heat
sinks. However, with rnuitiple fins radiating toward each other, the significance of the radiatioil term drop$. Nonetheless, heat sinks are usually black anodized to maximize radi'
.' ,
ation losses.
as
bottom
P
'=
2VS2
8 '< 40";
MAX 'lT2ZL cos 8 ' .
and
The s,urface area required for agive,n temperatur:e rise and
power dissipation can be estimated with fair accuracy from
Figure 27. The area efficiency is affected by heat ,sink orientation, length and fin spacing. The figure assumeS that the
surfaces are located in a vertical plane. With the surtaceS
horizontal,temperature rise is increased by perhaps 20 percent. Vertical dimensions longer than 4 iriches are less efficient. Commercial heat sinks are normally designed so that
fin spacing is not so close as to affect the results of the
figure.
, V [4'
(2)
]
PMAX=...§... --cos8 , 8~40",'
(3)
2ZL '11',
where ZL is the magnitude of the load impedance and 8 its,
phase angle. Maximum average' dissipation occurs for a
peak output swing, Ep, given by
2Vs
2Vs '
Ep=---, cos8:;>--;
(4)
'IT cos 8
.
'lTVp
or
2
Ep ";Vp,
100
p.5OI'I
" r-..
1IO
.......
..... I".......
10
2110
~
80
1IO
E
I"..
..........
P=
,~
,':
Z~ cos lilt [Vs - Ep cos (lilt + 8»).
'1
For Ep = Vs,the power ~k occu!,& for lilt = 3.
"t"
iIOO
10lI0
Hl:AT_ _ _
(5)
where Vp is the maximum available output swing.
The instantaneous power dissipation is
'(6)
('IT .,...
8).
With practical amplifiers Ep < Vs;· and a numerical solution
is required.
'
The instantaneous poWer di~ipatio-n over the'conducting
half cycle of one outPut tranSistor is sho)Nn in Figufe~8.
Power dissipation is near zero on the other half cyc~e. Ttle.
output level is that resulting in maximum peak and average
dissipation: Plo~ are given for a resistive and a series R·L
load. The latter is representative ofa 40 'Ioudspeakeroper~
atingbelow resonance and would be the wor~-caseb'ondi
tion in most audio applications. The peak dissipation of each
transistor is aboutfoof tirtlesaverage. In ac"applications,
power capabilitY is often limited by the peak ratings of·tl\e:
'
.
pbwer transistor.
2IlOO
~
TLfHf8710-28
Flgure27. A,heat sink I,requlred to cool thale pack.
age. Thle cu,.". glva, tha, rI.. In, ca.. temperatura as a fqnction of heat..lnk fin ares
with convectlon,~ng.
It is not possible to specify an unqualified thennai reSist&nce
for a convection or radiation cooled heat sink. Both mechanisms will give a lower thermal resistance with inCfeasing
temperature rise,. while heat losses' to radiation alSQ in:
crease with absolute temperature. Sln - 8)].
(7)
where = 60" and 8 is the absolute value of the phase
angle of ZL. Equivalent pulse width is toN "" 0.47' for 8 = 0
and toN "" 0.27' for 8 > 20', where 7' is the period of the
output waveform.
With the LM12, the peak junction·temperature rise for any
given waveform can actually be measured. This is done by
raising case temperature until power limiting is activated.
Temperature rise is then computed from the measured case
temperature based on a power·limit temperature of 230"C.
Altemately, the power-limit temperature may be determined
directly by measuring the dc dissipation at a collector-emitter voltage of 20V required to activate power limit. If this is
done over a range of case temperatures, the results can be
plotted and extrapolated to the power-limit temperature.
This procedure was used to give the peak temperature rise
as a function of frequency for an op amp driving a resistive
load under conditions of worst-case dissipation. The results
are plotted in Figure 29.
110
"
\..
Vs =t3DV
VOUT -t19.1V
RL =411
PAVO= 45.6W
PPK=62W
lk
voltage regulator dissipation
The pass transistor dissipation of a voltage regulator is easily determined in the operating mode. Maximum continuous
dissipation occurs with high line voltage and maximum load
current. As discussed earlier, ripple voltage can be averaged if peak ratings are not exceeded; however, a higher
average voltage will be required to ensure that the pass
transistor does not saturate at the ripple minimum.
Conditions during start-up can be more complex. If the input
voltage increases slowly such that the regulator does not go
into current limit charging output capaCitance, there are no
problems. If not, load capaCitance and load characteristics
must be taken into account. This is also the case if automatic restart is required in recovering from overloads.
Automatic restart or start-up with fast-rising input voltages
cannot be guaranteed unless the continuous dissipation rating of the pass transistor is adequate to supply the load
current continuously at all voltages below the regulated output voltage. In this regard, the LM12 performs much better
than IC regulators using fold back current limit, especially
with high-line input voltages above 20V.
power supplies
r--.
100
Shunt-and series-wound motors can generate back emfs
that are considerably more than the total supply voltage,
resulting in even higher peak dissipation than a permanentmagnet motor having the same locked-rotor resistance.
Power op amps do not require regulated supplies. However,
the worst-case output power is determined by the low-line
supply voltage in the ripple trough. The worst-case power
dissipation is established by the average supply voltage with
high-line conditions. The loss in power output that can be
guaranteed is the square of the ratio of these two voltages.
Relatively simple off-line switching power supplies can provide voltage conversion, line isolation and 5-percent regulation while reducing size and weight. The regulation against
ripple and line variations may provide a substantial increase
in the power output that can be guaranteed under worstcase conditions. In addition, switching power supplies can
convert low-voltage power sources such as automotive batteries up to regulated, dual, high-voltage supplies optimized
for powering power op amps.
70
10
A permanent-magnet motor can build up a back emf that is
equal to the output swing of the op amp driving it. Reversing
this motor from full speed requires the output drive transistor to operate, initially, along a loadline based upon the motor resistance and total supply voltage. Worst case, this
loadline will have to be within the continuous dissipation
rating of the drive transistor; but system dynamics may permit taking advantage of the higher pulse ratings. Motor inductance can cause added stress if system response is
fast.
10k
FREQUENCY (Hz)
TUH/8710-36
Figure 29. Peak Junction-temperature rise as a function
of frequency with an op amp driving a resistive load under conditions of worst-case dissipation.
903
checking thermal design
Thermal design margins can be established by determining
how' far the part can be pushed beyond nominal worst-case
before power limiting is activated. This extra stress' can be
applied by increasing case temperature, supply voltage, or
output loading.
Raising case temperature with worst-case electrical conditions has the advantage of giVing results that are easily interpreted in terms of thermal deSign margins. If the case
temperature, as measured at the center of the package bottom, ,must be raised 500C above ,the maximum design value
to activate power limiting, the worst-case, peak-junction
temperature is 1800C, or 500Cbeiow the power-limit temperature.
With this technique, it is important that the case temperature
be kept below 1400C. At 15O"C, the case-temperature limit
activates, shutting the IC down completely.
conclusions
A new concept for power limiting and advances in IC design
have been combined to produce a mon~lithic, high-power
op amp that challenges the best hybrid and discrete designs. Impressive power ratings are obtained along with better control of fault conditions. The part is easy to use, quite
tolerant of abuse and has few disagreeable characteristics.
Design problems peculiar to power op amps hllve been discussed. They present no serious difficulty if kept in mind.
Methods of increasing output capabilities beyond those of
the basic part were also shown to demonstrate its flexibility.
A number of conventional applications for power op amps
were detailed along with others that would not normally use
an op amp. It is expected that this power IC will recommend
itself for a wide range of currently obscure, general-purpose
"
applications.
One of thE! more onerous tasks with power devices is establishh1g that a deSign operates components within rating~.
Guidelines were given for determining continuous and transient dissipation. In addition, the basic problems of providing
adequate heat lIinking were outlined. DynamiC safe-area
protection is of particular help here ,in that design margins
can actually be measured, rather than inferred from published data.
904
Protection Schemes for
BI-FETTM Amplifiers and
Switches
National Semiconductor
Application Note 447
Wanda Garrett
To use integrated circuits in real applications, designers
must know the limitations of the devices. The majority of the
limitations are published in the datasheets, and these fall
into two categories: Absolute Maximums-which, if violated,
can cause damage or destruction of the device; and Electrical Characteristics-which indicate the performance limitations. Unfortunately, these specifications don't explain the
consequences of a violation, nor what may happen between
the violation of an Electrical Characteristic limit and an Abs.
Max. limit. This information is needed so the designer can
design an appropriate protection scheme.
than the negative common-mode limit, the input stage ceases to function properly and the output swings to its positive
limit. This apparent "phase-reversal" is temporary; bringing
the non-inverting input back within the legal input commonmode range restores the part's normal operation.
This article will focus on National Semiconductor Corp.
BI-FET op amps: how to improve their reliability and performance. In most cases, the results are similar for bipolar
op amps also.
In closed-loop operation, exceeding the negative commonmode at either input limit, also causes the output to swing to
the pOSitive supply rail.
If the inverting input is taken below the non-inverting input
while the op amp is operated open-loop, the output slews
toward the positive rail. Exceeding the negative commonmode limit in this condition does not cause a "phase reversal", as the output will still head toward, or remain at, the
positive rail.
Exceeding Positive Common-Mode LImit
THE BI-FET FAMILIES
Our BI-FET op amps are divided into families: LF411, LF441
and LF356. The LF411 family consists of LF411, LF351 ,
and TL081 (all singles); LF412, LF353, and TL082 (duals);
and LF347 (quad). This is a good general purpose set of op
amps that all have the same internal deSign, differing only
by grade.
The LF441 family consists of the LF441 (single), LF442
(dual), and LF444 (quad). This family gives nearly the same
DC performance as the LF411's for 1/12th the supply current. However, because they are low-power devices, they
are also proportionally slower than the 411 'so
The LF356 family includes the LF355, LF356, and LF357 (in
the commercial temperature range). The 355 is the lOW-Icc
part, and the 357 is the wide-bandwidth part. All of the family have good DC specs and can drive a lot of capacitance
(to .01 /JoF, typically). They are also among our faster op
amps, having slew rates which vary from 5V I /Jos (for the
355) to 50Vl/Jos (for the 357).
The operating restrictions for these families are nearly all
the same, as are the methods of protection. In some cases
(as will be pOinted out) certain families are better at surviving the abuses than others.
In general, the positive common-mode limit is at or beyond
the positive supply. Taking either input above the positive
common-mode limit while in open-loop operation does not
cause a "phase reversal" at the output; the output will slew
toward whichever rail one might expect. However, if both
inputs are driven above the positive common-mode limit,
the output will slew to the positive rail. In addition, while
operating in a closed-loop mode, taking either input above
the positive common-mode limit will also drive the output to
the positive rail.
'
INPUTS EXCEEDING SUPPLY RAILS
If either input is pulled above V + , nothing happens until the
difference between the input and V + gets near the breakdown voltage, typically 50V. At this pOint, the FET's gatesource junction avalanches and wiil draw all the current it
can. Limiting this input current to something less than 3 mA
helps prevent damage. The best protection (in addition to
limiting the input current) is a diode clamp from each input to
V +. If transients are expected, use a fast-recovery diode,
such as a IN4148. For low-leakage (but less speed), the C-B
junction of a good transistor (i.e. 2N3904) is recommended.
Failure to clamp the voltage or limit the current adequately
may not destroy the part, but the offset voltage and bias
current will be permanently degraded.
EXCEEDING COMMON-MODE INPUT VOLTAGE RANGE
The input common-mode range of any operational amplifier
is the range of voltages on the input terminals for which the
amplifier operates correctly. To understand what happens
when the common-mode range is exceeded, four cases
must be considered: open- and closed-loop operation at
both the positive and negative common-mode limits.
If either input is pulled more than a few tenths of a Volt
below V - (even if this pin is floating), a lightly-doped parasitic sub~rate transistor turns on. This transistor's collector
current cannot be controlled externally, so allowing it to turn
on can cause metal migration and destruction of the input
stage (or at least a major unbalaricing). In the newer LF411
and LF441 families, this transistor has been controlled by
the addition of a diode from base to emitter which kills the
gain of the transistor and keeps its current low. Any input
current should still be limited to 1 rnA or less. However, the
older parts and members of the LF356 family are still
Exceeding Negative Common-Mode Limit
In open-loop operation (i.e., no feedback from output to inverting input, or, during any time that the op amp is slew-rate
limited), taking the non-inverting input below the inverting
,input causes the output to slew toward the negative supply
rail. If the voltage at the non-inverting input is more negative
905
suSceptible, so it is best to protect all the BI-FETs from this
potential ,abuse by using the clamp diodes (see Figure 1
below).
y.
OPEF,lATING TEMPERATURE OUT OF,ABSMAX RANGE
BI-FETs generally operate well when the ambient te!11perature is cold. The·bias current becomes minimal, the input
noise often decreases, and the bandwidth increases. However, if the device is in a marginally stable design, it may
oscillate as its phase margin will also decrease.
Conversely, running the BI-FETs at temperatures greater
than 1OO"C brings the bias current into the nanoamp range,
and drops the gain-bandwidth product by 20% or more
(compared to 25·C performance). Most op amps quit working between 180"C and 25O"C due to excessive leakage
currents or Internal thermal shutdown mechanisms, .and the
BI-FETs are no exception. The maximum guaranteed junction (die) temperature of our ICs is 150"C, and some lowergrade parts and those in plastic DIP packages are guaranteed to as low as 100·C.
The type of package used affects, the maximum ambient
temperature allowed, since the junction temperature must
remain In the "legal" range and the different packages have
different heat-sinking properties. The metal can packages
have the lowest thermal resistance, and have the additional
advantage that heat-sink fins are easy to find and attach to
the package (when needed).
TLlH/8744-1
FIGURE 1. Clamping Inputs of Op Amp
Since this parasitic transistor turns on easily, the best way to
keep it turned off is to use a Schottky diode, its on-VOltage
being less than that required to turn on the transistor. For
lower leakage, a short-base switching diode (such as the
Fairchild FD200 series) may be used. Its forward drop will
be larger at low currents, but will stay constant for a wide
current range, as opposed to the relatively leaky Schottky
diodes.
DRIVING CAPACITANCE
Both the LF411 and LF441 families have a lot of trouble
driving more than about 200 pF without oscillating. Standard
techniques to get around this problem . are to add a small
resistor (about 500) in series witl) the output (see Figure 2)
or to use one of the LF356 family (the 356 itself being the
most popular for this purpose). An explanation of why the
356 output stage is so unusually strong is provided in the
second referenqe listed.
POWER SUPPLY SEQUENCING
Adding the clamp diodes shown in Figure 1 not only protects the inputs from transients when the circuit is operating,
but protects them as power is being applied to t~e circuit.
Because the parasitic transistor appears when the input
voltage is less than the negative supply, applying the positive supply or input voltage before the negative supply is
applied can cause this problem. For this reason, it is always
recommended that the negative supply be turned on first, if
the supplies can be turned on independently. This is especially important for protection of the BI-FET switches.
Also, even if the input stage is well protected with clamp
diodes and current limiting, the inputs should not be allowed
to be heavily unbalanced (for example, one input at ground
and the other at the rail) for extended periods of time (for
example, many hours). The long-term effects of an unbalanced differential pair are increased offset voltage and offset current.
TLlH/8744-2
FIGURE 2. Isolating a Capacitive Load
When extra output filtering is desired, a series RC damper
will often be more effective than just a large filter capaCitor.
SUPPLY VOLTAGES OUT OF RECOMMENDE;D RANGE
Attempting to run·a BI-FET on supply voltages less than the
recommended total of 10V will narrow the common-mode
input and output ranges, and slow the part down. In the
LF411 family, at supply voltages less than 7V, an internal
biasing zener turns off and the entire part quits working.
With the LF441 family, a supply voltage of less than 6V is
not enough to support the internal current source biasing,
so eventually these also turn off. And the LF356 family
needs all of the 10V to stay in operation.
Running the BI-FETs on suppi voltag~S greater tlian'the
Abs. Max. limit generally does no harm until the parasitic
diode from V + to the substrate breaks down (In LVceo) or
the input gate-source junction breaks down (BVgso). limiting the supply current to something less than 10 mA improves the chances of the op amp's survival. These breakdowns typically occur at about 50V, but the devices are only
tested up to 36V or 40V, depending on the device. In addition, power dissipation must be considered when the supply
voltage is large.
POWER SUPPLY BYPASSING
Another potential cause of oscillation is inadequate power
supply bypaSSing.
.
In addition to the familiar problem of noise added through
the supply inputs (due to poor high-frequency rejection), the
inductance of the power supply leads degrades the effectiveness of the op amp's internal compensation, which invites oscillation.
The BI-FETs need the supply bypassing most on their Vterminals, as do many of the bipolar-input amplifiers. Good
bypassing techniques include (1) putting the bypass capacitors right next to the IC, and (2) using an appropriate type
and size of capaCitor. Ceramic types are often used because of their small size and low cost, but their effective-
y
906
schemes will affect the offset drift; it is equally likely that the
drift will increase rather than decrease, because the sources of BI-FET Vos are complex.
The easiest Vos cancelling technique is the trim scheme
provided in the op amp's datasheet. The LF411 and LF441
require a 10k potentiometer between the trim pins (1 and 5),
with the wiper to V -. The LF356 family requires a 25k pot
with the wiper to V +. A larger pot would extend the trim
range, but this is not necessary since the specified resistance is sufficient to correct even the worst case Vos.
Dual and quad op amps have no trim pins, so they are used
most often when small offsets can be tolerated. An external
bias voltage can be added at the input to cancel the Vos at a
given ambient temperature (TA). Typical trim schemes are
given in Applications Note AN-3.
ness is limitec;l to about 1 MHz. Typical values used are
between 0.. 01 p.F and 0.47 p.F.
Tantalum capacitors are often used for high-frequency bypassiljQ. However, their lead inductance can sometimes aggravate the situation instead of correcting it. Adding a small
(0.01 p.F) ceramic disc capacitor in parallel with the tantalum 'improves the overall performance. Typical values used
for tantalum bypass capacitors range from 2.2 p.F to 10 p.F.
Mylar capacitors are also used for bypassing, but the monolithic ceramics have better high frequency performance and
cost less.
Where the supply voltages have poor load regulation, electrolytic capacitors (typically 10 p.F to 47 p.F) can provide
additional filtering.
DEALING WITH THE OFFSET VOLTAGE
In general, the reasons for the Abs. Max. ratings and recommendations are a combination of convention and necessity.
Exceeding the ratings and recommendations does not always mean death of the op amp, but the reliability and performance of the amplifier are kept at their highest when the
part is used property and protected from excesses.
If the offset voltage of a BI-FET op amp is first measured in
a test circuit, and then again after the device is installed in
the final circuit, a change in Vos will often be detected. This'
is due to a difference in stress put on the die when the
device (packaged or not) is installed in the two circuits. Because the input JFETs are largely surface devices, any
stress on them changes their characteristics noticeably.
This, then, changes the Vos of the input stage. This problem
is more apparent with the larger devices and packages, i.e.
when there is more surface to be stressed. Thus, the most
sensitive would be a large quad in a 14-pin DIP; the least, a
small single op amp in a metal can (TO-5) package.
References:
Brokaw, Paul: "An IC Amplifier Users' Guide to Decoupling
& Grounding or Making Things Go Right", Electronic Products, December 1977, pp. 45-53.
Frederiksen, Thomas M: "Intuitive IC Op Amps", R. R. Donnelley & Sons, 1984, p. 40: explanation of LF356 output
stage; pp. 271-272: power supply sequencing.
To improve the accuracy of the BI-FET op amps, the offset
voltage should be nulled after the devices are in their final
circuits. The BI-FET offset voltage has an associated drift of
between 2 p.VI'C and 10 p.woC (depending on the device)
for every millivolt'of offset at room temperature. The Vos null
Pease, Robert A: "Bounding, Clamping TeChniques Improve
Circuit Performance", EDN, Novllmber 10, 1983, pp. 277289.
907
National Semiconductor
Application Note 460
LM34/LM35 Precision
Monolithic Temperature
Sen$ors
..
INTRODUCTION
Most commonly-used electrical temperature sensors are difficult to apply. For eXlllmple, thermocouples have low output
levels and require cold junction compensation. Thermistors
are nonlinear. In addition, the outputs of these sensors are
not linearly propqrtlonal to any temperature scale. Early
monolithic sensors, such as the LM391.1, LM134 and
LM135, overcame many of these difficulties~ but their outputs are related to the Kelvin temperature scale rather than
the more popular Celsius and Fahrenheit scales. Fortunately, in 1983 two I.C;'s, the LM34 Precision Fahrenheit Temperature Sensor and the LM35 Precision Celsius Temperature Sensor, were introduced. This application note will dis- '
cuss the LM34, but with the proper scaling factors can easily be adlllPted to the LM35.
The LM34 has an output of 10 my/oF with a typical nonlinearity of only ±0.35°F over a -50 to + 300°F temperature
range, and is accurate to within ± O.4°F typically at room
temperature (77"F). The, LM34's low output impedance and
linear output characteristic make interfacing with readout or
control circuitry easy. An inherent strength of the LM34 over
other currently available temperature sensors is that it is not
as susceptible to 'large errors in its output from low level
leakage currents. For instance, many monolithic temperature sensors have an output of only 1 /AA,oK. This leads to a
10 K error for only 1 /.I.-Ampere of leakage current. On the
other hand, the LM34 may be operated as a current mode
device providing 20 /.I.AloF of output current. The same 1 /J-A
of leakage current will cause an error in the LM34's output
of only 0.05°F (or 0.03°K after scaling).
Low cost and high accuracy are maintained by performing
trimming and calibration procedures at the wafer level. The
device may be operated with either single or dual supplies.
With less than 70 /J-A of current drain, the LM34 has very
little self-heating (less than O.2"F in still air), and comes in a
TO-46 metal can package, a SO-8 small outline package
and a TO-92 plastic package.
FORERUNNERS TO THE LM34
The making of a temperature sensor depends upon exploiting a property of some material which is a changing function
of temperature. Preferably this function will be a linear function for the temperature range of interest. The base-emitter
voltage (VBE) of a silicon NPN transistor has such a temperature dependence over small ranges of temperature.
Unfortunately, the value of VBE varies over a production
range and thus the room temperature calibration error is not
specified nor guaranteeable in production. Additionally, the
temperature coefficient of about - 2 mVI"C also has a tolerance and spread in production. Furthermore, while the tempo may appear linear over a narrow temperature, there is a
definite nonlinearity as large as 3°C or 4°C over a full - 55°C
to + 1500C temperature range.
Another approach has been developed where the difference in the base-emitter voltage of two transistors operated
~
at different current densities is used as a measure of temperature. It can be shown that when two transistors, 01 and
02, are operated at different emitter current densities, the
difference in their base-emitter voltages, AVBE, is
AVBE = VBE1-VBE2 = kT In (JE1)
(1)
q
JE2
where k is Boltzman's constant, q is the charge on 'an electron, T is absolute temperature in degrees Kelvin and JE1
and JE2 are the emitter current densities of 01 and 02 respectively. A circuit realizing this function is shown in F1!JUfB
1.
TLlH/9051-1
FIGURE 1
Equation 1 implies that as long as the ratio of IE1 to IE2 is
held constant, then AVBE is a linear function of temperature
(thiS is not exactly true over the whole temperature range,
but a correction circuit for the nonlinearity of VBE1 and VBE2
will be discussed later). The linearity of this AVBE with temperature is good enough that most of today's monolithic
temperature sensors are based upon this prinCiple.
An early monolithic temperature sensor using the above
principle is shown in F1!JUfB 2. This sensor outputs a voltage
which is related to the absolute temperature scale by a faetor of 10 mV per degree Kelvin and is known as the LM135.
The circuit has a AVBE of apprOximately
(0.2 mV'OK) x (T)
developed across resistor R. The amplifier acts as a servo
to enforce this condition. The AVBE appearing across resistor R is then multiplied by the resistor string conSisting of R
+Ys
r - - - -.....-p--+-Your= IOmY/"K
R
IOOR
23R
TLlH/9051-2
FIGURE 2
908
non-inverting input of amplifier A2 is a voltage two diode
drops below the voltage across resistor nR1. This voltage is
then amplified by amplifier A2 to give an output proportional
to whichever temperature scale is desired by a factor of 10
mV per degree.
and the 26R and 23R resistors for an output voltage of
(10 mVI"K) x ne oIlhem should be logic one at any time.
_
Busy-bit Check Module
HB
These two bytes are the
LB
trajectory control word. A OA
hex LB indicates velocity and
position will be loaded and
both parameters are
absolute.
xx
xx
d
Setting bit ten of the trajectory control word selects stop
smoothly as the desired stopping mode. This mode stops
shaft motion by decelerating at the current user-programmed acceleration rate.
Comments
. P'?rt Bytes Command
sn
Busy-bit Check Module
FIGURE 7. Trajectory Programming Module"
c
1F
d
d
x1
00
c
. 01
STOP MODULE
This module demonstrates the programming flow required
to stop shaft motion.
While the LM628 operates in position mode. normal stopping is always smooth and occurs automatically at the end
of a specified trajectory (i.e. no stop module is required).
Under exceptional conditions. however. a stop module can
be used to affecta premature stop.
While the LM628 operates in velocity mode, stopping is always accomplished via a stop module.
The example stop module. shown in Rgure 8, utilizes an
LTAJ command sequence and an
command.
LTAJ
Comments
This command initiates
loading the trajectory
parameters input buffers.
Busy-bit Check Module
'HB
These two bytes are the
LB
trajectory control word. A x1
hex HB selects motor-off as
the desired stopping mode. A
00 hex.LB indicates no
trajectory parameters will be
loaded.
Busy-bit Check Module
The start motion control
must be
command.
executed to stop shaft
motion.
sn
sn,
Busy-bit Check Module
sn
FIGURE 8. Stop Module (Moto....Off)
Load Trajectoiy Parameters
Bits eight through ten of t/'le trajectory control word select
the stopping mode. See TBb/e V.
In the case of the example module, the first byte of the
trajectory contro,1 word. x1 hex, selects motor-off as the desired stopping mode. This mode stops shaft motion by setting the motor drive signal to zero (the appropriate offset-binary Code to apply zero drive to the motor).
Setting bit nine of the trajectory control word selects stop
abruptly as the desired stopping mode. This mode stops
shaft motion (at maximum deceleration) by setting the target
position equal to the current position.
II. PROGRAMS
This section focuses on the development of four brief
LM628 programs.
LOOP PHASING PROGRAM
Following initial power-up. the correct polarity of the motor
drive signal must be determined. If the polarity is incorrect
(loop inversion), the drive Signal will push the shaft away
929
Z
i
from its desired, position rather, than towards it. This r.a,sults
in "motor runaway", a condition characterized by the motor
running continuously at high speed."
The loop phasing program, detailed in Figt1r9 9, 'contains
both the example initialization and filter programming modules. It also contains an 'LTRJ command sequence and an
STT command.
If the polarity of the motor drive signal is Incorrect (Iqop
inversion), motor runaway will occur immediately litt$r execution of comman!! STT, or after the shaft is forced (CAREFU LLY) from its resting pOSition.
Loop inversion' can be corrected with one of three methods:
interchanging the shaft position encoder signals (channel A
and channel B), interchanging the motor power leads, or
inverting the motor command signal before application to
the molo,r drive amplifier. For LM629 based systems, loop
inversion can be correct4lld by interchanging the motor pow'er leads, interchanging the shaft position encoder Signals,
, or logically inverting the PWM sign Signal.
Note: Execution of this simple program'ls only !'$<:
1-._ _ _
+12V -12V
DAC0800
digital-to-analog
convert.r
1-.....- _ from
LN628/lN629 pin 17 (host Interrupt output)
to scope trigger
TLfH1I0B80-23
FIGURE 24. Circuit for Viewing the System Step Response with an Oscilloscope
941
T
5V/dIv
100 rnSEC/dlv
f'
Trigger. Signal +
Step Respon..
I
,
'~
+
CHI
,
(\.;,
-
\
CH2
TL/H/l0BflO-24
,
FIGURE 25. The Step Reeponaa of an Under Qampad Control Syatem
T
SV/dlv
100 msEc/dlv
I
Trigger Signal +
Step Respon..
+
-
I
V
V
CHI
CH2
TLlH/l0e60~25
, FIGURE 26. The Step Response of en OVer Damped Control System
T
5V/dlv
100 rnSEC/dlv
Trigger Signal +
step Response
f
I
+ ~I(
If
FIGURE 27. The Step Response of a Critically Damped Control sy~em
942
CHI
CH2
Tl.(H/l0860-26
A DMOS 3A, 55V, H-Bridge:
The LMD18200
National Semiconductor
Application Note 694
Tim Regan
INTRODUCTION
The switching power device shown in F/{Jure 1 is called an
H-Bridge. It takes a DC supply voltage and provides 4-quadrant control to a load connected between two pairs of power
switching transistors. Because the switches allow current to
flow bidirectionally, the voltage across the load and the direction of current through the load can be of either polarity.
Figure 2 shows a functional block diagram of the
LMD18200. The circuit contains four DMOS power switching transistors, with intrinsic clamp diodes, connected in an
H-Bridge configuration. All level shifting and drive circuits
are included to permit control of the H-Bridge from standard
logic compatible signal levels. Other unique features include
current sense circuitry, overcurrent and under-voltage protection, thermal warning and thermal shutdown. Each is discussed in more detail in the following section.
H-Bridges are often used to control the speed, position or
torque of DC and stepper motors. Traditionally implemented
with either discrete or monolithic bipolar transistors, fully integrated solutions are becoming increasingly popular in
printer, plotter, robotics and process control applications
that require 0.5A to 3.0A and operate from 12V to 55V. The
LMD18200 was designed to operate within this range and
was optimized for such applications.
+
Static
B1drectional
Switch
DC
Input
Supply,
A
Output
Vs
TL/H/l0B1S9-1
FIGURE 1. Basic H-Bridge Circuit
The LMD18200 was implemented in a process that allows
bipolar, CMOS and DMOS devices to be incorporated together on one die. As each of these types of transistor
structures has its own unique characteristics, each is ideally
suited for a different function. By integrating them together,
this allowed us to take advantage of several innovative design techniques to provide easy to use benefits typically
unassociated with a simple motor driver.
THERMAL FLAG OUTPUT
BOOTSTRAP 1
KEY FEATURES
DMOS Power Drivers
DMOS power transistors allow current to flow bidirectionally
and provide a lower voltage drop than similarly rated bipolar
power transistors by virtue of a greatly reduced on resistance for each switch. They also have the potential to operate at much faster switching speeds for more efficient operation. And, as each switch contains its own intrinsic protection diode, the additional external protection diodes that are
required for bipolar transistor implementations are no longer
necessary.
Low On ReSistance
Unlike bipolar transistors, which have a relatively high voltage drop across them, even at lower cUrrents, the DMOS
devices in the LMD18200 have a voltage drop that is essentially a linear function of temperature. The on resistance,
ROS(on), of each output transistor is typically 0.30 at a junction temperature of 25°C and 0.60 at 125°C. At 100"C and
1A of current, a comparable bipolar transistor will have a
voltage drop from collector to emitter of about 1.1 V whereas
with the LMD18200 this voltage drop will only be 0.45V. At
higher current levels the lower voltage drop across a DMOS
power device provides an appreciable reduction in power
dissipation resulting in smaller heat sink requirements and
better efficiency with more power throughput to the load.
OUTPUT 1
OUTPUT 2
10
BOOTSTRAP 2
11
1--I--=:.:...ti-l--4'"'l 8
CURRENT
SENSE
OUTPUT
DIREcnON 3
BRAKE 4
PWM 5
7
GROUND
TL/H110859-2
FIGURE 2. Block Diagram of the LMD18200
943
logic
Command
~.
,042 Off
A1·Qff
I...._..;;;A2;.;0:;;."_ _ _ __
~
R';'=O'~
:.....J ! ~ InIrIn.1c ,.
. ~
.
,
Total
Current
In 141
,
.,
Diode
. .t Revene cl:lrrtnt
1through switch
,
'
TUH/l0~59-3
FIGURE 3. A DMOS Switch with
Intrinsic Protection Diode .
,
O-----T----I
R";":'"~', , ' 0
Current in
,Cha"no'
0················
.
'"tr~ ~:·~1~ O--'TI-~'-'...;..~
Current
~u
"
a
. 0 _ ----------
~
-
TL/l't/l0959-4
FIGURE 4. Waveforms Illustrating the Commutation of "Reverse" Current
In One Switch (A 1) to "Forward" Current In Another SWitch' (A2)
Bidirectional Current Switches
with Intrinsic Protection Diodes
age drop not only takes away from the ayailable voltage to
be applied to the load but is also somewhat difficult to am·
plify due to very low or possibly fast varying common mode
voltage presented to the amplifier.
The principle employed in the LMD18200 is the same as
that used in discrete current sensing power MOSFETs.
Each DMOS power transistor is actually comprised of many
smaller cells connected in parallel. Due to the positive tern·
,perature coefficient of the ON resistance of each cell, the
'total current through the switch di\tides almost equally be·
tween the individual cells. A few of these cells are separat·
ed out to provide a current that is a scaled down replica of
the total switch current. Figure 5 shows a simplified func·
tional diagram of the current sensing' circuitry.
When driving inductive and inertial loads such as motors the
power switches must be able to conduct "forWard" as well
as "reverse" current. The energy stored in these types of
loads must generally be free to return to the supply.
The· conl(entional methQd of, providing a Path for reverse
current is to connect an antiparallel diode acro.ss ~he power
switch as sho~n in Figure 3.
'
With the DMOS structure used'in the LMD18200 this diode
is intrinsic. Reverse current is actually shared between the
power switch and the diode due to the fact that the 'DMOS
switch, can conduct current in either direction. For current
levels less than 2A to 2.5A the voltage across the power
!\witch, (lxROS(on)), is less than the forward threshold volt·
age of the diode and all of the current flows through the
switch. At higher current levels the diode conducts and the
. current is sl:1ared.
An important consideration in the design of the LMD18200
was to make sure that the power switches could handle not
only the load current but also the additional reverse recov·
ery current of the protection diodes. This is illustrated in
Figure 4 where switch A 1 is initially ON and conducting reo
verse current. At the interval when A 1 is commanded OFF
and the lower switch in the same leg of the H·Bridge, A2 is
commanded ON, a short deadtime (purposely buill in to the
LMD18200 to eliminate "shoot·through" currents) occurs.
During this time current begins to flow through the protection diode across switch A1. When' sYl,itch A2 comes ON,
the diode becomes reverse biased. Switch A2 must then
conduct the load current plus the reverse recovery current
of the diode for the short (approximately 100 ns) reverse
recovery time of the diode. This additional requirement on
the power switches has been accommodated in the design
of the LMD18200.
The current sourced by the Current Sense Output pin is a
current proportional to the sum of the total forward current
conducted by the two upper DMOS switches of the H·
Bridge. This sense current has a typical value of 377 p.A per
Amp of current through the power devices. Simply connect·
ing a resistor between the sense outputpin.and ground con·
verts this current to a voltage proportional to the CUrrent
being delivered to the load. This voltage is then suitable for
feedback control or load over·current protection purposes.
.
-.
I
I
I
I
I
I
I
I
I
I
I
: '--HW....
I
I
I
I
I
I
I
:~":Its.~
..----------------I
Current Sensing
A unique feature of the LMD18200 is circuitry that allows for
the sensing of the current through the load without affecting
the supply or ground return lines. A common method for
~n$ing the load current is to insert a small valued power
resistor in series with either the Vcc supply or grOl,lnd lines
and detect the voltage drop across this resistor. This volt·
,
-----------------.!
TUH/l0959-5
FIGURE 5. The Current Sensing
Circuitry of the LMD18200
944
Charge Pump and Bootstrap Circuitry
charge pump capacitor, Ccp, is charged to approximately
14V. When 01 Is switched ON the bottom of this capacitor
is connected to the supply voltage, Vs. This causes the voltage at point X, which connects to the gate, of the upper
DMOS power switch, to rise to about 14V 'more positive
than the supply. This ensures that the upper device
switches ON even if its source is at the VS potential.
In order to drive a DMOS switch ON; its gate must be driven
approximately 10V more positive than its source voltage.
The lower switches of the H-Bridge have their source terminals connected to ground and their gate drive is derived
from the Vs supply voltage to the device. The two upper
switches however have their source terminals connected to
the output pins which are continually bein!;! switched between ground and Vs. In order to generate the gate drive
voltage for these switches a charge pump circuit is used.
Figure 6a illustrates this circuitry.
Capacitor CcP is limited in value for practical considerations. Due to the limited charge that can be stored in Ccp
the turn-on time of the upper DMOS transistors is relatively
slow but nevertheless satisfactory for operating frequencies
up to around 1 kHz. Once the DMOS device is turned ON
the 300 kHz oscillator keeps the charge pump circuit running thereby holding the power device ON as long as it is
commanded by the input control to do so. This charge pump
circuit takes care of all the necessary voltage conditioning
required by the DMOS transistors so that the external logic
control applied to the LMD18200 can be simple TTL compatible signals.
Transistors 01 and 02 are toggled at an internally generated clock frequency of 300 kHz. When 02 is ON, the on-chip
+Vs
For higher frequency operation, faster turn-on of the upper
DMOS switches is necessary. This can be obtained through
the use of external bootstrap capaCitors. The bootstrap circuit is shown in Figure 6b. The operating principle is similar
to that of the charge pump Circuitry except that the switching of the bootstrap capacitor, CB, is assumed by the DMOS
power switches of the H-Bridge itself. With plenty of c!lrrent
available to charge these external capacitors they can have
a relatively large value (10 nF is recommended) and still be
charged in typically less than one microsecond. Since CB is
much larger than the input capacitance of the DMOS power
transistors, these transistors can now turn ON very rapidly,
typically in about 100 ns, thus allowing operating the
LMD18200 at switching frequencies up to 500 kHz. Figure 7
illustrates the switching performance of the upper transistors with and without the use of external bootstrap capacitors.
GROUND
TL/H/l0859-B
(a)
+Vs
PIN 1 OR 11
EXTERNAL
900TSlRAP
CAPACITOR
Overcurrent Protection
PIN 2 OR 10
The current through the upper two power DMOS switches is
c,ontinually monitored and compared against a shutdown
trip level (approximately 10A). In the event of a short batween the two outputs or a short from either output to
ground or any load condition creating excessive current to
GROUND
TUH/l0659-7
(b)
FIGURE 6. Internal Charge Pump Used In
the LMD18200 (a); the Use of External
Bootstrap CapaCitors (b)
~~,Dl\.
................. ,
.. " .... , . . . . .
J~~O)., ..
. " ............... , .............. .
I A2,B2 ON I- A2,Bl ON I A2,B2 ON I
I A2,B2 ON I A2,Bl ON I A2.B2 ON I
TUH/l0B59-B
TLlH/l0659-9
FIGURE 7. Comparison of SWitching Waveforms with and without the Use of Bootstrap CapaCitors
945
flow, the overcurrent protection circuitry will switch the upper switches OFF. A unique feature of this protection mechanism is that the protection circuitry will periodically (approximately every 8 /Ls) tum the upper switches back ON again,
so long as the input logic is commanding the switch to be
ON. This allows the H-Bridge to restart automatically following a temporary overload fault.
(the top switch in one leg of the H-Bridge together with the
bottom switch of the opposite leg) are driven ON and OFF
together ("locked" together, hence the name Locked Antiphase control). At zero average outp!.!t voltage, the average
voltage at. each output terminal is midway between the Vee
supply and ground. For this condition the conduction duty
cycle of each sw~tch is 50% and the average. current
through the load is zero.
As the A 1,B2 locked conduction interval is increased by
changing the duty cycle of the control signal (75% as shown
in the figure), the conduction time for the A2,B1 pair is correspondingly decreased. This duty cycle change makes the
average voltage at VoA more positive than VaB thereby
impressing a voltage across the load. The average current
through the load then flows in the direction from terminal
VoA to VaB. With a motor load this causes rotation in one
direction with a speed proportional to the amount that the
duty cycle deviates from 50%. Conversely, when the duty
cycle is decreased to less .than 50%, the average voltage
from VoA to VaB becomes negative, the average current
through the load then flows from VaB to VoA and the direction of rotation reverses.
If the ripple current through the load ever wants to reverse
its direction it is free to do so. This is due to the fact that two
switches are always driven ON and are always able to conduct current of either polarity. Another benefit of this type of
control is that the voltage across the load is always defined
by the state of the switches, regardless of the direction the
load current wants to flow.
Thermal WarnlngITherntal Shutdown'
As with any' power device protection against excessive operating temperature is a must. The LMD18200 continually
senses the junction temperature near the DMOS switches
and disables all of the switches in the event that this temperature reaches approximately 170"C thus protecting the
device from catastrophic failure. There is a slight amount of
hysteresis associated. with this temperature threshold so
that when the temperature cools slightly the device will automatically restart.
Another unique feature of the LMD18200 is the provision of
an early warning flag of .excessive operating temperature.
This is an open collector o!.!tput pin which pulls to a logic 0
state when the junction temperature reaches 145°C. This
flag can signal the system controller that the pOwer driver is
getting too hot and should be either shut down or have the
output power cut back. The warning flags from any !lumber
of H-Bridges can be directly wired together for an "Or'd"
connection.
.
Undervoltage Lockout
The LMD18200 also features undervoltage lockout This circuitry disables all of the switches when the DC power supply
voltage falls below approximately 10V. The reason for this
feature is that reliable, well controlled operation of the
switches cannot be assured without at least 10V applied.
In applications where fast dynamic control of inertial loads
(i.e., the rapid reversal of the direction of rotation of a motor)
it is important that the "regeneration" of net average power
from the load back to the supply be able to take place. With
two switches ON there is always a path for this regenerative
energy.
OPERATION
The average output voltage across the load of the H-Bridge
is continuously controlled by Pulse Width Modulation
(PWM). Either polarity of output voltage can be obtained
and current can flow through the load in either direction as
required. The LMD18200 has three logic control inputs,
PWM, Direction and Brake which control the switching action of the H-Bridge. Figure 8 outlines the effect of these
control inputs. The logiC control inputs can be used directly
(without external logic) to implement two of the more common PWM control techniques, Locked Antiphase control
and Sign/Magnitude control.
PWM
Dlr
Brake
Active Output Drivers
H
H
L
H
H
L
H
L
L
L
L
H
H
H
A1,B2
A2,B1
A1, B1
A1, B1
A2,B2
NONE
X
H
L
X
A major advantage of Locked Anti-phase control is that only
one control signal is required to control both the spaed and
direction of a motor load. Simply modifying the duty cycle
adjusts the average voHage and current to the load for
speed control and the direction of rotation depends on
whether the duty cycle is greater than or less than 50%.
One disadvantage of Locked Anti-phase control with the
LMD18200 is that the current sense output is discontinuous
as shown in Figure .9. This is becauSe the current sensing
transistors only mirror "forward" current through the upper
two DMOS power devices. "Reverse" current, when the direction of current flow is in the opposite direction of what it
should be for a given polarity of voltage across the load, is
not output to the current sense pin.
Sign/Magnitude Control
A second method of PWM control directly supported by the
LMD18200 is termed Sign/Magnitude control. The ideal
waveforms jor this technique are illustrated in Figure 10.
The voltage of the output terminal of one leg of the H-Bridge
is held stationary while the average voltage of the opposite
leg is varied by the duty cycle of a pulse width modulated
input Signal. The Sign or polarity of the voltage across the
load is dictated by which side of the H-Bridge is held stationary by having one of the transistors constantly ON, and the
Magnitude of the average load voltage is determined by the
switching duty cycle of the two switches in the opposite leg.
FIGURE 8. Control logic Truth Table
Locked Anti-Phase Control
The basic connection diagram and idealized waveforms for
driving an inductive load using Locked Anti-phase control
are illustrated in Figure 9. Under the control of the single
PWM input Signal, diametrically opposite pairs of switches
946
LOCKED ANTIPHASE CONTROL
+vee
+5V
PWII
1ILo-=DlR~
50% duty cycl.
Switch •• 'ON': U,B1
A1.B2
U.B1
~'~<_LOJ
75% duty cycle
A2.B1
A1.B2
25% duty cycle
A2.B1
A2,B1 A1.B2 U.B1
_ _ u1f][___ u_1 n
,;':_[UJ _____ IlJl _____
1_
m_
+ Vee
VoA-VoB OV-
---
--------
-----
_
------
_
-------
-----
-Vee
-~-
+
o-~---------------------------------------
'Output Current
from VoA to VOB
-~-
Current Sen..
output current
lIotor ActIon :
-lL1£-----------------C:1C:----- -------------------
+
o~~---lIotor stopped. a.erag.
current Is O.
lIotor turning In
direction set by
average current
flowing from VoA to
VoB.
lIotor running at
same spood as
with 75% duty cycle
but In opposite
direction.
TUH/l0859-10
FIGURE 9. Idealized Switching Waveforms for Locked Antiphase Control
947
SIGN/MAGNITUDE CONTROL
lJL
L
DIrectIon
5Y--------------------------~
,
I
OY----------------------------~·--------------------------SOlI: duty cycl.
25% duty cycle
50% duty cycle
75% duty cycle
+YCC
YeA
'
'
IU UU
~-------------------------------
Y
Yoa+ :
---
-
--
ru. _IJ[J ________ ~ ____________________ -+~-
output Curront
from YeA to Yoa
0- - - - - - - - - - - - -
-:~ - - - - - - -" - - - - - - -'- - - - - - - - - - - - - - -~-
+~Cur:ront Son..
output current
Motor ActIon:
-~
-~
-~
-~
0------------------"--------------------------------------Motor tum. at
average spaed In
dIrectIon set by
'curron! flowing from
,
YeA to YoB.
Motor turns In the
sam. direction as
with 50% duty cycle
but' at half tHe speed.
Motor turns at
average speed but
In opposite dIrection
as eel by ourront"
flowing from YoB to
Motor turns In oppos~
dIrection but 50l1: faster
than the spaed with 50%
duty cyol••
YeA·
TL/H/10859-11
FIGURE 10. Idealized Switching Waveforms for Sign/Magnitude Control
948
.--------------------------------------------------------------------.~
The logic level applied to the Direction input turns ON either
switch A1 or B1. This fixes output VoA or VoB at the positive supply voltage potential and therefore sets, the direction
of current flow through the load. The duty cycle of the signal
applied to the PWM pin then adjusts the average voltage
and current to the load. As the duty cycle is increased, the
power to the load increases causing a faster speed of rotation of motor loads.
Keeping one of the upper transistors continually ON for
Sign/Magnitude control is preferred with the LMD18200 because the current sense output will remain permanently active. Current will always be flowing through one upper transistor or the other (through switch A1 or B1) which will be
sensed and output to the current sense pin. This gives a
continuous representation of the load current without the
discontinuities of the locked anti-phase technique. This is
true so long as the direction of the current through the load
corresponds with the polarity of voltage across the load. If
the direction of rotation of a motor load is required to reverse there will be a short interval where the load regenerates net energy back to the supply and "reverse", current
flows through the upper power devices and momentarily
causes a discontinuity in the current sense output signal.
the ON/OFF switching action of the H-bridge. The combined total energy of a switch turning ON and the protection
diode of a switch turning OFF can be approximated by:
VSIOtoN
EON = --2--
+ Vs QRR + Vs 10 tRR
When turning OFF one of the DMOS switches and transferring the current back to the protection diodes of the other
switches, the turn-off energy can be approximated by:
E
VslotoFF
OFF =
2
The total average switching power dissipation can then be
found by:
Psw = (EON + EOFF) X f
This is the switching power dissipation for applications using
Sign/Magnitude control where only one transistor is
switched at a time. This power dissipation is doubled with
locked anti-phase control because two transistors are always being switched simultaneously:
Psw = 2 X (EON + EOFF) X f, for locked anti-phase.
For these equations use the following values:
Vs
Supply voltage
10
peak current to the load
toN
turn ON time of the DMOS transistors, 100 ns with
external bootstrap capacitors, 20 p.s without
toFF
turn OFF time of the DMOS transistors, 100 ns
with external bootstrap capaCitors, 20 p.s without
QRR
recovered charge of the intrinsic protection diode,
use 150 nanocoulombs
tRR
reverse recovery time of the intrinsic diode, use
100 ns
operating switching frequency of the H-Bridge
These values will provide a good, worst case approximation
of the switching power diSSipation.
Total Power DI88lpatlon, PTOT
, The total power dissipation of the package is the sum of
these three components:
Braking
Emergency braking of a motor by shorting its terminals is
achieved by taking both the PWM and Brake input pins to a
logic 1 level. If the Direction input is at a logic 1, then braking will be accomplished by the two upper switches (A1 and
81) turning ON and shorting the motor, if a logic 0 then the
lower switches (A2 and B2) will short out the motor. It is
preferable to perform braking using the upper switches because they are protected by the overcurrent trip circuitry.
CALCULATING POWER DISSIPATION
To obtain the full performance benefits of the LMD18200 it
is important to consider the power dissipation of the device
and provide adequate heat sinking as necessary. There are
three components that make up the total power dissipation,
Quiescent, Conductive and Switching power. The following
equations will provide a worst case approximation of each
of these components.
PrOT = Po + PCOND + Psw
,At low switching frequencies, less than 50 kHz, most of the
power dissipated is conductive. When operating at higher
frequencies, the switching power dissipation can become
considerable and must be taken into consideration.
At 25"C ambient operating temperature with the power TO220 package in free air, the LMD18200 can diSSipate approximately 3W without requiring a heat sink.
Quiescent Power DIsSipation, Po
This term is simply the quiescent, no load, power diSSipation:
PQ,= Is X Vee
Is = the quiescent supply current (typically 13 mA with a
maximum value of 25 mAl
Vee = the supply voltage
APPLICATION EXAMPLES
Applying the LMD18200 Is very easy because it is fully selfcontained. The only external components required for the
power stage are supply bypass capacitors and optional
bootstrap capacitors and/or a current sense resistor depending on the particular application. The challenging part
of any application is generating and modulating the PWM
control signal. This can be achieved with dedicated PWM
generators like the LM3525, with simple op amp/comparator configurations, a programmable micro-controller output
line, or with a dedicated motion control device like the
LM629.
Conductive Power DI88lpatlon, PCOND
This term is the power diSSipation of the switches carrying
the load current. In all applications the load current is conducted by two of the switches. The equivalent series resistance of the H-Bridge is approximately twice the on-resistance of one switch. The power dissipated by the switches
can be found by:
PCOND = 2 X 12RMS X ROS(on)
IRMS = worst case value of the RMS load current
Roston) = the ON resistance of a power switch at the operating junction temperature, 0.330 typically at
25"C and 0.60 maximum at 125"C.
Switching Power DI88lpatlon, Psw
Switching power dissipation is the combination of the energy dissipated by the switches and protection diodes during
949
z
~
;
~
;---------------------------------------------------------------------------------,
Ftgure 11 illustrates the direct interface of an LM629 to the
LMD18200 to control either the position or, velocity of a DC
motor., The LM629is a digitally programmable motor controller which outputs a Sign bit and variable PWM control
signal to drive the LMD18200. Feedback of the motor position is accomplished via an optical shaft encoder which generate$ a given number of counts per revolution of the motor
shaft. The digital control algorithm is proCesseilby the
LM629 in response to cdinmands from a host microcontrollar. As shown, the thermal flag output of the LMD18200 can
be used to shutdown the system ot back off the drive to the
motor should the IC begin to overheat. Emergency braking
can also be achieved by directly driving the Brake input of
the LMD18200 from an output line of the processor.
In many,applications it is desired to control the torque, of a
motor load which is proportional to. the current through the
motor. Using the current sense feature of the LMD18200
provides an easy means of sensing' and contrOlling the motor current as shownin.Figure 12. In this application the
LM3525 Regulating Pulse Width Modulator compares .the
voltage at the current sense output pin of the LMD18200
with an externally generated control voltage and adjusts the
duty cycle , of. the control, signal, (from, 0 to appro)(imately
5Q%) until the motor is, running at the set desired current
level. In this example the ,switching frequency is set to
40 kHz tbereby requiring the use ot boqtstrap capacitors.
This is ,also an ,example of loc,ked anti-ph!lSe control. By
simply inverting the phase ot' the single control input the
direction Of motor rotation can be reversed.:
+5V
, Motor voitage
Thermal Flag
IRQ
Sign
8 '
Host
p,C
-?',Bus
Olr
Motor
LM018200
LM629
Magnltud.I---I~PWM
Encoder
2 or 3
,TLIH/l,0859-1~
FIGURE 11. Direct Interface of an LMD 18200 to th, LM629 Motion Control Devi!l8
DIRECTION CONTROL
L..r
3
111-------------~1
3000
12V TO 24V
LM3525A
21-.....__--,
LM018200
+10V
VCURRENT
ADJUST
~.--..
O.25A ,TO 3.25A
24V DC MOTOR
11
lk
9~------.
10k
2
3.6k
6.19k
1%
TUH/l0859-13
FIGURE 12. UtilizIng the Current Sense Feature to Control ,he rorqu:e ,of a Motor Load
950
Figure: 13 shows a conventional analog control scheme
age motor current modulates or "dithers" about the preset
level. The amount of ripple current is proportional to the
time interval of the one-shot. A certain minimum amount of
ripple is required to prevent the voltage comparator from
oscillating. The equivalent of 50 mV voltage change at the
input to the comparator is sufficient.
termed "Fixed Off Time Control". This again takes advantage of the current sensing feature of the LMD18200. A
voltage 'repre$Elntjng the current through the motor is again
compared with an externally generated control voltage.
Whenever the motor current exceeds the desired set level a
one shot is triggered which turns on the two upper switches
of the H-Bridge, shorting out the motor for a fixed time interval. This causes the motor current to decrease. At the end
of the one-shot interval, voltage is reapplied to the motor
until the current once again exceeds the desired level. As
shown in the accompanying waveforms, F/{Jure 14, the aver-
The off time interval is equal to 1.1 Re, which are the timing
components,for the LM555 timer.
This application is an example of Sign/Magnitude control.
To reverse the motor direction simply drive the Direction
input of the LMD18200.
24 VOLTS
R
-
4
8
12kA
2
MAG.
5
3
1.33 AMP/VOLT
-
-
6
-
5
O.OII'~
6
PWM
5
2
+12V
10kA
LMD18200
24V
3 AMP
DC MOTOR
10kA
DIR
3
I I
BRAKE
10
FORWARD REVERSE
8
7
Torr = 1.1 RC
TL/H/10859-14
FIGURE 13. Fixed OFF Time Control
DIRECTION
OUTPUT 1
OUTPUT 2
REVERSE
_ _ _FORWARD
_ _ _ _---11..-_ _
_ _ _ _ _••
___. . 10
. . . . . .0. . . . .0. . . . 0. . . . .0. . .....
[l0 0 []
TIME
TIME
• TIME
MOTOR CURRENT -'-'--"'--"'-"'---1"'__
--"--------t--------+
TIME
CONTROLLED BY RC OF LM555N --JTOFFI-TL/H/10859-15
FIGURE 14. Switching Waveforms for the Fixed OFF Time Control Loop
951
~'-----------------------------------------------~~=====:l
.~ LM6281629 User'Guide ,
~papti~~:t,li~:~~~n;:,u~tor
."
i
. .
T...ble of Contents
1.0 INTRODUCTION
4.4 Initialization
1.1 Application Note Objectives
1.2 Brief Description of LM628/629
4.4.1 Hardware RESET Check
4.4.2 Initializing LM628 Output Port
4.4.3 Interrupt Commands
2.0 DEVICE DESCRIPTION
2.1 Hardware Architecture
2.2 Motor Position Decoder
2.3 Trajectory Profile Generator
2.4 Definitions Relating to Profile Generation
2.5 Profile Generation
2.6 Trajectory Resolution
2.7 Position, Velocity and Acceleration Resolution
2.8 Velocity Mode
2.9 Motor Output Port
2.10 Host Interface
2.11 Hardware Busy Bit Operation
2.12 Filter Initial Values and Tuning
4.5 Performance Refinements
4,5.1 Derivative Sample Rate
4.5.2 Integral Windup ,.
4,5.3 Profiles other than· Trapezoidal
4.5.4 Synchronizing Axes
4.6 Operating Constraints
4.6.1 Updating Acceleration on the Fly
4.6.2 Command Update Rate
5.0 THEORY
5.1 PIO Filter
5.1.1 PIO Filter in the Continuous Domain
5.1.2 PIO Filter Bode ,piots
3.0 USER COMMAND.,SET
5.2 PIO Filter Coefficient Scaling Factors for LM628/629
3.1 Overview
3.2 Host·LM628/629 .Communication-the BusV Bit
3.3 Loading the Trapezoidal Velocity Profile Generator
3.4 Loading PIO Filter Coefficients
3.5 Interrupt Control Commands
3.6 Data Reporting Commands
3.7 Software Example
4.0 HELPFUL USER IDEAS
5.2.1 PIO Filter OifferenCfil Equation
5.2.2 Difference Equation 'with LM628/629
Coefficients
5.2.3 LM628/629 PIO Filter Output
5.2.4 Scaling for kp and kcJ
5.2.5 Scaling for ki
5.3 An Example of a Trajectory Calculation
6.0 QUESTIONS AND ANSWERS
4.1 Getting Started
4.2 Hardware
6.1 The Two Most Popular Questions
6.2 More .on Acceleration Change
6.3 More on Stop Commands
6.4 More on Define Home
6.5 More on Velocity
6.6 More on Use of Commands
4.2.1 Host Microcontroller Interface
4.2.2 Position Encoder Interface
4.2.3 Output Interface
4.3 Software
7.0 ACKNOWLEDGEMENTS
8.0 REFERENCES AND FURTHER READING
952
..
r-------~----------------------------------------------------------_,~
List of Illustrations
Figure 1.
Figure '2:
LM628 and LM629 Typical System Block Diagram
Hardware Architecture of LM628is29
Figure 3.'
Quadrature Encoder Output Signals and Direction Decode Table
Figure 4.
Figure 5.
Figure 6.
L~628/629 Motor Position Decoder
Typical Trajectory Velocity Profile
Position, Velocity and Acceleration Registers
Figure 7.
LM628 12-Blt DAC Output Multiplexed Timing
Figure 8.
LM629 PWM Output Signal Format
Host Interface Internal I/O Registers
Figure 9.
Figure 10. Busy Bit Operation during Command and Data Write Sequence
Figure 11. Position vs Time tor 100 Count Step Input'
Figure 12. Basic Software Flow
Figure 13. LM628 and LM629 HO!lt, Output and Position Encoder Interfaces
Figure 14. LM628 Example of Linear Motor Drive using LM12
Figure 15. LM629 H-Bridge Motor Drive Example using LM18293
i4gure 16. Generating a Non-Trapezoidal Profile
Figure 17. Bode Plots of PID Transfer Function
Figure 18. Scaling for kpand
Figure 19. Scaling for k;
kcI
Figure 20. Trajectory Calculation Example Profile
Table I.
Trajectory Control Word Bit Allocation!!
953
Z
~
1.0 INTRODUCTION
Section 5 "Theory" is a short foray into theory which relates
the PIO coefficients that would be calculated from a continuous domain control loop analysis to those of the discrete
domain.,including the scaling factors' inherent to ,the
LM628/629. No attempt il! ,made to discuss pentrol system
theory as such, readers should consult, the ample ref~r
ences available, 'some'suggestions are made at the end of
this application note. Section 5 Concludes with an example
trajectory calculation, reviving those perhaps forgotten
ideas about acceleration, velocity, distance and time.
Section 6 "Questions and Answers~', is in question and ansWer fomiat and is born
of and dedicated to the many
interesting discussions with customers that have ta'ken
place.
'
1.1 Application Note Objective
This application note is intended to explain and complement
the information in the data sheet and also address the common user questions. While no initial familiarity with the
LM628/629 is assumed, it will be useful to have thEi'
LM628/629 data sheet close by to consult for detailed descriptions of the user command set, timing diagrams, bit
assignments, pin assignments, etc.
After the following brief description of the LM628/629, Section 2.0 gives a fairly full description of the device's operation, probably more than is necessary to get going with the
device. This section ends with an outline of how to tune the
control system by adjusting the PIO filter coefficients.
Section 3 "User Command Set" discusses the use of the
LM628/629 commands. For a detailed description of each
command the user should refer to the data sheet.
Section 4 "Helpful User Ideas" starts with a short description of the actions necessary to get going, then proceeds to
talk about some performance enhancements and follows on
with a discussion of a couple of operating constraints of the
device.
out
1-2 Brief Description of LM628/629
LM628/629 is a microcontroller peripheral that incorporates
in one device all the functions of a sample-data motion con"
trol system controller. Using the LM628/629 makes the patentially complex task of designing a fast and precise motion
control system much easier. Additional features, such as
trajectory profile generation, on the "fly" update of loop
compensation and trajectory, and status reporting, are included. Both position and velocity motion control systems
can be implemented with theLM628/629.
LM628 or LM629
TLlH/ll018-1
FIGURE 1. LM628 and LM629 Typical System Block Diagram
954
LM628/629 is itself a purpose designed microcontroller that
implements a position decoder, a summing junction, a digital
PID loop compensation filter, and a trajectory profile generator, Figure 1. Output format is the only difference between
LM628 and LM629. A parallel port is used to drive an 8- or
12-bit digital-ta-analog converter from the LM628 while the
LM629 provides a 7-bit plus sign PWM signal with sign and
magnitude outputs. Interface to the host microcontroller is
via an .8-bit bi-directional data port and six control lines
which includes. host interrupt and hardware reset. Maximum
sampling rates of either 2.9 .kHz or 3.9 kHz are available by
choosing the LM6268/9 device options that have 6 MHz or
8 MHz maximum clock frequencies (device -6 or -8 suffixes).
In. operation, to start a movement, a host microcontroller
downloads acceleration, velocity and target position values
to the LM628/629 trajectory generator. At each sample interval these values are used to calculate new demand or
"set point" positions which are fed into the summing junction. Actual position of the motor is determined from the
output signals of an optical incremental encoder. Decoded
by the LM628/629's position decoder, actual position is fed
to the other Input of the summing junction and subtracted
from the demand position to form the error Signal input for
the control loop compensator. The compensator is in the
form of a "three term" PID filter (proportional, integral, derivative), this is implemented by a digital filter. The coefficients
for the PID digital· filter are most easily determined by tuning
the control system to give the required response from· the
load in terms of accuracy, response time and overshoot.
Having characterized a load these coefficient values are
downloaded from the host before commencing a move. For
a load that varies during a movement more coefficients can
be downloaded and used to update the PID filter at the moment the load changes. All trajectory parameters except acceleration can also be updated while a movement is in progress.
2.0 DEVICE DESCRIPTION
2.1 Hardware Architecture
Four major functional blocks make up the LM628/629 in
addition to the host and output interfaces. These are the
Trajectory Profile Generator, Loop Compensating PID Filter,
Summing Junction and Motor Position Decoder (Figure 1).
•1
I
en
~
en
~
""
'"'"
~
EQUAL RATES •
OF ACCELERATION
AND DECELERATION
>\7TOPPING POSITION
IS INTEGRAL OF
TRAPEZOID
TIME
FIGURE 5. typical Trajectory Velocity Profile
957
TL/H/11018-5
z
~
When performing a move theL~28/62l1 uses the information as:specified by.the,host and.accelerates until tile target
velocity is reached. While doing this it takes note of the
counts taken to reach the target lIelocity. This
number
nu.r:nber"of cou'1ts is sUbtractecUrorr th"target position to
determine whEl!'e deceiel"lltion. ~hould commence to.ensure
the mot9r stops at ~he ~get position. LM628/62$ d~lera
tiQll rates .are equal. to 'the acceleration r"tes. In~mEl easas, depend.ing on the .reilltive target values of velOOity, acceleration and pOSition, the target velocity will not be
reached and ,deceleration will commence immediately from
aCC~19ration."
",.
2.7 POSition, Velocity and Acceleration Resolution
Every sample cycle, while thE! profile demands acceleration,
the acceleration register is added to the velocity register
which iri ,turn· is added to the position register. When the
demand forincreasiiig acceleration stops, only velOcity is
added to the'position register. Orily integer values are output from the position 'register to thesuniriling junction and
so fractional position countS 'must accumUlate over many
sample interials before an integer'count is added and 'the
position register changed. Figure 6 shows the pOSition, velocity and acceleration registers;.
0'
The ·position dynamic' range is derived from the 32 bits of
the integer position register, Flf}l.tre6. The MSB is used·for
the'direction sign in the conventional manner, the next bit
30 is used to' signify When a position ollerflow called '"wraparound" has'Occurred. If the wraparolilnd bit is set (or reset
when', going 'in a negative direction) while· in operation' the
status byte bit 4is set and optionallY can be used to iriterrupt the host. The remaining 30 ,bItS provide' the .available
dynamic range of position in either the: positive or negative
direction (± 1,073,741,824 counts).
Velocity has a resolution of 1/216 counts/sample and acceleration has a resolution of 1/216 counts/sample/sample
as ·mentionedabove. The dynamic range is 30 bits in both
cases. The loss of one bit is' due to velocity and acceleration
being unsigned and another bit is used to detect wraparound. This leaves 14 bitS or 16,3~3 int~ral cOunts and'16
bits for fractional Counts.
.'
. ..
~ "',
2.6 Trajectory Resolution
The resolution the motor sees for'position is one 'integral
count. The algOrithm used' to calculate the trajectory adds
the velocity to the current desired position once per sample
period and produces the next'desired position point. In order to allow very low velocities it is necessary to have velocities of fractional counts per sample. The LM628/629 in addition to the 32-bit position range keeps track of 16 bits of
fractional position. The need for fractional velocity counts
can be illustrated by the following example using a 500 line
(2000 count) 'encoder and an 8 MHz clock LM628/629 giving a 256 ~.sample interval. ,It the sm~I,lest resolution is 1
count per sample then the minimum velocity, would be 2
revolutions per second or 120 rpm. (1/2000.rlMl(count x
1/256 p,s cQunts/S9CQnd). Many 08Pplications require veloc;i,:
ties and steps in velocity less .than this amount. This ill pro~
vided by the fractional counts of acceleration and velocity.
r
I.
16 Qlt.
T
2.8 Velocity Mode
LM628 supports a velocity mode where the motor is cOmmanded to continue al'a specified velocity, until it is told to
16 Bit. T ' 6 Bit.
I
I
I
I Position
_____.....___--.l.! Velocity'
------------j. . .
" Accel.ration
In.tegar - - - - ' - - Fraction
FIGURE 6~ Position, Velocity and Acceleration Regl~ters
958
TLlH/llDI8-6
stop (LTRJ bits 9 or 10). The average velocity will be as
specified but the instantaneous velocity will vary. Velocities
of fractional counts per sample will exhibit the poorest instantaneous velocity. Velocity mode is a subset of position
mode where the position is continually updated and moved
ahead of the motor without a specified stop position. Care
should be exercised in the case where a rotor becomes
locked while in velocity mode as the profile generator will
continue to advance the position. When the rotor becomes
free high velocities will be attained to catCh-Up with the current desired position.
DUTY CYCLE:
(a)
ffi= orr
PWM MAGNITUDE WAVEFORMS (pin 19):
1 (ON)
0---------------1r':LK
t-~1
1
MIN
1
(b) j2a= DRIVE 0
"1 ::~ t(e)
&i= D5R~~E
1
2.9 Motor Output Port
LM628 output port is configured to 8 bits after reset. The
8-bit output is updated once per sample interval and held
until it is updated during the next sample interval. This allows use of a DAC without a latch. For 12-bit operation the
PORT12 command should be issued immediately after reset. The output is multiplexed in two 6-bit words using pins
18 through 23. Pin 24 is low for the least significant word
and high for the most significant. The rising edge of the
active low strobe from pin 25 should be used to strobe the
output into an external latch, see Figure 7. The DAC output
is offset binary code, the zero codes are hex'80' for 8 bits
and hex'800' for 12 bits.
I,
128
(0) j2a =
~~~
DRIVE
WAX
D~:;E
'elK
1------------...:;:;;.....-----------0 (orr)
TL/HI1101S-S
Nole: Sign output (pin 18) not shown.
FIGURE 8. LM629 PWM Output Signal Format
2.10 Host Interface
LM628/629 has three internal registers: status, high, and
low bytes, Figure 9, which are used to communicate with the
host microcontroller. These are controlled by the RD, WR,
and PS lines and by use of the busy bit of the status byte.
The status byte is read by bringing Fm and PS low, bit 0 is
the busy bit. Commands are written by bringing iNA and PS
low. When PS is high, WR brought low writes data into
LM628/629 and similarly, Fm is brought low to read data
from LM628/629. Data transfer is a two-byte operation written in most to least significant byte order. The above description assumes that CS is low.
feLK
DATA:~
SELECT:
128
20.. _ _ _ _ _~
(
.....,j)
(PINS 18-23) ~....._H_'._H_.IT_S_ _
(PIN 24)
(d)!E=
~ 1-------I!--I..
STROBE:
(PIN 25)
INTERNAL
DATABUS
TLlH/l101S-7
FIGURE 7. LM628 12-Blt CAe Output Multiplexed Timing
The choice of output resolution is dependant on the user's
application. There is a fundamental trade-off between sampling rate and DAC output resolution, the LM628 8-bit output
at a 256 p.s sampling interval will most often provide as
good results as a slower, e.g. microcontroller, implementation which has a 4 ms typical sampling interval and uses a
12-bit output. The LM628 also gives the choice of a 12-bit
DACoutput at a 256 p's sampling interval for high precision
applications.
00-07
PINS
LM629 PWM sign and magnitude signals are output from
pins 18 and 19 respectively. The sign output is used to control motor direction. The PWM magnitude output has a resolution of 8 bits from maximum negative drive to maximum
positive drive. The magnitude output has an off condition,
with the output at logic low, which is useful for turning a
motor off when using a bridge motor drive circuit. The minimum duty cycle is 1/128 increasing to a maximum of
127/128 in the positive direction and a maximum of
128/128 in the negative direcition, i.e., a continuous output.
There are four PWM periods in one LM629 sample interval.
With an 8 MHz clock this increases the PWM output rate to
15.6 kHz from the LM629 maximum 3.9 kHz sample rate,
see Figure 8 for further timing information.
TL/HI1101S-9
FIGURE 9. Host Interface Internal 110 Registers
2.11 Hardware Busy Bit Operation
Before and between all command byte and data byte pair
transfers, the busy bit must be read and checked to be at
logic low. If the busy bit is set and commands are issued
they will be ignored and if data is read it will be the current
contents of the I/O buffer and not the expected data. The
busy bit is set after the rising edge of the write signal for
commands and the second rising edge of the respective
read or write signal for two byte data transfers, Figure 10.
The busy bit remains high for approximately 15 p.s.
959
, "......._ _ _ ThIS sequence repeated until '_ _ _ _ _....~I·
all date: byt•• are written
...,.,f:
CS ~.
" . - - - -- :-\"'---_ _ _ _ _
'------../
WR
or
.
I
-:,t-
-----""""---\J
RD
co~it:nd
BU:,i _______1
X22I::::: tv!!/IX d8~~~:yt. XZZZX da~~W~yl. XZZZl
I
I
lS-2;"P; ~;.;
.
T\
I
I
I·
TLlH/ll018-10
FIGURE 10. Busy Sit Operation during Co",mand and Data Write Sequence
sired and actual position and velOCity, to see if the error
between desired and actual positions of the motor are constant and not increasing without bound. See Section 3.6 and
the data sheet for information about the reporting commands. Clearly it will be difficult to tune for best system
~esponse if the motor and its load cannot achieve the demanded values of acceleration and velOCity. When correct
operation is confirmed and limiting values understood, filter
tuning can commence.
Due to the basic difficulty of accurately modeling a control
system, with the added problem of variations that can occur
in mechanical components over time and temperature, it is
always necessary at some stage to perform tuning empirically. Determining the PID filter coefficients by tuning is the
preferred method with LM628/629 because of the inherent
flexibility in changing the filter coefficients provided by this
programmable device.
The busy bit reset to logic low indicates that high and low
byte registers shown in Flflure 9 have been either loaded or
read by the LM628/629 intemal microcode. To service the
command or data transfer this microcode which performs
the trajectory and filter calculations is interrupted, except in
critical areas, and the on-golng calculation is' suspended.
The microcode was designed thili way to achieve minimum
latency when communicating with the host However, if this
communication becomes too frequent and on-going calculations are interrupted too often corruption will ·occur. In a
256 /Ls sample interval, the filter calculation takes 50 /LSi
outputting a sample 10 /Ls and trajectory calculation 90 /Ls.
If the LM628 behaves in a manner that is unexpected the
host communication rate should be checked in relation to
these timings.
2.12 Filter Initial Values and Tuning
When connecting up a system for the first time there may be
a possibility that the loop phasing is incorrect. As this may
cause violent oscillation It is advisable to initially use ~ very
low value of proportional gain; say kp = 1 (with lid, kj and. iI
all set to zero), which will provide a weak'ievel of drive to the
motor. (The Start command, STT, is sent to LM628/629 to
close the control loop and energize the motor.) If the system
does oscillate with this low value of kp then the motor connections should be reversed.
Before tuning a control system the effect of each of the PID
filter coefficients should be understood. The following is a
very brief review, for a detailed understanding reference (2)
should be consulted. The proportional coefficient, kp, provides adjustment of the control system loop proportional
gain, as this is increased the output steady state error is
reduced. The error between the required and actual position
is effectively divided by the loop gain. However there is a
natural limi~tion on how far kp can be increased on its own
to reduce output position error because a reduction in
phase margin is also a consequence of increasing kp. This
is first encountered as ringing about the final position in response to a step change. input and then instability in the
form of osc\IIation as the phase margin becomes zero. To
improve stability, kd' the derivative coeffiCient, provides a
damping effect by providing a term proportional to velocity
in antipl]asE;! to the ringing, or viewed in another way, adds
some leading phase shift into the loop and increases the
phase margin.
Having determined that the loop phasing is correct kp ca.n
be increased to a value of about 20 to see that the control
system basically works. This value of kp should hold the
motor shaft reasonably stiffly, retuming the motor, to the set
pOSition, which will be zero until trajectory values have been
input and a position move performed. If oscination or unacceptable ringing' occurs with a kp value of ·20 reduce this
until it stops: Low values of acceleration and velocity can
now be input; of around 100; and a position move commanded to say 1000 counts. AII'values suggested here are
decimal.' For details of loading trajectory and filter parameters see Section 3.0, reference (5) and the data sheet.
It is useful at this stage to
different values !)f acceleration
and velocity to get a feel for the system limitations. These
can be determined by using the reporting commands of de-
In the tuning process the coefficients kp and lid are iteratively increased to their optimum values constrained by the system constants and are trade-offs between response time,
stability and final pOsition error. When kp and kd have been
determined the integral coefficient, k;, can be introduced to
remove steady state errors at the load. The steady statE;!
trY
960
errors removed are the velocity lag that occurs with a constant velocity output and the position error due'to a constant
static torque. A value of integration limit, ii, has to be input
with kj, otherwise kj will have no effect. The integral coefficient kj adds another variable to the system to allow further
optimization, very high values of kj will decrease the phase
margin and hence stability, see Section 5 and reference (2)
for more details. Reference (5) gives more details of PID
filter tuning and how to load filter parameters.
TABLE I. TraJectory Control Word Bit Allocations
Bit Position
Agure 11 illustrateS' how a relatively slow response with
overshoot can be compensated by adjustment of the PID
filter coefficients to give a faster critically damped response.
3_0 USER COMMAND SET
3_1 Overview
The following types of User Commands are available:
Initialization
Filter control commands
Trajectory control commands
Interrupt control commands
Data reporting commands
User commands are single bytes and have a varying number of accompanying data bytes ranging from zero to fourteen depending upon the command. Both filter and trajectory control commands use a double buffered scheme to input
data. These commands load primary registers with multiple
words of data which are only transferred into secondary
working registers when the hOst issues a respective Single
byte user command. This allows data to be input before its
actual use which can eliminate any potential communication
bottlenecks and allow synchronized operation of multiple
axes.
Bit 15
Bit 14
Bit 13
Bit 12
Not Used
Not Used
Not Used
Forward Direction (VelOCity Mode Only)
Bit 11
Bit 10
Bit 9
Bit 8
Velocity Mode
Stop Smoothly (Decelerate as Programmed)
Stop Abruptly (Maximum Deceleration)
Turn Off Motor (Output Zero Drive)
3.3 Loading the Trapezoidal Velocity Profile Generator
To initiate a motor move, trajectory generator values have
t6 be input to the LM628/629 using the Load Trajectory
Parameters, LTRJ, command. The command is followed by
a trajectory control word which details the information to be
loaded in subsequent data words. Table I gives the bit allocations, a bit is set to logic 1 to give the function shown.
6
5
4
Not Used
Not Used
Acceleration Will Be Loaded
Acceleration Data Is Relative
Bit
Bit
Bit
Bit
3
2
1
0
Velocity Will Be Loaded
Velocity Data Is Relative
Position Will Be Loaded
Position Data Is Relative
Underdamped
v
7
Bit
Bit
Bit
Bit
Bits 0 to 5 determine whether any, all or none of the position, velocity or acceleration values are loaded and whether
they are absolute values or values relative to those previously loaded. All trajectory values are 32-bit values, position
values are both positive and negative. Velocity and acceleration are 16-bit integers with 16-bit fraGtions whose absolute
value i,s always positive. When entering relative values ensure that the absolute value remains positive. The manual
stop commands bits 8, 9 and 10 are intended to allow an
unprogrammed stop in position mode, while a position move
is in progress, perhaps by the demand of some external
event, and to provide a method to stop in velocity mode.
They do not specify how the motor will stop in position
mode at the end of a normal position move. In position
mode a programmed move will automatically stc;>p with a
deceleration rate equal to the acceleration rate at the target
position. Setting a stop bit along with other trajectory parameters'at the beginning of a move will result in no movement!
Bits 8, 9 and 10 should only be set one at a time, bit 8 turns
the motor off by outputting zero drive to the 11)0tor,' bit 9
stops the motor at maximum deceleration by setting the target position equal to the current position and bit 10 stops
the motor using the current user-programmed acceleration
value. Bit 11 is set for operating in velocity mode and bit 12
is set for forward direction in velocity mode.
3.2 Host-LM628/629 Communication-The Busy Bit
Communication flow between the LM628/629 and its host
is controlled by using a busy bit, bit 0, in the Status Byte.
The busy bit must be checked to be at logic 0 by the host
before commands and data are issued or data is read. This
includes between data byte pairs for commands with multiple words of data.
V
Function
Critically Damped
-
II
V
V
10ms/d;v
10ms/d;v
TL/H111018-11
FIGURE 11. Position vs Time for 100 Count Step Input
961
~
z•
III(
the LM628/629 is programmed to interrupt its host, the
event which caused this interrupt can be determined from
bits 1 to 6 of the Status Byte (additionally bit 0 is the busy bit
and bit 7 indicates that the motor is off). All the Interrupt
Control commands are executable during motion.
Following immediately after the trajectory control word
should be two 16-bit data words for each parameter spepified to be loaded. These should. be in the descending order
of the trajectory control word bits, thatis acceleration, velocity and position. They are written to the L:M628/629 as
two pairs of data bytes in most to least significant byte order. The busy bit should be checked between the command
byte and the data byte pair forming the trajectory control
word and the individual data byte pairs of the data. The Start
command, STT, transfers the loaded trajectory data into the
working. registers of the double buffered scheme to initiate
movement of the motor. This buffering allows any parameter, except acceleration, to be updated while the motor is
moving by loading data with the LTRJ command and to be
later executed by using the STT command.
New values of acceleration can be loaded with LTRJ while
the motor is moving; but cannot be executed by the STT
command until the trajectory has completed or the drive to
the motor is turned off by using bit 8 of the trajectory control
word. If acceleration has been changed and STT is issued
while the drive to the motor is still present, a command error
interrupt will be generated and the command ignored. Separate pairs of LTRJ and STT commands should be issued to
first turn the motor off and then update acceleration. SystElm
oPeration when changing acceleration while the motor is
moving, but with the drive removed, is discussed in Section
4.5.1.
The Mask Interrupts command, MSKI, is used to tell
LM628/629 which of bits 1 to 6 will interrupt the host
through use of interrupt mask data associated with the command. The data is in the form of a data byte pair, bits 1-6 of
the .Ieast significant byte being set to logic 1 when an interrupt source is enabled. The Reset Interrupts command,
RSi'1, resets interrupt bits in the Status Byte by sending a
data byte pair, the least significant byte having logic O. in bit
pOSitions 1 to 6 if they are to be reset.
Executing the Set Index Position command, SIP, causes bit
3 of the status byte to be set when the absolute position of
the next index pulse is recorded in the index register. This
can be read with the command, Read Index Position, RDIP.
Executing either Load Position Error for Interrupt, LPEI, or
Load Position Error for Stopping, LPES, commands, sets bit
5 of the Status Byte when a position error exceeding a
specified limit occurs. An excessive position error can indicate a serious system problem and these two commands
give the option when this occurs of either interrupting the
host or stopping the motor and interrupting the host. The
excessive position is specified following each command by
a data byte pair in most to least significant byte ·order..
Executing either Set Break Point Absolute, SBPA, or Set
Break Point Relative, SBPR, commands, sets bit 6 of the
status byte when either the specified, absolute or relative,
breakpoint respectively is reached. The data for SBPA can
be the full position range (hex'COOOOOOO' to '3FFFFFFF')
and is sent in two data byte pairs in most to least significant
byte order. The data for the Set Breakpoint Relative command is also of two data byte pairs, but its value should be
such that when added to the target position it remains within
the absolute position range. These commands can be used
to signal the moment to update' the on-going trajectory or
filter cOefficients. This is achieved by transferring data from
the primary registers, previously loaded using LTRJ or LFIL,
to working registers, using the STT or UDF commands.
3_4 Loading PID Filter Coefficients
PID filter coefficients are loaded using the Load i:'ilter Parameters, LFIL, command and are the proportional coefficient kp, derivative coefficient kcj and integral coefficient k;.
Associated with kl' an integration limit, ii, has to be loaded.
This constrains the magnitude of the integration term of the
PID filter to the il value, see Section 4.4.2. Associated with
the. derivative coefficient, a derivative sample rate can be
chosen from 2048/fCLK to (2048 X· 256)/fCLK in steps of
2048/fcLK, see Section 4.4.1.
The first pair of data bytes following the LFIL command byte
form the filter control word. The most significant byte sets
the derivative sample rate, the fastest rate, 2048/fCLK, being hex'OO' the slowest rate (2048 X 256)/fCLK being
hex' FF'. the lower four bits of the least significant byte tell
the LM628/629 which of the coefficients is going to be loaded, bit 3 is kp, bit 2 is kj, bit 1 is kcj and bit 0 is iI. Each filter
coefficient and the integration limit can range in value from
hex'OOOO' to '7FFF', positive only. If all coefficient values
are loaded then ten bytes of data, including the filter control
word, will follow the LFIL command. Again the busy bit has
to be checked between the command byte and filter control
word and between data byte pairs. Use of new filter coefficient values by the LM628/629 is initiated by issuing the
single byte Update Filter command, UDF.
Interrupt bits 1, 2 and 4 of the Status Byte are not set by
executing interrupt commands but by events occurring durc
ing LM628/629 operation as follows. Bit 1 is the comlT)and
error interrupt, bit 2 is the trajectory complete interrupt and
bit 4 is the wraparound interrupt. These bits are also
masked and reset by the MSKI and RSi'1 commands respectively. The Status Byte still indicates the condition of
interrupt bits 1-6 when they are masked from interrupting
the host, allowing them to be incorporated in a polling
scheme.
3.6 Data Reporting Commands
Read Status Byte, RDSTAT, supported by a hardware register accessed via CS, RD and PS control, is the most frequently used method of determining LM628/629 status.
This is primarily to read the busy bit 0 while communicating
commands and data as described in Section 3.2.
When controlled movement of the motor has been
achieved, by programming the filter and trajectory, attention
turns to incorporating the LM628/629 into a system. Interrupt Control Commands and Data Reporting Commands enable the host microcontroller to keep track of LM628/629
activity.
There are seven other user commands which can read data
from LM628/629 data registers.
3.5 Interrupt Control Commands
There are five commands that can be used to interrupt the
host microcontroller when a predefined condition occurs
and tWo commands that control interrupt operation. When
962
The Read Signals Register command, RDSIGS, returns a
16-bit data word to the host. The least-significant byte repeats the RDSTAT byte except for bit 0 which indicates that
a SIP command has been executed but that an index pulse
has not occurred. The most significant byte has 6 bits that
indicate set-up conditions (bits 8, 9, 11, 12, 13 and 14). The
other two bits of the RDSIGS data word indicate that the
trajectory generator has completed its function, bit 10, and
that the host interrupt output (Pin 17) has been set to logic
1, bit 15. Full details of the bit assignments of this command
can be found in the data sheet.
The Read Index Position, RDIP, command reads the position recorded in the 32 bits of the index register in four data
bytes. This command, with the SIP command, can be used
to acquire a home position or successive values. These
could be used, for example, for gross error checking.
Read Desired Velocity, RDDV, reads the current desired velocity used to calculate the desired pOSition profile by the
trajectory generator. It is a 32-bit value containing integer
and fractional velocity information. Read Real Velocity,
RDRV, reads the instantaneous actual velocity and is a 16bit integer value.
Read Integration-Term Summation Value, RDSUM, reads
the acCumulated value of the integration term. This is a 16bit value ranging from zero to the current, ii, integration limit
value.
3.7 Software Example
The following example shows the flow of microcontroller
commands needed to get the LM628/629 to control a simple motor move. As it is non-specific to any microcontroller
pseudo commands WR',XXXXH and RD,XXXXH with hex immediate data will be used to indicate read and write operations respectively by the host to and from the LM628/629.
Decisions use.IF.. THEN .. ELSE. BUSY is a user routine to
check the busy bit in the Status Byte, WAIT is a user routine
to wait 1.5 ms after hardware reset.
Both on-going 32-bit position inputs to the summing junction
can be read. Read desired position, RDDP, reads the current desired position the demand or "set point input" from
the trajectory generator and Read Real Position, RDRP,
reads the current actual position of the motor.
LABEL
MNEMONIC
Initialization:
WAIT
RDSTAT
:REMARK
:Routine to wait 1.5 ms aft'er reset.
:Check oorreot RESET operation by reading the
:Status Byt'e. This should be either hex'84' or 'C4'
IF Status byte not equal hex'S4' or 'C4' THEN repeat
hardware RESET
:Make deoision concerning validity of RESET
Optionally the Reset can be further checked for correct operation as follows. It is useful to include this to reset all interrupt bits in
the Status Byte before further action:
'
MSKI
BUSY
WR,OOOOH
:Mask interrupts
:Check busy bit 0 routine
:Host writes two zero bytes of data to
:LM628/629. This mask disables all interrupts.
BUSY
:Check busy bit
RSTI
:Reset Interrupts oommand
:Check busy bit
BUSY
WR,OOOOH
:Host writes two zero bytes of data to LM62S/629
RDSTAT
:Status byte should read either hex'SO' or 'CO'
IF Status byte not equal hex'SO' or 'CO' THEN repeat
hardware RESET
IF Status Byte equal to hex' CO' THEN continue ELSE PORT
BUSY
:Check busy bit
RSTI
:Reset Interrupts
:Cheok busy bit
BUSY
:Reset all interrupt bits
WR,OOOOH
Set Output Port Size for a 12-bit DAC.
PORT
BUSY
:Check busy bit
PORTl2
:Sets LM62S output port to 12-bits
(Only for systems with 12-bit DAC)
,963
Load Filter Parameters
BUSY
LFIL
BUSY
WR,OOOaH
BUSY
WR,0032H
:Cheok busy bit
,:Load Filter Parameters command,
:Check busy bit
:Filter Control Word
Bits a to, 15 (MSB) set the derivative
:sample rate.
Bit ,3
Loading kp data
Bit, 2
Loading kl data
Bit'l
Loading kd data
Bit 0
Loading il data
:Choose to load kp only at maximum
:derivative sample rate then Filter Control
:Word = OOOaH
,:Cheok busy bit
:Choose kp
50, load data byte pair MS
:byte first
=
Update Filter
BUSY
:Cheok busy bit
UDF
Load Xrajectory Parameters
BUSY
:Cheok busy bit
LXRJ
:Load trajectory parameters command.
BUSY
:Check busy bit
WR,002AH
:Load trajeotory control word:
See Xable I
:Choose Positio,n mode, and load absolute
:aooeleration, velooity and 'position. Xhen
:trajectory control word = 002AH. Xhis means
:6 pairs ot data bytes should tollow.
:Cheok busy bit
BUSY
WR,XXXXH
:Load Aooeleration integer word MS byte ti,rst
BUSY
:Cheok busy bit
WR,XXXXH
:Load Aooeleration' traotional word MS byte tirst
BUSY
:Cheok busy bit
WR,XXXXH
:Load Velooity integer word MS byte tirst
:Cheok busy bit
BUSY
WR,XXXXH
:Load Velocity tractional word MS byte tirst
BUSY
:Cheok busy bit
WR,XXXXH
:Load Position MS byte pair tirst
BUSY
:Cheok busy bit
WR,XXXXH
:Load pOSition LS byte pair
Start Motion
:Cheok busy bit
BUSY
STr
:Start command
Check tor Xrajectory complete.
RDSXAX
:Check Status Byte bit 2 tor trajectory
:oomplete
Busy bit check routine
BUSY
RDSXAX
:Read status byte
It bit 0 is set XHEN BUSY ELSE REXURN
END
'ConsuH reference (5) for more Information on programming the LM628/629.
964
INITIALIZE
PORT
WAIT
1.5m.
LOAD
rlLTER
COErrs
HARDWARE
RESET
UPDATE
rlLTER
NO
LOAD
TRAJECTORY
PARAMETERS
ADDITIONAL
RESET
CHECK
START
IoIOTION
NO
YES
TUH/ll018-12
FIGURE 12. Basic Software Flow
965
4.0 HELPFUL USER IDEAS
4.2.2 Position Encoder Interface
The two optical incremental position' encoder outputs feed
into the LM628/629 quadrature depOder TTL inputs A and
B. The leading,phase of ~he quadrllture encoder output dafines the forward direction of the motor and should be can·
nected to input A. Optionally an index pulse may be used
from the pOSition encoder. This is connected to the TN input,
which should be tied high if not used, see Figure 13.
4.1 Oetting Started
This section outlines the aCtions that are neCessary to im·
plement a simple motion Control system using LM628/629.
More details on how LM628/629 works and the use of the
User Command Set are giv~n in the, ~~,ions "2.0 DEVICE
DESCRIPTION" and "3.0 U~I;R COMMAND SET".
4.2 Hardware
4.2.3 Output Interface
'LM628 has a parallel output of either 8 or 12 bits, the latter '
is output as two multiplexed 6·bit words. Figure 14 illustrates
how 8,motor might be driven,using a LM12 power linear
amplifier from the output of 8·bit DAC0800.
LM629 has a sign and magnitude PWM output, Figure 13, of
7·bit resolution plus sign. Figure 15 shows how the LM629
sign and magnitude outputs can be used to control the out·
puts of an LM18293 quad half·H driver. The half·H drivers
are used in pairs, by using 100 mO current sharing resistors,
and form a full·H bridge driver of 2A output. The sign bit is
used to steer the PWM LM629 magnitude output to either
side of the H·bridge lower output transistors while holding
the upper transistors on the opposite side of the H·bridge
continuously on.
The foll~ing hardware connections need to be made:
4.2.1 Host Mlcrocontroller Interface
Interface to the host microcontroller is via an 8·bit com·
mand/data port which is controlleliby four lines. These are
the conventional chip select ~, read RD, write WR and a
line called Port Select J5S, see Figure 13. J5S is used to
select user Command or Data transfer between the
LM628/629 and the host. In the special case of the Status
Byte (RDSTA bringing J5S, ~ and firj low together allows
access to this hardware register at any time. An optional
interrupt ,line, HI, from the LM628/629 to the host can be
used. A microcontroller output line is necessary to control
the LM628/629 hardware reset action. ,
n
./DO-D7
, '8
DAC~DAC7
cs
'8
RD
WD
PS
HOST
INTERFACE
LM628
OUll'UT
LM628/629
PWM MAG
HI
PWM SIGN
,
RST
} LM629
OUTPUT
la IAI~
'---.,.---I
OpnCAL POSmON
ENCODER INTERFACE
TLlH/ll018-13
FIGURE 13. LM628 and LM629 Host, Output and Position Encoder Interfaces
+20V
LW628
DAC0800
'our+ ............- ..
2.Skn
TL/H/ll018-14
FIGURE 14. LM628 Example of
Linear Motor Drive Using LM12
,966
.--------------------------------------------------------------------,~
5V
=F=
V MOTOR
~
LM18293
LM629
MAGNITUDE
1-+----....
"""'L_,
SIGNr-.....
TLlH/ll018-15
FIGURE 15. LM629 H-Brldge Motor Drive Example Using LM18293 .
967
interval Is loaded with the filter coefficient values as the
most significant byte of the LFIL control word everytime the
command is used, the host therefore needs to store the
current value for re-Ioading at times of filter coefficient
change.
4.3 Software
Making LM628/629 perform a motion control function requires that the host microcontroller, after initializing,
LM628/629, loads coefficients for the PID filter and,.then
loads trajectory Information. The interrupt and data reporting commands can then be used by the host ~p keep track
of LM628/629 actions. For detailed, e(n)/256
= Kj x T .'. kj = 65536 Kj x T.
Where T is the sampling interval 2048/fCLK.
For a 12-bit output. the factors are:
kp = 16 x Kp, kd = 16 x ~/Tsandkj = 4096Kj x T.
If the' 32-bit result register overflows into the most significant
16-bits as a result of a calculation, then all the lower bits are
set high to give a predictable saturated output. ,
N
~ a(n)
24 bit. "',_ _....&._ _....._ _.....
"=0
k,
5.3 An' Example of a Trajectory Calculation
R.sult
i;~i~~~~
16 bits ",,_ _....&._ __
r'-----_,--....,!"'""""I"'--.,
.
'---v---'
8-bH output
12-bH output
TL/H/ll018-19
FIGURE 19. Scaling for kl
166,667 COUNTS '-;·~I.'---- 666,667 COUNTS
----.+1.-
r.-------------------i
MAXIMUM VELOCITY
I
: - - - - EQUAL RATES
:
OF ACCELERATION
I
AND DECELERATION
-.~,.--
"
..:
~
:'
I
,0
.
15
166,667 COUNTS
I
./
;
~
I
?
ACCELERATION~
AVERAGE VELOCITY
,
DURING
AND DECELERATION
EQUALS 1/2 MAXIMUM VELOCITY
:--- _.:
I
I
45
30
, STOPPING POSIT/ON
IS INTEGRAL OF
TRAPEZOID AND
EQUALS
500 REVOLUTIONS
(1,000,000 COUNTS)
60
TIME (SECONDS)
TUH/ll018-20
FIGURE 20. Trajectory calculation Example Profile
971
maximum velocity or Ya ,of the total, or 333,333 counts. Acceleration, and deceleration takes 166,667 counts respectively.
6.2.2 Is there any way to change acceleration?
Answer: Acceleration change can be simulated by making
many small changes of maximum velocity. For instance if a
small velocity change is loaded, using LTRJ and
commands, issuing these r,epeatedly at predetermined time intervals will cause the maximum velocity to increment producing a piecewise linear acceleration profile. The actual
acceleration between velocity increments" remains the
same.
sn
The time interval used by the LM628/629 is the sample
interval Which is 256 ,.s for a felK 'of 8 MHz.
The number of'sample periods in 15 seconds = 15s/
206p.S = 56,600 samples
Remembering that distance Ii = at2/2 is traveled due to
acceleration 'a' and time 't'.
"
i'heref~re acceleration a = 2S/t2
=
2
6.3 More on Stop Commands
6.3.1 What happens If the on-going trajectory Is
stopped by setting L TRJ control word bite 9 or 10, stop
abruptly or stop smoothly, and then restarted by IssuIng Start, STT?
"
X 166,667/58,600
'" 97.1 x 10- 6 counts/sample2
Acceleration, and velocity values are' entered into
LM62S/629 as a 32-bit integer double-word but represents
a 16-bit integer plus 16-bit fractional value. To achieve this
acceleration and velocity decimal values are scaled by
65536 and any remaining fractions discarded. This value is
then converted to hex to enter into LM628 in four bytes.
Scaled acceleration a = 97.1 x 10- 6 X 65536
= 6.3'6 decimal = 00000006 hex.
Answer: While stopped the motor position will be held by
the control loop at the position determined as a result of
issuing the stop command. Issuing
will cause the motor
to ,restart the trajectory toward the original target position
with normal controlled acceleration. '
sn
6.3.2 What happens If the' on-golng trajectory Ia
stopped by setting LTRJ control word bit 8, motor-off?
Answer: The LM628's DAC output is set to mid-scale, this
puts zero volts on the motor which will stili have a dynamic
braking effect due to the commutation diodes. The LM629's
PWM output sets the magnitude output to zero with a similar
effect. If the motor freewheels or is moved the desired and
actual positions will be the same. This can be verified using
the RDDP and RDRP commands. When Start,
Is issued the loop will be closed again and the motor will move
toward the original trajectory from the actual current posi"
tion.
The maximum velocity can be ,calculated in two ways, either
by the distance in counts traveled at maximum velocity divided by the number of samples or by the acceleration mUltiplied by the number of samples over acceleration duration,
as follows:
Velocity = 666,667/117,200 = ,97.1 X 10-6 X 58,600
sn,
= 5.69 counts/sample
Scaled by 65536 becomes 372,899.8 decimal = 0005BOA3
hex.
Inputting these values for acceleration and velocity with the
target position of 1,000,000 decimal, 000F4240 hex will
achieve the desired velocity profile.
'
6.3.3 If the motor Ia off, how can the control loop be
cloeed and the motor energized?
, Answer: Simply by issuing the Start,
command. If any
previous trajectory has completed then the motor will be
held in the current position."lf a trajectory was in progress
when the motor-off command was issued then the motor
will restart and move to the target position in position mode,
or resume movement in velocity mode.
sn
6.0 QUESTIONS AND ANSWERS
6.1 The Two Moat Popular Questions
6.1.1 Why doesn't the ,"otor move, I've loaded filter parameters, trajectory parameters and Issued Update Filter, UDF, and Start, STT, commands?
Answer: The most like causfit is that a stop bit (one of bits 8,
9 or 10 of the trajectory control word) has been set in error,
supposedly to cause a stop in position mode. This Is unnecessary, in position mode the trajectory stops automatically
at the target position, see Section 3.3.
6.1.2 can acceleration be changed on the fly?
Answer: No, not directly and a command error interrupt will
be generated when
is issued if acceleration has been
changed. Acceleration can be changed if the motor is
turned off first using bit 8 of the Load Trajectory Parameter,
LTRJ, trajectory control word, see Section 4.6.1.
6.4 More on Define Home
6.4.1 What happens If the Define Home command, DFH,
Is Issued while a current trajectory Is In progress?
Answer: The position where the DFH command is Issued Is
reset to zero, but the motor still stops at the original position
commanded, i.e., the position where DFH is issued is substracted from the original target position.
6.4.2 Does Issuing Define Home, DFH, zero both the trajectory and position register.
Answer: Yes, use Read Real Position, RDRP, and Read Desired Position, RDDP to verify.
sn
6.2.More on Acceleration Change
6.5 More on Velocity
6.2.1 What happens at restart If acceleration Is changed
with the motor drive off and the motor Is stili m~:Vlng?
6.5.1 Why Is a command error Interrupt generated when
Inputting negative valuss of relative velocity?
Answer: The trajectory generation starting position is the
actual position when the
command is iSsUed, but assumes that the motor is stationary. If the motor is mOving
the control loop will attempt to bring the motor back onto an
accelerating profile, producing a large error value and less
than predictable results. The LM628/629 was not designed
with the intention to allow acceleration changes with moving
motors.
Answer: Beceuse the negative relative velocity would cause
a negative absolute velocity which Is not allowed. Negative
absolute values of velocity imply movement in the negative
direction which can be achieved by inputting a negative po-
sn
972
sition v~lue or in velocity mode by not setting bit 12. Similarly negative values of acceleration imply deceleration which
occurs automatically at the acceleration rate when the
LM628/629 stops the motor in position mode or if making a
transition from a higher to a lower value of veloCity.
6.5.2 What happens In velocity (or position) mode when
the position range Is exceeded?
Answer: The position range extends from maximum negative position hex'COOOOOOO' to maximum positive position
hex'3FFFFFFF' using a 32-bit double word. Bit 31 is the
direction bit, logiC 0 indicates forward direction, bit 30 is the
wraparound bit used to control position over-range in velOCity (or position) mode.
6.6.5 What happens if the motor Is not able to keep up
with the specified trajectory acceleration and velocity
values?
Answer: A large, saturated, position error will be generated,
and the control loop will be non-linear. The acceleration and
velocity values should be set within the capability of the
motor. Read Desired and Real Position commands, RDDP
and RDRP can be used to determine the size of the error.
The Load Position Error commands, for either host Interrupt
or motor Stopping, LPEI and LPES, can be used to monitor
the error size for controlled action where safety is a factor.
6.6.6 When is the command error bit 1 In the Status
Byte set?
Answer:
a) When an acceleration change is attempted when the motor is moving and the drive on.
When the position increases past hex'3FFFFFFF' the wraparound bit 30 is set, which also sets the wraparound bit in
the Status byte bit 4. This can be polled by the host or
optionally used to interrupt the host as defined by the MSKI
commands. Essentially the host has to manage wraparound
by noting its occurrence and resetting the Status byte wraparound bit using the RSTI command. When the wraparound
bit 30 is set in the position register, so is the direction bit.
This means one count past maximum pOSitive position
hex'3FFFFFFF' moves the position register onto the maximum negative position hex',COOOOOOO'. Continued increase ,
in positive direction causes the position register to count up
to zero and back to positive values of position and on
toward another wraparound.
Similarly when traveling in a negative direction, using two's
complement ,arithmetic, position counts range from
hex'FFFFFFF' (-1 decimal),to the maximum negative posi~
tion of hex'COOOOOOO'. One more ,negative count causes
the pOSition register to change to hex'3FFFFFFF', the maximum positive position. This time the wraparound bit 30 is
reset, causing ,he wraparound bit, 4 of the status byte to be
set. Also the direction bit 31 is reset to zero. Further counts
in the negative direction cause the position register to count
down to zero as would be expected. With management
there is no reason why absolute position should be lost,
even when changing between velocity and position modes.
b) When loading a relative velocity would cause a negative
absolute velOCity.
c) Incorrect reading and w~ting operations g\lnerally.
6.6.7 What does the trajectory complete bit 2 In the
Status Byte Indicate?
Answer: That the trajectory loaded by LTRJ and initiated by
has completed. The motor mayor may not be at this
position. Bit 2 is also set when the, motor stop commands
are executed and completed.
6.6.S What do the specified minimum and maximum val·
ues of velocity mean In reality?
sn
Answer: Assume a 500 line encoder = 1/2000 revs/count
is used.
The maximum LM628/6~9 velocity is 16383 counts/sample
and for a 8 MHz clock the LM628/629 sample rate is 3.9k
samples/second, multiplying these values gives 32k revs/
second or 1.92M rpm.
'
The maximum encoder rate is 1M counts/second multiplied
by 1/2000 revs/count gives 500'revs/second or 30k rpm.
The encoder capture rate therefore sets the maximum velocitylimit.
The minimum LM628/629 velocity is 1/65536 counts/sample (one fractional count), multiplying this value by the sample rate and encoder revs/count gives 30, x 10-6 revs/
second or 1.8 X 10- 3 rpm.
6.6 More on Use of Commands
6.6.1 If filter parameter and trajectory commands are
plpellned for synchronization of axes, can the Update
Filter, I,.IDF, and Start, STT, commands be Issued consecutively? ,
The LM628 provides no limitation to practical values of velocity.
Answer: Yes.
6.6.2 Can commands be Issued between another command and Its data?
6.6.9 How long will It take to get to position wraparound
In velocity mode traveling at 6000 rpm with a 500 line
encoder?
Answer: 107 minutes.
Answer: No.,
6.6.3 What Is the response time of the set breakpoint
commands, SBPA and SBPR?
"
7.0 REFERENCES AND FURTHER READING
1. ,LM628/LM629 Precision Motion Controller. Data sheet
March 1989.
2. Automatic Control Systems. Benjamin C. Kuo. Fifth edition Prentice-Hall 1987.
Answer: There is an uncertainty of one sample interval in
the setting of the breakpoint bit 6 in the Status Byte in response to these commands.
6.6.4 What happens when the Set Index POSition, SIP,
command Is Issued?
3. DC Motors, Speed Controls, Servo Systems. Robbins &
Myers/Electro Craft.
Answer: On the next occurrence of all three inputs from the
position encoder being low the corresponding position is
loaded into the index register. This can be read with the
Read Index Position command, RDIP. Bit 0 of the Read Signals register, shows when an SIP command has been issued but the index position has not yet been acquired.
RDSIGS command accesses the Read Signals Register.
4. PID Algorithms and their Computer Implementation. D.W.
Clarke. Institute of Measurement and Control, Trans. v. 6
No.6 Oct/Dec 1984 86/178.
5. LM628 Programming Guide. Steven Hunt. National Semiconductor Application Note AN-693.
973
CONT,ENTS
,;"1
• Introduction
• Princ;iple of Operation'
• Architecture
• AnalySis
•
•
•
•
,
0', '
Deslgn
Inductor Design
Transistor and Diode Selection
Capacitor Selection
• EMI
• Design Equations
INTRODUCTION
In modem electronic systems, voltage regulation is a basic
function required by: the system for optimal performance. ,
The regulator provides a constant output voltage irrespective of changes in line voltage, load requirements, or ambi·
ent temperature.
For years, mo'nolithic regulators have simplified power·'SIIp-'
ply design by reducing design complexity, improving reliability, and increasing the ease 'of maintenance, In the past,
monolithic regulator systems have been dominated,by linear
regulators because of relatively,101N cost, 10w,e1(ternal component count, excellent performance, and high reliability...
Ho~er, limitations,to applicability and performance of linear regulators can' force tI'Ie user to other more, complex
regulator,iysterns, s,",ch ~ the switching regulator.
BeCause of improve~ents in components made ~Specially
for them, switchlng·regulated power supplies have prolifer·
ated during t~e past few years. The emergence of inexpen-
.:'
sive, high-speed switching, po~er traflsi~tors" 10w~loss ferrites for inductOr cores, and low-cost I.SI circuits containing
all neCesSarY COntrol circuitry has significantly expanc;led the
range 'Of switching regulator application.
'
This application note desoribes a new integrated subsystem ' '
that contains the control circuitry, as well as the switching
elements, required for constructing s\yitc,hing, regulator s~
tems (Figur9 1). The principle of operatil)n is discussed, a
complete system descrip\iqn"provided!,lInd thE! analysis and
design of the basic confjgur,ations developed. Additional information concerning selection of external switching elements and 'd~gn 9f the inductor is provided.
PRINCIPLE OF OPERATION
A D.C. power s~pply is usually regulated by same type of
feedback circuit that sens,es any, change in the D.C. output
and develops a coritrql slgn~I, to ,Compensate for thl~
change.' This feedback m81ntains an essentially constant
output.
'
,
" " , , ",'
"
In a monolithic regulator, the output voltage iSSl\mpledand
a high-gain di.fferential amplifier compares a portion of this ,
voltage with reference voltage. ,The output of the an:.plifier'
is then used to modulate the Control element, a transistor,
by varying its operating pOint within tlie linear regic;>n or be- ,
tween the two operating extremes, cutoff' and saturation.
When, the pass tran"istor Is operated at a poiht between
cutoff 'and saturation, the regulator circuit is referred to as
lif198/" voltage rEigulatot. Whjjn, the pass transistOr 'is operate
ed only at cutoff or at saturation, the circuit is referred t9 as
a switching regulator.
'
"
Linear System
a
Swttchlng System
INPUT
OUTPUT
TUHill040-1
, FIGURE 1. Regl,llator System Block Diagrams
""."
974,
Besides high efficiency operation, another advantage of the
switching regulator is increased application flexibility offered
by output voltages that are less than, greater than, or of
opposite polarity to the input voltage. Figure 2 illustrates
these three basic operating modes.
One advantage of the switching regulator over the more
conventional linear regulator is greater efficiency, since cutoff and saturation modes are the two most efficient modes
of operation. In the cutoff mode, there is a large voltage
across the transistor but little current through it; in the saturation mode, the transistor has little voltage across it but a
large amount of current. In either case, little power is wasted, most of the input power is transferred to the output, and
efficiency. is high. Regulation is achieved by varying the duty
cycle that controls the average current transferred to the
load. As long as this average current is equal to the current
required by the load, regulation is maintained.
ARCHITECTURE
Each of the fundamental operating modes is built from the
same set of functional blocks (Figure 3). Additional functions are required for control and protection, but again,
these functional blocks are common to each of the operational modes. The different modes are obtained by proper
arrangement of these basic blocks.
Step-Down Configuration
IL
VIN
A O--Of""oOo-_..nrYY"\
_ _-o VOUT
+ SI L
01
+
TLlH/ll040-3
Step-Up Configuration
Inverting Configuration
01
VIN
-
lOUT
O--Of""ooo-_--lI4o-_--o VOUT
+ SI -
TLlH/ll040-4
TLlH/ll040-5
FIGURE 2. Basic Operating Modes
COMPARATOR
NON-INVERTING
INPUT
p---
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
9
COMPARATOR
INVERTING
TIMING
INPUT
CAPACITOR
__
IpK
SENSE
____ E ___ _
_l~cc
10
DRIVER
COLLECTOR
GROUND
13 BIAS
5
4
REFERENCE OP AMP
OP AMP
OP AMP
VOLTAGE INVERTING NON-INVERTING SUPPLY
INPUT
INPUT
OP AMP
OUTPUT
975
16
---H-
SWITCH
EIlITTER
FIGURE 3. Functional Block Diagram
SWITCH
COLLECTOR
DIODE
ANODE
DIODE
CATHODE
TLlH/11040-6
..
,... r------------------------------------------------------------------------------------------,
r;-
~
For maximum design flexibility and minimum external part
count, the LM78540 .was designed to include all of the fundamental building blocks in an uncommitted arrangement.
This provides for a simple, cost-effective design· of any
switching regulator mode.
ground as part of the common-mode range. This amplifier
may be connected to provide series pass regulation or, a
second output voltage, or configured· to provide special
functions for some ·of the more advanced applications.
The switching regulator can be 'operated over a Widinange
of power conditions, from batter)' power to high-voltage,
high-current supplies. Low voltage operation down to 2.4V
and low standby current, less than 2.5 rnA at'5V, make it
ideal for battery-powered systems. On the other end, highvoltage capability, up to 4OV, and high-current capability, up
to 1.5A ·peak current, offer an operating range unmatched
by other switching systems.
The functional blocks of the regulator, illustrated in AglIF8 3,
are:
-
Currert-controlled oscillator
Temperature-compensated current-limiting circuit
Temperature-compensated voltage reference
-
High-gain differential comparator
Power switching circuit
ANALYSIS-STEP-DOWN OPERATION
Figure 2 illustrates the basic configuration for a step-down
- High-gain amplifier
The current-controlled oscillator generates the gating signals used to control the on/off condition of the transistor
power switch. The oscillator frequency is set by a single
external capacitor and may be varied over a range of'
100 Hz to 100 kHz. Most applications require an oscillator
frequency from 20 kHz to 30 kHz. The oscillator duty cycle
(ton/totl) is internally fixed at 6: 1, but may be modified by the
current-limiting circuit.
switching voltage regulator system. The waveforms for this
system are shown in AguF8 4.
Assume, for analysis, that the following condition is true:
before the switch is turned on,
il = 0
When switch 51 is closed, the voltage at point A becomes:
VA = VIN - VSAT
where VSAT is the saturation voltage of the switch.
At this time, the diode is reverse biased and the current
through the inductor il is increasing at a rate equal to:
The temperature-compensated, current-limiting circuitry
senses the switching transistor current across an extemal
resistor and may modify the oscillator on-time, which in tum
limits the peak current. This provides protection for the
switching transistor and power diode. The nominal activation voltage is 300 mV, and the peak current can be programmed by a single resistor Rse.
~ = Vl = VIN - VSAT - VOUT
dt
L
L
The current through the inductor continues to increase at
this rate as long as the switch is closed and the inductor
does not saturate. Assuming that the output voltage over a
full cycle does not change significantly, this rate may be
considered to be constant, and the current through the inductor at any instant, while the switch is closed, is given by:
A 1.3V temperature-compensated, band-gap voltage source
provides a, stable reference to which the sampled portion of
the output is compared. The reference is capable of providing up to 10 mA .of current without an external pass transis-
tor.
'"
A high-gain differential comparator with a common-mode
input range extending from ground to 1.5V less than Vee is
used to inhibit the basic gating s'gnal generated by the oscillator tuming on the transistor switch when the output voltagE! is too high.
The transistor switch, in a Darlington configuration with the
collectors and emitter brought out externally for maximum
design flexibility, is capable of handling up to 1.5A peak current and up to 40V collector-emitter voltage. The power
Switching diode is rated for the same current and Voltage
capabilities as the transistor switch; both have switching
'
times that are normally 300 ns-500 ns.
Although not required by the basic operating modes, an In- '
dependent operational amplifier has. been included to increase flexibility. The characteristics of this amplifier are
similar to the LM741 , except that a power output stage has
been provided, capable .01' sourcing up to 150 mA and sinking 35 mAo The input has also been modified to include
il = (VIN -
VS~T -
VOUT) t
The peak current through the inductor, which is dependent
on the on-time ton of 51, is given by:
IPk = (VIN -
VS~T -
VOUT) ton
At the end of the on-time, switch 51 is opened. 5ince the
inductor ,current cannot 'change instantaneously, it generates a voltage that forward ,biases diode D1, providing a
current path for the inductor Gurrent. The voltage at point A
is now:
VA' = -Vo
where Vo is the forward voltage of the:, diode.
The current through the inductor now begins to decay at a
rate equal ~o:
dil
dt
976
= Vl =
L
_ (Vo
.
+ VOUT)
L
.--------------------------------------------------------------------,~
~
........
Ie
+IpK/2~
~
~
-lpK/2~
l- --7"\.. /".. /"..
rv:-_-_-_~~_--_"'\.:.T-___--_--_"'\.:.T-___--_--_,-_V_O_UT
VOur+VPK
VOUT VOUrVpK ...
TL/H/1104O-7
FIGURE 4. Waveforms for Step-Down Mode
The current through the inductor at any instant, while the
switch is open, is given by:
The ripple voltage will be increased by the product of the
output capacitor's equivalent series resistance (ESR) and ie
(though the two ripple terms do not directly add). Using
large-value, low-ESR capacitors will minimize the ripple voltage, so the previous analysis will remain valid.
iL = Ipk - (VO +LVOUT ) t
Assuming that the current through the inductor reaches zero
after the time interval toff, then:
I - (Vo
pk-
To calculate the efficiency of the system, n:
n = POUT
PIN
The input power is given by:
+LVOUT) t off
which results in the following relationship between ton and
PIN = IINVIN
The average input current can be calculated from the is
waveform of Figure 4:
loft:
ton =
VOUT + Vo
toff
VIN - VSAT - VOUT
In the above analySiS, a number of assumptions were made.
For the average output voltage to remain constant, the net
charge delivered to the output capacitor must be zero. Figure 4 (iL waveform) shows that:
(~) ton + (~) toff =
lOUT (ton
IIN(avg)
POUT = lOUT VOUT
Combining the above equations gives an expression for efficiency:
+ loft),
VOUT
) (VIN - VSAT + Vo)
VOUT + Vo
VIN
As the forward drops in the diode and switch decrease, the
efficiency of the system is improved. With variations in input
voltage, the efficiency remains relatively constant.
n = (
It was also assumed that the change (ripple) in the output
voltage was small in comparison to the output voltage. The
ripple voltage can be calculated from a knowledge of
switching times, peak current and output capacitor size. Agure 4 (ie waveform) shows that:
-
Co
1
Y2
(!.e!!
!.e!!) =
ton 4 + toff 4
Co
(ton)
ton + toff
The output power is given by:
or Ipk = 2 lOUT
For the average output voltage to remain constant, the average currljlnt through the inductor must equal the output current.
Vp p = .1Q =
ton(~)
= ton + toff = lOUT
IPk (ton/toff)
BCO
977
The above calculation for efficiency did not take into account quiescent power dissipation, which decreases efficiency at low current levels when the average input current
is of the same magnitude as the quiescent current. It also
did not take into account switching losses in the switch and
diode or losses in the inductor that tend to reduce efficiency. It does, however, give a good approximation for efficiency, providing a close match with what is measured for the
system.
The current through the inductor continues to increase at
this rate as long as the switch remains closed and the in·
ductor does not saturate. This rate will be constant if the
input voltage remains constant during the on·time of the
switch, and the current through the inductor at any instant,
while the switch is closed, is given by:
iL = (VIN -LVSAT) t
The peak current through the inductor, which is dependent
on the on·time Ion of 81, is given by:
ANALYSIS-STEP-UP OPERATION
Figure 2 illustrates the basic configuration for step-up
IpK = (VIN -L VSAT) Ion
switching voltage regulator system. The waveforms for this
system are shown in Figure 5.
To analyze, first assume that just prior to closing 81:
At the end of the on·time, switch 81 is opened. The inductor
generates a voltage that forward biases diode 01, providing
a current path for the inductor current. The voltage at pOint
Ais now:
iL = 0
When switch 81 is closed, the voltage at point A, which is
also the voltage across the switch, is:
VA = VOUT + Vo
The current through the inductor now begins to decay at a
rate equal to:
VA = VSAT
where VSAT is the saturation voltage of the switch.
At this time, the diode is reverse biased and the current
through the inductor iL is increasing at a rate equal to:
diL
dt
= VL = VIN L
diL
dt
VSAT
= VL = _ VOUT + Vo L
VIN
L
The current through the inductor and diode at any instant,
while the switch is open, is given by:
L
.
I
(VOUT
IL= pk -
+ LVo -
VIN) t
TL/H/11040-8
FIGURE 5. Waveforms for Step-Up Mode
978
.
Assuming that the current through the inductor reaches zero
after the time interval toll, then:
I - (VOUT
pk-
+L
Vo -
As the forward drops in the diode and switch are reduced,
the efficiency of the system improves.
The above calculation did not take into account quiescent
power dissipation or switching losses, which will reduce efficiency from the calculated value; it does, however, give a
good approximation for efficiency.
'
VIN)
toll
Thus, the relationship between ton and toll is given by:
ton = VOUT + Vo - VIN
toll
VIN - VSAT
ANALYSIS-INVERTING OPERATION
F/{Juf8 2 illustrates the basic configuration for an inverting
The above analysis assumes that the output voltage remains relatively constant. For the average output voltage to
remain constant, the net charge delivered to the output capacitor must be zero. Figuf8 5 (io waveform) shows that:
regulator system. The waveforms for this system are shown
in Figure 6.
To analyze, assume that the following condition is true just
prior to turning on the switch:
(~ ) toll = (ton + toff) lOUT
iL = 0
When switch S1 is closed, the voltage at pOint A is:
I - 2I
(VOUT + Vo - VSAT)
orpkOUT
V
V
IN - SAT
Also for the average output voltage to remain constant,. the
average current through the diode must equal the output
current. The ripple voltage can be calculated using F/{Juf8 5
(io waveform) where:
t1 =
VA = VIN - VSAT
where VSAT is the saturation voltage of the switch. At this
time, diode D1 is reverse biased and the current through the
.
inductor increases at a rate equal to:
diL
toff - C~UT) toff
CoCo
+ lOUT) t1
_ IOUTt1
2
Co
which simplifies to:
V
p.p
= (Ipk - IOUT)2
21pk
VIN - VSAT
L
The current through the inductor continues to increase at
this rate as long as the switch is closed and the inductor
does not saturate. This rate is constant if the input voltage
remains constant during the on-time of the switch, and the
current through the inductor at any instant, while the switch
is closed, is given by:
pk
.'
During time interval t1, the output capacitor Co ch~ges
from its minimum value to its maximum value. Therefore:
Vp_p = AQ =..2... (lpI!
VL
d1=T=
iL= (VIN -LVSAT)t
(toff)
Co
The peak current through the inductor, which is dependent
on the on-time ton of S1 is given by:
As with the step-down regulator, this ripple voltage will be
increased by the product of the output capacitor's ESR and
the ripple current through the capaCitor.
I
pk
To calculate the efficiency of the system:
= (VIN - VSAT)
L
ton
n = POUT
PIN
The input power is given by:
At the end of the on-time, switch S1 is opened and the
inductor generates a voltage that forward biases D1, providing a current path for the inductor current. The voltage at
point A is now:
PIN = IINVIN
The average input current can be calculated from the iL
waveform of F/{Jure 5:
VA = VOUT - Vo
The current through the inductor now begins to decay at a
rate equal tei:'
IIN(avg) =
~
diL = VL = _ (Vo - VOUT)
dt
L
L
The current through the inductor and diode at any given
instant, while the switch is open, is given by:
The output power is given by:
POUT = IOUTVOUT
Combining and simplifying the above equations gives an expression for efficiency:
iL = Ipk - (Vo -LVOUT ) t
VOUT
)
n - VIN - VSAT (
VIN
VOUT + Vo - VSAT
979
........
~
~
r-------------------------------------------------------------------------------------,
Assuming that the current through the inductor reaches zero
after a time interval 1:011. then:
','
Vp_p
COCo
which simplifies to:
, _ (Vo - VOUT) , "
Ipk -, ' L
toll,
Analysis shows the relationsl'lip between ton and
ton
V
1:011 to be:
, , (VIN
orlpk = 2 lOUT
2
_ IOUTt1
Co
toll X (lpk - IOUT)2
Co
"
21pk
This ripple voltage will be increased by the product of the
output capacitor's E$R and ttle ripple current through the
capacitor.
1:011 VIN- VSAT
The previous analysi$ assumes that the output voltage remains relatively constant. For the average output voltage to
remain constant, the net charge delivered to the output capacitor must be zero. 'Fl9ure 6 (io waveform) shQWS that: '
(ton
=
POp
= Vo - VOUT
(~ ) toff =
= aQ =....!..: (Ipk + lOUT) t1
To calculate the ef(iciency of the system:
n= POUT = IOUTVOUT
PIN
IINVIN
Average input current can be calculated from Figure 6 (is
waveform):
~ toll) lOUT
+'V
Vo -
IIN(a~) = ~ (ton t~n 1:011)
VOUT - VSAT)
V
IN - SAT
For averaQe output voltage to refllain constant,th.e average
current through the diode' must equal the output current.
The ripple voltage can be calculated using Figure 6 (io
waveform):
Combining and simplifying the previous equations gives 'an
expression for the system efficiency:
n = VIN - VSAT (
IVourl
)"
VIN
Vo + IVOUTI
Again, as the forward drops in the diode and switch are
reduced, the efficiency of the system improves. Also, since
switching losses and quiescent current power dissipation
are not included in the calculations, efficiency will be'somewhat lower than predicted by the above equation.
lOUT)
1:011- ( -,
- 1:011
,
Ipk
Duril)g time interval t1, tile output capacitor Co charges
from its most positive value to ,its most negative value;
therefore:
'
""
t1 =
VIN-VOUT+VD~-
_______________________________________
__
VS1~
V~~~
TLlH/11040-9
FIGURE 6. Voltage Inverter Wavetonna
980
Rse
VIN ____- .__________~~~~~----~------------------~~rT~----~
SV
0.311
17011
Vee
BIAS
Dl
Rl
•--------------------------...J,>M~----------_+------------+--_+ ',SV
VOUT
2Sk
R2
1.3k
Co
I
IOOI'F
TL/H/11040-10
FIGURE 7. Step-Up Voltage Regulator
comparison to the total period (ton + toft) SO that only a
small portion of the total time is spent in the linear mode of
operation, where losses are high. This can be achieved if
both ton and toft are made greater than or equal to 10 ","S.
The second constraint is due to the techniques used to reduce the effects of the switching mode of operation on external systems. Filtering requirements can be made less
stringent by maintaining a high switching frequency, i.e.,
above 15 or 20 kHz. This condition can be met by specifying
the total period, ton + toft, to be less than 50 ","S.
Therefore, the two design constraints are:
DESIGN-STEP-UP REGULATOR
A schematic of the basic step-up regulator is shown in Figure 7.
Conditions:
VIN = 5V
lOUT = 150mA
VOUT = 15V
Calculations:
VRIPPLE s; 1%
VOUT + Vo - VSAT)
'pk = 2 IOUT(max) (
V
V
IN -
I
pk
SAT
= 2(015) (15 + 1.25 - 0.45) :::: 1 A
•
5 - 0.45
ton ~ 10 "'"s; toft ~ 10 "'"s
(ton + toff) S; 50 "'"S
Therefore:
In some cases, both constraints cannot be met and some
trade-ofts will be necessary.
Following these constraints, value is selected for toff:
0.3
Rsc = - - :::: 0.30
'Pk
To calculate the ratio of ton/toft:
ton =
toft
toft = 10 ","S
It is now' possible to calculate values for the timing capacitor
~ and the inductor L.
The timing capacitor is related (by design) to the off-time by
the equation:
~ = (45 x 10- 5) toff
~ = (45 x 10- 5) 10- 5 = 4500 pF
VOUT+VO-VIN= 15+1.25-5:::: 1•9
VIN - VSAT
5 - 0.45
ton = 1.9 toft
At this point, a value is selected for toft, which in turn defines
ton. In making the selection, two constraints must be conSidered. The first constraint comes from efforts to maintain
high efficiency. Rise and fall times should be kept small in
Therefore, set CT = 5000 pF, which results in:
toff ::::
981
11
"'"S and ton :::: 21 "'"S
-~"_'"
'
r-------------------------------------------------------------------------------------~
R~ =
For the inductor
"",
. ,'(VOUT +VO"'" VIN)
L = toll
.
L = (11 x 10-6)
C
5 +
Select R2 = 1.3 kO and make R1 a 25 kO pot that can be
used for adjustments in the output voltage.
IPk
"~25 -
(15 X 103) 1.3 = 1.3 kO
' ... "
. 1.5, .
.
5) :::: 96 p.H
Note.: Sampling current as low as 100 p.A can be used without affecting the perfo~mance of t,he system.
R3 is, s$lected to provi!le enough base drive for transistor
01. Assume a forced {J of 20:
The inductor may be designed, using the equations in Appendix A, or purchased.· An inductor such as a. Delevan
3443-48, rated at 100 p.H, is cloSe enough in value for this
application.
, !e!!
1
IC2 :::: IB1 = {J = 20 = 5Q mA
The output capacitor Co value can be calculated using the
ripple requirement specified:
Co ~ Ipk (ton + toft)
,
8VRIPPLE
Let RS,=
I"_~ (1) (21 + 11) 10- 6 ~ 26.6 F
"V
(8) (150 X 10-3),
p.
R3,:::: VIN - 1.3 = 10 - 1:.3 = 1740
. ·Is
0.05..
1700.
.
Using 01 and. 02 with the external' resistor R3 makes it
possible to re!luce the .total pOVI/er dissipation and improve
the efficiency of this system over a system using 01 and 02
tied together as the control element. Each application
should be checkEld to' see ,which configuration yields the
best pertormance.
An optional capaCitor can be placed at the input to reduce
transients that may be fed back to the main supply. The
capacitor value is normally in the range ',of 100 p.F to
500 p.F, bypassed by a 0.Q1 p.F capacitor.
Select Co to be:
Co
=100 p.F
to allow for the additional ripple voltage caused by the ESR
of the capacitor.
. ,
The sampling network, Ri andR2, can be calculated as
follows. Assume the sampling. network current is 1 . rnA.
Then:
R1+R2=15kO
Applications with peak operating currents greater than 1.5A
or higher than 40V require an external transistor and diode
as shown in Figure 8. This circuit assumes a t5V input and a
70Voutput.
R2 = (R1 + R2) (VREF)
VOUT
RSC
,L
VIN ____- .______~__~~~~~----~------------------~~rr~~--~
.1SV
.0.03n
170 pH
CT
Mq
R4
27n
. BIAS
. r*l'.
---1----tR1
t-________~____________~~-------------------10-0-n--+_--------~~. .--~VOUT
687k
R2
13k
Co
I
70V
1200pF
TL/H/11040-11
FIGURE 8. Switching Regulator with 15V Input, 70V Output
982
r--------------------------------------------------------------------.~
DESIGN-STEP-DOWN REGULATOR
ton =
VOUT + Vo
toff
VIN - VSAT - VOUT
Figure 9.
Conditions:
VIN = 25V
IOUT(max) = 500 mA
VOUT = 10V
VRIPPLE
ton =
10 + 1.25 _ 0
toll
25-1.1-10- .8
< 1%
ton = 0.8 toff
Following design constraints previously discussed, a value
is selected for !off:
Calculations:
Ipk = 2 IOUT(max)
IPk = 2 (0.5) = 1A
toll = 22 p's
Therefore:
Rse
.'
Z
....,
.....
.....
Next, calculate the ratio of ton to toll:
A schematic of the basic step-down regulator is shown in
0.33
=-
IPk
ton = 18.6 p.s
Then calculate ~ and L:
= 0.330
~ = (45 x 10- 5) toll
CT = (45 x 10- 5) (22 x 10-6) ::::: 0.1 p.F
Rse
-+__________~.-~~~----~------------------~----_,
VIN ____
25V
0.311
Vee
BIAS
01
+ ____........ryyT"_......
L-____
Rl
15k
R2
1.3k
Co
Vour
10V
248 pH
I
100pF
TLlH/ll040-12
FIGURE 9. Step-Down Voltage Regulator
983
-z_
.....
r-------------------------------------------------------------------------------------~
Assuming that the sampling network current is 1 mA;then:',
Rt + R2 =10kG
L= (Vour: + VO) toft
Ipk
c(
L=
10
+1 1.25,(22
_
6"
X 10- ) = 248,...H
R2 = (R1
+ R2) VVREF
= 1.3 kG
OUT
Output capacitor Co
mems:
ca.n be c,lculated from ripple require-
Select R2 = 1.3 kG and make R1 a 15 kG pot that can be
used for adjustments in output voltage.
-
+
Co ~ Ipk (ton
toft)
8VRIPPLE
(1) (18.6 + 22) 10 - 6 = 50,...F
(8)(0.1)
Co .,
If Ipk ., 300 mA, during the off-time when the diode'is forward biased, the negative voltage generated at pi!,) 1 causes
a parasitic transistor to turn on, dissipating IIxcess power.
Replacing the internal diode with ari external diode eiiminates this condition and allows normal operation.
Select Co to be:
Co =
For applications with peak currents greater than 1A or voltages greater than 40V, an external transistor and diode are
required, as shown in Figure 10, which assumes a 30V input
and a 5V output at 5A.
100!:'-F
Rse
..........;--...----""
----......;~~-M,.....--
V,N - -.....
30V
Vee
BIAS
L
100pH
--- ---- ---~-
•____---------~~-------_+--------~~...
Rl
-_..VOUT
, 5V
50k
R2
13k
Co 12600PF-
TLlH/ll040-13
FIGURE 10. Modified Step-Down Regulator with SA, SV Output
984
DESIGN-INVERTING REGULATOR
Following design constraints. a value is selected for toft:
A schematic of the basic inverting regulator is shown in Figure 11.
Now. calculate
ton =
Or =
Conditions:
YIN = 12Y
10UT(max) = 500 mA
I
pk =
"'S
(45 x 10- 5) ton
CT = (45
VRIPPLE ~ 1%
VOUT = -15V
Calculations:
10
Or and L:
x 10- 5) 10- 5 = 4500 pF
Setting CT = 5000 pF makes toll :=:: 11
22,..s.
2I
(VIN + Vo - VOUT - VSAT)
OUT(max).
VIN - VSAT
L = (Vo - VOUT)
"'S and ton
:=::
ton
IPk
For 2N6051 VSAT ~ 2V
1.25 + 15)
L= (
(llX10- 6):=::70",H
2.57
The output capacitor Co again is calculated:
= 2(05) (12 + 1.25 + 15 - 2») "" 257
pk·
12 - 2
.
I
(Ipk - 10)2 ton
Co ~ ~-"---=-="'-
Therefore:
.
0.3
Rsc = -:=:: 0.10
Co ~
Ipk
Calculating the ratio of ton to toft.
2 IPk X VRIPPLE
(2.57 - 0.5)2 (11 X 10-6) = 97 F
(2) (2.57) (0.1)
'"
Co is selected to be 200 ",F,
ton = Vo - VOUT
toll
VIN - VSAT
ton = 1.25+15:=::2
toft
10 - 2
ton = 2 toll
R4
RSC
0.13n
p---
1
1
1
1
1
1
·1.
1
1
1
1
1
1
1
1
loon
720n
Vee
BIAS
D2
lN4003
---r1-
._-RI
1.3k
R2
L-____________________________________~r_----~~~------~_.---+VOUT
25k
-15V
TLIH/11040-14
FIGURE 11. Inverting Regulator
985
~
....
~
i
r---------------------------------------------------------------------------------------~_,
The sampling network, R1 allP R2, can easily be ca,lculated .
Assuming the sampling network c;:urrent Is is 1 mA:
R1
Combining Equations 1 and 2 and multiplying by 12 gives:'
(3)
Ll2 = (NI)2 (AL X 10-6) (millijoules)
VREF
=- = 1.3'kn
Any specifiC core has a maximum ampere-turn NI capability
limited by magnetic saturation of the core material •. The
maximum Ll 2SAT Qf the core can then be calculated from
Equation 3 or, if the saturation flux density BSAT is given,
from Equation 4:
Is
R2 = -VOUT = 15kn
Is
Set R1 = 1.3 kn and use a 25 kn pot for R2 so that output
voltage can be adjusted.
. Ll2 = (BSAT)2 (~: X 10- 4) (millijoules)
This application requires an external diode and transistor
since the substrate of the regulator is referenced to ground
and a negative voltage is present on the output. The external diode and transistor prevent the substrate diodes from a
forward-biased condition. See Appendix B for selection of
the diode and transistor.
The core selected for an application must have an Ll 2SAT
value greater than calculated to insure that the core· does
not saturate under maximum peak current conditions.
In switching regulator applications, power dissipation in the
inductor is almost entirely due to D.C. losses in the winding.
The dc resistance of the winding Rw can be calculated from
Equation 5:
R3 is provided for quick turn-off on the external transistor
and is usually in the range of 100n to 3000.. R4 can be
calculated as follQws:
Rw = P(f w/Aw) N
Ipk/ ,8
P
where:
= resistivity of wire (01cm)
f w = length of turn (cm)
Aw = effective area of wire (cm2)
VT = threshold voltage = 300 mV
VeE = base emitter drop across the external transistor
,8 :::::
(5)
where
R - VIN - VSAT - VT - VeE
4 -
(4)
Core geometry provides a certain window area Ae for the
winding. The effective area A' e is 0.5 Ac for toroids and
0.65 Ae for pot cores. Equation 6 relates the number of
turns, area of wire, and effective window area of a fully
wound core.
y.. hFE of the external transistor
If the 2N6051 is used, the value for R4 is:
R = .12 :- 1.3 - 0.3 - 0.7 ~ 7200.
4
(2.57/190)
Aw = A' elN (cm2)
Again, an optional capaCitor can be placed at the input to
reduce transients.
(6)
By combining Equations 5 and 6 and multiplying each side
by 12, the power dissipation in the winding Pw can be calculated:
APPENDIX A
ANALYSIS AND DESIGN OF THE INDUCTOR
Pw = 12Rw = 12P
To select the proper core for a specific application, two factors must be considered.
(!':)
N2
(7)
Substituting for N and rearranging:
The core must provide the desired. inductance without saturating magnetically at the maximum peak current. In this
respect, each core has a specific energy storage capability
Ll2SAT·
The window area for the core winding must permit the number of turns necessary to obtain the required inductance
with a wire size that has acceptable D.C. losses in the winding at maximum peak current. Each core has a specific dissipation capability Ll2 that will result in a specific power loss
or temperature rise. This temperature rise plus the ambient
temperature must not exceed the Curie temperature of the
core.
Ll2 = Pw (
~L::) X 10- 6 (millijoules)
(8)
Equation 8 shows that the Ll2 capability is directly related to
and limited by the maximum permissible power diSsipation.
One procedure for designing the inductor is as follows:
1. Calculate the inductance L and the peak current Ipk for
the application. The required energy storage capability of
the inductor LlPk2 can now be defined.
2. Next. from Equation 3 or. 4, calculate the maximum
Ll 2sAT capability of the selected core, where
Ll 2SAT >'Llp~
The design of any magnetic circuit is based on certain equations for formulae. Equation 1 defines the value of inductance L in terms of basic core parameters and the total
number of tums N wound on the core:
L = N2 X 0.41T p.Ae f eX 10- 5
(1)
3. From Equation 1, calculate the number of turns N required for the specified inductance L, and finally, from
Equation 7, the power dissipation Pw. Pw should be less
than the maximum permissible power dissipation of the
core.
where:
4. If the power losses are unacceptable, a larger core or
one with a higher permeability is required and steps 1
through 3 will have to be repeated.
p.
= effective permeability of core
f e = effective magnetic path length (cm)
= effective magnetic cross section (cm2)
Several design cycles are usually required to optimize the
inductor deSign. With a little experience, educated guesses
as to core material and size come close to requirements.
Ae
Equation 2 defines a compound parameter called the inductor index AL:
AL = 0.41T
p.Ae
f e X 10 (mH/1000 turns)
(2)
986
APPENDIXB
SELECTION OF SWITCHING COMPONENTS
APPENDIXC
SELECTION OF OUTPUT FILTER CAPACITORS
The designer should be fully aware of the capabilities and
limitations of power transistors used in switching applications. Transistors in linear applications operate around a
quiescent point; whereas in switching applications operation
is fully on or fully off. 'Transistors must be selected and tested to withstand the unique stress caused by this mode of
operation. Parameters such as current and voltage ratings,
secondary breakdown ratings, power dissipation, saturation
voltage and switching times critically affect transistor performance in switching applications. Similar parameters are
important in diode selection, including voltage, current, and
power limitations, as well as forward voltage drop and
switching speed.
In general, output capaCitors used in switching regulators
are large (> 100 ,...F), must operate at high frequencies
(>20 kHz), and require low ESR and ESL. An excellent
trade-off between cost and performance is the solid-tantalum capaCitor, constructed of sintered tantalum powder particles packed around a tantalum anode, which makes a rigid
assembly or slug. Compared to aluminum electrolytic capacitors, solid-tantalum capacitors have higher CV productper-unit volume, are more stable, and have hermetic seals
to eliminate effects of humidity.
APPENDIX 0
EMI
Due to the wiring inductance in a circuit, rapid changes in
current generate voltage transients. These voltage spikes
are proportional to both the wiring inductance and the rate
at which the current changes:
Initial selection can begin with voltage and current requirements. Voltage ratings of the switching transistor and diode
must be greater than the maximum input voltage, including
any transient voltages that may appear at the input of the
switching regulator. Transistor saturation voltage VCE(SAn
and diode forward voltage Vo at full load output current
should be as low as possible to maintain high operating
efficiency. The transistor and diode should be selected to
handle the required maximum peak current and power dissipation.
Good efficiency requires fast switching diodes and transistors. Transistor switching losses become significant when
the combined rise t, plus fall time tf exceeds:
.
0.05 (ton + toft)
V=L~
dt
The energy of the voltage spike is proportional to the wiring
inductance and the square of the current
E = 1/2U2
Interference and voltage spiking are easier to filter if the
energy in the spikes is low and the components predominantly high frequency.
The following precautions will reduce EMI:
-
For 20 kHz operation, tr + tf should be less than 2.5 ,...s for
maximum efficiency. While tranSistor delay and storage
times do not affect efficiency, delays in turn-on and turn-off
can result in increased output voltage ripple. For optimal
operation combined delay time td plus storage time ts
should be less than:
0.05 (ton
-
-
+ toft)
987
Keep loop inductance to a minimum by utilizing appropriate layout and interconnect geometry.
Keep loop area as small as possible and lead lengths
small and, in step-down mode, return the input capaCitor
directly to the diode to reduce EMI and ground-loop
noise.
Select an external diode that can hold peak recovery
current as low as possible. This reduces the energy content of the voltage spikes.
....
....
i
APPENDIXE
DESIGN EQUATIONS
1
LM78S40 Design 'Formulae
Characterl8l1c
IpI<
2IOUT(max)
Rsc
(VOUT + Vo - VSAT)
VIN - VSAT
2 IOUT(max)
Ion
VOUT + Vo
toff
VIN - VSAT - VOUT
(VOUT + Vo)
Ipk
(Max load
condition)
Vo - VIN
IVOUTI + Vo
(VOUT + Vo - VIN)
Ipk
VIN -VSAT
(IVOUTI + Vo)
~k ,
toff
toff
Ipk L
Ipk L
VOUT + Vo - VIN
IVOUTI + Vo
45 x 10-S,Ioff(p.s)
45 x 10-SIpn(p.s)
45 x 10-5 toff(p.s)
(Ip!< - IOUT)2 toff
(Ipk - IOUT)2 toff
8 VRIPPLE
21pk VRIPPLE
2 Ipk VRIPPLE
(VIN - VSAT + Vo)
VOUT
VIN
VOUT + Vo
VIN - VSAT (
VOUT
)
VIN
Your + Vo - Vs
Ipk (Ion +
IIN(avg)
toff
:I'
VIN -VSAT
lokI-
Co
Efficiency
VOUT
0.331p1<
Your + Vo
toff
Gr(,.F)
(VIN+ IVciuTI+Vo-VSAT)
2IOUT(max),
VIN - VSAT
O.33Ii>k
0.331pk
L
Inverting ,
Step Up
Step Down
!e!! (
2
toff)
!e!!
VOUT + Vo
)
VIN -;- VSAT + Vo'
2
Note: VSAr-Saturation voltage of the SWitching element
Vo-Forward voltage of the flyback diode
988
(
!e!! (
2
Ivoirrl
)
Vo + IVOUTI
IVOUTI + Vo
)
VIN + IVOUTI+vo- VSAT
LM385 Feedback Provides
Regulator Isolation
National Semiconductor
Application Note 715
Robert Pease
Fran Hoffart
You can use a conventional 4N27 optocoupler in a feedback arrangement (Figure 1) to design a switching regulator
with a floating output. The LM3524 switch-mode-regulator
Ie is configured as a simple flyback power supply with transformer-isolated output. The LM385 acts as a reference and
comparison amplifier that satisifes the 4N27's current demands for balancing the dc feedback to pin 2 of the
LM3524,.thereby closing the loop. The LM385 automatically
compensates for any LED degradation or optical-coupling
loss.
The 4N27 specs a 0.1 dc to 1.6 dc gain range; the ac gain
varies from 0.05 to 1.0. Fortunately, the "Miller" damper
from pins 5 to 6 nullifies the effect of the wide gain variance.
Moreover, the damper provides excellent loop stability for a
wide range of 4N27 optocouplers from several manufacturers. In the example shown, the LM385 provides 0.5 mA to
5 mA to the optocoupler.
POW~~~~
If the 5V output available from this circuit does not meet
your needs, choose R2 = Rl (VOUT - 1.25)/1.25. If VOUT
is greater than 6V, insert a zener diode between points X
and Y, with Vz = VOUT - 5V; this addition prevents the
voltage across the LM385 from exceeding its 5.3V max limit.
The circuit is suitable for regulated output voltages from
3.2Vto 25V.
VOUT
0------_--..--_---------------,
.J
+5'
e ..
+
,.
R,
15k
220
O.SW
'20
+.
10k
1_
'OOp'
0.0047
"
",.
45.3k
10.
lOOk
27
4~~
r
R.turn
...
,opr
5' .
(Pln1S)
-=
12.
-=
0.003
680k
"-'
"-'
L = 151umS #22 wire wrapped on YoW resistor body.
01 = op1lonal (see 1ex1).
470k
-=
-=
TL/H/11049-1
FIGURE 1. Optocoupler-based feedback circuit produces galvanically-Isolated. regulated voltages. The heavy
negative feedback compensates for wide variations In optocoupler gains. The values portrayed in this schematiC
yield 5V output; by varying R2. you can obtain voltages from 3.2V to 25V.
989
,py'rulmic Specifi~~tlons'for'
,$8rl1PUng AID Converters.
National Semiconductor
Application Note 769 '
Leon G. Melkonian
., ,".
<',I"""
generally specified in the data sheets at a set of input signal
frequencies, at a specifiC sampling rate, and with the signal
ampljtude at or near the maximum allowable level.' ,
1.0 INTRODUCTION
Traditionally; analog·tCi~digital converters (AOOs) have been
specified by their static characteristics, such as integral lind
differential nonlinearity, gain error, and offset error. These
specifications are important for determining the DCaccuracy of an AID converter, and are very important in application!! such as weighing, temperature measurement, andother ,situations where the input signal varies sloWly oYE/r time.
There is 'some ambiguity regarding the composition of the
nOise component of the SIN ratio. Some manufacturers reserve the term SIN ratio to include only the backgroand
noise and, the spurious noise, whereas others also include
the harmonics of the signal.
'
When comparing the SIN ratiO for Several sampling ADCs,
one should look in the data sheets to see how it is measured. When the harmonics are included, the SIN specification is frequently referred to as the Signal-to-{Nolae + DIstortion) or SINAD. Both signal-to-noise specifications exclude any DC offset from the noise component. To determine the background noise level, one must integrate the
noise spectral density over the bandwidth of interest.
Many applications, however,rElquire digitizing a signal which
varies qUickly over time. These include digital signal processing (DSP) ,applications, such
digital audio,spectral
analYSiS, and motion control. For these applications, DC accuracy is not as crucial as AC accuracy. The important
specifications for these applications are the dynamic specificatipns, such as signal-ta-noise ratio, total harmonic distortion, intermodulation distortion" and input bandwidth. A,n
AID converter by itself cannot accurately digitize high frequency Signals, due to limitations imposed by its conversion
time. (If the signal varies by more than % LSB during the
conversion time of the ADC, the conversion will not be fully
accurate.) To digitize a high frequency signal, one must use
a sample-and-hold (S/H) amplifier to "freeze" the Signal
long enough so that the ADc can make an accurate conversion. Hence, the dynamiC sp~ifications are not unique to
the ADC, but are properties of the S/H-ADC system. With
the advent of sampling ADCs, which have a SIH built onto
the chip with the ADC, it is now possible to meaningfully
characterize the dynamic specifications of a single device~'
as
Even a perfect ADC will have some noise, which arises from
the quantization process. If' one treats this quantization
noise as white noise and considers no other noise sources,
the maximum SIN ratio attainable for an n-bit ADC is 1.
Total Harmonic Distortion. or THO, relates the rms sum of
the amplitudes of the digitized Signal's harmonics to the amplitude of the signal:
'
, =
THD
In this application note, we discuss the meaning and signifi- "
cance 'of the various dynamic specifications for sampling
ADCs, and in the appendix we give a table which haS typical
values for these specifications for a number of sampling
ADCs.
2.0 MEANING OF THE DYNAMIC SPECIFICATIONS
Slgnal~to-Nolse Ratio. The signal-to-noise (SIN) ratio is
+ 1.76 dB.
SIN = 6.02n
Hence; one can see that the SIN ratio can be increased by
going to the higher resolution ADCs.
(V2,+V2+
13
,12
V~
)Y.'
••• , '
where V't is the amplitude of the' fundamental and Vflis the
amplitude of the ith harmonic. One generally includes all
harmOnics within the bandwidth of interest; however, sometimes in practice only the first five harmonics are taken into
account, because higher order harmonics have a negligible
effect on the THD.
the ratio of the Signal amplitude to the noise level. It is
...c
5
...
~
21
rREQUENCY
I
31
I
41
rREQUENCY
TL/H/11193-1
FIGURE 1. A Signal with a Single Frequency Component (left)
Suffers Harmonic Distortion after AID Conversion (right)
990
integral and differential nonlinearities are going down, proportionately, as the resolution increases. This is generally
the case.) Like the SIN ratio, the THO is generally specified
in the data sheets at a set of frequencies and with the signal
amplitude at or near the maximum allowable level. It is usually specified in decibels or as a percentage.
Having a low THO is especially important in applications
such as audio and spectral analysis because in these applications, particularly, one does not want the conversion pro·
cess to add new frequency components to the signal.
ADCs produce harmonics of an input signal because an
ADC is an inherently nonlinear device. This can be easily
seen by looking at the transfer curve of an ideal ADC, which
looks like a staircase with equal-sized steps (Figure 2). In a
real ADC, "bowing" and other nonlinearities add to the distortion. If the output of an ADC is fed to a perlect DAC, then
the transfer function of this system can be represented in
principle as a polynomial
ao
VOUT =
+ al(VIN) + a2(VIN)2 + aa(VIN)3 + ...
A perfectly linear system would have all the aj zero except
and al. The second harmonic appears, for example,
for
because a2 is nonzero. If one uses the trigonometric identity
ao
Intermodulatlon Distortion, or IMD, results when two frequency components in a signal interact through the nonlinearities in the ADC to produce signals at additional frequencies. If fa and fb are the signal frequencies at the input of the
device, the possible IMD products fmn are given by
fmn = m fa ± n fb' where m and n take on positive integer
values, and are such that fmn is positive. The jth order IMD
products are those for which m + n = j.
)2_1+cos2(1)t
(
COS(l)t 2
'
one can see how a second-order nonlinearity produces an
output that has a frequency that is twice that of the fundamental.
As one goes to higher resolution converters, the THO will
decrease because the transfer curve of the ADC more
closely resembles a straight line. (We are assuming that the
The second order intermodulation products of fa and fb'
which occur when m and n both equal I, are given by the
sum and difference frequencies of fa and fb.
Using the formula
(cos (l)lt + cos (l)2t)2 = COS2(1)1t + 2(cos (l)lt)(COS (l)2t) +
COs2(1)2t
and the trigonometric identity
2(cos (l)lt)(COS (l)2t) = cos «(1)1 + (l)2)t + cos «(1)1 - (l)2)t
one can see how a second-order nonlinearity leads to the
production of an output that has components at the sum
and difference frequencies of the inputs (and also at the
second harmonics). The intermodulation distortion due to
second order terms is commonly defined as
01
110
101
§ 100
~
:0
on
o
010
IMD = (Vt1 +
V~.-1
V~ + V~
001
where Va and Vb are the amplitudes of the fundamentals
and Vl,l and Vl,-1 are the amplitudes of the sum and difference frequencies, respectively. Figure 3 shows a particularly bad case of intermodulalion distortion; harmonic distortion products are also visible. In calculating the IMD for this
example, one must include the higher order IMD products to
get an accurate measure of the distortion.
FS
INPUT VOLTAGE
TL/H/11193-2
FIGURE 2. The Nonlinear Nature of the ADC Transfer
Curve Is the Cause of THO and IMO
FREQUENCY (kHz)
)V.,
I
10
FREQUENCY (kHz)
10
TL/H/11193-3
FIGURE 3. An Input Signal wIth Frequency Components at 600 Hz and 1 kHz
(left) Suffers Severe IMD after AID Conversion (right)
991
~ r-----------------------------------------------------------------------------~
te
~
The way IMDis specified forsampling,ADCs varies from
manufacturer to manufacturer. Variations o~ur in the number of,IMD products that are included in the measurement,
whether the two input frequencies have equal or unequal
amplitudes, and whether ,tile distortion is referenced to the
rms sum of the input amplitudes or to the amplitude of the
larger input. When comparin9 the IMD for several sampling
ADCs, especially if they are from different manufacturers,
one must know how it is measurEld iri,each case.
As one can infer from Figure 3. an ADC with a poor IMD
specification would lead to very pOQr performance in an audio or spectral analysis' application. Another reason for
wanting a good IMD specification is to prsv$nt the appearance ,of spurious signals produced by the coupling of strong
out-of-band frequency components with signals in ,the band
of interest.
Dynamic,Dlfferentiai Nonlinearity is ,the differential non·
linearity of the ADC for an AC ,input. It is frequently measured at the maximum sampling rate and wi,th an input that
is at the Nyquist frequency (half the sampling ,rate). Differen1
tial' nonlinearity is the deviation from the ideal 1 LSB input
voltage span that is associated with eaoh output ,code (Figure 5). It is measured using the histogrem, test.
111
110 '
... 101
8 100
5
I!=
5
Peak Harmonic is the amplitude, relative to the fundamental, of the largest harmonic resulting from the AID conversion ,of a Signal,. The peak harmonic is usually, but not always, the second harmonic. It is usually specified in decibels.'
,
011
010
DNL
=x -
FS/8
001
000
Peak Harmonic or Spurious Noise is the amplitude, relative to the signal level, of the next largest frequency component (other than DC). Spurious noise components are noise
components which are not integral multiples of the' input
signal, and are often aliased harmonics IHhe signal freQuency is a significant fraction of the sampling rate. This specifi.
cation is important ,b!lC8US8 some applications require that
the harmonics and Spurious ,noise components be smaller
th!!n the lowest amplitude Signal of interest.
Spurious-Free Dynamic Range is the ratio of, the signal
amplitude to the amplitude of the highest harmonic or spuri·
ous noise component; the input signal amplitude is at or
near full scale (F/fJure 4). This specification is simply the
reciprocal of the "Peak harmonic or spurious noise" if in the
measurement of that specification the input signal amplitude
'
is at full scale.
1 'i.SB = FS/8
o
FS
INPUT VOLTAGE
TUH/11193-5
FIGURE 5. Differential Nonlinearity Is a Measure of the
Deviation from the Ideal 1 LSB Input Voltage Span
Associated with Each Output Code
Dynamic Integral Nonlinearity is the integral nonlinearity
of the ADC for an AC input. Like the dynamic differential
nonlinearity, it is frequently measured at Nyquist operation.
Integral nonlinearity describes the departure of the ADC
transfer curve from the ideal transfer curve, excluding the
effects of offset, gain and quantization errors (Figure 6) .
n1
110
101
OdS . . . . - - , . - - - - - , - - - - - - - - SIGNAL AMPLITUDE
~
8
,~
...
SPURIOUS-fREE
DYNAMIC RANGE
'"0
!
PEAK HARMONIC
_____ OR SPURIOUS NOISE
100
on
010
001
NOISE FLOOR
INPUT VOLTAGE
TUH/11193-6
FIGURE 6. Integral Nonlinearity Measures such
Features as "Bowing" in an ADC Transfer Curve
FREQUENCY
TLJH/11193-4
FIGURE 4. Spurious-Free Dynamic Range Indicates
How Far below Full Scale One Can'
Distinguish Signals from NOise and Distortion
992
Effective Number of Bits (ENOB) is a specification that is
closely related to the signal-to-noise ratio. It Is determined
by measuring the SIN and using the equation
larger than the full power bandwidth. This will be the case if
the bandwidth is slew rate limited, for example. The small
signal bandwidth is important for those applications which
do not require the conversion of large amplitude, high frequency signals. Relying on the full power bandwidth specification in these cases would constrain one to a smaller
bandwidth than can actually be attained.
Sampling Rate, or throughput rate, depends on the length
of the conversion time, acquisition time, and other time delays associated with carrying out a conversion. Signals
which have frequencies exceeding the Nyquist frequency
(half the sampling rate) will be aliased to frequencies below
the Nyquist frequency. In order to prevent this signal degradation, one must sample the signal at a rate that is more
than twice the highest frequency component in the signal,
and/or process the signal through a low pass (anti-aliasing
filter) before it reaches the ADC. In some applications one
wants to sample at a rate much higher than the highest
frequency component of interest in order to reduce the
complexity of the anti-aliasing filter that is required.
ENOB = SIN -1.76
6.02
Some manufacturers define the effective number of bits using the SINAD instead of the signal-to-noise ratio. ThE!
ENOB generally decreases at high frequencies, and one frequently sees it plotted as a function of frequency, along with
the SINAD (Figure 7). The effective number of bits specification combines the effects of many of the other dynamic
specifications. Errors resulting from dynamic differential and
integral nonlinearity, missing codes, total harmonic distortion, and aperture jitter show up in the effective number of
bits specification.
Full Power Bandwidth has several definitions. A common
definition is that it is the frequency at which the SIN ratio
has dropped by 3 dB (relative to its low frequency level) for
an input signal that is at or near the maximum allowable
level. This corresponds to a drop in the ENOB by Yz bit
relative to its low-frequency level. Another definition is that it
is the frequency at which the input signal appears to have
been attenuated by 3 dB. Some manufacturers of flash converters define full power bandwidth as the frequency at
which spurious or missing codes begin to appear. (Missing
codes will occur if the dynamic differential nonlinearity is
greater than + 1 LSB.)
Small Signal Bandwidth is the frequency at which the SIN
ratio has dropped by 3 dB for an input signal that is much
!lmaller than the full-scale input, 20 dB or 4Q dB below fullscale, for example. The small signal bandwidth is generally
SAMPLE-AN[)';HOLD CIRCUITRY SPECIFICATIONS
Aquisition time, aperture time, and aperture jitter are specifications that relate to the internal sampling circuitry within
the ADC. These specifications can be easily explained with
the aid of the simple sample-and-hold circuit shown in Figure 8. The SIH amplifier is in "Sample" mode when the
switch is closed. In this case, the output of the amplifier is
following the input. When the switch is opened, the SIH
amplifier is in "Hold" mode; in this case, the output retains
the input voltage that was present before the switch was
opened.
"
en
Iii
...
...'"'"
6
\
C>
:::IE
:>
4
~
2
...>z
...t::
40
30
'@'
3
\
20
~
10
10
100
INPUT FREQUENCY (11Hz)
TLlH/11193-7
FIGURE 7. Effective Number of Bits and SIN Generally Drop at High Frequencies
993
Aperture time is important if one needs to acquire the value
of a signal at a precise ·time. Since the signal is not held
instantaneously upon application of the "Hold" command,
this command must be given roughly an "aperture time"
before one wants the signal to be "frozen".
The aperture. time is 1'10t a limiting factor on the frequency
for sinusoidal signals because for a sinusoidal signal, the
voltage error cau~d by the aplilrture time manifests itself as
a phase change, not ari amplitude or frequency change•.
Aperture Jitter is the uncertainty in the aperture time. Aperture jitter results from noise which is superimposed on the
"Hold" command, which affects its timing. Aperture jitter is
generally specified as an rms value, which represents the
standard deviation in the aperture. time.
The aperture jitter sets an upper limit on the maximum frequency sinusoidal signal that can be accurately converted.
In order not to lose accuracy, the rule of thumb is that the
signal must not change by more than ± Yz LSB during the
aperture jitter time. Using a full-scale sinusoidal signal V =
A sin (27Tft), we have
TI.IHI11193-B
FIGURE 8. Simple StH Circuit
Acquisition Time is ·the maximum time required to acquire
a new input voltage once a "Sample" command has been
given (Figure 9). A signal is "acquired" .when it has settled
to within a specified tolerance, usually Yz LSB, of the input
voltage. The maximum value of the acquisition time occurs
when the hold capaCitor must charge up from zero to its fullscale value (or the other way around, if it is larger). Acquisition time is important because it makes a significant contribution to the total time required to make a conversion.
r ------:::===...-..-;.1.:;_.;--
r-
FULL-SCALE
dV = 2'1TfA cos (27Tft) < ± Yz LSB
dt
taj
where .taj is the aperture jitter. Since Yz LSB = Al2n, Where
n is the resolution of the converter, we get
:I: 1/2 LSB
ERROR BAND
ov----I-I
f
<
1
27T e 2ne taj
As an example of using Ithis criterion, a 12-bit converter
whose StH amplifier has an aperture jitter of 100 ps could
convert full-scale signals having frequencies as high as
388 kHz. Of course, this would only be possible if the converter's sampling rate is at least twice as high as this frequency, in order to satisfy the Nyquist criterion.
ACOUISITION TIME
SAMPLE
TIME
TI.IH/11193-9
3.0 CONCLUSION
It is important to have a working knowledge of the dynamic
specifications of sampling ADCs in order to be able to select
a converter that is suitable for a specific system need. One
must also be aware that the test conditions and even the
definitions of the specifications may vary from manufacturer
to manufacturer. One must take these variations into account when comparing ADCs. Using the information in this
note, one should be able to understand the meanings of the
various specifications and determine which ones are important for the particular application at hand.
FIGURE 9. Acquisition Time
Aperture Time is another specification that is defined differently by different manufacturers. The strict definition is
that it is the time during which the signal is being disconnected from the hold capacitor after a "Hold" command has
been given. The broader definition is that it is the time between the application of the "Hold" command and when the
signal has been completely disconnected from the hold capacitor. The second definition includes the digital delay
which occurs between when the "Hold" command is applied and when the "switch" connecting the input signal to
the hold capacitor begins to open.
REFERENCE:
1. B. Blesser, "Digitization of Audio," J. Audio Eng. Soc.,
vol. 26, no. 10, pp. 742-743 (1978).
994
APPENDIX
What f()lIows is a table which presents values of the dynamic specif~tlons for a number of National's sampling ADCs.
Additional information, such as the values of SIN and THO
at frequencies not listed here, can be found in the data
sheets. The reference voltage that all of these parts are
specified at is + 5V, and the supply voltage is + 5V for the
ADC10461 and ADC10862 and ±5VfortheADC12441 and
ADC12451. The only other test conditions included here are
the input frequencies and signal amplitudes. Additional test
conditions, such as the ambient temperature, can be found
in the data sheets. Only the sampling ADCs whose dynamic
specifications are tested and guaranteed are included
here1,2. Additional !ijlmpling ADCs made by National are the
ADC0820, ADC1061, ADC1241, ADC1251; and the
ADC08031,
ADC08061,
ADC08131,
ADC08161,
ADC08231, ADC10061 , and ADC1031 families.
Dynamic Specifications for Selected Sampling ADCs
ADC10662 (Note 2)
10
10
Conversion Time
900ns
466ns
13.8 p.s
7.7 p.s
SIN Unipolar (Note ~)
Bipolar (Note 4)
58 dB
58 dB
71.5 dB
76.5 dB
68.7 dB
73.5 dB
THO Unipolar (Note 5)
Bipolar (Note 6)
-60 dB
-60 dB
-75dB
-75dB
-73.1 dB
-78.0 dB
-73 dB
-74dB
-78dB
-78dB
11.6
12.4
11.1
11.9
Peak Harmonic
Uni. (Note 11)
or Spurious Noise Bi. (Note 12)
-82dB
-80dB
-82 dB
-80dB
FullPowerBW
20kHz
20.67 kHz
55kHz
83kHz.
IMD Unipolar (Note 7)
Bipolar (Note 8)
ENOB Unipolar (Note 9)
Bipolar (Note 10)
sampling Rate
9
9
800kHz
1.5 MHz
ADC12441
ADC12451
ADC10461 (Note 1)
Spec
Resolution
12
+ sign
12
+ sign
Acquisition Time
3.5 P.s
3.5 p.s
Aperture Time
100 ns
100 ns
100 PSrms
100 PSrms
Aperture Jitter
Note 1: There are two and four Input channel
rnambars of the ADC10461 lemily, namely Iha ADC10462 and ADC10464. These products have the sarna dynamic
specification. as the ADC10461.
Note 2: The ADCl0664 is a 4-input channel member of Iha ADC10662 family (the ADC10662 has two input channels). These two products have the same dynemic
specification•.
Note 3: ADC10461:
liN = 50 kHz; VIN = 4.85 vPi'
ADC10862: liN = 50 kHz; VIN = 4.85 VPi'
ADCI2441: ~N = 20 kHz; VIN = 4.85 Vpop
ADC12451: liN = 20.87 kHz; VIN = 4.85 Vpop
Note 4; ADCI2441: ~N = 20 kHz; VIN = ±4.85V
ADC12451: liN = 20.67 kHz; VIN = ±4.85V
Note 5: ADC10461: liN = 50 kHz; VIN = 4.85 VPi'
ADC10862: liN = 50 kHz; VIN = 4.85 VPi'
ADCI2441: ~N = 19.688 kHz; VIN - 4.85 Vpop
ADCI2451: liN = 20.67 kHz; VIN = 4.85 Vpop
Note 8: ADCI2441: ~N = 19.688 kHz; VIN = ±4.85V
ADCI2451: liN = 20.87 kHz; VIN = ±4.95V
Note 7: ADCI2441: ~Nl = 19.375 kHz; IIN2 = 20.625 kHz; VIN = 4.85 VP1l
ADCI2451: IINI = 19.375 kHz; 11N2 = 20 kHz; VIN = 4.85 Vp-p
Note 8: ADCI2441: IINI = 19.375 kHz; 11N2 = 20.625 kHz; VIN = ±4.85V
ADCI2451: IINI = 19.375 kHz; IIN2 = 20 kHz; VIN = ± 4.85V
Note· 8: ADC10461: ~N = 50 kHz; VIN = 4.85 Vpop
ADC10862: ~N = 50 kHz; VIN = 4.85 Vp.p
ADCI2441: liN = 20 kHz; VIN = 4.85 VPi'
ADCI2451: liN = 20.67 kHz; VIN = 4.85 Vpop
Note 10: ADCI2441: liN = 20 kHz; VIN = ±4.85V
ADCI2451: liN = 20.67 kHz; VIN = ±4.85V
Note 11: ADCI2441: liN = 20 kHz; VIN = 4.85 vPi'
ADC12451: ~N = 20 kHz; VIN = 4.85 Vpop
Note 12: ADCI2441: liN = 20 kHz; VIN = ±4.95V
ADC12451: ~N = 20 kHz; VIN = ±4.85V
995
National Semiconductor
Application Note 775
Specifications and.
Architecture$ of Sample.- .
and-Hold Amplifiers
I. INTRODUCTION
Sample-and-Hold (StH) amplifiers track an analog signal,
and when given a "hold" command they hold the value of
the input lIignal at the instant ",hen the "hold" command
was issued,· thereby serving as an analog storage device.
An ideal StH amplifier would be able to track any kind of
input signal, and upon being given a hold command store at
its output, without delay, the precise value of the signal, and
maintain this value indefinitely. Unfortunately, ideal StH
amps do not yet exist, and to be able to pick a StH amp to
suit a particular application, one must be familiar with how
StH amps are characterized, and how the StH specifications will affect performance. In addition, it is helpful to be
familiar with the common architectures that are used for
StH amps, as the architecture has a profound effect on the
performance.
In this application note, we discuss the meaning and signifiance of the various specifications for StH amps, and we
also discuss several common 8tH architectures, and how
. the performance is influenced by the architectures. In the
appendix, we give a table which lists the key specifications
for a number of StH amps. Since the primary use of StHs is
in data conversion, we will refer to such applications when
discussing some of the specifications.
II. MEANING OF THE SPECIFICATIONS
When discussing StH speCifications, it is helpful to have the
circuit diagram of a StH amp at hand: Figure 1 shows a
schematic of the open loop configuration, which will be discussed later in more detail. Since a StH amp has two
modes. (the S!lmple mode and the hold mode), and two tra~- .
sitions between the modes (sample-to-hold and hold-tosample), it is convenient to discuss the specifications in
these four groupings. Figure 2 shows a StH timing diagram
that displays these two modes and two mode transitions.
SAMPLE MODE SPECIFICATIONS.
Offset Voltage is the deviation from zero of the output volt-' ,
age when the input voltage is zaro and the 8tH amp is in
sample mode. To maintain absolute accuracy in lin AtD
converter application, the offset voltage must be lass than
1f2 LSB, or .
FS
Ves < 2n + 1'
where F8 is full scale and n is the resolution of the analogto-digital converter (ADC). Many 8tH amps have provision
for nulling the offset voltage; however, manual nuliing can
be expensive. Sometimes the offset is specified as an Input
offset voltage; this is particularly useful if the StH ~an be.
configured for a gain other than unity..
."
'.
Gain Error is the fractional voltage difference between the
input voltage and the output voltage (excluding the ilffects
of offset voltage) when the StHamp is in sample mode;
here we assume the ideal gain is unity. If absolute accuracy'
is required in an AID application, the gain error should be
less than 1f2 LSB, or
Il.A = Vour-VIN <_1_
V
VIN
2n+1'
where h is the resolution of the converter:
> ....-_··VOUT
TLlHIH2I'S-1
FIGURE 1. A Simple StH Amplifier Consists of a Switch, Hold Capacitor, and Input and Output Buffers
Sampl. Mod.
Hold Mod.
------1--- Input Vol\oee
- - - - - - - - - - - - - - - - - - - - - -.....~TI,;;~
TLIH111215-2
FIGURE 2. S/H Timing Diagram Showing the Two Modes and the Two Transitions Between the Modes
996
Gain Linearity Error is the maximum deviation of the S/H's
transfer curve from an ideal straight line connecting the end
points of the transfer curve (the effects of offset and gain
error are excluded). Spectral distortion is a consequence of
gain linearity error in the S/H.
Slew Rate is the maximum rate of change of the output
voltage when the S/H amplifier is in sample mode. Because
the slew rate depends on the value of the hold capacitor,
this capacitance must be specified if the hold capaCitor is
extemal. The slew rate is Important because it affects the
full-power bandwidth and acquisition time of the S/H.
Full·Power Bandwidth is commonly defined in two ways.
Some manufacturers define it as the frequency at which the
voltage gain of the S/H amplifier drops by 3 dB relative to
the gain at dc for a full-scale input. Others derive the full
power bandwidth from a measurement of the S/H's slew
rate. According to this definition, the full power bandwidth is
equal to the frequency of the full-scale sine wave which has
its maximum rate of change equal to the slew rate; This is
given by
SR
SAMPLE·TO·HOLD TRANSITION SPECIFICATIONS
Aperture Time, also known as aperture delay, is a specification that is defined differently by different manufacturers.
The strict definition is that it is the time during which the
Signal is being disconnected from the hold capacitor after a
hold command has been given (Figure 3). The broader definition is that it is the time between the application of the
hold command and when the signal has been completely
disconnected from the hold capacitor. The second definition
includes the digital delay which occurs between when the
hold command is applied and when the switch connecting
the input signal to the hold capacitor begins to open.
BWIp=-211'Vp
where 2Vp is full scale and SR is the slew rate of the S/H.
Small Signal Bandwidth is the frequency at which the voltage gain of the S/H amplifier drops 3 dB relative to the gain
at dc for an input that is much smaller than full scale, such
as 20 dB or 40 dB below full scale. The small signal bandwidth is generally larger than the full power bandwidth; this
would be the case if the full-power bandwidth is slew rate
limited, for example. The small signal bandwidth is important
for those applications which do not require the conversion
of large amplitude, high frequency signall\. Relying on the
full power bandwidth speCification in these cases would
constrain one to a smaller bandwidth than can actually be
attained in practice.
Unlike aperture jitter, the aperture time is not a limiting factor on the maximum frequency for sinusoidal Signals because for a sinusoidal Signal, the voltage error caused by
the aperture time manifests itself as a phase change, not an
amplitude or frequency change.
Effective Aperture Delay Time is the time delay between
the generation of the hold command and the appearance at
the input of the final "held" voltage that exists on the hold
capacitor (Figure 3). If precise timing is required, the hold
command must be given an "effective aperture delay time"
before the in~nt at which the input value is desired.
Analog Input
~~~------------~
Logic _ _ _ _ _s_am...;p_18_ _ _-i
Input
Hold
Fully Closed
SWltCh---~~';';';";';;';;"'--"'" ...._ _.....;.....;.._ __
"'-
Fully Open
--------------------------------------~. Tim.
FIGURE 3. Aperture Time and Effective Aperture Delay Time
997
TLlH/11215-3
U) r-------------------------------------------------------------------------------------~
i
Ap~rture,Jltter, also known as aperture uncertainty, is
the uncertainty in the aperture' time: Aperture jitter results
from noise,whiohis superimposed on the,hold oommand,
whioh affects ,its timing. Aperture jitter is often ,speoi,fied as
an rms value, whioh represents the standard deviation in the
aperture time.
The aperture jittElr SE!ts an IIPper limit ,on th" maximum frequency simlsC1idal signal thlit oan be accurately'sampljKI by
a S/H,. In order not to lose aoollracy, the rule of t\lumbis
that the Signal must not ohange by' more than ± Yz LSB
during the aperture jitter' time. Using a, lull-llOale sinusoidal
signal V = A sin (21Tft), we have
.
,
ue of the hold oapacitor; This,will, how9ller"resultin a larger.
acquisition time. For AID applications, it is desirable that the
hold step be independent of the input vollage and less than
% LSB.
Hold Mode Settling Time is the time requirecffor the output
to settle within a specified,arror'band after a,hold command
has been given. This error band is oommonly specified as
1%, 0.1 % or 0.01 % of a full-soale step ,input For AID converter applioations, one needs the output to settle within
± % LSB before aconvel'$ion is started. ,The, hold mode
settling time is also important because the sum of the acquisition time,the'hold mode settling time, and the AID conver.
sion time determines the maximum sampling' rate of the
S/H-ADC system. (If the conversions are pipelined, the
sampling rate can be higher).
~
= 2'1TfACos(2'1Tft) < ±% LSB
dtlei
where A is' half the analog inpUt voltage range and lei is the
aperture jitter. Sinoe % LSB = Al2", where n is the resolution of the converter, we get
f
<
,
1
(fS>max = - - - ' - - - "
taq+tHS+tc
Sample-to-Hold Transient is th,!!, ~al1sient that ,appearll lit
thlil, output due to a sample-to-hold transition. The maximl,lm
amplitude of the transient is usually specified. S/Hs used to
deglitch the output of digital-to-analog converter must have
small sample-to-hold tran~ent.
1,
, 21T X 2"X lei
As an example of' using this oriterion, a 12-bit converter
whose S/H amplifier has 'an aperture,litter of 100 ps ,could
convert fUll-scale signals ha'(ing frequencies as high as
388 kHz. Of course, this would only be possible if th!l oonverter's sampling rate is at least twioe as high as this frequency, in order to satisfy the Nyquist criterion.
Cllarge Tran~fer,or charge 'InJection, is the amqunt of
charge transferred to the hold capacitor uPon opening the
switoh after a hold Command has been given. It ,is oaused by
capaoitive coupling between the hold capaCitor and the gate
of the transistor that serves as the switch. ,Because of this
charge transfer, there is a hold step at the output. For architectures in which the hold capacitor "sees" the input ,voltage, the oharge transfer is a function of the input voltage,
and can be a nonlinear function, leadil1g to har!TIonic distor~
tion.
Hold Step, also known as pedestal and sample-to-hold
offset, is the voltage step that appears at the olltput due to
the sample-ta-hold transition (F/{/ure 4). It is caused by a
transfer of charge to the hold capacitor due to the opening
of the switch. The hold step can be determined from the
charge transfer by
a
HOLD MODE SPECIFICATIONS'
Hold Capacito~ Leakage CUrrenJ is the' current whioh
flows in or out of the hold oapaCitor'''~/hile the S/H amplifier
is in hold mode. The leakage curtent conSists of three parts:
leakage through the dielectric of the hold capacitor, I~ge
through the analoj:J sWitch, and the input bias currlilnt, of the
output amplifier. (The leakage ourrents do not all naCessari-'
Iy /:lave the, same polarity). This specification is important
, because the droop rate is proportional to the hold capaCitor
leakage ourrent.
Droop Rate is the rate at which the output voltage is changing due to leakage from the hold oapaoitor. If the S/H has
an internal hold capacitor, the droop rate is specified in the
data sheets. However, if the hold capaoitor must be added
externally, the droop rate depends on the value of the hold
capacitor and is calculated from the equation
dVCH =~
dt
CH
where IL is the hold capaCitor leakage current.
Q
VHS=CH
where Q is the oharge transferred to the hold capacitor.
Hence, the hold step can be reduced by increasing the val-
Droop
Hold mode
settling time
Logic
Input
Sample
Input
Hold
TUH/11215-4
FIGURE 4. Sources of Error In Hold Mode and during the Sample-to-Hold Transition
998
The droop rate is important for applications where the sampled voltage must be held within a specified error band for
long periods of time. In AID applications, one does not want
the output to droop by more than % LSB during the conversion time. For these applications, the maximum allowable
droop rate of the S/H is given by
t
dVCH 2
FS
- < -10- =(2-n + 1) 10
dt
LSB
where FS is the full-scale voltage of the ADC, n is its resolution, and 10 is the ADC conversion time. The droop rate can
be reduced by increasing the value of the hold capacitor,
but this results in a higher acquisition time.
Feedthrough Attenuation Ratio is the fraction of the input
signal that appears at the output while the S/H amplifier is
in hold mode. The feedthrough attenuation ratio is generally
specified for a specific frequency of input signal. For AID
applications, the feedthrough must be less than % LSB for
a full amplitude input. Hence, the feedthrough attenuation
ratio must be at least
AF> 20 log (2n+1) dB
which can be simplified to AF
resolution of the converter.
> 6(n + 1) dB, where n is the
HOLD-TO-SAMPLE TRANSITION SPECIFICATIONS
Acquisition Time is the maximum time required to acquire
a new Input voltage once a sample command has been
given (Figure 5). A signal is "acquired" when it has settled
within a specified error band around its final value of output
voltage. The error band is usually either 0.1 %,0.01 %, 1 mV,
or % LSB (in applications that involve an ADC). The maximum value of the acquisition time occurs when the hold
capacitor must charge to a full-scale voltage change. The
acquisition time depends on the value of the hold capacitor,
and this value must be specified if the hold capacitor is supplied externally. The acquisition time can be reduced by
choosing a smaller hold capacitance; however, this will increase the hold step and droop rate.
"
VIN -
/
"'u.
---.l.
-
Full-scale
:l:1/2LSB
Error Band
Vo
ov
Aoqul.ltlon Time
Hold
II
Sample
- - - - - - - - - - - - - - - . Time
TLfHf11215-5
FIGURE 5. Acquisition Time
999
III. SAMPLE-AND-HOLD ARCHITECTURES
The symbol that is frequently used for the S/H amplifier in
system block diagrams is a switch in series with a capacitor
(FlfJure 6). Although the switch can control the mode of the
device, and the capacitor can store a voltage, Ii S/H using
Just these components 'WOUld have very poor performance.
By studying the deficiencies of such a configuration, one
can better appreciate the components that are added to this
basic core to comprise a practical S/H amplifier.
VIN - - - - " " "
0:r
YOUT
Gt.:r:.
TLlHf11215-6
FIGURE 6. S/H Symbol
First, when in sample mode the charging time of the hold
capaCitor for the S/H in Figure 6 is dependent on the source
impedance of the input. A large source impedance would
give a large RC time constant, leading to a high acquisition
time. To ameliorate this effect, one buffers the hold capacitor from the input with an operational amplifier (assuming
that the op amp is capable of driving a capacitive load). The
acquisition time will then be independent of the source impedance, and will in fact be low due to the low output impedance of an operational amplifier.
Second, when in hold mode the hold capacitor will discharge through the load. Hence, the droop rate will be load
dependent and could be very high. To ameliorate this problem, one buffers the hold capacitor from the output with an
op amp. the droop rate will then be independent of the load,
and will actually be rather low, due to the large input impednace of an op amp.
Hence, in addition to a switch and a hold capacitor, a practical SI H amplifier must include input and output buffers. The
two main variations of this structure, the open-loop and
closed-loop architectures, differ in the manner of their feedback.
In the open-loop architecture (Figure 7), the input and output buffer amps are each configured as voltage followers.
The advantage of this architecture is its speed-the acquisition time and settling time are short because there is no
feedback between the buffer amps. The disadvantage of
this architecture is in its accuracy, which suffers because of
the lack of feedback, causing the dc errors of both amplifiers to add.
For applications requiring high accuracy. one can use the
closed loop-architecture, with either a follower output (Figure 8) or an integrator output (Rgure 9). The feedback significantly improves the accuracy of the S/H relative to the
open-loop configuration. although the speed is somewhat
less.
In both the open-loop architecture and the closed-loop architecture with follower output, the charge transfer, and
hence the hold step, is a function of the input voltage. This
is because the hold capacitor is connected to the input signal (through the input buffer amp). The closed-loop architecture with integrator output ameliorates this problem by connecting the hold capacitor to virtual ground instead of the
nput signal. Hence the charge transfer is constant.
A new architecture whjch combines the ,speEKI of the openloop. configurationand the accu~cy of the closed-loop configuration is· the 'current-multiplexed architecture shown in
Figure 10. The L~6197, Nlitional's'High Performance VIPTM
Sample-and-Hold Amplifier' used tllis architeCture. This' architecture provides fClr a .cancellation of ch~rge injection,
allowing one to use a small. hold capacitor to get high
speeds without the disadvantage of a large hold st~P,."
In -the sample mode, the trllnsconduct8nce.,input stage grill
is connected to the output buffer, while switches S2 and S3
are closeG, .thereby shorting the dummy.capacitor CD and
grol!ncling CIne en~ of the .holdtcapacitor. allowing. it to
charge. The Ilold command conn~ input stage gm2 to the
output buffer and opens switches 82 and S3. The voltage
differential caused by charge injection into the hold capacitor is cancelled by an equal but opposite polarity of charge
injection into the dummy capacitor, which is the same value
as the hold capacitor. Hence, the common mode rejection
of gm2 results in a greatly reduced hold step.
> " , - - V OUT
TL/H/11215-7
FIGURE 7. Open-Loop Architecture
,
TUH/11215-8
FIGURE 8. ClOsed-loop Architecture with Follower Output
> ....- - VOUT
TL/H/11215-9
FIGURE 9. Clo.-d-Loop Architecture with Integrator Output
Input---I
> ....-Output
TUH/11215-10
FIGURE 10. Current Multiplexed Architecture
1000
IV. CONCLUSION
The selection of a S/H amplifier for a particular application
rE!quires an understanding of how S/Hs are specified and
how a particular specification will affect system performance; When comparing S/H amplifiers one must also be
aware that the test conditions and even the definitions of
the specifications may vary from manufacturer to manufacturer. A clear understanding of the meanings of the specifications should make it easier to compare S/Hs that are
tested using different definitions of the specifications.
APPENDIX
What follows is a table which presents values of the specifications for a number of National's S/H amplifiers. Additional
information, such as the values of the acquisition time and
hold mode settling time at other hold capacitor values and
to other accuracies, can be found in the data sheets. Additional S/H amplifiers made by National are the LH0023,
LH0043, and LH0053.
SPECIFICATIONS FOR SELECTED S/H AMPLIFIERS
Spec (Note 1)
Architecture
Input Offset Voltage
Gain Error
Small Signal BW
Slew Rate
Aperture Time
Aperture Jitter
Hold Step (Note 2)
Hold Mode Settling
TIme to 0.01 %
Hold Capacitor
Leakage Current
Droop Rate
Feedthrough Attenuation
Ratio at 1 kHz
Acquisition Time to 0.1 %
(Notes 3, 4)
LF398
LH4860·
LF6197
Closed-Loop,
Follower Output
±2mV
0.004%
Current Multiplexed
±1.0mV
Closed-Loop,
Integrator Output
±0.5mV
±0.005%
16 MHz
300Vl/Jos
6ns
35PSrms
±2.5mV
1 /Jos
60ns
50ns
30pA
5pA
6pA
±0.5I'V/l's
0.6/JoV/J£S
200ns
90 dB
±3mV
0.03%
25 MHz
145 VII'S
4ns
Bps,rns
±10mV
B3dB
100 ns
41'S
Note 1: The table lists the typical values of these specifications.
Note 2: LF398: Ct-i = 0.01 "F. VOUT = OV.
Note 3: I!J.VOUT = 10V.
Note 4: LF398: CH = 1000 pF.
1001
130 ns
20 Watt Simple Switcher
Forward Converter
National Semiconductor
Application Note 776
Frank DeStasi
Tom Gross
A 20W, 5V at 4A, step-down regulator can be developed
using the LM2577 Simple Switcher IC in a forward converter
topology. This design allows the LM2577 IC to be used in
step-down voltage applications at output power levels greater than the 1 A LM2575 and 3 A LM2576 buck regulators. In
addition, the forward converter can easily provide galvanic
isolation between input and oUtput.
The design speCifications are: Vi Range, : 20V-24V
Vo
:5V
lo(max)
:4A
flVo
:20mV
With the input and output conditions identified, the deSign
procedure begins with the transformer deSign, followed by
the output filter and snubber circuit design.
2. The duty cycle; ton/T, of the switch is determined by the
volt-second balance of the primary winding.
During ton;
Vi = Lp (fli/TON) - fli = (Vi/Lp) ton
Duringlo!t;
Vi = (Np/Ncl = Lp (fli/toff) - fli = (NpINcl (Vi/~p) toff
SeWn$! fli's equal;
(Vi/Lp) ton = (NpINcl (Vi/Lp)toff
ton/toff = Np/Nc
Since D = ton/T = ton/(ton + toFF)
max. duty cycle = Dmax = (NplNcll [(Np/Ncl + 1)
Dmax = (1.25)1 (1.25 + 1) = 0.56 (56%)
3. The output voltage equations of a forward converter provides the transformer's secondary-to-primary turns ratio:
Vo + Vdlode s: Vi min X Dmax (Ns/Np)
Ns/Np ~ (Vo + Vdiode)1 (Vimin X Dmaxl
NsINp ~ (5.5V)/(20V)(56%) = 0.49
fllet Ns/Np = 0.5
4. Calculate transformer's primary inductance by finding the
maximum magnetizing current (fliLp) that does not allow the
maximum switch current to exceed it's 3 A limit (capital I for
DC current, fli for AC current, and lower case i for total
current):
isw = ipri = iLo' + fliLp
TRANSFORMER DESIGN
1. Using the maximum switch voltage, input voltage, and
snubber voltage, the transformer's primary-to-clamp windings turns ratio is calculated:
Vsw ~ Vimax + Vim~ (Np/Nc) + Vsnubber
Np/Nc s: (Vsw - Vimax - Vsnubber)lVimax
Np/Nc s: (60V - 24V - 5V)/24V = 1.29
fl let Np/Nc = 1.25
The Vsnubber voltage is an estimate of the voltage spike
caused by the transformer's primary leakage inductance.
BasiC Forward Converter
v1e-----t--...---.
IlJ!
10
OO~-1~-1~--~'~+
UI
Lt.l2577
Feedbaok
TUH/11216-1
1002
Using standard inductors, a good practical value to set the
output inductor current (AiLo) to is 30% of the maximum
load current (10). Thus;
where iLo, is the reflected secondary current and AiLP is the
primary inductance current.
iLo' = iLo(Ns/Np)
(iLo reflected to primary)
isw(Pk) = (Io(max)
iLo = ILo ± AiLo/2
ILo = 10 (the load current)
lp=
iLo' = (10 ± AiLo/2)(Ns/Np)
+ AiLo/2)(Ns/Np)
isw = Isw + Aisw
isw(Pk) = iLo'(pk) + AiLP(Pk)
(Io(max) + AiLo/2)(NslNp) + AiLp(Pk)
~
Vprl X At/Ai
=
(VI - Vsst)(ton/AiLp(Pk)
= (Vi(max) - Vsst)(Omax/(AiLp(pk) X f)
= (24V - 0.8V)(0.56/0.7 x 52 kHz)
iLo'(pk) = (lO(max)
isw(pk) =
+ 0.15AiLo)(Ns/Np) + AiLp(pk)
AiLp(Pk) = isw(pk) - (Io(max) + 0.15AiLo)(Ns/Np)
AiLP(pk) = 3A - (4A + 0.15 x 4A)(0.5) = 0.7A
AiLo is the output inductor'S ripple current
lp =
Alet Lp = 350 p.H
357 p.H
OUTPUT FILTER-INDUCTOR
The first component calculated in the design is the output
inductor, using the current-to-voltage relationship of an inductor:
~
VL = Lo (AiLo/ton)
Choosing an inductor ripple current value of 0.310 and a
maximum output current of 4A:
AiLo
= 0.3 (4A) = 1.2A
Ouring Ion;
VL = Vs -VO -yo [whereVs = (Vi - Vsstl(NslNp)1
Thus,
[(Vi -Vsatl(Ns/Npl - Vd - Vol = Lo (AiLo/O) f
Lo = [(Vi - Vsatl(Ns/Np) - Vd - Vol X O/AiLo X f
Lo = [(24V-0.8V)(0.5)-0.5V-5VI56%/1.2AX52 kHz
La = 55p.H
AletLo
= 6Op.H
-----low
TlIH111216-2
0
./
0/
vL
VD
---- ---
-'oN
./
./l
A.
_'1.0
t
'ofF
I
T
t
-
)
TUH111216-3
1003
OUTPUT FILTER-CAPACITOR
Using the current-voltage relationship of inductors,
ts =
Since the output capacitor's curtent is equal to inductor's
ripple current, the output capacitor's value can be found
using the inductor's ripple current. Starting ,with the currentvoltage relationship, the output capacitance is calculated:
t..vo = 1/Co Ii dt
ts = IpRI lL/(VCE - VIN(1 + Np/Ncl)
Calculating for the average leakage inductance current,
ILL(AVE),
ILL(AVE) = IpRI(MAX) (tg)/2T
= IpRI(MAX)2 lLf/2(VCE - VIN(1 + Np/Ncl)
Solving for the snubber resistor;
= aiLo/ 4Co (TR/2)
n/
= (alla 8Co
Co =(aiLo-n/8aVo
However, the equivalent series resistance (ESR) of the capacitor multiplied by the inductor's ripple current creates a
parasitic output ripple voltage equal to:
RS = VRIILL(AVE)
Substituting ILL(AVE) and VR results In,
Rs = 2 (VCE - VIN(1 + Np/Ncl) X
oo -
aiLo = ESRco - 0.3 10
aVo = ESR
This parasitic voltage is usually much larger than the inherent ripple voltage. Hence, the output capacitor parameter of
interest, when calculating the output ripple voltage, is the
equivalent series resistance (the capacitance of the output
capacitor will be determined by the frequency response
analysis). Using a standard-grade capacitor with ESR of
0.050. produces a total output ripple voltage of:
aVo = 0.050. -1.2A ~ 60 mV
To get output ripple voltage of 20 mV or less (as was part of
the design specs) requires a capacitor with ESR of less than
17 mo..
(VCE - VIN - Vo)/(lL (lpRI(MAX»2f)
ChoOSing lL to equal 10% of lp,
Rs = 2 (65V - 24V - 1V) X (65V - 24V(2.25»/
(7 ,...H (3A)2 52 kHz)
= 268.90. ~ 2700.
Using the current-voltage relationship of capacitors,
a VR = (T - tsllc/Cs = (T - tg) VR/RsCs ~ VR/RsCSf
The capacitor Cs equates to,
Cs = VR/RsfaVR
40V/(2700)(52 kHz) 10V = 0.28,...F ~ 0.33,...F
The snubber diode has a current rating of 1A peak and a
reverse voltage rating of 30V.
Cs =
SNUBBER CIRCUIT
A snubber circuit (Cs, Rs, Dsl is added to reduce the voltage spike at the switch, which is caused by the transformer's leakage inductance. It is designed as follows: when the
switch is off,
OTHER COMPONENTS
Diodes, DR and OF, used in the secondary are SA, 30V
Schottky diodes. The same diode type is used for Dc, however a lower current diode could have been used.
A compensation network of Rc and Cc optimizes the regulator's stability and transient response and provides a softstart function for a well-controlled power-up.
VR = VCE - VIN - Vo
VLL = Vo + VR - VIN(NplNcl
Substituting for VR, the voltage across the leakage inductance, VLL, is,
VLL = VCE - VIN(1
IpRI(lLIVu)
Substituting for VLL,
+ NplNcl
The finished circuit is shown below.
5V. 4 A Forward Converter Circuit Schematic
~
+
0.33pr
Ra
Dr
27011.
LM2577-ADJ
--
1o=4A
L
CoUT
470 pr
CoUT2
0.1 pr
VOUT
5V
1\
1.2511.
FB .,:2:...._ _ _ _ _ _ _ _ _ _ _..
GND
3
TLlH/11218-4
1004
r-----------------------------------------------------------I~
f!
.....
~
BOY
3A
30V
TLlH/11216-5
TLlH/1121B-6
SWitch Current
SWitch Voltage
Vertical: 1 Aldlv
Horizontal: 5 ,.../div
Vertical: 10 V/dlv
Horizontal: 5 ,.../dlv
TL/H111216-7
TUH/11218-6
Inductor Current
Output Ripple Voltage
Vertical: 1 AldIv
Horizontal: 5 ,.../dIv
Vertical: 20 mVldlv
Horizontal: 10 ,..s/dlv
IOOmV
A
{
0
f
loomV
mA
200mA
TUH/11216-9
Load Step Response
A: Output Voftage Change, 100 mV/dlv
B: Output Current, 200 mA/dlv
Horizontal: 10 mo/dlv
1005
'.'
"
.: ..
,".
',
",'
~
National Semiconductor
Applicati~n "Note '177 •• ' "
Tom GrOss'
. '''"
LM2577 Three Output,'
Isoiated Flyback Regulator
..
'Jr'
:;-
Many voltage regulator applications ,require multiple outputs, such as a computer's power supply pr a r~ulator used
to meet the voltage, requirements Inside an automobile.
Some of these applications require isolation between the
regulator's input arid qutput for protection 'and separate
ground specifications. Using this. criteria,a LM2577 simple
switch~r flyback regulator, has been designed with multiple
(3) outputs and input-to-output isolation. The three outputs
are: 1) 5V @ 150 mA, 2) 7.5V @ 100 mA, and 3) -7.5V @
70 mAo The table below gives the electrical specifications.
The LM2577 flyback regulator uses a 4N27 optocouplerto
provide a galvaniC isolation. The base resistor of the optacoupler is chosen so that it is large enough (47 kO) to supply a minimum base currant_hlch in tum, demands a lower drive currant to the optocoupler's diode-but not so large
as to produce a pole in the regulator's frequency response.
If the pole's frequency is below the regulator loop's crossover frequency, stability problems will oCcur. Thus, a zero
must be developed, requiring extra circuitry, to compensate
for the extra pole in the loop.
'
An LM385 'Adjustable Voltage Reference, along with resistors 1'101 and 1'102, set the main output voltage to 5V ± 4%
by the equation: Vo = ,1.24V (1+ R02/R01). The LM385
supplies a ,drive (lurrent to the optocoupler (about 10 mAl
proportional to tlie outpui voltage. Due to the high gain of
the LM385, the LM2577's error amplifier is bypassed, and
the feedback signal is fed directly to the compensation pin.
Employing the error amplifier's gain block in the loop would
add with the LM385 gain (the optocoupler's gain is around
unity) to produce a very large overall loop gain. Such a large
loop gain makes the loop too difficult to stabilize-thus the
bYpa~ ~r ~I!II/i~i"~' Wi~h tl:!~: regulator inpOt' v~ltage of
26V arid f!!111C)~ on, all,butput~ tl\e fr~uEil;1CY response has
a crossoVer frequehii1y i lit"1 kHz and,phasemar9in of 90".
The flyback r,~iltor's modem operation is GQntinuous, so
a large primary'induCtance (Lp = 300 "I'll is needed for the
transformer. UslnQ a F'erroxcube 8,12,1=250-308 ,E core, the
primary winding requires about 50 ',tOms., With the turnsratios as they are shown on the schematic and the small
core size, the transformer windings must be wound tightly
so that they fit the cOre windOws. Interlaying the primary
winding betWeen the secondary windings improves the
transformers coupling.
The zener diode circuit (VZ, Rz, RI) is added to provide the
optocoupler !"ansistor with about 20 ,,,A of bi!lS currant, on
top of the'ourrent sourced .from the, compensation pin
(about 7 ~). The isolation resiStQr, between the compensation pin and Ule zener diode, .needs" to be as large as
100 kO, or at start"IlP, t~e compensation pin ,will see too
large a vOI~ge, turning the PQ:IY,r sWitC;h fullY on-;-thus forcing the t.M2577 into' cu~rantUtriit.,~Mso. to ens~re good line
regulatioq.,thl' dynamic Jnipedanceof the"zener, diode must
be very gOod.-? '!" ' ,
, , - . , ' ',: ,
",;'
,
Test da1li for ,'!his regulator fOlloWS tllli!' sctiematic. Since
feedback"is'taken from QUtp\lt 1; its loa,d 'and'llne regulation
are ~r than"thl!t -Of, the 9ther two oil,jputs/which rely on
feedback through the tranS(ormer Couplirig:. The output ripplE! voltage of all three outputs is largely dependent on the
filter capacitors used, !lnd ,could be reduced by the use of
additional high-quality filter capacitors or an additional L-C
filter section.
LM2577 Th.... Output, Isolated F1YbaCk Regulator
, T,i,
'
812-3C8
--1-.....--, ''':':-''-~~-''''-----1-o
VIN
18V-38V 0-....
10k
47011
Vz
4.7V
TL/H/11217-1
1006
r----------------------------------------------------------------,~
ELECTRICAL TEST DATA VI = 16V-36V
Output
Voltages
Line Regulation
(10 = Full Load)
Load Regulation
VOl = 5V
0.2%
0.04%
30 mA-150mA
50mV
V02 = 7.5V
0.3%
3%
20 mA-100 mA
50mV
V03 = 7.5V
0.3%
2%
12mA-70mA
50mV
(VI
=
26V)
Output Ripple Voltage
(TA = 25"C)
A{150 mA
50mA
o
TL/H/11217-3
TLlH/11217-2
Load Transient Response
A. Load Current, 50 mA/dly
B. Output Voltage Change
50 mVldly (AC-Coupled)
Horizontal: 5 ms/dly
Output Ripple Voltage
20 mVIdly (AC·Coupled)
Horizontal: 5 ms/dly
1007
~
.....
.....
National Semiconductor
Application Note 779,
Kerry Lacanette
A Basic Introduction to
Filters~Active, Passive,
and Switched-Capacitor
1.0 INTRODUCTION
Filters of some sort are essential to the operation 'of most
electronic circuits. It is therefore in the interest of anyone
involved in electronic circuit design to have the ability· to
develop filter circuits capable of meeting a given set of
specifications. Unfortunately, many in"the electronics field
are uncomfortable With, the subject, Whethe~due to a lack of
familiarity with ii, qr a rE:lluCtance
grapple with the mathematics involved in a complex filter design.
The frequency-domain behavior of a filter is described mathematically in terms of its transfer function or network
function. This is the ratio of the Laplace transforms of its
output and input signals. The voltage transfer function H(s)
of, a filter can therefore be written as:
H(s) : YOUT(S)
VIN(S)
.
to
This Application Ndte i~ intenci9(lto' serve as a very basic
introduction· to : Sonie' of t,ha mndamental' 'concepts and
terms associated with filters. It will not turn a novice into a
filter designer, but it can ser,ve as a starting point for those
' :
wishing to learn more about filter de~igl).
1.1 Filters apd,Slgnala: What Does a Filter Do?
a
an
In circuit theory, filter is
electrical network/tllat alters
the amplitude and lor phase bharact8tistics of a signal with
respect to frequency. Ideally, a filter will not add new frequencies to the input Signal, nor will it change the component frequencies of that Signal, but it will change the relative
amplitudes of the various frequency components and/or
their phase relationships. Filters are often used in electronic
systems to emphasize Signals in certain frequency ranges
and reject signals in other frequency ranges. Such a filter
has a gain which is dependent on signal frequency. As an
example, consider a situation where a useful signal at frequency f 1 has been contaminated with an unwanted signal
at f2. If the contaminated signal is passed through a circuit
(Figure 1) that has very low gain at f2 compared to fl' the
undesired signal can be removed, and the useful signal will
remain. Note that in the case of this simple example, we are
not concerned with the gain of the filter at any frequency
other than fl and f2. As long as f2 is sufficiently attenuated
relative to f 1, the performance of this filter will be satisfactory. In general, however, a filter's gain may be specified at
several different frequencies, or over a band of frequencies.
Since filters are defined by their frequency-domain effects
on signals, it makes sense that the most useful analytical
and graphical descriptions of filters also fall into the frequency domain. Thus, curves of gain vs frequency and
phase vs frequency are commonly used to illustrate filter
characteristics,and the most widely-used mathematical
tools are based in the frequency domain.
(1)
whereVIN(s} and VOUT(S) arE:! the input,and output signal
voltages and s is the complex frequency variable.
The transfer 'function defines the filter's response to any
arbitrary input Signal, but we are most often concerned with
its effect on continuous sine waves. Especially Important is
the magnitude of the transfer function as a function of frequency, which indicates the effect of the filter on the amplitud~s of sinuspidal signals at various frequencies. Knowing
the transfer function magnitude (or gain) al'each frequency
allows us' to determine how well the filter can distinguish
between signals at different frequencies. The transfer function magnitude versus frequency is called the amplitude
response or sometimes, especially in audio applications,
the frequency response.
Similarly, the phase response of .the filter gives the amount
of phase shift introduced in sinusoidal signals as a function
of frequency. Since a change in phase of a signal also represents a change in time, the phase characteristics of a filter
become especially important when dealing with complex
signals where the time relationships between signal components at different frequencies are critical.
By replacing the variable s in (1) with jCII, where j is equal to
Fr, and CII is the radian frequency (21ft), we can find the
filter's effect on the magnitude and phase of the input signal. The magnitude is found by taking the absolute value of
(1):
(2)
and the phase is:
arg HOCII) = arg VOU~OCII)
VINOCII)
(3)
FILTER
~ Ay=
---...
f,
f2
FREQUENCY
10t =t1
1
G.l@t=t2
INPUT SPECTRUM
OUTPUT
fl
f2
FREQUENCY
OUTPUT SPECTRUM
TUHI11221-1
FIGURE 1. Using a Filter to Reduce the Effect of an Undesired Signal at
Frequency f2. while Retaining Desired Signal at Frequency f1
1008
As an example, the network of Figure 2 has the transfer
function:
H(s) =
Ul
s
s2 + s + 1
tH,! 1
Itf'
the amplitude response curve of this filter is fairly smooth,
there are no obvious boundaries for the passband. Often,
the passband limits will be defined by system requirements.
A system may require, for example, that the gain variation
between 400 Hz and 1.5 kHz be less than 1 dB. This specification would effectively define the passband as 400 Hz to
1.5 kHz. In other cases though, we may be presented with a
transfer function with no passband limits specified. In this
case, and in any other case with no explicit passband limits,
the passband limits are usually assumed to be the frequencies where the gain has dropped by 3 decibels (to J212 or
0.707 of its maximum voltage gain). These frequencies are
therefore called the - 3 dB frequencies or the cutoff frequencies. However, if a passband gain variation (i.e., 1 dB)
is specified, the cutoff frequencies will be the frequencies at
which the maximum gain variation specification is exceeded.
(4)
Your
TL/H/11221-2
FIGURE 2. Filter Network of Example
This is a 2nd order system. The order of a filter is the highest power of the variable s in its transfer function. The order
of a filter is usually equal to the total number of capaCitors
and inductors in the circuit. (A capacitor built by combining
two or more individual capacitors is still one capacitor.)
Higher-order filters will obviously be more expensive to
build, since they use more components, and they will also
be more complicated to design. However, higher-order filters can more effectively discriminate between signals at
different frequencies.
Before actually calculating the amplitude response of the
network, we can see that at very low frequencies (small
values of 5), the numerator becomes very small, as do the
first two terms of the denominator. Thus, as s approaches
zero, the numerator approaches zero, the denominator approaches one, and H(s) approaches zero. Similarly, as the
input frequency approaches infinity, H(s) also becomes progressively smaller, because the denominator increases with
the square of frequency while the numerator increases linearly with frequency. Therefore, H(s) will have its maximum
value at some frequency between zero and infinity, and will
decrease at frequencies above and below the peak.
II'
OA~~~JH-r+~~,
~
I
0.7071
H-+++-I-t-+'Ikl--l
0.' t-+-+L'fl-t-t-t-t-t-N
0.4 t-+11'lr-H-+-i-t-'f-t-i
0.2
II
1fl~+-t-+-t-lC-++-i
0 .......--'-.................--'--'-...........
fe
fh
f)
o
1.0
2.0
FREQUDlCY (RADlANS !SECOIID)
TL/H/11221-3
(a)
To find the magnitude of the transfer function, replace s with
jro to yield:
A(ro)
= IH(s)1 = l-ro2l~ro + 11
,Jro2 + (1
(5)
ro2)2
The phase is:
9(ro)
= arg H(s) = 90· -
ro 2
tan- 1(1 _ ro2)
o
1.0
2.0
FlIEQUDlCY (IWlIANS I SECOND)
(6)
(b)
The above relations are expressed in terms of the radian
frequency ro, in units of radians/second. A sinusoid will
complete one full cycle in 2'11' radians. Plots of magnitude
and phase versus radian frequency are shown in Rgure 3.
When we are more interested in knowing the amplitude and
phase response of a filter in units of Hz (cycles per second),
we convert from radian frequency using ro = 2'11'f, where f is
the frequency in Hz. The variables f and ro are used more or
less interchangeably, depending upon which is more appropriate or convenient for a given situation.
TL/H/11221-5
FIGURE 3. Amplitude (a) and phase (b) response curves
for example filter. Unear frequency and gain scales.
The preCise shape of a band-pass filter's amplitude response curve will depend on the particular network, but any
2nd order band-pass response will have a peak value at the
filter's center frequency. The center frequency is equal to
the geometric mean of the - 3 dB frequencies:
fe = .Jiifh
(8)
where fe is the center frequency
f) is the lower -3 dB frequency
fh is the higher - 3 dB frequency
Another quantity used to describe the performance of a filter
is the filter's "0". This is a measure of the "sharpness" of
the amplitude response. The Q of a band-pass filter is the
ratio of the center frequency to the difference between the
Figure 3(8) shows that, as we predicted, the magnitude of
the transfer function has a maximum value at a specific frequency (roo) between 0 and infinity, and falls off on either
side of that frequency. A filter with this gf-neral shape is
known as a band-pass filter because it passes signals failing within a relatively narrow band of frequencies and attenuates signals outside of that band. The range of frequencies
passed by a filter is known as the filter's passband. Since
1009
-3 dB frequencies (also known as the -3 dB bandwidth).
Therefore:
1.2 The Basic Filter Types
Bandpass
There are five basic filter types (bandpass, notch, low-pass,
high-pass, and all-pass). The filter used in the example in
the previous section was a bandpass. The number of possible bandpass response characteristics is infinite, but they all
share the same basic form. Several examples of bandpass
amplitude response curves are shown In Figure 5. The
curve in 5(a) is what might be called an "ideal" bandpass
response, with absolutely constant gain 'within the passband, zero gain outside the passband, and an abrupt boundary between the two. This response characteristic is impossible to realize in practice, but it can be approximated to
varying degrees of accuracy by real filters. Curves (b)
through (f) are examples of a few bandpass amplitude response curves that approximate 'the ideal curves with varying degrees of accuracy. Note that while some bandpass
responses are very smooth, other have ripple (gain variations in their passbands. Other have ripple in their stopbands as well. The stopband is the range of frequencies
over which unwanted signals are attenuated. Bandpass filters have two stopbands, one above and one below the
passband.
(9)
When evaluating the performance of a filter, we are usually
interested in its performance over ratios of frequencies.
Thus we might want to know how much attenuation occurs
at twice the center frequency and at half the center frequency. (In the case of the 2nd-order bandpass abqve, the attenuation would be the same at both pOints). It is also usually
deSirable to have amplitude and phase response curves
that cover a wide range of frequencies. It is difficult to obtain
a useful response curve with a linear frequency scale if the
desire is to observe gain and phase over wide frequency
ratios. For example, if fa = 1 kHz, and we wish to look at
response to 10kHz, the amplitude response peak will be
close to the left-hand side of the frequency scale. Thus, it
would be very difficult to observe the gain at 100 Hz, since
this would represent only 1% of the frequency axis. A logarithmic frequency scale is very useful in such cases, as it
gives equal weight to equal ratios of frequencies.
Since the range of amplitudes may also be large, the amplitude scale is usually expressed in decibels (20IogIHOCil)I).
Figure 4 shows the curves of Figure S with logarithmic frequency scales and a decibel amplitude scale. Note the improved symmetry in the curves of FIgure 4 relative to those
of FigureS.
+20
+90
-
1
..
"
J
+10
"i
i
o
-3
-10
-20
,.......
+&0
+30
-30
-40
o
-30
~
-60
-90
0.1 0.2
fl fo fh
0.5 1.0 2.0
0.1 0.2 0.5 1.0 2.0 5.0 10
FREQUENCY CRADIANS / SECOND)
5.0 10
FREQUENCY CRADIANS / SECOND)
Cb)
TLlH/II221-4
Ca)
FIGURE 4. Amplitude Ca) and phase Cb) response curves for example bandpass filter.
Note symmetry of curves with log frequency and gain scales.
~1Il ~lLl ~b
FREQUENCY
FREQUENCY
Ca)
Cb)
FREQUENCY
FREQUENCY
Cd)
Ce)
FREQUENCY
FREQUENCY
CI)
FIGURE 5. Examples of Bandpass Filter Amplitude Response
1010
TLlHI11221-7
Cc)
TL/H/II221-8
TL/H/11221-6
Just as it is difficult to determine by observation exactly
where the passband ends, the boundary of the stopband is
also seldom obvious. Consequently, the frequency at which
a stopband begins is usually defined by the requiremel'lts of
a given system-for example, a system specification might
require that the signal must be attenuated at least 35 dB at
1.5 kHz. This would define the beginning of a stopband at
1.5 kHz.
The amplitude and phase curves for this circuit are shown in
Figure 7. As can be seen from the curves, the quantities fe,
flo and fh used to describe the behavior of the band-pass
filter are also appropriate for the notch filter. A number of
notch filter amplitude response curves are shown in Figure
8. As in Figure 5, curve (a) shows an "ideal" notch response, while the other curves show various approximations
to the ideal characteristic.
+20
The rate of change of attenuation between the passband
and the stopband also differs from one filter to the next. The
slope of the curve in this region depends strongly on the
order of the filter, with higher-order filters having steeper
cutoff slopes. The attenuation slope is usually expressed in
dBloctave (an octave is a factor of 2 in frequency) or dBI
decade (a decade is a factor of 10 in frequency).
+10
~-IO
1_20
Bandpass filters are used In electronic systems to separate
a signal at one frequency or within a band of frequencies
from signals at other frequencies. In 1.1 an example was
given of a filter whose purpose was to pass a deSired signal
at frequency f" while attenuating as much as possible an
unwanted signal at frequency f2. This function could be performed by an appropriate bandpass filter with center frequency f,. Such a filter could also reject unwanted signals at
other frequencies outside of the pasSband, so it could be
useful in situations where the signal of interest has been
contaminated by signals at a number of different frequencies.
+10
""
+80
1+
3
:
I
-30
-80
-
-to
Ie
0.1 0.2 0.5 1.0 2.0 5.0 10
FREQUENCY (RADIANS / SECOND)
(10)
TUHI11221-11
(b)
IH
FIGURE 7. Amplitude (a) and Phase (b) Response
Curves for Example Notch Filter
YIN
o
TL/H/11221-10
(a)
o
V---ft'f
1.0.
IJI~
1111.
Lilt.
- specification is
exceeded.
The addition of passband ripple as a parameter makes the
specification process for a Chebyshev filter a bit more complicated than for a Butterworth filter, but also increases flexibility.
11~=1
~
"
lV'
AuAx=o.1 dB
I 1111
i
I
2
~~
1111
f/f.
0.1 0.2 0.5 1.0 2.0 5.0 10
FREQUENCY (RADIANS I SECOND)
(a)
!
I
Flflure 26 shows the step response of 0.1 dB and 0.5 dB
ripple Chebyshev filters of various orders. As with the Butterworth filters, the higher order filters ring more.
TLlH/11221-39
1.2 r--.,...~--...~---r.ln"""""'----'
+10
0
-10
-20
-30
-40
b~j
1.0 1.f'ft.~~II!I_1I
~ ::: I,'
It
I
-50 ~=O.5 dB
-80
r'illllill
-70
I 111111
-80
0.4
rJ:
~
rt: '"'""'II"r=lo-t-=..
T:'.s
I
{j
II
0.2~~--~~+-~--~
li1/ £.L..
~ __LL..l
o......
o 4 8 12 16 20
f/f,
nilE (SECONDS)
0.1 0.2 0.5 1.0 2.0 5.0 10
FREQUENCY (RADIANS / SECONO)
TL/H/11221-40
(b)
0.4,
0.2
1/
'
oU ~
o 4 8
0.1
. 0.2
f/f. 0.5
12 11
nilE (SECONDS)
1.0
(b) 0.5 dB Ripple
FREQUENCY (RADIANS / SECOND)
(c)
TLlH/11221-42
(a) 0.1 dB Ripple
20
TLlH/11221-43
FIGURE 26. Step responses for Chebyshev
low-pass filters. In each case, 1110 = 1,
and the step amplitude Is 1.0.
TLlH/11221-41
FIGURE 25. Examples of Chebyshev amplitude
responses. (a) 0.1 dB ripple (b) 0.5 dB ripple. (c)
Expanded view of passband region showing form of
response below cutoff frequency.
Bessel
, All filters exhibit phase shift that varies with frequency. This
is an expected and normal characteristic of filters, but in
certain instances it can present problems. If the phase increases linearly with frequency, its effect is simply to delay
the output signal by a constant time period. However, if the
phase shift is not directly proportional to frequency, components of the input signal at one frequency will appear at the
output shifted in phase (or time) with respect to other frequencies. The overall effect is to distort non-sinusoidal
waveshapes, as illustrated in Figure 27 for a square wave
passed through a Butterworth low-pass filter. The resulting
waveform exhibits ringing and overshoot because the
square wave's component frequencies are shifted in time
with respect to each other so that the resulting waveform is
very different from the input square wave.
Note that a Chebyshev filter of order n will have n -1 peaks
or dips in its passband response. Note also that the nominal
gain of the filter (unity in the case of the responses in Figure
25) is equal to he filter's maximum passband gain. An oddorder Chebyshev will have a dc gain (in the low-pass case)
equal to the nominal gain, with "dips" in the amplitude response curve equal to the ripple value. An even-order
Chebyshev low-pass will have its dc gain equal. to he nominal filter gain minus the ripple value; the nominal gain for an
even-order Chebyshev occurs at the peaks of the passband
ripple. Therefore, if you're designing a fourth-order Chebyshev low-pass filter with 0.5 dB ripple and you want It
1020
1.2
1.0 I-:~
;
Tl/H/II221-44
FIGURE 27. Response of s 4th-order BuHerworth lowpass (upper curve) to a square wave Input (lower
curve). The "ringing" In the response shows that the
nonlinear phase shift distorts the filtered wave shape.
.-10
0~V/lV
0
2
4
8
8
nIlE (SECONDS)
10
TL/H/11221-47
FIGURE 30. Step responses for Bessel low-pass filters.
In each case, Ctlo = 1 and the Input step amplitude is 1.0.
Elliptic
The cutoff slope of an elliptic filter is steeper than that of a
Butterworth, Chebyshev, or Bessel, but the amplitude response has ripple in both the passband and the stopband,
and the phase response is very non·linear. However, if the
primary concern is to pass frequencies falling within a cer·
tain frequency band and reject frequencies outside that
band, regardless of phase shifts or ringing, the elliptic reo
sponse will perform that function with the lowest-order filter.
The elliptic function gives a sharp cutoff by adding notches
in the stopband. These cause the transfer function to drop
to zero at one or more frequencies in the stopband. Ripple
is also introduced in the passband (see Figure 31 ). An ellip·
tic filter function can be specified by three parameters
(again excluding gain and cutoff frequency): passband ripple, stopband attenuation, and filter order n. Because of the
greater complexity of the elliptic filter, determination of coefficients is normally done with the aid of a computer.
+10
o1--I~~H-l+HfHl
-10 1-+-I-++H+I4~~+-I-++1-I+H
-20 1-H-f-tH1IH--H'++H+Hl
TL/H/I1221-45
FIGURE 28. Response of a 4th-order Bessel low-pass
(upper curve) to a square wave Input (lower curve).
Note the lack of ringing In the response. Except for the
"rounding of the corners" due to the reduction of high
frequency components, the response Is a relatively
undlstorted version of the Input square wave.
The amplitude response of the Bessel filter is monotonic
and smooth, but the Bessel filter's cutoff characteristic is
quite gradual compared to either the Butterworth or Che·
byshev as can be seen from the Bessellow·pass amplitude
response curves in Figure 29. Bessel step responses are
plotted in Figure 30 for orders ranging from 2 to 10.
+10
i
I
-30 ~+H-I+H+f--\l'+H+HII
-40 1---f-+-H1+Htt-+++!1fH11
-50I-++~I1H-~~~
-~I-~~**I-~~~
I-+++H-I-Hl--l--H-I+IJ.II
!
I
""
I
When the avoidance of this phenomenon is important, a
Bessel or Thompson filter may be useful. The Bessel characteristic exhibits approximately linear phase shift with frequency, so its action within the passband simulates a delay
line with a low·pass characteristic. The higher the filter order, the more. linear the Bessel's phase response. Figure 28
shows the square-wave response of a Bessel low-pass filter. Note the lack of ringing and overshoot. Except for the
"rounding off" of the square wave due to the attenuation of
high·frequency harmonics, the waveshape is preserved.
11ME-
VllJr/
1'2
0.8 lUI
0.4 11111
I!I 0.8
-1: t:ttttllq.~
-70 1-+4-++1H+1+-II-I-+II-HII
_.L-..L...L~wu.~~~~
~
fIfo
0.1 0.2 0.5 1.0 2.0 5.0 10
FREQUENCY (RADIANS /SECOND)
-20 I-+-++I+HH--+-H-I\HII
-30 1-+4-1+I+HI-H-++PNI
TUH/11221-48
-~I-+4-1+I+HI-H-~~
FIGURE 31. Example of a elliptic low-pass amplitude
response. This particular filter Is 4th·order with Amax =
0.5 dB and f.lt e = 2. The passband ripple Is similar In
form to the Chebyshev ripple shown In Figure 25(c) •
-50 L-..L...L...J...IoWIJ._L...L.J..U.WJ
0.1 0.2 0.5 1.0 2.0 5.0 10
FREQUENCY (RADIANS / SECOND)
1.5 Frequency Normalization and Denormallzatlon
Filter coefficients that appear in tables such as Table 1 are
normalized for cutoff frequencies of 1 radian per second, or
CtlQ = 1. Therefore, if these coefficients are used to generate a filter transfer function, the cutoff (or center) frequency
of the transfer function will be at Ctl = 1. This is a convenient way to standardize filter coefficients and transfer functions. If this were not done, we would need to produce a
different set of coefficients for every possible center frequency. Instead, we use coefficients that are normalized for
CtlQ = 1 because it is simple to rescale the frequency be-
TL/H/11221-46
FIGURE 29. Amplitude response curves for Bessel
filters of various orders. The nominal delay of each
filter Is 1 second.
1021
havior of a 1 r.p.s. filter. In order to denormalize a transfer
function we merely replace each "s" term in the transfer
function with sl wO, where wO is the deSired cutoff frequency. Thus the second-order Butterworth low-pass function
1
H(s)
sign than passive filters. Possibly their most important atbibute is that they lack lndu&tors, thereby reducing the problems associated with those icomponents. Still, the problems
of accuracy and value spacing also affect capacitors, although to a lesser degree. PerformanOEl at high frequencies
is limited by the gain-bandWidth· product of the amplifying
elements, but within the amplifier's operating frequency
range, the op amp-based: active filter can achieve very good
accuracy, provided that low,tolerance resistors,and capacitors, are used, Active fi~ers will generate noise due to the
amplifying circuiby, but this can be minimized by the use of
low-noise amplifiers and careful circuit design.
.
=(s2 + 2s + 1)
(23)
could be denormalized to have a cutoff frequency of
1000 Hz by replacing s with 8/200071' as below:
.
1
H(s) =
s2
V2s
--:-:c::-;; + - - + 1
4 x 1()671'2
200071'
Figure ':12 shows a few common active filter configurations
(There are several. other useful designs; these
intended
to serve as examples). The second-drtler Sallen-Key lowpass filter in (a) can: be used as a b~ilding block for higherorder filters. By cascading~o or more of these cirCllits,
filters with orders offour
greater can: be built. The two
resistors and two capacitOrs connected to the op amp's
non-inverting input and to Y,N determine the filter'~ cutoff
frequency and affect the Q; the two resistors connected to
the inverting input determine the gain of the filter and also
affect the Q. Since the components that determine gain and
cutoff frequency also affect Q, the gain and cutoff frequency
can't be independently changed.
4 X 106 71'2
S2
+ 2828.~7I's +
are
4 x 106 71':1
3.948 x 107
s2 + 8885.8s + 3.948 x 107
or
If it is necessary to normalize a transfer function, the opposite procedure can be performed by replacing each "s" in
the transfer function with wOS.
APPROACHES TO IMPLEMENTING FILTERS: .
ACTIVE, PASSIVE, A(IID SWITCHED-CAPACITOR
2.1 Passive Filters
The filters used for the earlier exampleS were all made up of
passive components: resistors, capacitors, and inductorS,
so they are referred to as passIVe filters. A passive filter is
simply a filter that uses no amplifying elements (transistors~
operational amplifiers, etc.)'. In this resPect, 'it is the simplest
(in terms of the number of necessary components) implementation of a given transfer function. Passive filters have
other advantages as well. Because they have no active
components, passive filtell! require no Power supplies.
Since they are not restricted by the bandwidth limitations of
op amps, they can work well at very high frequencies. They
can be used in applications involving larger current or voltage levels than can be hal'1dled by active devices. Passive
filters also generate little nosie When compared with circuits
using active gain elements; The noise that they produce is
simply the thermal noise from the resistive. components,
and, with careful design, the amplitude'of this noise can be
very low.
Figures 32(b) and 32(c) are multiple-feedback filters using
one op amp for each second-order transfer function. Note
that each high-pass filter stage in FlflUre 32(b) requires
three capaCitors to achieve a second-order response. As
with the 'Salleti-Key filter, each compOnent value attects
more than one filter characteristic, sO filter perameterS can't
be independently adJusted.
ThE! second:Order state-vanable filter .circuit in Figura 32(d)
reqUires more 9P amps, but provides high-pass, low-pass,
and bandpass outputs from a Single circuit. By combining
the signals from the three outputs, any second-order transfer function can be realized.
When'the center frequency is very low compared to the op
amp's gain-bandwidth product, the characteristics of active
RC filters·are primarily dependent on external component
tolerances and temperature drifts. For predictable results in
critical filter circuits, external components with very good
absolute accuracy and very low sensitivity to temperature
variations must be used, and these can be expensive.
Passive filters have some important disadvantages in certain applications, however. Since they use no active elements, they cannot provide Signal gain. Input impedances
can be lower than desirable, and output impedances can be
higher the optimum for some applications, so buffer amplifiers may be needed. Inductors are necessary for the synthesis of most useful paSSive filter chara,cteristics, and these
can be prohibitivl!ly expensive. if high accuracy (1 % or 2%,
for exampie), small physical, size, or large value arEi· ra:
quired. Standard values of inductors arl! not very 910sely
spaced, and· it is diffcult to find an off-the-shelf unit within
10% of any arbitrary value, so adjustable inductors are often
used. Tuning these to the required values is time-cqnsuming
and expensive when producing I~rge·'quantities of filters.
Futhermore, complex passive filters (higher than 2nd-order)
can be difficult and time-consuming to,design.
When the center freqUency "'!Iltiplied by the filter's Q is
more than a small fraction of the op amp's gain-bandwidth
product, the filter's response will deviate from the ideal
transfer funcijon. The degree of deviation .depends on the
filtar topology; some topologies ·are designed to minimize
the effects of limited op amp bandwidth.
2.3 The Switched-capacitor FIlter
Another type of filter, called the swltched-capacltor filter,
has become widely available in monolithic form during the
last few: years. The switched-capaqjtor ,apProach overcomes'some .of the,problems inheremlnstandard active
filters, 'while 'adding some interesting new capabilities.
Switched-capacitor filters need no external capacitors or inductors, and their cutoff frequencies are set to a typical accuracy of ±0.2% by an external clock frequency. This allows consistent, repeatable filter designs using inexpensive
crystal-controlled oscillators, or filters whose cutoff frequencies are variable over a wide range simply by changing the
clock frequency. In addition, switched-capacitor filters can
have low sensitivity to temperature changes.
2.2 Active Filters
Active filters uSe amplifyingelemerits"'e~pecially op amps,
with resistors and capacitors in their feedbac,k loops, to ,syn~
thesize the desired filter characteristics.' Active fillers can
have high input impedanCe, low output impedance, and virtually any arbitrary gain. They are also usually easier to de-
1022
1
1
~I
YIN
Your
I
-
I
Your
TL/H/11221--50
(b) Multiple-Feedback 4th-Order Active High-Pass Filter.
Note that there are more capacitors than poles.
TL/H/11221-49
(a) Sallen-Key 2nd-Order Active Low-Pass Filter
TL/H/11221-51
(c) Multiple-Feedback 2nd-Drder Bandpass Filter
TL/H/11221-52
(d) Universal State-Variable 2nd-Order Active Filter
FIGURE 32. Examples of Active Filter Circuits Based on Op Amps, Resistors, and Capacitors
state-variable filter in Fl{Jure 32(d). except that the switchedcapacitor filter utilizes non-inverting integrators. while the
conventional active filter uses inverting integrators. Changing the switched-capacitor filter's clock frequency changes
the value of the integrator resistors, thereby proportionately
changing the filter's center frequency. The LMF100 and
MF10 each contain two universal filter blocks. while the
MF5 has a single second-order filter.
Switched-capacitor filters are clocked. sampled-data systems; the input signal is sampled at a high rate and is processed on a discrete-time. rather than continuous. basis.
This is a fundamental difference between switched-capacitor filters and conventional active and passive filters. which
are also referred to as "continuous time" filters.
The operation of switched-capacitor filters is based on the
ability of on-chip capacitors and MOS switches to simulate
resistors. The values of these on-chip capacitors can be
closely matched to other capacitors on the IC. resulting in
integrated filters whose cutoff frequencies are proportional
to. and determined only by. the extemal clock frequency.
Now. these integrated filters are nearly always based on
state-variable active filter topologies. so they are also active
filters. but normal terminology reserves the name "active
filter" for filters built using non-switched. or continuous. active filter techniques. The primary weakness of switched-capacitor filters is that they have more noise at their output&both random noise and clock feedthrough-than standard
active filter circuits.
While the LMF100. MF5. and MF10 are universal filters.
capable of realizing all of the filter types. the LMF40,
LMF60. MF4. and MF6 are configured only as fourth- or
sixth-order Butterworth low-pass filters, with no external
components necessary other than a clock (to set fo) and a
power supply. Fl{Jures 34 and 35 show typical LMF40 and
LMF60 circuits along with their amplitude response curves.
Some switched-capacitor filter products are very specialized. The LMF380 (FI{JUTe 36) contains three fourth-order
Chebyshev bandpass filters with bandwidths and center frequency spacings equal to one-third of an octave. This filter
is designed for use with audio and acoustical instrumentation and needs no external components other than a clock.
An internal clock oscillator can, with the aid of a crystal and
two capacitors. generate the master clock for a whole array
of LMF380s in an audio real-time analyzer or other multi-filter instrument.
Other devices, such as the MF8 fourth-order bandpass filter
(Figure 37) and the LMF90 fourth-order notch filter (Figure
38) have speCialized functions but may be programmed for
a variety of response curves using external resistors in the
case of the MF8 or logic inputs in the case of the LMF90.
National Semiconductor builds several different types of
switched-capacitor filters. Three of these. the LMF100. the
MF5. and the MF10. can be used to synthesize any of the
filter types described in Section 1.2. simply by appropriate
choice of a few external resistors. The values and placement of these resistors determine the basic shape of the
amplitude and phase response, with the center or cutoff
frequency set by the external clock. Figure 33 shows the
filter block of the LMF100 with four external resistors connected to provide low-pass. high-pass. and bandpass outputs. Note that this circuit is similar in form to the universal
1023
I~
YIN
~M"'+-"'-'''''''''
YLP
LOW-PASS
OutPUT
TlIH/11221-53
FIGURE 33. Block diagram of a second-order universal switched-capacitor filter, Including external resistors
connected to provide High-Pass, Bandpasa, and Low-Pass outputs. Notch and All-Pass responses can be obtained
with different external resistor connections. The center frequency of this filter Is proportional to the clock frequency.
Two second-order filters are Included on the LMF100 or MF10.
J1fL
+fN
-fN
CIJ(
Y+=fN
2
7
LMF40
I
v'"=-fN
v'" =- fN
6
4
5
-
Vour
~
TL/H/11221-54
(a)
, TlIH/11221-55,
(b)
FIGURE 34. TYpicalLMF40 and LMF60 application circuits. The Circuits shown operate on ± 5V power supplies a,nd
accept CMOS clock levels. For operation on single supplies or with TTL clock levels, see Sections 2.3 and 2.4. '
+10
0
~
-to
!
I
+10
,
0
-20
!
I
~'
-10
"'-
-10
-40
-50
-20
-10
-40
-50
-60
-60
0.1 0.2
0;5 1.0 2.0
5.0 10
0.1 0.2
FREQUENCY (1/f..W
(a) LMF40
0.5 1.0 2.0
5.0 10
FREQUENCY (1/f..W
TL/H/11221-56
(b) LMF60
FIGURE 35. Typical LMF40 and LMF60 amplitude response curves.
The cutoff frequency has been normalized to 1 In each case.
1024
TlIH/1 1221 -57
+5V
1
16
6
r-
10.1 }.IF
-5V
-
LMF380
~
~~
-
BANDPASS 1
11
5
!eLK
50
BANDPASS 2
12
4
fCLK
62.5
f02 =
IN3
5:
--
30 pF
3OPF
ClK
au T
fCLK
fOl =
IN2
10
DIVIDER {+2}
1:
71 t.4HZ+
8
0.1 }.I F~
INI
OSCllLATOR/
lEVEL SHIFTER
BANDPASS 3
14
3
fCLK
80
f03=
CUT1
CUT2
CUT3
TL/H/11221-58
(a)
10
0
S
~
I I I
II
-10
z
~
\
1\ 1\ \
/\1\ \
'I / A
\
/ IL I ."- I~ .\
-20
1/ 1/ /
-30
~
I V
\ \
,
-40
5k
10k
20k
4Dk
FREQUENCY (Hz)
TL/H/11221-59
(b)
FIGURE 36. LMF380 one-third octave filter array. (a) Typical application circuit for the top audio octave. The clock Is
generated with the aid of the external crystal and two 30 pF capacitors. (b) Response curves for the three filters.
1025
...--
r--~II,------------
VIN-W_-.....- .....w,..........--.
Your
+5V
-5V
TL/H/11221-60
FIGURE 37. The MF818 a fourth-order bandpa88 filter. Three external resl8tor8 determine the filter function.
A five-bit digital Input 8et8 the bandwidth and the clock frequency determlne8 the center frequency.
12T_----t
IN_...
J--~:'-"'-OUT
10
Lt.tF'90
+5V
14
+2, +598, +718
fC = 60 Hz
TLlHI11221-61
(a)
10.000
..........
"'"
,/
\
\ I
\ II
~
./
...-
/
v
-00.000
45.000
75.000
Frequency (Hz)
TL/H/11221-62
(b)
FIGURE 38. LMF90 fourth-order elliptic notch filter. The clock can be generated externally, or Internally with
the aid of a cry8tal. Using the circuit a8 8hown In (a), a 60 Hz notch can be built. Connecting pin 3 to V + yleld8
a 50 Hz notch. By tying pin to ground or V + , the center frequency can be doubled
or tripled. The re8ponse of the circuit In (a) 18 8hown In (b).
1026
:..
z•
.....
.....
LMF120
INI
11
IN2
IN3
.".
vGND
16
a
c::J
B c::J
CD
XTAL 1
OSCILLATOR/
LEVEL SHinER
XTAL2
DIVIDER CHAIN
(+1,2,., '" 256)
EJ B E3>
EJ EJ ~
B
B ~
CLKOUT
5
4
3
OUT1
OUT2
OUT3
TLlHI11221-63
FIGURE 39. Block diagram of the LMF120 customlzable swltched-capacltor tllter array.
The Internal circuit blocks can be Internally configured to provide up to three tllters with a totel
of 12 poles. Any unused circuitry can be disconnected to reduce power consumption.
Finally, when a standard filter product for a spepific applica·
tion can't be found, it often makes sense to use a cell-based
approach and build an application-specific ,ilter. An example
is the LMF120, a 12th-order customizable switched-capacitor filter array that can be configured to perform virtually any
filtering function with no external COmponents. A block diagram of this d~ce is shown in F/fJur9,39. The three input
sample..and-hold circuits, six second-order filter blocks, and
three output buffers can be interconnected to build from One
to three filters, with a total order of twelve.
Cost: No single technology is a clear winner here. If a single-pole filter is all that is needed, a passive RC network
may be an ideal solution. For more complex deSigns,
switched-capacitor filters can be very inexpensive to buy,
and take up very little expensive circuit board space. When
good accuracy is necessary, the pasSive components, especially the capacitors, used in the discrete approaches can
be quite expensive; this is even more apparent in very compact deSigns that require surface-mount components. On
the other hand, when speed and accuracy are not important
concerns, some conventional active filters can be built quite
cheaply.
2.4 Which Approach Is Beat-Actlve, Paaalve, or
Swltched-capacltor?
Noise: Passive filters generate very little noise Oust the thermal noise of the reSistors), and conventional active filters
generally have lower noise than switched-capacitor ICs.
Switched-capacitor filters use active op amp-based integrators as their basic internal building blocks. The integrating
capacitors used in these circuits must be very small in size,
so their values must also be very small. The input reSistors
on these integrators must therefore be large in value in order to achieve useful time constants. Large resistors produce high levels of thermal noise voltage; typical output
noise levels from switched-capacitor filters are on the order
of 100 P.V to 300 p.Vrms over a 20 kHz bandwidth. It is
interesting to note that the integrator input resistors in
switched-capacitor filters are made up of switches and capacitors, but they produce thermal noise the same as "real"
resistors.
Each filter technology offers a unique set of advantages and
disadvantages that makes it a nearly ideal solution to some
filtering problems and completely unacceptable in other applications. Here's a quick look at the most important differences ·between active, passive, and switched-capacitor filters.
Accuracy: 8witched-capacitor filters have the advantage of
better accuracy in most cases. Typical center-frequency accuracies are normally on the order of about 0.2% for most
switched-capacitor ICs, and worst-case numbers range
from 0.4% to 1.5% (assuming, of course, that an accurate
clock is provided). In order to achieve this kind of precision
using passive or conventional. active filter techniques requires the use of either very accurate resistors, capacitors,
and sometimes inductors, or trimming of component values
to reduce errors. It is possible for. active or passive filter
designs to achieve better accuracy than switched-capacitor
circuits, but additional cost is the penalty. A resistor-programmed switched-capacitor filter circuit can be trimmed to
achieve better accuracy when necessary, but again, there is
a cost penalty.
(80me published comparisons of switched-capacitor vs. op
amp filter noise levels have used very noisy op amps in the
op amp-based designs to show that the switched-capacitor
filter noise levels are nearly as good as those of the op
amp-based filters. However, filters with noise levels
1027
~r-------------------------------------------------------------------~
.....
!:_
at least 20 dB below those of most switched-capacitor designs can be built using low-cost, low-noise op amps such
as the LM833.)
ticular application depends on the application itself. Most
switched-capacitor filters have clock-to-center-frequency
, ratios of 50:1 or 100: 1, so the frequencies at which aliasing
begins to occur are 25 or 50 times the center frequencies.
When there are no signals with appreciable amplitudes at
frequencies higher than one-half the clock frequency, aliasing will not be a problem. In a low-pass or bandpass application, the presence' of signals at frequencies nearly as high
as the clock rate will often be acceptable because although
these signals are aliased, they are reflected into the filter's
stopband and are therefore attenuated by the filter.
Although switched-capacitor filters tend to have higher
noise levels than conventional active filters, they still,
achieve dynamic ranges on the order of 80 dB to 90 dBeasily quiet enough for most applications, provided that the
signal levels applied to the filter are large enough to keep
the signals "out of the mud".
Thermal noise isn't the only unwanted quantity that
switched-capacitor filters inject into the signal patl). Since
these are clocked devices, a portion of the clock waveform
(on the order of 10 mV p-p) will make its way to the filter's
output. In many cases, the clock frequency is high enough
compared to the signal frequency that the clock feedthrough can be ignored, or at least filtered with a passive
RC network at the output, but there are also applications
that cannot tolerate this level of clock noise.
When aliasing is a prol:!lem, it can sometimes be fixed by
adding a Simple, passive RC low-pass filter ahead of the
swltched-capacitor filter to remove some of the unwanted
high-frequency signals. This is generally effective when the
switched-capacitor filter is' performing a low-pass or bandpass function, but it may not be practical with high-pass or
notch filters because the passive anti-aliasing filter will reduce the passband width of the overall filter response.
Offset Voltage: Passive filters have no inherent offset voltage. When a filter is built from op amps, resistors and capacitors, its offset voltage will be a simple function of the
offset voltages of the op amps and the dc gains of the various filter stages. It's therefore not too difficult to build filters
with sub-millivolt offsets using conventional techniques.
Switched-capacitor filters have far larger offsets, usually
ranging from a few millivolts to about 100 mV; there are
some filters available with offsets over WI ObViously,
switched-capacitor filters are inappropriate for applications
requiring dc precision unless external circuitry is used to
correct their offsets.
Design Effort Depending on system requirements, either
type of filter can have an advantage in this category, but
switched-capacitor filters are generally much easier to design. The easiest-to-use devices, such as the LMF40, require nothing more than a clock of the appropriate frequency. A very complex device like the LMF120 requires little
more design effort than simply defining the desired performance characteristics. The more,difficult design work is done
by the manufacturer (with the aid of some specialized software). Even the universal, resistor-programmable filters like
the LMF100 are relatively easy to design with. The procedure is made even more user-friendly by the availability of
filter software from a number of vendors that will aid in the
design of LMF100"type filters. National Semiconductor provides one such filter software package free of charge. The
program allows the user to specify the filter's desired performance in terms of cutoff frequency, a passband ripple,
stopband attenuation, etc.; and then determines the required characteristics of the second-order sections that will
be used to build the filter. It also computes the values of the
external resistors and produces amplitude and' phase vs.
frequency data.
Frequency Range: A single switched-capacitor filter can
cover a center frequency range from 0.1 Hz or less to
100 kHz or more. A passive circuit or an op amp/resistor/
capacitor, circuit can be designed to operate at very low
frequencies, but it will require some very large, an~ probably
expensive, reactive components. A fast operational amplifier is necessary if a conventional active filter is to work properly at 100 kHz or higher frequencies.
Tunability: Although a conventional active or passive filter
can be designed to have virtually any center frequency that
a switched-capacitor filter can have, it is very difficult to vary
that center frequency without changing the values of sever,
al components. A switched-capacitor filter's center (or cutoff) frequency is proportional to a clock frequency and can
therefore be easily varied over a range of 5 to 6 decades
with no change in external circuitry. This can be an important advantage in applications that require multiple center
frequencies.
Where does it make sense to use a switched-capacitor filter
and where would you be better off with a continuous filter?
Let's look at a few types of applications:
Tone Detection (Communications, FAXs, Modems, BIomedical Instrumentation, Acoustical Instrumentation,
ATE, etc.): Switched-capacitor filters are almost always the
best choice here by virtue of their accurate center frequen"
cies and small board space requirements.
Component Count/Circuit Board Area: The switched-capacitor approach wins easily in this category. The dedicated, single-function monolithic filters use no external components other than a clock, even for multipole transfer functions, while passive filters need a capacitor or inductor per
pole, and conventional active approaches normally require
at least one op amp, two resistors, and two capacitors per
second-order filter. Resistor-programmable switched-capacitor devices generally need four resistors per second-orderfilter, but these usually take ,up less space than the components needed for the alternative approaches.
Noise Rejection (Line-Frequency Notches for Blomedical Instrumentation and ATE, Low-Pass Noise Filtering
for General Instrumentation, Anti-Alias Filtering for
Data Acquisition Systems, etc.): All of these applications
can be handled well in most cases by either switched-capacitor or conventional active filters. Switched-capacitor filters can run Into trouble if the signal bandwidths are high
enough relative to the center or cutoff frequencies to cause
aliasing, or if the system requires dc' precision. Aliasing
problems can often be fixed easily with an external resistor
and capaCitor, but if dc precision is needed, it is usually best
to go to a conventional active filter built with precision op
amps.
Aliasing: Switched-capacitor filters are sampled-data devices, and will therefore be susceptible to aliasing when the
input Signal contains frequencies higher than one-half the
clock frequency. Whether this makes a difference in a par-
1028
Controllable, Variable Frequency Filtering (Spectrum
Analysis, Multiple-Function Filters, Software-Controlled
Signal Processors, etc.): Switched·capacitor filters excel
in applications that require multiple center frequencies because their center frequencies are clock-controlled. Moreover, a single filter can cover a center frequency range of 5
decades. Adjusting the cutoff Irequency of a continuous filter is much more difficult and requires either analog
switches (suitable for a small number of center frequencies), voltage-controlled amplifiers (poor center frequency
accuracy) or DACs (good accuracy over a very limited control range).
Audio Signal Processing (Tone Controls and Other
Equalization, All-Pass Filtering, Active Crossover Networks, etc.): Switched-capacitor filters are usually too noisy
for "high-fidelity" audio applications. With a typical dynamic
range of about 80 dB to 90 dB, a switched-capacitor filter
will usuailly give 60 dB to 70 dB signal-to-noise ratio (assuming 20 dB of headroom). Also, since audio filters usually
need to handle three decades of signal frequencies at the
same time, there is a possibility of aliasing problems. Continuous filters are a better choice for general audio use, although many communications systems have bandwidths
and SIN ratios that are compatible with switched capaCitor
filters, and these systems can take advantage of the tunability and small size of monolithic filters.
1029
....
~ r---------------------------------------------------------------------------~
National Semiconductor
Application Note 813
Topics on Using
;I
II(
the LM6181-A New
Current Feedback Amplifier
Use your imagination . .. that's what jazz is al/ about. If you
make a mistake, make it loud so you won't make it next
time. -Art Blakey
INTRODUCTION
The high-speed demonstration board can be used to 'either
examine the time domain, or frequency domain. However,
the discussion will focus on using this b,oard for the purpose
of compensating the time domain response of the LM6181
for popular applications.
High-speed analog system design can often be a daunting
LM6181 Closed-Loop
Frequency Response
Vs = ± 15V; R, = 8200;
RL= 1kO
task. Typically, after the initial system definition and the design approach is established, the task of component selection commences. Unfortunately, simple reliance on data
sheet parameters provides only a partial feel for the device's actual operating nuances. This is unfortunately true
no matter how complete a high-speed amplifier data sheet
is written. Only by experimenting i.e., spending some time
on the bench with the part, will the requisite experience be
obtained for reliably using high-speed amplifiers. The highspeed demonstration board, described herein, can be effectively used to accelerate this process. In developing the
LM6181 application program, the key focus areas for making high-speed design a little easier included:
• DeSigning a product that is more forgiving-for example
it can directly drive backmatched cables (a heavy de
load), and significant capacitive loads (without oscillating).
• Developing a high-speed demonstration board that is
easily reconfigurable for either inverting or non-inverting
amplifier operation.
• Incorporate a highly accurate SPICE macromodel of the
LM6181 into National's macromodeling library. This macromodel can be used in conjunction with bench results
to more quickly converge on a reliable high-speed design.
Ahhough it may seem that evaluation of high-speed circuit
operation can be more quickly performed with computer
simulation, full bench evaluation can not be supplanted. By
integrating both of these complementary tools, the cycle
time from component selection to finalized design can be
reduced.
SOME BACKGROUND INFORMATION ON THE LM6181
The LM6181 is a high-speed current feedback amplifier with
typical slew rates of 2000 VI p.s, settling time of 50 ns for
0.1 %, and is fully specified and characterized for ± 5V, and
± 15V operation. Current feedback operational amplifiers,
like the LM6181, offer two Significant advantages over the
more popular voltage feedback topology. These advantages
include a bandwidth that is relatively independent of closedloop gain (see Figure 1), and a large signal response that is
closer to ideal. "Ideal" specifically means that the large
signal response is not overtly dominated by non-linear slewing behavior (Ref. 1), as is typically found for vohage feedback amplifiers. An obvious consequence is dramatic improvement in distortion performance versus the signal amplitude, and settling time.
OdB
f--
J.Ay1111111--+-tT'H::f+H---l
= -5
f--
-IA~ IJ I~ 111-++l+H+M-l
1--+-"'1"IT'
It-I'lltH
11111I'I'-"t-+.........++tI-\'H
11111111
1M ~
10M
l\
100M
fREQ.
TUH/II408-1
FIGURE 1. Unlike voltage feedback amplifiers which
directly trade bandwidth tor gain, current feedback
amplifiers provide conSistently wldeband performance
regardless of moderate closed-loop gain levels.
Examples of this includes driving cables, dealing with capacitive loads, and generally obtaining a user specified fidelity to the pulse response. Essentially, the demonstration
board simplifies the evaluation of high speed operational
amplifiers in either the inverting, or the non-inverting circuit
configurations. Appendix A includes the board schematic
with the associated configuration options. Layout of the
board included a host of mandatory high speed design considerations. These principles have been summarized in Appendix B (also see Ref. 2 to 4).
A popular application for high speed amplifiers includes driving backmatched cables as illustrated in Figure 2. Due to
loading and typical bandwidth requirements this particular
application places heavy demands on an amplifier. The
LM6181 output stage incorporates a high-current-gain output stage that provides a lower output impedance Into
heavy loads, such as 1000 and 1500. This enhances the
amplifier's ability to drive backmatched cables (±10V, into
1000) since the internal current drive to the amplifiers output stage is used more efficiently. Additionally, the benefits
of the current feedback topology of the LM6181 allows for
wideband operetion of 100 MHz, even when configured in
closed-loop gain configuration of + 2.
1030
+15V
"'Oo..I.~--.~F
son
RG-58 COAX.
)!~~~r--~~--e::::)--ir---o VOUT
~F
-15V
820n
son
Rt
820n
TLfHfl1408-2
FIGURE 2. Backmatchlng of a cable Is a clean way of terminating
the source to the characteristic Impedance. The LM6181 can deliver
± lOY Into the resulting dc load of 1000, at 100 MHz, typically.
EXPERIMENTING WITH THE TIME DOMAIN
Some consideration needs to be addressed for the test signal chosen to evaluate the transient response of a linear
system. By the properties of Laplace transforms, if a unit
impulse input is used and the measured output response is
integrated, the result of applying an inverse Laplace transform will yield the systems frequency response. This approach is not typically useful since pulse generators do not
generate impulses and the integration becomes unduly
complex. Additionally, this technique does not serve to establish an intuitive feel. Alternatively, if a slowly time-varying
input signal is used as the test input, the high-frequency
components in the system are not significantly excited. The
step response often provides a meaningful evaluation of
amplifier performance, and represents a more practical signal. Other advantages of using a step response is that it
directly provides the dc gain, and the high-frequency nature
of the step excites the high-frequency poles in the amplifier's system transfer function.
TLfHfll408-3
FIGURE 3. Always start the dynamic characterization of
high-speed amplifiers with an Input signal that
maintains adequate speed, with little aberatlon.
Measuring the Input Signal, from a fast pulse generator,
(a Hewlett-Packard 8082A pulse generator was used),
also provides a check of correct terminations of the
probe-oscllloscope combination.
Probably the largest area of difficulty in high-speed deSign is
when amplifiers drive capacitive loads. Unfortunately, many
amplifiers 01) the marketplace are specified to handle a
maximum of a meager 20 pF of capacitive load before oscillation occurs. This maximum limitation equivalently implies
that the amplifiers pulse response will be sensitive to typical
oscilloscope capacitance-the probe becomes an integral
part of the overall circuit, which makes meaningful judgements on measurements very difficult.
Although direct capacitive loading should typically be minimized in general practice, Figure 4 illustrates that for moderate values of capacitive load, due to the oscilloscope probe,
the LM6181 is still very well behaved. Figure 5 illustrates the
simulation using SPICE and the LM6181 macromodel. The
LM6181 SPICE macromodel has superb ac and transient
response characteristics. For availability information concerning the complete macromodeling library, including the
LM6181, along with an outline of the model's capabilities,
refer to Appendix C.
When evaluating step response performance of wideband
amplifiers it is imporlant to use a pulse generator that provides a sufficiently fast risetime. A step response, in relation
to the system that is being evaluated, must have a risetime
relationship of:
0.35
lrisetime
< (Bandwidth of Amplifier)
Therefore, evaluating the step response of the LM6181 amplifier, where the typical bandwidth for gains of + 2 is
100 MHz, will require a step input Signal with a maximum
risetime of 3.5 ns. Since there will always be a cerlain
amount of risetime degradation due to the oscilloscope
probe and the OSCilloscope, use the same measurement
equipment for evaluating both the integrity of the input signal and for measuring the output response of the system.
Flflure 3 illustrates a satisfactory input pulse for evaluating
the LM6181.
1031
....
cp
~
r-----------------~----------------------------------------------~----~--------,
COMPENSATING THE PULSE RESPONSE
~
Degradation in the phase margin, due to direct capacitive
loading of high-speed amplifiers can potentially induce oscillation. The output impedance of the amplifier, coupled with
the load capacit!lnce, forms a lag network in the loop transmission of the amplifier. Since this network delays the feedback, phase. margin is reduced such that even when a system is not OSCillating excessive ringing can occur, as illustrated in Figuf9 6 where the capacitive load is 48 pF.
A direct solution to reducing the ringing for driving capacitive
loads is to indirectly drive the load i.e., iSolate the load with
a real impedance, such as a moderately small value of resistance. In Figure 7 a 470 resistor was used to isolate the
capacitor's complex impedance from the amplifier's output,
·thereby preserving the amplifier's phase margin. An obvious
tradeoff exists between taming the time domain response,
and maintaining the amplifier's bandwidth, since this form of
compensation directly slows down the amplifier's response.
TL/H/11408-4
FIGURE 4. Output response of a real LM6181, Av = + 2,
Rf = RQ = 8200. Output load Is oscilloscope probe,
Tektronix P6106A,10 MO, 8.7 ·pF.
800mV
~
= Rg = 820n
~ ~
..
.,
400,mV
V
OmV
IJ
-400 mV
.,
-800 mV
On.
" V(6)
20n.
40 no
60no
80no
100n~
Time
TL/H/11408-5
FIGURE 5. Simulated output response of .,the circuit In Figure 3 using the LM6181 macromodel. See Appendix C for
more Information regarding tt,e LM6181 macromodel and National's Macromodeillbrary.
1032
r--------------------------------------------------------------------,~
For general applications of the LM6181, the suggested
feedback resistance, RI, is 8200. However, a characteristic
unique to current-feedback amplifiers is that they will have
different bandwidths depending on the feedback resistor RI.
This results in current-feedback amplifiers maintaining a net
closed-loop bandwidth that remains (this is of course an
approximation; second order effects do take their toll, of
course) the same for moderate variations of closed-loop
gain. This feature of current feedback amplifiers actually
makes them relatively easy to compensate. By simply scaling the gain setting and the feedback impedance, the appropriate bandwidth can be obtained at the desired value of
closed-loop gain. Figure 8 wss cut from the LM6181 data
sheet, and describes this relationship.
TL/H/11408-6
FIGURE 6. Direct capacitive loading will reduce the
phase margin and resulting pulse fidelity of any
amplifier. A pole Is created by the combination of the
op amp's output Impedance and the capacitive load.
This results In delaying the feedback or loop
transmission. In this example the LM6181 is directly
driving a 48 pF load. High-speed current-feedback
amplifiers can handle capacitive loads, and maintain
pulse fidelity, by Indirectly driving them. This Is
Illustrated in Figure 7.
TL/H/11408-9
Bandwidth vs RF and Rs
Av= -1,RL= 1kO
+15V
120
100
~.
,
\
80
820/1
40
,
20
Vs = :l:5V
\
820/1
TLlH/1140B-7
1\ Vs = :t15V
1\
r\.
~,
o I
0.5
I
1.0
1.5
2.0
2.5
3.0
3.5
RI at Rs (kn)
TL/H/11408-10
VOUT
FIGURE 8. By scaling both RF and Rs the closed-loop
gain stays constant but the bandwidth changes.
A practical application of using altered feedback values for
compensating the LM6181 when driving a 100 pF capacitive
load is illustrated in Figure 9. By reducing the open-loop
bandwidth of the amplifier, the resulting degradation of
phase margin is reduced, thereby improving the pulse response fidelity.
TLlH/11408-B
FIGURE 7. A small resistor can be used,
such as 470, at the output of the amplifier
to Indirectly drive capaCitive loads.
1033
f
w
r---------------------------------------------------------------------------------,
....
Inverting Gain
cp
~
z
Frequency Response
Vs = ± 15V; Ay = -1;
RF': 8200
>----1---...
oC
- - 0 VOUT
R.
1.2kn
1.80 0
.......
'>
Ci
1.2 len
13~0
~
"-
'"
."
e
TL/H/11408-11
z
...~
45°'
(10
OdS
'\ = lk
"
....
0
Your
1M
= 150
= 100
II
10M
'Ei'
90~' ~
e
t;:
:;:
--
CI)
..~
~
::I:
\\
100M
FREQ. (a)
TLlH/11408-13
Non-Inverting Gain
Frequency Response
Vs = ±15V;Av = +2;
R, = 8200
TLlH/11408-12
FIGURE 9. Normally, if RF = Rs = 8200, the LM6181
would OSCillate with 100 pF of capacitive load. In this
example the feedback, RF and Rs values are scaled to
1.2 kO so that the closed-loop gain Is Ay = + 2, but the
open-loop band width decreases, maintaining adequate
phase margin.
An often overlooked faclor in dynamically understanding
high-speed amplifiers is the effect that dc loading has on
amplifier speed. When driving backmatched cables, for example, the Thevenin equivalent load is usually either 1000,
or 1500. Figure 10 (from the LM6181 data sheet) provides
bandwidth versus dc load information. Figure 11 illustrates
the step response for the LM6181 in a gain of + 2, with a dc
equivalent load of 1000. When the step response is compared against Figure 4 it is obvious that dc loading will affect
amplifier bandwidth. Additionally, since amplifier dynamics is
also affected by supply voltage, the LM6181 is fully characterized for both ± 5V and ± 15V operation.
00
"'"
'>
Ci
"-
'"
45 0
~
90 0
."
e
z
~
135 0
~
!fl
""
e"
180 0 t;:
6dS
x
...
...
CI)
1\ = lk
"~
= 150
'\ = 100
RL
0
>
I III
1M
10M
r-
~
!:.!
if
100M
FREQ. (b)
TL/H/11408-14
Inverting Gain
Frequency Response .
Vs = ±15V;Ay = -10;
RF = 8200
~
i"'III
z
...~
~
g
20dS
'\ = lk--:
'\ = 150
1\ = 100
I I Ir
1M
10M
~
~
100M
FREQ. (e)
TLlH/11408-15
FIGURE 10. DC loading of a high-speed amplifier will
affect bandwidth. (Refer to the LM6181 data sheet for
± 5V bandwidth vs loading characteristic curves.)
1034
r--------------------------------------------------------------------,~
!;
.....
w
TLlHI11408-16
TLlH/11408-18
FIGURE 11. Output step response of LM6181 when
driving backmatched cables. Comparing this step
response to F/gure 4 Illustrates the bandwidth
reduction due to the 1000 resistive load.
FIGURE 13. Resulting pulse response for LM6181 using
Raarla. = 8800, AV = + 2, Rs = RF = 8200, CLOAD ::::
8.7 pF. Compare this reaponse with Figure 4, overshoot
and ringing has been dramatically reduced.
COMPENSATING NON-INVERTING CF AMPLIFIERS
Often, for the inverting amplifier configuration, simply scaling the feedback and gain setting resistor is the easiest way
of compensating for peaking and overshoot in the step response. The non-inverting configuration, however, can alternatively be compensated by adding a series input resistor,
as shown in Figure 12. This resistor, in combination with the
input and stray input capacitances of the amplifier bandwidth limit the input step response, and accordingly reduce
peaking in the output response. This effect is equivalent to
increasing the risetime of the leading edge of the input pulse
(some pulse generators have this adjustment).
SNAKE OIL AND SPICE MACROMODELS
CURE ALL EVILS
Not all amplifier macromodels are created equal. For example, driving capacitive loads with high-speed amplifiers is a
good way of evaluating and comparing op-amp macromodels. Capacitive loading directly affects the loop dynamics
of a closed-loop amplifier system. And since this capacitive
load interacts with the output impedance of the amplifier to
delay the feedback (or loop transmission), the phase margin
is reduced, as stated earlier.
Simulating high-speed systems when driving capacitive
loads places a demand on the amplifier'S macromodel. Constructing an accurate macromodel is not simple. Unfortunately, parameterized models (an efficient method of using
a computer to generate many inaccurate models per a typical workday) lack the extensive software testing and bench
measurement analysis required for sophisticated simulation
work. The amplifier's output stage, the frequency response,
and the input parasitic structures need to be carefully measured on the bench, then accurately mimicked in the macromodel. The moral is to be aware, and:
V,N o--Wlr-......----''---t
ALWAYS TEST YOUR MACROMODEU
TLlH/11408-17
f_
3 dB
of v::::
Compare the similarity between results in Fl{}ure 14 with the
bench results of Figure 6. Increased confidence in using a
specific high-speed amplifier macromodel can be obtained
by corresponding bench results of driving capacitive loads
with simulation results.
Driving reactive loads, such as capacitive loads, can be
used not only to indicate limitations for the associated
SPICE macromodel, but also to reveal some of the amplifier's high-speed personality. Never assume that a macromodel of an operational amplifier includes characteristics that
are germane to your particular simulation.
1
2,.. (CoptlonaJ + 3 pF) • R _
FIGURE 12. Peaking and ringing for non-Inverting
amplifier configurations can be reduced by adding a
series Input reSistor, R..rlee' This realstor Interacts with
the amplifiers Input capaCitance to provide a low pass
bandwidth limit for the Input pulse. If more bandwidth
reduction Is required Coptlonal can be used.
SUMMING THINGS UP
The focus has been on high-speed analog design methodology, as opposed to generating a plethora of varied application circuits. By establishing a foundation-understanding
the amplifier, referring to the typical characterization curves,
using correct high-speed layout techniques, knowing the
SPICE macromodels limitations, and adopting some basic
compensation techniques, a large fraction of everyday highspeed design challenges can be addressed confidently.
1035
....
~ r-----------------------------------------------------------------------------~
i
'1100 mV
"
-.:'
lit = I!g = 820n
G..OAD =48 pf
".
.
.,
400mV
','
An
IV
OmV
f\
~
V
v
--
"-
.-
-400 mV
-800 mV
On.
• V(6)-.4
SOn.
100 ns
150 ns
200
n.
Time
TLfHI11408-19
FIGURE 14. Simulation of LM6161 step response with Av =
1036
+ 2, RF =
Rs = 8200, and Croad = 48 pF.
Appendix A
C4
(Not. 2)
(R,)
R4
V+
+ ~OPF
JI
V
IN
(Not. I)
~
20011
0--"\("'''-",)_8_20_1I....- ._ _~~1~--1~':'0.01 pF
J2
':'
R5
(Not. 4)
R6
:>:......------~-C)-4'1191\j.9"'ft-C.....-..:o) Your
: -...-o--IIM..---o-----c,....~
R9
.....-_="~:'i_-_II£!.':'
0.01 pF
r:.J..,.
..
I
Not. 3
vTL/Hf11408-20
The LM6181 high speed demonstration board can be configured for either inverting or non-inverting amplifier configurations. This board was intentionally embellished with options so that it can be used as a general-purpose 8-pin opamp evaluation board.
Note 1: Terminate this BNC connection w~h the appropriate connector. 01herwise ringing due 10 high-frequency _ons will occur.
Note 2: Do not lead compensate current feedback ampllfiers-oscillaIIon
will result. Lead compensation uses a feedback capacitor, C4Note 3: C3 and A7 are opIionallag-compensation network points.
Note 4: A6 is lor back matched driving 01 cables.
1037
~
..-
i
r----------------------------------------------------------------------------,
Appendix B: High Speed Board Design Caveats
1. Good high frequency termination is always required for
the input signal. It is important, for evaluating any amplifier, to check the integrity of the inputSlgnal.
2. RF quality, ceramic capacitors are used for bypassing
and are placed close to the amplifiers supply pins.
3. The feedback network is placed in close proximity to the
amplifier.
4. The entire top side of the board is ground planed. This
lowers the high-frequency impedance for ground retum
, signals.
5. The amplifier inputs have ground plane voids since these
. amplifier nodes are sensitive to parasitic stray capacitance. This is specifically a key issue for the non-inverting
amplifier configuration.
6. All leads are kept as short as pOSsible, using the most
direct point-point wiring techniques.
1036
Appendix C: Features Modeled For LM6181 Macromodel
Supply-Voltage-Dependent Input Offset Voltage (Ves)
Temperature-Dependent Input Offset Voltage (TCVeS>
Supply-Voltage-Dependent Input
Bias Current (Ib+ & Ib- PSR)
Temperature-Dependent Input
Bias Current (TCIB+ & TCIB-)
Input-Voltage-Dependent Input
Bias Current (Ib- CMRR)
Non-Inverting Input ReSistance
Asymmetrical Output Swing
Output Short Circuit Current (lsC>
Supply-Voltage-Dependent Supply Current
Quiescent and Dynamic Supply Current
Input-Voltage-Dependent Input Slew Rate
Input-Voltage-Dependent Output Slew Rate
Multiple Poles and Zeroes in
Open-loop Transimpedance (Ztl
Supply-Voltage-Dependent Input Buffer Impedance
Supply-Voltage-Dependent Open-loop Voltage Gain (Avell
Feedback-Resistance-Dependent Bandwidth
Accurate Small-Signal Pulse Response
large-Signal Pulse Response
DC and AC Common Mode Rejection Ratio (CMRR)
DC and AC Power Supply Rejection Ratio (PSRR)
White and 1If Voltage Noise (en>
White and 1If Current Noise (in>
For information related to obtaining National's SPICE macromodeling library, including the lM6181, calla National
sales office.
REFERENCES
1. P. Allen "Slew Induced Distortion in Operational Amplifiers", IEEE J. Solid-State Circuits, Feb. 1977. Everything
you need to know about mathematically describing slewing behavior of voltage feedback amplifiers.
2. K. lacanette, K. Hoskins, "Preserving and Verifying the
lF400's Fast Settling Time", AN-428, National Semiconductor linear Applications Handbook.
3. J. Williams, "High Speed Amplifier Techniques", AN-47,
l.T.C. Well written, but check National's new high speed
products for upgrading speedloverall performance.
4. P. Brokaw, "An I.C. Amplifier User's Guide to Decoupling,
Grounding, and Making Things Go Right For a Change",
AN-202, Analog Devices. A must read for any high-speed
analog system level designer.
5. T. Frederikson, "Intuitive Op Amps", R.A. Donnelley and
Sons, 1984. Superbly written.
6. B.l. Siegel, "Simple Techniques Help You Conquer OpAmp Instability", EON, March 31, 1988.
7. B. Pease, "Troubleshooting Analog Circuits", Butterworth-Heinemann, 1991. Pease exposes the black art of
analog deSign, providing insight.
1039
Increasing the High Speed
Torque of Bipolar
'
Stepper Motors.
National Semiconductor
Application Note 828" .
Steven Hunt
INTRODUCTION
To successfully follow a velocity prOfile, a mptor and drive
combination must generate enough torque to: accelerate
the load inertia at the d~red rates, and drive the load
torque at the desired speeds. While the size of a bipolar
stepper motor generally dictates the low speed torque, the
ability of the drive electronics 'to force current through the
windings of the motor dictates the high 'speed torque. This
application note shows that increasing the slew rates of the
winding currents in a bipolar stepper motor pushes the motor to· deliver more torque at high speeds. Simple voltage
drives, LlR drives, and chopper drives are explained. LlR
drives and chopper drives achieve shaw rates higher than
those achieved by Simple. voltage drives. Finally, an example chopper drive is presented.
relative to a stable detent (zero torque) pOSition. N represents the number of motor poles; that is, the number of
electrical cycles per mechanical cycle or revolution. N.9,
therefore, represents the electrical equivalent of the mechanical rotor position. The torque contributions add,directly
..
.'
to yield a total torque of
Tt = T1 + T2 = T (i2 cos (N9) - i1 sin (N9».
(3)
Integrating (3) over a full period of one of the torque constants and multiplying the resuit by the reciprocal of that
period gives the average torque generated by the motor.
Assuming ideal square wave winding currents and sinusoidal torque constants (F/{Jure 2),. the motor generates an
average torque of
~vg = 2~ [J~ - i1 Tsin (N9) dN9 +
T
f:
BACKGROUND
In standard full-step operation, quadrature (out of phase by
90") bipolar currents (Figure f) energize the windings of a
bipolar stepper motor. One step occurs at each change of
direction of either winding current, and the motor steps at
four times the frequency of the currents. The ideal winding
currents of Figure f exhibit infinite slew rates.
Ideally, each phase contributes a sinusoidal torque;
T1 = -i1 TSin(N9) and
1T
i2 Tcos(N9) d N9] =
,(4)
2
(5)
= -lrateC\ Tcos.
7r
.
In open loop applications, adjusts automatically to match
the average torque generated by the motor with that required to execute a motion task. When the winding currents
and their respective torque constants are in phase ( is
zero), the motor generates the maximum average torque or
(1)
T2 = i2 Tcos(N9),
(2)
with the winding currents, i(t), in amps and the torque constants, -Tsin(N.9) and Tcos(N.9), in newton.centimeters per
amp. 9 represents the angular displacement of the rotor
pull-dut torque:
Tpull-out
'
2
= Tavg (max) = ;: Irated T.
(6)
n~
LJ
I
t
n
@
rooo~o~
phase
#2
TUH/11453-1
FIGURE 1_ Ideal Quadrature C"rrents Drive the Windings of a Bipolar Stepper Motor
1040
low step rates, assuming Vee = Vrated > > Vernl, the current easily slews to the peak value of Vrated/R before a
subsequent direction change (Figure 3a). At higher step
rates, because the time between direction changes is shorter, the current cannot reach the peak value (Agure 3b).
Vrated is the rated voltage of the windings.
Clearly from (4) and Figure 3, as the speed increases, decreases in the winding currents result in decreases in
Tpull-out. The torque vs. speed characteristic of a typical bipolar stepper motor (Figure 4) reflects this phenomenon.
Each pull-out torque curve bounds (on the right) a region of
torque-speed combinations inside which the stepper motor
runs and outside which the stepper motor stalls.
Square waves make good approximations for the winding
currents at low speeds only, and (6), therefore, makes a
good approximation of the pull-out torque at low speeds
only. Real winding currents have an exponential shape dictated by the L/R-time constants of the windings, the voltage
applied across the windings, and, to a lesser extent, the
back emf generated by the motor as the rotor spins. For
either winding,
i(t) = (10 - Vee; Vernl) e -LR!
+ Vee; Vernl
(7)
describes the winding current at a change in the direction of
that current, where 10 is the initial winding current, Vee is the
voltage applied across the winding, Vemf is the back emf,
and Rand L are the winding resistance and inductance. At
NO
'2 (t) " "
TcosNO
~
\ylr.ted
NO
TLlHI11453-14
FIGURE 2. Ideal Square Wave Winding Currents and Sinusoidal Torque Constants for Average Torque Calculation
(b)
TLlH/11453-15
FIGURE 3. Real Winding Current and Sinusoidal Torque Constant
vs Step Rate at Low Step Rates (a) and at High Step Rates (b)
1041
It follows then, that the goal of increasing the high speed
torque is achieved by increasing the winding currents at
high speeds. This, in tum, is achieved by increasing the slew
rates of the winding currents; for example, with the increased slew rates realized by raising Vee well .above
Vrated, the winding current easily slews to the peak value of
Vrated/R at both low and high step rates (Figure 5). Winding
currents realized with Vee = Vrated are represented with
dashed lines, and, assuming a means for limiting at
Vrated/R, winding currents realized with Vee > > Vrated
are represented with solid lines.
Both decreasing the L/R-time constants of the windings
and incr:easing the voltage applied across the windings increases the slew rates of the winding currents. L/R drives
and chopper drives take these tactics to raise the slew rates
of the winding currents well above those realized by simply
applying the rated voltage to the windings. The torque vs.
speed characteristic of a typical bipolar stepper motor (Figure 4 again) reflects the resulting high speed torque gains.
It is important to note, however, that applying
Vee > > Vrated also results in excessive winding currents at
low speeds. The winding currents must be held at or below
the rated limit (usually Vrated/R per winding) to hold power
dissipated inside the motor at or below the rated limit (usually 2 x Vrated x lrated)'
O~~~----~~~~UU
o
50 100
500 1000 5000 10000
STEPS/SECOND
TL/H/11453-3
FIGURE 4. A Typical Torque vs Speed Characteristic of a Bipolar Stepper Motor
- - - v,.ted /R
= 'rated
He
(b)
FIGURE 5. Real Winding Current vs Step Rate with Vee
TLlH/11453-6
> > Vrated at Low Step Rates (a) and at High Step Rates (b)
1042
r--------------------------------------------------------------------,~
SIMPLE VOLTAGE DRIVES
5ince both the LlR-time constants of the phase windings
and the rated supply voltage were increased by a factor of
four, ,the example drive would commonly be referred to as
an L/4R drive.
The maximum operating supply voltage of the power amplifi~
ers can limit the factor by which the supply voltage is increased above the rated voltage of the windings, but power
losses in the series resistors more likely limit this factor. If,
for example, 60V is applied across two O.SA, 1S0 phase
windings, two 10S0 series resistors are required to hold the
winding currents to the O.SA/phase limit This is an L/SR
drive. Power dissipated in the series resistors while the rotor
holds position is 10S X O.S X O.S X 2 = S2.SW, while
power dissipated in the entire drive is 60 X 0.5 X 2 = 6OW.
The drive efficiency approaches 12.5%. After looking at
these numbers, the drive designer may opt to cut losses by
using the 30V power supply/450 series resistor combination of an Ll4R drive. Unfortunately, while the rotor holds
position, total power dissipated in the series resistors remains high at 22.5W and drive effiCiency remains low at
25%.
5imple drives employ two H-bridge power amplifiers to drive
bipolar currents through the phase windings (Figure 6). For
either amplifier, closing switches 51 and 54 forces the rated
voltage (less two switch drops) across the winding, and current flows from supply to ground via 51, the winding, and
84. After opening 51 and 54, closing'52 and 53 reverses
the direction of current in the winding. This drive scheme is
commonly referred to as simple voltage drive. Because only
the winding resistances limit the winding currents, Vee cannot exceed Vrated.
URDRIVES
LlR drives employ two series power resistors to decrease
the L/R-time constants of the windings; for example, a 4S0
power resistor in series with each of two 1S0 winding resistances divdes the LlR-time constants by four and allows the
rated supply voltage to be increased by a factor of four.
Both the crispness of the response and the high speed
torque are increased. While the rotor holds position or
moves at low step rates, the series power resistors protect
the motor by holding the winding currents to the rated limit.
Vee =v",ted
52
-
pha •• #2
i
l
54
l1.IH/11453-2
FIGURE 6. Simple Voltage DrIve of a Bipolar Stepper Motor
1043
i
~ r-------------------------------------------------------------------------~
cp
~
CHOPPER DRIVES
Chopper drives increase the slew rates of the winding currentS by applying Vee > > Vrated; Feedback-driven switching of the H-bridges holds the winding currents to the rated
limit. Figure 7 shows the chopping ststes of a single
H-bridge of a chopper drive. A low value' resistor in the
ground lead of the H-Bridge converts the winding current
into a proportional feedback voltage, and the feedback voltage is compared to a reference voltage (not shown). While
the feedback voltage is less than the reference voltage,
switches 51 and 54 apply the full supply voltage across the
winding (Figure 7a), and the winding current increases rapidly. When the feedback voltage is equal to the reference
voltage; that is, when the winding current reaches the desired limit, 51 and 52 short the winding for a fixed period or
off-tifTIB (Figure 7b). During the off-time, the winding current
recirculates and decays slowly. At the end of the off-time,
(a)
51 and 54 reapply the full supply voltage across the windIng, and the winding current again increases. Repetition of
this sequence results in a Current chopping action that limits
the peak winding current to a level determined by the reference voltage and the resistor in the ground lead of the amplifier (F1f1U(9 7c), limit = Vreference/RS. Chopping of the
current only occurs when the current reaches the desirad
limit (usually the rated current of the winding). When the
winding current changes direction to step the motqr, the
general operation ramalns the same except 52 is held
closed and 51 and 53 are switched to limit the winding currant. Because the H-bridge shorts the winding for a fixed
period, this type of chopper drive is commonly referred to as
a fixed off-tifTIB drive. By eliminating the series resistors required by LlR drives, chopper drives incresse dramatically
the drive efficiency. Typical efficiencies of chopper drives
range from 75% to 90%.
(b)
(c)
TUH/1145S-7
FIGURE 7. The Chopping Statal of a Single H-Brldge of a Chopper Drive: the Full Vee I. Applied Acroaa the Winding (a),
the Winding I. Shorted (the Currant ReCirculates) (b), and the Chopped Winding Currant (c)
1044
AN LMD1820D-BASED CHOPPER DRIVE
plies the full supply voltage across the winding, and the
winding current again increases. Repetition of this sequence results in a current chopping action (Figure 10) that
limits the winding current to the O.5A rating while allowing
the 12V, 240 winding to be driven with 36V. Note: the RC
components associated with the LMC555 set the one-shot
timing pulse. To best illustrate the current chopping action,
the one-shot timing pulse or off-time was set at approximately 100p.s. Shorter off-times yield smoother winding currents.
The LMD18200 is a 3A, 55V H-bridge (Figure 8). It is built
using a multi-technology process which combines bipolar
and CMOS control (logic) and protection circuitry with
DMOS power switches on the same monolithic structure.
The LMD18200 data sheet and AN-694 contain more information about the operation of the LMD18200.
Two LMD18200 H-bridges form the core of an example
chopper drive (Figure 9). The PWM input (pin #5) of each
LMD18200 accepts a logic signal that controls the state of
that device. While the signal at PWM is logic-high, the Hbridge applies the full supply voltage across the winding,
and while the signal at PWM is logic-low, the upper two
switches of the H-bridge short the winding. The feedback
voltage associated with either H-bridge is directly proportional to the current in the winding driven by that device.
One half of an LM319 dual comparator compares the feedback voltage to the reference voltage. While the feedback
voltage is less than the reference voltage, the signal at
PWM is logic-high, the LMD18200 applies the full supply
voltage across the winding, and the winding current increases. When the winding current increases to the point the
feedback voltage and the reference voltage are equal, the
LM319 triggers the LMC555-based one-shot. For the duration of the one-shot timing pulse, the signal at PWM is logiclow, the LMD18200 shorts the winding, and the winding current recirculates and decays. After the timing pulse, the signal, a PWM returns to logic-high, the LMD18200 reap-
THERMAL
FLAG
9
BOOTSTRAP 1
1
The Dir input (pin #3) of each LMD18200 accepts a logic
signal that controls the direction of the current in the winding driven by that device; in other words, changing the logic
level of the signal at Dir commands the motor to take a step.
This chopper drive takes advantage of the current sense
amplifier on board the LMD18200. The current sense amplifier sources a signal level current that is proportional to the
total forward current conducted by the two upper switches
of the LMD18200. This sense current has a typical value of
377 ,..,A per Amp of load current. A standard v.,W resistor
connected between the output of the current sense amplifier (pin # 8) and ground converts the sense current into a
voltage that is proportional to the load current. This proportional voltage is useful as a feedback signal for control and/
or overcurrent protection purposes. The 18 kO resistors
(Figure 9) set the gain of the drive at approximately 0.15A
per volt of reference voltage (simply the reciprocal of the
product of 377 ,..,A/A and 18 kO).
OUTPUT 1
2
Vs
6
OUTPUT 2 . BOOTSTRAP 2
10
11
THERMAL
SENSING
UNDERVOLTAGE
LOCKOUT
1-+----+'1--0{) 8
CURRENT
SENSE
OUTPUT
DIRECTION 3
BRAKE "
PWM 5
7
GROUND
TL/H/II463-8
FIGURE 8. The LMD18200 3A, 55V Full H·Brldge
1045
~
'GO
Z•
x (1 + TC1 x (T - Tnom)
+ TC2 X (T-Tnom)2)
(12)
where is the value of the resistor at Tnom (usually
27"C), T is the temperature in ·C, TC1 is the linear temperature coeffiCient, and TC2 is the quadratic temperature coefficient.The equation will fit a quadratic curve through three
points in a temperatUre graph by solving three equations
with three unknowns: Since SPICE will give an error message if Ii resistor goes negative at any temperature, an offset bias is added to the resistor value whose voltage is then
subtracted "from" th$ respective input error source (Gb1,
Gb2, or Eos).
offset
47'-~~------~
RL4
L3
L4
R26
([I
TLIHI11488-8
FIGURE 6. Macromodel PSRR Slage
The signals generated at nodes 45 and 47 are directly reflected to the input of the amplifier via the second and third
terms of the Eos polynomial-controlled source. Since the
PSRR stages are referenc;edto ground, a large offset voltage will be developed if the model is operated from asymmetrical suppliEls. This compro!Tlise was neceSS9ry in order
to include the PSRR effects; however, if operation on asymmetricl!Il supplies is required, the PSRR effects can be disabled by changing the second and third polynomial terms in
Eos from 1 to O. For example; change:
I2
,t
,
'=
~R28' ~R29
,
'=
+18
'=
Yos
TLlHI114S8-9
The voltages generated at nodes 55; 56, and 57 are scaled
and usSdto control the ,Input error sources Gb2, Gb1, and
Eosrespectiv81y. The' simulated results compare quite
closely to the typical curves for the actual device as can be
seen in Figures 16 and 17.
E003 1 POLY(5) 99 50 45 0 47 0 57 0 59 81 -2,SE-3 9.3E-5 1 1 1 1
NOISE STAGES
The addition of noise effects to any macromodel is similar to
tl)e techniques used for input offset voltage and drift., The
total amplifier noise is lumped together and referred to tile
input of the model. Before noise sources are added, however: the rDodel, has t!) be rendered ~ntially noiseless. This
is easier than ,it sounds. though, because noise adds vectorially. The total contribution of several noise sources can be
found by:
Elltotal '" 4(En1)2 + (En2)2 + (En3)2 ••.
So, a latent noise source within the model will have to be
reduced to only ,y,. of the desired noise level to maintain an
accuracy of lass than 3% (.11 +0.252 = 1.03). Most of the
latent amplifier model noise comes from thermal noise generated by large.vs.luereslstors commonly used in macromodels. To reduce this noise, the resistor values are scaled so
their' thermal, noise is negligible compared to the desired
noise ,of: the amplifier. If resistor scaling is not possible, as
was the case with several resistors in the input stage of the
LM6181 macrornodel, a' noistJless resistor can be used. A
noiseless resistor is created by utilizing a voltage-controlled
current-source (G device) with the same,input and output
~errninals whose gm is set to the reciprocal of the required
value of, resistance
Figure 3 and the LM6181 netlist).
The only caveat with using noiseless resistors is, that a current-so~ ,is cpnsidered an open circuit when SPICE calculates the initial pjas point of the circuit T,herefore, at least
one other device must be connected to the nodes of the
noiseless resistor to avoid "floating node" errors.
'
Eoo 3 1 POLY(S) 99 50 45 0 47 0 57 0 59 61 -2.8E-3 9.3E·5 0 0 I 1
To set the component values in the PSRR stages, R25 and
R26 are arbitrarily chosen to be 100 The gm's of the current
sources are set so that the DC gain of each stage is equal
to the DC value of the PSRR or:
PSRR
G10 = 1020 X [_1_]
,
R25
(10)
where PSRR is the typical DC rejection ratio in dB. The
inductors, L3 and L4, determine the 3 dB frequency of each
stage and can be set with:
~
(11)
Resistors RL3 and RL4 cancel the zeros associated with
the inductors at a frequency above the unity gain frequency
of the amplifier. This helps with transient convergence when
simulating inductive or resistive power supply lines.
,
-18
(f)T.56
R27
, FIGURE 7. Macromode/ Thermal Effect Stagea
to:
L=
'
(f)T.57
,55
2'X 'IT X f3dB
{see
1054
r--------------------------------------------------------------------.~
Now that the macromodel is rendered essentially noiseless,
lumped noise sources can be added and referred to the
input sources. Figure 8 shows the equivalent noise model
which consists of an ideal noiseless amplifier, two noise-current generators (in + and in _), from each input to ground
and a noise-voltage generator (en) in series with non-inverting input.
the noise-voltage source (nodes 58 and 60). The reason for
using two identical circuits is so that a DC voltage would not
be created which would be seen as an offset voltage on the
input.
Flicker noise or 1/f noise-voltage comes from the SPICE
diode model. By setting the flicker noise exponent (AF) to 1
and property setting the flicker noise coefficient (KF), the
resulting noise voltage will accurately simulate the 1/f
noise-voltage spectral density with the correct "corner frequency". Equation 16 shows the noise-current that results
from the SPICE diode model where Id is the DC diode current and the 2 x q x Id term is negligible compared to the
1/f noise of the amplifier.
in2 = 2 x q x Id
+ KF
IdAF
x FREQUENCY
(16)
To determine the value for KF in the macromodel, the following equation can be used:
Ea2
KF = R2 X Id X 2
TL/HI114B8-10
FIGURE 8. Equivalent Amplifier Noise Model
The noise-current generators are called Fn1 and Fn2 in the
macromodel input stage (Figure 3), while the noise-voltage
generator is included in the Eos polynomial-controlled
source. The noise voltage or current which is actually referred to the input generators comes from separate noise
source stages in the macromodel.
The noise-voltage circuit (Figure 9) generates both 1/f and
white noise by using a 0.1V voltage-source which lightly biases a diode-resistor series combination. White noise is
simply the thermal noise-current generated in the resistor
which follows the spectral power density (per unit bandwidth) equation below:
58
6
2
CU63
CU
V17+
~
rn
_
-=
rn
In+
-=
TL/H/114B8-12
(14)
FIGURE 10. Macromoc:iel White
Noise-Current Generators
Since the noise-current through each of the resistors is
measured with the voltage-sources and directly referred to
the respective current-controlled current-source on the input, the value for each resistor can be found by rearranging
Equation 14 or:
60
v [ f 509
V18+
_
In-
i 2 =4XkXT
n
Resistance
(17)
where Ea is the noise-voltage spectral density of the amplifier at 1 Hz and Id is the DC current through the diode which
can be determined with the standard Schottky diode equation. Again, the "2" in the denominator comes from the fact
that the noise output is taken differentially across two identical circuits.
The white portion of the amplifier's noise current is modeled
by utilizing the thermal noise current of a resistor in series
with a zero volt voltage-source (see Figure 10).
e-+-------!
R30
4xkxT
R=
EN
FIGURE 9. Macromodel NOise Voltage Stage
where in is the noise-current through the resistor, k is Boltzmann's constant (1.381 x 10-23), and T is the temperature
in OK rC + 273.2"). By taking the square root of both sides
of the equation and multiplying by resistance, the required
value of resistance can be found for a given noise-voltage
spectral density with:
R =
en2
2x4XkxT
in2
(18)
The in term is the broad-band or white noise-current spectral density at the respective input of the amplifier.
To simulate the 1/f component of the noise-current, the
flicker noise coefficient (KF) in the model for each pair of
input transistors is set to obtain the correct corner frequency. In the LM6181 macromodel, KF is set to 4.13 X 10- 13
for Q1 and Q2 while KF is set to 6.7 x 10- 14 for Q3 and
04. The flicker noise exponent (AF) is left at its default value of 1.
TL/HI114B8-11
The macromodel's noise curves are compared to the actual
amplifier's curves in Figures 18 through 21. The simulation
results are quite close to the actual noise characteristics of
the amplifier. For more information on calculating and modeling amplifier noise, see references [3] and [9].
(15)
where en is the white noise voltage of the amplifier per JRi.
The "2" in the denominator comes from the fact that the
voltage is taken differentially across two identical circuits of
1055
Z
c»
~
OUTPUT STAGE
After the input signal is amplified and frequency shapad, it is
further processed by theootput stage shown in rl9ure 11.
The output stage performs three important function", namely, simulation of output impedance, short-circuit current limiting, and dynamic supply current.
The intermediate output signal appears at the output of the
last frequency-shaping stage as a hlgh-source-impedance
voltage referenced to VH. Voltage-controlled voltagesource, E1, level shifts the intermediate output'signal down
from the positive rail and· provides the output drive for the
model. Output impedance is modeled with the Combination
of R35 and L5. Resistor R35 simulates the DC output impedance which determines the behavior of the model when
driving heavy loads. Additionally, inductor L5 models the
characteristic rise in output impedance as a function of frequency which is common to' the emitter-follower output
stage found in many amplifiers. Since an ideal inductor as
modeled by SPICE has infinite Q, a bare inductor in the
signal path can cause convergence problems if the current
through it can change instantaneously. To lower the Q of
the inductor and prevent convergence problems during simulation, a large value 'resistor; RL5, is placed across L5. Capacitor CF1 models Stray capacitance across the feedback
resistor which dramatically affects the high frequency response of the amplifier.
.'
Short-circuit current limiting is also a necessary feature of
any good amplifier macromodel. The diodes 05 and 06
each in series with a voltage-source V5 and V6 accomplish
this function by effectively clamping the maximum voltage
across R35. The value of the voltage-sources can be set
with the following equation which was derived with the
Schottky diode equation and summing the currents at node
40 assuming the output is shorted to ground.
V = R35
x Isc - In [
..
Vee - R35
x Isc
Is X Zofr
+1
The·term Zofr is the output impedance of the last frequency
shaping stage (1 kG in this case), Is is the saturation current
of the diode, and VT is the thermal voltage k X T/q. Although it appears that the appropriate. parameters' are included in the equation, no attempt was made to -model the
dependence of short-circuit current on supply voltage or
temperature.
Another behavior that is often not included in op-amp macromodels is dynamic supply current. If the output of the
model is driven by an ideal VOltage-source, the simulated
output current of the model appears to come from nowhere,
i.e., the supply currents do not change. This apparent violation of the second law of thermodynamics has been solved
with diodes 07-08, current-sources F5-F6, and associated
circuitry. Since it is important to keep non-linear devices,
such as diodes, out of the signal path, only an ideal ammeter, VA8, was inserted in the output driver to sense the sinking or sourcing of output current. Current-c6ntrolled currentsource F5 mirrors the current sensed by VA8 and forces an
equal current through either 07 or 08 depending on its polarity. If current is being sourced into the load, the current
flows from the positive rail through E1 and VA8 to the output
node and no supply current correction is necessary. However, if the output stage is sinking current from the load, the
current flows from the output node up through VA8 and E1
into the positive rail.' To' compensate for this, F5 forces an
equal current through 07 and ammeter.VA7. This current is
then mirrored to current-source F6 which pulls an equal
amount of current out of the positive rail· and forces it into
the negative rail. Therefore, if the output stage is sourcing
current, it appears to come from ·the positive rail, whereas
current that is sinking from the load appears to go into the
negative rail. The net result of all these extra deviC91l is an
output fi\tage which closely models the behavior of the real
amplifier.
'
] ..'
'x VT(19)
99
F6
IVA7
F5
IVA8
9 9 _ - . _...
50
35
El
23 _ _ _'
VA8
V5
R35
40
L5
VOUT '
...._ _ _.....rrY"'l'"'-_ _.. 41
RL5
FI~URE 11. Macromod,l Output St~ge
1056
. TL/HI11488-13
LM6181 Macromodel Netllst
*******************************************
*LMS1Sl CURRENT FEEDBACK OP-AMP MACRO-MODEL
*******************************************
*
*connections:
*
•
*
*
*
*
.SUBCKT LMS1Sl
non-inverting input
I inverting input
I I positive power supply
I I I negative power supply
I I I I output
I I I I I
I I I I I
1 2 995041
*
*Features:
(TYP.)
*High bandwidth
100 MHz
*High slew rate
2000 V/~s
*Current Feedback Topology
*NOTE: Due to the addition of PSRR effects, model must be operated
*
with symmetrical supply voltages. To avoid this limitation
*
and disable the PSRR effects, see Eos below.
*
********** INPUT STAGE **********
*
GIl 99 5 POLY(l) 99 50 243.75U 2.70SE-S
GI2 4 50 POLY(l) 99 50 243.75U 2.70SE-S
FIl 99 5 VA3 100
FI2 4 50 VA4 100
Ql 50 3 5 QPN
Q2 99 3 4 QNN
GRl 5 S 5 S 2.3SE-4
*'4.2K noiseless resistor
Cl S 99 .4SSP
GR2 4 7 4 7 2.3SE-4
*'4.2K noiseless resistor
C2 7 50 .4SSP
GR3 99 S 99 S 1.5SE-3
*'S330hm noiseless resistor
Vl 99 10 .3
REl 10 30 130
Dl 30 S DX
GR4 50 9 50 9 1.5SE-3
*'S330hm noiseless resistor
V2 11 50 .3
RE2 11 31 150
D2 9 31 DX
Q3 S S 2 QNI
Q4 9 7 2 QPI
DSl 3 12 DY
VA3 12 5 0
DS2 13 3 DY
VA4 4 13 0
GRS 1 99 1 99 5E-S
.'20MEG noiseless resistor
GR7 1 50 1 50 5E-S
.'20MEG noiseless resistor
GBl 1 99 POLY(2) 99 50 5S 0 -1.2E-S 4E-S lE-3
FNl 1 0 VlS 1
GB2 99 2 POLY(3) 99 50 1 49 55 0 lS.5E-S -1.5E-7 -lE-7 -lE-S
FN2 2 0 V17 1
EOS 3 1 POLY(5) 99 50 45 0 47 0 57 0 59 Sl -2.SE-3 9.3E-5 1 1 1 1
,,
*To run on asymmetrical supplies, change to 0 •••••••••••••
1057
CIN1 1
CIN2 2
0 2P
0 5.75P
*
******** SECOND STAGE **********
*
13
99 50 4.47M
R8 99 49 7.19K
R9 49 50 7.19K
V3 99 16 1.7
D3 15 16 DX
D4 17 15 DX
V4 17 50 2.0
EH 99 98 99 49 1
G1 98 15 POLY(2) 99 8 50 9 0 1.58E-3 1.58E-3
*Fp1 = 27.96 KHz
R5 98 15 2.372MEG
C3 98 15 2.4P
*
********* POLE STAGE ***********
*
*Fp = 250 MHz
G2 98 20 15 49 1E-3
R14 98 20 1K
C4 98 20 .692P
*
********* POLE STAGE ***********
*
'Fp = 250 MHz
G3 98 21 20 49 1E-3
R15 98 21 1K
C5 98 21 .692P
*
********* POLE STAGE ***********
*
*Fp = 275 MHz
G4 98 22 21 49 1E-3
R16 98 22 1K
C6 98 22 .5787P
*
********* POLE STAGE ***********
•
'Fp = 500 MHz
G5 98 23 22 49 1E-3
R17 98 23 1K
C7 98 23 .3183P
*
********* PSRR STAGE ***********
*
G10 0 45 99 0 1.413E-4
L3 44 45 26.53U
R25 44 0 10
RL3 44 45 10K
G11 0 47 50 0 1.413E-4
L4 46 47 2.27364U
R26 46 0 10
RL4 46 47 10K
1058
*
******** THERMAL EFFECTS **********
*
112
R27
113
R28
114
R29
0
0
0
0
0
0
55
55
58
56
57
57
1
10 TC = 3.453E-3 7.93E-5
lE-3
1.5 TC = 9.303E-4 8.075E-5
lE-3
3.34 TC = 3.11lE-3
*
********* NOISE SOURCES ***********
*
V15
D9
R30
Vl6
D10
R31
V17
R32
V18
R33
58 0.1
58 59 DN
59 0 728.4
60 0.1
80 81 DN
81 0 728.4
62 0 0
82 0 73.6
83 0 0
83 0 1840
*
********* OUTPUT STAGE *********.*
*
F6 99 50 VA7 1
F5 99 35 VA8 1
D7 36 35 DX
VA7 99 36 0
D8 35 99 DX
El 99 37 99 23 1
VA8 37 38 0
R35 38 40 50
V5 33 40 5.3V
D5 23 33 DX
V6 40 34 5.3V
D8 34 23 DX
Cll 41 2 2.1P
L5 40 41 31N
RL5 40 41 lOOK
*
••• ****** MODELS USED ***********
*.MODEL
.MODEL
.MODEL
.MODEL
.MODEL
.MODEL
.MODEL
• ENDS
=
=
=
=
QNI NPN(IS
lE-14
QPI PNP(IS
lE-14
QNN NPN(IS
lE-14
QPN PNP(IS
lE-14
DX D(IS
lE-15)
DY D(IS = lE-17)
DN D(KF
1.667E-9
=
=
BF
BF
BF
BF
=10E4 VAF =62.9 KF =6.7E-14)
=10E4 VAl =62.9 KF =6.7E-14)
=10E4 VAl =82.9 KF =4.13E-13)
=10E4 VAl =62.9 KF =4.13E-13)
AF
=1 ITI =0 EG =.3)
1059
SIMULATION ACCURACY
CONCLUSION
The real test of a macromodel is how the simulation results
compare with the real-world device. The table below shows
some of the amplifier parameters and how the simulation
compares to actual device behavior. As can be seen, the
goal of a 10% match between the model and the actual
device was achieved.
A good figure of merit for a macromodel is the accuracy of
its small-signal transient response. Figures 14 and 15 show
the small-signal response of the real LM6181 and the simulation output. Notice that the simulated over-shoot and frequency of ringing closely match that of the actual device.
This is due to the accurate modeling of the frequency response and output impedance capabilities of the model.
A truly comprehensive SPICE compatible macromodel for
current-feedback amplifiers has been developed. The macromodel includes effects such as accurate input transfer
response, accurate AC response, temperature effects, DC
and AC PSRR, and noise. Even with the addition of all these
features, the macromodel's simulation speed is still more
than twice as fast as a device level micromodel. The speed
advantage of this macromodel mainly comes from the fact
that it converges extremely well. Since careful attention was
paid to convergence during the developm~nt of the model,
there Is no difficulty establishing a bias point or dealing with
large input signals. With detailed and accurate vendor supplied macromodels such as the one described in this paper,
the designer can easily verify the effects of strays and amplifier limitations in his circuit.
Parameter
RI = 1 kO
Typical Value
Simulation Results
% Error
127dBO
126.6dBO
4.5%
100 MHz
103.9 MHz
3.9%
IB+
1.5,..A
1.5,..A
0.0%
Zt(dc)
BW3dB
Av = -1 RI = 1 kO
IB-
-4.0,..A
-4.0,..A
0.0%
Vos
-3.34mV
-3.3mV
1.2%
Isupp
7.5mA
7.7mA
2.7%
Pulse Rasp. Overshoot
35%
34.8%
0.6%
Slew RateVIN = ±10V
1400Vlp.s
1468 Vlp.s
4.8%
Iso
130mA
l36.8mA
5.2%
en
5 nVl,fHz
4.9 nVl,fHz
2.0%
in+
3 pAl,fHz
2.96 pA/,fHz
1.3%
in-
16 pA/,fHz
15.1 pA/,fHz
5.6%
1060
I
r---------------------------~========================~~
m
*LM6181 Small-Signal Response. Av = +2.
*Rt
Rg
820ohm.
820
= =
c!;
*
XARl 3 2 7 4 6 LM6181
VP 7 0 15V
VN 4 0 -15V
VIN 3 0 PULSE (-.2V .2V 40N .2N .2N)
RF 6 2 8200hm
RI 2 0 8200hm
RL 6 0 10MEG
CL 6 0 8.7pF
.LIB CF.LIB
.OPTIONS RELTOL
.0001 CHGTOL
lE-20
.TRAN/OP .1N 200N
• PROBE
._------_ ..
SCOPE PROBE
=
TL/H/II488-14
FIGURE 12. Non-Inverting amplifier. Av = + 2.
It Is very Important to Include a model of the scope
probe on the output of the amplifier to obtain
reasonable results from the simulation.
=
• END
FIGURE 13. Non-Inverting Amplifier Netllst [9]
LM6181 Small-Slgnal Reaponse
Ay=
Rf
+2
= Rg = 8200
800mV,----,...----,----,-------,
~o~~--_fHft\A~--_+------_+------~
V~
O~r---~~---+_---+_----;
-'OOmV ~----.L.-t----t_---t_--__I
-~mV~
____
Ons
TIME (50 .s/div.)
~
____
5001
~
___
lOOns
~
__
150na
~
200ns
TIWE
TL/H/II48B-21
TLlHI1148B-15
FIGURE 14. LM6181 Smail-Signal Transient Response
FIGURE 15. LM6181 Simulated Transient Response
LM6181
Vos. + lB. -IBvsTemperature
LM6181 Vos.
+ lB. -IB
10
10
Vs
= 15V
f-- r--
/
-4
-6
........
+18 (IIA)
./
~
-18(!'A)
/
..... ~ V
'-...
-5
-8
-10
-55 -35 -15
J-
~r- +18 (lOA)
-2
J.
Vos (mV)
L
Vos (mV)
-10
-55 -40
5
25
45
65
85
105
125
--
......
V
/
-18 (lOA)
40
80
120
TEWP (Oc)
TEMP. (Oc)
TLlH/II48B-16
FIGURE 17. LM6181 Simulated Temperature Effects
TL/H/II488-22
FIGURE 16. LM6181 Temperature Eftects
1061
icp
LM6181 Voltage Nolae vs Frequency
LM6181 Voltage Noise va Frequency
Z
40nY
40
oC
3D
~
~
3DnV
\
20
20nY
:--..
10
:\
\
,
~
lOnV
o
OnV
I
10
100
Ik
10k
lOOk
1.0H
100H
10H
FREQUEljCY (Hz)
IkH
lOkH
TLlH/II488-19
TL/H/II488-17
FIGURE 18. LM8181 Voltag.Nolse Response
FIGURE 19. LM6181 Simulated Voltage·Nolse Response
LM6181 Current Noise va Frequency
LM6181 Current NoIse va Frequency
120
100
100kH
FREQUENCY
120pA
,
\
l00pA
10
10pA
SOpA
80
INVERTING INPUT
,1
\
.\
'
\
40
40pA
\
"
20
'20pA
OpA
1
10
INVER)"I,NG INPUT
'
'
""
NON-IN~~
::';INVERTING,
o
'
'100
lk
10k
lOOk
INPUT
I.DH
'FREQUENCY (Hz)
Tl/H/II488-20
FIGURE 20. LM6181 Current-Nolae Response
10H
..............
l00H
lkH
10kH
l00kH
FREQUENCY
TLlHI11488-18
FIGURE 21. LM6181 SImulated Current·Nolse Response
REFERENCES
5. Alexander, Mark, "AN-138 SPICE-Compatible Op Amp
Macromodels", Precision Monolithics Inc., Application Note
138
1. Boyle. G.A.. "Macromodellng of Integrated Circuit Operational Amplifiers", IEEE Journal of Solid-State Circuits, Dec.
1974 Vol. SC-9
6. Palouda, Hans, "Current Feedback Amplifiers Meet High
Frequency Requirements", Powerconversion & Intelligent
Motion, Sep. 1990, pp. 27-31
'
2. Bowers, D.F., "A Comprehensive Simulation Macromodel
for 'Current-Feedback' Operational Amplifiers", IEEE Proceedings, Vol. 137, Apr. 1990, pp. 137-145
3. Ryan, AI, "D~C Amplifier Noise Revisited", Analog Dialogue, Vol. 18, Num. 1, '1984, pp. 3~,10
7. Franco, Sergio, Design with Operationsl Amplifiers and
Analog IC's, McGraw-Hili, New York, NY, 1988
8. Williams, Arthur B., Electronic Filter Design Handbook,
4. Tabor, Joe, "Macromodels Aid in Use of Current-Mode
Feedback Amps", Electronic Products, Apr. 1992, pp. 2530
9. Tuinenga, Paul W., SPICE: A Guide to CifCIJit Simulation
& Analysis Using PSp;cee, Prentice-Hall, 1992
McGraw-Hili, New York, NY, 1981
1082
~
A SPICE Compatible
Macromodel for CMOS
Operational Amplifiers
National Semiconductor
Application Note 856
David Hindi
ABSTRACT
currents on the input protection diodes DP1-DP4. auiescent current is modeled with the combination of 12 and the
R8-R9 series resistors. As the supply voltage increases,
the current through R8 and R9 will increase, effectively simulating that behavior in the real device. Resistors R8 and R9
also act as a voltage divider and establish a common-mode
voltage (VH) for the model directly between the rails. If the
supply rails are symmetrical, i.e. ± 5V, node 49 will be at OV.
Voltage-controlled VOltage-source, EH, measures the voltage across R8 and subtracts an equal voltage from the positive supply rail to provide a stiff point between the rails
(node 98) to which many other stages in the model are referenced. Voltage-controlled current-source GO and resistor
RO model the gain of the input stage. The signal is then
passed to the frequency shaping stages for further conditioning.
A SPICE macromodel that captures the "personality" of
National Semiconductor's CMOS op-amps has been developed. The salient features of the macromodel are a
MOSFET input stage, Miller compensation, and a currentsource output stage. A description of the model will be given
along with correlation to actual device behavior.
INTRODUCTION
Recently, there has been a major thrust in lowering power
dissipation and supply voltages for analog system level design. In response to this, National Semiconductor has developed a family of CMOS op-amps which feature rail-to-rail
output swing, extremely low input bias current (10 fA typ.),
single supply operation, low power consumption, and an input common-mode range that includes the negative supply
rail [11. Due to the unique topology that makes these features pOSSible, a new SPICE macromodel was required in
order to achieve accurate simulation results.
MACROMODELING PHILOSOPHY
The philosophy used in creating this macromodel was a desire to design a model that would accurately simulate the
typical behavior of a CMOS op-amp while executing much
faster than a device level model (commonly referred to as a
micromodel). The "personality" of an op-amp can be captured by individually hand crafting and thoroughly testing
each model to ensure that it accurately simulates the behavior of the real device.
CMOS MACROMODEL INPUT STAGE
The input stage performs several important functions including non-linear input transfer characteristics, offset voltage,
input bias currents, second pole, and quiescent power supply current. The heart of the input stage consists of a differentlal amplifier which is made up of two simplified MOSFET
models (see Figure 1) [21. Input common-mode range can
be modeled by properly setting the zero bias threshold voltage (VTO) in the MOSFET model. In the case of the
LMC6484, which has rail-to-rail input common-mode range,
VTO is left at its default value of zero. Offset voltage is modeled with an ideal voltage source, Eos, while input bias/offset currents are modeled by properly setting the leakage
FREQUENCY SHAPING STAGES
In keeping with the philosophy of providing a macromodel
that is as accurate as possible, it has been determined that
the model must be capable of easily accommodating as
many poles and zeros that are necessary to precisely shape
the magnitude and phase response ofthe model [31. This is
accomplished with telescopic frequency shaping stages that
each have unity DC gain, making it easier to add poles and
zeros without changing the low-frequency gain of the model.
Each of the three types of frequency-shaping stages is
shown in Figure 1.
COMMON-MODE STAGE
Common-mode gain is modeled with a common-mode zero
stage whose gain increases as a function of frequency. A
voltage-controlled current-source, G4, is controlled with a
polynomial equation which adds the voltage at each input
(nodes 1 and 2) and divides the sum by two. This result is
the input common-mode voltage. The DC gain of the stage
is set to the reciprocal of the CMRR for the amplifier. An
inductor, L2, increases the gain of the stage at 20 dB/decade to model the roll-off of CMRR that occurs in most amplifiers. The output of the common-mode zero stage (node 16)
is reflected to the Eos source to provide an input-referred
common-mode error.
Characteristics of National Semiconductor's CMOS Operational Amplifiers
Common
Characteristics
Rail-to-rail output swing, ultra-low input bias current (10 fA typ.), low drift (1.3 p.V1°C), single supply
operation, input common-mode range includes ground, low power consumption, and high voltage gain.
LMCS60
Drives 6000 load, high bandwidth (1.4 MHz), high slew rate (1.1 V I p.s), comes in quad and dual
(LMCS62).
LPC660
Low power (215 ,...W/amp), comes in quad and dual (LPC662).
LMC6044
Low power (70 ,...Wlamp), comes in quad, single (LMCS041) and dual (LMC6042).
LMCS062
High precision dual (Vos = 100 p.V),low power (80 p.W/amp).
LMCS082
High preciSion dual (Vas = 150 p.V), drives 6000 loads, high bandwidth (1.3 MHz).
LMC6484
Rail-to-rail input common-mode range, operates on 3V single supply, drives 6000 loads, high bandwidth
(1.3 MHz), comes in quad and dual (LMC6482).
1063
National's.CMOS Op-Amp Macromodel .
":j"
.~,
\, OUTPUT STAGE
INPUT STAGE
..
.
." +vs .
":-',
1---'.
R9
..
15
-Vs
••
.
LI
m"
G3
."
Rf2
._49
"
..
FREQUENCY SHAPING STAGES
"
POLE
••
L2
C5
,.
.
15
POLE/ZERO
RI3
"
COMMON"MODE ZERO
TL/H/11712-1
FIGURE 1
OUTPUT STAGE
In the model, Miller compensation was used to obtain an
additional degree.of freedom in setting the open-loop gain,
slew rate, and first pole. The slew rate is defined by:
After the last frequency-shaping stage, the intermediate sIgnal is sent to the output stage. The output stage performs
several important functions including dominant pole, slew
rate limiting, dynamic supply current, short-circuit current
limiting, the balance of the open-loop gain, output swing
limiting, and output impedance. The output stage of the macromodel incorporates several new innovations in order to
accommodate the unique topology of National's CMOS opamps. To understand the unique features of this topology, a
description of the actual amplifier output stage is .in order.
"".!.!.
SR
. C3
while the first pole is determined with the equation:
f 1=
P
2 X
71"
1
.
..
x RS X C3 X (1+ AVOUT)
where AVOUT is the gain of the output stage. Note that the
slew rate can be set with CS while the first pole can be
independently set with the gain of the output stage. A gain
stage consisting of a voltage-controlled current-source G 1
and resistor RS takes the signal· from the last frequencyshaping stage and amplifies it by the balance of the openloop gain (G1 x RS "" AVOL - AVIN - Avou:r). A voltage
clamp made of 01, V2, 02, and V3 limits tlie drive to the
output current-source, G6~ to provide short~cirCuit current
limiting. Since the output stage has gain, output swing limiting is performed althe output node with a clamp consisting
of DS, V4, 06, and VS. A resistor, R17, models the slight
degradation in output swing a~ the amplifier is loaded.
The· main feature of National's CMOS amplifiers is that the
output can swing rail-to-rail. This is accomplished by removing the traditional output buffer and taking the output direCtly
from. the integrator. The output portion of thli! Integrator is a
common-source complementary push-pull gain stage which
functions as a current source., OejJ6nding on load rEisistance, the output stage can have a considerable amount of
gain. However, since the internal compensation capacitor is
referenced to the output node, the slew rate does not significantly change as the output is loaded. Also, loading the
output will reduce the open-loop gain of the amplifier 80that
the first pole will increase in frequency in order to maintain
the gain-bandwidth product of the amplifier.
·1064
DYNAMIC SUPPLY CURRENT
A behavior that is often not included in op-amp macromedels is dynamic supply current. If the output of the model is
an ideal current source, the simulated output current of the
model appears to come from nowhere, i.e., the supply currents do not change. This apparent violation of the second
law of thermodynamics has been solved with diodes 07OS, current sources F5-F6, and associated circuitry. Since
it is important to keep non-linear devices, such as diodes,
out of the signal path, only an ideal ammeter, VAS, was
inserted in the output driver to sense the sinking or sourcing
of output current. Current-controlled current-source, F5, mirrors the current sensed by VAS and forces an equal current
through either 07 or OS depending on its polarity. If current
is being sourced into the load, the current flows from the
positive rail through E1, VAS, and G6 to the output node and
no supply current correction is necessary. However, If the
output stage is sinking current from the load, the current
flows from the output node up through G6, VAS and E1 into
the positive rail. To compensate for this, F5 forces an equal
current through 07 and ammeter VA7. This current is then
mirrored to current-source F6 which pulls an equal amount
of current out of the positive rail and forces it into the negative rail. Therefore, if the output stage is sourcing current, it
appears to come from the positive rail, whereas current that
is sinking from the load appears to go into the negative rail.
The net result of all these extra devices is an output stage
which closely models the behavior of the real amplifier.
and powered from a 3V single supply. Then, a 3 Vpp squarewave was applied to the non-inverting input. The amplifier is
clearly capable of handling this rail-to-rail input and reproducing it on the output while driving a 4.7 kO load. The
simulation results $how that the macromodel accurately
models the slew rate and QUtput swing of the amplifier.
VOUT
.-------------.
I
! I8.7 !
I
1
10101
pF
11 -
-7.SV
1
1
._-----------_.
scope probe
Tl/H/11712-2
Note: It is very important to include a model of the scope probe on the
output of the amplifier to obtain reasonable nssults from the simulation.
FIGURE 2_ Non-Inverting Amplifier (Av
=
+ 1)
• LMC64S4 S.S. Pulse Response. V(6)
• Cload = scope
XAR1 a 6 7 4 6 LMC6484
SIMULATION ACCURACY
VP 7 0 7.5V
VN 40 -7.5V
VIN 3 0 PULSE (-.W .W
To ensure the accuracy of the macromodel, the simulation
results are compared to lab data taken from an actual device. Figure 2 shows a typical voltage follower transient response test circuit and Figure 3 shows a SPICE netlist [4]
for simulating the small-signal transient response of the
LMC64S4. Notice that the simulated response shown in Figure 5 compares quite closely with the actual response
shown in Figure 4 with the correct amount of over-shoot and
frequency of ringing.
au 20N 20N 5U)
Rout 60 10MEGohm
Gout 60S. 7pF
.L1B CMOSOA.LlB
.TRAN/OP .1N 10U
.PROBE
.ENO
Figures 6 and 7 demonstrate the rail-to-rail input and ouput
capabilities of the actual LMC64S4 and the model respectively. The amplifier was configured as a voltage follower
FIGURE 3_ Non-Inverting Amplifier Neliist to Simulate
the Small-Slgnal Response of the LMC6484 [4]
LMC8484 S_s. Pulse Response (V(6) CLOAD = scope)
400mV
200mV
r
OmV
!
I
'Ii
I
l-
-200mV
-400mV
01'1
a V(6)
21'1
TIME
TLlH/11712-4
FIGURE 5_ Simulated Small-8lgnal Transient Response
TLlH/I1712-3
FIGURE 4_ LMC6484 Small-8lgnal Transient Response
1085
LMC6484 L.S. Pulse Re.pOnse
.. (~v = +1,Vsupp = O,+3;R1 = 4.7k) .
YOUT
I.
,.,/M
TUH/11712-5
: [ II
I
1/ U
\1
~ ~r"111111111
O.ps
• ·Y(3)
Note: ThIs Phot!> d8m0nstratea the rall·lo-ralllnput/output capabilities of the
LMC6484 While powwed from a 3V single supply and driving a 4.1 kIl load.
Don' try this with an ordinary op-amp.
201'0
60ps
401"
80ps
1001's
TIME
TUH/11712-6
FIGURE 7. LMC6464 Simulated Lerg8-Slgnal
Transient Response
FIGURE 6. La..ge-Slgn&1 Tran.nt R"~.e
CONCLUSION
REFERENCES
An accurate SPICE macromodel has *11 developed that
captures the "personality" of National Semiconductor's
CMOS operational amplifiers. The macromodel includes ef·
fects such as rail-to-rail output swing, input common-mode
range, MOSFET input stage transfer characteristics, accurate frequency and transient response, slew rate llQd output
short-circuit currant. The model is not capable of Stmulating
PSRR, thermal effects, or noise at this time.
Since the macromodels are much less complex and have
fewer pan junctions than a 1ransistor level micromodel, simulation speed is much faster. For example, an LMC6484 macromodel simulation executed 34 times faster than its transistor level model. With accurate macromodels, tlie designer can quickly determine the dominant effects of a circuit
and explore effects that are difficult to obtain with lab bench
evaluation.
1. Monticelli, D.M.: "A Quad CMOS Single-Supply Op Amp
with Rail-ta-Rail Output Swing", IEEE Joumal of Solid
State Circuits, Dec. 1986 Vol. So.21.
2. Boyle, G.R.: "MaeromOdeling of Integrated Circuit Oper~
ational Amplifiers", IEEE Joums/of SoHd-$tate Circuits,
Dec. 1974 Vol. So.9.
.
.
3. Alexander, Mark: AN-13B Spice-Compstible OpAmp Mscromodels,. Precision Monolithics Inc., Application Note
138.
4. Tuinenga, Paul: SPICE: A Gllide to Circuit Simllfstion &
AnalYsis Using PSpiceR, Prentice-Hall, 1992.
" I':
'.
"',.:',
1066 '.
\,',
National Semiconductor
Application Note 861
Zahid Rahim
Guide to CRT Video Design
INTRODUCTION
This application note provides a design guide for successfully designing high frequency CRT video boards. For better
illustration, an example of a complete video board design
using the LM1203N RGB preamplifier and the LM2419 RGB
CRT driver is provided. The design includes: DC restoration,
contrast control, brightness control, cutoff adjustment, delta
gain adjustment (for white balance) and blanking at grid Gl.
The complete circuitry for the video board is shown in Figure 13. Figure 1 shows the pulse response at the cathode
for a 45 Vpp output signal. Rise and Fall times at the cathode were measured at 6 ns and 7.5 ns respectively and
settling time (to within ±50/0 of final value) was measured
at 20 ns. The overshoot and undershoot were measured at
5V. An NEC-50 multi-sync monitor was used to evaluate the
video board, the performance of the video board was very
good at 1024 x 1024 display resolution. Various sections of
Figure 13's circuit are described below in detail.
1.2 Gain Adjustment and Black Level Clamping
Potentiometers R16 and R25 allow the user to adjust the
gain of the Blue and Green channels respectively for
achieving correct white balance. The gain of the Red channel is fixed by resistor R20. Once white balance is achieved,
the contrast control potentiometer Rll A allows the user to
adjust the gain of all three channels simultaneously.
The black level control potentiometer, R27, allows the user
to clamp the black .level of the video signals to the desired
level. Potentiometer R27 should be adjusted such that the
video signals at the output of LM2419 (CRT driver) are biased within LM2419's linear operating region. To accomplish black level clamping, however, a back porch clamp
signal must be applied to the clamp gate input (pin 14) of
LM1203. The MM74HC86 quad exclusive-or gate generates
the required back porch clamp signal (see section 4.0).
1.0 RGB PREAMPLIFIER (LMl203)
1.3 Preamplifier Gain Peaking for Improved Rise and
Fall Times
The LM1203 is a wideband video amplifier system specifically designed for RGB CRT monitor applications (Reference l-LM1203 Data Sheet). The device includes three
matched video amplifiers, three matched attenuator circuits
for contrast control, and three gated differential input clamp
comparators for black level clamping of the video signal. In
addition, each video amplifier includes a gain adjustment or
"drive" pin for individual gain adjustment of each video
channel to allow white balance adjustment.
1.1 RGB Video Signals
The RGB video signals are AC coupled to the inputs of the
LM1203 preamplifier. As shown for the Green channel (see
Figure 13), Cl AC couples the video signal and R8 references the signal to 2.4 Voe reference voltage from pin 11.
The 75.0 resistor, Rl, is a termination resistor whose value
matches the characteristic impedance of the 75.0 coaxial
cable. Note that if a 50.0 video generator is used with 50.0
coaxial cables to test the video board then 50.0 termination
resistors should be used.
In the absence of R2, the stray input capaCitance of the
LM 1203 would effectively short R1 at high frequencies
causing reflections. The 33.0 resistor, R2 maintains reasonable termination at high frequencies thereby minimizing reflections. Note that the value of R2 should not be much
larger than 33.0 otherwise the rise and fall times of the output Signal would be degraded.
Connecting a small capaCitor from LM1203's drive pins
(pins 18, 22 and 27) to ground peaks the amplifier'S high
frequency gain and Increases the -3 dB frequency. USing
18 pF peaking capacitors (Cl00, Cl0l and Cl02 in Figure
13), LM1203's bandwidth is 70 MHz and rise/fall times under 7 ns. If the LM1203 is used to directty drive the LM2419
without the buffer transistors 01, 02 and 03 then 33 pF
peaking capacitors should be used. Refer to the LM 1203
data sheet for information on frequency response using various peaking capacitor values. To minimize overshoot, the
peaking capaCitor should be less than 60 pF.
1.4 Buffered Output
Some CRT drivers have large input capacitance which
makes it difficult for the preamplifier to directly drive the
CRT driver and yet maintain the required bandwidth. In such
applications, a buffer transistor is used between the preamplifier and the CRT driver (for example, tranSistor 01 for the
Green channel in Flflure 13). The buffer transistor used
should have a high fT at high currents. The LM1203 can
directly drive the LM2419 without sacrifice in bandwidth.
However, buffer transistors have been used in our design to
illustrate a complete design. The overall response of Figure
13's circuit is similar with or without the buffer transistors. A
2N5770 transistor was selected which has a minimum fT of
900 MHz. Note that for fast fall time, the emitter resistor of
the buffer transistor should not be much larger than 330.0.
1067
lOY
TL/H/I17S3--1
(a)
soJ n.
>SY
!
90%
"- r-...
.......
:--
{
I
t" .
I
10%
I
;./
si"
TLlH/11733-2
(b)
sJonl
>SY
90%
I"""
\
\
\
10%
\
\
.,.,.
5r
TLlHI11733-3
(c)
FIGURE 1. Pulaa Response at the cathode for FlgUI'tl 13 's Circuit
1068
2.0 RGB CRT DRIVER (LM2419)
The LM2419 is a high-voltage, wide-bandwidth amplifier that
drives the CRT's cathodes (Reference 2-LM2419 Data
Sheet). The outputs of the LM2419 are AC coupled to the
cathodes (see Figure 13) so that cutoff voltages greater
than 80V can be accommodated at the cathodes. Furthermore, large variation in cutoff voltages can be acccmmodated because of the 120V supply. With the video signal AC
coupled to the cathode, the Signal's DC information is lost.
To restore the DC information of the video signal, the video
signal's black level is clamped at the cathode.
Grids G1 and G2 should also have spark gaps. A 300V and
a 1 kV spark gap are recommended for G1 and G2 respectively. The PC board should have separate circuit ground
and CRT ground. The board's CRT ground is connected to
the CRT's ground pin and also directly connected to the
chassis ground. The spark gap's ground return should be to
the CRT ground so that high arc-over ground does not directly flow through the circuit ground and damage sensitive
Circuitry. At some point on the PC board, the circuit ground
and the CRT ground should be connected. Often a small
resistor is connected between the two grounds to isolate
them (see Figure 3).
2.1 Black Level Clamping (DC Restoratfon)
2.3 Overshoot Compensation
LM2419's overshoot is a function of both the input signal
rise and fall times and the capacitive loading. The overshoot
is increased by either more capacitive loading or faster rise
and fall times of the input signal. The circuitry to reduce
overshoot is shown in Figure 4. Without the compensation
circuit (i.e. without R2 and C1) the overshoot and undershoot for the PC board of Figure 10 were measured at 10%
and 15% respectively (VOUT = 40 Vp.p). With the compensation circuit in place (i.e. with R1 = 24.0, R2 = 3.9 k.o and
C1 = 3 pF), overshoot and undershoot were reduced to 0%
and 3.8% respectively. Inclusion of the compensation circuitry caused the rise and fall times to increase by 1 ns.
The values for the compensation circuit will depend on PCboard layout and LM2419 loading. Here's how to select the
correct component values for the compensation circuit
shown in Ftgure 4:
(a) R1 and R2 reduce the gain of the CRT driver at high
frequencies thereby reducing overshoot.
(b) C1 determines the frequency at which gain is reduced
and introduces a time constant in the pulse response.
(c) The time constant, T = R2 X C1 should be less than
20 ns. Capacitor C1 should be selected to be 3 pF or
slightly larger so as to eliminate the effect of stray capacitance. If C1 Is too large such that T > 20 ns then
the pulse response will be damped, causing long rise
and fall times and therefore picture smearing.
(d) Making R2 too large will cause a damped pulse response, giving rise to picture smearing. If there is a need
to change the high frequency gain to adjust the level of
overshoot then the value of R1 should be changed
since this will not affect the time constant.
Figure 2 shows the black level clamping Circuitry for the
Green channel. Capacitor C25 AC couples the video signal
to the cathode. Transistor 04 and diode 08 clamp the signal's black level to a voltage two diode drops greater than
the voltage at the base of 04. Adjusting the voltage at the
base of 04 using potentiometer R44 adjusts the clamp voltage thereby providing cutoff adjustment. Note that if the video Signal has a sync tip then the clamp circuit will clamp the
sync tip to the clamp voltage. The transistor selected for 04
should have a BVCEO rating greater than 120V and low
junction capaCitance. For our deSign, an MPSA92 PNP transistor was selected. Diode 07 is used to protect transistor
04 from an arc-over. 07 clamps 04's emitter to a diode
drop above 120V and provides a low impedance path for
the arc-over current to flow through D8 and 07 to the 120V
supply. The diodes used should have a high current rating,
low series impedance and low shunt capaCitance. An
FDH400 diode is recommended.
2.2 Arc Protection
The CRT driver must be protected from arcing within the
CRT. To limit the arc-over voltage, a 200V spark gap should
be used at each cathode. Diodes 01 and 02 (see Ftgure 3)
clamp the voltage at the output of LM2419 to a safe level.
The clamp diodes used should have a high current rating,
low series impedance and low shunt capacitance. FOH400
or equivalent diodes are recommended. Resistor R54 in FI{/ure 3 limits the arc-over current while R33 limits the current
into the CRT driver. Limiting the current into the CRT driver
limits the power dissipation of the output transistors when
the output is stressed beyond the supply voltage. The resistor values for R33 and R54 should be large enough to provide optimum arc protection but not too large that the amplifier's bandwidth is adversely affected.
+120Y
+80Y
3
R44 CUTOFF
20k ADJUSTMENT
R33
R45
33k
22
TO CATHODE
FIGURE 2. Black Level Clamp Circuit for DC Restoration
1069
TUH/11733-4
~
icc
r------------------------------------------------------------------------------------------,
(f) Suggested initial starting values for Figure.4's ci~cuit are:
R1 = 24n to 100n, C1 = 3 pF to 6 pF, R2 x C1 <
20 ns.
Flflure 5 shows the pulse response at the output of LM2419,
with and without compensation.
(e) With the value of R2 fixed, increasing the value of R1
will decrease the high frequency gain and therefore reduce the amplitude of the overshoot. Conversely, decreasing the value of R 1 will increase the. high frequency gain and therefore increase the amplitude of the
overshoot.
+80V
3
R33
01
FOH400
22
02
FOH400
Gl
R54
r-w.
C25
1 pF
100V
I
33
G2
BK
SGI
..t
J
200V.
RK
GK
h
CIRCUIT GNO
CRTGNO
(ARC GNO)
~kV
CRTGNO
(ARC GNO)
TL/H/11733-5
FIGURE 3. Arc Protection Circuit
R2
Cl
3.9k
3 pF
Rl
16,20,25 24n
3,4,10
TL/H/11733-15
FIGURE 4. Overshoot Compensation Circuit for LM2419
1070
-
WITHOUT
COMPENSATION
-
WITH
COMPENSATION
(see Figure 41
Vert.: 5V Idiv.
TLlH/11733-16
(a)
-
WITHOUT
COMPENSATION
-
WITH
COMPENSATION
(see Figure 41
Vert.: 5V/div.
TL/H/11733-17
(b)
FIGURE 5. Pulse Response with and without OVershoot Compensation
2.4 Suppressing Oscillation
As is the case with all wideband amplifiers, PC-board layout
precautions must be taken to prevent oscillation. Experimentation had shown that when the LM2419's output was
probed with a passive probe (100:1,5 kO probe) connected
to a 500 oscillOSCOpe, the LM2419's output burst into oscillation. However, when probed with a high input impedance
(1 MO) FET probe the oscillation was not present. Further
investigation showed that the oscillation was caused by: the
inductance of the trace connected between the LM120S's
output and the LM2419's input; type of loading-in this
case, the complex impedance of the 5 kO passive probe;
and high frequency channel-to-channel cross-talk internal to
LM2419. The oscillation can be eliminated by applying the
following guidelines:
(a) Minimize trace length between the preamplifier output
and LM2419 input. If long trace length is unavoidable
then use low value (220 for example) series resistors
with short lead length in the signal path to damp the
Inductance of the trace. Use carbon resistors and avoid
using wire wound resistors because they are inductive.
1071
(b) Avoid long wires to connect the LM2419 output to CRT.
socket. Inductance of the wire can cause ringing and·
possible oscillation depending on the characteristics of
the complex load. Use a low value resistor (500 for example) in series with the output of LM2419 to damp the·
wire's inductance. Since the input impedan~
the
LM2419 is high, the device is susceptible to high frequency cross-talk. If oscillation still persists then lowering the input impedance of LM2419 by connecting' a
1 kO resistor from LM2419's input to ground solves the
problem (R500, R501 and R502 in Figure 13). The 1 kO .
value is empirically determined, a lower value may be
required depending on the PC-board layout and hJad
characteristics.
of
To improve the. rise and fall times at the cathode, a small
iliductOr is often placed in series with the output of the amplifier. The series. peaking. inductor peaks the amplifier'S frequency response at the cathode thus improving the rise and
. fall times. The value of the inductor is empirically deter.• mined. An inductor value of 50 nH is a good initial starting
. value. NClte that peaking the amplifier's frequency response
will increase t\1e. overshoot. Therefore the value of the inductor selected is a compromise between optimum rise and
fall times and acceptable overshoot.
Two 500 series resistors between LM1203 output and
LM2419 input were required to damp the inductance of the
signal trace. Note that in this application, the LM1203 was.
used to directly drive the LM2419 without the use of buffer
transistors. When the series resistors were changed from
carbon to wirewound, the oscillation reappeared because of
the inductive characteristics of the wirewo·und resistors.
At low output voltage swing (for ex: VOUT < 5 Vp_p), the rise
and fall times may degrade by as much as 50% or more.
This is caused by the fact that LM2419 has a class "B"
output stage with a 600 mV dead band, thus giving rise to
cross-over distortion. Increased rise and fall times may give
rise to picture smearing at low contrast settings. Connecting
a 20 kO (YzW) resistor from LM2419's output to ground
bia"es the output stage in class "An mode thus maintaining
similar rise/fall times at both small and large output voltage
swing.
.2.6 Short Circuit Protection
Oscillations can often occur due to ground loop currents.
Having separate power and low voltage ground planes will
help. Refer to Section 7.2 for furthE!r details.
The output of the LM2419 is not short circuit protected.
Shorting the output to either ground or to V + will destroy
the device. The minimum DC load resistance the LM2419
can drive without damage is 1.6 kO to ground or to V +.
HowevE!r, driving. a 1.6 kO load for an extended period of
time is not recommended because of power dissipation
considerations. It the LM2419 is used to drive a resistive
load then the load should be 10 kO or greater.
2.5 Improving Rise and Fall nmes
Because of an emitter follower output stage, the rise and fall
times of the LM2419 are relatively unaffected by capacitive
loading. However, the series resistors (R33 and R54 for the
Green channel, see Figure 13) will increase the rise and fall
times when driving the CRT's cathode which appears as a
capacitive load. The capacitance at the cathode typically
ranges from 8 pF to 12 pF and every effort is made to minimize this capacitance.
3.0 BLANKING AT GRID G1
The circuit used to accomplish blanking is shown in Figure
6. A negative voltage is applied to grid G1 using the resistor
divider comprised of R58 and R60. Brightness control is
achieved by varying the bias at G1 using potentiometer
R60. Blanking at the grid is accomplished by R59, R62, 013
and 034.
.
GRID
Gl
R61
100,1!2W
SGS
C29
0.01
lkV
)"T
..1:
0ov
V
TL/H/11733-6
FIGURE 6. Circuitry for Blanking at the Grid
1072
For thermal and gain linearity considerations, the output low
voltage (white level) should be maintained above 20V. If the
device is operated at an output low voltage below 20V, the
power dissipation might exceed 4.7W per channel (i.e., 14W
power dissipation for the device). Note that the device can
be operated at lower power by reducing the peak-to-peak
video output voltage to less than SOV and keeping the
clamped video black level close to the supply voltage.
Maximum ratings require that the device case temperature
be limited to 90·C maximum. Thus for SO·C maximum ambient temperature and 13W maximum power dissipation, the
thermal resistance of the heat sink should be:
6SA';;: (90 - SO)·C/13W = 3·C/W
Resistor R62 biases the clamp diode D13. A 1S Vpp blanking signal is AC coupled through C34. Since the voltage at
node "B" can not go more than one diode drop above the
voltage at node "A", the blanking signal at G1 is clamped at
the G1 bias voltage.
During the blanking portion of the video signal, the blanking
signal goes low thus reverse biasing D13 and pulling G1
1SV negative with respect to Its normal bias voltage. This
action cuts off the CRT's beam current during the blanking
interval and accomplishes blanking.
4.0 BACK PORCH CLAMP GENERATOR
A versatile backporch clamp generator circuit is shown in
Figure 7. A quad exclusive-or gate (MM74HC86) is used to
generate the back porch clamp signal from the composite
H-Sync input signal. The composite H-Sync input signal may
have either positive or negative polarity. The logic level at
pin 11 (Flag Out) indicates the polarity of the H-Sync signal
applied to the clamp generator. The Flag output is a logic
low (less than 0.8V) if the H-Sync input Signal has a negative polarity and is a logic high (greater than 2.4V) if the
H-Sync input signal has a positive polarity.
5.1 Designing the Proper Heat Sink
Once the required thermal resistance of the heat sink has
been determined, the process of designing the heat sink
can begin. Figure 8 shows the thermal resistance versus the
required volume for an anodized or painted aluminum heat
sink. Note that the curve in Figure 8 is based on lab measurement of Ys' and Y1s" thick sheet aluminum and is only
intended as a design guide. The actual thermal resistance
of the heat sink is affected by many factors such as the
shape of the heat sink, the orientation of the heat sink, etc.
Once a heat sink is fabricated, its thermal resistance should
be measured under actual operating conditions. The following calculations show how to design a heat sink for the
LM2419.
Regardless of the H-Sync input signal's polarity, a negative
polarity H-Sync signal is output at pin 8. Furthermore, a negative polarity back porch clamp pulse is output at pin 3. The
width of the back porch clamp pulse is determined by the
time constant due to R28 and C12. For fast horizontal scan
rates, the back porch clamp pulse width can be made narrower by decreasing the value of R28 or C12 or both. Note
that an MM74C86 exclusive-or gate may also be used, however, the ,pin out is different than that of the MM74HC86.
5.0 THERMAL CONSIDERATIONS
The LM1203 preamplifier does not require a heat sink. However, the LM2419 requires a heat sink under all operating
conditions. For the LM2419, the worst case power dissipation occurs when a white screen is displayed on the CRT.
Considering a 20% black retrace time in a 1024 x 768 display resolution application, the average power dissipation
for continuous white screen is less than 4W per channel
with 50 Vpp output signal (black level at 7SV and white level
at 2SV). Although the total power dissipation is typically
12W for a continous white screen, the heat sink should be
selected for 13W power dissipation because of the variation
in power dissipation from part to part.
O.I~~
0.1
10
VOLUME (CU_'NCHES)
TUH/11733-8
FIGURE 8. Heat Sink Volume vs Thermal
Resistance for Anodized Sheet Aluminum
MM74HC86
:I: H SYNC
INPUT
R30
- H SYNC OUT
100
"'~1
lk
R31
10k
R28
16k
R32
014
lN914
I
BACK PORCH
CLAMP PULSE
lk
jC13
V
D.1J.lF
FLAG
OUT
C12
J120 P F
TL/H/11733-7
FIGURE 7. Backporch Clamp Pulse Generator Circuit
1073
-r-------------------------------~----~
I
Worst case power dissipation for LM2419 (White screen)
l3W
==
(c) The heat sink should be mounted vertically. This causes
the heat sink to lose heat most effectively because cOld
air is drawn to the bpttom of the h~t sink, heated and
moved to the top of the heat sink by convection. Fur·
thermore, mounting the heat sink vertically is especially
useful for heat sinks with fins.
Required heal sink thermal resistance, 9gA = SOC/W .
From thermal resistance curve in Figure 6, required ~olume:
of Aluminum (AI) = 2.2 cu' .
For a sheet of AI with thickness, T = %2",
required area, A = 2.2 cu" /(%al" = 24 sq" = S" x 3"
(d) Either an anodized heat sink should be used or black oil
paint or a dark varnish should be applied to the heat.
sink. This further reduces the heat sink's therm81 resist·
ance due to improved radiation heat transfer.
Therefore select an anodized or painted black. aluminum
heat sink of dimension S" x 3" X%2". Note that if the heat
sink surface is bright or shiny then the thermal resistance is
going to be higher than an anodized or black painted sur·
face because of the heat sink's lower emissivity.
6.0 CONTROLLING ELECTROMAGNETIC
INTERFERENCE (EMI)
5.2 Meaaurlng the Thermal Resistance of the Heat Sink
Whether a heat sink is designed or a commerciall~ designed
heat sink is used, the thermal resistance of the heat sink
should be measured under actual operating cOndition to en·
sure that the measured thermal resistance meets the speci·
fication. If the heat sink's thermal resistance is higher than
the required thermal resistance then the CRT driver's case
may operate at a temperature higher than the recommend·
ed operating temperature thereby adversely affecting the
long term reliability of the device.
Voltage spikes caused by fast switching currents and the
impedance of the supply line and ground connection can
give rise to EMI radiation. An effective way to combat such a
cause of EMI is by making use of power supply filtering and
generous use of ground plane on the printed circuit board.
The ground plane provides a low impedance return for the
fast switching current, thereby suppressing EMI radiation.
To measure the heat sink's thermal.resistance, a thermo·
couple may be used. The LM2419's metal tab is bolted on
to the heat sink with a screw, a washer and a lock nut. The
thermocouple's wire should be securely tightened between
the washer and the tab. Next, with the video board mounted
in the monitor, the LM2419's power dissipation should be
measured. The LM2419's case temperature is then mea·
sured under the operating condition using the thermocouple
device. The measured thermal resistance is then calculated
as follows :
S6metimes an undetected very high frequency (several
hundred MHz) oscillation in the circuitry can give rise to Significant EMI radiation. Such high frequency oscillation may
not be noticeable when viewing images on the screen or
may go undetected if the oscilloscope used is bandwidth
limited when compared with the frequency of oscillation. By
looking at the amplitude and frequency spectrum of the EMI
radiation, one can discern the presence of high frequency
.
oscillation within the Circuitry.
9SA = (To -TA)/PD
Often long. wires carrying high frequency signals can be a
big contributor of EMI radiation. If that is the case then
shielded cables should be used and the shield should be
grounded at both ends. Grounding the shield at both ends
allows the Signal's return current to flow through the shield
at high frequencies. The return current on the shield gener·
ates a field that tends to cancel the conductor's field there·
by minimizing EMI radiation.
where, To = Case temperature
T A = Ambient temperature
PO = Power DiSSipation
For our application, a ¥32" x 6" x 4" sheet of aluminum was
used under actual worst case operating condition. The mea·
sured thermal resistance of the shiny (unpainted) heat sink
was SOC/Wand decreased to 4°C/W after the heat sink was
painted black with an enamel spray paint. Optimizing the
shape of the heat sink could have improved the thermal
resistance to less than 4°C/W. This excercise illustrates
that the guidelines of section S.l can be used to deSign a
heat sink and proper characterization under actual worst
case operating conditions are needed to finalize the design.
Some very high frequency designs require the use of con·
ductive shield enclosures to minimize EMI radiation. In reo
sponse to the offending electromagnetic field, the shield
produces currents which in turn produce magnetic fields
that oppose and cancel the inducing field. A steel enclosure
provides excellent attenuation of EMI radiation through reo
flection and absorption loss (caused by exponential decay
of the electromagnetic wave's amplitude as it travels
through the medium).
5.3 Getting the Beat Performance from the Heat Sink
For best results, the following guidelines should be followed:
(a) A thermal joint compound (such as Thermacote from
Thermalloy or the 340 silicone heat sink compound from
Dow Coming) should be used between the LM2419's
metal tab and the heat sink. The thermal joint com·
pound is a grease that establishes a low thermal resist·
ance between the package and the heat sink by displac.
ing the air gaps.
(b) Proper torquing (i.e., mechanical stress) should be applied so that good thermal contact is established. A
torque of 6 Ib·inch is commonly applied.
. .
There are stringent requirements on the manufacturers of
electronic products to control the emiSSion of electromag·
netic waves. Electromagnetic waves not only interfere with
radio and TV reception but may also affect other electronic
.
devices in the Vicinity of tile source of radiation.
7.0 PC BOARD LAYOUT GUIDELINES
Optimum performance at high frequencies requires careful
attention to PC board layout. Before starting the PC board
. layout the circuit schematic should be carefully studied, high
frequency Signal paths and sensitive nodes should be
marked. Once a well thought out PC board layout plan has
been established, the actual board layout can commence.
The following guidelines are essential for PC boards de·
signed for 100 MHz or greater bandwidth.
1074
7.1 Adequate Ground Plane
For high frequency layouts, a solid ground plane is a must.
The ground plane provides a low inductance path for the
circuit's return current. Moreover, a ground strip between
two high frequency signal traces can reduce cross talk by
referring the stray capaCitance between the traces to
ground.
Because of the many restrictions placed on the layout, a
two sided board is recommended for bandwidths greater
than 100 MHz. On a two sided PC board, a full ground plane
is placed on the component side, for example the top side
of the board. Signal traces are then routed on the bottom
side of the board, this minimizes stray capaCitance and im·
proves the isolation between high frequency Signal paths
because the traces can be widely separated without affecting PC board real estate. Furthermore, a two sided board
also greatly reduces the number of jumpers required when
compared with a single sided board thus allowing optimum
layout. A double sided board, however, adds to the cost of
the board. A double sided board may cost 30% more than a
single sided board. Increasing competition for high volume
and low cost consumer products often necessitate the
choice of a single sided board. If designed right, a single
sided PC board can provide acceptable performance at
100 MHz.
When laying out a single sided PC board, every attempt
should be made to layout a solid unbroken ground plane.
Figure 9(a) shows ground voids along each column of pins
of the IC and is not recommended for high frequency layout
because it breaks up the flow of ground plane from the left
to the right. Such a layout may also compromise the stability
of the video amplifiers. The layout is improved by placing a
ground void around each pin (see Figure 9b) thus ensuring
a continuous flow of the ground plane from left to right.
Some designers use pin sockets to avoid soldering the IC to
the PC board. Pin sockets should be avoided if they reduce
the clearance between the pins and make it difficult to
achieve the layout of Figure 9(b).
(8) LAYOUT NOT RECOMMENDED
(b) RECOil MENDED LAYOUT
TLlH/I1733-9
FIGURE 9. Optimize High Frequency Layout by Having Ground Void around Each
Pin (b) Instead of Ground Voids along the Entire Column of Pins (a).
1075
i....
.- r-------------------------------------------------------------------------------------,
;
Figure 10(a). shows another common error made in many
PC board layouts. Trace "a" as shown in Figure 10(a) runs
both in the horizontal ar:ld the vertical dir(;lCtionthus .breaking up the flow of the ground plane. Too mlllny zig-zag
traces in the horizontal and vertical direction can render the
ground plane rather ineffective. Figure 10(b) shows that using jumpers to connect traces in the. vertical direction maintains the flow of the ground plane from left to' right. This
tech-:\ique '. is espeCiallY necessary
single sided PC
boards. Note that the effect of jumpers, in the signal path
must be considered. Normally jumpers are used in low frequency signal paths. Furthermore, with careful planning,
passive components can often be used as crossunders
such' that signal. traces can pass. under the components
thereby minimizing the number of jumpers required.
.
low voltage ground plane and making a single point ground
connection with. the low voltage ground.eliminated the oscil,
lalion. So, the recommendations, for laying out .. the PCboard llround plane are as follows:
(a) The PC-board should be laid out with a separate power
ground .plane for the CRT driver.
(b) The CRT driver's power supply bypass capacitOrs
should be connected to the power ground plane.
for
7.2 Avoiding Ground Loop
(c) The power ground plane should be' connected to ·the
low voltage ground plane 'at some point on the PCboard. The best place to connect the two ground planes
should be empirically determined during the prototype
design phase.
Use of above guidelines may also reduce ringing atthe preamplifier's output and therefore further improve the overall
system performance.
.
Often oscillations can occur due to ground loop currents.
When the CRT driver's output slews at high frequencies,
large transient current is injected to the ground plane. If
both the preamplifier and the CRT driver share a common
ground plane then the transient current may couple to the
sensitive inputs of the preamplifier and may cause the preamplifier to oscillate ther!lby causing both amplifiers to oscillate. The problem is severe if a wide bandwidth preamplifier such as the LM1203B (100 MHz bandwidth) is used on a
Single sided PC-board.
7.3 Power SUpply Bypassing,
Proper power supply bypassing is very critical for high frequency PC board layout. The power supply should be a low
impedance pOint. However, the parasitic inductance of the
supply lead can cause the power supply to be high impedance at high frequencies. Improper power supply bypassing
can not only produce excessive overshoot and ringing on
the amplifier's pulse response but can also cause oscillation.
.
(see
Figure 12) is
The LM1203 + LM2419 CRT neck board
a single sided board with a single ground plane. Because of
LM1203N's limited bandwidth of 7() MHz, riooscillalions
were observed. However, when the LM1203N was replaced
with the LM1203B, the LM1203B burst into oscillation. Separating the power ground (pin 5) of LM241!l from the
Both the LM1203 preamplifier. and the LM2419 CRT driver
have very low power supply rejection, especially the
LM2419 which has 0 dB power supply relection. Thus any
nolsa or ripple or translents,on LM2419's power supply
pin will appear dlractly at the device's output.
TRACE "a"
MODIFIED
USI~G
JUMPER Jl
'00 ..
U
VOL " O.IV _
Uf--",,":::::':'~ON~..:..,~.I~V- - - - "
TVH/11788-3
FIGURE 3. LM1202 Block Diagram
1084
Figure 4 shows a typical application for a single video channel. The video signal is AC coupled to pin 6. The LM1202
internally biases the video signal to 2.6 Vee. Contrast control is achieved by applying a OV to 4V DC voltage at pin 8.
The amplifiers gain is minimum (i.e maximum signal attenuation) if pin 8 is at OV and is maximum if pin 8 is at 4V. With
pin 9 (drive control) at OV, the amplifier has a maximum gain
of 10.
The complete AGB video preamplifier section is shown on
in Rgure 5. Note that pins 1 and 2 of IC1 are connected to
pins 1 and 2 of IC2 and ICS respectively. This allows IC1 to
provide a master contrast control and optimum contrast
tracking. Adjusting the contrast voltage at pin 8 of IC1 will
vary the gain of all three video channels simultaneously.
Drive control input (pin 9) of each LM1202 allows individual
gain adjustment for achieving white balance.
The black level of each video channel can be individually
adjusted to the desired voltage by adjusting ·the voltage at
pin 19. In a DC coupled cathode drive application, adjusting
the voltage at pin 19 of each IC will provide cutoff adjustment. In an AC coupled cathode drive application, the video
signal is AC coupled and DC restored at the cathode. In
such an application, the video Signal's black level may be
clamped to the desired level by simply biaSing pin 19 using a
voltage divider.
For DC restoration, a clamp signal must be applied to the
clamp gate input (pin 14). The clamp signal should be logic
low (less than 0.8Y) only during the back porch (black level
reference period) interval. The clamp gate input is TIL compatible. Brightness control is provided by applying a OV to
4V DC voltage at pin 19. For example, if pin 19 is biased at
1V then the video signal's black level will be clamped at 1V.
A 510'{} load resistor is connected from the video output pin
(pin 17) to ground. This resistor biases the emitter follower
output stage of the amplifier. For power dissipation considerations, the load resistor should not be much less than
510'{}.
RIGO
Vcc•
+12V
Rl10
200k
Rlf.
20
ClID
iO"PF
Vee1
+'2V
RED
VIDEO
RI15
330
VIDEO
'NPUT
OUT
RI02
3D
RIOl
75
RI04
'Ok
(TO CHANNELS 2 AND 3
F'OR ROB APPLICATION)
CLAWP GATE INPUT
D.OlJAF
TUH/11768-4
FIGURE 4. LM1202 Connection Diagram For Single Channel Application
1085
....
:g
RIOO
Z•
C
Veel
+12Y
RED VIDEO
INPUT
RI03
75
CI04
10/lF
RI04
10k
RI05
5k
DRIVE
O.OI/lF
RI14A
20
CI12A
CI13A
lo.OI/lF 14.7/1F
Veel
RI12A
R113A 51
510
+12V
GREEN VIDEO
INPUT
Rl03A
75
Cl03A
Cl02A
o.I/lFl 0.005/1Fl
CI04A
Rl02A
10I'F
30
Rl04A
10k
RI05A
5k
GREEN VIDEO
OUT
(TO CRT DRIVBR
330
SECTION)
CII4A
lo.II'F
VEE
-IV
DRIVE
O.OII'F
CI12B
CIIlB
lo.oll'F 14.7 /IF
Veel
RII2B
+12V
51
BLUE VIDEO
INPUT
BLUE VIDEO
OUT
Cl04B
RIO~I~/I-F~----~~~----~
75+
Rl04B
10k
Rl0~:~"'DC:RI"'V:-E--"'1"==--1
BACK PORCH
CLAMP SIGNAL INPUT
O.OII'F
TLlHI1I 7BB-S
FIGURE 5. COMPLETE PREAMPLIFIER SECTION
1088
DESIGNING THE CRT DRIVER SECTION
A simplified schematic of the LH2424 is shown in Figure 6.
Resistors R1 and R2 set up the bias voltage at the base of
01, giving rise to 1.2V drop across R3 when V + = + SOY.
With V+ fixed at +SOV, 01 acts as a constant current
source thus developing 1.2V across RS. The quiescent bias
voltage at the base of 02 is therefore approximately 1.7V,
the measured value is closer to 1.SV. The 1.SV DC bias at
the base of 02 appears across Rs and causes 9.7 mA current to flow through RF. If pin 1 is open circuit, 9.7 mA flowing through RF causes the quiescent output voltage to be
approximately 30V, thus biasing the output at one half the
supply voltage. It can be easily shown that for any supply
voltage the circuit output is biased at one half the supply
voltage when pin 1 is open circuit.
Connecting a gain setting resistor, RG in series with the input Signal, VIN and pin 1 accomplishes the task of voltage to
voltage gain. If VIN = 1.SV, the voltage across RG is OV and
Your = 30V. As the input voltage changes relative to the
1.SV DC bias, current is injected into the summing node
(inverting input, pin 1) and flows entirely through the feedback resistor RF because the current through Rs remains
unchanged due to the fixed 1.SV DC bias voltage impressed
across Rs. A current change of ±S.67 mA at the summing
node causes the amplifier's output to swing ± 20V from its
quiescent output DC voltage of 30V. Thus when operating
from V + = SOY, the input Signal should be referenced to
1.SV DC. The amplifier's AC gain is given by, Av =
-RF/RG·
CRT DRIVER SELECTION
LH2424 175 MHz CRT Driver
• CRT driver for 1S00 x 1200 and 2048 x 153S display
resolution
• Single channel CRT driver
• Closed loop transimpedance amplifier
• Internal feedback resistor
Having completed the design of the preamplifier section, we
can start designing the CRT driver section. The LH2424 was
selected because of its 175 MHz bandwidth, low cost and
ease of use. Moreover, the LH2424 is pin and function compatible with similar drivers from Motorola and Philips. The
LH2424 is a transimpedance amplifier with an internal feedback resistor. One external resistor connected in series with
the input accomplishes the task of voltage to voltage gain.
LH2424-KEY SPECIFICATIONS
• 175 MHz large signal bandwidth (at Vo = 40 Vpp)
• 2 ns rise and fall times
• Voltage gain of -13
• Output can Swing 50 Vpp (at V+ = SOV)
LH2424's 2 ns rise and fall times and 175 MHz bandwidth at
40 Vpp output voltage makes the device very suitable for
our design. When coupled with the LM1202 (1.5 ns rise/fall
times), the theoretical rise/fall time for the system is 2.5 ns
and is well within our design objectives.
V+
+60V
5
LH2424
R6
12
r-"t=-\'!v-1~___--1.!9-o
Your
R7
12
AV
= -(lV~) =
-13.6
lis
165
2,3,7,8...--+-.....- - -....-----1
TUH/1176B-6
FIGURE 6. Simplified Schematic of LH2424 CRT Driver
1087
variable capacitor is measured and the capacitor is replaced
with a fixed capacitor of measured value.
Figure 7 shows the schematic of the .complete CRT driver
section. Total series input resistance of lsoa and LH2424's
internal 3k feedback resistor configure the amplifier for a
gain of -20. A peaking capacitor, for example Cl for the
red video channel, is connected across the 1000 input resistor. At high frequencies, Cl bypasses the 1000 resistor,
R2, and significantly increases the amplifier's closed loop
gain thus causing high frequency peaking. Initially for protype design, a 10 pF-120 pf variable capacitor can be selected for Cl, C3 and CS. By varying the value of the peaking capacitor, the pulse response at the output of the
LH2424 can be optimized for fast rise/fall time and low
overshoot. Once the design is optimized, the value of the
The LH2424's pulse response exhibits a low frequency tilt.
This low frequency tilt causes picture smearing on the
screen and can be observed by displaying a black box on a
white background. The low frequency tilt is caused by thermal drift internal to the LH2424 and can be eliminated by
feeding back a portion of the output signal back to the amplifier'S input. As shown for the red video channel, R25, C7
and R26 accomplish the task of tilt compensation. One way
to compensate all three channels Is to display red, green
and blue horizontal bars on a white background and adjust
R26,R28 and R30 until picture smearing is eliminated.
+120Y
Cl
60 TO 120 pf •
Y+
+65Y
BLACK LEYEL
CUT-Off
ADJUSTMENT
03
fOH400
01
fDH400
R3
R6
20k
R7
22k
5
R8
10
TO RED CATHODE
C7, 1000 pf
+120Y
BLACK LEYEL
CUT-Off
ADJUSTMENT
D7
fOH400
05
fOH400
Rll
R14
20k
R15
22k
5
06
fOH400
R16
10
TO GREEN CATHODE
ca,
C5
60 TO 120 pf •
1000 pf
+120Y
Y+
+65Y
011
fOH400
09
fOH400
R19
012
fOH400
5 010
fOH400
BLACK LEVEL
CUT-Off
ADJUSTMENT
R22
20k
R23
22k
TO BLUE CATHODE
C9; 1000 pf
TLfHfl1788-7
FIGURE 7. COMPLETE CRT DRIVER SECTION
1088
As the bandwidth of the driver amplifier is increased, it becomes more difficult to maintain high breakdown voltages.
Although the video preamplifiers can provide full black level
DC restoration, at high resolutions it may become more appropriate to consider AC coupling to the cathode. With AC
coupling the CRT driver amplifier does not have to have a
supply voltage rating high enough to accommodate the DC
offsets required for individual gun matching. Figure 8 shows
the LH2424 operated from a 65V supply, whereas the AC
coupled cathode is operated from a 120V supply, leaving
a much larger voltage range for DC offset adjustment. A
1 ,..,F capacitor couples the signal to the cathode. To restore
the DC at the cathode, the MPSA92 high voltage transistor
and the diode D4 clamp the peak Signal voltage (i.e., black
level or sync tip level) on the cathode side of the capacitor
to 1.4V above the voltage set by the cut-off adjustment potentiometer. For arc-over protection, the second diode D3
prevents the transistor emitter from being pulled more than
0.7V above the 120V supply.
+120V
V+
+65V
03
FDH400
BLACK LEVEL
CUT-OFF
ADJUSTMENT
04
fDH400
R3
5
C2
1 J.lF
CRT
FIGURE 8. AC Cathode Drive with Black Level Clamping
1089
TLlH/11766-6
The high voltage differences betwC\l8n the anode of the CRT
and the gun grids.can often lead .to arc-oversor highly destructive. voltages. being'present on circuit elements connected to the CRT. To limit the potential 'arc-over voltage,
spark gaps are connected from the cathodes and the grids
to ground (see Flguf9 .9). Even with the spark gaps, the arcover voltage may be too high for the CRT driver. For added
protection, clamp diodes are· added to the driver outputs.
These diodes should have a high peak current capability,
low series impedance and a low shunt capacitance for them
to be effective. Adding the 5n and 10n series resistors will
help limit the arc-over current but this extra resistance will
contribute to slower ri~times. The rise· time can be improved by series peaking. A small inductor in series with· the
cathode can improve rise times at the. expense of introduc'
ing more overshoot into the signal. The actual.inductor·value is selected empirically to. get the best compromise. between ov.ershoot and rise time, 50 nH is a good starting
value. To fu~er protect the low voltage circuitry on·the video board from high arc-over current, a small isolation resistor of value 10n to 100n is used to isolate the circuit ground
from the CRTlarc ground.
r-------.---O+
V+
65V
9
Gl
Dl
FDH400
R3
C2
R8
RK
~
5
1 p.F
G2
10
SGl
D2
FDH400
I
OJ
200Vi
GK
]
SG21
200Vi
BK
SG31
~~Yl~0~~~
____________
CIRCUIT GND
~ r_~_~_v 2_0_0V_~ ,
___
]
I
~kV
CRT GND
(ARC GND)
TUH/11768-9
FIGURE 9. ARC Protection
Gl
SUPPLY (-70V)
+120V
R502
2.2M
K
R504
loon (1/2W)
C501
O.OlP.F
1 kV
R501
lOOk
I
Ulrt
15Vp_p
FIGURE 10. CRT Grid Blanking and Brightness Control
1090
TUH/11768-10
The circuit used to accomplish blanking is shown in Figure
10. A negative voltage is applied to grid G1 using the resistor divider comprised of R500 and R501. Brightness control
is achieved by varying the bias at G1 using potentiometer
R501. Blanking at the grid is accomplished by R502, R503,
0500 and C500. Resistor R502 biases the clamp diode
0500. A 15 Vpp blanking signal is AC coupled through
C500. Since the voltage at node "B" can not go more than
one diode drop above the voltage at node "A" the blanking
signal at G1 is clamped at the G1 bias voltage. Ouring the
blanking portion of the video signal, the blanking signal goes
low thus reverse biasing 0500 and pulling G1 15V negative
with respect to its normal bias voltage. This action cuts off
the CRT's beam current during the blanking interval and
accomplishes blanking.
A versatile back porch clamp generator circuit is shown in
Figure 11. A quad Exclusive-OR gate (MM74HC86) is used
to generate the back porch clamp signal from the composite
+H SYNC INPUT
H-sync input signal. The composite H-sync input signal may
have either positive or negative polarity. The logiC level at
pin 11 (Flag out) indicates the polarity of the H-sync signal
applied to the clamp generator. The Flag output is a logic
low (less than 0.8V) if the H-sync input signal has a negative
polarity and is a logic high (greater than 2.4V) if the H-sync
input signal has a positive polarity.
Regardless of the H-sync input signal's polarity, a negative
polarity H-sync signal is output at pin 8. Furthermore, a negative polarity back porch clamp pulse is output at pin 3. The
width of the back porch clamp pulse is determined by the
time constant due to R28 and C12. For fast horizontal scan
rates, the back porch clamp pulse width can be made narrower by decreasing the value of R28 or C12 or both. Note
that an MM74C86 Exclusive-OR gate may also be used,
however, the pin out is different than that of the
MM74HC86.
Jl=========::::n~=======
B.P. CLAMP OUT
Vcc 2
+5V
t H SYNC
INPUT
t-----------~~--~----------------_i,
R30
100
R31
10k
R32
lk
BACK PORCH
CLAMP PULSE
13
C13
C12
O.'I'F~
~'20PF
FLAG
IC = MM74HCBI (QUAD X - OR GATE)
OUT
(LOW FOR -H SYNC INPUT
HI FOR +H SYNC INPUT)
TLlH/II768-11
FIGURE 11. Back Porch Clamp Pulse Generator
SOl
.J:00V
-1--------,
-HI--+--,
BK -IHf--+--.
RK
GK
4.7k
25kV
G2
SUPPLY
0.01 I'F
I kV
I
I
0.01 I'F
I kV
TL/H/I1768-12
CRT Socket Hosiden HPS0380
FIGURE 12. CRT Socket Connection
1091
ADDITIONAl;; READING:
1. Grab, Bemard.. "Basic Television and'Videc Systems;"
(5th edition), McGraw Hill, N.Y.; lS84.
'"
,
2. Rahim, Zahld, "UnderStanding the oPeration, of a CRT
" monitor,"Application Note 656; Natio11al Semiconductor,
Corp.~
1989. "
",
"
' '
A typical connection diagram for the CRT socket is shown in
Figure 12. Note that pinout for the, socket, may be different
depending on the CRT-tube,used. ,',
A photOgraph 'of the fully assembled 1600 x 1280-pixel color CRT monitor is shown inFlgufe 13. The viewable screen
size is 27" with 0.37 mmdot pitch. The horizontal and vertical scan rates are 74kHz and 60 Hz respectively: The monitor weighs 110 Ibs. ' '
Nov,
3. -'- "- , "11,0 MHz CRT,Video amplifier fulfills demands
of,/:Iigh resolution monitors:'Application Note 598, Na->
" tional Semic;ondu~or Corp., April, '!!8~.
4. - - - '~Guide to CRT videc, design:' Application Note
861, National SemiconduCtor Corp.
5. LM1202 data sheet, National SemiCOnductor Corp.
6. LH2424 data sheet, Natiorial'Semicor:JduclOr CorP.
MEASURED DATA
Response at cath~de:
tR = 3.5 ns
IF = 3.4ns
Overshoot = 0.4V
Undershoot = OV
Settling time (±5%) = 12ns
Sub 3 ns rise and fall times can be achieved by including an
inductor in series with the output of the CRT driver. The
value of the inductor is empirically determined, 50 nH is a
good starting value. The inductor will improve,rise and fall
times at the expense of increaSed overshoot.
,
~"
I
'
.
ACKNOWLE,DGEMENTS:
The author would like to acknowledge Ron Page (National
Semiconductor Corp.) for designing the back porch clamp
generator circuit shown in Figure 11.
TUH/11768-13
FIGURE 13. Photograph of Fully Assembled 1600 x 1260·Plxel CRT Monitor
,,r'
1092
Audio Amplifiers Utilizing:
SPIKe™ Protection
National Semiconductor
Application Note 898
John DeCelles
INTRODUCTION
As technology develops, integrated circuits continue to pro-
These advantages, generally provided only in high-end discrete amplifiers, are accomplished by providing a protection
mechanism within a monolithic power package. Since audio
amplifier designers generally need to provide some sort of
protection to the output transistors in order to keep product
failures to a minimum, National Semiconductor'S Audio
Group has designed SPiKe (Self Peak Instantaneous Temperature ("Ke» Protection. This is a protection mechanism
designed to safeguard the amplifier's output from overvoltages, undervoltages, shorts to ground or to the supplies,
thermal runaway, and instantaneous temperature peaks.
vide an advantage to consumers requiring products with
more functionality and reliability for their money. It's been
less than fifty years since the first transistor began to provide audiO amplification to consumers. Technology
changed, bringing to the market higher power discretes and
hybrids with the later development of lower powered monolithics. Today with the development of IC technologies, highperformance monolithic audio amplifiers arrive, allowing
consumers to experience high-power, high-fidelity audio
systems in compact packages.
The OvertureTII Audio Power Amplifier Series possesses a
unique protection system that saves audio amplifier designers components, size, and cost of their systems. This translates into higher-power, more functional, more reliable, compact audio amplification systems.
The following pages will explain in detail each of the protections provided by SPiKe protected audio amplifiers, the advantages they bring to audio deSigners, and why they are
necessary.
Each of the protection sections on the following pages will
refer to Figure 1. (Amplifier Equivalent Schematic with Simplified SPiKe Protection Circuitry) when its functionality is
described.
TlIH/11869-1
FIGURE 1. Amplifier Equivalent Schematic with Simplified SPIKe Protection Circuitry
1093
SELF PEAK INSTANTANEOUS
TEMPERATURE LIMITING (SPIKe)
The uniqueness of SPiKe protected audio amplifiers is its
ability to monitor the output drive transistor's safe operating
area dynamically, regardles,s of an output to ground short,
an output to supply short, or the reaching of its power limit
by any pulse within the audio spectrum.
SPiKe Protection is a "uniquely-smart" protection mechanism that will adjust its output drive capability according to
its output' operating conditions, thus safeguarding itself
against the most stringent power limiting conditions.
As can be seen from Figures 28-C, the safe operating area
is reduced for all pulse widths as the case temperature increases., This indicates that good heatsinking is requi~ed for
optimal operation of the power amplifier. Figures 38-C illustrate the reduction of the safe operating area by the increasing effect of enabling SPiKe Protection on a 100 Hz sine
wave due to increasing case temperatures."
Other power amplifiers on the market provide SOA protection by calculating extemal resistances for adjustable current limiting whose primary function is to keep the amplifier
within its safe operating area. Not only do these amplifiers
requireextemal components, but they aiso have a design
conflict between fault protection and maximum output current drive capability. In order to keep the device from selfdestructing against output shorts to either supply rail, the
adjustable current limit must be Significantly lowered, thus
limiting the device's current drive capability.
As seen in the Current Umiting section, a short to ground
with an input pulse applied to the amplifier will be ,current
limited by the conventional current limiting circuitry for a few
hundred microseconds. When the junction temperature
reaches its limit, SPiKe protection takes over, limiting the
output current further, as the junction temperature tries to
rise above 2500C.
SPiKe protected audio amplifiers provide extensive fault
protection without sacrificing output current drive capability.
Its cirCUitry functions by sensing the'output transistor's temperature, enabling itself when the temperature reaches approximately 250·C. Depending upon the amplifier's present
operating conditions, the device will reduce the output drive
transistor's base current, as shown in Figure 1, keeping the
transistor within its safe operating area
Safe Operating Area
This protection scheme results in the power capabilities being dependent upon the case temperature, the transistor
operating voltages, VeE, and the power dissipation versus
time.
Safe Operating Area
5.-~rr~-'r-~'--r-'
5r-nr~~~~~~~
3:
...
~
'":::00
'"
4
3
~
0
~
= 25°C
TJ = 250°C
TC
o
o
20
O~~~~-L-L-L~~
40
60
80
COLLECTOR-EMITTER VOLTAGE (V)
TLlHI11869-20
o
20
40
60
80
COLLECTOR-EMITTER VOLTAGE (V)
TLlHI11869-21
0
0
20
40
60
TLlHI11869-22
FIGURE 2a. T c = 25"C
FIGURE 2b. Tc = 75"C
FIGURE 2c. Tc = 125"C
SPIKe Protection Response
SPiKe Protection Response
SPIKe Protection Response
TLlHI11869-23
FIGURE 38. TC = 75"C
TLlHI11869-24
FIGURE 3b. Tc = 80"C
1094
80
COLLECTOR-EMITTER VOLTAGE (V)
TLlHI11869-25
FIGURE SC. Tc = 85"C
FlgufBS 4 and 5 are provided for each SPiKe Protected audio power amplifier and should be used to determine the
power transistor's peak dissipation capabilities and the power required to activate the power limit. This information may
help a designer to determine the maximum amount of power
that SPiKe protected amplifiers may deliver into different
loads before enabling SPIKe protection.
Figure 4 shows the peak power dissipation capabilities of
the output drive transistor at increasing case temperatures
for various output pulse widths.
Figuf'9 5 shows the power required to activate SPiKe circuitry at increasing case temperatures over the operating voltage range.
Again, it is evident that good heatsinking and ventilation
within the system are important to the design in order to
achieve maximum output power from the amplifier.
SPiKe protected amplifiers provide the capability of regulating temperature peaks that may be caused by reaching the
power limit of the safe operating area. The reaching of power limits may result from increased case temperatures while
heavily driving a load or by conventional current limiting,
resulting from the output being shorted to ground or to the
supplies.
Pulse Power LImit
Pulae Power LImit
200
:g
z
2
160
iii
en
2i
120
~
,....'"
.......en~
100
\
:g
\
,"
o
0.1
60
,
TC
= 75°C
UII TC = 25°C
40
....
~
20
TC
...'",.
= 1250~,~
10
=250°C
= lOOms
To - 220
\.
"-
::::0
"-
80
iii
en
2i
0
...
;::
......
40
tw
z
~
80
TJ
i'...
TC
""""'25°C
"
75°C
125°C
I
I
o
o
100
=
20
40
60
80
COLLECTOR-EMITTER VOLTAGE (V)
PULSE WIDTH (ms)
TLlHI11B69-27
TLlH/llB69-26
FIGURE 5. Pulse Power DlaalpaUon va Vee
FIGURE 4. Pulse Power Dlaalpatlon va Pulae WIdth
1095
OVERVOLTAGE.....oUTPUT VOLTAGE CLAI\4PING
While, monitoring the output, the Ie also prQvidesSPiKe protection if needed. Finally, SPiKe protected audio amplifiers
possess an internal supply-clamplng mechanism; ,a zener
plus a diode drop from the output to the positive supply rail
and an intrinsic diode drop from the output to the negative
rail. This equates to clamping of approximatEi\ly BV on the
positive rail and O.BV on the negative rail as Can be seen in
Figures 6s and 6b, respectively.
One of the most important protection schemes Of 'an audiO
amplifier is the protection of the output drive transistors
against larQevoltage flyback spikes. These spikes are created by the sudden attempt to change the current flow in an
Inductive load, such as a speaker. When a push-pull amplifier goes into power limit (i.e., reaching the SOA limit) while
drMng ,an inductive load, the cUlTent present in the inductor
c;lrives the output beyond the, supplies. This large voltage
spike may exceed the breakdown voltage rating of a typical
audio amplifier and destroy the output drive transistor. In
general, the amplifier should not be stressed beyond its Abso/ute Maximum (No Signal) Voltage Supply Rating and
should be protected against any condition that may lead to
this type of voltage stress level. This type of protection generally requires the use of costly zener or fast recovery
Schottky diodes ,from the output of the device to each supply rail.
Figures 7a and 7b model the output stage for each overvoltage condition exemplifying how the voltage V!lBveforms are
clamped to their respective values for high frequency waveforms. As shown in the Self Peak Instantaneous Temperature Limiting (SPiKe) section, Figures 2a-o, the safe operating area for lower frequency waveforms is much'smaller
than for higher frequency waveforms. Therefore, the power
limits of low frequency waveforms may be reached much
more easily than for high frequency waveforms. It is due to
this fact that more extreme and more frequent overvoltages
may occur at lower frequencies, as shown in Figures 8-11.
The peak output voltage spikes may increase beyond the
described clamping values due to extreme power conditions, however, the waveforms will decrease to the clamping
values with the discharge of the output inductor current, as
shown in Figure 8. ,
However, SPiKe protected audio amplifiers possess a
unique overvoltage protection scheme that allows the device to sustain overvoltages for nominally rated speaker
loads. Referring to Figure 1, the protection mechanism functions by first sensing that the output has exceeded the supply rail, then immediately turns the driving output transistor
off so that its breakdown voltage is not exceeded. The circuitry continues to monitor the output, waiting to turn the
output drive transistor back on when the overvoltage fault
has ceased"
BASE
.....-_OUTPUT
BASE
TL/H/11869-2
FIGURE 6a. Positive Output
Voltage Clamping Waveform
TUH/11869-3
FIGURE 7a. Output Stage
Overvoltage Model (Vee)
Vee
BASE
.....--_OUTPUT
BASE
TUH/11869-4
FIGURE 6b. Negative Output
Voltage Clamping Waveform
TUH/11869-5
FIGURE 7b. Output Stage
Overvoltage Model (- VEE)
1096
to the amplifier output stage reaching the SOA (Safe Operating Area) limit. For this waveform, the collector-emitter
voltage is quite large, while the output current is also quite
large (4A). Referring to Figures 28-C, it is easily understood
that the SOA power limit has been reached.
When the SOA limit is reached, the SPiKe protection circuitry tries to limit the output current while the inductor tries to
continuously supply the current it has stored. Since the current in an inductor can't change instantaneously, the current
is driven back into the output up through the upper drive
transistor, as shown in Figure 78.
It is this current that causes the large flyback voltage spike
on the output waveform. The peak of the voltage spike can
be found by taking the current going through the output at
the time of the power limit multiplied by the 0.450 emitter
resistor and adding it to the zenar-diode combination. In Figure 6a this would be (2A)(0.45n) + 8V which is approximately 9V, as shown by the cursors. For the lower output
stage, the clamping voltage is controlled by an intrinsic diode that replaces costly output clamping diodes.
In Figure 8, when the current reaches close to zero, the
voltage at the output tends to move towards the output voltage that it would have been if the power limit had not been
reached. This is typical for all overvoltage occurrences. It
should be noted that when the overvoltage fault occurs, the
device is no longer functioning in the closed-loop mode.
In Figure 9, one waveform is actually a sinewave with SPiKe
protection enabled, as in Figures 3a-c, with the same overvoltage spikes as in Figure 8 and the other waveform is the
output current. In the middle of the response, the current is
rising toward 6A when SPiKe is enabied, caUSing a "bite" to
be taken out of the sinewave. The device is just trying to
limit the output current at this point, as explained in the
SPiKe Protection section. The overvoltage flyback spike
then occurs while. the output current discharges to zero.
However, this time when the current reaches zero, the current and voltage must make up for what it had lost and try to
return to its position on the amplified input waveform. The
voltage jumps: up tq its value, but the current must slowly
and continuol,jsly charge up to its place on the current waveform, then continue downward as the lower output stage
starts sinking current. It must be remembered that the current waveform would have been a sinewave if the SOA power limit hadn't been reached.
The lower output stage has the advantage of an intrinsic
diode from the negative rail to the output which can replace
the usual external clamping diode in an audio amplifier. This
intrinsic diode is an advantage of the monolithic IC, capable
of handling the large current flowing through the load at the
time of the power limit.
The system is not protected against all reactive loads since
these clamping diodes will dissipate large amounts of power
that cannot be controlled by the peak temperature limiting
circuitry if the fault is sustained for a long period of time. It
should also be noted that for purely reactive loads, all of the
power is dissipated in the amplifier and none in the load.
This implies that if the load is more reactive than resistive, at
those frequencies, more power will be dissipated in the amplifier than delivered to the speaker. Since the impedance
characteristics of a speaker change over frequency, it is
very important to know what types of loads the amplifier can
and cannot drive in order to not only match the amplifier and
speaker for optimum performance, but also to protect the
amplifier from trying to outperform itself. It is the mismatching of components or low dips in the resistive component of
a complex speaker that can cause an amplifier to go into
power limit. The likelihood of reaching the amplifier's power
limit is greatly reduced when the minimum impedance that
the amplifier can drive is known.
Figures 8-11 are examples of the LM3876 reaching its
power limit, experiencing large flyback voltages from an inductive load, for various input signals and loads.
The test conditions for Figures 8-11 are as follows:
- Using an LM3876
- No external compensation components
- Vee = ±35V
AVCL = 20
- lo/Div. = 2.0Aldiv
- ZL = 7.5 mH + 40 for Rgure 8
- ZL = 7.5 mH + 20 for Flf}ures 9-11
- f = 100 Hz for Figures 8, 9, and 11
...,.. f = 70 Hz for Figure 10
In Figure 8, the 4.5Vpk input signal applied to the amplifier
with a closed-loop gain of 20, produces the severely clipped
34V output voltage waveform, as shown. The sharp 48.5V
overvoltage spike that occurs at the crossover point is due
TL/H/11869-7
TLlH/11869-6
FIGURE 9. Reaching the SOA Power Limit,
f = 100 Hz, SPIKe Enabled
FIGURE 8. OVervoltage Exceeding Clamping Level
1097
MuHiple BOA power limits on the output waveform are the
difference between Ftgul¥lS 9 and' 10. Figure 10.is'intended
to show that multiple SOA power'limits can occur under
extreme loading conditions. The amplifi~:is·trylhg to drive a
70 Hz sinewave. into a 7.5 mHinductor. in series with' a 20
resistor, P,e:subjected to the' fulf'ouiplit
swing plus,ill",ge current draw from the'supply; Thisiype of
stress would destroY"an output stage dlscrete ti-,ansistor
whereas with ~PiKe protected ampliflersl the ~umlnt is internally IimitEld;i thus' pr8v!'lnt1ng 'Its' output:,.t{anlllStdfS from
being destroyed.:'." ' , ' ,
'
"<
,~, " " "'"
One note to make I!boUt this prQtecflOn scheme lii'that the
current limitation is"not sustained indefinitely. In essence,
the output shorts to either supply rail should not be sustained for anY period of time greater thana few seconds.
Frequent temporary' shorts from the outPut to either supply
rail will be protected, however, continued testing of the circuitry in this manner is not guaranteed and is likely to cause
degradation to the functionality and long-term reliability of
the device.
1100':
CH2
Vo
, ,
FIGUBE 1:3b.
TLfHf11889-16
tw =, 100 'lLS,IsPIKe (Not Enabled)
CH1
VIN
CH2
Vo
TLfH/11889~15
FIGURE 13c.
tw =
1 ma, tsPIKe
=
200 ILl
TLfHf11889-14
FIGURE 13d. tw
=
10 ma, tsPIKe
=
195 ILl
THERMAL SHUTDOWN-Continuoul Temperature RI..
An audio system designer's design cycle time is reduced by
eliminating the need for designing tricky thermal matching
between discrete output transistors and their biasing counterparts which are physically located some distance from
each other. Complex thermal sensing and control circuitry
provided from the legendary Bob Widlar, and the ability of
integrating it onto a monolithic amplifier, eliminates the external circuitry and long design time required in a discrete
amplifier design.
SPiKe protected audio amplifiers are safeguarded from
Thermal runaway, an area of concern for any complementary-symmetry amplifier. Thermal runaway is an excessive
amount of heating and power dissipation of the output transistor from an increased collector currant caused by the two
complementary transistors not having the same characteristics or from an uncompensated VeE being reduced by high
temperatures.
If proper heatsinking is not utilized, the die will heat up due
to the poor dissipation of power when the amplifier is being
driven hard for a long period of time. Once the die reaches
its upper temperature limit of approximately 165°C, the thermal shutdown protection circuitry is enabled, driving the output to ground. A pseudo "pop" at the output may occur
when this point is reached, due to the sudden interruption of
the flow of music to the speaker. The device will remain off
until the temperature of the die decreases about 10"C to Its
lower temperature limit of 155°C. It is at this point that the
device will tum itself on, again amplifying the input signal.
As can be seen in Fl{JIJfBS 14 and 15, the junction temperature VB time graph and the response to the activation of the
thermal shutdown circuitry perform In a Schmitt trigger fashIon, turning the output on and off, thus regulating the temperature of the die over time when subjected to high continuous powers with improper heatslnklng.
The intention of the protection Circuitry is to prevent the
device from being subjected to short-term fault conditions
that result In high power dissipation within the amplifier and
thus transgressing into thermal runaway. If the conditions
that cause the thermal shutdown are not removed, the amplifier will perform In this Schmitt trigger fashion indefinitely,
reducing the long-term reliability of the device.
The fairly slow-actlng thermal shutdown circuitry is not intended to protect the amplifier against tranSient safe operating area violations. SPIKe protection circuitry will perform
this function.
1101
TL/H/11889-17
FIGURE 14. Junction Temperature va Time
Off:
:rsD OfF:
TL/H/11889-18
FIGURE 15. Thermal Shutdown Waveform
TLlH/11889-19
FIGURE 16. Actual Thermal Shutdown Waveform
Interfacing the LM 12454/8
Data ·Acquisition System
Chips to Microprocessors
and Microcontrollers
National Semiconductor
Application Note 906
FaridSaleh
TABLE OF CONTENTS
-
A 32-word FIFO register for storage of conversion
results.
-
Interrupt control logiC with interrupt generation for 8 dif·
ferent conditions.
A 16-bit timer register.
1.0 INTRODUCTION
2.0 GENERAL OVERVIEW
2.1 The DAS Progremming Model
2.2 Programming Procedure
-
..,... Circuitry for synchronizing signal acquisition with exter·
nal events.
2.3 A Typical Program Flowchart and Alternative
Approaches
-
2.4 The DAS/Processor Interface
3.0 INTERFACING THE DAS TO HPCTM
MICROCONTROLLERS
3.1 Complete Address Decoding
3.2 Minimal Address Decoding
3.3 Timing Analysis
3.3.1 Complete Address Decoding Circuit
3.3.2 Minimal Address Decoding Circuit
4.0 A SYSTEM EXAMPLE: A SEMICONDUCTOR
FURNACE
4.1·System·Requirements and Assumptions
4.2 DAS Setup and Register Programming
4.3 Microcontroller Programming
4.3.1 HPC Assembly Routines for the Semiconductor
Furnace Example
1.0 INTRODUCTION
The LM12454/8family of data acquisition system (DAS)
chips offers a fully differential self·calibrating 12-bit-t. sign
AID converter with differential reference, 4 or 8 input analog
multiplexer and extensive flexible and programmable logic.
The logic embodies different units to perform specific tasks,
for instance: .
- An instruction RAM for stand·alone execution (after being programmed by the host) with programmable acqui·
sition time, input selection, 8-bit or 12-bit conversion
mode, etc.
-
A parallel microprocessor interface with selectable 8-bit
or 16-bit data accesS.
Because of its functionality and flexibility, working with the
LM12454/8 family may appear to be an overwhelming task
at first glance. However, this is not the case when the user
gains a basic understanding of the device's functional units
and the philosophy of its operation. This note shows how
easy it is to use the LM12454/8 family and walks the user
through the straightforward steps of the interfacing and programming of the device.
The LM12454/8 family has 6 members. The members and
their differences are shown in Table I. For simplicity, the
DAS abbreviation will be used throughout this Application
Note as a generic name for any member of the family. Simi·
larly, the drawings illustrate only the 8 input versions of the
family. Note that this Application Note should be used in
conjunction with the device data sheet and assumes the
reader has some degree of familiarity with the device. How·
ever, a brief overview of the DAS and information related to
the subjects being discussed are given here.
2.0 GENERAL OVERVIEW
2.1 The DAS Programming Model
1 illustrates the functional block diagram or user pro·
gramming model of the DAS. (This diagram is not meant to
reflect the actual implementation of the OAS internal build·
ing .blocks.) The DAS model consists of .the following
blocks:
FigUf9
-
A flexible analog multiplexer with differential output at
the front end of the device.
Limit registers for comparison of the inputs against high
and low limits in "watchdog" mode.
TABLE I: Members of the LM12454/8 Family
Device
Number
Clock
Frequency
(Max,MHz)
Operating
Supply Voltage
(V)
Number of
MUXlnputs
Internal
Reference
Low Voltage
Flag
Yes
LM12454
5
5.0 ±10%
4
Yes
LM12458
5
5.0 ±10%
8
Yes
Yes
LM12H454
8
5.0 ±10%
4
Yes
Yes
LM12H458
8
5.0 ±10%
8
Yes
Yes
LM12L454
6
3.3 ±10%
4
No
No
LM12L458
6
3.3 ±10%
8
No
No
1102
FIFO REG.
VREFOUT
I
I
\
INO
INI
IN2
IN3
IN4
INS
\
IN7
I
I
I
I
\
I
IN6
DATA
a/16-bit
I
\
\
INSTRUCTION RAM
RP=10
INTERRUPT ENABLE REG.
RP,=OI
RP=OO
INTERRUPT STATUS REG.
(RP: RAM Pointer)
LIMIT STATUS REG.
TIMER REG.
(Limits#2)
(Limlts#l)
(Instruotlons)
TUH/I1908-1
FIGURE 1. DAS Functional Block Diagram, Programming Model
-
-
Interrupt generatiQn logic to request service from the
processor under specified conditions. .
-
Parallel interface logic for input/output operations between the DAS and the processor. All the registers
shown in the diagram can be read and most of them can
also be written to by the user through the input!output
block.
-
A controller unit that controls the interactions of the different blocks inside the DAS and performs the conversion, comparison and calibration sequences.
tions are used in the watchdog mode and the user defined
limits are stored in them. Each watchdog instruction has 2
limits associated with it (usually the low and high limits, but
two low or two high limits may be programmed instead). The
DAS can start executing from Instruction 0 and continue
executing the next instructions up to any user specified instruction and, then "loops back" to Instruction O. This
means that not all a instructions need to be executed in the
loop. The Cycle may be repeatedly executed until stopped
by the user. The user should access the Instruction RAM
only when the instruction sequencer is stopped.
The FIFO Register is used to store the results of the conversion. This register is "read only" and all the locations are
accessed through a single address. Each time a conversion
is performed the result is stored in the FIFO and the FIFO's
internal write pOinter points to the next location. The pointer
rolls back to location 1 after a write to location 32. The
same flow occurs when reading from the FIFO. The internal
FIFO writes and the external FIFO reads do not affect each
other's pointer locations.
The DAS has 3 different modes of operation: 12·bit+ sign
conversion, a·bit + sign conversion and a-bit + sign comparison, (also called "watchdog" mode). In the watchdog
mode no conversion is performed, but the DAS samples an
input and compares it with the values of the two limits
stored in the Instruction RAM. If the input voltage is above
or below the limits (as defined by the user) an interrupt can
be generated to indicate a fault condition.
The INSTRUCTION RAM is divided into a separate words,
each with 48 (3x16) bit length. Each word is separated into
three 16-bit sections. Each word has a unique address and
different sections of the instruction are selected by the 2·bit
RAM pOinter (RP) in the configuration register. As shown in
Figure 1, the Instruction RAM sections are labeled Instructions, Umits #1 and Limits #2. The Instruction section
holds operational information such as; the input channels to
be selected, the mode of operation for each instruction, and
how long the acquisition time should be. The other two sec·
The CONFIGURATION Register is the main "control panel"
of the DAS. Writing 1s and Os to the different bits of the
Configuration Register commands the DAS to perform dif·
ferent actions such as start or stop the sequencer, reset the
pointers and flags, enter standby mode for low power consumption, calibrate offset and linearity, and select sections
of the RAM.
The INTERRUPT ENABLE Register lets the user activate up
to a sources for interrupt generation. It also holds two user
programmable values. One is the number of conversions to
be stored in the FIFO register before the generation of the
data ready interrupt. The other value is the instruction num·
ber that generates an interrupt when the sequencer reaches
that instruction.
The INTERRUPT STATUS and LIMIT STATUS Registers
are "read only" registers. They are used as vectors to indio
cate which conditions have generated the interrupt and
what limit boundaries have been passed. Note that the bits
-
-
A fully-differential, self·calibrating 12-bit+ sign AID
converter.
A 32-word FIFO register as the output data buffer.
An instruction RAM that can be programmed to repeat·
edly perform a series of conversions and comparisons
on the selected input channels.
A series of registers for overall control and configuration
of the DAS operation and indication of internal operational status.
1103
Defining a general programming procedure is not practical
due to the extreme flexibility of the ,DAS and the variety of
the applications. However, the following typical procedure
,demonstrates the basic, concepts of the DAS start-up routine:
are set in the status registers upon occurrence of their corresponding interrupt conditions, regardless of whether the'
condition is enabled for external interrupt generation.
The TIMER Register can be programmed to' insert a delay
before eXecution of each instruction. A bit in the Instruction
register enables or disables the insertion of the delay before
the execution of an instruction. '
,
-
Reset theDAS by setting the RESET bit and Select RAM
section "00" through the Configuration register.
Appendix A shows all the DAS accessible registers and a
brief descripti,on of their bits assignments. These bit assignments are discussed in detail in the data sheet and are repeated here fClr reference. There are also er:npty register
models available on the same pages that can be used as a
programming tool. The designer can fill these register models with "1s" and "Os" during deSign based on system requirements. The user can also use these sheets for design
documentation.
-
Load instructions to the Instruction RAM (1 to 8 instructions).
-
Select RAM section "01" (if used) through the Configuration register.'
-
Load limitS #2, 1 to 8 values (if used).
2.2 Programming Procedure
-
Initialize the Interrupt Enable register, by selecting the
conditions to generate an interrupt at the lliIT pin (if
used).
The DAS is deSigned for control by a processor. However,
the functionality of the DAS off loads the proCessor to a
great extent, resulting in reduction of the software overhead. At the start, the processor downloads a set of operational instructions to the DAS' RAM and registers and then
gives a start command to the DAS. The DAS performs continuous conversions and/or comparisons as dictated i)y the,
instrllctions and loads the conversion results in the FIFO.
Froin this point the processor has tWo basic options for interactionwith the DAS. Tile DAS can generate an inten:upt
to, the processor when the predetermined number of conver!lion results are stored in the FIFO or when any other
interrupt conditions have occurred. The processor will then
service the interrupt by reading the FIFO or taking corrective
action, depending on the nature of the interrupt. Alternatively, rather than responding to an interrupt, the processor at
any time can read the data or give a n!3W command to the
DAS.
' '
,
.,
-
Load limits # 1, 1 to 8 values (If used).
-
Select the RAM section "10" (if used) through the Configuration register.
-
Program the Timer register for required delay (if used).
-
Start the sequencer operation by setting the START bit
in the Configuration register. Set the other bits in the
Configuration register as required at the same time.
After the, DAS starts operating, the processor may respond
to interrupts from the DAS or it may interrogate the DAS at
anytime.
'
2.3 A Typical Program Flowchart and Alternative Approachea
A typic~1 DAS ,program flowchart is shown in Figure 2.' Figure 2a shows the initialization of the DAS and the start of
the conversions. Figure 2b shows the gep!!,ral fo~ of the
DAS interrupt service routine. It is assumed that the DAS
interacts with the processor through an interrupt line. This
means the host processor generally is busy with other tasks
and responds 'to theDAS through its interrupt service routine .
~
1Hl4
I Processor
Initialization
I
DAS Initialization
• Re.et tho DAS, S.lect RAM Section 0 (RP
=00)
(Write 0002H to CONfiGURATION Register)
• Load Instructions to INSTRUCTION RAN
(Write 1 to 8 Instruction., System Dependent Values)
=
• Select RAM Section 1 (RP 0 0, If U.ed
(Write 0100H to CONfiGURATION Register)
• Load Limit. # 1 to INSTRUCTION RAN, If Used
(Write 1 to 8 Limits, System Dependent Values)
• Select RAN Section 2 (RP
= 10),
If Used
(Writ. 0200H to CONfiGURATION Register)
• Load limits #2 to INSTRUCTION RAM, If Used
(Write 1 to 8 Limits, System Dependent Values)
• Initialize INTERRUPT ENABLE Register, If Used
(Conditions to Generate Interrupt at INT Pin)
• Initialize TIMER Register, If Used
I
Enable the Processor Interrupts if Not Enabled
I
Perform full Calibration
(Write 0008H to CONfiGURATION Register)
I
I
....
I
Start the DAS Conversion.
I
I (Write OOOO,OOOO,PPPO,POO 1 to CONfiGURATION Register) I
....
I Procossor Performs Other Tasks
and Responds to the DAS Interrupts
I
TL/H/1190B-2
FIGURE 2a. A Typical Program Flowchart for the DAS Initialization and Start of Conversions
1105
Perform the Processor Ho~ .. ,~ee in '; e•• PUSH Instructions, If Needed
Stop the DAS Convor.lons
(Write OOOOH to CONFIGURATION Register)
Road and Store the DAS' INTERRUPT STATUS Register
(The location for storage i. callod DAS_INT_IiEM)
'One of the limits has been passed.
Correctivi action to be taken by the processor.
Specified Instruction has been ,eached.
Conversion results to be read from the OAS.
Specified number of results is storod in FIFO.
Conversion results to be read from the DAS.
Auto Zero calibration is completed.
Roset the CAS.
Full calibration is completed.
Reset the CAS.
An instruction with PAUSE has boen reached.
Conversion results to be read from the DAS.
Low voltage has been detecled.
Corrective action to b. taken by the processor.
Return From STANDBY, DAS i. ready
Reset the DAS •
• Perform the Proce.sor Hous. K..ping, e.g. POP Instruclions, If Noedod
• Start the DAS Conversions
(Write OOOO,OOOO,PPPO,POO 1 to CONFIGURATION Register)
• Return from Interrupt
TL/H/II908-3
FIGURE 2b. A Typical Program Flowchart for the DAS Interrupt Service Routine
1106
There is a processor initialization step at the start of the
flowchart. It is included as a reminder that some specific
processor initialization may be needed just for interaction
with the DAS.
the logic family being used, and the loading (resistive and
capacitive) on the data bus being driven by the DAS, all can
affect conversion noise. Nevertheless, reading during conversions has been shown not to cause serious accuracy
problems in most systems.
There are two timing issues regarding the reading during
conversion.
During any read or write from or to the DAS, the DAS internal clock will stop while the ~ is low. This is done for
synchronization between external and internal bus activities,
thus preventing internal conflicts. Note that reads and writes
are asynchronous to internal bus activities. A pause of internal clock cycles will increase the total acquisition plus conversion time for each instruction. The amount of this time
increase is variable and is not easily predictable, because
the processor and the DAS work asynchronously. As a result, the user should not perform reads during conversions if
the fixed time intervals between the signal acquiSitions are
critical in the system performance.
The DAS initialization steps are a series of write operations
to the DAS registers. These steps are the same as mentioned in Section 2.2.
A full calibration cycle is usually performed after setting the
DAS' registers. This is required for 12-bit accuracy. You may
choose to perform one full calibration at power up, or periodic calibrations at specified time intervals, or conditionbased calibrations, e.g., calibrations after a specified
change in temperature. Calibration is done by writing the
appropriate control code to the Configuration register. A full
calibration cycle takes about 1 ms (989 /los) with a 5 MHz
clock and about 0.6 ms (618 /los) with an 8 MHz clock. You
can insert a delay after starting a calibration cycle, or can
detect the end of calibration by an interrupt, or by reading
the Interrupt Status register for the corresponding flag bit In
the flowchart, the end-of-calibration detection is handled in
the interrupt service routine. The full calibration cycle affects some of the DAS' internal flags and pOinters that will
influence the execution of the first instruction after calibration. To avoid false instruction execution, the DAS should be
reset after a calibration cycle. This is shown on the flowchart for the interrupt service routine.
After a calibration, the DAS is ready to start conversions.
Conversion is initiated by writing to the configuration register
and setting the START bit to "1". The data to be written to
the configuration register is shown in binary format in the
flowchart. The bits shown by "P" (program) are the control
bits thet determine different modes of operation during conversions. All the other bits should be programmed as
shown. As mentioned before, the host processor can perform data manipulation and other control tasks after starting
the DAS, and will respond to the DAS interrupts as required.
The second timing issue depends on the speed of the conversions and the speed of the read cycles from the FIFO.
The rule is to read the FIFO fast enough that old data will
not be overwritten with new data during continuous conversions.
Returning to the flowchart, the main task of the interrupt
service routine is to read the DAS' Interrupt Status register
and test its bits for the source of the interrupt. The interrupt
service routine shows all the interrupt bits in the DAS being
tested. However, real systems often use only a few number
of the interrupts, so the extra bit tests should be eliminated
from the routine. Also, the sequence in which the bits are
tested depends on the priority level of the interrupts in the
system. The tasks to be performed for each interrupt are
mainly system related and are not elaborated upon in the
flowchart. If conversions are stopped at the start of the interrupt service, one possibility is to restart conversion before returning from the interrupt service routine. Otherwise
conversions will be restarted again at some other point in
the system routines.
At the start of the interrupt service routine (Figure 2b), a
zero is written to START bit in the Configuration register, to
stop the conversion. Stopping the conversion is not necessarily needed unless it is required for accuracy or timing
purposes. Generally the results of conversions will be noisier and less accurate if reads or writes to and from the DAS
are performed while it is converting. However, the degree of
this inaccuracy depends on many aspects of system design
and is not easy to quantify. Power supply and ground routing, supply bypassing, speed of logiC tranSitions on the bus,
Multiplexed
Address/Data
2.4 The DAS/Processor Interface
The interface between the processor and the DAS is similar to a memory or I/O interface. Some possible DASI
microcontroller interface schemes are shown in Figures 3,
4 and 5.
Data Bus
DO (DO)
0115
Alo
A·.
HPCTM or 8051
Mi.rocontroller
Families
ALE
D~
INO
INl
LMl2458 IN2
Cs DAS
I------..J
~~--------------_H
ALE
INS
~
IN6
WRI----------------M WR
Interrupt Input
Analog
Inputs
IN7
INT
TL/H/I1908-4
FIGURE 3. LM12458 to HPC or 8051 Mlcrocontroller Interface
1107
CD
~
Z•
CC
DiO
Multipi~.ed
' Addre.s/Data
0'7
AiO
68Hell
Mlerocontroller
family
A'4 LM12458 IN2
IN3
CS DAS
.AS
IN4
Analog
Inputs
ALE
E
IN6
R/W
iiR
Interrl',pt I,nput
IN7
INT
TLlHI11908-5
FIGURE 4. LM12458 to'68HCIi Mlcrocontroller Interface
Iotultiple.ed
Addre.s/Data
i D~
DO ( D l
Data Bu.
D15
HPCTM or 8051
Mierocontroller
Address Bus
Families
Any Addre.s lin •• Hi her than A4 I
t>o- ..
"
~O
'
:
INO
IHl
A4 L1.l1245,8 IN2
DAS IN3
CS
IN4
ALE
ALE
INS
Ro
Viii
Ro
iiR
IN7
Intorrupt Input
INT
Analog,
Inputs
IH6
TL/H/11908-8
FIGURE 5. LM12458 to' HPC O'r 8051 Mlcrocontrollerlnterface (MInimum System)
external address latches are not required by the system~
The DAS can be accessed In either a-tilt or 16-bit data
width. BW (Bus Width) Input pin selects the 6-bit or 16-bit
access. In 6-blt access mode, each 16-blt I/O register is
accessed in 2 cycles. Address line AO selects the lower or
upper portions of a 16-bit register. In 16-blt access mode,
address line AO Is a "don't care". As shown in the F/{Jures
611 and 6b, the DAS appears to the processor as 14 separate 16-blt or 28 separate 8-bit I/O locations.
From the processor's point of view, the DAS is a group of
I/O registers with specifIC addresses. Figure 6 illustrates the
DAS registers with their address'8SslgnmentS and,the DAS
interface buses and control signals. The DAS provides standsrd architecture for address, data and control buses for
parallel interface to processO'rs. The DAS can be interfaced
to both multiplexed and non-multiplexed address/data blis
architectures. An ALE input and internal latches allow the
DAS to interface to a multiplexed. address/data bus when
1108
8 bit
INSTRUCTION RAM
ADD=OOOO I
ADD=OOOII
ADD=OOIO I
ADD=OOIII
ADD=OI 00 I
I
ADD=OIOII
ADD-01101
ADD=OIIII
I
I
RP
~
(Read/Write)
I
I
I
I
I
ADD=OOOOO
ADD=OOOIO
ADD=OOIOO
ADD=00110
ADD=01000
ADD=01010
ADD=01100
ADD=01110
= 10
Limits #2
ADD=OOOOI
ADD=00011
ADD=OOIOI
ADD=00111
ADD=OIOOI
I
ADD=01011
ADD=OIIOI
ADD=01111
RP = 01
limits #1
I
I
(RP = RAM Pointer)
(ADO = A4.A3.A2.AI.AO)
I
I
I
I-
I
ADD=OOOOO
ADD=OOOIO
ADD=OOIOO
ADD=OOIIO
ADO=OIOOO
ADD=OOOOI
ADD=OOOII
ADD=OOI 0 I
ADD=OOIII
ADD=01001
I
ADD=OIOIO
ADD=OIIOO
ADD=OIIIO
ADD=OIOII
ADD=OIIOI
ADD=OIIII
RP = 00
I
I
I
I
I
I
I
Instructions
ADD=OOOOO
ADD=OOOIO
AOD=OOIOO
AOD=OOIIO
ADD=OIOOO
ADD=01010
ADD=OIIOO
ADD=OIIIO
(Read/Write)
CONFIGURATION REGISTER
AQD=IOOOI
"
INTERRUPT ENABLE REGISTER
ADD=IOOII
ADD=IOOIO
"
INTERRUPT STATUS REGISTER
ADD=IOIOI _
ADD=IOIOO
I
ADD=IOOOO
(Read/Write)
A
,
D7 _. DO
DATA
A4 •• AO
ADDRESS
ALE
SYSTEM
(Road Only)
(Read/Write)
TIMER REGISTER L....;A;:;D;;.D=_I;.;O..;I.;.I.;.I.....'....;A;:;D;;.D=_I;.;O;.:I.;,I;;.0--l
DAS
cs
(Read Only)
1_ ~~D:~I~'!.I __:__AE~=~ ~O~'!. _I
(64 Locations. 2 address.s) ---------r--------(- - - - - - - - -:- - - - - - - - - J
Rii
CONVERSION FIFO
ViR
iNT
(R.ad Only)
LIMIT STATUS REGISTER
-ADD=IIOII
I
ADD=IIOIO
TL/H/II908-7
FIGURE 6a. DAS Registers, Address Asslgnments,lnterface Buses and Control Signal8 for 8-Blt Bus Width
~
INSTRUCTION RAM
-
(Read/Write)
________16 bit________
~A,
ADD=OOOOX
ADD=0001X
ADD=OO lOX
ADD=OO 11X
ADD=0100X
ADD=0101X
ADD=OOOOX
ADD=OOOOX
ADD=OOOIX
ADD=0010X
_ ADD=001IX
ADD=0100X
ADD=010IX
ADD=OOOIX
ADD=OOIOX
ADD=OIIOX
ADD=OIIIX
ADD=OIIOX
ADD=OIIIX
-
RP - 10
(RP = RAM Pointer)
(ADD = A4.A3,A2.A1,AO)
-
ADD=OOIIX
ADD=OIOOX
ADD=OIOIX
ADD=OIIOX
ADD=0111X
RP - 00
RP - 01
Llmlts'l
Limits #2
~
Instruction.
(Rood/Write)
CONFIGURATION REGISTER ' -_ _ _ _
AD;.;D..=.;,I.;.OO;.;O;;;X_ _ _....I
(Road/Write)
A
'I
"
INTERRUPT ENABLE REGISTER ...._ _....;.A;:;D;,.D=...;I..;O.;.OI..;X_ _ _ _..I
"
INTERRUPT STATUS REGISTER
ADD=1010X
TIMER REGISTER
ADD=IOIIX
D15 •• 00
DATA If
(Read Only)
A4 .• AO
ADDRESS If
SYSTEM
ALE
cs
(Read/Writ.)
DAS
(Read Only)
Rii
(32 Locations, 1 addr.,,)
ViR
(------------------)
iNT
(Read Only)
LIMIT STATUS REGISTER
ADD=1101X
TL/H/II908-8
FIGURE 6b. DAS Registers, Address Assignments, Interface Buses and Control Signal8 for 16-81t Bus Width
1109
~
~
cc
,--------------------------------------------------------------------------,
formance 16-bit microcontrollers. The HPC family is available in a variety of versions suitable for specific applications. The reader is encouraged to refer to HPC family data
sheets for complete information, available versions, and
their specifications. The HPC46083, a 16-bit microcontroller
with 16-bit multiplexed data and address lines, is one of the
simplest members of the family. It is a complete microcontroller containing all the necessary system timing, internal
·Iogic, ROM, RAM, and 1/0, and is optimized for implementing dedicated control functions in a variety of applications.
Its architecture recognizes a single 64k byte of address
space containing all the memory, registers and 1/0 addresses (memory-mapped 110). The addressing space of the first
512 bytes (OOOOH to 01 FFH) contains 256 bytes of on-Chip
user RAM and internal registers. (The address values are
given in hexadecimal format with suffix "H" as an indicator.)
The last 8 kbytes of the address space (EOOOH to FFFFH)
are on-Chip ROM used mainly for program storage. In the
following applications, the HPC46083 is setup for the expanded mode (as opposed to the single-chip mode) of operation that allows the external address range (0200H to
DFFFH) to be accessed. The external data bus in the HPC
family is configurable as 8-bit or 16-bit, allowing it to efficiently interface with a variety of peripheral devices.
The interface should. provide the address, data and control
signals to the DAS with the following requirements:
- An address decoder is needed to generate a chip-select
for the DAS within the required address range.
- The switching relationship between ALE,. OS, 'A15, WR,
address bus and data bus should satisfy the DAS timing
requirements. (Please refer to the data sheet for timing
requirements.)
-
When the DAS is working in an Interrupt-driven 1/0 environment, a suitable service request link between the
DAS and the system should be provided. This can be as
simple as connecting the DAS' lliiT output to a processor's interrupt input or as sophisticated as using interrupt
arbitration logic (interrupt controller) in systems that
have many 110 devices.
Figure 3 illustrates the generic interface for the National
Semiconductor's HPC family of 16-bit microcontrollers and
the 8051 family of 8-bit microcontrollers. Figure 4 illustrates
the interface for the 68HC11 family of microcontrollers or
the processors with similar control bus architecture. The circuits in Figures 3 and 4 are the maximum system schemes
assuming the microcontroller is acceSSing other peripherals
in addition to the DAS, therefore external address latches
and an address decoder are required to select the DAS as
well as the other peripherals. The size and complexity of the
address decoder, however, depends on the system. In a
minimum system scheme, the DAS can be interfaced to the
microcontroller with minimal externaliogic for address latches and address decoder. This is shown in Figure 5. Note
that the DAS' ~ signal is also latched with the ALE inside
the DAS, so a higher order address bit can be used to drive
OS input. In this scheme a wide range of addresses (with
many bits as "don't cares") are used to access the DAS.
Care must be taken not to use this address range for any
other memory or 1/0 locations. For example, lets assume bit
A15 is used for ~, and must be 1 (inverter in place) to
select the DAS. As a result, all the 32k of the upper address
range is used for the DAS. However, address bits A5 to A 14
are "don't cares" and the DAS can be mapped anywhere
within the upper 32k of the address range.
Interrupt handling is accomplished by the HPC46083's vector interrupt scheme. There are eight possible Interrupt
sources for the HPC46083. Four of these are maskable external interrupt inputs. These inputs can be programmed for
different schemes, e.g., interrupt at low level, high level, rising edge or falling edge. One of these interrupts is used for
interface with the DAS. The term "HPC" will be used
throughout the remainder of this discussion to refer to the
HPC46083.
Two different interface circuits are presented in Figures 7
and 8. The first circuit in Figure 7 uses complete address
decoding with the external address latches. This scheme
assumes the HPC is accessing other devices using other
address ranges. The circuit in Figure 8 assumes the DAS is
the only (or one of a few) peripherals interfaced to the HPC,
so incomplete address decoding is used for minimum interface logic. Note that the address decoding schemes used in
these circuits are only two of many different possibilities and
are presented as generic forms of address decoding. These
circuits are used as vehicles to illustrate the issues regarding the interface, and different schemes with other logic
families or PAL devices can also be used for interface circuits.
3.0 INTERFACING THE DAS TO HPC
MICROCONTROLLERS
In this section we are going to develop a detailed interface
circuit between the HPC46083 microcontroller and the DAS.
The HPC46083 is a member of the HPC family of high per-
1110
DA[O.t 15] DATA. BUS
•
U2
ADD[O .. 7] ADDRESS BUS
ADDO
T
Bt.tHz
II
U6
DO
eLK
D1
02
03
D.
II;;~
U,
Ifill II
--
IIII
(TOX)BO
7
"
'2
••
••
I
1
I
I
g;
1
A8
1
.5 •
2
'8
JPI.--,g
3§}o
3 .. }
II
I"2
(T3-~D
SO 85
CKX 83
(12-1/0
(
,
"'
SK B6
'5.
(il[DA)B7
I
v:
"Ig~
Pi
__ Q6
Q7
H~~~:
(~~~~~UItA====~
oR$B12
Vee
/ <: High or low limit determination, 0 = Inputs lower than limit generate interrupt, 1
generate interrupt
015-010 - Don't Care
PROGRAMMER'S NOTES:
Symbol:
Instruction" 0, Limit" 1: Address:
Note:
07-00:
08:
09:
I
015
1
014
1
013
1
012
1
010
011
I
Hexadecimal value:
Instruction" 1, Limit" 1: Address:
Note:
I
015
1
014
1
013
1
012
1
D6
D5
D4
03
02
01
DO
1
D6
D5
D4
03
02
01
DO
07
09
09
1
Symbol:
1
011
010
I
os
09
1
Hexadecimal value:
Instruction " 2, Umlt " 1: Address:
Note:
Symbol:
Hexadecimal value:
Instruction" 3, Limit" 1: Address:
Note:
Symbol:
Hexadecimal value:
Instruction" 4, Umlt " 1: Address:
Note:
Symbol:
Hexadecimal value:
Instruction " 5, Umlt " 1: Address:
Note:
= Inputs higher than limit
Symbol:
Hexadecimal value:
Instruction" 6, Limit" 1: Address:
Note:
Symbol:
Hexadecimal value:
Instruction" 7, Limit" 1: Address:
Note:
Symbol:
Hexadecimal value:
1127
07
APPENDIX A
INSTRUCTION RAM (Read/Write): (Continued)
07-00:
D8:
• Limit: 8·bit limit value
• Sign: Sign bit for limit value, 0 = Positive, 1 = Negative
· > / <: High or low limit determination, 0 = Inputs lower thim limit generate interrupt, 1 = Inputs higher than limit
generate interrupt
',
"
09:
D15-010
• Don't Care
PROGRAMMER'S NOTES:
Instruction "" 0, Limit "" 2: Address:
Note:
Symbol:
Hexadecimal value:
Instruction"" 1, Limit"" 2: Address:
Note:
Symbol:
Hexadecimal value:
Instruction "" 2, Limit "" 2: Address:
Note:
Symbol:
Hexadecimal valua:
2: Address:
Symbol:
Instruction "" 4, Limit "" 2: Address:
Note:
Symbol:
Instruction "" 3, Limit ""
Note:
Hexadecimal value:
Hexadecimal value:
Instruction "" 5, Umlt "" 2: Address:
Note:
Symbol:
Hexadecimal value:
Instruction "" 6, Umit ", 2: Address:
Note:
Symbol:
Hexadecimal value:
Instruction'" 7, Limit", 2: Address:
Note:
Symbol:
Hexadecimal value:
1128
APPENDIX A: Registers Bit Assignments and Programmer'. Notes
INTERRUPT ENABLE REGISTER (Read/Write):
015
I 014 I 013 I 012 1011
Number of results in FIFO to
Generate Interrupt (lNT2)
010
I
091
D8
Instruction Number
to Generate Interrupt
(lNT1)
'[)7
D6
05
INT7
INT6
INT5
D4
D3
INT4: 1NT3
02
01
Do
INti
INT1
INTO
01:
• INT1: Generates interrupt when the programmed instruction (010-08) is. reached for execution
02:
• INT2: Generates interrupt when number of ,conversion results in FIFO is equal.to the programmed
.
.
. ,
value (015-011)
03:
04:
• INT3: Generates interrupt when an auto·zero cycle is completed
·INT4: Generates interrupt when a full calibration cycle is completed
05:
06:
• INT5: Generates interrupt when a pause condition is encountered
• INT6: Generates interrupt when low power supply is detected
07:
010-08:
015-011:
• 1NT7: Generates interrupt when the chip is returned from standby and is ready
• Programmable instruction number to generate an interrupt when that instruction is reached foR execution
• Programmable number of conversion results in the FIFO to generete an interrupt
I
Symbol:
015 1 014 1 013,1,0121011
Hexadecimal value:
Interrupt Enable Register: Address:
Note:
Hexadecimal value:
TIMER REGISTER (Read/Write):
Timer delays the execution of an instruction if Timer bit is set in the instruction.
The time delay in number of clock cycles is:
Delay = 32 x N + 2 [Clock Cycles)
PROGRAMMER's NOTES:
Timer Register: Address:
Note:
Symbol
Hexadecimal value:
Timer Register: Address:
Note:
I
015 1 014 1 013
Symbol:
012 1 011
010 1 09
"
;,'
Bits # 0 to 7 enable interrupt generaton for the following conditions when the bit is set to 1.
DO:
• INTO: Generates interrupt when a limit is passed in w,atchdog mode'
PROGRAMMER's NOTES:
Interrupt Enable Register: Address: '
Note:
..
,.
:'
I~
:~
D8
07
Hexadecimal value:
1129
D6
05
02
01
DO
APPENDIX A: Reglatera BIt Aeeigmilenta and Programmer's Notes
FIFO REGISTER (Read only):
011-00:
- Conversion Result
",
For 12-bIt + sign: 12-bit result v8lue
ForS-bit + sign: 011-04 = resultvalue; 03-00 = 1110
012:
015-013:
- Sign: Conversion result sign bit, 0 = Positive, 1 = Negatlv~
-Instruction number associat~ with th~ cOnv~rsion result or tIl~ ~xt~~ sign bit for 2's compl~~nt
arithlMtic, nI~~ by bit 05 (Chan Mask) of Configuration R~glstM
PROGRAMMER'S NOTES:
FIFO Register: Addrns:
Symbol:
Not~:
INTERRUPT STATUS REGISTER (Read only):
BITS # 0 to 7 ~ interrupt flags (vectors) that will ~ Nt to 1 when th~ following conditions occur. Th~ bits Nt to 1 wh~h~r tha
or disabl~ in th~ IntMrupt Enable ~Ister. Th~ bits r~Nt to 0 wh~n th~ raglst~r is raad, or by a d~ raNt
through Configuration raglst~r.
Int~rrupt is ~nabi~
00:
- INSTO: Is Nt to 1 WMn a limit is ~ in watchdog m~
1 WMn tha progra~ Instruction (010-0S) is ruc~ for ~x~ution
1 when number of co~rslon results in FIFO Is ~quaJ to th~ programm~ value (015-011)
03:
1 when an auto-ZMO cycIe,!s compl~
04:
1 when a full calibration cycle Is complet~
05:
- INST5: Is Nt to 1 WMn a pauN condition is encou~
06:
- INSTS: Is Nt to 1 when low power supply Is d~
07:
- INST7: Is Nt to 1 when the chip Is ratum~ from standby and Is rudy
010-08: - Holds tha instruction number being execut~ or will be executed during a PaUN or TimM delay'
015-011: - Holds tha preMnt numbM of convnon rasults in tha FIFO while the device is running
01:
02:
- INST1:
-INST2:
- INST3:
-INST4:
Is Nt to
Is Nt to
Is Nt to
Is Nt to
PROGRAMMER'S NOTES:
Interrupt Status R4IgIater: Addrass:
Note:
Symbol:
1130
APPENDIX A: Registers Bit Aaalgnmenta and Programme". Note.
LIMIT STATUS REGISTER (Read only):
The bits in this register are limit flags (vectors) that will be
, individual instruction limits as indicated below.
DO: • Limit # 1 of Instruction # 0 is passed
01:
02:
03:
04:
05:
06:
07:
08:
09:
010:
011:
012:
013:
014:
015:
,. Limit
• Limit
• Limit
• Limit
• Limit
• Limit
• Limit
• Limit
• Limit
• Limit
• Limit
• Limit
• Limit
• Limit
• Limit
set to 1 when a limit is passed. The bits are associated to
# 1 of Instruction # 1 is passed
# 1 of Instruction # 2 is passed
# 1 of Instruction # 3 is passed
# 1 of Instruction # 4 is passed
# 1 of Instruction # 5 is passed
# 1 of Instruction # 6 is passed
# 1 of Instruction # 7 is passed
# 2 of Instruction # 0 is passed
# 2 of Instruction # 1 is passed
# 2 of Instruction # 2 is passed
# 2 of Instruction # 3 is passed
# 2 of Instruction # 4 is passed
# 2 of Instruction # 5 is passed
# 2 of Instruction # 6 is passed
# 2 of Instruction # 7 is passed
PROGRAMMER'S NOTES:
Limit Status Register: Address
Note:
Symbol:
1131
National Semiconductor
Application Brief 7
Multivibrator/Timer CAD'
Circuit design making, use of monolithic multivibrators and . astable operation is required). The Wnear Databook by' Natimers can be most easily and quickly done making use of a
tional Semiconductor should be consulted for the specifiC
simple CAD (computer aided design) program. Fortunately,
device pinout and additional device functions.
only 2 basic multivibrator types and 1 timer design type exThis program is .in "transportable" BASIC. No INPUT
ist, reducing the program requirements to 3 sets of algoprompts for strings or ELSE statements are used. All IF
rithms.
statements, if true, result in a GOTO. Variable and array
F/gufB 1 provides a view of the basic multivibrator and the
names are unique and are limited to 2 characters in length.
toN (pulse width) determining resistor and capacitor (R 1 and This program consists of multiple statement lines, which
C). the Advanced Bipolar Logic Databook by National Semimust be dissected for SQme unexpanded microcomputers.
conductor Corporation should be consulted for the specific
Some microcomputers may require that the DATA statements on lines 850 and 860 be implemented as strings, and
device pinout and functions.
the READ statement on line 250 be replaced with the string
FigufB 2 is a block diagram showing the basic timer and the
toN (pulse width) determining resistor and capaCitor (R 1 and handling routine.
C) along with the toFF determining resistor R2 (required if
Vee
R1
R1
C
TRIG
TIMER
PULSE OUT
TRIG IN
Tl/H/5248-1
Mulllvlbrators accommodaled by Ihls program are shown In linea 130
through 200 of the "sting.
FIGURE 1
The timars accommodated by this
program are shown on lines 210 and
220 of the listing.
FIGURE 2
100 For 1=0 to 10:PRINT:NEXT
110 PRINT"MULTIV by Bob Nelson - 2/1 183":PRINT:PRINT
120 PRINT"The following multivibrators are available for design:":Print
130 PRINT"DM54174121
One Shots
0"
140 PRINT"DM54174LS122
Retriggerable One Shots with Clear
1"
150 PRINT"DM54174123
Dual Retriggerable One Shots with Clear
2"
160 PRINT"DM54174L123
Dual Retriggerable One Shots with Clear
3"
170 PRINT"DM54174LS123
Dual Retriggerable One Shots with Clear
4"
180 PRINT"DM54174LS221
Dual One Shots with Schmitt-Trigger Inputs 5"
190 PRINT"DM86/9801
Retriggerable One Shots
6"
200 PRINT"DM86/9602
Dual Retriggerable, Resettable One Shots 7"
210 PRINT"LM555/555C
Timer
8"
220 PRINT"LM556/556C
Dual Timer
9"
230 PRINT:INPUT"Enter number representing choice .....•.•. ",N:PRINT
240IFN>9THEN100
250 FOR 1=0 TO N:READ K:READ RN:READ RX:NEXT:IF K < > .693 THEN 270
260 PRINT"Astable or Monostable (A/M)";:INPUT M$
270 INPUT"Ton in nanoSeconds";T1 :IF M$< > "A" THEN 300
280 INPUT''Toffin nanoSeconds";T2:IF 2·T2= "A" THEN 320
310 INPUT"R2 in Kohms";R2
320 IFT1>OANDR1>OTHEN340
1132
TL/H/5248-2
330 INPUT"C in picoFarads";C
340 IF K = .693 THEN 530
350 IFT1>OANDR1>OTHEN490
360 IFT1>OANDC>OTHEN450
370IFR1>OANDC>OTHEN410
380 IF R1 >0 THEN 400
390 R1 = RN:GOSUB 730:GOTO 350
400 GOSUB 710:GOT0690
410 IF K=OTHEN 430
420 T1 =K·C·CR1+.7):GOT0440
430 T1=.7·C·R1
440
450
460
470
480
490
500
510
520
530
540
550
560
570
580
590
600
610
620
630
640
650
660
670
680
690
700
710
720
730
740
GOSUB 720:GOTO 890
IF K =0 THEN 470
R1 = T1/CK·C-. 7):GOTO 480
R1 =T1/C.7·C)
GOSUB 730:GOTO 890
IFK=OTHEN510
C=T1/CK·CR1+.7»:GOTO 520
O=T1/C.7·R1)
GOSUB 790:GOTO 890
IFT1 =0 THEN 570
IF T2>0 AND R1 >0 AND R2>0 THEN 680
IF R1 >OANDT2=OAND R2=0 THEN 680
IF C>O THEN 650
IF R1 = 0 THEN 600
IF C>O THEN 620
IFR1>OTHEN610
R1 = RN:GOSUB 730:GOTO 530
GOSUB 710
T1 = K'CR1 + 2'R2)'C:T2 = K'R2'C:GOSUB 72O:IF M$< > "A" THEN 640
PRINT"Toff = ";T2;"nS"
GOT0690
R2=T2/CK'C):R1 = (T1ICK'C»-2*R2:GOSUB 73O:IF M$<>"A" THEN 670
PRINT"R2 = ";R2;"Kohms"
GOT0690
C=(T1 +T2)/CK'CR1 +2'R2»:GOSUB 790
PRINT:PRINT"Try same part again(yIN)";:INPUT A$:IF A$< > "N" THEN 270
END
PRINT.. ····INSUFFICIENTDATA····..: RETURN
PRINT"Ton = ";T1 ;"nS":RETURN
PRINT"R1 = ";R1 ;"Kohms"
IF R1 > = RN THEN 760
750 PRINT.. •••• ??STABILITY - R1 <";RN;"Kohms ......
760IFR1=";RX;"Kohms ......
780 RETURN
790 PRINT"C = ";C;"pF"
800 IF C> 0 THEN GOTO 820
810 GOSUB710:GOT0640
820 IFC>1000THEN840
830 PRINT.. • .. • ??ACCURACY - C < 1000 PI ......
840 RETURN
850 DATA 0, 1.4, 40, .45, 5, 260, .32, 5, 50, .33, 5, 400, .45, 5, 260
860 DATA .45,1.4,100, .31, 5, 50, .32, 5, 50, .693, .3, 10000, .693.•3, 10000
1133
C) r-------------------------------------------------------------------------------~
"r,"
~
National Semiconductor
Application Brief 10
Fluid Level Control
Systems Utilizing
the LM1830
, Abstract. The LM1830 fluid leV61 detector is a device in-
tended to signal the presence or absence of aqueous solutions. This application brief shows how to implement HIGH/
LOW limit control applications utilizing this device.
Many opportunities exist for a device that can reliably con, trol the operation of pumps or solenoid actuated valves in
fluid level control applications. Applications include sump
pumps, bilge pumps, washing machines, humidifiers, plating
baths, continuous replenishment photographic processors,
coffee makers, municipal water and waste treatment plants,
cooling towers, refrigeration equipment and others.
Classically, these needs have been met by various mechanical arrangements such as float valves or diaphragm actuated switches. These devices are bulky, inaccurate and, because they contain moving parts, unreliable-often with disastrous results when they fail. They are easily disabled by
" debris or environmental problems such as ice. They can be
expensive when used to control the level of corrosive fluids
such as plating baths or detergents, or when used to control
large differences in depth such as in municipal water towers. Mechanical control devices are prone to false actuation
in vehicular applications (such as bilge pump controls) due
to their own inertia. In many applications such as coffee
makers, they are too bulky to fit within the confines of the
package. By utilizing electronic means based on the
LM1830, problems inherent in mechanical solutions are
overcome and a reliable, cost effective approach to fluid
level control is made possible.
The LM1830 is a monolithic bipolar integrated circuit de, signed to detect the presence or absence of aqueous fluids.
An AC signal generated on-Chip is passed through two
probes within the fluid. A detector determines the presence
, of the fluid by using the probes in a voltage dMder circuit
and measuring the signal level across the probes. An AC
signal is used to prevent plating or dissoMng of the probes
as occurs when a DC signal is used. A pin is available for
connecting an external resistance in cases where the ,fluid
impedance is not compatible with the internal 13 kO divider
resistance.
The addition of a CD4016 quad CMOS analog switch (Figure 1) allows the LM1830 to be used for HIGH/LOW limit
control applications. The switch sections are opened and
closed by a control signal, where a HIGH level turns the
switch ON and a LOW level turns the switch OFF. Grounding the input of one switch section and pulling its output up
, with a resistor creates en inverter. Probes are connected to
the inputs of two of the remaining analog switches. Their
,outputs are connected to pin 10 of the LM1830
which is the detector input The remaining seCtion cif the
CD4016 is used to buffer the open cOllector output of the
LM1830. All of the control inputs of the quad analog switch
are tied to this output. The last switch section controls the
base of a transistor which in turn driVes relay or solenoid
actuated valve.
'
The start and stop probes are set at their appropriate levels
in the fluid container, and the ground return is connected to
a third probe located at a depth greater than the start and
stop probes. If the container is conductive, it may be used
as the ground return. Let's assume we have ,a situation
where we wish to empty the container when fluid reaches a
predetermined level [sump or bilge pump, F/(Jure·1(a)J. With'
no fluid covering either of the probes, pin 12 of the LM1830
switches LOW. This disables the relay and enables the analog switch connected to the start probe. Fluid eventually fills
the container, covering the start probe. Whfin' this occurs,
the output of the LM1830 switches HIGH' and the pump
relay is enabled, thereby draining the container. At the sarile
time, the analog switch used as an inverter enables the anelog switch connected to the stop probe and disables the
start probe. Draining continues until the stop probe is ~e
the level of fluid in the container. Then thi;{output olthe
LM1830 switches LOW, disabling the relay'(halting the drain
operation) and switching the start probe back to its active
state.
By reversing the labeling on the probes, as well as reversing
the polarity, of the relay drive, a container "fill" control is
implemented SUch as would be used in a water tower. Necessary circuit changes are shown in Flgure1(b).
'
A pump control for a waste water holding tank in a photOgraphic darkroom has been implemented with this circuitry.
This replaced a float actuated system which, failed consistently due to the corrosive nature of the chemicals ,us8d in
photographic prOC9!lsing. With one year of continUOUs service, no failures have occurred in thii system. Flirthermore,
there is ,no evidence of plating on the sense electrodes, in
spite of the fact that the waste water is loaded with silver
ions. A plastic holding tank is used, with stainless stael bolts
inserted through holes driliSd in the' tank as sense probes
(F/(Jure 2). A solid-state relay controls Ii % HP pump motor
to empty the tank.
Obviously, careful selection of probe materiais must be
made to maximize, ,reliability with this, system. Excellent
sources of information on materials in corrosive environments, are available ,in publications such as Omega's, Tern-,
perature Measurement HarKJbook, or Eastman Kodak's
Darkroom Design Manual
1134
a
1...a1
;...
v+
o
liS
lnF
11~II"~
1_"
1"
1l1li
1.
12
LM1830
1
1.
RYl"
10 3.311
12
V·
11k . . .--1P-_
TLIH/5071-1
FIGURE 1(a). "Emptying" Processes are Controlled with this Circuit
II~
RY1.~
TLIH/5071-2
°RY1
= Magnecraft Part #W388COX-5
TLIH/5071-3
FIGURE 1(b). Filling Processes are Implemented with
this Output Circuit and Relabeled Probes
A sealing compound applied externally protects
hook..." wire and p......nts leaks.
FIGURE 2. Typical Probe Installation
1135
High-Efficiency R~gulatQ(,
has Lo~ Drop-Out Voltage
National Semiconductor
Application ,8rief11
Conventional regulators have a high drap-out voltage that is
a function of the total a1Jtput current. HoWever, wilh just a
regulator chip, an external ti'arl'SiStor :alid a fev.(' pasSive"
components, this design forms a high oUtput c,urrent regulator with a limited input voltage and high efficiency. The circuit presented has Ii drop-out of 0.7V at 5A load current and
1.3V at a current level of as high as 1OA.
The circuit output voltage equals that of PNP regulator Ul
and may be expressed as VOUT = VREF (Al + A2)/Al
where VREF equals Ul's reference voltage of 1.2V. To compensate for bias-current errors and to keep the extra qui~s
cent current that is induced by this resistor network to a few
p.A., resistor Al is set at 28 kG. Thus for a 5V regulated
output voltage, A2 is set at 88.7 kG. In addition, the oUtput
voltage can be adjusted between 3V and 24V by varying R2.
The circuit can handle a great deal of current because, of
external PNP transistor Ql. At high current levels, the ~ir
cuit's drop-out voltage is a function of the saturation voltage
of the PNP device. As a result, Ql must have low saturation
levels for VeE and VSE along with a high beta. In addition,
the maximum output current is equal to the maximum output
sink of regulator Ul multiplied 'by the maximum beta of Ql.
A germanium transistor, such as a 2N4277 for the external
pass element, satisfies the above requirements. For the
components shown, the qircuit gives excellent regulation at
VIN = 5.7V up to 5A in ,load current, giving a drop-out of
only 0.7V.
Ul is biased to a minimum of 30 rnA by a resistor A3, which
also functions as 'a bleeding resistor for Ql. The on-off pin
of Ul permits extra 'remote on-off control and current-limiting functions for the circuit. Pulling this pin to ground enables the circuit, whereas keeping it open disables the circuit and leaves the regulator in the standby mode. The ratio
A5:A6 limits theinaximum output current. When the load
cllQ'ent exceeds thi!! riI~murn, the output voltage begins to
fall,and,the voltage across A6 decreaSjlS. This low voltage
c,uts off transistor Q2; thereby disablirlg the circuit output.
As a result, transistor Ql and the load, are protected from
overdrive and damage.
EFFICIENCY
USing National Semiconductor's regulator LM2931QT, external transistors Ql and ,Q2, and a few passive components,'this circuit forms a high-current regulator having a low
drop-out. For the components shown in the figure, the regulato( nas:a:drop-out of 0.7V at 5A load current and 1.3V at a
level as high as lOA. The on-off pin of regulator Ul provides
remote control, while transistor Q2 limits the maximum output current.
I
I
R4
lOOk
.LC2
25 p1'
R3
22
T
)01
2N4277
"
IN
,
REMOTE
ONIOFF
R5
3k
.
,
Ul. LM2931CT
VOLTAGE
REGULATOR
ONI
OFF
GROUND
,
Your
OUT
5V
Rl
28k
ADJUST
I
K02
2N4401
R6
ak
Cl
;:~ 3DOpI'
~
R2
BB.7k
~
TLlH/5623-1
Reprinted from EIecttonics. January 27, 1983 by permisskln.
1136
Wi~eAdjustable
Range
PN·P Voltage Regulator
National S~r:niconductor
Application Brief 12
What happens when the need arises for a regulator voltage
that isn't matched by your stock of fixed voltage I/C regulators? For the standard NPN pass transistor regulators
(LM340 for example) the answer may be as simple as adding a resistor (Rl) in the ground pin (Fl{}ure 1). The new
output voltage (Vo) will then be:
12.5 mA. The zener voltage variation due to this current
change will only be a faw hundred mY. That is, the output
voltage will vary slightly, but not as much (as high as a few
volts) as with a resistor to ground. Thus, a much better regulated output voltage is maintained.
Vo = VREG + 10 X Rl
where: VREG is the original regulator output voltage,
(1)
10 is the regulator's quiescent current.
But if the need is also for a low drop across the regulator,
then a PNP pass regulator is required. Simply adding a reSistor in the ground pin doesn't work, since the regulator
internal current varies too much because of increased base
drive to compensate for lower PNP beta. However, if a zener is used instead of a resistor, the higher voltages can be
accommodated (Figure 2). The new output voltage (Vo) is:
Vo = VREG
where Vz is the zener voltage.
+ Vz
(2)
As VREG is constant, the output voltage regulation will depend largely on the zener voltage (Vz) and its dynamic impedance.
The zener voltage will vary slightly with the current flowing
through. Let's .take the popular LM2931Z PNP regulator
from National Semiconductor as an example of variation of
the quiescent current. When the regulator load changes
from 50 mA to 150 mA, the zener current will increase by
One advantage inherent to this circuit is the ability to
achieve higher output voltages than the normal regulator
rating. The maximum regulator output is limited by the
breakdown of its internal circuitry. However, carefully selecting the zener to keep the input and ground pin differential
voltage well below tlie breakdown, the input is allowed to
exceed its maximum rating. For example, a 5V 3-terminal
LM2931Z PNP regulator (maximum operating input voltage
= 26V) can become a 56V regulator with a 51V zener. And
the input voltage can be as low as 56.6V with a load current
of 150 mA or less. Most of the PNP regulator's features are
still maintained. The short circuit protection mayor may not
be there, depending on the output voltage and the safe operating area of the output pass PNP transistor.
CapaCitors Cl and C2 should have the same values as
those specified for normal operation. However, their maximum operating voltage ratings should exceed the input voltage. Capacitor C3 should be located as close as possible to
the ground pin to get good decoupling and ensure stable
operation. The value of C3 will depend on zener impedance
and noise characteristics. The capacitor types must also be
rated over the desired operating temperature range.
I-:-r.....- VuuT
(GIN)
o.s~
!
....--I
'lJN-....I
b~-VOUT
B
TUH/5723-2
TL/H/5723-1
FIGURE 2. PNP Regulator
FIGURE 1. NPN Regulator
1137
National Semiconductor
.
Application Brief 24
iBenCh Testing LM3900 and
LM359 Input Parameters
Two input parameters are extremely important in designing
circuits with Norton op amps. These are the input bias current, ISlAS, and the mirror gain constant, AI. The mirror gain
is especially important when a Norton amplifier is used as a
voltage follower.
A Simplified schematic of the LM3900 is shown in Figure 1.
The op amp is basically a common emitter amplifier (03),
with an emitter follower output stage. Added to the base of
03 is a current mirror (01 and 02). If a fixed current is
injected into the non-inverting input and the output is fed
back to the inverting input, the output will rise until the current in 02 matches that flowing in 01. The currents in the
input terminals will not be equal since some current (ISlAs)
flows into the base of 03. This is especially noticeable when
the mirror current is very small-for instance in the 1 to 10
p.A range. Input currents may also be unequal due to mismatch in the mirror transistors, 01 and 02. The degree of
matching is called mirror gain, A" and Is ideally equal to "1".
Your
INPUT+
0-+-_.......
Vee
TLlH/5529-2
FIGURE 2. A simplified 8chematlc of the LM359
The test circuit for measurement of ISlAS in the LM3900 is
shown in Figure 3. Two voltage measurements are made at
the output of the LM3900, one with 51 closed and one with
51 opened. The output voltage increase is equal to the voltage appearing across the 1 MO resistor, multiplied by the
closed loop gain (Av) of 5. It is the result of 03 bias current
flowing in the 1 MO resistor. For the circuit shown the output
voltage increase multiplied by 200 gives the bias current In
nanoamperes.
IBIAS (nA)
INPUT
= 200 A vour = ( Av :~ MO )
A vour
+0-+-.......,
'wuIROR
TlIH/5529-1
FIGURE 1. A 81mpllfled schematic of the LM3900
The LM359 (Figure 2) differs from the LM3900 in that "03"
Is a cascode stage, and "04" is a darlington follower. Also,
the internal biasing is variable; set current (lSET) is determined by an external resistor. Gain-bandwidth product, slew
rate, input noise, output drive current, input bias current and,
of course, supply current all vary with set current
Any modern text detailing the operation of an op amp will
tell you how to bench test its parameters. Norton amplifiers
are, however, frequentiy overlooked and their important input parameters are difficult to test in the usual manner. Two
measurements and a simple calculation can provide accurate characterization of ISlAS and A,.
TL/H/5529-3
FIGURE 3. IBIAS can be evaluated by
mea8urlng the change In output voltage
when S118 opened and closed.
LM3900 mirror gain is measured using the circuit of F/(/ure
4. "R" is selected to provide the desired mirror current. The
voltage across each "R" is measured, and their ratio is
equal to the mirror gain, A,. As previously mentioned, the
1138
mirror gain is affected by the presence of IBIAS. Where IBIAS
is a significant part of the mirror current, the formula (true for
the LM3900 and the LM359) for AI becomes
AI = (V2) - RIBIAS
VI
Many of the LM359's data sheet parameters, including
IBIAS, are measured with ISET=0.5 mAo Three times this
current flows in the collector of 03A, making its bias current
about 15 pA. The LM3900 has a corresponding 03 collector current of only 3 pA, and its IBIAS=30 nA. However, the
R(1%)
'UIRROR
270kO
27kO
200 p.A
20pA
current, adding an unpredictable error term to the DC biasing equations. This eircumst/lnce can be avoided by sizing
the mirror, current at least 'h ISET. ,
Figures 5 and 6 show how to measure and calculate IBIAS
and AI for the LM359. RSET is selected to provide the appropriate set current and CcOMP is added for stability. IBIAS
and AI are measured with the same set currents used in the
data sheet.
All of the test circuits assume Vcc=12V. Accuracy is"as
good as the resistors and meter used. Matching is important
for the two "R's" used in Figures'4'and 6. 1% tolerance is
recommended for each resistor (5% resistors can be sorted
for accuracy) in Figuie 3, and the 100 kO resistor in Figure
5. Most 3% digit DVM's have sufficient accuracy for the
voltage measurements; input impedance must be at 'least
10 MO to prevent circuit loading in the mirror gain tests.
Detailed information concerning the use of the LM3900 and
LM359 can be found in their data sheets and in AN-72.
51
AI=~
TL/H/5529-4
Vee
330
R(I%)
'UIRROR
270kO
27kO
2.7kO
20pA
200 pA
1004
Vl
FIGURE 4. This circuit allows the measurement
of the mirror gain, "AI"
10 I!. VOUT = ISlAS ("A)
1"
RsET
>-....-o~VOUT
+ R_
'-V2".)
+ R _
'-VI".)
330
V-
TL/H/5529-6
AI = V+
TLlH/5529-5
FIGURE 5. IBIAS Is measured with
a set current of 500 p.A
LM3900 doesn't have a 400 MHz gain-bandwidth product.
The mirror gain is measured with ISET=5 pA, making IBIAS
so small it has little affect on the measurement. In a practical application IBIAS may be a significant part of the mirror
1139
FIGURE 6. Mirror gain, AI , Is
measured with ISET = 5 p.A
2mA
i
'Dithering' Display Expands
Bar Graph's R.esolution
National Semiconductor
Application Brief 25
Robert A. Pease
Commercially available bar-graph chips such as National's
LM3.914 offer an inexpensive and generally attractive way of
discerning 10. levels of signal. If 20, 30, or more steps of
resolution are required. however, bar-graph displays must
be stacked, and wHh that, the circuit's power drain, cost and
complexity all rise. But the techniques used here for creating a scanning-type "dithering" or modulated display will expand the resolution to 20 levels wHh only one 3914 or, alternately, make it possible to implement fine-tunlilg control so
that performance approaching infinite resolution can be
achieved.
The light-emltting-diode display arrangement for simply distinguishing 20 levels is achieved with a rudimentary squarewave oscillator, as shown in F/{/Uf'6 1. Here, the LM324 0scillator, running at 1 kHz, drives a 60 mV peak-te-peak signal into pin 8 of the 3914.
Now, the internal reference circuitry of the 3914 acts to
force pin 7 to be 1.26V above pin 8, so that pins 4 and 8 are
at an instantaneous potential of 4.0 mV plus a 60 mV pop
square wave, while pins 6 and 7 will be at 1.264V plus a
60 mV pop square wave. Normally, the first LED at pin 1
would turn on when V,N exceeded 130 mV, but beqause of
the dither caused by the AC component.of the oscillator's
output, the first LED now turns on at half IntenSity when V,N
rises above the aforementioned value. Full intensity Is
achieved when V,N = 190 mV.
When V,N rises another 70 mV or so, the first LED will fall
off to half brightness and the second one will begin to glow.
When V,N reaches 320 mV, the first LED will go off and the
second will turn on fully, and so on. Thus 20 levels of brightness are easily obtained.
+5V--~----,---~~--~----~--~~---,----~----,---~~--~----~-,
1Jj3914
BAR - GRAPH DRIVER
10kA
7
-
V~+I~V
__
~
~
__
BAR
OOOT
SWITCH
-
~
FULL SCALE
RHI
60 mV p-p
lOOkA
22A
O.OI"F
100kA
9
IIODESELECTOR
1.2kA
+Vs
__________________________
8
-
I
-
2.5 rnA p-p
-
\.
1.2kA
D-3V AT I kHz
IOOkA
TlIH/8739-1
FIGURE 1. Half tones. Input"'gnal biasing on LM3914 bar-graph chip Ia ..t by the Instantaneous output
of a low-amplltude square-wave oscillator so that bar-graph resolution can be doubled. Each of 10 LEOs
now has a fully-on and a psrtlally-on mode, making 20 statu dlscsmlble.
1140
;
._--_.----1_--~~--~----._--_.----1_--~~--~----t_--+5V
N
U1
lM3914
BAR - GRAPH DRIVER
8
YIN +10Y
10k.1l
o DOT
MODE
SWITCH
1.2kD.
FUll SCAlE-----------W---T-~,-----.....
I
"ty~
FUll SCAlE
TRII
R3
5k.1l
L - _............. ____________
• ____ JO.1I'F
22O.1l
+15V _ ......__________~--........-aRC--Urr--A__,
QRCUrr B
~
I
I
I
I
l
-=
-.
10kD.
R'
B 10~
!~~
100kD.
._-
+
+
ilM324
100k.1l
1DOkD.
TLlH/8739-2
FIGURE 2. Spectrum. Great.r r.soIutlon,llmHed only by the ability of the user to discern relative brightness, Is
achl.ved by .mployfng a trlangula....wav. oscillator and more sensitive control circuitry to set the voltage levels
and thus light levels of corresponding LEOs. Two RC networks, circuits A and B, provide required oscillator
coupling and attenuation. B replaces A If oscillator cannot suffer heavy loading.
Similarly, greater resolution can be achieved by employing a
triangular-wave oscillator and two simple RC networks as
seen in F/{/urB 2. Here, by means of circuit A, this voltage is
capacitively coupled, attenuated, and superimposed on the
input voltage at pin 5 of the LM3914. With appropriate setting of the 50 kG potentiometer, each incremental change in
VIN can be detected because the glow from each LED can
be made to spread gradually from one device to the next.
Of course, if the signal-source impedance is not low or linear, the AC signals coupled into the input circuit can cause
false readings at the output. In this case, the Circuit in block
B should be used to buffer the output of the triangular-wave
oscillator.
The display is most effective in the dot mode, where supply
voltages can be brought up to 15V. If the circuit's bar mode
is used, the potentials applied to the LEOs should be made
no greater than 5V to avoid overheating.
To trim the circuit, set the LM3914's output to full scale with
R3. RA or Rs should then be trimmed so that when one LED
is lit, any small measured change of VIN will cause one of
the adjacent LEOs in the chain to tum on.
1141
e
r-----------------------------------------------------------------------~
= RS-232
Line Driver
Power Supply.
'.'1
National Semiconductor
Application Brief 30
INTRODUCTION
A large segment of today's systems comply with the Electronic Industries Association (EIA) RS-232 specification for
the interface between data processing and data communications equipment. B~use this specifICation calls for the
use of positive and negative signall9Vels, the designer quite
often needs to ~dd a dual supply to a board which can otherwise operate from a single 5V supply. The LM1578A
Switching Regulator can be used to convert the already existing supply into a separate ± 12V supply for powering the
interface line drivers.
The current limit resistor, R4, is selected by dMding the current limit threshold voltage (approximately 100 mV) by the
maximum peak current level in the output switch (750 mA
steady-state). For our purposes R4 = 100 mV1750 mA =
0.130. A value of ,0.10, used here, will trip the current limit ,
at 1A peak. A more conservative design would use 0.150
for this resistor..
Capacitor C1 sets the oscillator frequency according to the ,
equation C1 = 80lf, where C1 is in nano-Farads and f is the
frequency of the oscillator in kHz. This application runs at
80 kHz and used a 1 nF (1000 pF) silver-mica capacitor.
The oscillator section provides a 10% deadtime each cycle
to protect the output transistor.
Capacitor 02 serves as a compensation capacitor for operating the circuit in the synchronous Conduction mode. That
is, the output transistor will switch on each cycle, thereby
eliminating the random noise spikes which occur with nonsynchronous operation and are at best difficult to filter. This
capacitor is optional and may be omitted H desired. If used,
a value of 10 to 50 pF should be sufficient for most applications.
The choice for an output capacitOr val~e depends primarily
on the, allowed output ripple voltage, t. VOUT. In most cases,
the capacitor's equivalent series resistance (ESR) at the
switching frequency produces more ripple voltage than
does the chlll"\ling and discharging 'Of the capacitQr., The
capacitor Should. be chosen to have an EISR S: t.VOUT/100
mA, ~here 100 ~A., is approximately the great8stripple current produces by the transformer secondary. Higher-value
capacitors tend to have lower ESR; 1000 ,..F aluminum
electrolytic was used in this circuit to assure low ESR, under
0.40.
The input capacitors, C5 and ce, are used to reduce the
transients that may be fedback to the main supply. Capacitor C5 is a 100 ,...F electrolytic and' is bypaSsed by ce, a
0.1 ,...1" ceramic disc.
For gOOd efficiency, the diodeS mUst have a loW· forward
voltage drop and be fest switching. 1N5819 Schottky diodes
work well.
'
CIRCUIT DESCRIPTION
The power supply, shown in Figure 1, operates from an input voltage as low as 4.2V, and delivers an output of ± 12V
at ± 40 mA with an efficiency of better than 70%. The circuit
provides a load regulation of ±1.25% (from 10% to 100%
of full load) and a line regulation of ±0.08%. Other notable
features include a cycle-by-cycle current limit and 8f1 output
voltage ripple of less than 40 mVp-p.
A unique feature of this flyback regulator is Its use of feedback from BOTH outputs. This dual feedback configuration
results in a sharing of the output voltage regulation by each
output so that one output is not left unregulated as in single
feedback systems. In addition, since both sides are regulated, it is not necessary to use a linear regulator for output
regulation. .,
COMPO"ENT SELECTION
The following design prOCEidure is provided for the user who
wishes to tailor the power supply circuit to fit their own specific converter application.
The feedback resistors, R2 and R3, may be selected as
follows by assuming a value of 10 kO for R1;
R2 = (VOlJT -1V)/45.8!IA = 240 kn
R3 = (IVOUTI + 1V)154.2 p.A = 240 kO
Actually, the currents used, to program the values for the
feedback resistors may vary from 40' p.A to 6Op.A, as long as
their sum is equal to the 100 p.A necessary to establish the
1V threshold across R1 (10 kO). Ideally, these currents
should be equal (50 !IA each) for optimal control. However,
as was done here, they may be mismatched In order to use
standard resistor values. This results in a slight mismatch of
regulation between the two outputs.
Vs
R2
, INVERTING
INPUT
Vs
8
- -.......-o+VOUT
C3
2 NON-INVERTING
INPUT
LII'578A
OSCILLATOR
CURRENT 7
LlIlIT
C4
'L...-~....-o-VOUT
COLLECTOR
EIlITTER 5
GROUND
R4
-
-
-
R3
Dl
-
FIGURE 1. RS-232 Power Supply (See Table I, Parte Ust)
1142
TL/H/8756-1
Transformer selection should be picked for an output transistor "on" time of 0.4/f, and a primary inductance high
enough to prevent the output transistor switch from ramping
higher than the transistor's rating of 750 mAo Pulse Engineering (San Diego, Calif.) and Renco Electronics, Inc.
(Deer Park, N.Y.) can provide further aSSistance in selecting
the proper transformer for a specific application need. The
transformer used in the power supply was a Pulse Engineering PE-64287 with turns ratio of Np:Ns:Ns = 1:1.6:1.6 and
primary inductance of 50 p.H.
Table I is a parts listing for the components used in the
building of the power supply circuit.
1143
TABLE I
PartsUat
R1 = 10 kO
R2 = 240kO
R3 = 240 kO
R4 = 0.10
C1 = 1000 pF
C2 = 18pF
C3 = 220 p.F
C4 = 220 p.F
C5 = 100 p.F
C6 = 0.1 p.F
All diodes are 1N5819
T1 = Pulse Engineering PE-64287
~'
Naficmal Semiconductor '
Instrumentatlbo Amplifier
Linear'Brief 1
.:.[
""')'
•
; t.,
' , ,:',
~
.'-,
,
The differential input single-ended output J~~me~iation
amplifier is one of the most versatile signal proCessing amplifiers available. It is used for precision amplification of differential dc or ac signals while rejecting large values of common mode noise. By using integrated circuits.I!,high level of
performance is obtained at minimum cost.' '
Figure 1 shows a basic instrumentation aMP,lifi~ which provides a 10 volt output for 100 mW Input;' While rejecting
greater than ± 11V of common mOde: noise: To otltalri:good
input characteristics, two voltage follQ)V8rS,btlffer the'lnput
signal. The LM102 is specifically designed for voltage follower usage and has 10,000 M.o input impedance with 3 nA
input currents. This high of an input impedance provides two
benefits: it allows the instrumentation amplifier to be used
with high source resistances and still have low error; and It
allows the source resistances to be unbalanced by over
10,000.0 with no degradation in common mode rejection.
The followers drive a balanced differential amplifier, as
shown in Figure 1, which provides gain and rejects the common mode voltage. The gain is set by the ratio of R4 to R2
and Rs to R3. With the values shown, the gain for differential signals is 100.
Figure 2 shows an instrumentation amplifier where the gain
is linearfy adjustable from 1 to 300 with a single resistor. An
LM101A, connected as a fast inverter, is used as an attenuator in the feedback loop. By using an active attenuator, a
•
'.:
~ery 'l6¥lim~danCE!
is" ~tWaYs preserrted to: the feedback
~el5!~; arid'domrriQn mode rejeCtion is unaff~d by ,g~n
changes. The LM101A, used as shown, has a greater bandwidth than the LM107, and may be used in fEied~ck network withciut instability. The gain is Iinea'rfY dependent on FIe
and Is equal to 10-4 Re."
,
',
"
a
To obtain good common mode rajectlon ratios, It is necessary that the ratio of ~ to R2 match the ratio of R5 to R3'
For example, If the resistors in circuit shown in Figure 1 had
a total mismatch of 0.1 'lb, the common mode rejection
would be 60 dB times the closed loop gain, or 100 dB. The
circuit shown in Figure 2 would have constant common
mode rejection of 60 dB, independent of gain. In either circuit, it is possible to trim any one of the resistors to obtain
common mode rejection ratios in excess of 100 dB.
For optimum performance, several Items should be considered during construction. R1 is used for zeroing the output
It should be a high resolution, mechanically stable potentiometer to avoid a zero shift from occurring with mechanical
disturbances. Since there ere severallCs operating in close
proximity, the power supplies should be bypassed with
0.01 p.F disc capacitors to insure stability. The resistors
should be of the same type to have the same temperature
coefficient.
A few applications for a differential instrumentation amplifier
are: differential voltage measurements, bridge outputs,
strain gauge outputs, or low level voltage measurement.
R2
lK
0.1"
R4
lOOK
0.1"
v+
8AtAIICE
•
R3
11
0.1"
H6
lOOK
0.1"
TLlHI8501-1
FIGURE 1. Differential-Input Instrumentation Amplifier
1144
R3
R5
10K
0.1%
10K
0.1%
y+
BALANCE
R2
R4
10K
0.1%
10K
0.1%
'GAIN ADJUST
A., = 10-4 R6
TL/H/8501-2
FIGURE 2. Variable Gain, DHferentlal·lnput Instrumentation Amplifier
1145
National Semiconductor
Linear Brief 2
Feedforward
Compensation
Speeds Op Amp
Robert J. Widlar
Apartado Postal 541
Puerto Vallarta, Jalisco
Mexico
A feedforward compensation method increases the slew
rate of the LM1 01 A from 0.51 p.S to 1OVI p.s as an inverting
amplifier. This extends the usefulness of the device to frequencies an order of magnitude higher than the standard
compensation network. With this speed improvement, Ie op
amps may be used in applications that previously required
discretes. The compensation is relatively simple and does
not change the offset voltage or current of the amplifier.
In order to achieve unconditional closed loop stability for all
feedback connections, the gain of an operational amplifier is
rolled off at 6 dB per octave, with the accompanying 90
degrees of phase shift, until a gain of unity is reached. The
frequency compensationhetworks shape the open loop response to cross unity gain before the amplifier phase shift
exceeds 180 degrees. Unity gain for the LM101A is designed to occur at 1 MHz. The reason for this is the lateral
PNP transistors used for level shifting have poor high frequency response and exhibit excess phase shift about 1
MHz. Therefore, the stable closed loop bandwidth is limited
to approximately 1 MHz.
C2
3pF
RZ
3011
RI
3811
VIN
-~NIr-....~-t
>-....~-VOUT
6 X 10-8
C2"--R2
CI
ISGpF
"OptIonal to Improve Response
with Fast-Rising Input Steps.
TUH/7327-2
Figure 2. Feedforward frequency compensation
Figure 3 shows the open loop response in the high and low
speed configuration. Higher open loop gain is realized with
the fast compensation, as the gain rolls off at about 6 dB
per octave until a gain of unity is reached at about 10 MHz.
R2
3811
120 r----,--r-""T"-r-""T"-r--.
RI
3111
225
100
v.. --W~"--4
>-....I - - V
OUT
(
80
,.1
z
~
60
135
~'-'
40
10
20
45
~
CI
30pF
I
i
:!
0
TL/H/7327 -1
Figure 1. Standard frequency compensation
Usually, the LM101A is frequency compensated by a single
30 pF capacitor between Pins 1 and 8, as shown in Fl!Jure 1.
This gives a slew rate of 0.5V1p.s. The feedforward is
achieved by connecting a 150 pF capacitor between the
inverting input, Pin 2, and one of the compensation terminals, Pin " as shown in Figure 2. This eliminates the lateral
PNP's from the signal path at high frequencies. Unity gain
bandwidth is 10 MHz and the slew rate is 10Vlp.S. The diode can be added to improve slew with high speed input
pulses.
100
Ik
10k lOOk 1M 11M 101M
FREQUENCY (HzI
TLJHI7327-3
Figure 3. Open loop response for both frequency compensation networks
1146
Figures 4 arid 5 show the small signal and large signal transient response. There is a small amount of ringing; however,
the amplifier is stable over a - 55'C to + 125'C temperature
range. For comparison, large signal transient response with
30 pF frequency compensation is shown in Figure 6.
As with all high frequency, high-gain amplifiers, certain precautions should be taken to insure stable operation. The
power supplies should be bypassd near the amplifier with
.01 ,..F disc capaCitors. Stray capaCitance, such as large
lands on printed circuit boards, should be avoided at Pins 1,
2, 5, and 8. Load capacitance in excess of 75 pF should be
decoupled, as shown in Figure 7; however, 500 pF of load
capacitance can be tolerated without decoupling at the expense of bandwidth by the addition of 3 pF between Pins 1
and 8. A small capacitor C2 is needed as a lead across the
feedback resistor to insure that the rolloff is less than 12 dB
per octave at unity gain. The capacitive reactance of C2
should equal the feedback resistance between 2 and
3 MHz. For integrator applications, the lead capacitor is isolated from the feedback capacitor by a resistor, as shown in
Figure 8.
TLlH17327-4
Feedforward compensation offers a marked improvement
over standard compensation. In addition to having higher
bandwidth and slew, there is vanishingly small gain error
from DC to 3 kHz, and less than 1 % gain error up to
100 kHz as a unity gain inverter. The power bandwidth is
also extended from 6 kHz to 250 kHz. Some applications for
this type of amplifier are: fast summing amplifier, pulse amplifier, Of A and AID systems, and fast integrator.
Figure 4. Small signal transient response with feedforward compensation
C3
RZ
5K
C2
lD,F
TUHI7327-5
Figure 5. Large signal transient response with feedforward compensation
>---"-VOUT
Cl
158pf
TLlHI7327 -8
Figure 8. Fast integrator
TUH17327-6
Figure 6. Large signal transient response with standard
compensation
RZ
JOK
V'NJV""""-~
R3
loon
Cl
lSOpF
TUH/7327-7
Figure 7. Capacitive load isolation
1147
...
cp
N
National Semiconductor
Linear Brief 4
Fast Compensation
Extends·Power Bandwidth
In all IC operational amplifiers the power bandwidth depends on the frequency compensation. Normally, compensation for unity gain operation is accompanied by the lowest
power bandwidth. A technique is presented which extends
the power bandWidth of the LM101A for non-inverting gains
of unity to ten, and also reduces the gain error at moderate
.
frequencies.
>;....~~-VOUT
i
In order to achieve unconditional stability, an operational
amplifier is rolled off at 6 dB per octave, with an accompanying 90 degrees of phase shift, until a gain of unity is
reached. Unity gain in most monolithic operational amplifiers is limited to 1 MHz, because the lateral PNP's used for
level shifting have poor frequency response and exhibit excess phase shift at frequencies above 1 MHz. Hence, for
stable operation, the closed loop bandwidth must be less
than 1 MHz where the phase shift remains below 180 degrees.
For high closed loop gains, less severe frequency compensation is necessary to roll the open loop gain off at 6 dB per
octave until it crosses the closed loop gain. The frequency
where it crosses must, as previously mentioned, be less
than 1 MHz. For closed loop gains between 1 and 10, more
frequency compensation must be used to insure that the
open loop gain has been rolled off soon enough to cross the
closed loop gain before 1 MHz is reached.
The power bandwidth of ari operational amplifier depends
on the current available to charge the frequency compensation capacitors. For unity gain operation, where the compensation capacitor is largest, the power bandWidth of the
LM101A is 6 kHz. Figure 1 shows an LM101Awith unity gain
compensation and Figure 3 shows the open loop gain as a
function of frequency.
C2
3D pF
~JoPF
AI
'::' 11K
TlIH/8455-2
FIGURE 2. LM101A with Frequency Compensation to
Extend Power Bandwidth
age with the 10k resistor and 300 pF Qapacitor, there is less
AC voltage across the 30 pF capacItOr and less Current is
needed for charging. Since the voltage divlsiOl) is frequency
sensitive, the open loop gain rolls off at 12 dB per octave
until a gain of 20 is reached at 50 kHz. From 50 kHz to
1 MHz the 10k resistor is larger than the impedance of the
300 pF capacitor and the gain rolls off at 6 dB per octave.
The open loop gain plot is shown in Figure 3. To insure
sufficient drive to the 300 pF capaCitor, it is connected to
the output, Pin 6, rather than Pin 8. With this frequency cOmpensation method, the power bandwidth is typically
15-20 kHz as a follower, or unity gain inverter.
IZO ..........,....--,-......--,-.,---.-.,
>~"'-vOUT
10 100 lK 11K lOOK 1M IBM
FREQUENCY (HrI
3D pF
TlIH/8455-3
Tl/H/8455-1
FIGURE 1. LM101A with Standard Frequency
Compensation
FIGURE 3. Open Loop Response for Both Frequency
Compensation Networks
A two-pole frequency compensation network, as shown in
Figure 2, provides more than a factor of two improvement in
power bandWidth and reduced gain error at moderate frequencies. The network consists of a 30 pF capacitor, which
sets the unity gain frequency at 1 MHz, along with a 300 pF
capacitor and a 10k resistor. By dividing the AC output volt-
This frequency compensation, in addition to extending the
. power bandwidth, provides an order of magnitude lower
gain error at frequencies from DC to 5 kHz. Some applications where it would be helpful to use the compensation are:
differential amplifiers, audio amplifiers, OScillators, and active filters.
1148
High Q Notch Filter
National Semiconductor
Linear Brief 5
The twin "Tn network is one of the few RC filter networks
capable of providing an infinitely deep notch. By combining
the twin "r' with an LM102 voltage follower, the usual
drawbacks of the network are overcome. The Q is raised
from the usual 0.3 to something greater than 50. Further,
the voltage follower acts as a buffer, providing a low output
resistance; and the high input resistance of the LM102
makes it possible to use large resistance values in the "Tn
so that only small capacitors are required, even at low frequencies. The fast response of the follower allows the notch
to be used at high frequencies. Neither the depth of the
notch nor the frequency of the notch are changed when the
follower is added.
In applications where the rejected Signal might deviate
slightly from the null of the notch network, it is advantageous to lower the Q of the network. This insures some
rejection over a wider range of input frequencies. Figure 3
shows a circuit where the Q may be varied from 0.3 to 50. A
fraction of the output is fed back to R3 and C3 by a second
voltage follower, and the notch Q is dependent on the
amount of Signal fed back. A second follower is necessary
to drive the twin "Tn from a low-resistance source so that
the notch frequency and depth will not change with the potentiometer setting. Depending on the potentiometer setting, the circuit in Figure 3 will have a response that falls in
the shaded area of Figure 2.
Figure 1 shows a twin "Tn network connected to an LM102
to form a high Q, 60 Hz notch filter.
>;.e--+
YOUT
_ _......-VOUT
10 =
..
-
1
2rii1c1
= 60Hz
Rl= R2 = 2 RS
Cl=C2=~
2
TL/H/8458-3
FIGURE 3. Adjustable Q Notch Filter
Tl/H/8458-1
FIGURE 1. HIgh Q Notch Filter
The junction of Rs and Cs, which is normally connected to
ground, is bootstrapped to the output of the follower. Because the output of the follower is a very low Impedance,
neither the depth nor the frequency of the notch change;
however, the Q is raised in proportion to the amount of signal fed back to Rs and Cs. Figure 2 shows the response of a
normal twin "Tn and the response with the follower added.
An interesting change in the high Q twin "Tn occurs when
components are not exactly matched in ratio. For example,
an increase of 1 to 10 percent in the value of C3 will raise
the Q, while degrading the depth of the notch. If the value of
Cs is raised by 10 to 20 percent, the network provides voltage gain and acts as a tuned amplifier. A voltage gain of
400 was obtained during testing. Further increases in Cs
cause the circuit to OSCillate, giving a clipped sine wave output.
The circuit is easy to use and only a few items need be
considered for proper operation. To minimize notch frequency shift with temperature, silver mica, or polycarbonate, capacitors should be used with precision resistors. Notch
depth depends on component match, therefore, 0.1 percent
resistors and 1 percent capacitors are suggested to minimize the trimming needed for a 60 dB notch. To insure stability of the LM102, the power supplies should be bypassed
near the integrated circuit package with .01 j.l.F disc capacitors.
i
!
FRlDUEIICY IHII
Tl/H/8458-2
FIGURE 2. Response of HIgh and Low Q Notch Filter
1149
d:
NationaISemicor:u;luQ.tor.
Linear Brief 6
..
.
.... :Fast Voltage Compar"tors
:with,Low Input Curre'nt . ,
.,' t,
,,'
,\
t."
>;
Robert J. Widlar
Apartado Postal 541
Puerto Vallarta, Jalisco
Mexico
~
" ,
\
..
., t:
I,,'
,L ",
Monolithic voltage comparators are available tOday' v.thlch
are both fast and: accurate~ They 'can deteCt thEl heightqf a
pulse with a 5 mV accuracywittiin 40 ns.How~ver,these
devices have relatively Iligti inpilt cwreflts arid low input
impedances, which reduces th~ir' accuracy and speed wh~n
operating from high source re$istanees. This is probably a
basic' limitation since the inpi!11tansistors Of the inte~rated
circuit must be' operated at Ii relatively high current to get
fast operation. Further, the circuit must be gold do~d to
reduce storage .lime, and this limits the current gain that can
be obtained in the transistors. High gain transistors operating at low collector currents are necessary to get good input
.
characteristics.
One Way of overcoming this difficulty is to buffer the input of
the comparator. A voltage follower is'·avS/lable which· is
ideally sllited for thiii jbb. This device, the LM1 02.", is both
fast and has a low input current. It can reduce the effective
input current of the comparatOr by more than three orders of
niagnitude without' greatly reducing ilpeed. '
. ,
.A comparato~ circuit fo~anAlO Converter which' uses this
technique is,shown i~Figuri 1a. An tM10? voltage follo\l(er
buffi3rs the. output of ladder netWork a,nd Qriv~ o,(1e inP\At
of the comparatOr. the analog 'signal is fed to the other
il"lput of the comparator. It should come from 'a low imped'snca sOurce such as the oUtput of a signal processing am'
plifier, or another LM102 blIffer amplifier.
a
Clamp diodes, 01 and 02, are included to make the circuit :
faster. These diodes clamp the output of the ladder so that
it is never more than 0.7V different from the analog input.
This redl.!ces the'voltageexcursion that the buffer must hanI.
',_,'.,
•
'R J, Widl." "A Fast Integrated Voltage FQII~", NsfionSJSemiConductrxCorporationAN-B. May,l968.
AI
1M
RZ
AI
5K
5K
5K
IIIK
RI.·
R5
"R3
11K
11K
IIIK
•
.,
~-\".
I YO
FROM SWITCHES!
LOGIC
RI
IUK
TLlH/84S7-1
a. usl~ !lladder network
ANALOG
INPUT .'
Rf·
IUK
OJ
R4
R3
HZ
IUK
4IK
2tK
.
fOln
01
fom
I
FROM SWITCHES
TO
. . LO.GJC ,
TL/H/8457 -2
b. using a binary-weighted network
Figure 1. Comparator circuits for fast AID convertera
1:150
die on the most significant bit and keeps it from slewing. If
fast, low capacitance diodes are used, the signal to the
comparator will stabilize approximately 200 ns after the
most significant bit is switched in. This is about the same as
the stabilization time of the ladder network alone, as its
speed is limited by stray capacitances. The diodes also limit
the voltage swing across the inputs of the comparator, increasing its operating speed and insuring that the device is
not damaged by excessive differential input voltage.
The buffer reduces the loading on the ladder from 45 ",A to
20 nA, maximum, over a - 55°C to + 125°C temperature
range. Hence, in most applications the input current of the
buffer is totally inSignificant. This low current will often permit the use of larger reSistances in the ladder which simplifies design of the switches driving it.
capability to the comparator in that it makes it equivalent to
a 710 and a two-input NAND gate. If not needed, the strobe
pins can be left unconnected without affecting performance.
The voltage gain of the LM106 is about 45,000 which is 30
times higher than that of the 710. The increased gain reduces the error band in making a comparison. The LM106 will
also operate from the same supply voltage as the LM102,
and other operational amplifiers, for ± 12V supplies. However, it can also be operated from ± 15V supplies if a 3V zener
diode is connected in series with the positive supply lead.
It is necessary to observe a few precautions when working
with fast circuits operating from relatively high impedances.
A good ground is necessary, and a ground plane is advisable. All the individual points in the circuit which are to be
grounded, including bypass capacitors, should be returned
separately to the same point on the ground so that voltages
will not"be developed across common lead inductance. The
power supply leads of the integrated circuits should also be
bypassed with low inductance 0.01 ",F capacitors. These
capacitors, preferably disc ceramic, should be installed with
short leads and located close to the devices. Lastly, the
output of the comparator should be shielded from the circuitry on the input of the buffer, as stray coupling can also
cause oscillation.
It is possible to balance out the offset of the LM 102 with an
external 1 kfl potentiometer, Rg. The adjustment range of
this balance control is large enough so that it can be used to
null out the offset of both the buffer and the comparator. A
10 kfl resistor should be installed in series with the input to
the LM102, as shown. This is required to make the short
circuit protection of the device effective and to insure that it
will not oscillate. This resistor should be located close to the
integrated circuit.
Although the circuits shown so far were designed for use in
A similar technique can be used with AID converters employing a binary-weighted resistor network. This is shown in
Figure lb. The analog input is fed into a scaling resistor, R1.
This resistor is selected so that the input voltage to the
LM102 is zero when the output of the O/A network corresponds to the analog input voltage. Hence, if the 01 A output
is too low, the output of the LM1 06 will be a logical zero; and
the output will change to a logical one as the 01 A output
exceeds the analog signal.
The analog signal must be obtained from a source impedance which is low by comparison to Rl. This can be either
another LM102 buffer or the output of the signal-processing
amplifier. Clamp diodes, 01 and 02, restrict the Signal swing
and speed up the circuit. They also limit the input signal
seen by the LM106 to protect if from overloads. Operating
speed can be increased even further by using silicon backward diodes ( a degenerate tunnel diode) in place of the
diodes shown, as they will clamp the signal swing to about
50 mY. The offset voltage of both the LM102 and the
LM106 can be balanced out, if necessary, with Re.
The binary weighted network can be driven with single pole,
single-throw switches. This will result in a change in the
output resistance of the network when it switches, but circuit
performance will not be affected because the input current
of the LM102 is negligible. Hence, using the LM102 greatly
simplifies switch design.
AID converters, the same techniques apply to a number of
other applications. Figure 2 gives examples of circuits which
can put stringent input current requirements on the comparator. The first is a comparator for signals of opposite polarity. Resistors (R1 and R2l are required to isolate the two
signal sources. Frequently, these resistors must be relatively large so that the signal sources are not loaded. Hence,
the input current of the comparator must be reduced to prevent inaccuracies. Another example is the zero-crossing detector in Figure 2b. When the input Signal can exceed the
common mode range of the comparator (± 5V for the
LM106), clamp diodes must be used. It is then necessary to
isolate the comparator from the input with a relatively large
resistance to prevent loading. Again, bias currents should
be reduced. A third example, in Figure 2c, is a comparator
with an ac coupled input. An LM106 will draw an input current which is twice the specified bias current when the signal is above the comparison threshold. Yet, it draws no current when the Signal is below the threshold. This asymmetrical current drain will charge any coupling capacitor on the
input and produce an error. This problem can be eliminated
by using a buffer, as the input current will be both low and
constant.
The foregoing has shown how two integrated circuits can be
combined to provide state-of-the-art performance in both
speed and input current. Equivalent results will probably not
be achievable in a single circuit for some time, as the technologies required are not particularly compatible. Further,
considering the low cost of monolithic circuits, approaches
like this are certainly economical.
Although it is possible to use a 710 as the voltage comparator in these circuits, the LM 106 offers several advantages.
First, it can drive a fan out of 10 with standard, integrated
OTL or TTL. It also has two strobe terminals available which
disable the comparator and give a high output when either
of the terminals is held at a logical zero. This adds logic
1151
VI
VZIY~.--4...-t
TLlH/8457-3
a. comparator for signals of,oppoalte polarity
VOUT
TLlH/8457-4
b. zero crossing detector
TL/H/8457 -5
c. comparator for AC coupled signals
Figure 2. Applications requiring low Input current comparators
1152
Precision AC/DC
Converters
National Semiconductor
Linear Brief B
Although semiconductor diodes available today are close to
"Ideal" devices, they have severe limitations in low level
applications. Silicon diodes have a O.SV threshold which
must be overcome before appreciable conduction occurs.
By placing the diode in the feedback loop of an operational
amplifier, the threshold voltage is divided by the open loop
gain of the amplifier. With the threshold virtually eliminated,
it is possible to rectify millivolt Signals.
Figure 1 shows the simplest configuration for eliminating diode threshold potential. If the voltage at the non-inverting
input of the amplifier is positive, the output of the LM 101 A
A useful variation of this circuit is a precision clamp, as is
shown in Figure 2. In this circuit the output is precisely
clamped from going more positive than the reference voltage. When EIN is more positive than EREF, the LM101A
functions as a summing amplifier with the feedback loop
closed through 0,. Neglecting offsets, negative feedback
keeps the summing node, and therefore the output, within
100 p.V of the voltage at the non-inverting input. When EIN
is about 100 P.V more negative than EREF, the output
swings positive, reverse biasing 0,. Since 0, now prevents
negative feedback from contrOlling the voltage at the inverting input, no clamping action is obtained. On both of the
circuits in Figures 1 and 2 an output clamp diode is added at
pin 8 to help speed response. The clamp prevents the operational amplifier from saturating when 01 is reverse biased.
When 01 is reverse biased in either Circuit, a large differential voltage may appear between the inputs of the LM101A.
This is necessary for proper operation and does no damage
since the LM1 01 A is deSigned to withstand large input voltages. These circuits will not work with amplifiers protected
with back to back diodes across the inputs. Diode protection
conducts when the differential input voltage exceeds O.SV
and would connect the input and output together. Also, unprotected devices such as the LM709, are damaged by
large differential input signals.
The circuits in Figures 1 and 2 are relatively slow. Since
there is 100% feedback for positive input signals, it is necessary to use unity gain frequency compensation. Also,
when 01 is reverse biased, the feedback loop around the
amplifier is opened and the input stage saturates. Both of
these conditions cause errors to appear when the input frequency exceeds 1.5 kHz. A high performance precision half
wave rectifier is shown in Figure 3. This circuit will provide
rectification witl) 1 % accuracy at frequencies from dc to 100
kHz. Further, it is easy to extend the operation to full wave
rectification for precision AC/OC converters.
..--EOUT
r---------------~
TLlH/8459-1
FIGURE 1. Precision Diode
swings positive. When the amplifier output swings O.SV positive, 0, becomes forward biased; and negative feedback
through 0, forces the inverting input to follow the non-inverting input. Therefore, the circuit acts as a voltage follower for positive Signals. When the input swings negative, the
output swings negative and 0, is cut off. With 0, cut off no
current flows in the load except the 30 nA bias current of the
LM101A. The conduction threshold is very small since less
than 100 P.V change at the input will cause the output of the
LM101A to swing from negative to positive.
e2
3,F
R'N
E'N --~N\f--4I""--------------""~EouT
~----~N~------~---EoUT
0'
INI14
RI
28K
1%
·EREF must have a
source impedance of less
than 20011 H 02 is
used.
---
Eu.·----t....--.......--....
,.,4
02
R4
15K
FIGURE 3. Fast Half Wave Rectifier
1153
02
lNI14
TLlH/8459-3
TLlH/8459-2
FIGURE 2. PreCision Clamp
01
lN914
This precision rectifier functions somewhat differently from
the circuit in Figure 1. The input signal is applied through Rl
to the summing node of an inverting operational amplifier.
When the·signal is negative, 01 is forward biased and develops an output signal across R2. As with any inverting amplifier, the gain is R2/Rl. When the Signal goes positive, 01. is
non-conducting and there is no output. However, a negative
feedback path is provided by 02. The path through 02 reduces the negative output swing to -O.1V, and prevents
the amplifier from saturating.
Since' the LM101A is used as an inverting amplifier, feedforward compensation can be used. Feedforward compensation increases the slew rate to 10 VI p,s and reduces the
gain error at high frequencies. This compensation allows the
half wave rectifier to operate at higher frequencies than the
previous circuits with no loss ih accuracy.
The addition of a second amplifier converts the half wave
rectifier to a full wave rectifier. As is shown in Figure 4, the
half wave rectifier is connected to inverting amplifier A2. A2
sums the half wave rectified signal and the input signal to
provide a full wave output. For negative input signals the
output of AI is zero and no current flows through R3. Ne-
If R3 is Yz Rs, the output is :: EiN. Hence, the· output .is al~
ways the absolute value of the input.
Filtering, or averaging, to obtain a pure dc output is very
easy to do. A capacitor, C2, placed across R7 rolls off the
frequency response of A2 to give an output equal to the
average value of the input. The filter time constant .is R7C2,
and must be much greater than the maximum period of the
input signal. For the values given in Figure 4, the time constant is about 2.0 seconds. This converter has better tlian
1% conversion accuracy to above 100kHz and less than
1% ripple at 20 Hz. The output is calibrated to read the rms
value of a sine wave input.
As with any high frequency circuit some care must be taken
during construction. Leads should be kept short to avoid
stray capacitance and power supplies bypassed with
0.Q1 p,F disc ceramic capacitors. Capacitive loading of the
fast rectifier circuits must be less than 100 pF or decoupling
becomes necessary. The diodes should be reasonably fast
and film type resistors used. Also, the amplifiers must have
low bias currents.
REFERENCES
oR. C. Dobkin, "Feedforward Compensation Speeds Op
Amp," National Semiconductor Corporation, LB-2, March,
1969.
R7 EIN·
gleeting for the moment C2, the output of A2 ·IS - Rs
For positive input Signals, A2 sums the currents through R3
and Rs; and
EIN- EIN]
EOUT=R7 [ .
R3
Rs
RI
ZOK
1"
R3
10K
1"
_~~NIr-4"'.-~M_~~-~~--t--EoUT
"'Feedforward compensatIon
can be used to make a fast
full wave rectifier without
DZ
11.14
a filler.
C3·
30pF
FIGURE 4. Preclalon AC to DC Converter
1154
Tl/H/8459-4
r-----------------------------------------------------------------------~
Ie op amps are widely accepted as a univerSal analog component. Although the circuit designs may vary, most devices
are functionally interchangeable. However, offset voltage
balancing remains a personality trait of tha particular amplifier design. The techniques shown here allow offset voltage
balancing without regard to the internal circuitry of the amplifier.
This adjustment method is also useful when the feedback
element is a capacitor or non-linear device.
'v
R3
R4
INPUT~Mr4I""
~
R3
___-OUTPUT
RANGE
RS
58K
~ ±v(~)
""-OUTPUT
R1 ~ 2000 R3 ff R4
R411 R3 ~'10 k!l'
, RANGE
~
±v
(R3J1 R4 )
TUH/8460-1
FIGURE 1. Offset Voltage AdJust,,",l1t for Invertll1g
Amplifiers Using 10 kO Source Resistance or ......
The circuit shown 'in Fidure'1 is used to balance' out the
offset voltege of inverting amplif1'ers having a sOurCe resistance of 10 kO or less. A small current is injected into the
. summing node of the amplifier through R1. Since R1 is 2000
times as large as the source resistance the voltage at the
arm of the pot is attenuated by a factor of 2000 at the summing node. With the values given and ± 15V supplies the
. output may be zeroed for offset voltages up to ±7.5 mW.
If the value of the source resistance is much larger than 10
kO, the resistance needed for R1 becomes too large. In this
case it is much easier to balance out the offset by supplying
a small voltage at the non-inverting input of the amplifier.
F/{/UfB 2 shows such a scheme. Resistors R1 and R2 divide
the voltage at the arm of the pot to supply a ±7.5 mW
adjustment range with ± 15V supplies.
TUH/B460-2
FIGURE 2. Offset Voltage Adjustment for Inverting
AmplHlers Using Any Type of Feedback Element
This technique of supplying a small voltage effectively in
series with the input is also. used for adjusting non-inverting
amplifiers. As is shown in Figure 3, divider R1, R2 reduces
the voltage at the arm of the pot to ±7.5 mW for offset
adjustment. Since R2 apJ:j8ars in seri~ with R4, R2 should
be considered when calculating the gain. If R4 is greater
than 10 kO the error due to R2 is less than 1%.
RS
R3
58K
OUTPUT
INPUT
GAIN~l+~
R4+ R2
TUH/8460-3
FIGURE 3. Offset Voltage Adjustment for
Non-Inverting Amplifiers
1155
r
%
Universal Balancing
Techniques
National Semiconductor
Linear Brief 9
A voltage follower may be balanced by the technique shown
in F/{/ure 4. R1 injects a current which produces a voltage
drop across Rs to cancel the offset voltage. The addition of
the adjustment resistors causes a gain error, Increasing the
gain by 0.05%. This small error usually causes no problem.
The adjustment circuit essentially causes the offset voltage
to appear at full output, rather than at low output levels,
where it is a large percentage error.
tv
RZ
_ _.--OUTPUT
INPUTS
R3
IK
113
HZ
R5
"JlJ2G"K""",~ :K
lOOK
~
R4
11
__......OUTPUT
RANGE = tV
R2-R3+R4
RANGE = tV
(~)
GAIN
INPUT
Differential amplifiers are somewhat more difficult to balance. The offset adjustment used for a differential amplifier
can degrade the common mode rejection ratio. Figure 5
shows an adjustment circuit which has minimal effect on the
common mode rejection. The voltage at the arrnof the pot
is divided by R4 and R5 to supply an offset correction of
±7.5 mY. R4 and R5 are chosen such that the common
mode rejection ratio is limited by the amplifer for values of
Rs greater than 1 1<0. If Rs is less than 1k the shunting of R4
by R5 must be considered when chOosing the value of R3.
!!!
R1
(--1!L)
R1+R3
TLlH/8480-5
FIGURE 6. Offset Voltage Adjustment for
Differential Amplifiers
TL/H/8480-4
FIGURE 4. Offset Voltage Adjustment for
Voltage Followers
c
(~)
R4
The techniques described for balancing offset voltage at the
input of the amplifier offer two main advantages: First, they
are universally applicable to all operational amplifiers and
allow device interchangeability with no modifications to the
balance Circuitry. Second, they permit balancing without interfering With the internal circuitry of the amplifier. The electrical parameters of the amplifiers are tested and guaranteed wHhout balancing. Although it doesn't usually happen,
balancing could degrade performance.
.
1156
rp....
National Semiconductor
Linear Brief 11
The LM 11 0 An Improved
Ie Voltage Follower
....
"
'J
Robert J. Widlar
Apartado Postal 541
Puerto Vallarta, Jalisco
Mexico
!l
'I
"
There are quite a few applications where op amps are used
as voltage followers. These include sample and hold circuits
and active filters as well as general purpose buffers for
transducers or other high-impedance signal sources. The
general usefullness of such an amplifier is particularly enhanced if it is both fast and has a low input bias current.
High speed permits including the buffer in the Signal path or
within a feedback loop without significantly affecting response or stability. Low input current prevents loading of
high impedance sources, which is the reason for using a
buffer in the first place.
The LM102, introduced in 1967, was designed specifically
as a voltage follower. Therefore, it was possible to optimize
performance so that it worked better than general purpose
Ie amplifiers in this application. This was particularly true
with respect to obtaining low input currents along with highspeed operation.
One secret of the LM102's performance is that followers do
not require level shifting. Hence, lateral PNP's can be eliminated from the gain path. This has been the most significant
limitation on the frequency response of general purpose
amplifiers. Secondly, it was the first Ie to use super-gain
transistors. With these devices, high speed operation can
be realized along with low input currents.
The LM11 0 is a voltage follower that has been designed to
supersede the LM102. It is considerably more flexible in its
application and offers substantially improved performance.
In particular, the LM11 0 has lower offset-voltage drift, input
current and noise. Further, it is faster, less prone to oscillations and operates over a wider range of supply voltages.
The advantages of the LM110 over the LM102 are described by the following curves. Improvements not included
are increased output swing under load, larger small-signal
bandwidth, and elimination of oscillations with low-impedance sources. The performance of these devices is also
compared with general-purpose op amps in Tables I and II.
The advantages of optimizing an Ie for this particular slot
are clearly demonstrated. Lastly, some typical applications
for voltage followers with the performance capability of the
LM110 are given.
I
LM102
LM110
BALANCE
V'
y.
R2
5111
R4
IK
OO.....~+.,.:::..-OUTPUT
03
I.PUT-+----~--{
U""----t-----DUTPUT
HI
IDK
HI
~---IOOSTER
HI
I•
31
----~-------+-------------.;;....-y-
......
.....
~~----~----4---------~~
__
BOOITER
,~
TLlH/8462-2
TLlH/8462-1
Biggest design difference between the LM102 and LM110 Is the elmlnatlon of the zener diodes (01 and 02) In the
biasing circuit This reduces noise and permits operation at low supply voltages.
1157
.....
.....
~
I.
!
!II
..ii....
I!:
.~;:; r-~ ~~::
~~~I~I5J 1""11
IZ
... ·a
I.
f ... a21°t
II
im~RTlOII<1lI
'I
•
•
Z
•
I.
!MIIZ
!'IV
E
,.
..!l!.
110
..
III
r-
c
;
..5
;2fl'
~
iii
~
.....
I!;
I
II!
I.
.
~
is
LMIII
\
II
E
11M
I.
I.
'111
I
llllli
0
-5
-15
11M
I
FREQUENCY 'HzI
FREQUENCY 'H.I
Power bandwidth of Ihe LMll 0 Is five timeD larg- '
or than Ihe LM102,
V.-:t1IV
T... -IIOt
-10
"-
10
~~,J
lMlIi
"I
1
Z
:.
•
~!Mll
r\'
5 'I
7
TIME"",
Eliminating zeners reduces typical high frequency
noise by nearly a factor or 10, Worst case noise
is raduced' even more. High frequency noise of
LM102 has caused problems when il was Includad inside feedback loop with other IC op amps.
TLlH/B462-3
Large signal pulse response shoWs 40V/ "'S slew
,for LMll0 and 10V/p.a for ,LM102. Leading edge
overshoot on LMll 0 Is virtually eliminated. so exlernal clamp diode frequently required on the
LM102 is not'neaded.
Table I. Comparing performance of military grade IC op
amps In the voltage-follower connection
Table II. Comparison of commercial grade devIces
Offset·· Bias·· Slewt
Supply·
Bandwidtht
Current
Device Voltage Current Rate
(MHz)
(my)
(nA) (V/",s)
(mA)
Supply·
Offset' Bias· , Slewt
Bandwldtht
Device Voltage Current Rate
Current
(MHz)
(mY)
(nA) (VI",s)
(mA)
LM110
6.0
10
40
,5.5
20
LM310
7.5
7.0
40
20
5.5
LM102
7.5,
100
10
10
5.5
LM302
15
30 '
20
10
5.5
MC1556
6.0
30
2.5
1
1.5
MC1456
10
30
2.5
1
1.5
p.A715
7.5
4000
20
10
7.0
p.A715C
7.5
1500
20
10
10
LM108
3.0
3
0.3
1
0.6
LM308
7.5
7.0
0.3
1
0.8
LM108A
1.0
3
0.3
1
0.6
LM308A
0.5
7.0
0.3
1
0.8
LM101A
3.0
100
0.6
1
3.0
LM301A
7.5
250
0.6
1
3.0
",A741
6.0
1500
0.6
1
3.0
p.A741C
6.0
500
0.6
1
3.0
"Maximum for -55"C ;; TA ;; 125'C
'Maximum at 25"C
tTypical al 25"C
'Maximum at 25'C
tTypical al 25'C
High pass active filter
RI
IlDK
..
............
c,"
C2"
O.02",F
0.0' p.I
INPiJT~ ~'
I
L~
i
II
4~
,?'
OUTPUT'
R2'
:~ 1l0K
~
'"
TLlH/8462-4
'Values are' for' 100 'Hz cutoff. Use
metalized polycarbonate capacitors
for good lemperature stability
1158
,
HIgh Q Notch Filter
&
VIIUT
RI
11M
VIN
C3
540pF
I
10 ~ 2"RICI ~ 60 Hz
RI
~
R2
~
2R3
CI~C2~~
2
CI
C2
no,F
no,F
TlIH/8482-5
Low Drift Sample and Hold·
RI
V+
1M
OUTPUT
R2
2K
tTeflon polyethylene or pOlycarbonate
dielectric capacitor
'Worst caae drift laaa than 3 mV sec
CIt
~'''F
TLlH/8482-6
Bandpass Filter
H2
IK
>=-.-OUTPUT
INPUT
TL/H/8462-7
1159
National Semiconductor
Linear Brief 12
An IC Voltage Comparator
for High Impedance
Circuitry
Robert J. Widlar
Apartado Postal 541
Puerto Vallarta, Jalisco
Mexico
The IC voltage comparators available in the past have been
designed primarily for low voltage, high speed operation. As
a result, these devices have high input error currents, which
limit their usafulness in high impedance circuitry. An IC is
described here that drastically reduces these error currents,
with only a moderate decreasa in speed.
This new comparator is considerably more flexible than the
older devices. Not only will it drive RTL, DTL and TIL logic;
but also it can interface with MOS logic and FET analog
switches. It operates from standard ± 15V op amp supplies
and can switch 50V, 50 mA loads, making it useful as a
driver for relays, lamps or light-emitting diodes. A unique
output stage enables it to drive loads referred to either supply or ground and provide ground isolation between the
comparator inputs and the load.
Another useful feature of the circuit is that it can be powered
from a Single 5V supply and drive DTL or TIL integrated
circuits. This enables the designer to perform linear functions on a digital-circuit card without uSi"" extra supplies. It
can, for example, be used as a'low-leveJ"photodiode detector, a zero crossing detector for magnetic transducers, an
interface for high-level logic or a precision multivibrator.
Figul"8 1 shows a simplified schematic of this versatile comparator. PNP transistors buffer the differential input stage to
get low Input currents without sacrificing speed. Becausa
the emitter basa breakdown voltage of thesa PNPs is typically 70V, they can also withstand a large differential input
voltage. The PNPs drive a standard differential stage. The
output of this stage is further amplified by the 05-0S pair.
This feeds a laterai PNP, Og, that provides additional gain
and drives the output stage.
The output transistor is 011 which is driven by the level
shifting PNP. Current limiting is provided by Rs and 010 to
protect the circuit from intermittent shorts. Both the output
and the ground lead are isolated from other points within the
circuit, so either can be usad as the output. The V- terminal
can also be tied to ground to run the circuit from a single
supply. The comparator will work in any configuration as
long as the grol,lnd terminal is at a potential somewhere
between the supply voltages. The output terminal, however,
can go above the positive supply as long as the breakdown
voltage of 011 is not exceeded.
·1"
r--e~--~---4~-----e~--v'
i...
..
~
R•
RI
..
>
718
r-L1I111
LMIOIL
LMIII
I
10
/
l-
.
I!!
II.
vos • vos + R,los
R1
_55°C $T..
UK
:? 125°C
I
III
Ik
10k
1_
1M
11M
INPUT RESISTANCE ((!I
TL/H/8463-2
Figure 2. illustrating the Influence of source resistance
on worst caie, equivalent Input offset voltage
Figul"8 2 shows how the reduced error currents of the
GROUND
...""
I.,
~-e~--~~----e-----------v
TUH/8463-1
LM111 improve circuit performance. With the LM710 or
LM106, the offset voltage is degraded for source resistances above 2000. The LM111, however, works well with
source resistances in exCess of 30 kO. FiguI"82 applies for
equal source resistances on the two inputs. If they are unequal, the degradation will become pronounced at lower resistance levels.
Table I gives the important electrical characteristics of the
LM111 and compares them with the specifications of older
ICs.
I
A few, typical applications of the LM111 are illustrated in
Figul"83. The first is a zero crOSSing detector driving aMOS
FIgure 1. Simplified schematic of the LM111
1160
...rp
Table I. Comparing the LM111 with earlier IC comparators. Values given ara worst case over a - SsoC
to + 125"C temperature range, except as noted.
LM111
LM106
LM710
Units
Input Offset
Voltage
4
3
3
mV
Input Offset
Current
0.02
7
7
'p.A
InputSias
Current
0.15
45
45
,.,.A
Common Mode
Range
±14
±5
±5
V
Differential Input
Voltage Range
±30
±5
±5
V
Voltage Gaint
200
40
1.7
VlmV
Response Timet
200
40
40
ns
Output Drive
Voltage
Current
50
50
24
100
2.5
1.6
V
mA
FanOut
(DTL/TTL)
6
16
1
Power
Consumption
80
145
160
Parameter
N
tlll'UT
a. zero crossing detector driving analog switch
-.--.--V·. 5V
_ - - - - t....
HI
UK
H5
2K
H2
IK
mW
MAGNETIC
tTypical ~t 25"C.
PICKUP
analog switch. The ground terminal of the IC is connected to
V-; hence, with ±15V supplies, the signal swing delivered
to the gate of 01 is also ± 15V. This type of circuit is useful
where the gain or feedback configuration of an op amp circuit must be changed at some precisely-determined signal
level. Incidentally, it is a simple matter to modify the circuit
to work with junction FETs.
The second Circuit is a zero crossing detector for a'magnetic pickup such as a magnetometer or shaft·posltion pickoff.
It delivers the output signal directly to DTL or TTL logic circuits and operates from the 5V logiC supply. The resistive
divider, R1 and R2, biases the inputs 0.5V above ground,
within the common mode range of the device. An optional
offset balancing circuit, R3 and R4, is included.
The next circuit shows a comparator for a low-level photodiode operating with MOS logic. The output changes state
when the diode current reaches 1 p.A. At the switching
point, the voltage across the photodiode is nearly zero, so
its leakage current does not cause an error. The output
switches between ground and -10V, driving the data inputs
of MOS logic directly.
The last circuit shows how a ground-referrec:J load is driven
from the ground terminal of the LM111. The input polarity is
reversed because the ground terminal is used as the output.
An incandescent lamp, which is the load here, has a cold
resistance eight times lower than it is during normal operation. This produces a large inrush current, when it is
switched on, that can damage the switch. However, the cur·
rent limiting of the LM111 holds this current to a safe value.
The applications described above show that the output-cir.
cuit flexibility and wide supply-voltage range of the LM111
opens up new fields for Ie comparators. Further, its low
error currents permit its use in Circuits with impedance levels above 1 kO. Although slower than older devices, it is
more than an order of magnitude faster than op amps used
as comparators.
TL/H/8463-4
b. detector for magnetiC transducer
HI
UM
.....-4.........-t....-V-· -IOV
TL/H/8463-5
c., comparator for low level photodlode
_--.-V·
+
"Input polarity is reversed
when using pin 1
V-
as output
TL/H/8463-6
d. driving ground-referred load
Figure 3. Typical applications of the LM111
The LM111 has the same pin configuration as the LM710
and LM106. It is interchangeable with these devices in ap·
pllcations where speed is not of prime concern.
1161
-
•.,... r-------------------------------------------------------------------------,
National Semiconductor
Linear Brief 14
~ Speed Up the LM108
Feedforward
Compensation
Feedforward frequency compensation of 'operational amplifiers can provide a significant increase in slew rate and
bandwidth over standard lag compensation. When feedforward compensation is applied to the LM101A operational
amplifier,1 an order of magnitude increase In bandwidth results. A simple feedforward network has also been developed for use with the LM108 micropower amplifier to give a
factor of five improvement in speed. It uses no active components and does not degrade the excellent dc cl:1aracteristics of the LM108.
'
Figure 1 shows a schematic of an LM108 using the new
compensation. The signal from the inverting input is fed forward around the input stage by a 500 pF capacitor, C1. At
high frequencies it provides a phase lead. With this lead,
When the LM108 is used with feedforward compensation; it,
is less tolerant of capacitive loading and stray capacitance.,
Precautions must be taken to insure stability. If load capaci1~0
100
ii
:!!
80
......
...c
......
c
60
z
C
>
..... ......
...
180
FEED FORWARD _
I'... COMPENSAlI~
.....
.....
40
,I!--~
"
.
~
20
! - - I-- STANDARD
r--1CDMPENSA liON
:&:
!c.-
Ilw' ~rl
, ~j=
~
V-
..
'"
90 .,
... ,-
ii:
f
!
45
....:
C2
SpF
..'"......
135
...
-20
1
10
100
lk' 10k lOOk 1M
10M
FREOUENCY 1Hz!
TL/H/7328-2
FIGURE 2. Open Loop Voltage Gain
INPUT
tance is greater than about 75 to 100 pF, it must be isOlated
as shown in Figure 3. A small capaCitor is always needed to,
provide a lead across the feedback resistor to compensate
for strays at the input. About 3 to 5 pF is the minimum value
capaCitor. ,Care must, be' taken to minimize stray, capacitance at Pins 1,'2'and 8 when feedforward compensation is,
used. Additionally, when the source resistance on the noninverting input is greater than 10k, it should be bypassed with
a 0.1 p,F capaCitor.
-'\1\"".._-1
> .....--OUTPUT
RZ
Cl
500 pF
lOOk
TLlHI7328-1
FIGURE 1. LM108 with Feedforward Compensation
overall phase shift is reduced and less compensation is
needed to keep the amplifier stable. ,The C2-R1 network
provides lag compensation, insuring that the open loop gain
is below unity before 180"C phase shift occurs. The open
loop gain and phase as a function of frequency is compared
with standard compensation in F/{Jure 2.
The slew rate is,, increased from 0.3V/ p,s to about 1.3V/p,s
and the 1 kHz gain is increased from 500 to 10,000. Small
signal bandwidth is extended to 3 MHz. The bandwidth must
be limited to 3 MHz because the phase shift through the
lateral PNP transistors used In the second stage becomes
excessive at higher frequenties. With'the LM101A, 10 MHz
bandwidth was possible since the signal' was bypassed
around the low frequency lateral PNP's. Nonetheless, 3
MHz is very respectable for a micropowei'amplifier drawing
only 300 p,A quiescent current.
INPUT .....'\I\j"""'.~
R4
5DO
> ...~NWo4It- OUTPUT
CL
ID'.D'Dl~F
Cl
5DDpF
~ CZ,>5 x
' ',F
RZ
,
TLlH/7328-3
FIGURE 3. Decoupllng Load Capac!tance
As with any externally compensated amplifier, increasing'
the compensation of the LM1 08 increases the stability at
the expense of slew and l1andwidth. The ci~cuit shown, is for
the faste!!t response. Increasing the size ,of C2 to 20 pr
30 pF will provide 2 or 3 times greater stability and capacitive
1162
load .tolerance. Therefore, the size of the compensation capaCitor should be optimized for the bandwidth of the particular-application.
The stability of the LM 108 with feedforward compensation is
indicated by the small signal transient responses shown in
F/{/urB 4. It is quite stable since there is little overshoot and
ringing even though the amplifier is loaded with a 50 pF
capacitor. Large signal transient response for a 20V Square
wave is shown in F/{/UrB 5. The small positive overshoot is
not severe and usually causes no problems.
.... n. .... .... .... ....
V
......................V.!I!'!f!J!'!.
... .... .... .. .. \:. .. ~ 1.~Jf~(!'!!.
I
\
.... .... .... .... .... .." .... .. Rsf=50K ....
l00mv~ ~ ••
.... ~.....................H.~1' .. rr.
Ct.=5OpF
IA
I
~
...................
......
~l"
TLlHI7328-6
RSooSK
ir...
~,
TLlHI7328-4
FIGURE 4. Small SIgnal Tranalent Response of LM108
with F••dtorwarel Compensation
The LM108 is unusually insensitive to power supply bypassing with the new compensation. Even with several feet of
wire between the device and power supply, it does· not be·
come unstable. However, it is still wise to bypass the sup-
FIGURE 5. Larg. SIgnal Transient Response of LM108
with Feedforwarel Compen/l8tlon
plies for .drill since noise on the.v + line can be injected to
the summing junction by the 500 pF feedforward capaCitor.
The new feedforward compensation is easy to use and offers a factor of flV9 improvement over standard compensation. Slew rate is increased to 1.3VI,...s and power bandwidth extended to 20 kHz. Also, gain error at high frequencies is reduced. This makes the LM108 more useful in preci·
sion applications where low de error as well as low ac. error
is desired.
REFERENCE
1. Robert C. Dobkin, "Feedforward Compensation Speeds
Op Amp," Nationsl Semiconductor L8·2, March. 1969.
1163
....
."
!9
High Stability Regulators
National Semiconductor
Linear Brief 15
Monolithic IC's have greatly simplified the design of general
purpose power supplies. With an IC regulator and a few
external components 0.1 % regulation with 1% stability can
be obtained. However, if the application requires better performance, it is advisable to use some other design approach.
Precision regulators can be built using an IC op amp. as the
control amplifier and a discrete zener as a reference, where
the performance is determined by the reference. F/fJures 1
and 2 show schematics of simple positive and negative regulators. They are ·capable of providing better than 0.Q1 %
regulation for worst case changes oHine, load and temperature. Typically, the line rejection is 120 dB to 1 kHZ; and the
load regulation is better than 10 p.V for a 1Achange. Temperature is the worst source of error; however, it is possible
to achieve less than a 0.01 % change in the output voltage
over a - 55°C to + 125°C range.
The operation of both regulators is straightforward. An internal voltage reference is provided by a high-stability zener
diode. The LM1 08A1 operational amplifier compares a fraction of the output voltage with reference. In the positive regulator, the output of the op amp controls the gr~und terminal
of an LM 1092 regulator through source follower, 01. Frequency compensation for the regulator is provided by both
the R1 C2 combination and output capacitor, Ca.
The negative regulator shown in F/fJUfB 2 operates similarly,
except that discrete transistors are used for the pass element. A transistor, 01, level shifts the output of the LM108
to drive output transistors, Os and 04. Current limiting is
provided by 02. Capacitors Cs and C4 frequency compensate the regulator.
In the positive regulator the use of an LM 109 instead of
discrete power transistors has several advantages. First,
the LM109 contains all the biasing and current limit circuitry
needed to supply a 1A load. This simplifies the regulator.
Second, and probably most important, the LM109 has ther-
mal overload protection, making the regulator virtually bumout prOof. If the power dissipation becomes excessive or if
there iii inadequate· heat sinking, the LM109 will tum off
when the chip temperature reaches 175"C, preventing the
device from being destroyed. Since no such device is avallable for use in the negative regulator, the heat sink should
be large enough· to keep the junction temperature of the
pass transistors at an acceptable level for worst case conditions of maximum ambient temperature, maximum input
voltage and shorted output.
Although the regulators are relatively Simple, some precautions must be taken to eliminate possible problems. A solid
tantalum output. capaCitor must be. used., Unlike electrolytics, solid tantalum capacitors have low internal impedance
at high frequencies. Low impedance is needed both for frequency compensation and to eliminate possible minor loop
oscillations. The power transistor recommended for the
negative regulator is a single-diffused wide-base device.
This transistor type has fewer oscillation problems than double diffused transistors. Also, it seems less prone to failure
under overload· conditions.
Some unusual problems are encountered in the construction of a high stability regulator. Component choice is most
important since the resistors, amplifier and zener can contribute to temperature drift. Also, good circuit layout is needed to eliminate the effect of lead drops, pickup, and thermal
gradients.
The resistors must be low-temperature-coefficient wirewound or precision metal film. Ordinary 1% carbon film, tin
oxide or metal film units are not suitable since they may drift
as much as 0.5% over temperature. The resistor accuracy
need not be 0.005% as shown in the schematic; however,
they should track better than 1 ppm/oC. Additionally, wirewound resistors usually have lower thermoelectric effects
than film types. The resistor driving the zener is not quite
c.'
v"
1
_4~.:iUt
VOUT -11V .
louT ';'.
HZ
••
,III" 1M'
110
1.1"
RI
1<
...
R.
tOetennlnes zener CU1T8nt.
May be adjusted to
.- .R3
•IK
D•
minimize thermal drift.
;SoUd tantalum
TLIH/8485-1
FIGURE 1. High Stability Positive Regulator
1164
HZ
!.It(
tDetennlnas zenar current. May be
adjusted 10 minimize thermal drffl.
*Solld tantalum
HI
1.3
I..UT-+-....--4I~----+---'
TUH/8465-2
FIGURE 2. High Stability Negative Regulator
as critical; but it should change less than 0.2% over temperature.
The excellent dc characteristics of the LM108A make It a
good choice as the control amplifier. The offset voltage drift
of less than 5 p.VlOC contributes little error to the regulator
output Low input current allows standard cells to be used
for the voltage reference instead of a reference diode. Also
the LM108 is easily frequency compensated for regulator
applications.
Of course, the most important item is the reference. The
IN829 diode is representative of the better zeners available.
However, It still has a temperature coefficient of
0.0005%/OC or a maximum drift of 0.05% over a -55°C to
+ 125"C temperature range. The drift of the zener is usually
linear with temperature and may be varied by changing the
operating current from Its nominal value of 7.5 mAo The temperature coefficient changes by about 50 p'vrc for a 15%
change in operating current. Therefore, by adjusting the ze-
ner current, the temperature drift of the regulator may be
minimized.
Good construction techniques are important. It is necessary
to use remote sensing at the load, as is shown on the schematics. Even an inch of wire will degrade the load regulation. The voltage setting resistors, zener, and the amplifier
should also. be shielded. Board leakages or stray capacitance can easily introduce 100 P.V of ripple or dc error into
the regulator. Generally, short wire length and single-point
grounding are helpful in obtaining proper operation.
REFERENCES
1. R.J. Widlar, "IC Op Amp Beats FETs on Input Current,"
Nstionsl Semiconductor AN-29, December, 1969.
2. R.J. Widlar, "New Developments in IC Voltage Regulators," in 1970 Internstionsl SoIId-StstB Circuits Conference Digest of Technicsl Pspers, Vol. XIII, pp. 158-159.
1165
....G r-------------------------------------------------------------------------,
",National Semiconductor
~
Easily Tuned Sine Wave
Oscillators
Linear Brief 16
a
One approach to generating sine waves is to filter a square
If lower distortion oscillator is needed, the circuit in FiguffJ
wave. This leaves only the sine wave fundamental as··the
2 can 'be used. Instead of driving the tuned circuit with a
output. Since a square wave is easily amplitude stabilized by . squar~, wave, a symmetrically clipped sine wave is used.
clipping, the sine wave output is also amplitude stabilized. f\. The Clipped sine wave, Of course, has less distortion than a
Clipping oscillator eliminates the problems encountered ,with
square wave and yields Ii low distortion output when filtered.
agc stabilized oscillators such as those using Wein bridges. ' This 'circuit is' riot as tolerant of component values as the
Additionally, since there is no sloW agc loop, the oscillator
one shown in FiguffJ 1. To insure oscillation, it is necessary
starts quickly and reaches final amplitude within a.few cy- , that sufficient signal is applied to the zeners for clipping to
cles.
occur. Clipping about 20% of the sine wave is usually a
good value. The level of clipping must be high enough to
Al
330K
A2
10K
+16-~""-"-"
01
lV
C4
.OlpF
~.;.1
_ _..._ _ SQUARE'
~OUTPUT
tCl-c2
*Frequency Adlust
• Amplitude Adjust
F .... ' l' • ,
o 2trCl JR;R;'
AI
200K
-16
SINE
OUTPUT
R6 .. ,
Il3
- 111M
18Qpf
TL/HI8486-1
FIGURE 1. Easily Tuned Sine Wave OSCillator
The circuit in FiguffJ 1 will provide both a sine and square
wave output for frequencies from below 20 Hz to above 20
kHz. The frequency of oscillation is easily tuned by varying a
single resistor. This is a considereble advantage over Wein
bridge circuits where two elements must be tuned simultaneously to change frequency. Also, the output amplitude is
relatively stable when the frequency is changed.
An operational amplifier is used as a tuned circuit, driven by
square wave from a voltage comparator. Frequency Is controlled by R1, R2, C1, C2, and R3, with R3 used for tuning.
Tuning the filter does not affect its gain or bandwidth so the
output amplitude does not change with frequency. A comparator is fed with the sine wave output to obtain a square
wave. The square wave Is then fed back to the input of the
tuned circuit to cause oscillation. Zener diode, 01, stabilizes
the amplitude of the square wave fed back to the filter input.
Starting is insured by Rs and Cs which provide dc negative
feedback around the comparator. This keeps the compera, tor in the active region.
insure oscillation over the entire tuning range. If the clipping
is too small, it is possible for the circuit to cease oscillation
due to tuning, component aging, or temperature changes.
Higher clipping levels increase distortion. As with the circuit
in F1f/uffJ 1, this circuit is self-starting.
Table I shows the component values for the various frequency ranges. Distortion from the circuit in FiguffJ 1 ranges
between 0.75% and 2% depending on the setting of R3'
Although greater tuning range can be accomplished by increasing the size of R3 beyond 1 kO, distortion becomes
excessive. Decreasing R3 lower than SOO can make the
filter oscillate by itself. The circuit in F/gUffJ 2 varies between
0.2% and 0.4% distortion for 20% clipping.
About 20 kHz is the highest usable frequency for these 0scillators. At higher frequencies the tuned circuit is incapable
of providing the high Q bandpass characteristic needed to
filter the input into a clean sine wave. The low frequency
end of oscillation is not limited except by capacitor size.
1166
...
C5
5pF
A5
10K
HZ"
ZOOK
Al
330K
A6
10K
A4
50
01
lV
R3"
lK
OZ
lV
C4
150pF
>-4t--OUTPUT
t Cl = C2
.. Frequency Adjust
• Clipping Level Adiust
Fo~
- 2",C1
1
Ji!G"R7
AI
ZooK
C3
150pF
TUH/8466-2
FIGURE 2. Low Distortion Sine Wave Oscillator
capacitance, causing spikes on the output. Therefore the
output of the comparator with the associated circuitry
should be shielded from the inputs of the op amp.
Component choice is also important. Good quality resistors
and capacitors must be used to insure temperature stability.
CapaCitor should be mylar, polycarbonate, or polystyrene electrolytics will not work. One percent resistors are usually
adequate.
The cirCUits shown provide an easy method of generating a
sine wave. The frequency of oscillation can be varied over
greater than a 4 to 1 range by changing a Single resistor.
The ease of tuning as well as the elimination of critical agc
loops make these oscillators well suited for high volume
production since no component selection is necessary.
TABLE I
C1,C2
Min
Frequency
Max
Frequency
0.47,...F
0.1,...F
.022,...F
.0047,...F
.002,...F
18Hz
80Hz
380Hz
1.7 kHz
4.4 kHz
80Hz
380Hz
1.7 kHz
8kHz
20kHz
In both oscillators, feedforward compensationS is used on
the LM101A amplifiers to increase their bandwidth. Feedforward increases the bandwidth to over 10 MHz and the slew
rate to better than 10 V/,...s. With standard compensation
the maximum output frequency would be limited to about
6 kHz.
Although these oscillators are not particularly tricky, good
construction techniques are Important. Since the amplifiers
and the comparators are both wide band devices, proper
power supply bypassing is in order. Both the positive and
negative supplies should be bypassed with a 0.1 ,...F disc
ceramic capacitor. The fast transition at the output of the
comparator can be coupled to the sine wave output by stray
REFERENCES
1. N.P. Doyle, "Swift, Sure Design of Active Bandpass Filters," EDN, Vol. 15, No.2, January 15,1970.
2. R.J. Widlar, "PreciSion IC Comparator Runs from 5V Logic Supply," National Semiconductor AN-41, October,
1970.
3. Robert C. Dobkin, "Feedlorward Compensation Speeds
Op Amp," National Semiconductor LB-2, March, 1969.
1167
-
~
LM 118 Op Amp Slews
70 V/ILSeC
National Semiconductor
Linear Brief 17 ..
One of the greatest limitations of today's monolithic,. op
amps is speed. With unity gain frequency compensation,
general purpose op amps have·.1 MHz: bandwidth and
0.3 Vp.s slew rate. Optimized compensation as well as feedforward compensation can improve op amp speed for some
applications. Specialized devices such as fast, unity-gain
buffers are available which provide partial solutions. This
paper will describe a new high speed monolithic amplifier
that offers an order of magnitude increl\se in speed with no
loss in flexibility over general purpose devices.
The LM118 is constructed by the standard six mask monolithic process and features 15 MHz bandwidth and 70 V/ p.s
slew rate. It operates over a ± 5 to ± 18V supply range with
little change in speed. Additionally, the device has internal
unity-gain frequency compensation and needs no external
components for operation. However, unlike other internally
compensated amplifiers, external feedforward compensation may be added to approximately ~ouble the bandwidth
and slew rate.
rent source load for high gain, drives a class B output The
collectors of ,he input stage and the base of Og are available for offset balancing and external compensation.
Frequency compensation is accomplished with three internal capacitors. Cl rolls off on half the differential input stage
so. that the high frequency signal path is single-ended. Also,
at '''high frequenCies, the signal Is fed forward around the
la,teral PNP transistors by a 30 pF capacitor, C2. This eliminates the excessive phase shift. Overall frequency response is then set by capacitor, Ca, which rolls off the ampUfier at 6 dB/octave. As previously mentioned feedforward
compensation for inverting applications can be applied to
the base of Og. Flflure 2 shows the open loop frequency
response of an LM118. Table I gives typical specifications
for the new amplifier.
.,-,
.......
lIB
100
.......
..
iii
80
C
80
:!!
DESIGN CONCEPTS
In general purpose amplifiers the unity-gain bandwidth is
limited by the lateral PNP transistors used for level shifting.
The response above 2 MHz is so poor that they cannot be
used in a feedback amplifier. If the PNP transistors are used
for level shifting only at DC or low frequencies and the signal is fed forward around the PNP transistors at high frequencies, wide bandwidth can be obtained without the excessive phase shift of the PNP transistors.
!:i
C>
>
L'
-'"
,
I"-
ZD
-""
0
h3
CI_.1
lGo'FT
H4
18K
21IK
Hi
10
100
I
~a3
I
Z
3
-
QI
+
~Q2
"'04
.....
~ ik
3D,F
TUH/6831-2
FIGURE 2. Open Loop Voltage Gain as a
FUnction of Frequency for LM118
TABLE I. Typical Specifications .for the LM118
Input Offset Voltage
HZ
IK
~
I~
~
QI
200nA .
Offset Current
~.
20nA
Voltage Gain
AI
Sl
Common MOj:Ie Range
IC:FI
HI
IK
2mV
Input Bias Current
50
QI
10k 100II 1M 11M IDIM
FREIlUENCY (Hzl
HJ
CIS
Ik
J
.~
IK
II(
,
...
-20
"
HI
I"
40
Output Voltage Swing
Small Signai Bandwidth
.....01
"
Slew Rate
~-~ ~ .;"
200k
"
±11.5Y
±13V
15MHz
70V/p.s
OPERATING CONFIGURATIO.N .
4
TUH/6831-1
FIGURE 1. Simplified Circuit of the LM118
Figure 1 shows a simplified schematic of the LM118. Transistors 01 and 02 are a conventional differential input stage
with emitter degeneration and resistive collector loads. Os
and 04 form the second stage which further amplify the
Signal and level shift the signal towards V-. The collectors
of Os and 04 drive a current inverter, 010 and 011 to convert from differential to single ended. Og, which has a cur-
Although considerable effort was taken to lTI!1ke tl1e .I..M,118
trouble free, high frequency amplifiers, are .more I>rone to
oscillations than low frequency devices such 811 .the
LM101A. Care mllst betaken to minia:nize the stray capaci- .
tance at the inverting input and at the output; however the
LM118 will drive a 100 pF load. Good power supply bypassing is also in order-O.1 p.F disc ceramic capacitors should
be used within a few inches of the amplifier. Additionally, a
small capacitor is usually necessary across the feedback
resistor to compensate for unavoidable stray capacitance.
Figure 3 shows feedforward compensation of the LM118 for
fast inverting applications. The Signal is fed from the summing junction to the output stage driver by Cl and R4' Re-
1168
~istors ,R5;' R6 and R7 have two purposes: they increase the
i!lternal operating current of the output stage to increase
slew rate and they provide offset balancing. The current
wast is nec;:essary to drive internal stray capacitance at the
higher 'sleW rate. Mismatch of the external resistors can
cause large voltage offsets so offset balanCing is necessary. For supply voltages other than ± 15V, R5 and R6
should be selected to draw about 500 p.A from Pins 1 and 5.
R2
One of the more important considerations for a I)igh ,speed
amplifier is settling time. Poor settling time can cancel the
advantages of having high slew rate and bandwidth. For
example-an amplifier can have severe ringing after a step
input. A relatively long time is then needed before the output
voltage can be read accurately. Settling time is the time
necessary for the output to slew through a defined voltage
change and settle to within a defined error of its final output
voltage. Figure 4 shows optimized compensation for settling
5K
R2
SK
RI
SK
RI
5K
C3
100 pF
R6
R3
IK
21K
1%
tSlew and settling lime to 0.1 %
for a 10V slep change is BOO ns.
R7
R4
2.SK
200K
BALANCE
--v·
tSlew raletypically 120 VI".s
t-...
TUH/6B31-3
C2
0.01 ~F ,
FIGURE 3. Feedforward Compensation
for Greater Inverting Slew Ratet
TUH/6631-4
When using feedforward resistor R4 should be optimized for
the application. It is necessary to have about 8 kO in the
path from the output of the amplifier through the feedback
resistor and through feedforward network to Pin 8 of the
device. The series resistance is needed to limit the bandwidth and prevent minor loop oscillation.
, At high gains, or with high value feedback resistors R4 can
be quite low--but not less than 1000. When the LM118 is
used as a fast integrator, with a large feedback capacitor or
with low values of feedback resistance, R4 must be increased to 8 kO to insure stability over a full - 55'C to
+ 125'C temperature range.
FIGURE 4. Compensation for Minimum Settllngt Time
to within 0.1 % error. Typically the settling time is 800 ns for
a simple inverter circuit as shown. Settling time is, of course,
subject to operating conditions external to the IC such as
closed loop gain, circuit layout, stray capacitance and
source resistance. An optional offset balancing circuit, Ra
and R4 is included.
The LM118 opens up new fields for Ie operational amplifiers. It is more than an order of magnitude faster than general purpose amplifiers while retaining the ease of use features. It is ideally suited for analog to digital converters, active filters, sample and hold circuits and wide band amplification. Further, the LM118 has the same pin configuration
as the LM101A or LM741 and is interchangeable with these
devices when speed is of prime concern.
1169
-..,.
co
r----------------------------------------------------------------------------,
~ + 5to ~ 15 Volts DC
~~:~~~ri~~~~onductor
Converter
a~,,',
,
INTRODUCTION
It is frequently necesSary to convei1a DC voltage to another
higher or lower DC-voltage while maximizing efficiency.
Conventional switching regulators are capable of converting
from a high input DC voltage to a lower output voltage and
satisfying the efficiency criteria. The problem is a little more
troublesome if a higher output voltage than the input voltage
is desired. Particularly, generating DC voltage with opposite
polarity to the input voltage usually involves a complicated
design.
This brief demonstrates the use of the switching regulator
idea for a + 5 volts to -15 volts converter. The converter
has an application as a power supply for MOS memories in
a logic system where only + 5 volts is available. However,
the principle used can be amplied for almost any input output combination.
OPERATION
The method by which the regulator generates the opposite
polarity is explained in F/{/IJre 1. The transistor 0 is turned
ON and OFF with a given duty cycle. If the base drive is
sufficient the voltage across the inductor is equal to the
~1
v.
,~
J' . . .
II
RL
I~
Ie
"*
Assuming a large capacitor, we can also write the current
change, as:
'
~I =
VOUT - VD
L
X TOFF
vOU,
TUH/8467-1
During the transistor ON time, energy is loaded into the inductor. In the same time interval, the capacitor is drained
due to the load resistor RL.
Drop in capacitor voltage:
~V = ILOAD X TON
C
li~~ ~~
T
i
I
I
I
I
I
I
'--TON • I. .1 To..
(3)
During the TOFF time the stored energy in the inductor is
transferred to the load and capacitor. A rough estimate of
TOFF can be expressed as:
'
Ie = ~V X C = ILOAD X VOUT
(5)
TOFF
Vss
The total inductor current during the OFF time can be written as:
'
I _ ~I _ VSS X TON
lJAI_~_-!-~
I
I
(2)
In order to get a general idea of the operation for certain
input output conditions, we will develop a set of equations.
I,NDUCTOR = ILOAD':'- Ie
Inspecting Figure 1. We find:
IINDUCTOR
'LOAD
VOUT
= -LX TOFF
Vss
TOFF = -V' X TON
(4)
OUT
The capacitor voltage will be restored with a average current given by:
J
L
Turning OFF the transistor the inductor current has a path
through the catch diode and this in tum builds up a negative
voltage across RL.
The figure also shows the current and voltage levels versus
time. A capacitor in parallel to the resistor will prevent the
voltage from dropping to zero during the transistor ON time.
I
I
I
I
e-"2-
2xL
(6)
(7)
which yields:
•
I
T
- 2 X L X ILOAD X VOUT
ON VSS2
(8)
Taking into account that the efficiency is in the order of 75%
the final expression is:
T
TUH/8467-2
FIGURE 1. SWItching Circuit for Voltage Conversion
supply voltage minus VSAT. The current change in the inductor is given by:
~I -- Vss - L VSAT X TON-TON
- Vss T
- 1.5 X L X ILOAD X VOUT
ON VSS2
(9)
The above equations will be applied to the regulator shown
at FlfJure 2. The regulator must deliver -15 volts at 200 mA
from a + 5 volt supply. Using a 1 mH inductor the TON time
for 02 is 0.18 ms from equation 9. TOFF is 60 /Ls from equation 4 and the oscillator frequency to:
(1)
1170
1
F=
TON
+ TOFF
=
4kHz
r-
v.. ~vo-------------~~----------~----------~--~
R3
36K
R5
10K
/I - POUT
PIN
~
IP
.....
CD
75%
= 6 kHz 80% DUTY
VRIPPLE = 100 mV @200 rnA OUT
IL = 200 mA MAX
VOUl = -15V
F
r-""".,.---fo------..,
Cl
L
lmH
11,.,F
R4
10K
RI
20K
D2
RI
C2
IN36BO
12K
+
50hF
-------......------..------------...--------------..---0
R2
51K
VOUl
= (V2 + VeE (~ +
VOUT
1)
TL/H/8467-3
FIGURE 2. Switching Regulator for Voltage Conversion
The LM311 performs like a free running ·multivibrator with
high duty cycle. The Ie. is designed to operate from a standard single 5 volt 'supply and has a high output current capa·
bility for driving the switching transistor Q2. The duty cycle is
given by the voltage divider Rs and R4 and the frequency of
C, in conjunction with Rs.
By setting the duty cycle higher than first calculated. the
output voltage will tend to increase above the desired out·
put voltage of 15 volts. However; an" extra loop performed
by Q, and the zener diode in conjunction with the resistor
network will modify the oscillator duty cycle until the desired
output level is obtained: .
The output voltage is given by:
VOU~ =
(Vz
+ VeE)
Data and results obtained with the design:
VIN = 5 volts
" VOUT = -15 volts
lOUT = max 200 mA
Efficiency ... 75%
Frequency ... 6 kHz 80% duty cycle
VRIPPLE ... 100 mV @ 200 rnA load
Line regulation: VIN = 5V to 10V < 3% VOUT
ILOAD = 200 mA
Load regulation: VIN = 5V < 3% VOUT
ILOAD = 0 - 100 mA
(:~ + 1 )
1171
o
..-
r-----------------------------------------------------------------------~
National Semiconductor
Linear Brief 19
~ PredictingOp Amp Slew
Rate Limited Response
The following analysis of sine and step voltage responses
applies to all single dominant pole op amps such as the
LM101A, LM107, LM108A, LM112, LM118 and the LM741.
Each of these op amps has an open loop response curve
with a shape similar to the one shown in F'lfJure 1. The distinguishing feature of this curve is the single low frequency
tumover from a flat response to a uniform - 20 dB per decade of frequency (-6 dB/octave) drop in gain, at least until
the curve passes through the 0 dB line. ClOsing the loop to
40 dB (X100) as shown with a dotted line on Figure 1 does
not change the shape of the curve, but it does move the
tumover to a higher frequency. These open loop and closed
loop response curves determine the gain applied to small
signal inputs. The logical question then arises as to when a
signal can no longer be treated as a small signal and the
amplifier response begins to deviate from this curve.
(3)
Sr = 2'ITfmax Vp
where:
(4)
Vo = output voltage
Vp = peak output voltage
S
.
dvo
r = maxtmum Cit
The maximum sine wave frequency an amplifier with a given
slew rate will sustain without causing the output to take on a
triangular shape is therefore a function of the peak amplitude of the output and is expressed as:
S,
(5)
fmax=-2'ITVp
120
1110
iii
3
10
!!!
..:
60
'"
"'"-
"-~
III
:i!
48
'">
20
"
~
!:;
Equation 5 demonstrates that the borderline between small
Signal rasponse and slew rate limited response is not just a
function of the peak output signal but that by trading off
. either frequency .or peak amplitude one can continue to
have a distortion free output FlfJure 2 shows a quick reference graphical presentation of equation 5 with the area
above any VPEAK line representing anundistorted IImali signal response and the area below a given VPEAK line representing a distorted sine wave response due to slew rate
limiting.
~
r\
-20
10
100
1110
1k 10l IDOl 1M 10M
-;j.
FREQUENCY(Hzl
-'!,
dvo
Cit
=
= Vpsin2'ITft
(1)
2'ITfVpcos2'ITft
(2)
III
..:
II:
•...
III
'"
v~~~=1'6~
VPEAK =IV
V'EAK -4V
V'EAK·2V
VPEAK -IV
""I-
FIGURE 1. Open and Closed Loop Frequency Re.ponse
The answer lies in the slew rate limit of the op amp. The
slew rate limit is the maximum rate of change of the amplHier's output voltage and Is due to the fact that the compensation capacitor inside the amplifier only has finite currents1
available for charging and discharging. A sinusoidal output
Signal will cease being a small signal when its maximum rate
of change equals the slew rate limit Sr of the amplifier. The
maximum rate of change for a sine wave occurs at the zero
crossing and may be derived as follows:
Vo
10
~
TLlH/8726-1
1/
SMALL SIGNAL
RESPONSE AREA
1/
.~f7
I
~
/
//
0.1
SLEW RATE
LIMITING AREA
.01
100
,.
,..
I.
1M
SINE WAVE FREQUENCY (Hz)
TLlH/8726-2
FIGURE 2. Sine Wave Response
As a matter of convenience, amplifier manufacturers often
give a "full-power bandwidth" or "large signal response" on
their specification sheets.
1172
,-------------------------------------------------------------------,r
This frequency can be derived by inserting the amplifier
slew rate and peak rated output voltage into equation 5. The
bandwidth from DC to the resulting fmax is the full-power
bandwidth or "large signal response" of the amplifier. For
example the full-power bandwidth of the LM741 with a 0.5V
p.s Sr is approximately 6 kHz while the full-power bandwidth
of the LM118 with an Sr of 70 V/p.s is approximately 900
kHz.
The step voltage response at the output of an op amp can
also be divided into a small signal response and a slew rate
limited response. The signal turnover and uniform - 20 dBI
decade slope shown in the small signal frequency response
curve of Figure 1 are also characteristic of a low pass filter
and one can in fact model an op amp as a low pass RC filter
followed by a very wideband amplifier. Figure 3 shows a
model ofaX1 00 circuit with a 3 dB down rolloff frequency of
The output will then be a ramp function with a slope of ,Sr
and a rise time equal to:
t ' r -- VSTEP
(8)
Sr
Subsituting equation 6 into equation 7 gives the critical value of VSTEP directly in terms of f3dS:
VSTEP f3db ;;, S
0.35
r
which can be graphed as shown in Figure 4. Any point in the
area above a VSTEP line represents an undistorted low pass
filter type response and any point in the area below a given
VSTEP line represents a slew rate limited response.
100 ,.........................-!"TTT"T.rII"l7Tl"",rr;
LOW PASS FILTER
RESPONSE AREA
...
.....'"
,.[ ·+r~}"
~
10
l.llJ
2:
C
'"
1"'=2.~C
0.35
(6)
tr=
f3dS
which for this example would be 35 p.s. Again this small
signal or low pass filter response ceases when the required
rate of change of the output voltage exceeds the slew rate
limit Sr of the amplifier. Mathematically stated:
VSTEP :<: Sr
(7)
tr
This means that as soon as the amplitude of the output step
voltage divided by the rise time of the circuit exceeds the Sr
of the amplifier, the amplifier will go into slew rate limiting.
SLEW RATE
LIMITING AREA
l':
lk
TL/H/8728-3
VSTE•• IV
VSTE. = 4V
VSTE. z 2V
VSTEP =IV
0.1
.01
I... ' 10kHz
VSTE.= 32V
VSTE• =16V
I,(
a:
•......
FIGURE 3. Small Signal Op Amp Model
10 kHz. From basic filter theory2 the 10% to 90% rise time
of single pole low pass filter is:
(9)
10k
lOOk
1M
10M
100M
3 dB DOWN FREQUENCY. f ... (Hz)
TLlH/8728-4
FIGURE 4. Step Voltage Response
The above equations and graphs should allow one to avoid
the pitfalls of slew rate limiting and also provide a means of
using engineering tradeoffs to extend the response of the
single dominant pole type of amplifier.
REFERENCES
1. Solomon, J. E.; Davis, W. R.; and Lee, P. L.: ':.4 Self-Compensated Monolithic Operational Amplifier With Low Input
Current and High Slew Rate'; pp. 14-15, ISSCC Digest
Tech. Papers, February 1969.
2. Millman, J. and Hawkias, C. C.: "Electronic Devices and
Circuits'; pp. 465-466, McGraw-Hili Book Company,
New York, 1967.
1173
"P
.....
CD
o
~
~
r-----------------------------------------------------------------------~
National Semiconductor
Unear Brief 20
A Fully Differential Input
Voltage Amplifier
INTRODUCTION
The instrumentation amplifier is Useful for amplifying small
differential signals which may lie riding on high common
IT)Qde.voltagelevels. These amplifiers are particularly useful
in amplifying signals in the milli-volt range which are supplied from a high impedance source (> 2 kG).
This brief will demonstrate how a low cost, high performance instrumentation amplifier can be buIlt using the newly
introduced LM3900 q!lad amplifier. It is also Indicated how a
compect transducer bridge amplifier system can be developed to take advantage of the versatility of the LM3900.
This current change will show up in the collectors of 01 and
02 ,with opposite polarity. The input mirror Qf the LM3900
returns AlaI to the Inverting input terminal where it is added
(with sign) to AIQ2 yielding a tot41 current change of 2AI.
This current flows tJvough the feedbackJesistor, R3, which
causes an output voltage change, AVo, which is given by:
,
AVIN
AVo = 2AI X R3 = 2 x ~ X R3
(2)
BASIC AMPLIFIER OPERATION
Figure 1 shows the basic operation of. the amplifier. The bias
of the LM3900 is set by the' resistors, R2 and Rs (neglecting
for now, the transistors 01 and 02). Current which enters
the non-inverting input of the LM3900 will be "mirrored"
about V- and then
be drawn into the inverting input
terminal. This, causes the current to flow through the feedback reSistOr, R3; which establishes the output voltage level. If R2 = R3 and further, if R2 is connected to ground (OV),
then the output voltage biasing level will also be exactly
zero volts. It should be noticed that an OUTPUT OFFSET
CONTROL can be implemented by supplying a reference
voltage, ER, between R2 alld ground;
At this point It is conv&nient to evaluate the result obtained.
The gain can be established by one resistor (Rl) according
to equation (3). Conventional instrumentation amplifiers
usually have a gain given by:
will
Ay
ZR3
0-
RI
R3
1M
V.
....._--OV-·-IIV
TL/H/B468-1
FIGURE 1. Balle Instrumentation Amplifier
Adding transistors 01 and 02, as shown in FtgUf8 1 will not
disturb this biasing if the two collector currents of the transistors are well matched for a OV differential input signal.
The current sources which bias 01 and 02, are chosen to
be 100 p.A each to guarantee high /3 and low offset voltage
in 01 and 02'
The gain of the amplifier Is calculated as follows:
Any differential input voltage, AVIN, appears across AI' and
produces a current change AI, which is given by:
AI = AVIN
Rl
(1)
to yield a gain;
(3)
Ay=1
+~
.
(4)
A
This means that the minimum gain of unity is obtained if R is
left out (A = co). Note that this is different from the result
indicated in equation (3) where unity gain is obtained for
Rl = 2R3
(5)
and minimum gain (or maximum attenuation) is obtained if
AI is left out (Rl = co). This suggests that the amplifier can
be turned OFF without disturbing the output voltage dc bias.
The two current sources, for 01 and 02 are implemented
with a dual transistor (03 and 04l in conjunction with an
additional amplifier of the ,LM3900 as shown in FigUT8 2.
The operation can be easily understood if R4 and R5 are
incorporated within ttl!! amplifier, which then takes the form
of a conventional opamp closed loop regulator which maintains a reference voltage (the drop across RS> at the emitter
of 04.
PERFORMANCE
The performance of t!le COmplete instrumentation amplifier
of FIf1UT8 2 is outlined below (Table I and FiguT8 3).
TABLE I. TypIcal Performance Characteristics
GAIN
Range 01 gain
-34 dB (R1= co) to 72 dB (Rl =0)
Av = 2R3
Gain is set according to:
R1
INPUT
Voltage offset referred to
Pas supply less 2.4V
input is adjustable to zero.
Neg supply less 300 mV
Common-mode and
differential input voltage
Common-mode rejection
115dB (gain of 1000)
ralioat10 Hz
Bias current (either input)
200nA
OUTPUT
Output offset is
12 mVrms (open loop)
adjustable to zero.
Output noise
3 mVnns (AcL = 66 dB)
FREQUENCY RESPONSE
Small signal frequency
response (-3 dB)
1174
1 MHz (gain of 1000)
3 MHz (gain of 1)
r---------_1~----------_1~
y+ - +16V
A6
9'0
I=~
-,
A1
11K
Rl1
L-~~
l
______________________
~~-----oy---'~
TLlH/8488-2
FIGURE 2. Bridge Amplifier
Since quantitative discussion of the sources of offset voltage is beyond the scope of this brief, only the procedure for
nulling the amplifier will be included.
Letting R1 go to 'zero causes the amplifier to operate in the
open-loop mode. The main offset voltage source is now the
VBE mismatch of Q1 and Q2. The output can be nulled by
the OUTPUT OFFSET CONTROL (the reference voltage for
R2) or by adjusting the value of R2. With R1 = 00, the main
offset voltage source is the mismatch in the collector currents of Qa and Q4' This is easily adjusted via R12. These
first and second adjustments interact, however, after repeating the procedure a couple of times a good result is
obtained.
rived from this basic connection which require amplifying
the low level differential Signals which are obtained from
sensors such as strain gages, pressure transducers, and
thermocouples. The performance of this instrumentation
amplifier is adequate for many system applications. (See
National Semiconductor Application Note 72, "The
LM3900 - A New Current-Differencing Quad of ± Input
Amplifiers" for further information.)
TRANSDUCER BIAS SOURCE
Having in mind that the LM3900 consists of four independent amplifiers makes it relatively easy to bias a transducer
bridge with a constant current source using only one more
of the amplifiers and one resistor. The technique is self-explanatory and is also shown in Figure 2.
CONCLUSION
A brief review of a new concept for an instrumentation amplifier has been presented. Many applications can be de-
1175
.21
.01
!
10 f--
..
18
c
co
!:;
40
~
II
~
R""
I'
R"ZMIl
-20
•
.0
.01
'K 11K .11•• M .OM
FREQUENCY (III)
TLlH/846B-3
FIGURE 3. Frequency Response
~
~
,--------------------------------------------------------------------------------,
National Semiconductor
.Unear Brief 21
!:!I Instrumentatlonal
Amplifiers
INTRODUCTION
One of the most useful analog subsystems is the true instru- ..
. mentation amplifier. It can faithfully amplify low level signals
in the presence of high common mode noise. This aspect of
its performance makes it especially useful as the input amplifier of a signal processing system. Other features of the .
instrumentation amplifier are high input impedance, low input current, and good linearity.
.
It has never been easy to design a high performance instrumentation amplifier; however, the availability of high performance IC's considerably simplifies the problem. IC op
amps are available today that can give very low drifts as well
as low bias currents; however, most of the circuits have
some drawbacks.
'
The most commonly used instrumentation amplifier designs
utilize either 2 or 3 op amps and several precision re.~i$tors.
These are capable of excellent performance; hoWever, for
high performance they require very precjsely matched resistors. The cor!"U)'Ion mqde rejection of these, designs depends
on resistor matching and overall gain.· Since op amp!lll!re
now available with exceedingly high CMRR, this is nq longer
a problem. The CMRR. of the instrQmentation ampl!lier is
approximately equal to balf.resistor mismatch, plus the gain.·
For a 1% resistor mi,smatch the CMRR is limited to 46 dB
plus the gain-referred to the input.
R4
1211
1%
Referred to the output, the common mode error is independent 'of gain and fixed by the resistor mismatch. For 1%
match the Elrror is 0.5%, and for 0.1 % match the error is
0.05%. These errors are not trivial in high precision systems,.
An instrumentation amplifier is shown here that compares
favorably with multiple op amp designs, yet does not require
precisely matched resistors. Further, the design allows a
single resistor to adjust the gain. In comparing this instrumentation amp to multiple op amp types there are of course
some drawbacks. The gain linearity and accuracy are not as
good as the multiple op anip circuits.
The errors appearing in multiple op amp circuits are independent of the output signal level. For example, a common
mode error at the output of 0.5% of full scale is a 33% error
if the desired output Signal is only 1.5% of full scale. With
the new circuit maximum errors at full scale output and the
percentage of output error decreases at lower output levels.
FigUfB 1 shows a general purpose instrumentation amplifier
optimized for wide bandwidth. It can provide gains from under 1 to over 1000 with a single resistor adjustment. Gain
linearity is worst for unity-gain at 0.4%, and gain stability is
better than 1.5% from -55°C to + 125°C. Typically over a
COC to + 7COC range gain stability is 0.2%. Common mode
rejection ratio is about 100 dB-lndependent of gain.
HI
1211
1%
HI
lillie
1%
..
>+-0 OUTPUT
-INPUT
• ,NPUT
0-++-1
0----+----+---'
Note: Since \he LMl14 Is an obsolete part. aubstIIuIIon of
\he LMl94 I. recommended. along with the removal
of \he two LMl94 diodes. This circuit hss not been
tasted with the LMl94 included.
Also. the LM185-1.2 could be subsIIIuted lor the
LMl13.
LM113
'---~~--.-O -16V
FIGURE 1.lnstromentatlon Amplifier
1176
TLlH/8727-1
Transistor pair, 01 and 02, are operated open-loop as the
input stage to give a floating, fully differential input. Current
sources, 03 and 04, set the operating current of the input
pair. To obtain good linearity the output current of 03 and
04 are set at about twice the current in R8 at full differential
voltage. The temperature sensitivity of the transconductance of 01 and 02 is compensated by making their operating current directly proportional to absolute temperature. It
has been shown that by biasing the base of transistor current sources at 1.22V, the output current varies as absolute
temperature. The LM113 diode provides a constant 1.22V
to the current sources. Both the compensated gm of 01 and
02 and the large degeneration from R8 give the amplifier
stable gain over a wide temperature range.
In operation, transistors 01 and 02 convert a differential
input voltage to a differential output current at their collectors. This is fed into a standard differential amplifier to obtain a single ended output voltage. Since the diff amp does
not see the common mode input voltage, 1% resistors are
adequate. Gain is set by the ratio of R8 (plus the re of 01
and 02) to the sum of RS and R7.
As mentioned previously this circuit is optimized for wide
bandwidth: however, it is easily modified for other applications. If low bias current is needed, all resistors can be increased by a factor of 100 and an LM 108 substituted for the
LM318. Other possible improvements are cascaded current
sources and a modified Darlington input stage.
1177
~
.....
National,Semiconductor'
Linear Brief 22 ' .
Low Drift Amplifiers' "
INTRODUCTION' ,
Since the introduction of the monolithic
amplifier, there
has been a continued improvement In' DC accuraCy. Bias
currents have been decreased 'by five order's of magnitude
over the past five years. Low offset Voltage drift is also necessary in high-accuracy clreuits. This is evidenced by the
popularity of low-drift amplifier types as well as requests for
selected low-drift op amps. However, little has been written
about the problems associated with handling microvolt signals with a minimum of errors.
A very low drift amplifier poses some uncommon application
and testing problems. Many sources of error can cause the
apparent circuit drift to be much higher than would be predicted. In many cases, the low drift of the op amp is completely swamped by external effects. while the amplifier is
blamed for the high drift.
Thermocouple effects caused by temperature gradient
across dissimilar metals are perhaps the worst offenders.
Whenever dissimilar metals are joined, a thermocouple results. The voltage generated by the thermocouple is proportional to the temperature difference between the junction
and the measurement end of the metal. This voltage can
range between essentially zero and hundreds of microvolts
per degree, depending on the metals used. In any system
. using integrated circuits, a minimum of three metals are
found: copper, solder, and kovar (lead material of the IC).
Nominally, most parts of the circuit are at the same temperature. However, a small temperature gradient can exist
across even a few inches-and this is a big problem with
the low level signals. Only a few degrees gradient can
cause hundreds of microvolts of error. Two places where
this shows up, generally, are the package-to-printed-circuitboard interface and temperature gradients across resistors.
Keeping package leads short and the two input leads close
together help greatly.
For example, a very low drift amplifier was constructed and
the output monitored over a 1-minute period. During the one
minute it appeared to have input referred offset variations of
± 5.0 p.V. Shielding the circuit from air currents reduced this
to ± 0.5 P.V. The 10 P.V error was due to thermal gradients
across the circuit from air currents.
Resistor choice as well as physical placement is important
for minimizing thermocouple effects. Carbon, oxide film, and
some metal-film resistors can cause large thermocouple errors. Wirewound resistors of evenohm or managanin are
best since they only generate about 2.0 p.V,oC referenced
to copper. Of course, keeping the resistor ends at the same
temperature is important. Generally, shielding a low-drift
stage electrically and thermally yields good results.
Resistors can cause other errors besides gradient generated voltages. If the gain setting resistors do not track with
temperature, a gain error will result. For example, a gain-of1000 amplifier with a constant 10 mV input will have 10V
output. If the resistors mistrack by 0.5% over the operating
temperature range, the error at the output is 50 mY. Referred to input, this is a 50 p.V error. Most precision resistors
use different material for different ranges of resistor values.
It is not unexpected that a resistor differing by a factor of
1000 does not track perfectly with temperature. For best
Ie
results, ensure that th,e gain fixing resistors are of the same
material or have tracking temperature coefficients ..
It is. appropriate to mention offset balancing as this can have
a large effect on drift. Theoretically, the drift of a transistor
differential amplifier. depends on the offset voltage..For· every miliivolt of offset vol~ge the drift is 3.6 p.V
TherE!fore, if the offset is nulled, the drift should be zero. When
working with IC opamps, this is not the case. Other effects,
such as second stage drift and internal resistor TC, make
the drift nontheoretical.
Certain types of amplifiers are optimized to have lower drift
with offset balancing such as the LM121 and LM725. With
this type of device offset, nulling improves the drift, and offset nulling should be used. Other types of devices, such as
selected LM741 's or LM308's, are selected for the drift without offset nulling connected to the device. The addition of a
balancing network changes the internal currents and thus
changes the drift-probably for the worse-so any offset
balancing should be done at the input.
No matter which null network is applied, highly stable resistors must be used. They should have low TC and track.
Wirewound pots are usually a good choice. Finally, when
the null network reduces a drift, the balanCing of the amplifier as close to zero offset as possible minimizes the drift.
Testing low-drift amplifiers is also difficult. Standard drift
testing techniques such as heating the device in an oven
and having the leads available through a connector, thermoprobe, or the soldering iron method do not work. Thermal
gradients can cause much greater errors than the amplifier
drift. Coupling microvolt signal through connectors is especially bad since the temperature difference across the connector can be 50"C or more. The device under test, along
with the gain setting resistor, should be isothermal. The circuit in Figure 1 will yield good results if well constructed.
rc.
,~k
CONNECTOR
>-Vos X 1000
'.
OVEN
AMBIENT
TL/H/8728-1
FIGURE 1. Drift Measurement Circuit
CONCLUSION
Low-drift amplifiers need extreme care to achieve reproducable low drift. Thermal and electrical shielding minimize
thermocouple effects. Resistor choice is also important as
they can introduce large errors. Careful attention to circuit
layout offset balancing Circuitry is also necessary.
1178
-National Semiconductor
Linear Brief 23
Precise Tri-Wave
Generation
INTRODUCTION
F=
The simple Tri-wave generator has become an often used
analog circuit. Tri-wave oscillators are more easily designed,
require less circuitry, and are more easily stabilized than
sine wave oscillators. Further, the highly linear output of todays Tri-wave generators make them useful in many
"sweep" circuits and tesf equipment.
This article describes a triangle wave generator with an easily controlled peak-to-peak amplitude. The positive and negative peak amplitude is controllable to an accuracy of about
± O.OW by a DC input. Also, the output frequency and symmetry are easily adjustable.
CIRCUIT DESCRIPTION
The Tri-wave oscillator consists of an integrator and two
comparatol"S-- ....--'~OUTPUT
Note 1: All operational amplifiers are LM118.
TL/H/8474-1
Note 2: All resistors are 1% unless otherwise specified.
Note 3: All diodes are 1N914.
Note 4: Supply voltage ± 15V,
11,82
Amplifiers A2 through A5 with transistors 01 through 04
form a log multiplier/divider. Since the currents into the op
amps are negligible, all the input currents flow through the
logging transistors. Assuming the transistors to be matched,
the Vbe of 04 is:
Vbe (04) = Vbe (01) + Vbe (03) - Vbe (02)
The Vbe'S of these transistors are logarithmically proportional to their collector currents so
log (1C4) = log (IC1)
+ log (Ics)
- log (1C2)
I
IC11C3
or C4 = Ic;where IC1' IC2' IC3, and 1C4 are the collector currents of
transistors 01-04.
Since ICl equal Ics and is proportional to the input, the
square of the inpu1 signal is generated. The square of the
input appears as the collector current of 04. Averaging is
done by C4, giving a mean square output. The filtered
outpu1 of 04 is fed back to 02 to perform continuous division where the dMsor is proportional to the output signal for
a true root mean square outpu1.
Due to mismatches in transistors, it is necessary to calibrate
the circuit. This is accomplished by feeding a small offset
into amplifier A2. A 10V DC input signal is applied, and Rl0
is adjusted for a 10V DC output. The adjustment of Rl0
changes the gain of the multiplier by adding or subtracting
voltage from the log voltages generated by the transistors.
Therefore, both the resistor inaccuracies and Vbe mismatches are corrected.
For best results, transistors 01 through 04 should be
matched, have high beta, and be at the same temperature.
Since dual transistors are common, good results can be obtained if 01, Q2 and 03, 04 are paired. They should be
mounted in close proximity or on a common heat sink, if
possible. As a final note, it is necessary to bypass all op
amps with 0.1 ,...F disc capacitors.
1183
CII~
U)
d:
....
'
r-------------------------------------------------------------------------------------,
National Semiconductor
Specifying SelectedOp ,
Li...ear Brief 26
..
Amps and Compar.ators'
.;
\
It is not infrequent that cor:001,ercially available ,standard IC
componel1ts do not fit a pa~icular application ~s ll1ey ~re
specified: Often, however, a standard device slliected to
tighter limits will work. Thereupon, the IC manufacturer may
be requested to supply a specially tested d~*e. '
The usual chain of events for a selected part is all follows: A
specification is serit to the rT)anufacturer with request for
quote. It is evaluated, at the rT)anuf,acturer ~or feasibility,
yield, and testing requirements, Then price and delivery are
quoted to the ~ustomer. (Sometimes this route is sllorteneci
by calling the manufacturer-;-but thi,s does not alwayswork.),
a
Some insight into the IC design and IC.testing can help both
the manufacturer and IC user with special selection. Proper
specification helps the manufacturer test as well as reduce
IC costs. Ambiguous or impossible specs will usually result
in the return of the specification to the customer for clarification and delay the delivery of the required parts.
~ffset
measuring the
'voltage at th;ee or more temperatures;
then subtracting and dividing by the temperature change to
obtain the drift-a long and tedious rrieasureinent.
'
In some cases tightened offset voltage specifiCations over
the operating temperature range, offer the same performance as a drift tested device, but a:re less expensive. This is
because offset voltage measurement, can be a go/no-go
measurement. For example, 15 p.V/·C can ~ guaranteed
oller a 100·C range by limiting the m!IXimul)'l offset voltag/il
to ±0.75 mV or a 1.5 mV band. If the application has an
error budget of
"X" volts, it may be better to tighten the
offset voltage, rather tha,n ~ave the manufacturer to drift
test. Drift testing a comparator is virtually impossible sinCe
they are not designed to operate closed loop.
±
Other parameters dependent upon matching are: offset current, common mode rejection, and supply rejections. These
can be greatly tightened at the expense of yield.
The manufacturer is usually familiar with the product and
production spread of devices. Further, test equipment is
available for measuring parameters specified by the data
sheet. In general, tighting selected data sheet parameters
causes no problems. Further, no additional test equipment
is needed for these tests-only the limits need be changed.
Bias current, supply current, gain, slew rate, and response
time are dependent upon both device design and processing. The limits for tighter parameters on these specifications
are more restrictive. Table II gives reasonable special seleetion limits. This is only a guideline and, of course, depends
on the device.
Perhaps one of the largest problems is over-specification.
Each tightened specification reduces the number of parts
available to the specification. For example, tightening several specifications at once could result in a 1 % or 0.1 % yield;
to supply 100 parts at this yield, between 10,000 and
100,000 parts might have to be tested, and that gets expensive.
Noise testing is in a class by itself. Op amp noise will vary
between manufacturers of the same device. Further, noise
will vary between different types of devices from the same
manufacturer. Since noise on a particular device is mostly
process dependent, it will be relatively consistant from a
single IC producer.
Of course, spec limits cannot be tightened to any desired
value. This is due to limitations on the IC design. For example, bias current, which depends on transistor HIe; can not
be tightened by a factor of 10. This would require beta's 10
times higher than normal. Also, some specifications are not
, independent, such as op amp bandwidth and slew-rate.
OP AMP AND COMPARATORS
These are the two most popular linear IC components requiring selection. Since many of the same speCifications apply to both types of devices, they will be covered together.
Table I shows the most common parameters tested on
these devices and the relative difficulty of testing on high
speed equipment.
Selected offset voltage and drift are very commonly speCified parameters. Offset voltage and drift depends on component matching. In general, drift is not usually tested on
general purpose devices; although, it may be guaranteed.
Offset voltage can be correlated to drift, and the offset limits
are set to guarantee the standard drift specification. Of
course, very low drift devices must be 100% tested for drift,
making them relatively expensive. Drift testing requires
Noise can be broken into two categories: white noise, and
popcorn noise. Both of these noise sources can be either
voltage or current noise. It is possible with advanced processing to make IC transistors as good as the best discrete
low noise transistors. With good processing only a very
small percentage of op amps will have any popcorn noise.
Noise measurements are time consuming and costly. Popcorn noise testing may take as much as 30 seconds per unit
which limits production to about 100 devices per hour. This
low production rate will increase costs. If not absolutely neeessary-do not specify noise.
As a final note, some mention should be made of other
special testing. Anything reasonable can be done; however,
it should be kept in mind that accurate specification in terms
of the IC parameters is necessary. It is unlikely a positive
result will come from a specification showing a system
schematic, system output, and stating "select devices to
produce desired outputs." Although this is an exaggeration,
it points out the type of specification to be avoided. Performance specification should apply to the IC not to a circuit
using the IC. Many manufacturers have circuits available
showing the various electrical tests and the way they are
done.
1184
TABLE I. Relative Ease of Parameter,:r~stlng
,.
Parameter
OpAmp
Offset Voltage
Offset Current
Bias Current
Supply Current
Common Mode/Supply Rejection
Gain
Input Resistance
Easy
Easy
Easy
Easy
Easy
Moderate
Guaranteed by
Bias Current
Measurement
Moderate
Difficult
Very Difficult
Very Difficult
Slew Rate
Bandwidth/Response Time
.Offset Voltage Drift
Offset Current Drift
",
Comparator
Easy
Easy
Easy
Easy
Easy
Moderate
. Guaranteed by
Bias Current
Measurement
Moderate
Difficult
Very Difficult
Very Difficult
Cost
low
low
low
low
low
low
NotTested
Relatively low
Moderate
High
High
TABLE II. Guideline to Tightened Specifications
Limit
Parameters
Offset Voltage
Offset Current
Bias Current
Supply Current
0.1 mV
-50% of Nominal
-50% of Nominal
-25% of Nominal
"
Gain
Common Mode/Supply Rejection
Slew Rate
Bandwidth
Response Time
Offset Voltage Drift
+ 100% of Nominal
+ 200% of Nominal
+ 30% of Nominal
+30% of Nominal
-30% of Nominal
0.2 ",VrCto 5 ",vrc
Offset Current Drift
Guarantee by Offset
Current limit
1185
Comments
Matching
Matching
Depends on HIe
Depends on Various Process
Parameters
Set by Design
Matching
Set by Design
Set by Design
Set by. Design and Processing
lower limit May Not Apply
to Many Op Amps
~
~.
~
r-----------------------------------------------------------------------------,
Micropower Thermdmeter
National Semiconductor
Linear Brief 27
The introduction of a monolithic temperature transducer for
the - 55'C to + 125'C temperature range can considerably
simplify the problems encountered in temperature measurement. The three most common sensors-thermistors, resistance sensors, and thermocouples-requlre a reasonable amount of circuitry for use. Thermistors are highly nonlinear, resistance sensors and thermistors require a stable
excitation voltage, and thermocouples have low output. Further, none of these sensors provide an output directly calibrated in a known temperature scale.
The new monolithic temperature transducer provides an
output directly proportional to absolute temperature at
10 mV/'K. The chip includes a temperature stable voltage
reference and op amp. These allow the output to be offset
and scaled to provide any desired temperature scale factor
and zero output temperature.
able. Since the temperature transducer requires about
1.0.mA for normal operation, the thermometer is pulsed at a
low duty cycle to reduce power consumption. A continuous
output is obtained between pulses by a sample and hold.
Since temperature does not usually change rapidly, the
pulsed operation of the thermometer does not detract from
its usefulness.
With the components shown, duty cycle is about 0.2% with
a one second sample rate. This gives an average current
drain of about 25 p.A plus the output current. It is designed
to operate over a supply voltage ·of 8.0V to 12V with good
results. A small 8.4V mercury battery can give an operationailife in excess of one year.
The output of the thermometer is a current proportional to
temperature which can be used to drive a meter for a direct
readout. Alternatively, a resistor or op amp can be used to
obtain a voltage output.
A complementary astable multivibrator, made of 01 and 02,
drives the LX5600 through R9. The timing is set by several
THERMOMETER DESIGN
The circuit shown will provide a temperature sensitive output with both zero and scale factor independently select-
r
R4
Uk
01
lN457
DZ
IN4i7
RI
10k
R7
4.7k
RZ
101111
..; ; - - - - '
-~7x"
L.
O.Z"'F
RICRi
Uk
RU
I
R3
802M
CI
Rl.
1.17k
I
I
I
I
I
I
I
I
I
I
RI
Uk
18k
R11
RIB
12k
3I.18k
(0.1118) AT
10 (B.lV - 8.01 To)
RIZ -10010 - R14
Rl. =1.1 X 10" - RIZ - R14
AT - TEIlll'ERATURE SPAN ("K)
10 • FULL SCALE OUTPUT CURRENT (AMPS)
118
.10k
To - TEMPERATURE FOR ZERO OUTPUT
OUTPUT
TUH/8476-1
Mlcropower Thermometer Circuit Diagram
1186
r---------------------------------------------------------------~------__,
comPonents. C1 and R3 control the off-time and C1, R1, R4
and R'7 control the on-time. R9 sets the operating current of
the t~sducer to 1.0 mA at the lowest supply voltage.
When the- transducer is "on," sample transistor 03 is also
on. The output of the op amp drives the sample capacitor,
C3, and MOSFET, 04. Feedback is obtained from R12, R14
and R 16 which set both the zero and scale factor of the
thermometer. When the transducer is turned off, a ,continuous output is provided byC3 and 04. Resistor R15 decreases the circuit's sensitivity to MOSFET gm, allowing almost
any MOSFET to be used. About 2.0V should be dropped
across R15 at full scale output fiB is used to trim the thermometer, Correcting for zener tolerance, temperature error
in the sensor and resistor tolerance. With the values shown,
a 0 to 50 ,..A output is obtained for a + 50°F to + 100"F
temperature change. Other ranges can be selected by using
the formulas shown in the box on the circuit diagram.
The low power consumption makes this thermometer especially attractive for battery operated equipment. Further, the
current source output allows long lines to be driven with no
loss of accuracy. Finally, the cirCUit is easy to set up for
almost any desired temperature range.
1187
r
If'
N
....
National Semiconductor
Unear Brief 28
General Purpose Power
Supply
INTRODUCTION
A general purpose lab type constant voltage/constant current power supply is easily made using standard Integrated
circuits. The circuit shown will provide up to 25V at up to
10A output with both the output voltage and current adjustable down to zero. Although relatively simple, very high performance is obtained.
Lab supplies must withstand considerable abuse. Good
control of maximum output current is mandatory both to protect the supply and the powered Circuitry. One of the shortcomings of many commercial supplies Is the use of a large
output capacitor to help frequency compensate the regulator loop. This output capacitor can discharge many times
the peak output current of the supply Into the load as well as
degrade the ac output impedance when the supply is used
as a constant current source. (Of course, the OUtput capacitor helps keep the ac output impedance low when the sup-
ply Is used as a constant voltage source.) The circuit shown
has good response both as a constant voltage or constant
current source.
The use of the LM395 monolithic power transistor as the
pass element considerably simplifies the design power. The
LM395 acts as a 2A current limited, thermelly limited, high
gain power transistor. Since only a maximum of 10 jJA Is
needed to drive the pass elements and complete overload
protection Is included on the chip, external biasing and protection circuitry Is minimized. Only two control op amps are
needad-one for voltage control and one for current control.
In constant voltage operation, a reference voltage is fed
from voltage control pot, R1, through a high frequency filter
into the non-Inverting input of an LM308 op amp. The output
of the LM308 drives seven paralleled LM395's as emitter
followers to obtain a 10A capability.
~----------------------------~~----~---r
C7
ZIV-3&V
R8
10k
r2.2lt
FO
Re
8.1
UNREGULATED
lOW
LM113
RI
10k
RZ
It
CURRENT
ADIUST
R3
Ik
R7
SOk
'='
51
Dl
11121
VOLTAGE
ADJUST
Cl
8.1~F
'SolId Tantalum.
"Lights during current limiL
..... .- - - -
~VTO-IOV
TLlH/84n-1
1188
Feedback is taken through R10 directly from the output with
the overall gain set at 5 by the ratio of R10 to R7. An additional LM395 is driven from the negative power supply lead
of the LM308 to provide some output current sink capability
(2A) so the supply can be quickly programmed even with
large capacitive loads. Frequency compensation is
achieved with C3 for the LM308 and C4 for the overall loop.
Resistor Rll, capacitors CS and C6 and network R1S-C9
suppress parasitic high frequency oscillations.
positive, reverse biasing D3 and the LM308 control the
outpput. When the current increases to the control point the
output of the LM101A swings negative and decreases the
drive to the output pass devices through D3, limiting the
current. (Note that no separate positive supply is needed
since the common mode operative range of the LM101A is
equal to the positive supply.) Diode, D2, clamps the output
of the LM 101 A when it is not regulating, decreaSing the
switchover time from voltage to current mode operation.
When the circuit is used in the constant current mode, the
LM101A overcomes the constant voltage loop to control the
output. Output current is sensed in R9 and compared with
the voltage between V+ and the arm of R2. R2 is connected across an LM113 low voltage reference diode to provide
a OV to 1.2V reference for OA to 12A output. When the
output current is below the set level, the LMl 01 A output is
A few special precautions are needed in construction for
proper operation. All LM39S's should be mounted on the
same heat sink to insure good current sharing. Also, a large
heat sink is necessary since 300W will be dissipated under
worst case conditions. Since the LM39S's are high devices,
the supply bypasses should be near the power transistors.
1189
~
~."
Microvolt comparator
National Semiconductor
Linear Brief 32
INTRODUCTION
Comparison of dc, signal levels within microvolts of each
other can be made. by using an .LM12:1A pre-amp. and an
LM111 comparator IC. Implementing this with \WO separate
IC's decreases .noise, eliminates troublesome thermal ef.
fects, and achieves a maximum. offset drift of 0.22 p.V/oC
(Figure 1).
DESIGNING WITH A PRE-AMP
With the bias network shown, the'LM121A input stage has
an open-loop temperature steble voltage gain. of close to
100. The 100k QUtput impedance of the LM121A is shunted
by Cs to filter out piCkup and internally generated noise. No
feedback to. theinp!lts of the pre-amp is employed to avoid
degrading common-mode rejection of the system.
The separate pre-amp with a gain of 100 provides 'two majOr
advantages over single comparator designs. Pirst, Vos and
other small errors attributed to the LM 111 are reduced by
the 100 gain factor. More important, temperature gradient
changes which occur within the LM111 when switching any
output load, are completely isolated by the separate packages and do not affect the pre-amp. If the entire microvolt
comparator were on a single silicon chip, a temperature variation of as little as 1/10WC across the input stage could
have a significant effect.
DeSigning a practical compatator with a voltage gain of 10
million involves protecting the input stage from temperature
changes or gradients, and avoiding problems of including
the noise filter within the positive feedback loop. The circuit
as shown has a 5 p.V hysteresis which can be trimmed to
1 p.V under certain conditions. Further, delays decrease
with increasing overdrive (see chart) due to elimination of
input stage thermal effects, saturating stages, and dielectric
soak or polarization effects on signal filter capaCitors
(Table I).
D
TABLE 1_ Typical Overdrive Delays
Hyst.
Set
RH
5 p.V 75kO
Rs
Delays with Various Overdrives
Cs
10kO
6800pF
Max.
25%
100%
1000%
100mV
2ms
1.8ms
600p.s
560 jJoS
------------""1
"0V REG 0-...- - - - - - -. .
33
r----I
,""'.....::..f
SIGNAL SOURCE
RS
I INPUT
IL. _
·WIREWOUNO
__
5.1.
I
'
~...I:,,::-"::..j
-------4I. . . .
.~~::::--4....
-..;;;...-O-10V REG
TLlH/8733-1
FIGURE 1. SchematiC Diagram
1190
This,effect is a major reason for designing circuits sensitive
and stable to microvolt dc signals with a separate pre-amplifier. Further, the special 4-transistor input stage, when adjusted to zero offset with the "balance" control between
pins 5 and 6, automatically reduces Vas change with temperature to almost zero.
FILTERING
The pre-amp/comparator system generates a continuous
stream of very fast pulses if assembled without a filter, even
with positive feedback for hysteresis. This is caused by both
stray output-input feedback, and noise. The noise is both
thermal and pickup from the environment, including power
switching transients and fluorescent light hash. To cure this,
shunt filter capacitor Cs is used.
Placing this capacitor outside the positive feedback loop
has two advantages. It eliminates a tendency for the comparator to oscillate during slow transitions. Also, response
time to small signals is halved since the positive hysteresis
feedback signal is not stored on the filter capacitor.
A higher frequency filter (Cd Is needed to provide a low
impedance shunt to any high frequency noise and stray
feedback that may be picked up between LMlll terminals
5 and 6. These two terminals have almost the same voltage
sensitivity as the normal input terminals. The positive feedback to terminal 5, as described below, is only delayed
slightly by this filter.
FEEDBACK
The positive feedback provided by the 5.1 k/33fi voltage
divider with RH is needed to insure clean, rapid changes of
state. It is applied to one of the "balance" terminals (pin 5)
of the LM 111 to simplify the circuit over a balanced feedback network, and to minimize signal stored on Cs as previously described. The current fed back to terminal 5 is single
ended with respect to the balance adjust network between
these terminals, and hence injects a dc offset of the desired
polarity and amplitude for a few microvolts of latching. '
PERFORMANCE
A tabulation is shown for one of the many possible combinations of input circuits, filters, etc. For large amplitude signals, Cs can be decreased and hysteresis increased for
greater speed. Conversely, to obtain hysteresis as low as
1 !£ V, trim RH (to about 300k) use a Cs of 0.01 !£F to 0.1 !£F
and have a low impedance source of signals.
For reduced ambient range and, drift specifications, an
LM321 can be paired with the LM311 for a cost saving while
maintaining the same comparison sensitivity.
DESIGN TIPS FOR MICROVOLT SIGNALS
Even with high performance devices such as the LM121,
microvolts of error can occur from thermocouple effects,
common-mode signals, "microphonics," or unbalances in
the input or nulling circuits. As pointed out in Application
Note AN-79, Kovar lead to copper circuit board thermocouple effects can cause a 3.5 !£V offset voltage for only O.l·C
difference across the input leads. A compact layout of input
connections and shielding from air currents will minimizE!
this problem.
Although the LM121A has excellent common-mode rejection (> 120 dB), a 1V change in common-mode voltage can
induce up,to 1 !£V of error voltage. For this reason commonmode voltage changes should be kept to a minimum. Also,
common-mode voltages allow mechanical vibrations in the
probe cable to induce "microphonic" noise signals. Short,
stiff, low capacitance and symmetrical input shielded wires
are recommended.
If it is possible to have a signal source balanced with regard
to ground, it will help decrease errors due to bias currents,
and noise due to common-mode aild microphonic effects.
Matched, low temperature coefficient parts should be used
in the balance network, and care should be exercised in
shielding input circuits and eliminating ground-loops.
APPLICATIONS
The microvolt comparator is particularly well suited to controllers or test equipment having thermocouples or strain
gauges as inputs. This includes wind speed indicators, RMS
to dc converters, vacuum gauges, gas analysis equipment,
conductivity gauges, and hot wire controls. The strain gauges can be used in materials testing, electronic weighing,
pressure transducers, and load limiting sensors for cranes,
hoists, and rolling mills.
As a temperature controller, Ys degree or less on-off differential can be obtained using thermocouple types E, J, T or
K. Other microvolt signals used for control may come from
Hall effect sensors, Bolometers, slide-wires, and heat-flow
thermopiles. A microvolt comparator will be useful in
"GolNo-Go" testing of low resistances such as switch and
relay contacts, RTDs, coil and fuse resistances, and pressure-sensitive-plastic conductors.
1191
--~
r--------------------------------------------------------------------------------,
~ A Micropower'
National Semioonductor
Linear Brief 34
Voltage Reference
A low-drift voltage reference can be easily made by convert·
ing a zero temperature coefficient current to a voltag&.
JFETs biased slightly below pinch·off exhibit a zero temper·
ature coefficient drain current (10) as shown in Figure 1.
With the ,above property and a micropoweroperational am'
plifier, used, to convert the drain current to a voltage, a 'low
power consumption voltage reference can be boilt as shown
in Figure 2. The consumption of LM4250 op amp is programmed through resistor, RSET. Potentiometer P1 should
be adjusted for low output (VREF) temperature coefficient.
Actually, it can be trimmed for positive, negative or ,zero
temperatu~e coefficient. The-output voltage is trimmed
through P2 and it is expressed by:
VREF = 101 (PI!
+ R1 + R2),
R2 = R3, 101' "" loss [1 _
~~S
Y
current less than 100 !IA. The characteristics of the lM4250
are a function of its supply current, which depends on RSET,
and V+. V+ can be provided by VREF through ,the addition
of a second FEr, J2, shown' in FlfJUre 3. This way the pa.
rameters of the op amp will be independent of. the unregulated input. The reference voltage can be taken from the
wiper of the potentiometer P2 (VREF = V+) or from the
source of J2 (VREF > V+). In the first case, the output
impedance of the circuit is quite high and buffering may be
required according to the application. The output imped·
ance in the second case is low, essentiaUy the 1/gm of (J2)
divided by the loop gain of the circuit. In this case, a small
temperature coefficient due to -the supply current of _the
LM4250 is going to be added and be compensated for by an
E!-dditional trimming of P1. VREF is computed by:
VREF '" 101 [P2
+ R1 + R21 + P~ [Is + 1011,
R2 = R3 I "" 6 (V+ - VeE)
, S,
RSET
With the values shown in Figure 2, the temperature coeffi·
cient of the output is 0.002%/OC I\nd the overall standby
10
Vas
TLlH/B734-1
FIGURE 1. FET Transfer Charaete,rlstlcs
V·
-
loj
.....+-oVREF(10V)
P2 = VREF Adjust
TL/H/B734-2
-
TLlH/8734-3
FIGURE 3. Improved Voltage Reference
FIGURE 2. Basic Voltage Reference
1192
Adjustable 3-Terminal
Regulator for Low-Cost
Battery Charging Systems
National Semiconductor
Linear Brief 35
With the introduction of the LM317, a' 3-terminal adjustable
regulator, it becomes relatively easy to design high-performance, low-cost battery charging systems. Even single battery cells can be charged on this new regulator, which is
adjustable down to 1.2V. The internal protection circuitry
can be used to limit charging current as well as to protect
against overloads. The output voltage is easily adjusted so
multiple voltage chargers can be made.
generated. The LM317 can also be used to limit the peak
charging current to a partially charged battery at a value
other than the regulator current limit. With R 1 in the circuit,
the output impedance is:
The ability to accurately ,adjust the ,output voltage of the
LM317 makes it especially attractive for constant voltage
battery charging applications. BatterieS are most quickly
charged by "constant-voltage" charging circuits; however,
close control of the charging voltage is necessary to preve(1t overcharging, especially with nickel cadmium cells. The
internal protection circuitry of the LM317 is helpful in protecting against accidental overlo~d conditions commonly
occurring in charging systems.
INTERNAL CURRENT LIMIT
The peak charging current or output current is controlled by
the internal current limit of the LM317. This current limit will
work even if a battery is connected backwards to the output
of the charger. Should a fault condition exist for an extended period of time, the ~hermallimiting circuitry will decrease
the output current, protecting the regulator as well as the
transformer. A constant voltage charger circuit is shown in
Figure 1. The output voltage is set with resistors R2 and R3
and givehby
VOUT =, 1.25 ( ,1
+ R3)
R2
R4
r--~--'
I
Rl
I
lour =
R1 (1
+
~:)
Including R1 in the feedback loop decreases the value of
resistor needed for a particular output impedance reducing
cost and power dissipation.
For example, with a 6V gelled electrolyte battery the regulator can be set to give a 6.9Y output. Nominally, the battery is
discharged to about 5V, making R1 0.40 output impedance
and limiting the charging current to 'O.5A at the start of
charging'rather than the internal current limit of the regulator. With a fully dischar,ged battery or under short circuit
conditions, the peak output current is still 2A for the
LM317K with the resistor dissipating 1.6A as opposed to 8W
if a 20 resistor were used directly in series with the battery.
Resistor R4 can be included to provide a low "topping-up"
current for a charged battery.
This regulator configuration provides some other important
features to the charger. If input power is removed and a fully
charged battery is connected to the charger output, there is
no damage. Under these conditions about 5 mA of current
will be drawn by divider R2, R3. Since there is no ground
connection to the LM317 regulator, very little current flows
through the LM317. In this respect, the LM317 differs from
other 3-terminal regulators, which can be damaged by applying power to the output terminal with the input open-circuited. If the battery is connected backwards, theLM317
will current limit and thermal limit normally, protecting the
charger.
DECREA$ING CURRENT LIMIT
Adding a single NPN transistor can be used to decrease the
current limit of the charge as shOWn in Figure 2.
R2
240
II
TLlH/8484-1
FIGURE 1. Constant Voltage Charging Circuit
Since, in low cost applications, no filter capaCitors are used
on the output of the rectifier, the battery is only charged on
the peaks of the sine wave. This requires the peak output
voltage from the transformer to be at least 50% greater
than the battery voltage plus 3V. However, little cost premium should result since the average current from the transformer is lower than capacitive input filter circuits. Optional
resistors R1 and R2 are used to further control the charging
characteristics. Resistor R1 controls the output impedance
of the charger allowing a "taper-charge" characteristic to be
1193
II
TLlH/8484-2
FIGURE 2. Constant Voltage Charger
with Peak Current Limiting
ReSistc\r R1senses the output current and turns Oil a1
lOUT R1 equals about 0.6V. Transistor Q~ pulls the
adjustnieQt terminal negatively decreasing the output voltage and Controlling the output current A limitation of this
circuit is that it does not work for direct short circuits. The
output voltage must be above about 0.6V for the external
current limiting to be active. The internal current limit of the
LM317, of course, is still operative. This is not usually a
problem sinCe batteries charge to aboveO.6V very quickly.
Resistors R4, R5 and R6 protect the rellulator and transistor
for both direct short circuits or reverse battery connections.
wtien
A simple consll!.nt current charger for any:type ,of battery is
shown in Figure 4. A resistor R1 between the adjustment
terminal and the output of the regulator sets the output cur, . '
rent at: .
~
1.25
OUT=Fi1
Rl
Dl
II
TLlH/8484-4
FIGURE 4. Constant Current Charger
Current can be set at anywhere between 10 mA and 1.5A by
appropriate resistor choice. Current regulation is very tight
at any currerit level since only 50 p.A flows out of the adjustment terminal. This circuit is also immune to damage from
shorts or reverse battery connections. The input voltage for
regulation should also be about 1.5 times the battery voltage plus av.
I
TLlH/B,484-3
FIGURE 3. Charger with No Battery Loa~ln9 when
Power is "OFF"
As illustrated in Ftgure 3, in float or standby applications, it is
desirable to remove all loading from the batt9l¥ when input
power is "OFF." When power is "ON," a1 is saturated,
grounding the voltage setting divider R2, R3 and the circuit
works in a similar manner to the charger circuit in Figure 1.
When power is "OFF," a1 is open, eliminating any loading
on the battery. A separate pair of low current diodes 01, .02
are necessary to bias aI, rather than the power bridge rectifier. If R1 wastiad to the output of the bridge, reverse current flow through the LM317 would keep a1 "ON" and'load·
ing the battery.
UNIQUEL.V SUITED
The ability to adjust the output of the LM317 3-terminal regulator makes it uniquely suited for battery charging systems.
Little has. been included about charging specific 'types of
batteries,' since, the characteristics of the charger should be
matched to the battery. These charger circuits, although
very simple, perform'well: they are easily modified for voltage, current or even temperature coefficient by making the
divider string temperature sensitive. More complex chargers
can be made since the output of the LM317 is easily con·
trolled by driving the adjustment terminal. Finally, the chargers are inherently protected against overioads and fault
conditions.
1194
Wide Range Timer
National Semiconductor
Linear Brief 38
orie of the problems encountered in potentiometer controlled circuits is dynamic range. With a linear pot, about a
100;1 range is the limit. Although the pot resolution may be
better than 1%, the angular disPlacement for good control
becomes too small. Usually, range switching is then used.
A logarithmic control is a possible solution. With log controis, the resolution is the same anywhere within the operating range. For example, if 40" rotation is equal to a change
from 10% to 100% of full scale, then 40· rotation is also
equal to a change from 0.01 % to 0.1 % of full scale. It is
easy to control a function over a 1,000,000:1 range with
good control anywhere within the range.
The exponential relationship between the emitter-base voltage of a transistor and its collector current is well known.
This relationship holds true within a few percent over extremely wide ranges.. Using a transistor pair, and an op amp,
it is easy to make a current source controllable over a 6
decade range.
FiglJf9 1 shows a timer which can be adjusted from 2 ms to
2000 seconds with a single control. An LM122 is used for
the timing function in conjunction with a current source that
is logarithmically controlled from a pot. The operation is as
follows:
Transistors 01 and 02 are a matched PNP pair. Resistor R1
and the op amp set up a constant current of 1 rnA through
01 using the internal 3V reference from the timer. With R2
at the most positive end of its range, the non-inverting input
of the op amp is a VREF. This forces the emitter-base voltage of 02 to equal 01' and since the transistors are
matched, the collector' current of 02 is also 1 rnA. A timeout period of 2 ms results.
Rotating R2 subtracts the voltage between the arm of the
pot and VREF from the emitter-base voltage of 02-1owering its collector current. The current is decreased by a factor
of 10 for every 60 mV developed. A total of 360 mV is
dropped across the pot, allowing a, reduction in 02 collector
current by a factor of 1,000,000 or from 1 mA to 1 nA. A
1 nA charging current gives a 2000 second time out. (At
maximum time, tllere is about a 30% error due to the 0.3 nA
input current of the comparator). Finally, diodes 01 and 02
temperature compensate the voltage across the pot.
Calibrating the circuit is relatively easy (except for obtaining
a log dial for the pot). Resistor R1 is adjusted for the minimum operating time removing for mismatch in the transistors, capecitor tolerance, and the offset of the op amp. R~ is
used to calibrate the full scale time by adjusting the drop
across R2 to 360 mV.
This type of log control is not limited to timers. If used in
oscillator or function generator circuits, an ultra wide range
vee can be made. Also, in power supply circuitry, it is pOSSible for a reguator to have as much resolution when adjusted
for O.OOW output as when the output is 10V. Finally; a log
current generator makes an easily adjusted low value current source without high value resistors.
y+
TRIGGER
•_-_-+__. .
TRIGGER
VREF
OUTPUT
LM3ZZ
R3
..._ _4~R/c
4111
aND
Rl
311
Cl
ljtF,
Tl/H/8487 -1
FIGURE 1. 2 ms to 2000 Second Timer
1195
~ r-----~~------------~------~----------~~--------------------------------~~
~ Circ~it Techniques for,'
National Semiconduct,pr,,;
Linear Brief 39
Av~jding
..
Oscillations in
Comparator Applications
When a high-speed comparator such as the LM111 is used
with fast input signals and low source impedances" the output 'response will normally be fast and stable, assuming that
the power supplies have been bypassed (with Q.1, p.F disc
capacitors), and that the output signal ii!, routed well away
from the inputs (pins 2 and 3) an~ 'aJso away from' pins 5
andS.
" , ' ", ,
However, when the input signal is a voltl!ge ramp or a~low
sine wave, or if the Signal source impedance is high (1 kG to
100 kG), the comparator may burSt irito oscillation near the
crossing-point. This is due to the high gain and wid~ !:>andwidth of comparators like the LM111. To avoid oscillaticln o,r
instability in such a usage, several precautions are recommended, as shown in Figure 1below.
",
"
1. The trim pins (pins 5 and S)' aCt as unwanted auxiliary
inputs. If these pins are not connec~ed to trimpot, they
should be shorted together. If they are connected to a
trim-pot,a 0.01' ~F capacitor C1 between pins 5 and Swill
minimize the susceptibility to AC coupling. A, smallercapacitor is 'used if pin 5 is used 'for positive feedback as iri
a:
Figure 1."
,
,
2. Certain sources will produce a cleaner cornparator Qutput
waveform if a 100 pF t01 000 pF Clapacitor C2 is' conneCted directly across the input pins. ",,'
,
"
3. When the signal source isapplied'through a resistive I'!~i
,work, As~ it is usually advan~l!~ous tp chqo~ an As' of
substantially the same value, both for DC and for dynamic
(AC) considerations. Carbon, tin~xide, and inetal~film resistors have all been used successfully in comparator input circuitry. Inductive wirewound resistors are not suitable.
4. When comparator circuits use input resistors (e.g. summing resistors), their value and placement are particularly
~
important. In all cases the body of the reSistor should be
close to the device or socket. In other words there should
be very little lead len~~Ii' or printed-cirollit foil ,run, between
comparatpr and resistor to radiate or pick up sighals. The
same applies tocapa6itors, pots, etc. For eXlimple, if'Rs
" ,.; 10 kQ; as little as 5 Inches' of '1e'8d between the res is,tors arid the'input pins 'cali' result i~ oScillations that are
very hard to damp. Twisting these input leads tightly is
, 'the, drilY (Second best) altematiVe to placing reSistors
close to the comparator.
r'·,
5. Sincet&edback' to almost any' pin of a' comp~tor can
result in C;lscillatlpll" the printed-circuit layout should b6
engineered thoughtfully. Preferably 'there should be a
groundplane under the LM 111 'circuitrY, for' example, one
side of a,double-Iayer,circuit card. Ground foil (br, positive
supply or negatiVe supply foil) sl'lould extend between the
output and the inputs, to act asa guard. ·The foil connections for the inputs should ibe as small, arid eompact as
possible/arid should be essentiallY surrotir'lded by ground
foil on all sides, to guard against capacitive coupling from
, any high-level signals (such as the output). If pins 5 and 6
, are not.used, they should be shorted together. IHhey are
connected to a trim-pot, the trim-pot should be located, at
most,',a, few' inches away from the ,LM111, 'and-the
0.01 p.F capaCitor should be installed. if this capacitor
cannot be, used; a shi~ldinll printed-circuit foil may ~,ad
,visable between pinsS and 7. The power.~ypply bypass
capaCitors should ,be located within, a couple inches, of
the LM,1,11. (Some other comparators requife the powersupply bypass to be located immediatelY adjacent to the
comparator.)
S. It is a standard procedure to use hystereSiS (pOSitive
feedback) around a comparator, to prevent oscillation,
, and to avoid, exc:essive noise on the output because the
r-_~----,,-oIBV
82
4.1k "
>,~--,,-oOUTPUT
-15V
TUH/8488-1
Pin connecttons shown arjllpr ~Ml,11 H in,8-lead,To,s h"'l'/1.etic package
FIGURE 1. Improved Positive Feedback
11'96
comparator is a good amplifier for its own noise. In the
circuit of F/{/ure 2, the feedback from the output to the
poSItive input will cause about 3 mV of hysteresis. However,if the value of Rs is larger than 1000, such as 50
kO, it would not be reasonable to simply increase the
value of the positive feedback resistor above 510 kO.
The circuit of Figure 3 could be used, but it is rather awkward. See paragraph 7, below, for the alternative.
7. When both inputs of the LM111 are connected to active
signals, or if a high-impedance signal is driving the positive input of the LM111 so that positive feedback would
be disruptive, the circuit of F/{/U1'8 1 is ideal. The positive
feedback is to pin 5 (one of the offset adjustment pins). It
is sufficient to cause 1 to 2 mV hysteresis and ensure
....-
sharp output transitions with input triangle waves from a
few Hz to hundreds of kHz. The positive feedback signal
across the 820 resistor swings 240 mV below the positive supply. This signal is centered around the nominal
voltage at pin 5, so this feedback does not add to the
Vos of the comparator. As much as 8 mV of Vas can be
trimmed out, using the 5 kO pot and 3 kO resistor as
shown.
8. These application notes apply specifically to the LM111,
LM211, LM311, and LF111 families of comparators, and
are applicable to all high-speed comparators in general,
(with the exception that not all comparators have trim
pins).
...
...----"""4~OI6V
r-~~----
4.7k
4.7k
>':---4~O OU~UT
-16V
-o15V
~~--__-oOU~UT
, II POSITIVE
----JVVV---:=!J FEEOBACK
TL/H/S4SB-2
Pin connecllons shown are for LMlll H In 8-1ead TO-5 hermetic package
TL/H/8488-3
FIGURE 3. Positive Feedback with
High Source ReSistanCe
FIGURE 2. Conventional Positive Feedback
11'97
~
_
National Semiconductor ,';'..
Linear Brief·4F
; preCisi()n .Reference.
U~~sOnly Ten
Microllmp~res' "
'FJ'"
""
',"
, r",
';',
.,
, ~,
,(
Increasingint",restJn.battery~pera~ed analog and digital circ;uitry in recent years has created tl'ieneed for a micro-power voltage reference. 'In particular, .the, reference ,shOllld
draw 10 fAA or I!I~ ll"d .operate from a single ~V s\lpply.
These requirementS' eliminate zener diodes Which tend to
have unpredictable temperature drift and are noisy' atlow
currents and low voltages. One possibility is the LM103 series of punch-through diodes which have break-down voltages of 1.8V to 5.6V aridoj!lerate well at 10 pA. Unfortunately, these devices drift at - 5 mVloC and extra circuitry
must be added to create a low-drif~ reference. Non-linearity
in the drift characteristic limits usable drift compensation to
about 50 ppm/oC. Variations in:'slope frOm. device to device
can be up to ± 0.5 mVJoe, so each reference must be Individually corrected for temperature drift in an oven test.
The LM 134 current source can provide an interesting solution to the Ipw-power-drain reference problem. This device
is a 3-terrnirial current source which has a compliance of 1V
to 40V and is programmable over a current range of 1 pA to
1oInA. CulTj3nt is determined by an 8xtemai resistor. With a
zero drift resistor, the LM134 current is directly proportional
to absolute, temperature ("K). Untrimmed accuracy of the
current is ±'3%, but the key to the success of the LM134 is
that initial errors are gain erroJ:S whic~ are trimmad to zero
when the external resistor is adjusted. Independent cif initial
current, if the current is adjusted to 298 p.A at T = 25"C
(298"K), all devices will· have a current dE!pendenC!il of 1
±O.01 pArCo
A voltage reference can be made by combining the positive
temperature co.f3fficient of the LM134 witl) the negative TC
of a forward-biasad diode. The Ie terminology for such a
reference is "bandgap reference" because the total voltage
of the reference is equal to the extrapolated (ooK) bandgap
voltage of silicon. An important characteristic of bandgap
references is that the zero TC voltage Is independent of
diode current even though tha diode voltage and TC are
not. This means that by adjusting the total voltage of the
reference to a fixed value, T.C. will be adjusted to near zero
at the same time. The zero TC voltage for most bandgap
references falls between 1.20V and 1.28V.
The circuit in Figure 1 is a micropower reference using the
LM134 and an MPSA43 transistor connected as a diode
with collector-base shorted. A transistor is used in place of a
diode because the transistor characteristics as a double-diffused structure are more consistent than a diode. In particular, the emitter-biased voltage drift of wide-base high-voltage transistors connected as diodes is very linear with temperature.
In F/(/ure 1, the LM134 controls the voltage between its R
and V- terminals to ::::: 64 mV. About 5.5% of the current
out of the R terminal flows out of the V- terminal. The total
current flowing through R2 is then determined by 67.7
mVIR1. Output voltage is the sum of the diode voltage, plus
the voltage across R2, plus 64 mV. The voltage TC across
'
. .~ :;
~.
..,I,
R2 and the: 64 ,m" is posiijve and. dir~ly pr9POrtiOriai to
absolute te~J?E!rature whil~ t!1e diode TO ~s ne~aHye. The
pverall Te of the output WIll. be near zllroJ < S~ ,ppl'l1rC)
wljen tile outpu~ is adjUsted to .1.253Y by. trimm!n,t" R2. 0
obtain this level of.perfprmanc9, R1 and fl2mustJrack well
over temperature. 1%. metal film resi!itors' are suggested.
:r
,
"
I
"
~.'
,
•
R3
3;B3k
VOUT
~"";''''--'V\j~-'1.253V
OpA-5pA
RZ
Tl/H/8735-1
FIGURE 1
For optimum results with a single. point adjustment of.voltage and temperature coefficient, an additional error term
must be accounted for. Internal to the LM134 are low Ides
FETs used for starting the control loop. This FET current
adds directly to the V- pin current and therefore creates an
additional output voltage equal to (ldsal(R2). Typical Idss is
200 nA, causing VOUT to be 14 mV high. Temperature coefficient of Ides is low, typically 0.1 %/oC. For best results in a
single point adjustment, VOUT should be adjusted to 1.253V
+ Idss (R2). Idss can be easily measured by open circuiting
R1 and measuring the drop across R2. The resulting voltage
must be divided by 2 due to an internal action which causes
2 Idss to flow when no current flows from the R pin. Example: with R1 open, 32 mV is measured across R2. Set VOUT
equal to 1.253V + 32 mV12 = 1.269V. Even lower TC can
be obtained by maasuring the output at 2 temperatures and
using the following formula to calculate the exact zero TC
output voltage for each reference.
T1 (V2 - V1)
VOUT(0 TC) = V1 T2 _ T1
Where:
V1 = Output voltage atT1
V2 = Output voltage at T2
T = Absolute temperture ("K)
1198
The limitation on temperature drift after a 2 point calibration
is non-linearity. This reference circuit has a non-reducible
bow error of = 10 ppml"C over a temperature range of
- 25·C to + 100"C and 5 ppm/·C from O"C to + 70·C. At
125·C, leakage creates significant error, causing the output
voltage to droop about 5 mY.
=
Noise of the reference consists primarily of theoretical shot
noise current from the LM134. At the 10 p.A level, this is
about 6 pAl v'Fii rms from 10Hz to 10kHz. Total output
noise would be 0.4 p.V/v'Fii rms over this frequency range,
except that C1 bypasses most of the noise above 2 kHz.
Measured output noise was 25 p.Vrms over a 10Hz to 10
kHz bandwidth with C1 = 1000 pF. Larger values of C1 may
be used if lower broadband noise is needed. Low frequency
noise is about 25 p.V peak-to-peak from 0.1 Hz to 10Hz.
The LM134 has a negative output resistance at the R pin
when resistance is inserted in series with the V- pin. The
value of this negative resistance is approximately -Rx/19,
where Rx is the equivalent resistance from V- to ground. In
this reference circuit Rx is 72 kG, yielding a negative output
resistance of 3.8 kG. Resistor R2 sums with this resistance
to give the reference a net zero output resistance (± 4000).
Loading should be limited to about 5 p.A. Line regulation for
the reference is typically less than 0.5 mV with an input
voltage of 5V ±2V. Minimum input voltage for a 2 mV drop
in output voltage is 2.5V at - 55·C, 2.4V at 25·C and 2.3V at
125·C.
Although this reference was designed for ultra-low operating current, there is no reason that It cannot be used at
higher current levels as well. All resistor values are simply
scaled downward. Higher operating current will give lower
output resistance, more drive capability, less sensitivity to
FET Idss, lower noise, and less droop at 125D C.
12
;;
.!
'"co
iii
>
...
.
...
.
to-
=>
to-
=>
4
-4
-
.....
,
-8
-12
-50
50
100
TLlH/8735-2
FIGURE 2. Output Voltage Drift
1199
150
TEMPERATURE COCI
f
......
~~----~--------------------------------------------------~
~ GetFa&fStableR.eSPOh$e
FrOl11lmprQv~d Uni~y-Gairi
Followers"
."...
~:~~~r!~~~conduetor
'
Robe~.A. Pea$e .
.
.~
...... .
a
.!.
In many applications, '1\ ~~ltv-gain foli~~j;lr (a.9~
o.parational amplifier with tight feedtlack to the inverting input)
may oscillate or exhibit bad ringing when: required to drive
heavy load capacitance. Fo." e)(8mple, thll LM110 follower
will normally drive a !So pF load ~acitor, but will not drive
500 pF, because the open-loop outout'impedance is lagged
by such a large capacitive load. The frequency atwhich this
lag occurs is comparable' to the gain7bandwidth product of
the amplifier, and when the phase margin is decreased to
zero, oscil!ation occurs.
'
any
. HI· ,'"
"
OUT
TL/H/B491-2
FIGURE 2. StabilizIng an Operational Amplifier for' :
Capacitive Load
A similar result will occur if you install R3 and
R2. Now the (AC) noise gain will be:
1
R4
RF
+ R3 + R3 +
ca, instead of
(RF) (R3 + R4)
R1
~
TL/H/B491-1
FIGURE 1. Unity-Gain Follower Attempting to Drive
Capacitive Load
While the solution to this problem is not widely known, an
analysis of the general problem shown in Figure 2 can lead
to a useful approach. It is generally known that increasing
the noise gain of an op amp's feedback network will improve tolerance of capacitive load. In Figure 2, adding a
resistor R2 "" RF/10 will do this. (A moderate capaCitor C2
is usually inserted in series with R2, to prevent the DC noise
gain from increasing also-to avoid degrading DC offset,
drift and inaccuracy.) If the op amp has a 1 MHz gain bandwidth product, and R1 = RF, the closed-loop frequency response will be Yz MHz. Adding R2 = RF/10 will drop the
closed-loop frequency response to 90 kHz, where the amplifier can usually tolerate a much larger CL;
Noise Gain =
As a simplification, if R1 is an open circuit, the AC noise gain
will be: (R4/R3 + RF/R3 + 1). Now it can be seen that
noise gain can be raised by having a low value of R3 and a
high value of R4 or RF (or both).
In particular, where RF is required to be 00, as in a follower,
the noise gain can be raised by adding a large R4 and a
small R5, as shown in Figure 3. If Rs is low, the AC noise
gain will be R4/R5 + 1. (If Rs is large and constant, R4
may be unnecessary, and the noise gain would then be Rsl
R5 + 1.) For LM110/LM310's R4 = 10 kO is recommended and when R5 = 3.3 kO, C5 = 200 pF, the LM110 will
stably drive CL up to 600 pF.
:~ + :~ + 1 (AC)
Noise Gain =
:~ + 1 (DC)
--.,
I
I
:SOURCE
I
I
--..I
TLlH/B491-3
FIGURE 3. Stabilizing a Unity-Gain Follower for
Capacitive Load
1200
Another application of this technique Is for .making a· fast
follower with a high slew rate. An LF356 is specified as a
follower, but an LF357 must be applied at an "Ay = 5"
t:nlnimum, because it has been "decompensated" with
smaller internal capacitor. Most people do not realize how
easy it is to apply an LF357 as a follower. In Figure 4, an
LF357 will have fast, stable response just like an LF356
does, when Rs is < 1 kG, but it will have a 50V I /los slew
rate (typical) vs. 12VI /los for an LF356.
HS
Uk
a
VOUT
-VS
TL/H/8491-5
TL/H/8491-4
FIGURE 4. Unlty-Galn Follower With Fast Slew Rate
Similarly, an LM348 is a fast decompensated quad 6p al)'lp.
Its bipolar input stage has a finite bias current, 200 nA mall:.
For best results, the resistance which makes up the noise
gain should be put equally in the plus and minus input circuits, as shown in F/{Jure 5. The LM349 can slew at 2VI /los
typical., and is much faster for handling audio signals without
distortion than the LM348 (which at 0.5V/ /los is only as fast
as an ordinary LM741). The same approach caribe used for
an LM101 with a 5 pF damping capacitor. While these circuits give faster slewing, the bandwidth may degrade if the
source impedance Rs increases. Also, when the AC noise
gain is raised, the AC noise will also be increased. While
most modem op amps have low noise, a noise gain of 10
may make a significant increase in output noise, which the
user should check to insure it is not objectionable.
FIGURE 5. Application of Fast Follower With Balanced
Resistors; R9 = R7 + Rs. A = 1/4 LM349 (or LM101
with 5 pF Capacitor)
If the series capacitor is much larger than necessary, noise
will be increased more than necessary. In general, choose
the C5 for FigureS, (e.g.) per these guidelines: (where", =
unity-gain bandwidth of op amp)
C5Min =
4_(1+R4)
R5
27/"R5,~ '"
R4 + R5
,7/" .
(R5)2
"2-"'-
For best results, choose the design center value of C5 to be
2 or 3 times C5 min.
1201
• r----------------------------------------------------------------------,
III
....
"
~'
,,'
Get More Power Out of
Dual or Quad Op-Amps
Nation!ll
Semiconductor
Linear Brief
44
Although simpie brute-force paralleling of op-amps is a bad
scheme for driving heavy loads, here is a good scheme for
dual op-amps. It is fairly efficient, and will not overheat if the
load is disconnected. It is not useful for driving active loads
or nonlinear loads, however.
In Figure 1, an LF353N mini-DIP can drive a 6000 load to
± 9V typical (± 6V min guaranteed) and will have only a
47"C temperature rise above free air. If the load R is removed, the chip temperature will rise to + 500C above free
air. Note that A2's task is to drive half of the load. A1 could
be applied as 'a unity-gain follower or inverter, or as a highgain or low-gain amplifier, integrator, etc.
While Figure 1 is suitable for sharing a load between 2 amplifiers, it is not suitable for 4 or more amplifiers, because
the circuit would tend to go out of control and overheat if the
load is disconnected.
Instead, Figure 2 is generally recommended, as it is capable of driving large output currents into resistive, reactive,
nonlinear, passive, or active loads., It is easily expandable to
use as many as 2 or 4 or 8 or 20 or more op-amps, for
driving heavier l o a d s . '
It operates, of course, on the principle that every op-amp
has to put out the same current as A1, whether that current
is plus, minus, or zero. Thus if the load is removed, all amplifiers will be unloaded together. A quad op-amp can drive
6000 to ± 11 or 12 volts. Two quads can put out ± 40 mA,
but they get only a little warm. A series R,C damper of 150
in series with 0.047 ""F is useful to prevent oscillations (although LM324's do not seem to need any R-C damper).
Of course, there, is no requirement for the main amplifier to
run only as a unity-gain amplifier. In the example shown, in
Figure 3, A1 amplifies a signal with a gain of + 10. A2 helps
it drive the load. Then A3 operates as unity-gain inverter to
provide V2 = -V1, and A4 helps it drive the load. This
circuit can drive a floating 20000 load to ±20V, accurately,
using a slow LM324 or a quick LF347.
10RI
lOOk
Bob Pease
RI
10k
VIII (±IV PEAKI"'_-~__
TL/H/8493-1
A1.A2
= 1/2 LM747 or 112 lF353oranyop-amp.
FIGURE 1. A 1 and A2 Share the Load
a
SENSE BUS
VINn-.....·~
TYPICAL
TYPICAL
=c>
R·CDAMPER
REPEAT
AS MANY
TIMES AS
NEEDED
= 1/4 LM324 or 1/4 LF347 or any op-amp.
TLlH/849S-2
FIGURE 2. Improved Load-stlarlng Circuit
1202
Rl
1"
R2
BOk
> ....___
56
..J\j""'~
_ _... Vl -IUVIN
5&
2Uk
1%
66
V2 - -1/1· -IOVIN
68
TUH/8493-3
FIGURE 3. Typical Application of Load-8harlng
1203
~
National Semiconductor
Linear Brief 45
~ Frequency-to-Voltage
Converter uses Sampleand-Hold to Improve
Response and Ripple
Most frequency-to~voltage (F-to-V) converters suffer from
the classical tradecff of ripple versus speed of response.
For example, the:basic F-to-V converter shown below has
13 mVp-p of ripple, and a rather slow O.S second settling
time, when CFILTER is 1 p.F.lf you-want less ripple than that,
the response time will be even slower. If you want quicker
response, it is easy to decrease CFILTER, but the rlpple'VliII
increase by tbe same factor.
"
The improved circuit in Figure 2 makes an end-run around
these compromises. A low-cOst sample-and-hold circuit
such as LF398 Can sample'the F-to-V's output at the peak
of its ripple, and hold it until the next cycle. The LF398 has
:falrly low output ripple (rms) but it does have some short
duration noise spikes and glitches which can be removed
easily with a simple output filter. The ripple at the output of
the active filter VS Is smaller than 1 mV peak, but the settling time for a step change of input frequency is only 60 ms,
or ten times quicker than the "basic" FVC with CFILTER =
1 p.F.
_----..---....
---4~IIV
10k
18k
10k
411,F
flN-f ~..-----~
FREIlUENCY INPUT
10 kHz FULL-SCALE
SQUARE WAVE OR
'UUETRAIN
YOUT
= fiN X (~)
(=~)
p-p
l2kil"
X (1.9V) X (1.1RMI
= ( _ I_)
X (1.9V)
RS (
x (I.IRMI
Rs
CFILTER
TUH/8494-1
FIGURE 1. Basic Frequency-Io-Voltage Convertar
r--4~--""--""---"--------"----~-----------------1~-----IW
10k
Ilk
V4
410,F
'="
fIN-IH~-~
LM331
~.ru'T
22k
FULL·
I
INPUT FREQUENCY
10 kHz FULL-SCALE
SQUARE WAVE OR
PULSES
VI
2ft
LF388
r9L-ro:-.r"'--"'--lr--rtr.~r:-..J
t
SCALE
VI
TI~F
'="
..----~w
t-~~--~~--------~~-------------------lOOk
~
_______________•______________
-J'~'
______________~'~'_____________________________J
OFFSET
ADjUST
F.TO·V CONVERTER
SAIIPLE AND HOLD
OPTIONAL ACTIVE FILTER
TLlH/8494-2
FIGURE 2. Improved F-Io-V Converter Using Sampleoand-Hold
1204
DETAILS OF OPERATION (Refer to Figure 3, Wavefon:ns)
When the. input frequency waveform has a negative-going
transition, pin 6 of the LM331 is driven momentarily lower
than the 13V threshold voltage at pin 7. This initiates a timing cycle controlled by the Rt and Ct at pin 5, and also
causes a transition from + 5V to OV at pin 3, (the normal
VFC logic output) which is usually left unused in F-to-V operation.
During the timing cycle (t = 1.1 x Rt x Ct = 75 /Ls, for the
example shown) a precision current source i = 1.9 V IRs
flows out of pin 1 of the LM331., and charges V1 up to a
value slightly higher than the average DC value of V1. At the
end of the timing cycle, V1 .stops charging up, and also V2
rises. The 10 kn pull-up resistor is coupled (through the 200
pF capacitor) to V3, and causes the LF398 to sample for
about 5 /Ls. Then the LF398 goes back into hold. This entire
operation is repeated at the same frequency as fiN. The
average voltage at V1 will be the same 10V full scale, according to the same formula of Figure 1. And the peak-topeak ripple can be computed as 65 mV peak, 130 mVp-p,
using the appropriate formula.
"N
::
Now, the input to the sample-and-hold at pin 3 may have a
10.000V average DC value, but the output will be at
10.065V, because the sample occurs at the peak value of
V1. Thus, to get an output with low offset, a 15 Mn resistor
is used to offset the V1 signal to a lower level. Trim the
offset adjust pot to get VOUT = 1Vat 1 kHz, and trim the
gain adjust pot to get VOUT = 1OV at 10kHz (the interaction is minor), as measured at V4, V5, or V6. The rms value
of the ripple at V4 is rather small, but the peak-to-peak ripple (spikes and glitches) may be excessive. A simple R-C
filter can provide a filtered output at V5; or a simple active
filter using an inexpensive LF351 , will give sub-millivolt
(peak) ripple at VB, with improved settling time and low output impedance.
This F-to-V converter will have a good linearity, better than
0.1 %, but only from 10kHz down to 500 Hz. Between
200 Hz and 20 Hz, VOUT is not very proportional to fiN. And
at 0 Hz, the output will be indeterminate, because the sample-and-hold will never samplel However, there are many Fto-V applications where a 20:1 frequency range is adequate.
lL-__
-!
.IV
VOIPlIIIOFLII3311
IOV----~
VPlN5
DV
VI
:::~
---=;;;;"""'------- - -__
-
-_ _
V2
.V-----'L_
V3
-.v
=r--r---......J~
.. "'''v. ____
~----:--,~+~--~---~~f..~~ZIO~.~V"'~
___
_ _ _- - - It
~
~
~~
ve8.13C1V
.
, fmV,.,
TUH/B494-3
FIGURE 3. Waveforms, Improved F·to·V Converter
1205
.
~r-----------------~--~------~------------------~~~--~--~~~
National Semiconductor ,..
Unear Brief 46
Robert A. 'Pease
~ AN,ew
Production
Techniqu~ for trim.mlng
Voltage Regulatpr8
Three-terminal adjustable voltage regulators such as the
LM31l and LM33(:.are becoming popular for making regulated supplies in instruments and. various other OEM applications. Because the regulated output voltage!s easily prog@mmed by two resistors, the designer can choose any
voltage in a wide range such as 1.2V to 37V. In a typical
example (FI{/IJf'9 1) the output voltage will be: ,
R2
VOUT = VREF ( R1
F~_VOUT
U.DV
Rl
124.'"
.).
+ 1 + R2 -lAD,!
H2
1.8,2••,"
, 28VDC
H3
LM1171LM317
500
OUTPUT ADJUST
(BLOCK
OIASRAM)
-
......,~...._ _~~_ VOUT
OUT
UV
TLlH/8495-2
FIGURE ~ Regulator with Small Adjustment Range
+ VREF
_ 1.25V
ADJ
Rl
VIN
124.1"
I
....._--....
+IADJ
RZ
H3
Uk
2.0&11'1"
.5%
In some designs, the engineering policy may frown on the
use of such trim pots, for one or more of the following reasons:
- Good trim pots are more expensive.
- Inexpensive trim pots may be drifty or unreliable.
- Any trim pot which can be adjusted can be
misadjusted, sooner or later.
To get a tighter accuracy on a regulated supply, while avoid, ing these disadvantages of trim pots, consider the scheme
in Ftguf'9 3.
RS
Uk
>5%
R2
TLlH/8495-1
FIGURE 1. Basic Regulator
In many applications, when R1 and R2 are inexpensive
± 1% film resistors, and the room temperature accuracy of
. the LM117 is better than ±3%, the OVerall accuracy of
± 5% will be acceptable. In other cases, a tighter tolerance
. such as ± 1% is required. Then a standard technique is to
make up part of R2 with a small trim pot, as in FIguf'92. The
effective range of R2 is 2.07k ± 10%, which is adequate to
bring VOUT to exactly 22.0V. (Note'that a 2000 rheOstat in
series with 1.96 kO ± 1 % would not necessarily give a
±5% trim range, because the end resistanca and wiper resistance could be as high as 100 or 200; and the maximum
value of an inexpensive 10% or 20% tolerance trimmer
might be as low as 1600 or 1600.)
R4
3.9.
.5"
±,,,
1.9111<
--
TLlH/8496-3
FIGURE 3. Regulator with Trlmmable Output Voltage
When first tested, VOUT will tend to be 4% to 6% higher
than the 22.0V target Then, while monitoring VOUT, snip out
. R3, R4, and/or R5 as appropriate to bring VOUT closer to
22:0V. This procadure will bring the tolerance inside ± 1 %:
-If VOUT is 23.08V or higher, cut out R3 (if lower,
don't cut It out).
- Then if VOUT is 22.47V or higher, cut out R4 (if lower, don't).
- Then if VOUT is 22.16V or higher, cut out R5 (if lower, don't).
The entire production distribution will be brought inside
22.0V ± 1%, with a cost of 3 inexpensive carbon resistors,
much lower than the cost of any pot. After the circuit is
properly trimmed, it is relatively immune to being misadjusted by a screwdriver. Of course, the resistors' carcasses
must be properly removed and disposed of, for full reliability
to be maintained.
An alternate scheme shown in Ftguf'94 has R6, R7, and R8
all shorted out initially with a stitch or jumper of wire. The '
1206
....
trim procedure is to open up a link to bring a resistor into
effect. The advantage of this circuit is that VOUT starts out
lowerthan the target value, and never exceeds that voltage
during trimming. In this scheme, note that a total "pot resistance" of 2150 is plenty for a 10% trim span, because the
minimum resistance is always below 10, and the maximum
resistance is always more than 2000-it can cover a much
wider range than a 2000 pot.
The circuit of Figure 5 shows a combination of these trims
which provides a new advantage, if a ± 2% max tolerance is
adequate. You may snip out R4, or link L1, or both, to accommodate the worst case tolerance, but in most cases,
the output will be within spec without doing any trim work at
all. This takes advantage of the fact that most ± 1 % resistors are well within ± Ya%, and most LM337's output voltage tolerances are between - %% and + 1%%, to cut the
average trim labor to a minimum. Note that L1 could be
made up of a 2.70 ± 10% resistor which may be easier to
handle than a piece of wire.
In theory, a 10% total tolerance can be reduced by a factor
of (2" - 1) when n binary-weighted trims are used. In practice, the factor 'Would be (1.8" - 1) if ±10% trim resistors
are used, or (1.9" - 1) if ±5% resistors are used. For n =
2, a 10% tolerance can be cut to 3.8% p-p or ±1.9%. For
n = 3, the spread will be 1.7% p-p or ±0.85%, and most
units will be inside ± 0.5%, perfectly adequate for many regulator applications.
National Semiconductor manufactures several families of
adjustable regulators including LM117, LM150, LM138,
LM117HV, LM137, and LM137HV, with output capabilities
from 0.5A to 5A and from 1.2V to 57V. For complete specifications and characteristics, refer to the appropriate data
sheet or the 1982 Linear Oatabook.
F"'-VOUT·22.0V
Rl
124±1%
R2
1.961< ±1%
R6
120±5%
R7
62 >5%
R4
Uk ±5%
..O;.;U;,;T...._ - - - YOUT' -14.0V ±2%
RI
33±5%
-If vour is lower than 20.90V, snip link 1 (if not, don't).
i!=
1 "F
TANTALUM
TLlH/8495-5
rl/H/8495-4
If IVourl is smaller than 13.75V, snip Ll and il will get bigger by 6%.
, Then H IVolJTl1s bigger than 14.20V, snip R4 and it will get smaller by 3%.
Thtm if Your is lower Ihan 21.55V, snip link 2 (H not, don'I).
FIGURE 5. Circuit Which Usually Needs No Trim
to Get VOUT Within ± 2% Tolerance
Thtm H Vour is lower than 21.82V, snip link 3 (if nol, don't).
FIGURE 4. Alternate Trim Scheme
1207
~
__
~
National Semiconductor
Linear Brief 47
Michael'Maida
High, VQltage, ,Adjustable "
~Power. ~upplie"
7,4."
HJGH
VPL:rAGE ADJUsTABLE POWER SUPPLIES
'''I'!
'
Th. floating·mode operation of adJustable three·termlnal
reguiators'lluch as the 'I..Ml17, family make them ,Ideal for
highlfoltage operation. The ,regulator, has no ground pin;
instead, all the quie8Q6nt current (about 5 mAl flows, to the
output terminal. Since the r~ulator 8E!8S only the Input-out·
put differential, its voltage rating - 40V .for. ,the ~ndard
LM1F series and 60V,~orthe high voltage LM1,17Hy,seri~s
"C':. will not ,be exceeded for outputs of hundreds of volts.
However, the ICmay I1rea~ down wh~n t~eoutputls short~
ed un~s special design approaches, are l,lset:l, to, prot8ct
agains~ it '"
,
,.1.
"
'.
.,'
Figure 1 shows how it's done. Zener'diode D1 ensures that
the LM317H sees only a 5V input-output differential ove~ the
entire range of output voltage from 1.2V to 160V. Since
high-voltage transistors by necessity have a low p, a DarIInl!iO':' is used to s~nd off the high voltage. The 2:ener im.
pedance Is low enough that no:bYpass capacitor is requjre,~
di~ly, at the LM317 input. (In fact, no capaCitor shqu/d bl'
used here if the circuit is to survive, an output shorjl)R3
limits short circuit current to 50 rnA The RC network on the
output improves transient response as does bypassing the
ADJUST pin, while R4 and 02 protect the ADJUST pin duro
ing shorts.
Since Q2 may dissipoate up to 5W normally' or lOW during a
short circuit, it should be well heat sunk. For higher output
currents substitute a pass device in a TO-3 or TO·220 pack·
age in place of the TO-1I02 NSD134 and reduce R3. Of
course, if the required output' current is less than 25 rnA, R3
can be increased to reduce the size of the heat sink needed.
VIN217DV~""'-----"-"
LM317H
OR LM317MP
ADJ
VOUT
OUT 1-~.....---~... 1.2V TO
16DV.25mA
R7
2.m
'&2
, '!'UIlF
OZ '
IN4801
R6
2Dk
5W
QI, 02: NSDI34 or similar
CI, C2: 1 ,.F, 2DDV MYLAR
CI
~1'.IlF
-
'Heat Sink
TL/HI7335-1
FIGURE 1. Basic High Voltage Regulator
1208
....
,-------------------------------------------------------------------------,
An :'improved approach is shown in Figure 2. Here an
LM329B S.9V zener reference has been stacked in series
with the LM317's internal reference. This both improves
tel'llperafurestability, Since the LM329B has a guaranteed
TC of' ± 20 ppm/'C, and Improves regulation, because more
loop gain is available from the LM317.
These techniques, can be extended for higher output voltages and/or currents by either using better high voltage
transistors or cascading or paralleling (with appropriate
emitter ballasting resistors) several transistors. The output
short circuit current, determined by R3, must be within Q2's
safe area of operation so that secondary breakdown cannot
occur.
VIN ~178V-4~----+-.,
LM317H
ORLM317MP
OUT ....t--...-
VOUT
..-+-IVTO
IBOV025 ..A
RI
AOJ
un
D2
lN4OO1
R5
~ LM329B
Uk
R7
2Dk
5W
CI
01, 02: NSD134 or similar
Cl, C2: 1 ,.F. 200V MYLAR
+,1.0,...
'Heat Sink
TLfHI7335-2
FIGURE 2. Precision High Voltage Regulator,
1209
~
~
~
~
r-------------------------------------------------------------------------,
~ Simp,le Voltmeter Monitors
National Semiconductor
Linear Brief 48
MiChael
MaidaI
,
TTLS..:.pplies
Using a National Semiconductor LMS914 bar/dot display
driver chip, a few resistors and some LEOs, a simple expanded-scale voltmeter is easily constructed. Furthermore,
it runs from the same single 5V ± 10% supply it monitors
and can provide TTL-compatible undervoltage and overvoltage warning signals.
The complete circuit is shown in Figure 1. Resistors R1 and
R2 attenuate Vee by a factor of three at the LMS914 signal
input, ensuring proper biasing of the IC with Vee as low as
4V. The IC's internal reference sets the voltage across the
series combination of RS, R4 and R5 at 1.25V, establishing
a reference load current of about 1 mA. This current is
joined by the small, constant current from the reference adjust pin (75 /LA, typ) and flows to ground through R6 and R7,
developing a voltage drop. Adjusting R6 varies this voltage
drop and, consequently, the voltage at pin 7, nominally,
1.BOSV (= 5.41V1S).
Pin 7 is connected to the top of the ,LMS914's intemal ten~,
step voltage divider (pin 6). The bottom of this divider (pin 4)
is connected to the center tap of potentiometer R4. By varying the pot setting this vOltage can be s~t to 1.47V
(= 4.41V1S) without siQl)ificantly affecting the potential',at
pin 7. The optional diode 01 protects against damaging the
IC by connecting the leads backwards.
In operation, the LMS914's ten internal voltage comparators
compare the signal 'input, Vee/S, to the reference voltage
on the divider, lighting each successive LED for every 100
mV increase in Vee above 4.5V., as shown. The LMS914
regulates the LED c\lrrents at 10 times the reference load
current, here about 10 mA, so external current-limiting resistors are not required. With pin 9 left open circuit, the
LMS914 functions in Dot mode (only one LED on at a time).
If desired, a Bar mode display could be obtained by connecting pin 9 to Vee, but the dot display seams more suitable in this application.
To calibrate, set Vci:, at 5.41V and adjust R6 until LED #9
and LED #10 are equally illuminated. (A built-in overlap of
about 1 mV ensures all LEOs won't go out at a threshold
point.) There's no need to vary the system supply voltage to
perform this adjustment. Instead, disconnect R1 from Vee
and connect it, to an accurate reference. Then, at 4.5V, adjust R4 until LED # 1 just barely turns on. There is a slight
interaction caused by the finite resistance (10k, typ) of the
LMS914~s voltage divider, so that repeating the above procedure 'once is advised.
LM3914
SIGNAL
INPUT
01
lN4IIDI
5v±~Bi"'''-------''''''
AI
21Nt
VccM
4.51-4.60
4.61·4.70
4.71-480
4.81-4.90
4,91-5.00
5.01-5.10
5.11-5.20
5.21·5.30
5.31-5.40
5.41-up
LED
lIIumlnaled
#1
A2
#2
10k
#3
#4
#5
#6
#7
#8
All fixed resistors are ± 1 % tolerance
#9
All potentiometers are ± 20%
#10
Cl: 2.2 ",F tantalum or 10 ",F aluminum electrolytic
FIGURE 1. 5V Power Supply Monitor
1210
R5
825
TUH/8496-1
...
The LED driver outputs can directly drive a TTL gate, so that
the LED #1. and LED #10 outputs may be used for undervoltage and overvoltage warning signals. These may be
used to initiate a soft shutdown or summon an operator, for
example. The interfacing circuitry is shown in Rgure 2. The
4700 resistor R8 ensures that the LM3914 output will saturate to provide the proper TTL low level. Pull-up resistor R9
provides the logic high level.
In the previous circuit the undervoltage LED goes out when.
Vee is less than 4.51V, a deficiency that is corrected here,
Transistors 01 and 02 shut off LED # 1 whenever any other
LED is tumed on by the LM3914. 02's output will directly
drive TTL
Calibration procedure is the same as before. The LM3914
output thresholds have been shifted up by 100 mV and output #10 is or-tied with output #9. Other outputs may be
wire-or'd together if 100 mV resolution is not necessary. If
desired, the outputs can be color coded by making LED # 1
and LED #10 red, LED #2 and LED #9 amber, and the
rest of the LEDs green to ease interpretation.
This circuit is useful where quick and easy voltage adjustments must be made, such as in the field or on the production line. The circuit's low cost makes it feasible to incorporate it into the system, where the overvoltage and undervoltage warning signals provide an attractive extra. Of course,
these techniques can be used to monitor any higher voltages, positive or negative.
5v~i'---~~-'--~-'-------------------------------------'
HIUHFOR
UNOERVOlTAGE ..........
TO LOGIC
RI4
150
#1'
'LED
*'
HIGH FOR
OVERVOlTAGE
'N
Is illuminated for 3V ,; Vee ,; 4.5W
01: 2N3906, 2N2907 or similar
02: 2N3904, 2N2222 or similar
TL/H/8496-2
FIGURE 2_ Power Supply Monitor with TTL Interface and Extended Undervoltage Range
1211
~
_
~
~ Programmable
National Semiconductor "
Linear Brief 49
Robert Pease
Powe.r
Regulators Help CheckOLJt
ComputerSystem
.,
Operating Margins
It is a familiar situation that 'some computer systems which
are functional with a 5V supply may run marginally at 5.1V
but can show a solid failure at '5.3V (or, vice versa) even
thCiugh all these voltages are within the system's'specifications. The lM338 is an exarnple of a monolithic voltage regulator which can be placed under computer control, and can
trim the supply to a particular v~ation above (and, below)
the design-center voltage. Simultaneously the computer is
exercised through a standard test sequence. Any deviation
from correct functioning, at one supply voltage level or another, will serve as a warning of impending rIlalfunction or
failure. This test approach can be used for diagnostics" for
troubleshooting, and for engineering evaluation. It can help
detect skew, race conditions, timing problems, and noise
and threshold problems.
The same basic function can be accomplished for -5.2V
regulators (as are used for ECl) using lM337 negative adjustable regulators. If the command is from TTL latches, the
circuit of Ftgure 2 will be suitable to interface between the
(OV and 2.4V) logic levels and the saturated PNP collectors
"
,
as shown. The resistors Rl0l-Rl04 are switched by transistors 0101-0104 in a similar way toFigure 1; Note that
the reSistors in Figure 2 are in 'Ii binarY-weighted proportion.
To decrease VOUT by 2%', just change Q4 to LOw' but to
increase VOUT by 2%, set 01 HIGH and 02, 03, 04 all
LOW, in a standard offset binary scheme.
TABLE I. Available Trim Ranile
01
02
03
04
,VOUT
%~VOUT
1
1
0
0
5.000V
(trimmed)
,1
1
0
1,
5.151V
+3.0%
1
1
1
0
5.299V
+6.0%
1
1
1
1
,5.469V
+9.4%
0
1
0
0
4.835V
-3.3%
1
0
0
0
4.669V
-6.6%
0
0
0
0
4.526V
-9.5%
HERE'S HOW
During normal operation, the latch (IC 1) is programmed to
have its 01 and 02 outputs HIGH, and its 03 and Q4 LOW
Then R4 and R5 are connected effectively in parallel with
R6, and VOUT is adjustec:Uo 5Vdf Q4 is commanded HIGH,
the net conductance from the adjust bus to ground will decrease, and VOUTwili rise 3% to 5.151V. COnversely'ifOl ill
commanded LOW, the output voltage will fall 3.3% to
4.835V. The complete list of o!Jtput voltages (in approximately 3.2% steps) is shown in Table I, covering a ±9.5%
total range.
'
,
'",
mI
,
,
Rgure 2 also provides another feature. If 05 goes LOW,
0105 will saturate and pull the adjust bus to within 100 mV
of ground, and the VOUT will collapse to -135V. The negative supply will be effectively shut down, and the computer
will draw substantially zero power.
In an extreme case of automation, the computer could trim
the - 5.2V supply to the "best" value, and the trimpot would
be completely superfluous. The circuit of Figure 2 has a trim
resolution of 3% steps, and can set VOUT well within 2% of
the ideal value, so long as some measurement has decided
which voltage is "ideal".
I voc NOMINAL
INPUT
ADDRESS IUS
VOUTPUT
&.DVoc
NOMINAL
ENABLE 5,DV
Vec
Rl
Uk
Uk
12k
124
.1"
Uk
R2
18k
PI ~~~-+--~--+-~~~~A~OJ~UU~
BUS
R3
02
~[02 ~____""'__-I-__.....~4\J.7k~. .
LATCH
DM747&
OR SIMILAR
R4
Uk
....
03· .....- - - - - - - -....--+~~
RI
R5
04
DATA
BUS
12k
346
± 1%
04*I-------------...~~~_~II,,-.,
PI
10D
'Note, Q3 and 04 Bre normally low
when VOUT is trimmed to 5.00 VOC.
FIGURE 1. Programmable Power Supply
1212
TL/H/7336-1
....
~
~
(
,
fUlLE
.,
".
.1"
OJ
-
-UVue
:1
1M
DO
mHTCH
DO
... ...
...
~
,>
DATA IUS
U.
I ••
~II' ~,a ~'D ~'M ~.,.n
~
...
...
.
'"~
. .'"....,. ....'D ..,"'"
iLl ~T""
~
..,'"
:Ill
• '11
-
....m.us
aUT
,,1
~~
I.
-ftVac IIOMIfIAL
",
.",
;.
•
...
HZ
u•
.,
'"u.
'01 Is normally LOW, all other a's are HIGH.
See Table II for available trim range.
tIIIF.DM
RECTIfiERS AID .ILnRl
TUHI7338-2
FIGURE 2. Programmable Negative Supply
TABLE II. Available Trim Range
Q1
Q2
Q3
Q4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1213
YOUT
5.200V
5.110V
5.025V
4.944V
4.853V
4.779V
4.707V
4.638V
5.310V
5.409V
5.513V
5.622V
5.757V
5.880V
6.010V
6.147V
%~YOUT
(trimmed)
-1.7%
-3.4%
-4.9%
-6.7%
-8.1%
-9.5%
-10.8%
+2.1%
+4.0%
+6.0%
+8.1%
+10.7%
+13.1%
+15.6%
+18.2%
;
:National Semiconductor
Line,'d3riEif 51 '
Add Kelvin Sensing ,and', '
Parallel Capability to
3·Terminal Regulators' '
Paralleling of 3-terminal regulators is generallY nofrecomthr0'th a,:pOl'!n8ctor. Total cost of added components is
mended because the devices do hot share currEl(lt' equally. , less an'Sq¢.'
F/{/UfB 1 shows the new Kelvin sense scheme using the
If, for instance, you try to make.a 3 'amp, regulator using
three 1 amp regulators, the device with the highest oU,tptit
I.,M338 S amp adjustable regulator. A 1 forces a voltage drop
could be carrying 2.S amps in a current limit mode. The, across RS eqUal tQ'the voltage across the parasitic resist- ;
regulator with the second highe,st output would be carrying ,lince, rs' The Current through R3 flows into the output of A 1
only 0.5 amps, and the third regulator would be totally off.
and out'ilie n~gative supply pin. This creates a voltage drop
The reliability of such a system is poor ,be~Us6 of the comacross R4, just equal to the voltage across r s, cancelling the
effect of s' on load regulation. There is an error in VOUT
bination of high temperature and high current in the first
regulator. A simple way to improve sharing is tq insert a,low • created by the quiescent current of A 1, but for a SV output,
value resistor in series with each output. The problem With , this error iii only about 0.7%. Voltage loss across rs must be
this approach is that Jpad, regulati,on is very ppor if .the tesis- > limit~d to 300 mV to avoid current limiting in A 1. If larger
tors are made large enough to ensure adequate sharing:
drops must be aceommodated, R3 and R4 will have to be
increased. C1 is:'necessary only if intermediate values of
A new techniqUe for current sharing overcomes the load
regulation problem and, as an added bonus, prol(ililes rEI;,
cap~tance (2 I-IF~20 p.F) are put directly across the load.
mote sensing capability not available in the standard 3-terAny of the positive adjustable regulators may be used in
minal regulators. This is a great advantage when ,the regula.., , ,'place of tI1& 'LM338.
tors must be mounted off-card with their outpul$' fed, '
r
'.*
~~------------~~----------~~+VOUT·&~
•
PARASlTI~ LINE AND
CONNECTOR RESIITANCE
.!LCI
R4
30
L __ ..._ _ _ _'"
hF
-r
I
.... -vOUT
-VIN-----------------------------------~
FIGURE 1
12141
TL/H/8498-1
....
r-------------------------------------------------------------------------,r
Figure 2 combines Kelvin sensing with paralleling, where
the voltage loss across the current sharing resistors is corrected by the sensing connection. rsl through rs3 are equal
lengths of #22 gauge lead wire which act as ballasting resistors. These resistors can be kept small because LM338
adjustment pins are paralleled, forcing the outputs to track
to within about 60 mY. rs4 consists of the parasitic resistance of any additional output lead plus connector loss. The
total loss for rs4 may be up to 0.25V without loss of proper
Kelvin sensing. Note tliat if U1 has the lowest reference
voltage of the three regulators, full Kelvin sensing might not
become effective until output current has increased above a
threshold value of several amps. If this is undesirable, the
adjustment pin of U1 may be connected to a 50 tap on R1,
increasing its effective reference voltage by 50 mY. The current load for U1 would be 1.5 amps higher, however.
r53*
0.03
*2FEETOF
"22 HOOKUP
WIRE
r12*
0.03
-+-::-....
+VIN-...
r,4
1I~.;....,...jV\l""""--~---~Mr_-_::=__- +VOUTI' 15 AMPS
VIN L---,r----'
RI
120
RJ
40
I
..!L-CI
2pF
I
--r-
L. ____ ...._ _ ___...
-VIN-------------------------.....;=It--VOUT
TL/H/8498-2
FIGURE 2
1215
~
.....
....
OpAmp
'~
National Semiconductor '
Linear Brief 52
Robert A. Pease
A, Low-Noise PreCi$ioo'
t.'
,
,
'.
.::"
'
""
posite op "amp, Ib1-lb2, will be very small, 1 nA or 2 nA.
Thus, errors caused by bias current and offset current drift
vs: temperature can be quite small, less than 0.1 p.V1°C at rs
= 1000fi.
•
It Is well known that the voltage noIse of an operational
amplifier can be decreased by increasing the emitter current
of the input stage. The signal-to-noise ratio will be improved
by the increase of bias, until the base current noise begins
to dominate. The optimum is found at:
The noise of 01A and 01B would norrnally be quite significant, about 6 nV/.JHz, but the 10 p.F capacitors completely
la(optimum) =
filter out the noise. At all frequencies above 10Hz, Q2A and
q
rs
02B act as the input transistors, while 01 A and 01 B merely
where rs is the output resistance of the signal source. For
buffe~ the lowest frequency and.DP signals.
example, in the circuit of Figure 1, when rs = 1 kfi'·and
For audio frequencies (20 Hz to 20 kHz) the voltage noise of
hFE = 500, the la optimum Is about 500 p.A or 560· p.A.
this amplifier is predicted to be 1.4 nV/.JHz, which is quite
However, at this rich current level, the DC base current will
small compared to the Johnson noise of the 1 kfi source,
cause a significant voltage error in the base resistance; and
4.0 nV/.JHz. A noise figure of 0.7 dB is thus predicted, and
even after cancellation, the DC drift will be significantly bighas been measured and confirmed. Note that for best DC
ger than when la is smaller. In this example, Ib = 1 p.A, so
balance R6 ='. ,976fi is added into the feedback path, so
Ib x rs = 1 mV. Even if the'lb and rs are well matched at
that the total impedance seen by the op amp at its negative
each input, it is not reasonable to expect the Ib x rs to track
input is 1kfi. But the 976fi is heavily bypassed, and the
better than 5 or 10 P.VI"C versus temperature.
total Jphnson noise contributed by the feedback network is
A new amplifier, shown in Figure 2, operates one transistor
below % nV/.JHz.
pair at a rich current, for low noise, and a second pair at a
much leaner current, for low base current. Although this ,.. To achieve lowest drift, below 0.1 p.V/oC, R1 and R2
shciuld; of course, be chosen to have good tracking tempco,
looks like the familiar Darlington connection, capacitors are
below 5 ppm/oC, and so should R3 and R4. When this is
added so that the noise will be very low, and the DC drift is
done, fhe drift referred to input will be well below 0.5 p.V1°C,
very good, too. In the example of Figure 2, 02 runs at
and this has been confirmed, in the range + 10"C to + 50"C.
la = 500 p.A and has very low noise. Each half of 01 is
operated at 11 p.A = Ie. It will have a low base currQnt
Overall, we have designed a low-noise op amp which can
(20 nA to 40 nA typical), and the offset current of the com- . rival the noise of the best audio amplifiers, and at the same
KT>"iiFE
--
Your
t' ....
I
I
I
.........
.... ,
I
I
..........
.........
I
..........
......... ....
......................
....
SIGNAL
SOURCE
rUH/8499-1
VOUT .. (n
+ 1) VIN + Ves x
(n
+ 1) + (1b2 -
Ibll x r. x (n
+ 1) + Vn_
X (n
+ 1) + in_ X (r. + RINl
FIGURE 1. ConventIonal Low-NoIse OperatIonal Amplifier
1216
X (n
+ 1)
time exhibits drift characteristics of the best low-drift amplifi,
ers. The amplifier has been used as a precision. pre-amp
(gain = 1000). and also as the output amplifier for a 20-bit
!;lAC. where low drift and low noise are both important.
Various formulae for noise:
to optimize the circuit for other r s levels. the emitter current
for 02 should be proportional to 1/.fr;. The emitter current
of 01A should be about ten times the base current of 02A.
The base current of the output op amp should be no niore
than 1/1000 of the emitter current of 02. The values of R 1
and R2 should be the same as R7.
Current noise of a transistor. per .'Hz. in =
Voltage noise of a transistor. per .'Hz. en = KT
.
.
{21
\fQiC
.J!
Voltage noise of a resistor. per .'Hz. en = ~4 KTRs
For a more coniplete analYSis of low-noise amplifiers. see
AN-222. "Super Matched Bipolar Transistor Pair Sets New
Standards for Drift and Noise". Carl T. Nelson.
OFFSET
ADJUST
1 5 V - t - - - -........-
...- - -....- -....- . . ,
zoo
zoo
±1%
±t"
lOOpF
>--+--VOUT
HF
10.OK
±1%
r,
1k
HI.
10.0
±t%
'Tracking TC < 5 ppml'C
"Solid tantalum
'''Tracking TC < 5 ppml'C,
Beckman 694·3·Rl00K·D or Similar
1.2M
5%
H7
15k
1%
' - - - -...--15V
FIGURE 2. New Low-Noise Precision Operational Amplifier as Galn-of-1000 Pre-Amp
1217
TUH/8499-2
~ r-----~--------------------------------------------------------------------~
~ p,P Interface for a
National Semiconductor
Linear Brief 53
Ti'm Regan
Free-Running AID Allows
Asynchronous Reads
In many data acquisition applications it is necessary to have
an A' to D converter operate as its maximum conversion
rate. The coritrolling 'microprocessor would then be able to
read the most current input data' at any point in time as
required by software. To minimize program execution time,
a DATA READ may not be snychronous to the completion
of a conversion, and herein lies a problem. It is jilntirely possible that the processor could assert a READ command
right at the instant the AID converter is updating its output
register. The data read would be the value of the converter's output lines in transition from the result of the previous
conversion to the latest result, and would very likely be in
error.
The addition of a simple binary counter to the AID interlace
circuitry can be used to generate a READY signal to the
microprocessor that will prevent a READ during a data update. The circuit of Figure 1 shows a CD4024BC7-stage ripple carry binary counter used in conjunction with an
ADC0801, 8-bit microprocessor competible A to D converter. Circuit operation relies on two basic properties of the
AID converter. First of all, the free-running conversion time
of the AID must be a constant number of clock cycles; and
secondly, the output latches must be updated prior to the
end of conversion signal. The ADC0801 fulfills both of these
requirements. The output data latches are updated one AID
clock period before the ~ falls low, and the free-running
conversion time is always 72 clock periods long.
As part of the system power-up initializaton sequence, a
logic low must be temporarily applied to the ~
~ input to the AID to force the converter to start. At
the end of a conversion, the ~ output goes low, and
both resets the counter outputs to all zeros and signals another conversion to start by pulling WR low. The length of
,time that the iNTR output stays low is normally only a few
internal gate propagation delays (approximately 300 ns) and
is independent of the AID clock frequency. The 1000 pF
capaCitor on this output extends this time to approximately
1 p.s to insure adequate reset time for the counter.
A conversion is started on the low to high transition of the
'i'IiI'm" and WR pins. The next data update will occur 71 clock
periods after this edge occurs. The counter will signal that a
data update is about to occur after 64 clock periods. If the
processor attempts a DATA READ within an 8 clock period
time frame around the data update time, its READY input
line will remain low, signifying a NOT READY condition. The
processor would then extend the READ cycle time until it
receives a READY indication created by the counter being
reset by iliiiR. This insures that the latches have already
been updated and proper data will be read.
If a READ is attempted during the 64 clock period interval
after the start of a conversion, the READY IN line to the
processor will go high to permit a normal READ cycle, and
sv
20
(+) 6
H
ANALOG
INPUT
7
sv
L
ClKOUT 19
14
>
C04024ac
RESET
ADcoaOI
2
vo,
3
":"
ClKIN
ISOh:
PROCESSOR
READY IN
TIming Diagram
INTR~
READY OUT
SIGNALS FROM
OTHER SYSTEM
PERIPHERALS
vo,~
AID READY OUT
OUTPUTLATCH/
NOT READY UPDATEO
n
I
TUH/8500-1
L.
' - - - DATA READ AT
THISTIME
A READ IS ATTEMPTED
aUT IS EXT~g~~R~~~~ ___- - - -
TUH/8500-2
FIGURE 1
1218
· th8 data outPut by the AID will be the result of ·the previous
oonvei'sion. The processor READY IN logic, as shown, reo
quires,:that all system devices that may need special READ
Qf WRITE'timing provide a NOT READY (a Logic 0 on their
READY OOT lines) indication until selected to be read from
or written to.
The chancE! of having the p~ocessor·extend its READ cycle
time is 1 in' 9 (8 clock periods out of 72) and the maximum
length.of time a READ would be extended is 8 AID clock
periods. These two timing considerations are insignificant
trade-offs to take to insure that proper AID data is always
read.
1219
..
"~
.
National Semiconductor
Appendix A
The Monolithic' Operational
Amplifier: A Tutorial Study
.
.'
Invited PaperIEEE Joumal of Solid-State Circuits, Vol. SC-9, No. 6
Abstract-A study is made of the integrated circuit operational amplifier (lC op amp) to explain details of its behavior
in a simplified and understandable manner. Included are
analyses of thermal feedback effects on gain, basic relationships for bandwidth and slew rate, and a discussion of polesplitting frequency compensation. Sources of second-order
bandlimiting in the amplifier are also identified and some
approaches to speed and bandwidth improvement are developed. Brief sections are included on new JFET-bipolar
circuitry and die area reduction techniques using transconductance reduction.
1.0 INTRODUCTION
The integrated circuit operational amplifier (IC op amp) is
the most widely used of all linear circuits in production today. Over one hundred million of the devices will be sold in
1974 alone, and production costs are falling low enough so
that op amps find applications in virtually every analog area.
Despite this wide usage, however, many of the basic performance characteristics of the op amp are poorly understood.
.
It is the intent of this study to develop an understanding for
op amp behavior in as direct and intuitive a manner as possible. This is done by using a variety of simplified circuit
models which can be analyzed in some cases by inspection,
or in others by writing just a few equations. These simplified
models are generally developed from the single representative op amp configuration shown in F/{Jures 1 and 2.
The rationale for starting with the particular circuit of Figure
1 is based on the following: this circuit contains, in simplified
form, all of the important elements of the most commonly
used Integrated op amps. It consists essentially of two voltage gain stages, an input differential amp and a common
emitter second stage, followed by a class-AB output emitter
follower which provides low impedance drive to the load.
The two interstages are frequency compensated by a single
small "pole-splitting" capaCitor (see below) which is usually
included on the op amp chip. In most respects this circuit is
directly equivalent to the general purpose LM101 [11, !lA
741 [21, and the newer dual and quad op amps [31, so the
results of our study relate directly to these devices. Even for
r -__________________
~----~--<>V~
+0-----+----,
VOUT
+
I
"*"
L----~------~--~--~~~JVEE
I
I
CLASS A8~
~ INPUTSTAGE--2NDSTAGE--OUTPUT
BUFFER
TLlHI8745-1
FIGURE 1. Basic two-stage IC op amp used for study. Minimal
modifications used In actuallC are shown in FIgure 2.
1220
.---------------------------------------------------------~~
'a
CD
:::J
a.
>e.
~
-I
::r
CD
i:
o:::J
2-
VOUT
;::;:
::::r
(S.
!6
CD
a
o·
:::J
TL/H/B745-3
(b)
TLlH/B745-2
Av(O) = voU! "" gml/35/3sf37~L
vin
1 + ri2/ rOl
»
3
"S!.
::::;;
(a)
FIGURE 2. (a) Modified current mirror used to reduce dc offset caused by base currents in
Q3 and Q4 in Figure 1. (b) Darlington p-n-p output stage needed to minimize gain fall-off when sinking large
output currents. This is needed to offset the rapid /3 drop which occurs in IC p-n-p's.
more exotic deSigns, such as wide-band amps using feedforward [4], [5], or the new FET input circuits [6], the basic
analysis approaches still apply, and performance details
can be accurately predicted. It has also been found that a
good understanding of the limitations of the circuit in Figure
1 provides a reasonable starting point from which higher
performance amplifiers can be developed.
The study begins in Section 2, with an analysis of dc and
low frequency gain. It is shown that the gain is typically limited by thermal feedback rather than electrical characteristics. A highly simplified thermal analysis is made, resulting in
a gain· equation containing only the maximum output current
of the op amp and a thermal feedback constant.
e.
Ci·
:!
»
(1)
where
-I
c
S"
~.
!!.
rOl' "" r04//r02'
It has been assumed that
/37RL < rOS//r09, gml = gm2, /37 = /3a·
The numerical subscripts relate parameters to transistor a
numbers (i.e., r95 is r9 of a5, /3s is /30 pf as, etc.). It has also
been assumed that the current mirror transistors a3 and a4
have a's of unity, and the usually small loading of Rs has
been ignored. Despite the several assumptions made in obtaining th'is" simple form for (1), its acicuracy is quite adequate for our needs.
An examination of (1) confirms the ;"'ay in which the amplifier operates: the input pair and current mirror convert the
input volt.agE! to a current gml Vin which drives the base of
the second stage. Transistors a5, a6, and a7 Simply multiply this current by /33 and supply it to the load RL. The linitll
output resistance of the first stage causes some loss when
compared with second stage input reSistance, as indicated
by the term 1/(1 + ri2/rOl'). A numerical example will help
our perspective: for the LM101A,Il "" 10 ",A, 12 "" 300 ",A,
/35 = /3s "" 150, and /37 "" 50. From (1) and dc voltage
gain with RL = 2 kO is
The next' three seations apply first-order models to the calculation ·of small-signal high frequency and large-signal
slewing characteristics. Results ·obtained include an accurate equation for gain-bandwidth product, a general expression for slew rate, some important relationships between slew
nite and bandwidth, and a solution for voltage follower behavior in a slewing mode. Due to the Simplicity of the results
in these sections, they are very useful to designers in the
development of new amplifier circuits.
Section 6 applies more accurate models to the calculation
of important second-order effects. An effort is made in this
section to isolate all of the major contributors to bandlimiting
in the modern amp.
In the final section, some techniques for reduction of op
amp die size are considered. Transconductance reduction
and layout techniques are discussed which lead to fabrica.
tion of an extremely compact op amp cell. An example yielding 8000 possible op amps per 3-in. wafer is given.
Av(O) "" 625,000
(2)
The number predicted by (2) agrees well with that measured
on a discrete breadboard of the LMl 01 A. but is much higher
than that observed on the integrated circuit. The reason for
this is explained in the next section.
2.0 GAIN AT DC AND LOW FREQUENCIES
B. Thermal Feedback Effects on Gain
A. The Electronic Gain
The electronic voltage gain will first be calculated at dc using the circuit of Figure 1. This calculation becomes straightforward if we employ the simplified transistor mOdel shown
in Figure 3(8). The resulting gain from Figure 3(b) is
The typicallC op amp is capable of delivering powers of 50100
to a load. In the process of delivering this power,
the output stage of the amp internally dissipates similar
power levels, which causes the temperature of the IC chip
to rise in proportion to the output diSSipated power. The
silicon chip and the package to which it is bonded are good
thermal conductors, so the whole chip tends to rise to the
same temperature as the output stage. Despite this, small
mW
1221
gz
c
CI.
'<
Tl/H/8745-4
'0 ..
2OO/IC MONOLITHIC NPN
'0 .. 801IC MONOLITHIC PNP
(a)
V,
'"L'
Tl/H/8745-~
(b)
FI,GURE 3. (a) Approximate 'IT moctel for CE trans,lstor at dc. Feedback element r,. "" /34ro Is Ignored since this greltly
simplifies hand ,calculations. The error caused Is usually less than 10 percent because /34, the Intrinsic /3 under the
emltter,ls quite large. Base resistanCe rx Is also Ignored for simplicity. (b) Circuit Illustrating calculaJJon of electronic
gain for op amp of Figure 1. Consideration Is given only to the fully loaded condition (RL "" 2 kO) where /37 Is failing (to
about 50) due to high current denslt)'. Under thl~ condition, the output reslltance of 06 and Q9 are nondomlnal!t.
temperature gradients from a few tenths to a few degrees
centigrade develop across the chip with the output section
being hotter than the rest. As Illustrated in Figure 4,these
temperature gradients appear across the input components
of the op amp and induce an input voltage which is proportional to the output dissipated pow~r.
Vin! ",,' ±KTPd(2 x, 10- 3)
"" ± 'YTPd
(4)
where'YT = KT(2 X 10-,3) V/W, since the transistor emit.
ter·base drops change about -2 mV/·C. '
For a thermally well designed IC op amp, in which the power
output devices are made to approximate either a point or
line source and the input components are placed on the
resulting isothermal lines (see below and Fl{JUre 8), typical
values measured for KT are
KT:::: O.3"C/W
(5)
a
To a first order, if can be assumed that the temperature
difference (T2 - T1) across a pair of matChed and closely
spaced components is given simply by
(T2 - T1) "" ±KTPd ·C
(3)
where
a
in TO-5 package.
The dissipated power in the class-AB output ~tage Pd is
written by inspection of ~igu'!14: ' ,
' ,
Pd , power dissipated in' the output circuit, ,
Kl a constant with dimensions of ·C/W.
The plus/minus sign is needed because the direction of the
thermal gradient is unknown. In fact, the sign may r~ve~
polarity during the output swing as the dominant source of
heat shifts from one transistor tb another. If the dominant
input components consist cif the differential transistor pair of
Figure 4, the thermally induced input voltage Yin! can be
cal,culated as
"
P _ VoVs - V02
d-
Ri
,(6)
where
,Vs= +Vcc whenVO> 0
Vs = -Vee when Va < O. '
A plot of' (6) is Figure 5 resembles the weli,known CIQs-AB
dissipation characteristics, with zero dissipation ocCurring
1222
+Vcc
-1
-VEE
HEAT
TEMPERATURE GRADIENT
TLlH/8745-6
FIGURE 4. Simple model illustrating thermal feedback in an Ie op amp having a single dominant source of self-heat, the
output stage. The constant 'YT "" 0.6 mV/W and Pd is power dissipated in the output. For simplicity, we Ignore Input
drift due to uniform heating of the package. This effect can be significant if the Input stage drift is not low, see [7).
-VEE
OUTPUT STAGE
---L----------------------~--------------------~--~VD
- Vee
TLlH/8745-7
FIGURE 5. Simple class-B output stage and plot·of power dissipated in the stage, Pd, assuming device
can swing to the power supplies. Equation (6) gives an expression for the plot.
for Va = 0, + Vee, -Vee. Dissipation peaks occur for Va =
+ Vcc/2 and - Vee/2. Note also from (4) that the thermally
induced input voltage Vinl has this same double-humped
shape since it is just equal to a constant times Pd at dc.
Now examine Figures 6(a) and (b) which are curves of
open-loop Va versus Vin for the Ie op amp. Note first that
the overall curve can be visualized to be made up of two
components: a) a normal straight line electrical gain curve
of the sort expected from (1) and b) a double-humped curve
similar to that of Figure 5. Further, note that the gain characteristic has either positive or negative slope depending on
the value of output voltage. This means that the thermal
feedback causes the open-loop gain of the feedback amplifier to change phase by 180", apparently causing negative
feedback to become positive feedback. If this is really true,
the question arises: which input should be used as the inverting one for feedback? Further, is there any way to close
the amplifier and be sure it will not find an unstable operating point and latch to one of the power supplies?
. The answers to these questions can be found by studying a
simple model of the op amp under closed-loop conditions,
including the effects of thermal coupling. As shown in Figure
7, the thermal coupling can be visualized as just an additional feedback path which acts in parallel w~h the normal electrical feedback. Noting that the electrical form of the thermal
feedback factor is [see (4) and (6»)
Ih =
aYin!
aVo
=
'YT
± RL (Vs
- 2VO)·
(7)
The closed-loop gain, including thermal feedback is
A (0)-
V
1223
- 1
P.
+ p.(fie ± fiT)
(8)
Yo
t
I
I
I
I
I
I-EUCTRICAL
I
I
I
\',
'
-------.. . .
~=------------VIN
I
SUM OF THERMAL
• ELECTRICAL
--..
I
,
,
I
I
I
I
\ I
\ I
j .
' ......
TL/H/8745-8
(a)
---I--+--t--i--+--YIN
llX\uV
,TLlH/8745-9
(b)
FIGURE 6. (a) Idealized dc transfer curve for an Ie op amp showing ,ta electrical and thermal components.
(b) Experimental open-loop transfer curve for a representative op amp (LM101). , ' ,t"
..'
,"
1224
.'~
'j,
>--.....--0 va
±
TUH/8745-10
FIGURE 7. Diagram used to calculate closed-loop gain with thermal feedback.
where p. is the open-loop gain in the absence of thermal
feedback [(1)) and f3e is the applied electrical feedback as
in Figure 7. Inspection of (8) confirms that as long as there
is sufficient electrical feedback to swamp the thermal feedback (i.e., f3e > f3T), the amplifier will behave as a normal
closed-loop device with characteristics determined principally by the electrical feedback (i.e., Av(O) '" 1I f3 e). On the
other hand, if f3e is small or nonexistant, the thermal term in
(8) may dominate, giving an apparent open-loop gain characteristic determined by the thermal feedback factor f3T.
Letting f3e = 0 and combining (7) and (8), Av(O) becomes
load resistor is used. For loads of 6 kO or more, the electrical characteristics should begin to dominate if thermal feedback from sources other than the output stage is negligible.
It should be noted also that, in some high speed, high drain
op amps, thermal feedback from the second stage dominates when there is no load.
As a second example, consider the so-called "power op
amp" or high gain audio amp which suffers from the same
thermal limitations just discussed. For a device which can
deliver 1W into a 160 load, the peak output current and
voltage are 350 mA and 5.7V. Typically, a supply voltage of
about 16V is needed to allow for the swing loss in the IC
output stage.lmax is then 8V/160 or 0.5A. If the device is in
a TO-5 package "YT is approximately 0.6 mV/W, so from
(11) the maximum usable dc gain is
Av(O) =
p.
.
(9)
1 ± WYT f'ls - 2Vo)
RL
Recalling from (6) that Vo ranges between 0 and Vs, we
note that the incremental thermal feedback is greatest when
Vo = 0 or Vs, and it is at these pOints that the thermally
limited gain is smallest. To use the amplifier in a predictable
manner, one must always apply enough electrical feedback
to reduce the gain below this minimum thermal gain. Thus, a
maximum usable gain can be defined as that approximately
equal to the value of (9) with Vo = 0 or Vs which is
I
RL
AV(O) max .. - V
"l'Ts
1
Av(O)lmax "" (0.6 x 10 3)(0.5) "" 3300.
(13)
This is quite low compared with electrical gains of, say,
100,000 which are easily obtainable. The situation can be
improved considerably by using a large die to separate the
power devices from the inputs and carefully placing the inputs on constant temperature (isothermal) lines as illustrated in Figure 8. If one also uses a power package with a
,--_-.!££':!!!.-_--,
(10)
Ix
or
1
(11)
Av(O)lmax "" - 1 - '
"YT max
It was assumed in (10) and (11) that thermal feedback dominates over the open-loop electrical gain, p.. Finally, in (11) a
maximum current was defined Imax = Vs/RL as the maximum current which would flow if the amplifier output could
swing all the way to the supplies.
I
I
I
t
J-'
L _
Equation (11) is a strikingly 'simple and quite general result
which can be used to predict the expected maximum usable
gain for an amplifier if we know only the maximum output
current and the thermal feedback constant "YT.
Recall that typically KT '" 0.3°C/W and n = (2 X 10- 3)
KT "" 0.6 mVlW. Consider, as an example, the standard IC
op amp operating with power supplies of Vs = ± 15V and a
minimum load of 2 kO, which gives Imax = 15V12 kO = 7.5
mAo Then, from (11), the maximum thermally limited gain is
about:
Av(o)lmax "" 1/(0.6 x 10-3)(7.5 x 10- 3)
(12)
"" 220,000.
Comparing (2) and (12), it is apparent that the thermal characteristics dominate over the electrical ones if the minimum
INPUT
PAIR
I
I
~NPN
-----~
TR~~~rs~1RS
TL/H/8745-11
FIGURE 8. One type layout in which a quad of input
transistors Is cross connected to reduce effect of
nonuniform thermal gradients. The output transistors
use distributed stripe geometries to generate
predictable Isothermal lines.
heavy copper base, n's as low as 50 p.V/W have been
observed. For example, a well-designed 5W amplifier driving
an 80 load and using a 24V supply, would have a maximum
gain of 13,000 in such a power package.
1225
+
Cc
, '2
+
Vo
Vi
V"I
Vo
IIm,V,
":'
":'
'11m, Viis)
Voll)"'-sCc
TL/H/8745-12
FIGURE 9. Flrst-order model of op amp used to calculate small signal high frequency gain. At frequencies of Interest
the Input Impedance of the second stage bacomeslow compared to first stage output Impedance due to Cc feedback.
Secause of this, first stage output Impedance can ba assumed infinite, with no 1088 In accuracy.
AVlO)
AVI..)
~bL-----
__________________________
~~~w
TLlH/8745-13
FIGURE 10. Plot of open-loop gain calculated from model In FIgure 9. The de and LF gain
are given by (10), or (11) If thermal feedback dominates.
As a final comment. it should be pointed out that the most
commonly observed effect of thermal feedback in high gain
circuits is low frequency distortion due to the nonlinear
transfer characteristic. Differential thermal coupling typically
fails off at an initial rate of 6 dBloctave starting around 100200 Hz, so higher frequencies are uneffected.
output stage is assumed to have unity voltage gain and is
ignored in our calculations. From Figure 9, the high frequency gain is calculated by inspection:
Av(CIl)
= IVo (S)I = 12!!!l1 = gin,
(14)
VI
sCe .CIlCe
where dc and low frequency behavior have not been Includ- '
ed since this was evaluated in the last section. Figure 10 is
a plot of the gain magnitude as predicted by (14). From this
figure It is a Simple matter to calculate the open-loop unity
gain frequency CIlu. which Is also the galn"bandwldth product
for the op amp under closed-loop conditions:
3.0 SMALL-810NAL FREQUENCY RESPONSE
At higher frequencies where thermal effects can be ignored,
the behavior of the op amp is dependent on purely electronic phenomena. Most of the important small and large signal
performance characteristics of the classical IC op amp can
be accurately predicted from very simple first-order models
for the amplifier in Figure 1 (8). The small-signal model that
is used assumes tnat the input differential amplifier and current mirror can be replaced by· a frequency independent
voltage controlled current source. see Figure 9. The second
stage consisting essentially of transistors 05 and 06, and
the current source load, is modeled as an Ideal frequency
independent amplifier block with a feedback or "Integrating
capacitor~' identical to the compensation capacitor, ce. The
IIIu
= g;o' .
(15)
In a practical amplifier, lIIu Is set to a low enough frequency
(by choosing a large Cel so that negligible excess phase
over the 90" due to Ce has built up. There are numerous
contributors to excess phase Including low ft p-n-p's, stray
capacitances, nondomlnant second stage poles, etc.
1226
These are discussed in more detail in a later section, but for
now suffice it to say that, in the simple IC op amp, tJ)u/21T is
limited to about 1 MHz. As a simple test of (15), the LM10l
or the ,...A741 has a first stage bias current 11 of 10,...A per
side, and a compensation capacitor for unity gain operation,
Ce, of 30 pF. These amplifiers each have a first stage gm
which is half that of the simple differential amplifer in Figure
1 so gm1 = q11/2kT. Equation (15) then predicts a unity
gain comer of
f _ tJ)u _ gm' _ (0.192 x 10-3 ) _
u - 21T - 21TCe - 21T(30 X 10 12) - 1.02 MHz (16)
4.0 SLEW RATE AND SOME SPECIAL LIMITS
A. A General Limit on Slew Rate
If an op amp is overdriven by a large-signal pulse or square
wave having a fast enough rise time, the output does not
follow the input immediately. Instead, it ramps or "slews" at
some limiting rate determined by internal currents and capacitances, as illustrated in Figure 11. The magnitude of
input voltage required to make the amplifier reach its maximum slew rate varies, depending on the type of input stage
used. For an op amp with a simple input differential amp, an
input of about 60 mV will cause the output to slew at 90
percent of its maximum rate, while a ,...A741 , which has half
the input gm, requires 120 mY. High speed amplifiers such
as the LM 116 or a FEr-input circuit require much greater
overdrive, with 1-3V being common. The reasons for these
overdrive requirements will become clear below.
An adequate model to calculate slew limits for the representative op amp In the inverting mode is shown in Figure
12, where the only important assumption made is that
12 ~ 21, in Figure 1. This condition always holds in a welldesigned op amp. (If one lets '2 be less than 21" the slew is
limited by 12 rather than I" which results in lower speed than
is otherwise possible.) Figure 12 requires some modification
for noninverting operation, and we will study this later.
The limiting slew rate is now calculated from Fig. 12. Letting
the input voltage be large enough to fully switch the input
differential amp, we see that all of the first stage tail current
211 is simply diverted into the integrator consisting of A and
Ce. The resulting slew rate is then:
which agrees closely with the measured values.
+
!
dVo
= iclt)
C .
slew rate = -d
t max
e
Noting that ie(t) is a constant 21" this becomes
(17)
dVo!
= 21,
(16)
dt max Ce ·
As a check of this result, recall that the ,...A741 has 11 =
10 ,...A and C1 = 30 pF, so we calculate:
TUH/8745-14
FIGURE 11. Large 81gnal "slewing" response
observed If the Input 18 overdrlven.
= 2 X 10- 5 = 067:!..
dt max 30 X 10- 12
·,...s
which agrees with measured values.
dvo!
(19)
+
OVERDRIVE
SLEW RATE .~I
dl
. I.ltl
Cc
mIX.
•
21,
CC
TL/H/8745-15
FIGURE 12. Model used to calculate 81ew rate for the amp of FIgure 11n the Inverting mode. For 8lmpllclty, all translator
a'8 are a8sumed equal to unity, although re8ults are essentially Independent of a. An ldentlcal8lew rate can be
calculated for a negative-going output, obtained If the applied Input polarity 18 reversed.
1227
,
i
d'(o!
= 2Cllu l l .
,",,"
(20)
•dt, max
,gml
Equation, (20) is a general and very useful relationship;, It
shows that, for a given unity-gain, frequency, 'blu, the ,slew
rate is' determined entirely by just the, ratio ,of first stage
operating current to ,first stage transconductance, 11/gml.
Recall that,Cllu is set ~tthe point where excess,phase begins to build up, and this point is determined largely by technology rather than circuit limitations. Thus, the only effective
means available to the circuit designer, for, increasing op
amp slew rate is ,to decrease the ratio of first stage transconductance to operating current, gml/1.
B_ Slew Limiting for Simple Bipolar Input stage
\.
dvo,
dt
= CllVp cos Clll.
dvol
= ruV '
p,
dt max
1 dvol
Cllmax = Vp
max'
dt
,(22)
!
dVo
(27)
Thus, power bandwidth and slew rate are directly related by
the inverse of the peak of, the Sine wave,Vp. Figure 13
shows the severe distortion of the output sine wave which
results if one attempts to amplify a sine wave which results
if one attempts to amplify a sine wave of frequency
Cll> Cllmax.
'
1Note that (21) applies only to the simple differenlial input siege of FlfJure
12. For compound inputstage,as in the LM10l or I'A741. gm1 is halflhatin
(21), and the slew rate in (23) is doubled.
USing this in (20), the maximum bipolar slew' rate is
~T'"
(23)
=2Cllu-'
dt max'
'q.'
This provides us with the general (and sqmewhat dismal)
conclusion that slew' rate in an op amp with a simple bipolar
input stage is dependent only upon the unity gain corner
and fundamental constants. 'Slew rate can be increased
only by incerasing the unity gain corner, which we have noted Is generally difficult to do., As a demonstration of the
severity of this limit, imagine an op amp -using ,highly advanced technology and clever design, which might have a
stable unity gain frequency of 100 MHz. Equation (23) predicts that the slew rate for this advanced device is only
-
(26)
so the highest frequency that can be reproduced without
slew limiting, Cllmax (power bandwidth) is
(21)
= q/kT.
(25)
This has a maximum when cos Cllt:= 1 giving
so that
,
,
C. P9werBandwidth
The significance of (20j is beSt seen by con~idering ~tle spe:
cific case ofa simple differenti;!.1 bipolar input as in Figure 1.
Fpr this circuit, the firSt stage transConductance (for (11 =,
1) isi ,
,',
"
"
9~1
"
Our hituitionregarding 'slew rate will be enhanced somewhat if we relate it to a term called "power bandwidth".
Power bandwidth is defined ,as the m8}(imum frequency at
which f~1I output swing (usually 10V peak} can be obtained
without distortion.' For, a sinusoidal output voltage volt) =
VpSinCllt, the rate of change of output~ or slew rate, required
to reproduce the output'is
",'
, gml = qll/kT
",
',dyoj' , ;, 3~
(24)
',"
dt'"
/-'S {.,._
'''''1"
,\m~.
whicn is good, b!Jt, hardly, impreSsive when compared with,
th,e Ilitficulty of l;>uil~,inQ a 100' Ml-iz op amp.2 But, there are
s~m,e,\Vaysto'!;IEitaround this'li!riit as we shall see shortly.
The large and small signa] 'behavior 'oHhe op amp can be
usefully related by combining (15) for ~u wi~h (18). The slew
rate becomes
' "
" ,,
,
2 We,8S!SJjme in all of these calculations that Cc is made large enough so
that the amplifier has less than 180' phase lag at '., •. thus making the amplifier sleble for unity Closed-loop gain. For higher gains one can of course
reduce Cc (if the IC allows external compensation) and increase the slew
rate according to (18),
+
V,SIN .. t
DISTORTED OUTPUT
IF",,> ""mIX
TL/H/8745-16
FIGURE 13. Slew limiting effects on output sinewave that occur frequency Is greater than power bandwidth, rumax.
The.onset of slew limiting occurs very,s,uddenly as Cll r~,acl!e!JCllmax-No.dlstortlon occurs below !"ma", while almost
complete triangul,a~lzatlo!l,occur!Jat freql,\enci~~ lust;$lig/ltly abo".e ~l\'.
ii
,:.
"
1228
{,,!,
Some numbers illustrate typical op amp limits. For a ,..A741
or LM101 having a maximum slew rate of 0.67V/,..s, (27)
gives a maximum frequency for an undistorted 10V peak
output of
f max =
ClImax
2:;;:- = 10.7 kHz,
2.0 kO each and these contribute an input offset of 1 mV for
each 40 (0.2 percent) of mismatch. The thermal noise of
the resistors also unavoidably degrades noise performance.
2) Slew Rate in the FET Input Op Amp: The FET (JFET or
MOSFET) has a considerably lower transconductance than
a bipolar device operating at the same current. While this is
normally considered a drawback of the FET, we note that
this "poor" behavior is in fact highly desirable in application's to last amplifiers. To illustrate, the drain current for a
JFET in the "current saturation" region can be approximated by
(31)
(28)
which is a quite modest frequency considering the much
higher frequency small signal capabilities of these devices.
Even the highly advanced 100 MHz amplifier considered
above has a 10V power bandwidth of only 0.5 MHz, so it is
apparent that a need exists for finding ways to improve slew
rate.
where
+
loss the drain current for VGS = 0,
VGS the gate source voltage having positive polarity for
fQrward gate-diode bias,
VT
the threshold voltage having negative polarity for
JFET's.
The small-signal transconductance is obtained from (31) as
gm = alO/aVG· Dividing by 10 and simplifying, the ratio
gmllO for a JFET is
gM
2
10 '" (VGS -
2 [loSS]'/2
Vr) = -VT""ID
.
(32)
Maximum amplifier slew rate occurs for minimum gmllo
and, from (32), this occurs when 10 or VGS is maximum.
Normally it is impractical to forward bias the gate junction so
a practical minimum occurs for (32) when VGS '" OV and 10
'" loss. Then
gmi
2
10
min'" -2 VT '
Comparing (33) with the analogous bipolar expression, (22),
we find from (20) that the JFET slew rate is greater than
bipolar by the factor
TL/H/8745-17
FIGURE 14. Resistive degeneration used to provide
slew rate enhancement according to (29).
JFET slew _ - VT2 CIIuf
bipolar slew - 2kTIqCllub
D. Techniques for Increasing Slew Rate
1) Resistive Enhancement of the Bipolar Stage: Equation
(20) indicates that slew rate can be improved if we reduce
first stage gm111,. One of the most effective ways of doing
this is shown in Figure 14, where Simple resistive emitter
degeneration has been added to the input differential amplifier (8). With this change, the gm,lI, drops to
gm' = -:---:::-3;.,:8"".5=-=.....,.,
I,
1 +TEI,126mV
(33)
(34)
where CIIuf and CIIub are unity-gain bandwidths for JFET and
bipolar amps, respectively. Typical JFET thresholds are
around 2V (Vr = - 2V), so for equal bandwidths (34) tells
us that a JFET-input op amp is about forty times faster than
a simple bipolar input. Further, if JFET's are properly substituted for the slow p-n-p's in a monolithic design, bandwidth
improvements by at least a factor of ten are obtainable.
JFET-input op amps, therefore, offer slew rate improvements by better than two orders of magnitude when compared with the conventional IC op amp. (Similar improvements are possible with MOSFET-input amplifiers.) This
characteristic, coupled with picoamp input currents and reasonable offset and drift, make the JFET-input op amp a very
desirable alternative to conventional bipolar designs.
(29)
at 25°C
The quantity gm1 II, is seen to decrease rapidly with added
RE as soon as the voltage drop across RE exceeds 26 mY.
The LM118 is a good example of a bipolar amplifier which
uses emitter degeneration to enhance slew rate [4]. This
device uses emitter resistors to produce REI, = 500 mY,
and has a unity gain corner of 1611('1Hz. Equations (20) and
(29) then predict a maximum inverting slew rate of
AS,an example, Figure 15, illustrates one design for an op
amp employing compatible p-channel JFET's on the same
chip with the normal bipolar components. This circuit exhibits a unity gain comer of 10 MHz, a 33 V I,..s slew rate, an
input current of 10, pA and an offset voltage and drift of 3
mV amd 3 ,..VI'C [6]. Bandwidth and slew rate are thus
improved over simple Ie bipolar by factors of 10 and 100,
respectively. At ,the same time input currents are smaller by
about 103, and offset voltages and drifts are comparable to
or better than slew enhanced bipolar circuits.
= 2C11u-J,- = CII u = 10~
(30)
dvoi
dt max
gm1
'
which is a twenty-fold improvement over a similar amplifier
without emitter rlOlsistors.
,..S
A penalty is paid in using resistivE1 slelA' enhancement, however. The two added emitter resistors must match extremely
well or they add voltage offset and drift to the input. In the
LM118, for example, the added emitter R's have values of
1229
~
::I
ti)
'ii
r---------~----~--------------~--------_1~------------~~_O~cc
"C
300
S::I
l-
e
L.:
CD
!E
Ie
'ii
c
0
:;::::;
1+1
f!
CD
a.
0
25
.2
.c
:g
~+CI~~--~~--_+--_oOUT
c
0
13.8
::E
CD
~
.c
~
ia.
e
1.(11<
11
~--4---~----~----~~----~----------~----~~--------------~---o-VEE
TL/H/8745-18
FIGURE 15. Monolithic operational amplifier employing compatible pochannel JFET's on
the same chip with normal bipolar components.
+@VoI
ti
Vshl
-
-
.,..
.
-+________-L__________
~~
______
~t
I~
VOIIhl
OUT1'IITfOA
NPH INPUT STAGE
VOPII)
TL/H/8745-19
FIGURE 16. Large signal response of the voltage follower. For an op amp with simple n-pon Input stage we get the
waveform VON(t), which exhibits a step slew "enhancement" on the positive going output, and a slew "degradation" on
the negative going output. For a pon-p Input stage, these etrecta are reversed as shown by vop(t).
1230
~--------------------------------------------------~~
5.0 SECOND-ORDER EFFECTS: VOLTAGE FOLLOWER
SLEW BEHAVIOR
If the op amp is operated in the noninverting mode and
driven by a large fast rising input, the ouput exhibits the
characteristic waveform in Figure 16. As shown, this waveform does not have the simple symmetrical slew characteristic of the inverter. In one direction, the output has a fast
step (slew "enhancement") followed by a "normal" inverter
slewing response. In the other direction, it suffers a slew
"degradation" or reduced slope when compared with the
inverter slewing response.
which is seen to be constant with time. The degraded voltage follower slew rate is then obtained by substituting (36)
into (35):
dvol
_ is _
211
(37)
dtdegr-Cs=Cc+Cs ·
Comparing (37) with the slew rate for the inverter, (18), it
is seen that the slew rate is reduced by the simple factor
1/(1 + Cs/Cd. As long as the input tail capacitance Cs is
small compared with the compensation amplifiers where Cc
is small, degradation become quite noticeable, and one is
encouraged to develop circuits with small Cs.
As an example, consider the relatively fast LM118 which
has Cc "" 5 pF, Ca "" 2 pF, 211 = 500 ,...A. The calcualted
inverter slew rate is 211 ICc "" 100V/,...s, and the degraded
voltage follower slew rate is found to be 211/(Cc + Ca) ""
70VI ,...s. The slew degradation is seen to be about 30 percent, which is very significant. By contrast a ,...A 741 has Cc
"" 30 pF and Cs "" 4 pF which results in a degradation of
less than 12 percent.
The slew "enhanced waveform can be similarly predicted
from a simplified model. By reversing the polarity of the input and initally assuming a finite slope on the input step, the
enhanced follower is analyzed, as shown in Figure 18. Noting that 01 is assumed to be turned ON by the step input
and 02 is OFF, the output voltage becomes
We will first study slew degradation in the voltage follower
connection, since this represents a worst case slewing condition for the op amp. A model which adequately represents
the follower under large-signal conditions can be obtained
from that in Figure 12 by simply tying the output to the inverting input, and including a capacitor Cs to account for the
presence of any capacitance at the output of the first stage
(tail) current source, see Figure 17. This "input tail" capacitance is important in the voltage follower because the input
stage undergoes rapid large-signal excursions in this connection, and the charging currents in Cs can be quite large.
Circuit behavior can be understood by analyzing Figure 17
as follows. The large-signal input step causes 01 to turn
OFF, leaving 02 to operate as an emitter follower with i~
emitter tracking the variational output voltage, volt). It IS
seen that volt) is essentially the voltage appearing across
both Cs and Cc so we can write
dvo
ic
is
dt""Cc ""Cs.
II
1
(38)
volt) "" - [211 + is(t)] dt.
Cc 0
The voltage at the emitter of 01 is essentially the same as
the input voltage, viet), so the current in the "tail" capacitance Ca is
(35)
Noting that ic '" 211 - is (unity a'S assumed), (35) can be
solved for is:
dVI
r'-V·
·(t)"'C-""~
e dt
t1
IS
(36)
Combining (38) and (39), volt) is
-volt) '" -
1
Cc
II
0
211 dt + -
1
Cc
0< t < t1.
(39)
III
(40)
0
CeVip
dt
t1
+
I-I
TL/H/8745-20
FIGURE 17. Circuit used for calculation of slew "degradation" In the voltage follower. The degradation Is caused by the
capacitor Ca, which robs current from the tall, 211, thereby preventing the full 211 from alewlng Ce•
1231
1
a.;C.
~
i
f
=
o
g
c:;.
o
1
i.o
i.
~
'2.
:i
~
:.
I
J
+
1+)
V,lt)
TLlH/8745-21
FIGURE 18. Circuit used for calculation of slew, "enhancement" in the voltage follower. The fast failing
Input casues a step output followed by a normal slew response as shown.
or
Ca
-volt) '" Cc Vip
211t
+ Co'
It can be seen that if one attempts to operate the first stage
at too Iowa current, these poles will bandlimit the amplifier.
If, for example, we choose 11 = 1 pA, and,assume Cm",,"
7 pF (consisting of 4 pF isolation capacitance and 3 pF
emitter transition capacitance) and Ca '" 4 pF,3 Pm/21T ""
0.9 MHz and Pt/21T "" 3 MHz either of which would seriously degrade the phase margin of a 1 MHz amplifier.
(41)
Equation (41) tells us that the output has an initial negative
step which is the fraction Ca/Cc of the input voltage. This is
followed by a normal slewing response, in which the slew
rate is identical to that of the inverter,. see (18). This response is illustrated in Figure 18.
.
If a design is chosen in which either the tail pole or the
mirror pole is absent (or unimportant), the remaining pole
rolls off only half the signal, so the overall response contains a pole-zero pair separated by one octave. Such a pair
generally has a small effect on amplifier response unless it
occurs near CIlw where it can degrade phase margin by as
much as 20·.
6. LIMITATIONS ON BANDWIDTH
In earilier sections, all bandlimiting Elffects were ignored except that of the compensation capacitor, Cc. The unity-gain
frequency was set at a point sufficiently low so that negligible excess phase (over the 90· from the dominant pole) due
to second-order (high frequency) poles had built up. In this
section the major second-order poles which contribute to
bandlimiting in the op amp are identified.
It is interesting to note that the compound input stage of the
classical LM10l and JJ.A741) has a distinct advantage over
the simple differential stage, as seen in Figure 19(b). This
circuit is noninverting across each half, thus it provides a
path in which. half the feedback signal bypasses both the
mirror and tail poles.
A. The Input Stage: pan-p'., the Mirror Pole, and the Tall
Pole
For many years it was popular to identify the lateral p-n-p's
(which have ft's '" 3 MHz) as the single dominant source of
bandlimiting in the IC op amp. It is quite true that the p-ri-p's
do contribute significant excess phase to the amplifier, but it
is not true that they are the sole contributor to excess phase
(9). In the input stage, alone, there is at least one other
important pole, as illustrated in figure 19(a). For the simple
differential input stage driving a differential-to-single ended
converter ("mirror" circuit), it is seen that the inverting signal
(which is the feedback signal) follows two paths, one of
which passes through the capacitance Ca, and the other
through Cm. These capacitances combine with the dynamic
resistances at their nodes to form poles deSignated the mirror pole at
B. The Second Stage: Pole Splitting
The assumption was made in Section 3 that the second
stage behaved as an ideal integrator having a single dominant pole response. In practice, one must take care in deSigning the second stage or second-order poles can cause
significant deviation from the expected response. Considerable insight into the basic way in which the second stage
operates can tie obtained by performing a small-signal analysis ona simplified version of the circuit as shown in Figure
20 [10]. A straightforward two-node analysis of Figure 2O(c)
produces the following expression for Vout.
vou!
-.- = -gmR1R2(1 - sCp/9 m) +
Is
(1
(42)
and the tail pole al'
+ S[Rl (Cl + Cp) + R2 (C2 + Cpl + gmR1R2C~
+ S2Rj R2 '[C1C2 + Cp (C.l + c~n.'" (44)
3 Ca can have a wide range of values depending on circuli configuration. It Is
largest for n·p·n input differential amps since the currant source has a col·
lector·substrate capacitance (Ca '" 3-4 pF at its output. For p·n·p input
stages it can be as smali as 1-2 pF.
(43)
1232
,--------------------------------------------------------------------..
"C
+
"C
CD
:::I
a.
;:C.
Cs
~
_--l~-~AILPOLE
';J
....--------,
CD
s:
o
f-)o---i":
:::I
2::;:
:r
(i'
>_I-OVo
r-
o
-g
MIRROR
POLE
ao·
MT
C
I
:::I
~
!!!.
TLlH18745-22
(a)
•
3
'2.
:;:
iii'
+
:'!
•
-I
(+)
c
s-:=!.
o----t:
!!!.
~
c
~
>-_-oVo
TL/H/8745-23
(b)
FIGURE 19. (a) Circuit showing "mirror" pole due to Cm and "tall" pole due to Ca. One component
of the signal due to an Inverting Input must pass through either the mirror or tail poles. (b) Alternate circuit to Figure
19(8) (LM101, ,..,A741) which has less excess phase. Reason Is that half the Inverting signal path need
not pass through the mirror pole or the tall pole.
The denominator of (44) can be approximately factored un·
der conditions that its two poles are widely separated. Fortunately, the poles are, in fact, widely separated under most
normal operating conditions. Therefore, one can assume
that the denominator of (44) has the form
O(s) = (1
= 1
(48)
"" --::-=-~
gmR1R2Cp'
The latter approximation (48), normally introduces little er·
ror, because the gm term is much larger than the other two.
We note at this point that Pl. which represents the dominant
pole of the amplifier, is due simply to the familiar Miller·mul·
tiplied feedback capacitance gmR2Cp combined with input
node resistance, R1. The nondominant pole P2 is found sim·
ilarly by equating 52 coefficients in (44) and (46) to get P1P2,
and dividing by Pl from (48). The result is
+ S/P1)(1 + S/P2)
+ s(1/P1 + 1/P2) + s2/P1P2'
(45)
With the assumption that P1 is the dominant pole and P2 is
nondominant, i.e., P1 -< P2, (45) becomes
O(s) "" 1 + 5/P1 + s2/P1P2.
(46)
Equating coefficients of s in (44) and (46), the dominant
pole P1 is found directly:
Pl ""
1
Rl(Cl
+ Cp) + R2(C2 + Cp) + gmR1R2Cp
P2 ""
gmCp
(49)
C1C2 + Cp (Cl + C2)
Several interesting things can be seen in examining (48)
and (49). First, we note that Pl is inversely proportional to
gm (and Cp), while P2 is directly dependent on gm (and Cpl.
(47)
1233
+
+
~-t----1~OVO
1 - - - -......- - - 1 - - 0 Vo
is
I
~G
I
*
I
I
*
*
(al
(b)
(el
TLIH/8745-24
FIGURE 20. Simplification of second stage used for pole-splitting analysis. Ca) Complete second stage with Input
stage and output stage loading represented by Ra. Ca. and RL. CL respectively. Cb) Emitter follower Ignored to
simplify analysis. Cc) Hybrid 'TT model substituted for transistor In Cb). Source and load Impedances are absorbed
into model with the total Impedances represented by R1. C1. and R2 and C2. Transistor base resistance Is Ignored
and Cp Includes both Cc and transistor collector-base capacitance.
,
DOMINANT
MILLER POLE
NON·DOMINANT
POLE
\
o •
gm2/C1C2
MAX. VALUE
FOR Cp > C1C!zIIC1+C21,
TL/H/8745-25
FIGURE 21. Pole migration for second stage employing "pole-splitting" compensation. Plot Is shown for
increasing Cp and It is noted that the nondomlnant pole reaches a maximum value for large Cpo
1234
IW
DOMINANT POLE
NON-OOMINANT POLE
~ .. 66 MHz
o •
1
2iiR 2C2 .. 32kHz
1
2wR,CI .. 8kHz
INITIAL POLES FOR Cp = 0
TL/H/8745-26
FIGURE 22. Example of pole-splitting compensation In the ,...A,741 op amp. Values used In (48) and
(49) are: gm2 = 1/870, Cp = 30 pF, C, "" C2 = 10 pF, R, = 1.7 MO, R2 = 100 kO.
Thus, as either Cp or transistor gain are increased, the dominant pole decreases and the nondominant pole increases.
The poles P1 and P2 are being "split-apart" by the increased
coupling action in a kind of inverse root locus plot.
This pole-splitting action is shown in Figure 21, where pole
migration is plotted for Cp increasing from 0 to a large value.
Figure 22 further illustrates the action by giving specific pole
positions for the ,...A741 op amp. It is seen that the initial
poles (for Cp = 0) are both in the tens of kHz region and
these are predicted to reach 2.5 Hz (P1/2'IT) and 66 MHz
(P2/2'IT) after compensation is applied. This result is, of
course, highly satisfactory since the second stage now has
a single dominant pole effective over a wide frequency
band.
illustrate, suppose we attempt to minimize power disSipation
by running the second stage of an LM118 (which has a
small-signal bandwidth of 16 MHz) at 0.1 mA. For this op
amp Cp = 5 pF, C, "" C2 "" 10 pF. From (49), the nondominant pole is
P2 "" 16 MHz
which lies right at the unity-gain frequency. This pole alone
would degrade phase margin by 45', so it is clear that we
need to bias the second stage with a collector current greater than 0.1 mA to. obtain adequate gm. Insufficient pole-splitting can therefore occur; but the cure is usually a simple
increase in second stage gm.
A second type of pole-splitting failure can occur, and it is
ofen much more difficult to cope with. II, lor example, one
gets over-zealous in his attempt to broadband the nondominant pole, he soon discovers that other poles exist within
the second stage which can cause difficulties. Consider a
more exact equivalent circuit for the second stage 01 Figure
20(a) as shown in Figure 28. 11 the follower is biased at low
currents or if cp, 02 gm, and/or rx are high, the circuit can
contain at least four important poles rather than the two
C. Failure of Pole Splitting
There are several situations in which the application of polesplitting compensation may not result in a single dominant
pole response. One common case occurs In very wide-band
op amps where the pole-splitting capacitor is small. In this
situation the nondominant pole given by (49) may not become broadbanded sufficiently so that it can be ignored. To
-
(50)
2'IT
i,
VI
FIGURE 23. More exact equivalent circuit for second stage of Figure 2O(a) including a simplified
'IT model for the emitter follower (R'lTl, C'lTl, gm.> and a complete 'IT for Q2 (rx2, R'lT2, etc.).
1235
PEAKING OR
-.-------x
POLE DUE TO /
FOLLOWER
jw
(
x---_.~_x
,\
x_
POLE DUE
TLlH/8745-28
FIGURE 24. Root IOCU8 for 8econd stage illustrating failure of pole 8plitting due to
high gm20 rx2. Cpo and/or low bla8 current In the emitter follower.
considered in simple pole splitting. Under these conditions,
we no longer have a response with just negative real poles
as in Figuf9 21, but observe a root locus of the, sort shown
in Figuf9 24. It is seen in this cese that the circuit contains a
pair of complex, possibly underdamped poles which, of
course, can cause peaking or even oscillation. This effect
occurs so commonly in the development of wide-band polesplit amplifiers that it has been (not fondly) dubbed "the
second stage bump."
There are numerous ways to eliminate the "bump," but no
Single cure has been found which is effective in all situations. A direct hand analysis of Figuf9 23 is possible, but the
results are difficult to interpret. Computer analysis seems
the best approach for this level of complexity, and numer·
ous specific analyses have been made. The following Is a
list of circuit modifications that have been found effective in
reducing the bump in various studies: 1) reduce gm2, rx2.
C,,2, 2) add capaCitance or a series RC network from the
stage input to ground-this reduces the high frequency local
feedback due to Cp, 3) pad capacitance at the output for
similar reasons, 4) increase operating current of the follower, 5) reduce Cp, 6) use a higher ft process.
D. Trouble81n the Output Slage
Of all the circuitry in the modern IC op a",p, the class-AB
output stage probably remains the most troublesome. None
of the Stages in use today behave as well as one might
desire when stressed under worst case conditions. To illustrate, one of the most commonly 'used output stages is
shown in F/{Jure 2(b). The p-n-p's in this circuit are "substrate" p-n-p's having low current ft's of around 20 MHz.
Unfortunately, both ,Po and ft begin to fall off rapi~1y at quite
low current densities, so as one begins to sink just a few
milliamps in the circuit, phase margin troubles can develop.
The worst effect occurs when the amplifier is operated with
a large capacitive load (>100 pF) while sinking high currents. As shown in Figuf9 25, the load capacitance on the
----~--------~~------~~+
L
"'-GIIC
TL/H/8745-29
FIGURE 25. Trouble81n the conventional cla88-AB output 8tage of Figure 2(b). The low ft output p-n-p'8
Interact with load capaCitance to form the equivalent of a one-port 08clllator.
'
1236
t------....
-oVOUT
TL/H/8745-30
FIGURE 26. The "BI-FETTM" output stage employing JFET's and bipolar n-p-n's to eliminate sensitivity to load
capacitance.
output follower causes it to have negative input conductance, while the driver follower can have an inductive output
impedance. These elements combine with the capacitance
at the interstage to generate the equivalent of a one-port
oscillator. In a carefully designed circuit, oscillation is suppressed, but peaking (the "output bump") can occur in most
amplifiers under appropriate conditions.
One new type of output circuit which does not use p-n-p's is
shown in Figure 26 [6]. This circuit employs compatible
JFET's (or MOSFET's, see similar circuit in [11]) in a FETI
bipolar Quasi-complementary output stage, which is insensitive to load capaCitance. Unfortunately, this circuit is rather
complex and employs extra process steps, so it does not
appear to represent the cure for the very low cost op amps.
7. The Gain Cell: Linear Large-Scale Integration
As the true limitations of the basic op amp are more fully
understood, this knowledge can be applied to the development of more "optimum" amplifiers. There are, of course,
many ways in which one might choose to optimize the device. We might, for example, attempt to maximize speed
(bandwidth, slew rate, settling time) without sacrificing dc
characteristics. The compatible JFETIbipolar amp of FlfJure
15 represents such an effort. An alternate choice might be
to design an amplifier having all of the performance features
of the most widely used general purpose op amps (i.e.,
""A741 , LM107, etc.), but having minimum possible die area.
Such a pursuit is parallel to the efforts of digital large-scale
integration (LSI) designers in their devlelopment of minimum
+
TLlH/8745-31
FIGURE 27. Basic gm reduction obtained by using spilt collector p-n-p's. Cc and area are reduced since Cc = gm1/CIlu'
1237
~.---------------~------------------------------------------------------------,
"0
~
u;
j
C'
~
';j
CD
s:::
o:::s
2-
C;'
o
-g
~
o:::s
e!.
~
'5!.
::;;
ii'
:"!
~
-I
c
0'
::::!,
e!.
en
c
Co
'<
(.)
25
OUT
25
40k
+
75k
130
TLlH/8745-34
FIGURE 29, Circuit for optimized gain cell which has been fabricated
In one-fourth the die size of the equivalent ".A741.
1239
~
~
u)
'iii
";:
.2
~
t-
ce
Many important contributions were made in the gain cell and
FET/bipolar op amp areas by R. W. Russell. The author
gratefully acknowledges his very competent efforts.
REFERENCES
[1]
i.:
I»
!E
"S.
E
ce
[2]
'iii
c
o
~
Bo
'0
c
::i!
o
~
Ci
..!!!
R. J. Widlar, "Monolithic Op Amp with Simplified Frequency Compensation," I££E, vol. 15, pp. 58-63, July
1967. (Note that the LM101 designed in 1967, by R. J.
Widlar was the first op amp to employ what has become the classical topology of Figure 1.)
D. Fullagar, "A New High Performance Monolithic Operational Amplifier," Fairchild Semiconductor Tech. Paper,1968.
[3] R. W. Russell and T. M. Frederiksen,"Automotive and
Industrial Electronic Building Blocks," 1£££ J. SolidState Circuits, vol SC-7, pp. 446-454, Dec. 1972.
[4]
Co>
:c
:t::
[7]
ACKNOWLEDGMENT
R. C. Dobkin, "LM118 Op Amp Slews 70V/p.s," Linear
Applications Handbook, National Semiconductor, Santa Clara, Calif:, 1974.
[5] R. J. Apfel and P.R. Gray, "A Monolithic Fast Settl~ng
Feed-Forward Op Amp Using Doublet Compression
Techniques," in ISSCC Dig. Tech. Papers, 1974, pp.
134-155.
[6]
R. W. Russell and D. D. Culmer, "Ion Implanted JFETBipolar Monolithic Analog Circuits," in ISSCC Dig.
Tech. Papers, 1974, pp. 140-141.
P. R. .Gray, "A 15-W Monolithic Power Operational Amplifier," 1£££ J. Solid-State Circuits, vol. SC-7, pp. 474480, Dec. ,1972.
[8] J. E. Solomon, W. R. Davis, and P. L. Lee, "A Self
Compensated Monolithic Op. Amp with Low Input Current' and High Slew Rate," ISSCC Dig. Tech. Papers,
1969, pp. '14-15.
'
[9]
B. A. Wooley, S. Y. J. Wong, D.O. Pederson, " A Computor-Aided Evaluation of the 741 Amplifier," 1£££ J.
Solid-State Circuits, vol. SC-6, pp. 357:366, Dec.
1971-
[10] J. E. Solomon and G. R. Wilson, "A Highly Desensitized, Wide-Band Monolithic Amplifier," /£££ J. SolidState Circuits, vol. SC-1, pp. 19-28, Sept. 1965.
[11] K.R. Stafford, R. A. Blanchard, and P. R. Gray, "A
Completely Monolithic Sample/Hold Amplifier Using
Compatible Bipolar and Silicon Gate FE;T Devices," in
ISSCC Dig. Teph. Papers, 1974, pp. 190-191.
[12] J. E. Solomon and R. W. Russell, "Transconductance
Reduction Using Mulitple Collector PNP Transistors in
an Operational Amplifier," U.S. Patent 3801923, Mar.
1974.
See also, as a gf!neral referefJC8:
[13] P. R. Gray and R. G. Meyer, "Recent Advances in
Monolithic Operational Amplifier Design," 1£££ Trans.
Circuits and Syst., vol. CAS-21, pp. 317-327, May
1974.
"
C
I»
Q.
Q.
ce
1240
V IF Converter ICs Handle
Frequency-to-Voltage
Needs
National Semiconductor
AppendixC
Robert A. Pease
Simplify your FIV converter designs with versatile V/F ICs.
Starting with a basic converter Circuit, you can modify it to
meet almost any application requirement You can spare
yourself some hard labor when designing frequency-to-voltage (F IV) converters by using a voltage-to-frequency IC in
your designs. These ICs form the basis of a series .of accurate, yet economical, FIV converters suiting a variety of applications.
Figure 1 shows an LM331 IC (or LM131 for the military temperature range) in a basic FIV converter configuration
(sometimes termed a stand-alone converter because it requires no op amps or other active devices other than the
IC). (Comparable V/F ICs, such as RM4151, can take advantage of this and other circuits described in this article,
although they might not always be pin-for-pin compatible).
This circuit accepts a pulse-train or SQuare wave input amplitude of 3V or greater. The 470 pF coupling capacitor suits
negative-going input pulses between 80 ".s and 1.5 ".s, as
well as accommodating square waves or positive-going
pulses (so long as the interval between pulses is at least 10
".s).
a time t = 1.1 RtC. The 1 ".F capacitor filters this pulsating
current from pin 1, and the current's average value flows
through load resistor RL. As a result, for a 10kHz input, the
circuit outputs 10 Vec across RL with good (0.06% typical)
..
nonlinearity.
IC Handles the Hard Part
The LM331 detects an input-signal change by sensing when
pin 6 goes negative relative to the threshOld voltage at pin 7,
which is nominally biased 2V lower than the supply voltage.
When a Signal change occurs, the LM331's input comparator sets an internal latch and initiates a timing cycle. During
this cycle, a current equal to VREF/RS flows out of pin 1 for
Two problems remain, however: the output at V1 includes
about 13 mVp-p ripple, and it also lags 0.1 second behind
an input frequency· step change, settling to p.1 % of fullscale in about 0.6 second. This ripple and slow response
represent an inherent tradeoff that applies to almost every
FIV converter.
The Art of Compromise
Increasing the filter capacitor's value reduces ripple but also
increases response time. Conversely, lowering the filter capacitor's value improves response time at the expense of
larger ripple. In some cases, adding an active filter results in
faster response and less ripple for high input frequencies.
Although the circuit specifies a 15V power supply, you can
use any regulated supply between 4 Vec and 40 Vec. The
output voltage can extend to within 3 Voc of the supply
voltage, so choose RL to maintain that output range.
Adding a 220 kO/O.1".F postfilter to the circuit slows the
response slightly, but it also reduces ripple to less than 1
mVp-p for frequencies from 200 Hz to 10kHz. The reduction
in ripple achieved by adding this passive filter, while not as
good as that obtainable using an active filter, could suffice
in some applications.
VS·,5V
10k
10k
88k
410 pF
'IN
o---J
-
. 5
Ct
1'0.OI Il F
10kHz FS
(VREF)
lM331
OUTPUT 1
(VI)
220k
r
OUTPUT 2
(V2)
10V
-JitNtr
III
lDO.·
DC FS
O.lIlF
'Use stable components with
low temperature coefficients
TL/H/8741-1
FIGURE 1. A Simple Stand-Alone FlY Converter Forms the
Basis for Many Other Convertar-Clrcult Configurations
1241
, Improving the saalc Circuit
.Further modifications and additions to the basic FIV converter shown in F/flure 1 can adapt It to specific performance requirements. Figure 2 shows one such modification,
which improves the converter's nonlinearity to 0.006% typical.
Aeconsideration of the basic stand-alone converter shows
why its nonlinearity falls short of th,is improved version's .. At
low input frequencies, the current source feeding pin 1 in
the LM33,1 is, tumed off most of the time. As the input frequency increases, however, the Currerit source stays on
more of the time, and its own impeclance attenuates the
output signal for an increasing traction of each cycle time.
This diSproportionate attenuation at higher frequencies
causes parabolic change in full-scale gain rather than the
desired linear one.
'
In the improved circuit, on the other hand, the PNP transistor acts as a cascade, so the output impedance at pin 1
sees a constant voltage that won't modulate the gain. Also,
with an alpha ranging between 0.998 and 0.990; the transistor exhibits a temperature coefficient of between ,1 0 ppm 1°C
and 40 ppm/°e-a fairly minor effect. Thus, this circuit's
nonlinearity does not e,xceed 0.Q1 % maximum for the 10V
output range shown and normally not worse than 0.01 %
for any supplyvoltage between 4V and 40V.
is
Add an Output Buffer
The circuit in Figure 3 adds an output buffer (unity-gain follower) to the basic single-supply FIV converter. Either an
LM324 or LM358 op amp functions well in a single-supply
circuit because these devices' common-mode ranges extend down to ground. But if a negative supply is available,
you can' use any op amp; types such as the LF351B or
'LM308A, which have low input currents, provide the best
accuracy.
The output buffer in Figure 3 also acts as an active filter,
fumishing a 2-pole response from a single op amp. This
filter provides the general response
VOUT"OUT = AL/(1 + K1p + K2p2).
(p is the differential operator d/dt.) As shown, AL controls
the filter's DC gain. The high frequency, response rolls off at
12 dB/octave. Near the circuit's natural resonant frequency,
you can choose the damping to give a little overshoot-or
none, as desired.
a
Vs • 4.6V TO 20V
Ql = 2N4250, 2N3906 or similar
hlgh·beta PNP transistor
Select Rx = [(Vs - 3V)/3V)
10k,
x
10k
:1±1%'
~
low temperature coefficients
Cl
470pF
lIN
0-1
10kll
'Use stable components with
-:J;'
':"
lM331
Ct
0.01 ~F'
_ . . .- -....OVOUT
~l
12k'I'"
6k'
GAIN
ADJUST
':"
':"
TL/H/B741-2
FIGURE 2. Adding a Cascade Transistor to the LM331's Output Improves Nonlinearity to 0.006%
C3
10k
10k
1.llk
0.001 ~F
.,:t
C,
LM331
""',:" 0.01 ~F'
.J..
1~
~I
12k ±1K·
Al
Sk"
=
1/2 LM358 or 1/4 LM324
'Use stable components wilh
GAIN
ADJUST
low lemperature coefficients
':"
TL/H/8741-3
FIGURE 3. The Op Amp on This FlY Converter's Output Acts as a Buffer as Well as a 2-Pole Filter
1242
Dealing with F/V Converter Ripple
Voltage ripple on the output of FIV converters can present
a problem, and the chart shown in Figure A indicates exactly
how big a problem it is. A simple, slow, RC filter exhibits low
ripple at all frequencies. Two-pole filters offer the lowest
ripple at high frequencies and provide a 30-times-faster step
response than RC devices.
To reduce a circuit's ripple at moderate frequencies, however, you can cascade a second active-filter stage on the FIV
converter's output. That circuit's response also appears in
Figure A and shows a significant improvement in low-ripple
bandwidth over the single-active-filter configuration, with
o;lIy a 30% degradation of step response.
C3
0.01 ~F
Cl
0.1 pF
RI
lOOk
V,N
TUH/8741-6
The circuit shown in Figure C does not require precision
passive components, but for best accuracy, choosing an A1
with a high CMRR is critical. An LM308A op amp's 96 dB
minimum CMRR suits this circuit well, but an LM358B's 85
dB typical figure also proves adequate for many applications. Circuit response is
VOUTIVIN = 1/(1 + (R1 + R2) C2p + R1R2C1C2p2).
For best results, choose R3 = R1 + R2.
I. r----r:.:.-_-u~~-••~,.~'O~LE~AC~TlV~'--,
fiLTER PER fiGURE 3
USIIiG SIMPLE ;00 W -1 ~f
~IL TER PER FI~URE I
Components Determine Response
100 H~""'d"--USI.GlW8'-POLEACTlV'
The specific response of the circuit in Figure 3 is
- - - FILTERS CASCADED
p.p
VOUT"OUT = RL/(1 + (RL + R2)C2p +
RLR2C1 C2C2p2).
Making C2 relatively large eliminates overshoot and sine
peaking. Alternatively, making C2 a suitable fraction of C1
(as is done in Figure 3) produces both a sine response with
o dB to 1 dB of peaking and a quick real-time response
having only 10% to 30% overshoot for a step response. By
maintaining Figure 3's ratio of C1 :C2 and R2:RL, you can
adapt its 2-pole filter to a wide frequency range without tedious computations.
L..-__--'-____J..-__- ' -__-----'
0.1
-Note: AI should have a high
CMRR for best results
FIGURE C. This 2·Pole Nonlnvertlng Filter Suits
Cascade Requirements on F/V Converter Outputs
- VOUTIVIN = 11(1 + (RF+ 2R2)C4p+ RFR2C3C4p2).
0.01
AI"
o-.It,I.,.,......J\M~H+
~O.OZ~F
-VOUTIVIN= n/(1 + (RF+R2+ nR2)C4p+ RFR2C3C4p2).
where n = DC gain. If RIN = RF and n = 1,
D. I
RZ
lOOk
cz
Figures Band C show filter circuits suitable for cascading.
The inverting filter in Figure B requires closely matched resistors with a low TC over their temperature range for best
accuracy. For lowest DC error, choose R5 = R2 +
(RINIRF)' This circuit's response is
-.-
"'~Mr--+--""OVOUT
10
100
FREQUENCY 1kHz)
TL/H/8741-4
This filter settles to within 1% of a 5V step's final value in
about 20 ms. By contrast, the circuit with the simple RC filter
shown in Figure 1 takes about 900 ms to achieve the same
response, yet offers no less ripple than F/{/ure 3's op amp
approach.
As for the other component in the 2-pole filter, any capacitance between 100 pF and 0.05 JlF suits C3 because it
serves only as a bypass for the 200 kO resistor. C4 helps
reduce output ripple in single poSitive power-supply systems
when VOUT approaches so close to ground that the op
amp's output impedance suffers. In this circuit, using a tantalum capaCitor of between 0.1 JlF and 2.2 JlF for C4 usually
helps keep the filter's output much quieter without degrading the op amp's stability.
FIGURE A. Output-Ripple Performance of Several
Different F/V Converter Configurations
Illustrates the Effect of Voltage Ripple
-Note: R'N and RF should be
closely matched with a good
TC of tracking. for best
accuracy
RF ~ nR'N
TL/H/8741-5
FIGURE B. You Can Cascade This 2-Pole Inverting
Filter onto an F/V Converter's Output
1243
parallel with it, to greatly tliminish the TC previously observed and yield a complete circuit with a lower TC than you
could obtain simply by buying low TC parts.
For example, if the circuit increases its full-scale output by
0.1 % per 30°C (33 ppml"C) during the oven test, adding
120 kO in series with Rx = 240 kO cancels the temperature-caused deviation. Or, if the full-scale output decreases
by -0.04% per 20"C (-20 ppm/oC), just add 1.2 MO in
parallel with Rx.
Note that to allow trimming in both directions, you must start
with a finite fixed TC (such as the -1 f 0 ppm/DC of Ctl,
which then nominally cancels out by the addition of a finite
adjustable TC. Only by using this procedure can you compensatefor whatever polarity of TC is.found by the oven
test.
You can utilize this technique to obtain TCs as low as 20
ppm/DC, or perhaps even f 0 ppm/DC, if you take a few
passes to zero-in on the best value for Rx. For optimum
results, consider the following guidelines:
• Use a good capaCitor for Ct; the cheapest polystyrene
capacitors can shift value by 0.05% or more per temperature cycle. In that case, you would not be able to distinguish the actual temperature sensitivity from the hysteresis, and you would also never achieve a stable circuit.
• After soldering, bake or temperature-cycle the circuit (at
a temperature not exceeding 75°C in the case of polystyrene) for a few hours to stabilize all components and to
relieve the strains of soldering.
• Do not rush the trimming. Recheck the room temperature value before and after you take the high temperature data to ensure a reasonably low hysteresis per cycle.
• Do not expect a perfect TC at - 25°C if you trim for ± 5
ppm/DC at temperatures from + 25°C to 6O"C. None of
the components in the figure's circuit offer linearity much
better than 5 ppml"C or 10 ppml"C cold, if trimmed for a
zero TC at warm temperatures. Even so, using these
techniques you can obtain a data converter with better
than 0.02% accuracy and 0.003% linearity, for a ±20"C
range around room temperature.
.
• Start out the trimming with Rx installed and its value near
the design-center value (e.g., 240 kO or 270 kO), so you
Avoid Low-Leakage Limitations
Note that in most ordinary applications, this 2-pole filter performs as well with 0.1 p.F and 0.02 p.F capacitors as the
passive filter in Figure 1 doas with 1 p.F. Thus, if you require
a 100 Hz FIV converter, the circuit in Figure 3 furnishes
good filtering with C1 = 10 p.F and C2 = 2 p.F, and eliminates the 100 p.F low-leakage capacitor needed in a passive filter.
Note also that because C1 always has zero DC voltage
across it, you can use a tantalum or aluminum electrolytic
capacitor for C1 with no leakage-related problems; C2, however, must be a low-leakage type. At room temperature, typical 1 p.F tantalum components allow only a few nanoamperes of leakage, but leakage this low usually cannot be
guaranteed.
Compensating for Temperature Coefficients
FIV converters often encounter temperature-related problems usually resulting from the temperature coefficients of
passive components. Following some simple design and
manufacturing guidelines can help immunize your circuits
against loss of accuracy when the temperature changes.
Capacitors fabricated from Teflon or polystyrene usually exhibit a TC of -110 ± 30 ppm/DC. When you use such a
component for the timing capacitor .in an FIV converter
(such as Ct in the figure) the circuit's output voltage-or the
gain in terms of volts per kilohertz-also exhibits a -110
ppml"CTC.
But the resistor-diode network (Rx, 01, 02) connected from
pin 2 to ground in the figure can cancel the effect of the
timing capacitor's large TC. When Rx = 240 kO, the current
flowing through pin 1 will then have an overall TC of 110
ppm/DC, effectively canceling a polystyrene timing capacitor's TC to a first approximation. Thus, you needn't find a
zero-TC capaCitor for Ct, so long as its temperature coefficient is stable and well established. As an additional advantage, the resistor-diode network nearly compensates to zero
the TC of the rest of the circuit.
.
Bake It for a While
After the circuit has been built and checked out at room
temperature, a brief oven test will indicate the sign and the
size of the TC for the complete FIV converter. Then you
can add resistance in series with Rx, or add conductance in
VS' 15V
~
~,'"
11k
-,,<18k
470pF
7
____ J
10;..
*~~_..!~
RX
-
FD333 or similar
silloon planar diode
5
-1...~,pF
._.!L _____ •
01.02 = lN4S4.
lit
""k±'''~
o:b
I
IIN~iH~-_ _ _-=-I
II'!.
•
I
2
I
lOUT
IT
12.1~.J:
13·~'PF
±1". ~ "9" - 1 -
[
RS
TTEFLONOR
"=' POLYSTYRENE
LM331A
VOUT
~RL
1DOk*
VIII....
T--t-o
'*
).
GAlli
ADJUST
*
'Use stable componenls with
low lemperalure coelllcienls
TLlH/8741-7
Two Diodes and a Resistor Help Decrease an F/V Converter's Temperature CoeffiCient
1244
er, that while the circuit's nonlinearity error is negligible, its
ripple is not.)
will be reasonably close to zero TC; you will usually find
the process slower if you start without any resistor, because the trimming converges more slowly.
The Circuit in Figure 4 offers a significant advantage over
some other designs because the offset adjust voltage derives from the stable 1.9 Vee reference voltage at pin 2 of
the LM331; thus any supply voltage shifts cause no output
shifts. The offset pot can have any value between 200 kO
and 2 MO •
• If you change Rx from 240 kO to 220 kO, do not pull out
the 240 kO part and put in a new 220 kO resistor-you will
get much more consistent results by adding a 2.4 MO
resistor in parallel. The same admonition holds true for
adding resistance in series with RX.
An optional bypass capacitor (C2) connected from the op
amp's positive input to ground prevents output noise arising
from stray noise pickup at that point; the capaCitance value
is not critical.
• Use reasonably stable components. If you use an LM331A
(±50 ppm/·C maximum) and RN55D film resistors (each
± 100 ppm/·C) for RL, Rt and Rs, you probably won't be
able to trim out the resulting ± 350 ppm/·C worst-case
TC. Resistors with a TC specification of 25 ppml"C usually
work well. Finally, use the same resistor value (e.g., 12.1
kO ± 1%) for both Rs and Rt; when these resistors come
from the same manufacturer's batch, their TC tracking will
usually rate at better than 20 ppm/·C.
A Familiar Reaponae
The circuit in Figure 4 exhibits the same 2-pole responsewith heavy output ripple attenuation-as the noninverting
filter in Figure 3. Specifically,
VOUTlloUT = RF/(1 + (R4 + RF)C4p + R4RFC3C4p2).
Here also, R5 = R4 + RF = 200 kO provides the best bias
current compensation.
Whenever an op amp is used as a buffer (as in Figure 3), its
offset voltage and current (±7.5 mV maximum and ±100
nA, respectively, for most inexpensive devices) can cause a
±17.5 mV worst-case output offset. If both plus and minus
supplies are available, however, you can easily provide a
symmetrical offset adjustment. With only one supply, you
can add a small positive current to each op amp input and
also trim one of the inputs.
The LM331 can handle frequencies up to 100 kHz by utilizing smaller-value capaCitors as shown in Figure 5. This circuit increases the current at pin 2 to facilitate high-speed
switching, but, despite these speed-ups, the LM331 's 500
ppml"C TC at 100 kHz causes problems because of switching speed shifts resulting from temperature changes.
Need a Negative Output?
If your FIV converter application requires a negative output
voltage, the circuit shown in Flflure 4 provides a solution
with excellent linearity (±0.003% typical, ±0.01% maximum). And because pin 1 of the LM331 always remains at 0
Voe, this circuit needs no cascade transistor. (Note, howev-
To compensate for the device's positive TC, the LM334
temperature sensor feeds pin 2 a current that decreases
linearly with temperature and provides a low overall temperature coefficient. An Ry value of 30 kO provides first-order
compensation, but you can trim it higher or lower if you need
more precise TC correction.
C,
Vs • 4.6V TO ZOY
O.OI,.f'
1l1li
~
10k
RX
C3
0.1 pF
h
LM331
10011*
VOUT
~I
R4
121< ±llI'
llIINe
C4
I.OZpF
22M
CI
0.001 pF
'Usa stable components wI1h
low temperature coefficients
TL/H/8741-8
FIGURE 4. In ThIs FIV CIrcuit, the Output-Buffer Op Amp DerIves Its
Offset Voltage from the Precision Voltage Source at Pin 2 of the LM331
1245
Detect F~!lCluencl.. Accurately·
responds within abput 20 ms.When the inputtalls from 9
kHz to O.IiI,kHz, however, the output reliPonds only after a
600 ms lag, so utilize thill circuit only in applications that can
tol~rate FIV..C?irc~its' inherent delays and ripples.
Using an FIV converter combined with a comparafor as a
frequency detector is an.c;>bviousappUcation for these deviee$. Bllt when the FN converter is utilized In this way, its
output rippl!il. hampers accurate fr.equency det!ilction,. and
the slow filter, frequency re$POnse causes delays.
If a quick response is not important, though,you can effectively utilize an LM331-based FIV converter to feed one or
more comparators, as shown in Figure 6. For an input frequency drop f~om 1.1 kHz to 0.5 kHz, the .converter's oLttput
Author's Biography'
B6b Pease is'1i staff scientist in the Advanced Linear Integrated Circuit Group at National Semicoriductor Corp.,-Santa Clara, CA. Holder of four patents, he lIamed a BSEE from
MIT. Bob lists tracking abandoned railroad roadbeds and
deslgnihg VIF oonverters as hobbies.
Vs =4.5V .TO 20V
81
6.81. ±1'"
.
'Use stable components with
low temperature coefficients
Cl
330pF
. Ct
LM331
R"---1...-------~
II
~330PF'
RF
l00k*
~~----e---~~~--4~VOUT
~[
Uk,
TUH/8741-9
FIGURE 5. An LM334 Temperatura Sensor Compensates f~r the F/V Circuit's Temperature CoeffiCient
,.
'Use stable components wllh
low temperature coefficients
8••
22M
·2
~I
10k
+V
HI,GH LIMIT
10k
!ill'
+V
-
LOW LIMIT
TL/H/8741-10
FIGURE 6. Combining a VIF Ie with Two Comparators Produces a Slow-Response Frequency Detector
1246
Versatile Monolithic VIFs
Can Compute as Well as
Convert with High
Accuracy
National Semiconductor
Appendix 0
Robert A. Pease
The best of the monolithic voltage-to-frequency (V IF) converters have performance that's so good it equals or exceeds that of modular types. Some of these ICs can be
designed into quite a variety of circuits because they're notably versatile. Along with versatility and high performance
come the advantages that are characteristic of all V IF converters, including good linearity, excellent resolUtion, wide
dynamic range, and an output signal that's easy to transmit
as well as couple through an isolator.
the input voltage. As might be expected, the circuit has a
capacitor, CL, with a sawtooth voltage on it. Generally
speaking, the circuit is a feedback loop that keeps this capaCitor charged to a voltage very slightly higher than the
input voltage, VIN. If VIN is high, CL discharges relatively
quickly through RL, and the circuit generates a high frequency. If VIN is low, CL discharges slowly, and the converter
puts out a low frequency.
When CL discharges to a voltage equal to the input, the
comparator triggers the one-shot. The one-shot closes the
current switch and also turns on the output transistor. With
the switch closed, current from the current source recharges CL to a voltage somewhat higher than the input. Charging continues for a period determined by RT and CT. At the
end of this period, the one-shot returns to its quiescent state
and CL resumes discharging.
One of the recently introduced monolithic types, the LM 131,
has both high performance and a design that's rather flexible. For instance, it can compute and convert at the same
time; the computation is a part of the conversion. Among
other functions, it can provide the product, ratio and square
root of analog inputs.
This IC has an internal reference for its conversion circuitry
that's also brought out to a pin, so it's available to external
circuits associated with the converter. Not surprisingly, it
turns out that any deviations of the reference, due to process variations and temperature changes have equal and
opposite effects on the scale factors of the converter and
the external circuitry. (This presumes, of course, that the
scale factor of the external circuitry is a linear function of
voltage.)
ReSistor Rs sets the amount of current put out by the current source. In fact, the current in pin 1, with the switch on,
is identical to the current in pin 2. The latter pin is at a
constant voltage (nominally 1.90V), so a given resistor value
can set the operating currents. When connected to a high
impedance buffer, this pin provides a stable reference for
external circuits.
The open-collector output at pin 3 permits the output swing
to be different from the converter's supply voltage, if the
load circuit requires. The supplies don't have to be separate, however, and both the converter and its load can use
the same voltage.
PRECISION RELAXATION OSCILLATOR
Before looking at some applications, quickly take a look at
the basic circuit of an LM131 V/F converter (Figure 1). Basically, this IC, like any V IF converter, is a precision relaxation
oscillator that generates a frequency linearly proportional to
Vs
1.9V-4--~--.J~
TUH/8742-1
FIGURE 1. A voltage-to-frequency converter such as this Is a relaxation OSCillator with a frequency proportional
to the input voltage. Current pulses keep CL'S average voltage slightly greater than the Input voltage.
Reprinted from ELECTRONIC DESIGN-December 8, 1978 @ 1979 Hayden PubllsNng Co" Inc,
1247
,',§TEADVA'S SHE GOES
,By f~rtlie simplest of the circuits that make use of the refer,ence q,mpot voltage from the LM131 is one that simply ties
thi~ o~tp~,pin right back to the signal input. This connection
'is just V IF converter with a constant input, which makes it
a constant-frequency oscillator. Even with this simple circuit
(Figure 2), variations in the reference voltage have two opposite effects that cancel each other out, so the circuit is
particularly stable. In this type of circuit, the temperature-dependent ,internal delays tend to cancel a,S well, which isn't
,trlle of', relaxation oscillators based on op,amps or comparators.
Resistors RL ,and Rs are !Jest taken from the same batch.
(Ai. must belai"ger than Rs, 'SO it's made up of tw<:l rE!sistors.) By ,dOing this, the tempco trackjng, which is the critical
parameter, is five to ten times better than it would be if RL
were a Single 3Q.l kO rE;lsistor.
Although the reference output, pin 2, can't be loaded with·
out affecting the converter's sensitivity;thEicomparator input, pin 7, has a high impedance so this connection does no
harm.
a:
vso-....._ ....-,
fOUT = 1.90V
1.90V
x !:!!!'x _'_1_,
RL
1
= 2.2
CL
Z
,10
1,1 RTOr
,
RM
xpr
'stlible component~ with
, I'ow tempco
Frequency stability is typically ±25 ppml'C, even with an
LM331, which as a V/F converter is specified only to 150
ppm/'C'maximum. From 20 Hz to 20 kHz, stability is excellent, and the circuit can generate frequencies up to 120 kHz.
Although the simplest way of using the reference output is
, to tie it back to the input, the reference can also be buffered
and amplified to supply such external circuitiy as a resistive
transducer, which might be a strain gauge or a pot (Figure
3). As in the stable oscillator already described, 'deviations
of the internal, reference voltage from the ideal cause the
transducer's and the converter's sensitMties to change
equally in oppOSite directions, so the effects cancel.
In this circuit, op amp A2 buffers and amplifies the constant
voltage at pin 2 of,the converter to provide the 5V excita~ion
for the strain gauge. Amplifier A 1, connected as an instrumentation amplifier, raises the output of the'strain gauge to
a 'usable level while rejecting common-mode pickup:
A potentiometer-type transducer works just as well with this
circuit. Its wiper output takes the place of A l's output as
shoWn at the X.
'
The reference terminal is both a constant voltage output
and a current programming input. So far, it's been shown
simply with one or two resistors going to ground. It is, however, a full-fledged signal input that accepts a signal from a
current source quite well.
TL/H/8742-2
FIGURE 2. A VIF converter Is a stable-frequency
oscillator If Its Input Is connected to Ita reference
output. If the reference voltage 'changes, the
'effects of the 'change cancel out, so the frequency
doesn't change. With low tempco components for'RT
and CT, frequency stability vs temperature can be
as good as ± 25 ppmrC.
Vs
VL
IVT020V
'Stable components wi1h low tempco
Al should have low offset; LM308A, 1/2 LM358A, LF351
22k
a, or similar
A2: General purpose, such as LF351 , 1/2 LM358A or LM741
r-_________r-_______...____...;.._ _-=&.8V~_I_--_+--OU-TP-U-T--~---..,
I
I
Ulk
±1"·
I
hI
I
I
I
I
II
3O.1k*
POT
IN
~"Dl.F'
LM131/LM331
REF
I
I
2
I,BV
12.n.*
I
I
IL _______________
lpF
11k"
I.F
4ft"
41
.....- ....
1...----------~----+___4_----+_-
- _ + -.....-
.................
-=,
'
,
"
',
TLlH/8742-3
FIGURE 3. III thl" straln-to-frequenc:y converter, the co"verter's reference excites the streln gauge (or the optional pot)
through buffer amp A2. This makes the circuit Insensitive to changes In the reference voltage.
,1248
linearity and accuracy. The trim circuit in Figure 5a needs
stable positive and negative supplies for the offset trimmer,
while the one in Figure 5b needs only a stable positive supply. Unmarked components in Figure 5b are the same as in
This extra input is what enables the LM131 to compute
while converting. For instance, it will convert the ratio of two
voltages to a frequency proportional to the ratio (F/{Jure 4).
The circuit is still a V IF converter, but has two signal inputs,
both of them going to rather unorthodox places at that. The
inputs, shown as voltages, are converted to currents by two
current pumps (voltage-to-current converters). Of course, if
currents of the proper ranges are available, the current
pumps aren't needed. The left current pump, which includes
01 and A1, determines how fast capacitor CL discharges
between output pulses. The other pump sets the current in
the reference circuit to control the amount of recharge current when the one-shot fires. Tying the comparator input,
pin 7, to the reference pin sets the comparator's trip point at
a constant voltage.
'Stable components w~h low tempco
Figure5a.
DV~'"
CURRENT
OUTPUT
lao".
FUU.acALE
Va
a
A1. A2 should have low offset and low bias
current: LM351 B. LM358A, LF353B, or similar
01, 02: 2N3565, 2N2484, or similar high /3
TLlH/8742-5
R1, R2, R3: Stable componenls
w~ low tempco
01:
/3:> 330
LM331
CL
TO.1/oiF
VL
I'I
ISO
liZ
•.'"F~
VI
IYTO -IOV
b
TL/H/8742-6
FIGURE 5. These current pumps adapt the converter
circuits in Figures 4 and 6to positive input voltages.
Optional offset trimming Improves linearity and
accuracy, especially with input signals that have a
wide dynamic range.
Note that the full-scale range of the current pumps can be
changed by varying the value of the input resistor(s). If either of these pump circuits is used with a single positive
supply, the op amp should be a type such as 1/2 LM358 or
1/4 LM324, which has a common-mode range that includes
the negative-supply bus.
'='
OUTPUT
COMPUTING SQUARE ROOTS IMPLICITLY
An analog divider computes the square root of a signal
when the signal is fed to the divider's numerator input, and
the output is fed back to the divider's denominator input.
vz
I.1VTO-IDV
TLlH/8742-4
FIGURE 4_ This circuit converts the ratio of two
voltages to an equivalent frequency without a
separate analog divider. Full-scale output
Is 15 kHz. The two op amp circuits convert the
Inputs to proportional currents.
To get an idea of how the circuit works, consider first the
effect of, for instance, tripling the input voltage, V1. This
make CL discharge to the comparator trip point three times
as fast, so the frequency triples. Next, consider a given
change, such as doubling the voltage at the other input, V2.
This doubles the recharge current to CL during the fixedwidth output pulse, which means CL'S voltage increases
twice as much during recharging. Since the discharge into
01 is linear (for V1 constant), it takes twice as long for CL to
discharge-the frequency becomes half of what it was before.
Although the current pumps in Figure 4 must have negative
inputs, rearranging the op amps according to Figure 5
makes them accept positive inputs instead. Trimming, out
the offset in the op amp gives the ratio converter better
OUT=~
OUT
OUTPUT
OUT:!
= IN
OUT
= -,
l,/
BUFFER
AMP
I
I
l1 :I
4:.J
:. TRANSDUCER
1
~
Tl/H/8742-IO
1251
ROOTLOOPCOMPU~
As a sign of this condition, when the converter hangs up,
the one-shot's timing node, pin 5, continues to charge well
beyond its normal peak of 2/3 Vs. As soon as the comparator A2 detectS this rise, it pulls up voltage Vx, current 11
increases, and the loop catches its breath again.
.
After all these nonlinear computations, this last circuit is
about as linear as it can be. It's a precision,ultralinear V/F
converter based on an LM331A (Figure 8) that has several
detail refinements over previous VIF converter circuits.
Choosing the proper components and trimming the tempco
give less than 0.02% error and 0.003% nonlinearity for a
± 20"C range around room temperature.
This cjrcuit has an active Integrator, which includes the op
amp and the integrating feedback capaCitor, CF. The integrator converts the input voltage, which is negative, into a
positive-going ramp. When the ramp reaches the converter
IC's comparator threshold, the one-shot fires and switches
a pulse of current to the integratQr's summing junction. This
current makes the integrator's output ramp down quickly.
When the one-shot times out, the cycle repeats.
There are several reasons this converter ci~it gives high
performance:
• A feedback limiter prevents the op amp from driving pin 7
of the LM331A negative. The limiter circuit arrangement
bypasses the leakage through CR5 to ground via R5, so
it won't reach the summing junction. Bypassing I~akage
this way is especially important at high temperatures.
• The offset trimming pot is connected to the stable 1.9Y
reference at pin 2 instead of to a power supply bus that
. might be unstable and noisy.
The circuit in Figure 7 IS an implicit loop (see "CompUting
Square Roots Implicitly") that uses IC1 as a voltage·to-frequency converter and divider, and IC2· as a frequency-tovoltage converter. The FIV converter, IC2, and the current
pump that includes A1 and the transistor return the output of
IC1 to its denominator input A relatively elaborate feedback
circuit like this is needed to convert IC1's frequency output
back to a current for its denominator input.
Looking at the circuit in more detail, IC1 puts out a frequency proportional to VIN divided by the feedback voltage, Vx.
The current 11 is generated by a current pump that has Vx
as its input (Figure 58). To develop the feedback IC2 converts the pulse output from IC1 into standard width precision
current pulses that charge capacitor C1. This capacitor integrates them into the voltage Vx, thus cloSing the loop.
Op amp A2, serving as a comparator, ensures that the circuit will always start and continue running. If VIN suddenly
Jumps to a higher voltage, one pulse from the one-shot in
IC1 may not be enough to recharge CL to a voltage higher
than the input. In such a case,the IC's internal logic keeps
its internal current switch turned on, and the voltage on CL
ramps up until it exceeds the input. During this time, however, IC1's output hasn't changed state. (Such a temporary
hang-up isn't. unique to this circuit, and equivalent things
happen to other V/Fs besides the LM131/LM331.) What is
worse here, though, is that the lack of pulses to IC2 means
that Vx and 11 decay. The recharging current, 12, is the same
as 11, so it not only becomes progressively harder for the
voltage on CL to catch up with the input, it may even fail to
catch up entirely if (12 x Ru is less than the input voltage.
Vs
I.V
VlF
CONVERTER
Ry
RT
1.81h·
ovro
rdU
lOOk
I.FT
ICI
lM331
1.11k*
-:r:
l'
11 • F'
Cr
&.01.F·
O.oI.F
p
Cl
I.F
'='
10k
l-
I
I
I
I
I
I 1...7
I
'Stable components with low tempco
AI, A2: 1/2 LM 358 or 1/2 LF353
Full·scale ou1put: 10 kHz
2211
I
I
I
I
Cl
I.F
'='
1.8111 .F
'='
TUH/8742-11
FIGURE 7. Two converter ICs generate an output frequency proportional to the square root of the Input voltage. The
Circuit Is an Implicit loop In which IC1aerves as a divider and V/F converter. ThlslC's output goes back to Its
denominator Input through F/V converter IC2 to make the circuit output equal the Input'. square root.
1252
Vs
13k
R3
12.1k*
1010
•
10k
~~~~~~--~6-~C~
RX
LIi331A
431JkNOM
CTRIMI
CRI
CRZ
12.1k*
6k'
SCALE
FACTOR
TRIll
3
T
RZ
CR3
":'
Uk
":'
OJl1l5tlpF -
OUTPUT
z.zk
RS
1
R4
1M
I'
":'
VIN
DV TO -10V
fOUT -
VIN
RS
1
2.09V
X R1 X RS Or
Full-scale output 10 kHz
'Stable components with low tampeo; see text
Or is Teflon or Polystyrene
All diodes 1N4S7. 1N484. or FD333 (Iow-Ieakege silicon)
TL/H/8742-12
FIGURE 8. An ultrapreclslon V /F converter, capable of beHer than 0.02% error and 0.003% nonlinearity for a
± 20"C range about room temperature, augments the basic converter with an external Integrator.
When doing a second round of trimming, though, note that a
resistor of, say, 4.3 MO, has about the same effect on tempco when shunted across a 220 kO resistor that it does when
shunted across one of 430 kO, namely, -11 ppml"C. This
technique can give tempeos below ± 20 ppml"C or even
±10 ppml"C.
• A small fraction (1S0 IJ.V, full-scale) of the input voltage
goes via R4 to the Rs network, which improves the nonlinearity from 0.004% to 0.002%.
• Resistors R2 and R3 are the same value, so that resistors such as Allen-Bradley type CC metal-film types can
provide excellent tempco tracking at low cost. (This
tracking is very good when equal values come from the
same batch.) Resistor R1 should be a low tempco metalfilm or wirewound type, with a maximum tempeo of
± 10 ppml"C or ± 25 ppml"C.
Some precautions help this procedure converge:
1. Use a good capacitor for CT. The cheapest polystyrene
capacitors will shift in value by 0.05% or more per temperature cycle. The actual temperature sensitivity would
be indistinguishable from the hysteresis, and the circuit
would never be stable.
In addition, Cr should be a polystyrene or Teflon type. Polystyrene is rated to SO°C, while Teflon goes to 150"C. Both
types can be obtained with a tempco of -110 ± 30 ppml"C.
Choosing this tempco for Cr makes the tempco, due to Cr,
of the full-scale output frequency 110 ppm/DC.
Using tight tolerance components results in a total tempco
between 0 ppm/DC and 220 ppm/DC, so the tempeo will
never be negative. The voltage at CR1 and Rx has a tempco of -6 mVI"C, which can be used to compensate the
tempco of the rest of the circuit. Trimming Rx compensates
for the tempco of the V /F IC, the capacitor, and all the
resistors.
A good starting value for selecting Rx is 430 kO, which will
give the 135 IJ.A flowing out of pin 2 a slope of 110 ppm/DC.
If the output frequency increases with temperature, a little
more conductance should be added in parallel with Rx.
2. After soldering, bake and/or temperature-cycle the circuit
(at a temperature not exceeding 75°C if Cr is polystyrene)
for a few hours, to stabilize ali components and to relieve
the strains from soldering.
3. Don't rush the trimming. Recheck the room temperature
value, before and after the high temperature data are taken, to ensure that hystereSis per cycle is reasonably low.
4. Don't expect a perfect tempco at - 25°C if the circuit is
trimmed for ± 5 ppml"C between 25°C and 60"C. If it's
been trimmed for zero tempco while warm, none of its
components will be linear to much better than 5 ppml"C
or 10 ppm/DC when it's cold.
The values shown in this circuit are generally optimum for
± 12V to ± 16V regulated supplies but any stable supplies
between ±4Vand ±22V would be usable, after changing a
few component values.
1253
_National
Semiconductor
"
APPENDIX H: Standard Resistance Values
The standard 1 % (and %%) resistor values are recommended for ease of design and for best availability when designing
precision analog circuits.
Standard Resistance Values for t.... 10·t0-100 OeC:ade
R.slstance Tolerance (+ %)
0.1
0.25
0.5
10.0
10.1
10.2
10.4
10.5
10.6
10.7
10.9
11.0
11.1
11.3
11.4
11.5
11.7
11.8
12.0
12.1
12.3
12.4
12.6
12.7
12.9
13.0
13.2
13.3
13.5
13.7
13.8
14.0
14.2
14.3
14.5
1
10.0
-
10.2
-
10.5
-
10.7
11.0
-
11.3
-
11.8
12.1
12.4
12.7
-.
13.0
13.3
13.7
14.0
14.3
11.8
2
5
0.1
0.25
0.5
1
-
-
-
-
14.7 14.7
14.9
15.0 15.0
15.2
15.4 15.4
15.6
15.8 15.8
16.0
11 . 16.2 18.2
16.4
16.5 18.S·
16.7
16.9 18.8
17.2
17.4 17.4
12 17.6
17.8 1'7.8
18.0
18.2 18.2
18.4
18.7 18.7
18.9
13 19.2 UM.
. 19.3
19.6 18.8
19.8
20.0 ' 20.0
20.3
' - 20.5 20.S
20.8
21.0 21.0
21.3
10
-
-
-'
-
-
-
-
2
5
-
-
-
15
-
-16
18
20
-
0.1
0.25
0.5
21.5
21.8
22.1
22.3
22.6
22.9
23.2
23.4
23.7
24.0
24.3·
24.6
24:9
25.2
25.5
25.8
26.1
26.4
26.7
27.1
27.4
27.7
28.0
28.4
28.7
29.1
29.4
29.8
30.1
30.5
30.9
31.2
1
2
5
21.5
-
- 22.1 -
22.8
22
-
23.7 - 24
23.2
24.3
'-
24.8
-
2S.5
28.7
28.1
27.4
.,...
28.0
-
28.7
-
28.4
30.1
-
30.8
-
-
27
30
-
0.1
0.25
0.5
,31.6
32.0
32.4
32.8
33.2
33.6
34.0
34.4
34.8
35.2
35.7
36.1
36.5
37.0
37.4
37.9
38.3
38.8
39.2
39.7
40.2
40.7
41.2
41.7
42.2
42.7
43.2
43.7
44.2
44.8
45.3
45.9
1
"
2,
5
32.4
-
33.2
33
31.8
-
-
-
34.0
34.&
-
3S.7
-
38.5
-
37.4
-
38.3
38.2
-
40.2
..,-
41.2
-
42.2
44,.2
45.3
43.2
-
36
-
-
-
39
-
-
43
-
-
0.1
0.25
0.5
46.4
47.0
47.5
48.1
48.7
49.3
49.9
50.5
51.1
51.7
52.3
53.0
53.6
54.2
54.9
56.6
56.2
56.9
57.6
58.3
59.0
59.7
60.4
61.2
61.9
62.6
63.4
64.2
64.9
65.7
66.5
67.3
1
2
5
48.4
-
47.5
-
48.7
-
48.8
- ..51.1 51
- 82.3 - 83.8 - 84.8 - '
88.2
,-
87.8
88.0
1254
56
-
-
80.4 - 81.8 62
- 63.4 - 84.8 68.5
- -
S~ard Resistance Values are obtained from the Decade Table by multiplying by multiples of
represent 1.210, 12. to, 1210, 1.21 kO, etc.
47
-
0.1
0.25
0.5
68.1
69.0
69.8
70.6
71.5
72.3
73.2
74.1
75.0
75.9
.76.8
77.7
78.7
79:6
80.6
81.6
82.5
83.5
84.5
85.6
86.~
87'.6
88.7
89.8
"90.9
92.0
93.1
94.2
,95.3
96.5
97.6
98.8
1
2
5
8a.1
68
-
88.a
-
71.5
73.2
75.0
-
75
- 78.8 - 78;7 80.8 - 82.S 82
- 84.S 88.8 - 88.7 .80.8 91
- 83.1 - 85.3 - .,....
,~
87.8.
-
-
10. As an example, 12.1 can
Based on the EDN Series, with 20% NEW material
Troubleshooting
Analog Circuits
Robert A. Pease, National Semiconductor
Don't understand analog troubleshooting? Relax.. Bob Pease does.
Based on his immensely popular series in EON, but with a wealth of new
material, this book covers all his "battle-tested" methods. It includes:
• advice on using simple equipment to troubleshoot
• plenty of step-by-step procedures that "walk you through"
analog troubleshooting methods
• generous helpings of Bob's unique insights, humor, and
philosophy regarding analog circuits
May 1991
208pp.
cloth
99 illus.
0750691840
$32.95
to order today, call
the EON Series
for
Design Engineers
1-800-366-2665
M-F 8:30-4:30 ES. T.
BUTTERWORTH- HEINEMANN
80 Montvale Ave., Stoneham, MA 02180
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