1994_Philips_Desktop_Video 1994 Philips Desktop Video
User Manual: 1994_Philips_Desktop_Video
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INTEGRATED CIRCUITS
Desktop Video Data Handbook
. Philips Semiconductors
PHILIPS
Cover art by Joe Kelly.
Moby Dick, the tale of a deranged whaling captain's obsessive voyage to find and
destroy the great white whale that had ripped off his leg, is at once an exciting sea
story, a sociological critique of various American class and racial prejudices, a
repository of information about whales and whaling, and a philosophical inquiry into
the nature of good and evil, of man and his fate. And it is three pages shorter than
the Philips Semiconductors 1994 Desktop Video Data Handbook.
Although it is now considered among the greatest of all novels, Moby Dick was
ill-received and poorly understood at the time. Herman Melville, its author, died in
poverty and obscurity in 1891.
No endorsement of contemporary whaling practices is intended by the allegorical
cover art.
No animals, virtual or otherwise, were injured in the creation of the cover.
Desktop Video Data Handbook
CONTENTS
page
SECTION 1
GENERAL INFORMATION
1-3
SECTION 2
APPLICATION NOTES AND MATERIALS
2-3
SECTION 3
FUNCTIONAL INDEX OF PRODUCTS
3-3
SECTION 4
PACKAGE OUTLINES
4-3
SECTION 5
NORTH AMERICAN SALES OFFICES,
REPRESENTATIVES, AND DISTRIBUTORS
5-3
DATA HANDBOOK SYSTEM
A-1
APPENDIX A
DEFINITIONS
Data Sheet
Identification
Product Status
Objective Speclflclllion
Formative or In Design
This data sheet contains the design target or goal specHications for
product development. Specifications may change in any manner
without notice.
Preliminary Specification
Preproduction Product
This data sheet contains preliminary data, and supplementary data
will be published at a later date. Philips Semiconductors reserves the
right to make changes at any time without notice in order to improve
design and supply the best possible product.
Product Specification
Full Production
Definition
This data sheet contains Final Specifications. Philips
Semiconductors reserves the right to make changes at any time
without notice, in order to improve design and supply the best
possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make
changes, without notice, in the products, including circuits, standard cells, and/or software, described
or contained herein in order to improve design and/or performance. Philips Semiconductors assumes
no responsibility or liability for the use of any of these products, conveys no license or title under any
patent, copyright, or mask work right to these products, and makes no representations or warranties
that these products are free from patent, copyright, or mask work right infringement, unless otherwise
specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation PrOducts are not designed
for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors
and Philips Electronics North America Corporation Product can reasonably be expected to result in a
personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers
using or selling Philips Semiconductors and Philips Electronics North America Corporation Products
for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors
and Philips Electronics North America Corporation for any damages resulting from such improper use
or sale.
Philips Semiconductors and Philips Electronics North America Corporation register
eligible circuits under the Semiconductor Chip Protection Act.
© Copyright Philips Electronics North America Corporation, 1994
Our appreciation is extended to the following persons for their assistance in the publication
of the Desktop Video Handbook:
To: all the Philips factory representatives who supplied updated data sheets at short notice.
also to:
Herb Kniess
Marc Schneider
Leo Warmuth
Joanne Puma
Celia Tippit
George Ellis
Steve Solari
Joe Kelly
Application notes
Application notes
Application notes
Layout
Compilation and Editing
Compilation, Editing, and Application notes
Concept
Cover Art
All rights reserved.
Printed in U.S.A.
Desktop Video Products
Table of Contents
Section 1 - General Information
Digital video now, an introduction .....................................................................................
Application configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pro Electron type designation code for integrated circuits ................................................................
Handling MOS devices ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
High-performance 8-bit video data converters ..........................................................................
Line-locked digital colour decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN ETV/IR89126
Digital interfaces for component video signals .....................................................
Encoding parameters of digital television for studios .............................. . . . . . . . . . . . . . . . . ..
CCIR REC. 601-2
RECOMMENDATIONS OFTHE CCIR, 1990 ......................................................
CCIR 656
Color space, digital coding, and sampling schemes for video signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Video signal bandwidth/resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TV transmission standards; colour systems ........................... ;................................................
International TV systems and standards ...............................................................................
Contact addresses ..................................................................................................
Video glossary .....................................................................................................
Alphanumeric index of products ......................................................................................
1-3
1-6
1-11
1-13
1-14
1-22
1-29
1-39
1-49
1-63
1-67
1-68
1-69
1-73
1-74
1-76
Section 2
DPC7110
Video capture card (24/16-bit) with display filter .................................. . . . . . . . . . . . . . . . . .. 2-3
DPC7116SD
Video to PCI demo board ....................................................................... 2-17
Clock and synchronization signals of SAA7187 and SAA7188: Application note for digital video encoder ........................ 2-30
DTV7188A
Evaluation board for SAA7188A encoder .......................................................... 2-48
DTV9051
Digital video evaluation module ........................................... . . . . . . . . . . . . . . . . . . . . . .. 2-54
DTV7199 Digital Television Demonstration System ...................................................................... 2-68
SAA7199B operational modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-93
DTV7194/96
Desktop video demo board ...................................................................... 2-103
Crystal specifications ............................................................................................... 2·139
TDA8708 black level and gain modulation circuit ........................................................................ 2-140
TDA9141 analog decoder application .................................................................................. 2-143
Digital video evaluation board ........................................................................................ 2-149
CVBS output filter for SAA7199B encoder .............................................................................. 2-157
SAA 1101 sync generator application .................................................................................. 2-162
The 12C-bus and how to use it (including specification) ................................................................... 2-163
12C bus addresses .................................................................................................. 2-182
12C parallel printer port adaptor ....................................................................................... 2-183
Interfacing the PCF8584 12C-bus controller to 80C51 family microcontrollers ........................... 2-184
AN425
What is Teletext? ................................................................................................... 2-204
Packet and Page Teletext data reception using the SAA5250 ............................................................. 2-213
June 1994
iii
Section 3
Analog-to-digital conversion
Analog-to-digital converter selection guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .
TDA8703
8-bit high-speed analog-to-digital converter. . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .
3-3
3-790
TDA8706
TDA8707
TDA8708A
3-803
3-813
3-825
3-842
3-859
3-878
3-893
3-908
3-924
TDA8708B
TDA8709A
TDA8712; TDF8712
TDA8714
TDA8716
TDA8718
TDA8755
TDF8704
TDA8758
TDA8760
6-bit analog-to-digital converter with multiplexer and clamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Triple RGB 6-bit video analog-to-digital interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video analog input interface ......................................................................
Video analog input interface .............................................. , ...................... .
Video analog input interface ..................................................................... .
8-bit digital-to-analog converters ................................................................. .
8-bit high-speed analog-to-digital converter ........................................................ .
8-bit high-speed analog-to-digital converter ........................................................ .
8-bit high-speed analog-to-digital converter ........................................................ .
YUV 8-bit video low-power analog-to-digital interface ................................................ .
8-bit high-speed analog-to-digital converter ........................................................ .
YC 8-bit low-power analog-to-digital video interface ................................................. .
1O-bit high-speed analog-to-digital converter ........ ; .............................................. .
3-933
3-1033
3-948
3-963
Auxiliary functions
PCF8574/PCF8574A
PCF8584
SAA1101
SAA5252
TDA2595
TDA4670
TDA4680
TDA4686
TDA4820T
TDA8444/ATIT
Remote 8-bit I/O expander for 12C-bus ............................................................ .
12C-bus controller .............................................................................. .
Universal sync generator (USG) .................................................................. .
Line twenty-one acquisition and display (LiTOD) ..................... ; .............................. .
Horizontal combination ........................ '.' ................................................ .
Picture signal improvement (PSI) circuit ........................................................... .
Video processor with automatic cut-off and white level control ........................................ .
Video processor, with automatic cut-off control ..................................................... .
Sync separation circuit for video applications ....................................................... .
Octuple 6-bit DAC with 12C-bus ...................................... ; ........................... .
TDA8446; TDA8446T Fast RGBIYC switch for digital decoding ...........................................................
TDA8540
4 x 4 video switch matrix .................... . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5
3-16
3-41
3-100
3-644
3-675
3-685
3-701
3-717
3-722
3-731
3-763
Analog color decoding
TDA3566A
TDA4665
TDA8501
TDA9141
PALINTSC decoder
Baseband delay line .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PALINTSC encoder .............................................................................
PALINTSC/SECAM decoder/sync processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-651
3-669
3-738
3-1010
Color decoding, encoding and clock ICs (digital)
SAA7110
SAA7151B
SAA7157
SAA7183
SAA7187
SAA7188A
SAA7191B
SAA7194
SAA7196
SAA7197
SAA7199B
SAA9051
SAA9057B
June 1994
One Chip Frontend 1 (OFC1) .................................................................... .
SAA7110 programming example ................................................................. .
Digital multistandard colour decoder with SCART interface (DMSD2-SCART) ........................... .
Clock signal generator circuit for digital TV systems (SCGC) ......................................... .
Digital video encoder (square pixel with Macrovision) ............................................... .
Digital video encoder (DENC2-SQ) ............................................................... .
Digital video encoder (DENC2-M) ................................................................ .
SAA7188A programming example ................................................................ .
Digital multistandard colour decoder, square pixel (DMSD-SQP) ...................................... .
Digital video decoder and scaler circuit (DESC) (short-form data sheet) ................................ .
Digital video decoder, scaler, and clock generator (DESCPro) ........................................ .
Clock signal generator circuit for Desktop Video systems (SCGC) ..................................... .
Digital video encoder, GENLOCK-capable ......................................................... .
Digital multistandard TV decoder ................................................................. .
Clock signal generator circuit for Digital TV systems (CGC) .......................................... .
iv
3-120
3-184
3-202
3-252
3-302
3-332
3-359
3-385
3-387
3-454
3-457
3-511
3-517
3-575
3-619
Digital-to-analog conversion
Digital-to-analog converter selection guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAA7165
Video enhancementand D/A processor (VEDA2) ....................................................
SAA7169
35 MHz triple 9-bit DIA converterfor high-speed video ................................................
SAA9065
Video enhancement and D/A processor (VEDA) .....................................................
TDA8702
8-bit video digital-to-analog converter ..............................................................
TDA8771
Triple 8-bit video digital-to-analog converter. . .. .. . . . .. . . . . .. . .. .. . . .. . . . . . . . . . .. . .. .. . . .. .. .. . .. . . ..
TDA8772; TDA8772A Triple 8-bit video digital-to-analog converter. . .. .. . . . .. . . . . .. . .. .. . . .. . . . .. . . . . .. . .. .. .. .. .. .. . . . . . . .
3-4
3-276
3-295
3-626
3-776
3-984
3-996
Digital video processing
SAA7116
SAA7152
SAA7164
SAA7186
SAA7192A
Digital video to PCI interface .. . . .. .. . .. . . .. .. . . . .. .. . . .. .. . . . .. . . .. . . . . . .. . . . . . .. .. . . . . . . . . . . . .. . .
Digital video comb filter (DCF) ....................................................................
Video enhancement and D/A processor (VEDA3) ............ . .. .. .. . . .. . . . .. . . . . .. . .. . . . . . . . . . . . .. . .
Digital video scaler ............................................................... . . . . . . . . . . . . . . .
Digital colour space converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-185
3-243
3-258
3-303
3-418
Teletext video processor .........................................................................
Teletext video processor .........................................................................
Interface for data acquisition and control (for multi-standard teletext systems) ...........................
Single chip economy 10 page teletexVTV microcontroller .............................................
Multi-standard Teletext IC for standard and features TV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-52
3-58
3-69
3-114
3-549
Plastic dual in-line package; 16 leads (300 mil) .................................................... ..
8-Pin Plastic SOL (Small Outline Large) Dual In-Line (DfT) Package .................................. .
24-Pin Plastic Dual In-Line (NIP) Package with Internal Heatspreader ................................. .
18-Pin Plastic Dual In-Line (NIP) Package with Internal Heatspreader ................................. .
16-Pin Plastic SO (Small Outline) Dual In-Line (DfT) Package ........................................ .
Plastic dual in-line package; 28 leads (600 mil) with internal heat spreader ............................. .
40-Pin Plastic Dual In-Line (NIP) Package ......................................................... .
Plastic small outline package; 28 leads; large body ................................................. .
Plastic small outline package; 24 leads; large body ................................................. .
20-Lead Dual In-Line; Plastic .................................................................... .
40-Pin Plastic VSO (Very Small Outline) Dual In-Line (DfT) Package .................................. .
Plastic small outline package; 16 leads; large body ................................................. .
20-Lead Mini-pack; Plastic ...................................................................... .
44-Pin Plastic Leaded Chip Carrier; Pocket Version (A) Package ..................................... .
68-Pin Plastic Leaded Chip Carrier; Pocket Version (A) Package ..................................... .
84-Pin Plastic Leaded Chip Carrier (A) Package .................................................... .
160-Pin Plastic Quad Flat Pack (H) Package ....................................................... .
32-Pin Plastic Shrink Dual In-Line (NIP) Package ................................................... .
24-Lead Plastic Shrink Dual In-Line Package ...................................................... .
52-Pin Shrink Dual In-Line Package; Plastic ....................................................... .
Plastic leaded chip carrier, 28 leads ............................................................... .
Plastic small outline package; 32 leads; large body ................................................. .
44-Pin Plastic Quad Flat Pack (8) Package ........................................................ .
Plastic thin quad flat package; 48 leads; 7 x 7 x 1.4 mm ............................................. .
100-Pin Plastic Quad Flat Pack (8) Package ...................................................... ..
80-Pin Plastic Quad Flat Pack (8) Package ....................................................... ..
Plastic shrink small outline package; 24 leads; medium body ......................................... .
120-Pin Plastic Quad Flat Pack (8) Package ....................................................... .
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
Teletext
SAA5191
SAA5231
SAA5250
SAA5296
SAA9042
Section 4
SOT38-1
SOT96A
S0T101
SOT102
SOT109A
SOT117-1
SOT129
SOT136-1
SOT137-1
S0T146EF4
S0T158A
SOT162-1
SOT163AG7
SOT187
SOT188AA
SOT189CG
SOT225
SOT232
SOT234AG
SOT247-1
SOT261-2
SOT287-1
SOT307-2
SOT313-2
SOT317
SOT318
SOT340-1
SOT349
Section 5
Sales Offices, Representatives & Distributors ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-3
Appendix A - Data Handbook System ....................................................................
June 1994
v
A-1
Desktop Video Products
Section 1
General Information
CONTENTS
Digital video now, an introduction .............................. . . . . . . . . . . . . . . . . . .
Application configurations ......................................................
Pro Electron type designation code for integrated circuits ...........................
Handling MOS devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . ..
High-performance 8-bit video data converters .....................................
Line-locked digital colour decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN ETVIIR89126 Digital interfaces for component video signals .. . . . . . . . . . . . . . . . . ..
CCI R REC. 601-2 Encoding parameters of digital television for studios ..............
CCIR 656 RECOMMENDATIONS OF THE CCIR, 1990 ...........................
Color space, digital coding, and sampling schemes for video signals .................
Video signal bandwidth/resolution ...............................................
TV transmission standards; colour systems .......................................
International TV systems and standards ........................ . . . . . . . . . . . . . . . . ..
Contact addresses ............................................................
Video glossary .......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Alphanumeric index of products .................................................
1-3
1-6
1-11
1-13
1-14
1-22
1-29
1-39
1-49
1-63
1-67
1-68
1-69
1-73
1-74
1-76
Philips Semiconductors Video Products
Digital video now, an introduction
CCIR601
In the old days, if you wanted to see video, you turned to your
television set. Nowadays, video is popping out all over--on PCs,
workstations, teleconferencing gear, and a spate of medical and test
equipment.
CCIR601 is an internationally established standard for digitizing
PAL, NTSC, and SECAM. This standard is frequently called D1 in
the U.S.
WHY?
We offer a chip set that is 100% compatible with this standard, as
well as other chip sets that address different market requirements.
Because humans live in a real-time, natural color world that
machines are just catching up with. Video enhances the
effectiveness of education, training, medical diagnosis, and just
about any attempt to communicate.
y
HOW?
People are using digital video processing ICs from Philips
Semiconductors-Signetics to facilitate the fusion of video and
graphics. Look:
INPUT
PROCESSING
FEATURE
PROCESSING
VIDEO
COMPUTER
GRAPHICS
OUTPUT
PROCESSING
~
VIDEO
"
COMPUTE
GRAPHICS
T
ORTHOGONAL SAMPLING STRUCTURE
Processing in the horizontal (X), vertical (V), and time (T)
dimensions requires that picture elements are in identical positions
in each frame. Philips' unique line-locked-clock implementation
satisfies this requirement.
Unfortunately, this simple diagram hides a host of difficulties,
including differences in scanning schemes, screen refresh rates,
resolution, and color encoding. Fortunately, Philips has been into
televisions since Felix was a kitten, and knows how to deliver video
that looks good, even under adverse conditions.
Examples of video processing include:
• Filtering in the X-direction: bandpass filter.
• Filtering in the V-direction: simple comb filter.
• Filtering in the T-direction: noise reduction.
In the Philips digital video system, the sample clock is synchronized
with the input's sync Signal. An internal discrete time oscillator is
used to demodulate the chroma.
WHAT DO YOU NEED?
The system that you select to decode and digitize your video signal
must meet the following requirements:
• Support for Standards
This concept combines quartz stability with adaptive handling of
video line frequency, and delivers picture elements in each field in
identical positions. After all, nobody wants pixels that deviate.
• Orthogonal Sampling Structure
• Ease of Implementation
It guarantees robust recovery of the video Signal, without jitter,
tearing or loss of color, even under the following adverse conditions:
• Time-base errors from
- VHS or Bmm tape playback
SUPPORT FOR STANDARDS
PAL, NTSC, SECAM
Philips digital video can detect which of the three international
broadcast standards it is receiving and automatically switch to
decode it!
- Videotape shuttle
- Videodisc freezeframe
• Poor signal-to-noise ratio from
- Low signal strength
S-VHS
Industrial applications frequently demand the increased performance
of Super-VHS. Philips digital video can process S-VHS with the
addition of a second analog-to-digital converter to handle the
chrominance channel.
June 1994
X
~
1-3
Philips Semiconductors Video Products
Digital video now, an introduction
With the TDA8708, one can select one of three composite video
signals to input to the system. This IC includes clamping, automatic
gain control, and drive for an extemallow-pass filter. The Signal is
then fed to an internal eight-bit analog to digital converter, and finally
output to the Digital MultiStandard Decoder.
EASE OF IMPLEMENTATION
The Philips digital video system is simple to use:
• No adjustments.
• All 5-volt operation.
• Small form-factor--all parts available in surface mount
• Architecture is partitioned to simplify the addition Of features.
• Digital circuitry is constant, reproducible, and not subject to
manufacturing variations.
• It is not influenced by variations in supply voltage or aging.
• There are no tolerances and therefore no need for circuit
adjustments.
• Digital control is readily implemented via 12C·, without the need for
D/As or other interfaces.
• Digital filters are implemented on-Chip, and offer linear phase
response.
• A single crystal supports different broadcast standards.
Digital MultiStandard Decoder (DMSD)
The DMSD accepts digitized composite video, performs horizontal
and vertical synchronization processing, and outputs Luminance (Y)
and Chrominance (U,V) signals. Via 12C (see glossary), one can
control color hue and luminance frequency response for optimum
performance.
Philips offers four DMSDs:
• SAA9051 for consumer applications:
7-bits; Y:U:V 4:1 :1; 13.5 MHz, 720 pixelslline
• SAA7151 for industrial applications:
8-bits; Y:U:V 4:2:2; 13.5 MHz, 720 pixels/line
• SAA719.1 for computer graphics:
8-bils; Y:U:V 4:2:2; NTSC 12.27 MHz, 640 pixels/line
PAUSECAM 14.75 MHz 768 pixels/line
• SAA7194(6) for computer graphics:
8-bits; Y:U:V 4:2:2; NTSC 12.27 MHz, 640 pixels/line
PAUSECAM 14.75 MHz 768 pixels/line
THE BUILDING BLOCKS:
INPUT PROCESSING
Analog to Digital Converter (AID)
We offer a broad range of high performance AIDs incorporating
Philips' unique folding and interpolation architecture (see glossary).
Two of these are specially configured for the digital video chip set:
the TDA8708 for composite video (CVBS) inputs, and the TDA8709
for chroma inputs in S-VHS applications.
INPUT PROCESSING
NO
VIDE01
Clock Generator Circuit (CGC)
This IC works together with the DMSD to lock to the incoming
signal's sync and generate the necessary system clocks. Philips
offers three CGCs, one for each DMSD.
DMSD
SAA7199
OR
SAA7189
TDA8707
4-.
SOURCE
SELECT,
CLAMP,
AGC,
1-+......
NO
U,V
DIGITAL
ENCODER
CLOCK
GENERATOR
CIRCUIT
SAA7186
SCALER HV
FILTER COLOR SPACE
CONVERTER
MEMORY
S-VIDEO
TRIPLE
DAC
AVP
TDA4680
TDA4684
TDA4686
SAA9065
SAA7165
8
RGB
OR
YUV
ANALOG
YUV
DIGITAL
COMPUTER
GRAPHICS
June 1994
ANALOG RGB
S-VIDEO
H
CGC
OUTPUT PROCESSING
FEATURE PROCESSING
1-4
ANALOG
RGB
Philips Semiconductors Video Products
Digital video now, an introduction
Video Enhancement and D/A processor (VEDA and
VEDA2)
FEATURE PROCESSING
Philips digital video architecture allows the data to be manipulated
and freely shifted in time between input and output. Examples of
processing which could be implemented here include manipulating
the size of the picture, filtering, noise reduction, or data
compression.
The SAA9065 (VEDA) and SAA7165 (VEDA2) accept YUV data
input, upsamples and interpolates and converts the data to analog
YUV signals. Both 7-bit 4:1:1 and 8-bit 4:2:2 data formats are
possible. Both devices can perform aperture correction and the
SAA7165 will perform color transient improvement. Both devices will
run at 30 MHz so that non-interlaced video can be supported.
Digital Color Space Conversion (DCSC)
The SAA7192 digital color space converter connects directly to
either the SAA7151 or SAA7191 DMSD. It accepts the Y:U:V data,
interpolates samples, digitally converts Y:U:V to R:G:B, and
performs inverse gamma correction via an on-chip look-up table. It
outputs R:G:B 8:8:8, which can then be manipulated as computer
graphics, or directly converted into analog red, green, and blue
through a D/A, such as the TDA8702 or SAA7169.
Analog Video Processor (AVP)
The TDA4680;4685 and 4686 include an analog matrix which will
covert analog YUV to analog RGB. These devices also accept
synchronous external analog RGB signals and switch between
these sources at a pixel rate thus allowing overlay capabilities. 12C
control of brightness, contrast and saturation is possible. All three
devices are pin compatible, the TDA4686 has higher throughput
bandwidth.
Digital Video Scaler (DVS)
The SAA7186 digital video scaler connects directly to all Philips 8-bit
decoders (SAA7151 B,SAA7191 B, and SAA7194/6) DMSD.lt
accepts the YUV data, interpolates samples, scales the video
downward to any desired size, filters the scaled video in both the
horizontal and vertical domains and performs digital color space
conversion of the YUV data into several formats of YUV and RGB
video. It also contains an output buffer with handshaking for ease of
interface and an anti-gamma ROM (bypassable).
GLOSSARY
12C Bus
The Inter-Integrated Circuit (12C) Bus is a two line, multi-master bus
developed by Philips to provide cost-effective control of analog and
digital functions among ICs.
12C can simplify the manufacturing process by enabling complete
calibration and test under computer control. Philips offers a large
family of 12C-capable integrated circuits, including microcontrollers,
microprocessors, and audio, video, and telephony ICs.
Digital Decoder and Scaler (DESC)
The SAA7194/6 integrates the functionality of the SAA7191 B digital
decoder, SAA7197 clock generator (SAA7196 only) and the
SAA7186 scaler IC's. Input processing, and feature processing are
integrated into one device.
Folding, Interpolating AIDs
This term describes the unique technology used in Philips' family of
high speed analog to digital converters.
Digital Encoder (DENC)
The SAA7199B (DENC) is a digital video to analog CVBS or
S-Video encoders. This device is multistandard. The 7199B accepts
digital RGB, YUV, 8-bit Indexed and digitized composite video as
inputs. It also features a digital genlock input to aid in synchronizing
the encoding system to other reference sources. The SAA7199 will
simultaneously output CVBS (composite) and S-Video into 75 ohm
loads.
June 1994
Designers are usually forced to choose between the high
performance and high power consumption of bipolar flash AIDs or
the low power consumption and low performance of CMOS AIDs. By
folding comparator inputs and interpolating the outputs, Philips is
able to realize an AID with one quarter the circuitry of a conventional
flash converter. That means high performance AIDs with power
consumption as low as 250 mW. In addition to video, these parts are
enabling new test and medical imaging applications.
1-5
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Figure 3. a-Bit Video Window Graphics with Encoder Gen-Locked to an External Source
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Philips Semiconductors Video Products
Pro Electron type designation code for integrated circuits
Basic type number
This type designation applies to semiconductor
monolithic, semiconductor multi-chip, thin film,
thick-film and hybrid integrated circuits.
THIRD LETTER
The third letter indicates the operating ambient
temperature range. The letters A to G give information
about the temperature:
A basic type number consists of three letters followed
A
by a serial number.
B
C
FIRST AND SECOND LETTER
D
E
Digital family circuits
F
G
The first two letters identify the family (see note 1).
Solitary circuits
SOlitary digital circuits
; analog circuits
: mixed analog/digital circuits
Microprocessors
microcomputer central processing unit
slice processor (see note 3)
correlated memories
other correlated circuits (interface, clock,
peripheral controller, etc.)
To the basic type number may be added:
Version letter( s)
A Single version letter may be added to the basic type
number. This indicates a minor variant of the basic
type or the package. Except for 'Z', which means
customized wiring, the letter has no fixed meaning.
The following letters are recommended for package
variants:
Charge-transfer devices and switched capacitors
The first two letters identify the following:
NT
NX
NY
hybrid circuits
logic circuits
memories
analog signal processing,
using switched capacitors
analog signal processing,
using change-transfer device
imaging devices
other correlated circuits
C
D
F
G
H
L
P
Q
T
U
June 1994
The range 0 to 75°C can be indicated by
SERIAL NUMBER
This may be either a 4-digit number assigned by Pro
Electron, or the serial number (which may be a
combination of figures and letters) of an existing
company type designation of the manufacturer.
The first two letters identify microprocessors and
correlated circuits as follows:
NH
NL
NM
NS
e
Example:
'B' or 'A'.
The second letter is a serial letter without any further
significance except 'H' which stands for hybrid circuits
(see note 2).
MA
MB
MD
ME
e
If a circuit is published for another temperature range,
the letter indicating a narrower temperature range may
be used or the letter 'N.
The first letter divides the solitary circuits into:
S
T
U
temperature range not specified below
(see note 4)
0 to +70 o
-55 to +125°e
-25 to +70 0
-25 to +85°e
-40 to +85°e
-55 to +85°e
1-11
for cylindrical
for ceramic Dil
for flat pack (2 leads)
for flat pack (4 leads)
for quadrature flat pack (QFP)
for chip on tape (foil)
for plastic Dil
for all
for miniature plastic (mini-pack)
for uncased chip
Philips Semiconductors Video Products
Pro Electron type designation code for integrated circuits
Alternatively a TWO LETTER SUFFIX may be used·
instead of a single package version letter, if the
manufacturer (sponsor) wishes to give more
information.
FIRST LETTER:
C
D
E
F
G
H
K
M
Q
R
S
T
W
X
Y
General shape
cylindrical
dual-in-line (DIL)
power DIL (with external heatsink)
flat (leads on 2 sides)
flat (leads on 4 sides)
quadrature flat pack (OFP)
diamond (TO-3 family)
multiple-in-line (except dual-, triple-,
quadruple-in-line)
quadruple-in-line (OIL)
power OIL (with external heatsink)
single-in-line
triple-in-line
lead chip-carrier (LCC)
lead less chip-carrier (LLCC)
pin grid array (PGA)
SECOND LETTER:
C
G
M
P
Notes
1. A logic family is an assembly of digital circuits designed to be interconnected and d~fined by its basic electrical characteristics (such as: supply
voltage, power consumption, propagation delay,
noise immunity).
Material
metal-ceramic
glass-ceramic (cerdip)
metal
plastic
To avoid confusion when the serial number ends with
a letter, a hyphen is used preceding the suffix.
Examples (see note 5)
PCF1105WP
Digital IC, PC family,
operational temperature
range -40 to +85°C, serial
number 1105, plastic leaded
chip-carrier.
GMB74LSOOA-DC
Digital IC, GM family,
operational temperature
range 0 to +70°C, company
number 74LSSOOA, ceramic
DIL package.
TDA1000P
Analog circuit, no standard
temperature range, serial
number 1000, plastic DIL
package.
SAC2000
Solitary digital circuit,
operational temperature
range -55 to + 125°C.
June 1994
1-12
2.
The first letter'S" should be used for all solitary
memories, to which, in the event of hybrids, the
second letter 'H' should be added (e.g., SH for
Bubble-memories).
3.
By 'slice processor; is meant: a functional slice of
microprocessor.
4.
In the case of two same types with two different
temperature ranges not specified below, one type
should use the letter 'A" as the third letter and the
other, the letter 'X'.
5.
Some companies have been using version letters
and/or two letter-suffix, which differ from the
Pro Electron definitions. In case of confusion
Pro Electron may be contacted.
Philips Semiconductors Video Products
Handling MOS devices
mounted. Take care that the circuits themselves, metal
parts of the board, mounting tools, and the person
doing the mounting are kept at the same electric
(ground) potential. If iUs impossible to ground the
printed-circuit board, the person mounting the circuits
should touch the board before bringing MaS circuits
into contact with it.
HANDLING MOS DEVICES
Though all our MaS integrated circuits incorporate
protection against electrostatic discharges, they can
nevertheless be damaged by accidental over-voltages.
In storing and handling them, the following precautions
are recommended.
Caution
Testing or handling and mounting call for special
attention to personal safety. Personnel handling MOS
devices should normally be connected to ground via a
resistor.
Soldering
Soldering iron tips, including those of low-voltage
irons, or soldering baths should also be kept at the
same potential as the MaS circuits and the board.
Storage and transport
Static charges
Store and transport the circuits in their original
packing. Alternatively, use may be made of a
conductive material or special IC carrier that either
short-circuits all leads or insulates them from external
contact.
Dress personnel in clothing of non-electrostatic
material (no wool, silk or synthetic fibers). After the
MaS circuits have been mounted on the board, proper
handling precautions should still be observed. Until the
sub-assemblies are inserted into a complete system in
which the proper voltages are supplied, the board is
no more than an extension of the leads of the devices
mounted on the board. To prevent static charges from
being transmitted through the board wiring to the
device, it is recommended that conductive clips or
conductive tape be put on the circuit board terminals.
Testing or handling
Work on a conductive surface (e.g., metal table top)
when testing the circuits or transferring them from one
carrier to another. Electrically connect the person
doing the testing or handling to the conductive
surface, for example by a metal bracelet and a
conductive cord or chain. Connect all testing and
handling equipment to the same surface.
Transient voltages
To prevent permanent damage due to transient
voltages, do not insert or remove MOS devices, or
printed-circuit boards with MOS devices, from test
sockets or systems with power on.
Signals should not be applied to the inputs while the
device power supply if off. All unused input leads
should be connected to either the supply voltage or
ground.
Voltage surges
Beware of voltage surges due to switching electrical
equipment on or off, relays and DC lines.
Mounting
Mount MaS integrated circuits on printed circuit
boards after all other components have been
June 1994
1-13
Philips Semiconductors Video Products
High-performance 8-bit video data converters
Wherever there's a need to display a picture
on a video screen, there's an attendant
demand to enhance the image. This requires
the analog video signals to be converted into
digital infonnation before the enhancement
techniques can be applied. Unfortunately,
although integrated 8-bit full-parallel flash
ADCs are available for converting
high-frequency video signals, the complex
circuitry they contain to achieve the required
high level of performance makes them too
expensive and power corisumingand,
paradoxically, even restricts their
perfonnance for many applications.
We have overcome this problem by
developing our innovative TDA87xx range of
20 MSPS to 50 MSPS, or even 100 MSPS
a-bit data converters and fabricating them in
a standard high-volume bipolar process
(SUBILO·N). This advanced process offers
high speed, high packing density and
excellent el.ement matching, all of which are
crucial factors for integrating
high-perfonnance data converters ..
June 1994
INNOVATIVE TECHNIQUE
REDUCES COST AND POWER
CONSUMPTION
The secret of the success of our TDA87xx '
data converters lies in an innovative folding
and interpolating technique which reduces
the number of on-Chip components to such
an .extent that cost is reduced by up to 90%,
and power consumption cut by up to 70%. A
unique added benefit is that the impressive
reduction of chip area we have achieved
allows us to offer TDA87xx data converters
not only in DIL packages but also in SO
packages for surface mounting.
PROFESSIONAL PERFORMANCE
AT A CONSUMER PRICE
Despite the remarkable reductions of power
consumption and price we have achieved for
our TDA87xx range, there is no sacrifice of
1-14
perfonnance. For example, our 75 MSPS
8-bit flash ADCtype TDA8714 consumes as
little as 325 mW, has a minimum differential
linearity error of only 1/2 LSB, and a
signal-to-noise ratio of 70 dB resulting in a
resolution of 7.6 effeCtive bits with an input
frequency of 4.43 MH2; (~5 MHz clock). This
compares well with the 6 effective-bit
resolution offered by expensive bipolar
professional ADCs and far outstrips the 3 or
4 effective-bit resolution obtainable with MOS
ADCs for consumer video applications.
The outstanding video frequency
perfonnance of our TDA87xx converters,
combined with their low cost and power
dissipation, makes them ideal for reducing
costs without degrading perfonnance in
professional and military applications and, for
the first time, brings affordable
high-perfonnance data conversion to a host
of consumer video applications.
Philips Semiconductors Video Products
High-performance 8-bit video data converters
within the transition range of only one of the
comparators, only one of the latches has to
change its output state for each sample.
Moreover, the 255 latches at the analog to
digital interface cause kick-back noise which
disturbs the sensitive analog circuitry.
The complex circuitry and immense number
of signal interconnections occupy a very
large area of silicon, restrict operating speed
and dissipate considerable power. Also, the
analog signal sampling process and
attendant aliasing effects impose stringent
demands on the distortion and noise behavior
of the analog circuitry.
A TO 0 CONVERSION
TECHNIQUES
Full-parallel conversion is
complex and power-hungry
Most currently available high-performance
8-bit ADCs use the full-parallel
implementation shown in a simplified form in
Figure 1. In this configuration, 255
comparators simultaneously compare the
level of the applied analog input signal with
255 different reference levels derived from a
resistor ladder. On the occurrence of each
sampling clock pulse, 255 latches store the
output states of the 255 comparators and a
255 to 8-line encoder converts the latch
outputs into an 8-bit code. Obviously, this
full-parallel system is inefficient because
much of the information stored in the latches
is redundant. For example, since each
sample of a full-scale input voltage ramp falls
Folding and interpolating
reduces on-chip components and
power consumption
An elegant method of reducing the
complexity of the full-parallel ADC circuitry, is
to reduce the number of latches and simplify
the encoding logic by combining the outputs
from several of the comparators and feeding
the resultant Signal to a single latch. This
"folding" technique is practical as long as the
comparators which have their outputs
combined are suffiCiently far apart on the
reference resistor ladder to ensure that any
input sample falls within the transition range
of only one of them.
The next logical step is to reduce the number
of comparators and combining circuits
(folding amplifiers), thereby also simplifying
the precision reference resistor ladder. This is
done by eliminating groups of intermediate
comparators fed by consecutive taps on the
reference resistor ladder and using a resistor
ladder at the remaining comparator outputs to
interpolate the missing signals.
I
I
I ENCODER I
I
I
SAMPLE
> - - - - 1 ' - - - - - - - - - { LATCH
3
digital
output
>---1------'----;
SAMPLE
LATCH
2
SAMPLE
>--11----------; LATCH
1
sample
clock
V255~
Vin
I
I
I
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lZ20378
Vl~
t
Figure 1. a-bit full-parallel ADC
At the sample clock, an array of 255 latches decides whether the output from each of 255 comparators is 1 or O.
The usage of the latches is inefficient - each has only to make one decision over the entire full-scale input range.
June 1994
1-15
Philips Semiconductors Video Products
High-performance a-bit video data converters
r:;1>------=4I
I V240
I
I
I
I
I
I
I
I
I
I
I
FOLDING
AMPLIFIER
INPUT TO SAMPLE LATCH
MEAr54
Figure 2. One of 16 identical sections of an 8·bit folding ACe
Folding the outputs of 16 comparators to one latch reduces the number of latches needed from 255 to 16.
Reducing the number of latches
by folding the analog input signal
Figure 2 shows one of the sixteen identical
sections of a ''folding" a-bit ADC with
waveforms for sampling a full-scale input
voltage ramp. Here, the outputs from every
16th comparator along the reference resistor
ladder are alternately ''folded" up and down
by sixteen 16-input analog gating circuits
(folding amplifiers), the output from each of
,which is sampled by a single latch. The
number of latches required for a complete
a-bit ADC is thus reduced form 255 to 16,
and the 255 to a-line encoder is simplified to
a 16 to a-line circuit. Because the signal
distribution problems and chip area for this
ADC configuration are also considerably
reduced, its overall performance actually
improves. Furthermore, .since it has only 16
connections between the analog and digital
circuitry instead of 255, kick-back noise is
much reduced.
Because the output code generated by the 16
latches after folding (fine conversion) is
repeated eight times during a full-scale input
June 1994
voltage ramp, a simple, easy to implement
3-bit coarse converter is needed to determine
which of the eight output code cycles is the
current one. It is also necessary to equalize
the delays introduced by the coarse and fine
conversion to ensure that the accuracy of the
final data stream is equal to that of the fine
converter.
Reducing the number of
comparators by interpolating
their outputs
The folding technique was used to reduce the
number of latches required for an a-bit ADC
and simplify the encoding logic, thereby
reducing chip area, power consumption and
signal distribution paths without
compromising performance. We will now
show how an interpolation technique is used
to further this aim by reducing the number of
comparators and consequently the number of
taps on the precision reference resistor
ladder and the number of folding amplifiers.
This interpolation technique exploits the fact
that a comparator output signal doesn't
change state instantly when the input
1-16
exceeds the reference level, but follows the
input signal linearly over the first part of the
transition range.
Figure 3 shows outputs Vo and V4 from two
of the comparators of the a-bit folding ADC
which are separated by three taps on the
reference resistor ladder. It is clear that, since
the transition ranges of these two
comparators overlap considerably, the three
intermediate outputs (Vlo V2 and V3 ) can be
derived by interpolation using a simple 3-tap
resistor ladder connected between output Vo
and V4 as shown in Figure 4. The distortion
introduced by the interpolation is unimportant
because only the zero crossings are of
interest for setting the sampling latch.
By using this interpolation technique, three
out of every four comparators are eliminated,
thereby reducing the number required for an
a-bit folding and interpolating ADC from 255
to 64. The interpolation technique also
reduces the number of taps required on the
precision reference resistor ladder from 255
to 64 and reduces the number of folding
amplifiers required from 16 to 4.
Philips Semiconductors Video Products
High-performance a-bit video data converters
to
sample
latches
MEA/55
lZ2038'
Figure 3. Interpolated zero crossings for three out of four comparator outputs
June 1994
1-17
Figure 4. Interpolation of three out of
every four comparator outputs with a
resistor ladder reduces the number of
comparators needed for an 8-bit ACe
from 255 to 64
Philips Semiconductors Video Products
High-performance a-bit video data converters.
The complete 8-bit folding and
interpolating ADC
Figure 5 is a simplified block diagram of a
complete 8-bit folding and interpolating ADC.
In this diagram, each of the folding amplifier
blocks contains 16 comparators and a folding
amplifier. Also, although the interpolation is
performed by resistor ladders at the outputs
of the folding amplifiers, the principle remains
the same as that described for interpolating
at the comparator outputs.
64-TAP
REFERENCE
LADDER
~
16
INTERPOLATION
RESISTOR
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SAMPLE
LATCHES
,,,,-.ro.--r:-1 /
lZ20380.r
Figure 5. Block diagram of a complete folding and interpolating ADC
Although, in practice, interpolation takes place after folding of the comparator output
signals instead of before as explained for clarity in the main text, the result is the same.
The folding amplifier blocks each contain 16 comparators and a folding amplifier.
Number of internal components for 8-bit full-parallel ADCs compared
with those required for folding and interpolating ADCs
Conventional
Full-Parallel ADC
Folding and
Interpolating ADC
Reference resistor taps
255
64
Comparators
255
64
0
24
Latches
255
16
Encoder stages
255
16
Interpolation resistor taps
Simple 3-bit coarse converter
Clock driver fan-out
Output buffers
June 1994
0
1
255
24
8
8
1-18
Philips Semiconductors Video Products
High-performance a-bit video data converters
APPLICATIONS FOR VIDEO ADCs
The high performance combined with the low
cost and power consumption of our TDA87xx
range of video data converters make them
suitable for applications ranging from costly
professional equipment requiring the highest
performance, to consumer equipment where
cost is the major factor.
To quote just a few examples, transportable
medical equipment, such as ultrasonic
scanners, demands high performance
combined with low power consumption. High
performance is also essential for converters
in sensitive high-frequency test and
measuring equipment such as oscilloscopes
and spectrum analyzers. The rapidly
expanding market for desktop video is
another application area. In the consumer
world of home entertainment systems, TV set
manufacturers and broadcast authorities are
meeting the demand for more TV channels
and enhancement of picture quality by using
digital signal processing techniques. For
example, low-cost converters are needed for
decoding MAC-encoded multi-channel TV
and sound information from broadcast
satellites, and for use in the new TV sets with
memory-based features that are appearing
on the market.
HOW WE MEASURE THE
PERFORMANCE OF OUR ADCs
For an ADC specification to be useful to an
equipment manufacturer, it must fully
characterize the dynamic performance of the
IC. Figures relating to integral and differential
linearity at low frequencies are of little use as
figures of merit because they have to be
laboriously converted into more useful figures
for many applications. Output signal-to-noise
ratio (SNR), provided it is related to input
frequency, is a much better and more
versatile figure of merit for an ADC because
the "noise" includes both the quantization
error and the harmonic distortion. Moreover
a simple formula can be used to convert SNR
into "effective bits". However, the SNR of an
ADC is not easy to measure, and additional
specific data relating to Total Harmonic
Distortion (THO) is often required as well.
This is why we have developed a special
Measurement Bench for accurate
determination of the static and dynamic
performance of our present and future ADCs.
ADC measurement bench
Our ADC measurement bench is arranged as
shown in Figure 6. It is for use in a laboratory
to determine the static and dynamic
characteristics of present and future ADCs
with up to 12 digital outputs and conversion
rates up to 100 MSPS. The following
characteristics can be measured:
- signal-to-noise ratio (SNR)
-
total harmonic distortion (THO)
differential non-linearity (DNL)
integral non-linearity (INL)
data timing.
A PC is used to control the measurement
bench and to acquire the sampled input
signal to test the ADC. The acquired Signal is
converted into a data file that is used by a
test program developed with scientific
Forth-language software called ASYST, to
create histograms, graphs, and a Fast
Fourier Transformation (FFT) which facilitate
analysis of the· ADC output data to determine
its operating char~cteristics.
Analog input signal
For accurate and complete determination of
ADC characteristics, it is necessary to test all
of the possible quantization levels. It is also
necessary to meet the requirements of the
Nyquist sampling theorem that states that it is
only possible to fully define an analog
waveform digitally if the sampling interval is
not more than half the bandwidth of the
analog signal.
Although it is possible to use an analog input
signal with a triangular or sawtooth (ramp)
waveform (theoretically infinite bandwidth),
we use a full-scale sinusoidal signal because
it has only one frequency component and is
comparatively easy to synthesize at high
frequencies.
test program
SPECTRUM
ANALYZER
dala file
PC 386125
DOS
ASYST
t6k
GPIB
command
synthesizer
power supply
pulse generator
sampling frequency
T100
TIME BASE AND SAMPLING FREQUENCY CONTROL
Figure 6. Block diagram of the measurement bench
June 1994
1-19
MEA/56
Philips Semiconductors Video Products
High-performance a-bit video data converters
Sampling method
At the start of a sinewave period, the slope of
the signal is maximum and equal. to
A27tfin vIs, where A is the peak amplitude.
The amplitude to be defined by 1 LSB of the
ADC is therefore 2A12N volts, where N is the
number of data outputs from the ADC. To
acquire every quantization level by real-time
sampling, 2N samples must be taken during
the period of one half cycle (one peak-topeak sweep) of the input signal which is tin/1t.
The time .available to describe 1 LSB is
therefqre tin/2N1t, leading to a required
conversion rate of2N1tfin. For an 8-bit ADC
with an input frequency of 5MHz, the
conversion rate would therefore have to be
4 GSPS, which is far above the maximum
conversion rate specified Jor any of our
ADCs.
Instead of using real-time sampling, our
measurement bench therefore uses the
multi-beat frequency method of sampling
illustrated in Figure 7.
Multi-beat frequency sampling uses the
principle of "aliasing" to convert the high
frequency input sinewave into a lower
frequency sinewave from which it is easier to
acquire all the quantization levels for
analysis.
Instead of acquiring all the samples during
the period of half an input cycle by sampling
at fs =2N7tfin , the required number of
samples (No) are now acquired over several
cycles of the input signal and used to
reconstruct a sinewave which is a lower
frequency aliased version of the input signal.
The ADC under test samples the sinewave
input at a rate offset by a small amount from
an integer multiple of the input frequency.
The small frequency offset is chosen so that
the ADC output only changes by one LSB at
the point of maximum slope of each
consecutive cycle of the input sinewave.
Since an LSB period at the point of maximum
slope ota sinewave is ~n/2N1t, the minimum
number of samples that must be acquired to
fully test all the quantization levels is No >
2N1t, in which No must be rounded to an
integer. For an 8-bit converter, No must be at
least 805.
Under these conditions, the minimum
sampling period {time to acquire all samples
during one input cycle).is tsmin =tin/NO
which gives a maximum sampling frequency
of fsmax = finNO. This maximum frequency is
too high to be practical and must be reduced
to fs =fsmaxlKo (ts =tsminKo), where the
difference between Ko and No are relative
primes. To minimize the sample acquisition
time, the value of Ko should, however, be the
minimum permitted by the maximum
conversion rate specified for the ADG under
test.
The measurement bench uses every Koth
output from the ADC under test to compile a
sampled sinEiwave acquired data file. The
information in the data file, which is
effectively a reconstruction of a sinewave,
which is a lower frequency aliased version of
the input signal, is then analyzed to
determine the ADC characteristics.
Measuring effective bits and
harmonic levels
To determine the signal-to-noise ratio (SNR)
and harmonic levels of our ADCs on the
measurement bench, the data in the acquired
sinewave file is transformed into the
frequency domain with a fast Fourier
transformation (FFT).
The levels of the signal, its harmonics and
the noise can now be clearly seen and easily
computed. The FFT is analyzed by the
computer to determine SNR =Psigna"Pnoise'
Instead of specifying SNR, it is possible to
specify effective bits (b), which are defined as
b = {SNR - 1.76)/6.02, where SNR is the
calculated value in dB when a full-scale
sinewave is analyzed.
By determining SNR as a function of input
frequency, it is easy to determine the N-bit
resolution bandwidth of an ADC which is
equal to the input frequency at which the
effective bits have decreased to N-Q.5. For
an 8-bit ADC, this occurs when the SNR is
46.9 dB.
INPUT SIGNAL SAMPlING:
at T1 = T~ I NO (N0=8) t t t t t t t t! ttt tt t t t t t t t t t t t
atTs =T1 KO(Ko--3)t t t t t t t t t
0
SIGNAL AFTER
SAMPUNG AT Is
NOT RECONSTRUCTED
•
RECONSTRUCTED
lEA 157
Figure 7. Principle of multi-beat frequency sampling
June 1994
1-20
Philips Semiconductors Video Products
High-performance a-bit video data conve.rters
Differential and integral
non-linearity ..
Differential non-linearity.(DNL) isa measure
of the maximum amou,nt by which the
distance between the midpoints of adjacent
steps on the ADC transfer function
(quantized output level as a function of input
level) differs from the width of. one LSB. It is
measured with a statistical test inwhich the
acquired sinewave file is used to generate a
histogram of the digitized signal with a
number H(i) for each output code (i). The
probability of obtaining each code is
calcuiated and the ratio of the number of
acquired samples of each code H(i) to the
total No of samples (No) represents the
differential non-linearity.
from the ideal. Since it is equal to the
maximum difference between the measured
and ideal quantization levels, it can be
calculated from the histogram used ,to
calculated DNl. Since INL(O) =ONL(O)l2, INL
can be calculated for each step. (i) of ,the
transfer function as INL(i) = INL(i..1) +
DNL(i)/2.. The maximum value thus obtained
is the integral non-linearity of the ApC.
Data timing
The relative timing of the output bits of the
ADC can be displayed on the screen of the
PC that forms part of the measurement
bench. Acquisition of the timing data can be
either synchronized with the ADC clock
pulses the frequencies up to 1 GHz, or
asynchronous at frequencies up to 2 GHz.
Integral non-linearity (INL) is a measur~ of
the deviation of the ADC transfer function
June 1994
1-21
APPLICATION SUPPORT
When designing data converters into a
system, it is essential to pay careful attention
to a number of circuit details to ensure that
the high performance of our les is fully
9.xploited. CorrectPCB layout is particularly
important,. with particular emphasis on track
. widths, avoidance of ground loops and
minimization of crosstalk between the analog
and digital circuitry. Care must also be taken
to understand the relative timing of the
sampled and output data. Other important
details include decoupling for noise reduction
and stability of internal reference levels,
decoupling and harmonic suppression for
clock signals, and power supply filtering.
Philips Semiconductors Video Products
Line-locked digital colour decoding,
Ton Nil/esen - CAB-Elcoma, N. V. Philips, Eindhoven (The Netherlands)
o digitally decode PAL or NTSC composite video
in a TV receiver, it is advantageous for t.he
T
sampling' rate .to be related to the colour subcarrter
signa~s
Onpresentedans cet article une methode de decodage
numerique des signaux video couleur basee sur des
fnlquences d'echantillonnage verrouillees sur Ia ligne, La
frequence d'echantillonnage estsynthetisee apartir de la
frequence d'un cristal. On genere une frequence stable
de Sous-pOl1euseen utilisant la frequence variable
d'echantillonnage par controle direct apartir du synthetiseur.
frequency because this simplifies the demodulator
and the chroma filters. However after colour decoding, the component video signals for luminance and
colour difference are available and the colour subcarrier is then no longer relevant. Line-locked sampling
is then a better choice.
In fact, for video processing and conversion to other
scanning frequencies, line-Io~ked sal!lpling is a na~ur
al choice because it results 10 orthogonal sampling,
which simplifies video signal processing with line and
field memories [I).
A digital colour decoding principle invoMng line-locked
sample frequencies is presented. The sampling frequency is synthesized from a crystal frequency. A stable
subcarrier frequency is generated from the variable
sampling frequency by forward control from the synthesizer.
June 1991
WHY LINE LOCKED?
Standard conversion to other scanning frequencies
might be used for instance for reductio~ of large. area
flicker by means of field rate conversIon to hIgher
frequencies. Another type of conversion is ~ompre.s
sion of the signals for features such as pIcture In
picture and multi picture-in-picture, whereas expansion of the signals is required for picture enlargement
or C-MAC decoding, etc..
1-22
Philips Semiconductors Video Products
Line-locked digital colour decoding
Converter (SRC) is via digital-to-analog(DA) and
analog-to-digital (AD) conversion. The subcarrierlocked samples are then converted to analog signals
and re-sampled with the line-locked sample frequency (fig. I a). Although this is a straigtforward
method, using well-known techniques, it is not attractive because it is expensive. It requires ADCs and
DACs, three of each for the three component signals,
including the reconstruction filters,. and a second
clock generator. Furthermore, the additional conversion step degrades signal quality. A second approach
is a SRCin the digital domain, the line-locked samples being calculated from surrounding subcarrier-Iocked samples by means of interpolating algorithms (fig. Ib). Both approaches require two clock
generators coupled to the video signal, one burstlocked and the second line-locked.
Some other examples of signal processing using line
or field memories are :
• cross colour and cross luminance reduction with
line-, field- or frame-combtilters,
• noise" reduction by an integrating temporal filter,
• resolution enhancement by a peaking spatial tilter.
Furthermore, a line-locked sample frequency is a
must for matrix displays such as LCDs, the index tube
and dot matrix printers and it is also a necessity for
display of good quality characters.
And last but not least, the circuitry for processing
line-locked component video signals is substantially
independent of transmission standards.
However, it is not necessary to have the line-locked
clock available with equidistant clock transitions.
Transfer .and processing of the samples with amplitude information belonging to line-locked sampling
positions can be done with a gated version of the
original clock (fig. Ic). The gated clock should then
have a constant number of clock transitions per line
period. However a reverse sample rate conversion is
then required before DA-conversion. This second
SRC is eliminated if the line-locked clock is physically available. DA-conversion is then done with the
line-locked clock. However the most complex part of
the sample rate conversion is the interpolating algorithm required [2J.
APPLICATION OF SAMPLE
RATE CONVERTER
If a subcarrier-locked colour decoder is used, linelocked samples can be obtained by sample rate
conversion. An obvious approach for a Sample Rate
a
b
N transitions per line period
c
Fig. 1. Application of sample rate converters: a. anolog sample rate converter. b. digital
sample rate converter and two clocks coupled to video signal. c. two digital sample rate
converters and single clock.
June 1991
1-23
Philips Semiconductors Video Products
Line-locked digital colour decoding
INTERPOLATION OF SAMPLES
COLOUR DECODING PRINCIPLE
In principle, interpolation is done by low-pass filtering. The low.pass filter should reject the sidebands of
the original subcarrier-Iocked samples, including at
harmonics of the sampling frequency, but should pass
the baseband spectrum containing the desired signal
with a flat frequency- and linear phase-characteristic.
Linear interpolation is certainly not sufficient, neither
in the passband nor in the stopband, to preserve good
signal quality. Each new sample should therefore be
calculated from several surrounding original samples
with proper weighting factors. The weighting factors
should be of sufficient number and sufficient accuracy to generate new samples with a timing accuracy
of about 0.2 ns, if the resulting signal should have"a
bandwidth of 5 M Hz and 8-bit quantization (fig. 2).
The NTSC and PAL colour systems use suppressedcarrier amplitude modulation with quadrature subcarriers (fig. 3). The chroma signal can be demodulated by multiplying it by the correctly-phased subcarrier
sine and cosine waves. This gives the colour difference signals plus some high frequency components,
U;U cos(2wsct)± Vsin 2(w sc t)
~-'-/--I~~
V+Vcos 2(w sc t)±Vsin 2(w sc t)
Usin(wsct)t VcoS(Wsct )
Mf sc - samples
"".g "g,,' ---r-.
l/"---.T···"'----r----
Fig. 3. Colour decoding principle for PAL system.
the latter being removed by filtering. For digital
signals, the chroma signal has to be multiplied by the
sampled subcarrier waves. If the sample rate is four
times the subcarrier frequency, with the correct phase,
the multiplications simplify to multiplication by I, 0,
- 1 and 0 of successive samples. With line-locked or
other sample frequencies asynchronous with the subcarrier, real four-q\Jadrant multipliers are required for
demodulation with the asynchronously-sampled subcarrier [3J.
In the subcarrier regenerator (fig. 4) the subcarrier
phase is coupled to the received colourbust. In order
to reduce the effects of noise, the phase information
extra.cted from several bursts is averaged by means of
a narrow filter whiCh in general is implemented as a
phase locked loop (PLL). In analog circuits, the phase
detector. normally consists of a multiplier and the loop
filter in a second order loop delivers an output signal
which is partly proportional to the phase detector
output signal and partly an integrated version of that
signaL So digitally these blocks can be realised with
adders, multipliers and an integrator.
Fig. 2. Principle of sample rate conversion.
For compatibility with non-standard video signals
with variable line frequencies, the conversion rate
cannot be expressed as a simple ratio of small prime
integers but is irrational and time-varying. As a
consequence the interpolating filters will be complex
with a large set of filter coefficients. A digital SRC
will therefore require a relatively large chip area.
These are the reasons for considering line-locked
colour decoding which produces line-locked samples
of the luminance and the colour difference signals
directly.
June 1991
'.O.K".
colour burst
~.~"
phase
detector
Fig. 4.
tor.
1-24
Schem~tic
rv
loop
filter
Wsc
To
tunable
oscillator
diagram of the analog subcarrier regenera-
Philips Semiconductors Video Products
Line-locked digital colour decoding
vious content of the accumulator is incremented by p
until overflow occurs at the value q. The next value
will then be the previous value plus p modulo q. So the
output resembles a time discrete quantised sawtooth
signal whose period is set by p. Obviously the ratio
between p and q equals the ratio between the clock
period and the period of the output signal /0. So the
control value p should be /01!cl' q. If the overflow
value is defilled as being I. then the input value
simplifies to p= /o/!cl (fig. 5b).
That brings us to our definition of a discrete time
oscillator (DTO) also known as ratio counter or rate
multiplier or accumulator or numerically controlled
oscillator. The input value should equal the ratio
between the desired output frequency and the clock
frequency. Its modulo I output indicates from zero to
one the instantaneous phase within a single preriod
(fig. 6).
The tunable oscillator is normally a voltage controlled
oscillator with an oscillator control sensitivity of Ko
(rd· s -I. V-I). So for an output frequency of ltJsc. the
subcarrier frequency. the loop filter has to deliver a
control voltage of ltJsc/ Ko. For Stnewave oscillators the
instantaneous output is sin (w..ci). As a consequence.
the oscillator transfers the input stgnal Wsc/ Ko to the
output .signal sin (ltJsct) which. apart from the sine
function and the constant Ko. is an integrating action.
The sine function prevents saturation of the output by
the ever increasing value of the instantaneous phase.
With the sine function the output phase follows the
instantaneous phase modulo 2 Jt radians.
THE DISCRETE TIME OSCILLATOR
(DTO)
fo
fo
Tct
frequency
control
value
clock frequency
The integrating and modulo function of the oscillator
can be realised digitally with an accumulator consisting of an adder and D-tlip-tlops (fig. 5a). The multibit
output of the adder is applied to its input via D-tlipflops which are clocked with the clock frequency !cl.
At the second input of the adder, a constant multi bit
value p is applied. So at each clock period the pre-
, -always zero
---
0.1 0 0 1 1 0 10 ...
o ~ (phase within a single period) < 1
Fig. 6. The discrete time oscillator.
Note that the ratio /o/!cl at the input is dimensionless,
indicating the phase increment per clock period.
whereas the output of the DTO is the instantaneous
phase modulo I. which in principle is varying. Both
signals can, in binary notation. be approximated to
the required accuracy. However if the clock frequency
is not constant whereas a constant subcarrier frequency should be generated, then the frequency
control value should be corrected accordingly to the
desired accuracy. As a consequence, the line-locked
clock should be known with sufficient accurary and
has therefore to be generated with a crystal frequency
as reference.
On
On=(On.'+P) moduloq
8
q--------------------~~---------------+-+-------/
I
I
/
--;----. /
/
/
N/j GENERATOR
/
/
b
It is a logical step to generate the line-locked sample
frequency from a crystal frequency by means of a
DTO. The DTO is clocked with the crystal frequency
!c and the desired output frequency is N.Ii; so the loop
~=~~P=~q
q
l/fo
fel
Fig. 5. Principle of the discrete time oscillator.
June 1991
1-25
Philips Semiconductors Video Products
Line-locked digital colour decoding
and the DTO the correction is done for the varying
clock frequency ..
Fig. 7. Generation of line-locked sampling frequency (N
with crystal accuracy.
Since the subcarrier DTO operates with the line-locked clock, a value Jcl NJi should be applied to its
input as frequency control value. This value is obtained via an arithmetical divider (AI B) which divides
the intermediate control value at t.he output of the
subcarrier loop filter by N j;./C from the horizontal
PLL. The intermediate control value should therefore
be Jc//c, the ratio between the subcarrier frequency
and the crystal frequency. Apart from long-term
variations, this ratio remains constant regardless of
the clock frequency. Consequently, the subcarrier
loop filter can be designed for narrow noise bandwidth, optimised for subcarrier regeneration. The
inaccuracy of the forward control due to the limited
word length of the signals is handled by the loop as
internally-generated noise and can be chosen at a
sufficiently low level.
ttl
filter in the horizontal phase locked loop should
deliver the numerical value N Jil!c (fig. 7).
The DTO delivers then a quantised sawtooth signal
with frequency N Ji but in the discrete time domain
sampled with the crystal clock.fc.However the sample
frequency should be available as a continuous signal
so that it can be used as the system clock. Therefore
the DTO output signal is converted from digital to
analog after a conversion from sawtooth to sinewave
via a sine-ROM. The reconstruction filter delivers
then an analog sinewave with no undesired harmonics
or mixing products. That sinewave is then converted
to the proper logical signal levels.
If this sample frequency generator is used in the
horizontal phase locked loop, then the relationship
between instantaneous sampling frequency and the
crystal controlled reference frequency is known. As a
consequence, the generated frequency control value
N Jil!c from the horizontal phase locked loop can be
used to correct the DTO in the subcarrier loop for
variations in N Ji.
LINE-LOCKED COLOUR DECODER
A complete block diagram of a line-locked colour
decoder is presented in figure 9. For simplicity, several functions such as automatic colour control, colour
killer, compensating delays etc. have been omitted in
the block diagram. The signal-flow in the horizontal
and subcarrier PLLs are indicated in heavy lines as is
the correction circuit (A/B) which corrects the subcarrier DTO for varying line. frequencies. The left-hand
part of the circuit operates with the crystal controlled
clock frequency /c and generates the line-locked sampling frequency N Ji with which the rest of the circuit
operates. The coupling between these two parts is via
the resynchronisation register R which delivers the
control value N Jil/c to the DTO.
FORW ARD CONTROL (DIVlDER)
In the synchronisation processing part, the N Ji sample frequency is divided down to the line frequency Ji.
The division ratio N can be made selectable to adapt
the sample frequency to the band with of the video
signal or. to different line frequencies. The counter
drives a state decoder which delivers several control
Figure 8 shows the subcarrier phase locked loop with
the burst phase detector, the loop filter, the DTO and
the sine plus cosine ROM which delivers the demodulating sine and cosine waves. Between the loop filter
phase
detector
loop
filter
correction
oscillator
sine /cosine ROM
~-----------------------------------,
sin(wsc t )
cos(oosc t )
burst
Fig. 8. Forward control of subcarrier OTO operating with line-Iocke~ clock.
June 1991
1-26
Philips Semiconductors Video Products
Line-locked digital colour decoding
composite video in
-
-
--- -
-
-- -
-
-
- - - --,'ine-'ocked
I digital outputs
r-------------~r-------------~~-y
u
r
I
I
I
I
I
I
I
INfl
I
I
forward
control
I
I
L __
Nfl
~
f,
Nf,
- - - - - - - ___________ J
c:::J fc
Nf'nom
- fc
------- ------I
Nf, generation
fsc nom
- fc
sync processing
colour decoding
Fig. 9. Simplified block diagram of line-locked digital colour decoder.
signals at line frequency. One of these line frequency
signals is applied to the horizontal phase detector
where its phase is compared with the phase of the
separated synchronisation signal. The result is applied to the loop filter and then added to the nominal
input value (N ji nomlIc) for the DTO. As a consequence
the loop filter has only to deliver the error on the
nominal value and the nominal value can be made
selectable to accomodate different line frequencies or
different numbers of samples per line.
The frequency control value has only to be updated
once per line period. However updating the sample
frequency also requires a new correction of the subcarrier DTOinput value. For that reason the control
values to both DTOs are effectuated on command of
a line frequency signal ji when both control values
have been calculated. In fact the subcarrier DTO is
updated somewhat later than the N ji-DTO to compensate for the delay of the video signals from ADC
to demodulator. The synchronisation signal ji acts as
write clock for the resynchronisation buffer R. The
new data is then clocked with .f.: and applied to the
input of the Nfi-DTO.ln the subcarrier DTO the new
value becomes availables as soon as the D-flip-flops
in front of the subcarrier DTO are clocked with a line
frequency signal.
ofa multiple input AND-gate. forms the phase detector. After passage through the loop filter, the result is
added to the nominal frequency control value
(/c n"m l Ic) and divided by N.M.f.:. After the division.
which takes several clock cycles, the result is applied
to the DTO via the D-flip-flops.
To prevent side-locking. the loop filter output ll./c l Ic
should be limited so that the regenerated subcarrier
remains close enough to the nominal value. The
nominal value can be altered to accommodate the
subcarrier frequency in different standards. This gives
this system a clear advantage over conventional decoders. Although only a single crystal frequency Ic is
present, any subcarrier can be regenerated with the
proper accuracy only by changing the nominal frequency control value /c "<>m/.f.:.
Let us consider now the analog part of the clock
generation circuitry. The reconstruction filter and
wave shaper for the N ji clock frequency can be
implemented with an analog PLL. The advantages of
this are:
• the filter curve tracks the input frequency so that
the bandwidth can be smaller than with a fixed filter:
this allows fewer bits to be used in the DA-converter ;
In the subcarrier loop the demodulated burst signal is
used as actual phase information for subcarrier regeneration. For PAL the average V-phase of the burst is
zero if the subcarrier phase is correct. So the
V-demodulator together with the burstgate. consisting
June 1991
• several line-locked frequencies can be generated if
the PLL is provided with dividers;
• the entire circuit can be integrated.
1-27
Philips Semiconductors Video Products
Line-locked digital colour decoding
--
4 bits mUltiplying DAC
phase
DAC detector
r-----------~~--,
tline-Iocked
( frequencies
forward control
of frequency step
Fig. 10. Analog Pll as reconstruction filter.
Such an implementation is indicated in figure 10. The
analog PLL is indicated with a charge pump phase
detector, a loop filter, a voltage controlled oscillator
(YCO) and the divider which delivers several linelocked frequencies. As a consequence the first part of
the circuit can also operate on a subharmonic of the
actual sample frequency.
The phase detector is driven by the DA-converter so
that these functions can be combined in form of a
multiplying DAC. Good results have been obtained
with a 4 bit DAC so that this function can be very
small in chip area. The required accuracy of the DAC
of course is dependent on the quality· of the reconstruction filter. A smaller filter bandwidth requires
fewer bits for the DAC. However a narrow noise
bandwidth of the PLL results in a slower response on
frequency steps and consequently larger phase errors.
That response can be improved by forward control of
the oscillator to the required frequency. That information is available at the input of the N Ji-DTO and
could be used via DA-conversion for pre-correction
of the YCO-frequency.
• owing to the orthogonal samples, line-locked decoding is optimized for the growing use of picture processing [4, 5] ;
• the system in principle is sample-rate-invariant so
that it has excellent multi-standard capabilities and it
enables the choice of a common clock for all standards;
• for applications somewhat further in the future, it is
quite important that the principle is directly applicable with matrix displays.
This article is written as a lecture (for ICCE 85 in
Chicago).
The factor N. which determines the sample frequency,
can have any appropriate value. An attractive choice
is N= 858 for 60 Hz TV systems and N= 864 for 50 Hz
systems. The sampling frequency will then be
13.5 MHz which is in accordance with the CCIR
recommendation for digital processing in studio
equipment. The number of active samples per line
period is then 720 for all TY standards.
VAN DE POLDER (LJ.). PARKER (D.W.). ROOS (J.). Eyolutio. or teleyision receiyer rrom a.alog to digital. Proc.
IEEE. 73, (1985).599-612.
RAMSTAD (T.A.). - Dlgilal methods ror conversion between
ubitr.ry s.mpling rrequencles. IEEE Trans. Acousl.. Speech
Signal Process. ASSP-31, (1984).577-591.
CONCLUSION
CLARKE (C.P.K.). - Digil.1 PAL decoding using line-locked
s.mpli.... 8th Int. Broadcasting Convenlion Proc .. lEE pub.
no 191. (1980).
4
In this presentation, the principle and the main advantages of line-locked colour decoding have been
shown:
June 1991
Memory b.sed re.tures. Philips publication 9398 401 30011.
(1985).
ceD ,Ideo memory systems. Philips publication 939832820011.
(1985).
1-28
Application Note
Philips Semiconductors Video Products
Digital interfaces for component video signals
AN ETV/IR89126
Author: A. H. Nillesen
Several coding parameters have to be specified for interconnecting the digital component video signals YO, UD and VD between several
devices. For the digital studio environment the CCI R has made two recommendations on these parameters.
CCIR Recommendation 601 describes an extensive family of clock frequencies and the signal amplitudes, timing codes and auxiliary data for
digital video component signals common to the 525- and 625-line TV standards. CCIR Recommendation 656 describes the means of
interconnecting digital television equipment complying with the 4:2:2 encoding parameters as defined in Recommendation 601.
In the early eighties the basic sampling clock of digital circuits for TV receivers has been chosen, by Philips, Siemens and others, in accordance
with the digital component studio standard CCIR Rec. 601, due to obvious benefits of having that parameter in common with the broadcasting
side (e.g. MAC~decoding and descrambling). However with respect to signal amplitudes and multiplexing format a different choice was made.
Possible benefits from the recommendations on these parameters were not seen, or considered as imaginary, whereas the drawbacks were
considered as serious. This paper addresses the signal amplitudes and the multiplexing format which have been chosen for digital YUV
interfaces in the TV receiver, including the extensions and revisions from later dates.
1. THE CONVERSION FACTOR
To express the amplitudes of the digital component signals, the conversion factor CF is defined as being the ratio between the digital and the
normalized representation of the signal. Normalization is done to Red=Green=Blue=1 at peak white and the digital signals are represented on a
scale of 256 (8 bits).
CF = Conversion _ Factor =
~=
. digital. signal a~plitude on 8 bits scale
normalised Signal amplitude (Rmax = G max = Bmax = 1)
}--------------------
- - - - - - - - - - - - - - - - - - - - - 255
CF*A
0---------------------
Figure 1. Definition of Conversion Factor CF
2. MAXIMUM AMPLITUDE OF NORMALIZED SIGNALS
With normalized signals the colour separation signals red, green and blue are unity at peak white: Rmax=Gmax=Bmax=1.
The colour equations for broadcast signals are based on the NTSC primaries as specified in CCIR Report 624-2. The resulting equation for the
luminance signal is:
Y.O.299*R+O.587*G+O.114*B
which gives:yP-p-1
(2.1)
IB-YI is maximum for R,G,B=O.O,l (=blue)
or R,G,B=l,l,O (=yellow=white minus blue)
which gives:
(B-Y)p-p=2*(1-0.114)=1.772
IR-YI is maximum for R,G,B-1,O,O (-red)
or R,G,B-O,l,l (-cyan-white minus red)
which gives:
(R-Y)p-p=2*(1-0.299)-1.402
maximum amplitudes of normalized signals
Yp _p -1, (B-Y)p_p .. 1.772, (R-Y)p_p=1.402
June 1991
1-29
(2.2)
Application Note
Philips Semiconductors Video Products
Digital interfaces for component video signals
AN ETV/IR89126
3. MAIN CODING PARAMETERS OF CCIR REC. 601/656
The digital component signals according to CCIR Rec. 601 have been chosen such that, coded in straight binary
- digital levels 0 and 255 are reserved for synchronization data.
• the luminance signal is to occupy only 220 quantisation levels, to provide working margins, and that black is at level 16.
• the colour difference signals are to occupy 225 quantisation levels and that the zero level is to be level 128 in order to cope with the bipolar
nature of the colour difference Signals.
The conversion factors follow from these limits on the digital signal range and the maximum peak-to-peak value of the normalized signals:
Signalp_p*CF
-digital-l~it
luminance:
Yp-p*CFy-219, which gives CFy-219
colour difference:
(B-Y)p-p*CFu=224,
(R-Y)p-p*CFv-224,
The resulting digital component signals CY, CU, CV are: 1)
CCXR digital YUV:
CY-219*Y+16
CU-126*(B-Y)+128
CV-160*(R-Y)+128
:}
binary coded
(3.1)
(3.2)
(3.3)
- the data words 0 and 255 are reserved for data identification
- the video data words are conveyed (CCIR Rec. 656) as a 27Mwords/second multiplex in the following order:
CU,Cy,CV,Cy,CU,CY,CV, etc.
in which the word sequence CU,CY,CV, refers to cosited luminance and colour-difference samples and the following word, CY, corresponds to
the next luminance sample.
4. PARAMETERS TO BE CONSIDERED FOR TV RECEIVERS
Without doubt the characteristics of analog or digital video component signals at broadcasting side and receiving end are quite different due to
the large differences in environment and cost/performance. As a consequence the coding characteristics of digital interface signals are
influenced differently by several parameters. Regarding signal amplitudes:
- maximum digital resolution should be balanced against:
- margin for static and dynamic amplitude changes, i.e. tolerances and multiplicative noise (echo, tilt).
- margin for additive noise.
- margin for filter overshoots
- probable limit on saturation
Also on the ratio between Signal amplitudes some criteria should be considered:
- simple gain correction to normalized signals e.g. matrixing.
- simple correction between digital decoder and interface.
The list can be extended with requirements from EMC, limitations or advantages of certainlC technologies, application specific requirements
etc. Although no choice is best in all cases, consensus is required on the major coding characteristics, due to obVious benefits of
standardization. The agreement on this subject between system engineers from the Consumer-Electronics and the Components divisions of
Philips (and others) will be explained in the following chapters.
5. MAIN CODING PARAMETERS FOR DIGITAL TV
The component video signals for digital TV are specified as:
digital TV signals:
YD=192*Y+16
UD-3/4*192*(B-Y)
VD-192*(R-Y)
}
straight binary
two's-complement
- multiplex formats are specified for sampling ratios of 4:1:1 and 4:2:2
1) CCI R recommendations use different nomenclature: Y, Ca, CR.
June 1991
1-30
(5.1)
(5.2)
(5.3)
Philips Semiconductors Video Products
Application Note
Digital interfaces for component video signals
AN ETV/IR89126
The colour difference signals are coded in two's complement in order to fit directly to digital arithmetic functions. The difference with the offset
binary coding of the CCIR signals (3.1-3.3) is an inversion of the MSB. Concerning the specified conversion factors it will be shown that several
criteria on the coding parameters are fulfilled simultaneously:
- digital resolution is practically optimum for 75% colour difference amplitudes.
- signal amplitudes fit conveniently to D2MAC decoders, taking into account 30% headroom for noise.
- UDND ratio fits conveniently to the required gain matching ratio for PAUNTSC colour difference signals.
- amplitude margin is in accordance with the amplitude tolerance of analog decoded signals.
- matrixing to colour selection signals is simple
6. PEAK AMPLITUDE RATIOS
The amplitude ratios should be chosen such that
- the. maximum amplitudes are more or less equal in order to maximize digital resolution
- simple gain ratios are required for matrixing
- required correction of the decoded signals is simple
in which 'simple' means that the required gain can be realized with very few additions.
6.1. Probable Maximum Saturation
Due to the gamma of the picture tube the displayed saturation will be higher than the electrical saturation except at 100%. Saturation is less
than 100% if the displayed colour has a certain white content, which means that none of the the RGB signals then becomes zero but have a
minimum non-zero value. That minimum value becomes relatively smaller if it is displayed via the gamma of the picture tube.
The electrical saturation can be expressed as
Emax - E min = 1
Emax
-
from which follows: displayed saturation = 1 _
in which
[~:~:
E min
Emax
r
amma
Emin is the minimum value of the RGB signals in coloured areas
Emax is the maximum value of the RGB signals in coloured areas
gamma is the gamma of the drive-to-output display characteristic.
As a consequence a minor reduction of the maximum displayed saturation will result in a significant reduction of the maximum amplitude of
the colour difference signals, e.g. only 5% reduction of the maximum displayed saturation at maximum intenSity results from 30% reduction
of the electrical saturation at gamma=2.4.
Therefore it is important to take into account that it is most unlikely that natural scenes contain fully saturated colours at maximum intenSity.
PAL and NTSC have been specified such that at maximum saturation the modulated subcarrier would never swing 'blacker-than-black' by
more than 33%. As a consequence the composite signal reaches 100% amplitude at 1/1.33=75% amplitude of saturated colours (yellow and
cyan in 100.0.75.0 EBU colour bars). On the same ground also D2MAC colour difference signals are specified for only 77% maximum
electrical amplitude. Furthermore the most common luminance step colour bar signals used as test signal result in colour difference signals
at 75% of their theoretical maximum amplitude [1].
For these reasons it is supposed that the colour difference signals will most probably not exceed 75% of their theoretical maximum value,
which corresponds to 96% maximum displayed saturation at a practical value of gamma=2.4. 2)
6.2. Ratio of Conversion Factors
For equal amplitudes of the digital signals the ratio of the conversion factors should be inversely proportional to the analog amplitudes. As a
consequence the ratio of the conversion factors for equal peak amplitudes at 75% maximum electrical saturation is given by
1 .
.
1
CF . CF . CF y.
u•
v - y p_p ·0.75 * (B - Y)p_p . 0.75 * (R - Y)p_p
Substitution of (2.2) gives CFy:CFu:CFv=1.0.75:0.95 which, after rounding to simple integers, results in:
(6.2)
2) It should be noted that the gamma of TV cathode ray tubes is about 2.4 whereas the 'transmitted' gamma is nominally 2.8 which results in
an overall gamma of 1.2.
June 1991
1-31
Application Note
Philips Semiconductors Video Products
Digital interfaces for component video signals
AN ETVII R89126
With these simple factors, which will lead to simple (digital) matrixing for Rand B, the probable maximum amplitudes of the digital signals
are practically equal which gives optimum digital resolution.
6.3. UN Gain Matching for PAL and NTSC
In NTSC and PAL the colour difference signals U=(B-V)' and V=(R-V)' used to modulate the subcarrier are reduced in amplitude with respect
to the normalized signals:
(6.3)
(6.4)
U=0.493*(B-V)
V=O.S77*(R-V) 3)
As a consequence gain correction is required to obtain normalized signal amplitudes from the demodulated U and V signals. The required
gain matching ratio, derived from (6.3) and (6.4), equals 0.493/0.S77=9/16. Therefore the ratio CFu/CFv=3/4 fits very conveniently to the
required gain matching ratio for UN from decoded PAL or NTSC signals. If the decoded V signal is first reduced with 3/4 (one adder) then
the remaining 'error' is 3/4, being the desired CFulCFv' The final correction of 3/4, which will result in equal conversion factors, should then
be applied just before or just after DA-conversion to obtain analog colour difference signals with normalized amplitudes, which is common
practice for TV receivers.
7. DIGITAL SIGNAL AMPLITUDES
The worst case margins required for noise and amplitude tolerances are quite large. Linear or statistical addition of these margins would lead to
insufficient digital resolution at quantisation in S bits. As an example, statistical addition of
- 30% headroom for noise (subchapter 7.1)
- lS% tolerance on transmitted burst-to-chrominance ratio [2]
- 2dB gain tolerance of analog decoders (subchapter 7.2)
would require a total range for the colour difference signals of more than two times the nominal value. Therefore the conversion factors have
been chosen such
- that there is sufficient margin in amplitude to handle the tolerance of analog decoders
and
- that the margin is according to the 'headroom' for additive noise as proposed by the EBU for D2MAC signals.
If, for certain applications, the margin is considered as insufficient then a kind of gain control should be applied. Gain control on the CVBS signal
in front of the digital decoder is already common practice (TDAS70S). However automatic gain correction of component signals, i.e. signals
originating from external RGB (SCART) or analog decoders, is far more complicated. Detection and control of the amplitudes should then be
done on the three component signals simultaneously.
7.1. noise
The criterion for noise handling capability in this context is the probability that signal quality is degraded by noise clipping due to signal
quantisation. A probability of one sample per line (about 10-3 ) seems a reasonable measure for good noise behavior. Assuming that the
noise has a Gaussian distribution (white noise), the peak value to be taken into account is then approximately three times the rms value, six
times for the peak-to-peak value.
Signal-to-noise-ratios below OdB are normal operating conditions in the design of TV circuits. E.g. for burst processing it is common practice
to design the subcarrier regenerator for stable output (less than 5 degree rms phase noise) at S/N=-10dB (CVBSp_plNoisenns) [3]. In that
case the required margin for noise amplitude would be approximately twenty times larger then the CVBS signal amplitude.
Although it is unlikely that such a margin is present in the analog prestages at nominal CVBS amplitude, it is obvious that a compromise is
necessary between quantisation noise and the margin for external noise. Therefore the worst probable case of SIN for D2MAC reception is
used as a guideline [4].
In the D2MAC system the carrier is frequency-modulated by the baseband signal [5]. In FM systems there is a rather sharp threshold
between carrier-to-noise ratios for 'good' and 'bad' SIN of the demodulated signal. Therefore the assumption is made that the worst probable
SIN for D2MAC reception occurs at a carrier-to-noise ratio of 11 dB, just above the threshold. That results in an unweighted noise level of
about -26dB (=0.05) [4,6] for the demodulated signal (depending on the filter response of the prestages). That means that 6*0.05=30%
headroom has to be taken into account for additive noise.
7.2. MAC Decoder
MAC decoding in principle is time-demultiplexing. Therefore the MAC decoder is transparent (no internal gain) with respect to digital
amplitudes. If the MAC (mid-range) clamping level is referred to as zero and if the peak-to-peak range is unity, then the MAC signals
according to the D2-MAC specification [5] are transmitted as:
Ym=Y-O.5, Um=O.733*(B-Y) and vm=O.927*(R-Y) ')
3) In NTSC the vectors I and Q are also derived from (B-V)' and (R-V)'.
June 1991
1-32
(7.1)
Application Note
Philips Semiconductors Video Products
AN ETVII R89126
Digital interfaces for component video signals
It is supposed that regarding DC level:
- the digitized grey clamping level equals 128 (analog 'zero' becomes digital 128)
and regarding AC input:
- the ratio between the nominal digital peak-to-peak amplitude and the maximum range (256) of the ADC equals MR (Modulation Range).
then the corresponding digital component signals will be (See Fig. 2):
(7.2)
(7.3)
(7.4)
MY-128+MR*256*(Y-O.5)
MU-128+MR*256*O.733*(B-Y)
MV-128+MR*256*O.927*(R-Y)
D2MAC SPECIFICATION
r~--------~A~--------~\
LINE 624
REFERENCE
LEVELS
NORMALIZED
VALUES
DIGITAL
LEVELS
LUMINANCE
~ ~
r~----------~A~-----------,
._---=
white = +0.5
Y
~
--- ---
1
128
grey = 0
black = -0.5
MR*256
y=o
________ _ _ _..J
~
/
digital]
value = 128+MR*256*
Ym=y-o.5
fanalog
G'alue
Figure 2. Relation Between Analog and Digital D2MAX Baseband Signals
4) The colour difference signals in the D2MAC multiplex are scaled to unity amplitude at 77% of their maximum value. As a consequence the
scale factors for B-Y and R-Yare 1/(0.77*1.772)=0.733 and 1/(0.77*1.402)=0.927 respectively.
June 1991
1-33
Application Note
Philips Semiconductors Video Products
Digital interfaces for component video signals
AN ETV/IR89126
With 30% headroom for additive noise (MR=O.77) the decoded signals (7.2)-(7.4) and the resulting conversion factors become:
MY=197*Y+29
CFy=197
MU=144*(B-Y)+128CFu=3/4*192
MV=183*(R-Y)+128CFv=183=19211.0S
(7.5)
(7.6)
(7.7)
Consequences for interfacing:
- luminance black level should be corrected to 16 (one adder).
- error on CFy results in an acceptable saturation error
- V-signal has to be corrected with 1921183w17/16*63/64 (two adders)
- no correction is needed for the U-signal
7_3. Analog Decoder
An accepted value for the specified tolerance on the output signals of analog colour decoders (e.g.TDA4SSS) is +/-2dB (0.8-1.2S). With a
fixed digital black level of 16 the available range for luminance is 2SS-16+ 1=240. Reduction with 2dB, rounded to the nearest multiple of 4
(resulting in an integer value for CFu), gives a nominal range of 192. That means that the digital interface Signals (CFy=192) can also handle
the amplitude tolerance of analog decoders.
7.4. Digital PAL Decoder
In PAL and NTSC decoders the amplitude of the demodulated U and V signals is, via action of Automatic Colour Control (ACC), directly
related to the amplitude of the colour burst. For PAL the relation can be derived from
BP=peak burst amplitude=317
Substitution in in (6.3) and (6.4) gives
U=l.lS*BP*(B-Y) and V=2.0S*BP*(R-Y)
(7.8)
If the burst peak amplitude in the digital PAL decoder is kept at BP=12S and the amplitude of the V signal is reduced with 3/4 then the
resulting UD and VD signals become:
UD=1.lS*12S*(B-Y)=3/4*192*(B-Y)
(7.9)
VD=3/4*2.0S*12S*(R-Y)=192*(R-Y)
(7.10)
which is in accordance with the desired interface signals (S.l )-(S.3).
7.5. Digital Matrixing
For certain applications, e.g. gamma correction for LCD, it might be required to operate on colour separation signals rather than colour
difference signals. With six adders the YD, UD and VD Signals can be matrixed to digital luminance, red and blue Signals normalized to a
conversion factor of 216.
luminance:
216*Y=9/8*YD
(one adder)
(7.11)
red:
216*R=9/8*YD+3/2*UD
(three adders)
(7.12)
blue:
216*B=9/8*(YD+VD)
(two adders)
(7.13)
These signals cover 90% (216) of the total range from black (16) to maximum (2SS).
8. DATA MULTIPLEXING
The video interface signal according to CCIR Rec.6S6 is based on 4:2:2 sample ratio. For digital TV the 4:1:1 sample ratio is an attractive
alternative, in particular for memory based processing of video originating from decoded CVBS signals. Therefore data formats have been
specified for 4:1:1 and 4:2:2 The luminance and colour difference signals are conveyed as separate data with identical clock rate according to
the luminance sample rate, 13.SMHz or 27MHz in case of frequency doubling. Luminance data is transferred on eight data lines, whereas the
colour difference signals are multiplexed on four or eight data lines.
The 4:2:2 multiplex format is chosen such that it can simply be made from the multiplexed data according to CCIR Rec.6S6.ln the 4:1:1 format
the UD and VD signals are multiplexed on separate data lines. The multiplex formats of the colour difference samples are given in the following
tables together with the cosited luminance sample.
June 1991
1-34
Philips Semiconductors Video Products
Application Note
AN ETV/IR89126
Digital interfaces for component video signals
'4:2:2' format
dataline
Y7
Y6
'4:1:1' format
samplebits
T7
Y6
...
...
YO
YO
C7
C6
V7
V6
samplebits
Y7
76
Y7
Y6
YO
YO
U7
U6
V7
V6
U5
U4
V5
V4
U3
U2
V3
V2
U1
UO
V1
VO
0
1
2
3
... . ..
...
...
. ..
CO
UO
VO
C7
C6
C5
C4
0
1
time-slot
time-slot
U7
U6
nextY
dataline
next Y-samples
The start of the multiplex frame is identified by the positive going edge of a control signal (BLN or HREF or MUX, depending on the integrated
circuit used as source).
9. CONCLUSION
Signal amplitudes and multiplexing formats for digital component video signals as used for interconnecting TV receiver functions are based on
receiver specific requirements. Concerning amplitudes the following criteria are fulfilled:
- digital resolution is practically optimum for 75% colour difference amplitudes.
- signal amplitudes fit conveniently to D2MAC decoders, taking into account 30% headroom for noise.
- UDND ratio fits conveniently to the required gain matching ratio for PAUNTSC colour difference signals.
- amplitude margin is in accordance with the amplitude tolerance of analog decoded signals.
- matrixing to colour selection signals is simple Data multiplexing parameters are specified for:
- 4:2:2 as well as 4:1:1 sample frequency ratio to cope with different bandwidths, in particular for memory applications
- clock frequency equal to luminance sample frequency for application with or without frequency doubling
The following figures give the characteristic amplitudes of the digital component video signals according to the specifications for application in
TV receivers and according to CCIR Rec.601.
June 1991
1-35
Philips Semiconductors Video Products
Application Note
Digital interfaces for component video signals
100 • O. 75 • 0
AN ETVIIR89126
COLOUR BARS (EBU)
100-p
Green (%) 7:
Red
~ J ~ ~ : _________ ...1_______
(%::~
on n-- nn. .
I_
Y=0.299*R + 0.587*G + 0.114*B
1 _ __
10075 Blue(%)
oRECEIVER SIGNALS
NORMALIZED
VALUES(%)
~§
A.
(
;:
0
...J
...J
Z
>-
0
zW
W
a:
(!)
~
zW
\
W
./"-....
ANALOG
DIGITAL
~
A
~
(!)
0
::2
a:
«
w
v
=>
...J
co
\
0
:5co
0.315 V
208
Ya = 0.315*Y
l
----------------52.58- - - - - - - - - - - - - - - - - -
\
~
------------------------l-------------w
100-
(
100% SATURATION
75% INTENSITY
--------l- -------------
16
100
1.05V
INVERTED
0-
R-V
--1-------------I
I
o
-52.58- - - - - - - -
0-
-----t- --------------
--j--------------I
I
Ua=V-b
-66.45- - - - -
------------------------------------TV Receiver Signals for 100.0.75.0 Colour Bars
June 1991
1
Vd = 192*(R-Y)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -101
66.45- - - - - - - - - - - - - - - - - - - - -
B-V
"'----------'
.
Va=Y-R
1-36
95
I
o ~------------~
Ud = 3/4*192*(B-V)
Philips Semiconductors Video Products
Application Note
Digital interfaces for component video signals
100.0.100.0
Green(%) '0:: L
n
Red (%) '0:-_
n
L_
n
__
n
AN ETV/IR89126
COLOUR BARS
n
n
' n
~
_.1""_ _ _.L
_ _ _ _ _ _ __
Y=0.299*R + 0.587*G +0.114*B
______ ...
1 _ _ __
100 Blue(%)
oNORMALIZED
VALUES (%)
~
~
0
~
w
I-
:c
3:
100% SATURATION
CCIR REC.601
100% INTENSITY
DIGITAL SIGNALS
A.
(
3:
0
...J
...J
w
>-
100-
Z
~
()
~
Z
Z
a:
~
W
W
"
W
~
(
\
C
w
a:
W
::J
...J
m
A
~
~
m
235
219*Y+16
Y
o70.10- - - - - - - - - - - - - - - - - - - -
R-Y
- - - - - - - - - -
240
- - -
128
0-
-70.10- - - - - - - - -
16
_ _ _ _ _ _ _ 240
88.60- - - - - - - - - - - - - - - - - - _ - - - __
B-Y
160*(R-Y)+ 128
0-
- - -
- - - - - - - - - - - - - - - - - - - - - - - - -
128
126*(B-Y)+128
16
Digital Component Video Signals According to CCIR Rec. 601 for 100.0.100.0 Colour Bars
June 1991
1-37
\
Philips Semiconductors Video Products
Application Note
Digital interfaces for component video signals
AN ETVIIR89126
REFERENCES
[1]
CCIR Recommendation 471-1; "Nomenclature and description of colour bar signals"
[2]
IBA Technical Review, part 2 Technical Reference Book, July 1974
[3]
Donald Richman; Proc. IRE, vol. 43, 1954; "Colour-carrier reference phase synchronization accuracy In NT8C colour television"
[4]
Appendix to part 2 of [5]; "Guidelines for system Implementation"
[5]
EBU Technical centre; Tech.3258-E; October 1986; "Specification of the systems of the MAC/packet family" ,
[6]
Amo Neelen, Philips Components division, PCAlE; private communication.
June 1991
1-38
Philips Semiconductors Video Products
Encoding parameters of digital television for studios
CCIR REC. 601-2
RECOMMENDATION 601-2
ENCODING PARAMETERS OF DIGITAL TELEVISION FOR STUDIOS·
(Question 25/1 t, Study Programmes 25G/I I, 251-1/1 I)
(1982- 1986- t 990)
Thc CClR,
CONSIDERING
(a)
that there are clear advantages for television broadcasters and programme producers in digital studio
standards which have the greatest number of significant parameter values common to 525-line and 625-line
systems;
(b)
that a world-wide compatible digital approach will permit the development of equipment with many
common features, permit operating economies and facilitate the international exchange of programmes;
(c)
that an extensible family of compatible digital coding standards is desirable. Members of such a family
could correspond to different quality levels, facilitate additional processing required by present production
techniques, and cater for future needs;
(d)
that a system based on the coding of components is able to meet some, and perhaps all, of these desirable
objectives;
(e)
that the co-siting of samples representing luminance and colour-difference signals (or, if used, the red,
green and blue signals) facilitates the processing of digital component signals, required by present production
techniques,
UNANIMOUSLY RECOMMENDS
that the following be used as a basis for digital coding standards for television studios in countries using
the 525-line system as well as in those using the 625-line system:
1.
Component coding
The digital coding should be based on the use of one luminance and two colour-difference signals (or, if
used, the red, green and blue signals).
The spectral characteristics of the signals must be controlled to avoid aliasing whilst preserving the
passband response. When using one luminance and two colour-difference signals as defined in Table I of
RECOMMENDS 4, suitable filters are defined in Annex III, Figs. 1 and 2. When using the E'R, E'G, E'n signals
or luminance and colour-difference signals as defined in Table II of Annex 1, a suitable filter characteristic is
shown in Fig. 1 of Annex Ill.
Main digital television terms used in the Recommendation are defined in Report 629.
1-39
Encoding parameters otdigital televi;sian, for studios
2.
Extensible family of compatible digital coding standards
The digital coding should- alloW the establishrrtentandevolution
digital coding standards.
of an'extensiblefamily
of compatible
It should be possible to interface simply between any two members of the family.
The member of the family to be used for the standard digital interface between main digital studio
equipment, and for international programme exchange (i.e. for the interface with video recording equipment and
for the interface with the transmission system) should be that in which the luminance and colour-difference
sampling frequencies are related in the ratio 4 : 2 : 2.
In a possible higher member of the family the sampling frequencies of the luminance and colour-difference
signals (or, if used, the red, green and blue signals) could be related by the ratio 4 : 4 : 4. Tentative specifications
for the 4 : 4: 4 member are included in Annex I (see Note).
Note - Administrations are urgently requested to conduct further studies in order to specify parameters of the
digital standards for other members of the family. Priority should be accorded to the members of the family below
4 : 2 : 2. The number of additional standards specified should be kept to a minimum.
3.
Specifications applicable to any member of the family.
3.1
Sampling structures should be spatially static. This is the case, for example, for the orthogonal sampling
structure specified in § 4 of the present Recommendation for, the 4 : 2 .: 2 member of the family.
If the samples represent luminance and two simultaneous colour~difference signals, each pair of
samples should be spatially co-sited. If samples representing' red, green and blue signals are used
they should be co-sited.
3.2
colour~difference
3.3
The digital standard adopted for each member of the family should permit world-wide acceptance and
application in operation; one condition to achieve this goal is that, for'each member of the family, the number of
samples per line specified for 525-line and 625-line systems shall be compatible (preferably the same number of
samples per line).
4.
Encoding parameter values for the 4 : 2 : 2 member of the family
The following specification (Table I) applies to' the 4:2 : 2' meniber of the family, to be used for the'
standard digital interface between main digital studio equipment and for international programme exchange.
1-40
Philips Semiconductors Video Products
Encoding parameters of digital television for studios
TABLE I -
CCIR REC. 601-2
Encoding parameter values for the 4 " 2 " 2 member of the family
525-line,60 field/s
systems
•Parameters
I. Coded signals: Y, CR , Cs
e)
625-line, 50 field/s
systems
e)
These signals are obtained from gamma pre-corrected signals, namely: E'y,
E'R - E'y, E's - E'y {Annex II, § 2 refers)
2. Number of samples per total line:
- luminance signal (Y)
858
864
-
429
432
each colour-difference signal
(CR, Cs )
3. Sampling structure
4.
Orthogonal, line, field and frame repetitive. CR and Cs samples co-sited with
odd (1st, 3rd, 5th, etc.) Ysamples in each line
Sampling frequency:
- luminance signal
-
13.5 MHz
6.75 MHz
each colour-difference signal
e)
e)
The tolerance for the sampling frequencies should coincide with the tolerance
for the line frequency of the relevant colour television standard
5. Form of coding
Uniformly quantized PCM, 8 bits per sample, for the luminance signal and
each colour-difference signal
6. Number of samples per digital
active line:
- luminance signal
- each colour-difference signal
720
360
7. Analogue-to-digital horizontal
timing relationship:
-
from end of digital active line
to OH
16 luminance clock periods
12 luminance clock periods
8. Correspondence between video
signal levels and quantization
levels:
-
scale
o to 255
- luminance signal
220 quantization levels with the black level corresponding to level 16 and the
peak white level corresponding to level 235. The signal level may occasionally
excurse beyond level 235
-
225 quantization levels in the centre part of the quantization scale with zero
signal corresponding to level 128
each colour-difference signal
9. Code-word usage
Code-words corresponding to quantization levels 0 and 255 are used
exclusively for synchronization. Levels 1 to 254 are available for video
e) See Report 624, Table I.
e) The sampling frequencies
of 13.5 MHz (luminance) and 6.75 MHz (colour-difference) are integer mUltiples of
2.25 MHz, the lowest common multiple of the line frequencies in 525/60 and 625/50 systems, resulting in a static
orthogonal sampling pattern for both.
1-41
Philips Semiconductors Video Products
Encoding parameters of digital television for studios
CCIR REC. 601-2
ANNEX I
TENTATIVE SPECIFICATION OF THE 4: 4: 4 MEMBER OF THE FAMILY
This Annex provides for information purposes a tentative specification for the 4: 4 : 4 member of the
family of digital cOding standards.
The following specification could apply to the 4 : 4: 4 member of the family suitable for television source
equipment and high quality video signal processing applications.
TABLE II -
A telltative specification for the 4 : 4 : 4 member of the family
I. Coded signals: Y, CR, Co
or R, G. B
These signals are obtained from gamma pre-corrected signals, namely: E'y,
E'R - E'y, E'n - E'yor E'R. E'G. E'/i
2. Number of samples per total line
for each signal
3. Sampling structure
864
858
Orthogonal, line, field and frame repetitive. The three sampling structures to
be coincident and coincident also with the luminance sampling structure of
the 4 : 2 : 2 member
4. Sampling frequency for each
signal
5. Form of coding
625-line, 50 field/s
systems
525-line, 60 field/s
systems
Parameters
13.5 MHz
Uniformly quantized PCM. At least 8 bits per sample
6. Duration of the digital active line
At least 720
expressed in number of samples
7. Correspondence between video
signal levels and the 8 most
significant bits (MBS) of the
quantization level for each
sample:
-
o to 255
scale
- R, G, B or luminance
signal
e)
- each colour-difference
signal (')
220 qu()ntization levels with the black level corresponding to level 16 and the
peak with level corresponding to level 235. The signal level may occasionally
excurse beyond level 235
225 quantization levels in the centre part of the quantization scale with zero
signill corresponding to level 128
(') If used.
1-42
Philips Semiconductors Video Products
CCIR REC.601-2
Encoding parameters of digital television for studios
ANNEX II
DEFINITION OF SIGNALS USED IN THE DIGITAL CODING STANDARDS
1.
Relationship of digital active line to analogue sync. reference
The relationship between 720 digital active line luminance samples and the analogue synchronizing
references for 625-Iine and 525-Iine systems is shown below.
TABLE III
S25-line,
60 field/s
systems
I
I
I
I
122 T
I
I
I
I
I
I
I
I
I
I
16 T
no T
i
I
I
I
OH
Digital active-line
period
(leading edge of line syncs.,
half-amplitude reference)
I
I
I
OH
I
I
I
62S-line,
50 fieJd/s
systems
I
I
I
I
I
Next line
132 T
12 T
nOT
I
I
I
I
I
I
T: one luminance sampling clock period (74 ns nominal).
The respective numbers of colour-difference samples can be obtained by dividing the number of luminance
samples by two. The (12, 132) and (16, 122) were chosen symmetrically to dispose the digital active line about the
permitted variations. They do not form part of the digital line specification and relate only to the analogue
interface.
1.
Definition of the digital signals Y, CR, CB, from the primary (analogue) signals E'R' E'G and E'B
This section describes, with a view to defining the signals Y, CR , CB , the rules for construction of these
signals from the primary analogue signals E'R' E'G and E's. The signals are constructed by following the three
stages described in § 2.1, 2.2 and 2.3 below. The method is given as an example, and in practice other methods of
construction from these primary signals or other analogue or digital signals may produce identical results. An
example is given in § 2.4.
2.1
Construction o/Iuminance (E'y) and colour-difference (E'R - E'y) and (E'B - E'y) signals
The construction of luminance and colour-difference signals is as follows:
E'y == 0.299ER
+
0.587Ee,
+
0.114Es
(See Note)
whence:
(ER - E'y) .. ER -0.299E R ...: 0.587Ee, - 0.114Es
- 0.701ER - O.587Ee, - 0.114Es
and:
(Es - E'y)
Es - 0.299E R - 0.587 Ee, - 0.1 14Es
- 0.299ER - 0.587 Be, + 0.886Es
Note. -
Report 624 Table II refers.
1-43
Philips Semiconductors Video Products
Encoding parameters of digital television for studios
CCIR: REC. 601-2
Taking the signal values as normalized to unity (e.g., 1.0 V maximum levels), the values obtained for
white, black and the saturated primary and complementary colours are as follows:
TABLE IV
2.2
Condition
E'R
E'G
E'B
E'y
E'R - E'y
E'B - E'y
White
1.0
1.0
1.0
1.0
0
0
Black
0
0
0
0
0
0
Red
1.0
0
0
0.299
0.701
-0.299
-0.587
Green
0
1.0
0
0.587
-0.587
Blue
0
0
1.0
0.114
-0.114
0.886
-0.886
Yellow
1.0
1.0
0
0.886
0.114
Cyan
0
1.0
1.0
0.701
-0.701
0.299
Magenta
1.0
0
1.0
0.413
0.587
0.587
Construction of re-normalized colour-difference signals (E 'eR and E 'eB )
Whilst the values for E'y have a range of 1.0 to 0, those for (E'R - E'y) have a range of +0.701 to
-0.701 and for (E'B -:- E'y) a range of+0.886 to -0.886. T9 restore the signal excursion of the colour-difference
signals to unity (i.e. + 0.5 to -- 0.5), coefficients can be calculated as follows:
K-~
R -
0.701 "'" 0.713; KB
=
0.5
0.886 = 0.564
Then:
E'eR
=
0.713 (ER - E'y) = 0.500E R - 0.419E 6 - 0.081Eo
and:
E'eB
=
0.564 (Eo - E'y)
=
-0.169E R - 0.331E 6 + 0.500E o
where E'eR and E'eB are the re-normalized red and blue ((olour-difference signals respectively (see Notes 1 and 2).
Note J - The symbols E'eR and E'eB will be used only to designate re-normalized colour-difference signals,
i.e. having the same nominal peak-to-peak amplitude as the luminance signal E'y, thus selected as the reference
amplitude.
Note 2 - In the circumstances when the component signals are not normalized to a range of 1 to 0, for example,
when converting from analogue component signals with unequal luminance and colour-difference amplitudes, an
additional gain factor will be necessary and the gain factors K R , KB should be modified accordingly.
1-44
Philips Semiconductors Video Products
Encoding parameters of digital television for studios
2.3
CCIR REC. 601-2
Quantization
In the case of a uniformly-quantized 8-bit binary encoding, 28, i.e. 256, equally spaced quantization levels
are specified, so that the range of the binary numbers available is from 0000 0000 to 1111 till (00 to FF in
hexadecimal notation), the equivalent decimal numbers being 0 to 255, inclusive.
In the case of the 4: 2 : 2 system described in this Recommendation, levels 0 and 255 are reserved for
synchronization data, while levels 1 to 254 are available for video.
Given that the luminance signal is to occupy only 220 levels, to provide working margins, and that black
is to be at level 16, the decimal value of the luminance signal, Y, prior to quantization, is:
Y
= 219 (E'y)
+
16,
and the corresponding level number after quantization is the nearest integer value.
Similarly, given that the colour-difference signals are to occupy 225 levels and that the zero level is to be
level 128, the decimal values of the colour-difference signals, CR and CB , prior to quantization are:
CR = 224 [0.713 (E'R - E'y)] + 128
and:
CB = 224 [0.564 (E'B - E'y)] + 128
which simplify to the following:
CR = 160 (E'R - E'y)] + 128
and:
CB
=
126 (E's - E'y)]
+ 128
and the corresponding level number, after quantization, is the nearest integer value.
The digital equivalents are termed Y, CR and CB.
2.4
Construction of Y, CR , CB via quantization of E'R, E'G, E'B
In the case where the components are derived directly from the gamma pre-corrected component signals
E'R, E'G, E'B, or directly generated in digital form, then the quantization and encoding shall be equivalent to:
+ 16
+ 16
E'R o (in digital form)
=
int (219 E'R)
E'Go (in digital form)
E'Bn (in digital form)
=
int (219 E'G)
=
int (219 E's) + 16
Then:
Y
=
77 E'
256 Ro
131
CR = 256 ERo -
CB =
-
~
256
E'
Ro -
+ 150
256 E Gn
+
29
256 Eoo
1 to
21
256 EGo - 256 EOn
87 E'
256 Go
+ ~
256
+
Eoo
128
+ 128
taking the nearest integer coefficients, base 256. To obtain the 4 : 2 : 2 components Y, CR , CB , low-pass filtering
and sub-sampling must be performed on the 4: 4: 4 CR , C B signals described above. Note should be taken that
slight differences could exist between CR , CB components derived in this way and those derived by analogue
filtering prior to sampling.
1-45
Philips Semiconductors Video Products
celR REG. 601-2
Encoding parameters of digital television for studios
ANNEX III
FILTERING CHARACTERISTICS
50
40
~"~
~
30
0..,'" 0..,'"i\."'"r--"'"
I -
~~ 40dB--'-
~
20
~
~
~
10
~"'\,,
1
0
~
l'''''\'' ,-"",\" 0..'\""\' l'''''"\"5l'''~
2
3
4
6
5.75
~
~12 dB
i'
~
7
6.75
8
9
10
11
a) Template for insertion loss/frequency characteristic
0.05
0.1dB
Frequency (MHz)
5.75
b) Passband ripple tolerance
5.75
c) Passband group-delay tolerance
FIGURE 1 - Specification for a luminance or RGB signal filter
used when sampling at 13:5 MHz
Note - The lowest indicated values in b) and c) are for 1 kHz (instead of 0 MHz).
1-46
13
t
13.5
Frequency (MHz)
Frequency (MHz)
12
14
15
Philips Semiconductors Video Products
Encoding parameters of digital television for studios
CCIR REC. 601-2
50
I
30
~"-"-" ~"-"-~ 10-"-"-" ,,"'""- '\ r--."'""-"-'\ r'--"-"-'" 40dB~
1'-
20
~
40
"'"
~
~
~
~.
~
10
~
0-.",,"-'0
1'\' ' ' ' ' ' '1l'--"",,,,\: ~""'\2 ~""-" [\,.~
~6dB
~ 1'' ' ' ' ' ' ' ~'
t
4
3.375
Frequency (MIIz)
3
2.75
5
t
6
6.75
a) Template for insertion loss/frequency characteristic
0.1
- 0.1
L..--------''---------'-----r--J
2.75
frequency (MHz)
b) Passband ripple tolerance
20
4n'~~~----10
-20
0
Frequency (Mllz)
' - - - - J dB loss frequency
c) Passband group-delay tolerance
FIGURE 2 - Specification for a colour·difference signal filter used when sampling at 6.75 MHz
Note - The lowest indicated values in b) and c) are for 1 kllz (instead of 0 MHz).
1-47
7
Philips Semiconductors Video Products
CCIR REC. 601-2
Encoding parameters of digital television for studios
60
..---.-
50
~
40
See Note 3 -
10
~'""-" k.."-"-"-"- t--"-"-'"' ~"-"-" '-"-"-"-"'-
0
1
2
~
t
2.75
m:\
55 dB
~
~
~
~
~
"-" ~6dB
.....
,,~
'-"" '
~"
1
\
~
~ \
20
~
~ I'
~ \\.""~
~ ",,-
3
4
3.375
Frequency (MHz)
5
6
t
t
6.25
6.75
7
a) Template for insertion loss/frequency characteristic
0.1
0.5
Jo.'.8
;;
~
- 0.5
- 0.1 0
2.75
Frequency (MHz)
b) Passband ripple tolerance
FIGURE 3 - Specification for a digital filter for sampling:rate conversion
from 4: 4 : 4 to 4 : 2 : 2 colour-difference signals
Notes to Figs. 1,2 and 3:
Note 1 - Ripple and group delay are specified relative to their values at 1 kHz. The full lines are practical limits and. the
dashed lines give suggested limits for the theoretical design.
Note 2. - In the digital filter, the practical and design limits are the same. The delay distortion is zero, by design.
Note 3 - In the digital filter (Fig. 3), the amplitude/frequency characteristic (on linear scales) should be skew-symmetrical
about the half-amplitude point, which is indicated on the figure.
'
Note 4 - In the proposals for the filters used in the encoding and decoding processes, it has been assumed that, in the postfilters which follow digital-to-analogue conversion, correction for the (sin x/x) characteristic of the sample-and-hold circuits
is provided.
1-48
Philips Semiconductors Video Products
RECOMMENDATIONS OF THE CCIR, 1990
CCIR 656
(ALSO RESOLUTIONS AND OPINIONS) VOLUME XI- PART 1
BROADCASTING SERVICE (TELEVISION)
CCIR
1. The International Radio Consultative Committee (CCI R) is the permanent organ of the International Telecommunication Union responsible
under the International Telecommunication Convention " ...to study technical and operating questions relating specifically to
radiocommunications without limit of frequency range, and to issue recommendations on them ..." (International Telecommunication
Convention, Nairobi 1982, First Part, Chapter I, Art. 11, No. 83).1
2. The objectives of the CCIR are in particular:
a. to provide the technical bases for use by administrative radio conferences and radiocommunication services for efficient utilization of the
radio-frequency spectrum and the geostationary-satellite orbit, bearing in mind the needs of the various radio services;
b. to recommend performance standards for radio systems and technical arrangements which assure their effective and compatible
interworking in international telecommunications;
c. to collect, exchange, analyze and disseminate technical information resulting from studies by the CCIR, and other information available, for
the development, planning and operation of radio systems, including any necessary special measures required to facilitate the use of such
information in developing countries.
1.
See also the Constitution of the ITU, Nice, 1989, Chapter 1, Art. 11, No. 84.
CCIR International Radio Consultative Committee
1-49
Geneva, 1990
Philips Semiconductors Video Products
RECOMMENDATIONS OF THE CCIH, 1990
CCIR 656
Rec.656
RECOMMENDATION 656
~
,
INTERFACES FOR DIGITAL COMPONENT VIDEO SIGNALS
IN 525-LlNE AND 625-LlNE TELEVISION SYSTEMS
(1986)
The CCIR,
CONSIDERING
a. that there are clear advantages for television broadcasting organizations and programme producers in digital studio standards which have
the greatest number of significant parameter values common to 525-line and 625-line systems;
b. that a world-wide compatible digital approach will permit the development of equipment with many common features, permit operating
economies and facilitate the international exchange of programmes;
c. that to implement the above objectives, agreement has been reached on the fundamental encoding parameters of digital television for
studios in the form of Recommendation 601;
d. that the practical implementation of Recommendation 601 requires definition of details of interfaces and the data streams traversing them;
e. that such interfaces should have a maximum of commonality between 525-line and 625-line versions;
f. that in the practical implementation of Recommendation 601 it is desirable that interfaces be defined in both serial and parallel forms;
g. that digital television signals produced by these interfaces may be a potential source of interference to other services, and due notice must
be taken of No. 964 of the Radio Regulations,
UNANIMOUSLY RECOMMENDS
that where interfaces are required for component-coded digital video signals in television studios, the interfaces and the data streams
that will traverse them should be in accordance with the following description, defining both bit-parallel and bit-serial implementations.
1.
Introduction
This Recommendation describes the means of interconnecting digital television equipment operating on the 525-line or 625-line
standards and complying with the 4 : 2 : 2 encoding parameters as defined in Recommendation 601.
Part I describes the signal format common to both interfaces.
Part II describes the particular characteristics of the bit-parallel interface.
Part III describes the particular characteristics of the bit-serial interface.
PART I
COMMON SIGNAL FORMAT OF THE INTERFACES
1.
General description of the interfaces
The interfaces provide a unidirectional interconnection between a single source and a single destination.
A signal format common to both parallel and serial interfaces is described in § 2 below.
CCIR International Radio Consultative Committee
1-50
Philips Semiconductors Video Products
RECOMMENDATIONS OF THE CCIR, 1990
CCIR 656
Rec.656
The data signal are in the form of binary information coded in 8-bit words. These signals are:
- video data;
- timing reference codes;
- ancillary data;
- identification codes.
2.
Video data
2.1
Coding characteristics
The video data is in compliance with Recommendation 601, and with the field-blanking definition shown in Table 1.
TABLE 1- Field interval definitions
625
525
V-digital field blanking
Finish
(V=O)
Field 1
Field 2
Line 624
Line 1
Start
(V= 1)
Line 23
Line 10
Start
(V=1)
Line 311
Line 264
Finish
(V=O)
Line 336
Line 273
F-digital field identification
Field 1
F=O
Line 1
Line 4
Field 2
F=1
Line 313
Line 266
Note 1 - Signals F and V change state synchronously with the end of active
video timing reference code at the beginmng of the digital line.
Note 2 - Definition of line numbers is to be found in Report 624. Note that
digital line number changes state prior to OH as shown in Fig. 1.
2.2
Video data format
The data words 0 and 255 (00 and FF in hexadecimal notation) are reserved for data identification purposes and consequently only 254
of the possible 256 words may be used to express a signal value.
The video data words are conveyed as a 27 Mwords/s multiplex in the following order:
Ca, Y, CR, Y, Ca, Y, CR, etc.
where the word sequence
next luminance sample.
Ca, Y,
CR, refers to co-sited luminance and colour-difference samples and the following word, Y, corresponds to the
CCIR International Radio Consultative Committee
1-51
Philips Semiconductors Video Products
RECOMMENDATIONS OF THE CCIR, 1990
CCIR 656
Rec.656
2.3
Timing relationship between video data and the analogue synchronizing waveform
2.3.1
Line interval
The digital active line begins at 244 words (in the 525-line standard) or at 264 words (in the 625-line standard) after the leading
edge of the analogue line synchronization pulse. this time being specified between half-amplitude pOints.
Figure 1 shows the timing relationship between video and the analogue line synchronization.
Analogue line blinking
----1
f'---...
./'l
II
7r
I-
"I'"
~
J
I
-- OH
L,
0H
J
TV line
---
16T(625) Nom
8T(525)
.
20T(625) Nom
10T(525)
.
Video data block
24T(625)
32 T (525)
---
64l.1.s (625)
63.5 I.I.s (525)
1'1
~I
I
1448T
-~-1
4T
Digital line blanking
288T(625)
276T(525)
Digital active line
1440T(625)
Digital line
1728T(625)
1716T(525)
FIGURE 1 - Data format and timing relationship with the analogue video signal
T:
clock period 37 ns nom.
SAV: start of active video timing reference code
EAV: end of active video timing reference code
CCIR International Radio Consultative Committee
'--
Philips Semiconductors Video Products
RECOMMENDATIONS OF THE CCIR, 1990
CCIR 656
Ree.6S6
2.3.2
Field interval
The start of the digital field is fixed by the position specified for the start of the digital line: the digital field starts 32 words (in
the 525-line systems) and 24 words (in the 625-line systems) prior to the lines indicated in Table I.
2.4
Video timing reference codes (SA V; EAV)
There are two timing reference codes, one at the beginning of each video data block (Start of Active \t1deo, SAY) and one at the end of
each video data block (End of Active \t1deo, EAV) as shown in Fig. 1.
Each timing reference code consists of a four word sequence in the following format: FF 00 00 XV. (Values are expressed in
hexadecimal notation. Codes FF, 00 are reserved for use in timing reference codes.) The first three words are a fixed preamble. The fourth
word contains information defining field 2 identification, the state of field blanking, and the state of line blanking. The assignment of bits within
the timing reference code is shown below in Table II.
TABLE 11- Video timing reference codes
Bit No.
Word
7 (MSB)
6
5
4
3
2
1
o (MSB)
First
1
1
1
1
1
1
1
1
Second
0
0
0
0
0
0
0
0
Third
0
0
0
0
0
0
0
0
Fourth
1
F
V
H
P3
P2
P1
Po
F = 0 during field 1
1 during field 2
V = 0 elsewhere
1 during field blanking
H= OinSAV
1 in EAV
Po, P1, P2, P3: protection bits (see Table III).
MSB: most significant bit
LSB: least significant bit
CCIR International Radio Consultative Committee
1-53
Philips Semiconductors Video Products
RECOMMENDATIONS OF THE CCIR, 1990
CCIR 656
Rec.656
Table I defines the state of the V and F bits.
Bits Po, P1, P2, P3, have states dependent on the states of the bits F, V and H as shown in Table III. At the receiver this arrangement
permits one-bit errors to be corrected and two-bit errors to be detected.
TABLE III - Protection bits
2.5
Bit No.
7
6
5
4
3
2
1
0
Function
Fixed 1
F
V
H
P3
P2
P1
Po
0
1
0
0
0
0
0
0
0
1
1
0
0
1
1
1
0
1
2
1
0
1
0
1
0
1
1
3
1
0
1
1
0
1
1
0
4
1
1
0
0
0
1
1
1
5
1
1
0
1
1
0
1
0
6
1
1
1
0
1
1
0
0
7
1
1
1
1
0
0
0
1
Ancillary data
Provision is made for ancillary data to be inserted synchronously into the multiplex during the blanking intervals at a rate of 27 Mwords/s.
Such data is conveyed by one or more 7-bit words, each with an additional parity bit (LSB) giving odd parity.
Each anCillary data block, when used, should be constructed as shown in Table IV from the timing reference code ANC and a data field.
2.6
Data words during blanking
The data words occurring during digital blanking intervals that are not used for the timing reference code ANC or for ancillary data are
filled with the sequence 80, 10,80, 10, etc. (values are expressed in hexadecimal notation) corresponding to the blanking level of the Ca, Y, CR,
Y signals respectively, appropriately placed in the multiplexed data.
CCIR Intemational Radio Consultative Committee
1-54
Philips Semiconductors Video Products
RECOMMENDATIONS OF THE CCIR, 1990
CCIR 656
Rec.656
TABLE IV -
Word
Ancillary data block
ANCcode
I" 0
I, I FF I:F I ~ I M4MI :L I: I~B
00
'/'-.../'t"
L o a : words
(00, FF excluded)
Word count or line number (Note 1)
Bit
WordMM
Word LL
7
6
5
432
1
0
I 0 ID111D1g 0 9 1Dsl 0 7 10 6 1 pi
10 10510410310,1011J 1
Odd word parity
L...-_ _ _ _
L...._ _ _ _ _ _ _ _ _
Data type (Note 1)
Fixed pattem
"Word counf specifies the length of the data field and lies in the range 1 to 1434. If word TT
specifies a line number then 011 to Do contain the binary equivalent of the line number and
the word count is assumed to be zero. The ancillary data block(s) may be transmitted when
time is available during horizontal or vertical blanking following the EAV timing reference
signal.
Note 1 - The precise location of the ancillary data blocks and the coding of words 3, 4 and 5 require
further study.
PART II
BIT-PARALLEL INTERFACE
1.
General description of the interface
The bits of the digital code words that describe the video signal are transmitted in parallel by means of eight conductor pairs, where each
carries a multiplexed stream of bits (of the same significance) of each of the component signals, Ca, Y, ~, Y. The eight pairs also carry
ancillary data that is time-multiplexed into the data stream during video blanking intervals. A ninth pair provides a synchronous clock at 27MHz.
The signals on the interface are transmitted using balanced conductor pairs. Cable lengths of up to 50 m (= 160 feet) without
equalization and up to 200 m (= 650 feet) with appropriate equalization (see § 6) may be employed.
The interconnection employs a twenty-five pin D-subminiature connector equipped with a locking mechanism (see § 5).
For convenience, the eight bits of the data word are assigned the names DATA 0 to DATA 7. The entire word is designated as DATA
(0-7). DATA 7 is the most significant bit.
Video data is transmitted in NRZ form in real time (unbuffered) in blocks, each comprising one active television line.
2.
Data signal format
The interface carries data in the form of 8 parallel data bits and a separate synchronous clock. Data is coded in NRZ form. The
recommended data format is described in Part I.
CCIR International Radio Consultative Committee
1-55
Philips Semiconductors Video Products
RECOMMENDATIONS OF THE CCIR, 1990
CGIR 656
Rec.656
3.
Clock signal
3.1
General
The clock signal is a 27 MHz square wave where the 0-1 transition represents the data transfer time. This signal has the following
characteristics:
3.2
Width:
18.5 ± 3 ns
Jitter:
less than 3 ns from the average period over one field.
Clock-to-data timing relationship
The positive transition of the clock signal shall occur midway between data transitions as shown in Fig. 2.
Timing reference
for data and clock
I
~
FIGURE 2 -
Clock-to-data timing (at source)
=
1
1728
IH
= 37ns
Clock period (625):
T
Clock period (525):
T=~=
1
37ns
IH
Clock pulse width:
t =
Data timing - sending end:
td =
18.5 ± 3ns
18.5 ± 3ns
fH: line frequency
4.
Electrical characteristics of the interface
4.1
General
The interface employs nine line drivers and nine line receivers.
Each line driver (source) has a balanced output and the corresponding line receiver (destination) a balanced input (see Fig. 3).
Although the use of ECl technology is not specified, the line driver and receiver must be ECl-compatible, i.e. they must permit the use of
ECl for either drivers or receivers.
All digital signal time intervals are measured between the half-amplitude points.
CCIR International Radio Consultative Committee
1-56
Philips Semiconductors Video Products
CCIR 656
RECOMMENDATIONS OF THE CCIR, 1990
Rec.656
Transmission
line
Source
B
FIGURE 3 -
4.2
Destination
I
I
I
I
Line driver and line receiver interconnection
Logic convention
The A terminal of the line driver is positive with respect to the B terminal for a binary 1 and a negative for a binary 0 (see Fig. 3).
4.3
4.4
Line driver characteristics (source)
4.3.1
Output impedance: 110 n maximum
4.3.2
Common mode voltage: -1.29 V ± 15% (both terminals relative to ground).
4.3.3
Signal amplitude: 0.8 to 2.0 V peak-to-peak, measured across a 110 n resistive load.
4.3.4
Rise and fall times: less than 5 ns, measured between the 30% and 80% amplitude points, with a
110 n resistive load. The difference between rise and fall times must not exceed 2 ns.
Line receiver characteristics
4.4. 1
Input impedance: 110 n ± 10 n.
4.4.2
Maximum input signal: 2.0 V peak-ta-peak.
4.4.3
Minimum input signal: 185 mV peak-to-peak.
However, the line receiver must sense correctly the binary data when a random data signal produces the conditions
represented by the eye diagram in Fig. 4 at the data detection point.
4.4.4
Maximum common mode signal: ± 0.5 V, comprising interference in the range 0 to 15 kHz (both
terminals to ground).
4.4.5 Differential delay: Data must be correctly sensed when the clock-to-data differential delay is in the
range between ± 11 ns (see Fig. 4).
5.
Mechanical details of the connector
The interface uses the 25 contact type D subminiature connector specified in ISO Document 2110-1980, with contact assignment shown
in Table V.
Connectors are locked together by a one-piece slide lock on the cable connectors and locking posts on the equipment connectors.
Connectors employ pin contacts and equipment connectors employ socket contacts. Shielding of the interconnecting cable and its connectors
must be employed (see Note).
Note - It should be noted that the ninth and eighteenth harmonics of the 13.5 MHz sampling frequency (nominal value) specified in
Recommendation 601 fall at the 121.5 and 243 MHz aeronautical emergency channels. Appropriate precautions must therefore be taken in the
design ad operation of interfaces to ensure that no interference is caused at these frequencies. Emission levels for related equipment are given
in CISPR Recommendation: "Information technology equipment -limits of interference and measuring methods" Document CISPRIB (Central
Office) 16. Nevertheless, No. 964 of the Radio Regulations prohibits any harmful interference on the emergency frequencies.
CCIR International Radio ConsUltative Committee
1-57
Philips Semiconductors Video Products
RECOMMENDATIONS OF THE CCIR, 1990
CCIR 656
Rec.656
Vmin
j\.
FIGURE 4 -
Reference transition
of clock
Idealized eye diagram corresponding to the minimum input signal level
Tmin = 11 ns
Vmin = 100mV
Note - The width of the window in the eye diagram, within which data must be
correctly detected comprises ±3 ns clock jitter, ±3 ns data timing (see § 3.2),
and ±5 ns available for differences in delay between pairs of the cable.
TABLE V Contact
Contact assignments
Signal line
1
Clock A
Contact
Signal line
14
Clock B
System ground
2
System ground
15
3
Data 7A (MSB)
16
Data 7B
4
Data6A
17
Data6B
5
Data5A
18
Data5B
6
Data4A
19
Data 4B
7
Data3A
20
Data3B
8
Data2A
21
Data 2B
9
Data 1A
22
Data 1B
10
DataQA
23
DataOB
11
Spare A-A
24
SpareA-B
12
Spare B-A
25
Spare B-B
13
Cable shield
-
-
CCIR International Radio Consultative Committee
1-58
Philips Semiconductors Video Products
CCIR 656
RECOMMENDATIONS OF THE CCIR, 1990
Rec.656
Any spare pairs connected to contacts 11,24 or 12,25 are reserved for bits of lower significance than those carried on contacts 10,23.
6.
Line receiver equalization
To permit correct operation with longer interconnection links, the line receiver may incorporate equalization.
When equalization is used, it should conform·to the nominal characteristics of Fig. 5. This characteristic permits operation with a range of
cable lengths down to zero. The line receiver must satisfy the m~ximum input signal condition of § 4.4
/
.
20
./
18
V
./
I
IV
16
/'rl
14
I
m 12
:8.
c
·iii
Cl
.,>
Q)
/
10
V
I'CI
Qi
II:
V
8
6
//
4
V
I
J
u>c
Q)
::J
C"
>u
~
.~
a.
f--
m
-
E
Q)
~
g
U
c
I'CI
.~ I
::J
...J
::J
C"
~
u
/
cQ)
f--
~
'S·I
~
~
2
o
0.1
--I---
~
~
0.2
FIGURE 5 -
0.5
2
5
Frequency (MHz)
10
20
50
Line receiver equalization characteristic for small signals
PART III
BIT-SERIAL INTERFACE
1.
General description of the interface
The multiplexed data stream of 8-bit words (as described in Part I) is transmitted over a single channel in bit-serial form. Prior to
transmission, additional coding takes place to provide spectral shaping, word synchronization and to facilitate clock recovery.
2.
Coding
The 8-bit data words are encoded for transmission into 9-bit words as shown in Table VI.
For some 8-bit data words alternative 9-bit transmission words exist, as shown in columns 98 and m, each 9-bit word being the
on each successive occasion that
complement of the other. In such cases, the 9-bit word will be selected alternately from columns 98 and
anysuch 8-bit word is conveyed. In the decoder, either word must be converted to the corresponding 8-bit data word.
m
CCIR International Radio Consultative Committee
1-59
Philips Semiconductors Video Products
RECOMMENDATIONS OF THE CCIR, 1990
CCIR 656
Rec.656
TABLE VI - Encoding table
Input
Output
Input
Output
8B
9B
gg
8B
9B
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
iF
20
21
22
23
24
25
26
27
28
29
2A
OFE
027
108
033
iCC
037
1CB
039
1C6
03B
1C4
030
1C2
140
OB4
14B
1A2
OB6
149
OBA
145
OCA
135
002
120
004
129
006
125
ODA
115
OEA
OB2
02B
104
020
102
035
1CA
04B
1B4
040
1B2
101
2B
2C
20
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
52
53
54
55
053
1AC
057
1A8
059
1A6
05B
050
1A4
065
19A
069
196
026
08C
02C
098
032
OBE
034
OC2
046
OC4
04C
OC8
058
OBi
14E
OB3
14C
OB9
06B
194
060
192
075
18A
08B
174
080
172
093
16C
Input
gg
109
173
103
167
1CO
141
1CB
130
1B9
13B
1B3
137
1A7
Output
8B
9B
56
57
58
59
5A
5B
5C
50
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
60
6E
6F
70
71
72
73
74
75
76
097
168
099
166
09B
164
090
162
OA3
15C
OA7
158
025
OA1
029
091
045
089
049
085
051
08A
0A4
054
0A2
052
056
1A9
05A
1A5
06A
195
096
169
OA9
156
DAB
154
OA5
15A
OAO
152
155
77
78
79
7A
7B
7C
70
7E
7F
80
CCIR International Radio Consultative Committee
Input
gg
iDA
15E
106
16E
1BA
176
1B6
17A
1AE
175
15B
1AB
150
1AO
1-60
Output
8B
9B
81
82
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9E
9F
AO
Ai
A2
A3
A4
A5
A6
A7
A8
A9
M
AB
OM
055
1M
005
12A
095
16A
OB5
14A
09A
165
OA6
159
OAC
153
OAE
151
02A
092
04A
094
OA8
OB7
OF5
OBB
OED
OBO
OEB
007
000
OOB
146
OC5
13A
OC9
136
O~B
134
OCO
132
001
12E
003
gg
105
160
1B5
16B
157
148
10A
144
112
142
114
128
122
124
Input
Output
8B
9B
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
01
02
03
04
05
06
12C
009
126
OE5
11A
OE9
116
02E
101
036
1C9
03A
1C5
04E
1B1
05C
1A3
05E
1A1
066
199
06C
193
06E
191
072
180
074
18B
07A
189
08E
185
09C
171
09E
163
OB8
161
OBC
147
OC6
143
gg
Input
Output
8B
gg
gg
07
08
09
OA
DB
DC
DO
DE
OF
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FO
FE
FF
OCC
139
OCE
133
008
131
OOC
127
OE2
123
OE4
110
OE6
11B
OE8
119
OEC
117
OF2
113
OF4
100
076
10B
OC7
13C
047
1B8
067
19C
071
198
073
18E
079
18C
087
186
OC3
178
062
190
Philips Semiconductors Video Products
CCIR 656
RECOMMENDATIONS OF THE CCIR, 1990
Rec.656
3.
Order of transmission
The least significant bit of each 9-bit word shall be transmitted first.
4.
Logic convention
The signal is conveyed in NRZ form. The voltage at the output terminal of the line driver shall increase on a transition from 0 to 1
(positive logic).
5.
Transmission medium
The bit-serial data stream can be conveyed using either a coaxial cable (§ 6) or fibre optic bearer (§ 7).
6.
6.1
Characteristics of the electrical interface
Line driver characteristics (source)
6. 1. 1
Output impedance
The line driver has an unbalanced output with a source impedance of 75 n and a return loss of at least 15 dB over a frequency
range of 10 to 243 MHz.
6. 1.2
Signal impedance
The peak-to-peak signal amplitude lies between 400 mV and 700 mV measured across a 75
connected to the output terminals without any transmission line.
6.1.3
n resistive load directly
DC offset
The DC offset with reference to the mid amplitude point of the signal lies between +1.0V and -1 .0 V.
6. 1.4
Rise and fall times
The rise and fall times, determined between the 20% and 80% amplitude pOints and measured across a 75 n resistive load
connected directly to the output terminals, shall lie between 0.75 and 1.5 ns and shall not differ by more than 0.40 ns.
6.1.5
Jitter
The timing of the rising edges of the data Signal shall be within ± 0.10 ns of the average timing of rising edges, as determined
over a period of one line.
6.2
Line receiver characteristics (destination)
6.2.1
Terminating impedance
The cable is terminated by 75
6.2.2
n with a return loss of at least 15 dB over a frequency range of 10 to 243 MHz.
Receiver sensitivity
The line receiver must sense correctly random binary data either when connected directly to a line driver operating at the
extreme voltage limits permitted by § 6.1.2, or when connected via a cable having loss of 40 dB at 243 MHz and a loss characteristic of
1/ ft.
Over the range 0 to 12 dB no equalization adjustment is required; beyond this range adjustment is permitted.
6.2.3
Interference rejection
When connected directly to a line driver operating at the lower limit specified in § 6.1.2, the line receiver must correctly sense
the binary data in the presence of a superimposed interfering signal at the following levels:
d.c.
Below 1 kHz:
1 kHz to 5 MHz:
Above 5 MHz:
±2.5 V
2.5 V peak-to-peak
100 mV peak-to-peak
40 mV peak-to-peak
CCIR International Radio Consultative Committee
1-61
Philips Semiconductors Video Products
RECOMMENDATIONS OF THE CCIR, 1990
CCIR 656
Rec.656
6.3
Cables and connectors
6.3.1
Cable
It is recommended that the cable chosen should meet any relevant national standards on electro-magnetic radiation.
Note -It should be noted that the ninth and eighteenth harmonics of the 13.5 MHz sampling frequency (nominal value) specified in
Recommendation 601 fall at the 121.5 and 243 MHz aeronautical emergency channels. Appropriate precautions must therefore be taken
in the design and operation of interfaces to ensure that no interference is caused at these frequencies. Emission levels for related
equipment are given in CISPR Recommendation: "Information technology equipment -limits of interference and measuring methods'
(Document CISPR/B (Central Office) 16). Nevertheless. No. 964 of the Radio Regulations prohibits any harmful interference on the
emergency frequencies.
6.3.2
Characteristic impedance
The cable used shall have a nominal characteristic impedance of 75 Q.
6.3.3
Connector characteristics
The connector shall have mechanical characteristics conforming to the standard BNC type (IEC Publication 169-8). and its electrical
characteristics should permit it to be used at frequencies up to 500 MHz in 75 n circuits.
7.
Characteristics
To be defined.
CCIR International Radio Consultative Committee
1-62
Philips Semiconductors Video Products
Color space, digital coding, and sampling schemes
for video signals
There are various ways to represent video
information. This note describes some
aspects of different color spaces, conversion
between them, and normalized digital coding:
RGB at video camera output
The principal signal components of color
camera or scanners, or other imaging pickup
devices are Red, Green and Blue, RGB.
These are also the principal components for
video signal reproduction (Le. picture display)
at the monitor, as the CRT phosphors are
comprised of these colors. But there is a
non-linear relation between the camera signal
pickup function (light input) and the CRT
signal display function (light output). The
transfer function is approximately
exponential; and commonly referred to as
"gamma" curve. Gamma is mainly a light
reproduction function of the CRT.
Rdisplay = Rcamera1
Gdisplay
Bdisplay
=Gcamera1
=Bcamera1
During the development of the video
transmission standards it was decided to
compensate for this gamma-curve at the
source side (camera, studio), and not to
burden the television receiver with this effort
and cost. The NTSC standard defines a
gamma of 2.2, the PAL and SECAM
standards defines a gamma of 2.8. Normally
this gamma-correction is performed directly
in the camera.
Rlransmil = Rpickup 1ty
Glransm~ =
Btransmit
Gpickup 1ty
= Bpickup 1/1
The gamma-pre-corrected RGB signals at
the camera output are stretched in the darker
range and compressed in the lighter signal
range. This has, as a side effect, a positive
effect on noise influence on the transmission
channel. The human eye is more sensitive to
noise in dark areas, where the gamma
behavior of the CRT reduces visibility.
Computer graphics generation is defined
normally in "linear" RGB color space. The
computer monitor of today has often a
smaller gamma factor than used by the
television standard definition, but there is no
standard value. Sometimes it is compensated
in the monitor itself, or by means of the
look-up tables of the graphics RAMDAC, or
not at all. The human eye is not very
sensitive against gamma mismatch.
If video (camera) RGB gets merged with
computer RGB, it is preferably be done in the
same RGB space, including the assumed
gamma. The anti-gamma compensation, as
implemented in the Philips scaling ICs ,
compensates for a gamma-pre-correction of
1 .4 only. The remaining gamma factor is
assumed to be still performed by the
computer monitor. A greater value of
gamma-correction-compensation would lose
more digital codes in the available 8-bit
num.ber range, and produce larger
quantization steps in bright areas, which is
not acceptable.
RGB can assume only positive values, and
generate a cube like color space. The RGB
components are commonly normalized to
unity (e.g. 1 Volt peak-peak as analog signal).
If any of the components is 0, it means there
is no color of this component, if it is 1, there is
full (100%) saturation of this color. All
components equal zero represents the color
'black', all components equal 1 represents
bright 'white'. The RGB cube is an additive
color space.
Matrix to YUV (YCbCr)
In order to allow a compatible migration from
black&white television to color television the
YUV color space was utilized. Y stands for
the luminance (lightness) information, and is
compatible to black&white (and gray) signal.
U and V are the so-called color difference
signals B-Y an R-Y, and carry the additional
color information (additive color space). The
YUV representation of video information is
also oriented on the human perception of
visual information, whereby RGB
representation is more based on the technical
reproduction of color information. The human
eye senses luminance and color with. different
receptors. There are less color receptors,
and they have significant less spatial
resolution. The YUV color space
representation can take advantage of that
fact, by spending less bandwidth for color
difference information than for luminance
information (see sampling schemes, later in
this note).
Luminance Y can be positive only, the color
difference signals U and V can be positive or
negative. Commonly YUV is also normalized
to unity (peak-to-peak = 1). The following
matrix equation transforms
gamma-pre-corrected and normalized RGB
into normalized YUV (see also CCIR
recommendation 601).
0.299 * R
0.587 * G
0.114 * B
U
Cb
(B
Y)
0.169 * R
0.331 * G
0.500 * B
V
Cr
(R
Y)
0.500 * R
0.419 * G
0.081 * B
Y
(NOTE: For analog signal processing often un-normalized signals are used,
which results in different number in the matrix equations, but does not
change the cross relationship between RGB and YUV.)
June 1994
1-63
Philips Semiconductors Video Products
Color space, digital coding, and sampling schemes
for video signals
U and V form a square color plane. But for
colors of natural pictures and due to some
restrictions in the video standards NTSC and
PAL, this square color plane is reduced to a
color circle plane. The vectors of natural
colors don't point into the extreme .90mers of
the square UV plane. The size of that circle is
further restricted, if luminance values are
close to minimum or maximum. There can't
be ·any color in black or white e.g .. (Artificial
VUV Signals, e.g., test signals can use those
extreme combinations). The VUV color space
is best represented by a round column, with
the dimension of luminance V as axle in its
center, and this round VUV color space
column is shaped to a point at the bottom and
at the top.
CCIR rec. 601 describes also how to
represent these VUV signals by digital codes.
It is recommended not to use the entire
available number range for nominal signal
values, but leaving some margin, room for
digital signal processing, e.g. for over and
under shoots. In an 8 bit system, luminance
y
Cr
The codes 00 hex and FF hex should not be
used for video signal coding. These two
codes are reserved for synchronization
purposes (see CCIR rec 656).
(Note regarding nomenclature: The terms
"VUV" and "YCbCr" are referring to the same
color space and cross relationship to RGB.
The expressions "B-V" and "R-V" are
normally used for non-normalized color
difference signals. It is not part of any
standard specification, but some literature is
using the term "VUV" to indicate analog
0.299
(-~;:;~;;~~0.299
Cb
V black is coded with 16 decimal (= 10
hexadecimal), 100% white is coded with 235
decimal (= EB hexadecimal). Th.e color
difference Signals Cb and Cr are coded in
offset binary, which 'offsets' the 'no color'
pOint into the middle of the number range to
code 128 (80 hex). 100% color saturation
uses the codes from 16 (10 hex) to 240 (FO
hex). 75% color saturation uses only codes
from 44 (2C hex) to 212 (D4hex) (see also
data sheet SAA7151B, Fig.13, for example).
(- ----------(2*0.886)
--;~;-)
--;~;-)
signal representation, and the term "YCbCr"
for its digital representation. Most data sheets
and documents in this book are using both
terms interchangeable .for digital Signal
representation of normalized signals.)
The CCIR recomrnendation 601 (re-printed
elsewhere in this book) gives an example of
a digital RGB to VUV conversion. It is
assuming digital sampled RGB, defined in
codes like' luminance signal V, i.e., between
16 for black and 235 for full saturation. The
given equation assumes a matrix realization
by means of 8x8bit multipliers, which is only
approximating the correct relationship. This
equation system should not be used as
reference to construct the inverse matrix from
VUV to RGB. Today's technology allows
matrix implementation by means of look-up
tables, avoiding the limiting multiplier
resolution and truncation problem.
The accurate digital RGB to digital VCreb
conversion is described by the followirg
matrix:
0.587
(- ----------(- ----------0.587
(2*0.701)
0.587
(2*0.886)
0.114
R
--;~;-) (-~;:;~;~~~-
--;~;j
G
--;~;-) (-~;:~~;;~~-
--;~;j
B
The digital RGB ranges from 16 to 235, i.e. over 219 possible values. The digital CrCb goes from 16 to 240, uses 224 possible values. This
causes a re-normalization factors.
The inverse matrix from digital VCreb to digital RGB (16 to 235) calculates to:
DJ D
1.371
- 0.698
June 1994
o
1-64
Philips Semiconductors Video Products
Color space, digital coding, and sampling schemes
for video signals
YIQ, and other YUV related color
spaces
YIO color space is similar to YUV color space
except that it has the I and 0 color axes
rotated 33 degrees with the respect to the U
and V axes of the YUV definition .. "I" means
"in phase", and "0" means "quadrature
phase". This color space was adopted by
early NTSC systems to take full advantage of
the human eye color response with respect to
color bandwidth capability.
I
Q
V * cos (33°) - U * sin(33°)
+ U * cos (33°)
v * sin(33°)
The Philips digital decoder have fully
adjustable "hue" control. The demodulation
angle can be programmed to any value, and
can achieve an 1-0 demodulation,
i.e., generating I and 0 outputs instead of U
andY.
Some other color space approaches (like
HSI, or HSV, or HSL etc.) describe the UV
plane in polar coordinates by means of a
vector, its length(S =saturation) and its
angle(H =hue). The luminance (Intensity,
Value, Lightness) corresponds to the Y of
RGB, but can also be used for YUV or
YCbCr. At each pixel a sample is taken for R,
G, and B, or Y, U, and V etc.
YUV space. This color space representations
are related to the quadrature encoding of U
and V onto a color subcarrier, in the
transmission standards NTSC and PAL.
All three components have the same spatial
resolution (bandwidth). If 8 bits per
component is used, a 24 bit system is
required.
CMYK for color printer
CMYK color space is a subtractive color
space used for color printing. CMYK stands
for Cyan, Magenta, Yellow and Black. It
describes, which color component is
removed from white, to generate a certain
wanted/printed color. In theory, only the CMY
portion is required, however,in actual printing
ink applications, black ink is added to
enhance the contrast ratio and purity of the
black portion of the image. K is defined as
min(CMY), that is, K is equal the lowest value
otC, M, orY.
4:2:2 YCbCr sampling
Figure 2 represents a more effective
sampling format, in which Y samples are
measured at each pixel position, and Cb and
Cr samples only at every second pixel
position. By that the color information has
horizontally a resolution, that is. half of that of
luminance. The human eye does not perceive
chrominance with the. same clarity as
luminance,. therefore this type of data
reduction causes very little visual loss of
content. The 4:2:2 sampling scheme reduces
the data bandwidth need by a third.
The relation of CMY to RGB is given
vectorally as :
Cb and CR samples are co-sited with every
second Y samples, but starting with the first
Y sample of each line. It 8 bits per
component is used, a 16 bit system is
, required.
4:4:4 sampling (RGS, YCbCr)
Figure 1 illustrates the sampling positions for
4:4:4 sampling, which is mainly used for
FIELDl LlNEl
FIELD2 LlNEl
FIELDl LlNE2
FIELD2 LlNE2
FIELDl LlNE3
-~ -~ -~ -~ -~ -~-~
~
~
~
~
~
~
~
-~ -~ -~ -~ -~ -~ -~
~
~
~
~
~
~
~
FIELD2 LlNE3
[j]
Y, Cb, Cr SAMPLE
Figure 1. 4:4:4 Sampling Scheme
FIELDl LlNEl
~
FIELD2 LlNEl
-~
FIELDl LlNE2
FIELD2 LlNE2
[j]
•
June 1994
~
-~
FIELDl LlNE3
(tl
FIELD2 LlNE3
-~
Y, Cb. Cr SAMPLE
-. -. -..
-.
-. -. -.
• ~ • ~ • ~
-~
-~
-~
• ~ ...,....• ~ - • (tl
•
-~
~
-~
•
-~
~
-~
Y SAMPLE ONLY
Figure 2. 4:2:2Sampling Scheme
1-65
-,-~
•
(tl
-~
Philips Semiconductors Video Products
Color space, digital coding, and sampling schemes
for video signals
4:2:0 YCbCr (spatial) sampling
4:1:1 YCbCr(orthogonal)
sampling
Figure 3 is an example of 4:1:1 sampling,
often used in consumer type video products.
The achievable color bandwidth in this case
is only one third that of luminaric::e;But in .
broadcasted video (NTSC, PAL, or SECAM),
or in tape-recorded video, there is normally
not more chroma bandwidth
supported/available.
The CbCrsamples are taken co-sited with
every fourth·luminance pixel, but starting with
the first lUminance sample of each line. An 8
bit per component system is capable of fitting
into a 12 bit wide frame'buffer'. 7 bit per
component and 6 bit per component systems
are also used in combination with 4~1:1
sampling, which reduces the needed
frame buffer capacity even more (e.g., for PIP
function on television sets).
FIELD2LiNE'
FIELD' LlNE2
FIELD2L1NE2
•
[!J - . - . - . -[!J - . - . - . ~~
• • .' ftJ • . • . • Ii]
1:!1 - "" - ... - .. -[!} --. - . - . -~
'[!:I
FIELD2 LlNE3
~
In the example in Figure, 4 a ,non-interlaced
video source is represented, as those
compression standards know only 'pictures'
and use whole frames, 'or just one field ..
[i] •
•
•
ftJ • • • Ii]
[!J - . - •. - . -.[!J - . - . - . -~
(!J •
•
•
(il •
•
•
Ii)
FIELD' LINE'
FIELD' LlNE3
This sampling scheme is. used generally for
MPEG and H-261 compression standards,
and is also called ·coded picture sampling".
Figure 4 shows the two dimensional 2:1
sub-sampling of color pixels relative to
luminance pixels. The CbCr samples are not
co-sited with a luminance sample, but
representing the color information for a
quartet of four Y pixels, ordered in a square.
The CbCr values are normally derived
(calculated) from a 4:4:4 or 4:2:2 sampling
scheme by both horizontal and v,ertical
filtering aAd interpolation. Usually the CbCr
values are transported only every second
scan line with pairs of Y samples, the other
line carries only Y samples (4:2:0). The
overall data bandwidth of 4:2:0 sampling .is
identical to 4:1:1 sampling.
Y. Cb. Cr SAMPLE
Y SAMPLE ONLY
Figure3. 4:1.:1 Sampling Scheme
LINE'
LlNE2
UNE3
UNE4
UNE5
UNES
D
•
June 1994
• •
D
• •
• •
D
• •
• • •
e'
•
• • • • •
• • • • •
D
D
• • • • •
• • • • • • •
0
D
D
• • • •
• •
D
D
.'
Cb, Cr SAMPLE
Y SAMPLE ONLY
Figure 4. 4:2:0 Sampling Scheme
1-66
Philips Semiconductors Desktop Video Products
Video signal bandwidth/resolution
BANDWIDTHS OF VARIOUS VIDEO SIGNALS
FORMAT RESOLUTION
FORMAT
TOTAL RESOLUTION
ACTIVE RESOLUTION
BANDWIDTH
BANDWIDTH
MBytes/sec
(burst)1
MBytes/sec
(continuous )2
CCIR 601 (30 Frames per Second, 4:3 Aspect Ratio)
aCIF
214 x 131
176 x 120
1.68
1.27
CIF
429 x 262
352 x 240
6.74
5.07
Full resolution
858 x 525
720 x 485
27.0
20.95
176 x 144
1.69
1.27
CCIR 601 (25 Frames per Second, 4:3 Aspect Ratio)
aCIF
216 x 156
CIF
432 x 312
352 x 288
6.74
5.07
Full resolution
864 x 625
720 x 576
27.0
20.74
Square Pixel (30 Frames per Second, 1:1 Aspect Ratio)
aCIF
195x131
160x 120
1.53
1.15
CIF
390 x 262
320 x 240
6.13
4.61
Full resolution
780 x 525
640x480
24.55
18.43
Square Pixel (25 Frames per Second, 1:1 Aspect Ratio)
aCIF
236 x 156
192x 144
1.84
1.38
CIF
472x312
384 x 288
7.36
5.53
Full resolution
944 x 625
768 x 576
29.5
22.12
NOTE:
1. Burst bandwidth assumes that the transfer of video occurs only during the active period.
2. Continuous bandwidth assumes entire frame time is used to transfer active video.
Data rates given here are for .16-bit 4:2:2 VCRCe video; if 24-bit RGB is used, the rates are 150% higher.
May 1994
1-67
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," COLOR SYSTEI~S
~NTSC
~PAL
rz:2l
TV transmission standards; colour systems
SECAM
,.~-
~~
~
. et ;i
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II)
en
(II
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Philips Semiconductors Video Products
International TV systems
and standards
Country
VHF
standard for
colour
UHF
Country
A
VHF
standard for
colour
UHF
F
Afganistan
B
Albania
B
Algeria
B
Angola
I
PAL
G,H
Finland
B
G
PAL
France
E
L
SECAM
PAL
French
Polynesia
K1
G
Argentina
N
N
PAL
Australia
B
G
PAL
Gabon
K1
Austria
B
G
PAL
Gambia
(K1)
Azores
M
German
Oem. Rep.
B
G
Bahamas
M
NTSC
German
Fed. Rep.
B
G
Bahrain
B
PAL
Ghana
B
Gibraltar
B
NTSC
Greece
B
B
Bangla-Desh
B
Barbados
N
Belgium
B
Bermuda
M
Bolivia
N
Brazil
M
Brunei
B
Bulgaria
0
H
PAL
Greenland
MIB
NTSC
Guadeloupe
K1
PAL
Guatemala
M
PAL
Guana (French)
K1
M
K
C
Canada
M
M
NTSC
NTSC/
PAL
M
NTSC
M
NTSC
Hong Kong
B
Hungary
0
K
SECAM
Iceland
B
Chad
K1
India
B
Chile
M
M
NTSC
Indonesia
B
China
0
K
PAL
Iran
B
Colombia
M
M
NTSC
Congo
0
Costa Rica
M
M
NTSC
Cuba
M
M
NTSC
Cyprus
B
G,H
PAL
Czechoslovakia
0
K
SECAM
Dahomey
K1
K1*
Denmark
B
G
Djibouti
K1
Dominican Rep.
M
Iraq
Ireland
PAL
SECAM
NTSC
M
NTSC
SECAM
EISalvador
M
M
NTSC
Equatorial
Guinea
B
Ethopia
B
G
PAL
SECAM
B
SECAM
A,I
I
Israel
B
G
PAL
Italy
B
G
PAL
Ivory Coast
K1
PAL
SECAM
Jamaica
M
Japan
M
Jordan
B
M
NTSC
PAL
K
E
G,H
PAL
J
0
B
PAL
I
PAL
M
NTSC
M
B
Ecuador
SECAM
M
M
B
Egypt
SECAM
Honduras
Centro Afr. Rep.
June 1994
PAL
G
Haiti
Canary lsI.
M
PAL
H
SECAM
NTSC
M
SECAM
PAL
NTSC
Burma
Cambodia
SECAM
PAL
1-69
Kenya
B
PAL
Korea, North
0
SECAM
Korea, South
M
Kuwait
B
M
NTSC
PAL
Philips Semiconductors Video Products
International TV systems
and standards
Country
L
Lebanon
Liberia
Libya
Luxembourg
M
Madagascar
Madeira
Malagasy
Malawi
Malaysia
Mali
Malta
Martinique
Maruitania
Maruitius
Mexico
Monaco
Mongolia
Morocco
Mozambique
VHF
standard for
UHF
colour
B
B
B
C
G,L
Country
R
Reunion
SECAM
PAL
SECAM
PAU
SECAM
Rumania
S
SabahiSarawak
St.Kitts
Samoa
Saudi Arabia
Senegal
Sierra Leone
Singapore
South Africa
Spain
Sri Lanka
Sudan
Surinam
Swaziland
Sweden
Switzerland
Syria
K1
PAL
SECAM
B
K1
B
B
G-
K1
K1'H
B
PAL
K1
B
B
M
E
M
G,L
0
B
B
PAL
SECAM
SECAM
NTSC
PAU
SECAM
T
Tahiti
Taiwan
Tanzania
(Zanzibar)
Thailand
Togo Rep.
Trinidad &
Tobago
Tunisia
Turkey
SECAM
N
Netherlands
Neth. Antilles
B
M
New Caledonia
New Zealand
K1
Nicaragua
Niger
Nigeria
Norway
M
K1
0
Oman
P
Pakistan
Panama
Paraguay
Peru
Philippines
Poland
Portugal
Puerto Rico
G
M
B
PAL
NTSC
SECAM
PAL
B
B
G
NTSC
SECAM
PAL
PAL
B
G
PAL
M
B
M
N
M
M
0
M
B
G
M
M
M
M
K
U
Uganda
United Arab
Emirates
United Kingdom
Upper Volta
Uruguay
USA
USSR
PAL
NTSC
PAL
NTSC
NTSC
SECAM
PAL
NTSC
Q
Qatar
June 1994
B
PAL
1-70
VHF
K1
0
standard for
UHF
colour
SECAM
0
B
M
M
M
B
G
PAL
NTSC
NTSC
SECAM
K1
B
B
I
B
B
B
M
B
B
B
B
I
G
M
G
G
G
PAL
PAL
PAL
PAL
PAL
NTSC
PAL
PAL
PAL
SECAM
K1
M
M
B
B
B
M
PAL
SECAM
M
B
B
NTSC
SECAM
(PAL)
B
PAL
K1
M
NTSC
PAL
B
G
A
K1
N
M
0
PAL
PAL
N
M
K
PAL
NTSC
SECAM
Philips Semiconductors Video Products
International TV systems
and standards
Country
VHF
standard for
UHF colour
* Estimated
o .There is no local broadcast station,
V
Venezuela
Vietnam (Khmer)
V
Vemen
(Arab Rep.)
Yemen
(Oem. Rep.)
Yugoslavia
Z
Zaire
Zambia·
Zimbabwe
June 1994
M
M
M
but one can listen to a broadcast
form a neighbouring country.
NTSC
NTSC
- There is no broadcast.
PAL
B
B
B
K1
B
B
H
PAL
SECAM
PAL
1-71
Philips Semiconductors Video Products
International TV systems
and standards
BASIC CHARACTERISTICS OF VIDEO AND SYNCHRONIZING SIGNALS
CCIR system designation
Charactarlstlcs
A
N
M
C
B,G
H
D,K
I
Kl
L
E
Number of lines per frame
405
525
625
625
625
625
625
625
625
625
819
Number of fields per
second
50
60
5Q
50
50
50
50
50
50
50
50
Line frequency
4-1, Hz, and
tolerances
10,125
15,625
to. 15%
15,625
to.02%
15,625
15,625
15,625
15,625
15,625
20,475
to.02%
to.02%
(to.oool%)
(to.oool%)
15,625
to.02%
(to.oool%)
to.02%
(to.oool%)
to.02%
(to.oool%)
(59.94)
15,750
15,734
(to.oool%)
(to.0003%)
Interlace ratio
211
211
211
211
211
211
211
211
211
211
211
Aspect ratio
4/3
413
413
413
413
4/3
413
413
4/3
413
413
Blanking level, IRE units
0
0
0
0
0
0
0
0
0
0
0
Peak-white level
100
100
100
100
100
100
100
100
100
100
100
Sync-pulse level
-43
-40
-40
-43
-43
-43
-43
-43
-43
-43
-43
Picture-black level to
blanking level (setup)
0
7.5
:t2.5
7.5
:t2.5
0
0
0
0
0-7
ocolor
ocolor
0-7 mono
0-5
0-7 mono
Nominal video bandwidth,
MHz
3
4.2
4.2
5
5
5
5.5
6
6
6
10
Assumed display gamma
2.8
2.2
2.2
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
Notes: (1) Systems A, C, and E are not recommended by CCIR for adoption by countries setting up a new televiSion service. (2) Values of horizontal line rate tolerances in parentheses
are for color television. (3) In the systems using an assumed display gamma of 2.8, an overall system of gamma of 1.2 is assumed. All other systems assumed an overall transfer function
of unity.
CCIR COLOR SYSTEMS CHARACTERISTICS (II)
Hem
Subcarrier frequency, MHz
'so multiple of 4-1
June 1994
MlNTSC
3.579545 ± 10
455
tsc = TtH
MlPAL
3.575611.49 ± 10
B,G.H,PAL
4.433618.75±5
I
IIPAL
14.433618.75 ± 1
1135
909
tsc = 4
tsc = 7tH
1-72
I
+
25 t H
B,D,G,H,K,Kl,LlSECAM
'OR = 4.406250 ± 2000
foe = 4.250000 ± 2000
'OR= 2824-1
'oe= 2724-1
Philips Semiconductors Desktop Video Products
Contact addresses
Requests for various standards specifications can be directed to the following:
CCIR
The International Radio Consultative Committee
International Telecommunications Union
Place Des Nations
CH-1211 Geneva
20 Switzerland
Telephone: (011) 4122 730 5800
CCITI
The International Telephone and Telegraph Consultative Committee
International Telecommunications Union
Place Des Nations
CH-1211 Geneva
20 Switzerland
Telephone: (011) 4122 730 5851
EBU
European Broadcasting Union
The Technical Center of the EBU
32, Avenue Albert Lancaster
B-1180 Brussels
Belgium
EIA
Electronic Industries Association
2001 Pennsylvania Avenue, NW
Washington, DC 20006
Telephone:
Headquarters: (202) 457 4936
(800) 854 7179
Standards:
IEEE
Institute of Electrical and Electronics Engineers
Headquarters:
Standards Office:
345 East 47th Street
IEEE Service Center
P.O. Box 1331
New York, NY 10017
Piscataway, NJ 00855
Telephone: (212) 705 7900
Telephone: (908) 981 0060
SMPTE
Society of Motion Picture and Television Engineers
595 W. Hartsdale Avenue
White Plains, NY 10607
Telephone: (914) 7611100
June 1994
1-73
Philips Semiconductors Video Products
Video glossary
AC-COUPLED - A means by which the
constant, or DC component, of a signal is
removed, usually by passing the signal
through a capacitor.
Color Difference Signals "7The
.
chrominance information of a video signal,
expressed as the combination of tWo
orthogonal axis signals, B-Y (also called U or
Cb) and R-Y (also called V or Cr). These
signals contain no luminance (Y) information.
AM - Amplitude Modulation (AM) is a
modulation process by which the amplitude of
the carrier signal is scaled in proportion to the
modulation signal (which is the signal which
carries the content). AM modulation is used
for the video portion of the transmitted TV
signal for both NTSC and PAL standards.
Composite Video - Composite video
(CVS/CVBS) signal carries video picture
information for color, brightness and
synchronizing signals for both horizontal and
vertical scans. Sometimes' referred to as
"Baseband Video".
DEFINITION OF TERMS
Anti-Top Flutter Pulse - Disables the phase
detector during equalization and framing
times.
APL - Average Picture Level. The mean or
average signal level during the active video
period. It is expressed as a percentage of the
difference between blanking and peak white
(0 and 100 IRE).
AV - Audio Video
Back Porch - That section of the video
waveform between the end of horizontal sync
and the beginning of active video. The color
burst signal is inserted during this period.
Bandwidth - The frequency range over
which an input signal of uniform amplitude
will be passed with uniform output (within a
specified limit).
Baseband Video - Same as Composite
Video (CVS or CVBS)
CTV - Color Television
CVBS or CVS - Same as composite video.
Data Slicing - The process of extracting
digital data from an incoming, non-TIL
Signal.
DC Coupled - An electrical connection
passing both the DC component as well as
the AC component of a signal.
DC Restoration - The process of setting the
,DC level of a video signal to a defined level.
DC restoration is generally applied during the
back porch region of the video signal by
means of a clamp pulse applied to the
restoration circuit at that pOint of the signal.
Demodulation - The process by which the
original signal content is recovered from the
modulated carrier. In color television,
demodulation may additionally refer to the
recovery of the color difference signals from
the modulated chroma subcarrier.
Black Burst - Black Burst (Color Black) is a
composite video signal containing sync
information, color reference (burst) and setup
information (in the case of NTSC). Black
Burst is often used as the studio reference to
facilitate synchronization of all the devices in
the system.
Equalization Pulses - The pulses existing
before and after the vertical pulse during the
vertical interval. These are half horizontal in
length and are inserted to effect the half-line
offset in vertical sync required for interlace.
Black Level - The signal level which
represents black picture intensity. For NTSC,
this level is 7.5 IRE (also called Setup) and
for PAL this level is 0 IRE.
Field - For interlaced video the total picture
is divided into two fields, one even and one
odd each containing one half of the total
vertical information. Each field takes one
sixtieth of a second (one fiftieth for PAL) to
complete. Two fields make a complete frame
,of video.
Black Level Noise - Very similar to a white
spot noise spike except it is in the opposite or
black level direction.
Blanking Level- The video level
immediately preceding or following horizontal
sync exclusive of the active video region. The
video level for blanking is defined as 0 IRE. In
the case of PAL, blanking level and black
level are the same.
Breezeway - That portion of the Back Porch
between the end of horizontal sync and the
beginning of the color burst.
June 1994
FM - Frequency modulation is the method by
which the modulation signal which contains
the information is used to vary the frequency
of the carrier. For NTSC and PAL video, FM
modulation is used to transmit the sound
portion of the program.
Frame - One frame (two fields) of video
contains the full vertical interlaced information
content of the picture. For NTSC this consists
of 525 lines and for PAL a frame is consisted
of 625 lines.
1-74
Front Porch - The section of the video
signal that lies between the end of active
video and the beginning or leading edge of
horizontal sync.
Full Field Teletext- In this mode, Teletext
information is transmitted over, virtually, all
available TV lines.
Gamma - Cathode ray tubes (CRTs) do not
have a linear relationship between brightness
and the input voltage applied. To compensate
for this non-linearity, a pre distortion or
gamma correction is applied, generally at the
camera source. A value of gamma equal to '
2.2 is typical, but can vary for different CRT
phosphors.
Genlock - Two composite video Signals can
by phase locked to each other by
synchronizing both the compOSite sync and
color burst of the two signals. This proc;ess is
called genlock.
Ghost Rows - These are the rows that are
specified by the "row address field" of the
"page header" but do not get displayed.
These are rows 24 to 31. Sometimes referred
to as "Extension Packets", these rows carry
miscellaneous control information. (Page
extension for Telesoftware, linked pages,
higher display level, etc.)
Harmonic Distortion - A distortion added to
a Signal which consists of multiples or
harmonics of that signal which were not
present in the original. System non-linearity
can contribute to this distortion.
Horizontal Blanking - The sum of the front
porch, horizontal sync and back porch
periods, i.e. the entire period from the end of
active video to the beginning of active video
on a line.
Horizontal Sync - A negative active pulse of
287mv amplitude (300mv for PAL) inserted in
the composite video signal. This pulse is
extracted by the monitor (or receiving
system) and used to horizontally synchronize
or define the left hand side of the image.
Hue - Tint or color such as red, pink, yellow,
etc.
Hum - An undesirable superimposition of
60Hz (50Hz in Europe) power energy into the
signal content.
Intercarrier Sound - The means by which
sound is separated from the modulated
television signal by the use of a sound carrier
to beat against the video carrier. This
produces a 4.5MHz signal which contains the
audio portion of the television signal.
Interlace - A method to give a higher
apparent number of lines on the television
CRT screen. One television frame is written
on the CRT with television lines of the "even
field" placed in between those of the "odd
field".
Philips Semiconductors Video Products
Video glossary
IQ Signals - Similar to the color difference
signals (R-Y), (B-Y) but using different vector
axis for encoding or decoding. Used by some
USA TV and IC manufacturers for color
decoding.
IRE - 1/140 of a volt which is the peak to
peak amplitude of a video signal from the
bottom of sync to the top of peak white. Sync
and burst amplitude is defined as 40 IRE
units, while active video is 100 IRE Max. The
unit was originally defined by the Institute of
Radio Engineers, hence the name.
Linear Distortion - Distortions which are
independent of amplitude.
Luminance - The brightness or black and
white content of a picture. No hue or
saturation components exist. Luminance is
also referred to by the letter Y and is defined
as a sum of scaled red, green and blue
primaries by the formula:
Y=.30R+.59G+.11 B.
Modulation - The process whereby a signal
containing information is used to vary some
characteristic of a carrier. In the case of AM
the carrier amplitude is varied, in the case of
FM the carrier frequency is varied and in the
case of chroma modulation, the phase of the
carrier (called subcarrier in this case) is
modulated.
NABTS - North American Broadcasting
Teletext Specifications. Note that this is not
a standard.
This document specifies both the acquisition
protocol and the display format. The display
format is NAPLPS.
NAPLPS - North American Presentation
Level Protocol Syntax. Again, this is not a
display standard. It applies to both Teletext
and Videotex services.
Non-Linear Distortion - These are
distortions which are amplitude dependent.
Differential gain and phase measurements
are used to measure these distortions.
NTSC - National Television Standards
Committee (USA).
Page Header - This is equivalent to Row O.
Carry Control information about this page.
PAL - Phase Alternate Line. A television
standard used in Europe and other countries
which alternates the relationship of the color
axes on a line by line basis so that color
modulation errors can be canceled out.
Peak White - Maximum amplitude signal
corresponding to the maximum brightness of
the video screen.
June 1994
Peritel - An audiolvideo connector standard
for European TV receivers. Serves the same
purpose as AV connector on some of the
newer American TV sets.
Quadrature AM - Refers to the process by
which two different modulation signals each
modulate carriers of the same frequency but
which are 90 degrees out of phase. The
summed signals can be added together for
transmission and can be recovered at the
receiver end if they are demodulated 90
degrees apart. This is the process used to
modulate chrominance information onto the
color subcarrier of a video signal.
Quadrature Distortion - Distortion which
results if the sidebands of a vestigial
sideband transmission are uneven or
asymmetrical. If synchronous decoding is
used instead of envelope detection, this
distortion can be minimized.
RF Video - System used on standard
Television transmissions via an antenna or
cable system. Baseband video is amplitude
modulated on an RF carrier.
RGB - Three separate signals of Red, Green
and Blue ussd to produce a color image.
R-Y, G-Y, B-Y - Red, Green or Blue signals
without the luminance (-Y).
Sandcastle Pulse - Multilevel pulse
generated by the horizontal processor and
the vertical deflection circuit. This pulse
contains gating pulse and blanking signal
information for use by the color decoder and
the video control circuits.
Saturation - A characteristic describing color
amplitude or intenSity. A color of a given hue
may consist of low or high saturation value
which relates to the vividness of the color.
SECAM - Sequential Color and Memory
system. TV color system used primarily in
France and the USSR.
Setup - A video level which, for NTSC,
defines black level and which is 7.5 IRE
above blanking. Pal does not have setup.
SRM - Service Reference Model of NAPLPS.
It is a skeleton NAPLPS, specifying a low
level type display in order to allow for easy
implementation (256h x 200v pixels).
Subcarrier - The carrier used to convey
chroma information within the composite
video signal. The R-Y and B-Y color
difference signals are modulated onto the
subcarrier by a process of quadrature AM
modulation. The frequency of the subcarrier
signal is related to the odd half-line multiples
of the horizontal frequency in such a manner
as to allow the chrominance frequency
spectrum to co-exist or interleave within the
luminance spectrum.
1-75
Synchronous Detection - A process by
which demodulation is performed by
multiplying the signal by another signal
generated by a oscillator which is locked to
the original carrier. This is the method
preferred over envelope detection.
Teletext - One way broadcast of digital
information.
Termination - Unless proper source and
termination impedance's are presented to a
transmission line, such as a co-ax cable,
undesirable reflections and ringing can occur.
Video transmission cable typically has a
characteristic impedance of 75 ohms and
should be terminated by same.
Unmodulated - Refers to the pure carrier
frequency with no AM, FM, or Phase
modulation imposed upon it. Also referred to
as CW or continuous wave.
Vectorscope - An oscilloscope specifically
designed to demodulate and display chroma
as an x-y display of the decoded color with
respect to the R-Y and B-Y (or I and Q) axis.
Hue is displayed as the angle around the
display, and saturation as the amount of
displacement from the center.
Vertical Blanking Interval (VBI) - The time
it takes the beam to fly back to the top of the
screen in order to retrace the opposite field
(odd or even). VBI is in the order of 20 TV (25
for PAL) lines. Teletext information is
transmitted over 4 of these lines (lines
14-17).
Videotex - A two-way interactive system
through which the user can communicate to a
large, organized and secure, database
through a telephone line using the TV as the
display medium.
Waveform Monitor - An oscilloscope
designed to measure the specific timings of a
video signal.
World System Teletext (WST) - World
System Teletext is based on the British
teletext standard in which a one-to-one
correspondence exists between transmitted
characters,page memory, word addresses
and the display screen character locations.
Over 98% of the world's teletext decoders are
WST compatible.
V Signal- Luminance. Determines the
brightness of each spot (pixel) on CRT
screen either color or BIW systems, but not
the color.
Philips Semiconductors Video Products
Alphanumeric index of products
Analog-to-digital converter selection guide ...•.........................................................................
Digital-to-analog converter selection guide ... ;.........................................................................
PCF8574/PCF8574A
Remote 8-bit I/O expander for 12C-bus ..........................................................
12C-bus controller .................................... '. . . .. .. . . .. . . . . . . . .. . . . . .. . . . . . .. . . . .. . .
PCF8584
SAA1101
Universal sync generator (U$G) .............................,.................................. .
Teletext video processor ............... ',.' .................................................... .
SAA5191
SAA5231
Teletext video processor ..................................................................... .
Interface for data acquisition and cOntrol (for multi-standard teletext systems) .....' .................. .
SAA5250
Line twenty-one acquisition and. display (UTOD) ................................................. .
SAA5252
Single chip economy 10 page teletextfTV microcontroller ......................................... .
SAA5296
One Chip Frontend 1 (OFC1) ..... : ........................................................... .
SAA7110
Digital video to PCI interface .................................................................. .
SAA7116
SAA7151B
Digital multistandard colour decoder with SCART interface (DMSD2-SCART) ........................ .
SAA7152
Digital video comb filter (DCF) ................................................................ .
SAA7157
Clock signal generator circuit for digital TV systems (SCGC) ...................................... .
SAA7164
Video enhancement and D/A processor (VEDA3) ................................................ .
SAA7165
Video enhancement and D/A processor (VEDA2) ............ , ................................... .
SAA7169
35 MHz triple 9-bit D/A converter for high-speed video ..... " ................ '" .................. .
SAA7183
Digital video encoder (square pixel with Macrovision) ............................................. .
SAA7186
Digital video scaler .......................................................................... .
SAA7187
Digital video encoder (DENC2-SQ) ............................................................ .
SAA7188A
Digital video encoder (DENC2-M) ............................................................. .
SAA7191B
Digital multistandard colour decoder, square pixel (DMSD-SQP) ................................... .
SAA7192A
Digital colour space converter ................................................................. .
SAA7194
Digital video decoder and scaler circuit (DESC) ................................................. .
SAA7196
Digital video decoder, scaler, and clock generator (DESCPro) ..................................... .
SAA7197
Clock signal generator circuit for Desktop Video systems (SCGC) .................................. .
SAA7199B
Digital video encoder, GENLOCK-capable ...................................................... .
SAA9042
Multi-standard Teletext IC for standard and features TV ........................................... .
SAA9051
Digital multistandard TV decoder .............................................................. .
SAA9057B
Clock signal generator circuit for Digital TV systems (CGC) ....................................... .
SAA9065
Video enhancement and D/A processor (VEDA) ................................................. .
TDA2595
Horizontal combination ....................................................................... .
TDA3566A
PAUNTSC decoder .. : ...................................................................... .
TDA4665
Baseband delay line ......................................................................... .
TDA4670
Picture signal improvement (PSI) circuit ........................................................ .
TDA4680
Video processor with automatic cut-off and white level control ..................................... .
TDA4686
Video processor, with automatic cut-off control .................................................. .
TDA4820T
Sync separation circuit for video applications .................................................... .
TDA8444/ATIT
Octuple 6-bit DAC with 12C-bus ............................................................... .
TDA8446; TDA8446T
Fast RGBNC switch for digital decoding ........................................................ .
TDA8501
PAUNTSC encoder ......................................................................... .
TDA8540
4 x 4 video switch matrix ..................................................................... .
TDA8702
8-bit video digital-to-analog converter .......................................................... .
TDA8703
8-bit high-speed analog-to-digital converter ..................................................... .
TDA8706
6-bit analog-to-digital converter with multiplexer and clamp ........................................ .
TDA8707
Triple RGB 6-bit video analog-to-digital interface ................................................. .
TDA8708A
Video analog input interface .................................................................. .
TDA8708B
Video analog input interface .' ................................................................. .
TDA8709A
Video analog input interface .................................................................. .
TDA8712; TDF8712
8-bit digital-to-analog converters .............................................................. .
TDA8714
8-bit high-speed analog-to-digital converter ..................................................... .
TDA8716
8-bit high-speed analog-to-digitalconverter ..................................................... .
TDA8718
8-bit high-speed analog-to-digital converter .................................................. : .. .
TDA8755
YUV 8-bit video low-power analog-to-digital interface ............................................ '..
TDA8758
YC 8-bit low-power analog-to-digital video interface .......................................... : ... .
1O-bit high-speed analog-to-digital converter .................................................... .
TDA8760
TDA8771
Triple 8-bit video digital-to-analog converter ..................................................... .
TDA8772; TDA8772A
Triple 8-bit video digital-to-analog converter .......................... , .......................... .
TDA9141
PAUNTSC/SECAM decoder/sync processor ................. , ....•.•............•...............
TDF8704
8-bit high-speed analog-to-digital converter ..................................................... .
June 1994
1-76
3-3
3-4
3-5
3-16
3-41
3-52
3-58
3-69
3-100
3-114
3-120
3-185
3-202
3-243
3-252
3-258
3-276
3-295
3-302
3-303
3-332
3-359
3-387
3-418
3-454
3-457
3-511
3-517
3-549
3-575
3-619
3-626
3-644
3-651
3-669
3-675
3-685
3-701
3-717
3-722
3-731
3-738
3-763
3-776
3-790
3-803
3-813
3-825
3-842
3-859
3-878
3-893
3-908
3~924
3-933
3-948
3-963
3-984
3-996
3-1010
3-1033
Desktop Video Products
Section 2
Application Notes and Materials
CONTENTS
DPC7110
Video capture card (24/16-bit) with display filter . . . . . . . . . . . . . . . . ..
DPC7116SD
Video to PCI demo board ....................................
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder .........................................
DTV7188A
Evaluation board for SAA7188A encoder .......................
DTV9051
Digital video evaluation module ................................
DTV7199 Digital Television Demonstration System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SAA7199B operational modes ..................................................
DTV7194/96
Desktop video demo board ...................................
Crystal specifications ..........................................................
TDA8708 black level and gain modulation circuit ...................................
TDA9141 analog decoder application ............................................
Digital video evaluation board ...................................................
CVBS output filter for SAA7199B encoder ........................................
SAA 1101 sync generator application .............................................
The 12C-bus and how to use it (including specification) ..............................
12C bus addresses .............................................................
12C parallel printer port adaptor ..................................................
AN425
Interfacing the PCF8584 12C-bus controller
to 80C51 family microcontrollers ...............................
What is Teletext? ..............................................................
Packet and Page Teletext data reception using the SAA5250 ........................
2-3
2-17
2-30
2-48
2-54
2-68
2-93
2-103
2-139
2-140
2-143
2-149
2-157
2-162
2-163
2-182
2-183
2-184
2-204
2-213
Philips Semiconductors Video Products
Video capture card (24/16-bit) with display filter
DPC7110
Author: Herb Kniess
The demonstration schematic shown on the
following pages is mea,nt to be a baseline
reference design showing the application of
the Philips SAA7110 Single-Chip Video
Decoder providing video overlay on the VGA
monitor and capture on a standard PC ISA
bus computer.
The board contains 4 basic elements to
provide video display on the PC VGA
monitor. The first element is the SAA7110
video decoder. It digitizes the incoming
analog baseband video signals and decodes
it into color difference information. Sync,
clock and blanking signals are also provided
to drive memory controllers such as the MCT
MVM121A on this board.
The second function, as mentioned above, is
to store the digital video data into memory.
This particular board can use memory up to
24-bit RGB format, therefore, the MCT
memory controller converts the digital YUV
color difference data from the SAA71110 to
24-bit RGB internally before storing the data
in VRAM. The memory controller's job is to
write data to memory and scan convert it up
on the read side to VGA timing frequencies
supplied by connection to the VGA feature
connector for sync and pixel clock.
The memory controller sits on the ISA bus
directly for programming of display modes
May 20,1994
and reading and writing video memory for
record and playback of live video clips.
The third portion of the system is memory.
This board uses VRAM so that the graphics
display can make use of the serial port of
VRAMs for high speed display. DRAM
solutions would require 2 or 4 times the
number of devices to meet the bandwidth
requirements for video input and VGA
display.
The fourth and final part of this system is the
DAC and VGA output. On a typical display
screen you might have graphics and live
video at the same time. Under windows, a
color key area is painted where the live video
screen should appear. The memory controller
listens to the data on the VGA feature
connector along with sync and clock to tell
the RGB DAC when to switch between digital
RGB pixels from the video memory or analog
VGA RGB from the graphics board. A short
loop back cable must be connected from the
VGA card output to the mini a-pin DIN
connector on the overlay board. This
loop-back cable allows analog RGB from the
VGA boad to be mixed with analog video in
the 24-bit DACs analog mulitplexer. Do not
force the connector into the SVIDEO
connector, as it is only a 4-pin version.
2-3
Software comes with the demo board that
auto installs under Windows 3.1 and higher.
Video for Windows 1.1 is required for capture
and play-back. You can get a copy from
Microsoft. Video for Windows must be
installed first. All you have to do is select the
drive where the floppy is and type install. It
will do the rest, you will have to answer yes
several times, that's all.
After installing the software you must align
the board for your particular VGA card and
timing on the feature connector. Under the
SETUP menu for the VMPLUS application for
the board, you can select INPUT
VIEWPROT, OUTPUT VIEWPORT, and VGA
PARAMETERS to set up the board. After you
remove any color key area overlap or noise
caused by VGA feature connector timing
errors, be sure to save your changes under
the setup menu SAVE CHANGES.
There are a number of special effects you
can experiment with, such as ZOOM,
CHANGE PICTURE SIZE, etc. Be sure to
check out the video control capability of the
SAA711 0 under VIDEO PARAMETERS. A
parallel YUV connector is provided to allow
connection to other signal processing boards.
There is also a 24-bit RGB connector
provided for connection to LCD panels. Be
careful. The RGB connector runs
non-interlaced at the VGA scan rates!
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DEVICE SPECIFICATIONS AVAILABLE AT THE DESIGN TIME.
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THE CIRCUIT
IN THIS SCHEMATICS
IS NOT REDUCED TO PRACTICE.
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MeT, Inc. RESERVE ALL RIGHTS TO MODIFY THE INFORMATION
IN THIS APPLICATION SCHEMATICS. MeT WILL NOT BE LIABLE
FOR ANY ERROR IN THIS DOCUMENT OR INFRINGEMENTS OF PATENT
~~~~iIg~~FERENT PARTIES, FROM USE OF THIS APPLICATION
MEDIA COMPUTER TECHNOLOGIES, INC.
2900 Lakeside Drive, Suite 101
Santa Clara, CaLiforni.a 95054
TEL; (408) 988-2590
FAX: (408) 988-2611
Reprinted with permission from Media Computers Technologies, Inc.
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7110 Fab Rev B BOM
Bill Of Materials
Revised:
February 1, 1994
Revision: 3.0
11:05:12
See Notes on stuffing option
Item
Quantity
36
4
7
8
9
11
2
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
31
32
33
34
35
36
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
May 20, 1994
1
1
1
2
1
1
1
1
4
3
13
5
16
7
1
4
6
1
6
1
2
1
1
1
Reference
Part
C1,C2C8,C9,C10,C43,C47,C49
C3,C4,C12,C13,C14,C15,C16,C17,
C22,C24,C26,C28,C29,C30,C32,
C33,C34,C35,C36,C37,C38,C39,
C41,C44,C45,C46,C48,C50,C51,
C52,C54,C55,C57,C59,C61,C65
C5,C6
C7,C11,C21,C31,C40,C42,C53,
C56,C58,C62,C64
C19,C18
C20
C23
C25,C27
C60
C63,C66
C67,C68,C69
C70,C71,C72
01,02,03
JPl
JP2
JP3
JP4
JP5
JP7,JP6
J1,J2,J3
J4
J5
J6
J7
L1
L2,L3,L4,L5
Q1,Q2,Q3
R1,R3,R4,R5,R6,R7,R8,R9,R10,
R11, R50, R53, R55
R2,R15,R20,R39,R40
R12,R13,R30
R14,R16,R17,R18,R19,R21,R22,
R23,R24,R25,R26,R27,R28,R29,
R31,R32
R33,R37,R38,R44,R45,R46,R48
R35
R36,R41,R42,R43
R47,R49,R51,R52,R54,R56
SW1
U1,U2,U3,U5,U6,U7
U4
U10,U8
U9
U11
U12
0.33uF
O.luF
1
U13
1
1
U14
U15
U18, U19
U17
VR1
VR2
Y1
1
1
220pF
22uF
1000pF
.001nF
47uF
10pF
100uF
O.OluF
0.47uF
47pF
1N4148
HEADER 3X2
HEADER 3
HEADER 13X2
HEADER 5X2
HEADER 20X2
JMP3
CON24
RCA JACK
MINI DIN 4
8 PIN MINI DIN
DB15 HO
10UH
F.BEAD
2N2222
47
820
4.7K
22
75
180
10
150
SW OIP-6
MT42C8255_S
74F04
74F125
MVM121A
SAA7110
EPM7064LC68
16L8
74F257
74F74
74F245
STV8438
78L05
LM7805
26.8 MHz
2-15
DPC7110
Philips Semiconductors Video Products
Video capture card (24/16-bit) with display filter
All resistors are 5% unless noted
Notes
1.
U12 7064EPLD needed for Horizontal filter only
This filter can e used only in 16bit RGB board.
2.
For 512K, 24 bit RGB board, do not stuff U1,U2,U3
Short J2 & J3 for 24 bit RGB board
3.
For 1024K, 24 bit RGB board, Short J2 & J3
4.
For 512K, 16 bit RGB board do not stuff U1,U2,U3,U7
Stuff U12 for horizontal filter OR Short J1 & J2
5.
For 1024K 16 bit RGB board do not stuff U3,U7
Stuff U12 for horizontal filter OR Short J1 & J2
6.
Do not stuff R34 ( 680K )
May 20, 1994
2-16
DPC7110
Philips Semiconductors Video ProduC's
Video to PCI demo board
DPC7116SD
Author: Herb Kniess
The schematics following on the next few
pages show the application reference design
of a complete audio and video board
operating on a personal computer equipped
with a PCllocal bus. The board will digitize,
decode, scale, and send video data to 2
different PCI memory locations. PCI bus is
the latest high speed local bus for personal
computers. Pentium, 486, and even POWER
PC systems can make use of such a system
bus for transferring large amounts of high
speed data, such as full motion video, directly
to CPU memory or graphics screen without
the need for an additional frame buffer. The
cost savings is obvious. This concept is
known as SHARED FRAME BUFFER.
The PCI bus has 100 MBytes of useable data
bandwidth. At peak, this video capture card
could produce 45 mbytes of 24-bit RGB data
if a full screen high resolution PAL video
signal was connected to one of the video
inputs. In practice 20-30 mbytes is a more
realistic number for data bandwidth
requirements of high quality full motion video.
Small pictures and slow frame rates will
reduce the data rates even further if
necessary.
The board contains a TV tuner, BTSC stereo
audio decoder for TV sound, video decoder
and picture scaler, and single chip PCI bus
interface. The SAA7116 contains all circuitry
necessary for a complete interface between
the Philips SAA7196 video decoder scaler
output bus and PCI bus. The SAA7116 is a
PCI bus master and contains an internal
1 KByte FIFO to decouple realtime video data
June 7,1994
rates and the PCI bus burst transfer modes.
The FIFO size is very generous in order to
accommodate worst-case conditions on PCI
bus data transfers.
This demo board is not just a technology
demonstration of the products mentioned
above, but satisfies the needs of the
computer industry to bring video into a PCI
equipped computer at minimum possible
cost. There is no wasted hardware or
additional cost to the customer once a PCI
equipped computer has been purchased in
order to add video. There is no secondary
frame buffer needed to convert video data
rates to graphic data rates. The SAA7116
makes use of the SHARED FRAME BUFFER
concept.
OPERATION
Analog video signals are supplied to the
board and are digitized by the TDA8708 or
TDA8709 AID converters. The digital
composite video data is passed to the
SAA7196 video decoder scaler. The decoder
function is necessary to convert the video
data into color difference YUV or RGB data
formats for the graphics frame buffer or CPU.
The SAA7196 will decode NTSC, PAL, or
SECAM video standards. The decoder also
generates pixel clOCk and sync signals to
feed the scaler portion of the SAA7196. The
scaler function will reduce the picture size
with proper filtering vertically and horizontally
to provide a picture of any size as required by
an application. The SAA7196 has an optional
2-17
YUV data port for external signal connection
as provided by connector J4 on the board.
Do not connect the composite or S-VIDEO
inputs at the same time because they share
the same input on the TDA8708 data
converter.
A Philips FI 1236F TV tuner is also provided
on the board to optionally send baseband
audio and video Signals to the signal
processing devices. Audio signal processing
is handled by the TDA9855 stereo TV
decoder. It contains a complete stereo
decoder function as well as volume, treble,
bass, pseudo-stereo, and mixing functions.
All devices, including the TV tuner, are
controlled via the 12C serial 2-wire bus
generated in the SAA7116 PCI interface.
Software drivers are supplied with the board
which run under VIDEO FOR WINDOWS
VIDCAPV1.1.
Under WINDOWS VIDCAP, you can select
direct PCI transfer to the graphics display
buffer or transfer to CPU memory. If the video
data is sent to CPU memory, the frame
update rate is limited by the ability of the CPU
to transfer data to the screen. The transfer
rate will not be .real time 30 frames/second.
Even a Pentium system cannot handle video
data rates as high as direct transfer to the
frame buffer at 24 MBytes/sec.
Drivers for VIDCAP and other applications
are available to support the WINDOWS
development environmel")t. Philips
Semiconductors will make interface
documentation and software support
available on a developer basis.
Philips Semiconductors Video Products
Video to PCI demo board
DPC7116SD
SAMPLE MACRO FILE FOR SAA7116 DEBUGGER
; filename: v16p.mac
;This file initializes the SAA7116 to send RGB15 640x480
;with CCIR 601 compatible levels to a frame buffer located at Oxa0200000
[PEG]
MEM(60)=00000000
MEM(40)=00000000
WAIT(Ol)=OOOfffff
MEM(40)=00000040
12C COMMAND/STATUS
CAPTURE CONTROL
CAPTURE CONTROL
WAIT(Ol)=OOO~ffff
MEM(00)=00000004
MEM(04)=00000004
MEM(08)=00000004
MEM(Oc)=00000004
MEM(10)=00000004
MEM(14)=00000004
MEM(8c)=00000000
MEM(90)=00000000
MEM(5c)=80404020
MEM(40)=000080cO
12C(400e)=38
12C(400f)=50
MEM(40)=00008040
WAIT(Ol)=OOOfffff
DMAIE
DMA2E
DMA3E
DMA10
DMA20
DMA30
DMA_E_END
DMA_O_END
PHASE
CAPTURE CONTROL
; CAPTURE CONTROL
;The SAA7116 is initialized at this point
MEM(00)=a0200000
MEM(04)=Oqoooooo
MEM(08) =00000000
MEM(Oc)=a0200800
MEM(10)=00000000
MEM(14)=00000000
MEM(18)=00000bOO
MEM(lc)=OOOOOOOO
MEM(20)=00000000
MEM(24)=00000bOO
MEM(28)=00000000
MEM(2c) =00000000
MEM(30)=eeeeee01
MEM(34)=eeeeeeOl
MEM(38)=00200020
MEM(3c)=00000103
MEM(40)=000000cO
MEM(44)=00000000
MEM(48)=OOOOOOOO
MEM(4c)=00000001
MEM(50)=OOOOOOOl
MEM(54)=OOOOOOOO
MEM(58)=0005007c
MEM(5c)=461e1eOf
MEM(60)=OOOOOOOO
MEM(64)=OOOOOOOO
MEM(68)=OOOOOOOO
MEM(6c)=OOOOOOOO
MEM(70)=OOOOOOOO
MEM(74)=00000000
MEM(78)=OOOOOOOO
MEM(7c)=00000000
MEM(80)=00000000
MEM(84)=00000000
MEM(88)=OOOOOOOO
MEM(8c)=a02eece4
MEM(90)=a02ef4e4
12C(4000)=50
June 7,1994
DMA1E
DMA2E
DMA3E
DMA10
DMA20
DMA30
STRD1E
STRD2E
STRD3E
STRDlO
STRD20
STRD30
MODE_E
MODE_O
FTRIG_PLA, FTRIG_PAC
AMODE, FTOGGLE, INCDEC_E, INCDEC_O
CAPTURE CONTROL - reset prst
RETRY_WAIT
INTERRUPT MASK
MASK_E
MASK_O
MLEN_E, MLEN_O
FAEMPTYFLAG, FAFULLFLAG
PHASE
12C COMMAND/STATUS
12CD
12CD1_E, 12CDO_E
12CD3_E, 12CD2_E
12CD5_E, 12CD4_E
12CD7_E, 12CD6_E
12CD1_0, 12CDO_O
12CD3_0, 12CD2_0
12CD5_0, 12CD4_0
12CD7_0, 12CD6
12CD_EN_O, 12CD_EN_E
DMA_E_END
DMA_O_END
°
2-18
Philips Semiconductors Video Products
Video to PCI demo board
DPC7116SD
12C(4001)=7f
12C(4002)=53
12C(4003)=43
12C(4004)=19
12C(4005)=OO
12C(4006)=46
12C(4007)=OO
12C(4008)=7f
12C(4009)=7f
12C(400a)=7f
12C(400b)=7f
12C(400c)=40
12C(400d)=84
12C(4010)=OO
12C(4011)=2c
12C(4012)=40
12C(4013)=40
12C(4014)=34
12C(40l5)=Oc
12C(40l6)=fb
12C(4017)=d4
12C(4018)=ec
12C(4019)=80
12C(4020)=90
12C(4021)=80
12C(4022)=80
12C(4023)=04
12C(4024)=8a
12C(4025)=fO
12C(4026)=fO
12C(4027)=Of
12C(4028)=80
12C(4029)=16
12C(402a)=OO
12C(402b)=OO
12C(402c)=OO
12C(402d)=OO
12C(402e)=OO
12C(402f)=OO
12C(4030)=8f
MEM(40)=00008ff3
CAPTURE CONTROL - enable pegasus
[]
June 7,1994
2-19
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Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
Author: Leo Warmuth.
1.0 INTRODUCTION
The devices of the SAA7187/88 family of
video encoders can be used in a variety of
applications differing regarding the signal flow
of timing information. Video timing is defined
by clock signals, synchronization signals and
blanking signals. The video encoder ICs can
generate these signals by itself (master
mode), or can accept them as input (slave
mode). The master/slave characteristic can
be chosen independently for clock and
sync-signals.
This application note describes the various
clock and synchronization signals, their
functions, and how to select and program
them. The timing relation of some of these
signals is programmable. An application
example shows a possible configuration.
2.0
CLOCK LLC AND CREF
SIGNAL
The SAA7187/88 has two clock signals: LLC
and CREF, functionally compatible with other
Philips digital video processing circuits. LLC
on pin 38 is the Line-Locked-Clock in double
pixel clock frequency. CREF on pin 39 is the
clock qualifier signal, accompanying LLC, to
indicate on which LLC edges the 16 bit wide
YUV data stream transports valid data. CREF
is continuously toggling in pixel rate
frequency, but is not meant as pixel clock.
The transitions of CREF have to maintain
certain setup and hold times relative to clock
LLC (see data sheet). The digital encoder ICs
can generate and provide (drive) the clock
signals by its own by means of the built-in
crystal oscillator, or receive the clock signals
from external. In remote genlock mode, LLC
and CREF can be fed from one of the Philips
digital decoder (DMSD), but must then be
accompanied by RTC signal (real time control
information).
2.1
Built-in clock signal
generator
SAA7187/88 has built-in an optional crystal
oscillator for LLC frequency. A crystal with
double pixel clock frequency as base
frequency, or as third harmonic frequency,
with appropriate auxiliary circuitry, can be
connected between the pins XTALi (input,
pin 41) and XTALo (output, pin 40). The
swing at the XTAL-pins is about 1vpp, and is
DC-compensated via an internal resistor
between the two pins. Alternatively an
external crystal oscillator could directly drive
intoXTALL
An internal switch, hardware controlled by
CDIR at pin 36, selects whether the IC
provides or receives clock signals LLC and
CREF (see Table 1). If CDIR is low, clock is
taken from the internal crystal oscillator and
the IC outputs LLC at pin 38.and CREF at
pin39. IfCDIR is high, LLC pin and CREF
pin are both switched to be input. The IC then
requires a double pixel clock LLCfrom
external circuitry at pin 38. Under certain
conditions, CREF input at pin 39 has
data-phase (timing) relevance, but it does not
have directly clock and data qualifying
function.
Table 1. Selection of Clock Modes
CDIR
LLC
CREF
Pin 36
Pin 38
Pin 39
low
output
output
XTALo
Pin 40
XTALi
Pin 41
local crystal
RTCE
Pin 43
subaddress
61hex
don't care
don't care
don't care
don't care
low
output
output
high
input
don't care
but constant
don't care
don't care
0
high
input
input
don't care
don't care
0
high
input from
DMSD/CGC
don't care
but constant
don't care
RTCOfrom
DMSD
1
high
input from
DMSD/CGC
input from
DMSD/CGC
don't care
RTCOfrom
DMSD
1
May 1994
don't care
external
oscillator
RTCI
2-30
2.2
External Clock
In the "clock slave mode" case, i.e., if clock is
provided from external into LLC pin 38, a
CREF-like signal can optionally be applied to
pin 39, but this is not required. If the IC sees
a toggling signal, Le., edges, at pin 39, CREF
will contribute to re-synchronization of the
internal horizontal counter (once per line) and
- by that - defines the active data phases in
the 16 bit wide YUV input data stream. If
horizontal synchronization from external via
RCV1 or RCV2 is selected, Le., the encoder
IC is in slave mode regarding horizontal
timing, CREF defines together with the
selected horizontal reference input signal,
when the horizontal trigger counter has to
start. From there the programming parameter
HTRIG (11 bits in subaddress 6E and 6F)
defines the start of the horizontal pixel
counter, and the LSB of the parameter
HTRIG determines one of the two possible
phases of the internally effective CREF
relative to the external provided CREF. The
horizontal reference edge is defined
regarding source and polarity by the various
bits in subaddress 6Chec (see also later in
this application note: re-trigger).
If no CREF is provided to the IC, a horizontal
reference signal input is sampled direct with
LLC resolution. The phase of the internal
CREF, and expected valid data phases, are
defined by the selected horizontal reference
edge, and by the LSB of HTRIG. The
horizontal reference edge is defined
regarding source and polarity by the various
bits in subaddress 6Chec (see also later in
this application note: re-trigger).
Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
LLC INPUT
CREF INPUT
111/1/1/11
A) HS_REF INPUT
AO) HTRIG·LSB = 0
INTERNAL CREF
ACTIVE CLOCK
VALID DATA EXPECTED
Al) HTRIG-LSB = 1
INTERNAL CREF
ACTIVE CLOCK
VALID DATA EXPECTED
Figure 1. Timing of internal CREF and expected valid data input, if CREF and
horizontal reference is provided from external into the encoder IC
LLC INPUT
CREF INPUT, CONSTANT LOW OR HIGH
B) HS_REF INPUT
l1li
AO) HTRIG·LSB =0
INTERNAL CREF
ACTIVE CLOCK
VALID DATA EXPECTED
Al) HTRIG-LSB =1
INTERNAL CREF
ACTIVE CLOCK
VALID DATA EXPECTED
Figure 2. Timing of internal CREF based on horizontal reference signal input only
May 1994
2-31
Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
2.3
Clock accuracy
The digital encoder SAA7187 and SAA7188A
synthesize all horizontal and vertical timing
as well as the color subcarrier oscillation from
the provided clock LLC, respectively crystal.
If the clock frequency deviates from its
nominal value, line and field frequency will
change accordingly. Consumer type receiver
equipment is rather tolerant regarding these
raster frequencies, and can normally accept
and follow several % deviations from the
standard raster frequencies.
But the subcarrier frequency has much
higher requirements regarding accuracy and
stability to ensure proper color decoding.
Broadcast quality class specification asks for
less than 2ppm deviation of sub carrier
frequency. Consumer type equipment may
accept up to 50ppm static deviation, but
dynamic deviation should be kept much
smaller and very slow.
In case the crystal or the provided LLC at the
digital encoder does not have the correct
frequency, the synthesized color subcarrier
May 1994
frequency can still be adjusted to the required
frequency value, by programming the 32 bit
of "FSC" under subaddress 63hex to 66hex
appropriate. Subcarrier phase reset PHRES
in subaddress 70hex has then to be switched
off, ie., set to 00. In general, such an
adjustment of "FSC" would produce a
non-standard video output signal regarding
subcarrierto line phase coupling, comparable
to a regular VCR signal. The resulting video
signal shows correct subcarrier frequency
and (slightly) incorrect raster frequencies. It
can be decoded and displayed correctly by
any equipment that could handle VCR
signals, e.g. by a consumer type television
set.
2.4
Remote Genlock
In remote genlock mode the digital encoder
runs with the line locked clock LLC,
generated by a digital multi standard decoder
(DMSD) respectively clock generator (CGC),
like SAA7110, SAA7196, SAA7197 or
SAA7157. In the decoding process the line
locked clock LLC is derived from an analog
2-32
video input signal as reference. If this input
video signal is not stable or non standard,
e.g., a camcorder play back Signal, the
DMSD will control LLC to stay line locked,
which may result into a non-nominal clock
frequency. The Philips digital decoder
provides an RTC-signal (real time control
information) to enable the digital encoder
(DENC) to compensate such non-nominal
clock, if decoder and encoder are running the
same system, i.e., same sampling scheme
(CCIR or SOP) and same video norm (field
frequency, subcarrier frequency). Decoder
LLC and RTCO output signal from DMSD
must be connected to LLC and RTCI input
signal of DENC. Horizontal and vertical sync
signal of both systems can run with phase
offset. The data path can have any
processing delay, or may be not closed at all.
SAA7187 can be paired for remote genlock
operation with the SAA711 0, or SAA7191 B
plus SAA7197, or with SAA7196.
SAA7188A can be paired for remote genlock
operation with SAA7151B plus SAA7157.
Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
3.0
RASTER CONTROL OUTPUT
SIGNALS
The NTSC / PAL video encoder has an
internal synchronization circuitry. For the
purpose of this application note it is referred
to as horizontal counter - counting in clocks
along a horizontal line - and as vertical
counter - counting in half lines through a
video field. A third counter for color field
sequence identification is implemented to
support the interlace characteristic of the
video signal as well as to distinguish the
NTSC four color field sequence, and PAL
eight color field sequence. The IC has four
Raster Control pins (RCxx), which reflect the
timing and status of the internal
synchronization circuitry. Two of them carry
vertical/field synchronization signals, and
two carry horizontal/line synchronization
information. One of each pair is output only,
the other one can be defined as output or as
input, to re-trigger the internal
synchronization circuitry. (The nomenclature
of these four pins is related to data flow in a
particular application, but should not be
understood as restriction.) All four signals are
defined on one and the same internal
synchronization circuitry.
3.1
3.1.1 Field Reference Signal Types
For both field reference outputs, one signal
out of a set of the following three signal types
can be selected independently.
VS
Vertical Sync signal is nominal active
(nominal high) for 3 lines if 60Hz
timing is selected, or for 2.5 lines if
50Hz timing is selected, i.e., during
those half lines, in which the analog
CVBS output contains the main
vertical sync pulses ..
FS
Frame Sync signal is an oddjeven
signal, that is active (nominal low)
during every first i.e. odd field, and
inactive (nominal high) during every
second, i.e., even field in the 2:1
interlace scheme of two fields in one
frame. The first field is that field, in
which the first main vertical sync
pulse (serration pulse) starts in
coincidence with the begin of a line.
FSEQ
Vertical - Field - Reference
Output Signals
The digital encoder SAA7187 and SAA7188A
have two pins to output field reference Raster
Control signals. RCM1 on pin 29 has output
only functionality, and a fixed (nominal) signal
polarity. RCV1 on pin 6 has selectable signal
polarity and can be used as output or as input
to re-trigger internal timing (see later in this
application note).
rising) edge of VS, and all edges of FS and
FSEQ occur at nominal field start (according
to CCIR nomenclature), and on half line
boundaries. For standard interlaced mode
and nominal field length, FS is low for 262.5
(312.5) lines and high for 262.5 (312.5) lines,
for example. The leading (nominal falling)
edge of FS or the leading (nominal rising)
edge of FSEQ indicates the begin of a frame,
the begin of a field, and also the begin of a
line, and can be used to reset/trigger external
vertical as well as horizontal synchronization
counter.
The color Field SEQuence signal
indicates the start of the color field
sequence (see CCIR report 624,
e.g.). FSEQ is active (nominal high)
during the first field of the 4-(NTSC)
or 8-(PAL) color field sequence for
standard encoding. FSEQ is inactive
(nominal low) through all the other
fields.
The position of the output signals VS, FS and
FSEQ as RCM1 at pin 29, as well as RCV1
at pin 6, has a fix timing relationship to the
internal horizontal and vertical counters and
is not directly effected by programming of
HTRIG or VTRIG. The leading (nominal
If the encoder is forced into non-interlaced
mode through external re-trigger, the FS
function is meaningless. If non-standard
encoding regarding subcarrier-to-line
coupling is applied, selection of FSEQ
function is meaningless.
Selecting any of these signal for output as
RCM1 on pin 29 or as RCV1 on pin 6 has no
direct effect on internal blanking or other
processing in the encoder IC itself. RCM1
and RCV1 as output are just auxiliary timing
signals for use by the application
environment, to support the video signal
source (e.g., MPEG decompression circuitry,
or video memory controller, or graphics
generator) to time its data stream output.
3.1.2 Pin 29: RCM1
Pin 29 RCM1 has output only function and
carries field synchronizing raster control
information. Via two SRCM bits in
sUbaddress 6Dhex one of three types of field
sync signals can be selected.
Table 2. Selection of RCM1 signal function on Pin 29
F
=relevant function, x = other function/signal definition, - =don't care
SHORT NAME
BITS UNDER
SUBADDRESS 61 h
BITS UNDER
SUBADDRESS 6Dh
FUNCTION
RESULTING SIGNAL
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
-
- - - -
FISE
0 0
0
VS50Hz
active high for 2.5 lines at begin of every field
0 0
1
VS 60Hz
active high for 3 lines at begin of every field
0
1
0
FS 50Hz
low in first (odd) field, 312.5 lines
high in second (even) field, 312.5 lines
0
1
1
FS 60Hz
low in first (odd) field, 262.5 lines
high in second (even) field, 262.5 lines
x
x
x
x
SRCM
x
select RCM 1 signal function
1 0
0
FSEQ 50Hz
high in the first field of 8 field sequence
1 0
1
FSEQ 60Hz
high in the first field of 4 field sequence
1
x
n.a.
1
May 1994
x
select field frequency (V-pulse sequence)
select number of clockslline (selects FSEQ as 4 or 8 field sequence)
F
F F x
x
reserved, do not use
2-33
Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
3.1.3 Pin 6 as Output: RCV1
Pin 6 RCV1 can assume output as well as
input function and carries field synchronizing
raster control. information. Via two SRCV1 x
bits, PRCV1 bit and ORCV1 bit in
subaddress 6Chex one of three types of field
sync signals can be determined for RCV1
output.
Table 3. Selection of RCV1 output signal function on pin 6
F
=relevant function, x =other function/signal definition, - =don't care
BITS UNDER
SUBADDRESS 6Ch
BITS UNDER
SUBADDRESS 61 h
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
-
x
x
x
x
x
x
SHORT NAME
F
FUNCTION
RESULTING SIGNAL
select field frequency (V-pulse sequence)
select number of clockslline (defines FSEQ as 40r 8 field sequence)
FISE
x
x
x
x F x x x
PRCV1
Select RCV1 signal polarity
x
x
x
F x
x x x
ORCV1
Input or Output of RCV1 signal
F F x
x x x x x
SRCV1
Select RCV1 signal function
x
0 x
-
input
RCV1 is input, see Table 6
0 0
1 0
0
VS50Hz
Active high for 2.5 lines at begin of every field
0 0
1 1
O.
VS50Hz
Active low for 2.5 lines at begin of every field
0 0
1 0
1
VS 60Hz
Active high for 3 lines. at begin of every field
0 0
1 1
1
VS60Hz
Active low for 3 lines at begin of every field
0 1
1 0
0
FS50Hz
Low in first (odd) field, 312.5 lines
High in second (even) field, 312.5 lines
0 1
1 1
0
FS50Hz
High in first (odd) field, 312.5 lines
Low in second (even) field, 312.5 lines
0 1
1 0
1
FS60Hz
Low in first (odd) field, 262.5 lines
High in second (even) field, 262.5 lines
0 1
1 1
1
FS 60Hz
High in first (odd) field, 262.5 lines
Low in second (even) field, 262.5 lines
1 0
1 0
0
FSEQ50Hz
1 0
1 1
0
FSEQ50Hz
Low in the first field of 8 field sequence
1 0
1 0
1
FSEQ 60Hz
High in the first field of 4 field sequence
x
1 0
1 1
1
FSEQ60Hz
1 1
- -
x
n.a.
May 1994
High in the first field of 8 field sequence
Low in the first field of 4 field sequence
reserved, do not use
2-34
Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
3.2
Horizontal - Line Reference Output Signals
The digital encoder SAA7187 and SAA7188A
have two pins to output line reference Raster
Control signals. RCM2 on pin 30 has output
only functionality, and a fixed (nominal) signal
polarity. RCV2 on pin 7 has selectable signal
polarity and can be used as output, or as
trigger input to re-synchronize internal timing,
or as 'blanking' input to gate input data
stream (see later in this application note).
Both horizontal raster control output signals
can be freely defined along the line, and are
active (nominal high) between "begin" and
"end" (see Table 4). Begin and end can be
chosen independently for RCM2 and RCV2.
Both pairs are relative to the same internal
horizontal counter, and are defined in LLC
clocks. The internal horizontal counter
manifests its timing in the analog output, and
can depend on re-trigger via RCV1 or RCV2
input signals and programming of HTRIG
under subaddress 6Ehex and 6Fhex (see
later in this application note).
RCM2 and RCV2 as output are auxiliary
timing signals for use by the application
environment, e.g., to help the data source
(MPEG decompression circuitry, video
memory controller or graphics overlay
generator) to time its data stream, or disable
it. The programming of RCM2 and RCV2 as
output does not effect internal blanking, data
enabling, or any timing or processing in the
encoder IC itself.
3.2.1 Pin 30: RCM2
Pin 30 RCM2 has output only function. RCM2
is active high between 'Begin = BMRQ' and
'End = EMRQ' in every line, i.e., also during
vertical blanking interval VB!. Programming of
FAL and LAL has no effect on RCM2. If End
is programmed before (Le., with a lower
number than) Begin, RCM2 may be
seen/understood as an active low signal
between End and Begin.
3.2.2 Pin 7 as Output: RCV2
Pin 7 RCV2 can assume output as well as
input function (see Tables 3, 4, and 5).
Program bit ORCV2 = 1 defines pin 7 for
RCV2 output signal. RCV2 output is active
(nominal high) from programmed 'Begin =
BRCV' to 'End = ERCV'. The polarity is
defined by program bit PRCV2.
Program bit CBLF defines whether RCV2
output is active in every line (CBLF = 0),
regardless of vertical pOSition, or whether
RCV2 output is only active during selected
vertical active range (CBLF = 1). Vertical
active range is defined between 'first active
line' FAL and 'last active line' LAL under
subaddress 7Bhex to 7Dhex. By that, RCV2
as output signal could be used as horizontal
line timing reference signal ("HREF") or as
composite blanking signal ("CBN"), to enable
data output at the video signal source. But if
pin 7 is programmed as RCV2 output signal,
its signal and related programming has no
effect for any timing, blanking, data enabling
or processing in the encoder IC itself. FAL
and LAL defines internal vertical blanking,
independently of whether CBLF is selecting it
for gating of RCV2 output or not.
Table 4. Definition of output timing of RCM2 (pin 30) and RCV2 (pin 7)
PROGRAM
WORD
11 BIT ADDRESS IN HORIZONTAL DIRECTION
RCM2 PIN30
RCV2 PIN7
LLC RESOLUTION
OUTPUT ONLY
ONLY IF OUTPUT
BRMQ
subaddress 71 hex, 73hex
L-to-H transition, riSing edge
ERMQ
subaddress 72hex, 73hex
H-to-L transition, falling edge
BRMQ
subaddress 77hex, 79hex
begin of 'active' phase
subaddress 78hex, 79hex
end of 'active' phase
ERMQ
Table 5. Selection of RCV2 output signal function on pin 7
F = relevant function, x = other function/signal definition, - = don't care
BITS IN SUBADDRESS 6Chex
SHORT NAME
FUNCTION DESCRIPTION
7 6 5 4 3 2 1 0
x
x
F
PRCV2
Polarity of RCV2
x
x
F x
ORCV2
110 of RCV2
x
F x
x x
x
x
x
x x
x
x
x x
x
x
x
RCV2 in VBI (see FAL and LAL)
RVC2 is input, see Table 7
x
0 x
input
0
1 0
"HREP'
RCV2 output is active high between BRCV till ERCV in every line of the entire field, Le.,
including VBI
0
1 1
"HREF_"
RCV2 output is active low between BRCV till ERCV in every line of the entire field, Le.,
including VBI
1
1 0
"CBN"
RCV2 output is active high between BRCV till ERCV in active lines only from FAL to LAL,
Le., excluding VBI
"CB"
RCV2 output is active low between BRCV till ERCV in active lines only from FAL to LAL,
Le., excluding VBI
1 1 1
May 1994
CBLF
2-35
Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
4.0
RASTER CONTROL INPUT
SIGNALS,
SYNC-SLAVE-MODE
The internal synchronization circuitry of the
digital encoder SAA7187 and SAA718SA are
always defined by FISE (number of clocks
per line, subaddress 61hex), FLEN (number
of lines per field, subaddress 7Ahex and
7Dhex), and PAL (defining color field
sequence length, subaddress 61 hex). In sync
slave mode, those horizontal and vertical
counters can be re-triggered by an external
trigger event at pin 6 as RCV1 input and/or at
pin 7 as RCV2 input. The rising or falling
edge can be selected as timing reference
(trigger event) to re-synchronize the internal
synchronization circuitry, regarding horizontal
or vertical counter, or odd-even flip-flop, or
color field sequence counter. As long as no
trigger event occurs the internal counters are
free running in the defined loops. Any single
occurance of the selected edge in RCV1 or
RCV2 input will hard re-trigger - I.e., it is not
May 1994
a smoothed PLL procedure. Due to
processing pipeline delay, the resulting
re-synchronization does not take effect
before the next following corresponding
period. A programmable vertical and
horizontal trigger offset can be applied via
VTRIG and HTRIG.
RCV2 as input can also optionally be used as
·composite blanking" signal to gate the input
data stream, but only for data coming through
V-port (and D-port).
VTRIG represents a negative delay between
external trigger event and internal vertical
counter start, i.e., start of main vertical sync
(serration) pulses. The external
re-synchronization event at RCV1
over-writes the vertical counter state with
VTRIG value, which then synchronizes the
next vertical period to the external trigger
signal. VTRIG is defined with 5 bits under
subaddress 70 hex. The programmed VTRIG
number corresponds with the position of the
2-36
external trigger event along the field, counted
in half lines. Programming 00 will synchronize
the internal vertical counter to generate
vertical sync at the begin of that same half
line, in which the external trigger event
occurs. Programming of 1F hex results in
vertical sync output 31 half lines ahead 6f the
external trigger input, for example.
HTRIG represents a negative delay between
external trigger event and internal horizontal
counter start, I.e., leading edge of horizontal
sync pulse. The external re-synchronization
event at RCV1 or RCV2 over-writes the
horizontal counter state with HTRIG value,
which then synchronizes the next horizontal
period to the external trigger Signal. HTRIG is
defined with 11 bits under subaddresses 6E
hex and 6F hex in LLC clock resolution, and
covers the whole line period. The
programmed HTRIG number corresponds
with its position (in LLC clOCks) along the
scan line.
Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
4.1
Pin 6 as Input: RCV1
If pin 6 is selected as input, RCV1 signal
could carry field synchronization information
in a form like vertical sync VS, or frame sync
FS, or field sequence identification FSEQ.
The actual re-trigger function of RCV1 input
is defined via the two SRCV1 bits, TRCV2
bit, ORCV1 bit and PRCV1 bit, all in
subaddress 6Chex, and the PAL bit in
subaddress 61 hex. Table 6 describes signal
meaning and effect of RCV1 as input at pin 6.
Table 6. Selection of RCV1 input signal function on pin 6
F = relevant function, x = other function/signal definition, BITS UNDER
SUBADDRESS 6Ch
BITS UNDER
SUBADDRESS 61 h
= don't care
SHORT
NAME
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
RCV1
INPUT
PIN6
FUNCTION:
Active edge results in retrigger of following counters:
HORIZONTAL
VERTICAL
ODDIEVEN
0 0 0 0 0
x
VS
rising
horizontal
vertical
(n-interl.)
0 0 0 0 1
x
VS
falling
horizontal
vertical
(n-interl.)
0 0 1 0 0
x
VS
rising
vertical
0 0 1 0 1
x
VS
falling
vertical
0 1 0 0 0
x
FS
rising
horizontal
vertical
odd field
0 1 0 0 1
x
FS
falling
horizontal
vertical
odd field
0 1 1 0 0
x
FS
rising
vertical
odd field
0 1 1 0 1
x
FS
falling
vertical
odd field
COLOR FIELD SEQ
1 0 0 0 0
0
FSEQa
rising
horizontal
vertical
odd field
1st of a fields
1 0 0 0
1
0
FSEQa
falling
horizontal
vertical
odd field
1st of 8 fields
1 0
1 0
0
0
FSEQa
rising
vertical
odd field
1st of 8 fields
1 0
1 0
1
0
FSEQa
falling
vertical
odd field
1st of 8 fields
1 0 0 0
0
1
FSEQ4
rising
horizontal
vertical
odd field
1st of a fields
horizontal
vertical
odd field
1st of 8 fields
vertical
odd field
1st of 8 fields
vertical
odd field
1st of a fields
1 0 0 0
1
1
FSEQ4
falling
1 0
0
1
FSEQ4
rising
1 1 1 0
1
1
FSEQ4
falling
x x x
x
n.a
x
n.a.
1 0
1 1
x x x
1
x
- x x x x x x
x x
x
x
x x
x
F x
F x
x
F
reserved, do not use
output
RCV1 is output, see Table 3
Select field frequency (V-pulse sequence)
select clocks per line
defines FSEQ as 4 or a field sequence
FISE
x
PRCV1
Select RCV1 signal porlarity
x
x
x
ORCV1
Input or Output of RCV1 signal
x x F x
x
x
x
x
TRCV2
RCV1 or RCV2 for horizontal trigger
F F x
x
x
x
x
SRCV1
Select RCV1 signal function
May 1994
x
2-37
Philips Semiconductors Desktop Video Products
Clock and synchronization signals ofSAA7187 andSAA7188
Application note for digital video encoder
4.2
Pin 7 as Input:
RCV2
If pin 7 is selected as Input, RCV2 signal can
carry just line synchronization information like
horizontal sync HS, or input data gating
function like HREF or CBN. The horizontal
re-trigger function and the data input gating
function can be utilized seoarately, or they
combined. The actual function of RCV2 input
is defined via the CBlF bit, ORCV2 bit,
PRCV2 bit and TRCV2 bit, all in subaddress
6Chex. Table 7 describes signal meaning and
effect of RCV1 as input at pin 6.
Table 7. Selection of RCV2 input signal function on pin 7
(">cn defines other functions/signals)
BITS IN
SUBADDRESS 6Chex
RCV21NPUT
pin 7
7 6 5 4 3 2 1 0
F
F
F
FUNCTION DESCRIPTION
SHORT NAME
PRCV2
Polarity of RCV2
ORCV2
I/O of RCV2
RCV2 in VBI (see FAl and LAl)
CBlF
F
Select horizontal trigger from RCV1/2
TRCV2
0
0 0
-
any input
but not used for re-trigger or gating
0
1 0 0
input high
enable V-port data: input for encoding
0
1 0 1
input low
disable V-port data input for encoding
input low
enable V-port data input for encoding
input high
disable V-port data input for encoding
1
0 0 0
rising edge
horizontal re-trigger, with HTRIG
1
0 0
1
falling edge
horizontal re-trigger, with HTRIG
1
1 0 0
rising edge
horizontal re-trigger, with HTRIG
input high
disable V-port data input for encoding
input low
1
x
May 1994
1 0 1
x 1 x
falling edge
enable V-port data input for encoding
horizontal re-trigger, with HTRIG
input low
disable V-port data input for encoding
input high
enable V-port data input for encoding
output
RCV2 is output, see Table 5
2-38
Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
5.0 SYNC TIMING
DEPENDENCIES
The selected "active" edge of the external
timing reference signal RCV1 or RCV2 loads
the internal horizontal counter with the
HTRIG value. At the end of the line the
counter is automatically reset, and all timing
signals are in phase with the requesting
re-trigger. This horizontal counter also
defines the begin and end pOints of the raster
control output signals.
The effect of VTRIG for vertical
synchronization timing is very similar.
RECV21NPUT
HREF LIKE
RISING EDGE SELECTED
AS TIMING REFERENCE
OR
RCV INPUT
e.g .. AS FS
INTERNAL
H·COUNTER
(SYMBOLIC)
BMRQ
EMRQ
RCM2 OUTPUT
OR
I
/
-----(I
RCV20UTPUT
(HERE WITH NEGATIVE POLARITY)
r
BRCV
ERCV
~'-
_ _ _ _ _ _ _ _ _......
r
....._ _ _ _ _ _ _ _ _ _.....
Figure 3. Horizontal ti ming for re-trigger and raster control output signal definition
May 1994
2-39
Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
6.0
APPLICATION EXAMPLE
Figure 4 points out several of those features
that can be realized in an application with
SAA7188A (or SAA7187). Two or more digital
video encoder devices can be locked to each
other. All their analog video outputs are
completely in phase: horizontally, vertically
and also the subcarrier. One of the devices
functions as timing master, the other ones
work in sync slave mode. The master device
provides on RCM1 the color field sequence
indication signal FSEO, which transports
horizontal and vertical reference as well as
subcarrier phase reference via the color field
sequence indication. The RCV1 inputs of the
other devices are set to FSEO function and
also used to trigger line timing. VTRIG and
HTRIG are both set to zero.
RCM2 output of the master device can be
freely defined in horizontal timing. By that it
can be used as input data gating Signal
(HREF-gate) at the RCV2 inputs of the other
encoder devices. This RCM2 output signal of
the master device (or of each device) could
also be fed back to its own RCV2 input for
input data gating function.
RCM1 and RCM2 outputs of the slave
devices can be used as trigger and timing
signals for the digital video signal sources.
May 1994
RCM1 can be chosen as a vertical sync, or
as an odd/even Signal. RCM2 can be defined
as an HS for trigger and counting purposes,
or it can be used as a source gating signal. It
can be placed 'early' to compensate for
pipeline delay on the data delivery side, such
as memory access, etc.
If the RCV2 pins of the slave (and/or the
master) device are not used as gating input,
they could be switched to output, and could
be used as (early) enabling signal (CBN) at
the signal source. In that case even VBI
blanking is supported. (This option is not
shown in Figure 4).
The digital encoder that works as timing
master in the configuration of Figure 4 can be
genlocked to an analog video reference
Signal via digital encoder circuitry. For this
purpose, the SAA7188A can be combined
with the SAA7151B, SAA7157 and
TOA8708/09. The SAA7187 can be
combined with the SAA7191 B, SAA7197 and
TOA8708/09 or with the SAA711 O. The digital
real-time decoder system locks itself to the
analog reference video signal and generates
line-locked clock, horizontal and vertical sync
signals, and the real-time control signal RTC.
If the encoder runs with the line-locked clock
of the decoder, it is important to also have the
2-40
RTC wire connected, in order to maintain the
correct subcarrier frequency in the encoder,
same as in the analog reference signal. To
have the same clock at both the decoder and
encoder side is very interesting in some
applications; for example, asa frame buffer
as it avoids the complications of an
asynchronous two-clock system.
The SAA7151 B or other decoder can provide
a pair of vertical and horizontal syncs as VS
and HS, or provide an odd/even signal FS
("ODD" on pin 39 of SAA7151B, for example)
to synchronize the digital encoder to the
reference video signal, and also into the
correct interlace sequence. Proper
programming of HTRIG and VTRIG can
adjust pipeline processing delay in decoder
and/or frame buffer circuitry. If FS from the
decoder is used as RCV1 input for the first
"master" encoder, it can also be utilized as a
horizontal reference signal. Then RCV2 is
free to be used as gating input, fed by the
RCM2 output, or it can be switched to output
a CBN-like signal to one of the video signal
sources.
Figure 4 shows a rather complex system,
but the various timing techniques, as
discussed above, can be applied in simpler
systems, too.
Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
SAA7151B
ANALOG VIDEO INPUT
(R EFERENCE)
REAL TIME
VSI
HSI
FS HREF
RTC LLC
!
l
~
!o.-
STABLE CLOCK
WDEO DA>A S"'EA"
! j
RTC
r.:
-LLC RCVl
HS, GATE
RCV2
"-
FRAME
BUFFER
SAA7188A
v
CVBS
ANALOG
VIDEO_OUT
VIDEO
RCMl RCM2
HREF,GATE
FSEQ
r
RTC
"
GRAPHICS
GENERATOR
v
T
~
LLC RCVl RCV2
SAA7188A
GRAPHICS
RCMl
HS OR GATE
..
F
1
-.-
---
--
---
--
LLC RCVl RCV2
RTC
CVBS
SAA7188A
OTHERS
RCM2
RCMl
RCM2
~
~
+
OTHER USES
VSOR FS
Figure 4. Possible Application with SAA7188A
May 1994
2·41
CVB S
~
Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
7.0
APPENDIX: SOME PROGRAMMING TABLES
7.1
Synchronization Signals (6C, 60, 70)
7.1.1
Subaddress 6C hex
Table 8. Program for RCV1 and RCV2 function at pin 6 and pin 7 in subaddress 6C-hex
BITS IN
SUBADDRESS 6Chex
7 6 5 4
SHORT NAME
FUNCTION DESCRIPTION
DEFAULT
AFTER RESET
3 2 1 0
PRCV2
0
RCV2 is active high, rising edge is timing reference
1
RCV2 is active low, falling edge is timing reference
SRVC2
a
CBLF& ORCV2
0 0
RCV2 is input, has no input data gating function,
but can be used for horizontal re-trigger, see TRCV2
0 1
RCV2 is output, horizontal (timing) reference signal in all lines,
begin and end freely programmable by BRCV and ERCV
1 0
RCV2 is input, and has input data gating function,
can also be used for horizontal re-trigger, see TRCV2
1 1
RCV2 is output, can be used as external composite blanking signal,
horizontal begin and end defined by BRCV and ERCV,
vertial first active line defined by FAL,
first inactive line defined by LAL (FAL - LAL, then all lines active).
00
PRCV1
0
RCV1 is active high, rising edge is timing reference
1
0
RCV1 is active low, falling edge is timing reference
ORCV1
0
RCV1 is input
1
RCV1 is input
a
TRCV2
0
Horizontal re-trigger by RCV1 , RCV1 must be input
1
Horizontal re-trigger by RCV2, RCV2 must be input
a
SRCV1
0 0
VS (vertical sync), every field
0 1
FS (frame sync), oddJeven
1 0
FSEQ color field sequence indication
1 1
0 0 0 0 0 0 0 0
May 1994
00
n.a.; don't use this combination
00 hex
default after reset
IC is prepared to accept an Odd/_even Signal at RCV1
(rising edge at begin of first field)
2-42
0000 0000
Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
7.1.2
Subaddress 60 hex
Table 9. Program for RCM1 at pin 29 and "Line 21" encoding in subaddress 60-hex
BITS IN
SUBADDRESS 6Dhex
7 6
5 4
3 2
SHORT NAME
CCEN
"Line 21" encoding, Closed Caption and Extented Data service
0 0
no "line 21" encoding in either field
0
"Line 21" encoding in first (odd) field only (extented data),
data content as programmed in subaddress 69hex and 6Ahex
1
1 0
"Line 21" encoding in second (even) field only (Closed Caption),
data content as programmed in .subaddress 67hex and 68hex
1 1
"Line 21" encoding in both fields
SRCM
select type of field reference output signal on pin 29 RCM1
0 0
VS (vertical sync), active high during serration pulses (3 or 2.5 lines)
0 1
FS (frame sync), active low during odd field, high during even field
1 0
FSEQ color (field sequence indication signal), active high during
first field of four fields, if FISE = 1 (60 Hz, 525 lines)
first field of eight fields, if FISE = 0 (50 Hz, 625 lines)
1 1
n.a.; do not use this combination
0 0 0 0
7.1.3
FUNCTION DESCRIPTION
1 0
reserved
Subaddress 70 hex
Table 10. Program for VTRIG and VBI (vertical blanking interval) in subaddress 70-hex
BITS IN
SUBADDRESS 70hex
7 6 54
x
SHORT NAME
FUNCTION DESCRIPTION
VTRIG
vertical trigger phase off~et
3 2' 1 0
x x
x
x
half line number, in which vertical/field trigger input occurs
SBLBN
Vertical Blanking Interval (VBI)
0
blanking is enforced in all lines outside FAL-to-LAL,
(First Active Line to Last Active Line, see subaddress 7B, 7C, and 7D)
1
blanking is only enforced only during equalization and serration (vertical sync) pulses,
i.e., 9 (60Hz) or 7.5 (50Hz) lines, signal insertion alo encoding also outside
FAL-to-LAL, allowing data, time code or test signal insertion in regular VBI
PHRES
color subcarrier reset mode, to support SC-H coupling
0 0
continuously running color subcarrier oscillation, e.g., for remote genlock RTC mode
0 1
color subcarrier phase reset every second line
1 0
color subcarrier phase reset every eighth field (PAL)
1 1
color subcarrier phase reset every fourth field (NTSC)
May 1994
2-43
Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
7.2
Video Standard Parameters (61, 70, 60)
7.2.1
Subaddress 60 hex
Table 11. Basic video standard parameters in subaddress 61-hex
BITS IN
SUBADDRESS 61-hex
7 6
SHORT NAME
FUNCTION DESCRIPTION
FISE
field frequency mode select
0
50 Hz, 312.5 lines per field, 5 V-sync serration pulses etc,
(start pre-equalization pulses 310 lines after field start)
864 (CCIR) pixels per line, i.e., 1778 LLC, 13.5 MHz
944 (SOP) pixels per line, Le., 1888 LLC, 14.75 MHz
FSEO generates 4 field sequence
1
60 Hz, 262.5 lines per field, 6 V-sync serration pulses etc,
(start pre-equalization pulses 259.5 lines after field start)
858 (CCIR) pixels per line, Le., 1716 LLC, 13.5 MHz
780 (SOP) pixels per line, Le., 1560 LLC, 12.27 MHz
FSEO generates 8 field sequence
PAL
no color subcarrier phase toggle switch, for NTSC encoding
1
PAL-switch, Le., subcarrier phase switch (±45° toggle) for V-color
component in alternative lines, for PAL encoding
extended chrominance bandwidth, e.g., option for S-video output
1
standard chrominance bandwidth
no Real Time Control applied, standard subcarrier generation, relies on
clock LLC stability
1
Real Time Control of subcarrier frequency generation,
RTC connection from appropriate Philips decoder needed
luminance (black to white) is adjusted to 100 IRE
1
luminance (black to white) is adjusted to 92.5 IRE,
giving room for 7.5 IRE setup, e.g., for NTSC
nominal (standard) phase of PAL-switch
1
opposite to standard, e.g., to adjust pipeline delay in RTC mode
DOWN
1
PAL switch phase
0
0
0
luminance gain select
0
INPI
1
Real Time Control enable
0
YGS
0
chrominance bandwidth
0
RTCE
1
switch of subcarrier phase for V-component in altemative lines
0
SCBW
0
analog output (DACs)
DACs in normal operation, analog output of encoded video signal
1
0
DACs are switched to lowest output voltage
0
0 0
DEFAULT
AFTER RESET
5 4 3 2 1 0
0
May 1994
1 0 1 0
1
15 hex
reserved
0
default after reset
0001 0101
2-44
Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
7.2.2
Subaddress 70 hex
Table 12. Program for subcarrier phase reset (Se-H) in subaddress 70-hex
BITS IN
SUBADDRESS 70hex
7 6
SHORT NAME
FUNCTION DESCRIPTION
VTRIG
vertical trigger phase offset
SBLBN
Vertical Blanking Interval (VBI)
5 4 3 2 1 0
x x x x x
half line number, in which vertical/field trigger input occurs
0
blanking is enforced in all lines outside FAL-to-LAL,
(First Active Line to Last Active Line, see subaddress 7B, 7C, and 7D)
1
blanking is only enforced only during equalization and serration (vertical sync) pulses,
i.e., 9 (60Hz) or 7.5 (50Hz) lines, signal insertion alo encoding also outside FAL-to-LAL,
e.g., data, time code or test signal insertion in regular VBI
PHRES
0 0
color subcarrier reset mode, to support SC-H coupling
continuously running color subcarrier oscillation, e.g., for remote genlock RTC mode
0 1
color subcarrier phase reset every second line
1 0
color subcarrier phase reset every eighth field (PAL)
1 1
color subcarrier phase reset every fourth field (NTSC)
7.2.3
Subaddress 60 hex
Table 13. Program for cross color reduction in analog eveS-out under subaddress 50-hex
BITS IN
SUBADDRESS 60hex
7 6 5 4
3 2 1 0
0 0
0 0 0 0
SHORT NAME
FUNCTION DESCRIPTION
reserved
CCRS
Cross Color Reduction, reducing cross talk from luminance into chrominance as support for
the testination receiver I decoder filter are active only from FAL-to-LAL, i.e., active video
0 0
standard CVBS, straight addition of luminance and chrominance signals
0 1
notch filter at 4.5 Mhz in luminance signal before adding chrominance,
e.g., for PAL color subcarrier or NTSC sound carrier
1 0
notch filter at 3.3 Mhz in luminance signal before adding chrominance, wide and deep,
e.g., for NTSC color subcarrier
1 1
notch filter at 3.3 Mhz in luminance signal before adding chrominance, more narrow than
other one, e.g., for NTSC color subcarrier
May 1994
2-45
Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
7.3
Input Data Format and Signal Flow (3A, 68)
7.3.1
Subaddress 3A hex, SAA7188A only
Table 14. Program for input data de-formating in subaddress 3A-hex
BITS IN
SUBADDRESS 3A-hex
7 6
BIT NAME
5 4 3 2 1 0
MUV2C
(M-port chroma two's complement)
Cb-Cr data at M-port is expected in two's complement
0
Cb-Cr data at M-port is expected in offset binary (acc. to CCIR 656)
1
MY2C
Y data at M-port is expected in straight binary (acc. to CCIR 656)
1
VUV2C
VY2C
(V-port luminance two's complement)
0
Y data at V-port is expected in two's complement around medium gray
1
Y data at V-port is expected in straight binary (CCIR- and DTV-mode)
V656
16 bit YUV interface formed by V-port = Y & D-port = UV
1
8-bit wide CCIR656 compatible data format at V-port
00
internal color bar test signal switch
0
normal encoding of input data
1
color bar test signal via encoding of LUT values
0 1 0 0
1
1
13 hex
default after reset
Table 15. Program for input data selection in subaddress 68-hex
BITS IN
SUBADDRESS 6B-hex
3 2
SEL_ED
Pin 18
BIT NAME
FUNCTION DESCRIPTION
1 0
MODIN
defines data from which port gets encoded
0 0
-
data from M-port gets encoded
0 1
1
data from M-port gets encoded
0 1
0
data from V(/D)-port gets encoded
1 0
-
data from V(/D)-port gets encoded
1 1
1
data from V (lD )-port gets encoded
1 1
0
May 1994
x
x
x
x
0
0001 0011
Subaddress 6B hex, SAA7188A only
0 x
1
..
reserved
0
5 4
0
data format at V-port and D-port
0
CBENB
7 6
0
Cb-Cr data at V/D-port is expected in offset binary (CCIR-mode)
1
7.3.2
1
(V/D-port chroma two's complement)
Cb-Cr data at V/D-port is expected in two's complement
(compare DTV-mode of SM7151B)
0
0 0
1
(M-port luminance two's complement)
Y data at M-port is expected in two's complement around medium gray
0
0
DEFAULT
AFTER
RESET
FUNCTION DESCRIPTION
data from M-port gets encoded
other function: line number for closed caption encoding
2-46
Philips Semiconductors Desktop Video Products
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
7.4
Input Data Formats (subaddress 3A), SAA7187 only
7.4.1
Subaddress 3A hex, SAA7187 only
Table 16. Program for input data de-formating in subaddress 3A-hex
BITS IN
SUBADDRESS 3A-hex
7 6
5 4
3 2
BIT NAME
1 0
FMT
0 0
0
Input Data Formats
YUV 4:4:4 on 24 pins, Y on VP1, V=Cr on VP2, U=Cb on VP3
1
YUV 4:2:2 on 8 pins, on VP1, multipexed according to CCIR-656
1 1
reserved
VUVC
chroma two's complement
a
Cb-Cr input data is expected in two's complement
0
1
Cb-Cr input data is expected in offset binary (CCIR-mode)
VY2C
luminance two's complement
0
Y data at V-port is expected in two's complement around medium gray
1
Y data at V-port is expected in straight binary (CCIR- and DTV-mode)
a
reserved
0 0 0
CBENB
000
internal color bar test signal switch ..
0
normal encoding of input data
1
color bar test signal via encoding of LUT values
May 1994
00
YUV 4:2:2 on 16 pins, Y on VP1, U=Cb and V=Cr multipexed on VP3
1 0
0 0 0 0
DEFAULT
Al!'TER
RESET
FUNCTION DESCRIPTION
0 0 0
0
00 hex
default after reset
2-47
a
0000 0000
Philips Semiconductors Video Products
Evaluation board for SAA7188A encoder
DTV7188A
Author: George Ellis
OVERVIEW
The Philips SAA7188A digital video encoder
has been developed to address the
consumer and set-top converter market. This
device offers an excellent ratio of
performance to cost. It has a highly
programmable feature set designed for
flexible interfacing in a variety of
environments. The following application
board information is provided to aid
customers in the development of their
products.
decoded from the video data stream and
used to drive the encoder in slave mode.
• The encoder can receive clock information
from a server (such as an MPEG decoder)
and provide handshake information (HREF
and VERT) to download data from the
server.
• The SAA7188A can be run in Master mode
providing clock and sync timing to other
slave devices.
Input Section
BOARD FEATURES
The evaluation board consists of three major
sections:
• An input section consisting of:
- A dual converter which will digitize both
S-Video and composite video (replacing
the TDA8708A and TDA87Q9A parts).
This device is the TDA8758.
- The SAA7152 digital adaptive comb
filter.
- The SAA7151B, CCIR601-based,
multi standard digital video decoder.
- The SAA7197 clock generator.
• An interface section consisting of:
- ECL to TTL translators for converting
CCIR656 (01) data to TTL levels.
- A PLD device to extractthe sync timing
information from the 01 video data.
• The encoding section, conSisting of:
- SAA7188A digital video encoder.
- A n S87C055 microcontroller for
programming the system and providing
on-screen display.
- A PCF8598 EEPROM to allow the user
to save custom settings.
Ancillary TTL, voltage regulation and filtering
components are provided to complete the
functionality of the evaluation board.
The system can be configured for a variety of
operational modes.
• Composite or S-Video can be digitized and
decoded and this data, clocks and sync
information used to operate the encoder in
RTC remote genlock mode. This is called
DTVmode.
• 01 (CCIR656) video data can be input from
a digital generator. The sync timing is
June 1994
Either composite or S-Video can be selected
to be digitized by the TDA8758. The input
selection of the AID converter is controlled by
programming the SEL pins with the general
purpose switches on the decoder (GPSW1
and GPSW2).
The digitized video is then routed to the
SAA7152 comb filter, which, in the case of
composite video, separates the data into
luminance and chrominance data. In the case
of S-Video, the comb filter is bypassed in
software. The comb filter can be removed
entirely and bypassed at JP5 with jumpers.
The SAA7151 B, in conjunction with the
SAA7197 (or SAA7157), decodes the chroma
into baseband U and V, performs luminance
processing and generates the clock and sync
signals.
01 Interface Section
The Encoder Section
The SAA7188A has three 8 bit data ports.
For this application, the MP port, which is·a
multiplexed YCbCr port, is used to receive
the 01 data stream. the VP port is used to
receive the Y portion of the SAA7151 B data
stream and the CP port receives the UV
(CbCr) portion. Selection between the two
inputs is done using the SEL_ED pin,
controlled via a port from the microcontroller
(P2.0). The VP/CP port is set to 16 bit mode
by 12C programming.
In the 01 mode, clock (ENC_LLC), Data (on
the MP port), HREF (ENC_HREF), field 10
(ENC_FI) are all that is needed to drive the
SAA7188A.
In the DTV mode, the 16 bit VUV data stream
is used, along with ENC_LLC, ENC_CREF,
ENC_HREF, ENC_FI and ENC_RTC. All
derived via JP1.
NOTE: In both modes, the CDIR is set to
select the clocks as INPUTS. CDIR is
controlled by port P2.1 of the microcontroller.
Other interfacing modes are available, CDIR
can be set to select that the SAA7188A
function as a clock MASTER. The signals
RCV1 and RCV2 can be set to be either
INPUTS for external H and V
synchronization, or they can be configured as
OUTPUTS. As inputs, the reset point can be
offset with programming. As outputs, the
position can be programmed with respect to
the internal H and V origins.
As an alternative to digital video from the
SAA7151 B input section (DTV mode), the
board will accept CCI R656 (01) input. Being
that 01 is an ECL data format, ECL to TTL
conversion will be necessary (a negative
9 volt supply is also required).
This allows for a wide variety of handshaking
with various data servers, such as MPEG
decoders, graphic systems, FIFOs, etc.
Selection between the two video inputs is as
follows:
Anti-aliasing filters are suggested on the
output, however, because the SAA7188A is
twice over-sampled, these filters can be
simple. The filters shown here are
inexpensive and provide some sin(x)/x
compensation.
For video from the SAA7151B (DTV
mode), jumpers are installed onto JP1
(except across pins 55-56 and 57-58.
Jumper JP3 is not connected.
To select 01 video, remove JP1 jumpers
from pins 39 to 60 and install a shunt to
JP3.
Devices U2, U3, and U4 translate the ECL
data and clock into TTl. U1 then decodes the
TTL data to extract HREF, Vert. Sync. and
Field 10 to synchronize the encoder.
2-48
Use the jumpers selections at JP1 and JP3 to
avoid configuration conflicts.
External 12C control is available by interfacing
to JP2.
The PLD source for the EOV-SOV decoder,
U1 is provided; it is done under the SNAP
programming format.
A sample programming example is also
provided in Section 3, following the data
sheet.
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Evaluation board for SAA7188A encoder
" D1 EOV-SOV-decoder for synchronization signals
@PINLIST
INPUT [ 7 .. 0 ] I
CLK
I
HREF
0;
VBLK
0;
FID
0;
@GROUPS
@TRUTHTABLE
@LOGIC EQUATIONS
CODE[3 .. 1] . CLK
CLK ;
CODE1.D
INPUT[7 .. 0]
FFH
CODE2.D
= INPUT [7 .. 0 ]
OOH
CODE3.D
= INPUT[7 .. 0]
OOH
LOOK
CODE1 * CODE2 * CODE3
LOOK * INPUT6 +
/LOOK * FID
CLK;
FID.D
FID.CLK
INPUTS * LOOK +
/LOOK * VBLK
CLK;
VBLK.D
VBLK.CLK
HREF.D
INPUT4 * LOOK
* HREF
CLK
+ /LOOK
HREF.CLK
=
@INPUT VECTORS
@OUTPUT VECTORS
@STATE VECTORS
@TRANSITIONS
June 1994
2-53
DTV7188A
Application Note
Philips Semiconductors Video Products
DTV9051
Digital video evaluation module
7-bit digital video evaluation module featuring the SAA9051 and TDA4680 integrated circuits
THEORY OF OPERATION
The Digital Video EvaluatiQn BQard was
designed tQ prQvide a cQmpact,
self-cQntained demQnstratiQn system fQr the
Philips SAA9051 Digital Multistandard CQIQr
TelevisiQn DecQder. The bQard accepts
cQmpQsite videQ (CVBS) signals .or S-VHS
(Y, C) signals and digitally decQdes these
input signals intQ luminance and cQIQr
difference cQmpQnents. The digital .outputs .of
the decQder are stQred in a 6 Megabit frame
memQry and made available fQr .output fQrmat
cQnversiQn tQ analQg red, green, and blue
(RGB). An 87C751 micrQcQntrQller is required
tQ send initializatiQn infQrmatiQn tQ variQus
devices .on the bQard.
In .order tQ decQde analQg cQmpQsite signals
tQ cQmpQnent fQrm, the TDA8708 8-bit NO
CQnverter digitizes the input signal and sends
the data tQ the SAA9051 Digital Multistandard
DecQder. The digital decQder generates a
6.75MHz clQck locked tQ the hQrizQntal sync
.of the input CVBS signal. This 6.75MHz clock
is sent tQ the SAA9057 clock generatQr fQr
frequency multiplicatiQn tQ 13.5MHz and
27MHz. The 13.5MHz clQck frQm the
SAA9057 is sent back tQ the SAA9051 and
TDA8708 and used as the system clock fQr
digitizing and .output timing .of the SAA9051.
The FIFO memQries and the SAA9060 triple
8-bit D/A converter alsQ use the 13.5MHz
clQck.
The digital data .output frQm the SAA9051 is
sent tQ the frame memory in a 12-bit data
bus. The bus prQvides 8 bits fQrm luminance
and 4 bits for multiplexed chrQma in a Y:U:V
4: 1: 1 ratiQ. Each field memQry consists .of 3
TMS4C1050 256K x 4 first-in-first-Qut (FIFO)
memQries. The field memQries are always
alternately read fQr .output data but the
writing, .or input, tQ the memQries can be
stQPped .on an .odd field bQundary by pulling
the still line tQ a IQgical LOW. A freeze frame
.of the input video signal is realized when a
IQgical LOW is maintained .on the still line.
After the data is read .out .of the frame
memQries, it is sent tQ the triple D/A
cQnverter, the SAA9060, fQr cQnversiQn tQ
analQg Y, R-Y, B-Y cQmpQnent signals. The
gain .of the SAA9060 is cQntrQlled via 12C
serial cQntrol .of a D/A cQnnected tQ bias at
Pin 8. The pull-up resistors .on Pins 9, 10, and
11 are required tQ match the analQg .outputs
.of the SAA9060 tQ the input levels .of the
TDA4680 .output RGB prQceSSQr.
Finally, the TDA4680 RGB prQcessQr
cQnverts the cQIQr difference cQmpQnent
signals back tQ RGB. The TDA4680 has the
capability to cQntrQI the black level, cQntrast,
saturatiQn, and individual gain .of each RGB
.output. 75 .ohm buffers are added tQ prQvide
IQW impedance .outputs fQr RGB and sync
May 10, 1991
signals. Three 12C-cQntrQlled D/As are
CQnnected tQ Pins 21, 23, and 25 .of the
TDA4680 tQ allQw the black level .of the RGB
.outputs tQ be individually adjusted.
The SAA9051 dQes mQre than just decQde
cQmpQsite videQ input signals intQ their cQIQr
difference cQmpQnents. The DMSD alsQ
prQvides twQ prQgrammable timing signals fQr
sync and clamping in the TDA8708 NO. It
alsQ prQvides blanking, hQrizQntal sync, and
vertical sync fQr interface tQ memQry and
output circuits. The SAA9051 maintains a
clQse relationship between the 13.5MHz
clQck and the input hQrizQntal sync. The
phase jitter .of the master clQck is kept in the
5 ns range. All .output signals from the
SAA9051 are synchrQnQus tQ the 13.5MHz
clQck, and have prQper set-up and hQld times
fQr easy interface tQ variQus types .of memQry.
If S-VHS capability is required, the TDA8709
ND can be used tQ digitize the chrQma
PQrtiQn .of the input signal. The luminance
signal must still be applied tQ the TDA8708
fQr digitizing and sync processing. The
TDA8708 cQntains a three channel input
multiplexer, AGC circuit, and black level
clamp.
AnQther feature .of this demQnstratiQn bQard
is the absence .of any chrQminance or
luminance delay lines. NQ mechanical
adjustments are required. All parameters fQr
cQIQr decQding and level setting can be made
by micrQprQcessQr CQntrQI. The SAA9051 can
decQde seven variatiQns .of PAL and NTSC
fQrmats and maintain vertical, hQrizQntal, and
cQlor lock even in VCR shuttle .or scan mode.
The 26-pin CQnnectQr prQvides all digital and
timing infQrmatiQn .on the .output side .of
memQry.
With minQr mQdificatiQn, this evaluatiQn bQard
can be upgraded tQ accept the SAA7151
Digital Multistandard DecQder.
DESIGN CONSIDERATIONS
A Single 10 tQ 12-vQlt PQwer supply was
chQsen tQ prQvide the simplest PQwer supply
cQnnectiQn. MQst .of the bQard uses 5 VQlt
PQwer. Therefore, the 5 VQlt PQwer regulatQr
diSSipates abQut as much PQweras the rest
.of the bQard. the TDA4680 and TDA8444 are
cQnnected tQ the 8 VQlt PQwer regulatQr.
AnalQg +5V and digital +5V are iSQlated with
1OO~H inductQrs and bypassed at each
active cQmpQnent. Special attentiQn is paid tQ
the data CQnverter analQg supply and clock
generatQr circuit. The SAA9057 clQck
generatQr alsQ has a bulk 220~F capacitQr .on
analQg supply tQ remQve any IQW frequency
ripple. A separate 5-VQlt regulatQr fQr this IC
and the analQg supply fQr the digital decQder
2-54
will keep clQck jitter well belQw 10 nS relative
tQ input sync.
Since the sample clock frequency .of this
system is 13.SMHz, it is impQrtant tQ take
care in grQunding in order tQ keep clock nQise
away from analQg videQ inputs. A commQn
grQund plane is suggested fQr the data
cQnverters, SAA9051, and SAA9057. Other
grQund planes can be used fQr the .output
sectiQn and fQr any IQgic .or memQry
reqUirement, but careful design shQuld allQw
fQr .one CQmmQn grQund cQnnectiQn PQint fQr
all grQund planes.
AnQther SQurce .of nQise is clQck feedthrQugh
intQ the data CQnverters. A resistQr is
nQrmally placed in series with the clQck line tQ
slQW dQwn the fast rise and fall times. Stray
capacitance of the wiring and input pins .of
the data CQnverters will aid in reducing the
high frequency energy cQupled intQ analQg
circuits.
On the .output side, nQise can be easily
cQupled frQm digital data lines feeding the
SAA9060 01A CQnverter tQ the analQg .output
pins .of this device. Careful trace layQut is
required in .order tQ minimize clQck .or data
interference.
12C COMMUNICATIONS
A Philips SemicQnductors 87C751
micrQprQcessQr is supplied tQ send PQwer-up
infQrmatiQn tQ the SAA9051, TDA8444, and
TDA4680. NQrmally, rQughly .one secQnd after
PQwer is supplied tQ the bQard, 20 data bytes
are sent tQ variQus slave devices. This
message will nQt SUPPQrt multi-master 12C
protQcQI. TherefQre, any cQnnectiQn tQ the
12C bus cQnnectiQn jack if fQrbidden unless it
is in the high inactive state fQr clQck and data.
If an external cQmputer .of CPU is used fQr
12C cQntrQl, data transmissiQn can safely
begin three secQnds after bQard PQwer-up.
By this time the 87C751 CPU has cQmpleted
sending the power-up instructiQn sequence,
and has entered a halt-inactive state.
ImplementatiQn .of autQmatic brQadcast
standard detectiQn WQuid require QngQing 12C
cQmmunicatiQn between the SAA9051 and
the Qn-bQard CPU. This can be seen as
activity .on the clQck and data lines .of the 12C
cQnnectQr, making external cQntrQI .or testing
.of the bQard impQssible. In this case, the
87C751 shQuld be remQved frQm the bQard tQ
allQw external 12C cQntrQI .of the digital
decQder and analQg functiQns.
Philips has made available 12C cQntrQI
sQftware fQr hardware develQpment and
debug .of 12C products. This sQftware runs
under MS-DOS, and uses a parallel printer
PQrt as an 1/0 CQnnectQr. This sQftware has
user-friendly menus fQr variQus 12C devices
as well as a universal message generatQr
menu fQr cQntrQI .of any 12C device.
Application Note
Philips Semiconductors Video Products
DTV9051
Digital video evaluation module
OUTPUT VIDEO BUFFERS
Most analog RGB monitor connections
require 75 ohm source terminated, 1 volt
peak-to-peak video signals. The RGB output
connectors meet this requirement, but the
analog output levels can be adjusted in the
TDA4680 to about 6dB from the nominal 1
volt peak-to-peak standard. Sync is not
supplied on the RGB lines.
Looking at the supplied schematic, you
should note the 10 ohm resistors in the
collector leads of the output transistors.
These resistors are required to keep high
frequency video signals off of the 5V power
supply lines and reduce power dissipation in
the output transistors. These output buffers
are not power-efficient, but do provide a
simple 75 ohm output stage and DC output
level at ground during blanking time.
GENERATION OF THE SANDCASTLE SIGNAL
A very simple resistor and diode circuit is
used to generate the sandcastle signal
required by the TDA 4680 for proper
operation. Unfortunately, the SAA9060 has a
22 clock pipeline delay from data input to
analog output. The same BLN signal from the
SAA9051 is used for the SAA9060 and
sandcastle, so there will be a slight loss of
picture information on the right side of the
screen in this implementation. Because
monitors are typically overscanned, this
shouldn't cause a visible effect. A delay of the
BLN signal would be required to eliminate
this loss of picture information.
MEMORY INTERFACE AND FIELD
ID GENERATION
This demonstration board contains 2 fields of
memory organized as 256K x 12 bits each.
Normal video signals are interlaced with even
and odd fields. A D flip-flop can be clocked by
vertical sync from the DMSD, and BLN can
be used to determine and even or odd field
by connecting it to the data input of the same
flip-flop. This works well for standard signals.
The Field ID is used only as a reset for a
divide-by-two flip-flop from vertical sync. In
this way, if there is not a good field interlace,
the field memories will still be written to on an
alternate basis.
Only active picture information is stored in
memory. The BLN signal is used to store 720
picture elements for each scan line. Each
field memory has enough storage even for
PAL video signals.
A digital data bus connector is provided on
the output side of the memory for expansion
to 8-bit 4:1:1 digital output format. The
memories are rated for 30ns clock maximum.
May 10,1991
Therefore, the memory could be read out at
rates higher than 13.5MHz if modifications
were made to the board.
SYSTEM IMPROVEMENTS
There are several areas in the design of this
board which can be improved if necessary.
The software for the microprocessor can be
easily expanded to include automatic
detection of broadcast standard by the
SAA9051. Only about 10% of the 2KB ROM
is currently used for board set-up.
This board is double-sided. If a ground plane
were added, the system signal-to-noise ratio
would be improved.
to improve stability of color and black level,
an external circuit feeding RGB signals back
into the TDA4680 dark current input is
suggested. The external circuit required
about six extra transistors and is not
necessary for many applications. The
TDA4680 application diagrams show this
implementation.
PC BOARD LAYOUT
CONSIDERATIONS
The Philips DeskTop Video ICs are designed
for lowest radiated and conducted noise
performance. The high noise performance
can only be achieved if great care is taken
with the PC board layout. The layout should
be optimized for lowest noise on the IC's
analog and digital power and ground lines.
A good decoupling with minimized
interconnection length between the
decoupling capacitors and the corresponding
IC pins is important for low inductive ringing.
Analog and Digital Ground
Planes
The DeskTop Video ICs with analog and
digital circuits, such as ND converter, color
decoder, clock generator and D/A converter
should have two separate ground planes.
The lowest noise in the content of the digital
data stream and a minimum uncertainty of
clock jitter can be aChieved on most of the
PC boards by connecting both ground planes
near the clock generator (SAA9057A,
SAA7157, or SAA7197).
Analog and Digital Power
Supplies
The impedance of the power supply lines
should be as low as possible. In order to
provide EMI suppression in series to the
analog supply pins of the ICs, a ferrite bead
or, better, a ferrite EMI suppressor should be
connected.
2-55
Supply Decoupling
Decoupling capacitors can further reduce the
noise on the power supply lines. For optimum
performance, a 100nF multilayer ceramic
capacitor should be placed as close as
possible to every supply pin of the ICs and
should be connected to the corresponding
digital or analog ground plane. This is needed
especially for the analog supply Pins 4 and 5
at the clock generator. In addition to the
multilayer ceramic capacitors, a 5-1011F
electrolytic capacitor should be placed near
each IC.
Analog Signal Lines
The analog part of the board design should
be isolated as much as possible from the
digital signal and clock lines.
Optimum performance is achieved by
overlaying the analog components with the
analog ground plane.
The video signal lines at the ND converter
TDA8708 and TDA8709 from Pin 19 to
Pin 20 should be as short as possible to
minimize noise pickup.
Application Note
Philips Semiconductors Video Products
DTV9051
Digital video evaluation module
12C VALUES
The following values are loaded into the
12C-addressable components at power-up.
This corresponds to video input #1, NTSC,
NTSC matrix, 1 volt peak-to-peak output.
SAA9051
TOA8444
Slave Address 8AH
Slave Address 40H
Slave Address 88H
64H
26H
2AH
Reg 00
35H
Reg 00
TOA4680
26H
13H
OAH
1EH
33H
f8H
OOH
22H
CAH
OOH
34H
FEH
23H
34H
29H
3FH
34H
OOH
3FH
20H
77H
Reg 00
20H
EOH
20H
40H
3FH
OOH
89H
Reg OCH
10H
Reg OOH
Reg OAH
NOTE:
TDA4680 register OBH is omitted. The TDA4670 responds to this subaddress only.
CONCLUSION
This digital multi standard decoder board
provides a means of evaluating the
performance of the Philips digital television
system, and of quickly prototyping your
application. The digital video system delivers
a robust, flexible, and cost-effective solution
for digitizing video images.
May 10,1991
2-56
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Philips Semiconductors Video Products
Application Note
Digital video evaluation module
DTV9051
PHILIPS DMSD2 DEMO BOARD PARTS LIST (Revised May 10,1991)
ITEM
QUANTITY
REFERENCE
PART
1
8
J-Y/C CHROMA1, J-BLU 1, J-GREEN1, J-IN1, J-RED1, J-SYNC1, J-IN2, J-IN3
BNC
2
8
R1,R2,R3,R4,R5,R6,R7,R8
75
3
1
S1
SWSPDT
4
2
R46, R47
6.8K
5
1
C5
0.22
6
7
R11,.R10, R12, R21, R48, 17149, R50
10K
7
1
JP2
10 volt in
8
1
J-IIC1
4PIN
9
1
P1
DB26
10
1
JP1
BLANK JUMP
11
5
C1, C2, C3, C4, C39
3.3/16V
12
1
VR1
LM7805
13
1
VR2
LM7808
14
35
C69,C6,C9,C14,C17,C22,C23,C24,C25,C26,C27,C29,C33,C34,C35,C40,
C41, C42, C43, C44, C45, C58, C59, C60, C61, C62, C63, C64, C65, C66, C74,
C75, C77, C81, C86
0.1
15
6
C70,C49,C50,C68,C71,C73
22120V
16
1
C72
220/10V
17
14
C76,C28,C30,C31,C32,C46,C47,C52,C53,C54,C55,C78,C79,C80
22116V
18
3
L5, L4, L7
100llH
19
1
L6
100llH
20
1
U1
TDA8709
21
1
U2
TDA8708
22
1
U3
SAA9051
23
1
C7
0.33
24
2
R13,R36
330
750
25
4
R14; R16, R18, R19
26
2
R15, R60
680K
27
1
Y1
24.576
L2, L3
221lH
28
2
29
2
'C10, C12
30pF
30
2
C11,C13
30pF
31
1
R17
32
1
U4
15
,
SAA9057
.'
33
2
R20, R39
34
2
JP3, JPDMSD ADD
35
1
C8
1nF
36
1
l1
10llF
37
2
C15, C16
1/16V
"
May 10,1991
470
HEADER 3
2-58
Application Note
Philips Semiconductors Video Products
Digital video evaluation module
DTV9051
PHILIPS DMSD2 DEMO BOARD PARTS LIST (Revised May 10,1991)
REFERENCE
ITEM
QUANTITY
38
4
R26,R43,R44,R45
39
4
R27,R51,R52,R53
10
40
9
R28,R29,R30,R31,R32,R33,R54,R55,R56
4.7K
PART
68
41
5
01, 02, 03, 04, 05
PN2222
42
2
C20, C21
10nF
43
5
02,D3,04,05,06
1N4148
44
3
U7,U6,U9
74HC74
45
2
U8,U5
74AHCT27
46
1
C19
33pF
47
1
R34
8.2K
48
1
R35
2.4K
49
6
U1~U11,U12,U13;U14,U15
TMS4C1050
50
1
JP5
JUMPER
51
1
R59
56K
52
1
Y20
3.5-12 MHz
53
1
C83
3.3nF
54
2
C85, C84
20pF
55
1
C82
15/16V
S87C751-XXXX
56
1
U16
57
1
U17
PCF8582AP
58
1
R37
560
59
1
R38
820
60
1
R40
680
61
2
R41, R42
100
62
1
C36
100pF
330pF
63
2
C37, C38
64
1
JP4
WIRE
65
1
U21
SAA9060
66
1
U22
TDA4680
67
1
U20
TOA8444
68
1
R58
82K
69
2
R57,R60
20K
70
1
R9
12K
May 10,1991
2-59
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JUMPER WIRE NOT CONNECTED
CHROMAGAIN • f - -
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4 PIN
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D
2
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3
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4
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3
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03 9
02 10
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or
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1 W
R 15
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Application Note
Philips Semiconductors Video Products
DTV9051
Digital video evaluation module
PHILIPS SAA90S1 VS.O AND SAA7191 V1 BLANK AND SYNC TIMING
NOTE: VNL ON, VCR Mode
Field One, Odd NTSC 60Hz
llu
LINE.
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5
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NOTE: Leading edge of V-sync may move with Input noise conditions.
COMPOSITE SYNC
VERTICAL SYNC
BLN (HREF)
I
I
I
VERTICAL SYNC
125~SEC
Field Two, Even NTSC 60Hz
COMPOSITE SYNC
UNE.
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4
5
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L -_ _
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May 10,1991
2-67
Application Note
Philips Semiconductors Video Products
DTV7199 Digital Television Demonstration System
Author: Herb Kniess
SECTION 1: OVERVIEW
The DTV7199 evaluation board provides a
comprehensive means of demonstrating and
evaluating the latest digital video signal
processing devices from Philips
Semiconductors. Color encoding and
decoding is performed using a
line-locked-clock system. The following ICs
are featured:
TDA8708
Video AID converter, 30M Hz,
8-bit, for CVBS and Y, with analog
pre-processing, clamp and gain
control
TDA8709
Video AID converter, 30M Hz,
8-bit, for C of S-Video, with analog
pre-processing, clamp and gain
control
SAA7151B
Digital Multi Standard Decoder
(DMSD), for CCIR-601 pixel raster
(industrial applications)
SAA7157
Clock Generator Circuit (CGC) for
SAA7191B
SAA7191
Digital Multi Standard Decoder
(DMSD), for square pixel raster
(graphics environment)
SAA7197
Clock Generator Circuit (CGC) for
SAA7191
SAA7192A
Digital Color Space Converter
(DCSC), interpolation filter, YUV
to RGB matrix
SAA7169
Triple DAC, 30M Hz, 9-bit in each
channel
SAA7199B
Digital Encoder (DENC),
GENLOCK capable, from digital
YUV or RGB into analog CVBS or
S-Video
S87C054
Microcontroller,80S1-based,
dedicated for video control
applications, with OSD, on-Chip
EPROM.
Analog video input is accepted in CVBS or
S-Video form, in NTSC, PAL, or SECAM
color standards. The video signals are
digitized and sent to the digital decoder
(DMSD) SAA7151B or SAA7191B for
synchronization processing, line-locked-clock
generation, and color decoding. The output
bus of the DMSD contains digital YUV
baseband information. The data is sent to a
two-field frame store for buffering and time
base conversion. After the frame buffer, the
YUV data is converted to 24-bit RGB data in
the SAA7192A color space converter. The
24-bit RGB data is fed to the .SAA7169 Triple
DAC for analog RGB output conversion and
also to the SAA7199B digital encoder
(DENC). The encoder can be programmed in
various modes, such as GENLOCK so that
time base correction of input Signals is
June 1, 1992
possible. The encoder can operate in NTSC
or PAL television standards.
Various board configurations are possible by
changing jumper settings and by
reprogramming several of the signal
processing devices. In addition, two 60-pin
headers are provided to allow external
connection of digital YUV data before and
after the frame buffer. The MTV onboard
microprocessor sends configuration data to
various devices via an 12C serial two-wire
bus. A connector for the serial data is also
provided to allow external computer control to
the board via a DOS software package
supplied with each board.
SECTION 2: INPUT VIDEO DATA
CONVERSION
Input video sources can be NTSC, PAL, or
SECAM world standards in Y/C or composite
formats by four BNC connectors. Refer to
"Input" section schematic. An S-Video or Y/C
connector is provided at JSVID2 for these
higher performance Y/C input signals. The
Philips TDA8708 8-bit 30MHz AID converter
at location U2 is used for composite or Y
signal processing. It has a three-channel
multiplexer for input source selection, video
clamp for DC restoration, and automatic gain
control in front of the high performance 8-bit
AID converter. Input source selection is
controlled via two switch signals from the
SAA7191 and connected to the TDA8708 at
Pins 14 and 15. The switch signals are
programmed in the DMSDs via the 12C bus.
If the higher performance Y/C input format is
desired, a second data converter is required
for digitizing the chrominance, or "C", half of
the input signal. The TDA8709 at location U1
provides this function. Low pass filters for
removing high frequency components in the
analog input signals are provided between
Pins 19 and 20 of both AID converters before
digitizing. Please note that the AC reference
for the converters is the analog power supply.
The power supplies for these devices are
well decoupled since the performance of the
entire system is determined at the input data
converters. The digitizing clock is provided
by the SAA7197 clock generator at location
U3 with a rate of two times the final pixel rate
for decoded Signal at the output of the
DMSD. The clock rate of the converters is
line-loaded and can range from 24- to 30MHz
depending on input television standards and
the type of digital decoder used. The clock
input on Pin 5 of both AID converters is fed
with a series resistor, which slows the clock
slopes down in order to minimize the effect of
high rise times from the clock line entering
2-68
analog areas around the converter. Clamping
and sync pulses coming from the decoder
are fed to the AID converters on Pins 27 and
26 to inform internal digital level detectors
when to activate and make automatic
adjustments of gain and black level on each
scan line.
It is recommended that the input signal area
and the data converters share a common
ground plane for analog and digital grounds
at the converters. However, it is possible to
have separate ground planes and have the
common point under the data converters on
Pins 23 and 8. High amplitude noise between
Pins 23 and 8 should be avoided. Otherwise
it may cause ground loop conditions within
the converters. The entire video signal is
digitized in order to recover the sync and
color burst information. The converters
deliver 8-bit digital data in a two's
complement format to the decoder input.
The format selection is made by grounding
Pin 9 on both converters. For other
applications the AID converters can be
operated in binary format.
SECTION 3: DIGITAL COLOR
DECODING
After converting analog video inputs to digital
data it is the function of the Digital Multi
Standard Decoder (DMSD) to provide clock
information, sync, blanking and, of course,
luminance and decoded color difference
video data known as YUV or Y, RY, BY.
Refer to the "Inpur' section schematic.
The output signals are all synchronized to the
input video timing in frequency and phase via
a clock control loop feeding from U4 DMSD
on Pin 36 called Line Frequency Control
Output (LFCO) to U3 SAA7197 clock
generator. LFCO is internally generated via
the crystal reference on Pins 33 and 34 of the
DMSD and made to phase lock to incoming
video sync. The frequency of LFCO is one
half of the pixel clock frequency at the output
of the DMSD, so the SAA7197 must multiply
this synthesized frequency by 2 and 4 for the
system line-locked clock. In order to close the
PLL loop, the clock generators' clock outputs
are fed back to the DMSD clock inputs and
the AID converters' clock inputs. The system
works as a highly stable digital PLL because
the DMSD calculates the clock frequency of
LFCO on a line-by-line basis and in
conjunction with the crystal reference
maintains a constant number of clock
samples for each input video scan line
regardless of input signal conditions.
The DMSD also decodes the color
information from video Signals. The UV
Application Note
Philips Semiconductors Video Products
DTV7199 Digital Television Demonstration System
output bus contains the color information in
one of several programmable industry
standard formats such as CCIR 601. In
CCIR 601 the output data bus is 8 bits Y of
luminance and 8 bits UV time multiplexed.
This is 16 bits per pixel or clock cycle. A
4:1:1 mode is also available via 12C
programming if memory cost is too high for
4:2:2 CCIR 601 mode. RAMs U8 and U9
could be removed for 4:1:1 operational mode.
The DTV7199 demo board is capable for
applications of the square pixel DMSD
SAA7191 B as well as of the CCIR-DMSD
SAA7151B. Only the DMSD IC and the
related reference crystal must be exchanged
(see Table 2). The board layout is prepared
to support both systems. Also, the MTV
controller contains software to set up both
ICs.
SECTION 4: MEMORY
INTERFACE AND STORAGE
The 16-bit data bus from the DMSD is being
clocked at rates from 12-15MHz. High speed
serial RAMs were chosen to store the data
without the need for memory addressing and
counting chains. Refer to FIFO and
MEMCON schematic. Each RAM is really a
FIFO with 256k by 4 bits memory. Input and
output clocks can run independently with
some limiting restrictions. Four RAMs, U9,
U10, U 11, U 12, make up a bank for field one.
Four RAMs, U8, U7, U6, U5, make up the
bank for field two. If memory cost is too high
for 4:2:2 CCIR 601 mode, RAMs U8 and U9
could be removed for 4: 1: 1 operational mode.
Video data from the DMSD is stored
alternately in each bank. Only data during
active portion of each scan line is written to
the memory. Less than 75% of the RAM is
used for each incoming field, even in PAL or
SECAM modes.
The simple memory controller comprised of
U15, U17, U19, U51, U20, U21 and U54
uses vertical sync to reset the memory
pointers and horizontal blanking to stop and
start reading and writing the memory. The top
portion of the schematic is for writing into
memory. The bottom portion is for reading
from memory. Devices U15 and U54 provide
timing delays to guarantee that complete
fields will be stored in memory. U51 B will
inhibit writing to memory on frame boundaries
and provide a freeze frame picture for quality
analysis and special effects. Both fields will
be displayed so there may be inter-field
motion displayed on the monitor. The "still
picture" switch activates the freeze frame
with a low on U51 B Pin 12. Switch S 1 must
be in the down position for active video. The
up position is for still frame (both fields).
June 1, 1992
The DMSD generates an HREF signal for
enabling writing to memory. A comparable
signal must be generated for reading from
memory. The SAA7199B encoder does not
deliver such a Horizontal Blanking, but needs
to receive it. HREFO, or Horizontal Blanking,
is generated via counters for output video
timing only by using HSYNC from DENC to
trigger counters. Refer to HREFGEN
schematic.
The HREF generator times the correct
horizontal blanking interval and generates a
delayed HSYNC signal for display monitor
from the HSYNC from the SAA7199B
encoder. U26 Pin 2 receives HSYNC from
the encoder and generates a single clock
reset pulse via U27 Pin 3 to reset U28 and
U29 counters. The output timing diagram and
clock cycles are shown. It is important only
that the total number of clock cycles of HREFO
at U53 Pin 6 be set properly regarding
display and SAA7199B timing scheme. Table
1 shows how to select the memory read
blanking timing interval depending on how
the board is programmed, which standard is
applied and which type of decoder is
installed. If there is an error between
memory write format (number of pixels per
line) and memory read format, there will be a
horizontal error line-by-line down the screen
because the line lengths are different.
HSYNCO is generated at U27 Pin 6 with a
delay because of the pipeline delay through
the SAA7192A color space converter. The
RGB data must be in time with the RGB sync
at the SAA7169 DAC outputs. Transistor Q2
provides composite sync for RGB monitors.
Data for the SAA7199B must be read from
memory early to compensate the delay
through the SAA7192A color space
converter. The SAA7199B encoder has a
programmable HSYNC for this very reason. It
is not known what delay future memory or
memory controllers will produce so the
SAA7199B is prepared to adjust for new
devices.
SECTION 5: COLOR SPACE
CONVERSION AND DAC
Data from memory read operations is passed
through jumper JP14 to the Digital Color
Space Converter SAA7192A. Refer to
SAA7192 schematic. Normally 24 jumpers
are installed on the board to pass data from
the memory through the connector. However,
a daughter board can be added using JP3
and JP14 to multiplex YUV or RGB data at
JP14. The data coming from memory must
be disabled via the expansion board. Make
special note of U16 Pin 5. HREFO is delayed
2-69
by one additional clock to compensate for the
memory read delay of one clock. If this delay
is not compensated for from the memory, the
color space converter will not demultiplex the
UV data bus correctly. U47, U48, U49 switch
data on to the RGB output bus of the
SAA7192A when MTV 87C054 says there is
a character to display. The VCTRL signal
from MTV controls which talks into the RGB
data bus, either the SAA7192A or the MTV.
Pin 61 of the SAA7192A tri-states its output
RGB bus.
The SAA7169 DAC is wired in a standard
configuration, with the low order 2 bits of all
three 1O-bit wide input ports grounded for
8-bit operation. RP1 and RP2 provide low
order bit pull-up when the RGB data bus is
switched to MTV-sourcein order to meet the
CCI R 601 requirement of 16 for black levels.
JP13 chooses two clock phases for U50.
MEMRD is preferred.
SECTION 6: DIGITAL ENCODER
AND GENLOCK
The SAA7191 decoder provides the memory
write clocks and timing, and the SAA7199B
digital encoder provides the memory read
clocks and timing. These input and output
clocks can be synchronous or asynchronous.
The digital encoder will synchronize to any
video reference input signal via U23
TDA8708 in the same manner as the
SAA7191 DMSD if programmed to do so
(GENLOCK mode). Refer to previous
discussions on Digital Decoding. It can also
run in a stable mode, by use of its crystal
reference and U24 SAA7197 clock generator.
A small change in the output level of the
SAA7199B DACs can be made by changing
the bias on Pin 63. Linearity may be affected
with large changes in bias. Key input at Pin
73 has been deactivated by pull-down
resistor R45. The clock generator power
supply has been well filtered at Pin 5 to
guarantee minimum effects from input video
timing crosstalk. Crystal selection for the
SAA7199B should be made as shown in
Table 2. See application note "SAA7199B
Operation Modes".
SECTION 7: POWER SUPPLY
GROUNDING AND LAYOUT
Clean analog power supplies are essential if
the full performance of an 8-bit system is to
be realized. The analog supplies on the AID
converters and the clock generator are the
most sensitive. The performance of the AID
converter determines the signal-to-noise ratio
of the complete system. The performance of
Philips Semiconductors Video Products
Application Note
DTV7199 Digital Television Demonstration System
the clock generator determines system clock
jitter and, to some extent, the quality of the
chroma.demodulation.
Noise on Pins 21 and 22 of the TDA8708 AID
converter will degrade the signal~to-noise
ratio of ari8;log input signals. PfI~ase note that
the low pass filter at Pins 19 and 20 has an .
AC reference to the analog supply on Pin 22.
Therefore, noise on Pin 22 would directly be
coupled to input signals being digitized.
The SM7197 must have a clean analog
supply at Pin 5 which must be directly
connected to Pin 37 on the SAA7191 B or
SAA7151B decoders because olthe close
coupling of the LFCt> signal betWeen the
clock generator and the decoders.
Bypassing capaCitors at pins of both devices
is a must. Of course, all digital power inputs
must be bypassed on all devices.
The DTV7199 evaluation board makes use of
one other power supply isolation technique.
The input and output supplies are regulated
separately. This isolation.guarantees
minimum crosstalk between input decoding
and output encoding. Small ferrite core
June 1,1992
inductors further reduce analog and digital
supply crosstalk.
In many computer applications it is not
possible to regulate the digital supplies
because ofcurrenllirriits placed on higher
supplyyoltages. In this case, only the lower
current analog supplies should be regulated.
Total analog supply current is under 100mA
for input cirCUits and also under 1OOi11A for
output circuits. Because of delay differences
in power supply sequencing during power up,
it is suggested that 5V regulated analog
supplies have parallel opposite biased diodes
connected to the digital supply. This will keep
both supplies in sync during power up. This is
needed to perform a determined power-on
reset procedure at SM7157 and SAA7197.
1N4148 diodes will supply enough current for
a short period of time and allow regulation
isolation of about 600mV.
A single ground plane has been shown to be
effective under input components and ICs
such as the TDA8708, SAA7197 and
SM7191 B. After the decoder, a digital
ground plane could be used if there are a
large number of digital devices and fast
2-70
memory. The input ground plane could be
considered analog ground. The evaluation
board uses a single ground plane for the
entire board. A Single ground plane appears
to work well for most applications.
Clock and data line routing should be kept
away from analog components and analog
signals. The most critical signal is LFCO
between the digital decoder and the clock
generator. It has an analog characteristic
and may pick up unwanted digital noise. The
length of the LFCO trace between these two
devices must be kept to a minimum.
SECTION 8: FACTORY JUMPER
CONFIGURATION
The factory jumper configuration is required
for normal operation of the DTV7199 demo
board when the 87C054 microcontroller has
been installed. Software version 1.x will only
configure the board for NTSC mode using the
SAA7191 decoder with video input connected
to JIN2. Anyone of the push buttons can be
used to switch the ·Philips Digital Video"
message on the screen, on and off.
Philips Semiconductors Video Products
Application Note
DTV7199 Digital Television Demonstration System
Table 1: HREF Length Jumper Table
12.272727
I
14.75
I
13.50
I
13.50
I
I
60Hz
140
50Hz
176
I
60Hz
138
I
50Hz
144
SQUARE PIXELS
SQUARE PIXELS
CCIR601
SAA7191
CCIR 601
SAA7151B (SAA9051)
ICCIR 601
SAA7151B (SAA9051)
Table 2: Crystal Selection
SYSTEM
ACTIVE PIXELS
SQUARE PIXELS
SAA7191
CRYSTAL
DECODER
640 or 768
26.800MHz
SAA7191 decoder
720
24.576MHz
SAA7151 decoder
Table 3: Factory Jumper Settings
JP3
Install all jumpers except bottom six.
JP14
Install all jumpers except bottom six.
JP2
Install jumper to left for SAA7151 (right for SAA7191).
JP20
Installed
JP5
Install jumper to the left.
JP7
Open
JP8
Open
JP6
Open. This is the microprocessor reset.
JP13
Install jumper to the right.
JP19
Open. Install jumpers only if RTC function is required.
JI2C
This connector is for 12C communications.
JP15
Install jumpers depending on which decoder is used.
(See previous section on HREF LENGTH JUMPER TABLE.)
June 1, 1992
2-71
Philips Semiconductors Video Products
Application Note
DTV7199 Digital Television Demonstration System
Table 4. JP3 Functions
PINS
JP3
FUNCTIONS
Table 5. JP14 Functions
PINS
JP14
FUNCTIONS
1,2
DY7
1,2
OY7
3,4
DY6
3,4
OY6
5,6
DY5
5,6
OY5
7,8
DY4
7,8
OY4
9,10
DY3
9,10
OY3
11,12
DY2
11,12
OY2
13,14
DYl
13,14
OYl
15,16
DYO
15,16
OYO
17,18
DUV7
17,18
OY7
19,20
DUV6
19,20
OY6
21,22
DUV5
21,22
OY5
23,24
DUV4
23,24
OY4
25,26
DUV3
25,26
OY3
27,28
DUV2
27,28
OY2
29,30
DUVl
29,30
OYl
31,32
DUVO
31,32
OYO
33,34
LLCI
33,34
OUV7
35,36
VSI
35',36
OUV6
37,38
HREFI
37,38
OUV5
39,40
CREFI
39,40
OUV4
41,42
LL31
41,42
OUV3
43,44
HSI
43,44
OUV2
45,46
SDA
45,46
OUVl
47,48
SCL
47,48
OUVO
49,50
FEIN
49,50
HREFO, KEY
51,52
RESI
51,52
MEMREAD, RESO
53,54
LLCO, VSYNCO
53,54
55,56
55,56
LL30,OPT2
57,58
GROUND
57,58
CREFO,OPTl
59,60
GROUND
59,60
GROUND
June 1, 1992
2-72
Philips Semiconductors Video Products
Application Note
DTV7199 Digital Television Demonstration System
SECTION 9: DEFAULT REGISTER CONFIGURATION VALUES
For composite video input at JIN2; Decoding of NTSC into YUV 4:2:2.
NTSC - SQUARE PIXEL
NTSC - CCIR MODE
REGISTER
(HEX)
SAA7191
SAA7199B
REGISTER
(HEX)
SAA7151B
SAA7199B
00
66H
OCH
00
50H
OCH
01
7FH
OOH
01
3AH
OOH
02
53H
OOH
02
07H
OOH
03
43H
OOH
03
F7H
OOH
04
19H
FOH
04
CBH
FOH
05
OOH
20H
05
OOH
2BH
52H
06
19H
52H
06
35H
07
OOH
OAH
07
OOH
11H
08
7FH
30H
08
BOH
30H
09
7FH
OOH
09
30H
OOH
OA
7FH
OOH
OA
7FH
OOH
OB
7FH
OOH
OB
7FH
OOH
OC
40H
56H
OC
24H
OFH
00
80H
OOH
00
4CH
OOH
OE
79H
OCH
OE
30H
OOH
OF
78H
OF
58H
10
OOH
10
60H
11
18H
11
21H
12
COH
12
OOH*
13
OOH*
14
36H
15
OBH
16
FEH
17
02H
18
OOH
NOTE:
SAA7192A is always programmed in
register 0 with 2A hex.
* Reserved; Program as OOH only.
June 1, 1992
2-73
Application Note
Philips Semiconductors Video Products
DTV7199 Digital Television Demonstration System
SECTION 10: MENU
CONTROLLED SOFTWARE (DVS)
The Desktop Video Software (DVS) package
supports programming of the digital video ICs
on the demo board DTV7199. It guides the
user with a menu-controlled graphic interface,
showing how to program individual functions
and bits accessible by the 12C bus. Detailed
device 12C register data can be obtained by
using the "special options" function. The
software runs on a PC or compatible and
talks to the 12C bus via an interface board at
the parallel printer port. See application note
"12C Parallel Printer Port Adaptor". The DVS
also allows a software-only demonstration
mode; neither 12C bus interface nor device
samples are required to be connected to
operate this demo-mode.
This section gives a short guideline on how to
get started using the Desktop Video control
software for demonstration and evaluation
purposes. The menu-controlled software
offers a lot more features than the
fundamental functions described here.
How to Use the Software-only
Demonstration Mode
Required Equipment
The following equipment is required to
operate the DVS software in demonstration
mode:
eIBM-PC/AT compatible personal
computer, with at least 384 Kbytes of
system memory available
eMS-DOS or PC-DOS operating system
epreferablya color graphics adaptor and
associated monitor
efloppy disk containing the DVS software
and setup files
Procedure
Follow the instructions step by step to install
the software and get it started:
Switch the personal computer and its
monitor on. Wait for completion of self test
and booting of the operation system.
Insert the floppy disk containing the
Desktop Video Software into a disk drive.
Change the current home drive to this drive.
You may copy the content of the DVS
floppy into a dedicated directory on the hard
disk. This will improve the speed for loading
the program and the relateo utility and
setup files.
Type "DVS " to start DVS. The
control software will display "Philips
Semiconductors" on the PC screen and
perform an automatic search for installed
June 1, 1992
desktop video devices and their respective
12C addresses. Because in demonstration
mode there are no such devices connected,
the search will result in "not in use" noted
on the screen for all devices supported by
the software.
Set the devices of interest "active" by using
the "+" key on the numeric keypad and the
cursor up/down to move to the concerned
devices.
Hit "" to finish the device activation
and to proceed with the page assignment
procedure. A default device-to-page
assignment is offered. If you like, use the
function keys to redefine the page
aSSignment.
Hit "" to confirm the device to page
assignment and to proceed.
12C bus check will report "not ready".
Enable demonstration mode by chOOSing
"A" to neglect real1 2C bus operation.
Load any of the predefined settings: Press
"F" to select the file selection menu, press
"L" and enter a filename. "0" gives a
directory of available settings.
Now you have access to all the
programming parameters of the selected
'active' devices. Every device is assigned to
a page number and can be selected by
typing the appropriate function key. Subject
to the amount of programmability for a
certain IC, the page may have sub-pages
called sheets, which are accessible with
page up/page down.
Move the cursor up/down to select a
parameter. Use"+/-" keys of the numeric
keypad to change the selected parameter.
The DTV7199 Demonstration
Board under Control of DVS
Required Equipment
In order to operate the Demo Board
DTV7199 under DVS control the following
items are required in addition to that which is
mentioned for the software-only
demonstration mode:
eDemo Board DTV7199
15-16kHz hori~ontal and 50/60Hz vertical .
scan frequencies, and/or
eTV-monitor, with built-in color decoder, with
'external' CVBS or S-Video input
-cables to connect the video signal source to
the board (BNC or S-Video), cables to
connect the board's RGB output (BNC) to
the monitor, cable to connect the encoded
CVBS from the board (BNC or S-Video) to
the TV monitor.
Procedure
Follow the instructions step by step to power
up the system and run the software:
Connect the DTV7199 demo board with a
signal source at the input BNC connector
JIN2. Switch the signal source on.
Connect the RGB outputs and associated
sync BNC connectors with a RGB monitor,
or
Connect the encoder output CVBS-out or
S-Video out with a TV monitor.
Power up the demo board with the 12C
cable not connected to the board. The
on-board control software embedded in the
MTV loads the default parameters. This
requires a few seconds and then the 12C
bus is idle.
The monitor shows a picture according to
the default settings.
Plug the 12C bus adapter board into the
parallel printer connector (Centronics
Interface) of the personal computer.
Connect the 12C cable (gray, 4 wires) to this
12C bus adapter board.
Switch the personal computer and its
monitor on. Wait for completion of self test
and booting of the operation system.
Insert the floppy disk containing the
Desktop Video Software into a disk drive.
Change the current home drive to this drive.
You may copy the content of the DVS
floppy into a dedicated directory on the hard
disk. This will improve the speed for loading
the program and the related utility and
setup files.
-one or two video signal sources, e.g., video
test pattern generator, or a video camera,
video tape recorder, etc.
Type "DVS " to start DVS. The
control software will display "Philips
Semiconductors" on the PC screen and
perform an automatic search for installed
desktop video devices and their respective
addresses. The found devices are listed
with their 12C addresses and declared as
"active". If necessary, that can be changed
using cursor keys and "+/-" keys.
-RGB monitor, capable of displaying analog
RGB inputs at television frequencies of
Hit "" to confirm the device search
program results as displayed and to
ePower supply 8V DC, 1A
-12C bus adapter board, to be connected to
the PC's parallel printer board and
associated 12C cable
2-74
Philips Semiconductors Video Products
Application Note
DTV7199 Digital Television Demonstration System
proceed to the page assignment procedure.
A default device-to-page assignment is
offered. If you like, use the function keys to
redefine the page assignment.
Hit "" to confirm the device to page
assignment and to proceed.
In normal DVS operation mode the
initialization is performed by selecting a
predefined initialization data files.
Press "F" to select the file selection menu,
press "L" and enter a filename; the file
"DTV7199" is provided as default setting.
Typing "D" would display a directory of
available settings.
The software pre-loads all the device
parameters; but the actual transmission into
the 12C device registers is inhibited until the
transmission is triggered by typing "T" to
select the transmit option and "I" to perform
the initialization.
The RGB monitor (respectively the TV
monitor) should now show a picture
according to the programming as loaded by
the file.
Now there is access to all the programming
parameters of the selected 'active' devices.
Every device is assigned to a page number
and can be selected by typing the
appropriate function key F1, F2, etc.
Subject to the amount of programmable
parameters for a certain IC, the page may
have sub-pages called sheets, which are
accessible with page up/ page down.
Use cursor up/down to select a parameter.
Use"+/-" keys of the numeric keypad to
change the selected parameter. As long as
June 1, 1992
transmit function is enabled, the changes of
parameters are updated immediately into
the device programming registers.
The results of new programming can be
studied directly on the monitor screen.
Loading Look-up Tables of
SAA7192A and SAA7199B
Under the programming page of the Digital
Color Space Converter SAA7192A, select the
OS" special option to load the Video Look-up
Tables (VLUT). The sub-menu asks for a
filename with the data for the contents of the
VLUT. Enter "?" to see the available files or
give the desired filename. All files with the
extension '.VLT' are data files for VLUT.
Under the pages for the digital encoder
SAA7199B one will also find a similar special
option "S" sub-menu to load data into the
encoders Color Look-up Tables (CLUT). The
files that are provided for this purpose carry
the extension '.CLT'.
The DVS floppy also contains a utility
program SHOW_LUT.exe, which shows the
content of VLT-files as well as CLT-files in a
graphic representation. Under DOS just type
"SHOW_LUT filename.CLT".
Determining 12C Register
Contents
By means of DVS it is possible to determine
the binary or hexadecimal values for the
various programming registers for certain
programming configurations. These codes
can serve as reference for a specific device
initialization of a dedicated system, where the
programming is drawn from a ROM, PROM
or other system file. The software-only
2-75
demonstration mode of DVS is especially
very helpful for this purpose to obtain the
'compiled' 12C register content based on the
chosen parameter programming.
The SAA7192A has a single byte for 12C
programming. The binary representation of
the selected programming is directly
displayed on that single device page.
For the digital decoders SAA7151B and
SAA7191 B, as well as the digital encoder
SAA7199B, the "special option" is supported
by pressing OS". This submenu directly
displays the table of the 12C registers,
displaying the content in binary as well as in
hexadecimal representation. For the encoder
this table is in the sub-sub-menu Read the
section on Registers.
Please note that these tables do not include
the 12C address and the subaddresS/index
data required to program the ICs. Refer to the
respective data sheets for the exact data
protocols for initialization of each device.
Saving of device and board
program settings
It is possible to store the device settings as a
data file for use in future sessions. The
program saves the settings of all devices in
one turn; press "P to select the file option
and OS" to select the save to file option. The
user is asked for a file name. the filename
must not have any file extension; this is
automatically set to' .VAL' by the program.
Please make sure that a unique new filename
is used to store the setting, otherwise the
program will update the device settings of the
previously loaded data file as default file.
Application Note
Philips Semiconductors Video Products
DTV7199 Digital Television Demonstration System
SECTION 11: NOTES
SOFTWARE:
DVS V. 303 OR LATER
FOR USE ON PC DOS
SYSTEMS
UNIVERSAL 12C V. 3.2
OR LATER
MTV CPU (ON BOARD)
V1.0 OR LATER
1. Do not connect the printer 12C adaptor
cable to the demonstration board until the
microprocessor has sent out the board
configuration data after power up.
2. Only install jumpers at JP19 if RTC feature
is required.
If jumpers are installed at JP19, then U24
output clock generator, must be removed.
The "B" versions of the digital decoder and
digital encoder support RTC (Real Time
Control). Real time control means that the
Digital Encoder SAA7199B,will GENLOCK
to the timing signals from the Digital
Decoder and clock generator. RTC is a
special GENLOCK mode of the Philips
Digital Video product family.
3. JP2 selects slave address BA or BE for the
digital decoder. The microcontroller
June 1, 1992
transmits data to slave address BA for the
SAA7191 and to slave address 8E for the
SAA7151B.
4. The microprocessor may have other menu
and programming functions at a future
date. If so, the sign-on message will
contain new instructions and options as
they become available.
5. IC U14 may not be installed from the
factory. It can be used to store screen
messages and board configuration settings
in future software revisions of the onboard
microprocessor at U13.
6. A display monitor such as Sony 1342Q or
similar is a good choice for evaluating the
YIC, RGB, or CompOSite Video outputs
from the evaluation board. This monitor
also displays and decodes PAL if the demo
board is reprogrammed.
7. The onboard microprocessor will set up
the board for NTSC mode, SAA7199B
GENLOCK active, SAA7191 decoder
installed, video input composite at JIN2. It
is recommended that a reference Signal be
connected to the GENLOCK input
connector at JGL 1 so that the digital
encoder, SAA7199B, will have a reference.
2-76
The reference can be the same video
source as the input signal. Double
termination of the source signal will be
compensated by the automatic gain
functions in the TDAB70B AID converters.
B. High stability GENLOCK even to VCR-type
signals is possible with the digital decoder
and the digital encoder as well.
GENLOCK to VCRs in high speed shuttle
or search mode is excellent even for the
digital encoder.
.
9. Real Time Control (RTC) allows the
SAA7199B encoder to use sync and
clocks from the input section comprised of
the SAA7191, SAA7197, and the
TDAB70B. The SAA7199B does not
require the reference crystal or the
SAA7197 at location U24 to operate in
RTCmode.
RTC signals from the digital decoder
transport frequency, phase and other
critical timing information about the system
clock for other Philips' devices such as the
SAA7199B encoder. RTC is a special
minimum system configuration feature. It
is not a requirement of most applications to
make use of RTC.
Philips Semiconductors Video Products
Application Note
DTV7199 Digital Television Demonstration System
DIVAS EVALUATION BOARD (Revised May 21,1992)
REVISION: E
Bill of Materials May 21, 1992
ITEM
QUANTITY
1
7
C1,C2,C3,C4,C59,C62,C76
3.31lF
PART
2
23
C5, C6, C7, C8, C13, C17, C18, C19, C21, C23, C27, C28, C31, C49, C57, C77, C78, C79,
C80,C82,C126,C129,C132
221l F
3
52
C9, C10, C11, C12, C14, C15, C16, C20, C22, C24, C25, C26, C29, C30, C32, C33, C37,
C38,C43,C44,C45,C50,C51,C52,C53,C54,C58,C60,C61,C66,C67,C69,C70,C71,
C72, C73, C74, C75, C97, C121, C122, C123, C124, C125, C127, C128, C130, C131,
C142,C143,C144,C145
0.11lF
4
5
C34,C40,C55,C56,C84
20pF
5
3
C35, C41, C83
30pF
REFERENCE
6
2
C36, C42
11lF
7
2
C39, C68
.221lF
8
3
C46, C63, C133
.0011lF
9
4
C47, C48, C64, C65
10
1
C81
10pF
220llF
11
12
C85, C88, C89, C92, C93, C96, C109, C112, C113, C116, C117, C120
12
6
C86, C90, C95,
cm, C114, C118
390pF
560pF
220pF
13
6
C87, C91, C94, C110, C115, C119
14
2
C134, C135
.011lF
15
3
C136, C137, C138
XXXX
16
3
C139, C140, C141
17
3
D1,D2,D3
18
1
J-8V1
19
10
J-BLUE1, J-CHROMA1, J-CVBS1, J-GL 1, J-GREEN1 , J-IN1, J-RED1, J-SYNC1, J-IN2,
J-IN3
20
1
J-GND1
21
3
J-GND2, J-GND3, J-GND4
22
1
J-GND5
23
1
J-12C1
24
2
J-SVID1, JSVID2
25
3
JP2, JP5, JP13
26
2
JP3, JP14
680pF
1N4148
8VDC
BNC
GND
GNDTP
J-GND
4PIN
S-VIDEO
HEADER 3
HEADER30X2
27
1
JP6
JUMPER
28
1
JP15
HEADER8X2
29
2
JP17, JP18
30
1
JP19
HEADER 2
RTC MODE CONTROL
31
1
JP20
HREFO
32
9
L 1, L2, L3, L4, L5, L6, L7, L8, L 13
100llH
221lH
33
3
L9, L10, L14
34
2
L11, L12
10llH
35
15
L15, L16, L17, L18, L19, L20, L21, L22, L23, L24, L25, L26, L27, L28, L29
2.71lH
36
2
01,02
37
7
R1,R2,R3,R4,R7,R30,R36
38
13
R5,R6,R10, R11, R19,R20,R21,R22, R23,R32,R39,R50,R51
June 1,1992
PN2222
-
2-77
75
10K
Philips Semiconductors Video Products
Application Note
DTV7199 Digital Television Demonstration System
DIVAS EVALUATION BOARD (Continued) (Revised May 21 1992)
ITEM
QUANTITY
39
6
R8,R9;R13,R14,R33,R34
REFERENCE
PART
750
40
4
R12, R15, R35, R41
330
41
4
R16,R37,R59,R60
42
1
R17
47K
43
13
RP1, RP2, R18, R24, R25, R27, R28, R45, R53, R54, R55, R56, R58
4.7K
44
1
R26
45
2
R29,R40
46
1
R31
33K
47
1
R38
680K
48
3
R42,R43,R44
49
3
R46,R47,R48
50
1
R49
51
1
R52
6.8K
52
1
R57
100K
22
10
1.5K
30
15
15K
53
1
RP3
54
1
S1
55
4
S2,S3,S4,S5
56
1
U1
TDA8709
57
2
U2,U23
TDA8708
58
2
U3,U24
59
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SAA71918
60
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61
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62
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PCF8582E
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63
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65
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Application Note
DTV7199 Digital Television Demonstration System
APPENDIX TO DTV7199 APPLICATION NOTE
Measurements on SAA7199B
The digital encoder SAA7199B is brought into
slave mode and a digital pattem generator is
applied to feed the data to the encoder's
input. With a test pattern according to CCIR
test procedure 100% luminance (white) and
75% color saturation (see application note
"Digital interface for component video'
signals") a standard color bar test signal is
generated. Figure 1 shows the measurement
on Tektronix 521A vectorscope for a PAL
signal under a 13.5MHz clock (CC1R 601).
The color dots are clearly in the target boxes.
The small deviations (spot size and angle)
are in the accuracy limitations of an 8-bit
representation of video baseband signals.
provides luminance ramps and color
saturation (envelope) ramps together. It
supports differential phase measurement with
real video specific constraints (no saturation
at black). The result of such a check is
shown in Figure 4. The differential phase
Figure 2 shows the transients for 100% color' error is less than 1.5 degrees peak-to-peak.
. The CCIR color bar tolerance boxes are
saturation in primary colors by means of a
multiple color sawtooth test signal. This .testabout four times as large.
signal, shown in Figure 3 in its time domain,
Figure 1. Color bar test signal on thevectorscope .
June 1,1992
2-89
Philips Semiconductors Video Products
Application Note
DTV7199 Digital Television Demonstration System
Figure 2. Color transients
Figure 3. Color and luminance ramps combined signal
June 1,1992
2-90
Philips Semiconductors Video Products
Application Note
DTV7199 Digital Television Demonstration System
Figure 4. Differential phase measurement
June 1,1992
2-91
Philips Semiconductors Video Products
Application Note
DTV7199 Digital Television Demonstration System
Figure 5. Differential ph~se measure'ment
Second color ramp
June 1, 1992
2-92
Philips Semiconductors Video Products
Application Note
SAA71998 operational modes
Author: Herb Kniess
INTRODUCTION
The SAA7199B Digital Video Signal Encoder
can be configured to operate in one of four
different modes. Each operation mode has
different system cost and interface
considerations. One or more modes may be
implemented for each application depending
on system requirements and hardware
interfaces. This note describes the different
hardware configurations for the different
modes and also the available timing
programmabilities.
GENLOCK MODE
In many system applications it is necessary
to GENLOCK the CVBS video output of the
encoder to a master timing reference. It is
necessary in GENLOCK MODE to adjust the
horizontal sync and subcarrier phase relative
to the master reference in order to
compensate for external phase shift or signal
delays in cable connections. The SAA7199B
can GENLOCK to stable references and also
to signals with time base errors such as
signals from consumer VCRs. As all signals
including the subcarrier will follow the
reference signal, RS170A cannot be enforced
automatically; if the reference is standard, the
encoded CVBS will be standard. See Figure
1 for connection diagram.
GENLOCK mode can be turned off via 12C
control register in the absence of a reference
sync signal and the sync-to-clock PLL will
assume the nominal default frequency (see
Stand Alone Mode). In GENLOCK mode it is
necessary to digitize the reference signal
using the TDA8708 AID converter. The
TDA8708 AID converter is operated at
normal data rates, not 2><, as in applications
with the 8-bit digital decoders. The SAA7197
clock generator is used to assist in
generation of the system clock. A stable
crystal reference completes the GENLOCK
configuration. An external stable clock could
be supplied at Pin 59 instead of the crystal
oscillator. It is important to note that in
GENLOCK mode the SAA7199B will
precisely follow the sync and subcarrier
phase of the reference signal. The
SAA7199B generates all sync, clock, and
timing signals to strobe and trigger the data
source. The SAA7199B supports that by
extensive programmability.
Input data, e.g., from a frame buffer memory,
must be supplied when requested so that
encoded signals will be available on DAC
outputs in time with the reference signal.
Data inputs to the encoder must be supplied
ahead of the analog output sync signal
because of internal pipe line delays of 55
clocks. The horizontal sync (HSN) on Pin 84
can be programmed relative to the reference
June 1992
signal to compensate for memory access
delays and the 55 clock pipeline delay in the
encoder (see also the chapter on Timing later
in this application note). The composite
blanking CBN must be supplied to Pin 23 as
an input to synchronize data handling. Pin 3
VS/CSY is normally programmed as vertical
output to be used as a reset for memory
controllers at the beginning of a field at line 6.
A single clock system is shown for
convenience and ease of interface (for the
double clock system, please refer to the
datasheet). IC 3A and 3B delay the system
clock by at least 8ns at Pins 55 and 49 to
follow the LDV clock requirements. LDV
latches data from the signal data source.
STAND ALONE MODE
STAND ALONE MODE is a Simplified version
relative to GENLOCK mode but shows the
same data input interface. The TDA8708 AID
converter is not used and stable sync and
timing signals are always generated by the
SAA7199B based on a stable clock Since
the subcarrier frequency is also synthesized
out of this clock frequency, the clock needs to
have sufficient accuracy and stability to
ensure RS1970A standard. It is an option to
let the clock be generated by the SAA7199B
itself in conjunction with a SAA7197 and a
crystal.
The crystal reference frequency is
24.576MHz for CCI R system or 26.8MHz for
square pixel system, but only one crystal for
PAL or NTSC. CCIR-624 specifies - as
broadcast requirement - a tolerance of 5ppm
(NTSC) respectively 2ppm (PAL), but regular
consumer-like equipment except static
deviations of 50ppm or more. By means of
FSC(0 ... 7) in programming register index-OD
frequency offset in the crystal reference can
be compensated in the range of ±450ppm in
steps of 2ppm. An external stable reference
clock could be used at Pin 59 instead of the
crystal oscillator. See Figure 2 for connection
diagram. U2A and U2B is used again to delay
the main encoder clocks relative to LDV
about 10ns. LDV latches data from memory.
SLAVE MODE
All timing signals such as sync, clocks, and
blanking are provided by external sources.
The clocks must be crystal stable, without
exception.
Note the clock delay through UIA and UIB of
about 10ns. No other components are
required because the external source
provides all timing information. Pin 59 XTALI
should be grounded because the reference
crystal is not needed. Figure 3 shows pin
connections and signal directions. The output
2-93
analog sync will contain proper equalizing,
serration, and burst blanking signals even if
they are not contained on input sync signals.
As an option, the clock may be generated by
the SAA7199Ain conjunction with SAA7197
and a reference crystal (see Stand Alone
Mode).
REMOTE GENLOCK (RTC MODE)
RTC MODE (Real Time Control) is an
exclusive feature of Philips Digital Decoders
and Digital Encoders. Pin 57 (RTCI) must be
programmed and connected to a SAA7191 B
or SAA7151B digital decoder RTCO pin. In
RTC mode the digital decoder front end
provides all timing information including the
clock to the SAA7199B. The clock frequency
may vary, especially since a digital decoder
could be locking to a VCR source. However,
with the connection of RTCO from a decoder,
the encoded subcarrier in the SAA7199B will
be stabilized even with VCR sources as
inputs. RTC and the DMSDs LLC-clock can
be applied to the SAA7199B under stand
alone, as well as slave mode. The connection
block diagram is shown in Figure 4. Note the
clock delay through U3A and U3B of about
10ns.
RTC MODE allows a complete decoding and
encoding system to be configured with only
four processing devices. The following ICs
are required as the minimum configuration:
1. TDA8708 AID Converter
2. SAA7151B or SAA7191B Digital Decoder
3. SAA7157 or SAA7197 Clock Generator
4. SAA7199B Digital Encoder
The RTC line contains valuable data about
the system clock phase and frequency and
related subcarrier information generated
within the decoder during the color
demodulation process. The data is updated
every line and coded in a serialized protocol;
protocol start is self-synchronizing, i.e.,
sender and receiver can have different
line-sync phase.
When a SAA7199B is connected directly to
the decoder clock system, it is possible to
encode stable subcarrier even with variable
but line-loaded system clocks from the
decoding front end. The output sync and
subcarrier from the encoder will have the
same timing (standard or non-standard) as
the input demodulated signals (standard or
non-standard) in front of the decoder. The
digitized CVBS in front of the DMSD can be
applied to the CVBS input Pins (76-83) of the
SAA7199B to be used with the CVBS key
function. The timing programming range of
HS as DMSD output and HSN as DENCs
Application Note
Philips Semiconductors Video Products
SAA71998 operational modes
input allows direct sync-coupling. The
subcarrier phase is adjustable via
programming as needed by the application
purpose. The DP inputs of the SAA7199B
may carry manipulated or other video overlay
data. With a memory buffer included in the
system between DMSD and DENC, the sync
timing can be different in phase than the
accumulated data processing delay of about
150 clocks, but will remain constant because
the clocks are the same.
Output Timing to GENLOCK
Reference Input
whole cycle of 360 degrees in 256 steps,
which means 1.4 degree each step.
The SAA7199B has an internal timing
machine which generates all timing and
gating signals to generate the proper sync
pulse position (phase), sync pulse duration,
sync slopes, default blanking, burst gate
position and length as well as burst envelope
(shaping) for all possible clock frequencies
and video standards to be selected. The
result of that can be seen in the CVBSoutput
signal- or Y-C outputs at Pins 69, 67 and 65.
The adjustment of GENLOCK-delay and
subcarrier phase offset is relevant in an
application where the generated DENC
output is further processed and mixed with
other video signals for editing purposes. Also
for modulating multiple video sources onto
one cable or for broadcasting by air a
well·defined phase relationship of these
Signals is necessary in order to keep channel
cross-talk under control.
DATA, BLANKING, AND SYNC
TIMING
In GENLOCK mode the DENC refers its
internal timing machine to the digital CVBS
signal (applied to the Pins 76 to 83). The
DENC investigates that external CVBS,
detects the slope of the horizontal
synchronization pulse, and locks phase and
frequency of the clock via SAA7197 and
sampling ADC TDA8708 to this reference
tREF1(Line-Locked-Clock system). Beyond
that it is possible to program a constant time
offset between sync-pulse of the reference
tREF1 and sync-pulse of the CVBS output,
respectively the Y-C outputs (compare Figure
5), but maintaining the Line-Locked-Clock
feature. By programming the GDC-bits in
register index-05 to zero the CVBS output is
17 pixel clock cycles later than the reference
CVBS; programming GDC to 17 decimal (11
hexadecimal) brings reference and CVBS
output into identical phase. Increasing the
GDC value up to 63 decimal (3F
hexadecimal) brings the internal timing
scheme and the output CVBS in advance of
the reference input by up to 46 pixel clock
cycles earlier.
Processing Delay and
Programmable Timing
Depending on the different operation modes
of the digital encoder SAA7199B, the timing from the digital input side to the analog output
respectively to the analog CVBS reference can be programmed in different ways.
Figure 5 is a reprint of Figure 10 from the
SAA7199B data sheet; it shows the timing of
input data and sync to output representing
that sync and data. There is a constant 55
pixel clock pipeline delay from input data to
analog output signals. The horizontal
sync-signal HSN at Pin 84 can be an input or
an output depending on the selected
operational mode of the encoder. The relative
timing of HSN to the analog output sync is
programmable for input as well as for output
modes.
Composite blanking CBN at Pin 23 must
have a rising edge at the beginning o.f active
data to ensure proper operation of the UV
format demultiplexer and also to remove the
blanking condition. Video blanking is forced
during vertical and horizontal blanking
regardless of the state of CBN signal of Pin
23.
Independent of this GENLOCK-delay
programming via GDC, it is also possible to
adjust the subcarrier phase of the output
relative to the subcarrier phase at the
reference input. The programming byte
CHPS(0 .. 7) in register index~oC covers the
CBN and tREF2
The proceSSing (pipeline) delay tENC from
digital data input to analog output is constant
under all modes, input formats, clocks and
other programming conditions and is 55 pixel
clockS (compare Figure 5). Data fed into the
digital input ports DPn (n=1,2,3) are visible
55 pixel clock cycles later in the analog video
output signal. Figure 5 shows the compOSite
blanking input CBN in nominal standard form;
CBN may claim a wider blanking period if
less data than the nominal active pixels per
line are available. The same processing
delay tENC = 55 pixel clocks ahead of the
leading slope of the CVBS output signal is
the reference point for the leading edge of the
(imaginary) sync pulse at the data input. In
Figure 5 this point is signed with tREF2. The
different standard requirements for NTSC
and PAL and the various possible clock
frequencies result in different number of clock
pulses for the nominal blanking period, and
for the time from the start of sync to the end
of line blanking. Table 1 lists the relevant
numbers. The number for nominal line
blanking period is implemented via the
internal timing machine as default; it cannot
be shortened, but blanking can be extended
by CBN at Pin 23. The rising slope of CBN
also synchronizes the UV format demultiplex
sequence.
Table 1. Standards and Number of Clocks
STANDARD
SYSTEM
PIXEL CLOCK
ACTIVE
PIXELS
LINE
BLANKING
(PIX-Cl)
SYNC START
TO ACTIVE
LINE
LINE PERIOD
2.0V
TIL level low, i.e., < 0.8V
HIGH
LOW
=
LUTs:
BYPASS
ACTIVE
Look-up tables not in signal path
the three RAM-tables are used independently as three 8-bit --+ 24-bit Look-up tables in the three channels RGB or
8~24
the RAM-block is used as one 8-bit --+ 24-bit look-up table to transform indexed or palettized 8-bit color into
24-bit color
=
YUV
June 1992
2-96
Application Note
Philips Semiconductors Video Products
SAA71998 operational r:nodes
Table 3. VTBY and CCIR Bits
SELECTED:
PROGRAM·BYTE
MPK
PIN #32
INDEX09HEX
INDEXOOHEX
D7
VTBY
LOW
0
LOW
1
D2
CCIR
D5
MPKC1
D4
MPKCO
LUTs
X
X
IN DATA-PATH
IN BYPASS
X
X
LOW
0
X
X
DMSD-2
LOW
1
X
X
CCIR 601
HIGH
X
0
0
HIGH
X
0
0
0
DMSD-2
HIGH
X
1
0
0
CCIR601
HIGH
X
X
0
1
HIGH
X
X
1
HIGH
X
X
1
NOTES:
X
HIGH
LOW
LEVELS
ACC. TO
don't care
=
June 1992
TTL level high, i.e., > 2.0V
TTL level low, i.e., < O.8V
2-97
IN DATA-PATH
IN DATA-PATH
CCIR601
0
DON'T USE
DON'T USE
1
8~24
BITS
CCIR601
Application Note
Philips Semiconductors Video Products
SAA71998 operational modes
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June 1992
2-98
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Philips Semiconductors Video Products
Application Note
SAA71998 operational modes
Figure 2. SAA7199Bclock wiring Stand Alone mode
June 1992
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Application Note
Philips Semiconductors Video Products
SAA71998 operational modes
CVBS input signal;
GENLOCK only
trREF1
trREF2
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f--I
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Figure 5. Processing delay and programmable timing
June 1992
~
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0 to 64017201780
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HSN output signal
2-102
Philips Semiconductors Video Products
Application Note
DTV7194/96
Desktop video demo board
Author: Leo Warmuth
OVERVIEW
The DTV7194/96 demo board shows the
system concept of Philips desktop video ICs.
The main video processing functions
incorporated in the demo board, are:
1. Video capture with multistandard
decoding
2. Standardized digital video signal interface
3. Digital scaling
4. Frame buffer and related control
5. Video encoding
6. DACs and RGB conversion.
The DTV7194/96 demo board features the
following Philips desktop video ICs:
TDA8708
8-bit ADC for CVBS and Y
TDA8709
8-bit ADC for CVBS and C
SAA7194/96
Digital true multistandard
decoder-NTSC, PAL, and
SECAM; horizontal and
vertical scaling with filtering
in both horizontal and
vertical domains; control
function for brightness,
contrast, and saturation;
expansion port 110;
SAA7196 also includes
clock generator circuit
SAA7197
Clock generator; only
needed in combination with
SAA7194
SAA7199B
Digital NTSC/PAL encoder
SAA7169
Three channel ADC (RGB)
SAA7165
DAC for YUV 4:2:2 with
peaking; color and transient
improvement
TDA4686
High-speed YUV-RGB
matrix with switch and
control functions
This document focuses on the functionality
and interfaces of the new highly integrated
video capture IC SAA7194/96, also called
DESC:
- Digital multistandard decoder (NTSC, PAL,
SECAM); SAA7196 includes also clock
generator circuit.
- Expansion port with standardized digital
video interface, CCIR oriented coding of
digital YUV
- SCaling with programmable filter in
horizontal and vertical direction for
anti-aliasing and asynchronous FIFO buffer
for easy memory interface.
In addition, a memory controller is described,
realized by means of PLDs, which
demonstrates both scaler output interface
modes: synchronous (transparent) and
asynchronous (FIFO) operation. The problem
of conversion from interlaced to
non-interlaced video signal and vice-versa is
addressed, too.
The appendix shows all the schematics and
listings of the PLD programming, Le., logic
equations and state machine definitions.
FRONT END
The front end, with the analog-to-digital
converters TDA8708 and TDA8709, includes
automatic clamp and gain control. This
circuitry is identical to the front end
processing used for SAA7191 and SAA7151.
For a more detailed description, please refer
to the application note "DTV7199 Digital
Television Demonstration System," p. 2-68.
There is no significant fLinctional difference
between SAA7194 and SAA7196 beyond the
clock generator circuit inside the SAA7196.
The application circuitry described here is
prepared for either one. The application,
including the programming model for the
decoder part of the SAA7194/96, is very
similar to that of the SAA7191.
The demo board also uses the following
Philips ICs with general purpose functions:
THE PORTS OF THE SAA7194/96
PCF8574
12C serial-to-parallel
interface
PL22V10
Programmable Logic Device
(PLD)
PLC42VA10
PLD
PML2552
PLD
87C054
Microcontroll.er (MTV),
12C controller,
character overlay generator
PCF8582E
EEPROM with serial1 2C
interface
82B715
12C booster
May 16,1993
Adaptor
The layout of the DTV7194/96 demo board
provides a ring of through-hole measurement
points around the 120-lead quad flat pack
(QFP) package. This layout enables the
signals at each pin to be probed.
Expansion Port
The expansion port of the SAA7194/96 is a
bi-directional digital video signal interface
with YUV and 4:2:2 sampling scheme. The
signal format, i.e., the meaning of the code
values, is based upon CCIR recommendation
2-103
601. The expansion port carries three types
of signals:
- 16-bit wide YUV data
- synchronization signals, HREF and VS
- LLC and CREF clock signals.
These signals can be selected independently
as input or output by means of the 12C bus.
The direction pin DIR can switch the data
stream on a pixel-by-pixel basis.
The expansion port taps the signal path
between the decoder part and scaler part of
the SAA7194/96. The expansion port
interface, as output, looks exactly like the
output of the SAA7191, and is compatible. As
input, the expansion port feeds the scaler
part of the SAA7194/96. As input, it can
share its timing with the decoder part, or it
can provide its own timing signals, including
clock, even if it is asynchronous to the line
locked clock of the decoder part. In the latter
case, the decoder part, together with the
analog front end (ADCs) and CGC,
determines its clock and stays locked to the
incoming analog CVBS or YIC signal.
The signals of the expansion port are brought
onto a separate connector called DAVE. The
two 12C signals are also provided. The
connector is prepared for a ribbon cable
connection, input or output, and support
interface to other video signal processing
devices, e.g., for compression or
decompression, video conference.
Scaler output port
The scaler output of the SAA7194/96 hasdepending on the chosen data format-up to
32 data lines in the VRO port. The
SAA7194/96 provides various RGB, YUV,
and gray-scale data formats at the VRO
scaler output port. The circuitry of the
DTV7194/96 demo board supports the two
formats:
- RGB 24 bits in 4:4:4 sampling scheme
- YUV 16 bits in 4:2:2 sampling scheme, one
pixel at a time.
The color key 'alpha-bit' is available and used
in both formats. The demo board does not
utilize the 2-pixels-per-longword formats,
which are provided by the SAA7194/96 for
wider memory organizations, which would
enable very-high-speed read pixel rates at
the display side.
The scaling output port of SAA7194/96 has
two interface modes:
- the asynchronous FIFO mode
- the synchronous transparent mode.
The DTV7194/96 demo board works in both
interface modes.
In the asynchronous FIFO buffer mode the
SAA7194/96 operates with a FIFO 16 words
Revised: June 1, 1994
Application Note
Philips Semiconductors Video Products
DTV7194/96
Desktop video demo board
deep and up to 32 bits wide, and provides the
signals:
- HFL, the 'half-full-flag', indicates that the
device has at least 8 valid words in the
output FIFO
- INCADR, the 'increment-address' signal,
indicates-together with HFL-that the
memory controller should increment line
and/or field pointer
FRAME BUFFER
Concept for Frame Buffer
Controller
The concept for the memory control on the
DTV7194/96 demo board is guided by the
desire to:
- maximize the usage of given memory
capacity
and requires the signals:
- VCLK, a gated clock burst, as answer to a
request by HFL to empty the FIFO
- ensure synchronous scaling and display
sizing
- VOEN, output enable signal, whose use is
optional.
- minimize the effort on control logic.
The operation of the FIFO mode requires that
the memory controller provide a gated VCLK
after an HFL request to empty, or partly
empty, the FIFO. It is recommended to apply
a burst of 8 VCLK pulses. The SAA7194/96
has already "preloaded" the output with the
"next-to-deliver" signal before it requests a
burst of VCLK. Then, the first VCLK rising
edge clocks out the next following sample.
VCLK is the clock which directly writes into
memory or a register immediately following
the DESC output.
For the synchronous, transparent mode the
SAA7194/96 requires a continuous clock
VCLK, synchronous to its scaler input, and
delivers output data qualified by various valid
and gate signals:
- PXO: qualifying the actual pixel as valid
- LNO: telling that this line (will) carry valid
data
.
- HRF: delay compensated HREF Signal
- HGT: enveloping that part of line selected
for scaling
- VGT: enveloping that part of field selected
for scaling
- OlE: identifying odd and even field.
Not all these signals are needed at the same
time, but their availability may simplify the
design of a memory controller, or make a
system more flexible and capable. For
example, the presence of the false-state of
the line qualifier LNO or vertical gate VGT
informs the system that there will be, for a
certain time, no HFL request, and the system
may undertake other access to the memory.
The demo board DTV7194/96 is made to
demonstrate both scaler output interface
modes. As all pins of the SAA7194/96 are
available on test pOints, the behavior of the
concerned control signals can easily be
observed. The control logic for both cases is
embedded in a single PLD implementation.
For the PLD programming, refer to the
listings in the appendix. Some aspects of the
logic equations and state machine structure
are explained in the following section.
May 16,1993
- support interlace/non-interlace conversion
The solution has the following main
components:
Serial Stream with embedded "Marker"
The video scanning technique maps the
three-dimensional video stream into a
one-dimensional, serial signal stream. But
some markers are inserted as dummy pixels
(not to be displayed), to signal when a line,
field, or frame is complete. This stream is
written into memory in a strict serial
one-dimensional manner.
The start-time of the read process is
controlled by given display raster
coordinates, and then data is read until an
end-of-line marker is found in the data stream
(or an end-of-field/frame marker). The read
process pauses and resumes again at given
display raster coordinates.
Independent of the actual input picture
dimensions, the memory can get filled up to
the last pixel. There is no waste by
incompletely filled rows. A change of input
picture dimensions, e.g., changing of scaling
factor, is immediately transported to the read
and display window control by the Signal
stream itself.
CCIR-601 reserves the codes 00 hex and FF
hex for synchronization purposes. The
SAA7194/96 ensures that the signal stream
does not use these codes. The DTV7194/96
demo board uses the code 00 hex as
end-of-line marker (eol) and the code FF hex
as end-of-field (eof) marker.
Alpha "Marker"
In an extension to this eol/eof marker concept
the alpha bit (color key signal) is also
encoded into the data stream by means of a
special marker-code. The luminance value of
that pixel, which should be keyed-out, is
overwritten with a code, to be interpreted as
'transparent', Le., as a pixel not to be
displayed. This approach makes the need for
an additional alpha bit plane in the memory
obsolete, reduces memory requirements, and
enhances memory efficiency.
2-104
The SAA7194/96-in FIFO mode-fills up
unused FI FO burst words with dummy pixels.
The fill vallJes are coded with 01 hex. The
DTV7194/96 demo board uses this code as
transparent pixel, or key marker, too.
Two Field Buffer Banks (FBB)
The frame buffer memory is split into two
banks, one for "odd" (upper) fields the other
for "even" (lower) fields, respectively, "even"
and "odd" lines. The address-pointer toggle
from one bank to the other can be controlled
independently for read and write processes.
Conversion between interlace and
non-interlace schemes can easily be
performed.
If a video source is interlaced, the first (odd)
field gets written into the "lower" FBB, the
second (even) field gets written into the
"upper" FBB (field toggling). Reading for an
interlaced output (video display) accesses
the memory in opposite order: during odd
field the "upper" FBB gets read, during even
field the "lower" FBB gets read. The time
sequence is maintained and no tearing
occurs where read- and write-address-pointer
are crossing. Reading for a non-interlaced
output will "de-interlace" the stored two-field
picture by reading from both FBB in a
line-alternating fashion (line toggling).
A non-interlaced source writes its first line,
and all odd lines, into the "upper" FBB, and
the interleaving even lines into the "lower"
FBB (line toggling). Reading for a
non-interlaced display will access the
memory in identical order. Reading for an
interlaced output will "interlace" the stored
single frame into two fields by reading during
the "odd" field from the "upper" FBB, and then
during the "even" field from the "lower" FBB in
a field-alternating fashion (field toggling).
Serial Memory: FRAMs
Because the video data stream in this
application is exclusively serial, FIFO-DRAM
ICs are utilized for the frame buffer circuitry.
These FRAMs don't need any addressing
(which saves external address generation)
and therefore significantly simplifies the
control logic. But VRAMs or standard DRAM
memory applications could also be used and
would benefit by the "marker" control concept
and two field buffer bank approach.
Byte Serial, Field Serial
Most of the commonly available memory ICs
have an address space which is deeper than
the number of pixels in a standard video field.
The used FRAMs, for example, have 262144
storage locations. A regular NTSC field with
240 lines and 640 SO-pixels per line results
into 158600 pixels total, which is about 58%
of the available memory address range.
An effective way to get higher memory
utilization is to place the information
Philips Semiconductors Video Products
Application Note
DTV7194/96
Desktop video demo board
belonging to one pixel into two memory
addresses. The 16-bit wide YUV format could
be converted into two consecutive bytes
(byte-serialized), like a 01 or CCIR-656 data
stream. This approach would require memory
with double the speed.
A similar saving of memory devices can be
achieved by writing the two fields of an
interlaced source into a single FBB, one after
the other. They can be read again for
interlaced display in the same sequence. This
approach is supported as an option by the
OTV7194/96 demo board.
It is obvious that then only 85% of a regular
NTSC-SQP field or frame will fit into the given
memory space. But this conflict can be
resolved either by "cropping" only the
interesting area of the field, i.e., throwing
peripheral information away, or by
"squeezing" the picture content into fewer
pixels, i.e., scaling somewhat down. Both
methods can be combined and are supported
by the scaling function of the SAA7194/96.
Programming of source size determines the
cropping function. Destination size, relative to
source size, determines the scaling factor.
Both source and destination size can be
defined independently in horizontal and
vertical dimensions.
The memory control function of the
OTV7194/96 demo board is capable of
demonstrating various methods of optimal
memory usage and minimum control effort for
different application requirements. Because
the demo board combines various
approaches in the same hardware, the
circuitry itself may show a certain amount of
overhead. The various algorithms are
selectable via 12C programming. As the logic
is embedded in PlOs, the circuitry offers a
multitude of options (by re-programming the
PlOs).
The following description will focus on the
core functionality.
Functional Description and
Partitioning
output port VRO and the frame buffer. The
PlO PlC42VA12 named WSYNCB works as
clock divider, clock driver, and timing circuit,
and takes care of the interface logic to serve
the FIFO output mode of the SM7194/96.
But it can also be switched to operate for
transparent mode.
For the FIFO mode, the input Signals HFl
and INCADR are used, and a burst of 8
VClK cycles is provided. For the transparent
mode, the input signals pxa, HRF, and SVS
are used. In both operation modes a unified
set of control Signals is sent to the secor'ld
PlO. These control signals are closely
related to the chosen frame buffer control
circuit. The signals are:
- GATE gate Signal valid data at VRO-port
=
- EOl end-of-line flag, to insert an
end-of-line marker
- EOF end-of-field flag, to insert an
end-of-field marker. If both flags (EOl and
EO F) occur together, an end-of-frame is
signaled to reset the write address pOinter
- FBBIO field buffer bank 10, to control into
which frame buffer bank the actual data
needs to be written.
The second PlO PMl2552, which is named
WPATH, is used mainly as a huge data bus
multiplexer. The data streams for YUV format
and RGB format are mapped into the frame
buffer in such a way that its output busses
can be used directly by the SM7199, which
can accept YUV as well as RGB formats. A
third data bus is provided for the Red-signal,
necessary for the 24-bit RGB format.
WPATH further inserts the marker codes for
EOl, EOF, and ALPHA into the data stream.
It also generates the delay adjusted write
enable (WE1 and WE2) and write pointer
reset (RSTR) Signals for the frame buffer.
For the details of the PlO programming, refer
to the listings in the appendix. The various
operation modes of the write control logic are
programmable via 12C, and the serial-toparallel converter IC PCF8574 at position
U20 with 12C device slave address 42 hex.
Frame Buffer
Read Interface, Window
The frame buffer memory block consists of
12 FRAM les. The 24~bit RGB format with
interlaced signal requires that capacity. A
straight 16-bit wide YUV frame buffer
requires only 8 FRAMs. With some
restrictions in .available picture size, a set of
only 4 FRAMs is needed. To support only
smaller picture sizes, e.g., CIF-format, the
application requires just 2 FRAM ICs.
The schematic sheet WINOOW.SCH shows
the read control logic. By means of two a-bit
words the horizontal and vertical start points
of display window are defined, and present
the scaled picture. If the display timing is
synchronized to the expansion port, this
signal can be chosen as background signal.
In case the display (output) timing is
determined by the SAA7199 digital encoder
in master mode operation, then an artificial
color bar test pattern is used as background
signal. The combined signal is fed to the
digital encoder and to two OACs for
Write Interface
The schematic sheet WRITE.SCH shows the
interface between the SAA7194/96 scaler
May 16,1993
2-105
YUV-conversion (SAA7165) and
RGB-conversion (SAA7186), and is also
brought to a connector (JP7). It can also be
multiplexed via this connector with an
external signal by means of the MUTE control
signal.
The Pl22V10 PLO, named REAOClK, is
mainly the function of a signal source selector
and clock driver. The two PMl2552 PlOs
share the task to define the horizontal and
vertical position (start point) of the window.
REAOV performs a vertical counter, counting
in half lines. The vertical window offset is
defined by VOS[B .. 1] via PCF8574 at position
U34 with 12C device slave address 40 hex.
The vertical starting trigger is sent from
REAOV to READH in the form of the auxiliary
signal FS-GO. FS-GO is a kind of delayed
field-I 0 signal, changing its state in that line
where the window should start.
REAOH performs ahorizontal pixel count.
The horizontal window offset is defined by
HOS[8 .. 1] via PCF8574 at position U35 with
12C device slave address 41 hex. When both
horizontal and vertical enabling signals are
true, REAOH will start reading from the frame
buffer. The incoming data stream is checked
for the relevant marker codes. If an
end-of-line or end-of-field is detected, the
read process is stopped until the next
horizontal or vertical enabling signal,
respectively. As the FS-GO signal carries the
odd/even field 10, REAOHB can decide from
which field buffer bank to read (RE1 or RE2).
The horizontal counter is also used to
generate the auxiliary signal HS2RO, to be
sent to REAOV. HS2RO is a half-line
indication Signal, staying lOW for the first
half line, and then HIGH for the second half
line. This enables REAOV to count vertically
in half lines. Comparing the vertical sync
edges of VSO with the state of HS2RO
defines the output 10, i.e., display field 10,
and when to reset the read address pOinter.
The vertical counter in REAOV is also used
to generate a luminance and color test
pattem as baCkground signal. Further, the
video overlay control signals from the MTV
microcontroller can be used to add .
foreground signals.
For the details of the PlO programming, refer
to the listings in the appendix. The different
operation modes of the read control logic are
selectable via 12C and the serial-to-parallel
converter IC PCF8574 at position U40 with
12C device slave address 43 hex.
Implementation, control logic
The listings of the programs of the PlOs as
given in the appendix contain extensive
comments to improve the understanding of
the logic equations and statements. A few
Philips Semiconductors Video Products
\ i!
DTV7194/96
Desktop'video demo board
explanations regarding the construction of the
state machines are given in this section.
WSYNC
The main state. machine in WSYNC handles
the interface with the scaler output of the
SAA7194/96 in FIFO mode. The IDLE state is
the state after regular VClK-burst .
transmission, waiting for further HFl, or an
INCADR=lowstimuli, to.enterthe INCHOT
state. INeHOT has two exits.
Combining INCADR-Iow with HFl-high
signals the end of a line and generates an
EOl-fiag. But the LlNEND state can,not
return to IDLE, otherwise it would be
re-triggered by a second line-increment pulse
combination, and issue a second EOL. The
memory read control side would be
mis-triggered by this. Therefore, the LlNEND
state is extended by lWAIT, and can toggle
between these two states without action, in
order to be insensitive in the case of a
second line-increment pulse. sequence. A
regular HFl during lWAIT starts the normal
VClK bursts.
The second exit of INCHOT is the return to
neutral HFl-INCADR combination, which
signals the vertical end of processing, and
issues an EOF-flag~ In this VERTEND state a
line-increment condition may occur to signal
the begin of an oddfield. Then EOl~EOF
double flag is issued to indicate Field 10 reset
and Frame Buffer Bank pOinter reset.
The state machine for the transparent mode
is somewhat simpler. it is built to generate the
same EOl and EOF flags.
WPATH
WPATH is mainly a data bus multiplexer. The
control signals need to be registered to be
synchronous to data. WPATH sorts out the
FI FO fill pixels, inserts the alpha marker and
EOl and EOF markers. The reset of the write
address pointer is,delayed another clock
cycle to avoid conflict with'a last write of EOF.
READCLK
In this programming, READClK is used
mainly for clock selection and as clock driver.
It also route~ the horizontal and vertical sync
signals depending on who the timing master
is.
READV
The main function olREADV is the,vertical
counter, which is re-triggered every field by
VSEN,C; the phase of verti,cal sync relative to
the halfline signakHS2RD determines
whether the followig field is treated as an odd
or even field. The equal comparison with
VOS resets the read address pointer with
RSTR. The following state, VWB1,
represents the vertical window start for
READH, by providing FSGO.
May 16,1993
Application Note
The vertical states distinguish an idle range.
above. and below·the line, where the window
start'is defined~ (This may be used to issue
different background signals, which is not
implemented here).
AGB information (that is, they are
synchronous). Brightness, saturation, and
contrast control may be affected via the 12C
bus. Also, peak white and color balance may
be controlled via 12C;
READV also generates VSl, a 10-line long
vertical blanking signal to support the
generation on the sandcastle pulse sequence
for the TDA4,686.
The TDA4686 uses a multi-level pulse to
control certain blanking and timing
parameters, called a sandcastle pulse.
Because this pulse is generally derived from
the sync signals, it is necessary to account
for the 44 clock pipeline delay introduced by
the SAA7165 when generating ,this pulse so
that the pulse has the proper positional
relation with the output video from the
SAA7165. This is achieved by the PlD
"castl".
READH
READH has an horizontal. counter. It starts
the programmable (HOS) horizontal window
and also generates the half line reference
signal HS2RD. The horizontal state machine
is triggered by the window start condition. and
the end-of-line and/orend-of-field marker in
the data stream. The state machine has to
work around the signal delays between
enabling a read cycle at the FRAMs, and
placing valid data on the output bus. In the
FIRST state, the marker decoding logic will
not see valid data, but the tristate signal of
the FAAMs. In the LASn (and WBlK1)
state, the reading from the FAAMs has
already stopped, but there may be the next
marker in the signal path pipe line. If this pixel
was not a marker, it was a real pixel, I.e., the
first pixel of the next line. This pixel is lost for
display.
DIGITAL ENCODER SAA7199B
The backend circuitry with the digital NTSt
and PAL encoder is id,entical to the backend
processing of the DTV7199 demo board. For,
a detailed description please refer to the
application note "DTV7199 Digital Television
Demonstration System," p. 2-72.
VIDEO DACS AND MATRIX
For conversion of the digital YUV data stream
to analog AGB,the SAA7165 video DAC is
used to convert the data ,stream to analog
YUV, and the TDA4686 AGB matrix
combination IC is used to convert the analog
YUVinto analog AGB. with control over
brightness, saturation, and contrast.
The SAA71.65 (VEDA2) filters and
demultiplexes the UV data and positions this
chroma data with respect to the proper
luminance samille andpeiforms the 0 to A
conversion. In addition, software controlled
aperture correctio.n and color transient
improvement of the video may be performed
to enhance picture quality.
The TDA4686 receives this analog YUV
signal,reclamps it and convertsitto AGBvia
an analog matrix .. Two additional AGB
Signals maybe switched into this path,
assuming that they are congruent to the main
2-106
Additional circuitry at the output is used to
produce proper DC and drive levels to drive
75n loads.
A more detailed description of this analog
backend module is given in the application
note titled "Digital Video Evaluation Board"
(also inthis chapter, p. 2-171); along with
register programming for these two devices.
INTERLACED VIDEO SIGNALS
The broadcast television standards-and the
related camera standards--'-are all interlaced.
There are two fields (field rate 50Hz or 60Hz),
whose scan lines are .interleaved to each
other. The second field scans its lines right in
between the lines of the first field, but a
moment-i.e., a period of the field rate-later.
Both fields together form a frame. The
line-to-field scan. interlacing method was
developed to balance achievable vertical
resolution with motion resolution and required
transmission bandwidth. For mainly sUltic
pictures and scenes, a high vertical
resolution can be achieved by counting the
information of two fields as one frame. For
high motion video pictures, a time resolution
of 50Hz or 60Hz is achieved, which is .
superior to the 24Hz of cinema film.
If both input and output of the frame buffer
memory is structured in an interlaced
manner, the situation is rather obvious. ThiS
is the case if the SAA7194/96 decodes a
standard television signal and the SAA7199
encbdes a standard television Signal. We
have to take care that the lines of the second
field get displayed inbei\veen. thE! two lines of
the first field,as they were 'scanned in the
first place. In a straightforward way, the two
fields are written into1Wo memory banks, and
also read from them in the right s~quence
and phase (i.e,. starting the lirie counting).
In the case that input and output field rates
are not identical, two memory banks are
clearly insufficient toenSlJre that field two is
always and only read after the correlated
Application Note
Philips Semiconductors Video Products
Desktop video demo board
preceding field one. An incorrect field
sequence would generate motion disrupting
artifacts Oumping back and forth).
If the vertical scan speed, i.e., time from line
to line, is not the same at the write and read
side of the memory, so called ''tearing'' can
occur. This is the case if the signal source is
generated by scaling, for example. The write
and read pOinters in the memory address
space are crossing each other. The results
are that information displayed as one field are
originated by separate fields.
To avoid these two artifacts, memory with a
capacity to store four fields and dedicated
control would be necessary. The DTV7194/96
demo board, however, solves this problem
with only two memory banks (field stores) by
exchanging odd and even fields. If input and
output are synchronous in vertical, it is
ensured that reading and writing happens on
different field buffer banks, and do never
cross. For 1:1 mapping (i.e., no scaling) the
output picture appears one line lower thant
the original.
If the input of the frame buffer memory is
non-interlaced material, and the output of the
memory needs to be interlaced, e.g., for the
DENC, then "re-interlacing" has to take place.
Non-interlaced video can get fed in via the
expansion port from video decompression or
artificial sources (graphics generation), or the
scaling function itself can generate it by
May 16,1993
DTV7194/96
programming it to one-field-only operation
(odd field only, even field only).
''Ae-interlacing" can be achieved by proper
modification either of the write or read control
of the frame buffer. The alternating lines of a
non-interlaced field can be written in a
line-toggling fashion into both memory banks,
but read in a field toggling manner. This kind
of re-interlacing is comparable-also
comparable in results-to film-to-TV
conversion.
If the input of the frame buffer memory is
interlaced material, and the output of the
memory needs to be non-interlaced, then
"de-interlacing" has to take place.
Non-interlaced frame buffer output may be
required for display on a computer monitor, or
to drive a video printer, or to feed a
compression engine. De-interlacing can be
achieved by proper modification either of the
write or read control of the frame buffer. The
alternating fields of an interlaced frame can
be written in a field-toggling fashion into both
memory banks, but read in a line toggling
manner. De-interlacing in that way works well
for static pictures, but creates artifacts during
motion. DTV7194/96 has no provisions,
regarding memory control, against these
artifacts. The more preferable approach is to
select the one-field-only operation for the
scaling function in the SAA7194/96.
If both the input and output of the frame
buffer are non-interlaced data streams, the
2-107
situation is transparent; one field is the same
as one frame. The field toggling write mode
would just write into one memory bank,
depending on actual phase of vertical to
horizontal sync. The read control has no
chance-by any means-to know from where
to read. Therefore, for this case, a line
toggling mode on both sides is appropriate.
This approach also allows storage of larger
frames, e.g., 800 pixels by 600 lines, with the
given board architecture, as it splits a frame
into two 'interlaced' memory banks. But the
demo board is not made to clock with real
VGA clock rates.
The FBB pointing sequence as part of the
memory control can ''field-toggle'' or
"line-toggle" between the two memory banks.
This toggle mode is selectable via 12C, both
for writing and reading, and independently of
each other. By that, interlaced and
non-interlaced video signals can be handled
and converted into each other.
SUMMARY
Many other data output formats and memory
architectures are possible using the
SAA7194/96 and associated chips. This
application note touches on just a subset of
possibilities to suggest an approach that uses
minimum memory and memory control
devices to implement a system.
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PHILIPS SEMICONDUCTORS
811 E.
ARQUES AVE.
....L
SUNNYVALE. CA 94099
WAR"1UTH .. KNIESS. ELLIS
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DTV7194:
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06
05
04
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C~20 ~f2 C~33
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3
5
7
9
4
6
9
10
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13 14
15 16
17 18
1920
2122
2324
2526
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4u
3132
3334
3536
3738
3940
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7
10
11 12
13 14
9
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VR01B
VR017
VR016
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VR012
VR011
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VR09
VR08
VR07
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CHR7
CHR6
CHR5
CHR4
CHR3
CHR2
0
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VROO
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VR030
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YUV9
YUV9
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11 12
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2122
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2526
2729
2930
- 31 32
33 34
3536
3739
3940
pin 51 is ·not u ... d ..
pin SO is not u •• d ..
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811 E. ARQUES AVE SUNNYVALE CA..
SUNNYVALE CA i 94088
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811 E. ARQUES AVE.
SUNNYVALE CA. 94088
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1013
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103
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101
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PHILIPS SEMICONDUCTORS
811 E. ARQUES AVE.
SUNNYVALE CA. 84088
WARMUT H. KHI ESS. ELLIS
GN01
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FRAME BUFFER READ CONTROL
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DIN36
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OUTPUT
LFCO
LLC
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~~~
~
H5YENC
HCL
CLKOUT
PIXCLK
CLKSEL
CLKIN
N
~
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HS-
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R82
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811 E. ARQUES AVE
SUNNYVALE CA. 94088
WARMUTH~ KNIESS. ELLIS ..
[~~~~;AL
--
......
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SCHNEIDER
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B17
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Philips Semiconductors Video Products
Application Note
Desktop video demo board
DTV7194/96
Programs of the PLDs used on DTV7194/96 board
WSD.EQN
WriteSync & Clock :
clock drivers
HFL,INCADR --> VCLK, EOL, EOF for
asynchronous FIFO mode "
PXQ, HRF, SVS --> EOL, EOF for
synchronous TRANSPARENT mode "
" WSD
=========
" PLC42VA12
" U16
CONTROL PARAMETER
/ SORT-bits
SORT7
SORT6
SORTS
SORT4
#7:
POLV, here not used
#6:
POLH, here not used
#5:
FIFOMODE :HFL and INCADR are the only (external) inputs
to the fifomode state machine
else: TRANSPARENT MODE: under trigger of SVS, HRF and pXQ
#4:
INTRL: interlaced/non-interlaced field mode
only relevant if VRO is in transparent mode
INTRL=l: FBBID is 'field toggling
issue RSTW before writing in even fields only,
(reset frame buffer write address pointer)
i.e. at the transition from odd to even field
i.e. if vertend is not 'disturbed' by 'linc'
RSTW is coded as 'eol & eof', or 'new-frame'
else: non-interlace: FBBID is line toggling
RSTW at the beginning of every field
under IIC address 42 hex
NOMENCLATURE:
FBBID : field buffer bank ID:
1
o
field buffer bank
field buffer bank
The lines of the upper field buffer bank are 'on screen' above
the corresponding lines of the lower bank.
DESC / scaler generates
data for the _upper_ bank during the _even_ (2nd) field,
data for the lower bank during the _odd_ (1st) field.
(--> extra line increment pulse at begin of odd field)
READ out of memory and line counting at the output / display
side is perfomed in such a way, that
during _odd_ field the _upper_ frame buffer bank is read,
during _even_ field the _lower_ frame buffer bank is read,
i.e. : the input odd field gets displayed as output even field,
the input even field gets displayed as output odd field.
Result:
The FrameBuffer represents a one-:-field pipeline delay.
Benefit:
No tearing at memory pointer cross-over.
@PINLIST
" pin#:
to go into PLC42VA12
" 1: LLC2 or LLCB from expansion port
CLOCKIN
VCLK
CLOCK
CLKE
CLKF
o
HFL
INCADR
PXQ
HRF
I
I
I
I
SVS
I
"18:
"17:
"16:
"15:
B
o
o
May 16,1993
;
;
;
;
;
clock
CLKAB
clock
clock
at VRO-port, DESC-scaler output
at VRO-port-to-PML interface, PML-side
at memory wJ:".ite interface, Y-G-channel
at memory write interface, RB-channel
second clock driver for FRAM memory bank "
fifo half full flag
increment address, for line and field end
pixel qualifier in transparent data stream
horizontal reference signal
in transparent-data-stream "
2
:
vertical sync, referring to scaler output
"
"
"
"
"
5:
6:
4:
3:
2-.118
Application Note
Philips Semiconductors Video Products
Desktop video demo board
GATE
EOLPIN
EOFPIN
0
0
0
FBBID
o
VMUX
0;
;
;
VCLKGATE B;
SORT4
I;
SORTS
DTV7194/96
"20: valid pixel at VRO = in front of WPATHPMB
"21: end of line flag, to WPATHPML
"22: end of field flag, to WPATHPML
" both EOL & EOF together:
reset of FBBID write pointer for odd=l.field "
"23: Frame Buffer Bank ID: where to write to
FBBIB = 1, i.e. 'odd field' into bank 1
FBBIB = 0, i.e. 'even field' into bank 2
" for re-interlacing of a non-interlaced source,
write in line-toggling manner into both banks,
if there are two banks (sortS = 0)
"19: VMUX control for SAA7l94/96 fifomode to 16 bit
here used as RSTW monitor pin
"14: reserved, to 'time-adjust' VCLK burst-gate
" can not used externally "
SORTx under I2C bus address 44 hex
"7: Source Field Mode:
1
Interlaced
o
non-interlaced
" 8: Scaler Output Interface Mode, VRO operation
1
FIFO-mode
o
transparent-mode
@GROUPS
@TRUTHTABLE
@LOGIC EQUATIONS
SORTS * SORT4
/SORTS
/SORTS * /SORT4
FIFOMODE
INTRL
FINT
VCLKGATE
CLOCKS === "
" intermediate internal clock •
CLOCKIN
1
1 ;
1 ;
INTCLK
INTCLK
INTCLK
INTCLK
CLOCK.OE
CLKE .OE
CLKF .OE
CLOCK
CLKE
CLKF
" === MODES OF OPERATION === "
" Scaler Output Interface Mode "
" interlace / non-interlace "
" forced interlaced, FID-toggle"
• pixel clock at VRO & WPATH-in "
• pix-elk for WPATH-out & FRAM
• just a second driver for FRAMs'
" === CONTROL ===
• continuous clock
"OR burst of clocks
" to 'adjust' timing
" clock for VRO
" valid FIFO data at VRO
FIFOMODE * Q3 * (Q2 + Ql + QO)
" countl ..
+ FIFOMODE * /Q3 * Q2 * /Ql * /QO
count8
+ /FIFOMODE * PXQ
" valid PXQ data at VRO
EOL
EOF ;
/FIFOMODE
+
FIFOMODE * Q3
VCLKGATE.OE
1 ;
VCLK
INTCLK * VCLKGATE
GATE
EOLPIN
EOFPIN
= 0
VMUX
test
eol * eof
rstwtest .d
test
rstwtest .clk
CLOCK
vrnux
test * /rstwtest
" reserved
" for monitor purpose only
" for simulation only
" for simulation only
" leading edge
" ===
Q[O .. 3] .CLK
Q[O .. 3] .RST
Q [0 .. 3] . SET
May 16,1993
REGISTERS
"
"
"
"
"
"
"
"
"
"
"
"
=== "
CLOCK
1
1
" state machine register "
2-119
Philips Semiconductors Video Products
Application Note
Desktop video demo board
FBBID
FBBID
FBBID
FBBID
FBBID
FID
.CLK
.J
.K
.SET
.RST
EOL
EOL
EOL
.CLK
.SET
.RST
CLOCK
1
1
EOF'
EOF
EOF
.CLK
.SET
.RST
CLOCK
1
DTV7194/96
" Frame Buffer Bank ID, "
CLOCK
FBBIDJ
FBBIDK
1
1
FBBID
where to write to "
" i f there is interlaced source "
@INPUT VECTORS
H _____________ H
-------------
[ FIFOMODE, INCADR,HFL,
EOL, EOF,
SVS,HRF,PXQ, INTRL,FINT,FID ]
" for _FIFO_ mode "
" default input, no action"
" regular HFL, start burst "
" incadr-up
field incr."
hfl-up --> line incr. "
NEUTRAL
HFULL
INCLO
LINC
" for _TRANSPARENT_ mode"
" valid pixel, set LA
" horizontal reference "
"forced interlaced, fid=even"
"forced interlaced, fid=odd "
" horizontal reference "
" horizontal blanking
" horizontal blanking
" end of vertical sync "
"forced interlaced, fid=even"
"forced interlaced, fid=odd "
PX
HREFI
HREFFE
HREFFO
HREFN
BLANK I
BLANKN
VEBLNK
VEBLNE
VEBLNO
VS
" vertical sync
WAIT
~ulse
" aux. wait cycle->RSTW "
BLIWAIT
BLNWAIT
o
TM
FM
o
-0-0-
1-
1-
1-0--
B
B
B
B
;
;
"escape from fifomode states"
"escape from transp.m states"
" BOTH modes use the same
output flags/vector "
@OUTPUT VECTORS
"--------------"
--------------
EOLINE
EOFIELD
NEWFRAME
FLAGS OFF
[EOL, EOF] JKFFSR
1 0 B;
0 1 B;
1
B;
B;
0
set EOL "
set EOF "
set EOL & EOF,
RSTW"
reset EOL, EOF "
FBBTOG
UPPERB
LOWERB
FBBIDJ, FBBIDK
lIB;
lOB;
0 1 B;
toggle FBBID
pointer to upper fbb "
pointer to lower fbb "
@STATE VECTORS
" two state machines on a single
4-bit vector set"
Q3,Q2,Q1,QO
IDLE
LA
FA
VP
May 16,1993
0
0
0
0
1
1
0
B
B ;
B ;
B ;
"for ===transparent=== mode"
" idle
" this Line is/was Active "
" this Field is/was Active "
" vertical pause & reset
2-120
Philips Semiconductors Video Products
Application Note
Desktop video demo board
INC HOT
LINEND
VERTEND
COUNTO
COUNT 1
COUNT 2
COUNT3
COUNT4
COUNTS
COUNT 6
COUNT 7
COUNT8
0
0
1
1
1
" for --- FIFO === mode "
" incadr is low (hot to act)"
" hfl at inc-hot, issue eol "
B ;
B ;
B ;
1
1
0
0
0
1
1
1
0
1
0
DTV7194/96
" after field increment
B
B
B
B
B
B ;
B
B
B
" 8 additional states for"
fifo BURST count
count through the
VCLK burst
" Q3 to :
" enable VCLK for VROport"
" generate GATE for WPATH"
last cycle for gate "
@TRANSITIONS
"============"
" CASE-statements for
WHILE [IDLE)
CASE
[PX) "transparent mode"
.. [LA)
[HFULL)
[COUNTO)
[INCLO)
[INCHOT)
WHILE [INCHOT)
CASE
[LINC)
[LINEND)
[NEUTRAL)
.. [VERTEND)
[TM)
.. [IDLE)
WHILE [LINEND)
CASE
[NEUTRAL)
WITH [FBBTOG)
[IDLE)
[TM)
[IDLE)
WHILE [VERTEND)
CASE
[HFULL)
[VERTEND)
[WAIT]
WITH [UPPERB]
[IDLE]
[LINC]
WITH [UPPERB]
[LINEND]
[TM]
[IDLE]
..
..
===
FIFO
===
WITH [FLAGSOFF)
WITH [FLAGSOFF)
ENDCASE
WITH [EOLINE)
WITH [EOFIELD)
ENDCASE
ENDCASE
WITH [NEWFRAME]
..
WHILE
WHILE
WHILE
WHILE
WHILE
WHILE
WHILE
WHILE
WHILE
[COUNTO]
[COUNT1]
[COUNT2)
[COUNT3]
[COUNT4]
[COUNTS]
[COUNT6]
[COUNT7]
[COUNT8]
CASE
CASE
CASE
CASE
CASE
CASE
CASE
CASE
CASE
[]
[]
[)
[]
[)
[]
[]
[]
..
..
..
..
[]
[COUNT1]
[COUNT2]
[COUNT3]
[COUNT4]
[COUNTS]
[COUNT6]
[COUNT7]
[COUNT8]
[IDLE]
" IF-statements for
WHILE [LA]
IF
[BLANKI]
[BLIWAIT]
IF
IF
[BLANKN]
IF
[BLNWAIT)
IF
[VS]
[FM]
IF
WHILE [FA]
[PX]
IF
IF
[VS)
IF
[FM)
WHILE [VP)
IF
[HREFI)
IF
[HREFFE)
IF
[HREFFO)
IF
[HREFN)
IF
[VEBLNK]
[VEBLNE)
IF
IF
[VEBLNO)
IF
[FM)
May 16,1993
WITH [FBBTOG)
WITH
WITH
WITH
WITH
WITH
WITH
WITH
[LOWERB)
[FBBTOG)
[LOWERB)
[UPPERB)
[UPPERB]
[FBBTOG]
[UPPERB]
mode"
ENDCASE
ENDCASE
ENDCASE
ENDCASE
ENDCASE
ENDCASE
ENDCASE
ENDCASE
ENDCASE
ENDCASE
===
TRANSPARENT
THEN
THEN
THEN
THEN
THEN
THEN
[LA]
[FA]
[LA]
[FA)
[VP)
[IDLE]
THEN
THEN
THEN
[LA]
[VP)
[IDLE)
THEN
THEN
THEN
THEN
THEN
THEN
THEN
THEN
[IDLE)
[IDLE]
[IDLE)
[IDLE)
[IDLE]
[IDLE]
[IDLE]
[IDLE]
===
mode "
WITH [EOLINE]
WITH [EOLINE]
WITH [EOFIELD)
WITH [FLAGSOFF]
WITH [EOFIELD)
WITH [NEWFRAMEj
WITH [NEWFRAME)
WITH [NEWFRAME)
2-121
Philips Semigonductors Video Products
Application Note
Desktop video demo board
DTV7194/96
WPD.EQN
DATA PATH interface VRO to frame buffer "
mUltiplex for YUV and RGB bus formats
marking data with eo1, eof, alpha=key
frame buffer write enable and reset
" WPD
H
R
PML2552
U17
CONTROL, in byte 'SORT', under IIC address 44 hex
SORT2
SaRTI
SaRTO
I
I
I
RGB
1
1
VRO data format
RGB 15 bit, 5-5-5
RGB 24 bit
YUV (16 bit)
1
°
°
FBN : number of field buffer banks in use:
l o n e field buffer bank only
(but do write-enable to both banks in parallel)
two field buffer banks
(before RSTW write eof-mark into both banks
i.e. req. for 're-interlacing'
non-interlaced into interlaced
@PINLIST
CLKA
CLKB
CLKE1
CLKE2
"pin-#"
36
24
" 65
56
I;
H
I
I
I;
R
clock
clock
clock
clock
R
HIBYT[7 .. 0]
for
for
for
for
input register
input register
output register (main=GI)
output register (side=BI)
in case of YUV-16
" Y
RED
in case of RGB-24
in case of YUV-16
UV
" GREEN in case of RGB-24
not used in YUV-16 format
" BLUE in case of RGB-24
8
alpha-bit,
color key
H
MIBYT [7 .. 0]
I;
H
LOBYT[7 .. 0]
R
ALPHA
GI [7 .. 0]
BI [7 •. 0]
GATEPIN
EOLPIN
EOFPIN
FBBIDIN I
RSTW
WEI
WE2
STILL
SORTO
GI - channel to FRAMs, also serial
BI - channel to FRAMs
0
0
o
°
°
" 51
" 52
" 53
" 54
gate over VCLK-bursts,i.e.valid pixels"
end-of-line (frame) marker
end-of-field/frame marker
frame buffer bank ID, to write to
" 46
" 47
" 48
reset of frame buffer write pointer
write enable for frame buffer bank 1
write enable for frame buffer bank 2
" 50
" 23
STILL
: freeze picture, no write
sort1=1 & sortO=l : RGB15
sort1=1 & sortO=O : RGB24
data format select:
1
RGB 24 bit (15 bit)
YUV 16 bit
FEN, number of field buffer banks used
l o n e field buffer bank only
two field buffer banks
SaRTI
I
;
" 22
SORT2
I
;
H
20
°
°
@GROUPS
FILLV
KEYMARK
EOLMARK
EOFMARK
FBBEMARK =
0,0,0,0, 0,0,0,1
0,0,0,0, 0,0,0,1
0,0,0,0,0,0,0,0
1,1,1,1, 1,1,1,1
1,1,1,1, 1,1,1,1
" fifo fill pixel value H
"transparent ALPHA pixel"
" end of line marker
" end of field marker
" field buffer bank end "
@TRUTHTABLE
May 16,1993
2-122
Philips Semiconductors Video Products
Application Note
Desktop video demo board
@LOGIC EQUATIONS
FB2
ISORT2
FBI
SORT2
YUV
ISORT1
RGB24
RGB15
RGB
CLK
SORT1
SORT1
SORT1
CLKB ;
ID[31. .24]
ID[23 .. 16]
ID[15 .. 8]
ID[15 .. 8]
KEY
KEY
.ID
.ID
.D
.SET
.SET
.D
ID[31. .24]
ID[23 .. 16]
ID[15 .. 8]
KEY
.CLK
.CLK
.CLK
.CLK
DTV7194/96
• write into both FBs in parallel
n
* ISORTO
SORTO
INPUT REGISTER
FBBIDN
EOL1
EOF1
EOL2
EOF2
GATE
.D
.D
.D
.D
.D
.D
FBBIDN
EOL1
EOF1
EOL2
EOF2
GATE
WEI
WE2
RSTW
.CLK
.CLK
.CLK
.CLK
.CLK
.CLK
.CLK
.CLK
.CLK
HIBYT[7 .. 0]
MIBYT[7 .. 0]
LOBYT [7 .. 0]
1
May 16,1993
8 of 10 JKPR552 with •
common set and clock n
CLKA
CLKB
CLK
CLK
IFBBIDIN
EOLPIN
EOFPIN
EOL1
EOF1
GATEPIN
n
to find leading edges
n
--__
n
10 *
n
declarations ___ "
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
FBBIDN .RST
IFB1 ;
EOL1
.RST
1
EOF1
.RST
1
.RST
EOL2
1
EOF2
.RST
GATE
.RST
.RST
WEI
IFREEZE
.RST
WE2
IFREEZE
RSTW
.RST
1
FREEZE .CLK
RSTW
FREEZE .RST
1
FREEZE.D = ISTILL
EOLFLG
EOFFLG
FBBEFLG
RSTWFLG
FLAGS
FILLPIX
BOTG8
n
ALPHA
n
JKCL552 "
.RST is active LOW
n
• update with next frame"
" 'still' is active low"
"'freeze' is active high"
" ==== FLAGS DECODING & RESET CONTROL
EOL1 * IEOF1 * IEOL2
" eol edge n
IEOLl * EOF1
* IEOF2
" eof edge "
" both 1st"
(EOLl * EOF1) * I(EOL2 * EOF2)
(EOL1 * EOF1) *
(EOL2 * EOF2)
" both lIst"
EOLFLG + EOFFLG + FBBEFLG
ID[31 .. 24]
01H
ID[23 .. 17] == OOH
n catch and limit
green-undershoot"
2-123
Application Note
Philips Semiconductors Video Products
DTV7194/96
Desktop video demo board
/KEY * /FLAGS
GIR[7 .. 3).00
+ /KEY * /FLAGS
+ /KEY * /FLAGS
+ KEY * /FLAGS
+
EOLFLG
EOFFLG
FBBEFLG *
/KEY * /FLAGS
+ /KEY * /FLAGS
+ /KEY * /FLAGS
+ /KEY * /FLAGS
KEY * /FLAGS
EOLFLG
EOFFLG
FBBEFLG *
*
*
*
*
+
GIR[2 .. 0) .00
BI [7 .. 3) .OD
YUV
RGB24
RGB15
YUV
RGB24
RGB15
+
BI[2 .. 0).OD
*
*
*
*
*
" === MUX & MASK & MARK
YUV
* ID[3l. .27)
RGB24 * ,ID[23 .. 19)
RGB15 * ID[25 .. 21)
OOH
" KEYMARK "
" EOLMARK "
OOH
1FH
" EOFMARK "
1FH
" FBBEMARK"
* ID[26 .. 24)
YUV
RGB24 * ID[18 .. 16)
*/BOTG8
RGB24 * 2H
* BOTG8
RGB15 * 2H
" KEYMARK "
1H
OH
" EOLMARK "
7H
" EOFMARK "
7H
" FBBEMARK"
* ID[23 .. 19)
* ID[15 .. 11)
* ID[20 .. 16)
*
ID[18 .. 16)
* ID[10 .. 8]
* 2H
OUTPUT REGISTER
GIR[7 .. 0)
BI [7 .. 0]
GI [7 .. 0]
GI [7 .. 0] .
RSTW
WE1
.CLK
.CLK
OE
D
D
+
+
+
+
WE2
. D
+
+
+
+
CLKE1 ;
CLKE2 ;
GIR[7 .. 0)
WE1 + WE2
RSTWFLG ;
GATE * YUV
GATE * RGB
EOLFLG
EOFFLG
FBBEFLG
GATE * YUV
GATE * RGB
EOLFLG
EOFFLG
FBBEFLG
*
*
*
*
(
(
(
(
/FBBIDN
/FBBIDN
/FBBIDN
/FBBIDN
"+
"+
"+
"+
*
*
*
*
(
(
(
FBBIDN
FBBIDN
FBBIDN
FBBIDN
+
+
+
+
(
FB1"
FB1"
FB1"
FB1"
* /FILLPIX
FB1
FB1
FB1
FBI
*
/FILLPIX
@INPUT VECTORS
@OUTPUT VECTORS
@STATE VECTORS
@TRANSITIONS
May 16,1993
2-124
'Application Note
Philips Semiconductors Video Products
Desktop video demo board
DTV7194/96
WREDD.EQN
Multipexer and register between
DESC VRO and field buffer in the
red channel: 24 bit / 15 bit
" WREDD
U18
PL22V10
CONTROL
SaRTO
1
o
@PINLIST
CLK
ID[7 .. 0)
RI [7 .. 0)
SORTO
SORT1
CLKAB
I
I
0
;
I
I
I
;
;
;
under IIC address 44 hex
RGB15 , i.e. 5 bit red
RGB24 , i.e. 8 bit red
" pin if "
1
9 .. 2
" 16 .. 23
11
15
14
13
clockf for all red channel
input from register U19
output, to memory input
to control 8/5 bit multiplex
here not in use
here not in use
here not in use
@GROUPS
@TRUTHTABLE
@LOGIC EQUATIONS
RGB24
RGB15
/SORTO
SORTO
RI [7 .. 3)
.D
RI [2 .. 0)
.D
RI [7 .. 0)
.CLK
RGB24
RGB15
RGB24
RGB15
CLK
* ID[7 .. 3)
* ID[ 6 .. 2)
* ID [2 .. 0)
2H
*
@INPUT VECTORS
@OUTPUT VECTORS
@STATE VECTORS
@TRANSITIONS
May 16,1993
2-125
Philips Semiconductors Video Products
Application Note
Desktop video demo board
DTV7194/96
RCD.EQN
" RCD = READ-CLOCK
" U4l
@PINLIST
"pin-#
select clock and sync system
clock divider, clock drivers
sync select
for PL22VlO
CLK
CLKENC
I;
PIXENC
I;
LLC2B
EXTCLK
I;
B;
4
"14
dedicated clock input for PLD = pixclk
double pixel clock from DENC-clock-out,
as selected by CLKSEL=VIEW3
pixel clock from DENC-clock-out,
as selected by CLKSEL=VIEW3
pixel clock of DESC as on eXp.port
external clock, here not used
MEMREAD
REDCLK
CLKEI
LDV
CLKMTV
0;
0;
0;
0;
0;
"22
"21
"20
"19
"18
read clock for FRAMs, luma/green channel "
read clock for FRAMs, red & blue channel "
read/pixel clock, color difference
pixel clock for output/display/DENC, LDV "
half pixel clock for MTV micro controller"
HSB
VSB
HSENC
VSENC
CBN
I;
I;
B;
B;
"17
"16
"23
horizontal sync at DESC's expansion port"
vertical sync at DESC's expansion port
horizontal sync of/for DENC, active HIGH"
vertical sync
of/for DENC, active HIGH"
CBN for DENC, inverted copy of HSENC
VIEW3
I;
VIEW7
I;
I;
0;
" VIEWx has I2C-address = 46 hex "
here not used
" clock source select, display/read-clock
@ pin CLKSEL of saa7l99b
view3 = 0 :
CLKIN = LLCB of export
view3 = 1 :
LLC from DENC-CGC
sync master select
view7
0
eXpans.Port
sync master
(make sure: view3 = 0, too)
view7
DENC = sync master
@GROUPS
@TRUTHTABLE
@LOGIC EQUATIONS
DENC
XPORT
PIXCLOCK
VIEW7
/VIEW7
" DENC is sync timing master "
" sync timing signals from eXpansion port "
XPORT * LLC2B
* PIXENC
+ DENC
MEMREAD
REDCLK
LDV
CLKEI
PIXCLOCK
PIXCLOCK
PIXCLOCK
PIXCLOCK
CLKMTV.D
CLKMTV.CLK
/CLKMTV
PIXENC
HSENC
HSENC.OE
VSENC
VSENC.OE
CBN
XPORT
XPORT
XPORT
XPORT
XPORT
+ DENC
" clock for FRAM- read interface"
" second driver
" pixel clock = LDV "
" 1/2 pixel clock for uC "
" toggle by pixclk "
*
HSB
* VSYNCB
* /HSB
* /HSENC
" blanking is active low "
@INPUT VECTORS
@OUTPUT VECTORS
@STATE VECTORS
@TRANSITIONS
May 16,1993
2-126
Application Note
Philips Semiconductors Video Products
Desktop video demo board
DTV7194/96
RVD.EQN
vertical start of display window FSGO
memory read pointer reset RSTR
background data path pass through
VCTRL check for MTV micro RGB overlay
OVL = overlay insert, maybe used as MPK "
READV
"RVD
" PML2552-35
" U37
CONTROL PARAMETER in byte VIEW, 12C-address = 46 hex
VIEW7
VIEW6
VIEW5
I
I
I
I
I
I
I
I
I
I
I
o
o
CLKA
CLKB
CLKEl
CLKE2
VIEW3
VIEW2
VIEWl
VIEWO
I
1: MTV-RGB overlay inserted in data path
(native mode if SAA7l99 is used for output)
MPK carries (RGB) tagging information for LUT
0: MTV overlay is NOT inserted in data
(native mode if DACs for RGB output is used)
but MPK carries switching information
Four modi for display sync- and data path:
Syncs from :
Background signal :
DECoder (DESC, XPT)
eXPansionPorT/2 in/out
DECoder (DESC, XPT)
count- pattern, INTRL
ENCoder, gl/master
count pattern, INTRL
VGA:
ENCoder double clock generated pattern
double H+V-rate,
(every 2nd VS suppressed)
1
@PINLIST
VIEW4
"pin-nr"
I
I
"
"
"
"
;
;
VOS[7 .. 0]
BY [7 .. 0)
BUV[7 .. 1]
I
I
I
YW [7 .. 0]
UVW[7 .. 0]
0
0
"
"
"
"
"
"
;
;
;
VSENC
HS2RD
B
I
RSTR
OVL
VSL
FSGO
0
"48
0
0
0
"50
"51
"53
KEY
I
;
"54
VIEW4
VIEW5
I
;
"23
" 22
VIEW6
I
;
" 20
VCTRL
MTVG
MTVB
I
I
;
;
"52
"45
;
;
pixel-clock,
pixel clock,
pixel clock,
pixel clock,
36
24
65
56
"46
" 47
"
"
Vertical OffSet of inserted window
background luminance channel, Y
background chrominance channel, UV
background = signal at expansion port "
luminance output, respectively Green
colour difference output, resp. Blue
VS at ENC, vertical sync, active HI
half line pulse from READH-pld
" l.half-line LOW, 2nd half of line HIGH"
reset read pointer for both FRAM banks"
insert MTV-overlay, switches RGB-yuv
extented vertical sync for sandcastle "
indicates vertical start of window
n
INTRL : FSGO takes FID
at VWBegin,
NINTL : FSGO = line pulse at VWBegin n
active (LOW) during inserted picture
to control data output enable
" also used as KEY, if ENC in genlock
view4
1 : code OVL
background signal:
view5 = 0:
XPORT 1/2 intensity
view5 = 1 :
color pattern, or VGA
timing master (sync) :
view6
0
DESC-eXpansion-Port,
i.e. ENC is slave
view6
ENC is sync master
( view6 = 1: VGA. mode) "
=
n
May 16, 1993
all clocks
same as LDV,
for display,
i.e. output
RGB overlay from micro controller->MPK"
green overlay from MTV
blue overlay from MTV
sacrifice LSB of background color
2-127
Application Note
Philips Semiconductors Video Products
Desktop video demo board
DTV7194/96
@GROUPS
@TRUTHTABLE
H
MODI truth table ( as in equation: === MODE CONTROL TABLE ===H
DECS, ENCS , VGA, PATTERN, OVLE, RGBONYUV )
VIEW6, VIEW5, VIEW4
100
0
1
0
000
1
0
0
o
1
0
1
o
1
1
0
0
o
o
1
0
o
1
o
0
1
o
0
o
@LOGIC EQUATIONS
XPORTB
PIP
MODE CONTROL TABLE
/PATTERN
/KEY ;
H window is active
low in order to be used @ DENC-KEY
HORIZONTAL CLOCKS
CLK
HS2 .D
CNTCLK
CLKB ;
HS2RD
= /HS2 ;
H
H
HS2
.SET
HS2
.CLK
VQ[2 .. O).SET
VQ [2 .. 0) . CLK
FSGO
.SET
FSGO
.CLK
.J
FSGO
.K
FSGO
INTRL
.SET
INTRL
.CLK
FID
.SET
.CLK
FID
VSL
. SET
VSL
.CLK
VSL
.J
VSL
.K
CPHASE .SET
CPHASE .CLK
VCTRLID .SET
VCTRL2D .SET
VCTRLID .CLK
VCTRL2D .CLK
1 ;
===
1st half line LOW, then HIGH
FULL LINE CLOCK ----
H
H
H
H === REGISTER
declarations === H
.SET guides snap to use 9 JKPR552 with
common clock and common preset H
H
edges produce half line clocks H
CLK
1 ;
H
state machine register
H
CLK
1 ;
indirect state register
H
H
CLK
FSGOJ
FSGOK
1 ;
H
auxilliary control state
H
internal control sta.te
H
vertical sync long
H
CLK
1 ;
H
CLK
1 ;
H
CLK
VSLJ
VSLK
H
CLK
1
1
CLK
CLK ;
H
H
H
u/v multiplex phase
for color pattern
H
MPK switches SAA7199 intoH
foreground RGB overlay
H === COUNT VERTICAL ===H
H.RST guides snap to use 8 JKCL552
with _individual_ clock inputs and _individual_ clear,
but asynchronous clear, which gets
'synchronized', i.e. 'gated' by VQ state machine
COUNT[7 .. 0).J
1 ;
COUNT[7 .. 0).K
=1 ;
COUNT[7 .. 0) .RST = /CNTRST
CNTCLK
COUNTO.CLK
COUNTl.CLK
/(/CNTCLK * COUNTO)
COUNT2.CLK
/(/CNTCLK * COUNTO*COUNT1)
/(/CNTCLK * COUNTO*COUNT1*COUNT2)
COUNT3.CLK
COUNT4.CLK
/(/CNTCLK * COUNTO*COUNT1*COUNT2*COUNT3)
COUNT5.CLK
/ (/CNTCLK * COUNTO*COUNT1*COUNT2*COUNT3*COUNT4) ".
COUNT6.CLK
/ (/CNTCLK * COUNTO*COUNTl *COUNT2*COUNT3*COUNT4
*COUNT5) ;
COUNT7.CLK
/(/CNTCLK * COUNTO*COUNT1*COUNT2*COUNT3*COUNT4
*COUNT5*COUNT6) ;
May 16,1993
2-128
Philips Semiconductors Video Products
Application Note
Desktop video demo board
DTV7194/96
--- VERTICAL EVENTS --VSI
VBEND
VSENC
COUNT [7 .. 0]
COUNT[7 .. 0]
VSLE
count[7 .. 0]
COUNT [7 .. 0]
"vbend
"VSLE
VWB
" VSENC from ENC "
COUNT [7 .. 0]
VERTICAL BLANKING INTERVAL--"
" about 16 lines = 10hex "
10H
VSLong for sandcastle --- "
" 10 or 10.5 lines "
OAR
07H
05H
" for simulation purposes ONLY "
7
VOS [7 .. 0]
;
VERTICAL WINDOW BEGIN
" input to state machine "
PATL7
PATL[6 .. 0]
" === COLOR TEST PATTERN
COUNT7 ,,* ( FID + /FID * HS2 )" ;
40H
PATC7
PATC [6 .. 0]
HS2 * INTRL * COUNTS
40H
IDB [7 .. 1] . ID
LUMA[5 .. 0]
LUMA6
LUMA7
IDB [7 .. 1] . CLK
BY [7 .. 1]
IDB [6 .. 1]
/IDB7
IDB7
CLKB
" luminance background
1/2 contrast
" brightness offset
" sign extension
" =======
IDA [7 .. 1] . ID
BUV[7 .. 1]
COLR[5 .. 0]
IDA[6 .. 1]
/IDA7
COLR6
COLR7
IDA7
IDA[7 .. 1] .CLK = CLKA
" color diff. background"
" ======= 1/2 saturation"
" offset binary
" sign extension
MTV RGB OVERLAY
VCTRL1D .D
VCTRL2D .D
OVLG. CLK
OVLB. CLK
OVLG. ID
OVLB. ID
BLACK [7 .. 0]
GREEN [7 .. 0]
BLUE [7 .. 0]
OVLGREEN [ 7 .. 0 ]
VCTRL ;
VCTRL1D
CLKB
CLKA
MTVG
MTVB
10H
B4H
B4H
OVLG *
+ /OVLG *
OVLBLUE[7 .. 0]
OVLB *
+ /OVLB *
OVLAY
VCTRL1D * OVLE
[7 .. 0] .OD
/OVLAY *
UV[7 .. 0] .OD
OVLAY *
/OVLAY *
Y
OVLAY *
OVL
OUTABLE
GREEN[7 .. 0]
BLACK[7 .. 0]
BLUE [7 .. 0]
BLACK[7 .. 0]
YW [7 .. 0]
UVW[7 •. 0]
YW [7 •. 0] .OE
UVW [7 •. 0] .OE
100% saturation 75%
"dec hex
dec hex"
16
10
16
10·
• 235
EB
180
B4 "
EB
180
" 235
B4 "
" green overlay "
• blue overlay "
" === DATA OUTPUT
PATTERN * PATL[7 .. 0] +
XPORTb * LUMA[7 .. 0]
OVLGREEN [7 .. 0 ]
PATTERN * PATC[7 .. 0] +
XPORTb * COLR[7 .. 0]
OVLBLUE[7 .. 0]
VCTRL2D + PIP * RGBONYUV;
VCTRL2D + /PIP
Y [7 .. 0] .CLK
UV [7 .. 0] . CLK
May 16,1993
" IDBO "
" IDAO "
" MPK is active high •
CLKE2 ;
CLKE1 ;
Y [7 .. 0]
UV[7 .. 0]
OUTABLE
OUTABLE
2-129
Philips Semiconductors Video Products
Application Note
Desktop video demo board
DTV7194/96
@INPUT VECTORS
" for VQ vertical state machine, for FSGO etc."
[ ENCS,VGA, VSI,HS2RD,HS2,
INTRL,FID,
VSlIZ
VSl
-0
100
110
B;
B;
VS2IZ
VS2
-0
111
101
B;
B;
VS2XZ
VSLEND
VSVGA
VSEND
ENDVBI
MIDLINE
NEXTLINE
-1
VWBEGOF
VWBEGNI
VWBEGLE
EVNFNL
ODDFNL
NONINL
111
-01
1-0---0
-10
-01
1--
-1-
-11
-11
-01
-01
-01
-01
--1
--1
--1
11
010
11
0-
VSLE,VBEND,VWB
" to reset counter
" VS rose in 1st half line,
'even' 2nd field, fid=> 0 "
" to reset counter
VS
rose in 2nd half line,
"
'odd' 1st field, fid=> 1 "
" don't check for interlace "
B;
B;
B;
B;
B;
B;
B;
" end of VBI, enter LINE ZERO"
" reset counter for active v."
" line zero --> IDLETOP
" or toggle FSGO --> VWB1 "
" rstr in odd field "
" rstr i f non interlaced"
" line end--> vwb1 "
B;
B;
B;
B;
B;
B;
" for INRTL-FID state machine "
VSODD
VSEVEN
TF1, TFO
lOB;
B;
@OUTPUT VECTORS
COUNTRST
TICFID1
TICFIDO
VSLRST
FBRESET
GOTOGGLE
GOCLEAR
GOSET
[ CNTRST, TF1, TFO, VSLJ, VSLK, RSTR, FSGOJ, FSGOK
1
0
0
0
0
0
0
0
B;
0
1
0
B;
0
0
0
0
O.
B;
0,
0
B;
0
1
B;
0
1
B;
0
0
0
1
B;
0
0
0
0
B;
@STATE VECTORS
VBI
LINEZERO
IDLETOP
VWB1
IDLEBOT
VGA2VS
VGABOT
DUMMY
VQ2,VQ1,VQO
1
1
1
0
0
0
0
0
0
1
0
1
0
1
1
1
0
FIELD1
FIELD2
NINT1
NINTO
B;
B;
B;
B;
B;
B;
B;
B;
INTRL, FID
1
1 B;
B;
1 B;
0
0 B;
vertical states
keep free: 16 + 1 line
counter restart for act. video"
above Vertical window Begin
flag window start, issue FSGO "
after window begin, till VS
" jump over 2nd VS in VGA mode
" and after that
"
"
"
"
"
"
" interlaced & field ID states"
" interlaced: field 1
" interlaced: field
" likes odd field "
" likes evn field "
@TRANSITIONS
" vQ vertical state machine "
WHILE [VBI]
IF
[VSLEND]
IF
[ENDVBI]
May 16,1993
WITH [VSLRST]
THEN [VBI]
THEN [LINEZERO]
2-130
Application Note
Philips Semiconductors Video Products
Desktop video demo board
DTV7194/96
WHILE [LINEZERO]
[MIDLINE]
WITH [COUNTRST]
IF
IF
[NEXTLINE]
THEN [LINEZERO]
THEN [IDLETOP]
WHILE [IDLETOP]
[VSlIZ]
IF
IF
[VS1]
IF
[VS2IZ]
IF
[VS2]
IF
[VSVGA]
IF
[VWBEGOF]
IF
[VWBEGNI]
[VWBEGLE]
IF
WITH [FBRESET]
WITH [FBRESET]
WITH [GOTOGGLE]
THEN
THEN
THEN
THEN
THEN
THEN
THEN
THEN
WITH [GOSET]
WITH [GOCLEAR]
WITH [GOCLEAR]
THEN [IDLEBOT]
THEN [IDLEBOT)
THEN [IDLEBOT]
WITH
WITH
WITH
WITH
THEN
THEN
THEN
THEN
THEN
WHILE [VWB1]
IF
[ODDFNL]
IF
[EVNFNL]
IF
[NONINL]
WHILE [IDLEBOT]
IF
[VSlIZ]
[VS1]
IF
IF
[VS2IZ]
IF
[VS2)
[VSVGA]
IF
WHILE [VGA2VS]
[VSEND]
IF
WHILE [VGABOT]
IF
[VS2XZ]
IF
[VS2]
WITH
WITH
WITH
WITH
[COUNTRST]
[TICFIDO]
[COUNTRST]
[TICFID1]
[COUNTRST]
[TICFIDO]
[COUNTRST]
[TICFID1]
WITH [COUNTRST]
WITH [TICFID1]
May 16,1993
THEN [VGABOT]
THEN [VBI)
THEN [IDLEBOT]
" INTRL-FID state machine,
[FIELD1]
[VSEVEN]
[VSODD]
[FIELD2)
[VSEVEN]
[VSODD]
[NINT1]
[VSEVEN]
[VSODD]
[NINTO]
[VSEVEN]
[VSODD]
[IDLEBOT]
[VBI]
[IDLEBOT]
[VBI]
[VGA2VS]
THEN [VGABOT]
WHILE [DUMMY]
[]
IF
WHILE
IF
IF
WHILE
IF
IF
WHILE
IF
IF
WHILE
IF
IF
[IDLETOP]
[VBI]
[IDLETOP]
[VBI]
[VGA2VS]
[IDLETOP]
[IDLETOP]
[VWB1]
'spinning wheel' for interlaced"
"11"
THEN [FIELD2]
THEN [NINTO]
"10"
"00"
THEN [NINT1]
THEN [FIELD1]
"01"
"11"
THEN [NINTO]
THEN [NINT1)
"00"
"01"
THEN [NINTO]
THEN [FIELD1]
"00"
"11"
"10"
"01"
"00"
2-131
Philips Semiconductors Video Products
Application Note
Desktop video demo board
DTV7194/96
RHD.EQN
H
RHD = ReadH
H
H
==========
PML2552-35
" U36
horizontal definition of display window "
generation of half-line signal HS2RD
memory READ control, FBBID, RE1, RE2,
data path check for eol/eof/key marker
data path gating, OE
CONTROL PARAMETER
VIEW3
VIEW2
VIEWI
VIEWO
1
non-interlaced display
o interlaced display
1 : 50Hz, 944 clocks per H-line
o : 60Hz, 780 clocks per H-line
one field buffer bank only
two field buffers in use
clock direction, not relevant for READH, but for READCLK
clock from encoder-CGC, e.g. genlock, or stand-alone
clock from decoder to encoder, RTC-Iock-operation,
e.g. slave mode, stand-alone mode
@PINLIST
"pin-#"
CLKA
" 36
CLKB
CLKE2
I
" 24
" 56
;
CLKE1
" 65
GO[7 .. 0)
BO[7 .. 0)
HOS[8 .. 1)
I
I
I
YW[7 .. 0)
UVW[7 .. 0)
0
HSENC
HS2RD
RE1
RE2
OVL
I
"
"
"
"
"
46
47
48
50
51
WINDOW
FSGO
0
;
" 52
I
;
" 53
KEY
INSERT
0
;
H
VIEWO
I ;
" 23
VIEW1
I ;
" 22
VIEW2
I
" 20
54
I ;
May 16, 1993
=
"
"
"
"
"
"
0
0
0
0
MEMREAD, memory read clock, pixel clock,
for byte-serial-mode, this is 2* pixel-elk"
pixel clock, also for internal count
pixel clock, same as LDV, for YW,
for output, i.e. display
for UVW, parallel-mode: same as LDV
clke2
serial-mode: clkel = /LDV, i.e. like elkin;
half period shifted clock = inverted clock"
luma input channel, Y,Green, or serial"
color diff. input. channel, UV, Blue
Horizontal OffSet of inserted window
I2C address: 48 hex
luminance output, respectively Green
colour difference, resp. Blue
HSN of DENC, horiz.sync,
active HIGH
1st half line LOW, 2nd half line HIGH
read enable FRAM bank 1
read enable FRAM bank 2
overlay by MTV, propagated by RVD-pld
could be used as MUTE from external
active HIGH during inserted signal
indicates vertical start of window
" interlaced output (view1=0):
FSGO changes to FID at VW-start
" non-interl.output (viewl=1):
FSGO = line pulse at VW-start
active LOW if PIP or overlay
insert of scaled signal (PIP)
" VIEWx has 12C addresss
46hex "
FBBID toggle mode, if 2 FBBanks
1 : non-interlaced out --> field toggle
o : INTeRLaced display --> line toggle
if only single field buffer: no toggle"
pixels-per-line selection, 50/60 Hz SQP
1 : 50HzSQP: 944 pixel clocks / H-line
o : 60HzSQP: 780 pixel clocks / H-line"
FBB modes, one or two FBBanks in use
1
1 FBB only, FBBID fix=1, no toggle
o : 2 FBB active, FBBID toggle enabled,
FBBID set to 1 @ FSGO rising edge
(FBBID = 1 points to the UPPER bank "
2-132
Philips Semiconductors Video Products
Application Note
Desktop video demo board
@GROUPS
HEOLMARK
"EOFMARK
HKEYMARK
DTV7194/96
0,0,0,0, 0,0,0,0
1,1,1,1, 1,1,1,1
0,0,0,0, 0,0,0,1
H
H
H
end of line marker
end of field marker H
color key marker,i.e.
a transparent pixel
H
@TRUTHTABLE
@LOGIC EQUATIONS
INTRL
SQ50
SQ60
FB1
/VIEWO
VIEW1
!VIEW1
VIEW2
H
H
H
CLK
HBL
HS2RD
RQ [2 .. 0]
FBBID
WINDK
RE1
RE2
CLKB
CLK
CLK
CLK
CLK
CLK;
CLK;
CLK;
.CLK
.CLK
. CLK
.CLK
.CLK
.CLK
.CLK
HBL
.SET
HS2RD
.SET
RQ [2 .. 0] . SET
FBBID
.SET
1;
1;
1;
1;
WINDO
WINDK
RE1
RE2
1;
1;
1;
1;
.SET
.SET
. SET
.SET
interlaced display
1 frame buffer bank only
=== REGISTER & CLOCKS
declarations
state register
state register
H
state registers
set and toggle via state machine
H
1 = upper=odd,
= lower=even
H
to enable the data output H
H
to send a 'window' signal
H
H
H
°
H
=== HORIZONTAL COUNT ===
.rst guides snap to use 10 * JKCL552 with individual
COUNT[9 .. 0] .RST
/CNTRST
H
reset and individual clock
COUNT[9 .. O].J
= 1
COUNT[9 .. O].K
= 1
COUNTO.CLK
CLK
COUNT1.CLK
/(/CLK * COUNTO)
COUNT2.CLK
/(/CLK * COUNTO*COUNT1)
COUNT3.CLK
/(/CLK * COUNTO*COUNT1*COUNT2)
COUNT4.CLK
/(/CLK * COUNTO*COUNT1*COUNT2*COUNT3)
COUNT5.CLK
/(/CLK * COUNTO*COUNT1*COUNT2*COUNT3*COUNT4)
COUNT6.CLK
/(/CLK * COUNTO*COUNT1*COUNT2*COUNT3*COUNT4
*COUNT5) ;
COUNT7.CLK
/(/CLK * COUNTO*COUNT1*COUNT2*COUNT3*COUNT4
*COUNT5*COUNT6) ;
COUNT8.CLK
/(/CLK * COUNTO*COUNT1*COUNT2*COUNT3*COUNT4
*COUNT5*COUNT6*COUNT7) ;
COUNT9.CLK
/(/CLK * COUNTO*COUNT1*COUNT2*COUNT3*COUNT4
*COUNT5*COUNT6*COUNT7*COUNT8) ;
H
HOSO
HOS9
H
HBL . J
TRIGGER
HS2RD.K
RESTART
+
CNTRST
May 16,1993
HSD
HSD
HBL
HBL
HBL
*
*
*
*
H
H
=== HORIZONTAL EVENTS ===
to adjust for uv-sequence H
/HBL ;
rising edge is leading edge
COUNT[9 .. 0]
023H
35 = some room
COUNT[9 .. 0]
05FH * SQ60
H
140 - 45 = 95
COUNT[9 .. 0]
H
176 - 45 = 131
083H * SQ50
H
restart to position HWB in 'active line' only
TRIGGER + RESTART
H
H
2-133
H
H
H
H
H
H
H
H
H
H
H
H
H
Philips Semiconductors Video Products
Application Note
Desktop video demo board
HBL . K
CLAMP
BLANK
MIDLINE
HS2RD.J
HWB
• after 2nd restart •
/HSD * COUNT[9 .. 0] == 001H ;
• from count=48 W
HBL * (COUNT[7 .. 4] == 0011B +
COUNT[7 .. 5] == OIOB
"to
count=95"
• insert RGB reference values for sandcastle clamp W
HBL * /HS2RD ;
" yuv = 'null'
• mid line n*fh/2 - 'front blank'= W
SQ60 * (COUNT[9 .. 0]
149H) +
W 780/2 ( 95-35) W
SQ50 * (COUNT[9 .. 0] == 177H)
• 944/2 - (131-35) W
/HBL * MIDLINE ;
/HBL * COUNT[9 .. 0] == HOS[9 .. 0]
"horizontal window begin, after vertical window begin W
IDA[7 .. 0]
IDA [7 .. 0]
IDA [7 .. 0)
EOL
EOF
KEY
TPIX
OVLAY
WINDR
WINDO.D
WINDK.D
DTV7194/96
n
=== CONTROL & OUT === •
"EOLMARK
end of line marker
"EOFMARK = end of field marker "
"KEYMARK = color key marker,
i.e. transparent pixel
this is not a pixel to display·
OOH
FFH
01H
EOL + EOF + KEY ;
OVL ;
/RQ2*RQ1*RQO * /TPIX
• have read (good) data"
(WINDR*INSERT + BLANK) * /OVLAY
" output data •
/(WINDR*INSERT + BLANK + OVLAY)
• use as DENC KEY n
N
DATA PATH THRU
IDA [7 .. 0). ID
IDA [7 .. 01 . CLK
IDB [7 .. 01 . ID
IDB [7 .. 0) . CLK
GO[7 .. 0]
CLKA ;
BO[7 .. 0]
CLKB ;
Y
[7 .. 0).00
[7 .. 0].00
/BLANK * IDA[7 .. 0]
/BLANK * IDB[7 .. 0]
W
[7 .. O).CLK
[7 .. O).CLK
CLKE2 ;
CLKE1 ;
YW
[7 •• 0)
Y [7 .. 0]
W[7 .. 0]
W
Y
WW[7 .. 0)
YW [7 .. O).OE
WW[7 .. O).OE
WINDOW
KEY
WINDO * /OVL
WINDO * /OVL
WINDK + OVL
/WINDOW ;
* 10H
BLANK
BLANK*/CLAMP * 80H
CLAMP * 10H
" window is active high "
key is active low
N
@INPUT VECTORS
[ FSGO,HBL ,HWB, EOL,EOF,
IDA7,IDA6,IDA5,IDA4,IDA3,IDA2,IDA1,IDAO,
INTRL,FB1,FBBID ]
FSGUP
1 B;
·also FSGO line pulse w
FSGDN
I B;
from odd to even
WAIT
- - 0
B;
HSTARTU
- 0 1
--1 B;
wH-window begin Upper"
HSTA,RTL
- 0
--0 B;
"H-window begin Lower·
NOFLAG
0
B;
EOLI
1 1-- B;
EOLN2U
1 001 B;
" toggle to lower "
EOLN2L
I 000 B;
" toggle to upper
EOLN1
1 01- B;
1
EOFODD2
- 1
101 B;
toggle to lower "
EOFODD1
- 1
11- B;
EOFEVN
- 1
B;
" set fbbid anyhow N
.
N
.
@OUTPUT VECTORS
[ FBBID, REI, RE2 1
FBBLO
0
0 0 B;
FBBUP
1
0
B;
DUMREAD
1 1 B;
READU
1 0 B;
READL
0
B;
0
NOREAD
B;
May 16,1993
" FBBID : where to read from
JKFFS
• set to lower field buffer bank·
" set to upper field buffer bank"
" dummy read at window-frame begin "
" read from upper FBB
" read from lower FBB
., stop reading after EO-marker
2-134
Application Note
Philips Semiconductors Video Products
Desktop video demo board
DTV7194/96
@STATE VECTORS
DUMMY2
IDLODD
IDLEVN
WINACT
RIBBON
FIRST
SECOND
LAST1
RQ2,RQ1,RQO
JKFFS
0
0 B;
0
"B;
1
B;
1
B;
B;
1
B;
1
B;
1
1
B;
.
.
--- for WINACT --2nd dummy read at window begin
··
··
·
display zones and
window generation
read 1st tristate
J:".e~d 2nd tristate
check for eof
"
·
··
··
@TRANSITIONS
There is a pipeline delay until an eol or eof marker is
detected. In that moment - as an eol marker is found - there
are already initiated two more reads from FRAM,
i.e. the first two pixels of the next line are already read.
These first two pixels of every line get lost.
At the begin of a frame buffer bank, i.e. for the first line,
two pixels have to be thrown away artificially : an extra read
at vertical window begin and excursing loop via dummy2.
If an end of field is indicated by a plain eof marker (no
preceding eol, irregular case) there get two pixels lost, too.
If an end of field is indicated by a sequence of eol and eof
marker (regular case) only one pixel gets lost.
WHILE [IDLEVN)
THEN
[DUMMY2)
IF
[FSGUP)
WITH [DUMREAD)
• for parity, throw first 2 pixel of Frame Buffer Bank away,
• like first 2 pixel of other lines
WHILE [IDLODD)
[FSGDN)
THEN
[RIBBON)
IF
[WAIT)
THEN
[IDLODD)
WITH [NOREAD)
IF
WHILE [DUMMY2)
[)
IF
THEN
[RIBBON)
WHILE [RIBBON)
IF
[HSTARTU)
[HSTARTL)
IF
[WAIT)
IF
THEN
THEN
THEN
[FIRST)
[FIRST)
[RIBBON)
"
WITH [READU]
WITH [READL)
WITH [NOREAD)
• first, second
from issue a 'read' to FRAM to receiving
related 'correct' data in PLD there is a pipeline delay of
2 clocks. Don't use these intermediate data.
Don't check for 'eol' or 'eof', as there is rubbish in pipe.
WHILE [FIRST)
[)
IF
WHILE [SECOND)
[)
IF
WHILE [WINACT)
[EOLI)
IF
IF
[EOLN1)
IF
[EOLN2U)
IF
[EOLN2L)
[EOFODD2)
IF
IF
[EOFODD1)
[EOFEVN]
IF
WHILE [LAST1)
"last+1 pixel
IF
[EOFODD2)
[EOFODD1)
IF
IF
[EOFEVN]
[NOFLAG]
IF
May 16,1993
THEN
[SECOND)
THEN
[WINACT)
THEN
THEN
THEN
THEN
THEN
THEN
THEN
[LAST1)
[LAST1)
[LAST1)
[LAST1)
[IDLODD)
[IDLEVN)
[IDLEVN)
WITH
WITH
WITH
WITH
WITH
WITH
WITH
[NOREAD)
[NOREAD)
[FBBLO)
[FBBUP)
[FBBLO)
[NOREAD)
[NOREAD)
" check last+1 'read' for eof "
first pixel of next line, lost in the pipe "
THEN
[IDLODD]
WITH [FBBLO)
THEN
[IDLODD]
WITH [DUMREAD]
THEN
[IDLEVN]
THEN
[RIBBON)
2-135
PhilipS Semiconductors Video Products
Application Note
Desktop video demo board
DTV7194/96
RREDD.EQN
" RREDD:
U38
PL22V10
@PINLIST
REDCLK
RO[7 .. 0]
VCTRL
MTVRED
insert red for MTV-red for menu overlay
Also insert of blank level during CBN
" pin # "
I
I
I
I
1
2 .. 9
;
;
OUT[7 .. 0] 0
PIXCLK
CBN
I
" 11
" 13
pixel clock for red channel "
Red channel from FRAM memory
overlay control
overlay black/red select
" 23. ;16: output after register"
" 14
here not used
" 15
to insert clamp reference BLACK
CBN is active low during blank
@GROUPS
@TRUTHTABLE
@LOGIC EQUATIONS
BLACK [7 .. 0]
RED
[7 .. 0]
OUT [7 .. 0] .D
OUT [ 7 .. 0 ] . CLK
10H ;
B4H ;
VCTRL
VCTRL
!VCTRL
+
+ /VCTRL
" 100%
* /MTVRED
* MTVRED
* /CBN
* CBN
REDCLK
= EB,
BLACK
RED
BLACK
RO
75% = B4 "
[7 .. 0]
[7 .. 0]
[7 .. 0]
[7 .. 0]
;
@INPUT VECTORS
@OUTPUT VECTORS
@STATE VECTORS
@TRANSITIONS
May 16,1993
2-136
Application Note
Philips Semiconductors Video Products
Desktop video demo board
DTV7194/96
CASTLD.EQN
generation of SANDCASTLE timing for
TDA4686, and sync signals for
RGB monitor output
( or PL22V10
" CASTLD
U26
PLC42VA12
TASK
castl gets - horizontal sync/blanking - active high
(leading edge is used as timing reference)
and - vertical syncs : VSENC and VSLong)
castl delivers :
- combined vertical and horizontal blanking as CBLANK
- sandcastle HCLAMP signal,
to construct externally 'analog' sandcastle pulse
- horizontal sync HSYCM and vertical sync VSYNCM
for RGB monitor timing, both selectable in polarity
castl counts horizontally with CLKMTV, half the pixel rate
CONTROL PARAMETER
COSY (SORT3)
1
HSYNCM is Composite Sync for Monitor, like CBLANK
o
horizontal and vertical sync on separate wires
POLH (SORT6) # hsP : select polarity of HSYNCM for monitor
1 : positive sync pulse
0: negative sync pulse
POLV (SORT7)
# vSP : select polarity of VSYNCM for monitor
1 : positive sync pulse
0: negative sync pulse
Concept :
=========
5 bit counter and
2 bit statemachine (blank, clamp)
enable counting
HSENC triggers counter:
begin H blanking
reset counter
(48 pixclk) : then
begin H sync
count 24
begin H clamp
(24 pixclk) : then
reset counter
count 12 more
(24 pixclk) : then
H clamp
count 12
end
(36 pixclk) : then
reset counter
count 18 more
( 8 pixclk) :
count 4
then
end H sync
end H blanking
stop counting
count 26 more
(52 pixclk) : then
wait for next HSENC trigger
HSYNCM is copy of internal horizontal sync timing
VSYNCM is copy of selected VSLong (10 lines) timing
CBLANK is 'or' of VSLong and Hblank
"pin-#"
@PINLIST
CLKMTV
CBN
VSL
VSENC
HSENC
COSY
1
2
I
5
6
POLH
POLV
HSYNCM
VSYNCM
CBLANK
HCLAMP
hqO
hq1
0;
0;
0;
0;
"20
H
21
M
22
H
23
0;
H
0;
H
May 16,1993
16
15
half pixel clock, CLKMTV
composite blanking, here not used
vsx, vsd or vsx carries VSLong
VSN @ DENC, vertical sync, active High
HSN @ DENC, horizontal sync, active High M
monitor sync composite or separate (SORT4)
1 : composite sync on HSYNCM
o : separate syncs VSYNCM and HSYNCM
polarity of HSYNCM for monitor (SORT6)
polarity of VSYNCM for monitor (SORT7)
for monitor H synchronisation
for monitor V synchronisation
composite blanking for sandcastle
clamp part of sandcastle, 'burst key'
for test purposes only
for test purposes only
H
M
2-137
Applic,ation Note
Philips Semico9ductors Video Products
Desktop video demo board
DTV7194196
@GROUPS
@TRUTHTABLE
@LOGIC EQUATIONS
REGISTER & CLOCKS
CLK
HQ[l. .0]
HQ[l. .0]
.CLK
.SET
declarations
CLKMTV
CLK
1
state machine registers
• ===
=== •
HORIZONTAL COUNT
COUNT [4 .. 0] . RST
ICNTRST
• from state machine •
COUNT [4 .. O].J
ICNTHLD
COUNT [4 .. O].K
ICNTHLD
COUNTO.CLK
ICLK
I(CLK * COUNTO
COUNT1.CLK
COUNT2.CLK
I(CLK * COUNTO * COUNT1
COUNT3.CLK
I (CLK * COUNTO * COUNT1 * COUNT2 ) ;
COUNT4.CLK
I(CLK * COUNTO * COUNT1 * COUNT2 * COUNT3 ) ;
• ===
CNT08
CNT24
CNT48
CNT60
HBLANK
HCLAMP
HSYNC
COUNT [4 .. 1]
COUNT[4 .. 1]
COUNT[4 .. 1]
COUNT[4 .. 1]
HQO + HQ1
HQO * HQ1
HQ1
HORIZONTAL EVENTS
2H
6H
CH
FH
• horizontal blanking (& sync) •
• 'burst key' for sandcast1e
CONTROL & OUT
VSLONG
CBLANK
VSYNCM
HSYNCM
VSL ;
VSLONG + HBLANK ;
POLV * VSLONG
+ IPOLV * IVSLONG
POLH *
(HSYNC
+ IPOLH * I( HSYNC
+
COSY * VSENC
COSY * VSENC
@INPUT VECTORS
[ HSENC, CNT08, CNT24 , CNT48 , CNT60 ]
SYNC
1
1
B;
C08
1
B;
C24
B;
1
C48
1
B;
C60
B;
1
HOLD
o
1
B;
@OUTPUT VECTORS
[ CNTRST, CNTHLD
RESTART
lOB;
STOP
B;
1
GO
B;
o
@STATE VECTORS
[ HQ1. HQO
IDLE
0
0 B;
BLK1
0
1 B;
CLAMP
1
1 B;
BLK2
lOB;
@TRANSITIONS
WHILE [IDLE]
IF
[C60]
IF
[HOLD]
IF
[SYNC]
WHILE [BLK1]
IF
[C60]
IF
[C48]
WHILE [CLAMP]
IF
[C60]
IF
[C24]
WHILE [BLK2]
IF
[C60]
IF
[COal
May 16,1993
WITH [STOP]
WITH [STOP]
WITH [GO]
THEN [IDLE]
THEN [IDLE]
THEN [BLK1]
WITH [RESTART]
THEN [BLK1]
THEN [CLAMP]
WITH [RESTART]
THEN [CLAMP]
THEN [BLK2]
WITH [RESTART]
THEN [BLK2]
THEN [IDLE]
2-138
Philips Semiconductors Video Products
Crystal specifications
The Philips line of digital decoders requires crystals which meet specific specifications. Picking a crystal vendor solely on the basis of frequency
will not guarantee satisfactory performance.
Operational failures that could be related to crystal dysfunction are:
1. Inability to achieve line lock (hOrizontal lock)
2. Inability to achieve chroma lock
3. Slowness of lock acquisition.
The crystal specifications are:
Nominal frequency:
26.800000MHz (square pixel decoders)
24.576000MHz (CCIR decoders)
Load capacitance CI:
8pf
Adjustment tolerance:
±40ppm
Resonance resistance R r:
50 n (square pixel)
60n(CCIR)
Drive level dependency:
80n
Motional capacitance C 1 :
1.1 fF (square pixel)
1.0 fF (CCIR)
Parallel capacitance Co:
3.5 pF (square pixel)
3.3 pF (CCIR)
Temperature range To:
o to 70 °Celsius
Frequency stability:
±20ppm
The Philips part numbers for these crystals are:
9922 520 30004 for the square pixel systems (26.800000MHz)
992252030009 for the CCIR system (24.576000MHz)
The Philips crystals can be obtained from:
Philips Components Passive Group. phone: (803) 772-2500
The crystals are also available from ECliptek. Their part numbers are:
ECX-2194-26.800MHz
and
ECX-2097-24.576MHz
Ecliptek can be reached at (714) 433-1200. The contact sales representative is Rodney Mills.
May 1993
2-139
Application Note
Philips Semiconductors Video Products
TDA8708 black level and gain modulation circuit
Author: Herb Kniess
The Philips TDA8708 8·bit AID converter
digitizes video signals and contains black
level and automatic gain control circuits. The
binary levels for sync and black are internally
fixed in the device. Sync tip is maintained at
OOH and black level is maintained at 40H. It
may be desirable to allow manual override of
these automatic features. The following
circuit describes a method for overriding the
automatic features of the TDA8708 as well as
retaining them.
MANUAL GAIN CONTROL
Normal operation and connections of the
TDA8708 are shown on page 2 of the
schematic when it is used in conjunction with
the Philips SAA71 XX series Digital Video
Decoders. The only changes to the normal
circuit are made through connections labeled
"Black" and "Gain." Normally, a capacitor is
connected to ground at Pin 25 of the data
converter. This capacitor holds a charge
dependent on the level of the input video
signal and the control voltage necessary at
Pin 25 to maintain sync level of OOH.
Currents near 50·100 microamps are
generated within the converter during
horizontal blanking times to charge or
discharge the capacitor as necessary, in
order to maintain the preset binary output
levels of the converter. The voltage on Pin
25 controls the gain of the input amplifier of
the converter.
A similar circuit and current source is
implemented on Pin 24. However, its only
function is to provide the proper DC offset
voltage necessary to maintain the black level
at 40H regardless of changes of input signals
or bias changes on input pins 16, 17, or 18.
April 1993
Under normal operation, the data converter
binary outputs are maintained at preCise
digital values.
Page 1 of the application schematic shows
that the gain connection to Pin 5 of the
TDA8708 is connected to capacitor C1 via an
analog switch at U2. During horizontal
blanking time the analog switch maintains a
connection from Pin 25 of the converter to
capacitor. Thus, sync levels are maintained
via the automatic circuits in the converter.
However, if necessary, the control voltage on
Pin 25 can be switched to the input voltage at
Pin 12 of analog U2 switch during the active
video time of each scan line. DAC7 of U1
and bias resistors R1, R2, and R3 provide a
variable control voltage for manual control of
gain only during the active video portion of
the scan line.
The bandwidth of the control voltage on Pin
25 of the converter can be as high as 5 Mhz
so that a precise match of the timing of the
gain change is possible at the beginning and
ending of blanking times. Noise on the gain
control pin must be kept to a minimum in
order to avoid AM modulation of the input
video signal. The digital decoder can be
reprogrammed to adjust the timing of the
HCL and HSY timing signals to carefully
match the timing diagram of page 1 of the
schematic. Refer to the TDA8708 data sheet
for a discussion of the operation of these
signals in the TDA8708. Do not worry that
the modified positions of the HSY and HCL
signals might affect the operation of the
converter. They will not because the change
in position is small compared to the overall
width of the pulses. For optimum
performance, the beginning and ending of the
2·140
gate signal at Pins 5 and 6 of U3 should be
set within the minimum blanking time of any
signal being digitized.
BLACK LEVEL CONTROL
Analog switch U2 provides another function
besides control of the gain voltage at Pin 25
of the TDA8708 converter. It can be
switched to inject a DC pulse on Pin 4 to R15
at Pin 19 of the data converter. Pin 19 is the
video output of the input amplifier of the
TDA8708. It is nominally about 1V PP. If a
DC pulse is added to the video signal at R15
during active video time, the DC level
between blanking and active video can be
modified. The data converter still provides a
constant black level of 40H during blanking
time but the data converter can produce other
levels for black during active video depending
on the polarity and level of the injected signal.
DAC6 and bias resistors R6, R4, and R5
provide a variable bias at Pin 5 of U2, which
is gated onto the video signal by gate pulse
at Pin 3 of U5.
It is desirable to inhibit the modulation of
black and gain signals during the vertical
sync area so that proper integration of the
vertical sync will be maintained by processing
circuits. This is accomplished by VSYNC
INHIBIT at Pin 11 of U5. Additional control
functions are provided by logic levels of
DAC5 and DAC4, which turn on and off the
black level and gain modification signals at
U2. It should be noted that different bias
resistors can be selected on DAC7 and
DAC6 pins to affect the allowable range of
control but the DAC full range of OOH to 3FH
should be used in order to give the finest
degree of control.
~
."
2:
co
co
Co)
TDA5705 BLACK LEVEL AND GAIN MODULATOR
--I
CJ
»
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"-I
0
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4.7K
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(BRIGHTNESS AND CONTRAST)
VCC
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(C
DACD
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VCC
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1-1
PIN
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16 VCC
PIN 8
3
0
a.
GND
VEE
c
REMOVE T DA8444 TO
SET AGC OPERATION
~
TIMING DIAGRAM
~
ecr
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CHR3
CHR2
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UV6
UVS
UV4
UV3
UV2
UVl
UVO
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Philips Semiconductors Video Products
Application note
TDA9141 analog decoder application
Author: George Ellis
OVERVIEW
AID CONVERSION AND CLOCK
LEVEL CONTROL
Analog solutions for video decoding and
digitization are available in addition to the
digital methods mentioned elsewhere in this
book. The individual components are
generally of lower cost; however, trade-offs
with regard to the total number of
components to perform a specific function
must be considered.
The analog Y, U, and V signals are applied as
AC coupled inputs to three TDA8709 AJD
converters. Gain controls for all three
converters and a black level control for the Y
converter are provided by the level control
block.
An IIC controllable level control circuit is
achieved using a TDA8444 6-bit octal DAC to
produce DC control of· the gain control inputs
of the data converters. A fourth DAC output
is gated to be applied only during blanking,
and is added to the Y input signal to produce
a DC offset of the luma signal, thus allowing
control over the black level. These DC levels
could as easily be derived from resistors
instead of the DAC, for use in systems that
have these parameters preset at the factory.
SYSTEM CONFIGURATION
This application is divided into four blocks:
1. Analog video to analog YUV decoding
2. AJD converter with clock and support
circuitry
3. Level control circuit for block 2
The Clamp Select pin (pin 27) is set to adjust
the DC level of the U and V converters to a
value corresponding to decimal value 128
during the application of the positive clamp
pulse derived from the decoder block. The
Clamp Select pin of the Y converter is set to
force the DC input level to correspond to a
value of decimal 16. This sets the converters
to the appropriate digital value during
blanking.
4. Optional RGB output block
Various elements of this application need not
be used if not called for by the application.
The intent here is to demonstrate a full
featured solution.
Each converter is capable of selecting one of
three inputs applied, and a simple low-pass
filter is inserted between the selected signal
and the AJD input to remove any possible
high frequency noise that could cause
aliasing effects.
DECODER
Composite, S-video, or analog RGB can be
input to the Philips TDA9141 multi-standard
decoder. This device, in conjunction with the
TDA4661 delay line, will decode the NTSC,
Pal and Secam standards, and output them
as analog Y (luma) and UV (chroma) outputs.
The luma-to-chroma delay is matched;
therefore, no luminance delay line is
necessary. If NTSC is desired exclusively,
the TDA4661 delay line need not be used.
The delay line is used as a chroma comb
filter for NTSC, and although not strictly
required, it does reduce undesirable
cross-color effects. Note that unlike older
delay lines that work in the subcarrier
base-band, the TDA4661 works in the
demodulated UV color-difference band, and
is implemented with charged-coupled
technology instead of using a bulky glass
delay line.
Optional color transient improvement and
peaking can be applied to the YUV signal by
use of the TDA4670; again, this may be
deleted in a no-frills application.
Two comparators are used to extract
horizontal blanking and clamp signals from
the sandcastle pulse generated by the
TDA9141, and are used for the AJD
converters. The TDA9141 also outputs a
line-locked 6.75MHz clock that is used in the
conversion process.
The decoder and color transient device are
controlled via the IIC two-line interface bus.
The decoder can be programmed for
automatic detection of the three video
standards.
April 8, 1993
The 6.75MHz clock from the TDA9141 is a
low level sawtooth with an amplitude of about
1 Vpp. This signal is very similar to the
LFCO signal available from the digital chip
decoders, thereby making it possible to
generate 13.5MHz, 27M Hz, and CREF
signals using the same device as that used
by the digital chip set, the SAA7197.
The UV bandwidth is one halfthe 13.5MHz
luma bandwidth, therefore, the 13.5MHz
clock is divided by two. The 13.5MHz signal
and the CREF Signal are delayed to match
the delay introduced in producing the 6.75
clock.
The 6.75 clock is used for the conversion
process of the U and V converters and for the
multiplexers that follow. This results in one
UV pair for every two luminance samples.
The outputs of the multiplexers and the luma
AJD converter are latched with D flip-flops
using the 13.5 clock.
The resulting digital format is the 16 bit 4:2:2
format used by various digital systems,
including the Philips video scaler (SAA7186)
and encoder (SAA7199B). This is also an
efficient storage modelor video as it uses 16
bit wide memory structures instead of 24.
A new triple input YUV AJD converter has
been added to the Philips line, the TDA8758,
which outputs the 4:2:2 format; however, it
will not be available until the end of 1993, and
therefore has not been included in the
handbook.
2-143
RGB OUTPUT AND YUV BUFFER
STAGE
If YUV to RGB conversion is necessary for
output to a monitor or for RGB digitizing, the
TDA4686 is useful. This device has a YUV
to RGB analog matrix with two additional
RGB inputs that can be switched in at a
pixel-by-pixel rate.
The circuit shown here will drive an analog
RGB monitor with 75 n loading. It may also
be used to drive the inputs of three RGB
digitizing AJD converters (same circuit as the
Y converter, times three). Because the
TDA4686 has brightness, contrast, and
saturation controls via IIC bus, the input
circuit previously described would not be
necessary, as all gain and black level
adjustments can be made with the TDA4686.
If YUV analog component video output is
desired, the YUV levels that are input to the
TDA4686 can be buffered by high speed op
amps to drive 75 n loads. For component
video, the output levels are set to .7 Vpp for
full scale U, V, and non-composite Y (Y
without sync) driven into 75 n. A series
resistor is needed to match the cable
impedance and the driven device would have
a 75 n termination load. This requires that
the gain of the op amps be set such that full
scale output is 1.4 Vpp before the series
matching resistor.
SUMMARY
Full featured desktop video solutions can
generally be met with far fewer parts if a
digital chip set is used. This is due to the fact
that these digital solutions were designed for
this market, where the analog methods were
originally designed for consumer (TV)
applications where there is no requirement
for digitization and data format. There are,
however, many low end applications where
various portions of this application could be
useful.
Philips Semiconductors Video Products
Application note
TDA9141 analog decoder application
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Philips Semiconductors Video Products
Digital video evaluation board
Author: George Ellis
OVERVIEW
In order to individually evaluate the Philips
digital video encoding and video DAC
systems, the SAA7199B and SAA7165
(SAA9065) chips, respectively, a demo board
was developed that is capable of receiving
digital data from a broadcast quality video
test generator.
This board receives input in the D1 digital
video format, converts the data to the 16 bit
422 data format used by the Philips system,
and produces the clocks and sync signals
necessary to drive the encoder and video
DAC. The board generates analog
composite video and S-video using the
SAA7199B digital encoder, and it produces
analog YUV (Y, Cb, Cr) using the SAA7165.
It also converts the analog YUV into analog
RGB using the TDA4686, thus demonstrating
a complete digital-to-analog video output
solution.
01 DIGITAL VIDEO FORMAT
D1 digital video (parallel mode) is an industry
standard used to transfer video without any
loss of quality. Being digital in nature, this
signal can be duplicated indefinitely, and
therefore is used in many broadcast
production facilities.
D1 is transferred as a nine-pair (8 bit D1) or
as an eleven-pair (10 bit D1) ECl cable
configuration; the 8 bit D1 format is used for
this demo board.
Upon input to the demo board, these signals
are converted to TIL levels consisting of 8
data bits and one 27MHz clock stream.
The luminance (Y) and chrominance (Cb, Cr)
are multiplexed onto the 8 bit data path in the
order: Cb, Y, Cr, Y, etc. (see Figure 1). For
each two clock cycles, one luminance and
one of the two chrominance signals are
transmitted. This is the same luminance and
chrominance data bandwidth used by the
Philips cnip set, with the exception that it is
mUltiplexed.
De-multiplexing the luma and chroma data
produces 8 bit data paths each for luminance
and chrominance, clocked at a 13.5 MHz
clock rate. There is now one luma byte
delivered for each 13.5MHz clock and one
pair of chroma axis bytes for every two clock
intervals; this is exactly the data format
required by the digital chip set.
The D1 format also inserts markers into the
data path that define the beginning and end
of active video. These markers consist of 4
hex bytes: FF, 00, 00, XV. The series, FF 00
00 is used to initiate the start or end of active
video and to latch the XY byte information.
April 12, 1993
The XY byte contains three bits that define
the following (see Figure 2):
- End or Start of Horizontal Blanking
- End or Start of Vertical Blanking
- Field 1 or Field 2 Status.
Although horizontal and vertical sync are not
included in these codes, their relation to the
blanking signals is known, and they can be
reconstructed.
BOARD DESCRIPTION
Reference to sheet one of the schematic
shows that the demo board consists of four
subsections:
- ECl translation and power regulation
- D1 to 422 demultiplexing
- Digital YUV to analog composite encoding
- Digital YUV to analog YUV and analog
RGB conversion.
ECl Translation
Sheet two shows the D1 signal input at
connector P1 as eight pairs of data and one
pair of clock lines. These lines are
terminated through 470 n resistors to
-5 VDC and are converted from differential
ECl data into ground referenced TIL data
(U32-U34).
Standard three terminal regulators are used
to convert unregulated positive and negative
9 volt inputs to regulated positive 5 VDC
(Vcc), negative 5 VDC and positive 8 VDC.
Bypass caps are shown and are distributed
throughout the board.
U51 is a programmable microcontroller that
will initialize the appropriate devices upon
power up by use of the Philips 12C interface.
12C programming can also be performed over
the 12C bus via external connectors (JP4 and
JP5 shown on sheet 5).
01 to 422 Demux
The 8 data lines enter buffer U31 on sheet 3
and are clocked sequentially through U12,
U13, and U14 at a 27 MHz clock rate. If a
byte value of FF is detected at U26 at the
output of U14, and if data byte values of 00
are detected by U5A and U5B at the outputs
of U13 and U 12, the coincidence of these
signals latches the contents of bits Tl6, Tl5,
and Tl4 into U 15. These signals are
reclocked at a 13.5 MHz rate and are output
by U17 and U6B as HREF (horizontal
blanking), vertical blanking, and field ID.
The 27 MHz clock is divided in half by U27A
and buffered by U7. Counters U8 and U9 are
loaded to a preset by HREF and clocked by
the 27 MHz clock to produce a horizontal
sync reset pulse at the output of U22A.
2-149
The 8 bits of multiplexed YUV data are
duplicated into two identical buses. One bus
(to be demuxed as Y) is connected to the
A 1-D1 inputs of U20 and U18, the other bus
(to be demuxed as UV) is connected to the
A2-D2 inputs of U19 and U21. The outputs
of all four of the demux devices are returned
to the alternate inputs of the same device,
QA-QD of U20 and U18 are returned to the
correspondingA2-D2 inputs, and QA-QD of
U19 and U21 are returned to the
corresponding A 1-D1 inputs. All four devices
are clocked at the same 27 MHz rate, and the
WS (write strobe) is supplied with a common
13 MHz clock. Due to the reversal of the
input arrangement, the write strobe in one
case will latch the Y data, and in the other
case will latch the UV data. The data output
from U18-U21 actually changes at a
13.5 MHz rate due to the feedback of the
data and the 13.5 MHz write strobe. This
data is latched and buffered by U24 for Y and
U23 for UV. These two devices can also be
tristated in the case it is desired to input
alternative data from connector JP1. This
tristate is controlled by jumper JP3.
Digital YUV to Analog Composite
Encoding
The 16 bits of demuxed Y and UV are input
to the data ports of the SAA7199 digital
encoder. The device is supplied with a
13.5 MHz pixel clock, HREF for blanking, HS
for horizontal reset, and Field ID for vertical
reset. The TSG422 generator does not
output interlaced vertical blanking, the
generator produces vertical blanking at the
beginning of line 263, as opposed to starting
midway between lines 262 and 263, as is the
case in analog video. The SAA7199B needs
only to be reset vertically once to place it in
the proper field sequence; the device will
then create the proper vertical
synchronization. That being the case, field ID
is used to reset the device vertically for the
first field, and the SAA7199 calculates and
correctly produces the interlaced vertical
interval between field 1 and 2.
The signal ClK_13 is used both to latch the
data (via the lOV pin) and, after a delay
period produced by U47A and U47B, is
applied to the ClKIN and llC pins. The
delay is to ensure that latching the data and
clocking it do not occur simultaneously.
The SAA7199B simultaneously outputs
composite video and S-video (separate
luminance and chrominance). Output filters
are applied to these outputs to low pass any
residual clock energy and to provide sin(X)/x
correction. The output of the compOSite filter
is buffered; this allows for driving long cable
lengths without effecting the output filter
characteristics.
Philips Semiconductors Video Products
Application note
Digital video evaluation board
U54, 04, and 05 strip and buffer sync from
the luminance portion of the S-video output.
This composite sync is used for the analog
YUV and RGB that is produced by the .
SAA7165 and TDA4686 devices (described
in the next section). The position of this sync
relative to the active YUV (RGB) signals is
programmable via the SAA7199B.
demuxed D1 data (JP3 shorted) or the data
input from connector JP1 (JP3 open). An
example of data that could be input to the
demo board at JP1 is the data stream from
the Philips digital decoder (SAA7151B,
SAA7191B, or SAA7194(6)).· The sync and
clock signals from the decoder are input at
connector JP2.
The SAA7199B is programmed to run in
slave mode with YUV as the input format.
The following chart lists the complete register
settings for initializing the encoder:
Connectors JP2 and JP1 are oriented such
that the D1 demo board may be connected
directly above the Philips DTV7199 demo
board. JP2 connects to JP1 0 of the
DTV7199 and JP1 connects to JP14 of the
DTV7199. The same mechanical relation
exists between the pair of connectors.
02
85
03
3B
SUB ADDR
DATA
SAA71998
00
AE
01
00
02
03
04
00
00
44
05
30
06
52
07
30
08
10
09
00
OA
00
DB
00
OC
A6
OD
00
OE
OD
These registers are programmed via the 12C
bus, either by the microcontroller or the 12C
interface connectors JP4 or JP5.
Note that the encoder has both digital (Vcc)
and analog (AVcc) power connections .. AVcc
is produced from Vcc by the filter network
comprised of L4, C64, C65, and C67.
Digital YUV to Analog YUV and
RGB conversion
Sheet five indicates the data buses Y[0 .. 7)
and UV[0 .. 7) input to U53 in parallel with the
outputs of U38 and U38 tristate buffers.
These buffers, in conjunction with U23 and
U24 (sheet 3) and the signal D1 SEL set by
jumper JP3, select the input to the SAA7165
(and the SAA7199B) to be either the
April 12, 1993
provided by the microcontroller set AGB
levels to .7 Vpp (full scale).
The default register settings are:
SUBADDR
DATA
SAA7165*
01
04
TDA4686
00
09
01
30
The SAA7165 also receives the 13.5 MHz
clock and HREF sigrials to clock and blank
the conversion process.
02
27
03
19
04
iF
The video DAC outputs analog Y, U, and V
on separate outputs. The polarity of the U
and V signals is controllable in software for
flexibility with all systems. The SAA7165
also provides controllable color transient
improvement. The analog YUV signals are
buffered by U42-U44 to provide .7 Vpp
signals (full scale video) into a 75 n
terminated load.
05
iF
06
iF
07
iF
08
iF
As with the SAA7199B, the SAA7165 has
both digital (Vcc) and analog (Vcc_ANA).
This separation if effected by L2, C22, and
C23.
The YUV outputs are also fed to the inputs of
the TDA4686 via resistornetiNorks to provide
the proper voltage range to the TDA4686.
This device requires a full scale Y input of .45
Vpp, U input is 1.33 Vpp full scale, and V is
1.05 Vpp full scale.
The TDA4686 has an analog YUV to RGB
matrix with software control of contrast,
brightness, and saturation via the 12C bus.
The TDA4686 requires a two-level timing
signal called 'sandcastle' to initiate certain
internal processes. This signal is
synthesized by U40A, U45A, U46A, and
U45B from vertical sync and HREF. HREF is
delayed in this circuit to compensate for the
pipeline delay of the video through the
SAA7165.
The output of the TDA4686 are fed to a
modified emitter follower circuit that ensures
the proper DC blanking levels and drives
75 n loads. The default register setting
2-150
09
iF
OA
3F
OB
00
OC
80
OD
1A
*There is no sub address 00 for the
SAA7165.
JP4 and JP5 are connected in parallel to
allow daisy chaining of the 12C cables to
facilitate a multiple board configuration.
Because the state of the 12C bus is not
necessarily known upon reset, the 12C
interface should be disconnected when
resetting the board via the microcontroller.
The subaddress settings given are suggested
initial values; consult the individual data
sheets to manipulate the user-adjustable
controls such as contrast, brightness,
aperture control, color transient improvement
settings, etc.
Performance tests of the SAA7199B using
the Tektronix VM700A Video Measurement
Test Set were made using the D1 demo
Board, and results published in a document
titled "SAA7199 Performance
Measurements." This .document is published
as a separate data sheet.
Philips Semiconductors Video Products
Application note
Digital video evaluation board
Active video line
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Figure 1. Data Format Comparison
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268 words
4 words
1400 words
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Video
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Ancillary data
SOV
Video
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Total hne = 1715 words
Horizontal blanking
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Figure 2. Active Video Markers for 01 Video
April 12, 1993
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Application note
eV8S output filter for SAA71998 encoder
Author: George Ellis
OVERVIEW
THE FILTER
Peak performance of the SAA7199B can be
obtained by the use of an output filter
connected between the CVBS output of the
device and the output connector. This filter
provides sin(x)/x equalization for the CVBS
(composite video) signal.
The filter is illustrated in Figure 4. It is a
modified low pass filter with components
added to provide sin(x)/x equalization (C1,
L 1, and R2). Sin(x)/x attenuation is
calculated by the formula
THEORY
Sin(x)/x attenuation occurs with all DACs
(digital-to-analog convertors) due to the
sampling clock. This attenuation increases
as the output frequency of the DAC increases
and reaches total attenuation when the DAC
output is equal to the sample frequency (see
Figure 1.)
Another result of clocking the DAC is the
creation of energy which is centered at
multiples of the sample frequency fs and has
a bandwidth of 2(fs-fv), where fv is the
highest frequency of the output signal (see
Figure 2). This non-baseband energy is
referred to as 'aliasing', and if fs is less than
twice the frequency of fv. this aliasing will
extend into the baseband signal. This is not
desirable because it produces visible
corruption of the video signal.
The requirements of the filter, therefore, are
that 1) it provides sufficient attenuation at
frequencies above fv and 2) it applies the
appropriate inverse sin(x)/x boost at
frequencies below fv. Figure 3 shows an
example of this filter requirement as a graph
of gain versus frequency.
April 13, 1993
where fx is the frequency in question. The
number mifs is in radians, before calculating
the sin .. This number should be converted to
degrees (there are 57.29 degrees per one
radian).
In this case, attenuation was calculated for
3.58 MHz and 4.43 MHz, the color subcarrier
frequencies for NTSCand Pal, respectively.
A(3.58 MHz) = .881
A(4.43 MHz)
= .834
The attenuation in decibels can be calculated
from the formula:
dB = 2010g(A(x))
This gives a value of -1.04 dB down for 3.58
MHz and a value of -1.57 dB down for 4.433
MHz. The filter, therefore, must provide a
boost of 1.04 dB at 3.58 MHz, and of 1.57 dB
at 4.433 MHz.
Figure 5 is a plot of the filter ranging from
1 MHz to 100 MHz and from 0 dB to -50 dB
down, and Figure 6 shows the same
2-157
frequency spread and a gain range from 0 dB
to -20 dB to better illustrate the sin(x)/x
correction.
Starting with a gain value of -6 dB (as would
be expected for the 50% DC signal drop
across the termination resistor), it can be
seen that at a frequency of 3.58 MHz the gain
is -5 dB, and at 4.43 MHz the gain is -4.5
dB, a boost of 1 dB and 1.5 dB, respectively,
as required (see Figure 6). Figure 5 shows
an attenuation of -22 dB at 8 MHz, -40 dB at
9 MHz, and a value of -43 dB at 13 MHz (the
clock frequency).
Many different filters can be made to meet
the sin(x)/x requirement. This filter was
chosen to provide augmentation up through
the Pal subcarrier region. A filter with a cutoff
at lower frequencies could be designed for
use with NTSC only. This filter was also
chosen for economic reasons, and more
expensive filters could certainly be deSigned
with improved performance. This filter was
found to have a good performance to cost
ratio and can be made from standard
component values and 5% tolerance parts.
If large capacitive loads are expected to be
encountered, it may be desirable to buffer the
output filter with a high speed op amp. If this
is the case, the filter should be terminated
with a 75 n load at the input of the op amp.
The op amp should be operated in
non-inverting mode with a gain of two.
Philips Semiconductors Video Products
Application note
CV8S output filter for SAA71998 encoder
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April 13, 1993
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1) +1.04 dB AT 3.58 MHz
2) +1.58 dB AT 4.43 MHz
PHILIPS SEMICONDUCTORS
GEORGE ELLIS
Title
CVBS OUTPUT FILTER
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Philips Semiconductors Video Products
Application note
SAA 1101 sync generator application
LOCK TO SUBCARRIER
The SAA1101 can be configured to run in a
mode in which the output pulses are locked
to a subcarrier signal that is either internally
generated (as shown here), or can be applied
as an AC coupled, low level input to pin 1.
The internal clock oscillator is used here with
the frequency selected to be 2.517482MHz
(CSO and CS1 = 0). Remember that for
different choices of oscillator frequency, the
LC values of the tank circuit (L 1 and C11) will
change accordingly.
The NTSel system is selected in this
example; all outputs are active HIGH (see
waveforms shown in data Sheets).
LOCK TO EXTERNAL
COMPOSITE SYNC
This schematic illustrates a lock to external
sync application that uses an external PLL to
generate a clock that is optimized for stability.
Monostables are added to the reference and
variable phase detector inputs to allow
offsetting the sync outputs with respect to the
composite sync input signal.
As above, the NTSC1 standard and
2.517482MHz clock are selected. The use of
an external PLL (the HC4046) along with
optimized loop filters and stable discrete
components, produces a very stable clock (5
percent, or better, resistors and COG
capacitors are recommended).
The lock mode selection is not critical in this
application because the internal oscillator is
not used; LMO and LM1 are grounded for
convenience. The subcarrier input at pin 1 is
used as an inverter for the output of the sync
stripper before it is fed to the ESC input (pin
11), which requires an active HIGH signal.
Either pot R4 or pot RS will move the
generated sync output relative to sync in,
therefore, only one need be adjustable. Pot
R11 is used to adjust the oscillator free-run
frequency. R10, pot R11, and C9 must be
temperature stable parts for oscillator
frequency stability over temperature.
The outputs of the SAA 1101 are active HIGH
signals which can directly drive inverting
buffers for use as conventional active LOW
drivers.
ACTIVE NEGITIVE TTL COMPOSITE SYNC
(FROM SYNC STRIPPER OR OHlER DEVICE)
NOTE:
PIN 81SVSS AND
PIN 16 IS VCCf"OR ALl.
IC'SEXCEPTSAA1101
NOT£:EITHERR40RR8WILLPOSITION
THE OUTPUT SYNC TO THE RIGHT OR LEF"T
WITH RESPECT
TO THE INPUT
SYNC.
ONLY
ONE OR THE OTHER NEEC 8E ADJUSTED
LOCK TO EXTERNAL 5YNC
LOCK TO 5UBCARRIER
April 8, 1993
2-162
Philips Semiconductors Video Products
The 12C-bus and how to use it
(including specification)
1.0 THE 12C-BUS BENEFITS
DESIGNERS AND
MANUFACTURERS
In consumer electronics, telecommunications
and industrial electronics, there are often
many similarities between seemingly
unrelated designs. For example, nearly every
system includes:
• Some intelligent control, usually a
single-chip microcontroller
• General-purpose circuits like LCD drivers,
remote 1/0 ports, RAM, EEPROM, or data
converters
• Application-oriented circuits such as digital
tuning and signal processing circuits for
radio and video systems, or DTMF
generators for telephones with tone dialling
To exploit these similarities to the benefit of
both systems designers and equipment
manufacturers, as well as to maximize
hardware efficiency and circuit simplicity,
Philips developed a simple bidirectional
2-wire bus for efficient inter-IC control. This
bus is called the Inter IC or 12C-bus. At
present, Philips' IC range includes more than
150 CMOS and bipolar 12C-bus compatible
types for performing functions in all three of
the previously mentioned categories. All
12C-bus compatible devices incorporate
an on-Chip interface which allows them
to communicate directly with each other via
the 12C-bus. This design concept solves the
many interfacing problems encountered when
designing digital control circuits.
Here are some of the features of the 12C-bus:
• Only two bus lines are required; a serial
data line (SDA) and a serial clock line
(SCL)
• Each device connected to the bus is
software addressable by a unique address
and simple masterl slave relationships
exist at all times; masters can operate as
master-transmitters or as master-receivers
• It's a true multi-master bus including
collision detection and arbitration to
prevent data corruption if two or more
masters simultaneously initiate data
transfer
data line to preserve data integrity
• The number of ICs that can be connected
to the same bus is limited only by a
maximum bus capacitance of 400 pF
Figure 1 shows two examples of 12C-bus
applications.
1.1 Designer Benefits
12C-bus compatible ICs allow a system
design to rapidly progress directly from a
functional block diagram to a prototype.
Moreover, since they 'clip' directly onto the
12C-bus without any additional external
interfacing, they allow a prototype system to
be modified or upgraded simply by
'clipping' or 'unclipping' ICs to or from the
bus.
Here are some of the features of 12C-bus
compatible ICs which are particularly
attractive to designers:
• Functional blocks on the block diagram
correspond with the actuallCs; designs
proceed rapidly from block diagram to final
schematic
• No need to design bus interfaces because
the 12C-bus interface is already integrated
on-chip
• Integrated addressing and data-transfer
protocol allow systems to be completely
software-defined
• The same IC types can often be used in
many different applications
• Design-time reduces as designers quickly
become familiar with the frequently used
functional blocks represented by 12C-bus
compatible ICs
• ICs can be added to or removed from a
system without affecting any other circuits
on the bus
• Fault diagnosis and debugging are simple;
malfunctions can be immediately traced
• Software development time can be
reduced by assembling a library of
reusable software modules.
• Serial, 8-bit oriented, bidirectional data
transfers can be made at up to 100 kbiVs
in the standard mode or up to 400 kbiVs in
the fast mode
In addition to these advantages,the CMOS
ICs in the 12C-bus compatible range offer
designers special features which are
particularly attractive for portable equipment
and battery-backed systems.
They all have:
• Extremely low current consumption
• On-Chip filtering rejects spikes on the bus
• High noise immunity
January 1992
2-163
• Wide supply voltage range
• Wide operating temperature range.
1.2 Manufacturer benefits
12C-bus compatible ICs don't only assist
designers, they also give a wide range
of benefits to equipment manufacturers
because:
• The simple 2-wire serial1 2C-bus minimizes
interconnections so ICs have fewer pins
and there are not so many PCB tracks;
result - smaller and less expensive PCBs
• The completely integrated 12C-bus protocol
eliminates the need for address decoders
and other 'glue logic'
• The multi-master capability of the 12C-bus
allows rapid testing and alignment of
end-user equipment via external
connections to an assembly-line computer
• The availability of 12C-bus compatible ICs
in SO (small outline), VSO (very small
outline) as well as OIL packages reduces
space reqUirements even more.
These are just some of the benefits.
In addition, 12C-bus compatible ICs increase
system design flexibility by allowing simple
construction of equipment variants and easy
upgrading to keep designs up-to-date. In this
way, an entire family of equipment can be
developed around a basic model. Upgrades
for new equipment, or enhanced-feature
models (Le. extended memory, remote
control, etc.) can then be produced simply by
clipping the appropriate ICs onto the bus. If a
larger ROM is needed, it's simply a matter of
selecting a microcontroller with a larger ROM
from our comprehensive range. As new ICs
supersede older ones, it's easy to add new
features to equipment or to increase its
performance by simply unclipping the
outdated IC from the bus and clipping on its
successor.
1.3 The ACCESS. bus
Another attractive feature of the 12C-bus for
deSigners and manufacturers is that its
simple 2-wire nature and capability of
software addressing make it an ideal platform
for the ACCESS.bus (Fig.2). This is a
lower-cost alternative for an RS-232C
interface for connecting peripherals to a host
computer via a simple 4-pin connector (see
Section 19).
Philips Semiconductors Video Products
The 12C-bus and how to use it
(including specification)
SOA
SCL
SOA
SCL
(b)
Figure 1. Two Examples of 12C-Bus Applications: a) A High Performance Highly Integrated TV Set; b) Cellular Radio Chip Set
Table 1. Definition of 12C-8us Terminology
Description
Term
Transmitter
The device which sends the data to the bus
Receiver
The device which receives the data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a transfer
Slave
The device addressed by a master
Multi-master
More than one master can attempt to control the bus at the same time without corrupting the message
Arbitration
Procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so
and the message is not corrupted
Synchronization
Procedure to synchronize the clock signals of two or more devices
January 1992
2-164
Philips Semiconductors Video Products
The 12C-bus and how to use it
(including specification)
Figure 2. The ACCESS.bus - A Low-Cost Alternative to an RS-232C Interface
MICRO·
CONTROLLER
A
SD"
SCL
MICRO·
CONTROLLER
8
Figure 3. Examples of an 12C-Bus Configuration Using Two Microcontrollers
2.0 INTRODUCTION TO THE
12C-8US SECIFICATION
For a-bit digital control applications, such as
those requiring microcontrollers, certain
design criteria can be established:
• A complete system usually consists of at
least one microcontroller and other
peripheral devices such as memories and
I/O expanders
• The cost of connecting the various devices
within the system must be minimized
• A system that performs a control function
doesn't require high-speed data transfer
• Overall efficiency depends on the devices
chosen and the nature of the
interconnecting bus structure.
In order to produce a system to satisfy these
criteria, a serial bus structure is needed.
Although serial buses don't have the
throughput capability of parallel buses, they
do require less wiring and fewer IC
connecting pins. However, a bus is not
merely an interconnecting wire, it embodies
all the formats and procedures for
communication within the system.
Devices communicating with each other on a
serial bus must have some form of protocol
which avoids all possibilities of confusion,
data loss and blockage of information. Fast
devices must be able to communicate with
slow devices. The system must not be
dependent on the devices connected to it,
January 1992
otherwise modifications or improvements
would be impossible. A procedure has also to
be devised to decide which device will be in
control of the bus and when. And, if different
devices with different clock speeds are
connected to the bus, the bus clock source
must be defined. All these criteria are
involved in the specification of the 12C-bus.
controlling the bus can be connected to it. As
masters are usually micro-controllers, let's
consider the case of a data transfer between
two microcontrollers connected to the
12C-bus (Fig.3). This highlights the
master-slave and receiver-transmitter
relationships to be found on the 12C-bus. It
should be noted that these relationships are
3.0 THE 12C-BUS CONCEPT
not permanent, but only depend on the
direction of data transfer at that time. The
transfer of data would proceed as fOllows:
The 12C-bus supports any IC fabrication
process (NMOS, CMOS, bipolar). Two wires,
serial data (SDA) and serial clock (SCl),
carry information between the devices
connected to the bus. Each device is
recognised by a unique address - whether
it's a microcontroller, LCD driver, memory or
keyboard interface - and can operate as
either a transmitter or receiver, depending on
the function of the device. Obviously an LCD
driver is only a receiver, whereas a memory
can both receive and transmit data. In
addition to transmitters and receivers,
devices can also be considered as masters
or slaves when performing data transfers
(see Table 1). A master is the device which
initiates a data transfer on the bus and
generates the clock signals to permit that
transfer. At that time, any device addressed
is considered a slave.
The 12C-bus is a multi-master bus. This
means that more than one device capable of
2-165
1. Suppose microcontroller A wants to send
information to microcontroller B:
- microcontroller A (master), addresses
microcontroller B (slave)
- microcontroller A (master-transmitter),
sends data to microcontroller B
(slave-receiver)
- microcontroller A terminates the transfer.
2. If microcontroller A wants to receive
information from microcontroller B:
- microcontroller A (master) addresses
microcontroller B (slave)
- microcontroller A (master-receiver)
receives data from microcontroller B
(slave-transmitter)
- microcontroller A terminates the transfer.
Even in this case, the master (microcontroller
A) generates the timing and terminates the
transfer.
The possibility of connecting more than one
microcontroller to the 12C-bus means that
Philips Semiconductors Video Products
The 12C-bus and how to use it
(including specification)
4.0 .GENERAL
CHARACTERISTICS
more than one master could try to initiate a
data transfer at the same time. To avoid the
chaos that might ensue from such an event an arbitration procedure has been developed.
This procedure relies on the wired-AND
connection of all 12C interfaces to the
12C-bus.
Both SDA and SCl are bidirectional lines,
connected to a positive supply voltage via a
pull-up resistor (see FigA);When the bus is
free, both lines are H1GH. The output stages
of devices connected to the bus must have
an open-drain or open-collector in order to
perform the wired-AND function. Data on the
12C-bus can be transferred at a rate up to
100 kbitls in the standard-mode, or up to
400 kbitls in the fast-mode. The number of
interfaces connected to the bus is solely
dependent on the bus capacitance limit of
400 pF.
If two or more masters try to put information
onto the bus, the first to produce a 'one' when
the other produces a 'zero' will lose the
arbitration. The clock signals during
arbitration are a synchronized combination of
the clocks generated by the masters using
the wired-AND connection to the SCl line
(for more detailed information concerning
arbitration see Section 7.0).
5.0 BIT TRANSFER
Generation of clock Signals on the 12C-bus is
always the responsibility of master devices;
each master generates its own clock Signals
when transferring data on the bus. Bus clock
signals from a master can only be altered
when they are stretched by a slow-slave
device holding-down the clock line, or by
another master when arbitration occurs.
Due to the variety of different technology
devices (CMOS, NMOS, bipolar) which can
be connected to the 12C-bus, the levels of the
logical '0' (lOW) and '1' (HIGH) are not fixed
and depend on the associated level of Voo(see Section 15.0 for Electrical
Specifications). One clock pulse is generated
for each data bit transferred.
during the HIGH period of the clock. The
HIGH or lOW state of the data line can only
change when the clock signal on the SCl line
is LOW (see Fig.5).
5.2 START and STOP Conditions
Within the procedure of the 12C-bus, unique
situations arise which are defined as START
and STOP conditions (see Fig.6).
A HIGH to lOW transition on the SDA line
while SCl is HIGH is one such unique case.
This situation indicates a START condition.
A lOW to HIGH transition on the SDA line
while SCl is HIGH defines a STOP condition.
START and STOP conditions are always
generated by the master. The bus is
considered to be busy after the START
condition. The bus is considered to be free
again a certain time after the STOP condition.
This bus free situation is specified in Section
15.0.
Detection of START and STOP conditions by
devices connected to the bus is easy if they
incorporate the necessary interfacing
hardware. However, microcontrollers with no
such interface have to sample the SDA line
at least twice per clock period in order to
sense the transition.
5.1 Data Validity
The data on the SDA line must be stable
+Voo
Rp
pull up
Rp
resistors
SDA (Serial Data Line)
SCl (Serial Clock Line)
r------ -----I
i
I
I
iSCLKNd
lOUT
II
I
I
! I
I
I
I
I
I
I
--I
--1
I
I
DATA
1
INI
SCllS-.
IN
1_ _ _ _ _ _ - - - - - - - - - - '
I
I SCLK
I
II_ _IN_ _ _ _ _ _ _ _ _ _ _ _ _ _ -.JI
DEVICE 2
DEVICE 1
Figure 4. Connection of 12C-Bus Devices to the 12C-Bus
i rt==::~
/i
I
I
I
I
I
---r.!r--\!
. t----r!j----,L -
SCL
I
I
(fala line
I change I
I
stable;
I oldala I
I
data valid
I allOwed I
Figure 5. ,Bit Transfer on the 12C-Bus
-1\ i
I
I
I
I
r=~::~
___
!
I
I
rr--I
I
~~
stop condilion
Figure 6. START and STOP Conditions
January 1992
2·166
__
Philips Semiconductors Video Products
The 12C-bus and how to use it
(including specification)
SDA
-S--1LW---A--A--,----y-y--~---rJ0+
-i
SCl
I
!
acknowledgement
signal from receiver
MSB
acknowledgement I'
signal from receiver I
i
i
!
!
!
!
.
I
Interrupt within receiver clock line held low while
!
i
I
b~e.compl~te.
j
interrups are
se,::i':~d"
:
I
I
~
~~,VnLJ!i
i S I 1 2 -- 7 8 9
'1
2
3 8
9
IPI
ACK
L ....,
ACK
L_.J
STOP CONDITION
START CONDITION
Figure 7. Data Transfer on the 12C-Bus
DATA OUTPUT
BY TRANSMITIER
DATA OUTPUT
BY RECEIVER
SCl FROM
MASTER
+!
:
r----v--\r_-_\I/
\j..-.L.---A--- A - - - /
:,
I
:
I
"~-"""\.:=J
I
I
I
acknowledge
-+--n
I I '-I 1 '-I
r-\'
r\
/\
8 "---1 9 ' - -
r-\
L~
2
L __ -.J
I
clock pulse for
acknowledgement
START CONDITION
Figure 8. Acknowledge on the 12C-Bus
I~,~ounting HIGH period
I
state
I
ClK1~-----?~
-"..
ClK21
counter
reset
I
\('
SCl~"-)_ _ __
Figure 9. Clock Synchronization During the Arbitration Procedure
6.0 TRANSFERRING DATA
6.1 Byte Format
Every byte put on the SDA line must be 8-bits
long. The number of bytes that can be
transmitted per transfer is unrestricted. Each
byte has to be followed by an acknowledge
bit. Data is transferred with the most
significant bit (MSB) first (Fig.7). If a receiver
can't receive another complete byte of data
until it has performed some other function, for
example servicing an internal interrupt, it can
hold the clock line SCL LOW to force the
transmitter into a wait state. Data transfer
then continues when the receiver is ready for
another byte of data and releases clock line
SCL.
In some cases, it's permitted to use a
different format from the 12C-bus format (for
CBUS compatible devices for example). A
message which starts with such an address
can be terminated by generation of a STOP
January 1992
condition, even during the transmission of a
byte. In this case, no acknowledge is
generated (see Section 9.1.3).
6.2 Acknowledge
Data transfer with acknowledge is obligatory.
The acknowledge-related clock pulse is
generated by the master. The transmitter
releases the SDA line (HIGH) during the
acknowledge clock pulse.
The receiver must pull down the SDA line
during the acknowledge clock pulse so that it
remains stable LOW during the HIGH period
of this clock pulse (Fig.8). Of course, set-up
and hold times (specified in Section 15) must
also be taken into account.
Usually, a receiver which has been
addressed is obliged to generate an
acknowledge after each byte has been
received, except when the message starts
with a CBUS address (see Section 9.1.3).
2-167
When a slave-receiver doesn't acknowledge
the slave address (for example, it's unable to
receive because it's performing some
real-time function), the data line must be left
HIGH by the slave. The master can then
generate a STOP condition to abort the
transfer.
If a slave-receiver does acknowledge the
slave address but, some time later in the
transfer cannot receive any more data bytes,
the master must again abort the transfer. This
is indicated by the slave generating the not
acknowledge on the first byte to follow. The
slave leaves the data line HIGH and the
master generates the STOP condition.
If a master-receiver is involved in a transfer, it
must signal the end of data to the slavetransmitter by not generating an acknowledge
on the last byte that was clocked out of the
slave. The slave-transmitter must release the
data line to allow the master to generate the
STOP condition.
Philips Semiconductors Video Products
The 12C-bus and how to use it
(including specification)
7.0 ARBITRATION AND CLOCK
GENERATION
time (tHD;STA) of the START condition which
results in a defined START condition to the
bus.
7.1 Synchronization
Arbitration takes place on the SDA line, while'
the SCL line is at the HIGH level, in such a
way that the master which transmits a HIGH
level, while another master is transmitting a
LOW level will switch off its DATA output
stage because the level on the bus doesn't
correspond to its own level.
All masters generate their own clock on the
SCL line to transfer messages on the
12C-bus. Data is only valid during the HIGH
period of the clock. A defined clock is
therefore needed for the bit-by-bit arbitration
procedure to take place.
Clock synchronization is performed using the
wired-AND connection of 12C interfaces to the
SCL line. This means that a HIGH to LOW
transition on the SCL line will cause the
devices concerned to start counting off their
LOW period and, once a device clock has
gone LOW, it will hold the SCL line in that
state until the clock HIGH state is reached
(Fig.9). However, the LOW to HIGH transition
of this clock may not change the state of the
SCL line if another clock is still within its LOW
period. The SCL line will therefore be held
LOW by the device with the longest LOW
period. Devices with shorter LOW periods
enter a HIGH wait-state during this time.
Arbitration can continue for many bits. Its first
stage is comparison of the address bits
(addressing information is in Sections 9.0
and 13.0). If the masters are each trying to
address the same device, arbitration
continues with comparison of the data.
Because address and data information on the
12C-bus is used for arbitration, no information
is lost during this process.
When all devices concerned have counted off
their LOW period, the clock line will be
released and go HIGH. There will then be no
difference between the device clocks and the
state of the SCL line, and all the devices will
start counting their HIGH periods. The first
device to complete its HIGH period will again
pull the SCL line LOW.
arbitration during the addressing stage, it's
possible that the winning master is trying to
address it. The losing master must therefore
switch over immediately to its slave-receiver
mode.
In this way, a synchronized SCL clock is
generated with its LOW period determined by
the device with the longest clock LOW
period, and its HIGH period
determined by the one with the shortest clock
HIGH period.
7.2 Arbitration
A master may start a transfer only if the bus
is free. Two or more masters may generate a
START condition within the minimum hold
A master which loses the arbitration can
generate clock pulses until the end of the
byte in which it loses the arbitration.
masters, there is no central master, nor any
order of priority on the bus.
Special attention must be paid if, during a
serial transfer, the arbitration procedure is still
in progress at the moment when a repeated
START condition or a STOP condition is
transmitted to the 12C-bus. If it's possible for
such a situation to occur, the masters
involved must send this repeated START
condition or STOP condition at the same
position in the form&t frame. In other words,
arbitration isn't allowed between:
- A repeated START condition and a data
bit
- A STOP condition and a data bit
- A repeated START condition and a
STOP condition.
7.3 Use of the Clock
Synchronising Mechanism as a
Handshake
If a master also incorporates a slave function
and it loses
Figure 10 shows the arbitration procedure for
two masters. Of course, more may be
involved (depending on how many masters
are connected to the bus). The moment there
is a difference between the internal data level
of the master generating DATA 1 and the
actual level on the SDA line, its data output is
switched off, which means that a HIGH
output level is then connected to the bus.
This will not affect the data transfer initiated
by the winning master.
Since control of the 12C-bus is decided solely
on the address and data sent by competing
In addition to being used during the
arbitration procedure, the clock
synchronization mechanism can be used to
enable receivers to cope with fast data
transfers, on either a byte level or a bit level.
On the byte level, a device may be able to
receive bytes of data at a fast rate, but needs
more time to store a received byte or prepare
another byte to be transmitted. Slaves can
then hold the SCL line LOW after reception
and acknowledgement of a byte to force the
master into a wait state until the slave is
ready for the next byte transfer in a type of
handshake procedure.
On the bit level, a device such as a
microcontroller without, or with only a limited
hardware 12C interface on-Chip can slow
down the bus clock by extending each clock
LOW period. The speed of any master is
thereby adapted to the internal operating rate
of this device.
transmitter 1 loses arb~ration
i~ _ _D~A..2. ..~D~ _ _ _ _ _
DATAl
DATA 2
SDA
SCL
Figure 10. Arbitration Procedure of Two Masters
January 1992
2-168
Philips Semiconductors Video Products
The 12C-bus and how to use it
(including specification)
- Master-transmitter transmits to
slave-receiver. The transfer direction
is not changed (Fig.12)
8.0 FORMATS WITH 7-SIT
ADDRESSES
Data transfers follow the format shown in
Fig.11. After the START condition (S), a slave
address is sent. This address is 7 bits long
followed by an eighth bit which is a data
direction bit (R/W) - a 'zero' indicates a
transmission (WRITE), a 'one' indicates a
request for data (READ). A data transfer is
always terminated by a STOP condition (P)
generated by the master. However, if a
master still wishes to communicate on the
bus, it can generate a repeated START
condition (Sr) and address another slave
without first generating a STOP condition.
Various combinations of read/write formats
are then possible within such a transfer.
NOTES:
1. Combined formats can be used, for
example, to conUol a serial memory.
During the first data byte, the internal
memory location has to be written. After
the START condition and slave address is
repeated, data can be transferred.
2. All decisions on auto-increment or
decrement of previously accessed
memory locations etc. are taken by the
designer of the device.
3. Each byte is followed by an
acknowledgement bit as indicated by the
A or A blocks in the sequence.
4. 12C-bus compatible devices must reset
their bus logic on receipt of a START or
repeated START condition such that they
all anticipate the sending of a slave
address.
- Master reads slave immediately after
first byte (Fig.13). At the moment of the
first acknowledge, the master-transmitter
becomes a master-receiver and the
slave·receiver becomes a
slave-transmitter. This acknowledge is
still generated by the slave. The STOP
condition is generated by the master
- Combined format (Fig.14). During a
change of direction within a transfer, the
START condition and the slave address
are both repeated, but with the R/W bit
reversed.
Possible data transfer formats are:
~W::::~::D-K:·:rrrr
SCrul'-'7\f\fV1-~7V:VV1-~~
:_~~ ~L-.JL..J
ST ART
ADDRESS
CONDITION
I
IL..J I
DATA
ACK
RIW
IL..J
ACK
DATA
ACK
:_~~
STOP
CONDITION
Figure 11. A Complete Data Transfer
~~f{~~f~~1f~]
~~@ A ~§S31NA [P]
L data transferred J
A
I
(n bytes + acknowledge)
'0' (write)
[2J
from master to slave
o
from slave to master
=
A acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
S = START condition
P = STOP condition
Figure 12. A Master-Transmitter Addresses a Slave Receiver With a 7-Bit Address. The Transfer Direction is not Changed
[~~~~f5~fH~S%¥6¥.~
A
I
I
DATA
L
(read)
[Aa
DATA
EW~jl
_I
data transferred
(n bytes + acknowledge)
Figure 13. A Master Reads a Slave Immediately After the First Byte
I
I
read or write
(nbyte.
+ackY
J
I
read or write
• ~:::~~dd;~~~~:I~~ge bits
depends on R/W bits.
Sr = repeated START condition
Figure 14. Combined Format
January 1992
J IIL
2-169
(nbyte.
I
+ack.)"
direction
of transfer
may change
at this point
Philips Semiconductors Video Products
The 12C-bus and how to use it
(including specification)
Table 2 Definition of Bits in the First Byte
Slave address
Rlbit
. Description
0000000
0
0000000
1
START byte
000000.1
X
CBUS address
0000010
X
Address reserved for different bus format
0000011
X
Reserved for future purposes
00001XX
X
Reserved for future purposes
11111XX
X
Reserved for future purposes
1111 OXX
X
1O-bit slave addressing
General call address
NOTES:
1. No device is allowed to acknowledge at the reception of the START byte.
.
..
2. The CBUS address has been reserved to enable the inter-mixing of CBUS compatible and 12C-bus compatible devices In the same system.
12C-bus compatible devices are not allowed to respond on reception of this address.
..
..
3. The address reserved for a different bus format is included to enable 12C and other protocols to be mixed. Only 12C-bus compatible devices
that can work with such formats and protocols are allowed to respond to this address.
9.0 7-BIT ADDRESSING
(see Section 13.0 for 10-Bit
Addressing)
The addressing procedure for the 12C-bus is
such that the first byte after the START
condition usually determines which slave will
be selected by the master. The exception is
the 'general call' address which can address
all devices. When this address is used, all
devices should, in theory, respond with an
acknowledge. However, devices can be
made to ignore this address. The second
byte of the general call address then defines
the action to be taken. This procedure is
explained in more detail in Section 9.1.1.
9.1 Definition of Bits in the First
Byte
The first seven bits of the first byte make up
the slave address (Fig.15). The eighth bit is
the LSB (least significant bit). It determines
the direction of the message. A 'zero' in the
least significant position of the first byte
means that the master will write information
to a selected slave. A 'one' in this position
means that the master will read information
from the slave.
When an address is sent, each device in a
system compares the first seven bits after the
START condition with its address. If they
match, the device considers itself addressed
by the master as a slave-receiver or
slave-transmitter, depending on the RfliI bit.
A slave address can be made-up of a fixed
and a programmable part. Since it's likely that
there will be several identical devices in a
system, the progr~irlmable part of the slave
address enables the maximum PQssible
number of such devices to be connected to
January 1992
the 12C-bus. The number of programmable
address bits of a device depends on the
number of pins available. For example, if a
device has 4 fixed and 3 programmable
address bits, a total of 8 identical devices can
be connected to the same bus.
The 12C-bu8 committee coordinates
allocation of 12C addresses. Further
information can be obtained from the Philips
representatives listed on the back -cover. Two
groups of eight addresses (OOOOXXX and
1111 XXX) are reserved for the purposes
shown in Table 2. The bit combination
11110XX of the slave address is reserved for
1O-bit addressing (see Section 13).
9.1.1 General Call Address
The general Call address is for addressing
every device connected to the 12C-bus.
However, if a device doesn't need any of the
data supplied within the general call
structure, it can ignore this address by not
issuing an acknowledgement. If a device
does require data from a general call
address, it will acknowledge this address and
behave as a slave-receiver. The second and
following bytes will be acknowledged by
every slave-receiver capable of handling this
data. A slave which cannot process one of
these bytes must ignore it by not
acknowledging. The meaning of the general
call address is always specified in the second
byte (Fig.1S).
There are two cases to consider:
• When the least significant bit B is a 'zero'
• When the least significant bit B is a 'one'.
When bit B is a 'zero';, the second byte has
the following definition:
2-170
- 00000110 (H'OS'). Reset and write
programmable part of slave address by
hardware. On receiving this 2-byte
sequence, all devices designed to
respond to the general call address will
reset and take in the programmable part
of their address. Precautions have to be
taken to ensure that a device is not
pulling down the SDA or SCL line after
applying the supply VOltage, since these
low levels would block the bus
- 00000100 (H'04'). Write programmable
part of slave address by hardware. All
devices which define the programmable
part of their address by hardware (and
which respond to the general call
address) will latch this programmable
part at the reception of this two byte
sequence. The device will not reset.
- 00000000 (H'OO'). This code is not
allowed to be used as the second byte.
Sequences of programming procedure are
published in the appropriate device data
sheets.
The remaining codes have not been fixed
and devices must ignore them.
When bit B is a 'one'; the 2-byte sequence is
a 'hardware general call'. This means that the
sequence is transmitted by a hardware
master device, such as a keyboard scanner,
which cannot be programmed to transmit a
. desired slave address. Since a hardware
master doesn't know in advance to which
device the message has to be transferred, it
can only generate this hardware general call
and its own address - identifying itself to the
system (Fig.17).
The seven bits remaining in the second byte
contain the address of the hardware master.
Philips Semiconductors Video Products
The 12C-bus and how to use it
(including specification)
This address is recognised by an intelligent
device (e.g. a microcontroller) connected to
the bus which will then direct the information
from the hardware master. If the hardware
master can also act as a slave, the slave
address is identical to the master address.
In some systems, an alternative could be that
the hardware master transmitter is set in the
slave-receiver mode after the system reset.
In this way, a system configuring master can
tell the hardware master-transmitter (which is
MSB
now in slave-receiver mode) to which
address data must be sent (Fig.18). After this
programming procedure, the hardware
master remains in the master-transmitter
mode.
LSB
~
slave address
--.-J
Figure 15. The First Byte After the START Procedure
lololololololololAlxlxlxlxlxlxlxl~IAI
~
~ ~ second byte -.~
lirst byte
(general call address)
Figure 16. General Call Address Format
Figure 17. Data Transfer From a Hardware Master-Transmitter
s
write
a. Configuring master sends dump address to hardware master
writ~
L- -- _______1
Cn bytes + ack.)
b. Hardware master dumps data to selected slave
Figure 18. Data Transfer by a Hardware-Transmitter Capable of Dumping Data Directly to Slave Devices
January 1992
2-171
Philips Semiconductors Video Products
The 12C-bus and how to use it
(including specification)
r-l
~-l
I
II
SDAi"\1 I
~I
~
. .L -_ _ _ _---.,._ _ ,.. ----.l
ack,,"~~;~ge
I liI I
(HIGH)
I I
I
SCL
I
TI\
I 1U
L~J
!,\ r;\
. U
L
\...
r;\
__
..1 ' U
fa\
t;\
~ U
~ U
ACK
I I
~
I I
L~J
1·--- start byte 00000001 - I
Figure 19. START Byte Procedure
rl
L.-...I'-----'L--I'--...lI...---"-----.J\===~
SDA
I
I
---~
SCL
I I
I I
I
I
DLEN -l-I-I-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---l
L~J
lSI,
START
condition
CBUS
address
RfW
ACK
bit
related
clock pulse
n -data bits
CBUS
load pulse
STOP
condnion
Figure 20. Data Format of Transmissions with CBUS TransmitteriReceiver
9.1.2 START byte
Microcontrollers can be connected to the
12C-bus in two ways. A microcontroller with
an on-chip hardware 12C-bus interface can be
programmed to be only interrupted by
requests from the bus. When the device
doesn't have such an interface, it must
constantly monitor the bus via software.
Obviously, the more times the microcontroller
monitors, or polls the bus, the less time it can
spend carrying out its intended function.
transmitted by a master which requires bus
access, the START byte (00000001) is
transmitted. Another microcontroller can
therefore sample the SOA line at a low
sampling rate until one of the seven zeros in
the START byte is detected. After detection
of this LOW level on the SDA line, the
microcontroller can switch to a higher
sampling rate to find the repeated START
condition Sr which is then used for
synchronization.
There is therefore a speed difference
between fast hardware devices and a
relatively slow microcontroller which relies on
software pOlling.
A hardware receiver will reset on receipt of
the repeated START condition Sr and will
therefore ignore the START byte.
In this case, data transfer can be preceded
by a start procedure which is much longer
than normal (Fig.19). The start procedure
consists of:
- A START condition (S)
- A START byte (00000001)
An acknowledge-related clock pulse is
generated after the START byte. This is
present only to conform with the byte
handling format used on the bus. No device
is allowed to acknowledge the START byte.
- An acknowledge clock pulse (ACK)
- A repeated START condition (Sr).
After the START condition S has been
January 1992
9.1.3 CBUS Compatibility
CBUS receivers can be connected to the
12C-bus. However, a third bus line called
OLEN must then be connected and the
2-172
aCknowledge bit omitted. Normally, 12C
transmissions are sequences of 8-bit bytes;
CBUS compatible devices have different
formats.
In a mixed bus structure, 12C-bus devices
must not respond to the CBUS message. For
this reason, a special CBUS address
(0000001 X) to which no 12C-bus compatible
device will respond, has been reserved. After
transmission of the CBUS address, the OLEN
line can be made active and a CBUS-format
transmission (Fig.20) sent. After the STOP
condition, all devices are again ready to
accept data.
Master-transmitters can send CBUS formats
after sending the CBUS address. The
transmission is ended by a STOP condition,
recognised by all devices.
NOTE: If the CBUS configuration is known,
and expansion with CBUS compatible
devices isn't foreseen, the designer is
allowed to adapt the hold time to the specific
requirements of the device(s) used.
Philips Semiconductors Video Products
The 12C-bus and how to use it
(including specification)
10.0 ELECTRICAL
CHARACTERISTICS FOR 12C-BUS
DEVICES
The electrical specifications for the liDs of
12C-bus devices and the characteristics of the
bus lines connected to them are given in
Tables 3 and 4 in Section 15.
12C-bus devices with fixed input levels of
1.5 V and 3 V can each have their own
appropriate supply voltage. Pull-up resistors
must be connected to a 5 V ± 10% supply
(Fig.21). 12C-bus devices with input levels
related to V DO must have one common
supply line to which the pull-up resistor is
also connected (Fig.22).
Input levels are defined in such a way that:
- The noise margin on the LOW level is
0.1 Voo
- The noise margin on the HIGH level is
0. 2VOO
When devices with fixed input levels are
mixed with devices with input levels related to
V DO, the latter devices must be connected to
one common supply line of 5 V ± 10% and
must have pull-up resistors connected to their
SDA and SCL pins as shown in Fig.23.
- As shown in Fig.24, series resistors (Rs)
of e.g. 300 Q can be used for protection
against high-voltage spikes on the SDA
and SCL lines (due to flash-over of a TV
picture tube, for example).
V002,3 are device dependent (e.g., 12V)
VOOI·SV±IO'Yo
V002
V003
V004
Rp
SOA
SCL
Figure 21. Fixed Input Level Devices Connected to the 12C-Bus
VOO =e.g.3V
Ap
SOA
SCL
Figure 22. Devices with Wide Supply Range Connected to the 12C-Bus
V002,3 are device dependent (e.g., 12V)
VOOI·
SV±IO'Yo
V002
V003
Ap
SOA
SCL
Figure 23. Devices with Input Levels Related to Voo (Supply V001)
Mixed with Fixed Input Level Devices (Supply V002 3) on the 12C-Bus
Voo
Voo
Figure 24. Series Resistors (RS) for Protection Against High-Voltage Spikes
January 1992
2-173
Philips Semiconductors Video Products
The 12C-bus and how to use it
(including specification)
10.1 Maximum and minimum
values of resistors Rp and Rs
• A fast-mode which allows a fourfold
increase of the bit rate to 0 to 400 kbitls
Ap max as a function of bus capacitance.
The maximum HIGH level input current of
each inputloutput connectiori has a specified
maximum value of 10 IJA. Due to the desired
noise margin of 0.2Voo for the HIGH level,
this input current limits the maximum value of
Ap. This limit depends onVoo. The total
HIGH level input current is shown as a
function of Ap max in Fig.2B.
For standard-mode 12C-bus devices, the
values of resistors Ap and As in Fig.24
depend on the following parameters:
- Supply voltage
- Bus capacitance
- Number of connected devices (input
current + leakage current).
• 10-bit addressing which allows the use of
up to 1024 additional addresses.
There are two reasons for these extensions
to the 12C-bus specification:
- New applications will need to transfer a
larger amount of serial data and will
there.fore demand a higher bit rate than
100 kbitls. Improved Ie manufacturing
technology now allows a fourfold speed
increase without increasing the
manufacturing cost of the interface
circuitry
The supply voltage limits the minimum value
of resistor Ap due
to the specified minimum sink current of 3 rnA
at VOLmax = 0.4 V for the output stages. Voo
as a function of Ap min is shown in Fig.25.
The desired noise margin of 0.1 V00 for the
LOW level, limits the maximum value of As.
As max as a function of Ap is shown in
Fig.26.
The bus capacitance is the total capacitance
of wire, connections and pins. This
capacitance limits the maximum value of Ap
due to the specified rise time. Fig.27 shows
11.0 EXTENSIONS TO THE
12C-BUS SPECIFICATION
The 12C-bus with a data transfer rate of up to
100 kbitls and 7-bit addressing has now been
in existence for more than ten years with an
unchanged specification. The concept is
accepted world-wide as a de facto standard
and hundreds of different types of 12C-bus
compatible ICs are available from Philips and
other suppliers. The 12C-bus specification is
now extended with the following two features:
- Most of the 112 addresses available with
the 7-bit addressing scheme have been
issued more than once. To prevent
problems with the allocation of slave
addresses for new devices, it is
desirable to have more address
combinations. About a tenfold increase
of the number of available addresses is
obtained with the new 1O-bit addressing.
10
Y
Vsv
LL ~
I
Rp(kO)
minimum
value Rp
(kO)
VOO-2.5V
I
/
/
II
J
I
o
o
/
/
V. .-;'5 V
/ 1/
; ' 10V
i
400
800
voo(v)
1?00
1600
maximum value Rs (0)
Figure 25. Minimum Value of Rp as a Function of
Supply Voltage with the Value of Rs as a Parameter
Figure 26. Maximum Value of Rs as a Function of
the Value of Rp with Supply Voltage as a Parameter
~o
minimum
value Rp
(kO)
/:V
/
/'
minimum
value Rp
(kO)
i
16
1-+t+-+----\-\-+----+----+----+----+_+-----1
l\
1\\
12
\\
' \ .... RS-O·
~
I--ma,.
R~f j':::~
f"=:: ~ I:=:::::,
@VOD=5V I
o
I
o
80
200
Figure 27. Maximum Value of Rp as a Function of
Bus Capacitance for a Standard-Mode 12C-Bus
January 1992
120
?OO
total high level input current
buscapacitance (pF)
!IiA)
Figure 28. Total HIGH Level Input Current as a Function of
the Maximum Value of Rp with Supply Voltage as a Parameter
2-174
Philips Semiconductors Video Products
The 12C-bus and how to use it
(including specification)
All new devices with an 12C-bus interface are
provided with the fast-mode. Preferably, they
should be able to receive and/or transmit at
400 kbitls. The minimum requirement is that
they can synchronize with a 400 kbitls
transfer; they can then prolong the lOW
period of the SCl signal to slow down the
transfer. Fast-mode devices must be
downward-compatible which means that they
must still be able to communicate with 0 to
100 kbitls devices in a 0 to 100 kbitls
12C-bus system.
Obviously, devices with a 0 to. 100 kbitls
12C-bus interface cannot be incorporated in a
fast-mode 12C-bus system because, since
they cannot follow the higher transfer rate,
unpredictable states of these devices would
occur.
Slave devices with a fast-mode 12C-bus
interface can have a 7 -bit or a 1O-bit slave
address. However, a 7-bit address is
preferred because it is the cheapest solution
in hardware and it results in the shortest
message length. Devices with 7 -bit and 1O-bit
addresses can be mixed in the same 12C-bus
system regardless of whether it is a 0 to
100 kbitls standard-mode system or a 0 to
400 kbitls fast-mode system. Both existing
and future masters can generate either 7-bit
or 1O-bit addresses.
12.0 FAST-MODE
In the fast-mode of the 12C-bus, the protocol,
format, logic levels and maximum capacitive
load for the SDA and SCl lines quoted in the
previous 12C-bus specification are
unchanged. Changes to the previous 12C-bus
specification are:
- The maximum bit rate is increased to
400 kbitls
- Timing of the serial data (SDA) and
serial clock (SCl) signals has been
adapted. There is no need for
compatibility with other bus systems
such as CBUS because they cannot
operate at the increased bit rate
- The inputs of fast-mode devices must
incorporate spike suppression and a
Schmitt trigger at the SDA and SCl
inputs
- The output buffers of fast-mode devices
must incorporate slope control of the
falling edges of the SDA and SCl
signals
- If the power supply to a fast-mode
device is switched off, the SDA and SCl
I/O pins must be floating so that they
don't obstruct the bus lines
- The external pull-up devices connected
to the bus lines must be adapted to
accommodate the shorter maximum
January 1992
permissible rise time for the fast-mode
12C-bus. For bus loads up to 200 pF, the
pull-up device for each bus line can be a
resistor; for bus loads between 200 pF
and 400 pF, the pull-up device can be a
current source (3mA max.) or a switched
resistor circuit as shown in Fig.37.
13.0 10-BIT ADDRESSING
The 1O-bit addressing does not change the
format in the 12C-bus specification. Using 10
bits for addressing exploits the reserved
combination 1111XXX for the first seven bits
of the first byte following a START (S) or
repeated START (Sr) condition as explained
in Section 9.1. The 1O-bit addressing does
not affect the existing 7-bit addressing.
Devices with 7-bit and 1O-bit addresses can
be connected to the same 12C-bus, and both
7 -bit and 1O-bit addressing can be used in a
standard-mode system (up to 100 kbitls) or a
fast-mode system (up to 400 kbitls).
Although there are eight possible
combinations of the reserved address bits
1111 XXX, only the four combinations
11110XX are used for 1O-bit addressing. The
remaining four combinations 11111 XX are
reserved for future 12C-bus enhancements.
13.1 Definition of Bits in the First
Two Bytes
The 1O-bit slave address is formed from the
first two bytes following a START condition
(S) or a repeated START condition (Sr).
The first seven bits of the first byte are the
combination 1111 OXX of which the last two
bits (XX) are the two most-significant bits
(MSBs) of the 10-bit address; the eighth bit of
the first byte is the R/W bit that determines
the direction of the message. A 'zero' in the
least significant position of the first byte
means that the master will write information
to a selected slave. A 'one' in this position
means that the master will read information
from the slave.
If the R/W bit is 'zero', then the second byte
contains the remaining 8 bits (XXXXXXXX) of
the 1O-bit address. If the RIW bit is 'one', then
the next byte contains data transmitted from
a slave to a master.
13.2 Formats with 10-bit
Addresses
Various combinations of read/write formats
are possible within a transfer that includes
1O-bit addressing. Possible data transfer
formats are:
- Master-transmitter transmits to
slave-receiver with a 10-bit slave
address. The transfer direction is not
changed (Fig.29). When a 10-bit
2-175
address follows a START condition,
each slave compares the first seven bits
of the first byte of the slave address
(11110XX) with its own address and
tests if the eighth bit (RNJ direction bit) is
O. It is possible that more than one
device will find a match and generate an
acknowledge (A 1). All slaves that found
a match will compare the eight bits of the
second byte of the slave address
(XXXXXXXX) with their own addresses,
but only one slave will find a match and
generate an acknowledge (A2). The
matching slave will remain addressed by
the master until it receives a STOP
condition (P) or a repeated START
condition (Sr) followed by a different
slave address
NOTES:
1. Combined formats can be used, for
example, to control a serial memory.
During the first data byte, the internal
memory location has to be written. After
the START condition and slave address is
repeated, data can be transferred.
2. All decisions on auto-increment or
decrement of previously accessed
memory locations etc. are taken by the
designer of the device.
3. Each byte is followed by an
acknowledgement bit as indicated by the
A or A blocks in the sequence.
4. 12C-bus compatible devices must reset
their bus logic on receipt of a START or
repeated START condition such that they
all anticipate the sending of a slave
address.
- Master-receiver reads slavetransmitter with a 10-bit slave
address. The transfer direction is
changed after the second RIW bit
(Fig.30). Up to and including
acknowledge bit A2, the procedure is the
same as that described for a
master-transmitter addressing a
slave-receiver. After the repeated
START condition (Sr), a matching slave
remembers that it was addressed
before. This slave then checks if the first
seven bits of the first byte of the slave
address following Sr are the same as
they were after the START condition (S),
and tests if the eighth (RIW) bit is 1. If
there is a match, the slave considers
that it has been addressed as a
transmitter and generates acknowledge
A3. The slave-transmitter remains
addressed until it receives a STOP
condition (P) or until it receives another
repeated START condition (Sr) followed
by a different slave address. After a
repeated START condition (Sr), all the
other slave devices will also compare
the first seven bits of the first byte olthe
slave address (1111 OXX) with their own
Philips Semiconductors Video Products
The 12C-bus and how to use it
(including specification)
time. The transfer direction is changed
after the second RIW bit
- Combined format. A master transmits
data to one slave and then transmits
data to another slave .(Flg.32). The
same master occupies the bus all the
time
- Combined format. 10-bit and 7-bit
addressing combined in one serial
addresses and test the eighth (RIW) bit.
However, none of them will be
addressed because RIW = 1. (for 10-bit
devices), or the 11110XX slave address
(for 7-bit devices) does not match)
- Combined format. A master transmits
data to a slave and then reads data
from the same slave (Fig.31). The
same master occupies the bus all the
, , I lOX X
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PCF8584
12C CONNECTOR
Figure 2. PCF8584 to 8OC31 Interface
Basic PCF8584/8031 Driver
Routines
In the listing section (page 2-188), some basic routines are shown. The routines are divided in two modules. The module ROUTINE
contains the driver routines and initialization
of the PCF8584. The module INTERR contains the interrupt handler. These modules
may be linked to a module with the user program that uses the routines in INTERR and
ROUTINE. In this application note, this module will be called USER. A description of
ROUTINE and INTERR follows.
Module ROUTINE
Routine Sendbyte (Lines 17-20)This routine sends the contents of the
accumulator to the PCF8584. The address is
such that AO =O. Which register is accessed
depends on the contents of ESD-ES2 of the
control register. The address of the PCF8584
April 1990
is in variable 'PCF8584'. This must have
been previously defined in the user program.
The DPTR is used as a pointer for
addressing the peripheral. If the address is
less than 255, then RO or R1 may be used as
the address pointer.
Routine Sendcontr (Lines 25, 26)This routine is similar to Sendbyte, except
that now AO =1. This means that the
contents of the accumulator are sent to the
control register S1 in the PCF8584.
Routine Readbyte (Lines 30-33)This routine reads a register in the PCF8584
with AO =o. Which register depends on ESO
-ES2 of the control register. The result of the
read operation is returned in the accumulator.
Routine Readcontr (Lines 37-39)This routine is similar to Readbyte, except
that now AO =1. This means that the
accumulator will contain the value of status
register S1 of the PCF8584.
Routine Start Lines (44-56)This routine generates a START-condition
and the slave address with a R/W bit. In line
44, the variable IIC_CNT is reset. This
variable Is used as a byte counter to keep
track of the number of bytes that are received
or transmitted. IIC_CNT is defined in module
INTERR.
Lines 45-46 increment the variable
NR_BYTES if the PCF8584 must receive
data. NR_BYTES is a variable that indicates
how many bytes have to be received or
transmitted. It must be given the correct value
in the USER module. Receiving or
transmitting is distinguished by the value of
the DIR bit. This must also be given the
correct value in the USER module.
Philips Semiconductors Video Products
Application Note
Interfacing the PCF8584 12C-bus controller
to 80C51 family microcontrollers
Then the status register of PCF8584 must be
read to check if the 12C bus is free. First the
status register must be addressed by giving
ESo- ES2 of the control register the correct
value (lines 47-48). Then the Bus Busy bit is
tested until the bus is free (lines 49-50). If
this is the case, the slave address is sent to
data register SO and the 12C_END bit is
cleared (lines 51-53). The slave address is
set by the user program in variable USER.
The LSB of the slave address is the RIW bit.
12C_END can be tested by the user program
whether an 12C reception/transmission is in
progress or not.
Next the START condition will be generated
and interrupt generation enabled by setting
the appropriate bits in control register S1.
(lines 54-55).
Now the routine will return back to the user
program and other tasks may be performed.
When the START condition, slave address
and RIW bit are sent, and the ACK is
received, the PCF8584 will generate an
interrupt. The interrupt routine will determine
if more bytes have to be received or
transmitted.
Routine Stop (Lines 59-62) Calling this routine, a STOP condition will be
sent to the 12C bus. This is done by sending
the correct value to control register S1 (lines
59- 61). After this the 12C_END bit is set, to
indicate to the user program that a complete
12C sequence has been received or
transmitted.
Routine 12C_lnit (Lines 65-76)This routine initializes the PCF8584. This
must be done directly after reset. Lines
67-70 write data to 'own address' register
SO'. First the correct address of SO' is set in
control register S1 (lines 67-68), then the
correct value is written to it (lines 69-70). The
value for SO' is in variable SLAVE_ADR and
set by the user program. As noted previously,
register SO' must always be the first register
to be accessed after reset, because the
PCF8584 now determines whether an
80Cxxx or 68xxx microcontroller is
connected. Lines 72-76 set the clock register
S2. The variable 12C_CLOCK is also set by
the user program.
to be transmitted.
NR_BYTES, IIC_CNT and SLAVE were
explained earlier. 12C_END and DIR are flags
that are used in the program. 12C_END
indicates whether an 12C transmission or
reception is in progress. DIR indicates
whether the PCF8584 has to receive or
transmit bytes. The interrupt routine makes
use of register bank 1.
The transmission part of the routine starts at
line 42. In lines 42-43, a check is made
whether IIC_CNT =NR_BYTES. If true, all
bytes are sent and a STOP condition may be
generated (lines 44-45).
Next the pointer for the internal RAM is
restored (line 46) and the byte to be
transmitted is fetched from the internal RAM
(line 47). Thenthis byte is sent to the
PCF8584 and the variables are updated
(lines 47-49). The interrupt routine is left and
the user program may proceed. The. receive
part starts from line ~5. First a check is made
if the next byte to be received is the last byte
(lines 56-59). If true the ACK must be
disabled when the last byte is received. This
is accomplished by resetting the ACK bit in
the control register S1 (lines 60-61r
Next the received byte may be read (line 62)
from data register SO. The byte will be
temporary stored in R4 (line 63). Then a
check is made if this interrupt was the first
after a START condition. Ifso, the byte read
has no meaning and the interrupt routine will
be left (lines 68-70). However by reading the
data register SO the next read cycle is
started.
If valid data is received, it will be stored in the
intemal RAM addressed by the value of
BASE (lines 71-73). Finally a check is made
if all bytes are received. If true, a STOP
condition will be sent (lines 75-78).
EXAMPLES
In the listing section (starting on page 8),
some examples are shown that make use of
the routines described before. The examples
are transmission of a sequence, reception of
12C data and an example that combines both.
Module INTERR
This module contains the 12C interrupt
routine. This routine is called every time a
byte is received or transmitted on the 12C
bus. In lines 12-15 RAM space for variables
is reserved.
The first example sends bytes to the PCD
8577 LCD driver on the OM 1016
demonstration board. Lines 7 to 10 define the
interface with the other modules and should
be included in every user program. Lines 14
to 16 define the segments in the user
module. It is completely up to the user how to
organize this.
BASE is the start address in the internal
80C51 RAM where the data is stored that is
received, or where the data is stored that has
Lines 24 and 28 are the reset and ihterrupt
vectors. The actual user program starts at
line 33. Here three variables are defined that
April 1990
2-187
AN425
are used in the 12C driver routines. Note that
PCF8584 must be an even address,
otherwise the wrong internal registers will be
accessed! Lines 37-42 initialize the interrupt
logic of the microcontroller. Next the
PCF8584 will be initialized (line 45).
The PCF8584 is now ready to transmit data.
A table is made in the routine at line 61. For
the PCD8577, the data is a control byte and
the segment data. Note that the table does
not contain the slave address of the LCD
driver. In lines 51-54, variables are made
ready to start the transmission. This consists
of defining the direction of the transmission
(DIR), the address where the data table
starts (BASE), the number of bytes to
transmit (NR_BYTES, without slave
address!) and the slave address (SLAVE) of
the 12C peripheral that has to be accessed.
In line 55 the transmission is started. Once
the 12C transmission is started, the user
program can do other tasks because the
transmission works on interrupts. In this
example a loop is performed (line 58). The
user can check the end of the transmission
during the other tasks, by testing the
12C_END bit regularly.
The second example program receives 2
bytes from the PCF8574P I/O expander on
the OM1 016 demonstration board. Until line
45 the program is identical to the transmit
routine because it consists of initialization
and variable definition. From line 48, the
variables are set for 12C reception. The
received bytes are stored in RAM area from
label TABLE. During reception, the user
program can do other tasks. By testing the
12C_END bit the user can determine when to
start processing the data in the TABLE.
The third example program displays time
from the PCF8583P clock/calendar/RAM on
the LCD display driven by the PCF8577. The
LED display (driven by SAA1064) shows the
value of the analog inputs of the AID
converter PCF8591. The four analog inputs
are scanned consecutively.
In this example, both transmit and recei.ve
sequences are implemented as shown in the
previous examples. The main clock part is
from lines 62-128. This contains the calls to
the 12C routines. From lines 135-160,
routines are shown that prepare the data to
be transmitted. Lines 171 to 232 are the main
program for the AD converter and LED
display. Lines 239 to 340 contain routines
used by the main program. This demo
program can also be used with the 12c
peripherals on the OM1016 demonstration
board.
Application Note
Philips Semiconductors Video Products
Interfacing the PCF8584 12C-bus controller
to 80C51 family microcontrollers
ASM51
LOC
TSW
ASSEMBLER
OBJ
Routines for PCF8584
LZNE
1
2
3
4
5
6
7
8
9
0000:
0000: 900000
0003: 1'0
0004: 22
0005:
0005: 900001
0008: 801'9
OOOA:
OOOA: 900000
OOOD: EO
OOOE: 22
0001':
0001': 900001
0012: '801'9
R
R
R
R
R
0014:
0017:
OOlA:
001C:
750000
200002'
0500
7440
R
R
R
001E:
0021:
0024:
0027:
0029:
002B:
002E:
120005
120001'
30EOFA
E500
C200
120000
744D
R
R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
SOURCE
$TZTLE (Routines for PCF8584)
$PAGELENGTH(40)
,Program written for PCF8584 as master
PUBLZC
PUBLZC
PUBLZC
EXTRN
EXTRN
EXTRN
READBYTE,READCONTR,SENDBYTE
SENDCONTR,START,STOP
UC_ZNZT
BZT(Z2C_END,DZR)
DATA(SLAVE,ZZC_CNT,NR_BYTES)
NUMBER(SLAVE_ADR,Z2C_CLOCK,PCF8584)
,Define code segment
ROUTZNE
SEGMENT CODE
RSEG
ROUTZNE
,SENDBYTE sends a byte to PCF8584 with AO=O
,Byte to be send must be in accu
SENDBYTE:
MOV DPTR,iPCF8584 ,Register address
SEND:
MOVX @DPTR,A
,Send byte
RET
,SENDCONTR sends a byte to PCF8584 with AO-l
,Byte to be send DlUst be in accu
SENDCONTR:
MOV DPTR,iPCF8584+01H ,Register address
.niP SEND
,READBYTE reads a byte from PCF8584 with AO=O
IReceived byte is stored in accu
READBYTE:
MOV DPTR,iPCF8584 ,Register address
REC:
MOVX A,@DPTR
,Receive byte
RET
,READCONTR reads a byte from PCF8584 with AO=l
,Received byte is stored in accu
READCONTR:
MOV DPTR,iPCF8584+01H IRegister address
.nIP REC
,START tests if the Z2C bus is ready. zf ready a
,START-condition will be sent, interrupt generation
land aclalowledge will be enabled.
START: MOV IIC_CNT,i.OO ;Clear 12C byte counter
JB DIK,PROCEED ,If DZR is 'receive' then
INC NR_BYTES
,increment NR_BYTES
PROCEED:NOV A,i40H
, Read STATUS register of
I
April 1990
R
R
R
48
49
SO
51
52
53
54
8584
CALL' SENDCONTR
TESTBB: CALL READCONTR
JNB ACC.O,TESTBB; Test BBI bit
NOV A,SLAVE
CLK Z2C_END
;Reset 12C ready bit
CALL SENDBYTE
;Send slave address
MOV A,#01001101B;Generate START, set ENI,
;set'ACK
2-188
AN425
Philips Semiconductors Video Products
Application Note
Interfacing the PCF8584 12C-bus controller
to 80C51 family microcontrollers
0030: 120005
0033: 22
003':
0036:
0039:
003B:
74C3
120005
D200
22
R
R
R
003C:
E'
003C:
003D: 120005
00'0: 7400
00'2: 120000
00'5:
0047:
OO'A:
004C:
00'1':
7420
120005
7400
120000
22
0050:
April 1990
R
R
R
R
R
R
55
56
57
58
59
60
61
62
63
6'
65
66
67
68
69
70
71
72
73
74
75
76
77
78
,
CALL SENDCON'l'R
RET
;STOP will generate a STOP condition and set the
;:I2C END bit
STOP:
MOV A,i11000011B
CALL SENDCON'l'R ; Send STOP condition
SETB :I2C_END
;Set :I2C_END bit
RET
;:I2C_init does the initialisation of the PCF8584
:I2C_:IN:IT:
;Write own slave address
CLR A
CALL SENDCON'l'R ;Write to control register
MOV A,iSLAVE_ADR
CALL SENDBYTE
;Write to own slave
; register
;Write clock register
MOV A,i20H
CALL SENDCON'l'R ;Write to control register
MOV A,i:I2C_CLOCK
CALL SENDBYTE
;Write to clock register
RET
END
2-189
AN425
Philips Semiconductors Video Products
Application Note
Int~rfacing the PCF8584 12C-bus control~er
to BOC51 family microcontrollers
ASM51
LOC
TSW
ASSEMBLER
OBJ
J:2C J:N'l'ERRUPT ROUTJ:NE
LJ:NE
1
2
3
4
5
6
7
0000:
R
0001:
0002:
0003:
0000:
0000
R
13
14
15
16
17
18
19
20
21
R
22
23
24
R
0000
8
9
10
11
12
25
26
27
28
0000:
0000:
0002:
0004:
0007:
R
COEO
CO DO
75D008
300016
R
OOOA: E502
R
OOOC:
OOO!':
0012:
0014:
0016:
0017:
0019:
001C:
001E:
R
B50105
120000
8032
A800
E6
0500
120000
0502
8026
April 1990
R
R
R
R
R
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
SO
51
SOURCE
$TJ:TLE (J:2C J:N'l'ERRUPT ROUTJ:NE)
$PAGELENGTH(40)
PUBLJ:C
PUBLJ:C
PUBLJ:C
EXTRN
EXTRN
J:N'l'O_SRV
DJ:R,J:2C_END
BASE,NR_BYTES,J:J:C_CN'l',SLAVE
COt)E (SENDBYTE, SENDCON'l'R, STOP)
CODE {READBYTE, READCON'l'R)
;
;Define variables in RAM
J:J:C_VAR /ilEGMEN'l' DA'l'A
BASE:
NR_BYTES: DS 1
J:J:C_CN'l':DS 1
SLAVE: DS 1
;Pointer to J:2C table (till
.;256)
;NUmber of ~es to rcv/tr.m
;J:2C byte counter
;Slave address after STAR'l'
; Define variable segment
BJ:T_VAR SEGMEN'l' DA'l'A BJ:'l'ADDRESSABLE
RSEG BJ:'l'_VAR
STATUS: DS 1
;Byte with flags
J:2C_END BJ:T STATUS.O
;Defines if a J:2C
;transmission is finished
;'1' is finished
;'0' is not ready
DJ:R
BJ:'l' S'l'ATUS.3
;Defines direction of J:2C
; transmission
; ' l' :'l'ransmit
'0' : Receive
;Define code segment for routine
J:J:C_J:NT SEGMEN'l' CODE PAGE
;Program uses registers in RBl
USJ:NG 1
PUSH ACC
;Save acc. en psw on stack
PUSH PSW
MOV PSW,108H
;Select register bank 1
JNB DJ:R,RECEJ:VE ;Test direction bit
;8584 is MST/TRM
;Program part to transmit bytes to J:J:C bus
MOV A,J:J:C_CN'l'
;Compare J:J:C_CN'l' and
;NR_BYTES
CJNE A,NR_BY'l'ES,PROCEED
CALL STOP
;All bytes transmitted
JMP EXJ:'l'
PROCEED:MOV RO,BASE
;RAM pointer
MOV A,@RO
;Source is internal RAM
J:NC BASE
;update pointer of table
CALL SENDBYTE
;Send byte to J:J:C bus
J:NC J:J:C_CN'l'
;update byte counter
JMP EXJ:T
2-190
AN425
Application Note
Philips Semiconductors Video Products
Interfacing the PCF8584 12C-bus controller
to 80C51 family microcontrollers
0020:
0020: E502
0022:
0023:
0024:
0027:
04
04
B50105
7448
R
R
52
53
54
55
56
57
58
59
60
0029: 120000
R
61
002C: 120000
002F: FC
R
62
63
64
65
66
0030: E4
0031: B50202
0034: 8006
0036:
0038:
0039:
003A:
003C:
A800
EC
F6
0500
0502
003E: E501
0040: B50203
0043: 120000
0046: DODO
0048: DOEO
004A: 32
004B:
April 1990
R
67
68
69
70
R
71
72
R
R
74
73
R
R
R
75
76
77
78
79
80
81
82
83
84
;Program to receive byte from IIC bus
RECEIVE:
NOV A,IIC_CNT
;Test i f last byte is to be
; received
INC A
INC A
CJNE A,NR_BYTES,PROC_RD
NOV A,#01001000B;Last byte to be received.
;Disable ACK
CALL SENDCONTR ;Write control word to
;PCF8584
PROC_RD:CALL READBYTE
;Read 12C byte
NOV R4,A
;Save accu
;If RECEIVE is entered after the transmission of
;START+address then the result of READBYTE is not
; relevant. READBYTE is used to start the generation
;of the clock pulses for the next byte to read.
;This situation occurs when IIC_CNT is
CLR A
;Test I IC_CNT
CJNE A,IIC_CNT,SAVE
JMP END_TEST
;START is send. No relevant
;data in data reg. of 8584
SAVE~
NOV RO,BASE
NOV A,R4
;Destination is internal RAM
NOV @RO,A
INC BASE
END_TEST: INC I IC_CNT
;Test if all bytes are
; received
NOV A,NR_BYTES
CJNE A, I IC_CNT, EXIT
CALL STOP
;All bytes received
EXIT:
POP psw
POP ACC
RETI
;Restore psw and accu
END
2-191
AN425
Philips Semiconductors Video Products
Application Note
Interfacing the PCF8584 12C-bus controller
to 80C51 family microcontrollers
ASM51
LOC
TSW
ASSEMBLER
Send a string of bytes to the PCF8577 on OM1016
LINE
OBJ
AN425
1
2
SOURCE
$TITLE (Send a string of bytes to the PCF8577 on
OM1016)
$PAGELENGTH(40)
3
4
5
iThis program is an example to transmit bytes via
iPCF8584
ito the 12C-bus
PUBLIC
EXTRN
EXTRN
EXTRN
7
8
SLAVE_ADR,I2C_CLOCK,PCF8584
CODE(I2C_INIT,INTO_SRV,START)
BIT(I2C_END,DIR)
DATA(BASE,NR_BYTES,IIC_CNT,SLAVE)
10
11
12
13
14
15
iDefine used segments
USER
SEGMENT CODE
RAMTAB SEGMENT DATA
16
RAMVAR
SEGMENT DATA
;Segment ~or user program
;Segment for table in
;internal RAM
;Segment for RAM variables
lin RAM
0000:
R
0000: 020000
R
0003: 020000
R
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
0055
001C
0000
0003:
0005:
0007:
0009:
33
34
35
36
38
D2A8
D2AF
D2B8
0288
39
40
41
OOOB: 120000
R
OOOE: 120021
R
April 1990
42
43
44
45
46
47
48
49
SO
STACK:
RSEG
OS 20
RAMVAR
CSEG AT OOH
JMP MAIN
CSEG AT 03H
JMP INTO_SRV
iReserve stack area
;Reset vector
;I2C interrupt vector
; (INTO/)
RSEG USER
;Define 12C clock, own slave address and PCF8584
ihardware address
SLAVE_ADR EQU 55H
;Own slave address is 55H
12C_CLOCK EQU 00011100B ;12.00MHz/90kHz
PCF8584
EQU OOOOH
;PCF8584 address with AO=O
;0000: 7581FF
R
37 MAIN:
MOV SP,#STACK-l ;Initialise stack pointer
;Initialise 8031 interrupt registers for 12C
; interrupt
SETB EXO
;Enable interrupt INTO/
SETB EA
;Set global enable
SETB PXO
;Priority level '1'
SETB ITO
;INTO/ on falling edge
;Initialise PCF8584
CALL 12C_INIT
;Make a table in RAM with data to be transmitted.
CALL MAKE_TAB
;Set variables to control PCF8584
2-192
Philips Semiconductors Video Products
Application Note
Interfacing the PCF8584 12C-bus controller
to 80C51 family microcontrollers
0011: 0200
0013: 750000
0016: 750005
R
R
R
51
52
53
0019: 750074
R
54
001C: 120000
R
001F: 80FE
55
56
57
58
LOOP:
0021:
0021: 7800
R
59
60
61
62
MAKE_TAB:
NOV RO,#TABLE
R
63
64
65
66
67
68
69
70
71
72
73
74
75
76
0023:
0025:
0026:
0028:
0029:
002B:
002C:
002E:
002F:
0031:
7600
08
76FC
08
7660
08
760A
08
76F2
22
0000:
SETB OIR
;OIR='tranamission'
NOV BASE,#TABLE ;Start address of I2C-data
NOV NR_BYTES,#05H ;5 bytes must be
; transferred
NOV SLAVE,#01110100B ;Slave address PCF8577
; + WR/
CALL START
;Start I2C transmission
JMPLOOP
1
NOV
INC
NOV
INC
NOV
INC
NOV
INC
NOV
OOOA:
April 1990
@RO,#OO
RO
@RO,#OFCH
RO
@RO,#60H
RO
@RO,#ODAH
RO
@RO,#OF2H
;Make data ready for I2C
; transmission
;Controlword PCF8577
; '0'
;'1'
;'2'
;'3'
RET
TABLE:
RSEG RAMTAB
OS 10
77
78
79
80
;Endless loop when program
; is finished
;Reserve space in internal
;data RAM
;for I2C data to transmit
END
2-193
AN425
Application Note
Philips Semiconductors Video Products
12 C-buscontroller
Interfacing the· PCF8584
to 80C51 family microcontrollers
ASM51
LOC
TSW
ASSEMBLER
OBJ
Receive 2 bytes from
LXNE
1
2
3
4
5
t~e
PCF8574P on
AN425
OMI0l~
SOURCE
$TXTLE (Receive 2 bytes from the PCF85,74P on OMI016)
$PAGELENGTH(40)
,This program is an example to receive bytes via
;PCF8584
;from the X2C-bus
6
7
8
9
PUBLXC
EXTRN
EXTRN
EXTRN
10
SLAVE_ADR,X2C_CLOCK,PCF8584
CODE(X2C_XNXT,XNTO_SRV,START)
BXT (X2C_END, DXR)
DATA(BASE,NR_BYTES,XXC_CNT,SLAVE)
11
12
13
14
15
;.
;Define used segments
USER
SEGMENT CODE
RAMTAB SEGMENT DATA
16
RAMVAR
SEGMENT DATA
;Segment for user program
;Segment for table in
;internal RAM
;Segment for RAM variables
lin RAM
0000:
R
0000: 020000
R
0003: 020000
R
17
18
19
20
21
22
23
24
25
26
27
28
STACK:
RSEG
DS 20
,Reserve stack area
CSEG AT OOH
JMP MAXN
,Reset vector
CSEG AT 03H
JMP XNTO_SRV
;X2C interrupt vector
(XNTO/)
1
29
30
31
32
33
34
35
36
38
0055
001C
0000
0003:
0005:
0007:
0009:
D2A8
D2AF
D2B8
D288
OOOB: 120000
R
OOOE:
0010:
0013:
0016:
R
R
R
R
C200
750000
750002
75004F
39
40
41
42
43
44
45
46
47
48
49
50
51
RSEG USER
;Define X2C clock, own slave address and PCF8584
,hardware address
SLAVE_ADR EQU 55H
;Own slave address is 55H
X2C_CLOCK EQU 00011100B ;12.00MHz/90kHz
PCF8584
EQU OOOOH
;PCF8584 address with AO=O
;0000: 7581FF
R
37 MAXN:
MOV SP,#STACK-l ;xnitialise stack pointer
;Xnitialise 8031 interrupt registers for X2C
; interrupt
SETB EXO
;Enable interrupt XNTOI
SETB EA
;Set global enable
SETB PXO
;Priority level '1'
SETB XTO
;XNTOI on falling edge
,
;Xnitialise PCF8584
;Set variables to control PCF8584
CLR DXR
; DXR='receive'
MOV BASE,#TABLE ;Start address of X2C-data
MOV NR_BYTES,#02H ;2 bytes must be received
MOV SLAVE,#01001111B ;Slave address PCF8574
; + RD
April 1990
2-194
Philips Semiconductors Video Products
Application Note
Interfacing the PCF8584 12C-bus controller
to 80C51 family microcontrollers
0019: 120000
R
52
CALL START
;Start X2C transmission
;Endless loop when program
lis finished
53
001C: 80FE
54
55
LOOP:
.JMPLooP
0000:
56
57
58
59
TABLE:
RSEG RAMTAB
DS 10
OOOA:
April 1990
R
60
61
62
63
;Reserve space in internal
;data RAM
;for received X2C data
END
2-195
AN425
Application Note
Philips Semiconductors Video Products
Interfacing the PCF8584 12C-bus controller
to 80C51 family microcontrollers
ASMS1
LOC
TSW
ASSEMBLER
OBJ
Demo program for PCFSSS4 I2C-routines
LINE
1
2
3
S
7
S
9
SOURCE
$TITLE (Demo program for PCFSSS4 I2C-routinea)
$PAGELENGTH(40)
;Program displays on the LCD display the time (with
;PCFSSS3). Dots on LCD display blink every second.
IOn the LED display the values of the successive
;ana1og input channels are shown.
;Program reads analog channels of PCFSS91P.
;Channe1 number and channel value are displayed
; successively.
;Va1ues are displayed on LCD and LED display on I2C
;demo board.
10
11
12
13
14
lS
16
... ,
lS
19
0000:
0014:
001S:
R
PUBLIC
EXTRN
EXTRN
EXTRN
SLAVE_ADR,I2C_CLOCK,PCFSSS4
CODE(I2C_INIT,INTO_SRV,START)
BIT(I2C_END,DIR)
DATA (BASE, NR_BYTES, I IC_CNT, SLAVE)
;D6fiila "'lIau. iiawwailtii
USER
SEGMENT CODE
RAMTAB
SEGMENT DATA
20
21
22
23
24
2S
RSEG RAMVAR
STACK: DS 20
PREVIOUS: DS 1
CHANNEL:DS 1
27
CONVAL: DS 3
RAMVAR
SEGMENT
DATA
0016:
0017 :
0000: 020000
R
0003: 020000
R
2S
29
30
31
32
33
34
3S
36
OOSS
001C
0000
3S
39
40
00A3
41
42
00A2
43
009F
U
009E
4S
April 1990
AN425
; Segment for user program
; Segment for table in
,internal RAM
; Segment for variables
;Stack area (20 bYtes)
;Store for previous seconds
,Channel number to be
; sampled
;Ana1og value sampled
; channel
;Converted BCD value sampled
; channel
CSEG AT OOH
LJMP MAIN
;Reset vector
CSEG AT 03H
LJMP INTO_SRV
;INTOI
;Vector I2C-interrupt
RSEG USER37 ;Define I2C clock, own slave address and address for
;main processor
SLAVE_ADR EQU SSH
;Own slaveaddress is SSh
I2C_CLOCK EQU 00011100B ;12.00MHz/90kHz
PCFSSS4
EQU OOOOH
;Address of PCFSSS4. This
;must be an EVEN number I I
;Define addresses of I2C peripherals
PCFSSS3R EQU 10100011B ;Address PCFSSS3 with Read
; active
PCFSSS3w EQU 10100010B ; Address PCFSSS3 with Write
; active
PCFSS91R EQU 10011111B ; Address PCFSS91 with Read
; active
PCFSS91W EQU 10011110B ; Address PCFSS91 with Write
; active
2-196
Application Note
Philips Semiconductors Video Products
Interfacing the PCF8584 12C-bus controller
to 80C51 family microcontrollers
ASM51
LOC
TSW
ASSEMBLER
OBJ
Demo program for PCF8584 12C-routines
LINE
SOURCE
0074
46
PCF8577W
0076
47
SAA1064W
R
48
49
50
OOOB: 120000
R
OOOE: 751500
R
51
52
53
54
55
56
57
58
59
60
61
0000: 7581FF
0003: D2A8
00~5: D2AF
0007: D2B8
0009: D288
0011:
0013:
0016:
0019:
001C:
001D:
R
62
63
64
65
66
67
001F: l!'501
R
68
0021: 120000
0024: 3000FD
R
R
69
70
0027:
0029:
002C:
002F:
0031:
0033:
0035:
0038:
R
003B:
003D:
0040:
0043:
0046:
0049:
D200
750000
750002
7500A2
E4
F500
D200
750000
7500A2
7401
F500
F500
120000
3000FD
C200
750000
750004
7500A3
120000
3000FD
004C: 7800
004E: 7902
0050: E6
April 1990
R
R
R
R
R
71
72
73
74
75
76
R
77
R
78
79
R
R
R
R
R
R
R
R
R
R
80
81
82
83
84
85
86
87
88
89
90
91
92
93
EQU 01110100B ;Address PCF8577 with Write
; active
EQU 01110110B ;Address SAA1064 with Write
; active
MAIN:
MOV SP,#STACK-1 ;Define stack pointer
;Initia1ise 80C31 interruptregisters for 12C
;interrupt (INTO/)
SETB EXO
;Enable interrupt INTO/
SETB' EA
;Set global enable
SETB PXO
;Priority level is '1'
SETB ITO
;INTO/ on falling edge
;Initialise PCF8584
CALL 12C_INIT
MOV CHANNEL,#OO ;Set AD-channel
;Time must be read from PCD8583.
;First write word address and control register of
;PCD8583.
SETB DIR
;DIR='transmission'
MOV BASE,#TABLE ;Start address 12C data
MOV NR_BYTES,#02H ;Send 2 bytes
MOV SLAVE,#PCF8583W
CLR A
MOV TABLE,A
;Data to be sent (word
; address) .
MOV TABLE+1,A
(control
; byte)
CALL START
;Start transmission.
FIN_1: JNB 12C_END,FIN_1 ;Wait till transmission
; finished
;Send word address before reading time
REPEAT: SETB DIR
;'transmission
MOV BASE,#TABLE ;I2C data
MOV SLAVE,#PCF8583W
MOV A,#Ol
MOV NR_BYTES,A ;Send 1 byte
MOV TABLE,A
;Data to be sent is '1'
CALL START
;Start 12C transmission
FIN_2: JNB 12C_END,FIN_2 ;Wait till transmission
; finished
;Time can now be read from PCD8583. Data read is
;hundredths of sec's, sec's, min's and hr's
CLR DIR
;DIR='receive'
MOV BASE,#TABLE ;I2C table
MOV NR_BYTES,#04; 4 bytes to receive
MOV SLAVE,#PCF8583R
CALL START
;Start 12C reception
FIN_3: JNB 12C_END,FIN_3 ;Wait till finished
;Transfer data to R2 ••• R5
MOV RO,#TABLE
;Set pointers
MOV R1,#02H
;Pointer R2
TRANSFER:MOV A,@RO
2-197
AN425
Philips Semiconductors Video Products
Application Note
Interfacing the PCF8584 12C-bus controller
to 80C51 family microcontrollers
ASM51
TSW
ASSEMBLER
LOC
OBJ
LINE
0051:
0052:
0053:
0054:
0057:
0058:
005A:
F7
08
09
0500F9
ED
543F
FD
94
95
96
97
98
99
100
101
102
103
104
R
105
005B: 7800
0050: 7600
005F: 08
R
106
107
108
110
0063: 430301
R
0066:
0067:
0068:
006A:
R
112
113
114
115
116
117
118
119
Demo program for PCF8584 I2C-routines
SOURCE
MOV @R1,A
INC RO
INC R1
DJNZ NR_BYTES,TRANSFER
MOV A,R5
;Mask of hour counter
ANL A,#3FH
MOV R5,A
;Data must now be displayed on LCD display.
;First minutes and hours (in R4 and R5) must be
;converted from BCD to LCD segment data. The segment
;data
;will be transferred to TABLE. RO is pointer to
; table
MOV RO,#TABLE
MOV @RO,#OOH
;Control word for PCF8577
INC RO 0060: 120080
R
109
CALL CONV
_ _ .!'II
0060:
0060:
006F:
0072:
0075:
0078:
EB
13
4003
430101
0200
750000
750005
750074
120000
R
007B: 3000FD
007E: 8026
R
R
R
R
R
0080: 90009C
R
0083: ED
0084: C4
0085: 120096
R
0088:
0089:
008C:
0080:
008E:
ED
120096
EC
C4
120096
April 1990
R
R
120
121
122
123
124
125
126
127
128
AN425
__ .l'
__ "
;Switch on dp betw66u hOurs allu. lI1.1. .l1\ll;.elJ
ORL TABLE+3,#01H
;If lsb of seconds is '0' then switch on dp.
MOV A,R3
;Get seconds
RRC A
;lsb in carry
JC PROCEED
ORL TABLE+1,#01H;switch on dp
;Now the time (hours,minutes) can be displayed on
;the LCD
PROCEED:
SETB DIR
;Direction 'transmit'
MOV BASE,#TABLE
MOV NR_BYTES,#05H
MOV SLAVE,#PCF8577W
CALL START
;Start transmission
FIN_4:
JNB I2C_END,FIN_4
JMP ADCON
;Proceed with AD-conversion
;part
129
130 ;*****************************************************************
131 ;Routines used by clock part of demo
132
133 ;CONV converts hour and minute data to LCD data and
; stores
134 lit in TABLE.
135 CONV:
MOV DPTR,#LCD_TAB ;Base for LCD segment
; table
136
MOV A,R5
;Hours to accu
137
SWAP A
;Swap nibbles
CALL LCD_DATA
138
;Convert 10's hours to LCD
;data in table
139
MOV A,R5
;Get hours
140
CALL LCD_DATA
141
MOV A,R4
;Get minutes
142
SWAP A
CALL LCD_DATA
143
;Convert 10's minutes
2-198
Philips Semiconductors Video Products
Application Note
Interfacing the PCF8584 12C-bus controller
to BOC51 family microcontrollers
ASMSl
LOC
TSW
ASSEMBLER
OBJ
0091: EC
0092: 120096
0095: 22
0096:
0098:
0099:
009A:
009B:
540F
93
F6
08
22
009C:
009C:
009F:
00A2:
OOAS:
FC60DA
F266B6
3EEOFE
E6
LINE
R
00A6: EB
00A7: 13
00A8: S03C
OOAA: 33
OOAB: B51402
R
OOAE: 800A
OOBO: 0515
00B2: E515
R
00B4:
00B7:
OOBA:
OOBC:
R
R
R
B40403
751500
8B14
E515
a
OOBE: 900193
00C1: 93
a
00C2: 7800
R
April 1990
144
145
146
147
148
Demo program for PCF858'
I~C-routines
SOURCE
MOV A,R4
CALL LCD_DATA
;Convert minutes
RET
1
;LCD_DATA gets data from segment table and stores it
lin TABLE
LCD_DATA:ANL A,#OFH
;Mask off LS-nibble
MOVC A,@A+DPTR ;Get LCD segment data
MOV @RO,A
;Save data in table
INC RO
149
150
151
152
153
RET
154
155 ;LCD_TAB is conversion table for LCD
156 LCD_TAB:
157
DB OFCH,60H,ODAH; '0','1','2'
158
DB OF2H,66H,OB6H; '3','4','5'
DB 3EH,OEOH,OFEH; '6','7','8'
159
160
DB OE6H
'9'
161
162 ;*******************************************************************
163
164
165 1These part of the program reads an analog
; input-channel.
166 ;Displaying is done on the LED-display
167 IOn odd-seconds the channel number will be
; displayed.
168 IOn even-seconds the analog value ·of this channel is
; displayed
169 ;Then the next channel is displayed.
170
171 ADCON: MOV A,R3
;Get seconds
172
;lsb to carry
RRC·~
JNC NEW_MEAS
173
;Eyen seconds; do a
;measurement on the current
; channel
174
175 ;Display and/or update channel
176
RLC A
; Restore accu
177
CJNE A,PREVIOUS,NEW_CH ;If new seconds,
;update channel number
178
JMP DISP_CH
179 NEW_CH: INC CHANNEL
180
MOV A,CHANNEL
;If channel-4 then
;channel:-O
181
CJNE A,#04,DISP_CH
182
MOV CHANNEL,#OO
183 DISP_CH:MOV PREVIOUS,a3 ;Update previous seconds
184
MOV A,CHANNEL
;Get segment value of
; channel
185
MOV DPTR,#LED_TAB
186
MOVC A,@A+DPTR
187
188
MOV RO, #TABLE
;Fill table with I2C.data
2-199
AN425
Philips Semiconductors Video Products
Application Note
Interfacing the PCF8584 12C-bus controller
to 80C51 family microcontrollers
ASM51
TSW
ASSEMBLER
Demo program for PCF8584 I2C-routines
LOC
OBJ
LINE
00C4:
00C6:
00C7:
00C9:
OOCA:
OOCB:
OOCC:
OOCD:
OOCE:
OOCF:
OODO:
00D1:
7600
08
7677
08
F6
E4
08
F6
08
F6
08
F6
189
190
191
192
193
194
195
196
197
198
199
200
201
202
MOV
INC
MOV
INC
MOV
CLR
INC
MOV
INC
MOV
INC
MOV
203
204
205
206
207
208
209
MOV BASE,#TABLE
MOV NR_BYTES,#06H
MOV SLAVB,#SAA1064W
CALL START
00D2: D200
R
750000
750006
750076
120000
R
R
R
R
OOEO: 3000FD
00E3: 020027
R
R
00D4:
00D7:
OODA:
OODD:
OOE6: 120108
R
00E9: 3000FD
R
OOEC: 7801
OOEE: 8616
OOFO: E516
R
R
R
210
211
212
213
214
215
216
217
218
219
220
00F2: 7917
00F4: 120154
R
R
00F7: 900193
OOFA: 7817
OOFC: 12018A
R
R
R
OOFF: 12012C
0102: 3000FD
R
R
0105: 020027
R
April 1990
221
222
223
224
225
226
227
228
229
230
231
SOURCE
@RO,#OO
RO
@RO, #77H
RO
Cf.RO,A
A
RO
Cf.RO,A
RO
@RO,A
RO
Cf.RO,A
SETB DIR
FIN_5:
;SAA1064 instruction byte
;SAA1064 control byte
; Channel number
;Second digit
;Third digit
;Fourth byte
;I2C transmission of channel
; number
JNB I2C_END,FIN_5
JMP REPEAT
; Repeat clock and AD cycle
; again
;Measure and display the value of an AD-channel
NEW_MEAS: CALL AD_VAL
;Do measurement
;Wait till values are available
F:IN_6: JNB :I2C_END,F:IN_6
;Relevant byte in TABLE+l. Transfer to AN_VAL
MOV RO,#TABLE+l
MOV AN_VAL,Cf.RO
MOV A,AN_VAL
;Channel value in accu for
; conversion
;AN_VAL is converted to BCD value of the measured
;voltage.
;:Input value for CONVERT in accu
;Address for MSByte in Rl
MOV Rl, #CONVAL
CALL CONVERT
;Convert 3 bytes of CONVAL to LED-segments
MOV DPTR,#LED_TAB ;Base of segment table
MOV RO, #CONVAL
CALL SEG_LOOP
;Display value of channel to LED display
CALL LED_D:ISP
F:IN_8: JNB :I2C_END,FIN_8 ;Wait till :I2C
;transmission is ended
JMP REPEAT
;Repeat clock and AD cycle
232
233
234 ;***********************************'****************************
235 1Routines used for AD converter.
236
237 ;A:IN reads an analog values from channel denoted by
; CHANNEL.
2-200
AN425
Philips Semiconductors Video Products
Application Note
Interfacing the PCF8584 12C-bus controller
to 80C51 family microcontrollers
ASM51
TSW
ASSEMBLER
LOC
OBJ
0108:
010A:
010C:
010E:
0111:
D200
7800
A615
750000
750001
R
R
R
R
R
238
239
240
241
2'2
243
0114: 75009E
0117: 120000
R
R
244
245
011A: 3000FD
R
246
OllD: C200
0111': 750000
R
R
247
248
249
250
251
0122:
0125:
0128:
012B:
R
R
R
012C:
012C:
012F:
0131:
0133:
0135:
0136:
0138:
0139:
013B:
013C:
0131':
0142:
0145:
01'7:
014A:
OUD:
0150:
0153:
750002
75009F
120000
22
431780
7800
7917
7600
08
7677
08
7600
08
120185
120185
120185
D200
750000
750006
750076
120000
22
0154: 751'005
0157: A4
0158: A7FO
015A: 09
April 1990
LINE
252
253
254
255
256
257
R
R
R
R
R
R
258
259
260
261
262
263
26'
265
266
267
268
269
270
271
272
273
R
274
R
275
276
277
278
279
280
R
R
R
281
282
283
284
285
286
287
Demo program for PCF8584 I2C-routines
SOURCE
;Send controlbyte:
AD_VAL: SETB DIR
;I2C transmission
MOV RO,#TABLE
;Define control word
MOV @RO,CHANNEL
MOV BASE,#TABLE iSet base at table
MOV NR_BYTES, #0 lH i Number of bytes to be
isend
MOV SLAVE,#PCF8591W ;Slave address PCF8591
CALL START
iStart transmission of
icontrolword
FIN_7: JNB I2C_END,FIN_7 iWait until tranmission is
ifinished
iRead 2 data bytes from AD-converter
iFirst data byte is from previous conversion and not
irelevant
CLR DIR
iI2C reception
MOV BASE,#TABLE iBytes must be stored in
iTABLE
MOV NR_BYTES,#02Hi Receive 3 bytes
MOV SLAVE,#PCF8591R iSlave address PCF8591
CALL START
RET
iLED DISP displays the data of 3 bytes from address
iCONVAL
LED_DISP:
ORL CONVAL,#80H ;Set decimal point
MOV RO,#TABLE
MOV Rl,#CONVAL
MOV @RO,#OO
iSAA1064 instruction byte
INC RO
MOV @RO,#01110111B iSAA106' control byte
INC RO
MOV @RO,#OO
;First LED digit
INC RO
CALL GETBY
;Second digit
CALL GETBY
;Third digit
CALL GETBY
;Fourth digit
SETB DIR
;I2C transmission
MOV BASE,#TABLE
MOV NR_BYTES,#06
MOV SLAVE,#01110110B
CALL START
;Start I2C transmission
RET
;CONVERT calculates the voltage of the analog value.
;Analog value must be in accu
;BCD result (3 bytes) is stored from address stored
lin Rl
; Calculation: AN_VAL· (5/256)
CONVERT:MOV B,#05
MOL AB
;b2 •• bO of reg. B
2E+2 •• 2EO
;b7 •• bO of accu
2E-l •. 2E-8
MOV @Rl,B
; Store MSB (10EO-units)
INC Rl
2-201
AN425
Application Note
Philips Semiconductors Video Products
Interfacing the PCF8584 12C-bus controller
to 80C51 family microcontrollers
ASM51
LOC
TSW
ASSEMBLER
OBJ
LZNE
015B: 7700
288
015D:
0160:
0162:
0164:
0165:
0167:
0168:
289
290
291
292
293
294
295
296
B41C02
8002
4006
C3
9419
07
8011'3
297
298
016A: B70A03
299
300
016D:
016E:
0170:
0171:
0173:
0176:
0178:
17
2419
09
7700
840302
8002
4006
301
302
303
304
305
306
307
017A:
017B:
017D:
017E:
0180:
C3
9403
07
8011'3
B70AOl
308
309
310
311
312
0183: 17
0184: 22
0185:
0186:
0187:
0188:
0189:
E7
11'6
08
09
22
018A: 7903
018C: E6
018D: 93
018E:
01811':
0190:
0192:
11'6
08
D911'A
22
April 1990
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
Demo program for PCII'8584 Z2C-routines
SOURCE
MOV @Rl,IOO
,Calculate 10E-l unit
,(10E-l is 19h)
TEN_CH: CJNE A,119H+03B;Vl ,Check if accu <- 0.11
JMP TENS
,accu-O.ll, update tens
,accuutput would Increase to almost half
pulse and the actual active video picture.
ot'Ethemet rates!
Because of the limited number of available
One horizontal line (525) of data =37 Bytes
lines in the VBI, the actual amount of data
or =296 bits per linelfield
that can be transmitted is limited to about
17.76Kbitslsec times the number of
296
transmitted lines. So, if we were to transmit 3
x 60 Welds per second)
lines of Teletext data per field, that would
17,760 bits/sec per line data rate
work out to:
x 251 (usable lineslfjeld)
4,457,760 bitslsec data rate
One horizontal line (525) of data =37 Bytes
or =296 bits per line/field
296
x 60
17,760
x3
53,280
Welds per second)
bits/sec per line data rate
lines/sec
bits/sec
Basic Teletext system overview
• Teletext is a format to transmit data within a
video signal
• Can be multiplexed with the video, or not
• Data rate is a few MBitis
• Accepted global standard (WST)
• Secure delivery data channel
• Data error checking
• Low cost
• Uni-directional
• Page format: 24 rows x 40 columns
June 1994
So, a three line/field transmission has an
effective data rate close to ISDN ratesl
2-204
Now the data rate has been increased to
over 4.5Mbits/sec, half Ethemet speedl
Philips Semiconductors Video Products
What is Teletext?
WHERE CAN TELETEXT DATA RESIDE IN A VIDEO SIGNAL?
VERTICAL SYNC SEQUENCE
-
VERTICAL BLANKING INTERVAL
22
ACTIVE VIDEO
PICTURE
--
The Teletext signal is generally found
inside the Vertical Blanking Interval.
f - - However, in a non terrestrial broadcasting
environment like cable TV or satellite, it would
be possible to use the entire video frame to
send data on a dedicated 6MHz channel.
252
VERTICAL SYNC SEQUENCE
(beginning of field 2)
WHAT DOES THE DATA LOOK LIKE?
Each Video line use to convey the
Teletext data is called a Teletext Data Line.
..1 - - - - - - 1-
45 bytes (360 bits) 625 line _ _ _ _------..,..~I
37 bytes (296 bits) 525 line
CLOCK RUN-IN
L - -_ _
COLOR BURST
' - - - - - - - HORIZONTAL SYNC
June 1994
2-205
Philips Semiconductors Video Products
What is Teletext?
625 LINE WST TELETEXT TRANSMISSION
ROW
ROW ADDRESS
SBITS
MAGAZINE ADDRESS
3 BITS
DISPLAY
525 LINE WST TELETEXT TRANSMISSION
ROW
ROW ADDRESS
SBITS
TABULATION
BIT
MAGAZINE ADDRESS
3 BITS
June 1994
2-206
Philips Semiconductors Video Products
What is Teletext?
HOW IS IT BROADCAST TO
CUSTOMERS?
The most common way for Teletext to reach
a large customer base is to send it using
normal over-the-air broadcast television
transmissions. Although this is the common
approach, it is not the only method. Cable
companies can distribute the data on a
dedicated channel or add it to the VBI of an
existing channel. Multi-point Distribution
System operators (MMDS or wireless cable)
can provide Teletext data via direct
microwave transmissions to the customer.
Satellite broadcasters can use the same
approach as well. Figure 3 is an example.
And signal distribution isn't required to
general off-air distribution. Teletext can also
be used over a video local area network
(VLAN) for supporting anything from printing
devices, data servers, and even individual
workstations. A simple way to provide secure
data delivery in a growing multi-media
environment and at a low cost.
WORKSTATION
MAC, PC, OR UNIX
INSERTER
WORKSTATION
TELEVISION
Figure 3. A Broadcast transmission example
June 1994
2-207
PERSONAL COMPUTER
Philips Semiconductors Video Products
What is Teletext?
VIDEO LAN
VIDEO
SERVER
CLASSROOM
CLASSROOM
Figure 4. An example of remote corporate training
In Figure 4, an instructor at a corporate
headquarters could be teaching a class
locally while also delivering the same
information to students at multiple remote
sites. In addition to the normal video and
audio transmissions, the instructor could
send data specifically to individual students
at the remote site (or sites) on demand over
the same video link. Teletext offers a new
way to add addition information to video
training without affecting the current video
distribution network.
June 1994
2-208
Philips Semiconductors Video Products
What is Teletext?
WHAT ABOUT ERROR
CORRECTION?
PAGE HEADERS Packet Address 0
The WST standard provides for two basic
layers of error correction for page format
Teletext, Hamming code is used for
addressing, and parity for character data.
The Hamming correction can catch both
single and double bit errors, while the parity
checking can resolve single bit errors. For
Packet 31 transmissions, there is the
addition of a 16 bit CRC check added to the
end of the data packet, although this is
optional. Both page format Teletext and
Packet 31 could be encoded with 8 bit data
allowing any third party protection format to
be used.
This packet contains page number and
control information, plus 32 display
characters including 'TIME'. It appears at the
top of the display.
WHAT ARE TELETEXT
PACKETS?
Packets are the actual data information with
an assigned address. There are three basic
types of packet in the WST standard, page
headers, normal rows, and extension
packets. Each has a specific assigned
purpose and bit format:
Packet Number
Function
Packet (row) 24
Page Extension
Packet (row) 25
Telesoftware
Packet (row) 26
Schedule Information &
Page Related
Redefinition
Packet Address 1 - 23
Packet (row) 27
These contain 32 bytes (40 bytes 625 line) of
data defining a row of 32 (40) characters on
the display. The address defines the vertical
position of the row.
Linked Pages
(FLOF/FASTEXT)
Packet (row) 28
Page Related
Redefinition
Packet (row) 29
Magazine Related
Redefinition
Packet (row) 30
Broadcaster Data
Services
Packet (row) 31
Independent Data
Services (Multi-media)
NORMAL ROWS-
EXTENSION PACKETS Packet Address 24 - 31
Typically each has its own special function
and is not directly displayed. They are used
to enhance the performance of the more
advanced decoders or to provide special data
services.
There are a total of eight extension packet
functions pre-defined under the WST
standard. They are:
With these extensions, Teletext can support a
wide variety of functional services from
programming a VCR to acquiring the latest
software for a home or business computer.
EXTENSION PACKET PROCESSING
AFTER PROCESSING
RECEIVED DATA
DISPLAYED PAGE
BASIC
PAGE
DATA
(ROWS 0-23)
HOST
MEMORY
OR
STORAGE
EXTENSION
PACKETS
June 1994
PROCESSING
2-209
Philips Semiconductors Video Products
What is Teletext?
HOW DOES A DECODER
FUNCTION?
There are tWo basic architectures to a WST
decoder. The first is for standalone
applications, as in a television set or a
set-top decoder (Figure 5). These units are
self contained and usually offer limited
capabilities for extension packet handling.
Generally the decoder is made up of a video
input processor (VIP), the Teletext processor,
some form of page memory storage for
received data, a character generator to drive
a CRT, and a character language font ROM
for displaying the text in the native language
the receiver is being used. These processors
offer a simple serial interface for
communicating with the televisions
microcontroller. Although the actual data
usually can be removed via this interface, it is
generally not recommend for performance
reasons.
The second method for receiving Teletext
data is to use a acquisition only decoder. This
type of decoder relies on a host
microprocessor to determine what happens
to the received data once is has been
acquired and error checked. At this pOint, the
processor must handle all of the storage and
display functions remaining to present the
data to the user. This is the preferred method
used for teletext interacting with a personal
computer. Because the host computer
already has memory, disk, networking, and
advanced display functions, there is no need
to have these function duplicated in the
Teletext receiver. (See Figure 6.)
Typically a decoder used in this method
supports all of the packets described under
the WST standard. The text processor is a
minimal Teletext decoder only handling the
error correction and acquisition functions. It is
therefore quite flexible in supporting multiple
packet format reception.
TO CRT
R
VIDEO
INPUT
VIDEO
PROCESSOR
, TEXT
PROCESSOR
PAGE
MEMORY
CHARACTER
GENERATOR
G
B
BLANK
TV
SYNC
FONT
ROM
MICROCONTROLLER
SERIAL INTERFACE
Figure 5.
AERIAL
\V
SYNC
~
UHFNHF
TUNER
&IF
VIDEO
VIDEO
INPUT
PROCESSOR
DATA
CLOCK
TEXT
PROCESSOR
1
PAGE
MEMORY
Figure 6.
June 1994
CONTROL
DATA
2-210
HOST
ifF
HOST
Philips Semiconductors Video Products
What is Teletext?
WHAT ARE SOME
RECOMMENDED
CONFIGURATIONS?
For basic level 1 Teletext reception in the 525
line television system, the standard
configuration is comprised ofthe SAA5191
data slicer, SAA9042 WST Teletext decoder,
a DRAM for local storage, and either a
microcontroller as the control host or and 12C
UART to interface to an external host (i.e., a
microcomputer). This solution will not decode
Packet 31 transmissions but will decode all
other extension packets.
Figure 7 demonstrates a standalone decoder
with the acquisition and display sections of
the SAA9042 timed from the incoming video
Signal. Although this will work quite well for
set-top or computer add-in card applications,
SAA5191
it should be noted that in the absence of any
incoming composite sync signal, or if the
Signal is very noisy, the field sync integrator
in the acquisition section will not be able to
detect the start of the field. Consequently the
display section will not receive a reliable
vertical trigger, and thus a stable text display
cannot be guaranteed under all signal
conditions.
SAA9042
R
VIDEO IN ------I~ CV
SAND
LL3A
B
SDA
LL3D
12CTO!1C
OR UART
SCL
13.5MHzD
TTC
TO DISPLAY
OR
ENCODER
G
II'lTI:RRUPT
INT
TTC
RSA
TTD
VCS
11.4545MHz
I - - -.......-----<-.j
TID
VSD
VSA
HSD
-=
0
I
J
COMP SYNC
256Kx4DRAM
(64 PAGE)
Figure 7. Standalone Example (Direct Sync Mode Shown)
June 1994
2-211
Philips Semiconductors Video Products
What is Teletext?
For acquisition only and Datacast reception
(packet 31), the SAA5250 CMOS Interface
for Data Acquisition and Control, or CIDAC,
is a WST decoder designed for direct
interfacing to a microprocessor host. Unlike
the SAA9042, CI DAC only has one
acquisition channel and support for only a
2Kx8 static RAM for local buffering. But
because CIDAC was intended to interface to
a microprocessor, the need for most of the
larger local storage and multiple acquisition
channels are unnecessary in this application
since the microcomputer host has superior
storage and data transfer capabilities already.
In the circuit shown in Figure 8, the SAA5231
is used purely as a data slicer since the
CIDAC doesn't require a dot clock for display
the VCO section of the SAA5231 is left
unused. Because the CIDAC was design as
a multi-Teletext format decoder, the chip was
designed primarily for full field data reception.
For VBI applications, it is suggested to add a
simple circuit between the SAA5231 and the
CIDAC that creates a VBI 'window'.
SAA5231
The purpose of the VBI window generator is
simple. To aid the CIDAC in the reduction of
invalid data being processed, and to provide
the host microprocessor with a data valid
interrupt so the microprocessor will not be
required to poll the CIDAC on a regular basis
to determine if new data has arrived.
The TDA4820T is a adaptive sync separator
which provides the PLD with vertical and
composite sync. With these signals at hand,
the PLD simply counts the number of
horizontal lines after the vertical sync period
until the desired active video line for the
window to open is found. Upon finding this,
the PLD then allows the data from the
SAA5231 to be passed onto the CIDAC, but
not before it is gated with the composite
blanking signal first. This has the result of
passing only valid data for a select number of
horizontal lines and pre-filtering out any sync
or color burst information which could be
confused as valid data.
The other function the PLD generates is a
simple interrupt pulse for the microprocessor.
This pulse can be generated before, during,
or after the window closes. The choice is up
to the PLD's designer and is important for the
microprocessors best performance. In
addition, it is recommended that the PLD
designer add a hardware select line from the
PLD to the microprocessor to allow it to
select full field or VBI reception for flexibility.
In conclusion, the WST Teletext format allows
a system designer great flexibility while
providing a low cost means to deliver secure
data over a wide area network. Philips
Semiconductors has been providing
complete Teletext solutions since the formats
early beginning and as a customer you can
look forward to continued innovative and cost
effective solutions from Philips
Semiconductors, World wide supplier of
Teletext components.
PLD
V'BT/FIELD SELECT
cv
VIDEO IN
vcs
0ATA]I'rr
22V10
DLY_CLK
TTC
11.4545MHz
0
I
~
SAA5250
WIN_DATA
TTD
C'BB"
TTD
TTC
DB<7 .. 0>
C'BB"
ALE
VALIN
SRAM
CS
J.ifS
WE
1m
2Kx8
AD'::10 .. 0>
DB<7 .. 0>
Figure 8. An Example WST Packet 31 Decoder for Multi-Media Applications
June 1994
2-212
WR
Interface information
Philips Semiconductors Video Products
Packet and Page Teletext data reception usi ng the SAA5250
Authors:
J. R. Kinghorn
A. Guenot
Philips Product Concept & Applications Lab, Southampton England
Philips Semiconductors, Paris France
Revised:
M. T. Schneider
Philips Product Concept & Applications Lab, California
SUMMARY
Two methods of transmitting serial data in
World System Teletext (WST) format are
available. These are the independent data
line or 'Packet 31' method, and the page
format technique. For universal application in
a subscription Teletext environment the
receiving equipment must be able to accept
both forms of transmission. The
Multistandard acquisition circuit CIDAC
(SAA5250) or CMOS Interface for Data
Acquisition and Control, is available to
simplify the receiver design.
INTRODUCTION
Recently there has been a great upsurge in
interest in using Teletext to transmit serial
data. This can be achieved without interfering
with the normal Teletext service, and the data
can be used for many purposes. For
instance, a nationwide one way data
distribution service could provide customer
support for a computer software
manufacture, sending both new product
announcements, software updates and bug
fixes automatically.
through the conventional television receiving
circuitry of tuner, I.F., and demodulator stages
to produce a baseband composite video
signal (CVBS). This is applied to the Teletext
data slicer and acquisition decoder, which
provides a data output to the host computer
rather than the usual text display output.
At the receiving end, a variety of terminal
equipment types can be envisaged
depending on the application. A common
requirement, however, is for a 'black box'
which can be connected to an aerial input
signal and deliver a parallel data output to a
desktop computer. This unit can be largely
transparent to the application, being the
equivalent of a data link in a conventional
wired computer installation. A block diagram
of such an adapter unit is shown in Figure, 1.
The Teletext decoder can use a
microprocessor to format the data output and
provide control of the system. Tuning in the
local broadcast station and selection of the
required service can be done through the
controls on the adapter unit, or alternatively
by sending commands from the host
computer through a suitable interface logic.
Facilities for descrambling the data and
access control can be provided in the
software of the adapter unit or in the host
computer according to the particular
requirements of a service.
The UHF or VHF aerial signal is passed
\V
RF INPU T
~
TUNER/IF
DATA
SLICER
TELETEXT
ACQUISITION
DECODER
HOST INTERFACE
(ORIlC)
h
Figure 1. Data Adapter Unit
2-213
Revised: June 1994
Philips Semiconductors Video Products
Packet and
Pag~ Teletext
The Teletext Decoder
As mentioned earlier, the requirements for a
Teletext decoder to receive serial data are
quite different from a conventional decoder in
a television set, or set-top decoder. To begin
with, an RGB text display output is not
usually required as perfectly adequate
character generating capacity is available on
the host computer's display. The data output
is the main requirement; demanding
reasonably direct access to the acquisition
memory from the host. Facilities for access
control and descrambling the data may be
needed, together with special error-checking
algorithms.
As a further complication, two entirely
different transmission methods are used for
serial data; the page format method and the
independent data line or 'packet 31' method.
Each of these methods has its advantages
and disadvantages, but it appears likely that
both will be used commercially.
If only page format data reception is
required, a standard Teletext decoder chip
can be used with appropriate control
software, see Reference 1. However, the
adapter deSigner may require a universal
decoder capable of operating on either form
of transmission. For reasons of economy,
duplication of circuitry should be avoided if
possible. On the other hand, good
COMPOSITE
VIDEO
CVBS
Interiaceinformation
data reception using the· SAA5250
performance (I.e. speed) and adaptability
may be prerequisites in acompetitive design.
The multi standard acquisition circuit CIDAC
(SAA5250) provides a solution to these
problems. Originally deSigned for the
reception of the Frenctl ANTIOPE and the
World Sy~tem Teletext formats, it is equally
capable ofacquiring data using the
independent data line transmissio.n
technique. The device can be programmed to
operate in various modes and two of these
are suitable for the independent data line and
the page format transmissions respectively. A
block diagram ofa multistandard Teletext
decoder for serial data is shown in Figure 2.
Composite video is supplied to a standard
Philips data slicer (SAA5231 or SAA5191)
circuit which performs adaptive data slicing
and supplies serial data and clock to the
CIDAC (SAA5250). The other section of the
data slicer is concerned with display timing
synchronization is not used. All of the CIDAC
timing is derived from the 5.7273Mhz
(6.9375Mhz in 625 line) data clock.
Acquisition of the data is performed by the
CIDAC circuit (SAA5250).
The received data is buffered in a standard
low cost 2K x 8 static RAM connected to the
CIDAC. The chip performs appropriate prefix
processing according to the operating mode
sel.ected, and the storage of particular
CIDAC
SAA5250
2K x 8 STATIC RAM
Figure 2. Serial Data Teletext Decoder
2-214
packets of data is undElr software control.
Data. is.retrieved from the RAM via CIDAC's
parallel interface to a host interface or a
microcontroller.
If a microcontroller is used, the microcode is
responsible for formatting the data into the
form required to interface with the host
computer (I.e. an RS-232 serial interface at
9600 baud). The microcontrolleritself can be
one of several standard types, 8051, 8049,
6801, 6805, etc. Any controls (I.e. to select
the service) can be implemented locallY in the
decoder using port pins of the
microcontroller; alternatively if the output
interface is made bi-directional, selections
can be made using the host computer
externally. Access controls and descrambling
are dealt with using the appropriate software
in the decoder's microcontroller acting on the
corresponding received data.
Alternatively, these functions may be
performed by the host computer, with the
decoder simply acting as a transparent data
link and no microcontroller is used in this
configuration. The same hardware
configuration can be used as a receiver for
downloadable software, or as a standard
acquisition unit for normal World System
Teletext or pages with the host computer
used as the display unit.
HOST INTERFACE
OR
MICROCONTROLLER
DATA OUTPUT
Philips Semiconductors Video Products
Interface information
Packet and Page Teletext data reception using the SAA5250
The CIDAC Circuit
The CIDAC itself performs the acquisition
functions and interfaces with the memory and
host. A block diagram of the device is shown
in Figure 3.
The received serial data from the data slicer
is checked for framing code (which is
programmed from the host) during a line
timing window derived from the VCS sync
signal. This timing window can be moved
within limits under software control to
compensate for the different framing code
delays. After detection of the framing code,
the information is converted into 8 bit parallel
form. In addition, the VAL OUT output (pin 2)
will reflect the position of the programmed
framing window.
The functions performed by the data depend
on the operating mode selected, and are
controlled by the sequence controller circuit.
Some data bytes are Hamming protected,
and these are passed through Hamming
correction logic. Most of the operating modes
have hardware recognition of a channel or
magazine, so the appropriate input data is
compared with the requested magazine
number in the channel comparator. This
ensures that only data from the selected
magazines is loaded into memory, and that
the acquisition process is not burdened with
irrelevant data.
The format counter is used to count the
number of bytes loaded into memory on each
data line; this value can be loaded by the
software. In long and short Didon (ANTIOPE)
modes this information is taken from the
broadcast format byte via the format
transcoder.
Storage of the data in memory also depends
on the selection of slow or fast mode. In slow
mode, all data from the selected magazine is
stored in memory regardless of any further
conditions. It is then up to the host software
to search for the appropriate data by looking
for a start-of-page flags, packet number
recognition, etc. This method is suitable for
modest operating speeds such as the packet
31 system, in which the host has no difficulty
in keeping up with the overall data
throughput.
Alternatively if fast mode is chosen, data is
only stored after recognition by the CIDAC
hardware of an appropriate 'start-of-page'
flag. This flag depends on the system; codes
SOH, RS for Didon, a bit in the PS byte for
NABTS, or row 0 (page header) for World
System Teletext. Using fast mode
considerably simplifies the host's task in page
recognition, so the position of the data to be
checked becomes defined in memory. Fast
mode is implemented by page flag detection
circuitry in the sequence controller.
DB<7.. 0>
ALE
HOST
INTERFACE
SERIAUPARALLEL
CONVERTER
FORMAT
PROCESSOR
DCK
2KBYTE
FIFO MEMORY
CONTROLLER
FORMAT
TRANSCODER
VALIN/SYNC
VAL OUT
WR
FORMAT
COUNTER
VALIDATION
SIGNAL
PROCESSING
CBB
SAA5250
Figure 3. The SAA5250 (CIDAC)
2-215
Philips Semicoriductors Video Products
Interface information
Packet and Page Teletext data reception using the SAA5250
Fast mode is suitable for the page format
data transmission method, as the data may
be mixed up with a large number of normal
teletext pages and interleaved in. time. With a
suitably fast host, slow mode could be used .
but it should be remembered that the number
of data lines transmitted might increase over
time. Also, genuine full channel operation will
be impossible in slow mode.
The extemal 2K x 8 static RAM is used as a
first-in-first-out (FIFO) memory so that the
transmission order is carefully preserved.
Flags associated with the FIFO controller
allow the host to see whether the FIFO is
empty, has a character for reading, or it is full.
Writing to the memory depends on the
reception of tral1smitted data. And a read
cycle occurs when it's requested by the host.
Ttle CIDAC memorY interface has interleaved
read and write cycles clocked at the
transmission rate, so in principle the host
could read the data as fast as it is coming
into the FI FO (Approx. one
byte/microsecond). Any standard 2K x 8
Static RAM (Le. 6116) can be connected to
the memory interface and the timing
requirements are not very critical.
The interface to the host is an 8 bit parallel
bus together with the appropriate
handshaking control signals. Data and
address are multiplexed on the bus in
accordance with normal microprocessor
practice. A feature of the CIDAC is the
support of a MOTEL (Motorola/Intel) parallel
(programmable) host interface.
components. Communication between the
host and CIDAC is always initiated by the
host.
Since CIDAC does not provide an interrupt
function to the host, the host must poll to
CIDAC to see when new data has arrived.
However, .the designer can generate a field
interrupt easily by adding only a small
amount of exterriallogic.
The Intel protocol (Le., 8051,8049, etc.)
latches the address with ALE, and has
separate RD* and WR* pulses for reading
and writing respectively. The Motorola
protocol (Le. 6801, 6805) has an AS pulse for
latching addresses, a DS pulse every cycle,
and a R/W* signal to distinguish read and
write cycles.
Various write registers in CIDAC allow the
selection of the operating mode, and the
loading of the channel number. There are two
registers which can be read by the host; the
data register (which contains the next byte of
data readfrOfn the FIFO memory by the
CIDAC hardware), and a status register to
indicate whether the FIFO memory is empty,
normal, or full.
CIDAC distinguishes between these two
protocols by looking at the state of the RD
(OS) line during the ALE (AS) pulse and
switches over automatically as necessary.
This facility permits many types of host
interfaces to be connected to CIDAC without
extensive interface bus translation
The rate of reading the FIFO depends
entirely on the host, as it is asynchronous
compared to the transmission. However, the
software designer must ensure that, on
average, the host reads the FIFO at least as
fast as the data is arriving, otherwise the
buffer can overflow.
2-216
Interface information
Philips SemiGonductors Video Products
Packet and Page Teletext data reception using the SAA5250
Data Formats
CIDAC is capable of receiving data in various
formats, with options for Didon (ANTIOPE),
NABTS, and World System Teletext
reception. For the purpose of this paper,
however, only two operating modes need
concern us. These comprise the 'Didon
medium prefix slow' mode, used for 'packet
31' transmissions and 'WST fast' mode for
page format data reception (previously
known as the UK 'CEEFAX' Teletext format).
These data formats are shown in Figure 4.
S
The Didon medium prefix format (Figure 4a)
has simply two channel address bytes after
the framing code, followed by user data. The
channel bytes are each 8/4 Hamming
protected and use the same algorithm for
Didon and WST.
For reception of World System Teletext,
CIDAC has a 'WST fast' mode (Figure 4b)
with three bits of the first byte used as a
channel address or 'magazine' number. The
remaining bit and subsequent byte form five
USER DATA BYTES + CRC
B A1 A2
S
: CLOCK - SYNC BYTES
B
: BYTE SUNC BYTE
A 1 A2: PACKET ADDRESS BYTES
(a)
S
(RUN-IN)
(FRAMING CODE)
DIDON Medium Prefix
B M R
40 BYTES OF DATA (625)
32 BYTES OF DATA (525)
M
R
(625)
~IIIIIIIII
M
T
R
(525)
S
: CLOCK - SYNC BYTES
(RUN-IN)
B
: BYTE SUNC BYTE
(FRAMING CODE)
M, R
MAGAZINE & ROW ADDRESS GROUP
(Tabulation bit also included in 525 line operation)
(b) WST Prefix
Figure 4.
2-217
bits corresponding to the row address.
Detection of the Row 0 (page header) in fast
mode is the page flag indicating the storage
of subsequent data in the FIFO.
The reception software must examine the
data at the start of the sequence to determine
the page number. If the data is not the
desired page, the software arranges a
re-initialization of CIDAC to search for the
next page header.
Philips Semiconductors Video Products
Interfaoe infbrmation
Packet and Page Teletext data 'reception uSing the SAA5250
Receiving Datacast' .
Let us consider the use ofCIDAC for
receiving packet 31 transmissions in more
detail. The Datacast specification
(Refer~nce 2),d~fil1es four independent data
ch~nnels using mess~ge .bits XX01 in the first
byte following the .framing code.Wi~h the
second byte set t9 1111 , this is equivalent to
packet 31, or magazine 8,1,2, or 3 in
conventional (WST) teletext terms. The
format is show in Figure 5.
It will be recalled that CIDAC checks the first
two bytes after the framing code in Didon
medium Prefix mode, so this provides the
means to select the data channel required.
All subsequent bytes are stored in the FIFO
and need to be processed by the host
software. The Format Type byte (FT)
indicates whether the Packet Repeat (RI) or
Continuity Indicator (CI) bytes are present.
Next, the packet Address Length byte (AL)
indicates to the host how many bytes
following are used to identify the packet
address.
Following the bytes allotted for the packet
address comes the optional Repeat Indicator
(RI). The RI value indicates the number of
times the packet has been transmitted (I.e.
first, second, third, etc., repeat of packet).
The Continuity Indicator (CI) , which is again
optional, increments at each transmission of
a packet to a given address. This allows the
host software to detect the omission of a
packet in the sequence;
Following the 'prefix' bytes, there is a
sequence of between 28 to 32 (36 in 625
line) user data bytes used to convey the
serial data. The data can be represented as
either 8 or 7 bit (with parity) data. CIDAC can
be set up to enable or disable the parity
checking feature. When parity is enabled, the
last bit of.each byte is used by the software
to detect a parity error in the data.
Recognition
A software routine must be written to handle
the recognition of the desired packet address
in the data stream. This involves checking·
the Address Length (AL) and packet address
bytes to identify the desired service. If a
correspondence is not found, the routine can
rapidly unload the incorrect user data bytes
from the FIFO (without processing it), before
the next data packet arrives and the checking
process is restarted.
A 16 bit cyclic redundancy check (CRC)
follows the user data at the end of the packet.
This allows the integrity of the user data and
the continuity indicator (CI) byte to be
checked for any errors that may have
occurred in transmission. As for the host
software, the functions it needs to perform
during packet 31 reception fall into three
broad categories of operation; they are:
Formatting & Error Checkirig
The last step is to handle the formatting and
error checking functions once the desired
data packet is located. To do this, the routine
has to:
- Check the Format Type (FT)
- The Repeat Indicator (RI) byte
- The Continuity Indicator (CI) byte
- Handle CRC check on the Data
Initialization
The initialization process for the CIDAC will
need to select the proper operating mode. An
example might be:
- Didon medium prefix slow mode
- No parity checking
- The desired data channel
- A framing code value
-. Sync delay time & sync pulse width.
This procedure will cause CIDAC to acquire
all packet 31 transmissions for a specified
data channel.
.
CLOCK RUN·IN
FRAMING CODE
I
S
I ~DRESS
MAGAZINE & ROW
GROUP (MRAG)
B
DATA CHANNEL
SET TO 1111 FOR INDEPENDANT DATA·LlNES
USER DATA BYTE GROUP
FT
AL
~ll
I
(OPTIONAL UNCER CONTROL OF FT BYTE)
PACKET ADDRESSES
(4 BYTES IN THIS EXAMPLE)
NOTE:
Figure 5. The Datacast Format
2-218
CRC
16-BITCRC
The CRC is based on the CI byte (H present)
and the user data byte group.
Interface information
Philips Semiconductors Video Products
Packet and Page Teletext data reception using the SAA5250
If the Repeat Indicator is in use, the software
should arrange temporary buffering of the
multiple transmissions of data and make a
choice on the basis of the comparisons, plus
the CRC check, as to which data is valid. The
data must only be sent to the host once from
the decoder if the proper data sequence is to
be preserved. The Repeat Indicator is used
by the software routine to ensure that
repeated data is not sent out to the host
again. A simplified flow chart can be found in
Figure 6.
Figure 6. CIDAC Acquisition Flowchart (1 of 2)
2·219
Interface information
Philips Semiconductors Video Products
Packet and Page Teletext data reception using the SAA5250
NO
• Don't care when no repeat facility
Figure 6.
CIDAC Acquisition Flowchart (2 of 2)
2-220
Philips Semiconductors Video Products
Interface information
Packet and Page Teletext data reception using the SAA5250
CONCLUSION
REFERENCES
RECOMMENDED READING
The CIDAC decoder can form the basis of an
acquisition only Teletext decoder operating
on both the 'page format' and the 'Packet31,
types of transmission. With suitable software,
a high performance and efficient design can
be achieved.
1. Tarrant, David R. 'Data Link Using
Page-Format Teletext Transmissions',
IERE, Electronic Delivery of Data and
Software Conference. September 1986.
'World System Teletext and Data
Broadcasting System Technical
Specification'. December 1987, United
2. BBC Datacast Technical Specification,
1985.
Special Note: The SAA5243 (CCT)
mentioned in Reference 1 is no longer in
production. A suitable replacement can be
found in the table below:
625 line only
Kingdom Department of Trade and Industry,
London England.
'Digital Video Signal Processing'. June 1988.
Philips Components publication No. 9398 063
30011
Data Sheets for the Philips SAA5191 &
SAA5231 Data Slicers (available from your
local Philips Semiconductors Salesman).
Data Sheet for the SAA5250 CMOS Interface
for Data Acquisition and Control (CIDAC).
SAA5244A
SAA5246A
SAA5247
SAA5248
SAA5249
SAA5254
SAA5280
Data Book of the 12C controlled television
tuner front-end Modules, Philips Components
publication No. 939818250011
All of the above parts include a built-in data
slicer, therefore no need for a SAA5231 data
slicer.
525/625 line
SAA 9042 + SAA 5191
SAA5296
2-221
Philips Semiconductors Video Products
Interface information
Packet and Page Teletext data reception using the SAA5250
APPENDIX A
CIDAC Operating 'Modes for World System Teletext
1. WST (CEEFAX) Teletext Mode
Set up Magazine number in the 3 LSB's of Register 1.
SLOW mode: All data from magazine stored.
FAST mode: All data from magazine stored once Row 0 is detected.
2. DIDON Medium Prefix Mode (packet 31)
Set up magazine number in the 3 LSB's of Register 1.
Set up Row number in 4th LSB of Register 1 and the 4 LSB's of Register 2.
SLOW mode: All data from magazine with a specific packetnumber is stored.
FAST mode: Not valid for World System Teletext reception.
3. No Prefix Mode
No set up.
All data of every magazine and packet number is stored.
APPENDIX B
CIDAC Register Address Mapping
Below is the addressing definition for access to the CIDAC registers.
ADDRESS
CS
DB2
ADDRESS CIDAC REGISTER
R
W
H
L
L
L
L
L
Write Register RO
H
L
L
L
L
H
Write Register R1
H
L
L
L
H
L
Write Register R2
H
L
L
L
H
H
Write Register R3
H
L
L
H
L
L
Write Register R4
H
L
L
H
L
H
Write Register RS
H
L
L
H
H
L
Write Register R6 (used for CIDAC init only)
H
L
L
H
H
H
Write Register R7
L
H
L
L
L
L
Read Status Register
L
H
L
L
L
H
Read Data Register
L
H
L
L
H
L
Not Used
L
H
L
L
H
H
Not Used
DB1
DBO
2-222
Philips Semiconductors Video Products
Interface information
Packet and Page Teletext data reception using the SAA5250
APPENDIXC
CIDAC Register Organization
CIDAC WRITE REGISTERS
OATABYTE
FUNCTION
REGISTER
mode & parity
00
07
06
05
04
03
02
01
00
X
X
X
mode
parity
prefix2
prefix1
prefixO
format
01
val
fmt2
fmt1
fmtO
fstdgt3
fstdgt2
fstdgt1
fstdgtO
channel number
02
thdgt3
thdgt2
thdgt1
thdgtO
scdgt3
scdgt2
scdgt1
scdgto
hamming
03
X
X
max5
max4
max3
max2
max1
maxO
frame code
04
val7
val6
valS
val4
val3
val2
val 1
valO
sync process
05
pol
del6
del5
del4
del3
del2
del1
delO
init register 1
06
X
X
X
X
X
X
X
X
burst blanking
07
X
X
bst5
bst4
bst3
bst2
bst1
bstO
NOTE:
1. This is a fictitious register. Only the address needs to be accessed to reset CIDAC.
CIDAC READ REGISTERS
OATABYTE
FUNCTION
REGISTER
07
06
05
04
03
02
01
00
FIFO status
00
X
X
X
X
X
DB2
DB1
DBO
FIFO data
01
07
06
05
04
03
02
01
DO
NOT USED
02
X
X
X
X
X
X
X
X
NOT USED
03
X
X
X
X
X
X
X
X
APPENDIXD
Suggested Data Slicer Components for 625/525 Line Operation
The examples in this application note were designed for operation in both 625 and 525 line Teletext systems. Depending on which line standard
is chosen, some of the peripherals commonly around the data slicer need to be adjusted for proper operation. The table below shows these
values:
PIN NUMBER
VALUE WITH SAA5250
VALUE WITH SAA9042
PIN NAME
SAA5191 OR SAA5231
525 LINE
625 LINE
525 LINE
625 LINE
5
Store Amplitude
560 pF
470 pF
560pF
470pF
8
Data Timing
470 pF
390 pF
330pF
270pF
9
Store Phase
11
Crystal
12
Clock Filter
270pF
220 pF
120 pF
100pF
11.4545 MHz
13.875 MHz
11.4545 MHz
13.875 MHz
39 pF
27pF
39pF
27pF
2-223
Interface information
Philips Semiconductors Video Products
Packet and Page Teletext data reception using the SAA5250
CRYSTAL SPECIFICATION
Quartz Crystal
11.4545MHz (525 line)
13.875MHz (625 line)
Nominal Frequency
11.4545 MHz
Frequency Tol @ 25°C
+/- 50ppm
Temperature Stability
+/-30ppm
Temperature Range
-20 to +70°C
Load Capacitance (CL)
15pF
Shunt capacitance (Co)
5 pF typical, 7pF Max.
Motion Capacitance (C1)
19 fF typical
Resonance resistance (Rr)
10 Ohms typical, Max. 60 Ohms
Aging
+/- 5ppm/year
Mode of operation
Fundamental
Drive Level
100 IlWatts Correlation
SUPPLIERS
The crystals above can be ordered from the Philips Components Passives Group, the part numbers are:
4322 143 04890 (13.B75MHz)
For 11.454, contact Philips Passives.
The Component Passive group can be reached at (803) 772-2500.
The crystals are also available from Ecliptek inc. Their part numbers are:
ECX - 2384 - 11.454MHz.
ECX - 2383 - 13.875MHz
ECX - 2382 -13.500MHz (not used with the SAA5250, but listed for reference)
Ecliptek can be reached at (714) 433-1200. The contact sales representative is Mr. Rodney Mills.
2-224
Desktop Video Products
Section 3
Functional Index of Products
CONTENTS
Analog-to-digital conversion
Analog-to-digital converter selection guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TDA8703
8-bit high-speed analog-to-digital converter ...................................... , . . . . . . . . . . . . . . . . . .
TDA8706
6-bit analog-to-digital converter with multiplexer and clamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
3-790
3-803
Triple RGB 6-bit video analog-to-digital interface............................. ........................
Video analc,] input interface ..................................................................... .
Video analog input interface ..................................................................... .
Video analog input interface ..................................................................... .
8-bit digital-to-analog converters ................................................................. .
8-bit high-speed analog-to-digital converter ........................................................ .
3-813
3-825
3-842
3-859
3-878
3-893
3-908
3-924
3-933
3-1033
3-948
3-963
TDA8707
TDA8708A
TDA8708B
TDA8709A
TDA8712; TDF8712
TDA8714
TDA8716
TDA8718
TDA8755
TDF8704
TDA8758
TDA8760
8-bit high-speed analog-to-digital converter ........................................................ .
8-bit high-speed analog-to-digital converter ........................................................ .
YUV 8-bit video low-power analog-to-digital interface ................................................ .
8-bit high-speed analog-to-digital converter ........................................................ .
YC 8-bit low-power analog-to-digital video interface ................................................. .
1O-bit high-speed analog-to-digital converter ....................................................... .
Auxiliary functions
PCF8574/PCF8574A
PCF8584
TDA2595
TDA4670
TDA4680
TDA4686
TDA4820T
TDA8444/ATIT
Remote 8-bit I/O expander for 12C-bus .............................................................
12C-bus controller......... ......................................................................
Universal sync generator (USG) .................................................................. .
Line twenty-one acquisition and display (LITO D) .................................................... .
Horizontal combination .......................................................................... .
Picture signal improvement (PSI) circuit ........................................................... .
Video processor with automatic cut-off and white level control ........................................ .
Video processor, with automatic cut-off control ..................................................... .
Sync separation circuit for video applications ....................................................... .
Octuple 6-bit DAC with 12C-bus .................................................................. .
TDA8446; TDA8446T
TDA8540
Fast RGBIYC switch for digital decoding .......................................................... .
4 x 4 video switch matrix
SAA1101
SAA5252
3-5
3-16
3-41
3-100
3-644
3-675
3-685
3-701
3-717
3-722
3-731
3-763
Analog color decoding
TDA3566A
PAUNTSC decoder ............................................................................. ~
TDA4665
TDA8501
TDA9141
Baseband delay line ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAUNTSC encoder .............................................................................
PAUNTSC/SECAM decoder/sync processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-651
3-669
3-738
3-1010
Color decoding, encoding and clock ICs (digital)
SAA7110
SAA7151B
SAA7157
SAA7183
SAA7187
SAA7188A
SAA7191B
SAA7194
SAA7196
SAA7197
SAA7199B
SAA9051
SAA9057B
One Chip Frontend 1 (OFC1) .................................................................... .
SAA7110 programming example ................................................................. .
Digital multistandard colour decoder with SCART interface (DMSD2-SCART) ........................... .
Clock signal generator circuit for digital TV systems (SCGC) ......................................... .
Digital video encoder (square pixel with Macrovision) ............................................... .
Digital video encoder (DENC2-SQ) ............................................................... .
Digital video encoder (DENC2-M) ................................................................ .
SAA7188A programming example ................................................................ .
Digital multistandard colour decoder, square pixel (DMSD-SQP) ...................................... .
Digital video decoder and scaler circuit (DESC) (short-form data sheet) ................................ .
Digital video decoder, scaler, and clock generator (DESCPro) ........................................ .
Clock signal generator circuit for Desktop Video systems (SCGC) ..................................... .
Digital video encoder, GENLOCK-capable ......................................................... .
Digital multistandard TV decoder ................................................................. .
Clock signal generator circuit for Digital TV systems (CGC) .......................................... .
3-120
3-184
3-202
3-252
3-302
3-332
3-359
3-385
3-387
3-454
3-457
3-511
3-517
3-575
3-619
Digital-to-analog conversion
Digital-to-analog converter selection guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAA7165
Video enhancementand D/A processor (VEDA2) ....................................................
35 MHz triple 9-bit D/A converterfor high-speed video ................................................
SAA7169
SAA9065
Video enhancement and D/A processor (VEDA) .....................................................
TDA8702
8-bit video digital-to-analog converter ....................... , . . . . . . . . .. . . . . . . .. . . . . . .. . . . . . . . .. . . ..
TDA8771
Triple 8-bit video digital-to-analog converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TDA8772; TDA8772A Triple 8-bit video digital-to-analog converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4
3-276
3-295
3-626
3-776
3-984
3-996
Digital video processing
SAA7116
SAA7152
SAA7164
SAA7186
SAA7192A
Digital video to PCI interface ..................................................................... .
Digital video comb filter (DCF) .................................................................. ..
Video enhancement and D/A processor (VEDA3) ................................................... .
Digital video scaler ............................................................................. .
Digital colour space converter .................................................................... .
3-185
3-243
3-258
3-303
3-418
Teletext video processor ........................................................................ .
Teletext video processor ........................................................................ .
Interface for data acquisition and control (for multi-standard teletext systems) .......................... .
Single chip economy 10 page teletextlTV microcontrolier ............................................ .
Multi-standard Teletext IC for standard and features TV ............... , .............................. .
3-52
3-58
3-69
3-114
3-549
Teletext
SAA5191
SAA5231
SAA5250
SAA5296
SAA9042
Philips Semiconductors Video Products
A to D converter selection guide
Part
Resolution
Power
Convert
Rate
Clamp
AGe
Number of
Inputs
Outputs
Comments
Applications
TDA8703
8 bits
290mW
40MHz
No
No
One
Binary and
Two's compo
TTL compatible
General Purpose
TDA8706
6 bits (X3)
300mW
20MHz
Yes
No
Three multiplexed inputs
Binary TTL
Internal Reference
YUV, PIP applications
TDA8708NB
8 bits
365mW
32MHz
Yes
Yes
One of three
Binary and
Two's compo
Peak white is
248 for 8708A
255 for 8708B
Video decoding, frame grabbers
TDA8709A
8 bits
380mW
32M Hz
Yes
No
One of three
Binary and
Two's compo
Ext. voltage gain
control
Video signal and chroma proc.
TDA8714
8 bits
325mW
75MHz
No
No
One
Binary and
Two's compo
7.6 effective bits at
4.43MHz
High speed applications: radar,
medical, physics, etc.
TDA8716
8 bits
780mW
100MHz
No
No
One
Binary ECL
with overflow
Compo ECL clock
Very high speed ECL
applications
TDA8718
8 bits
1140mW
600MHz
No
No
One
Binary ECL
with overflow
Compo ECL clock
Ultra high speed ECL
applications
TDA8755
8 bits
565mW
20MHz
Yes
No
Three multipie xed inputs
Binary and
Two'scomp.
4:1:1 data encoder
YUV video conversion
TDA8758G
8 bits (X2)
475mW
32M Hz
Yes
Yes
5
Two'scomp.
TTL compatible
white peak disable
Dual video AID composite or
S-Video
TDF8704
8 bits
365mW
50MHz
No
No
One
Binary and
Two'scomp.
-40, +85 temp
range
Automotive/High temp. general
purpose
June 1994
3-3
Philips Semiconductors Video Products
D to A converter selection guide
Part
Resolution
Power
Convert Rate
(Max.)
Comment.
Number of
DACslPackage
Application.
General purpose
TDAB702
Bbits
250mW
30MHz
One
750 load
TDAB712
Bbits
250mW
50MHz
One
750 load
High speed general purpose
TDAB771
Bbits
175mW
35MHz
Three'
3 volts pIp out into 1K 0
Triple output general purpose
TDAB772
Bblts
260mW
310mW
35MHz
85M Hz
Three
TDA7169
9 bits
35M Hz
Three
750 load
RGB or YUV video
TDA7165
B bits
30M Hz
Three
Digital YUV to analog YUV converter
with
aperture and color improvement
Interfaces to RGB monitor drivers
TDA9065
Bbits
30MHz
Three
Digital YUV to analog YUV converter
with
aperture improvement
Interfaces to RGB monitor drivers
June 1994
. 75 0 load, separate blanking and sync
Inputs
3-4
RGB or YUV video with sync on signal
Product specification
Philips Semiconductors Video Products
PCF857 4/PCF8574A
Remote 8-bit I/O expander for 12C-bus
GENERAL DESCRIPTION
The PCF8574 is a single-chip silicon gate CMOS circuit. It provides remote I/O expansion for the
MAB8400 and PCF84CXX microcontroller families via the two-line serial bidirectional bus (1 2 C).
It can also interface microcomputers without a serial interface to the 12 C-bus (as a slave function only).
The device consists of an 8-bit quasi-bidirectional port and an 12 C interface.
The PCF8574 has low current consumption and includes latched outputs with high current drive
capability for directly driving LEDs. It also possesses an interrupt line (I NT) which is connected to the
interrupt logic of the microcomputer on the 12 C-bus. By sending an interrupt signal on this line, the
remote I/O can inform the microcomputer if there is incoming data on its ports without having to
communicate via the 12 C-bus. This means that the PCF8574 can remain a simple slave device.
The PCF8574 and the PCF8574A versions differ only in their slave address as shown in F ig.9.
Features
•
•
•
•
•
•
•
•
Operating supply voltage
2.5 V to 6 V
Low stand-by current consumption
max. 10 /1A
Bidirectional expander
Open drain interrupt output
8-bit remote I/O port for the 12 C-bus
Peripheral for the MAB8400 and PCF84CXX microcontroller families
Latched outputs with high current drive capability for directly driving LEDs
Address by 3 hardware address pins for use of up to 8 devices (up to 16 with PCF8574A)
I NT +-+-1:...:.3__________~
PCF8574
PCF8574A
AO--+-------------------~
Al --+-----------------~
PO
A2--~~------------_.
Pl
--+---••
+---+
SDA+-t-'-'-_.I
+---+
SCL
P2
SHIFT
REGISTER
I/O
PORTS
P3
P4
P5
P6
P7
write pulse
read pulse
VDD --~------I
VSS
7Z85821.2
Fig.1 Block diagram.
PACKAGE OUTLINES
PCF8574P, PCF8574AP: 16-lead D I L; plastic (SOT38).
PCF8574T, PCF8574AT: 16-lead mini-pack; plastic (S016L; SOT162A).
May 1989
3-5
Philips Semiconductors Video Products
Product specification
Remote 8-bit I/O expander for 12C-bus
PCF8574/PCF8574A
PINNING
P5
Fig.2 Pinning diagram.
7ZB7597.1
address inputs
1 to 3
AO to A2
4 to 7
PO to P3\
9 to 12
P4 to P7
8
negative supply
13
VSS
INT
14
SCL
serial clock line
15
SDA
serial data line
16
VDD
positive supply
I
8-bit quasi-bidirectional I/O port
interrupt output
r----~--~------VDD
write pulse
~---_------t
data from
shift register ~------1I---t 0
Q
FF
PO to P7
po~~~;on --t-~--+------I
L...--+_ _-4-_ _ _ vss
read pulse
~--+-------I
>-_____-+
data to
shift register
7 Z87598.1
Fig.3 Simplified schematic diagram of each port.
May 1989
3-6
to interrupt
logic
Philips Semiconductors Video Products
Product specification
Remote 8-bit lID expander for 12C-bus
PCF8574/PC F8574A
CHARACTERISTICS OF THE FC-BUS
2
The 1 C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are
a serial data line (SDA) and a serial clock line (SCl). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated
only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable
during the H IG H period of the clock pulse as changes in the data line at this time will be interpreted
as control signals.
SDA
/
-~~
i
---~
SCL
data line
stable:
data valid
change
of data
allowed
7Z87019
Fig.4 Bit transfer.
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-lOW transition of the
data line, while the clock is HIGH is definedas the start condition (S). A lOW-to-HIGH transition of
the data line while the clock is HIGH is defined as the stop condition (P).
r---r
SDA
SCL
r---l
--1\I...-+!,.--__--LC
___ ==~-----..l....-----+i.....In--i \
i--\'-__---'/r---+i--+--
SDA
I
I
I
I
:
IL
SCL
___
-.J
start condition
stop condition
F ig.5 Definition of start and stop conditions.
May 1989
3-7
7Z87005
Product specifica:tion
Philips Semiconductors Video Products
PCF857 4/PCF8574A
Remote 8-bit I/O expander for 12C-bus
CHARACTERISTICS OF THE 12 C-8US (continued)
System configuration
A device generating a message is a "transmitter", a device receiving a message is the "receiver". The
device that controls the message is the "master" and the devices which are controlled by the master
are the slaves".
II
SDA----------~------------~------------~--------------~------------~-
SCL --.-------+-----~------~----~~-----+----~~------~----~------i_-
Fig.6 System configuration.
Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to
receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge
bit is a HI G H level put on the bus by the transmitter whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception
of each byte. Also a master must generate an acknowledge after the reception of each byte that has been
clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during
the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse, set up and hold times must be taken into account. A master receiver
must signal an end of data to the transmitter by not generating an acknowledge on the last byte that
has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable
the master to generate a stop condition.
start
condition
clock pulse for
acknowledgement
I
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
+
--~
I
I
I
I
I
~'---~/--'---'X'----_>C ~ ~):
/
--~
DATA OUTPUT
BY RECEIVER
7Z87007
Fig.7 Acknowledgement on the 12 C-bus.
May 1989
3-8
Product specification
Philips Semiconductors Video Products
PCF8574/PCF8574A
Remote 8-bit I/O expander for 12C-bus
Timing specifications
All the timing values are valid within the operating supply voltage and ambient temperature range and
refer to VI Land VIH with an input voltage swing of VSS to VOO.
parameter
symbol
min.
typo
max.
SCL clock frequency
fSCL
-
-
100
tsw
-
-
100
tBUF
4.7
-
-
jJ.s
tsu; STA
4.7
-
-
jJ.s
tHO; STA
4.0
.-
-
Tolerable spike width on bus
Bus free time
Start condition set-up time
Start condition hold time
I
I
unit
kHz
' ns
I
I
I
jJ.s
tLOW
4.7
-
-
tHIGH
4.0
-
-
jJ.s
SCL and SOA rise time
tr
-
-
1.0
jJ.s
SCL and SOA fall time
tf
-
-
jJ.s
Oata set-up time
tsu; OAT
250
-
0.3
-
Oata hold time
SCL LOW time
SCL HIGH time
jJ.s
I
ns
tHO; OAT
0
-
-
ns
SCL LOW to data out valid
tvo; OAT
-
-
3.4
jJ.s
Stop condition set-up time
tsu; STO
4.0
-
-
jJ.s
PROTOCOL
SCl
SDA
7ZB7793.2
tHD:STA
tSU:DAT
tHD:DAT
Fig.8 12 C-bus timing diagram.
May 1989
3-9
tVD:DAT
tSU:STO
!
s::
~
<0
CD
<0
FUNCTIONAL DESCRIPTION
\J
JJ
Addressing (see Figs 9, 10 and 11)
(J)
CD
slave address
S
~
'5.
0
1-
1
I~-
'----;;- :
A2 : A 1 : AO:
0
I I ~ -~.
A
S
1 :
1 :
en
3
slave address
1 : A2 : A 1 : AO:
I I
0
3o·
0r-+
0
:::I
CD
A
Q.
c:
(X)
0
S'
I
(a) PCF8574.
0-
7Z96587
(b) PCF8574A.
0
Fig.9 PCF8574 and PCF8574A slave addresses.
CD
Each bit of the PCF8574 I/O port can be independently used as an input or an output. Input data is transferred from the port to the
microcomputer by the READ mode. Output data is transmitted to the port by the WR ITE mode.
slave address (PCFS 5 74)
..
~
SOl
t
start condition
WRITE
TO
PORT
DATA OUT
FROM PORT
PJ
0CD
0
\J
a
0-
c:
0
Cil'
:::J
0CD
...,.
0...,.
data to port
data to port
A
A
~_ _ _ _ _~A
o
x
"'C
::;;
-
SCL
SDA
ii!
;:::;:
-1
-,
0
0
A2
Al
AO
'
0
1A
I
1-
DATA 1
:A
1
1-
,-
acknowledge from slave
It
~
1
I
I
I
\
I
I
!
!
~
I
I
1__
I
!
DATA 1 VALID
I
tpv
_I
7ZB7593.1
Fig.10 WRITE mode (output port).
(f)
acknowledge from slave
:
_I
cr
c::
IA
----------------------~I--------------------~~
tpv
I
,-
DATA 2
:t
_ It
R /W : acknowledge from slave
1-
I\)
0
, 1
:kAT:AilD
I
1__
""U
o
"T1
ex>
01
-.....J
~
""U
o
"T1
ex>
01
-.....J
~
»
\J
a0a
c:
(J)
"0
CD
Q.
ff
~
g
s::
-0
~
JJ
(1)
co
Q)
co
3
0
(1)
(X)
I
CT
;::::;:
0
S
SDA
0
t
start condition
slave address (PCF8574)
data from port
A
J..
0
0
r A2
A1
I
AO
n
READ FROM
PORT
~
DATA INTO
PORT
INT
slave
I
I
1
I
1
I
1
_I
1
1
I
I
1
1--- tiv
II
1
1
I
1___ tph
I
~.
:::I
0-
c:
0
5"
iil
:s;
0CD
0
-0
8.c:
!l
(/I
'""'I
stop
1
I
i
CD
0
0
a.
1 condition
h
1
X
(J)
(1)
from master
DATA 3
(/I
~
1
=x..----------------D-A-T-A-1----------+-!.....,~
I
.....l
~
t
: acknowledge
--------------------------------~I
il
"0
IA ' - D A T A 4
l d
R /W I acknowledge
1 from
X
J..
"'
DA~A 1
:A
(1)
data from port
~
-5"
DATA 4
0
'""'I
N
()
I
CT
C
en
!
I~~I--------------------------~----
__ I
1--- tps
1
1
in:
I
--I
1
1-- tir
I
1
--I 1-- tir
7ZB7596.1
Fig.11 READ mode (input port).
Note
A LOW-to-HIGH transition of SDA, while SCL is HIGH is defined as the stop condition (Pl. Transfer of data can be stopped at any moment by a
stop condition. When this occurs, data present at the last acknowledge phase is valid (output model. Input data is lost.
-u
()
'i1
(X)
01
"'..J
~
-U
()
'i1
(X)
01
t
-0
8.
~
(/I
"0
CD
o
3i
~
a:
o
:::I.
Philips Semiconductors Video Products
Product specification
Remote 8-bit I/O expander for 12C-bus
PCF857 4/PCF8574A
Interrupt (see Figs 12 and 13)
The PCF8574/PCF8574A provides an open drain output (lNT) which can be fed to a corresponding
input of the microcomputer. This gives these chips a type of master function which can initiate an
action elsewhere in the system.
PCF8574
PCF8574
(1)
(2)
PCF8574A
(16)
MICROCOMPUTER
INT
t---------+-----+--7ZB7599.1
F ig.12 Appl ication of multiple PCF8574s with interrupt.
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time
tiv the signal INT is valid.
Resetting and reactivating the interrupt circuit is achieved when data on the port is changed to the
original setting or data is read from or written to the port which has generated the interrupt.
Resetting occurs as follows:
• In the READ mode at the acknowledge bit after the rising edge of the SCL signal.
• In the WRITE mode at the acknowledge bit after the HIGH-to-LOW transition of the SCL signal.
Each change of the ports after the resettings will be detected and after the next rising clock edge, will
be transmitted as I NT.
Reading from or writing to another device does not affect the interrupt circuit.
slave address ( PCF8 5 7 4)
____
r -_ _ _ _
~A~
data from port
~
A
SDA
t
+_I
1
start cond ition
t
R /W I acknowledge
1 from slave
t
P5
stop
condition
1
I
I
SCL
I
1
I
DATA INTO
I NT
p0
1
I
I
1
I
I
I
I
1
1
---t-l
:
1 ---------------rl
I
~I
LI
--I
_I
1-- tiv
1-- tir
Fig.13 Interrupt generated by a change of input to port P5.
May 1989
3-12
7ZB-J594.1
Philips Semiconductors Video Products
Product specification
Remote 8-bit liD expander for 12C-bus
PCF8574/PCF8574A
FUNCTIONAL DESCRIPTION (continued)
Quasi·bidirectional 1/0 ports (see Fig.14)
A quasi-bidirectional port can be used as an input or output without the use of a control signal for
data direction. At power-on the ports are HI G H. I n this mode only a current source to VDD is active.
An additional strong pull-up to VDD allows fast rising edges into heavily loaded outputs. These devices
turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The ports
should be HIGH before being used as inputs.
slave address (PCF8574A)
data to port
data to port
J.
SDA
I SiD
:
1 : 1
: ' : A2 : Al : AD:
t
start condition
D
t
R /Vii
IA I
t
:<
:<
P3
P3
t
t
acknowledge
from slave
SCl
P3
OUTPUT
VOLTAGE
t
--nL-__________________
P3
PULL-UP
OUTPUT
CURRENT
t
I.
~1
I
I OHt:
,
~
I
7Z87595.1
I
IOH
Fig.14 Transient pull-up current 10Ht while P3 changes from LOW-to-HIGH and back to LOW.
RATINGS
Limiting values i.n accordance with the Absolute Maximum System (I EC 134)
parameter
symbol
min.
max.
unit
Supply voltage range
VDD
-0.5
+ 7.0
V
VI
VSS -0.5
VDD+ 0.5
V
DC input current
± II
-
20
mA
DC output current
± 10
-
25
mA
VDD or VSS current
± IDD; ± ISS
-
100
mA
Total power dissipation
I nput voltage range
Ptot
-
400
mW
Power dissipation per output
Po
-
100
mW
Operating ambient temperature range
Tamb
-40
T stg
-65
+ 85
+ 150
°C
Storage temperatu re range
°C
HANDLING
I nputs and outputs are protected against electrostatic discharge in normal handling. However, to be
totally safe, it is desirable to take normal precautions appropriate to handling MaS devices (see
'Handling MaS Devices')'
May 1989
3-13
P~Qduct specification
Philips Semiconductors Video Products
Remote 8-bit I/O expander for 12C-bus
PCF8574/PCF8574A
CHARACTERISTICS
VDD = 2.5 to 6 V; VSS = 0 V; Tamb = -40 to
parameter
+ 85 oC unless otherwise specified
conditions
symbol
min.
typo
max.
unit
\/00
2.5
-
6.0
V
100
1000
VpO R
-
40
2.5
1.3
100
10
2.4
JlA
JlA
V
VIL
-0.5
-
0. 3V OO
V
-
rnA
-
1
JlA
7
pF
0. 3V OO
V
400
Supply
Supply voltage
Supply current
operating
standby
Power-on reset level
VOO = 6 V;
no load;
VI =VOO or
VSS
fSCL = 100 kHz
note 1
Input SCL; input/output SOA
I nput voltage LOW
+ 0.5 V
VIH
0. 7V OO
Output current LOW
VOL = 0.4 V
10L
3
Leakage current
VI = VOO or
VSS
IILI
-
VI = VSS
CI
-
I nput voltage LOW
VIL
-0.5
I nput voltage HI G H
VIH
0.7VDO
-
VI ~ VOO or
~VSS
± IIHL
-
-
VOL = 1 V;
VOO = 5 V
10L
10
25
-
rnA
-
300
JlA
Input voltage HIGH
I nput capacitance (SCL, SOA)
VOO
I/O ports
Maximum allowed input
current through
protection diode
Output current LOW
Vbo
+ 0.5 V
JlA
Output current HIGH
VOH = VSS
10H
30
Transient pull-up current
HIGH during acknowledge
(see F ig.14)
VOH = VSS;
VOO = 2.5 V
-IOHt
-
1
-
rnA
CliO
-
-
10
pF
I nput/Output capacitance
Port timing
(see Figs 10 and 11)
CL = ~ lOO pF
Output data val id
tpv
-
JlS
tps
0
-
4
I nput data set-up
-
Jls
tph
4
-
-'
JlS
I nput data hold
May 1989
3-14
Product specification
Philips Semiconductors Video Products
PCF8574/PCF8574A
Remote 8-bit I/O expander for /2C-bus
conditions
parameter
symbol
min.
typo
max.
unit
Interrupt INT
Output current LOW
VOL
= 0.4 V
IOL
1.6
-
-
rnA
Leakage current
VI = VOO or
VSS
IILI
-
-
1
Il A
tiv
-
-
4
Il S
tir
-
-
4
IlS
VIL
-0.5
-
VIH
0. 7V OO
-
V
0. 3V OO
VOO + 0.5 V
IILI
-
-
250
tNT timing
(see Figs 11 and 13)
CL
= ~ 100 pF
I nput data valid
Reset delay
I
Select inputs AO, Al, A2
I nput voltage LOW
I nput voltage HI G H
I nput leakage current
pin at VOO or
VSS
nA
Note to the characteristics
1. The power-on reset circuit resets the
(with current source to Vool.
1
2
C-bus logic with VOO
< VPOR
and sets all ports to logic 1
Purchase of Philips' 1 2 C components conveys a license under the
Philips' 12 C patent to use the components in the 12 C-system provided
the system conforms to the 12 C specifications defined by Philips.
May 1989
3-15
Preliminary spf!ciflca~l,on
Philips Semiconductors Video Products
12C-bus controller
PCF8584
GENERAL DESCRIPTION
The PCF8584 is an integrated circuit designed in CMOS technology which serves as an interface between
most standard parallel-bus microcontrollers/processors and the serial 12 C-bus. The PCF8584 provides
both master and slave functions. Communication with the 12 C-bus is carried out on a byte-wise basis
using interrupt or polled handshake. It controls all the 12 C-bus specific sequencing, pr~tocol, arbitration
2
and timing. The PCF8584 allows parallel-bus systems to communicate bidirectionally with the 1 C-bus.
Features
• Parallel-bus/1 2 C-bus protocol converter
• Compatible with most parallel-bus processors including MAB8049, MAB8051, SCN68000 and Z80
• Automatic selection of bus interface
• Programmable interrupt vector
• Multi-master capability
• 12 C-bus monitor mode
• Long-distance mode
• Operating supply voltage 4.5 to 5.5 V
• Operating temperature range -40 to +85 °C
PACKAGE OUTLINES
PCF8584P: 20-lead DI L; plastic (SOT146).
PCF8584T: 20-lead mini-pack; plastic (S020; SOT163A).
May 1994
3-16
Philips Semiconductors Video Products
Preliminary specification
12C-bus controller
PCF8584
DB7
DB6
DB5
DB4
DB3
DB2
DBl
DBO
I V DD
15
14
13
12
11
9
8
7
120
~.::
VSS
10
~
SDA
2
DIGITAL
FilTER
1 +---j
~
DIR
BUS BUFFER
-
EN
8
I
MSB
I
I
I
I ~
I
DATA SHIFT REGISTER SO
AND READ BUFFER
LSB
8
DATA CONTROL
I
I
I
I
I
I"'-
COMPARATOR SO, SO'
~
"'-
8
"'"-
I
I
x
I
X
"'-
I
I
I
I
I
"-
OWN ADDRESS SO'
8
PCF8584
I
I
I
I
INTERRUPT VECTOR S3
SCl
3
DIGITAL
FilTER
CLOCK REGISTER S2
1
•
x
I
I
x
I
x
S24
I
S23
S22
CLOCK
SClCONTROl
PIN
I ESO I ESl I ES2
PIN
I
I STA I STO
19
17
-
CS
lACK
} write only
. } read only
ADO!
BB
}
REGISTER CONTROL
BUS BUFFER CONTROL
INTERRUPT CONTROL
RESET!STROBE CONTROL
6
AO
18
16
-
-
WR (RIW)
-
--
RD (DTACK)
5
4
-
--
INT
lACK
1
ClK
MBD90B
Where:
( ) indicate the SCN68000 pin name designations.
X = don't care.
Fig.1 Block diagram.
May 1994
I
S20
SCl
I STS I BER I lRB I AAS I lAB I
0
" 7
--
RESET!
STROBE
S21
REGISTER Sl
ENI
CLOCK PRESCAlER
SCl MULTIPLEXER
BUS BUSY lOGIC
ARBITRATION lOGIC
---
I
8
CONTROL STATUS
}
8
3-17
Philips Semiconductors Video Products
Preliminary specification
12C-bus controller
PCF8584
PINNING
ClK
VDD
SDA or SDA OUT
RESET / STROBE
SCl orSCl IN
lACK or SDA IN
WR(R/W)
4
CS
INT or SCl OUT
RD (DTACK)
AO
DB7
DB6
DB1
DB5
DB2
DB4
VSS
DB3
MLA012
Where:
( ) indicate the SCN68000 pin name designations.
Fig.2 Pinning diagram.
Pin functions
pin
mnemonic
function
description
ClK
I
Clock input from microprocessor clock generator (internal pUll-up).
2
SDA or
SDA OUT
I/O
2
1 C-bus serial data input/output (open-drain).
Serial data output in long-distance mode.
3
SClor
SCl IN
I/O
C-bus serial clock input/output (open-drain).
Serial clock input in long-distance mode.
4
lACK or
SDAIN
5
INT or
SClOUT
6
AO
7
8
9
DBO
DB1
DB2
10
VSS
May 1994
2
1
I nterrupt acknowledge input (internal pull-up); when this signal
is asserted the interrupt vector in Register S2 will be available at
the bus port if the EN I flag is' set. Serial data input in long-distance
mode.
0
Interrupt output (open-drain); this signal is enabled by the ENI flag
in Register S1. It is asserted, when the PIN flag is res~t. (PIN is reset
after one byte is transm itted or received over the 12 C-bus). Serial clock
output in long-distance mode.
Register select input (internal pull-up); this input selects between the
control/status register and the other registers. logic 1 selects Register
Sl, logic 0 selects one of the other registers depending on bits loaded
in ESO, ES 1 and ES2 of Register S 1.
I/O
I/O
I/O
Bidirectional 8-bit bus port.
Negative supply voltage.
3-18
Preliminary specification
Philips Semiconductors Video Products
12C-bus controller
PCF8584
Pin functions (continued)
pin mnemonic
function
description
11
12
13
14
15
DB3
DB4
DB5
DB6
DB7
I/O
I/O
I/O
I/O
I/O
Bidirectional 8-bit bus port.
16
RD (DTACK)
1(0)
RD is the read control input for MAB8049, MAB8051 or Z80-type
processors. DTACK is the data transfer control output for 68000-type
processors (open-drain).
17
CS
Chip select input (internal pull-up).
18
WR (R/W)
WR is the write control input for MAB8048, MAB8051 or Z80-type
processors (internal pull-up). R/W control input for 68000-type
processors.
19
RESET/
STROBE
20
VDD
May 1994
I/O
Reset input (open-drain); this input forces the 12 C-bus controller
into a predefined state; all flags are reset, except PIN, which is set.
Also functions as strobe output.
Positive supply Voltage.
3-19
. Preliminary specification
Philips ~emiconductors Video Products
PCF8584
12C-bus controller
FUNCTIONAL DESCRIPTION
General
The PCF8584 acts as an interface device between standard high-speed parallel buses and the serial
2
2
1 C-bus. On the 1 C-bus, it can act either as master or slave. Bidirectional data transfer between the
2
1 C-bus and the parallel-bus microprocessor is carried out on a byte-wise basis, using either an interrupt or polled handshake. Interface to either 80XX-type (e.g. MAB8048, MAB8051, Z80) or 68000type buses is possible. Selection of bus type is automatically performed (see Interface mode control).
Table 1 Control signals utilized by the PCF8584 for processor interfacing
type
R!W
WR
RD
MAB8049/51
NO
YES
YES
NO
NO
SCC68000
YES
NO
NO
YES
YES
Z80
NO
YES
YES
NO
YES
DTACK
lACK
The structure of the RCF8584 is similar to that of the 1 2 C-bus interface section of the MAB8400-series
of microcontrollers, but with a modified control structure. The PGF8584 has five internal register
locations. Three of these (Own Address register SO'; Clock register S2 and I nterrupt Vector S3) are
used for initialization of the PCF8584. Normally they are only written once directly after resetting of
the PCF8584. The remaining two registers function as double registers (Data Buffer/Shift register SO,
and Control/Status register S1) which are used during actual data transmission/reception. By using
these double registers, which are separately write and read accessible, overhead for register access is
reduced. SO is a combination of a shift register and data buffer. SO performs all serial-to-parallel interfacing with the 12 C-bus. S1 contains 12 C-bus status information required for bus access and/or
monitoring.
Interface mode control (I MC)
Selection of either an 80XX-mode or 68000-mode interface is achieved by detection of the WR - CS
signal sequence. The concept takes advantage of the fact that the write control input is common for
both types of interfaces. The chip is non-initialized after reset until register SO' is accessed. An 80XXtype interface is default. If a HIGH-to-LOW transition of WR (R/W) is detected while CS is HIGH, the
680DO-type interface mode is selected and the DTACK output is enabled.
Note:
The very first access to the PCF8584 after a reset must be a write access to register SO' in order to set
the appropriate interface mode.
May 1994
3-20
Phiiips Semiconductors Video Products
Preliminary specification
12C-bus controller
PCF8584
FUNCTIONAL DESCRIPTION (continued)
Set-up Registers SO', S2 and S3
Own Address Register SO'
When addressed as a slave, this register is loaded with the 7-bit 12 C-bus address to which the PCF8584
is to respond. The "Addressed As Slave" (AAS) bit in Status register S1 is set when thisaddress is
received. Programming of this register is accomplished via the parallel-bus when AO is LOW, with the
appropriate bit combinations set in Control Status register S1 (S1 is written when AO is HIGH). Bit
combinations for accessing all registers are given in Tables 4 and 5. After reset SO' has default address
'00' Hex.
Clock Register S2
Register S2 provides control OVer chip clock frequency and SCL clock frequency. S20 and S21 provide
a selection of 4 different 1 2 C-bus SCL frequencies which are shown in Table 2.
Table 2 Register S2 selection of SCL frequency
S21
S20
SCL approximate frequency
(kHz)
a
a
a
90
1
45
1
a
11
1
1
1.5
bit
S22, S23 and S24 are used for control of the internal clock prescaler. Due to the possibility of varying
microprocessor clock signals, the prescaler can be programmed to adapt to 5 different clock rates,
thus providing a constant internal clock. This is required to provide a stable time base for the SCL
generator and the digital filters associated with the 12 C-bus signals SCL and SDA. Selection for adaption
to external clock rates is shown in Table 3. After reset, a clock frequency of 12 MHz is the default value.
Table 3 Register S2 selection of clock frequency
S24
bit
S23
S22
clock frequency
(MHz)
a
x
x
3
1
a
4.43
1
a
a
1
6
1
1
a
8
1
1
1
12
Where: X
May 1994
= don't care.
3-21
Philips Semiconductors Video Products
Preliminary specification
12C-bus controller
PCF8584
Interrupt Vector S3
The interrupt vector register provides an 8-bit user-programmable vector for vectored-interrupt microprocessors. The vector is sent to the bus port when an interrupt acknowledge signal is asserted and the
ENI (enable interrupt) flag is set. Default vector values are as follows:
• Vector is '00' Hex in 80XX-mode
• Vector is 'OF' Hex in 68000-mode
On reset the PCD8584 is in the 80XX mode, thus the default interrupt vector becomes '00' Hex.
Interface Registers SO and S1
Data Shift Register SO
SO acts as serial shift register interfacing to the 12 C-bus. SO is a combination of a shift register and a data
buffer; parallel data is always written to the shift register and read from the data buffer. Serial data is
shifted in/out the shift register, and in receiver mode the data from the shift register is copied to the data
buffer during the acknowledge phase (see also PIN bit). All read and write operations to the 12 C-bus are
done via this register.
Control/Status Register S1
Register S 1 is accessed by a HI G H signal on register select input AO. To facilitate communication
between the microcontroller/processor and the 12 C-bus, register S 1 has separate read and write functions
for all bit positions.
The write-only section has been split into 2 parts:
• The ESO (Enable Serial Output) enables or disables the serial output. When ESO is LOW, register
access for initialization is possible. When ESO is HIGH, serial communication is enabled; communication with serial shift register SO is enabled and the S1 bus status bits are made available for reading.
Select control bits ES 1 and ES2 control selection of other registers for initialization and control of
normal operation. After these bits are programmed for access to .the desired register (see Tables 4
and 5), the register is selected by a logic LOW level on register select pin AO.
Note:
With ESO
May 1994
= 0, bits ENI, STA, STO and ACK of S1 can be read for test purposes.
3-22
Philips Semiconductors Video Products
Preliminary specification
12C-bus controller
PCF8584
FUNCTIONAL DESCRIPTION (continued)
Control/Status Register S1 (continued)
Table 4 Register access control; ESO = logic 0 (serial interface off)
AO
ES1
ES1
lACK
operation
H
X
X
X
READ/WRITE CONTROL REGISTER (S1)
STATUS (S 1) not available
L
0
0
X
READ/WRITE OWN ADDRESS (SO')
L
0
1
READ/WRITE INTERRUPT VECTOR (S3)
L
1
a
X
X
READ/WRITE CLOCK REGISTER (S2)
Table 5 Register access control; ESO = logic 1 (serial interface on)
AO
ES1
ES2
lACK
operation
H
X
WRITE CONTROL REGISTER (S1)
H
READ STATUS REGISTER (S1)
L
X
X
X
X
H
H
0
H
READ/WRITE DATA (SO)
L
X
1
H
READ/WRITE INTERRUPT VECTOR (S3)
X
0
X
L
READ INTERRUPT VECTOR
(acknowledge cycle)
X
1
X
L
long-distance mode
Instruction control bits ENI, STA, STO and ACK are used in normal operation to enable the interrupt
output (INT),generate 12 C-bus START and STOP conditions, and program the acknowledge response,
respectively. These possibilities are shown in Table 6.
May 1994
3-23
Preliminary specification
Philips Semiconductors Video Products
12C-bus controller
PCF8584
Table 6 Instruction table for serial bus control
STA
STO
present mode
function
operation
1
0
SLV/REC
START
transmit START 4- address
remain MST/TRM if
R/W= logic 0; go to
MST /R EC if R/W = logic 1
1
0
MST/TRM
REPEAT START
same as for SLV/REC
0
1
MST/REC
MST/TRM
STOP READ
STOP WRITE
transm it stop
go to SLV/REC mode
(see note 1)
1
1
MST
DATA CHAINING
send STOP, START and
address after last
master frame without
STOP sent (see note 2)
0
0
ANY
Nap
no operation (see note 3)
Notes to Table 6
1. In master-receiver mode, the last byte most be terminated with ACK bit HIGH ("negativeacknowledge"; see 12 C-bus specification).
2. If both STA and STO are set HIGH simultaneously in master mode, a STOP condition followed by
a START condition + address will be generated. This allows "chaining" of transmissions without
relinquishing bus control.
3. All other STA, STO mode combinations not mentioned in Table 6 are Naps .
The instruction bits are defined as follows:
• STA, STO: These bits control the generation of the 12 C-bus START condition + transmission of
slave address and R/W bit, generation of repeated START condition, and generation of the STOP
condition.
• ENI: This bit enables the external interrupt output INT, which is generated when the PIN bit
is reset.
• ACK: This bit must be set normally to a '1'. This causes the 12 C-bus controller to send an acknowledge
automatically after each byte (this occurs during the ninth clock pulse). The bit must be reset when
the 12 C-bus controller is operating in master/receiver mode, and requires no further data to be sent
from the slave transmitter. This causes a negative acknowledge on the 12 C-bus, which halts further
transmission from the slave device.
May 1994
3-24
Philips Semiconductors Video Products
Preliminary specification
12C-bus controller
PCF8584
FUNCTIONAL DESCRIPTION (continued)
12 C-bus status information
The read-only section consists of 12 C-bus status information. The functions are as follows:
• STS: When in slave-receiver mode, this flag is asserted when an externally generated STOP condition
is detected (only used in slave-receiver mode).
• BER: Bus error. A misplaced START or STOP condition has been detected.
• LRB/ADO: Last Received Bit/Address 0 "General Call" Bit. This dual function status bit holds the
value of the last received bit over the 12 C-bus when AAS == O. Normally this will be the value of the
slave acknowledge; thus checking for slave acknowledgment is done via testing of the LRB bit.
When AAS == 1 ("Address As Slave"), the 12 C-bus controller has been addressed as a slave and this
bit will be set if the slave address received was the "general call" address, or if it was the 12 C-bus
controller's slave address.
• AAS: "Addressed As Slave" bit. When acting as slave-receiver, this flag is set when an incoming
address over the 12 C-bus matches the value in Own Address register SO', or if the 12 C-bus "general
call" address ("00" Hex) has been received.
• LAB: "Lost Arbitration" bit. This bit is set when, in multmaster operation, arbitration is lost to
another master on the 12 C-bus.
• BB: "Bus Busy" bit. This is read-only flag indicating when the 12 C-bus is in use. A zero indicated
that the bus is busy, and access is not possible. This bit is set/reset by STOP/START conditions.
PIN bit
The PIN bit "Pending Interrupt Not" is a read-only flag which is used to synchronize serial communication.
Each time a serial data transmission is initiated (by setting the STA bit in the same register), the PI N will
be set automatically. After successful transmission of one byte (9 clock pulses, including acknowledge),
this bit will be automatically reset indicating a complete byte transmission. When the EN I bit is also set,
the PI N flag triggers an external interrupt via the I NT output when PI N is reset. When in receiver mode,
the PIN bit is also reset on completion of each received byte. In polled applications, the PIN bit is tested
to determine when a serial transmission has been completed. During register transfers the 12 C-bus controller
Data Register SO and its internal shift register (not accessible directly), the 12 C-bus controller will delay
serial transmission by holding the SCL line LOW until the PIN bit becomes set. In receiver mode, the PIN
bit is automatically set when the data register SO is read. When the PIN bit becomes set all status bits will
be reset, with exception of BB.
May 1994
3-25
Philips Semiconductors Video Products
Preliminary specification
12C-buscontroller
PCF8584
Multi-master operations
To avoid conflict between data and repeated START and STOP operations, multi-master systems have
some limitations:
• Transmissions requiring a repeated START conditi.on must have identical format among all potential
masters for both read and write operations
• For correct arbitration masters may only attempt to send data simultaneously to the same location,
if they use the same formats (Le. number of data bytes, location of the repeated START, etc.). If
this condition is designed not to occur, differing formats may be used.
Reset A low-level pulse on the RESET input forces the 12 C-bus controller into a well-defined state. All
flags are reset (zero state), except the PIN flag, which is set. The RESET pin is also used for the STROBE
output signal. Both functions are separated on-chip by a digital filter. The reset input signal has to be
sufficiently long (minimum 30 clock cycles) to pass through the filter. The STROBE output signal is
sufficiently short (8 clock cycles) to be blocked by the filter. For more detailed information on the
Strobe function see Special function modes.
Comparison to the MAB8400 12 C-bus interface
The structure of the PCF8584 is similar to that of the MAB8400 series of microcontrollers, but with
a modified control structure. Access to all 12 C-bus control and status registers is done via the parallelbus port in conjunction with register select input AO, and control bits ESO, ES1 and ES2. The main
differences are highlighted below.
Deleted functions
The following functions are not available in the PCF8584:
•
•
•
•
•
Always selected (ALS flag)
Access to the bit counter (BCO to BC2)
Full SCL frequency selection (2 bits instead of 5 bits)
The non-acknowledge mode (ACK flag)
Asymmetrical clock (ASC flag)
Added functions
The following functions either replace the. deleted functions or are completely new:
•
•
•
•
•
•
•
•
•
Chip clock prescaler
Assert acknowledge bit (ACK flag)
Register selection bits (ES 1 and ES2 flags)
Additional status flags
Automatic interface control between 80XX and 68000-type microprocessors
Programmable interrupt vector
Strobe generator
Bus monitor function
Long-distance mode (non-1 2 C-bus mode; only for communication between remote
parallel-bus processors)
May 1994
3-26
Philips Semiconductors Video Products
Preliminary specification
12C-bus controller
PCF8584
Special function modes
Strobe
When the 12 C-bus controller receives its own address (or the "00" Hex general call address) followed
immediately by a STOP condition (i.e. no further data transmitted after the address), a strobe output
signal is generated at the RESET/STROBE pin (pin 19). The STROBE signal consists of a monostable
output pulse (active LOW), eight clock cycles long (see Fig.10). It is generated after the STOP condition
is received, preceded by the correct slave address. This output can be used as a bus access controller for
multi-master parallel-bus systems (see Fig.14).
Long-distance mode
The long-distance mode provides a serial communication link between parallel processors using two or
more 12 C-bus controllers. This mode is selected by setting ES1 to logic 1 while the serial interface is
enabled (ESO = 1). In this mode the 12 C-bus protocol is transmitted over 4 unidirectional lines, SDA,
OUT, SCL IN, SDA IN and SCL OUT (pins 2, 3, 4 and 5). These communication lines should be
connected to the line drivers/receivers for long distance applications. Specification for long distance
transmission is then given by the chosen standard. Control of bus frequency, data transmission etc. is
the same as in normal 12 C-bus mode. After reading or writing data to shift register SO, long-distance
mode must be initialized by setting ESO and ES1 to logic 1. Because the interrupt output I NT is not
available in this operating mode, data reception must be polled.
Monitor mode
When the 7-bit Own Address register SO' is loaded with all zeros, the
2
1 C monitor. The main features of the monitor mode are as follows:
•
•
•
•
•
•
•
1
2
C-bus controller acts as a passive
The controller is always selected
The controller is always in the slave-receiver mode
The controller never generates an acknowledge
The controller never generates an interrupt request
A pending interrupt condition does not force SCL LOW
Received data is automatically transferred to the read buffer
Bus traffic is monitored by the PI N bit, which is reset after the acknowledge bit has been
transm itted and is set as soon as the first bit of the next byte is detected
May 1994
3-27
Philips Semiconductors Video Products
Preliminary specification
12C-bus controller
PCF8584
RATINGS
Limiting values in accordance with the Absolute Maximum System (lEC 134)
parameter
symbol
min.
max.
unit
Supply voltage range (pin 20)
VDD
-0.3
+ 7.0
V
Voltage range on any input*
VI
-0.8
VDD+ 0.5
V
DC input current (any input)
± II
± 10
-
10
rnA
10
rnA
300
mW
50
mW
-40
+ 85
°C
-65
+ 150
°C
DC output current (any output)
Total power dissipation
Power dissipation per output
Operating ambient temperature range
Storage temperature.range
Ptot
Po
Tamb
T stg
* Measured via a 500 .n resistor.
Note to the Ratings
Stresses above those listed in accordance with Absolute Maximum System may cause permanent damage
to the device. This is.a stress rating onlY,and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating condition for extended periods may affect reliability.
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be
totally safe, it is good practice to take normal precautions appropriate to handling MOS devices (see
'Handling MOS Devices').
May 1994
3-28
Philips Semiconductors Video Products
Preliminary specification
12C-bus controller
PCF8584
CHARACTERISTICS
Voo = 5 ± 10%; VSS = 0 V; T amb = -40 to + 85 °C; unless otherwise specified
symbol
min.
typo
max.
unit
VOO
4.5
5.0
5.5
V
note 1
note 2
1001
1002
-
-
2.5
1.5
J.lA
rnA
Input voltage lOW
note 3
VIL1
0
-
0.8
V
Input voltage HIGH
note 3
VIH1
2.0
-
Input voltage lOW
note 4
VIl2
0
VOO
0. 3V OO
V
-
Input voltage HI G H
note 4
VIH2
0. 7V OO
-
VOO
V
Resistance to VOO
Tarnb = 25 °C;
note 5
R·I
25
-
100
kn
Output current lOW
VOl=O.4V
IOl
3.0
-
-
rnA
Output cu rrent HI G H
VOH = 2.4 V;
note 6
-IOH
2.4
-
-
rnA
note 7
±llO
-
-
1
J.lA
parameter
conditions
Supply
Supply voltage range
Supply current
standby
operating
Inputs
SCl, SOA
V
Outputs
leakage current
Notes to the characteristics
1. 22 kn pull-ups on DO to 07; 10 kn pull-ups on SOA, SCl, RO; RESET tied to VSS; remaining pins
open-circuit.
2. Same as note 1, but ClK waveform with 50% duty factor at 12 MHz.
3. ClK, lACK, AO, CS, WR, RO, RESET, TTL level inputs.
4. SOA, SCl, DO to 07, CMOS level inputs.
5. ClK, lACK, AO, CS, WR.
6. DO to 07.
7. DO to 07 3-state, SOA, SCl, INT, RO, RESET.
May 1994
3-29
Philips Semiconductors Video Products
Preliminary specification
12C-bus controller
PCF8584
Timing specifications
All the timing values are valid within the operating supply voltage and ambient temperature range and
refer to V I l and V IH with an input voltage swing of VSS to V D D·
symbol
min.
typo
max.
unit
SCl clock frequency
fSCl
100
kHz
Tolerable bus spike width
parameter
12 C-bus timing
tsw
-
Bus free time
tBUF
4.7
Start condition set-up time
tsu; STA
4.7
Start condition hold time
tHD;STA
4.0
SCl lOW time
tlOW
4.7
-
SCl HIGH tim,e
tHIGH
4.0
-
SCl and SDA rise time
tr
-
-
SCl and SDA fall time
tf
Data set-up time
tsu; DAT
250
tHD; DAT
a
Data hold time
SCl lOW to data out valid
tVD; DAT
-
Stop condition set-up time
tsu; STO
4.0
May 1994
3"30
100
ns
-
J.lS
-
J.lS
-
J.lS
-
J.lS
1.0
J.lS
0.3.
J.lS
-
ns
3.4
J.lS
-
J.lS
J.lS
ns
Philips Semiconductors Video Products
Preliminary specification
12C-bus controller
PCF8584
Parallel interface timing (see Figs 3 to 10)
All the timing limits are valid within the operating supply voltage and ambient temperature range and
refer to VIL and VIH with an input voltage swing of VSS to VDD.
CL = 100 pF, R L = 1.5 kU (connected to VDD) for open-drain and high-impedance outputs, where
applicable (for measurement purposes only).
parameter
figure
symbol min. typo
Clock rise time
3
tr
-
Clock fall time
3
tf
-
I nput clock period
(50% duty factor)
3
tCLK
83
CS set-up to RD, WR LOW
4
tSUl
30
CS hold from RD, WR HIGH
4
tHDl
0
AO set-up to RD, WR LOW
4
tSU2
10
tHD2
20
tWl
230
max.
unit
-
6
ns
6
ns
-
333
ns
-
ns
-
ns
-
ns
-
ns
AO hold from RD, WR HIGH
4
W R pu Ise width
4
R D pu Ise width
4
tW2
Data set-up before WR HIGH
4
tSU3
150
-
-
ns
Data valid after RD LOW
4
tVD
-
110
180
ns
Data hold after WR HIGH
4
tHD3
30
-
-
ns
Data bus floating after RD HIGH
4
tFL
70
5 and 6
tSU4
30
-
ns
AO set-up to CS LOW
R/WR set-up to CS LOW
5 and 6
tSU5
30
-
-
ns
Data val id after CS LOW
5
tVDl
110
180
ns
5 and 6
tdl
-
3tCLK+ 75
3tCLK+ 150
ns
AO hold from CS HIGH
5 and 6
tHD4
0
-
ns
R/WR hold from CS HIGH
5 and 6
tHD5
0
Data hold after CS HI G H
5
tHD6
160 -
-
ns
DTACK HIGH from CS HIGH
5 and 6
td2
-
100
120
ns
-
ns
-
ns
DT ACK LOW after
CS LOW
230
-
ns
-
ns
ns
ns
Data hold after CS HI G H
6
tHD7
0
Data set-up to CS LOW
6
tSU6
0
-
INT HIGH from lACK LOW
7 and 8
td3
-
130
180
ns
Data valid after lACK LOW
7 and 8
tVD2
-
140
190
ns
May 1994
3-31
Philips Semiconductors Video Products
Preliminary specification
12C-bus controller
PCF8584
Parallel interface timing (continued)
typo
max.
unit
230
-
-
ns
100
-
-
ns
td4
-
3tCLK+ 75
3tCLK+ 150
ns
td5
-
120
140
ns
-
ns
-
ns
symbol min.
parameter
figure
lACK pulse width
Data hold after lACK HIGH
7 and 8 tW3
7 and 8 tHD8
DTACK LOW from lACK LOW
8
DTACK HIGH from rACK HIGH
8
Reset pulse width
9
tW4
30tCLK
-
Strobe pu Ise width
10
tW5
8tCLK
8tCLK+ 90
Notes to parallel interface timing
1. A minimum of 6 clock cycles must elapse between consecutive parallel-bus accesses when the
12 C-bus controller operates at 8 or 12 MHz. This may be reduced to 3 clock cycles for lower
operating frequencies.
2. After reset the chip clock default is 12 MHz.
elK
MLA013
Fig.3 Clock input timing.
May 1994
3-32
Philips Semiconductors Video Products
Preliminary specification
12C-bus controller
PCF8584
Timing diagrams
AO
WR
DO to D7 - - - - - - - - - - - [
MLA014
(a)
cs
AO
DO to D7
--------+---l
- - tVD--
MLA015
(b)
Fig. 4 Bus timing (80XX-mode); (a) write cycle, (b) read cycle.
May 1994
3-33
Preliminary specification
Philips Semiconductors Video Products
12C-bus controller
PCF8584
AO
RiW
- - tSU5 ---
DO to 07
--------+--{
tV01---
DATA VALID
--
OTACK
- - - td1 -
---
Fig.5 Bus timing; 68000-mode read cycle.
May 1994
3-34
MLA016
Preliminary specification
Philips Semiconductors Video Products
12C-bus controller
PCF8584
AO
Rm
- - tSU5--
DO to 07
DATA VALID
--tSU6---
DTACK
- - td1 - - MLA017
Fig.6 Bus timing; 68000-mode write cycle.
May 1994
3-35
Preliminary specification
Philips Semiconductors Video Products
12C-bus controller
PCF8584
INT
-
tW3--
lACK
---
tVD2
--
DO to 07 - - - - - - - - - - - - {
DATA VALID
MLA018
Fig.7 Interrupt timing; 80XX-mode.
---
td3
INT
lACK
\
---
I
1\
tVD2
-V
t W3 - -
-/
\
DO to 07
/
/
---
--
tHD8
DATA VALID
\
I
--td4-
II
\
DTACK
/
\
--Fig.8 Interrupt timing; 68000-mode.
May 1994
3-36
td5
--
MLA019
Philips Semiconductors Video Products
Preliminary specification
12C-bus controller
elK
RESET
PCF8584
lJUlJlJlJlJ1Jlf---~
~~
1--.- - - -
~~
.1
____________
(3_0_C_YC_le_S_m_i_ni_m_U_m_)____________
tW4
MLA020
Fig.9 Reset timing.
elK
STROBE
I.
__- - - - - - tW5
-------i.~1
MLA021
Fig.10 Strobe timing.
May 1994
3-37
Philips Semiconductors Video Products
Preliminary speCification
12C-bus controller
PCF8584
APPLICATION INFORMATION
"-
.A
K
ADDRESS BUS
MAB8048/
MAB8051
V
U
"'I
~
o'ECODER
~
~
SC
I.
"-
.A
K
DATA
"'I
-
)
\
PCF8584
v
SDA
RD
+---+
-
WR
~
-
INT
7Z28116
Fig.11 Application diagram using the MAB8048/MAB8051.
AS
UDS
-
LDS
DECODER
-
CS
ADDRESS
"
..
./
A1
A1,A2,A3
SCN68000
~
FCX
IPX
INTERRUPT
HANDLER
INTERRUPT
REQUEST
~
lACK
PCF8584
-INT
I..SDA~
R/W
-DTACK
A
K'f
DATA
")
..
7Z28117
Fig.12 Application diagram using the SCN68000.
May 1994
3-38
Philips Semiconductors Video Products
Preliminary specification
12C-bus controller
PCF8584
"-
A
"-'I
~
ADDRESS BUS
D
DECODER
v
~
~
-
MAB8088
SCL
lOR
~
-
lOW
K
DATA
'I
INTR
--"
PCF8584
t-.
A
>
SDA
~
-----.":.
INT
,..
-
lACK
7Z28115
Fig.13 Application diagram using the 8088.
May 1994
3-39
Preliminary specification
Philips Semiconductors Video Products
PCF8584
12 C...;bus controller
GLOBAL SYSTEM BUS
12C-BUS
7Z28118
Fig.14 STROBE as bus access controller.
Purchase of Philips' 12 C components conveys a license under the
Philips' 12 C patent to use the components in the 12 C-system
provided the system conforms to the 12 C specifications defined
by Philips.
May 1994
3-40
Philips Semiconductors Video Products
Product specification
Universal sync generator (USG)
FEATURES
• Programmable to seven standards
• Additional outputs to simplify
signal processing
• Can be synchronized to an external
sync. signal
• Option to select the 524/624 line
mode instead of the 525/625 line
mode
• Lock from subcarrier to line
frequency
GENERAL DESCRIPTION
SAA1101
QUICK REFERENCE DATA
SYMBOL
Voo
100
fosc
-
-
MAX.
UNIT
V
5.5
10
24
~
MHz
ORDERING AND PACKAGE INFORMATION
EXTENDED
TYPE NUMBER
SAA1101P
SAA1101T
The SAA1101 is a Universal Sync
Generator (USG) and is designed for
application in video sources such as
cameras, film scanners, video
generators and associated
apparatus. The circuit can be
considered as a successor to the
SAA 1043 sync generator and the
SAA1044 subcarrier coupling IC.
January 1990
MIN.
4.5
PARAMETER
supply voltage range (pin 28)
quiescent supply current
clock oscillator frequency
3-41
PACKAGE
PINS I PIN POSITION I MATERIAL
plastic
DIL
28 I
S028
28
I plastic
I
CODE
1
SOT117
SOT136A
Product specification
Philips Semiconductors Video Products
Universal sync generator (USG)
SAA1101
CSO CS1 CLO
NORM
SI
13
18
CS
CB
BK
10
OSCI
HD
VD
OSCO
WMP
CLP
12
25
VLE
26
27
11
FSI
FSO
PHASE
DETECTION
9
10
7Z24897
Voo
PH
VSS
Fig.1 Block diagram.
January 1990
RR
3-42
LM1
LMO
ECS
Philips Semiconductors Video Products
Product specification
Universal sync generator (USG)
SAA1101
PINNING
SYMBOL
FSI
FSO
CS1
CSO
OSCI
OSCO
VLE
PH
LM1
LMO
ECS
RR
FUNCTIONAL DESCRIPTION
Generation of pulses
Generation of standard pulses such
as sync, blanking and burst forTV
systems: PAL BIG, PALN, PALM,
SECAM and NTSC. In addition a
number of non-standard pulses have
been supplied to simplify signal
processing. These signals include horizontal drive, vertical drive, clamp
pulse, identification etc. It is possible
to select the 524/624 line mode
instead of the 525/625 line mode for
all the above TV systems for applications such as robotics, games and
computers.
January 1990
3
4
5
6
7
8
9
10
11
DESCRIPTION
subcarrier oscillator input, where f max =5 MHz
subcarrier oscillator output
clock frequency selection - CMOS input
clock frequency selection - CMOS input
clock oscillator input, where f max =24 MHz
clock oscillator output
vertical in-lock enable - CMOS input
phase detector output - 3-state output
lock mode selection - CMOS input
lock mode selection - CMOS input
external composite sync. signal- CMOS Schmitt-trigger
input
12
13
frame reset - CMOS Schmitt-trigger input
set identification, used to set the correct field sequence
in PAL-mode. The correction (inversion of fH2) is done at
the left-hand slope of the SI-pulse. Minimum pulse width
is 800 ns. CMOS Schmitt-trigger input.
Vss
ID
BK
14
15
ground
identification - push-pull output
burst key (PAUNTSC), chroma-blanking (SECAM) push-pull output
CB
17
18
composite blanking - push-pull output
composite sync. - push-pull output
19
20
21
clamp pulse - push-pull output
white measurement pulse - 3-state output
vertical drive pulse - push-pull output
22
23
horizontal drive pulse - push-pull output
used with X, Y and Z to select TV system; NORM =0,
625/525 line mode (standard); NORM =1,624/524 line
mode - CMOS input
clock output - push-pull output
TV system selection input - CMOS input
SI
Fig.2 Pinning configuration;
SOT117.
PIN
1
2
CS
CLP
WMP
VD
HD
NORM
16
Y
24
25
26
Z
27
TV system selection input - CMOS input
TV system selection input - CMOS input
VDD
28
voltage supply
CLO
X
3-43
Philips Semiconductors Video Products
Product specification
Universal sync generator (USG)
Lock modes
The USG offers four lock modes:
•
•
•
•
Lock from the subcarrier
Slow sync. lock, external H ref
Slow sync. lock, internal H ref
Fast sync. lock, internal Href
LOCK FROM SUBCARRIER
Lock from subcarrier to the line.
frequency for the above mentioned
TV systems is given below; the
horizontal frequency (fH) = 15.625
kHz for 625 line systems and
15.734264 kHz for 525 line systems.
SECAM (1 and 2)
PALN
NTSC (1 and 2)
PALM
PAL BIG
282f H
229.2516f H
227.5fH
227.25f H
283.7516f H
SAA1101
SELECTION OF LOCK MODE
of internal and external frames will
result in the addition or suppression of one line depending on the
direction of the fault. The
maximum lock time for frame lock
is 6.25 s, see Fig. 3(b).
Lock mode is selected using the
inputs LMO and LM1 as illustrated in
the Table below.
2. Sync. lock fast. A fast lock of
frames is possible with a frame
reset which is extracted out of the
incoming external sync. signal,
see Fig. 3(c).
LMO LM1
3. Sync. lock with external reference.
Lock of an external sync. signal to
the line frequency with an external
line reference to make possible a
shifted lock. The subcarrier input
is, in this case, used as an external
input for the horizontal reference,
see Fig. 3(d).
These relationships are obtained by
the use of a phase locked loop and
the internal programmed divider
chain, see Fig. 3(a).
0
0
0
1
0
1
1
1
SELECTION
lock to subcarrier
slow sync. lock
external Href
slow sync. lock
internal Href
fast sync. lock internal
Href
The different lock modes are illustrated by the following figures:
PH
SUB·
LOCK TO AN EXTERNAL SIGNAL
SOURCE
CARRIER
OSCILLATOR
The following methods can be used
to lock to an external signal source:
1. Sync. lock slow; the line frequency
is locked to an external signal. The
line and frame information are
extracted from the external sync.
signal and used separately in the
lock system. The line information
is used in a phase-locked loop
where external and internal line
frequencies are compared by the
same phase detector as is used
for the sUbcarrier lock. The
external frame information is
compared with the internal frame
in a slow lock system; mismatch
January 1990
logic a
logic a
7Z24899
Fig.3(a) Lock to subcarrier.
SAA1101
10
LMO
logic 1
LM1
logic 0
3-44
7Z24901
Fig.3(b) Slow sync lock,
internal H ref
Product specification
Philips Semiconductors Video Products
Universal sync generator (USG)
SAA1101
LOCK WITH HORIZONTAL AND
VERTICAL SIGNALS
(slow lock modes only)
SAA1101
10
LMO
Fig.3(c) Fast sync lock,
internal Href
LM1
logic 1
7Z24902
logic 1
Fig.3(d) Slow sync lock,
external H ref
Selection of Clock Frequency
The clock frequency is selected using the CSO and CS1 inputs as illustrated
below.
CSO
CS1
FREQUENCY
625 LINES
525 LINES
UNITS
0
0
1
1
0
1
0
1
160fH
320fH
960fH
1440fH
2.5
5
15
22.5
2.517482
5.034964
15.104893
22.657340
MHz
MHz
MHz
MHz
Where the horizontal frequency, fH = 15.625 kHz for 625 lines anp
15.734264 kHz for 525 lines.
January 1990
3-45
It is possible to use horizontal and
vertical signals instead of composite
sync signals. The connections in this
situation are: the external horizontal
signal is connected to the ECS input
(pin 11) and the vertical signal to the
RR input (pin 12). The HIGH time of
the horizontal pulse must be less than
14.4 J.LS, otherwise it will be detected
as being a vertical pulse and will
corrupt the vertical slow lock system.
Philips Semiconductors Video Products
Product specification
Universal sync generator (USG)
SAA1101
Oscillators
The subcarrier oscillator has FSI as
its input and FSO as its output. It is
always used as a crystal oscillator
with a series resonance crystal with
parallel load capacitor. The maximum
frequency, f max = 5 MHz and the load
capacitor, C L = 10 < C L < 35 pF.
39 pF
OSCI
~l
5
500 [
15MHZr
~
The clock oscillator has OSCI as its
input and OSCO as its output. It can
be used with an LC oscillator or a
series resonance crystal with parallel
load capacitor (Fig.4). The maximum
frequency, f max = 24 MHz and the
load capacitor, C L =10 < CL < 35 pF.
kn
SAA1101
~
6
1
39 pF
kn
OS CO
7Z24903
Fig.4 Crystal oscillator circuit.
Selection of TV System
Selection of the required TV system is achieved by the X, Y and Z inputs as
illustrated by the following Table.
Selection of 625/525 (standard;
interlaced mode) or 624/524 lines
(non-interlaced mode)
Selection is achieved using the
NORM input. When NORM = 0, 6251
525 (standard) lines are selected;
when NORM = 1, 624/524 line are
selected.
Output Dimensions
All push-pull outputs: standard
output 2 mA.
SYSTEM
SI;CAM1
PALN
NTSC1
PALM
SECAM2
PAL BIG
NTSC2
Phase detector, PH: 3-state output
2mA.
January 1990
Y
0
0
0
0
1
1
1
0
0
1
1
0
0
1
Z
0
1
0
1
o(with identifier)
1
o(short blanking)
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
PARAMETER
SYMBOL
Voo
V,
I,
10
100
White measurement pulse, WMP:
3-state output 2 mA.
X
Ptot
Tsta
supply voltage
input voltage
maximum input current
maximum output current
maximum supply current in Voo
maximum power dissipation
storage temperature range
• Input voltage should not exceed 7 V.
3-46
MIN.
-0.5
-0.5
-
-55
MAX.
UNIT
V
+7
Voo + 0.5' V
'mA
±10
mA
±10
mA
25
mW
400
+150
°C
Philips Semiconductors Video Products
Product specification
Universal sync generator (USG)
SAA1101
CHARACTERISTICS
VDD = 4.5 to 5.5 V· Tamb = -25 to +70 oC unless otherwise specified
SYMBOL
I
PARAMETER
I
CONDITIONS
I
MIN. I TYP.
I MAX. I UNIT
Supplies
VDD
IDD
supply voltage
[ supply current (quiescent)
1
Tamb =25 °C
1
~.5
1
Inputs
input leakage current
I
I Tamb =25 °C
I -
I
-
I
100
I nA
CMOS COMPATIBLE; X, Y, Z, NORM, CSO, CS1 , LMO, LM1 AND VLE
input voltage HIGH
input voltage LOW
1
I
1
~.3VDD ~
1
SCHMITT TRIGGER INPUTS; ECS, RR AND SI
I
positive-going threshold
negative-going threshold
hysteresis
I
OSCILLATOR INPUTS; ascI AND FSI
1
input voltage HIGH
input voltage LOW
1
Outputs
PUSH-PULL OUTPUTS; CB, CS, BK, ID, HD, VD, CLP AND CLO
VOH
1output voltage HIGH
VOL
output voltage LOW
1-10 = 2 rnA; V DD = 5 V
10 = 2 rnA; V DD = 5 V
-
-
4.5
1 -
1 -
1
0.5
I~
OSCILLATOR OUTPUTS; OSCO AND FSO
VOH
1output voltage HIGH
VOL
output voltage LOW
1-10 =0.75mA;VDD =5V 1 4.5
10 = 0.75 rnA; V DD = 5 V
-
-
-
1 -
1
0.5
I~
3-STATE OUTPUTS; WMP AND PH
VOH
VOL
±I oz
January 1990
Ioutp"t voltage
HIGH
Otltput voltage LOW
OFF-state current
1-'100==22rnA;
mA; Voo =5 V
V =5V
DD
Tamb = 25°C
3-47
4.5
-
I- I
-
-
-
I
0.5
50
I~A
Product specification
Philips Semiconductors Video Products
SAA1101
Universal sync generator (USG)
OUTPUT WAVEFORMS
The output waveforms for the different modes of operation are illustrated by
Figs5and6.
: start half picture
(1) H = 1 horizontal scan.
Fig.5 Typical output waveforms for PAUCCIR and SECAM. In the 624-line
mode the output waveforms are identical to the first half picture of PAUCCIR
and are not interlaced.
January 1990
3-48
Philips Semiconductors Video Products
Product specification
Universal sync generator (USG)
SAA1101
e=~========~~===========·Lr
UL
I
I
I I I I
----------------·LnLrrJl
UUUL
7Z24906
(1) H = 1 horizontal scan.
(2) NTSC mode reset; the fourth half picture is identical to the second half
picture for NTSC.
Fig.6 Typical output waveforms for NTSC and PAL-M. In the 524-line mode the
output waveforms are identical to the first half picture of NTSC and are not
interlaced.
January 1990
3-49
Philips Semiconductors Video Products
Product specification
Universal sync generator (USG)
SAA1101
WAVEFORM TIMING
The waveform timing depends on the frequency of the oscillator input (fosd. This is illustrated in the table below as the
number (N) of oscillations at OSCI. The timings are derived from N x tOSCI ± 100 ns.
One horizontal scan (H) =320 x tOSCI = 1/fH .
Where tOSCI = 200 ns for PAUSECAM and 198 6 ns for NTSC/PAL-M
SYMBOL
PARAMETER
NTSC
PAL-M
SECAM
4.8
4.77
4.77
4.8
~s
24
2.4
4.8
2.5
2.38
4.77
3
2.38
4.77
3
2.4
4.8
2.5
~s
~s
12
24
H
-
2.5
3
3
2.5
H
2.5
3
3.5
2.5
H
-
11.12
PAL
UNIT
N
Composite sync (CS)
t WSC1
t WSC2
tWSC3
-
horizontal sync pulse
width
equalizing pulse width
serration pulse width
duration of pre-equalizing
pulses
duration of post-equalizing pulses
duration of serration
pulses
Composite blanking (CB)
HORIZONTAL BLANKING PULSE WIDTH
t WCB
t WCB
t WCB
PAUSECAM/PAL-M
NTSC1
NTSC2
12
-
11.12
10.53 *
1.6
1.59
12
~s
-
-
~s
-
-
~s
60
56
53
1.6
~s
8
FRONT PORCH
tpCBCS
front porch
1.59
DURATION OF VERTICAL BLANKING
PAUSECAM/PAL-M
NTSC1
NTSC2
25H +tWCB
-
-
21H +tWCB
19H +tWCB
-
21H +tWCB
-
25H +tWCB
-
-
-
-
-
-
-
12
28
Burst key (BK) (not SECAM)
tWBK
tpCSBK
*
January 1990
burst key pulse width
CS to burst key delay
burst suppression
2.38
5.56
9
2.4
5.6
9
Horizontal blanking pulse width for NTSC2 can be 11.12 ~s maximum
3-50
2.38
5.76
11
-
~s
-
~s
-
H
Product specification
Philips Semiconductors Video Products
SAA1101
Universal sync generator (USG)
SYMBOL
NTSC
PAl-M
SECAM
H623 to H6
H310to H318
H622 to H5
H311 to H319
H523 to H6
H261 to H269
H523 to H6
H261 to H269
H523 to H8
H260to H270
H522 to H7
H259 to H269
-
-
-
-
-
-
-
7.2
1.6
Il s
Il s
-
-
-
note 1
note 2
2.4
1.6
2.38
1.59
2.38
1.59
2.4
1.6
Il s
Il s
12
8
7.2
0.8
64
7.15
0.79
63.56
7.15
0.79
63.56
7.2
0.8
64
Il s
Il s
Il s
36
4
10
1.6
6
1.59
6
1.59
10
1.6
Il s
8
2.4
34.4
10
2.38
34.16
9
2.38
34.16
9
2.4
34.4
10
Il s
Il s
H
12
172
PARAMETER
PAL
UNIT
N
Burst key (BK) (not SECAM) (continued)
POSITION OF BURST SUPPRESSION
first half picture
second half picture
third half picture
fourth half-picture
-
Burst key (BK) (SECAM)
tWBK
tpBKCS
chroma pulse width
CS to chroma delay
-
36
8
DURATION OF VERTICAL BLANKING
SECAM1
SECAM2
-
Clamp pulse (ClP)
tWCLP
tpCSCLP
clamp pulse width
CS to CLP delay
Horizontal drive (HO)
tWHD
tpHDCS
pulse width
CS to HD delay
repetition period
Vertical drive (VO)
tpVDCS
VD duration
CS to VD delay
H
White measurement pulse (WMP)
pulse width
CS to WM P delay
duration of WMP
January 1990
3-51
Philips Semiconductors Video Products
Preliminary specification
Teletext video processor
FEATURES
• Adaptive data slicer
• Crystal-controlled data clock
regeneration with a bit rate of
6.9375 MHz
• Adaptive sync separator, horizontal
phase detector and 13.5 MHz
VCO to provide display phase
locked loop (PLL)
• TV synchronization at teletext
mode
'SAA5191
QUICK REFERENCE DATA
SYMBOL
MIN.
PARAMETER
Vp
supply voltage (pin 16)
Ip
supply current
Vi eVBS
CVBS input signal on pin 27
(peak-to-peak value)
-
atpin2 LOW
at pin 2 open-circuit
Vo
V F13
VSYNC
VCS
GENERAL DESCRIPTION
The SAA5191 is a bipolar integrated
circuit that extracts teletext data from
the video signal (CVBS), regenerates
the teletext clock (TIC) and
synchronizes the text display to the
television signals (VCS). This device
operates in conjunction with the
Digital Video Teletext (back-end)
Decoder (DVTB - SAA9042A) or any
other compatible device.
March 1991
Tamb
TYP.
MAX.
UNIT
12
-
V
70
-
mA
1
-
V
2.5
V
output signals TIC and TID
(peak-to-peak value, pins 14, 15) 2.5
3.5
4.5
V
13.5 MHz clock output signal
(peak-to-peak value, pin 17)
1
2
3
V
video sync output signal
(peak-to-peak value, pin 1)
-
-
1
V
SYNC output signal TCS
200
450
650
mV
video composite sync level
on output pin 25
LOW
-
0.4
V
HIGH
2.4
5.5
V
0
+70
°C
operating ambient temperature
ORDERING AND PACKAGE INFORMATION
EXTENDED
TYPE NUMBER PINS
SAA5191
28
3-52
PACKAGE
PIN POSITION
OIL
MATERIAL
CODE
plastic
SOT117
~
III
a;i
(1
~
<0
CD
r-+
CD
X
r-+
~
v
~.
~
VCS
24
25
PC
23
:lr
CBB
22
21
10
<
0:
V';1
::L
19
20
+12V
18
16
F13
(13.5 MI
clock)
1
28
TCS
l;=J
SENSE
r-r- r-"NO INPUT"
composi te
video
input
w
tn
w
+
---1
~II
II
27
ADAPTIVE rSYNC
SEPARATOR t--
SAA5191
:L
~
~ HORIZONTAL
PULSE
GENERATOR
~
PHASE
~
DETECTOR
ADAPTIVE
DATA
SLICER
VCO
(")
CD
en
en
0...,.
LATCHES
T
DUAL
POLARITY
BUFFER
17
CD
0
"'0
...,.
0
CLOCK
PHASE
DETECTOR
rl
[>~ -.
I
I
[>~ -.
TID
(data)
TIC
(clock)
26
.-.
SENSE
"NO LOAD"
~
12
PHASE
SHIFTER
SENSE
EXTERNAL
DATA
GAIN
SWITCH
~
U
HFLOSS
COMPENSA TOR
r
2
!: input
set video
level
sync output
~
3
4
5
1
6
8
t;
OSCILLATOR
DIVIDER
BY2
7
9
11
11
13
GND
I I
~
t!l
data
input
Fig.1 Block diagram.
I
C:::J
XTAL
4;3.875 MHz
l',~
~..U::'-'1.4Q
en
»
»
01
-.L
c.o
-.L
-c
~
3·
:r
III
-'" 12V
+ 12V
TCS
PI.
VCS
~
470
0
CVBS
15
IJH
sakn
F13
10 nF
6.8pF
TID
(1) (2)
23
22
21
20
19
18
17
16
15
15
IJH(4)
SAA5191
27
pF
TIC
I
.....
: h.2kn
'T'
dala
input
•
I
~
CBB
MEH1S6
22 pF
47 nF
21
20
19
18
SAA5191
(1) inductance 15!1H at 1 kHz, Co = 2.2 pF. Adjust free-running frequency to 13.5 ± 0.1 MHz
or apply 13.5 MHz quarz crystal as shown in additional drawing
(2) Crystal: f", 13.5 MHz (e.g. Philips catalogue number 4322143 04101); adjustmenttolerance ±40. 10-6 ;
load capacitance CL = 22 pF; resonance resistance Rr = 22 pF; typical motional capacitance C,
= 23 fF;
static parallel capacitance Co = 5.5 pF; frequency tolerance ±3Q. 10-6 in temperature range
T .. -20 to +700 . Adjust free-running frequency to 13.5 ± 0.5 MHz.
(3) Crystal: f .. 13.875 MHz; adjustment tolerance ±40· 10-6 ; load capacitance CL = 15 pF; typical
resonance resistance Rr
= 15 0
(maximum 60 0); typical motional capacitance Cl = 19 fF; static
parallel capacitance Co = 5 pF; frequency tolerance ±30.10-6 in temperature range T =-20 to +700 .
(4) Coil: Fixed inductance 15 !1H ±20%, quality factor Q > 20.
Fig.3 Test circuit and application circuit using LC-circuit or a crystal for VCO (clock F13).
March 1991
3-57
Philips Semiconductors Video Products
Preliminary specification
Teletext video processor
SAA5231
GENERAL DESCRIPTION
The SAA5231 is a bipolar integrated circuit intended as a successor to the SAA5030. It extracts Teletext Data from the video signal, regenerates Teletext Clock and synchronizes the text display to the
television syncs. The integrated circuit is intended to work in conjunction with CCT (Computer
Controlled Teletext), EUROM or other compatible devices.
Features
• Adaptive data slicer
• Data clock regenerator
• Adaptive sync separator, horizontal phase detector and 6 MHz VCO forming display phase
locked loop (PLL)
QUICK REFERENCE DATA
Supply voltage (pin 16)
Supply current (pin 16)
Video input amplitude (pin 27) (peak-to-peak value)
pin 2 LOW
pin 2 HIGH
Storage temperature range
Operating ambient temperature range
November 1986
in~line;
typo
12 V
typo
70 rnA
V27-13(p-p)
typo
1 V
V27-13(p-p)
T stg
typo
2,5 V
Tamb
PACKAGE OUTLINE
28-lead dual
VCC
ICC
plastic (SOT117).
3-58
-20 to + 125 °C
o to + 70
°C
z
~
3
;So
r-+
3
g.
~
ro
CD
~
m
<
(ves)
sandcastl.
input pulse
(PL/C88)
video recorder
mod. input
Vec
(VCR)
(+12V)
sync Input
or
an composite
sync input
1--------'-1'11-- e ':tz,::~
c:
~
iil
o
"0
a.
~
CD
8.
~
(J)
(J)
(m)
:::l
a.
:s;
ao
telCt composite
f/)
en
CD
0:
CD
video composite
sync output
~
rot
~
C"
"tI
o-C
(Fel
(SCSI
.Ieta.ct date
OU,put
CTTDI
Co)
composite
video input
.letext"c:1ock
output
(TTC)
&.
co
Fig. 1 Block diagram.
"tI
en
~
(J1
I\)
~
....t.
i
3·
:r
I»
-<
f/)
I
o
~
o
:::l
Philips Semiconductors Video Products
Preliminary specification
Teletext video processor
SAA5231
PINNING
text comp
sCo
(D
o
-C
8.c:
~
_."
,<::J
17
.{~
-;;;
~.
g
x;::::;:
1I
CHANNEL
COMPARATOR
HAMMING
CORRECTOR
.7
DB7
CD
_ 0
el>
Sl)"""
:::JQ.
Q.Sl)
Sl)"""Sl)
Q.Sl)
-0
CD.!)
CD c:
CD (J) •
(D
ALE
_
21 .' ~
RD
ro::J
Q.
3
0'
-
~o
,::J
o"""
WR
FORMAT
PROCESSOR
FORMAT
TRANSCOOER
FI
FORMAT
COUNTER
2 K BYTE
FIFO MEMORY
CONTROLLER
SAA5250
n-
VALIDATION
SIGNAL
PROCESSING
.
MEMORY INTERFACE
,---------+-L-t1----tsJ1l,.39'30 JSL29.22
1
1 U
MS
We
A10
to AO
U
07 to DO
-c
f40 };o
T
VOO
Vss
~
CJ)
7Z96680
»
»
01
I\:)
Fig. 1 Block diagram.
01
o
3'
::r
II>
-
~
g
Philips Semiconductors Video Products
Preliminary specification
Interface for data acquisition and control
(for multi-standard teletext systems)
VAL INt
SYNC
SAA5250
AS
A7
AS
A4
A3
A2
At
OBS
AO
OB4
07
OB3
08
OB2
05
OB1
04
DBO
03
ALE
02
Ot
DO
R5
lZ96674
Fig. 2 Pinning diagram.
November 1987
3-71
Preliminary specification
Philips Semiconductors Video Products
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
PINNING FUNCTION
mnemonic
pin no.
function
A10and
AO to A9
hnd
30 to 39
Memory address outputs used by CIOAC to address a 2 K byte buffer
memory
VAL OUT
2
Validation output signal used to control the location of the window
for the framing code
VAL IN/SYNC
3
Validation input signal (line signal) used to give or calculate a window
for the framing code detection
CBB
4
Colour burst blanking output signal used by the SAA5230 as a data
slicer reset pulse
OCK
5
Data clock input, in synchronization with the serial data signal
SO
6
Serial data input, arriving from the demodulator
MS
7
Chip enable output signal for buffer memory selection
WE
8
Write command output for the buffer memory
OB7 to 080
9 to 16
8-bit three state input/output data/address bus used to transfer
commands, data and status between the CIOAC registers and the CPU
ALE
17
Oemultiplexing input signal. for the CPU data bus
CE
18
Chip enable input for the SAA5250
WR
19
Write command input (when LOW)
VSS
RO
20
ground
21
Read command input (when LOW)
DO to 07
22 to 29
8-bit three state input/output data bus used to transfer data between
CIDAC and the buffer memory
VOO
40
+5 V power supply
November 1987
3-72
Philips Semiconductors Video Products
Preliminary specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
FUNCTIONAL DESCRIPTION
Microcontroller interface
The microcontroller interface communicates with the CPU via the handshake signals OB7 - OBO,
ALE, CS, RO, WR. The microcontroller interface produces control commands as well as programming
the registers to write their contents or read incoming status/data information from the buffer memory.
The details of the codes used to address the registers are given in Table 2.
The CIOAC is 'MOTEL' compatible (MOTEL compatible means it is compatible with standard
Motorola or Intel microcontrollers).ltautomatically recognizes the microcontroller type (such as the
6801 or 8501) by using the A LE signal to latch the state of the R 0 input. No external logic is required.
Table 1 Recognition signals
~
CIOAC
8049/8051
timing 1
6801/6805
timing 2
ALE
ALE
AS
RD
i:i'n
IlV
WR
WR
RtW
Table 2 CIOAC register addressing
IZ
w
codes
~
CL
o..J
OS, E, 4>2
R
W
CS
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
OB2
OBl
OBO
function
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
write
write
write
write
write
write
write
write
0
0
0
1
0
read status
read data register
test (not used)
test (not used)
W
>
W
C
November 1987
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
3-73
register RO
register R1
register R2
register R3
register R4
register R5
command register R6 (initialization command)
register R7
Preliminary specification
Philips Semiconductors Video Products
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
Register organization
ROregister
Table 3 RO Register contents
R04
slow/fast mode
R03
parity
R02 to ROO
used prefixes
a = slow mode
a = no parity control
1 = fast mode
1 = odd parity
000 =OIOON long
001 to: 01 DON medium
010 = OIDON short
011 = not used
100 =U.K. teletext.
101 = NABTS
110\'h
f
111 I WIt out pre IX
~.
.
magazine end row address group
MRAG
A
format
A1
A2
A1
. A2
DIDON
short
DIDON
medium
DIDON
long
r-Fc--I
L.. _ _
[--~--I
A3
CI
format
I·II~
A1
A2
A3
CI
PS
lZ9667S
Fig. 3 Five prefixes.
All of the bytes (see Fig. 3) are Hamming protected. The hatched bytes are always stored in the
memory in order to be processed by the CPU (see section 'Prefix processing'). In the mode without
prefix all of the bytes which follow the framing code are stored in the memory until the end of the
data packet, the format is then determined by the contents of the R3 register.
If R03 = 0; no parity control is carried out and the 8-bits of the incoming data bytes are stored in the
fifo memory.
If R03 = 1; the 8th bit of the bytes following the prefix (data bytes) represents the result of the odd
parity control.
If R04 =0; the device operates in the slow mode. The CIDAC retrieves data from the user selected
magazine (see section 'Rl and R2') and without searching for a start to a page stores the data into the
FIFO memory.
November 1987
3-74
Philips Semiconductors Video Products
Preliminary specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
If R04 = 1; the device operates in the fast mode. Prior to writing into the FIFO memory, the CIDAC
searches for a start to a page which is variable due to the different prefixes:
• DIDON (long, medium and short): using the redundant bytes, SOH RS, X RS and SOH X (where X
is a bit affected by a parity error)
• NABTS, the least significant bit of the PS byte is set to 1
• U.K. teletext, ROW = 0
R1 register
Table 4 R1 Register contents
~
~
....
ffi
:iE
a-
S
~
w
c
R17
VAL IN/SYNC
R16 to R14
format table
1 = VAL
0= SYNC
000
001
010
011
1XX
R13 to R10
channel numbers (first digit)
= list 1
= list 2
= list 3
= list 4
= maximum/default value used
first digit hexadecimal value
(R3)
Note
X =don't care
If VAL IN/SYNC = 1; the line signal immediately produces a validation signal for the framing code
detection.
If VAL OUT =0; the line signal is used as a starting signal for an internally processed validation signal
(see Fig. 15). The framing code window width is fixed at 13 clock periods and the delay is determined
by the contents of the R5 register (R56 to R50).
At any moment the user is able to ensure that the framing code window is correctly located. This is
accomplished by the VAL OUT pin reflecting the intemal validation signal. A CBB signal with
programmable width (see section 'R7 register') can also be generated, this is used as a data slicer reset
pulse by the SAA5230. The line signal is used as the starting point of the internal CBB signal width
fixed by the contents of the R7 register.
If R16 = 0; then bits R15 and R14 provide the format table number using 0 IDON long and short
prefixes (see Table 6).
If R16 = 1; then the format is determined by the contents of the R3 register.
The bits R13 to R10 represent the first channel number to be checked in the prefix. In U. K. teletext
mode only 3 bits are required, so R13 = X.
November 1987
3-75
Philips Semiconductors Video Products
Preliminary specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
Table 5 Format table
format byte
B8, B6, B4 and B2
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1i 10
1111
list 1
list 2
list 3
list 4
0
1
2
3
4
8
12
16
20
24
28
32
36
40
0
1
2
3
0
1
2
3
6
10
14
18
22
26
30
0
1
2
3
7
5
9
13
17
21
25
29
33
37
41
45
49
44
48
34
38
42
46
50
11
15.
19
23
27
31
35
39
43
47
51
Note
B8 = MSB and B2 = LSB.
R2 register
Table 6 R2 Register contents
R27 to R24
R23to R20
channel number, third digit
channel number, second digit
(hexadecimal value, third digit)
(hexadecimal value, second digit)
Note
R27 and R23
=MSB and R24 and R20 = LSB
The R2 register provides the other two parts of the channel number (depending on the prefix) that
require checking.
November 1987
3-76
Preliminary specification
Philips Semiconductors Video Products
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
R3 register
Table 7 R3 register contents
R35 to R30
6-bit format maximum/default value
000000 =0
000001 = 1
111111
=63
This 6-bit byte gives:
• In the DIDON long and short mode, a maximum format in case of corrupted transmission (multiple
errors on the Hamming corrector)
• A possible 63-bit format for all types of prefix
R4 register
~
<
Q
Table 8 R4 register contents
R47 to R40
IZ
w
a-bit register used for storing the framing code value which will be compared with the
third byte of each data line
::E
A.
o...I
W
>
w
Q
R5 register
Table 9 R5 register contents
R57
negative/positive
R56 to R50
synchronization delay
o = negative edge for sync signal
7-bit sync delay, giving a maximum
delay of (2 7 - 1) x 10& ps/F (Hz)
1 = positive edge for sync signal
Note
F = data clock acquisition frequency (DCK).
Using R57 it is possible to start the internal synchronization delay (tOVAL) on the positive or negative
edge.
November 1987
3-77
Preliminary specification
PhilipS. Semiconductors Video Products
Interface for data acquisition and control:
(for multi-standard teletext systems)
SAA5250
R6 write command register
This is a fictitious register. Only the address code (see Table 2) is required to reset the CIOAC. Se.e
Table 11 for the status of the FI FO memory on receipt of this command.
Rl register
Table 10 R7 register contents
R75 to R70
6-bit register used to give a maximum colour burst blanking signal of:
(2 8 - 1) X 108 ps/F (Hz)
Note
F
=data clock acquisition frequency.
Fifo status register (read RO register)
Table 11 Fifo register contents
DB2 to DBO
DB2 = 1
memory empty
o B1 =1, data not present
in the read data register
DBO =0
memory not full
Once the relevant prefix and the right working modes have been given by the corresponding registers,
a write command to the R6 register enables the CIOAC to accept and process serial data.
Channel comparator
This is a four bit comparator which compares the three user hexadecimal defined values in R1 and R2
to the corresponding bytes of the prefix coming from the Hamming corrector. If the three bytes match,
the internal process of the prefix continues. If they do not match the CIDAC returns to a wait state
until the next broadcast data package is received.
FI FO memory controller
The FIFO memory contains all the necessary functions required for the control of the 11-bit address
memory (2 K byte). The functions contained in the FIFO memory are as follows:
•
•
•
•
•
•
•
•
write address register (11-bits)
read address register (11-bits)
memory pointer (11-bits)
address multiplexer (11-bits)
write data register (8-bits)
read data register (8-bits)
data multiplexer
control logic
The FIFO memory provides the memory interface with the following:
• .11-bit address bus (A10 to AO)
• 8-bit data bus (07 to DO)
• two control signals, memory select (MS) and write enable (WE)
November 1987
3-78
Preliminary specification
Philips Semiconductors Video Products
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
Operation
The CIDAC uses the same clock signal for data acquisition and internal processing, this allows the
CIDAC to have a write and a read cycle during each character period (see Fig. 13). The first half of the
character period is a write cycle and the second half is a read cycle. Consequently, fQr an 8 MHz bit
rate the maximum memory cycle time is 500 ns.
When the first data byte is written into the FI FO memory, thus transferred into the read register, the
FIFO memory enters the status shown in Table 12.
Table 12 FI Fa status
DB2 to DBO
DB2 = 1
memory empty
DB1 =0
data available
DBO=O
memory not full
When the FI Fa memory is full two events occur:
• the write address register points to the next address after the last written address
• when new data is to be written, the memory select signal output ceases
...~z
w
l
9
w
>
w
Q
Memory interface
The memory interface contains all the buffers for the memory signals mentioned in the seCtion
'FIFO memory controller'.
Page detection
This part of the CIDAC contains a parallel register with logic which detects (only in fast mode) a start
of a page or data group (see section 'RO register').
Hamming correction (see Tables 13 and 14)
The Hamming correction provides (see section 'Prefix processing'):
• hexadecimal value of the Hamming code
• accept/reject code signal
• parity information
November 1987
3-79
Philips Semiconductors Video Products
Preliminary specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
Table 13 Hamming correction (coding)
Hexadecimal
notation
0
1
2
3
4
5
6
7
8
9
A
B
C
B8
B7
B6
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
0
0
1
1
1
1
0
E
F
I
I
1
I
1
B5
64
B3
B2
1
0
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
10
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
1
1
1
1
0
'1
1
0
0
1
1
0
0
1
1
0
0
t
1
0
1
0
1
0
B1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
Note
B7
B5
B3
B1
= B8 e B6 e B4
= B6 e B4 e B2
= B4 e B2 e B8
= B2 e B8 e B6
= exclusive OR gate function
B8, B6, B4 and B2 = data bits
B7, B5, B3 and B1 = redundancy bits
6l
Table 14 Hamming correction (decoding)
A
B
C
1
1
1
1
0
0
1
1
1
0
1
1
1
0
0
1
0
0
0
1
A.B.C =0
1
0
0
0
1
0
1
0
interpretation
information
1
0
0
0
0
0
0
0
0
no error
error on
error on
error on
error on
error on
error on
error on
error on
accepted
corrected·
accepted
corrected
accepted
corrected
accepted
corrected
accepted
1
multiple errors
B8
B7
B6
B5
B4
83
82
B1
Note
A
B
= 88 e 86 e B2 e 81
= BB e B4 e B3 e B2
November 1987
C = B6 e B5 e B4 e B2
D=B8eB7eB6eB5eB4eB3eB2eBl
3-80
rejected
Philips Semiconductors Video Products
Preliminary specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
Format processing
The fonnat processing consists of two parts:
part 1
A format transcoder produces a 6·bit code (up to 63) and uses the following as inputs:
• DIDON long and short prefixes;
hamming corrected code (4·bits)
accept/reject code condition
table number (see section 'Rl register', bits R15 and R14)
• Other prefixes (R16 = 1)
• 6-bit maximum/default format (see section 'R3 register')
part 2
A format counter operating at the character clock frequency which receives the 6-bit code from the
format transcoder and is used to check the data packet length following the prefix.
Serial/parallel converter
The serial/parallel converte!" consists of three parts:
~
C
tZ
• An 8·bit shift register which receives the SO input and operates at the bit frequency (DCK).
• An 8-bit parallel register used for storage.
~
• A framing code detection circuit. This logic circuit compares the 8-bits of the R4 register with that
of the serial register. If seven bits out of eight match (in coincidence with a validation window), it
produces a start signal for a new teletext data line to the sequence controller.
9w
Clock generation
w
A.
>
w
C
The clock generator does the following:
• acts as a buffer for the DCK clock
• generates the character clock
As soon as a framing code has been detected, a divide by 8 counter is initialized and the character
clock is started. The clock drives the following:
• sequence controller
• parallel registers
• format counter
November 1987
3·81
Preliminary specification
Philips Semiconductors Video Products
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
Processing of VAL and eBB signals
The circuit has one input (VAL IN/SYNC) and two outputs (VAL OUT and CBB). The circuit consists
of:
• 7·bit counter operating at OCK frequency which produces the framing code validation pulse delay
• 7·bit comparator which compares the contents of the R5 register (bits R56 to R50) to the bit
counter
• a 6-bit counter operating at OCK frequency which produces the CBB pulse width
• 6-bit comparator which compares the contents of the R7 register (bits R75 to R70) to the bit
counter
• control logic required to provide the start condition for the VAL signal and the CBa pulse width
(on the negative or positive edge of the sync signal)
The caB signal usefulness occurs when the associated video processor:
• has no sandcastle pulse to send back to the demodulator
• carries out the synchronization of the time base clock. In this event the CBB acts as a data slicer reset
pulse
The VAL OUT is a control signal which reflects the internal_framing code window.
Prefix processing (see Table 21)
Figs 4 to 9 show the acquisition flow charts for each prefix type coded in the RO register (bits R02 to
ROO).
As soon as an initialization command is received by the CIOAC, a write command to the R6 register
(only the address is significant), is ready to receive data from a dedicated channel number and store
the data in the F I Fa memory (explained in the following paragraphs, each paragraph being dedicated
to an individual type of prefix).
olDON long (see Fig. 4)
In this mode, the continuity index, format and data bytes are written into the FI FO memory. (In fast
mode, information can be written into the FI FO memory only after a page detection.)
Table 15 Continuity index processing result
07
06
05
04
03
02
01
DO
NR
X
X
X
CI3
CI2
Cil
CIO
Table 16 Format processing result
07
06
05
04
03
02
01
DO
A/R
X
F5
F4
F3
F2
Fl
FO
Note
AIR = 0, if rejected
AIR = 1, if accepted
X =don't care
November 1987
3-82
Philips Semiconductors Video Products
Preliminary specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
OIDON mediun (see Fig. 5)
Only data bytes are written into the FIFO memory. (In fast mode, information can be written into the
FIFO memory only after a page detection.)
OIDON short (see Fig. 6)
In this mode, format and data bytes are written into the FIFO memory. (In fast mode, information can
be written into the FI FO memory only after a page detection.)
Table 17 Format processing result
07
06
05
04
03
02
01
DO
AIR
X
F5
F4
F3
F2
F1
FO
NABTS (see Fig. 7)
In this mode, the continuity index, packet structure and data bytes are written into the FI FO memory.
(In fast mode, information can be written into the FIFO memory only after a page detection.)
~
Q
tZ
w
::E
0-
9w
>
w
Table 18 Continuity index processing result
07
06
05
04
03
02
01
DO
AIR
X
X
X
Cl3
CI2
Cl1
CIO
Table 19 Packet structure processing result
07
06
05
04
03
02
01
DO
A/R
X
X
X
PS3
PS2
PS1
PSO
Q
U.K. teletext (see Fig. 8)
In this mode, the magazine and row address group (two bytes) and data bytes are written into the FIFO
memory. (In fast mode, information can be written into the FI FO memory only after a flag detection.)
Table 20 Magazine and row address group processing results
07
06
05
04
03
02
01
DO
A/R
X
X
RW4
RW3
RW2
RW1
RWO
Without prefix
All the data following the framing code are stored in the FI FO memory.
November 1987
3-83
Philips Semiconductors Video Products
Preliminary specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
Table 21 Prefix processing
prefixes
constructi on
of prefixes
bytes stored in FI FO
memory during slow mode
bytes stored in FIFO
memory during fast mode
OIOON
long
Al, A2, A3,
CI, F and '0
CI, F and 0
CI·, F· and O·
OIOON
medium
Al, A2 and 0
0
O·
OIOON
short
Al, F and 0
F and 0
F· and O·
Al, A2, A3
CI, PS and 0
CI, PS and 0
CI·, PS· and 0*
MRAG and 0
MRAG and D
MRAG* and 0*
NABTS
U.K.
teletext
without
prefix
all bytes of the data packet following the framing code are
written into the FIFO memory
Note
• =after page/flag detection
A 1, A2, A3 are channel numbers
CI = continuity index
F = format
PS = packet structure
0= data
MRAG = magazine and row address group
November 1987
3·84
Philips Semiconductors Video Products
Preliminary specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
FAST
~
<
C
tZ
w
2E
A-
S
W
>
W
C
FAST
~'
PROGRESS
1
o
Fig. 4 OIDON (long) acquisition flow chart.
November 1987
3-85
Philips Semiconductors Video Products
Preliminary specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
INITIALIZE CIDAC
SET PAGE IN PROGRESS FLAG
lZ96681
Fig. 5 DIDON (medium) acquisition flow chart.
November 1987
3-86
Preliminary specification
Philips Semiconductors Video Products
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
INITIALIZE CIDAC
FAST
<
~
c
~
z
w
:IE
~
9w
>
w
C
Fig.6 DIDON (short) acquisition flow chart.
November 1987
3-87
Preliminary specification
Philips Semiconductors Video Products
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
SAVE CI BYTES
SET DATA GROUP IN
PROGRESS FLAG
Fig. 7 NABTS acquisition flow chart.
November 1987
3-88
Philips Semiconductors Video Products
Preliminary specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
~------------------~SLOW
i
tZ
w
:E
a..
9
w
>
w
Q
WRITE ROW NUMBER INTO FIFO
LOAD FORMAT COUNTER
WITH IMPLICIT FORMAT
Fig. 8 U.K. teletext acquisition flow chart.
November 1987
3-89
Philips Semiconductors Video Products
Preliminary specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5~50
Fig. 9 Without prefix acquisition chart.
clock input to
5
OCK O-;~-I------.4--I ~>O---' data lICquisition
circuit
o
so O-;I-~------....a
data input to
~__.... dlltlllCqui.ition
circuit
D - clamping diodes
CSI • clamping pulse, the pul~ width
is given by the R 7 register
Fig. 10 SO and DCK input circuitry.
November 1987
3-90
UI66"
Preliminary specification
Philips Semiconductors Video Products
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
RATINGS
Limiting values in accordance with the .Absolute Maximum System (lEC 134)
parameter
conditions
Supply voltage range
symbol
min.
max.
unit
VOO
6,5
V
VOO+O,3
V
Input voltage range
VI
-0,3
-0,3
Total power
dissipation
Ptot
-
400
mW
Operating ambient
temperature range
Tamb
0
70
°C
Storage temperature
range
T stg
-20
+125
°C
O.C. CHARACTERISTICS (except SO and OCK)
VOO
<
~
Q
tZ
w
:E
= 5 V ±10%; VSS =0 V; Tamb =0 to 70 oC, unless otherwise specified
parameter
conditions
symbol
min.
typo
max.
unit
Supply voltage range
VOO
5,5
V
VIH
4,5
2
5,0
Input voltage HIGH
Input voltage LOW
VIL
-
p.A
-
-
V
-
-
0,4
V
VOL
P
-
-
0,4
V
5
-
mW
C,
-
-
7,5
pF
Voo-O,4
VOL
Power dissipation
Input capacitance
Output voltage HIGH
'load
Output voltage LOW
'load =4 mA,
at pins 9 to 16
and 22 to 29
Q
V
V
II
Input leakage current
-'
w
>
w
VOO
VOH
CL.
o
= 1 mA
'load = 1 rnA
all other
outputs
November 1987
-
0,8
1,0
-
3-91
-
Preliminary specification
Philips Semiconductors Video Products
Interface for data acquisition and control
(for multi~standard teletext systems)
SAA5250
SO and DCK D.C. CHARACTERISTICS (see Fig. 10)
VOO = 5 V; VSS =0 V; Tamb =0 to 70 oC, unless otherwise specified
parameter
conditions
OCK
Input voltage range
(peak-to-peak value)
Input current
Input capacitance
External coupling
capacitor
VI =Oto VOO
SO
D.C. input voltage
range HIGH
D.C. input voltage
range LOW
A.C. input voltage
(peak-to-peak value)
Input leakage current
Input capacitance
External coupling
capacitor
November 1987
min.
typo
max.
unit
Vl(p_p)
2,0
5
-
-
II
CI
200
V
p.A
-
-
30
pF
Cext
10
-
-
nF
note 1
VIH
2,0
-
-
V
note 2
. VIL
-
-
0,8
V
30
V
p.A
pF
-
nF
VI =OtoVOO
symbol
Vl(p_p).
II
CI
2,0
-
-
-
-
·,0
Cext
10
3-92
-
-
Preliminary specification
Philips Semiconductors Video Products
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
A.C. CHARACTERISTICS
Voo = 5,V ±10%; Reference levels for all inputs and outputs, VIH =2 V; VIL =0,8 V; VOH
VOL =0,4 V; CL =50 pF on oB7 to oBO; Tamb =0 to 70 °C, unless otherwise specified
parameter
conditions
Microcontroller
interface
Figs 11 and 12
Cycle time
Address pulse width
=2,4 V;
symbol
min.
typo
max.
unit
tcy
400
tLHLL
-
-
ns
50
-
-
ns
-
ns
-
ns
ns
Ro HIGH or WR to
ALE HIGH
Fig. 11
tAHRo
0
OS LOW to AS HIGH
Fig. 12
tAHRo
0
ALE LOW to Ro
LOWorWR LOW
Fig. 11
tALRo
30
AS LOW to OS HIGH
Fig. 12
tALRo
30
Write pulse width
t\NL
120
-
Address and chip
select set-up time
tASL
10
-
-
ns
...z
Address and chip
select hold time
tAHL
20
-
-
ns.
D.
::E
Read to data out
period
tRo
-
-
130
ns
W
Data hold after RD
tOR
10
-
100
ns
Q
Rm to OS set-up
time
Fig. 12
tRWS
40
-
Fig. 12
tRWH
10
Data set-up time
write cycle
tow
50
ns
Data hold time
write cycle
two
10
-
ns
tRL
150 or
OCK +50
-
-
ns
R/W to OS hold time
-
ns
~
ct:
o
w
o.J
>
w
Read pulse width
November 1987
note 3
3-93
ns
ns
ns
PhiliPlil Semiconductors Video Products
Preliminary specification
Interface for data acquisition and control
(for multi-standard teletext systems)
parameter
conditions
Memory interface
Fig. 13
SAA525Q
symbol
min.
typo
max.
unit
WE LOW to DCK
, falling edge
twEL
10
-
80
ns
WE HIGH to DCK
falling edge
twEH
10
-
80
ns
MS lOW to DCK
rising edge
tMSL
10
-
80
ns
MS HIGH to DCK
rising edge
tMSH
10
-
85
ns
Address output from
DCK rising edge
tAV
10
-
120
ns
Data output from
WE falling edge
tDWl
0
-
10
ns
Data hold from
WE rising edge
tOWH
0
-
-
ns
tAD
-
-
3x DCK
-110
ns
-
ns
-
ns
Address set-up time
to data
note 4
WE pulse width
note 5
twEW
3x DCK
-
MS pulse width
note 6
tMSW
2x DCK
-
,
Demodulator interface
(see SO and DCK D.C.
CHARACTERISTICS) Fig. 14
OCK lOW
conversion
rate < 7,5 MHz
tDCKl
55
-
-
ns
DCK HIGH
conversion
rate < 7,5 MHz
tDCKH
55
-
-
ns
Serial data set-up time
tSSD
0
tHSO
30
-
-
ns
Serial data hold time
Validation signal
set-up time
tSVALI
50
-
-
ns
Validation signal
hold time
tHVALI
50
-
-
ns
Other I/O Signals
Fig. 15
User definable width
as a mUltiple of DCK
period
Validation signal width
User definable delay
as a multiple of DCK
period
November 1987
ns
note 7
twC8B
0
-
63
DCK
tWVAL
X
12
X
DCK
tDVAl
0
-
127
DCK
3-94
Preliminary specification
Philips Semiconductors Video Products
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
Notes to the characteristics
,. Unless R7
=00 the value given is unacceptable.
2. When CBI signal is maintained at 0 V (R7 = 00) and if SD input signal is correctly referenced to
ground, no coupling capacitor is required.
3. DCK
+ 50 is the
DCK period plus 50 ns.
4.3 x DCK - 110 is 3 x DCK periocl- 110 ns.
5. 3 x DCK is 3 x DCK period.
6. 2 x DCK is 2 x DCK period.
7. X
= irrelevant.
~
«
c
....z
w
:t
a.
9w
>
w
C
November 1987
3·95
Philips Semiconductors Video Products
Preliminary specification
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
READ CYCLE
~------------~------tCY--------~----------.1
ALE
tRl_
BUS
WRITE CYCLE
I~-------------------
tCY-------------------.1
ALE
BUS
Fig. 11 Timing diagram for microcontroller interface (Intel).
November 1987
3-96
Preliminary specification
Philips Semiconductors Video Products
Interface for data acquisition and control
(for multi-standard teletext systems)
SAA5250
14---------------------------- Cy--------------------------__.
t
-
tAHRO
tALRO-
OS
(pin
ADI
(1)
AS
(pin ALEI
--tRWS-
-tRWH
R/w
(pinWRI
-tAHL
write cycle
-tow
BUS
o IN
r
tAHL
(11
tRO
"
reed cycl,
(11 ALE,
CS, RD, WR
end DB7 to DBO
Fig. 12 Timing diagram for microcontroller interface (Motorola).
November 1987
3-97
--
z
~
-::J
0
_
3
"CD
C"
!!!
....
<0
"'\J
~
~.
(J)
CD
3~
g3 .
=CD
ac
c_ 0
s»
1- !
00
.......
!e.o
s» .,
charactar
pet'iod
r---__ J
--,L _ _ _ _ _ _ _ _
r--------,L_
~
::Jo. :s;
o.s»
s»., s» ~
o.s» &
c
Co
"'\J
-0
CD.o
CD c
~
CD ~:
x=
en ::J
OCK
-0
dis»
-::J
CD 0.
3
eo°::J
.,
WE
o
cp
<0
00
MS
A10toAO
tOWH-'
-tOWL
07toOO
_tAo~1
OATAOUT
OATAIN
DATA OUT
lZ96682
"'\J
~
CJ)
Fig. 13 Timing diagram for memory interface.
-:t;>
:t;>
01
I\)
01
o
3·
:i"
III
-
W
C
VAL INI
SYNC
so
CLOCK SYNCHRONIZATION
BITS
FRAMING
CODE
14--------r--tDVAL----------~~.
VAL
OUT
CBB
7Z96671
Fig. 15 Timing diagram for all other 1/0 signals.
November 1987
3-99
Product specification
Philips Semiconductors
Line twenty-one acquisition and display
(LITO D)
SAA5252
FEATURES
• Complete 'stand-alone' Line 21 decoder in one package
• On-chip display RAM allowing full page Text mode
• Enhanced character display modes
• Full colour captions
• RGB interface for standard colour decoder ICs
GENERAL DESCRIPTION
• Automatic handling of Field 2 data
• Automatic selection of (1H, 1V), (2H, 1V) or (2H, 2V)
scan modes
• On board OSD facility using Character generator
• RGB inputs to support existing OSD ICs
• 12C-bus or 'stand-alone' pin control
The SAA5252 (LITOD) is a single-chip CMOS device,
which will acquire, decode and display Line 21 Closed
Captioning data from a 525-line composite video signal.
Operation as an On-Screen Display (OSD) device is also
possible. Normal and line progressive scan modes are
supported.
• Automatic data-ready signal generation on data
acquisition
• Can decode signals recorded on standard VHS and
S-VHS tape.
QUICK REFERENCE DATA
PARAMETER
SYMBOL
MAX.
TYP.
MIN.
UNIT
Voo
supply voltage
4.5
5.0
5.5
V
100
supply current
-
30
-
rnA
Vsyn
CVBS sync amplitude
0.1
0.3
0.6
V
Vvid
CVBS video amplitude
0.7
1.0
1.4
V
Tamb
T stg
operating ambient temperature
-20
-
+70
°C
storage temperature
-55
-
+125
°C
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
April 1994
PINS
PIN POSITION
MATERIAL
CODE
SAA5252P
24
DIL
plastic
SOT101
SAA5252T
24
S024L
plastic
SOT137-1
3-100
Philips Semiconductors
Product specification
Line twenty-one acquisition and display
SAA5252
(LiTOD)
BLOCK DIAGRAM
VSS
VDD
V
H
i.c.
6
17
16
OSCIN
15
CHARACTER
GENERATOR
ROUNDING
ITALICS
AND
RGB
MULTIPLEXOR
OSCGND
OSCOUT
14
13
9
RGBREF
BLAN
R
G
B
BlANIN
10
11
SAA5252
12
5
3
BLACK
4
IREF
RIN
GIN
BIN
DR
SDA
SCl
CVBS
MB8623-1
2
1 C/Dc
Fig_1 Block diagram.
April 1994
3-101
Product specification
Philips Semiconductors
Line twenty-one acquisition and display
(LiTOD)
SAA5252
PINNING
SYMBOL
CVBS
PIN
DESCRIPTION
1
composite video input; signal should be connected via a
100 nF capacitor
12C/DC
2
input selects 12C or Direct Control
SDA
3
serial data port for 12C-bus or mode select input for
direct control
SCL
4
serial clock input for 12C-bus or mode select input for
direct control
DR
5
data-ready signal to microcontroller (active-LOW) or
mode select input for direct control
IREF
BLACK
OSCGNO
i.c.
6
internally connected; connect to Vss for normal
operation
V
7
vertical reference input for display timing
H
8
horizontal reference input for display timing
BLANIN
9
video blanking input from external OSD device
RIN
10
RED video input from external OSD device
RGBREF
GIN
11
GRE.EN video ihput from external OSD device
BLAN
BIN
12
BLUE video input from external OSD device
RIN
B
13
BLUE video output
GIN
G
14
GREEN video output
BIN
R
15
RED video output
BLAN
16
video blanking output
RGBREF
17
input voltage defining output HIGH level for RGB pins
for closed captioning output
Voo
18
+5 V supply
Vss
OSCOUT
19
OV ground
20
oscillator output
OSCIN
21
oscillator input
OSCGND
22
oscillator ground
BLACK
23
video black level storage input; connected to Vss via
100 nF capacitor
IREF
24
reference current input; connected to Vss via 27 kQ
resistor
OSCIN
OSCOUT
Vss
VOO
MB8822·'
April 1994
3-102
Fig.2 Pin configuration.
Philips Semiconductors
Product specification
Line twenty-one acquisition and display
(LiTOD)
SAA5252
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
V lmax
PARAMETER
CONDITIONS
supply voltage (all supplies)
MIN.
MAX.
UNIT
-0.3
+6.5
maximum input voltage (any input)
note 1
-0.3
VOmax
maximum output voltage (any output)
note 1
-
VDD + 0.5 V
VDD + 0.5 V
Vdif
difference between Vss and OSCGND
-
±0.25
IIOK
DC input or output diode current
-
±20
mA
lomax
maximum output current (each output)
-
±10
mA
Tamb
T stg
operating ambient temperature
-20
+70
°C
storage temperature
-55
+125
°C
Yes
electrostatic handling
V
V
human body model
note 2
-2000
+2000
V
machine model
note 3
-200
+200
V
Notes
1. This maximum value has an absolute maximum of 6.5 V independent of VDD.
2. The human body model ESD simulation is equivalent to discharging a 100 pF capacitor via a 1.5 kQ resistor, which
produces a single discharge transient. Reference "Philips Semiconductors Test Method UZW-80/FQ-A302 (similar
to MIL-STD 883C method 3015.7)".
3. The machine model ESD simulation is equivalent to discharging a 200 pF capacitor via a resistor and series inductor
with effective dynamic values of 25 Q and 2.5ItH, which produces a damped oscillating discharge. Reference
"Philips Semiconductors Test Method UZW-80/FQ-8302 (similar to EIAJ IC-121 Test Method 20 condition C)".
Quality
This device will meet the requirements of the "Philips Semiconductors General Quality Specification UZW-80/FQ-0601"
in accordance with "Quality Reference Pocketbook (order number. 9398 51034011)". This {fetails the acceptance
criteria for all Q & R tests applied to the product.
April 1994
3-103
Product specification
Philips Semiconductors
Line twen.ty-one acquisition and display
(UTOD) ,
SAA5252
CHARACTERISTICS
VDD
= 5 to 5.5 V; Vss =0 V; Tamb = -20 to +70 °C; unless otherwise specified.
SYMBOL
CONDITIONS
PARAMETER
MIN.
MAX.
TYP.
UNIT
Supplies
V DD
supply voltage
4.5
5.0
5.5
V
IDDtot
total supply current
-
30
-
rnA
Inputs
CVBS (PIN
1)
V syn
sync vOltage amplitude
0.1
0.3
0.6
V
Vvid(p-p)
video voltage amplitude
(peak-to-peak value)
0.7
1.0
1.4
V
Vdat
caption data voltage
amplitude
0.25
0.35
0.49
V
Zsource
source impedance
-
-
250
Q
VI
input switching voltage level
of sync separator
1.7
2.0
2.3
V
ZI.
input impedance
2.5
5
-
kQ
input capacitance
-
-
10
pF
R24
resistor to ground
-
27
V 24
voltage on pin 24
-
%VDD
-
V
CI
IREF (PIN
24)
kQ
H (PIN 8)
Vil
LOW level input voltage
-0.3
-
+0.8
V
VIH
HIGH level input voltage
2.0
V
III
input leakage current
Ilmax
CI
maximum input current
-1
-
VD D + 0.5
input capacitance
tr
pulse rise time
-
tf
pulse fall time
-
-
tw
pulse width
VI
=Oto VD D
-10
+10
J.tA
+1
rnA
-
10
pF
-
5
J.ts
5
J.ts
scan mode 1H
1
12
63
J.ts
scan mode2H
1
6
31
J.ts
v (PIN 7)
Vil
LOW level input voltage
-0.3
-
+0.8
V
VIH
HIGH level input voltage
2.0
-
V DD + 0.5
V
III
input leakage current
-10
-
+10
J.tA
Ilmax
CI
maximum input current
-1
+1
rnA
input capacitance
10
pF
tr
pulse rise time
-
-
5
ns
tf
pulse fall time
-
5
ns
tw
pulse width
1
-
-
J.ts
April 1994
VI
=OtOVDD
3-104
Product specification
Philips Sem iconductors
Line twenty-one acquisition and display
(UTOD)
PARAMETER
SYMBOL
SAA5252
MIN.
CONDITIONS
MAX.
TYP.
UNIT
RGBREF (PIN, 17)
VI
input voltage
III
input leakage current
VI
=0
to Voo
-0.3
-
Voo
V
-10
-
+10
itA
R, G ANO B (PINS 15,14 AND 13; NOTE 1)
V il
LOW level input voltage
-0.3
-
0.8
V
VIH
HIGH level input voltage
2.0
-
Voo + 0.5
V
ZI
input impedance
2.5
5.0
-
kQ
-
0.8
V
Voo + 0.5
V
-
+10
80
~
ns
-
80
ns
0.8
V
Voo
V
-10
-
+10
itA
BLANIN (PIN 9)
V il
LOW level input voltage
-0.3
VIH
HIGH level input voltage
2.0
III
input leakage current
VI
tr
input rise time
between 10% and 90%
tf
input fall time
between 90% and 10%
=0 to Voo
-10
-
12 C/DC (PIN 2)
V il
LOW level input voltage
0
V IH
HIGH level input voltage
2.0
III
input leakage current
VI
=OtoVoo
SCl (PIN 4)
Vil
LOW level input voltage
-0.3
-
1.5
V
VIH
HIGH level input voltage
3.0
Voo + 0.5
V
fclk
clock frequency
0
100
kHz
tr
input rise time
between 10% and 90%
-
2
tf
input fall time
between 90% and 10%
-
2
III
input leakage current
VI
+10
CI
input capacitance
-
its
its
itA
10
pF
=0
-10
to Voo
-
Inputs/outputs
CERAMIC RESONATOR (PINS 20, 21 AND 22; SEE FIG.5)
fosc
oscillator frequency
11.82
12
12.18
MHz
CO
parallel capacitance
5.35
series capacitance
37.4
-
pF
Cl
-
L1
series inductance
35.5
-
Rl
series resistance
6
25
ItH
Q
-
pF
BLACK (PIN 23)
Cblack
storage capacitor to ground
-
100
-
nF
Vblack
black level voltage for
nominal sync amplitude
1.8
2.15
2.5
V
III
input leakage current
-10
-
+10
itA
April 1994
VI
=Oto VDO
3-105
Philips Semiconductors
Product specification
Line twenty-one acquisition and display
SAA5252
(UTOD)
SYMBOL
SDA (PIN
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
3; OPEN DRAIN)
VIL
LOW level input voltage
-0.3
VIH
HIGH level input voltage
3.0.
III
input leakage current
CI
input capacitance
tr
-
+1.5
V
VDD + 0.5
V
-
+10
I-lA
10
pF
2
!As
2
I-ls
0.5
V
-
-
200
ns
-
-
400
pF
VI = Oto VDD
-10
input rise time
between 10% and 90%
tl
input fall time
between 90% and 10%
-
VOL
LOW level output voltage
IOL = 3 mA
0
tl
output fall time
between 3 V and 1 V
CL
load capacitance
DR (PIN
TYP.
5; OPEN DRAIN)
V IL
LOW level input voltage
-0.3
-
+1.5
V
VIH
HIGH level input voltage
3.0
-
VDD + 0.5
V
III
input leakage current
VI = Oto VDD
-10
I-lA
LOW level output voltage
IOL = 1.6 mA
0
-
+10
VOL
0.4
V
tl
output fall time
between 4 V and 1 V
with 3.3 kQ to 5 V
-
-
50
ns
CL
load capacitance
-
-
100
pF
Outputs
R, G AND B (PINS
15,14 AND 13; CAPTION MODE)
-
0.2
V
V 17
V 17 + 0.4
V
-
-
200
Q
-
-
50
pF
10
ns
10
ns
-
0.4
V
2.8
V
50
pF
10
ns
10
ns
10
ns
VOL
LOW level output voltage
IOL = +2 mA
VOH
HIGH level output voltage
IOH
Zo
output impedance
CL
load capacitance
tr
output rise time
between 10% and 90%
tl
output fall time
between 90% and 10%
0
BLAN (PIN
0
=-2 mA
V 17
0.3
16)
VOL
LOW level output voltage
IOL=+2mA
VOH
HIGH level output voltage
IOH
CL
load capacitance
tr
output rise time
between 10% and 90%
tl
output fall time
between 90% and 10%
tskew
skew delay time between
display and R, G, B, BLAN
April 1994
-
=-2 mA
1.1
3-106
-
Philips Semiconductors
Product specification
Line twenty-one acquisition and display
(UTOD)
SYMBOL
PARAMETER
SAA5252
CONDITIONS
TYP.
MIN.
MAX.
UNIT
12C timing (see Fig.3)
tLOw
clock LOW time
4
-
tHIGH
clock HIGH time
4
tSU;DAT
data set-up time
250
tHD;DAT
data hold time
170
tSU;STO
set-up time from clock
HIGH-to-STOP
4
-
tBUF
START set-up time
following a STOP
4
tHD;STA
START hold time
tSU;STA
START set-up time
following clock
LOW-to-HIGH transition
tr
output rise time
between 10% and 90%
tf
output fall time
between 90% and 10%
-
~s
-
ns
-
ns
-
-
~s
4
-
-
~s
4
-
-
~s
-
-
10
ns
10
ns
~s
~s
Note
1. These inputs are analog, V IL and VIH values are quoted as a guide for digital RGB users.
SDA
SCL
SDA
tSU;STO
Fig.3 12C-bus timing diagram.
April 1994
3-107
Product specification
Philips Semiconductors
Line twenty-one acquisition and display
SAA5252
(LiTOD)
APPLICATION INFORMATION
100 nF
CVBS~
C5
CVBS
24
2
1 C/Dc
2
23
SOA
+5V
3.3
kn
12C-bus
to
microcontroller
SCl
OR
to
microcontroller
22
4
21
5
20
GIN
BIN
OSCIN
OSCOUT
12MHz
18
8
17
16
10
15
11
14
12
13
VOO
RGBREF
BlAN
R
G
B
(1) Value dependent on application.
Fig.4 Application diagram.
Fig.5 Ceramic resonator equivalent circuit.
April 1994
I-~
OSCGNO
+5V
7
BlANIN
RIN
100 nF
19
SAA5252
H
BLACK C4
27 kn
VSS
i.c.
V
IREF
3-108
MBB624 ·2
Product specification
Philips Semiconductors
Line twenty-one acquisition and display
(LiTOD)
SAA5252
DISPLAY GENERATOR
Display of external On-Screen Display (OSD) facilities
General Description
The R, G, Band BLAN outputs of the display have the
capability to be put in a 3-state mode allowing other OSD
devices to take control of the television R, G, Band BLAN
signals.
The displayed characters are defined on a 5-by-12 matrix
within a 7-by-13 window, allowing one blank pixel either
side of the character and a blank pixel row above. There
are a number of display options available controlled by
Register 1, or external pins in 'stand-alone' mode.
When the BLANIN is held HIGH then the R, G, Band
BLAN outputs from display are disabled and the R, G, B
and BLAN signals come directly from the RGBIN and
BLANIN inputs. This will allow On-Screen Display to be
placed on top of the captioning without any corruption,
leaving the captions intact when the On-Screen Display is
switched off (BLANIN goes LOW). In this form of operation
the RGBIN and RGBOUT pins can be considered
transparent; BLANIN goes through the normal output
buffer to BLAN.
The three display modes are video, text and caption, the
device is powered up in the video mode.
The display generator reads the Pre-amble Address Code
(PAC) then the data associated with that row. Each
character is then rounded after which it can be italicized
and/or underlined, depending on the PAC or mid-row
codes, before being passed on to the output circuitry.
Figure 6 shows the character set.
Table 1 Register map (WRITE).
07
REGISTER
05
06
03
04
V
02
01
DO
H3
H2
H1
HO
EN1
ENO
M1
MO
00
DF1/2
RGB,BLAN H
+ve/-ve
+ve/-ve
01
CLEAR
CH 211
02
-
-
-
-
ROW3
ROW2
ROW1
ROWO
03
-
-
.-
COL4
COL3
COL2
COL1
COLO
04
-
OSD6
OSD5
OSD4
OSD3
OSD2
OSD1
OSDO
+ve/-ve
NARROW ACQOFF
/WIDE
Table 2 Register map (READ).
REGISTER
07
06
05
04
03
02
01
00
00
POR
0
0
0
F1/F2
EDS
PARITY
SHUTDOWN
DATA
READY
01
PARITY
ERROR
DATA
BIT7
DATA
BIT6
DATA
BIT5
DATA
BIT4
DATA
BIT3
DATA
BIT 2
DATA
BIT 1
02
PARITY
ERROR
DATA
BIT7
DATA
BIT6
DATA
BIT5
DATA
BIT4
DATA
BIT3
DATA
BIT2
DATA
BIT 1
April 1994
3-109
Philips Semiconductors
Product specification
Line twenty-one acquisition and display
SAA5252
(LiTOD)
a
b6 -
0
0
bS-
0
b4b 3 b 2 b 1 bO
1~lum~
•o • •o
•
0
0
white
o
0
0
1
1
white
underline
o
0
1
0
2
green
o
0
1
1
3
green
underline
o
1
o
0
4
blue
o
1
o
1
5
blue
underline
o
1
1
0
6
cyan
o
1
1
1
7
cyan
underline
1
0
0
0
8
red
1
0
0
1
9
red
underline
1
0
1
0
A
yellow
1
0
1
1
B
yellow
underline
1
1
0
0
C
magenta
1
1
o
1
D
magenta
underline
1
1
1
0
E
italics
1
1
1
1
F
italics
underline
0
0
0
w
0
1
0
1
1
~
[J
~
~
~
~
~
~
~
1
1
1
0
2
1
0
3
1
0
1
0
4
1
1
5
1
1
0
6
7
~
Bg B D
rn ~ Bg ~ '9
U~ ~ ~ § 0
D
~.
~
signifies "flash on'; command
signifies a tr1insparent space
~ ~ g§ § §
~ ~ g m§ ~
~ § § g~ g
~ § 6 ~ ~. g
[J ~ ~ 8 § ~
~ § BB ~ B
D~ § rn ~ ~ g
~ ~ ~ ~ ~ [j] ~
~ ~ ~ ~ ~ ~ ~
~ ~ ~ Q~ ~ ~
~ DD~ g ~ B
§ D~ ~ ~ 0 0
g~ 0g§ § I
MBB625-2
The '0' and 'zero' use the same character, 4Fh.
Fig.6 Character set.
April 1994
3-110
Product specification
Philips Semiconductors
Line twenty-one acquisition and display
(LiTOD)
SAA5252
12C INTERFACE
Description of WRITE registers
The write subaddresses auto increment from 0 through to 4 at which point they stay until a new write subaddress is sent.
Registers are set to all logic 0 at power-up.
Table 3 Register 0 WRITE (Control Byte 1).
BIT
DESCRIPTION
DO to 03
HO to H3 set the offset position from the start of the horizontal sync pulse, set to a nominal value on reset.
04
Vertical sync pulse expected to be negative going logic 0 or positive-going logic 1.
05
Horizontal sync pulse expected to be negative going logic 0 or positive-going logic 1.
06
Video outputs will be positive going logic 0 or negative-going logic 1.
07
Data field select. When set to logic 0 Field 1 is decoded, when set to logic 1 Field 2 is decoded.
Table 4 Register 1 WRITE (Control Byte 2).
DESCRIPTION
BIT
00,01
Display mode selection bits. Table 8 shows the possible display modes.
02,03
Enhanced caption mode selection bits. Table 9 shows the possible enhanced caption modes.
04
When set to logic 1 acquisition of caption data is inhibited to allow the display to be used for
On-Screen Display purposes.
05
Acquisition window selection. When set to logic 0 only Line 21 is checked for caption data. When set to
logic 1, lines 19 to 23 of both fields are checked, allowing encrypted video signals to be handled.
06
User channel selection.
07
Clears the page memory when set HIGH. The page memory will be within two fields (30 ms).
Table 5 Register 2 WRITE (On-Screen Display data row address).
DESCRIPTION
BIT
DO to 03
Row 0 to 3 sets the row address for On-Screen Display. This stored value will be incremented by overflow
increments of Register 3.
Table 6 Register 3 WRITE (On-Screen Display data column address).
DESCRIPTION
BIT
DO to 04
Columns 0 to 4 sets the column address for On-Screen Display. This stored value will be incremented by
writes to Register 4.
Table 7 Register 4 WRITE (On-Screen Display data).
BIT
DO to 06
April 1994
DESCRIPTION
OSDO to OSD6, On-Screen Display data bits writing to this register causes Register 3 to increment its
stored value.
3-111
Product specification
Philips Semiconductors
Line twenty-one acquisition and display
(LiTOD)
SAA5252
Table 8 Display modes.
DISPLAY MODE OPTIONS
Video only
M1
0
,
' , MO
0
Text mode
0
1
Normal caption mode
1
0
Enhanced caption mode
1
1
EN1
ENO
EN1
ENO
Shadowed characterNideo background
0
0
Shadowed character/Mesh background
0
1
Normal characterNideo background
1
0
Normal character/Mesh background
1_
1
Table 9 Enhanced caption modes.
ENHANCED CAPTION MODES
Enhanced caption modes
,
Description of READ registers
The read subaddresses auto increment from 0 through to 2 at which point they stay until anew read subaddress is sent.
All the bits in Table 10 are reset to logic 0 after the register is read.
Table 10 Register 0 READ (status).
BIT
DESCRIPTION
DO
Data ready (new data has been acquired).
D1
Parity error shut-down, goes HIGH when SAA5252 has a parity shut-down condition.
D2
Indicates the following bytes are extended data service bytes.
D3
Indicates Field 1 or Field 2 data bytes.
D7
Indicates Power-On Reset (PaR) has occurred, all1 2 C-bus write registers have been reset to 10gicO.
Table 11
R~gister
1 READ (first data byte).
BIT
DESCRIPTION
DO to D6
Data Bit 1 to Data Bit 7 (see note 1).
07
Parity error flag bit. Bit goes HIGH when a parity error has occurred.
Note
1.
In the Line 21, specification data bits are numbered 01 to 08.
Table 12 Register 2 READ (second data byte).
BIT
DESCRIPTION
DO to D6
Data Bit 1 to Data Bit 7 (see note 1).
D7
Parity error flag bit. Bit goes HIGH when a parity error has occurred.
Note
1.
In the Line 21, specification data bits are numbered 01 to 08.
April 1994
3-112
Philips Semiconductors
Product specit'ication
Line twenty-one acquisition and display
(tiTOD)
SAA5252
Interface to microcontroller using 12C-bus
'STAND-ALONE' (NON 12C-BUS) OPERATION
The interface to the microcontroller is via the two-wire
serial 12C-bus, and optionally by a Data-Ready signal
(DR). On power up the microcontroller initializes the
device by anl2C-bus WRITE to Registers 0
(Control Byte 1). The 12C-bus subaddress is then auto
incremented to point to Register 1 (Control Byte 2). These
two registers configure the device to the users
requirements.
To set the SAA5252 for 'stand-alone' operation pin 2
(l2C/DC) is tied lOW. This will change the operation of the
SCl, SDA and DR pins to mode select inputs which will
select as shown in Table 13.
If the device is to be used for data acquisition only, then
there are three methods by which the microcontroller can
be informed of the arrival of valid Line 21 data:
• It can poll the DR pin, if the function has been enabled,
and wait for it to go lOW.
In the caption mode the SAA5252 operates in the basic
Normal character/Black background mode. This complies
with the FCC ruling. In the.Enhanced caption mode the
set-up will be Shadowed characterNideo background.
SDA and SCl in the 'stand-alone' operation act as bits MO
and M1 in Table 8.
Table 13 Stand-alone modes.
DR
• It can use the negative edge of the DR signal to cause
an interrupt.
• It can poll the Data Ready bit (bit DO of the status byte,
12C-bus READ Register 0).
When valid data is detected, the microcontroller must
initiate an 12C-bus READ of Registers 0, 1 and 2. The first
and second data bytes from the most recently received
Line 21 are in Register 1 and Register 2 respectively.
The DR pin, and the Data Ready bit (Status bit DO) will be
cleared after any register has been read. paR is reset
after Register 0 has been read.
April 1994
3-113
SCL SDA
MODE OF
OPERATION
CHANNEL
RECEPTION
0
0
0
Video mode
Channel 1
0
0
1
Text mode
Channel 1
0
1
0
Normal captions
Channel 1
0
1
1
Enhanced captions Channel 1
1
0
0
Video mode
1
0
1
Text mode
Channel 2
1
1
0
Normal captions
Channel 2
1
1
1
Enhanced captions Channel 2
Channel 2
Philips Semiconductors Video Products
Objective specification
Single chip economy 10 page teletext!
TV microcontroller
GENERAL DESCRIPTION
The SAA5296 is a ten page teletext decoder
and TV controllC. The device will decode
625 line and 525 line based WST
transmissions and provides tuner control
functions and On Screen display (OS D)
facilities. The teletext decoder hardware is a
derivative of IVT1.1 X and the TV control
functionality is provided by an on-chip
industry standard 80C51 microcontroller. A
ten page static RAM is included on board
providing a single chip teletext decoder and
OSD display memory. The SAA5296 is
intended for use as the central control
mechanism in a television receiver.
SAA5296
• Single crystal oscillator for teletext decoder,
display and microcontroller
• Packet 26 engine for real time processing
of accented (and other) characters
Text
• Pa~e links in packet 27, and packet 8/30
are Hamming decoded
• Ten page (10240 x 8) on board teletext and
OSDmemory
• 260 characters in mask programmed ROM
• Eastern European, Western European and
Turkish language covered in one device
• optional storage of packet 24 in display
memory
• 625 line and'525 line acquisition and
display
• Video signal quality detection
• Automatic FRAME output control.with
manual override
• Acquisition and decoding of VPS data
(EBU PDC System A)
The SAA5296 will be available as a mask
programmed ROM version. An EEPROM
version will also be available for software
dev~lopment. Both versions are available in a
SDIL-52 package and QFP-80 package. The
QFP-80 package also has the capability of
external ROM.
• Slave synchronization
• Simultaneous acquisition and storage of 10
teletext pages
• Standby mode for teletext hardware
• Double size, width and height character
capability for OSD
Microcontroller
• Enhanced display features including
meshing, shadowing and additional display
attributes
• BOC51 instruction set
FEATURES
• Definable OSD border colours in TV mode
• 768 bytes of RAM
General
• Extension packet and Inventory page
storage
• Eight 6-bit PWMs. One 14-bit PWM for
tuning control
• Complete Teletext decoder and TV control
in a single integrated circuit
• Automatic detection of Fastext
• Four ADCs implemented as B bit DAC and
comparator with 4 multiplexed inputs
• +5V power supply
• Page clearing within one line
• RGB interface to standard colour decoder
ICs, push pull output drive
• Display clock derived internally to reduce
peripheral components to a minimum
• 32Kbytes mask programmed ROM
• 4 high current open drain port output
• Master and slave byte wide 12C-bus
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
VERSION
PACKAGE
PINS
PIN POSITION
MATERIAL
CODE
SAA5296ZP/nnn
(note 1)
ROM
52
SDIL
plastic
SOT247
SAA5296H/nnn
(note 1)
Internal/External
ROM
80
QFP
plastic
SOT318
SAA5296XP/NV
EEPROM
52
SDIL
plastic
SOT247
SAA5296H/NV
EEPROM
80
QFP
plastic
SOT318
NOTE:
1. nnn refers to the program mask number.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Voo
Supply voltage
4.5
5.0
5.5
V
100
Supply current
-
115
-
mA
loos
Supply current - standby text
30
40
mA
fCLK
Clock frequency
-
12
-
MHz
Tamb
Operating ambient temperature
-20
-
+70
°C
February 1994
3-114
Philips Semiconductors Video Products
Objective specification
Single chip economy 10 page teletext!
TV microcontroller
SAA5296
Black IRef
R.G.B.
Teletext
CVBSO.--+...........,
CVBSI
I---t--.. VDS.
Acquisition
COR
VSync
Acquisition
HSync
TIming
Frame
XtalIn
XtalOut
OscGnd
Reset
Vdd
Vss
Test
Pl.O-I.7
P2.0-2.7
PO.O-O.7
P3.0-3.4
Figure 1. Block Diagram
February 1994
3-115
Philips Semiconductors Video Products
Objective specification
Single chip economy 10 page teletext!
TV microcontroller
SAA5296
+
:m:nn lotO
lOW
10t0
Vfune
Vdd
'''''~EEPROM
'~.:
. i~47",;;!;1~.~,3oF
~
0000
Vu
Vu
S~296
~OL- ~:~T:O
.~
r-r-"""T""""""'''''F-I~V''
~~I
~::~ I---I-I---I-I-~++++--"} g~
Brightness .----l=-++H~~H~J-4P2.2JPWMI P1.7/SDA
P2.3/PWM2 P1.61SCL
.---+++++-H6!:"=F+-CJ-4 P2.4/PWM3 P1.3trl
~
ContraSt
Sawration
g.
~:me (L)::====tttttl=~~~~tt~~~=~
P2.S/PWM4 P1.2I1NTO 1-_ _ _ _- -......_...... ~ .
::...r----+-I-+-bt8==+-If-++-t::::>----I P2.6/PWMS purro
Volume (R)
Vdd
__
P2.7/PWM6 PI.O/INTI \---...,,..---.....,,.,,....--1
;:_~~~~~~V~I~r-~P3.O/ADCO
~
.uuuuu
Vafc
.-
-'::"~7ilinnn~~
~:~~
P3.3/A0C3
-(:!
r~~'~'I'~==;.;~L
.~~========~j
..
1"' I I
~ ~ I
~~
PO.I
PO.2
Vddm =....lli
X~~:
~
Xtal1n
Os~d~~
~
~
=::; 4
F
:":
f--
I.~
Receiver
Vdda \
IvSync
--- - - - - - - Field tlyback
·;~s~ ~ II~I!~i n~I- -.- . Ilr!:- n~;:r-l.-v-\- Lioeftl : ; ~ :
-=
r-:,
11.._:':..-:-::.:.:.::::::::
;ulpar- ~t
~e! 1=;11 ~4JI)UO: External memory read strobe
11
WR: External memory write strobe
17
Program store enable output: Read strobe to external program memory.
18
Address Latch Enable: Output pulse for latching the low byte of the address during access
to external memory.
-
13,
Address Latch Enable: Output pulse for latching the low byte of the address during access
to external memory.
ADQ-AD7
-
69-76
ADO - AD7: External memory multiplexed low order address and data bus.
A8-A15
-
55-52, 35-32
A8 - A15: External memory high order address.
NOTE:
1. 7 bit open drain port QFP80 variant.
MICROCONTROLLER INTERFACING
The 80C51 CPU communicates with the peripheral functions uSIng Special Function Registers
(SFRs) which are addressed as direct RAM. The registers in the teletext decoder appear as
normal SFRs in the microcontroller memory map, but are written to using a serial bus. This bus
is controlled by dedicated hardware which uses a simple handshake system for software
synchronization. The SFR map is given: .
..
Address
(hex)
8 bytes
F8
FO
B
E8
SAD
EO
ACC
D8
S1CON
DO
PSW
CB
TXTB
S1STA
S1DAT
S1ADR
PWM3
PWM4
PWM5
TDACl
TDACH
PWM7
PWMO'
PWM1
PWM2
TXT9
TXT10
TXT11
TXT12
TXT14
TXT15
TXT16
TXT2
TXT3
TXT4
'TXT5
TXT6
TXT7
THO
TH1
CO
TXTO
TXT1
B8
TXT13
TXT17
BO
P3
A8
IE
AO
P2
98
SAD2
90
P1
88
TCON
TMOD
TlO
Tl1
80
PO
SP
DPl
DPH
February 1994
PWM6
PCON
3-118
Objective specification
Philips Semiconductors Video Products
Single chip economy 10 page teletext!
TV microcontroller
SAA5296
The following SFRs are standard 8051 SFRs and their contents and application have not been changed for the SAA5296: ACC, B, PSW, PO,
P1, P2, P3, PCON, TCON, TMOD, TLO, THO, TL 1, TH1, SP, DPL and DPH. SFRs S1 CON, S1 STA, S1ADR and S1 DAT are standard
P8xCE652 SFRs and their contents and application have not been changed for the SAA5296. The contents of the remaining registers are
specific to the SAA5296 and are shown below:
Register
Bit7
Bit6
BitS
Bit4
Bit3
Bit2
Bit 1
IE
EA
ES1
-
-
ET1
EX1
ETO
EXO
TXTO
X24
POSITION
DISPLAY
X24
AUTO
FRAME
DISABLE
HDR ROLL
STATUS
ROW ONLY
DISABLE
FRAME
VPSON
INVON
TXT1
EXTPKOFF
8 BIT
ACQOFF
X26
FULL FIELD
FIELD
POLARITY
H POLARITY
V POLARITY
TXT2
-
REQ3
REQ2
REQ 1
REQO
SC2
SC1
SCO
TXT3
-
-
PRD3
PRD2
PRD1
PRDO
TXT4
-
PRD4
EASTiWEST
DISABLE
DBLHT
BMESH
ENABLE
CMESH
ENABLE
TRANS
ENABLE
SHADOW
ENABLE
TXT5
BKGNDOUT
BKGND IN
'COR OUT
'COR IN
TEXT OUT
TEXT IN
PICTURE
ON OUT
PICTURE
ONIN
TXT6
BKGNDOUT
BKGND IN
'COR OUT
'COR IN
TEXT OUT
TEXT IN
PICTURE
ON OUT
PICTURE
ONIN
TXT7
STATUS
ROW TOP
CURSOR
ON
CONCEAU
TOP"/
REVEAL
BOTTOM
smIDDBL
HEIGHT
BOX ON
24
BOX ON
1-23
BOX ON
0
TXT8
-
-
-
-
-
-
-
CVSSO/
TXT9
CURSOR
FREEZE
CLEAR
MEMORY
AO
R4
R3
R2
R1
RO
TXT 10
-
-
C5
C4
C3
C2
C1
CO
TXT11
D7
D6
D5
D4
D3
D2
D1
DO
TXT12
625/525
SYNC
ROMvER
R4
ROMVER
R3
ROMVER
R2
ROMVER
R1
ROMVER
RO
TXT ON
VIDEO
QUALITY
TXT13
-
PAGE
CLEARING
625/525
DISPLAY
525 TEXT
625 TEXT
PKT 8/30
FAST EXT
TXTIIFACE
BUSY
TXT14
-
-
-
-
PAGE 3
PAGE 2
PAGE 1
PAGE 0
TXT15
-
-
-
BLOCK 3
BLOCK 2
BLOCK 1
BLOCK 0
TXT17
-
TDACL
TDACH
TXT16
BitO
CVBS1
Y2
Y1
YO
-
-
X1
X2
-
-
FORCE 625
FORCE 525
SCREEN
COL 2
SCREEN
COL 1
SCREEN
COLO
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TDO
TDE
-
TD13
TD12
TD11
TD10
TD9
TD8
PWMo-5
PWE
-
PV5
PV4
PV3
PV2
PV1
PVO
SAD
VHI
CH1
CHO
ST
SAD7
SAD6
SAD5
SAD4
SAD2
-
-
-
-
SAD3
SAD2
SAD1
SA DO
February 1994
3-119
Philips Semiconductors
Preliminary 'specification
One Chip Frontend 1 (OFC1)
SAA7110
Digital multistandard colour decoder with 2 AID converters
SHORT DESCRIPTION
The one chip frontend SAA7110 is a digital multistandard
colour decoder (OCF1) on the basis of the digitallV-2 system with 2 integrated NO converters, scibek generation circuit(CGC) and BCS- (Brightness, Contrast, Saturation) control.
• The YUV bus supports a data rate of:
(780 x ftJ for 60 Hz 12.2727MHz (NTSC)
(944 x ftJ for 50 Hz 14.75MHz(PALlSECAM)
• Square pixel-format with 168/~0 active samples per line
on the YUV bus
.
• CCIR 601 level compatible
• 4:2:2 and 4:1:1 YUVoutput formats in 8-bit resolution
• User programmable luminance peaking for aperture correction
FEATURES
• Six analog inputs (six times CVBS or three times Y/C or
combinations)
• Com patible with memory-based
clock, square pixel)
• Three analog processing channels
•
•
•
•
Three built in analog anti alias filters
Analog signal adding of two channels
Two Video CMOS 8-bit A/D- converters
Full programmable static gain for the main channels or automatic gain control for the selected CVBS/y channel
• Selectable signal (white) peak control
features
(line-tocked
• Requires only one crystal (26.8MHz) for all standards
• Real-time status information output (RTCO)
• Brightness Contrast Saturation control for the YUV-bus
• Negation of picture possible
• One. user programmable general purpose switch on an output pin
• Luminance and chrominance Signal processing for standards PAL-BIG, NTSC-M, SECAM
• Switchable between on-chip Clock Generation Circuit
(CGC) and external CGC (SAA7197)
• Full range HUE control
• Automatic detection of 50/60Hz field frequency -> automatic switching between standards PAL and NTSC, SECAM forceable
• Power On Control
2
• 1 C-bus controlled
• Horizontal and vertical sync detection for all standards
• Cross-colour reduction by chrominance comb filtering for
NTSC or special cross-colour cancellation for SECAM
• UV signal delay lines for PAL to correct chrominance
phase errors
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN
V DD
digital supply voltage range
4.5
5.5
V
V DDA
analog supply voltage range
4.75
5.25
V
Tamb
ambient temperature range
0
70
°C
MAX
UNIT
ORDERING AND PACKAGE INFORMATION
PACKAGE
EXTENDED TYPE
NUMBER
PINS
SAA7110
68
April 1994
I
I
PIN POSITION
PLCC
3-120
1
1
MATERIAL
Plastic
I
I
COD.E
SOT188CG14
-u
i
~
co
co
III
IllCD-IG')
-oo:Ym
o g:~~~
n g.[~ ~
r
~
"»
o
G')
::0
OCF1-SAA7110
AOUT
»
3:
f.---IE.
BYPASS
~ ~
C/)
r
~(jd~' ~
g
:y III
en
CD:y;:=;:()
~ output; CGCE=O -> input); this is the system clock, its frequency is 1888*fh for 50 Hz/625 lines per field systems and
1560*fh for 60 Hz/525 lines per field systems; or variable input clock up to 32M Hz
in input mode.
30
LLC2
0
Line Locked Clock output; fLLC2=0.5xfLLC; (CGCE=1 -> output; CGCE=O -> High
impedance)
31
CREF
I/O
CLOCK REFERENCE I/O (CGCE=1 -> output; CGCE=O -> input). This is a clock
qualifier signal distributed by the internal or an external clock generator circuit
(CGG). Using CREF all interfaces on the YUV bus are able to generate a bus timing with identical phase.
RESET active LOW I/O (CGCE=1 -> output; CGCE=O -> input); sets the device
into a defined state. All data outputs are in high impedance state. The 12C-bus is
reset (waiting for start condition). Using the external CGC, the LOW period must
be maintained for at least 30 LLC clock cycles.
32
RESN
I/O
33
CGCE
I
CGC Enable input Signal, active HIGH; (CGCE=1 -> On chip CGC active;
CGCE=O -> External CGC mode: use SAA7197)
34
V DD4
P
positive supply voltage (+ 5 V)
35
V SS4
P
ground
36
37
April 1994
HCL
HSY
I/O
HORIZONTAL CLAMPING pulse I/O (programmable via IIC-bit PULlO, PULlO=1
-> output, PULlO=O -> input); this signal is used to indicate the black level clamping period for the analog input interface. The beginning and end of its HIGH period (only in the output mode) can be programmed via the 12C-bus register 03h,
04h in 50 Hz mode and registers 16h, 17h in 60 Hz mode, active HIGH.
I/O
HORIZONTAL SYNC indicator signal I/O (programmable via IIC-bit PULlO,
PULlO=1 -> output, PULlO=O -> input); is used to indicate the sync tip part of the
CVBS input signal for gain control purposes. This signal is fed to the analog interface. The beginning and end of its HIGH period (only in the output mode) can be
programmed via the 12C-bus register 01 h, 02h in 50 Hz mode and registers 14h,
15h in 60 Hz mode, active HIGH.
3-123
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
TABLE 1. PINNING
PIN NO.
38
DESCRIPTION
SYMBOL IIOIP
HS
0
HORIZONTAL SYNC output signal (programmable; the high period is 128 LLC
clock cycles. The position of the positive slope is programmable in 8 LLC increments over a complete line (= 64 us) via 12C-bus register 05h (50 Hz mode) or
18h (60 Hz mode).
39
PLIN
(HL)
0
PAL IDENTIFIER NOT output signal; marks for demodulated PAL signals the inverted line (PLlN=LOW) and a non inverted line (PLlN=HIGH) and for demodulated SECAM signals the DR line (PLlN=LOW) and the DB line (PLlN=HIGH). Select PLIN function via IIC-bit RTSE=O.
(H-PLL LOCKED output signal; a HIGH state indicates that the internal PLL has
locked; select HL function via 12C-bit RTSE=1).
40
ODD
(VL)
0
ODD/EVEN field identification (output); a HIGH state indicates the odd field. Select ODD function via IIC-bit RTSE=O.
(VERTICAL LOCKED output signal; a HIGH state indicates that the internal VNL
is in a locked state; select VL function via 12C-bit RTSE=1).
I/O
VERTICAL SYNC Signal I/O (programma~1e via IIC-bit OEHV, OEHV=1 -> output, OEHV=O -> input); this signal indicates the vertical sync with respect to the
YUV output. The high period of this signal is approximate six lines if the vertical
noise limiter (VNL) function is active. The positive slope contains the phase information for a deflection controller, e.g. TDA9150. In input mode, this signal is used
to synchronize the vertical gain- and clamp-blanking stage, active HIGH.
HREF
0
HORIZONTAL REFERENCE output signal; this signal is used to indicate data on
the digital YUV bus. The positive slope marks the beginning of a new active line.
The HIGH period of HREF is either 768 Y samples or 640 Y samples long depending on the detected field frequency (50/60 Hz-mode). HREF is used to synchronize data mUltiplexer / demultiplexers. HREF is also present during the vertical blanking interval.
43
VSS3
P
ground
44
V DD3
P
positive supply vOltage (+ 5 V)
Y (7~2)
0
Digital Y (luminance) output signal; higher 6 bits of the 8-bit luminance output signal as part of the digital YUV bus (data rate LLC/2), or A/D2(3) output (data rate
LLC/2) selectable via IIC-bit SQPB=1.
41
42
45-50
VS
51
V SS2
P
ground
52
V DD2
P
positive supply voltage(+ 5 V)
53-54
Y (1-0)
0
Digital Y (luminance) output signal; lower 2 bits of the 8-bit luminance output signal as part of the digital YUV bus (data rate LLC/2), or A/D2(3) output (data rate
LLC/2) selectable via IIC-bit SQPB=1
0
Digital UV (color difference) output signal; multiplexed color difference signal for
U and V component of demodulated CVBS or Chroma signal. The format and
multiplexing scheme can be selected via 12c-bus control. These signals are part
of the digital YUV bus (data rate LLC/4),or A/D3(2) output (data rate LLC/2) selectable via IIC-bit SQPB=1
I
FAST ENABLE INPUT signal (active LOW); this signal is used to control fast
switching on the digital YUV bus. A HIGH at this input forces the IC to set its Y
and UV outputs to the high impedance state. (Set lie-bits MS24 and MS34 and
MUYC to LOW to use the FEIN function).
(MULTIPLEX COMPONENTS (input signal); control signal for the analog multiplexers for fast switching between locked VIC signals or locked CVBS signals.
FEIN automatically fixed to LOW (Digital YUV bus enabled), if one of the three
MUXC functions are selected (MS24 or MS34 or MUYC = HIGH)
55-62
63
April 1994
UV (7-0)
FEIN
(MUXC)
3-124
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SAA7110
TABLE 1. PINNING
PIN NO.
SYMBOL IIOIP
DESCRIPTION
64
GPSW
(VBLK)
0
GENERAL PURPOSE SWITCH (output signal); the state of this signal is programmable via 12C-bus register DDh, bit 1; select GPSW function via IIC-bit VBLKA=D.
(Vertical BLanK test output; select VBLK function via IIC-bit VBLKA =1)
65
XTAL
0
26.8 MHz crystal oscillator output; not connected if TTL clock signal is used
66
XTALI
I
Input terminal for 26.8 MHz crystal oscillator or connection of external oscillator
with TIL compatible square wave clock signal.
67
VSS1
P
ground
68
V OO1
P
positive supply vOltage (+ 5 V)
FIGURE 3. PINNING OCF1-SAA711 0
52'-l ()
c:a X
(')C\I
<
en -l
cn
cncn
ww w () 0< ~
en
cn
a: a: a:
0
()
fi:
a... a...
00 en
< cn > ~
:J
-l
~ ~
G::J
;: 6cn z
&iE
:;
~
::J
::J
VSSA4
UV2
AI42
UV3
VDDA4
UV4
AI41
UV5
VSSA3
UV6
AI32
UV7
SAA7110.VO
VDDA3
AI31
YO
Y1
VSSA2
VDD2
(OCF1.VO)
AI22
VDDA2
VSS2
Y2
AI21
Y3
VSSS
Y4
AOUT
Y5
VDDAO
Y6
VSSAO
Y7
LFCO
VDD3
10
10
()
C\I
U. Z
cn -l
--' () w cn
--' a: w
-l
() a:
> ~
0
0
April 1994
W
()
(!)
()
"'" cn"'"
0
0
> ~
3-125
--'
()
I
>cn
I
cn
I
cn w cn
E.G> a:
~
z 0
I
::::J::::J
it 8
u.
(')
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
eliminates most of the colour carrier signal, therefore, it
must be by-passed for S-Video (S-VHS, H18) signals.
The high frequency components of the luminance signal can
be "peaked" (control for sharpness Improvement via 12C
bus) in two bandpass filters with selectable transfer characteristic.
A coring circuit '~ith selectable char~cte~istic improves the
signal once more, this signal is then added to, the original
('unpeaked') signal. A switchable amplifier achieves a common DC amplification, because the DC gains are different in
both chrominance trap modes.
The improved luminance signal is fed via the variable delay
compensation to the BCS-contr~l and the·output interface.
4. FUNCTIONAL DESCRIPTION
ANALOG INPUT PROCESSING
The OCF1 offers six analog signal Inputs, two' analog' main
channels with clamp circuit, analog amplifie"anti alias filter,
and video CMOS ADC. A .third analog .channel also with
Clamp circuit, analog amplifier, anti alias filter can be added
or switched to both main channels directly before.the ADCs.
ANALOG CONTROL CIRCUITS
The clamp control circuit controls the' proper clamping of
the analog input signals. The coupling capacitor is also
used to storage and filter the clamping voltage. The normal
digital clamping level for luminance or CVBS signals is 64
and for chrominance signals 128.
The gain control circuits generate via 12C the static gain lev"
els for the three analog amplifiers or controls one of these
amplifiers automatically via a build in Automatic Gain Control AGC. The AGC is only used to amplify a CVBS or Y sig~
nal to the required signal amplitude, matched to the ADCs
input voltage range.
The anti alias filters are adapted to the clock frequency.
The vertical blanking control circuit generates a 12C programmable vertical blanking pulse. During the vertical blanking time gain and clamping control were frozen.
The fast switch control circuit is used for special applications.
CHROMINANCE PROCESSING
The 8-bit chrominance signal passes the input interface, the
chrominance bandpass filter to eliminate DC components,
and is finally fed to the multiplication inputs of a quadrature
demodulator, where two subcarrier signals from the local oscillator (DT01) with 90 degree phase shift are applied. The
frequency is dependent on the present colour standard.
The multiplier operates as a quadrature demodulator for all
PAL and NTSC signals; it operates as a frequency down
mixer for SECAM signals.
The two multiplier output signals are converted to a serial
UV data stream and applied to two lowpass filter Stages,
then to a gain controlled amplifier. A final multiplexed lowpass filter achieves, together with the preceding stages, the
required bandwidth performance.
The from PAL and NTSC originated signal are applied to a
comb filter.
The signal, originated from SE;CAM is fed through a clochefilter (0 Hz center frequency), a phase demodulator and a
differentiator to obtain frequency- demodulated colour-difference signals. The SECAM signal is fed after de-emphasis
to a cross-over switch, to provide the both serial-transmitted
colour-difference signals. These signals are fed to the BCS
control and finally to the output formatter stage and to the
output interface.
LUMINANCE PROCESSING
The 8-bit luminance signal, a digital CVBS format or a luminance format (S-VHS, H18), is fed through a switchable prefilter. High frequency components are emphasized to compensate for loss. The following chrominance trap filter (fo
4.43 MHz or to = 3.58 MHz center frequency selectable)
=
April 1994
YUV-BUS, DIGITAL OUTPUTS
The 16-bit YUV~bus transfers digital data from the output interfaces to a feature box, or a field memory, a digital colour
space converter (SAA 7192 DCSC) or a Video enhancement and D/A processor (SAA7165 VEDA2). The outputs
are controlled via the 12C bus in normal selections, or they
are controlled by an output enable chain (FEIN on pin 63).
The YUV data rate equals LLC2. Timing is achieved by
marking each second positive rising edge of the clock LLC
in conjunction with CREF (clock reference).
The output signals Y7 to YO are the bits of the digital luminance signal. The output,signals UV7 to UVO are the bits of
the multiplexed colour difference signals (B-Y) and (R-Y).
The frame in the format tables is the time, required to transfer a full set of samples; In'case of 4:2:2 format two lumi~
nance samples are transmitted in comparison to one U and
one V sample within the frame. The time frames are controlled by the HREF signal.
Fast enable is achieved by setting input FEIN to LOW. The
signal is used to control fast switching on the digital YUV~
bus. High on this pin forces the Y and UV outputs to a highimpedance state.
SYNCHRONIZATION
The prefiltered luminance signal is fed to the synchroniza~
tion stage.' It's bandwidth is reduced to 1 MHz in a low-pass
filter. The sync pulses are sliced and fed to the phase detectors to be compared with the sub-divided clock frequency.
The resulting output signal is applied to the loop filter to accumulate all phase deviations. Adjustable output signals (e.
g. HCL and HSy) are generated according to analog frontend requirements. The output signals HS, VS, and PUN
are locked to the timing reference guaranteed between the
input signal and the HREF signal as further improvements to
the circuit may change the total processing delay. It is therefore not recommended to use them for applications, which
ask for absolute timing accuracy to the input signals. The
loop filter signal drives an oscillator to generate the line frequency control output signalLFCO.
CLOCK GENERATION CIRCUIT
The internal CGC generates all clock signals required in the
one chip frontend. The output signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is
the multiple of the line frequency:
7.38 MHz 472 x fH in 50 Hz systems
3-126
=
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SAA7110
=
6.14 MHz 360 x fH in 60 Hz systems
Internally the LFCO signal is multiplied by factors 2 or 4 in
the PLL circuit (including phase detector, loop filtering, VCO
and frequency divider) to get the LLC and LLC2 output clock
signals. The rectangular output clocks have a 50% duty factor.
It's also possible to operate the OCF1 with an external CGC
(SAA7197) providing the signals LLC and CREF for the
OCF1. The selection of the intern/external CGC will be controlled by the CGCE input signal.
RTCOOUTPUT
This real time control and status output signal contains serial information about actual system clock, subcarrier frequencyand PALISECAM sequence. The signal can be used for
various applications in external circuits, e. g. in a digital encoder to achieve "clean" encoding.
POWER-ON RESET
Power-on reset is activated at power-on (only using internal
CGC), when the supply voltage decreases below 3.5 V. The
indicator output RESN is LOW for a time. The RESN signal
can be applied to reset other circuits of the digital TV system.
April 1994
3-127
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RESN
SAA7110
~
SYNC SLICER
PHASE
DETECTOR
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DETECTOR
~ LOOP 2FILTER
::D
m
I
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ADJUST
~ LlNE.LOCKED ~CREF
CLOCK
~~.'~.T~n
9
0
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~ LLC2
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d:
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:::J
Preliminary specification
Philips Semiconductors
One Chip Frontend 1 (OFC1)
SAA7110
5. CLAMP AND GAIN DESCRIPTION
CLAMPING
The coupling capacitance is used as clamp capacitance for
each input. An internal digital clamp comparator generates
the information about clamp-up or clamp-down. The clamping levels for the two AID channels are adjustable over the
8-bit range (1 to 254). Clamping time in normal use is set
with the HCL pulse at the back porch of the video Signal.
The clamping pulse HCL is user adjustable.
GAIN CONTROL
The luminance AGC can be used for every channel were luminance or CVBS is coming in. AGC active time is the sync
tip of the video signal. The sync tip pulse HSY is user adjustable. The AGC can be switched off and the gain for the
three main input channels can be adjusted independently.
Signal (white) peak control limits the gain at signal overshoots. The flow charts on this page and on the next page
show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control.
FIGURE 7. AUTOMATIC GAIN CONTROL RANGE
analog input level
controlled ADC input level
FIGURE 8. CLAMP AND GAIN FLOWCHART
CLAU = CLAMP UP
VBLK VERTICAL BLANKING PULSE
WIPE = WHITE PEAK LEVEL (ADJUSTABLE)
SBOT = SYNC BOTTOM lEVEL (ADJUSTABLE)
Cll = CLAMP LEVEL (ADJUSTABLE)
CLM = CLAMP ACTIVE
HSY = HORIZONTAL SYNC PULSE
HCl = HORIZONTAL CLAMP PULSE
=
NOACTlON
o
April 1994
3-131
Preliminary specification
Philips Semiconductors
One Chip Frontend 1 (OFC1)
SAA7110
FIGURE 9'. LUMINANCE AGC FLOWCHART
GAIN FLOW CHART
B
o
x = SYSTEM VARIABLE (START WITH 0)
Y = IAGV-FGVI > GUDL
VBLK = VERTICAL BLANK PULSE
HSY = HORIZONTAL SYNC PULSE
SBOT = SYNC BOTTOM LEVEL (ADJUSTABLE)
WIPE = WHITE PEAK lEVEL (ADJUSTABLE)
IVAl = INTEGRATION VALUE GAIN (ADJUSTABLE)
WVAL = INTEGRATION VALUE WIPE (ADJUSTABLE)
IGAI = INTEGRATION FACTOR GAIN (ADJUSTABLE)
IWIP = INTEGRATION FACTOR WIPE (ADJUSTABLE)
AGV ACTUAL GAIN VALUE
FGV = FROZEN GAIN VALUE
GUDL = GAIN UPDATE lEVEL (ADJUSTABLE)
WASE = WHITE PEAK RESET ENABLE
=
WIRS = WHITE PEAK RESET SELECT
L= UNE
F
= FIELD
April 1994
3-132
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
6. LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); all ground pins as well as all supply pins connected together.
TABLE 2. LIMITING VALUES
SYMBOL
MIN
MAX
UNIT
T stg
Storage temperature
PARAMETER
-65
+150
°C
-10
+80
°C
0
+70
°C
tamb
Temperature under bias
Tamb
Operating ambient temperature range
V DD
Supply voltage digital
-0.5
+7.0
V
V DDA
Supply voltage analog
-0.5
+7.0
V
VI
I nput voltage digital
-0.5
+7.0
V
VI
I nput voltage analog
-0.5
+7.0
V
VdiffGND
Difference voltage VSSAall - VSSall
-
100
mV
V ESD
Electrostatic * handling for all pins
-
±2000
V
2.5
W
Ptot
total power dissipation
* Equivalent to discharging a 100pF capacitor through an 1.5kQ series resistor
7. ELECTRICAL CHARACTERISTICS
TABLE 3. ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITIONS
MIN
LIMITS
TYP
MAX
4.5
5
5.5
V
rnA
UNIT
Supply
V DD1 -5
digital supply voltage range
IDD1 -5
digital total supply current
VDDAO ,2-4
analog supply voltage range
IDDAo ,2-4
analog total supply current
-
-
250
4.75
5
5.25
V
-
-
150
rnA
Analog part
Icl amp
clamp current
Vi=1.25VDC
-
±2
-
J-lA
Vi (pp)
input voltage
(AC coupling necessary)
Ccoup=10nF
0.5
1
1.38
Vpp
IZd
i,nput impedance
Iclamp off
200
-
-
kQ
Ci
input capacitance
a
channel crosstalk
f 2-5 (max)
SIN (f~f6)
April
1994
-
-
10
pF
f< 5MHz
-
-50
-
dB
maximal harmonic distortion
(Input signal: near full scale
sinus)
at 4.0MHz,
gain=OdB,
AAF=on
-
t.b.d.
-
dB
signal-to-noise ratio
(Input signal: near full scale
sinus)
at 4.0MHz,
gain=OdB,
AAF=on
-
t.b.d.
-
dB
3-133
Preliminary specification
Philips. Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
TABLE 3. ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITIONS
MIN
LIMITS'
TVP
MAX
UNIT
ACCs
Gdiff
analog bandwidth
differential phase
(Amplifier and AAF=bypass)
differential gain
(Amplifier and AAF=bypass)
f LLC
clock rate ADC
DLE
ILE
DC differential linearity error
DC integral linearity error
B
YUV (see TABLE 7)
"
~
Y - output
I
I
HREF (50 Hz)
~
1
18*2/LLC
768 * 2/LLC
176*2/LLC
"I
30*2/LLC
94 * 2/LlC
I
IX
PUN (50 Hz)
~
~4/LLC
~~
HS (50 Hz)
64 *2/LLC
HS (50 Hz)
programming range
1~
-118
0
#-l
(step size: 8ILLC)
HREF (60 Hz)
~ 18*2/LLC
640*2/LLC
1.
140*2/LLC
.~~
HS (60 Hz)
~
64*2/L!-C
HS (60 Hz)
programming range
~
-97
0
#-l
(step size: 8/LLC)
Note: HRMV=1 and HRFS=O
April 1994
3-138
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
FIGURE 12. HREFTIMING
LL27
CREF
._-....
INTERNAL
BUS CLOCK
HREF
Yn
UVn
HREF
Yn
763
-----+'"
(50Hz)
UVn
V762
Yn
635
(60Hz)
UVn
April 1994
V634
3-139
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SAA7110
FIGURE 13. VERTICAL TIMING
condition: Nominal input signal, 50 Hz
a: 1st field
625
2
4
I
I
I
7
5
I
I
input CVBS
HREF
~
I 533*2/LLC
~ IE- 2 * 2ILLC
VS
I
ODD
313
b: 2nd field
I
314
315
I
316
I
317
318
I
I
319
I
320
I
321
I
I
input CVBS
HREF
VS
ODD
condition: Nominal input signal, 60 Hz
525
a: 1st field
2
I
3
I
4
I
6
5
I
I
7
I
8
I
9
I
I
input CVBS
HREF
H1*2ILLC
VS
~ 1E-2 *2/LLC
I
ODD
b: 2nd field
2F
2f4
2f5
2f6
2f1
2YS
2f9
O
2T
2r
inputCVBS
HREF
VS
ODD
Note: HRMV=1 and HRFS=O
April 1994
3-140
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SAA7110
9. DIGITAL OUTPUT CONTROL
FIGURE 14. FEIN TIMING
LLC
HMt::r-I-------.,f--L'
TABLE 4. DIGITAL OUTPUT CONTROL
OEYC
FEIN
0
0
Z
1
0
active
X
1
Z
YUV(15:0)
1O. REALTIME CONTROL OUTPUT
FIGURE 15. REAL TIME CONTROL OUTPUT
transmitted once per line
SEQUENCE
LOW
HIGH
HPLL-INCR.
FSCPLL-INCR.
~
128
Note: RICO-sequence is generated in LLC/4.
For transmission LLC/2-timing is required.
April 1994
~
3-141
RESERVED
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
11. OUTPUT FORMATS
TABLE 6. 4:2:2 FORMAT
TABLE 5. 4:1:1 FORMAT
BUS SIG-
BUS SIG-
Pixel Byte Sequence
NAL
Pixel Byte Sequence
NAL
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UVO
YFRAME
UV
FRAME
U7
U6
V7
V6
U5
U4
V5
V4
U3
U2
V3
V2
U1
UO
V1
VO
U7
.U6
V7
V6
U5
U4
V5
V4
U3
U2
V3
V2
U1
UO
V1
VO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b
0
0
0
0
0
0
0
0
U7
U6
U5
U4
U3
U2
U1
UO
0
1
2
3
4
5
6
7
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UVO
Y FRAME
UV
FRAME
V7
V6
V5
V4
V3
V2
V1
VO
1
U7
U6
U5
U4
U3
U2
U1
UO
2
V7
V6
V5
V4
V3
V2
V1
VO
3
U7
U6
U5
U4
U3
U2
U1
UO
4
V7
V6
V5
V4
V3
V2
V1
VO
5
0
4
Data rate
Sample frequency
LLC2
LLC2
LLC4
LLC4
Note:
Y
U
V
0
2
0
4
Note:
Y
U
V
Data rate
Sample frequency
LLC2
LLC2
LLC8
LLC8
12. PROCESSING DELAY
TABLE 7. PROCESSING DELAY (CVBSIN - YUVOUl)
FUNCTION
ANALOG DELAY (typical)
AIN41 -> ADCIN(AOUl)
(ns)
AFCCS=O
AFCCS=1
20
without AMP + AAF
with AMP, without AAF
April 1994
I
DIGITAL DELAY
ADCIN(AOUl) -> YUVOUT
(1/LLC)
[yDEL=O, CAD2/3=1j
50
with AMP + AAF (50Hz)
50+25
with AMP + AAF (60Hz)
50+35
I
I
3-142
248
50+50
50+70
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
13. YUV OUTPUT SIGNAL RANGE
FIGURE 16. YUV OUTPUT SIGNAL RANGE
+255.....------
+255
+------
+240
blue 100%
+240
red 100%
+212
blue 75%
+212
red 75%
+235
+128
LUMINANCE 100%
+255
~
+128
+128
U-COMPONENT
1
+44
+16
o
+---------
+16
V-COMPONENT
yellow 75%
+44
yellow 100%
+16
o
(a) Y Output Range
1
o
(b) U Output Range (8-Y)
(c) V Output Range (R-Y)
celR Rec. 601 digital levels
14. OSCILLATOR APPLICATION
FIGURE 17. OSCILLATOR APPLICATION
quartz (3rd harmonic)
26.8MHz
.....- - -
XTAL
XTAL
65
SAA7110
XTALI
C=10pF
:I:
:I:
65
SAA7110
J1Jl
66
XTALI
66
L=10uH +/-20%
C=1nF
(a) With Quartz Crystal
April 1994
cyan 75%
cyan 100%
3-143
(b) With External Clock
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SAA7110
15. CLOCK GENERATION CIRCUIT
The internal CGC generates the system clock LLC, LLC2 and the clock reference signal CREF. The internal generated LFCO
(triangular waveform) is multiplied by four via the analog PLL (including phase detector, loop filter, VCO and frequency divider). The rectangular output signals have 50% duty factor.
FIGURE 18. CLOCK GENERATION CIRCUIT
LFCO
BANDPASS
ZEROCROSS
PHASE
LOOP
FC=LLC/4
DETECllON
DETECTION
FILTER
LLC
DIVIDER
1/2
LLC2
CREF
16. CLOCK FREQUENCIES
TABLE 8. SYSTEM CLOCK FREQUENCIES (MHZ)
CLOCK
50Hz
XTAL
April 1994
60Hz
26.8
LLC
29.5
24.545454
LLC2
14.75
12.272727
LLC4
7.375
6.136136
LLC8
3.6875
3.068181
3-144
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
17. POWER·ON CONTROL
Power-on reset is activated at power-on (only using internal CGC) and if the supply voltage decreases below 3.5 V. The
RESN signal can be applied to reset other circuits of the digital TV system.
FIGURE 19. POWER-ON CONTROL
POCVDD
ANALOG
...
LLC
CGCE
.
...
..
+
POCVDD
DIGITAL
I
9-
POC
LOGIC
~
DELAY
CONTROL
...
RESN
-t
I
--.
CLOCK
OUTPUT
ACTIVE
CONTROL
CLOCKljO
CONTROL
TABLE 9. POWER-ON CONTROL SEQUENCE
I NTERNAL POWER ON
CONTROL SEQUENCE
DIRECTLY AFTER
POWER ON ASYNCHRONOUS RESET
START SYNCHRONOUS
IIC RESET SEQUENCE
STATUS after
IIC RESET
STATUS after
POWER ON CONTROL
SEQUENCE
April 1994
PIN OUTPUT STATUS
FUNCTION
Y(7:0), UV(7:0), RTCO, PUN, ODD,
GPSW, SOA, HREF, HS, VS, HCL,
HSY --> high impedance state
LLC, LLC2, CREF --> HIGH state
direct switching to high impedance (outputs) or input mode (I/Os) for
20 - 200ms
LLC, LLC2, CREF became active
starting IIC reset sequence
Y(7:0), UV(7:0), HREF, HS
--> held in high impedance state
VS, HCL, HSY
--> held in input function mode
RTCO, PUN, ODD, GPSW, SOA active
3-145
SAODh=7Dh (VTRC=O, RTSE=1,
HRMV=1, SSTB=O, SECS=1),
SAOEh=OOh (HPLL=O, OEHV=O,
OEYC=O, CHRS=O, GPSW1 =0),
SA31 h=OOh (AOSL(1 :0)=00, WIRS=O,
WRSE=O, SQPB=O, AFCCS=O, VBLKA=O, PUUO=O)
After power on (reset sequence) a
complete IIC transmission is requiredl
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
18. IIC DESCRIPTION
19. lie-BUS FORMAT
TABLE 10.
SLAVEADDRESS
lie FORMAT
SUBADDRESS
DATA (n bytes)*
S
start condition
SLAVEADDRESS
1001110Xb (IICSA=LOW) or 1001111Xb (IICSA=HIGH)
A
acknowledge, generated by the slave
SUBADDRESS
subaddress byte, see reference table
DATA
data byte, see reference table
p
stop condition
X
read/write control bit
X=O, order to write (the circuit is slave receiver)
X=1, order to read (the circuit is slave transmitter)
SLAVEADDRESS
9Ch for write (IICSA=O)
9Dh for read (IICSA=O)
9Eh for write (IICSA=1)
9Fh for read (IICSA=1)
SUBADRESSES
00 h - 19h Decoder part
1Ah - 1Fh reserved
20h - 34h Frontend part
* If more than one byte DATA are transmitted, then auto-increment of the subadress is performed.
April 1994
3-146
Preliminary specification
Philips Semiconductors
One Chip Frontend 1 (OFC1)
SAA7110
19.1 IIC-BUS RECEIVER-TRANSMITTER OVERVIEW TABLE
TABLE 11. IICOCF1
OCF1-Receiver
Slave-Addresses 100111 OOb, 9Ch [IICSA=O]
10011110b, 9Eh [IICSA=1]
I
OMSO-SQP+BCS SLAVE RECEIVER (SU 00h-19h)
REGISTER FUNCTION
SUB
AD DR
DATA BYTE
07
06
05
04
03
02
01
DO
006
IDEL6
005
IDEL5
004
IDEL4
003
IDEL3
002
IDEL2
001
IDEL1
000
IDELO
Increment delay
00
007
IDEL7
Horizontal sync HSY
begin 50 Hz
01
015
HSYB7
014
HSYB6
013
HSYB5
012
HSYB4
011
HSYB3
010
HSYB2
009
HSYB1
HSYBO
Horizontal sync
HSY stop 50 Hz
02
023
HSYS7
022
HSYS6
021
HSYS5
020
HSYS4
019
HSYS3
018
HSYS2
017
HSYS1
016
HSYSO
Horizontal clamp
HCL begin 50 Hz
03
031
HCLB7
030
HCLB6
029
HCLB5
028
HCLB4
027
HCLB3
026
HCLB2
025
HCLB1
024
HCLBO
Horizontal clamp
HCL stop 50 Hz
04
039
HCLS7
038
HCLS6
037
HCLS5
036
HCLS4
035
HCLS3
034
HCLS2
033
HCLS1
032
HCLSO
Horizontal sync
after PHI1 50 Hz
05
047
HPHI7
046
HPHI6
045
HPHI5
044
HPHI4
043
HPHI3
042
HPHI2
041
HPHI1
040
HPHIO
Luminance control
06
055
BYPS
054
PREF
053
BPSS1
052
BPSSO
051
CORI1
050
CORIO
049
APER1
048
APERO
Hue control
07
063
HUEC7
062
HUEC6
061
HUEC5
060
HUEC4
059
HUEC3
058
HUEC2
057
HUEC1
056
HUECO
Color Killer Threshold QUAM
08
071
CKTQ4
070
CKTQ3
069
CKTQ2
068
CKTQ1
067
CKTQO
066
XXX
065
XXX
064
XXX
Color Killer Thresh.
SECAM
09
079
CKTS4
078
CKTS3
077
CKTS2
076
CKTS1
075
CKTSO
074
XXX
073
XXX
072
XXX
Sensitivity PAL
switch
OA
087
PLSE7
086
PLSE6
085
PLSE5
084
PLSE4
083
PLSE3
082
PLSE2
081
PLSE1
PLSEO
Sensitivity SECAM
switch
DB
095
SESE7
094
SESE6
093
SESE5
092
SESE4
091
SESE3
090
SESE2
089
SESE1
088
SESEO
Gain Control Chrominance
OC
103
COLO
102
LFIS1
101
LFISO
100
XXX
099
XXX
098
XXX
097
XXX
096
XXX
Standard/mode control
OD*
111
VTRC
110
XXX
109
XXX
108
XXX
107
RTSE
106
HRMV
105
SSTB
104
SECS
I/O and clock control
OE*
119
HPLL
118
XXX
117
XXX
116
OEHV
115
OEYC
114
CHRS
113
XXX
112
GPSW
Control #1
OF
127
AUFD
126
FSEL
125
SXCR
124
SCEN
123
XXX
122
YDEL2
121
YDEL1
120
YDELO
Control #2
10
135
XXX
134
XXX
133
XXX
132
XXX
131
XXX
130
HRFS
129
VNOl1
128
VNOIO
Chroma gain reference
11
143
CHCV7
142
CHCV6
141
CHCV5
140
CHCV4
139
CHCV3
138
CHCV2
137
CHCV1
136
CHCVO
Chroma saturation
12
151
XXX
150
SATN6
149
SATN5
148
SATN4
147
SATN3
146
SATN2
145
SATN1
144
SATNO
Luminance contrast
13
159
XXX
158
CONT6
157
CONT5
156
CONT4
155
CONT3
154
CONT2
153
CONT1
152
CONTO
Horizontal sync HSY
begin 60 Hz
14
167
HS6B7
166
HS6B6
165
HS6B5
164
HS6B4
163
HS6B3
162
HS6B2
161
HS6B1
160
HS6BO
Horizontal sync
HSY stop 60 Hz
15
175
HS6S7
174
HS6S6
173
HS6S5
172
HS6S4
171
HS6S3
170
HS6S2
169
HS6S1
168
HS6S0
Horizontal clamp
HCL begin 60 Hz
16
183
HC6B7
182
HC6B6
181
HC6B5
180
HC6B4
179
HC6B3
178
HC6B2
177
HC6B1
176
HC6BO
April 1994
3-147
ooa
OBO
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (QFC1)
TABLE 11. IICOCFl
Horizontal clam p
HCL stop 60 Hz
17
191
HC6S7
190
HC6S6
189
HC6S5
188
HC6S4
187
HC6S3
186
HC6S2
185
HC6S1
184
HC6S0
Horizontal sync
after PHil 60 Hz
18
199
HP617
198
HP616
197
HP615
196
HP614
195
HP613
194
HP612
193
HP611
192
HP610
19
207
BRIG7
206
BRIG6
205
BRIG5
204
BRIG4
203
BRIG3
202
BRIG2
201
BRIGl
200
BRIGO
Luminance
ness
bright-
OUAO SLAVE RECEIVER (SU 20h-32h)
REGISTER
FUNCTION
SUB
AOOR
OATABYTE
07
D6
05
04
03
02
01
00
006
AIND3
005
AIND2
004
FUSEl
003
FUSEO
002
AINS4
001
AINS3
000
AINS2
Analog Control #1
20
007
AIND4
Analog Control#2
21
015
VBCO
014
MS34
013
MX241
012
MX240
011
MS24
010
REFS4
009
REFS3
008
REFS2
Mix Control
#1
22
023
GACOl
022
GACOO
021
CSEL
020
YSEL
019
MUYC
018
CLTS
017
MX341
016
MX340
Clamp level
Control 21
23
031
CLL217
030
CLL216
029
CLL215
028
CLL214
027
CLL213
026
CLL212
025
CLL211
024
CLL210
Clamp level
Control 22
24
039
CLL227
038
CLL226
037
CLL225
036
CLL224
035
CLL223
034
CLL222
033
CLL221
032
CLL220
Clamp level
Control 31
25
047
CLL317
046
CLL316
045
CLL315
044
CLL314
043
CLL313
042
CLL312
041
CLL311
040
CLL310
Clamp level
Control 32
26
055
CLL327
054
CLL326
053
CLL325
052
CLL324
051
CLL323
050
CLL322
049
CLL321
048
CLL320
Gain Control
Analog #1
27
063
HOLD
062
GASL
061
GAI25
060
GAl 24
059
GAl 23
058
GAI22
057
GAI21
056
GAI20
White Peak
Control
28
071
WIPE7
070
WIPE6
069
WIPE5
068
WIPE4
067
WIPE3
066
WIPE2
065
WIPEl
064
WIPEO
Sync bottom
Control
29
079
SBOn
078
SBOT6
077
SBOT5
076
SBOT4
075
SBOT3
074
SBOT2
073
SBOTl
072
SBOTO
Gain Control
Analog #2
2A
087
IWIPl
086
IWIPO
085
GAI35
084
GAl 34
083
GAl 33
082
GAI32
081
GAI31
080
GAI30
Gain Control
Analog #3
2B
095
IGAll
094
IGAIO
093
GAI45
092
GAl 44
091
GAl 43
090
GAl 42
.089
GAI41
088
GAI40
MIX Control
#2
2C
103
CLS4
102
XXX
101
CLS3
100
CLS2
099
XXX
098
XXX
097
TW03
096
TW02
Integration
value gain
2D
111
IVAL7
110
IVAL6
109
IVAL5
108
IVAL4
107
IVAL3
106
IVAL2
105
IVAL1
104
IVALO
Blank pulse
V SET
2E
119
VBPS7
118
VBPS6
117
VBPS5
116
VBPS4
115
VBPS3
114
VBPS2
113
VBPSl
112
VBPSO
Blank pulse
V RESET
2F
127
VBPR7
126
VBPR6
125
VBPR5
124
VBPR4
123
VBPR3
122
VBPR2
121
VBPRl
120
VBPRO
ADCsGain
Control
30
135
XXX
134
WISL
133
GAS3
132
GAD31
131
GAD30
130
GAS2
129
GAD21
128
GAD20
MIX Control
#3
31*
143
AOSLl
142
AOSLO
141
WIRS
140
WRSE
139
SOPB
138
AFCCS
137
VBLKA
136
PULIO
Integrationvalue white
peak
32
151
WVAL7
150
WVAL6
149
WVAL5
148
WVAL4
147
WVAL3
146
WVAL2
145
WVALl
144
WVALO
MIX Control
#4
33
159
OFTS
158
XXX
157
CHSB
156
XXX
155
CAD3
154
CAD2
153
XXX
152
XXX
April 1994
3-148
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
TABLE 11. IICOCF1
Gain Update Level
I
34
I
167
MUD2
I
166
MUD1
I
165
GUDL5
I
164
GUDL4
I
163
GUDL3
I
162
GUDL2
I
161
GUDL1
I
160
GUDLO
* Subadresses to be reset --> OD to 7Dh,
OE and 31 to OOh after RESN=O (CGCE=O) or POWER ON (CGCE=1)
Note: All reserved XXX-bits must be set to LOW
Slave-Addresses 10011101 b, 90h [IICSA=O]
10011111 b, 9Fh [IICSA=1]
I
OCF1-Transmitter
BYTE NO. 0 (transmitted if SSTB = 0 or after RESN has been 0)
VERSION
STATUS BYTE
ID(7:0)
I
I
07
ID7
I
I
06
ID6
I
I
05
ID5
I
I
04
ID4
I
I
03
ID3
I
I
02
ID2
I
I
01
ID1
I
I
00
IDO
Indicates the version number of the IC
e.g. : SAA7110 V1 =01h
BYTE NO.1 (transmitted if SSTB = 1)
s~~~~ru~ooll~_M_+1_0_6~1_0_5_~I~~_+1_0_3~1_0_2_~I_~_+1_0_O~
STTC
I
HLCK
I
FIDT
I
GUM
I
XXX
I
WIPA
STTC
Status Bit for horizontal time constant.
Status LOW: TV-time constant, HIGH: VCR-time-constant
HLCK
Status Bit for locked horizontal frequency.
Status LOW: locked, HIGH: unlocked
FIDT
Identification Bit for detected field frequency. Status LOW: 50 HZ,HIGH: 60 Hz
GUM
Gain value for active luminance channel is limited (max or min), active HIGH
XXX
reserved
WIPA
White peak loop is activated, active HIGH
ALTD
Status HIGH: Line-alternating color burst has been detected (PAL or SECAM)
CODE
Status HIGH: Any color signal has been detected
April 1994
3-149
I
ALTD
I
CODE
Preliminary specification
Philips Semiconductors
One Chip Frontend 1 (OFC1)
SAA7110
TABLE 12. lie DETAILSUOOh-04h(000-039)
IIC-RECEIVER :(SLAVE-ADDRESS 9Ch / 9Eh)
DMSD-SQP SLAVE RECEIVER (SU OOh-19h)
007-000
Subaddress 00 Increment delay IDEL
CONTROL BITS*
DECIMAL
MULTIPLIER
DELAy TIME (STEP
SIZE = 4/LLC)
IDEL7
IDEL6
IDEL5
IDEL4
IDEL3
IDEL2
IDELl
IDELO
-1 ...
-4
1
1
1
1
1
1
1
1
... -195
-780 (max. value for 60
Hz systems)
0
0
1
1
1
1
0
1
.;. "236
-944 (max. value for 50
Hz systems)
0
0
0
1
0
1
0
0
... -256
-1 024 (outside central
, counter)**
0
0
0
0
0
0
0
0
Where:
* A sign bit, designated A08 and internally set to HIGH, indicates values are always negative.
** The horizontal PLL does not operate in this condition. The system clock frequency is set to a
value fixed by the last update and is within +/-7.1% of the nominal frequency.
Subaddress 01 Horizontal sync begin 50 Hz HSYB
015-008
CONTROL BITS
, DECIMAL
MULTIPLIER
DELAY TIME (STEP
SIZE 2/LLC)
=
HSYB7
+191...
-382
1
... -64
+128
1
HSYB6
HSYB5
HSYB4
0
1
1
1
1
1
1
1
0
0
"0
0
0
0
HSYB3
HSYB2
HSYBl
Subaddress 02 Horizontal sync stop 50 HzHSYS
HSYBO
023-016
CONTROL BITS
DECIMAL
MULTIPLIER
DELAY TIME (STEP
SIZE 2/LLC)
=
HSYS7
HSYS6
HSYS5
HSYS4
HSYS3
HSYS2
HSYSl
+191...
-382
1
0
1
1
1
1
1
1
... -64
+128
1
1
0
0
0
0
0
0
Subaddress 03 Horizontal clamp begin 50 Hz HCLB
HSYSO
031-024
CONTROL BITS
DECIMAL
MULTIPLIER
DELAY TIME (STEP
SIZE 2/LLC)
=
HCLB7
HCLB6
HCLB5
HCLB4
HCLB3
HCLB2
HCLB1
HCLBO
+127...
-254
0
1
1
1
1
1
1
1
... -128
+256
1
0
0
0
0
0
0
0
Subaddress 04 Horizontal clamp stop 50 Hz HCLS
039-032
CONTROL BITS
DECIMAL
MULTIPLIER
DELAY TIME (STEP
SIZE 2/LLC)
=
HCLS7
HCLS6
HCLS5
HCLS4
HCLS3
HCLS2
HCLS1
+127...
-254
0
1
1
1
1
1
1
1
... -128
+256
1
0
0
0
0
0
0
0
April 1994
3-150
HCLSO
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SAA7110
TABLE 13. II DETAIL SUOSh-OSh(040-0S5)
047-040
Subaddress 05 Horizontal sync start after PHI1 50 Hz HPHI
DECIMAL
MULTIPLIER
DELAY TIME
SIZE 8/LLC
=
CONTROL BITS
(STEP
HPHI7
HPHI6
HPHI5
HPHI4
HPHI3
HPHI2
HPHI1
HPHIO
+127...
Forbidden; outside available central counter
range
0
1
1
1
1
1
1
1
... +118
Forbidden; outside available central counter
range
0
1
1
1
0
1
1
0
+117...
-32 fA.s (max. negative
value)
0
1
1
1
0
1
0
1
... -118
+31.7 fA.s (max. positive
value)
1
0
0
0
1
0,
1
0
-119 ...
Forbidden; outside available central counter
range
1
0
0
0
1
0
0
1
... -128
Forbidden; outside available central counter
range
1
0
0
0
0
0
0
0
Subaddress 06 Luminance control
055-048
Aperture factor APER
049-048
APERTURE FACTOR
CONTROL BITS
APER1
APERO
0
0
0
1
0.25
0
1
2
O.S
1
0
3
1
1
1
0
'.'
Corner correction CORI
CORING
050
+1- LSBS IN 8 BIT
CONTROL BITS CORI
0
o (OFF)
0
1
1
0
1
2
2
1
0
3
3
1
1
' .
0
Aperture bandpass (center frequency) BPSS
053-0S2
BANDPASS CENTER FREQ.
CONTROL BITS
50Hz
60Hz
BPSS1
BPSSO
4.S MHz
3.8 Mhz
0
0
4.3 MHz
3.4 MHz
0
1
3.0 MHz
2.5 MHz
1
0
3.2 MHz
2.7 MHz
1
1
April 1994
3-151
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
TABLE 13. II DETAIL SU05h-06h(040-055)
054
Prefilter active PREF
PREFILTER
CONTROL BIT PREF
Bypassed
0
Active
1
055
Chrominance trap bypass BYPS
CHROMA TRAP
CONTOL BIT BYPS
MODE
Active
CVBS
Bypassed
S-Video
TABLE 14. II DETAIL SU07h-OBh(056-095)
063-056
Subaddress 07 Hue phase control HUEC
CONTROL BITS
HUE PHASE (DEG)
HUEC7
HUEC6
HUEC5
HUEC4
HUEC3
HUEC2
HUEC1
+178.6 ...
0
1
1
1
1
1
1
1
... 0...
0
0
0
0
0
0
0
0
... -180
1
0
0
0
0
0
0
0
071-064
Subaddress 08 Control number 1
Color killer threshold QAM (PAL/NTSC) CKTQ
071-067
CONTROL BITS
THRESHOLD
(reference is nominal burst amplitude = 0 dB)
CKTQ4
CKTQ3
CKTQ2
CKTQ1
-30 dB ...
1
1
1
1
1
... -24 dB ...
1
0
0
0
0
... -18 dB
0
0
0
0
0
Subaddress 09 Control number 2
CKTQO
079-072
Color killer threshold SECAM CKTS
079-075
CONTROL BITS
THRESHOLD
(reference Is nominal burst amplitude = 0 dB)
CKTS4
CKTS3
CKTS2
CKTS1
-30 dB ...
1
1
1
1
1
... -24 dB ...
1
0
0
0
0
... -18 dB
0
0
0
0
0
Subaddress OA PAL switch sensitivity PLSE
SENSITIVITY
April 1994
HUECO
CKTSO
087-080
CONTROL BITS
PLSE7
PLSE6
PLSE5
PLSE4
PLSE3
PLSE2
PLSE1
LOW
1
1
1
1
1
1
1
1
MEDIUM
1
0
0
0
0
0
0
0
HIGH
0
0
0
0
0
0
0
0
3-152
PLSEO
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
TABLE 14. II DETAIL SU07h-OBh(056-095)
095-088
Subaddress OB SECAM switch sensitivity SESE
CONTROL BITS
SENSITIVITY
SESE7
SESE6
SESE5
SESE4
SESE3
SESE2
SESE1
LOW
1
1
1
1
1
1
1
1
MEDIUM
1
0
0
0
0
0
0
0
HIGH
0
0
0
0
0
0
0
0
SESEO
Sensitivity HIGH means immediate sequence correction
TABLE 15. IICDETAILSUOCh-OEh(096-119)
Subaddress OC Gain control chrominance
103-096
102-101
AGC (Automatic Gain ControQ - loop filter LFIS
CONTROL BITS
AGC - LOOP FILTER
TIME CONSTANT
LFIS1
LFISO
Slow
0
0
Medium
0
1
Fast
1
0
Actual chroma gain 'frozen'
1
1
Color on COLO
103
COLOUR ON
CONTROL BIT COLO
Automatic color killer
0
Color forced on
1
Subaddress 00 Standard/mode control
111·104
SECAM mode bit SECS
104
FUNCTION
CONTROL BIT SECS
other standards
0
SECAM
1
Status Byte select SSTB
105
FUNCTION
CONTROL BIT SSTB
Statusbyte is Byte 0 (see Transmitter)
0
Statusbyte is Byte 1 (see Transmitter)
1
HREF-POSITION select HRMV
April 1994
106
FUNCTION
CONTROL BIT HRMV
HREF position like SAA7191
(8 LLC2 later)
0
HREF normal position
1
3-153
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SAA7110
TABLE 15. IIC DETAIL SVOCh-OEh(096-119)
Real-time-outputs-mode select RTSE
107
FUNCTION
CONTROL BIT RTSE
PUN switched to output pin 39
aDD switched to output pin 40
0
HL switched to output pin 39
VL switched to output pin 40
1
TVNCR-mode select VTRC
111
FUNCTION
CONTROL BIT VTRC
TV mode
0
VTR mode
1
Subaddress OE I/O and clock control
119-112
General purpose switch GPSW
112
FUNCTION
CONTROL BIT GPSW
0
switches directly pin 64 GPSW
(application dependent) [VBLKA 0]
=
1
TABLE 16. IIC DETAIL SUOEh-OFh(114-127)
Select chrominance input CHRS
114
FUNCTION
CONTROL BIT CHRS
controlled by BYPS (subadress 06)
0
chroma input is CHR(7:0)
1
Output enable YUV-data OEYC
115
FUNCTION
CONTROL BIT OEYC
YUV-bus high impedance/input
0
Output YUV-bus active
1
Output enable horizontaljvertical sync OEHV
116
FUNCTION
CONTROL BIT OEHV
HS, HREF and VShigh impedance/inputs
0
Output HS, HREF and VS active
1
Horizontal PLL clock HPLL
119
FUNCTION
CONTROL BIT HPLL
PLLclosed
0
PLL open, horizontal frequency fixed
1
April 1994
3-154
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
TABLE 16. IIC DETAIL SUOEh-OFh(114-127)
127·120
Subaddress OF Control number 1
122-120
Luminance delay compensation YDEL
CONTROL BITS
LUMINANCE DELAY COMPENSATION
(steps in 2/LLC)
YDEL2
YDEL1
YDELO
0
0
0
0
3
0
1
1
-4
1
0
0
Enable or disable of sync and clamp pulses (HSY, HCL) SCEN
124
FUNCTION
CONTROL BIT SCEN
Disable sync and clamp (set to HIGH)
0
Enable sync and clamp
1
125
SECAM cross color reduction SXCR
FUNCTION
CONTROL BIT SXCR
Reduction OFF
0
Reduction ON
1
Field selection FSEL
126
FUNCTION
CONTROL BIT FSEL
50 Hz, 625 lines
0
60 Hz, 525 lines
1
Automatic field detection AUFD
127
FUNCTION
CONTROL BIT AUFD
Field state direct controlled via FSEL
0
Automatic field detection
1
TABLE 17. IIC DETAIL SU10h-13h(128-158)
Subaddress 10 Control number 2
135-128
Vertical noise reduction VNOI
129-128
FUNCTION
CONTROL BITS
VNOl1
VNOIO
Normal mode
0
0
Searching mode
0
1
Free running mode
1
0
Vertical noise reduction bypassed
1
1
130
HREF select HRFS
FUNCTION
CONTROL BIT HRFS
HREF matched to YUVoutput
0
HREF matched to CVBS input
1
April 1994
3-155
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SAA7110
TABLE 17. IIC DETAILSU10h-13h(128-158)
Subaddress 11 Chromlnance gain reference value CHCV
143-136
CONTROL BITS
REFERENCE VALUE
CHCV7
CHCV6
CHCV5
CHCV4
CHCV3
CHCV2
CHCV1
CHCVO
Maximum
1
1
1
1
1
1
1
1
CCIR-Ievel for PAL
0
1
0
1
1
0
0
1
CCI R-Ievel for NTSC
0
0
1
0
1
1
0
0
Minimum
0
0
0
0
0
0
0
0
Subaddress 12 Chrominance Saturation Control
150-144
CONTROL BITS
GAIN
SATN7
SATN6
SATN5
SATN4
SATN3
SATN2
SATN1
1.999 (MAXIMUM)
0
1
1
1
1
1
1
1
1 (CCI R-Ievel)
0
1
0
0
0
0
0
0
0
SATNO
o (COLOUR OFF)
0
0
0
0
0
0
0
-1 (inverse chroma)
1
1
0
0
0
0
0
0
-2 (inverse chroma)
1
0
0
0
0
0
0
0
Subaddress 13 Luminance Contrast Control
158-152
CONTROL BITS
GAIN
CONT7
CONT6
CONT5
CONT4
CONT3
CONT2
CONT1
1.999 (MAXIMUM)
0
1
1
1
1
1
1
1
70(CCI R-Ievel)
0
1
0
0
0
1
1
0
CONTO
1
0
1
0
0
0
0
0
0
o (LUMINANCE OFF)
0
0
0
0
0
0
0
0
-1 (inverse luminance)
1
1
0
0
0
0
0
0
-2 (inverse luminance)
1
0
0
0
0
0
0
0
TABLE 18. IIC DETAILSU14h-18h(160-199)
Subaddress 14 Horizontal sync begin 60 Hz HS6B
167-160
CONTROL BITS
DECIMAL
MULTIPLIER
DELAY TIME (STEP
SIZE 2/LLC)
=
HS6B7
HS6B6
HS6B5
HS6B4
HS6B3
HS6B2
HS6B1
+191...
-382
1
0
1
1
1
1
1
1
... -64
+128
1
1
0
0
0
0
0
0
Subaddress 15 Horizontal sync stop 60 Hz HS6S
HS6BO
175-168
CONTROL BITS
DECIMAL
MULTIPLIER
DELAY TIME (STEP
SIZE 2/LLC)
=
HS6S7
HS6S6
HS6S5
HS6S4
HS6S3
HS6S2
HS6S1
+191...
-382
1
0
1
1
1
1
1
1
... -64
+128
1
1
0
0
0
0
0
0
April 1994
3c156
HS6S0
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SAA7110
TABLE 18. lie DETAILSU14h-18h(160-199)
Subaddress 16 Horizontal clamp begin 60 Hz HC6B
183-176
CONTROL BITS
DECIMAL
MULTIPLIER
DELAY TIME (STEP
SIZE = 2/LLC)
HC6B7
HC6B6
HC6BS
HC6B4
HC6B3
HC6B2
HC6Bl
+127 ...
-254
0
1
1
1
1
1
1
1
... -128
+256
1
0
0
0
0
0
0
0
Subaddress 17 Horizontal clamp stop 60 Hz HC6S
HC6BO
191-184
CONTROL BITS
DECIMAL
MULTIPLIER
DELAY TIME (STEP
SIZE = 2/LLC)
HCL67
HC6S6
HC6SS
HC6S4
HC6S3
HC6S2
HC6S1
+127...
-254
0
1
1
1
1
1
1
1
... -128
+256
1
0
0
0
0
0
0
0
Subaddress 18 Horizontal sync start after PHil 60 Hz HP61
DECIMAL
MULTIPLIER
HC6S0
199-192
CONTROL BITS
DELAY TIME (STEP
SIZE = 8/LLC
HP617
HP616
HP61S
HP614
HP613
HP612
HP611
HP610
+127...
Forbidden; outside available central counter
range
0
1
1
1
1
1
1
1
... +98
Forbidden; outside available central counter
range
0
1
1
0
0
0
1
0
+97 ...
-32 f.AS (max. negative
value)
0
1
1
0
0
0
0
1
... -97
+31.7 J.ts (max. positive
value)
1
0
0
1
1
1
1
1
-98 ...
Forbidden; outside available central counter
range
1
0
0
1
1
1
1
0
... -128
Forbidden; outside available central counter
range
1
0
0
0
0
0
0
0
TABLE 19. lie DETAIL SU19h(200-207)
Subaddress 19 Luminance brightness control
OFFSET
April 1994
207-200
CONTROL BITS
BRIG7
BRIG6
BRIGS
BRIG4
BRIG3
BRIG2
BRIG1
BRIGO
255 (bright)
1
1
1
1
1
1
1
1
139 (eel R-Ievel)
1
0
0
0
1
0
1
1
128
1
0
0
0
0
0
0
0
o (dark)
0
0
0
0
0
0
0
0
3-157
P(eliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
TABLE 20. IIC DETAIL ~U20h(000-006)
DUAD SLAVE RECEIVER (SU 20h~32h)
007-000
Subaddress 20 Analog control #1
Analog input select 2 AINS2
000
FUNCTION
CONTROL BIT AINS2
Analog input AI 22 selected
0
Analog input AI21 selected
1
001
Analog input select 3 AINS3
FUNCTION
CONTROL BIT AINS3
Analog input AI32 selected
0
Analog input AI31 selected
1
Analog input select 4 AINS4
002
FUNCTION
CONTROL BIT AINS4
Analog input AI42 selected
0
Analog input AI41 selected
1
Analog function select FUSE
004-003
CONTROL BITS FUSE(1 :0)
FUNCTION
FUSE1
FUSEO
AMPLIFIER + ANTI ALIAS FILTER
bypassed
0
0
0
1
AMPLI FI ERactive
1
0
AMPLIFIER + ANTI ALIAS FILTER active
1
1
Analog input disable 2 AIND2
005
FUNCTION
CONTROL BIT AIND2
Analog inputs 2 enabled
0
Analog inputs 2 disabled
1
Analog input disable 3 AIND3
006
FUNCTION
CONTROL BIT AIND3
Analog inputs 3 enabled
0
Analog inputs 3 disabled
1
TABLE 21. IIC DETAIL SU20h-21 h(007-015)
007
Analog input disable 4AIND4
April 1994
FUNCTION
CONTROL BIT AIND4
Analog inputs 4 enabled
0
Analog inputs 4 disabled
1
3-158
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SAA7110
TABLE 21. lie DETAIL SU20h-21 h(007-015)
Subaddress 21 Analog control #2
015-008
Reference select channel 2 REFS2
008
FUNCTION
CONTROL BIT REFS2
Automatic clamping active
0
Reference level selected
1
Reference select channel 3 REFS3
009
FUNCTION
CONTROL BIT REFS3
Automatic clamping active
0
Reference level selected
1
Reference select channel 4 REFS4
010
FUNCTION
CONTROL BIT REFS4
Automatic clamping active
0
Reference level selected
1
MUXe select channel 24 MS24
011
FUNCTION
CONTROL BIT MS24
Analog MUX2 controlled by MX24
0
Analog MUX2 controlled by MUXe
1
Analog MUX2 control MX24
013-012
CONTROL BITS MX24(1 :0)
FUNCTION
MX241
MX240
ADDER mode
0
0
ch2 on, ch4 off
0
1
ch2 off, ch4 on
1
0
both off
1
1
MUXe select channel 34 MS34
014
FUNCTION
CONTROL BIT MS34
Analog MUX3 controlled by MX34
0
Analog MUX3 controlled by MUXe
1
Vertical blanking. control off VBeO
April 1994
015
FUNCTION
CONTROL BIT VBCO
vertical blanking on
0
vertical blanking off
1
3-159
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SAA7110
TABLE 22. IIC DETAIL SU22h-23h(016-031)
Subaddress 22 Mix control #1
023-016
Analog MUX3 control MX34
017-016
CONTROL BITS MX34(1 :0)
FUNCTION
MX341
. MX340
ADDER mode
0
0
ch3 on, ch4 off
0
1
ch3 off, ch4 on
1
0
both off
1
1
Clam p function test CLTS
018
FUNCTION
CONTROL BIT CLTS
normal clamp mode
0
CLAAn, CLAUn adjusted via CLL32 value
for testing (do not use)
1
Fast digital multiplexing channel 2/3 active MUYC
019
FUNCTION
CONTROL BIT MUYC
normal mode on CHR channel
0
multiplex mode on CHR channel
for test purpose only (do not use)
1
Luminance select YSEL
020
FUNCTION
CONTROL BIT YSEL
AD converter 2 -> CVBS
0
AD converter 3 -> CVBS
1
Chrominance select CSEL
021
FUNCTION
CONTROL BIT CSEL
AD converter 3 -> CHR
(MUXC not inverse (MUYC=1»
0
..
AD converter 2 -> CHR
(MUXC inverse (MUYC=1»
1
Automatic gain control GACa
023-022
CONTROL BITS GACO(1:0)
FUNCTION
GAC01
GACOO
automatic gain control off
0
0
automatic gain control channel 2
0
1
automatic gain control channel 3
1
0
automatic gain control channel 4
1
1
April 1994
3-160
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
TABLE 22. IIC DETAIL SU22h-23h(016-031)
031-024
Subaddress 23 Clamp level control 21 CLL21
DECIMAL CLAMP LEVEL
CONTROL BITS
CLL217 CLL216 CLL215 CLL214 CLL213 CLL212 CLL211
CLL210
1...
0
0
0
0
0
0
0
1
... 64 ...
a
1
0
0
0
0
0
... 128...
1
0
0
0
0
a
a
0
0
... 254
1
1
1
1
1
1
1
0
TABLE 23. IIC DETAIL SU24h-SU27h(032-063)
039-032
Subaddress 24 Clamp level control 22 CLL22
DECIMAL CLAMP LEVEL
CONTROL BITS
CLL227 CLL226 CLL225 CLL224 CLL223 CLL222 CLL221
1...
0
0
0
0
0
0
1
0
... 64 ...
0
1
0
0
0
0
0
... 128...
1
0
0
0
0
a
0
0
... 254
1
.1
1
1
1
1
1
0
Subaddress 25 Clamp level control 3.1 CLL31
DECIMAL CLAMP LEVEL
047-040
CONTROL BITS
CLL317 CLL316 CLL315 CLL314 CLL313 CLL312 CLL311
CLL310
1...
0
0
0
0
0
0
0
1
... 64 ...
0
1
0
0
0
0
0
0
... 128...
1
0
0
0
0
0
0
0
... 254
1
1
1
1
1
1
1
0
055-048
Subaddress 26 Clamp level control 32 CLL32
DECIMAL CLAMP LEVEL
April 1994
CLL220
0
CONTROL BITS
CLL327 CLL326 CLL325 CLL324 CLL323 CLL322 CLL321
CLL320
1...
0
0
0
0
0
0
0
1
... 64 ...
0
1
0
0
0
0
0
0
... 128...
1
0
0
0
0
0
0
0
... 254
1
1
1
1
1
1
1
0
3-161
Preliminary specification
Philips Semiconductors
One Chip Frontend 1 (OFC1)·
SAA7110
TABLE 23. lie DETAIL SU24h-SU27h(032-063)
Subaddress 27 Gain control analog #1
063-056
Static gain control channel 2 GAI2
DECIMAL MULTIPUER
GAIN
(STEP SIZE
dB)
061-056
CONTROL BITS
=0.19
GAI25
GAI24
GAI23
GAI22
GAI21
GAI20
0
0...
-2.82 dB
0
0
0
0
0
... 15...
o dB
0
0
1
1
1
1
... 31 ...
+3 dB
0
1
1
1
1
1
... 47 ...
+6dB
1
0
1
1
1
1
... 63
+9 dB
1
1
1
1
1
1
Gain mode select GASL
062
FUNCTION
CONTROL BIT GASL
difference value integration
0
fix value integration
1
Automatic gain control integration HOLD
063
FUNCTION
CONTROL BIT HOLD
AGe active
0
AGe integration hold (freeze)
1
TABLE 24. lie DETAIL SU28h-2Bh(064-093)
Subaddress 28 White peak control WIPE
071-064
CONTROL BITS
DECIMAL WHITE PEAK LEVEL
WIPE7
WIPE6
WIPES
WIPE4
WIPE3
WIPE2
WIPE1
128...
1
0
0
0
0
0
0
0
... 254
1
1
1
1
1
1
1
0
255 (White peak control off)
1
1
1
1
1
1
1
1
Subaddress 29 Sync bottom control SBOT
DECIMAL SYNC BOTTOM LEVEL
April 1994
WIPEO
079-072
CONTROL BITS
SBOT7
SBOT6
SBOTS
SBOT4
SBOT3
SBOT2
SBOT1
1...
0
0
0
0
0
0
0
1
... 254
1
1
1
1
1
1
1
0
3-162
SBOTO
Preliminary specification
Philips Semiconductors
One Chip Frontend 1 (OFC1)
TABLE 24.
SAA7110
lie DETAIL SU28h-2Bh(064-093)
Subaddress 2A Gain control analog #2
087-080
Static gain control channel 3 GAI3
085-080
GAIN
(STEP SIZE
0.19 dB)
DECIMAL MULTIPUER
CONTROL BITS
=
GAI35
GAI34
GAI33
GAI32
GAI31
GAI30
-2.82 dB
0
0
0
0
0
0
... 15...
o db
0
0
1
1
1
1
... 31 ...
+ 3 dB
0
1
1
1
1
1
... 47 ...
+6 dB
1
0
1
1
1
1
... 63
+9 dB
1
1
1
1
1
0 ...
Integration factor white peak IWIP
CONTROL BITS IWIP(1 :0)
FUNCTION
IWIP1
IWIPO
fast
0
0
I
I
0
1
1
0
slow
1
1
Subaddress 2B Gain control analog #3
095-088
Static gain control channel 4 GAI4
DECIMAL MULTIPUER
1
087-086
GAIN
(STEP SIZE
dB)
093-088
CONTROL BITS
=0.19
GAI45
GAI44
GAI43
GAI42
GAI41
GAI40
0
0...
-2.82 dB
0
0
0
0
0
... 15...
o db
0
0
1
1
1
1
... 31...
+ 3 dB
0
1
1
1
1
1
... 47 ...
+6 dB
1
0
1
1
1
1
... 63
+9 dB
1
1
1
1
1
1
TABLE 25. II C DETAI L SU2Bh-2Eh(094-119)
095-094
Integration factor normal gain IGAI
FUNCTION
April 1994
CONTROL BITS IGAI(1 :0)
IGAI1
IGAIO
slow
0
0
I
I
0
1
1
0
fast
1
1
3-163
Preliminary specification
Philips Semiconductors
One Chip Frontend 1 (OFC1)
SAA7110
TABLE 25. II C DETAI L SU2Bh-2Eh(094-119)
Subaddress 2C Mix control #2
103-096
Two's complement channel 21W02
096
FUNCTION
CONTROL BIT TW02
unipolar
0
two's complement (normal mode)
1
Two's complement channel 31W03
097
FUNCTION
CONTROL BIT TW03
unipolar
0
two's complement (normal mode)
1
Clamp level select channel 2 CLS2
100
FUNCTION
CONTROL BIT CLS2
CLL21 active
0
CLL22 active
1
Clamp level select channel 3 CLS3
101
FUNCTION
CONTROL BIT CLS3
CLL31 active
0
CLL32 active
1
Clamp level select channel 4 CLS4
103
FUNCTION
CONTROL BIT CLS4
CLL2n active
0
CLL3n active
1
Subaddress 2D Integration value gain IVAL
DECIMAL INTEGRATION VALUE GAIN
111-104
CONTROL BITS
IVAL7
IVAL6
IVAL5
IVAL4
IVAL3
IVAL2
IVAL1
IVALO
1...
0
0
0
0
0
0
0
1
... 255
1
1
1
1
1
1
1
1
Subaddress 2E Blank pulse VBLK-set VBPS
119-112
DECIMAL MULTIPLIER
SET
LINE NUMBER
step size = 2
VBPS7
VBPS6
VBPS5
VBPS4
VBPS3
VBPS2
VBPS1
VBPSO
CONTROL BITS
0...
o after "VS
0
0
0
0
0
0
0
0
... 131 ...
(max. for 60Hz)
262 after"VS
1
0
0
0
0
0
1
1
... 156
(max. for 50Hz)
312 after "VS
1
0
0
1
1
1
0
0
April 1994
3-164
Preliminary specification
Philips Semiconductors
One Chip Frontend 1 (OFC1)
SAA7110
TABLE 26. lie DETAil SU2Fh-31 h(120-143)
Subaddress 2F Blank pulse VBLK-reset VBPR
127-120
CONTROL BITS
DECIMAL MULTIPLiER
RESET LINE NUMBER
step size 2
VBPR7
VBPR6
VBPR5
VBPR4
VBPR3
VBPR2
VBPR1
VBPRO
0 ...
o after"VS
0
0
0
0
0
0
0
0
... 131...
(max. for 60Hz)
262 after "VS
1
0
0
0
0
0
1
1
... 156
(max. for 50Hz)
312 after "VS
1
0
0
1
1
1
0
0
=
Subaddress 30 ADCs gain control
135-128
Fix gain A/D converter channel 2 GAD2
FUNCTION
129-128
CONTROL BITS GAD2(1 :0)
GAD21
GAD20
0
o dB
0
0.05 dB
0
1
0.10dB
1
0
0.15dB
1
1
Gain AID select channel 2 GAS2
130
FUNCTION
CONTROL BIT GAS2
fix gain via lie GAD2
0
automatic gain via loop
1
Fix gain AID converter channel 3 GAD3
132-131
CONTROL BITS GAD3(1 :0)
FUNCTION
Gain
GAD31
GAD30
OdB
0
0
0.05 dB
0
1
0.10dB
1
0
0.15 dB
1
1
AID select channel 3 GAS3
133
FUNCTION
CONTROL BIT GAS3
fix gain via lie GAD3
0
automatic gain via loop
1
White peak mode select WISl
134
FUNCTION
CONTROL BIT WISL
difference value integration
0
fix value integration
1
143-136
Subaddress 31 Mix control #3
136
Pulses I/O control PULIO
April 1994
FUNCTION
CONTROL BIT PULIO
Hel, HSY -> input pins
0
Hel, HSY -> output pins
1
3-165
Preliminary specification
Philips Semiconductors
One Chip Frontend 1 (OFC1)
SAA7110
TABLE 27. IIC DETAILSU31h-33h(137-154)
Pin function switch VBLKA
137
FUNCTION
CONTROL BIT VBLKA
GPSW active (normal)
0
VBLK test output active
1
Analog filter control clock select AFCCS
138
FUNCTION
CONTROL BIT AFCCS
=
not divided (control clock LLC/2),
cut frequency approximate 10MHz
0
=
divided (control dock LLC/4),
cut frequency approximate. 5MHz
1
DMSD-SOP bypassed SOPB
139
FUNCTION
CONTROL BIT SQPB
DMSD-data to YUV output
0
AID-data to YUV output
for test purpose only (do not use)
1
White peak slow up integration enable WRSE
140
FUNCTION
CONTROL BIT WRSE
hold in white peak mode
0
slow up integration with one value in H or V
(dependent on WIRS)
1
White peak slow up integration select WIRS
141
FUNCTION
CONTROL BIT WIRS
slow up integration with one value per line
0
slow up integration with one value per field
1
Analog test select AOSL
143-142
CONTROL BITS AOSL(1 :0)
FUNCTION
-.
AOSL1
AOSLO
AOUT connected to ground
0
0
AOUT connected to input AD2
0
1
AOUT connected to input AD3
1
0
AOUT connected to channel 4
1
1
Subaddress 32 Integration value white peak IVAL
DECIMAL INTEGRATION VALUE
WHITE PEAK
1...
... 127 (max.)
April 1994
151-144
CONTROL BITS
WVAL7 WVAL6
WVALS WVAL4 WVAL3 WVAL2 WVAL1
WVALO
0
0
0
0
0
0
0
1
o .'
1
1
1
1
1
1
1
3-166
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
TABLE 27. IIC DETAIL SU31 h-33h(137-154)
Subaddress 33 Mix control #4
159-152
Clock select AD2 CAD2
154
FUNCTION
CONTROL BIT CAD2
LLC
for test purpose only (do not use)
0
LLC/2
1
TABLE 28. IIC DETAIL SU33h-34h(155-167)
Clock select AD3 CAD3
155
FUNCTION
CONTROL BIT CAD3
LLC
for test purpose only (do not use)
0
LLC/2
1
Change sign bit UV data CHSB
157
FUNCTION
CONTROL BIT CHSB
UV output unipolar
0
UV output two's complement
1
Output format select OFTS
159
FUNCTION
CONTROL BIT OFTS
4:1:1 format
0
4:2:2 format
1
Subaddress 34 Gain update level
167-160
Gain update level GUDL
165-160
DECIMAL
update
HYSTERESIS
for 8bit gain
I new gain - old
gain
CONTROL BITS GUDL(5:0)
1=
GUDL5
GUDL4
GUDL3
GUDL2
GUDL1
GUDLO
0
0...
OLSB
>0
0
0
0
0
0
... 7 ...
+/- 7 LSB
>7
0
0
0
1
1
1
>31
OFF
always
1
X
X
X
X
X
167-166
MUXC phase delay MUD2(1)
FUNCTION
CONTROL BITS
MUD2
MUD1
no phase delay
0
0
1 LLC cycle phase delay for CLAA path
0
1
2 LLC cycle phase delay for CLAA path
1
0
3 LLC cycle phase delay for CLAA path
1
1
April 1994
3-167
Preliminary specification
Philips Semiconductors
One Chip Frontend 1 (OFC1)
SAA7110
19.2 SOURCE SELECTION MANAGEMENT
FIGURE 20. SOURCE SELECTION OVERVIEW
~-"""CHROMA
REF128
GAI4
GAI3
GAI2
HT1093
GACa
All switch control bits set to LOW in this sheet!
TABLE 29. SOURCE SELECTION MANAGEMENT example table
INPUT
April 1994
EXAMPLE1
EXAMPLE2
EXAMPLE3
SIGNAL
MODE
SIGNAL
MODE
SIGNAL
MODE
AIN21
CVBS1
0
CVBS1
0
Y1
6
AIN22
CVBS2
1
C2
AIN31
CVBS3
2
Y2
AIN32
CVBS4
3
C3
AIN41
CVBS5
4
Y3
AIN42
CVBS6
5
CVBS6
7
8
5
C2
Y2
C3
Y3
C1
7
8
6
EXAMPLE4
SIGNAL
MODE
Y1
6
CVBS2
1
CVBS3
2
CVBS4
3
CVBS5
4
C1
6
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SAA7110
TABLE 30. SOURCE SELECTION MANAGEMENT example sheets
AI41 -
A141-
AI42 AI31 AI32 AI21
AI42 CHROMA
CHROMA
AI31 A132-
~.....--~ LUMA
AI22 -
;::LL__,,-.....--+
LUMA
AI22
MODE 0 - CVBS1
MODE 1 - CVBS2
AI41 AI31
CHROMA
CHROMA
~.....--~ LUMA
MODE 2 - CVBS3
AI31 AI32 AI21 -
LUMA
MODE 3 - CVBS4
CHROMA
CHROMA
LUMA
LUMA
AI22 -
MODE 4 - CVBS5
MODE 5 - CVBS6
A141-
A141-
AI42
AI21
CHROMA
CHROMA
LUMA
LUMA
AI22
MODE 6 - Y1 + C1
MODE 7 - Y2 +C2
AI41
CHROMA
LUMA
MODE 8 - Y3 + C3
April 1994
3-169
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
TABLE 31. SOURCE SELECTION MANAGEMENT IIC control
MODE
0
1
2
3
4
5
6
7
8
AIND4
1
1
1
1
0
0
0
1
0
AIND3
1
1
0
0
1
1
1
0
0
AIND2
0
0
1
1
1
1
0
0
1
FUSE1
FUSEO
1
1
AINS4
X
X
X
X
1
0
0
X
1
AINS3
X
X
1
0
X
X
0
1
0
0
X
X
X
X
1
0
X
AINS2
1
VBCO
0
MS34
0
MX241
0
0
X
X
X
X
0
0
1
MX240
1
1
X
X
X
X
1
1
0
MS24
0
REFS4
1
1
1
1
0
0
0
1
0
REFS3
1
1
0
0
1
1
1
0
0
REFS2
0
0
1
1
1
1
0
0
1
GAC01
GACOO
0
1
0
1
1
0
1
0
1
1
1
1
0
1
1
0
1
1
9
CSEL
X
X
X
X
X
X
0
1
0
YSEL
0
0
1
1
1
1
0
1
0
MUYC
0
0
CLTS
0
0
MX341
X
X
0
0
1
1
1
0
MX340 c
X
X
1
1
0
0
0
1
1
CLS4
X
X
X
X
1
1
1
X
0
0
GABL
0
CLS3
X
X
0
0
0
0
1
0
1
CLS2
0
0
X
X
X
X
0
1
X
4 LSB
0011
BYPS
0
0
0
0
0
0
1
1
1
SU20h
D9h
D8h
BAh
B8h
7Ch
78h
59h
9Ah
3Ch
SU21h
16h
16h
05h
05h
03h
03h
12h
14h
21h
SU22h
40h
40h
91h
91h
D2h
D2h
42h
B1h
C1h
SU2Ch
03h
03h
03h
03h
83h
83h
A3h
13h
23h
SU06h
SU30h*
0011
OXXXXXXX
44h
44h
1XXXXXXX
60h
60h
60h
60h
44h
60h
44h
Note: CLL21 =65d, CLL22=128d, CLL31 =65d, CLL32=128d, GA14=15d, GA13=15d, GAI2=15d; X set to 0
*Optional: values for AD-gain (+2LSB's gain resolution) active [not active: for all modes 40h]
April 1994
3-170
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
19.3 ANTI-ALIAS FILTER CURVE
FIGURE 21. ANTI-ALIAS FILTER CURVE
a(50Hz, AFCCS=O)
b(50Hz, AFCCS=1) LLC=29.50MHz
c(60Hz, AFCCS=O)
d(60Hz, AFCCS=1) LLC=24.54MHz
NdB
3.0
0.0
\\
\ ~ ""~
\ f\.
\ \
\ \
\
1\ ' \
\ \
\ '\.
\ \
\
\ \
\.
\ \
\
t\c
d\ \ b
I\.
\ i\
\.
~
'\.
\ \
\ \
\
\
\
\
-3.0
-6.0
-9.0
-12.0
",
-15.0
-18.0
.'",a
-21.0
-24.0
-27.0
-30.0
-33.0
-36.0
-39.0
0.0
10.0M
5.0M
20.0M
"
~
25.0M
15.0M
30.OM
FREQ/Hz
19.4 CORING FUNCTION
TABLE 32. CORING
+64
+48
+32
+16
a(
0
-32
-64
V
C9
April 1994
V
CORI1
l)a
-16
-48
~
V
Coring function adjustment by subadress 06h to affeet the bandfilter output signal. The thresholds are
related to the 13-bit word width in the luminance processing part and influence the 1LSB to the 3LSB (YO
to Y2) with respect to the 8-bit luminance output.
Vc
co
"'!"
~
C\J
C?
CD
0
CD
+
C\J
C'?
+
co
-.:t
+
Cb
+
3-171
CORIO
a
0
1
b
1
0
c
1
1
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
19.5 LUMINANCE FILTER CURVES
TABLE 33. LUMINANCE FILTER CURVES
Luminance control SU06h, 50HZ/CVBS mode, prefilter on, coring off
18~--------~-----------r----------'---------~
12r-----~~~~~~~~_r----------i_--------__i
6~--~~~~--~~----~----------~--------~
0
!Xl
:g.
~
-6
-12
50Hz
-18
-24
-30
0
4
2
6
8
fY(MHz)
Luminance control SU06h, 50Hz/CVBS mode, prefilter on, coring off
18~--------~-----------r----------'---------~
12r---------~--~~~--_r----------~--------~
-12
I------------+----------_r........,.------~.;;;.;...------~
-18
r---------~----------_r
-24
I-----------f-----------+-I:I-------+-----------I
____
------~--------~
-~ ~--~----~----~----~~~~----~----~--~
o
4
2
fY(MHz)
April 1994
3-172
6
8
Preliminary specification
Philips Semiconductors
One Chip Frontend 1 (OFC1)
SAA7110
TABLE 33. LUMINANCE FILTER CURVES
Luminance control SU06h, 50Hz/CVBS mode, prefilter off, coring off
18.------.-------.-------..,.-------,
12r----~~~~~~--r------+-------i
-12~-----~~---~+_~__~~-~~---~
-18~-----+_-----~~~---~~---~
-24 I - - - - - - - o f - - - - - - + - - l
-30
L . . . - - - r - - - . L - - - . - -_ _.L-..aII:--.--_ _"'--_ _..,.-_---J
o
2
8
6
fY(MHz)
Luminance control SU06h, 50Hz/Y+C mode, prefilter off, coring off
18
12
----
6
0
co
::!..
~
83h
82h
81h
80h
-6
-12
50Hz
-18
-24
-30
o
4
fY(MHz)
April 1994
3-173
6
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
TABLE 33. LUMINANCE FILTER CURVES
Luminance control SU06h, 50HZ/Y+C mode, prefilter on, coring off
18~--------~----------~-----------r--------~
6~----~~~~~-------+--------~~~~----~
0
1il
:g,
~
-6
-12
50Hz
-18
-24
-30
0
2
4
fY(MHz)
Luminance control SU06h, 60Hz/CVBS mode, prefilter on, coring off
18~----~------~------~-------r------~----~
12j_-----t~~~t:==~dr------j_----_r----_j
-12r-----~~----~------_+--~rlH~------_r~~~
-18 I--------lf-------f-------+--......I
-24~----~f-----_4------_+--~
___+------~----~
-30~~~~~~--~--~--~--~--~---r--~--~~
o
2
3
fY(MHz)
April 1994
3-174
5
6
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SAA7110
TABLE 33. LUMINANCE FILTER CURVES
Luminance control SU06h, 6OHz/CVBS mode, prefilter on, coring off
18
12
~
6
~
o
~
-
-~~
I/"
....
~ ~ JV::::::: ~
~I" - ~
~, rJ/
~
H~
U~
~
-12
60Hz
-18
-24
-~
fY(MHz)
Luminance control SU06h, 60Hz/CVBS mode, prefilter off, coring off
18~----~------~----~-------r------r-----~
12r-----~~~~~~--t_----_r----~r_--__i
6r-~~~~~-=~--~~------_r------r_----_;
-12~-----+------+------4~-4~~~----T=~--~
-18~-----+------+------4--~~~------~~--~
....._+_------+_----__1
-24 1-------+------+-------4--~
-~~~--~---r--~--r-~--~~~--~--~~r-~
o
3
2
fY(MHz)
April 1994
3-175
4
5
6
Rhilips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SAA7110
TABLE 33. LUMINANCE FILTER CURVES
Luminance control SU06h, 60Hz/Y+C mode, prefilter off, coring off
18
12
.
-
6
0
~
---.::::::
i~~
CD
~
~
-6
-12
50Hz
"
-18
-24
-30
o
2
4
6
8
fY(MHz)
Luminance control SU06h, 60Hz/Y+C mode, prefilter on, coring off
18~---------'----------~-----------r--------~
12r-----~~~. .~~~----~------~
0
CD
~
~
-6
-12
50Hz
-18
-24
-30
0
2
6
fY(MHz)
April 1994
3-176
8
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
20.
lie START SETUP
The following values are optimized for the EBU colour bar (100% white and 75% chrominance amplitude) input signal. The
decoder output signal level fulfills the CCIR Rec.601 specification. The input of 100% color bar level is possible, but the signal
(white) peak function reduces the digital luminance output. With another setup it is possible to proceed 100% color bar signal
without luminance amplitude reduction. The way is to modify the AD input range for this input level by reducing the gain
reference value (SBOT > 06h) and adjusting the digital Y output level with contrast and brightness control.
. TABLE 34. IIC START SETUP
NAME
SUB
FUNCTION
(hex)
VALUES(bin)
7
6
5
4
3
2
1
0
start
0
0
1
1
0
0
4C
00
IOEL(7:0)
Increment delay
0
1
01
HSYB(7:0)
Horizontal sync HSY begin 50Hz
0
0
1
1
1
1
0
0
3C
02
HSYS(7:0)
Horizontal sync HSY stop 50Hz
0
0
0
0
1
1
0
1
00
03
HCLB(,7:0)
Horizontal clamp HCL begin 50Hz
1
1
1
0
1
1
1
1
EF
04
HCLS(7:0)
Horizontal clamp HCL stop 50Hz
1
0
1
1
1
1
0
1
BO
05
HPHI(7:0)
Horizontal sync after PHI1 50Hz
1
1
1
1
0
0
0
0
FO
06
BYPS, PREF, BPSS(1 :0),
BFBY, CORI(1 :0), APER(1 :0)
Luminance control
0
0
0
0
0
0
0
0
00
07
HUEC(7:0)
Hue control
0
0
0
0
0
0
0
0
00
08
CKTQ(4:0), XXX
Colour killer threshold PAL
1
1
1
1
1
X
X
X
F8
09
CKTS(4:0), XXX
Colour killer threshold SECAM
1
1
1
1
1
X
X
X
F8
OA
PLSE(7:0)
PAL switch sensitivity
0
1
1
0
0
0
0
0
60
OB
SESE(7:0)
SECAM switch sensitivity
0
1
1
0
0
0
0
0
60
OC
COLO, LFIS(1 :0), XXXXX
Gain control chrom inance
0
0
0
X X
X
X
X
00
OD
VTRC, XXX, RTSE, HRMV,
SSTB,SECS
Standard/Mode control
0
X
X
X
0
1
1
0
06
OE
HPLL, XX, OEHV, OEYC,
CHRS, X, GPSW
I/O and clock control
0
X
X
1
1
0
X
0
18
OF
AUFO, FSEL, SXCR, SCEN,
X, YOEL(2:0)
Control #1
1
0
0
1 X
0
0
0
90
10
XXXXX, HRFS, VNOI (1 :0)
Control #2
X
X
X
X X
0
0
0
00
0
1
0
1
0
0
1
59
2C
IPAL
Chroma gain reference
1
11
CHCV(7:0)
0
0
1
0
1
1
0
0
12
SATN(7:0)
Chroma saturation
0
1
0
0
0
0
0
0
40
13
CONT(7:0)
Luminance contrast
0
1
0
0
0
1
1
0
46
14
HS6B(7:0)
Horizontal sync HSY begin 60Hz
0
1
0
0
0
0
1
0
42
15
HS6S(7:0)
Horizontal sync HSY stop 60Hz
0
0
0
1
1
0
1
0
1A
16
HC6B(7:0)
Horizontal clamp HCL begin 60Hz
1
1
1
1
1
1
1
1
FF
17
HC6S(7:0)
Horizontal clamp HCL stop 60Hz
1
1
0
1
1
0
1
0
DA
18
HP61(7:0)
Horizontal sync after PHI1 60Hz
1
1
1
1
0
0
0
0
FO
19
BRIG(7:0)
Luminance brightness
1
0
0
0
1
0
1
1
8B
INTSC
1A-1F reserved
April 1994
3-177
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SAA7110
TABLE 34. IIC START SETUP
20
AIND4, AIND3, AIND2,
FUSE(1 :0), AINS4, AINS3,
AINS2
Analog control #1
1
1
0
1
1
0
0
1
D9
21
VBCO, MS34, MX24(1 :0),
MS24, REFS4, REFS3,
REFS2
Analog control #2
0
0
0
1
0
1
1
0
16
22
GACO(1 :0), CSEL, YSEL,
MUYC, CLTS, MX34(1 :0)
Mix control #1
0
1
0
0
0
0
0
0
40
23
CLL21 (7:0)
Clamp level control channel 2 1
0
1
0
0
0
0
0
1
41
24
CLL22(7:0)
Clamp level control channel 2 2
1
0
0
0
0
0
0
0
80
25
CLL31 (7:0)
Clamp level control channel 31
0
1
0
0
0
0
0
1
41
26
CLL32(7:0)
Clam p level control channel 3 2
1
0
0
0
0
0
0
0
80
27
HOLD, GASL, GAI2(5:0)
Gain control analog #1
0
1
0
0
1
1
1
1
4F
28
WIPE(7:0)
White peak control
1
1
1
1
1
1
1
0
FE
29
SBOT(7:0)
Sync bottom control
0
0
0
0
0
0
0
1
01
2A
IWIP(1 :0), GAI3(5:0)
Gain control analog #2
1
1
0
0
1
1
1
1
CF
2B
IGAI(1 :0), GAI4(5:0)
Gain control analog #3
0
0
0
0
1
1
1
1
OF
2C
CLS4,X,CLS3,CLS2,XX,
TW03, TW02
Mix control #2
0
X
0
0
X
X
1
1
03
2D
IVAL(7:0)
Integration value gain
0
0
0
0
0
0
0
1
01
1
0
0
1
1
0
1
0
9A
1
0
0
0
0
0
0
1
81
0
0
0
0
0
0
1
1
03
0
0
0
0
0
0
1
1
03
2E
VBPS(7:0)
50Hz
60Hz
50Hz
Vertical blanking pulse SET
2F
VBPR(7:0)
30
X, WISL, GAS3, GAD3(1 :0),
GAS2, GAD2(1 :0)
ADCs gain control
X
1
0
0
0
0
0
0
44
31
AOSL(1 :0), WIRS, WRSE,
SOPB, AFCCS, VBLKA,
PULIO
Mix control #3
0
1
1
1
0
1
0
1
75
32
WVAL(7:0)
Integration value white peak
0
0
0
0
0
0
1
0
02
33
OFTS, X, CHSB, X, CAD2,
CAD3, XX
Mix control #4
1
X
0
X
1
1
X
X
8C
34
MUD2, MUD1, GUDL(5:0)
Gain update level
0
0
0
0
0
0
1
1
03
60Hz
Vertical blanking pulse RESET
Note: Values recommended for a CVBS (PAL or NTSC) signal, input AI21 via ND channel 2 (MODE 0), and
4:2:2 CCIR output signal level; all X values must be set to LOW; HPHI and HP61 -> application dependent.
April 1994
3-178
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
21. APPLICATION SHEET
FIGURE 22. OCF1 APPLICATION SHEET
VDDC>----------------------~1_~~
100n
C15
VDDAC>------------~~_+~
100n
100n
C10
C14
I---t--t-t---.
100n
C13
\ISS
A142~6
Rs
75
10n
AI42
VSSA
A141~5
R5
Y7 ~:~:...;~~£>Y(7:0)
Y6
Y5
Y4
Y3
Y2 53 1
Y1 54 0
YO
O(\lC')v
11
10n 13
««««
0000
0000
»»
AI41
75
VSSA
AI32
~
R4175
A131~3
R3
10n
15 AI32
55
10n
17
AI31
10n
19
AI22
10n 21
AI21
75
VSSA
AI22
~2
R2
SAA7110
OCF1
75
VSSA
AI21
~1
R1
75
VSSA
VDD
SCL
SDA
FEIN(MUXC)
RS
~----'~----=~
63
CGCE
SCL
SOA
FEIN(MUXC)
42
29
LLC 30
LLC2 31
CREF 32
RESN 26
LFCO
r--~~_6-t5 XTAL
«
C\I C') HCL
a.. a.. ~ ~ ~ HSY
~~~~~~ g«CI) a: a: a:
Note: Unused analog inputs should be not connected!
April 1994
3-179
T""
(f)
UV(7:0)
HREF 38
HREF
HS 1-4-1 ---t:::>HS
VS 3
VS
RTCO 23
RTCO
AOUT 64
AOUT
GPSW(V8LK) 39
GPSW(VBLK)
PUN(HL) 40
PLlN(HL)
ODO(VL)
ODD(VL)
\ISS
(f) T"" C\I C') V LO
(f) (f) (f) (f) (f) (f)
7
UV7 56 6
UV6 57 5
UV5 58 4
UV4
UV3
UV2
UV1
UVO
36
37
LLC
LLC2
CREF
RESN
LFCO
HCL
SY
H
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SAA7110
21.1 APPLICATION WITH EXTERNAL CGC
FIGURE 23. APPLICATION WITH EXTERNAL CGC
63
FEIN(MUXC)
40
ODD(VL) I - - - - - - { : : > ODD(VL)
FEIN(MUXC)
30
33
CGCE
65
XTAL
66
XTALI
~~~~
CI)CI)CI)CI)
C17
C18
LLC2
29
LLC 31
CREF 32
RESN 26
LFCO
SAA7110
OCF1
~~~~ ~~~~~~
36
t---+-........--+-c> HCL
Cl)T""C\lC')vLO «
CI)CI)CI)CI)CI)CI)
~Q.Q.
=«CI)
C\I C') HCL
37
00
W
f3 f3 HSY I--+-........--+-c> HSY
a: a: a:
~OP
n.c.
lV$
..-........---t:::>RESN
CREF
VDDAC>--------------~----------------~
VDDC>--------~----~------_.------~
C22
C21
0«
00
R10
C\lOZu.«
OU(f)~U
>~ CGC ~~~U~
1k
10an
100n
2
~~
SAA7197
0 «
rr.
gco g~ gre
16 LFCOSEL
2
CI)
CI)
~ ~
....J....J....J
LLC2B
LLC2A
I...------c> LLCB
The OCF1 supports for special applications the use of an external Clock Generator Circuit (CGC, SAA7197). For normal
operation the build in CGC fulfills all requirements.
April 1994
3-180
Preliminary specification
Philips Semiconductors
SAA7110
One Chip Frontend 1 (OFC1)
22. STARTUP, SOURCE SELECT AND STANDARD DETECTION FLOW EXAMPLE
FIGURE 24. SOFlWARE FLOW EXAMPLE
without standard routine
I......··········.. ···....··············..·....·.. ··············........
yes=XXOXXXOO
yes=XXIXXXOO
yes=XXIXXXXX
yes=XXOXXXOl
April 1994
3-181
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
MODE 0 STARTUP and STANDARD Procedure
SLAVE %78
IOCF1 NTSC-setup
SUB 00 WRITE
4C 3C 00 EF BD FO 00 00
F8 F8 60 60 00 06 18 90
00 2C 40 46 42 1A FF DA
FO 8B 00 00 00 00 00 00
09 17 40 41 80 41 80 4F
FE 01 CF OF 03 01 81 03
44 75 01 8C 03
SUB 21 WRITE 16
I REFS OFF CLAMP AKTIV
READ 1
#STANDARD
IF l@XXOXXXOO
THEN GOTO BW 50Hz
ENDIF
IF 1 @XX1XXXOO
THEN GOTO BW 60Hz
ENDIF
SUB 06 WRITE 00
ENDIF
IF 1 @XX1XXXXX
THEN GOTO NTSC
ENDIF
IF 1 @XXOXXXXX
THEN GOTO PAL
ENDIF
IStatus?
SAA7110
THEN GOTO SECAM
ELSE PRINT "PAL"
GOTO STOP
#SECAM
SUB 00 WRITE 07
PRINT "SECAM"
GOTO STOP
#STOP
MODE 0 Source Select Procedure
SLAVE %78
SUB 06 WRITE
SUB 20 WRITE
SUB 21 WRITE
SUB 22 WRITE
SUB 2C WRITE
SUB 30 WRITE
SUB 31 WRITE
INO COLOR
INO COLOR
!60Hz
April 1994
IOCF1
ICVBS MODE 0
IAI21 ACTIVE
IREFS ON
IAD2->LUMA and CHROMA
ICLAMP SELECT
IGain AD2 active
lAOSL -> 01b
SUB 21 WRITE 16
I REFS OFF CLAMP AKTIV
SLAVE %78
SUB 06 WRITE
SUB 20 WRITE
SUB 21 WRITE
SUB 22 WRITE
SUB 2C WRITE
SUB 30, WRITE
SUB 31 WRITE
150HZ
#BW 60Hz
PRINT "BLACK&WHITE"
SUB 06 WRITE 80
SUB 2E WRITE 81
IVBPS
GOTO STOP
#PAL
SUB 00 WRITE 06
SUB 11 WRITE 59
SUB 2E WRITE 9A
PAUSE %150
IF 1 @XXOXXXOI
00
09
17
40
03
44
75
MODE, I Source Select Procedure
#BW 50Hz
'PRINT "BLACK&WHITE"
SUB 06 WRITE 80
SUB 2E WRITE 9A
IVBPS
GOTO STOP
#NTSC
SUB 00 WRITE 06
SUB 11 WRITE 2C
SUB 2E WRITE 81
PRINT "NTSC"
GOTO STOP
ISECS -> 1
00
08
17
40
03
44
75
10CF1
lCVBS MODE 1
IAI22 ACTIVE
lREFS ON
IAD2->LUMA and CHROMA
ICLAMP SELECT
IGain AD2 active
!AOSL -> 01b
SUB 21 WRITE 16
I REFS OFF CLAMP AKTIV
MODE 2 Source Select Procedure
SLAVE %78
SUB .06 WRITE
SUB 20 WRITE
SUB 21 WRITE
SUB 22 WRITE
SUB 2C WRITE
SUB 30 WRITE
SUB 31 WRITE
ISECS -> 0
ICHCV
IVBPS
00
BA
07
91
03
60
B5
10CF1
!CVBS MODE 2
lAI31 ACTIVE
IREFS'ON
IAD3->LUMA and CHROMA
lCLAMP SELECT
IGain AD3 active
1AOSL -> lOb
SUB 21 WRITE 05
1REFS OFF CLAMP AKTIV
MODE 3 Source Select Procedure
SLAVE %78
SUB 06 WRITE
SUB 20 WRITE
SUB 21 WRITE
SUB 22 WRITE
SUB 2C WRITE
SUB 30 WRITE
ISECS -> 0
ICHCV
!VBPS
I 150ms
3-182
00
B8
07
91
03
60
10CF1
lCVBS MODE 3
lAI32 ACTIVE
!REFS ON
IAD3->LUMA and CHROMA
ICLAMP SELECT
IGain AD3 active
Philips Semiconductors
Preliminary specification
One Chip Frontend 1 (OFC1)
SUB 31 WRITE B5
lAOSL -> lOb
SUB 21 WRITE 05
!REFS OFF CLAMP AKTIV
SAA7110
SUB
SUB
SUB
SUB
SUB
MODE 4 Source Select Procedure
SLAVE %78
SUB 06 WRITE
SUB 20 WRITE
SUB 21 WRITE
SUB 22 WRITE
SUB 2C WRITE
SUB 30 WRITE
SUB 31 WRITE
00
7C
07
D2
83
60
B5
lOCF1
!CVBS MODE 4
!AI41 ACTIVE
!REFS ON
!AD3->LUMA and CHROMA
!CLAMP SELECT
!Gain AD3 active
!AOSL -> lOb
SUB 21 WRITE 03
!REFS OFF CLAMP AKTIV
00
78
07
D2
83
60
B5
!OCF1
!CVBS MODE 5
!AI41 ACTIVE
!REFS ON
!AD3->LUMA and CHROMA
!CLAMP SELECT
lGain AD3 active
lAOSL -> lOb
SUB 21 WRITE 03
IREFS OFF CLAMP AKTIV
Space for notes:
MODE 6 Source Select Procedure
SLAVE %78
SUB 06 WRITE
SUB 20 WRITE
SUB 21 WRITE
SUB 22 WRITE
SUB 2C WRITE
SUB 30 WRITE
SUB 31 WRITE
80
59
17
42
A3
44
75
SUB 21 WRITE 12
lOCF1
lY+C MODE 6
lAI21=Y, AI42=C
IREFS ON
!AD2->LUMA, AD3->CHR
!CLAMP SELECT
!Gain AD2 active
lAOSL -> 01
!REFS OFF CLAMP AKTIV
MODE 7 Source Select procedure
SLAVE %78
SUB 06 WRITE
SUB 20 WRITE
SUB 21 WRITE
SUB 22 WRITE
SUB 2C WRITE
SUB 30 WRITE
SUB 31 WRITE
80
9A
17
B1
13
60
B5
SUB 21 WRITE 14
!OCF1
lY+C MODE 7
lAI31=Y, AI22=C
!REFS ON
!AD3->LUMA, AD2->CHR
!CLAMP SELECT
!Gain AD3 active
!AOSL -> lOb
lREFS OFF CLAMP AKTIV
MODE 8 Source Select Procedure
SLAVE %78
SUB 06 WRITE 80
SUB 20 WRITE 3C
April 1994
WRITE
WRITE
WRITE
WRITE
WRITE
27
C1
23
44
75
SUB 21 WRITE 21
MODE 5 Source Select Procedure
SLAVE %78
SUB 06 WRITE
SUB 20 WRITE
SUB 21 WRITE
SUB 22 WRITE
SUB 2C WRITE
SUB 30 WRITE
SUB 31 WRITE
21
22
2C
30
31
OCF1
Y+C MODE 8
AI41=Y, AI32=C
3-183
lREFS ON
!AD2->LUMA, AD3->CHR
!CLAMP SELECT
!Gain AD2 active
!AOSL -> 01
lREFS OFF CLAMP AKTIV
Philips Semiconductors Desktop Video Products
SAA7110 programming example
SAA7110 PROGRAMMING EXAMPLE
Slave address is .9C (IICSA=O) or .9E (IICSA=1)
FUNCTION
SUBADDRS
DATA
00
01
02
03
04
05
06
07
08
09
4C
3F
OD
EF
BD
FO
01
02
F8
F8
Increment Delay
Begin HSY (50Hz)
End HSY (50Hz)
Begin HCL (50Hz)
End HCL (50Hz)
Horizontal Sync after PHI1 (50Hz)
Luminance Control
Hue Control
QUAM Color Killer Threshold
SECAM Color Killer Threshold
OA
OB
OC
00
OE
OF
10
11
12
13
90
90
00
86
18
BO
00
59
40
55
PAL Sensitivity Switch
SECAM Sensitivity Switch
AGC Loop Time Constant Control/Color Killer ON/OFF (MSB)
Standard/Mode Control
I/O and Clock Control
Control #1
Control #2
Chroma Gain Reference
Chroma Saturation
Luminance Contrast
14
15
16
17
18
19
1A
1B
1C
10
42
1A
FC
D3
E2
AA
00
00
00
00
Begin HSY (60Hz)
End HSY (60Hz)
Begin HCL (60Hz)
End HCL (60Hz)
Horizontal Sync after PHI1 (60Hz)
Luminance Brightness
Reserved
Reserved
Reserved
Reserved
1E
1F
20
21
22
23
24
25
26
27
00
00
7A
23
C1
40
80
40
80
41
Reserved
Reserved
Analog Control #1
Analog Control #2
Mix Control #1
Clamp Level Control
Clamp Level Control
Clamp Level Control
Clamp Level Control
Gain Control #1
28
29
2A
2B
2C
20
2E
2F
30
31
32
FE
01
C5
OF
23
01
9A
03
40
75
02
White Peak Control
Sync Bottom Control
Gain Control #2
Gain Control #3
Mix Control #2
Integration Value Gain
Vertical Blank Pulse SET
Vertical Blank Pulse RESET
ADC Gain Control
Mix Control #3
Integration Value White Peak
33
34
8C
03
Mix Control #4
Gain Up-date Level
April 1994
21
22
31
32
3-184
Preliminary specification
Philips Semiconductors Desktop Video Products
SAA7116
Digital video to PCI interface
GENERAL DESCRIPTION
FEATURES
• 1024 byte FIFO memory size
• Full multistandard video input capability
(with Philips Video Decoder Chipset)
• Programmable minimum burst transfer size
• Image resolution up to 768 x 576 (full PAL
or SECAM resolution)
• Data formats:
- RGB 15 packed
- RGB 24 packed
- YUV 16 packed; CCIR 6014:2:2
- YUV 9 planar; Indeo® DVI compatible
- YUV 12 planar
- YUV 16 planar
• Even and odd fields can be sent to
independent destinations
• Zero wait state PCI burst writes
• Field rate sent to target can be throttled
(field masking)
• 160-pin plastic quad flat pack
• Power consumption approximately
1.0 Watt
APPLICATIONS
• Capture Chipset:
- SAA7151B (CCIRdecoder)
- SAA7191B (square pixel decoder)
- SAA7196
(square pixel decoder
with scaler and clock)
(one chip decoder)
- SAA7110
- SAA7186
(digital video scaler)
• Real-time video capture to graphics RAM
and/or CPU RAM
The SAA7116 is a video capture IC that
serves as an interface between the Philips
video capture chipset and the PCI bus. The
digitized video which can incorporate filtering,
scaling and translation is presented to the IC
in one of three formats: RGB 5:5:5, YUV
4:2:2, or RGB 8:8:8. The SAA7116 contains
FIFOs to decouple the real time video data
stream from the PCI bus and provides DMA
channels to deliver th~ video d~ta in packed
format (I.e., for local display) and in planar
format (I.e., for compression). The SAA7116
is both a PCI bus master and slave. It
operates in master mode to transfer video
data across the PCI bus and operates in
slave mode to program local registers.
• PCI multi-media designs
• Feed video to all relevant PC destinations
(frame buffers and SW/HW codecs)
ORDERING INFORMATION
PACKAGE
EXTENDED
TYPE NUMBER
PINS
SAA7116H
160
I
PIN POSITION
I
I
I
QFP
I
I
MATERIAL
Plastic
CODE
SOT225
BLOCK DIAGRAM
VRO[31..0]
FIFO
LNO
PXO
VGT
HGT
OlE
VCLK
SCL
SDA
-
--
FIFO
INPUT
CONTROL
-
FIFO
OUTPUT
CONTROL
f-----
REO
I---
GNT
MASTER
LOGIC
f-
MASTER
LATENCY
TIMER
~
~
ADDRESS
GENERATOR
12C
INTERFACE
~
FRAM E
TRDY
IRDY
STOP
DEVS EL
~
AD[31 . .01
-
ADDRI
DATA
MUX
CIBE[3 .. 0]
L....--
Q;
I
PAR.
PARITY
I+-SLAVE LOGIC
LOCAL REGISTERS
CONFIGURATION. REGISTERS
IDSEL
I---
5l
®Indeo is a regislered trademark of Intel Corporation.
June 1994
-
~
3-185
Preliminary specification
Philips 5emiconductors Desktop Video Products
.SAA7116
Digital. vioeo to PCI interface
PIN CONFIGURATION
160
121
H
R
,
/-.
1
=0
40=
F=
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
120
QUAD
FI.AT
pACK
,
,/
H
H
41
80
F=
81
34
NOTE:
35
36
37
38
39
40
# means Active LOW
Function
Vee
Vee
NC
NC
NC
NC
VCLK
Vee
VRSTN
GND
GND
SCL
SDA
NC
Vee
INn
PRSn
PCLK
GNn
Vee
GND
GND
REO.
AD31
Vee
AD30
GND
AD29
AD28
Vee
AD27
GND
AD26
AD25
Vee
AD24
GND
CBE3.
IDSEL
Vee
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
7S
77
78
79
80
Function
GND
AD23
Vee
AD22
GND
AD21
AD20
Vee
AD19
GND
AD18
AD17
Vee
AD16
GND
CBE2.
FRAME.
Vee
GND
GND
Vee
IRDY.
TROY.
Vee
GND
Vee
DEVSEL.
STOP.
GND
NC
Vee
. NC
PAR
GND
CBE1.
Vee
AD15
AD14
GND
GND
Pin
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Function
Vee
AD13
Vee
AD12
ADll
GND
AD10
Vee
AD9
AD8
GND
CBEO#
Vee
AD7
AD6
GND
AD5
Vee
Vee
AD4
AD3
GND
GND
AD2
Vee
ADl
ADO
GND
GND
INT]INO
INT_PINl
INT_PIN2
Vee
NC
NC
NC
TN
PO
Vee
Vee
Pin
12'1
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
PIN DESCRIPTIONS
5YMBOL3
PIN
NUMBER
51GNAL TYPE
INPUTI
OUTPUT
TYPE2
DESCRIPTION
'5IGNAL
DIRECTION
PCI Address and Data Pins
ADO
107
3-5tate
I/O
Address and Data are multiplexed on the same PCI pins.
bit 0
AD1
106
3-5tate
1/0
Address and Data are multiplexed on the same PCI pins.
bit 1
AD2
104
3-5tate
1/0
Address and Data are multiplexed on the same PCI pins.
bit 2
AD3
101
3-5tate
1/0
Address and Data are multiplexed on the same PCI pins.
bit 3
AD4
100
3-5tate
1/0
Address and Data are multiplexed on the same PCI pins.
bit 4
AD5
97
3-5tate
1/0
Address and Data are multiplexed on the same PCI pins.
bit 5
AD6
95
3-5tate
1/0
Address and Data are multiplexed on the same PCI pins.
bjt6
AD7
94
3-5tate
1/0
Address and Data are multiplexed on the same PCI pins.
bit 7
AD8
90
3-5tate
1/0
Address and Data are multiplexed on the same PCI pins.
bit 8
AD9
89
3-5tate
1/0
Address and Dahl are multiplexed on the same PCI pins.
bit 9
AD10
87
3-5tate
1/0
Address and Data are multiplexed on the same PCI pins.
bit 10
AD11
85
3-5tate
1/0
Address and Data are multiplexed on the same PCI pins.
bit 11
AD12
84
3-5tate
I/O
Address and Data are multiplexed on the same PCI pins.
bit 12
AD13
82
3-5tate
I/O
Address and Data are multiplexed on the same PCI pins.
bit 13
AD14
78
3-5tate
I/O
Address and Data are multiplexed on the same PCI pins.
bit 14
AD15
77
3-5tate
I/O
Ad.dress and Data are multiplexed on the same PCI pins.
bit 15
AD16
54
3-5tate
I/O
Address and Data are multiplexed on the same PCI pins.
bit 16
June 1994
3-186
FunCtiOn
GND
GND
PXQ
LNQ
HGT
VGT
OE
VR08
VR09
VR010
VROll
VR012
VR013
Vee
GND
,Vee
VR0137
VR0138
VR0139
Vee
GND
GND
Vee
VR017
VR018
VR019
VR020
VR021
VR022
VR023
VRQ24
VR025
VR026
VR027
VR028
VR029
VR030
VR031
GND
GND
Philips Semiconductors Desktop Video Products
Preliminary specification
Digital video to PCI interface
SYMBOL3
PIN
NUMBER
SAA7116
SIGNAL TYPE
INPUTI
OUTPUT
TYPE2
SIGNAL
DIRECTION
DESCRIPTION
AD17
52
3-State
I/O
Address and Data are multiplexed on the same PCI pins.
bit 17
AD18
51
3-State
I/O
Address and Data are multiplexed on the same PCI pins.
bit 18
.'
AD19
49
3-State
I/O
Address and Data are multiplexed on the same PCI pins.
bit 19
AD20
47
3-State
I/O
Address and Data are multiplexed on the same PCI pins.
bit 20
AD21
46
3-State
I/O
Address and Data are multiplexed on the same PCI pins.
bit 21
AD22
44
3-State
1/0
Address and Data are multiplexed on the same PCI pins.
bit 22
AD23
42
3-State
I/O
Address and Data are multiplexed on the same PCI pins.
bit 23
AD24
36
3-State
1/0
Address and Data are multiplexed on the same PCI pins.
bit 24
AD25
34
3-State
I/O
Address and Data are multiplexed on the same PCI pins.
bit 25
AD26
33
3-State
I/O
Address and Data are multiplexed on the same PCI pins.
bit 26
AD27
31
3-State
I/O
Address and Data are multiplexed on the same PCI pins.
bit 27
AD28
29
3-State
I/O
Address and Data are multiplexed on the same PCI pins.
bit 28
AD29
28
3-State
I/O
Address and Data are multiplexed on the same PCI pins.
bit 29
AD30
26
3-State
I/O
Address and Data are multiplexed on the same PCI pins.
bit 30
AD31
24
3-State
I/O
Address and Data are multiplexed on the same PCI pins.
bit 31
C/BE3#
38
3-State
I/O
Bus Command and Byte Enables are multiplexed on the same PCI pins.
Lane 3
CIBE2#
56
3-State
I/O
Bus Command and Byte Enables are multiplexed on the same PCI pins.
Lane 2
CIBE1#
75
3-State
I/O
Bus Command and Byte Enables are multiplexed on the same PCI pins.
Lane 1
CIBEO#
92
3-State
I/O
Bus Command and Byte Enables are multiplexed on the same PCI pins.
Lane 0
PAR
73
3-State
I/O
Parity is even parity across AD[31 .. 0j and C/BE[3 .. 0j#. PAR is stabel and valid one
clock after the address phase.
PCllnterface Control Pins
FRAME#
57
slt/s
I/O
Cycle Frame is driven to indicate the beginning and duration of an access.
IRDY#
62
sItts
I/O
Intiator Ready indicates the ability to complete the current data phase of the
transaction as busmark.
TRDY#
63
sitts
I/O
Target Ready indicates the ability to complete the current data phase of the
transaction as receiver.
STOP#
68
sItts
I/O
Stop indicates the current target i~ requesting the master to stop the current
transaction.
IDSEL
39
I
I
Initialization device Select is used as a chip select during configuration read and
write transactions.
DEVSEL#
67
sItts
I/O
Device Select, when actively driven, indicates the driving device has decoded its
address as the target of the current access.
PCI System Control Pins
PRST#
17
I
I
PCI Reset on PCI bus. If PRST# is asserted, all PCI output signals are 3-stated.
PCLK
18
I
I
PCI Clock provides timing for all transactions on PCI and is an input. All other PCI
signals, except PRST#, INTA#, INTB#, INTC# AND INTD#, are sampled on the rising
edge of PCLK, and all other timing parameters are defined with respect to this edge.
INT PINO
110
I
I
Interrupt address designation, defines PCI interrupt number. Do not connect.
INT_PIN1
111
I
I
Interrupt address designation, defines PCI interrupt number. Do not connect.
INT_PIN2
112
I
I
Interrupt address designation, defines PCI interrupt number. Do not connect.
INT#
16
OD
0
PCI Interrupt is used to request an interrupt. Interrupt number is defined by interrupt
address pins 110,111,112.
REQ#
23
3-State
0
GNT#
19
3-State
I
June 1994
Request to the arbitor, that this device desires use of the bus..
Grant indicates that access to the bus has been granted.
3-187
Philips Semiconductors Desktop Video Products
Preliminary specification
Digital video to PCI interface
SYMBOL3
PIN
NUMBER
SAA7116
SIGNAL TYPE
INPUTI
OUTPUT
TYPE2
SIGNAL
DIRECTION
DESCRIPTION
Video Pins
VR031
158
I
I
Video Data from Video input source, e.g., SAA7196
VR030
157
I
I
Video Data from Video input source, e.g., SAA7196
bit 30
VR029
156
I
I
Video Data from Video input source, e.g., SAA7196
bit 29
VR028
155
I
I
Video Data from Video input source, e.g., SAA7196
bit 28
VR027
154
I
I
Video Data from Video input source, e.g., SAA7196
bit 27
VR026
153
I
I
Video Data from Video input source, e.g., SAA7196
bit 26
VR025
152
I
I
Video Data from Video input source, e.g., SAA7196
bit 25
VR024
151
I
I
Video Data from Video input source, e.g., SAA7196
bit 24
VR023
150
I
I
Video Data from Video input source, e.g., SAA7196
bit 23
VR022
149
I
I,
Video Data from Video input source, e.g., SAA7196
bit 22
VR021
148
I
I
Video Data from Video input source, e.g., SAA7196
bit 21
VR020
147
I
I
Video Data from Video input source, e.g., SAA7196
bit 20
VR019
146
I
I
Video Data from Video input source, e.g., SAA7196
bit 19
VR018
145
I
I
Video Data from Video input source, e.g., SAA7196
bit 18
VR017
144
I
I
Video Data from Video input source, e.g., SAA7196
bit 17
VR016
139
I
I
Video Data from Video input source, e.g., SAA7196
bit 16
VR015
138
I
I
Video Data from Video input source, e.g., SAA7196
bit 15
VR014
,137
I
I
Video Data from Video input source, e.g., SAA7196
bit 14
VR013
133
I
I
Video Data from Video input source, e.g;, SAA7196
bit 13
VR012
132
I
I
Video Data from Video input source, e.g., SAA7196
bit 12
VR011
131
I
I
Video Data from Video input source, e.g., SAA7196
bit 11
VR010
130
I
I
Video Data from Video input source, e.g., SAA7196
bit 10
VR09
129
I
I
Video Data ffom Yideo input source, e.g., SAA7196
bit 9
VR08
128
I
I
Video Data from Video input source, e.g.,SAA7196
bit 8
PXO
123
I
I
Pixel Qualifier, e.g., from VROO of SAA7196
LON
124
I
I
Line Qualifier, e.g" from VR010f SAA7196
VGT
126
I
I
Vertical Gate signal, e.g., from VR05 of SAA7196
,Horizontal Gate signal, ~.g., from VR04 of SAA7196
bit 31
Video Control
HGT
125
I
I
SDA
13
OC
I/O
Data signal of 12C bus
SCl
12
OC
I/O
Clock signal of 12C bus, single master operation only
OE
127
I
I
Odd-even field indicator, e.g., from VR06 of SAA7196,
VClK
7
I
I
Video input clock, e.g., same as VClK pin of SAA7196
VRSTN#
9
I
0
TN
117
I
I
PO
118
I
0
June 1994
Video Reset; to reset video capture device, e.g., SAA7196
Test Pin, pull high or leave unconnected for normal operation.
Test Pin, don't connect.
3-188
Preliminary specification
Philips Semiconductors Desktop Video Products
Digital video to PCI interface
SYMBOL3
PIN
NUMBER
SAA7116
DESCRIPTION
SIGNAL TYPE
INPUTI
OUTPUT
TYPE2
SIGNAL
DIRECTION
Miscellaneous
VCC5
1,2,8,
15,20,
25,30,
35,:40,
43,48,
53,58,
61,64,
66,71,
76,81,
83,88,
93,98,
99,105,
113,119,
120,134,
140,143
Supply power
GND
10,11,
21,22,
27,32,
37,41,
45,50,
55,59,
60,65,
69,74,
79,80,
86,91,
96,102,
103,108,
109,121,
122,135,
141,142,
159,160
Ground
NC
3,4,5,6,
14,70,
72,114,
115,116,
161
No Connection
NOTES:
2. PCI Signal Type Definitions:
I
Input is a standard input-only signal.
Totem Pole Output is a standard active driver.
3-State 3-State is a bi-directional, 3-State input/output pin.
slt/s
Sustained 3-State is an active log 3-State signal owned and driven by one and only one agent at a time. The agent that drives
an slt/s pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving a sNs signal any
sooner than one clock after the previous owner 3-states it. A pullup is required to sustain the inactive state until another agent
drives it, and must be provided by the contral resource.
00
Open Drain allows multiple devices to share as a wire-OR.
oe
Open Collector
3. The symbol # at the end of a signal name indicates that the active state occurs when the signal is at a low voltage.
o
June 1994
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Philips Semiconductors Desktop Video Products
Preliminary specification
Digital video to PCI interface
1.0 INTRODUCTION
1.1
SAA7116
video data across the PCI bus and operates
in slave mode to program local control
registers of SAA7116.
Global Overview
Figure 3 is a block diagram of a Multimedia
System. The SAA71161C along with the
Philips video capture chipset provide the
solution for the Capture portion of this
diagram.
1.1.1
The SAA7116 is a video capture IC that
serves as an interface between the Philips
video capture chipset and the PCI bus. The
Philips video capture chipset provides
digitized, translated, filtered and scaled data
to the SAA7116 IC in one of three formats:
RGB 5-5-5, YUV 4:2:2, or RBG 8-8-8. The
SAA7116 contains FIFOs to decouple the
real time input video data stream from the
PCI bus and provides DMA channels to
deliver the video data in packed format (Le.,
for local display) and planar format (Le., for
compression).
The SAA7116 is both a PCI bus master and
slave. It operates in master mode to transfer
system memory as specified by the local
DMA channel control registers.
There are six DMA address registers. The
DMA address and stride registers can be
programmed to send even and odd fields of
an interlaced video stream to the same
location or even fields to one location and
odd fields to another. Data is transferred in
both packed and planar modes. Data format
and resolution can be programmed on a field
by field basis.
Input Interface Description
The Philips video capture chipset receives an
NTSC, PAL, SECAM composite interlaced or
non-interlaced analog video signal, provides
analog to digital conversion, NTSC to
RGBNUV translation, and image filtering and
scaling. The Philips video capture chipset,
e.g., TDA8708A and SAA7196, outputs the
video data to the SAA7116 IC in one of three
formats: YUV 4:2:2 (16 bit), RGB 5-5-5 (15
bit) or RGB 8-8-8 (24 bit).
1.2 Reference Documents
Philips Desktop Video Data Handbook 1994
PCI Local Bus Specification
Obtain from PCI Special Interest Group
1.1.2 Output Interface Requirements
(503)696-6111 - Help Line
(800)433-5177 - USA only documentation
(503)797-4207 -outside USA
documentation
During active capturing of video data, the
master PCI state machine will request the
bus once image data has been received and
an appropriate address has been generated.
It will generate burst writes of video data onto
the PCI bus to frame buffer memory or
PAL
NTSC
SECAM
CPU/DRAM
r-----------.
:ElEr
DRAM
Capture
Compress
AID
&
DECODER
SCALER
Display
B EJ
B
SCSI:
HDISK
CDROM
SLOW VO (ISA) -'------''-----'--'--''-
Concurrency:
1. CPU bus
2. PCI
3. Slow I/O bus
Figure 3. Multimedia System Configuration
June 1994
3-190
G
G
Preliminary specification
Philips Semiconductors Desktop Video Products
Digital video to PCI interface
2.0 FUNCTIONAL
DESCRIPTIONS
2.1
Block Diagram
The Block Diagram on page 3·185 illustrates
the main design partitions of the SAA7116 IC.
Signal polarities are not indicated on any of
the diagrams. Please rrefer to Pin
Description.
2.2 FIFO
The FIFO block accepts data from the Philips
Video Decoder or Scaler in three different
pixel formats (YUV16, RGB16, and RGB24),
assembles this data into 32·bit words, buffers
the data in a FIFO memory, and, in
conjunction with the PCI bus master control
logic, transmits the image data on to the PCI
bus.
The FIFO Input Control Logic samples LNO
and PXO to determine if the data driven by
the Video Decoder or Scaler is valid and
should be written into the FIFO.
Active to inactive transitions on HGT and
VGT indicate an end of line (EOL) or end of
fieldlframe (EOF) has occurred.
June 1994
SAA7116
2.2.1 Pixel FIFO
The pixel FIFO acts as a buffer between the
slow, steady pixel data stream generated by
the Video Decoder or Scaler and the fast,
"bursty" PCI bus.
2.3 Address Generator
The Address Generator provides the DMA
address to be driven onto PCI for a bus
cycle. There are 6 DMA address registers: 3
even registers and 3 odd registers. Each
DMA register has an associated stride
register.
2.4 Address/Data multiplexer
The Address/Data MUX controls whether
address and a bus command or data and
byte enables are driven onto the PCI bus. It
is controlled by the Master Control Logic.
2.5 Master Control Block
The Master Control Block orchestrates the
flow of address and data onto the PCI bus
during master cycles.
Once a DMA address is generated, the
Master Control Logic asserts REO to the PCI
3·191
bus and waits for the assertion of GNT. Once
GNT is asserted, the Master Control Block
asserts FRAME, and drives the address and
bus command onto the PCI bus. On the
.
subsequent clock, the Master Control Logic
switches the Address/Data MUX to drive data
and byte enables and asserts IRDY. The
SAA7116 supports 0 WS burst writes.
2.6 Master Latency Timer
The Master Latency Timer is an 8 bit counter.
When the Master Control Logic asserts
FRAME, the Master Latency Timer/Counter is
enabled. If FRAME is de-asserted before the
counter expires, the Master Latency Timer is
meaningless. If the counter expires before
the de·assertion of FRAME, or other STOP
condition is asserted, and GNT is
deasserted, the bus cycle will be terminated.
2.7
Slave Logic
The Slave Logic decodes PCI cycles to
memory and configuration registers. Some of
these local registeres are transmitted on the
12C interface to the 12C-controlled ICs of the
video capture IC set.
Preliminary specification
Philips Semiconductors Desktop Video Products
SAA7116
Digital video to PCI interface
2.8
Programmable Registers of SAA7116
REGISTER TYPES
Read/reset. This register type may
be read, or be reset to 0 bywriting
a 1 into the corresponding bit
location. Writing 0 has nQ effect.
Events internal to the SAA7116
can cause this register type to be
set to 1. All bits are .initialized to 0
upon hardware reset.
RR
RO x . Read-only with value x. Writing to
this type of register has no effect.
RW
Read/write. All bits are initialized
to 0 upon hardware reset.
RS
Read/set. This register type may
be read, or be set to 1 by writing a
1 into the corresponding bit
location. Writing 0 has no effect.
Events internal to SAA7116 can
cause this register type to be reset
to O. All bits are initialized to 0
upon hardware reset. .
2.8.1
NOTES:
1. All bit positions not listed in the following
register description are of type RO Ob.
2. Registers marked with an * are actively
used while capture is enabled, and should
only be changed when the SAA7116
capture is inactive.
0* registers can be changed during
even field capture.
e* registers can be changed during
odd field capture.
3. Register types marked with ** are used
during 12C cycles, and should only be
changed when the 12C controller is
inactive.
PCI Configuration Registers
OFFSET
BITS
TYPE
REGISTER
..
WORD 3
OOh
04h
WORD 2
24123
131
I
WORD 1
1St 15
WORD
B
0
17
01
31:16
RO
Device 10
1223h
15:0
RO
Vendor ID
8086h
29
RR
Master Abort Generated
A value of 1 indicates that a master abort was generated while attempting to perform a
DMA operation. Writing a 1 will reset this bit.
28
RR
Target Abort Detected
A value of 1 indicates that a target abort was detected while performing a DMA
operation. Writing a 1 will reset this bit.
26:25
RO
DEVSEL# Timing
01b
SAA7116 performs "Medium" speed device select.
08h
2
RW
Master Enable
1 = enable SAA7116 master cycles.
0= disable SAA7116 master cycles.
1
RW
Memory Enable
1 = enable SAA7116 slave decode to memory mapped registers. This
configuration is required to access the SAA7116 memory registers.
0= disable SAA7116 memory registers.
31:8
RO
Class Code
040000h
The code for "Multimedia Video Device" is returned in this register.
OCh
7:0
RO
15:8
RW
Revision ID
OOh
Latency Timer
Specifies the number of PCI clocks that must elapse before a de-assertion of the GNT#
pin will cause the SAA7116 master to give up ownership of the PCI bus.
10h
3Ch
31:12
RW
Memory Base Address
11:0
RO
Specifies the base address of the SAA7116 memory-mapped registers. SAA7116
claims a 4K address space by making bits 11:0 of this register RO OOOh.
OOOh
15:11
RO
Interrupt Pin
OOOOOb
10:8
RO
This register specifies the PCI interrupt line that the SAA7116 is connected to. Values
of 1, 2, 3, and 4, correspond to INTA#, INTB#, INTC#, and INTD#, respectively. Bits
10:8 of this register echo the status of the 3 pins inCpin[2:0], which should be wired
appropriately in hardware.
7:0
RW
Interrupt Line
This is an 8-bit register, used by BIOS software to indicate which IRQ line (for PC
architectures) SAA7116 is mapped to.
June 1994
3-192
Preliminary specification
Philips Semiconductors Desktop Video Products
SAA7116
Digital video to PCI interrace
2.8.2 Memory Registers
NOTE: Memory registers are accessed through PCI control base memory address register 10h with appropriate offset shown below.
OFFSET
BITS
TYPE
REGISTER
WORD 3
OOh
04h
08h
OCh
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
WORD 2
24123
131
I
16 1 15
WORD 1
WORD
817
31:1
e*RW
DMA 1 (Even)
0
ROOb
Base address for even field DMA channel 1. This value is specified as a standard 32-bit
byte address. The LSB is forced to O.
31:2
e*RW
DMA2 (Even)
1:0
ROOOb
Base address for even field DMA channel 2.
31:2
e*RW
DMA3 (Even)
1:0
ROOOb
Base address for even field DMA channel 3.
31:1
o*RW
DMA 1 (Odd)
0
ROOb
Base address for odd field DMA channel 1.
31:2
o*RW
DMA2 (Odd)
1:0
ROOOb
Base address for odd field DMA channel 2.
31:2
o*RW
DMA3 (Odd)
1:0
ROOOb
Base address for odd field DMA channel 3.
15:2
e*RW
Stride 1 (Even)
1:0
ROOOb
Address stride for even field DMA channel 1. Bits 15:0 specify a byte value to be added to
the address of the last pixel of a scan line, to generate the address of the next consecutive
scan line. The two LSBs are forced to O.
15:2
e*RW
Stride 2 (Even)
1:0
ROOOb
Address stride for even field DMA channel 2.
15:2
e*RW
Stride 3 (Even)
1:0
ROOOb
Address stride for even field DMA channel 3.
15:2
o*RW
Stride 1 (Odd)
1:0
ROOOb
Address stride for odd field DMA channel 1
15:2
o*RW
Stride 2 (Odd)
1:0
ROOOb
Address stride for odd field DMA channel 2.
15:2
o*RW
Stride 3 (Odd)
1:0
ROOOb
Address stride for odd field DMA channel 3.
31:8
*RW
Route (Even)
Pixel router mode for even fields. The following values are defined, based on pixel format:
Pixel Format
RGB 24 packed
RGB 16 packed
YUV 16 packed
YUV 16 planar
YUV9 planar
YUV 12 planar
7:0
*RW
Value
393939h
eeeeeeh
eeeeeeh
aaaaffh
aaaaffh
aaaaffh
Mode (Even)
Pixel format for even fields. The following formats are defined:
Pixel Format
RGB 24 packed
RGB 16 packed
YUV 16 packed
YUV 16 planar
YUV 12 planar
YUV9 planar
June 1994
Value
OOh
01h
41h
C1h
C2h
C3h
3-193
0
01
Philips Semiconductors Desktop Video Products
Preliminary specification
Digital video to PCI interface
OFFSET
BITS
TYPE
REGISTER
SAA7116
WORD 3
WORD 2
WORD 1
16115
34h
31:8
*RW
Route (Odd)
See description for even field route.
7:0
*RW
Mode (Odd)
See description for even field mode.
38h
22:16
*RW
FIFO Trigger Planar Mode
Specifies the number of Dwords that must collect in FIFO 1 (the "yo FIFO) before a PCI
data transfer is triggered, in planar pixel modes.
6:0
*RW
FIFO Trigger Packed Mode
Specifies one-half the number of Dwords that must collect in the internal FIFOs before a
PCI data transfer is triggered, in packed pixel modes.
3Ch
9:8
*RW
Reserved
2
*RW
Field Toggle
Leave alone or set to 0,0.
When enabled, field toggle mode causes the SAA7116 to emulate interlaced video, when
presented with a non-interlaced video signal. This is done by internally toggling the
odd/even field signal and overwriting the detection from a non-interfaced or distorted input
signal (e.g., VCR-feature modes).
1 = enable field toggle mode
0= disable field toggle mode
1
*RW
Reserved
Set to 1.
0
*RW
Reserved
Set to 1.
40h
15
*RW
Range Enable
Specifies whether address range checking is enabled. Note that this feature is only
intended to be disabled for test purposes. DMA end (even and odd) must also be set, for
this feature to function.
1 = enable address range checking
0= disable address range checking
14
*RW
Corrupt Disable
Specifies how the FIFO overflow condition is handl.ed.
1 = ignore FIFO overflow. This setting is intended for test purposes ONLY.
0= drop remainder of current field if FIFO overflows.
11
RR
Address Error (Odd)
Specifies whether an internal DMA address exceeding DMA End (Odd) was generated.
1 = odd field address error detected. The remainder of the odd field was dropped.
0= no address errors detected
This bit must be reset once triggered.
10
RR
Address Error (Even)
Specifies whether an internal DMA address exceeding DMA End (Even) was generated.
1 = even field address error detected. The remainder of the even field was dropped.
0= no address errors detected
This bit must be reset once triggered.
9
RR
Field Corrupt (Odd)
1 = FIFO overflow detected during odd field capture. The remainder of the odd field
was dropped.
0= no FIFO overflows detected.
This bit must be reset once triggered
June 1994
3-194
WORD 0
Preliminary specification
Philips Semiconductors Desktop Video Products
Digital video to PCI interface
OFFSET
BITS
TYPE
REGISTER
SAA7116
WORD 3
WORD 2
WORD 1
WORD 0
16[ 15
40h
(cont.)
8
RR
7
*RW
Field Corrupt (Even)
1 = FIFO overflow detected during even field capture. The remainder of the even field
was dropped.
0= no FIFO overflows detected.
This bit must be reset once triggered.
FIFO Enable
Writing a 0 to this location puts the internal FIFO and 12C logic into a reset state. Writing a
1 enables the FIFO and 12C logic.
6
*RW
VRSTN#
This bit is tied directly to the VRSTN# output pin. Writing a 0 puts the external
decoder/scaler/clock generator into a reset state. Writing a 1 brings them out of reset.
5
RR
Field Done (Odd)
1 = end of captured odd field detected. This bit is set once the final pixel of the odd
field has been transferred on the PCI bus.
= end of odd field not detected yet.
4
RR
Field Done (Even)
1 = end of captured even field detected. This bit is set once the final pixel of the even
field has been transferred on the PCI bus.
= end of even field not detected yet.
3
RS
Single Field Capture (Odd)
o
o
Setting this bit causes the SAA7116 to capture a single odd field. This bit is reset once the
field capture operation has been completed.
2
RS
Single Field Capture (Even)
Setting this bit causes the SAA7116 to capture a single even field. This bit is reset once
the field capture operation has been completed.
RW
Capture (Odd)
Setting this bit causes the SAA7116 to continuously capture odd fields. Clearing this bit
causes the SAA7116 to stop capturing AFTER the current field capture has been
completed.
o
RW
Capture (Even)
Setting this bit causes the SAA7116 to continuously capture even fields. Clearing this bit
causes the SAA7116 to stop capturing AFTER the current field capture has been
completed.
44
7:0
*RW
Retry Wait Counter
Specifies the number of Clocks that the SAA7116 PCI master will wait after receiving a
disconnect from a slave, before retrying a transaction to the current destination.
June 1994
3-195
Preliminary specification
Philips Semiconductors Desktop Video Products
Digital video to PCI interface
OFFSET
BITS
TYPE
REGISTER
SAA7116
WORD 3
WORD 2
WORD 1
WORD 0
16115
48h
RW
Interrupt mask, start of field
1
enable interrupt for start of field. This interrupt is triggered for every incoming
field, regardless of whether it is being captured.
o = disable this interrupt
9
RW
Interrupt mask, end of odd field
1 = enable interrupt for end of captured odd field.
o disable this interrupt.
8
RW
Interrupt mask, end of even field
1 = enable interrupt for end of captured even field.
o = disable this interrupt.
2
RR
10
=
=
Interrupt status, start of field
This bit is set when the start of field interrupt has been triggered.
RR
Interrupt status, end of odd field
This bit is set when the end of captured odd field interrupt has been triggered.
o
RR
Interrupt status, end of even field
This bit is set when the end of captured even field interrupt has been triggered.
4Ch
31:0
*RW
Field Mask (Even)
For continuous capture mode only, this 32-bit pattern specifies a sequence of even fields
to either capture or mask. The LSB is the first field in the sequence. A bit value of 1
corresponds to a field to capture, and a value of 0 to a field to mask. See the Mask Length
(Odd) description for an example.
SOh
31:0
*RW
Field Mask (Odd)
For. continuous capture mode only this 32-bit pattern specifies a sequence of odd fields to
either capture or mask. The LSB is the first field in the sequence. A bit value of 1
corresponds to a field to capture, and a value of 0 to a field to mask. See the Mask Length
(Odd) description for an example.
54h
20:16
*RW
Mask Length (Odd)
Specifies the length (minus 1) of the odd field mask. For example, a mask value of
00000001h and a mask length value of 1h causes every other field to be captured. A mask
of 00000001 h and a mask length of Oh causes every field to be captured.
4:0
*RW
Mask Length (Even)
Specifies the length (minus 1) of the even field mask.
58h
22:16
*RW
FI FO Almost Empty Pointer
Specifies the number of Dwords needed in FIFO 1 to trigger an almost empty condition.
This condition is used to terminate PCI burst transfers. If it is set too low, FIFO underflows
could result. A good value is 5h.
6:0
*RW
FIFO Almost Full Pointer
Specifies the number of Dwords needed in FIFO 1 to trigger an almost full condition. This
condition is used to flag FIFO overflows and to terminate capture of the current field. If it is
set too high, overflows may not be detected in time, and unpredictable behavior may
result. To utilize the entire FIFO, a good setting is 7Ch. This value may be decreased to
simulate a smaller FIFO.
5Ch
31:24
**RW
12C Phase 4
12C clock cycles are broken into four phases by the SAA7116 12C master. This register
specifies the duration of the fourth phase in number of VCLK cycles (typically 80 ns).
23:16
**RW
12C Phase 3
The duration of the 3rd 12C clock phase in VCLK cycles.
15:8
**RW
12C Phase 2
The duration of the 2nd 12C clock phase in VCLK cycles.
7:0
**RW
12C Phase 1
The duration of the first 12C clock phase in VCLK cycles.
June 1994
3-196
Preliminary specification
Philips Semiconductors Desktop Video Products
Digital video to PCI interface
OFFSET
BITS
TYPE
REGISTER
SAA7116
WORD 3
WORD 1
WORD 2
WORD 0
16115
60h
31:24
RO
12C Read Data
a bits of read data returned by an 12C read operation.
Warning: do not read this register while an 12C read operation is in progress.
23:16
**RW
12C Auto Address
The 12C slave address to be used for all auto-update cycles.
11
RO
12C SCL Input
The state of the 12C SCL signal external to the SAA7116 may be read on this bit.
10
RO
12C SDA Input
The state of the 12C SDA signal external to the SAA7116 may be read on this bit.
9
RR
12C Direct Abort
This bit indicates whether the last 12C direct cycle was successful.
0= success
1 = cycle aborted
This bit must be reset once triggered.
a
RR
12C Auto Abort
This bit indicates whether the last 12C auto update cycle was successful.
0= success
1 = cycle aborted
This bit must be reset after being set.
3
RW
12C SCL Output
When in 12C bypass mode, the value of this bit is driven out onto the SCL pin.
2
RW
12C SDA Output
When in 12C bypass mode, the value of this bit is driven out onto the SDA pin.
RW
o
RW
12C Bypass
1 = enable 12C bypass mode. When in this mode, the SCL and SDA pins are driven
by the 12C SCL Output and 12C SDA Output bits, respectively.
0=
disable 12C bypass mode. This is the normal mode of operation. In this mode, the
SCL and SDA pins are driven by the SAA7116 12C bus master logic. This
configuration must be selected for 12C direct and auto update cycles to function.
12C Auto Enable
This bit enables the 12C automatic update mode. In this mode, data stored in the SAA7116
"Auto Data" registers is automatically copied through the 12C interface to the control
register of video capture ICs at the beginning of each field. The SAA7116 stores 2 banks
(1 per field) of a registers each, allowing up to a external1 2C registers to have separate
values for even and odd fields. This feature is intended to allow each field to have its own
scale factors and color space. ,
1= enable 12C auto update mode.
0=
disable 12C auto update mode.
64h
24
RS
12C New Cycle
When this bit has been set, the SAA7116 will execute a direct 12C cycle, using the 12C
Direct Address, Sub-address (for write cycles), and Write data (for write cycles) fields. This
bit is automatically cleared when the cycle has been completed. The 12C Direct Abort bit
should then be checked for successful completion.
23:16
**RW
12C Direct Address
The 12C slave address used for 12C direct cycles. The upper 7 bits of this field specifiy a
device address, while the LSB specifies whether a read or write operation is to be
performed on the 12C bus. A value of 1 corresponds to a read and a 0 to a write.
15:8
**RW
12C Direct Sub-address
The a-bit sub-address to be used for 12C direct WRITE cycles. This field is ignored for
reads.
7:0
**RW
12C Direct Write Data
a bits of write data to be used for 12C direct WRITE cycles. This field is ignored for 12C
read cycles.
June 1994
3-197
Preliminary specification
PhilipS SemiconQuctors Desktop Video Products
SAA7116
Digital video to PCI interface
OFFSET
BITS
TYPE
REGISTER
WORD 3
WORD 1
WORD 2
WORD 0
16[ 15
68h
31:24
**RW
12C Auto Sub-address 1 (Even)
Sub-address for .auto update cycle 1, to be written during the EVEN field. Since the scaling
registers of SAA7196, for example, are double buffered, the results of this cycle won't be
seen until the ODD field.
23:16
**RW
15:8
**RW
12C Auto Data 1 (Even)
Data for auto update cycle 1.
12C Auto Sub-address 0 (Even)
Sub-address for auto update cycle O.
6Ch
70h
74h
78h
7:0
**RW
12C Auto Data 0 (Even)
Data for auto update cycle O.
31:24
**RW
23:16
**RW
12C Auto Sub-address 3 (Even)
12C Auto Data 3 (Even)
15:8
**RW
12C Auto Sub-address 2 (Even)
7:0
**RW
12C Auto Data 2 (Even)
31:24
**RW
23:16
**RW
12C Auto Sul::!-address 5 (Even)
12C Auto Data 5 (Even)
15:8
**RW
12C Auto Sub-address 4 (Even)
7:0
**RW
12C Auto Data 4 (Even)
31:24
**RW
23:16
**RW
12C Auto Sub~address 7 (Even)
12C Auto Data 7 (Even)
15:8
**RW
12C Auto Sub-address 6 (Even)
7:0
**RW
12C Auto Data 6 (Even)
31:24
**RW
12C Auto Sub-address 1 (Odd)
Sub-address for auto update cycle 1, to be written during the ODD field. Since the scaling
registers of SAA7196, for example, are .double buffered, the results of this cycle won't be
seen until the EVEN field.
7Ch
80h
84h
June 1994
23:16
**RW
12C Auto Data 1 (Odd)
Data for auto update cycle 1.
15:8
**RW
12C Auto Sub-address 0 (Odd)
Sub-address for auto update cycle O.
7:0
**RW
12C Auto Data 0 (Odd)
Data for auto update cycle O.
31:24
**RW
23:16
**RW
12C Auto Sub-address 3 (Odd)
12C Auto Data 3 (Odd)
15:8
**RW
12C Auto Sub-address 2 (Odd)
7:0
**RW
12C Auto Data 2 (Odd)
31:24
**RW
23:16
**RW
12C Auto Sub-address 5 (Odd)
12C Auto Data 5 (Odd)
15:8
**RW
12C Auto Sub-address 4 (Odd)
7:0
**RW
12C Auto Data 4 (Odd)
31:24
**RW
23:16
**RW
12C Auto Sub-address 7 (Odd).
12C Auto Data 7 (Odd)
15:8
**RW
12C Auto Sub-address 6 (Odd)
7:0
**RW
12C Auto Data 6 (Odd)
3-198
Preliminary specification
Philips Semiconductors Desktop Video Products
Digital video to PCI interface
OFFSET
BITS
TYPE
SAA7116
REGISTER
aah
23:16
**RW
WORD 2
WORD 3
24123
131
I
16 115
WORD 1
WORD
817
12C Register Enable (Odd)
This field specifies which of the a auto update sub-addressldata registers for ODD field
auto updates is valid. The LSB corresponds to subaddressldata 0, and the MSB to
subaddressldata 7. A value of 1 in a bit position enables the corresponding
subaddressldata pair.
7:0
**RW
12C Register Enable (Even)
This field specifies which of the a auto update sub-addressldata registers for EVEN field
auto updates is valid. The LSB corresponds to subaddressldata 0, and the MSB to
subaddressldata 7. A value of 1 in a bit position enables the corresponding
subaddressldata pair.
aCh
90h
June 1994
23:2
e*RW
DMA End (Even)
1:0
ROOOb
This register sets the upper bound (inclusive) of the address window that the SAA7116
master may write to during even field DMA. The Range Enable bit must be set for this
feature to function. Although only 24 bits are defined in this register, software should write
a full 32-bit byte address, to maintain compatibility with possible future implementations of
the SAA7116. The current SAA7116 design uses the a MSBs of the 3 DMA even channel
address registers (depending on which channel is active) as the a MSBs of DMA End.
23:2
o*RW
DMA End (Odd)
1:0
ROaOb
This register sets the upper bound (inclusive) of the address window that the SAA7116
master may write to during odd field DMA. The Range Enable bit must be set for this
feature to function. Although only 24 bits are defined in this register, software should write
a full 32-bit byte address, to maintain compatibility with possible future implementations of
the SAA7116. The current SAA7116 design uses the a MSBs of the 3 DMA odd channel
address registers (depending on which channel is active) as the a MSBs of DMA End.
3-199
0
01
Preliminary specification
Philips Semiconductors Desktop Video Products
SAA7116
Digital video to PCI interface
LIMITING VALUES
In accordance with the Absolute Maximum Rating system (lEG 134).
MIN.
MAX
UNIT
Voo
Supply voltage
-0.5
6.5
V
VI
DG input voltage on all pins
-0.5
Voo
V
100
Supply current
-
200
mA
Ptot
Total power dissipation
Tstg
Storage temperature range
Tamb
VESO
SYMBOL
PARAMETER
0
1
W
-65
150
°G
Operating ambient temperature range
0
70
°G
Electrostatic handling 1 for all pins
-
±2000
V
MIN.
MAX.
4.75
5.25
V
200
mA
V
NOTES:
1. Equivalent to discharging a 150pF capacitor through a 1.5kU series resistor.
DC CHARACTERISTICS
Voo = 4.75 to 5.25V; Tamb = 0 to 70 o G, unless otherwise specified.
SYMBOL
PARAMETER
CONDITION
UNIT
Voo
Supply voltage
Ip
Total supply current
VIH
Input HIGH voltage
2.0
Vcc+0.5
VIL
Input LOW voltage
-0.5
0.8
V
IIH
Input HIGH leakage current
VIN = 2.7V
Note 1
70
IlA
IlL
Input LOW leakage current
VIN = 0.5 V
Note 1
-70
IlA
VOH
Output HIGH voltage
lOUT =-2 mA
VOL
Output LOW voltage
IOUT=3 mA, 6 rnA
Note 2
Inputs LOW; no output loads
2.4
V
0.55
V
10
pF
12
pF
GIN
Input pin capacitance
CCLK
CLK pin capacitance
CIDSEL
IDSEL pin capacitance
8
pF
Lpin
Pin inductance
20
nH
±70
IlA
8
pF
5
3-State Outputs
10 off
High-impedance output current
CI
High-impedance output capacitance
-
12C-bus, SDA and SCl
VIL
Input voltage LOW
-0.5
1.5
V
V IH
Input voltage HIGH
3
Voo+0.5
V
liN
Input current
-
±10
IlA
lACK
Output current on SDA pin
Acknowledge
3
-
mA
VOL
Output voltage at Acknowledge
ISOA=3 mA
-
0.4
V
NOTES:
1. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with 3-State outputs.
2. Signals without pull up resistors must have 3 mA low output current. Signals requiring pull up must have 6 mA.
June 1994
3-200
Preliminary specification
Philips Semiconductors Desktop Video Products
SAA7116
Digital video to PCI interface
AC CHARACTERISTICS
VDD
= 4.75 to 5.25V; Tamb = 0 to 70°C, unless otherwise specified.
PARAMETER
SYMBOL
CONDITIONS1
MAX.
MIN.
-
UNIT
ns
tCYC
ClK cycle time
30
tHIGH
ClK HIGH time
12
tlOW
ClKlOWtime
12
-
ClK slew rate
1
4
V/ns
tVAl
ClK to signal valid delay - bussed signals
2
11
ns
tVAl (ptp)
ClK to signal valid delay - pOint-to-point
2
12
ns
toN
Float to acitve delay
2
11
ns
28
ns
ns
ns
toFF
Active to float delay
tsu
Input set up time to ClK - bused signals
7
ns
tsu (ptp)
Input set up time to ClK - point-to-point
10
ns
tH
Input hold time from ClK
0
ns
tRST
Reset active time after power stable
1
ms
tRST-ClK
Reset active time after ClK stable
tRST-OFF
Reset active to output float delay
IOH(AC)
Switching current HIGH
100
(Test point)
VOUT = 3.1
Switching current lOW
\rOUT~2.2
- 44
1.4)
0.024
V OUT
0.023
VOUT = 0.71
-5 < VIN ~-1
11.9*(Vou-r-S·25)
*(VOUT+2.45)
rnA
-142
rnA
rnA
95
2.2> VOUT > 0.55
(Test point)
+ (VOUT -
-25
ns
rnA
-44
0
!!II:
GPSW1 GPSW2
MUXC
test pins
V001 toVoD4
VSS1 toVSS4
5,18,28,52
19,38,51,67
I
,
68
66
44
r
65
24
25
r
Co)
14 to 17
20 to 23 ..
CUV Oto
CU 1/7
6to 13
STATUS
REGISTER
SDA
SCL
RESN
45 to 50 53 54
40
:
41
12 C-BUS
CONTROL
3
~
I
55 to 62
~
~
r
3
::I
Q.
c:
-Ig. in&
5"S" is:<
-::J
CD a. 0
"'0
~~
~ ~
a
00. c:
CD 0
It
-0
(l)
(J)~
00.
CD
I
0
(J)O
00.
OUTPUT
INTERFACE
42
LUMINANCE
PROCESSOR
....
64
Y utput
(Y 7toYO)
U1 output
(U V7to UVO)
--
HREF
»~
-JJ
-I
FEIN
clock
r
37
status
t
I
"
:;-
i43\63
(l)
0
I\)
INPUT
INTERFACE
-
(J)
0'
s::g
SAA7151A
CHROMINANCE PROCESSOR
N
(f)
0-
•
aCo)
"'0
::J
'5'
Q.
1 1,2
COMPONENT PROCESSING,
SCART INTERFACE CONTROL,
FAST SWITCH INSERTION
CVB Oto
CV BS7
::::::r -"
(J)~
0-
Ci)
~~
»3
cO"
0
"j;
+5V
~O
;::+
.--
SYNCHRONIZATION
\26
29
\so
131
132
\39
RTCO
ODD
-----
CLOCK
LFCO
35
~
~
33
VSSA
,...
34
127
CREF
Ll27
V DDA
....
~
14
+5V
36
XTAL
XTALI
ICSA
GPSWO
HCL
HSY
VS
HS
"'0
MEH292
(J)
»
»
Fig, 1 Block diagram (application circuits see Figures 17, 18 and 19),
'"
....A,
01
....A,
III
~
3'
5'
III
-<
(f)
'0
(l)
Q,
::::!>
0
III
CI:
0
::I
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (OMSD2-SCART)
SAA71518
6. PINNING
SYMBOL
PIN
DESCRIPTION
SP
1
connected to ground (shift pin for testing)
AP
2
connected to ground (action pin for testing)
RESN
3
reset, active-LOW
CREF
4
clock reference, sync from external to ensure in-phase signals on the Y-, CUV- and YUV-bus
VOO 1
5
+5 V supply input 1
CUVO
6
CUV1
7
CUV2
8
CUV3
9
CUV4
10
chrominance input data bits CUV7 to CUVO (digitized chrominance signals in two's
complement format from a S-Video source (S-VHS, Hi8) or time-multiplexed
colour-difference signals from a YUV(RGB) source or both in combination)
CUV5
11
CUV6
12
CUV7
13
CVBSO
14
CVBS1
15
CVBS2
16
CVBS3
17
VOO 2
18
+5 V supply input 2
ground 1 (0 V)
VSSl
19
CVBS4
20
CVBS5
21
CVBS6
22
CVBS lower input data bits CVBS3 to CVBSO
(CVBS with luminance, chrominance and all sync information in two's complement format)
CVBS upper input data bits CVBS7 to CVBS4
(CVBS with luminance, chrominance and all sync information in two's complement format)
CVBS7
23
GPSW1
24
status bit output FSSTO or port 1 output for general purpose (programmable by subaddress OC)
GPSW2
25
status bit output FSST1 or port 2 output for general purpose (programmable by subaddress OC)
HCL
26
black level clamp pulse output (begin and stop programmable), e.g. for TDA8708A (ADC)
LL27
27
line-locked system clock input signal (27 MHz)
VOO3
28
+5 V supply input 3
HSY
29
hor.sync pulse reference output (begin and stop programmable), e.g. for gain adj.TDA8708A (ADC)
VS
30
vertical sync output signal (Fig.10)
HS
31
horizontal sync output signal (Fig.14; start point programmable)
RTCO
32
real time control output; serial increments of HPLL and FSCPLL and status PAL or SECAM
sequence (Fig.9)
XTAL
33
24.576 MHz clock output (open-circuit for use with external oscillator)
XTALI
34
24.576 MHz connection for crystal or external oscillator (TTL compatible squarewave)
April 1993
3-204
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA71518
SYMBOL
PIN
DESCRIPTION
VSSA
LFCO
35
analog ground
36
line frequency control output signal, multiple of horizontal frequency (nominal 6.75 MHz)
VOOA
37
+5 V supply input for analog part
VSS2
38
ground 2 (0 V)
ODD
39
odd/even field identification output (odd
SDA
40
12C-bus data line
SCL
41
12C-bus clock line
HREF
42
horizontal reference for YUV data outputs (for active line 720Y samples long)
= HIGH)
IICSA
43
set module address input of 12C-bus (LOW = 1000 101X; HIGH
CPI
44
clamping pulse input (digital clamping of external UV signals)
Y7
45
Y6
46
Y5
47
Y4
48
Y3
49
Y2
50
VSS3
51
ground 3 (0 V)
VOO4
Y1
52
+5 V supply input 4
53
YO
54
UV7
55
UV6
56
UV5
57
UV4
58
UV3
59
UV2
60
= 1000 111X)
Y signal output bits Y7 to Y2 (luminance), part of the digital YUV-bus
Y signal output bits Y1 to YO (luminance), part of the digital YUV-bus
UV signal output bits UV7 to UVO, part of the digital YUV-bus
UV1
61
UVO
62
GPSWO
63
port output for general purpose (programmable by subaddress aD)
fast enable input (active-LOW to control fast switching due to YUV data; HIGH =YUV high-Z
FEIN
64
MUXC
65
multiplexer control output; source select signal for external ADC (UV signal multiplexing)
FSO
66
fast switch and sync insertion output; gated FS signal from FSI or sync insertion pulse in full
screen RGB mode
VSS4
FSI
67
ground 4 (0 V)
68
fast switch input signal fed from SCART/peri-TV connector (indicates fast insertion of RGB signals)
April 1993
3-205
Philips ,Semiconducto(s Video Products
Prelimi,nary specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA71518
IICSA
UV1
HREF
UVO
SCL
GPSWO
FEIN
SDA
MUXC
ODD
V SS2
FSO
V OOA
FSI
SP
LFCO
SAA7151B
XTALI
XTAL
RTCO
HS
VS
HSY
V003
LL27
MEH293
Fig.2 Pin configuration.
7. FUNCTIONAL DESCRIPTION
Chrominance processing
System configuration
The 8-bit chrominance input signal
(signal "C" out of CVBS or VIC in
Fig.4a) is fed via the input interface
to a bandpass filter for eliminating
the DC component, then to the
quadrature demodulator. Subcarrier
signals from the local oscillator
(DT01) with 90 degree phase shift
are applied to its multiplier inputs.
The frequency depends on set TV
standard.
The SAA7151 B system processes
digital TV signals with line-locked
Clock in PAL, SECAM and NTSC
standards (CVBS or S-Video) as well
as RGB signals corning from a
SCAFH/peri-TV connector. The
different source signals, are switched,
if necessary matrixed·and converted
(Fig.3 and Table 1).
8-bit CVBS data (gigitized composite
video) and 8-bit UV data (digitized
chrominanceand/or time-multiplexed
colout-difference signals) are fed to the
SAA7151 B. The data rate is 27 MHz.
April 1993
The multipliers operate as a
quadrature demodulator for all PAL
and NTSC signals; it operates as a
frequency down-mixer for SECAM
3-206
signals.
The two multiplier output signals are
converted to a serial UV data stream
and applied to two low-pass filter
stages, then to a gain controlled
amplifier. A final multiplexed
low-pass filter achieves, together
with the preceding stages, the
required bandwidth performance.
The from PAL and NTSC originated
signals are applied to a comb-filter.
The signals, originated from SECAM,
are fed through a cloche filter (0 Hz
centre frequ$ncy), a phase
demodulator and a differentiator to
obtain frequency-demodulated
colour-difference' signals.
Preliminary specification
Philips Semiconductors Video Products
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA71518
+
~
II
II
~~
R
b:~
~rr
(J)~
G
B
B
sync
sync
TDA8446
..
VIDEO
SWITCH AND
MATRIX
,--+
LI
12c-bus
(select)
CVBS
..
CVBSIY
..
....
VIDEO
SWITCH
chroma
MUXC
CPI
GPSW1
from SCART interface SAA7151 B
~
lP
r.VBSlY/sync
ClK
FSI •
V
C.....
T
+5V
clamping
I FSO
sync
TDA8540
Lft[S~~ClP
CPO
~
HCl
_
S1
CSO
SW1
FS*
CPI
SW2
T~
j
~
t----
FS
~~
(CHROMINANCE) 0
so
MULTIPLEXER
R
G
I
~$
CUV(7- 0)
S
8-bitADC
and multiplexer
HCT4053
c
~
r---
TDA8709A
ADI
~
VO ..
ADI
TDA8708A
8-bitADC
(lUMINANCE)
0' CVBS(7-0)
t:.~
0
0
VIC
iG~iGB
V....
iClK
GPSW2
* fast SWitchinJ, of V signal for insertion
(UVare swit ed inside SAA7151B)
GPSW
MEH305·3
Fig.3 System configuration, RGB fast switch interface included (SCART).
The SECAM signals are fed after
de-emphasis to a cross-over switch,
to provide the both serial-transmitted
colour-difference signals. These
signals· are finally fed via the fast
switch to the output formatter stages
and to the output interface.
Chrominance signals are output in
parallel (4:2:2) on the YUV-bus. The
data rate of Y signal (pixel rate) is
13.5 MHz. UV signals have a data
rate of 13.5 MHz/2 for the 4:2.2
format (Table 2) respectively
13.5 MHzl4 for the 4:1.1 format
(Table 3)
April 1993
Component processing and
SCARl interface control
The 8-bit multiplexed colour-difference
input signal (signal CUV, Fig.1, out of
matrixed RGB in Fig.3) is fed via the
input interface to a chrominance stop
filter (UV signal only can pass
through; Figures 20 to 22). Here it is
clamped and fed to the offset
compensation which can be enabled
or disabled via the 12C-bus.
For matrixed RGB signals - the full
screen SCART mode and the fast
insertion mode (blanking/switching)
are selectable. The chrominance
stop filter is automatically bypassed
in full screen SCART mode.
3-207
Full screen RGBmode (SCART):
The CUV digital input signal (7-0)
consists of time-multiplexed samples
for U and V. An offset correction for
both signals is applied to correct
external clamping errors. An internal
timing correction compensates for
slight differences in timing during
sampling. The U and V signals are
delay-compensated and fed to the
output formatter. The format 4:2:2 or
4:1:1 is generated by a switchable
filter.
The control signals for the front end
(Figures 3 and 18) MUXC, status bits
FSST1, FSSTO (outputs GPSW2,
GPSW1).and FSO are generated by
the SAA7151 B.
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA71518
Table 1 SCART interface control (Fig.3)
MODE
CONNECTION
FSO GPSW GPSW MUXC
2
1
chroma output TDA8709A
ofTDA8446 selected CUV
(7-0)
toTDA8709A Input
luminance
fast switch
TDA8446
input selector
(via 12C-bus)
TDA8540
RGB
only
0
0
0
0
0
0
0
1
high-Z
VIN2
UN
sync (RGB)
sync (RGB)
VIC or
CVBS
only
0
0
0
0
1
1
0
1
C
VIN1
C
V (VIC) or CVBS V (VIC) or CVBS
Fast
switch
0
0
1
1
0
0
0
1
C
VIN2
O.5(C+U}1
O.5(C+V} V (VIC) or CVBS V (VIC) or CVBS
0
0
1
1
1
1
0
1
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
1
RGB
only
Fast
switch
Fast insertion mode:
Fast insertion is applied by
FSI pulse to ensure correct timing.
The RGB source signal is matrixed
into UV and inserted into tbe CVBS
or VIC source signal after two field
periods if FSI pulses are received.
The output FSO is set to HIGH
during a determined insertion
window (screen plain minus 6 % of
horizontal and vertical deflection).
Switch over qepends on the phase of
FSI in relation to the valid pixel
sequence depending on the
phase-different weighting factors.
They are applied to the original and
the inserted UV data (Figures
5 and 6)
The control signals for the front end
(Table 1) MUXC, FSO, status bits,
FSST1 and FSSTO (outputs GPSW2
and GPSW1) are generated by the
SAA7151B.
The amplitude of chrominance and
April 1993
not used
high-Z
VIN2
UN
V (RGB)
,sync (RGB)
not used
C
JVIN2
I
JO.S(C+V)
O.5(C+UV Y (RGB)
V (VIC) or CVBS
not used
colour-difference signals are scaled
down by factor 2 to avoid overloading
of the chrominance analog-to-digital
converter. The amplitudes are
reduced in the TDA8446 by signals
on lines GPSW2 and GPSW1.
Luminance processing
The luminance input signal, a digital
CVBS format or an 8-bit lUminance
format (S-Video), is fed through a
sample rate converterto reduce the
data rate to 13.5 MHz (Fig.4b).
Sample rate is converted by means
of a switchable pre-filter. High
frequencyconiponents are
emphasized to compensate for loss
in the following chrominance trap
filter. This chrominance trap fmer
(fo =4.43 MHz or fo =3.58 MHz
centre frequency 'selectable)
eliminates the most of the colour
carrier signal, therefore, it must be
bypassed for S-Video signals.
3-208
The high frequency components of
the luminance signal can be
"peaked" in two bandpass filters with
selectable transfer characteristic.
A coring circuit (±1 LSB) can improve
the signal, this signal is then added
to the original signal. A switchable
amplifier achieves a common DC
amplification, because the DC gains ,
are different in both chrominance
trap modes. Additionally, a cut-off
sync pulse is generated for the
original signal in both modes.
Synchronization
The I,uminance output signal is fed to
the synchronization stage. Its
bandwidth is reduced to 1 MHz in a
low-pass filter (sync pre-filter).
The sync pulses ,are sliced and fed
to the phase detectors to be ,
compared with the sub-divided clock
frequency. The resulting output
signal is applied to the loop filter to
~
~g
=
::J"'CC
<0
<0
(J)S:
(,)
0-
clamping
r
:~
OSCE
C VBS
~ ;TERFAC~
:~
JJc
CHROMINANCE
STOP FILTER,
r.:o
COMPENSATION
fo
~
DELAY
CO"P'NSAIDN
+-OFTS,IPBP
TIME
rco
(,)
r\)
....
CHRS
UVSS
CDPO
,"T'RPOLATION
C
QUADRATURE
BANDPASS
1-"+
D'MOD;LATOR
-+
r-.
LOWPASS
FILTER
GAIN
t- CONTROLLEC~
AMPLIFIER
<0
r
,
SEQUENCE
PROCESSOR
SAA7151B
rr
~
PLSE(7-0) SEOA
SESE(7-Q)
CDVI
~~ig(2~
CHROMINANCE
CCIR
SUVI
i
~
STANDARD
DETECTION
CD 0.
~Il>
Il> ""'"
00.
CD 0
-0
0~O
(J)~
00.
I\)
CD
.0
(J)O
00.
»~
~
24 GPl W2
25 G~:SW1
SCART
INTERFACE
CONTROL
1
'"
1
Y
(7-0
OFTS
COLO
OEDY
OEDC
OEHS
CHSB
PHASE
DEMODULATOR
AND
AMPLITUDE
DETECTOR
I
~~
I
65 MU XC
66
...-
DIFFERENTIATOR
r
OUTPUT
FORMATTER
AND OUTPUT
INTERFACE
::s Il>
-::s
F
l==,
UV
!
BURST GATE
ACCUMULATOR
I - ~L
42
,
CLOCHE
FILTER
(SECAM)
LOOP
FILTER
PI2
CKTO(4-0)
LFIS(2-1)
1
i
COMB FILTER
AND
SECAM
RECOM BINATION
i
LOOP
FILTER
PI1
o
~
11FF
CKTS (4-0)
CHCV (7-0) ____
i
LOWPASS
FILTER
t--t
h
f
•
FISE
DISCRETE TIME
OSCILLATOR (DT01)
AND DIVIDER
I
32
1
CGFX, AMPF(3-Q)
CHROMINANCE
HUEC(7-0)
FAST SWITCH
AND
WEIGHTING
UV
i
BYPS
YDELO
CDMO
F=!t
-f !:!".
-.~
I - - (7-(
UV
OFFSET
INPUT
C
»3
~44
1
SXCR
DE-EMPHASIS
F~(o
68 FSI
I--
FsL
FSST FSDL(2-0)
GPSI(2-1)
OFTS
FSIV
CDET+-
(J)
------- --------------------------------------------------------------------------------------- -1--------t,..l!ll"'I"'Ii
g.4(a)
'4-1
»
»
~
.....
(]I
.....
OJ
-u
~
3'
:5'
Ql
-;~~~T~~E 14-
CRYSTAL
CLOCK
GENERATOR
VNOI (1-0)
WIND
BOFL
BFON
FSEL
AUFD
VERTICAL
PROCESSOR - . FIDT
COUNTER
LINE-LOCKED
CLOCK
GENERATOR
~4CR.E.F
~
27 Ll2
-
HLCK
HPLL
VTRC
HLCK
HCLB (7-0)
HCLS (7-0)
HSYB (7-0)
HSYS (7-0)
HPHI (7-0)
IDEL (7-0)
I------i PROGD~~~ABLE ~
i
i
SCEN
OEVS
OEHS
LOOP
FILTER
::IJ
--I
(DT02)
l"IXT:
34 XTALI
DAC
IICSA 43
1
63
GPSWO
111
26
29
HCL HSY
30
VS
131
"tJ
~
36
39
3'
(J)
HS
ODD
LFCO
Fig.4(b) Detailed block diagram; continued from Fig.4(a).
MEHA295-1
»
»
.......
""""
CJ1
""""
to
5'
~!Il
~
"0
CD
~
n
~
0
:J
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
accumulate all phase deviations.
There are three groups of output
timing signals:
a. signals related to data output
signals (HREF)
b. signals related to the input signals
(HSY, and HCL)
c. signals related to the internal sync
phase
SAA7151B
second positive rising edge of the
clock LL27 synchronized by CREF.
All timings of the following diagrams
are measured with nominal input
signals, for example coming from a
pattern generator. Processing delay
times are taken between input and
data output, respectively between
internal sync reference (main counter
= 0) and the rising edge of HREF.
YUV-bus formats
4 : 2 : 2 and 4 : 1 : 1
The output signals Y7 to YO are the
bits of the digital luminance signal.
The output signals UV7 to UVO are
the bits of the digital colour-difference
signal. The frames in the Tables
2 and 3 are the time to transfer a full
set of samples. In case of 4: 2 : 2
format two luminance samples are
transmitted in comparision .to one U
and one V sample within one frame.
The time frames are controlled by
the HREF signal, which determines
the correct UV data phase. The YUV
data outputs can be enabled or set to
3-state position by means of the
FEIN signal. FEIN =LOW enables
the output; HIGH on this pin forces
the Y and UN outputs to a
high-impedance state (Fig,5).
Line locked clock frequency
All horizontal timings are derived
from the main counter, which
represents the internal sync phase.
The HREF signal only with its critical
timing is phase-compensated in
relationship to the data output signal.
Future circuit improvements could
slightly influence the processing
delays of some internal stages to.
achieve a changed timing due to the
timing groups band c.
The HREF signal only controls the
data multiplexer phase and the data
output sig nals.
The 1S-bit YUV-bus transfers digital
data from the output interfaces to a
feature box, or to the digital-to-analog
converter (OAC). Outputs are
controlled via the 12C-bus in normal
selections, or they are controlled by
output enable chain (FEIN, pin S4).
The YUV-bus data rate 13.5 MHz.
Timing is achieved by marking each
Table 2 for the 4 : 2 : 2 format (720
pixels per line). The quoted
frequencies are valid on the YUVbus. The time frames are controlled
by the HREF signal.
Table 3 for the 4 : 1 : 1 format (720 pixels per line). The quoted frequencies
are valid ori the YUV-bus. The time frames are controlled by the HREF signal.
OUTPUT PIXEL BYTE SEQUENCE
OUTPUT
YO (LSB) YO
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
YS
YS
Y7 (MSB) Y7
YO
Y1
Y2
Y3
Y4
Y5
YS
Y7 Y7 Y7 Y7
YO (LSB)
Y1
Y2
Y3
Y4
Y5
YS
Y7 (MSB)
YO
Y1
Y2
Y3
Y4
Y5
YS
Y7
YO
Y1
Y2
Y3
Y4
Y5
YS
Y7
YO
Y1
Y2
Y3
Y4
Y5
YS
Y7
YO
Y1
Y2
Y3
Y4
Y5
YS
Y7
YO
Y1
Y2
Y3
Y4
Y5
YS
Y7
YO
Y1
Y2
Y3
Y4
Y5
YS
Y7
VO
V1
V2
V3
V4
V5
VS
V7
UO
U1
U2
U3
U4
U5
US
U7
0
0
0
0
VS
V7
US
U7
0
0
0
0
V4
V5
U4
U5
0
0
0
0
V2
V3
U2
U3
VO
V1
UO
U1
0
0
0
0
VS
V7
US
U7
0
0
0
V7
UVO (LSB)
UV1
UV2
UV3
UV4
UV5
UVS
UV7 (MSB)
0
0
"2
V3
V4
V5
VS
V7
UO
U1
U2
U3
U4
U5
US
U7
1
2
3
4
5
Yframe
0
1
2
3
4
UV frame
0
UVO (LSB) UO
UV1
U1
UV2
U2
U3
UV3
UV4
U4
UV5
U5
UVS
US
UV7(MSB) U7
Yframe
o
UV frame
0
April 1993
.~
YO
Y1
Y2
Y3
Y4
Y5
YS
Y7
VO
V1
YO
Y1
Y2
Y3
Y4
Y5
YS
2
YO
Y1
Y2
Y3
Y4
Y5
YS
YO
Y1
Y2
Y3
Y4
Y5
YS
4
VO
V1
V2
V3
V4
V5
vs
LFCO is required in an external PLL
(SAA7157) to generate the line-locked
clock frequency LL27 and CREF.
YUV-bus, digital outputs
PIXEL BYTE SEQUENCE
3-211
0
0
4
YO
Y1
Y2
Y3
Y4
Y5
YS
Y7
YO
Y1
Y2
Y3
Y4
Y5
YS
Y7
0
0
0
0
0
0
0
0
V4
V5
U4
U5
V2
V3
U2
U3
0
VO
V1
UO
U1
5
S
7
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
Signal levels (Figures 11 and 12)
The nominal input and output signal
levels are defined by a colour bar
signal with 75 % colour, 100 %
saturation and 100 % luminance
amplitude (EBU colour bar).
CUV-bus input format
The CUV-bus transfers the digital
chrominance/colour-difference
SAA7151B
signals from the ADC to the
SAA7151 B (Fig.5; Table 1):
- normal mode for digital chrominance
transmission.
- UV colour-difference mode for
colour~difference signals UV (out of
matrixed RGB signals)
- FS mode (fast switch mode; UV
inserted into chrominance signal C
with addition of the two signal
spectra).
Ll27
HREF
.~",...,,:::{:=i{H~:(!I- - ~- ";" -: ---'-----+-~..;.---+---'"!"-' --,
A. /::/yj .
-;.: tHD
,1
i.-l
~\::;:;:;:'!j}.'=}:A~_+-~-----;.,_ _- - ! - _
... tOHHt-
YUV
,
-.: from 3-state :.-
:...! tsu:+FEIN
The RTCO output signal (Fig.9)
contains serialized information about
actual clock frequency, subcarrier
frequency and PAUSECAM
sequence. This signal may
preferably be used with the
frequency-locked digital video
encoder SAA7199B.
,
"
CREF
RlCc output
-~tos:'-,
:::::}}}}{{:{:{{{{{:}}:::::::::I::t:::~=~=~~
MEH548
Fig.5 Timing example of fast enable input (FEIN).
April 1993
3-212
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA71518
LL27 clock
LL13.5 clock
MUXC
J
J
I
0
2
/
\
'--
Normal mode (chrominance pixel byte sequence)
chrominance
]
co
X
X
C1
C2
X
C3
X
X
U3
X
C4
X
C5
X
V5
UV colour-difference mode (UV pixel byte sequence)
colourdifference
]
vo
X
•
valid colourdifference
UO
X
X
V1
U2
(1)
t
•
(1)
(1)
X
V1
V4
U3
X
V5
Fast switch mode (data insertion)
(V5 + C5)/2
CUV
valid CUV
X
X
(V1 +C1)/2
(U3 + C3)/2
•
(1)
(1)
X
(V5 + C5)/2
MEH332·2
Fig.6 CUV input formats.
(1) each second sample only after a MUXC change is taken for down-sampling to 13.5 MHz to reduce
cross-talk components between U and V signals.
April 1993
3-213
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA71518
aold + 1 new
new
118 old + 7/8 new
1/4 old + 3/4 new
318 old + 5/8 new
1/2 old + 1/2 new
518 old + 3/8 new
3/4 old + 1/4 new
718 old + 118 new
Note: in 4:2:2 format weighting
in 1/4 steps only.
old
T(n-2)
T(n)
T(n-1)
T(n+2)
T(n+1)
MEH307
Fig.7 Addition of weighted components.
FS
uv
fast switch weighting for 4:2:2 format
]
LL6.75
X X
ua, vo
U1, V1
0
I
I
I
4
2
I
5
4
I
I
I
I
I
6
8
9
10
11
FS
uv
12
I
I
I
I
13
14
15
16
fast switch weighting for 4:1:1 format
~
LL3.375
X
uo, vo
'{
U1,V1
3
0
I
LL27
~
U3, V3
2
1"
LL27
X
U2, V2
I
I
2
3
4
I
I
I
I
I
I
5
7
8
9
10
11
12
I
I
I
I
13
14
15
16
Fig.8 Weighting factors of fast switching for 4:2:2 and 4:1:1 formats.
April 1993
3-214
MEH308
Preliminary specification
Philips Semiconductors Video Products
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA71518
LL27
CREF
.---.f.'~
HREF
: start 01
~ &dive line
Byte numbers for pixels:
Y signal
SO/60 Hz
U and V signal
MEH297-'
LL27
CREF·
1-. ,,~~---------------
HREF
end 01
,
active line 1
Byte number for pixels:
Y signal
SO/60 Hz
U and V signal
MEH298-'
Fig.9 Line control by HREF in 4:2:2 format for 50 Hz and 60 Hz systems.
HIL transition
4 bits
5 bits
:~ 1:::nte~~tart): ~ in~~~~nt -.l Ire~:rve
:
,
RTCOa
•
OC: :
13
bits 13 to 0 :
0
bit
2120
i~~~~~~t
.
15 .
rese:e
.
5
\seq~uencebit (1)
:
1 0:
reserved (2)
/
'~IIIIIIIIIIIIIIm»~t@Jl_
0
4
(1) Sequence bit:
1
SECAM: 0 equals DB-line
1 equals DR-line
PAL:
0 equals (R-Y) line normal
1 equals (R-Y) line inverted
NTSC: 0 (no change)
8
14
19
1 - .- - - - - - - - - . .
time slot
(LL27/4)
t t i .i i t
valid
61
67
not valid
MEH34'-'
(2) Reserve bits: 236 for 50 Hz systems; 233 for 60 Hz systems.
Fig.10 RTGO timing.
April 1993
bits 21 to 0
10
.
3-215
Preliminary specification
Philips Semiconductors Video Products
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA7151B
LL27
:
: ~::
\....Ji"LJi
CREF
I
I
I
I
I
I
I
I
I
I
I
,
I
I
,
I
•
I
I
I
I
I
I
I
I
I
I
~:
4-
HREF
Byte numbers for pixel I:
I
I
i
:
'
,
,
:
~-----:
:
: stanof:
:
I
I
I
I
I
I
:
:
active
~ne
I
'I
:
:
Y signal
S0160 Hz
U and V signal
MEH21I7·1
LL27
CREF
~ ,,~----------------
HREF
end of
,
active line :
Byte number for pixels:
Y signal
SO/60 Hz
UandV signal
MEH2II8-1
Fig.9 Line control by HREF in 4:2:2 format for 50 Hz and 60 Hz systems.
HlL transition
(counter start)
RTCOf1lJjJJJ.·
(1) Sequence bit:
•..
.
5 b'
Its
HPLL
,
~ ::~~~n~ -.i: I:bit~
::
.
:
13
,0
4
8
0
2120
14
19
1 - '- - - - - - -• •
SECAM: 0 equals DB-line
1 Aquals DR-line
PAL:
0 equals (R-Y) line normal
1 equals (R- Y) line inverted
NTSC: 0 (no change)
FSCPLL
i~rement
bits 21 to 0
15
time slot
(LL27/4)
sequence bit (1)
~
10
iii iii
valid
.: \
:
5
1 0:
61
reserved (2)
~
67
not valid
MEH3041·1
(2) Reserve bits: 236 for 50 Hz systems; 233 for 60 Hz systems,
Fig.to RTCO timing.
April 1993
rese~e
~
ljlllllllllllillml~tro)l_
~ 128 docks
:
,
4 bits
reserve
,
3-216
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (OMSD2-SCART)
(a) lsI field
SAA71518
625
6
8
9
I
I
I
I
inputCV8S
HREF
VS
I
4=
ODD
(b) 2nd field
313
315
I
I
2x2lLl27
input CVBS
HREF
~
i'
·--1
VS
.1
ODD
ioll
71)( 21Ll27
2 x 21LL27
Fig.11 (a) Vertical timing diagram at 50 Hz.
MEH335·1
(a) 1 sl field
input CVBS
HREF
VS
I
ODD
(b) 2nd field
+ 2 x 21Ll27
263
264
265
266
267
268
269
270
271
I
I
I
I
I
I
I
I
I
inputCVBS
HREF
~ 59x2lLl27
VS
I
I
., loll
ODD
Fig.11 (b) Vertical timing diagram at 60 Hz.
April 1993
3-217
2 x 21Ll27
MEH336·1
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA71518
+127
1----------
+105
+100
+106
+95
+76
----r--------c
chrominance
01-----+---
0
U
V
component of
.52 I - - - - + - - - L .
·64
blanking level
·76
·91
·103
::::::::L::::::::::::::::: :::::::::::::-::::::
·91
·103
sync
~~: ~: =: : : :=: : : =: : : =: : :.~: ~=\:=: :-:=:,..,=..=. =.,..=,....=.,...=:.....=:..:.=: : : :=,.: ,:=: : : =: : : =': : .=.':-: =: : :~ =.=.=::::::=:.:::.=.:=====
·128
(b) CUV input signal range
(U and V out of RGB; in FS
mode ranges x 0.5).
(a) eVBS input signal range.
------l-------
+255 1 - - - - - - +235
~~==~============-==== ====
1----------
+127 1 - - - - - - -
+127 1 - - - - - - -
+100
+105
whi. 100 %
------- -------. blue 75 %
------- -------. red 75 %
luminance signal
output range
+0 1 - - - - + - - -
+ 128 1-----+----
V-component
output signal range
U·component
output signal range
-101
+12
t ______.
_______
yel!ow 75 %
-106
______
J_______.
cyan 75 %
------- -------. black
0'-------
(c) Voutput signal range.
-128
-128 ' - - - - - - -
(d) U output signal range (B-V).
(e) Voutput signal range (R-V).
MEH299-3
Notes: 1. All levels are related to EBU colour bar.
2. Values in decimal at 100 % luminance and 75 % chrominance amplitude.
Fig.12 Input and output signal ranges in DTV mode (digital TV).
April 1993
3-218
Preliminary specification
Philips Semiconductors Video Products
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA7151 B
+127 f - - - - - - - - - -
+127 f - - - - r - - - - - - - - - - - - - _lreserved
+106
+95
-:--:--,"~[~I:--:-----:----:--------------r--------- ~~
100 %
50 Hz mode
chrominance
50 Hz mode
~ -:::::r::::::::--j----j-------
chrominance
60 Hz mode
C
chrominance
u
v
component of
-52 f - - - - f - - - - . L -64
blanking level
-91
-103
:;:
:::: :::1:::::::::::::::::: :: ::::: :::::: -:: ::::
_: : : : : : : :rI~
j
-128 f - - - - - - - - - -
(b) CUV input signal range
(U and V out of RGB; in FS
mode ranges x 0.5).
(a) CVBS input signal range.
+255 f - - - - - - -
+255 f - - - - - - -
+255 f - - - - - - -
+212
+212
+235
------- -------- blue 75 %
------- -------- red 75 %
luminance signal
output range
+128 f - - - f - - -
+128 I - - - - f - - -
+128 f - - - - - t - - -
U-component
output signal range
+44
+16
______ J________
V-component
output signal range
yellow 75 %
+44
______ J________
cyan 75 %
------- -------- black
0'-------
(c) Youtput signal range.
(d) U output signal range (B-Y).
(e) Voutput signal range (R-Y).
MEH300 -3
Notes: 1. All levels are related to EBU colour bar.
2. Values in decimal at 100 % luminance and 75 % chrominance amplitude.
3. For SECAM input signals the CCIR levels will be exceeded.
Fig.13 Input and output signal ranges in CCIR mode.
April 1993
3-219
Preliminary specification
Philips Semiconductors Video Products
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA7151B
cves
+
HSY
: :size ~LL27
prog~~:,ing + 191
(stetr~~)
:1 ~
~
:
+
HCL
HCL
programming
range
+ 127
(step size:
~LL27)
-128
i, 0
L---J'L
.------?/
+
'
,
,
1
~.r-- 83,5X2llL27(~)
~
:
:011
.: 4 x 2ILL27 (SO Hz) HREF
..
: : : lOx 2JLL27 (60 Hz)
posnlon
+235
V-output
-64
~"-(.;.---..,...-----~J-::0_ _ _ _ _ _ _ _--11
::~':6::t::::::::::::::::::::+::::::bt--m-m _ -mn-mm7r--------J/
,
HREF
,
:
:
,
. .719!
- - - - - 720x2JLL27,
F
,
.,011
16 x2JLL27 (SO Hz)
: 12 x 2ILL27 (60 Hz)
:+-----+:
:
HS
-----1+
,
i4
HS
~~9~a:z~~ntr.a~~)
+431
144 x 2JLL27 (SO Hz)
138 x 2ILL27 (60 Hz)
HREF length lix
i,
'
64 x2ILL27
:0
-432
----7.j~~(-~'------'----------------~#_____1
t-I
(1) the processing delay will be influenced in future enhancements
MEH549
Fig.14 Horizontal sync and clamping timing for 50/60 Hz
(signals HSY, HCL, HREF and HS).
April 1993
,
.,4
3-220
Preliminary specification
Philips Semiconductors Video Products
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA7151B
8. LIMITING VALUES
In accordance with the Absolute Maximum Rating ystem (IEC 134); ground pins 19,
35, 38, 51 and 67 as well as supply pins 5, 18, 28, 37 and 52 connected together.
SYMBOL
VOO
PARAMETER
supply voltage (pins 5, 18, 28, 37, 52)
MIN.
MAX.
-0.5
7.0
VdiffGNO difference voltage Vss A - V SS(1 to 4)
UNIT
V
±100
mV
VI
voltage on all inputs
-0.5
V oo+0.5
V
Va
voltage on all outputs (10 max = 20 mA) -0.5
VO o +0.5
V
Ptot
total power dissipation
-
2.5
W
T stg
storage temperature range
-65
150
°C
Tamb
operating ambient temperature range
0
70
°C
V ESO
electrostatic handling* for all pins
±2000
V
9. CHARACTERISTICS VOO
SYMBOL
= 4.5 to 5.5 V; Tamb = 0 to 70°C unless otherwise specified.
PARAMETER
VOO
supply voltage range (pins 5, 18,28,37,52)
100
total supply current (pins 5, 18, 28, 37, 52)
CONDITIONS
MIN.
4.5
VOO =5 V; inputs LOW;
outputs not connected
MAX.
TYP.
UNIT
5
505
V
100
250
mA
V
12C-bus, SDA and SCL (pins 40 and 41 )
VI L
input voltage LOW
-0.5
1.5
V IH
input voltage HIGH
3
Voo +0.5 V
140 ,41
input current
lACK
output current on pin 40
acknowledge
3
±10
VOL
output voltage at acknowledge
140
=3 mA
-
-
IlA
-
mA
0.4
V
0.6
V
Data, clock and control inputs (pins 3, 4, 6 to 17,20 to 23,27,34,64 and 68); Figures 12 and 13
VI L
LL27 input voltage (pin 27)
V IH
VI L
other input voltages
V IH
Ileak
input leakage current
C1
input capacitance
LOW
-0.5
HIGH
2.4
LOW
-0.5
HIGH
2.0
data inputs; note 1
I/O high-impedance
clock inputs
tSU.OAT
input data set-up time
tHO.DAT
input data hold time
-
Fig.15
11
3
-
V oo +0.5 V
0.8
V
Vo o +0.5 V
10
IlA
8
pF
8
pF
10
pF
-
ns
ns
* Equivalent to discharging a 100 pF capacitor through a 1.5 kil series resistor.; inputs and outputs are protected
against electrostatic discharge in normal handling. Normal precautions appropriate to handle MaS devices is
recommended ("Handling MaS Devices").
April 1993
3-221
Preliminary specification
Philips SemiconductorS Video Products
Digital mul,tistandard colour decoder
with SCART interface (DMSD2-SCART)
SYMBOL
PARAMETER
SAA71518
CONDITIONS
MIN.
TYP.
MAX.
UNIT
YUV-bus, HREF and VS outputs (pins 30,42,45 to 'SO and pins 53 to 62), Figures 9 and 12 to 13
VOL
VOH
CL
0
-
output voltage HIGH
,2.4
load capacitor
15
-
1.4
1
output voltage LOW
notes 1 and 2
0.6
V
Voo
V
50
pF
-
2.6
V
-
Voo
V
-
0.6
V
Voo
V
25
pF
-
-
ns
-
ns
-
ns
-
Hz
LFCO output (pin 36)
Vo
output signal (peak-to-peak value)
V3S
output voltage range
note 2
Control outputs (pins 24 to 26, 29, 31, 32, 33, 39, 63; 65 and 66); Fig.11, 14 and 15
VOL
output voltage LOW
VOH
output voltage HIGH
2.4
CL
load capacitor
7.5
Timing of YUV-bus and control outputs
toH
. output signal hold time
notes 1 and 2
0
Figures 9 and 11
YUV, HREF, VS
at CL =15 pF;
13
controls at CL =7.5 pF 13
tos
output set-up time
YUV, HREF, VS
at CL =50 pF;
controls at CL =25 pF
20
tsz
data output disable transition time
to 3-state condition
22
tzs '
data output enable transition time
from 3-state condition
20
-
±400
-
20
ns
ns
ns
Chrominance PLL
fc
catching range
Crystal oscillator
Figures 17 and 18; note 3
-
24.576
-
MHz
-
±50
10-6
±20
10-6
temperature range Tamb
0
70
°C
load capacitance CL
8
-
-
pF
series resonance resistance Rs
-
40
80
n
fn
nominal frequency
~f Ifn
permissible deviation fn
X1
crystal specification:
3rd harmonic
temperature deviation from fn
motional capacitance C1
parallel capacitance Co
April 1993
3-222
1.5±20% -
fF
3.5±20% -
pF
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SYMBOL
PARAMETER
cycle time
tp
duty factor
tr
rise time
tf
fall time
MIN.
CONDITIONS
Line locked clock Input LL27 (pin 27)
tLL27
SAA71518
TYP.
MAX.
UNIT
Fig.S and 15
note 4
35
-
39
ns
tLL27H It LL27
40
50
60
%
-
-
5
ns
6
ns
Notes to the characteristics
1. Data output signals are Y7 to YO and UV7 to UVO. All other are control output signals.
2. Levels are measured with load circuit. YUV-bus, HREF and VS outputs with 1.2 k.Q in parallel to 50 pF at 3 V (TIL load);
LFCO output with 10 kn in parallel to 15 pF and other outputs with 1.2 kn in parallel to 25 pF at 3 V (TTL load).
3. Recommended crystal: Philips 4322 143 05291.
4. tsu, ~o, toH and too include tr and It·
Table 4 High-impedance control for YUV-bus (Fig.15)
OEDY
OEDC
FEIN
Y(7:0)
UV(7:0)
0
0
1
1
0
Z
Z
Z
active
X
X
0
0
0
0
1
Z
Z
Z
April 1993
1
0
1
Z
Z
active
3-223
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA7151B
;..
clock input LL27
~,
t LL27
tLl""R
v,'::
_____--'iT
E~;~
11'
--------J
1......
-.i
tsu : tHO
tf
:.-
i
--.:
:.-.~
O.6V
t' :.-
i'
:
~!:m::
input data
,,
,
,,
,
:,
inputCREF
,,
,
:,
~
,:
illl
tzs
tHD
~:
i
~:~=:::
: . - - tsz
~
~~AP~
input FEIN
~:..
tsu:
i~~
output data
M:::
,~~~!
tsu
i
tHD
l x=:::
MEH550
Fig.15 Data input and output timing diagram.
24.576 MHz
(3rd harmonic)
'oF
r
X1
""
,,,H
±20%
c!s
T
XTAL
12 PF ±
33
XTAL
-
33
SAA7151B
SAA7151B
XTALI
34
JUU~
34
12 PF:±
>'
(b)
(a)
MEH302·1
Fig.16 Oscillator application (a) and optional clock from external (b).
April 1993
3-224
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA71518
CPI
VSS
III
+-::--:--::1111-<,.-._15
0.111FII
67 51 38 19
W
0.111FII
lli:';
+5 V
chrominance
CUV7 to CUVO
I T
X1:
Philips 432214305291
52
1
12pF
;;;r
CUVO 6
7
48
~8
~9
~10
.9dY§. 11
~12
..£b!YZ. 13
r--Y1
45
r---YZ
32 f--_ _ _...:.R.:..:.T::::CO~
31 I-_ _ _---:..:.HS:::.-,~
SAA71518
~----H"""'V:::;...Y-I...~
14
29~----=~~
..bl- 15
1L- 16
..!d- 17
26 I-_ _ _....:HC=.::L-.
42 ~-----!..!!HR"",E,-F•
41 ....._ _ _ _""'SCC""')L_ _ ~ C-bus
40~----=SO~A~~
39 1-_ _ _ _0""0""0'--.
63 ~----,G..........
PiSW",O....
64 ~_ _ _....:Fc.::E::.:..IN,-'"
43 14-_ _ _-""IIC"'-SA"(from SCART)
2~--....,
~20
~21
~22
~23
+--~~--_I~__i34
11----.
=~
4
2425
36
~
35 VSSA
37 VO A
~ 27
-
65
66
FSI
LFCO
+5V
II
II
0.111F
digital
MUXC
2.211H
FSO
GPSW1
11 0. 1 11 F
II
1O-,I1'-.F--.
2 1-........
l_+---c:-:--::-_+,;'nllt110.1 I1F UI
-11
5-,
-19
-16
31----.U
-=-:....<::..:..----.
III
-~l~
f> 13 MHz
I
Vooanalog +5 V
41----------lli
....~anaI09
GPSW2
1~
~R~E~S~N_+-+-~_ _ _ _ _~12
~=L~=7~A~_+-+-_ _ _ _ _---I7
1
Voo
dig~al
+5 V
1-
~C~R~E~F____' -________'15
6 9 13 -
_ _ _ _ _ _ _ _ _ _~10
_ _ _ _ _ _ _ _ _~14
~L=L~13~B_ _ _ _ _ _ _ _ _'20
~L=~~7~B
~L=L~13~A
'=:=
==
0.1 I1F
18~.......-
3-225
0.1 I1F
-...
Fig.17 Application of SAA7151 B.
April 1993
BAT45 150
~n.l-:·:\ ~i ~
68
1nF*
!'.i~
FS
Tdig~al
~ 3
~ 12pF
10 I1H~'
Y7 to YO
YO
47~
46~
30
LO
YUV-bus
53~
50~
49~
~24.576MHZ
~
r--!!Y1
54
---.------~-_i33
X1
61
55~
~
Voo
.9:!Y1
luminance
CVBS7 to CVBSO
UVO
59~
58~
57~
56~
._----1111-~~ 28
0.1I1 F "
digital
62
60~
II
~0-.1-I1:::1FIIHW---"'---I18
._---,,-1IIIII-~~
uvo
UV7 to
44
~~digital
MEH328·
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
2.21l H
+12V
~
.
8
t3
CI)
~
18
-4
17
5
16
1 o',~
.. IlF
1 O.,~IlF
..
B
75n
~
G
fi4
E
,g
19~~
3
II
a:
R
n-:
15
7
14
-8
13
J O.~ iJF
.
~
TO.1IlF
+12V
p
U signal
Y signal
V signal
GPSW2
FSO
CVBS/Y
toSM7151B
O'I~ iJF
I
TDA8446
6
II
~
0. 15 1l F
4.71l F
1 nF
§
20
2
In+
75n~
U
1
sync
I-
sync
1 L
4.7 kn [)
~
SAA71518
-9
C
O,!. iJF
12
II
C signal
11
10
chrominance
bandpass filter
HCl
~-----,i-----;
47
kn
l
OiLJ
'
l'i
:
1 :
I ,--------- t-!
~
~
GPSW1
ClO
-c::J1kn
SCl
SCl
12C-bus
SDA
SDA
(to SM7151 B)
750
U
1
unused signal
outputs
'-- 2
20H
10 kn
-c::J-r
191---
+5
1~
'"L-.J'
18
3
m+
17
4
u
~
~
150n
~
audio so urce
contr01
r
22 iJF
-
750
~
C
(chrominance)
~
CVBS
~
Y
..
TDA8540
6
o.~ iJF
J
0,,1 iJF
.
.
150
22 iJF
15
on
r-r+llH
C
14
..-7
1
75n
-c::::J.
16
5
O.~ iJF
[
8
13
9
12 -
10
11
22n
==
Vp
0.1 iJF
~
~
"9
+8V
10,'
[ 22n
f
~
7808
stabilizer
.."
~
) 1.6 kn
220pF
H~
O.~ IlF
II
Fig.18 Application of input signal selecting (SCART interface).
April 1993
3-226
330n
...ts
-c::J- ~
MEH330·4
»
"0
2:
GPSWI
to pin 8
<0
GPSW2
~
~.-f--+-""3
MUXC
11
HeT
2 MHz lOW-pass filters
~
4053
U signal
from pin 17
I ko
~
00.
II~
~'8
,g
.
CUV{7-O)
12r
VINII
(l)S=
g
S
en
~~
:::J Sll
<
131 CUVO
~
-6'
::Dc
141--
15
J.
«
I kO
""0
~9.
CC
n
J'kO
o1220
II CUV7
)I~O
CPI
'---
CVBS{7-0)
I ' CVBS7
""0
HCl
en
[15.60
+5 V (digital supply)
HSY
~
......
-'"
UV gain level for CCIR
Fig.19 Application circuit analog-to-digital conversions.
MEH329-6
01
-'"
{D
~
3'
S"
III
--....'
~~
.~
'43h
",,
0
\\
-6
-12 I - f -
43h
....
~
Ii
~
63h
W
~~
53h
~&.
73h
~~
r-
rt
60 Hz NTSC;
pre-filter on
I---f-
-18
-24
-30
o
2
3
4
5
fy(MHz)
6
7
Fig.27 Maximum luminance peaking control as a function of four different aperture centre frequencies
controllable by subaddress byte 06; aperture factor 1; coring off; chroma trap on; pre-filter on ;
and bandfilter on.
MSH3l4
18
12
43h,
Vy
(dB)
---- -
6
,.-- ~h
/42h
~~
/
........
41h
:-.......
/'
~ ,,\
"\.\\'
,
,\1
-6
-12
-
~
~41h
-
/:..
JV'Aah
42h/
I
40~ ~\
-
,,--- .....................
IV/", II."
V
K..'
~~
-
60 Hz NTSC;
pre-filter on
-18
-24
.
-30
o
2
3
4
fy(MHz) 6
7
Fig.28 3.8 MHz luminance peaking control as a function of four different a.perture factors controllable by
subaddress byte 06; coring off; chroma trap on; pre-filter on and bandfilter on.
April 1993
3·238
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA7151B
MEH315
18
/23h
12
33h ,
Vy
(dB)
.L~
./'"
...
~V
~ ~
6
~
13h
,
\\\
-6
f----I-
60 Hz NTSC;
pre-filter off
-
-~
~~
~ i-"""
~
03h
-12 f - - - - r
i . - 03h
13h
...... ~ "'~
...... ,,~
r--
'r/'
fl./'
,
~
23h-
. \33h
"
-18
-24
-30
o
4
5
fy(MHz)
7
6
Fig.29 Maximum luminance peaking control as a function of four different aperture centre freQuencies
controllable by subaddress byte 06; aperture factor 1; coring off; chroma trap on; pre-filter off ;
and bandfilter on.
MEH316
18
12
Vy
(dB)
--
6
~
0
...........
~
OO~
-6
-12
03h.
-....
......
"
'"
"
01h/
r---- -:-
60 Hz NTSC;
~-
pre-filter off
·18
/
~h
02h
1//i"'"' 01h
ooh _
Jf/ V
/
./
,}2h
'\.
\.\
~\\
['\ \'
'V /V
-
"
..... ~
:::!Ii'"
-
,/
'V
\,
\
I
-24
-30
U
..
o
2
fy(MHz)
6
7
Fig.30 4.1 MHz luminance peaking control as a function of four different aperture factors controllable by
subaddress byte 06; coring off; chroma trap on; pre-filter off and bandfilter on.
April 1993
3-239
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
Vy
(dB)
18
~~--~~~~~~--4--
12
~~--r,~~~~~--4-~
SAA7151'B
Vy
(dB)
50 Hz S-Video ;
chroma trap off
·6
o
2
12~~~~~~~+-~--~~
50Hz S-Video;
chroma trap off
·6
6
8
2
4
6
fy(MHz)
Fig.32 2.6 MHz luminance peaking control control as
a function of four different aperture factors
controllable by subaddress byte 06;
pre-filter off; coring off and bandpass filter on.
Fig.31 4.1 MHz luminance peaking control control as
a function of four different aperture factors
controllable by subaddress byte 06;
pre-filter off; coring off and bandpass filter on.
MEH320
24
Vy
(dB)
MEH319
24
18
Vy
18
(dB)
12
12
6
6
60 Hz S-Video;
chroma trap off
-6
o
.12
2
4
60 Hz S-Video;
chroma trap off
·6
6
8
L---L.._ _L--1-----l_ _...L.---I__....L.-......J
o
fy(MHz)
2
4
6
8
fy(MHz)
Fig.34 2.6 MHz luminance peaking control control as
a function of four different aperture factors
controllable by subaddress byte 06;
pre-filter off; coring off and bandpass filter on.
Fig.33 4.1 MHz luminance peaking control controias
a function of four different aperture factors
controllable by subaddress byte 06;
pre-filter off; coring off and bandpass filter on.
April 1993
8
fy(MHz)
3-240
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA7151B
MEH321
18
MEH322
18
Vy
83h
12
V
(dB)
6
/'"
82h
l:::::I--te1h
./' r..,.....--' J......-t-'
Vy
12
. .v ~
(dB)
~p- p
BOh
~
~ to--""1 l88h
89h
50 Hz Y/C;
all filters off
-6
60 Hz Y/C;
-6
all filters off
-12
-12
-18
2
4
6
-18
8
fvlMHzl
o
2
4
6
8
Fig.3S 4.1 MHz luminance peaking control in
so Hz I S-VHS mode as a function of four
different aperture factors controllable by
subaddress byte OS.
Fig.35 4.1 MHz luminance peaking control in
50 Hz I S-VHS mode as a function of four
different aperture factors controllable by
subaddress byte os.
B3h
Vy
(dB)
12~-W~~4--+~~~--~~
-6 f---+----4
60 Hz Y/C;
-61---+--+ bandfilter on +--+---i
50 Hz Y/C;
bandfilter on
-12
2
L--L._L-.--L---IL---1---I_-1-_
o
8
4
fy(MHz)
6
8
fy(MHz)
Fig.38 Maximum luminance peaking control in
so Hz I S-VHS mode as a function of four
aperture centre frequencies controllable by
subaddress byte os.
Fig.37 Maximum luminance peaking control in
50 Hz I S-VHS mode as a function of four
aperture centre frequencies controllable by
subaddress byte os.
Purchase of Philips' 12C components conveys a license under the
Philips' 12C patent to use the components in the 12C-system
provided the system conforms to the 12C specifications defined
by Philips.
April 1993
4
3-241
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder
with SCART interface (DMSD2-SCART)
SAA71518
11. PROGRAMMING EXAMPLE
Coefficients to set operation for application circuits Figures 17, 18 and 19. Values recommended for PAL CVBS input
signal and 4:2:2 CCIR output signal (all numbers of the Table 6 are hex values).
Table 7 Recommended default values (note 1)
SUBADDRESS
BIT NAME
FUNCTION
VALUE (HEX)
00
01
02
IDEL(7-0)
HSYB(7-0)
HSYS(7-0)
increment delay
horizontal sync HSY begin
horizontal sync HSY stop
4D
3D
OD
03
04
05
HCLB(7-0)
HCLS(7-0)
HPHI(7-0)
horizontal clamping HCL begin
horizontal clamping HCL stop
horizontal sync after PHI1
F3
C6
FB
06
BYPS, PREF, BPSS(1-0)
BFBY, CORI, APER(1-0)
luminance bandwidth control:
02 (note 2)
07
HUEC(7-0)
hue control (0 degree)
00
08
CSTD(2-0), CKTQ(4-0)
miscellanous controls #1
09
09
OSCE, LFIS(1-0),CKTS(4-0)
miscellanous controls #2
CO
OA
PLSE(7-0)
PAL switch sensitivity
4D
OB
SESE(7-0)
SECAM switch sensitivity
40
OC
FSAU, GPSI(2-1), CGFX,
AMPF(3-0)
miscellanous controls #3
80
OD
COLO, CHSB, GPSWO,
SUVI, SXCR, FSDL(2-0)
miscellanous controls #4
60
OE
CCIR, COEF, OEHS, OEVS
UVSS, CHRS, CDMO, CDPO
miscellanous controls #5
B4
OF
AUFD, FSEL, HPLL, SCEN,
VTRC, MUIV, FSIV, WIND
miscellanous controls #6
9F
10
ASTD, OFTS, IPBP, CDVI,
YDEL(3-0)
miscellanous controls #7
CO
11
CHCV(7-0)
nominal chrominance gain
4F
12
OEDY, OEDC, VNOI(1-0),
BFON, BOFL(2-0)
miscellanous controls #8
C2
Notes to Table 7
1 Slave address is 8A (hex) at IICSA =LOW or 8E (hex) at IICSA = HIGH.
2 Dependent on applications (Figures 23 to 38)
April 1993
3·242
Philips Semiconductors Video Products
Preliminary specification
Digital video comb filter (DCF)
1. FEATURES
• Comb filter circuit for luminance
and chrominance separation
• Applicable for standards
PAL BIG, M and N
PAL 4.43 (525 lines; 60 Hz)
NTSC M and N
NTSC 4.43 (50 and 60 Hz)
• Luminance and chrominance
bypasses with short delay in case
of no filtering
• Line·locked system clock;
CC IR-compatible
• 12C-bus controlled
SAA7152
2. GENERAL DESCRIPTION
The CMOS digital comb filter circuit
is located between video analog-todigital converters and the video
multistandard decoder SAA7151 B
(not applicable for SAA7191 B). The
two-dimensional filtering is only
appropriate for standard signals from
a source with constant phase
relationship between subcarrier
signal and horizontal frequency. The
comb-filter has to be switched off for
VTR signals and for separate VBS
and and C signals. In VCR and
S-Video operation the luminance
3. QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
V DD
supply voltage (pins 11, 34, 44)
Ip
total supply current
4.5
TYP.
MAX.
5.0
5.5
V
85
180
mA
Vi
input levels
TTL -compatible
Vo
output levels
TTL -compatible
LL27
typical system clock frequency
Tamb
operating ambient temperature
range
27
0
UNIT
-
MHz
70
°C
4. ORDERING INFORMATION
EXTENDED
TYPE NUMBER PINS
SAA7152
May 1993
44
PACKAGE
PIN POSITION
PLCC
MATERIAL
CODE
plastic
SOT187
3-243
low-pass and the chrominance
bandpass parts can still be used for
noise reduction purposes.
The processing delay is
21 x LL27 clocks in active mode or
3 x LL27 in short delay bypass
mode (BYPS = 1).
Philips Semiconductors Video Products
Preliminary specification
Digital video comb filter (DCF)
SAA7'152
5. BLOCK DIAGRAM
+5V
I
VOOD1
SAA7152
NLlNi~
LINE
DELAY 1
r
- .......
CLOCK
BUFFER
B~~¥~~~S
-+ clk
f-
12C-bus
SDA
23
t
SCL
24
12C-BUS
CONTROL
----.
LOW-PASS
FILTER
J
4-
--.
121
122
I
JJp
ADDER
AND
LIMITER
~AP
~
DESCRIPTION
1
reset input; active-LOW
LL27
2
line-locked system clock input (27 MHz)
CINO
3
S
CIN3
6
CIN4
7
CINS
8
CIN6
9
CIN7
10
May 1993
'-YCMB
112,33,43
RESN
4
i~LlN,
LLEN
14-
6. PINNING
CIN1
CO UT(7-0)
__ COMB FILTER
LOGIC
(MED)
~_
CCMB,
TAPS
VSS01 to V SS03
Fig.1 Block diagram.
CIN2
35 to 42
chrominance bvoass
[1
RESN
PIN
REGISTER
1 1
~ TAPS,
CFRQ
control bits
SYMBOL
MULTIPLEXER
LINE
DELAY 2
C~RQ
.
YOU T(7-0)
OUTPUT
INTERFACE
...
r--
2
25 to 32
1
10103
jCSEL
LL27
BYPS
BANDPASS r-FILTER 1
I luminance bVDass
INPUT
INTERFACE
+
~CFRQ
LLEN
CVBS(7 -0) 20 to 13
CIN(7-0)
to VOOO3
1 11 ,34,44
chrominance input data bits CINO to CIN7
3-244
MEH423-1
Philips Semiconductors Video Products
Preliminary specification
Digital video comb filter (DCF)
SYMBOL
PIN
SAA7152
DESCRIPTION
V OO1
11
+5 V supply input 1
V SS1
12
ground 1 (0 V)
CVBSO
13
CVBS1
14
CVBS2
15
CVBS3
16
CVBS4
17
CVBS5
18
CVBS6
19
CVBS7
20
CVBS input data bits 0 to 7
SP
21
connected to ground (shift pin for testing)
AP
22
connected to ground (action pin for testing)
SDA
23
12C-bus data line
SCL
24
12C-bus clock line
YOUT7
25
YOUT6
26
YOUT5
27
YOUT4
28
YOUT3
29
YOUT2
30
YOUT1
31
YOUTO
32
V SS2
33
ground 2 (0 V)
V OO2
34
+5 V supply input 2
COUT7
35
luminance (Y) output data bits 7 to 0
COUT6
36
COUTS
37
COUT4
38
COUT3
39
COUT2
40
COUT1
41
COUTO
42
VSS3
43
ground 3 (0 V)
VOO3
44
+5 V supply input 3
May 1993
chrominance (C) output data bits 7 to 0
3-245
Preliminary sPecification
Philips Semiconductors Video Products
Digital video comb filter (DCF)
SAA7152
YOUT5
YOUT6
YOU17
VSS3
VOD3
SAA7152
RESN
~~~52
000
0
Biii~~~~i
>
~
>
~
~
~
~
Fig.2 Pin configuration.
CVBS
y
ADC
TDA8708A
f----+
YOUT(7-0)
CVBS(7-0)
CVBSIY
DMSD
DCF
L
DIGITAL
VIDEO
COMB
FILTER
CHROMA
SAA7152
ADC
UV
YUV
SAA7151B
TDAB709A
-r-+
CIN(7-0)
COUT(7-0)
LL27
i
clock
CUV
CREF
LL27
LFCO
i
CGC
SAA7157
MEH563
Fig.3 System environment.
May 1993
3-246
----+
Philips Semiconductors Video Products
Preliminary specification
Digital video comb filter (DCF)
SAA7152
7. 12C-BUS FORMAT
_S---I-I_SL_Pl._~E_A_D_D_R_ES_S-,I_A...&.1_S_U_BA_D_D_RE_S_s...&.I_A-...L_D_A_JA_O_L....-A.....I.1~~~~~~ ....L-_D_A_JA_n-...L_A----II_p----I
1
.....
S
start condition
1011 0010 (B2 h)
acknowledge, generated by the slave
subadress byte (Table 1)
data byte (Table 1)
stop condition
SLAVE ADDRESS
A
SUBADDRESS*
DATA
P
x
readlwrite control bit
X =0, order to write (the circuit is slave receiver) .
X =1, order to read (the circuit is slave transmitter)
* If more than 1 byte DATA are transmitted, then auto-increment of the subaddress is performed.
Table 1 12C-bus; subaddress and data bytes for writing (after X =0 in address byte)
FUNCTION
SUBAOORESS
Controls
00
07
05
06
BYPS CSEL
DATA
04
I 03
CCMB VCMB
I TAPS
02
01
CFRO NUN
DO
LLEN
Function of the bits of Table 1:
Select bypass with a short delay; all other functions are disabled:
BVPS
o = no bypass; 1 = comb filter bypassed (delay is 3 LLC)
1-'_._'-'-'-'-'-'- ._._._._._._._._._._._._._._ . ..;..._._._._._._.-._._._._.-._._.CSEL
Input mode select
0
CCMB
Select comb filtering: 0
1
= CVBS selected;
1
= V/C selected
1-._._._._._._._.- ._._._._._._._._._._._._._._._._._._._._._.-._._._._.-._._.-
= chrominance is bandpassed;
= chrominance is comb-filtered
1-._._.-._'_._._.- ._._._._._._._._._._._ . .....;..-._._._._._._._._.-._._._._.-._._.VCMB
Enable chrominance substruction from CVBS signal:
o = disabled, CVBSIY signal is only low-passed
1 = enabled (chrominance trap or comb filtering)
1-._'-'-._._._._.- ._._._._._._.-.-._._._._.-._._._._._._._._.-._._._._.-._._.TAPS
Selects tap for switching V and C to adder:
o = for bandpass/low-pass combination
1 = for comb filter active
1-'_._------------ -----------------_._-_.-._-_._---_._._._._.-._.-._._.-._.-.CFRO
Select centre frequency and matching factor of chrominance filter:
o = 4.43 MHz;
1 = 3.58 MHz
1-'_._'-'-'-'-'-'- '_._'-'-'-'_._'-'-'-----'-'_._._'-'---'-'-'-._'---'-'-._._.NUN
Select delay (number of lines):
0 = 4-line comb filter for standard PAL
1 = 2-line comb filter for standard NTSC
1-._._.-._._._._.- ._._'-'-'-'-'-'-'-'_._._.-._._._'-'_._._'_.-._._'-'_.-._._.LLEN
May 1993
Selects the number of clocks for each line delay:
o = 1728 clocks (625 lines); 50 Hz)
1 = 1716 clocks (525 lines; 60 Hz)
3-247
Preliminary specification
Philips Semiconductors Video Products
SAA7152
Digital video comb filter (DCF)
MEH424
o
video
v~
·6
r-...
"1\
/
(dB)
·12
, ( '\ /V "1\
V
·18
I
I
I
·24
·30
·36
·42
·48
r\
I
I
\
1\
~
II
II
\
o
2
4
6
10
14
12
16
!(MHz)
FigA Frequency response of bandpass filters 1 and 2 with CFRQ-bit
video
V
·6
/
(dB)
·12
V
v
MEH425
r-......
"1\
~
I
·42
, I
I
I
·36
V
V
~
II
1\
I
·30
/
"
·18
·24
= 1.
II
v
·48
o
2
8
6
10
12
14
!(MHz)
Fig.S Frequency response of bandpass filters 1 and 2 with CFRQ-bit
May 1993
3-248
=O.
16
Philips Semiconductors Video Products
Preliminary specification
Digital video comb filter (DCF)
o
video
SAA7152
-r--
-6
--
MEH426
r--...... ...........
~
(dB)
-12
-18
-24
"'\\
,
~
-30
\\
-36
-42
~
-48
2
4
6
8
10
12
14
16
f(MHz)
Fig.6 Frequency response of low-pass filter with CFRQ-bit = 1.
video
-
-6
MEH427
r-. ..........
........
"\
(dB)
-12
-18
-24
1\
\
-30
\
-36
\
-42
\
-48
o
2
6
8
10
12
14
f(MHz)
Fig.7 Frequency response of low-pass filter with CFRQ-bit =o.
Purchase of Philips' 12C components conveys a license under the
Philips' 12C patent to use the components in the 12C-system
provided the system conforms to the 12C specifications defined
by Philips.
May 1993
3-249
16
Philips Semiconductors Video Products
Preliminary specification
Digital video comb filter (DCF)
SAA7152
8. LIMITING VALUES
In accordance with the Absolute Max!mum Rating System (IEC 134).
SYMBOL
PARAMETER
MAX.
MIN.
UNIT
V DD
supply voltage (pins 11, 34, 44)
-0.5
7.0
V
VI
voltage on all inputs
-0.5
VDD+0.5
V
Va
voltage on all outputs (10 max =20 mAl -0.5
VDD+0.5
V
Ptot
total power dissipation
-
1.0
W
Tst9
storage temperature range
-65
150
°C
Tamb
operating ambient temperature range
°C
electrostatic handling* for all pins
a
-
70
V ESD
±2000
V
* Equivalent to discharging a 100 pF capacitor through a 1.5 kn. series resistor.; inputs and outputs are protected
against electrostatic discharge in normal handling. Normal precautions appropriate to handle MaS devices is
recommended ("Handling MaS Devices").
9. CHARACTERISTICS
V DD1 to V DD3 =5 V; Tamb
SYMBOL
=a to 70 °C and measurements taken in Fig.1
PARAMETER
VDD
supply voltage range (pins 11, 34, 44)
IDD
total supply current (pins 11, 34, 44)
unless otherwise specified.
CONDITIONS
TYP.
MIN.
4.5
Voo = 5 V; inputs LOW;
outputs not connected
MAX.
UNIT
5
5.5
V
85
180
mA
1.5
V
12C-bus, SDA and SCL (pins 23 and 24)
VI L
input voltage LOW
-0.5
V IH
input voltage HIGH
3
123 ,24
input current
lACK
output current on pin 23
acknowledge
VOL
output voltage at acknowledge
123
= 3 mA
-
V o o+0.5 V
±10
~A
3
-
mA
-
0.4
V
0.6
V
Data and clock inputs (pins 2 to 10 and pins 13 to 20)
V IL
LL27 input voltage (pin 2)
LOW
HIGH
2.4
other input voltages
LOW
-0.5
V IH
VI L
HIGH
VIH
Ileak
input leakage .current
CI
input capacitance
tSU.OAT
input data set-up time
tHD.OAT
input data hold time
-0.5
V o o+O.5 V
-
2.0
data inputs
Fig.8
11
3
3-250
0.8
V
VOO+0.5 V
-
clock inputs
May 1993
-
-
10
~A
8
pF
10
pF
-
ns
-
ns
Philips Semiconductors Video Products
Preliminary specification
Digital video comb filter (DCF)
SYMBOL
SAA7152
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Data outputs (pins 25 to 32 and pins 35 to 42)
output voltage LOW
0
VOH
output voltage HIGH
2.4
CL
load capacitor
8
VOL
Timing of data outputs
-
0.6
V
VDD
V
25
pF
-
ns
32
ns
39
ns
Fig.8
tOH
output signal hold time from
positive edge of LL27
C L =8 pF
3
too
output delay from
positive edge of LL27
CL =25pF
-
Line locked clock input LL27 (pin 2)
-
Fig.8
tLL27
cycle time
note 1
35
tp
duty factor
tLL27H /t LL27
40
tr
rise time
tf
fall time
-
-
50
60
%
-
5
ns
-
6
ns
Note to the characteristics
1. tsu, tHO, tOH and ta~ include tr and tf·
;...
!...
-----'1
.,i,':
_ _ _ _ _--.J.
tsu
! tHO
~:.--.,
I
I
-.1
tf :.-
~
0.6 V
tir :.-
'I
I
input data
, :m:::
:...
~ tOH ~
output data
r
~,.i '\! .,. ._____---J~~ ~;~
1
dock input LL27
~i,
t LL27
t ill7 H
too
not valid
. ~~~~!-----./:m'----"C:-~ :::
MEHS56-1
Fig.8 Data input and output timing.
May 1993
3-251
Philips Semiconduc~ors Video Products
Preliminary specification
Clock signal generator circuit
for digital TV systems (SCGC)
FEATURES
• Clock generation suitable for digital
TV systems (line-locked)
• PLL frequency multiplier to
generate 4 times of input frequency
• Dividers to genElrate clocks LL 1.5A,
LL 1.58, LL3A and LL38 (4th and
2nd multiples of input frequency)
• PLL mode or VCO mode selectable
• Reset control and power fail
detection
• Suitable for applications with
feature box and picture memory
GENERAL DESCRIPTION
The SAA7157 generates all clock
signals required for a digital TV
system suitable for the SAA715x
family and the SAA71998 (DENC).
The circuit operates in either the
phase-locked loop mode (PLL) or
voltage controlled oscillator mode
(VCO).
May 1992
SAA7157
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDDA
analog supply voltage (pin 5)
4.5
5.0
5.5
V
VDDD
digital supply voltage (pins 8, 17)
4.5
5.0
5.5
V
IDDA
analog supply current
3
9
mA
IDDD
digital supply current
10
60
mA
V LFCO
LFCO input voltage
(peak-to-peak value)
1
VDDA
V
fj
input frequency range
6.0
7.25
MHz
VI
input voltage LOW
input voltage HIGH
0
2.0
0.8
V DDD
V
V
Vo
output voltage LOW
output vOltage HIGH
0
2.6
0.6
VDDD
V
V
Tamb
operating ambient temperature
range
0
70
°C
-
ORDERING INFORMATION
EXTENDED
TYPE NUMBER PINS
PACKAGE
PIN POSITION
MATERIAL
CODE
SAA7157
20
DIL
plastic
SOT146
SAA7157T
20
mini,-pack (S020)
plastic
SOT163A
3-252
Philips Semiconductors Video Products
Preliminary specification
Clock signal generator circuit
for digital TV systems (SCGC)
MS
SAA7157
1
I
I
I
15
18
117
SAA7157
LOOP
FILTER
i
PHASE
DETECTOR
T
11
LFCO
II
PRE-FILTER
AND
PULSE
SHAPER
~... ~
MS
L'K'"
:~
FREQUENCY
DIVIDER
1: 2
= LOW
~
..
•
VCO
FREQUENCY
~-DIVIDER
1 :2
r r-"'-
L ~~
----;
DELAY
Lf?
,..
L
~
LL1.SA
(LL27A)
10
LL1.SB
(LL27B)
14
20
15
LL3A
--.
LL3B
CREF
r
POWER-ON
RESET
12
LFC02 19
RESN
2
CE
16
LFCOSEL
l
FUNCTION DESCRIPTION
The SAA7157 generates all clock
signals required for a digital TV
system suitable for the SAA715x
family consisting of an 8-bit analogto-digital converter (ADC8), digital
video multistandard decoder
(DMSD2) and video enhancement
and D/A processor circuit (VEDA).
Optional extras (feature box, video
memory etc.) can be driven via
external buffers, advantageous for a
digital TV system based on display
standard conversion concepts.
The 6.75 MHz input signal LFCO
(triangular waveform) coming from
the DMSD or LFC02 is multiplied to
27 MHz by the PLL (including phase
detector, loop filter, VCO and
frequency divider) and output on
LL 1.5A (pin7) and LL 1.5B (pin 10).
The 13.5 MHz frequencies are
generated by dividers using ratio of
1:2 and are output on LL3A (pin 14)
and LL3B (pin 20).
May 1992
7
3
4
6,9,13,18
V SSA
V SSD
PORD
I
w;;
MEH452
~~
Fig.1 Block diagram.
The rectangular output signals have
50 % duty factor. Outputs with equal
frequency may be connected
together externally. The clock
outputs go HIGH during power-on
reset (and chip enable) to ensure
that no output clock signals are
available before the PLL has locked-on.
Mode select MS
The LFCO input signal is directly
connected to the VCO at MS = HIGH.
The circuit operates as an oscillator
and frequency divider. This function
is not tested.
Source select LFCOSEL
Line frequency control signal (LFCO)
is selected by LFCOSEL input.
LFCOSEL =LOW:
signal from LFCO (pin 11) is selected.
LFCOSEL = HIGH:
signal from LFC02 (pin 19) is selected.
This function is not tested.
Chip enable CE
The buffer outputs are enabled and
3-253
RESN is set to HIGH by
CE = HIGH (Fig.4).
CE = LOW sets the clock outputs
HIGH and RESN output LOW.
CREF output
TV2 digital clock reference output
signal. Clock qualifier signal to TV
system with 2 times of LFCO or
LFC02 frequency.
Power-on reset
Power-on reset is activated at
power-on, when the supply voltage
decreases below 3.5 V (Fig.4) or
when chip enable is done. The
indicator output RESN is LOW for a
time determined by capacitor on
pin 3. The RESN signal can be
applied to reset other circuits of this
digital TV system.
The LFCO or LFC02 input signals
have to be applied before RESN
becomes HIGH.
Preliminary specification
Philips Semiconductors Video Products
Clock signal generator circuit
for digital TV systems (SCGC)
SAA7157
PIN CONFIGURATION
PINNING
SYMBOL
PIN
. DESCRIPTION
= PLL mode)
= outputs enabled)
LL3B
MS
1
mode select input (LOW
CE
2
chip enable freset (HIGH
PORD
3
p0'1er-on reset delay, dependent on external capacitor
V SS D4
vooo2
VSSA
4
analog ground (0 V)
VOO A
5
analog supply voltage (+5 V)
VSS0 1
6
digital ground 1 (0 V)
LFC02
LFCOSEL
CREF
LL1.5A
7
line-locked clock output signal 1.5A (4 times fLFCO)
VOOD1
8
digital supply voltage 1 (+5 V)
VSSD2
9
digital ground 2 (0 V)
LL3A
VSS03
RESN
LL1.SB
LL1.58
10
line-locked clock output signal 1.58 (4 times fLFca)
LFCO
11
line-locked frequency control input signal 1
RESN
. 12
Fig.2 Pin configuration.
reset output (active-LOW, Fig.4)
VSSD3
13
LL3A
14
digital ground 3 (0 V)
line-locked clock output signal 3A (2 times fLFca)
CREF
15
clock reference output, qualifier signal (2 times f LFca )
= LFCO selected)*
LFCOSEL
16
LFCO source select (LOW
VOOD2
17
digital supply voltage 2 (+5 V)
VSSD4
18
digital ground 4 (0 V)
LFC02
19
line-locked frequency control input signal 2*
LL38
20
line-locked clock output signal 38 (2 times fLFCO)
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); ground
pins as well as supply pins together connected.
SYMBOL
PARAMETER
MIN.
VOOA
analog supply voltage (pin 5)
-D.5
VOOO
digitalsupply voltage (pins 8 and 17)
-D.5
VdiffGNQ difference voltage VO OA - VOOO
MAX.
UNIT
7.0
V
7.0
V
±100
mV
Va
output voltage (10M = 20 mA)
-D.5
VOOO
V
Ptot
total power ~issipation (DIL20)
a
1.1
W
TstQ
storage temperature range
-65
150
°C
Tamb
operating ambient temperature range
0
70
°C
VES O
electrostatic handling** for all pins
tbf
V
May 1992
3-254
* MS and LFC02 functions are not
tested. LFC02 is a multiple of
horizontal frequency.
** Inputs and outputs are protected
against electrostatic discharge in
normal handling. However, to be
totally safe, it is recommended to
take normal handling precautions
appropriate to "Handling MOS
devices ".
Philips Semiconductors Video Products
Preliminary specification
Clock signal generator circuit
for digital TV systems (SCGC)
CHARACTERISTICS
VOO A = 4.5 to 5.5 V; VOOO
SYMBOL
SAA7157
= 4.5 to 5.5 V; fLFCO = 6.0 to 7.25 MHz and Tamb = 0 to 70°C unless otherwise specified.
PARAMETER
CONDITIONS
V OOA
analog supply voltage (pin 5)
VOOO
IOOA
1000
digital supply current (Is + 117 )
note 1
Vreset
power-on reset threshold voltage
Fig.4
MIN.
TYP.
4.5
5.0
digital supply voltage (pins 8 and 17)
4.5
5.0
analog supply current (pin 5)
3
10
MAX.
UNIT
5.5
V
5.5
V
9
mA
-
60
mA
3.5
-
V
V OOA
V
-
V OOA
V
7.25
MHz
10
pF
Input LFCO (pin 11)
V 11
DC input voltage
0
Vi
input signal (peak-to-peak value)
1
fLFCO
input frequency range
6.0
Cn
input capacitance
Inputs MS, CE, LFCOSEL and LFC02 (pins 1,2, 16 and 19); note 3
V 1L
input voltage LOW
0
0.8
V
V 1H
input voltage HIGH
2.0
VOOO
V
fLFC02
input frequency range for LFC02
6.0
7.25
MHz
III
input leakage current
LFCOSEL
50
150
~
others
-
10
~
5
pF
C1
input capacitance
Output RESN (pin 12)
VOL
output voltage LOW
10 L = 2 mA
0
0.4
V
VOH
output voltage HIGH
10H = -0.5 mA
2.4
VOOO
V
td
RESN delay time
C3
20
200
ms
10 L = 2 mA
0
0.6
V
2.4
VOOO
V
= 0.1IlF; Fig.4
Output CREF (pin 15)
VOL
output voltage LOW
V OH
output voltage HIGH
10H = -0.5 mA
fCREF
output frequency CREF
Fig.3
2 fLFCO 2)
MHz
CL
output load capacitance
tsu
set-up time
Fig.3; note 1
12
-
ns
tHO
hold time
Fig.3; note 1
4
-
ns
15
40
pF
Output signals LL 1.5A, LL 1.5B, LL3A and LL3B (pins 7,10,14, and 20); note 3
VOL
output voltage LOW
10 L = 2 mA
0
VOH
output voltage HIGH
10H =-0.5 mA
2.6
tcomp
composite rise time
Fig.3; notes 1 and 2
May 1992
3-255
-
0.6
V
VOOO
V
8
ns
Philips Semiconductors Video Products
Preliminary specification
Clock signal generator circuit
for digital TV systems (SCGC)
SYMBOL
fLL
PARAMETER'
SAA7157
CONDITIONS
output frequency LL 1.SA
TYP.
MIN.
-
Fig.3
output frequency LL 1.S8
t r, tf
rise and fall times
note 1 ; Fig.3
-
tLL
duty factor LL 1.SA, LL 1.58, LL3A
and LL38 (mean values)
note 1 ; Fig.3;
at 1.5 V level
43
output frequency LL3A
output frequency LL38
MAX.
UNIT
4 f LFCO(2)
MHz
4 f LFCO(2)
MHz
2 f LFCO(2)
MHz
2 f LFCO(2)
MHz
-
5
ns
SO
57
0/0
Notes to the characteristics
1. f LFCO = 7.0 MHz and output load 40 pF (Fig.3). V SSA and VSSD short connected together.
2. tcomp is the rise time from LOW of all clocks to HIGH of all clocks (Fig.3) including rise time, skew and jitter
components. Measurements taken between 0.6 V and 2.6 V. Skew between two LLx clocks will not deviate more
than ±2 ns if output loads are matched within 20 %.
3. MS and.LFC02 functions not tested.
CREF
,!7~,
, , -.~===-
2.4 v
~-,' - - - , - - - -
0.6 V
-:~~
tHO
2.6V
LL1.SA
LL1.S8
1.SV
1'--_ _ _--'1
-+---------
0.6 V
---+--
0.6 V
t LL3H
LL3A
LL38
1.SV
1'--------11--../1
MEH456
Fig.3 Output timing.
May 1992
Philips Semiconductors Video Products
Preliminary specification
Clock signal generator circuit
for digital TV systems (SCGC)
SAA7157
71-m ______ -_m_ mm __ m_m __
~,
m__ m__ m---__ mm__ m_ on m__ m_
I
ov
power-on
LFCO
RESN
LL1.SA
LL1.S8
LL3A
LL38
IIIIIII
PLL lock-on
MEH457
Fig.4 Reset procedure.
7
1
~
VODD
LL1.SA
LL1.S8
LL3A
LL38
16
19
MS
CE
LFCOSEL
LFC02
CREF
VSSO
LFCO
RESN
MEH468
Fig.5 Internal circuit.
May 1992
+3.5 V
Philips Semiconductors Video Products
Preliminary specification
Video enhancement and D/A processor (VEDA3)
1. FEATURES
• CMOS circuit to enhance video
data and to convert luminance and
colour-difference signals from
digital-to-analog
• 16-bit parallel input for 4:1:1 and
4:2:2 VUV data
• Data clock input LLC (line-locked
clock) for a data rate up to 45 MHz
• 8-bit luminance and 8-bit
multiplexed colour-difference
formats (optional 7-bit formats)
• MC input to support various clock
and pixel rates
• Formatter for VUV input data;
4:2:2 format, 4:1:1 format and filter
characteristics selectable
• HREF input to determine the active
line (number of pixels)
• Controllable peaking of luminance
signal
• Coring stage with controllable
threshold to eliminate noise in
luminance signal
• Interpolation filter suitable for both
formats to increase the data rate in
chrominance path
• Polarity of colour-difference signals
2. QUICK REFERENCE DATA
SYMBOL
MIN.
PARAMETER
TVP.
MAX.
UNIT
VOOO
supply voltage digital part
4.5
5
5.5
V
V OOA
supply voltage analog part
4.75
5
5.25
V
100
total supply current
-
160
mA
VI L
input voltage LOW on VUV-bus
-0.5
0.8
V
V IH
input voltage HIGH on VUV-bus
2
Vooo+0.5
V
f LLC
input data rate
-
-
45
MHz
VoV,CO
output signal V, ±(R-V) and
±(B-V) (peak-to-peak value)
-
2
-
V
RL V,CO
output load resistance
125
-
ILE
DC integral linearity error in
output signal (8-bit data)
DLE
Tamb
n
-
1
LSB
DC differential error in
output signal (8-bit data)
-
-
0.5
LSB
operating ambient temperature
range
0
-
70
°C
3. ORDERING INFORMATION
EXTENDED
TYPE NUMBER PINS
SAA7164
April 1993
44
PACKAGE
PIN POSITION
PLCC
MATERIAL
CODE
plastic
SOT187
3-258
SAA7164
selectable
• Separate digital-to-analog
converters (9-bit resolution for V;
8-bit for colour-difference signals)
• 1 V (p-p)/ 75 n outputs realized by
two resistors
• No external adjustments
• All functions controlled via 12C-bus'
~
2:
~
(0
(0
m
r-
t.)
0.11lF
15kO
~i-.>c:J0.11lF
0.11lF
~--U-~
0.11lF
H~
V ODD1
V
12
31
0.11lF
0.11lF
~
o·
0
DDD2
21 to 14
r+
YUV-bus
...
Y
FORMATIER
::IJ
VDDA1
VDDA2
VDDA3
CUR
V DDA4
32
37
40
41
42
•
PEAKING
AND
CORING
~
io.
data clock
DAC3
UV7 to UVO
11 t04
~
'"
01
UV
FORMATIER
14-
~
~
INTERPOLATION
~
~
2
~39
CREF
LL27
MC
LLC
HREF
25
I~
4
~
DAC1
43
~33
~
a.
II)
.....
8.c:
0
-0
~
"0
0"'"'
0
CD
1 V (p-p)
'"";;50
REFLuv ~
en
en
0
-<
±(B-Y)
Q(1~ 75 0(1)
"'"'
m
~
Cuv
0.11lF
.~
II
0
0
£
1 V (p-p)
500(1)
»
±(R-Y)
75 0(1)
I
-U)
27
SCL
~
28
2
1 C-BUS
CONTROL
JS
.....
i
TIMING
CONTROL
26
RESN
12c
I
24
T
c:
6"
iil
»
Y
~50Q(1~
~
75 0(1)
~36
~
44
a.
0
1 V (IJ-p)
,..
DAC2
::::J
0-
Ir-~
REFLy
3
3
:J
Cy
0.11lF
1
I--
~
i
(0
rL .....--
:J
0
CD
CD
:J
SWITCH
t.)
::r
$l)
$l)
--
DATA
~
3:
H~
~
Y7toYO
G')
0.11lF
H~ H~ ~--n--~
OO
II)
CD
:J
:;
+5 V
~
III
0
C
+5V
CD
-0
i3.
0
0
+5V
<
~
SDA
29
13
V
!'.~SSDl
"
I---
..
30
V
~~SSD2
TEST
CONTROL
22
23
(MS1)
(MS2)
~~
SAA7164
~
~~
3
34
35
38
-0
~~
(1) output amplitude determined by resistors (R L> 1250)
Fig.1 Block diagram and application circuit.
V
V
V
!'. ~ SSAl ~ ~ SSA2 ::!~ SSA3
!i
3·
MEH510
(J)
5·
D)
»
»
-....J
-<
0>
a.
~
~
III
-0
~
g
o::::J
Philips Semiconductors Video Products
Preliminary specification
Video enhancement and D/A processor (VEDA3)
5. PINNING
SYMBOL
REFLy
PIN
DESCRIPTION
1
low reference of luminance DAC (connected to VSSA1)
Cy
2
capacitor for luminance DAC (high reference)
SUB
3
substrate (connected to VSSA1)
UVO
4
UV1
5
UV2
6
UV3
7
UV4
8
UV5
9
UV6
10
UV signal input bits UV7 to UVO (digital colour-difference signal)
UV7
11
VDDD1
12
+5 V digital supply voltage 1
VSSD1
13
digital ground 1 (0 V)
YO
14
Y1
15
Y2
16
Y3
17
Y4
18
Y5
19
Y6
20
Y signal input bits Y7 to YO (digital luminance signal)
Y7
21
MS2
22
mode select 2 input for testing chip
MS1
23
mode select 1 input for testing chip
MC
24
data clock CREF (13.5 MHz e. g.); at MC =.,HIGH the LLC divider-by-two is inactive
LLC
25
line-locked clock signal (LL27 = 27 MHz)
HREF
26
data clock for YUV data inputs (for active line 768Y or 640Y long)
RESN
27
reset input (active LOW)
SCL
28
12C-bus clock line
SDA
29
12C-bus data line
VSSD2
30
digital ground 2 (0 V)
V DDD2
31
+5 V digital supply voltage 2
V DDA1
32
+5 V analog supply voltage for buffer of DAC 1
(R-Y)
33
±(R-Y) output signal (analog signal)
V SSA1
34
analog ground 1 (0 V)
April 1993
3-260
SAA7164
Philips Semiconductors Video Products
Preliminary specification
Video enhancement and OfA processor (VEDA3)
SYMBOL
PIN
DESCRIPTION
VSS A2
35
analog ground 2 (0 V)
(8-Y)
36
±(8-Y) output signal (analog colour-difference signal)
VDDA2
37
+5
VSSA3
38
analog ground 3 (0
Y
39
Y output signal (analog luminance signal)
V DDA3
40
+5
CUR
41
current input for analog output buffers
VDDA4
42
supply and reference voltage for the three DACs
CUV
43
capacitor for chrominance DACs (high reference)
REFLuv
44
low reference of chrominance DACs (connected to VSSA1)
V
V
SAA7164
analog supply voltage for buffer of DAC 2
V)
analog supply voltage for buffer of DAC 3
PIN CONFIGURATION
SCL
RESN
HREF
LLC
MC
REFLy
SAA7164
MS1
MS2
Y7
Y6
Y5
Y4
MEH511
Fig.2 Pin configuration.
April 1993
3-261
Preliminary specification
Philips Semiconductors Video Products
SAA7164
Video enhancement and D/A processor (VEDA3)
FUNCTIONAL DESCRIPTION
The CMOS circuit SAA7164
processes digital YUV-bus data up to
a data rate of 45 MHz. The data
inputs Y7 to YO and UV7 to UVO
(Fig.1) are provided with 8-bit data.
The data of digital colour-difference
signals U and V are in a multiplexed
state (serial in 4:2:2 or 4:1:1 format;
Tables 2 and 3).
Data is read with the rising edge of
LLC (line-locked clock) to achieve a
data rate of LLC at MC = HIGH only.
If MC is supplied with the frequency
CREF (LLC/2 for example), data is
read only at every second rising
edge (Fig.3).The 7-bit YUV data are
also supported by means of the
R78-bit (R78 = 0). Additionally, the
luminance data format is converted
for internal use into a two's
complement format by inverting
MSB. The Y input byte (bits Y7 to YO)
represent luminance information; the
UV input byte (bits UV7 to UVO) one
of the two digital colour-difference
signals in 4:2:2 format (Table 2).
The HREF input signal (HREF =HIGH)
determines the start and the end of
an active line (Fig.3), the number of
pixels respectively . The analog
output Y is blanked at HREF =LOW,
the (8-Y) and (R-Y) outputs are in a
colourless state. The blanking level
can be set by the BLV-bit.
The SAA7164 controllable via the
12C-bus
Y and UV formatters
The input data formats are formatted
into the internally used processing
formats (separate for 4:2:2 and 4:1 :1
formats). The IFF, IFC and IFL bits
control the input data format and
determine the right interpolation filter
(Figures 10 to 13).
There are the two switchable
bandpass filters BF1 and BF 2
controlled via the 12C-bus by the bits
BP1 ,BPO and BFB. Thus, a
frequency response is achieved in
combination with the peaking factor K
(Figures 5 to 9; K is determined by
the bits BFB, WG1 and WGO).
The coring stage with controllable
threshold (4 states controlled by C01
and COO bits) reduces noise
disturbances (generated by the
bandpass gain) by suppressing the
amplitude of small high-frequent
signal components. The remaining
high-frequent peaking component is
available for a weighted addition
after coring.
Peaking and coring
Peaking is applied to the Y signal to
compensate several bandwidth
reductions of the external
pre-processing. Y signals can be
improved to obtain a better
sharpness.
Table 1 LLC and MC configuration modes in DMSD applications
PIN
INPUT SIGNAL
COMMENT
LLC
MC
LLC (LL27)
CREF
The data rate on YUV-bus is half the clock rate
on pin LLC, e. g. in SAA7151B, SAA7191 and
SAA7191 B single scan operation.
LLC
MC
LLC (LL27)
MC = HIGH
The data rate on YUV-bus must be identical to
the clock rate on pin LLC, e. g. in double scan
applications.
Table 2 Data format 4: 2: 2. (Fig.3)
INPUT
YO (LSB) YO
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7 (MSB) Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
ua
LLC2ILL3
MC = HIGH
The data rate on YUV-bus must be identical to
the clock rate on pin LLC, e~ g. SAA9051 single
scan operation,
Note: YUV data are only latched with the rising edge of LLC at MC
April 1993
3-262
= HIGH.
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
(LSB)
UV1
UV2
UV3
UV4
UV5
UV6
UV7(MSB)
VO
V1
V2
V3
V4
V5
V6
V7
UO
U1
U2
U3
U4
U5
U6
U7
va
UO
U1
U2
U3
U4
U5
U6
V7 U7
va
U1
U2
U3
U4
U5
U6
U7
V1
V2
V3
V4
V5
V6
V1
V2
V3
V4
V5
V6
Y frame
0
1
2
3
5
UV frame
a
uva
LLC
MC
PIXEL BYTE SEQUENCE
2
4
4
V7
Philips Semiconductors Video Products
Preliminary specification
Video enhancement and D/A processor (VEDA3)
Interpolation
Data switch
The chrominance interpolation filter
consists of various filter stages,
multiplexers and de-multiplexers to
increase the data rate of the
colour-difference signals by a factor
of 2 or 4. The switching of the filters
by the bits IFF, IFC and IFL is
described previously. Additional
signal samples with significant
amplitudes between two consecutive
signal samples of the low data rate
are generated. The time-multiplexed
U and V samples are stored in
parallel for converting.
The digital signals are adapted to the
conversation range. U and V data
have a-bit formats again; Y can have
9 bits dependent on peaking.
Blanking and switching to colourless
level is applied here. Bits can be
inverted by INV-bit to change the
polarity of colour-difference output
signals.
Digital-to-analog converters
Conversion is separate for Y, U
and V. The converters use resistor
chains with low-impedance output
buffers. The minimum output voltage
is 200 mV to reduce integral
Table 3 Data format 4 : 1 : 1
INPUT
PIXEL BYTE SEQUENCE
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
UVO
UV1
UV2
UV3
UV4
UV5
UV6
UV7
0
0
0
0
V6
V7
U6
U7
0
0
0
0
V4
V5
U4
U5
0
0
0
0
V2
V3
U2
U3
0
0
0
0
VO
V1
UO
U1
0
0
0
0
V6
V7
U6
U7
0
0
0
0
V4
V5
U4
U5
0
0
0
0
V2
V3
U2
U3
0
0
0
0
VO
V1
UO
U1
Y frame
0
1
2
3
4
5
6
7
UV frame
0
April 1993
4
3-263
SAA7164
non-linearity errors. The analog
signal, without load on output pin, is
between 0.2 and 2.2 V floating. An
application for 1 VI 75 n on outputs
is shown in Fig.1 .
Each digital-to-analog converter has
its own supply and ground pins
suitable for decoupling. The
reference voltage, supplying the
resistor chain of all three DACs, is
the supply voltage VDDA4. The
current into pin 41 is 0.3 mA ; a
larger current improves the
bandwidth but increases the integral
non-linearity.
Philips Semiconductors Video Products
Preliminary specification
Video enhancement and DfA processor (VEDA3)
SAA7164
LL27
(LLC)
CREF
internal
bus clock
(LLC2)
,
HREF
,
,
--LJ~startof.
1,:
i
active line
i,:
Byte numbers for pixels:
Y signal
50Hz
U and V sig~n-=al_ _..J '-
- -
... 1
-----=-_=____~ ..... ---=-=----~ '-
.....
Y signal
60 Hz
U and V sig-:;...n_al_ _..J
--=-=--...1 . . .-----=--=----oJ . . .--==-oJ
.....
MEH268
LL27
(LLC)
CREF
internal
bus clock
(LLC2)
i end of . ~LI_----!_ _ _.!....-_ _...!..-_ __
HREF
i
active line
i
Byte number for pixels:
Y signal
50Hz
U and V sign~~
Y signal
60Hz
U and V signaJ~
MEH269
Fig.3 Line control by HREF for 4: 2 : 2 format, CREF
50 Hz and 60 Hz field.
April 1993
3-264
=13.5 MHz; HREF = 720 pixel;
Philips Semiconductors Video Products
Preliminary specification
Video enhancement and D/A processor (VEDA3)
7. LIMITING VALUES
In accordance with the Absolute Maximum Rating System (lEG 134).
SYMBOL PARAMETER
MIN.
MAX.
UNIT
VDDD1
supply voltage range (pin 12)
-0.3
7
V
V DDD2
supply voltage range (pin 31)
-0.3
7
V
V DD A1
supply voltage range (pin 32)
-0.3
7
V
V DDA2
supply voltage range (pin 37)
-0.3
7
V
VDDA3
supply voltage range (pin 40)
-0.3
7
V
VDDA4
supply voltage range (pin 42)
-0.3
7
V
-
±100
mV
VdiffGND difference voltage V SSD - V SSA
Vn
voltage on all input pins 4 to 11,
14 to 27 and 41
-0.3
V DDD
V
Vn
voltage on analog output pins 33,
36 and 39
-0.3
V DDD
V
total power dissipation
0
tbf
mW
Ptot
T stg
storage temperature range
-55
150
oG
Tamb
operating ambient temperature range
0
70
oG
V ESD
electrostatic handling* for all pins
±2000
V
* Equivalent to discharging a 100 pF capacitor through a 1.5 kn series resistor.
8. THERMAL RESISTANCE
SYMBOL
Rthj -a
April 1993
PARAMETER
from junction-to-ambient in free air
THERMAL RESISTANCE
46
3-265
Kf\N
SAA7164
Philips Semiconductors Video Products
Preliminary specification
Video enhancement and DfA processor (VEDA3)
SAA7164
9. CHARACTERISTICS
VOOO = 4.5 to 5.5 V; VOOA = 4.75 to 5.25 V; LLC = LL27; MC = CREF = 13.5 MHz; Tamb = 0 to 70 °C; measurements
taken in Fig.1 unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VO OO1
supply voltage range (pin 12)
for digital part
4.5
5
5.5
V
VOO 02
supply voltage range (pin 31)
for digital part
4.5
5
5.5
V
V OOA1
supply voltage range (pin 32)
for buffer of DAC 1
4.75
5
5.25
V
VOOA2
supply voltage range (pin 37)
for buffer of DAC 2
4.75
5
5.25
V
VOOA3
supply voltage range (pin 40)
for buffer of DAC 3
4.75
5
5.25
V
VOOA4
supply voltage range (pin 42)
DAC reference voltage
4.75
5
5.25
V
1000
supply current (10001 + 10002 )
for digital part
mA
supply current (IOOA1 to 100A4)
for DACs and buffers
-
140
100A
-
20
mA
-0.5
-
0.8
V
2.0
-
YUV-bus inputs (pins 4 to 11 and 14 to 21 )
V IL
input voltage LOW
VIH
input voltage HIGH
CI
input capacitance
III
input leakage current
Figures 3 and 4
VI = HIGH
-
Vooo+0.5 V
10
pF
4.5
~A
0.8
V
Inputs MS1, MS2, MC, LLC, HREF and RESN (pins 22 to 27)
VIL
input voltage LOW
-0.5
VIH
input voltage HIGH
2.0
VI = HIGH
-
CI
input capacitance
III
input leakage current
V24
MC input voltage for LL27
27 MHz data rate
2.0
CREF signal on MC input
CREF data rate; note 1
-
-
Vooo+0.5 V
10
pF
4.5
~A
Vooo+0.5 V
I-
V
12C-bus SCL and SDA (pins 28 and 29)
VI L
input voltage LOW
VIH
input voltage HIGH
II
input current
VI = LOW or HIGH
VOL
SDA output voltage LOW (pin 29)
129 =3 mA
during acknowledge
-0.5
3.0
129
output current
Digital-to-analog converters (pins 1, 2, 41, 42, 43 and 44)
VOAC
input reference voltage for internal
resistor chains (pin 42)
ICUR
input current (pin 41)
V 1,44
reference voltage LOW
CL
external blocking capacitor to VSSA1
for reference voltage HIGH (pins 2 and 43)
April 1993
R41 -42 = 15 kn
3
1.5
V
Vooo+0.5 V
±10
~A
0.4
V
-
mA
V
4.75
5
5.25
-
300
-
~A
0
-
V
0.1
-
~F
pin connected to VSSA 1 -
-
3-266
-
Philips Semiconductors Video Products
Preliminary specification
Video enhancement and D/A processor (VEDA3)
SYMBOL
f LLC
Res
PARAMETER
data conversation rate (clock)
resolution
SAA7164
CONDITIONS
luminance DAC
-
chrominance DACs
-
Fig.3
TYP.
MIN.
-
MAX.
45
UNIT
MHz
bit
9
8
-
bit
ILE
DC integral linearity error
8-bit data
-
-
1.0
LSB
DLE
DC differential error
8-bit data
-
-
0.5
LSB
Y, ±(R-Y) and ±(B-Y) analog outputs (pins 39,33 and 36)
Vo
output signal voltage (peak-to-peak value) without load
-
2
-
V
V33,36,39
output voltage range
0.2
-
2.2
V
V39
output blanking level
Y output; note 3
16
V33 ,36
±(R-Y), ±(8-Y); note 4
128
R33,36,39
internal serial output resistance
.n
.n
tbf
-
LSB
output no-colour level
22.2
37
41
ns
50
without load; note 2
25
RL 33,36,39 output load resistance
external load
125
B
output signal bandwidth
-3 dB
20
td
signal delay from input to Youtput
LLC timing (pins 25)
-
LSB
MHz
ns
LLC; Fig.3
tLLC
cycle time
tp H
pulse width
40
60
%
tr
rise time
5
ns
tf
fall time
-
6
ns
tsu
input data set-up time
6
ns
tHD
input data hold time
3
-
YUV-bus timing (pins 4 to 11 and 14 to 21)
MC timing (pin24)
tsu
tHD
Fig.5
ns
Fig.5
6
input data set-up time
input data hold time
3
-
-
ns
-
ns
ns
RESN timing (pin 27)
tsu
set-up time after power-on or failure
active LOW; note 5
4 xtLLC
Notes to the characteristics
1. YUV-bus data is read at MC = HIGH (pin 24) clocked with LLC (Fig.5) . Data is read only with every second
rising edge of LLC when CREF = LLC/2 on MC-pin 24.
2. 0.2 to 2.2 V ouput voltage range at 8-bit DAC input data. The data word can increase to 9-bit dependent on
peaking factor.
3. The luminance signal is set to the digital black level: 16 LSB for BLV-bit = 0; 0 LSB for BLV-bit = 1.
4. The chrominance amplitudes are set to the digital colourless level of 128 LSB.
5. The circuit is prepared for a new data initialization.
April
1993
3-267
Philips Semiconductors Video Products
Preliminary specification
Video enhancement and D/A processor (VEDA3)
SAA7164
input clock
LLC (LL27)
0.6 V
,/- ------
MEH270
data valid
Fig.4 YUV-bus data and CREF timing.
PROCESSING DELAY
LLC CYCLES
REMARKS
YUV digital input
to
YUV analog output
44
at MC'
88
at MC
April 1993
3-268
= "1"
= LLC/2
Preliminary specification
Philips Semiconductors Video Products
SAA7164
Video enhancement and D/A processor (VEDA3)
10. 12C-BUS FORMAT
I
S
I SLAVE ADDRESS I
S
A
I SUBADDRESS I A
A
DATAO
DATAn
start condition
1011 111X
acknowledge, generated by the slave
subaddress byte (Table 4)
data byte (Table 4)
stop condition
SLAVE ADDRESS
A
SUBADDRESS·
DATA
P
x
readlwrite control bit
X = 0, order to write (the circuit is slave receiver)
X = 1, order to read (the circuit is slave transmitter)
* If more than 1 byte DATA are transmitted, then auto-increment of the subaddress is performed.
Table 412C-bus transmission
FUNCTION
I
SUBAOORESS
DATA
03
02
01
DO
Peaking and coring
01
0
C01
COO
BP1
BPO
BFB
WG1
WGO
Input formats; interpolation
02
IFF
IFC
IFL
0
0
0
0
0
InpuVoutput setting
03
a
a
a
a
DRP
BLV
R78
INV
07
06
05
04
Bit functions in data bytes:
C01
to
COO
BP1, BPa and BFB
Control of coring threshold:
Bandpass filter selection:
C01
COO
0
0
0
1
1
0
1
BP1
BPO
BFB
0
0
0
1
1
0
1
0
0
0
0
characteristic
characteristic
characteristic
characteristic
0
0
X
1
1
BF1 filter bypassed Fig.9
not recommended
X
April 1993
coring off
small noise reduction
medium noise reduction
high noise reduction
1
3-269
1
Fig.S
Fig.6
Fig.7
Fig.8
Preliminary specification
Philips Semiconductors Video Products
Video enhancement and D/A processor (VEDA3)
BFB, WG1 and WGO
Peaking factor K:
BFB
0
0
_)10
0
1
1
1
1
IFF, IFC, IFL
Input format and filter control
at 13.5 MHz data rate:
SAA7164
WG1 WGO
0
0
1
1
0,
0
1
1
0
1
0
1
0'
1
0
1
IFF
IFC
IFL
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
X
K
K
K
K
K
K
K
K
::::i
=
=
=
=
1/8;
1/4
112
1;
O·,
1/4;
112
1;
maximum peaking
peaking off
minimum peaking
maximum peaking
4 : 2 : 2 format; -3 dB attenuation
at 1.6 MHz video frequency; Fig.10
4 : 2 : 2 format; -3 dB attenuation
at 600 kHz video frequency; Fig.11
4 : 2 : 2 format; -3 dB attenuation
at 2.5 MHz video frequency; Fig.13
UV input data code:
o = two's complement;
BLV
Blanking level on Y output:
o =16 LSB;
A78
YUV input data solution:
o = 7-bit data;
INV
Polarity of colour-difference
output signals:
1
= offset binary
=0 LSB
1
= 8-bit data
o = normal polarity equal to input signal
1 = inverted polarity
Purchase of Philips' 12C components conveys a license under the
Philips' 12C p~tent to use the components in the 12C-system
provided the system conforms to the 12C specifications defined
by Philips.
April 1993
minimum peaking
4 : 1 : 1 format; -3 dB attenuation
at 1.6 MHz video frequency; Fig.10
4 : 1 :, 1,format; -3 dB attenuation
at 600 kHz video frequency; Fig.11
4 : 1 : 1 format; -3 dB attenuation
at 1.2 MHz video frequency; Fig.12
DAP
1
=
=
=
3-270
I
Philips Semiconductors Video Products
Preliminary specification
Video enhancement and D/A processor (VEDA3)
SAA7164
MEH271
16
~
/
Vy
(dB)
/
(1)
12
/
V
10
8
6
/
/
/
J
2
..,,- ~ r--....
/"
J
/
(3)
V
V
/"
o
\
.........
\
"
-""
\
---
r--
\
\
1,\ \
'~
---
/ / / (4)
V/ /
/"
/" r;...~/'
~
~
'" '\
\
/
(2)
/
) /
4
o
~
,/'
14
'\~
\
1,\\
I'..... ~ '\.\
.............
\
"
"i'....~ ~
2
4
........ ~
6
Fig.5 Peaking frequency response with 12C-bus control bits BPi
(1) K = 1; (2) K = 1/2; (3) K = 1/4 and (4) K =1/8.
fy(MHz)
7
=0; BPO =0 and BFB =0:
MEH272
16
14
(dB)
,/
12
10
/
/
/
6
I
/""
/
/
/
2
-
........
I'-....
"\ \
--io-.. .........
/
/ 1/ / '
V/ . /
/ V"" V" ~
~
4
....--
(2)
I
8
o
V
(1)
Vy
(3)
".........
..-
r--.....
(~ ,..-
L.0V . . . . . .
\
" ,,\
\
\
"-... '\
"
\
\
\\
"",'"
~~
2
3
5
Fig.6 Peaking frequency response with 12C-bus control bits BPi
(1) K = 1; (2) K =1/2; (3) K =1/4 and (4) K =1/8.
April 1993
1\
-........
~~
o
\
3-271
6
fy(MHz)
=0; BPO =1 and BFB =0:
7
Preliminary specification
Philips Semiconductors Video Products
SAA7164
Video enhancement and D/A processor (VEDA3)
MEH273
6
V
(1)
4
Vy
(dB)
V
2
0
I
8
I
J
(2)
~
2
'\
/
I--
"""-
~~
/
"1\
..... ~
"
V
r--- ....
I I ~v
I 11/ (4)
II V ~
1/// V
4
~
I
II I
6
..
I
'"
/
---
\
\
"\.
1\
'\ \
" "'-
r--.....
~\
'\\
-""t\. ~
..... ~
~
" r--...'
~
J[#'"/
.....
......... ~
~v
o
2
4
5
fy(MHz)
Fig.? Peaking frequency response with 12C-bus control bits BP1 = 1; BPO = 0 and BFB = 0:
(1) K = 1; (2) K = 1/2; (3) K = 1/4 and (4) K = 1/8.
MEH274
16
14
(dB)
12
I
10
8
/
V
6
I /
IV
4
2
/
IJ /
V/.1
J. V/'. . . V
V
o ~
o
/
J
.........
V
(1)
Vy
"
f\.
V
(2)
f'....
/
V
-
(3)
V
r-.....
/
/"
(4)
"\.
r\.
"-~
'\.
"
--.. """"
~
.........
"-
--
s--
/V
2
4
""- .............
r--.
"'\.
. . . 1'..
'\
~
"""
"-
~'\
..........
---
.........
~
r.-.. . . . . ~~
~~
6
fy(MHz)
7
Fig.8 Peaking frequency response with j2C-bus control bits BP1 = 1; BPO = 1 and BFB = 0:
(1) K = 1; (2) K = 1/2; (3) K = 1/4 and (4) K = 1/8.
April 1993
3-272
Philips Semiconductors Video Products
Preliminary specification
Video enhancement and D/A processor (VEDA3)
SAA7164
I.4EH275
10
Vy
(dB)
8
6
(1)
4
2
~
.....-
----
.-""
~
.- - '
V-
- --- ~
(2)
--
I--- ~
l.---' .........(3)
i.----
-2
-4
o
4
2
5
6
7
fy(MHz)
Fig.9 Peaking frequency response with 12C-bus control bits BP1 = 0; BPO = 0 and BFB = 1;
bandpass filter BF1 bypassed and peaking off; (1) K = 1; (2) K = 1/2; (3) K = 1/4.
April 1993
3-273
Preliminary specification
Philips Semiconductors Video Products
Video enhancement and D/A processor (VEDA3)
MEH277
o
r--~
I
'
-3 dB
-8
Vu
"
\
(dB)
-16
-24
1\
\
-32
\
\
\
/
/
/ " :--....
"-
1\
If
\
I
-40
I
I
\
-48
\
\
\
-56
-64
SAA7164
\
o
2
\
,
\
1\
\
1
I
4
6
5
fy(MHz)
7
Fig.10 Interpolation filter with 12C-bus control bits IFF = 0; IFC = 0 and IFL = 0 in 4:1:1 format,
and control bits IFF = 1; IFC = 0 and IFL= 0 in 4:2:2 format; 13.5 MHz data rate.
MEH278
--"""'-l
-3 dB
-8
Vu
(dB)
""
\
-16
,
\
-24
~
~
I
-32
......--... ....
\,
/" ~
-40
/
I
\
"\.
"1\\
1\
-48
\
\
\
\
-56
-64
o
2
I
I
I
I
4
3
\
\
\
5
6
fy(MHz)
Fig.11 Interpolation filter with 12C-bus control bits IFF = 0; IFC = 0 and IFL = 1 in 4:1:1 format,
and control bits IFF = 1; IFC = 0 and IFL =1 in 4:2:2 format; 13.5 MHz data rate.
April 1993
3-274
7
Preliminary specification
Philips Semiconductors Video Products
SAA7164
Video enhancement and D/A processor (VEDA3)
--
-8
Vu
(dB)
MEH279
~
.......
-3 dB
'" 'r\..
"-
-16
1\
\
-24
-32
\
/
-48
-56
o
j.;'"
----
!'...
"l\\
~,
\
1\
\
\
-40
-64
./
7
I
I
I
I
I
I
I I
2
\
\
\
1\
\
\
4
6
5
7
fy(MHz)
= 0; IFC = 1 and IFL = 0 in 4:1:1
Fig.12 Interpolation filter with 12C-bus control bits IFF
13.5 MHz data rate.
MEH280
o
1..-
-3
-8
Vu
(dB)
dB
--
t--
~
"""
-16
-24
I":
~
~
1\
-32
\
-40
-48
o
2
4
\,
5
\
\
6
7
fy(MHz)
Fig.13 Interpolation filter with 12C-bus control bits IFF
13.5 MHz data rate.
April 1993
\
1\
\
-56
-64
format;
3-275
= 1; IFC = 1 and IFL = X in 4:2:2 format;
Philips Semiconductors Video Products
Preliminary specification
Video enhancement
and D/A processor (VEDA2)
FEATURES
• CMOS circuit to enhance video
data and to convert luminance and
colour-difference signals from
digital-to-analog
• Digital colour transient improvement
block DCTI to increase the
sharpness of colour transitions.
The improved pin-compatible
SAA7165 can supercede the
SAA9065.
• 16-bit parallel input for 4:1:1 and
4:2:2 YUV data
• Data clock input LLC (line-locked
clock) for a data rate up to 32 MHz
• S-bit luminance and S-bit
multiplexed colour-difference
formats (optional 7-bit formats)
• MC input to support various clock
and pixel rates
• Formatter for YUV input data;
4:2:2 format, 4:1:1 format and filter
characteristics selectable
• HREF input to determine the active
line (number of pixels)
• Controllable peaking of luminance
signal
• Coring stage with controllable
threshold to eliminate noise in
luminance signal
• Interpolation filter suitable for both
fvrmats to increase the data rate in
chrominance path
• Polarity of colour-difference signals
selectable
• All functions controlled via 12C-bus
SAA7165
PARAMETER
SYMBOL
TYP.
MAX.
UNIT
VDDD
supply voltage digital part
4.5
5
5.5
V
V DDA
supply voltage analog part
4.75
5
5.25
V
IDD
total supply current
-
tbf
-
mA
VI L
input voltage LOW on YUV-bus
-0.5
-
O.S
V
V IH
input voltage HIGH on YUV-bus
2
V DDD +0.5
V
f LLC
input data rate
VO V,CD
output signal Y, ±(R-Y) and
±(B-Y) (peak-to-peak value)
32
RL V,CD
output load resistance
ILE
DC integral linearity error in
output signal (S-bit data)
DLE
DC differential error in
output signal (S-bit data)
Tamb
125
operating ambient temperature
range
0
MHz
2
V
-
n
1
LSB
-
0.5
LSB
-
70
°C
• Separate digital-to-analog converters
(9-bit resolution for Y;
8-bit for colour-difference signals)
• 1 V (p-p)/ 75 n outputs realized by
two resistors
• No external adjustments
ORDERING INFORMATION
EXTENDED
TYPE NUMBER PINS
SAA7165
April 1993
MIN.
44
3-276
PACKAGE
PIN POSITION
PLCC
MATERIAL
CODE
plastic
SOT187
»
P>
.....
"0
2:
-J
0. CD
(0
(0
w
+5V
B
00
+5V
0.11~ 15kO
~
IOCTII
0.1 ~F
0.1 ~F
~--U-~
~--U--~
0.1 ~F
0.1 ~F
Y7toYO
21 to 14
~
0.1 ~F
r-U~ H~ ~--n-~
VOOA1
VOOA2
VOOA3
CUR
V OOA4
12
31
32
37
40
41
42
..
PEAKING
AND
CORING
,..
Y
...... P>
H~
V OOO2
I'"
Y
FORMATTER
"'"-» CD
:J
-O:::r
0.1 ~F
V OOO1
,---to
Y UV-bus
+5V
~
.
Ir
DAC3
O:J
O 0
~ CD
en 3
Cy
2
~39
'-----'
1
DATA
data clock
o......
UV7 to UVO
11 t04
~
UV
FORMATTER
w
N
-..j
CREF
LL27
MC
LLC
25
26
RESN
27
SCL
28
SDA
29
~
I
24
HREF
~ f---
TIMING
CONTROL
~
r-~
INTE~t~.~~TION ~ OCT I
Ir~
1 V (I>-p)
~~~ 5OC(1~ 75
!
r
j
I---
~
~
DAC2
~36
1
i
~
4
L-...t
DACl
2
V
~~ SS01
TEST
CONTROL
22
23
(AP)
(SP)
3
V
::::~
Co
S-
en
~
~
-u
a
Co
~
en
»
~
43
±(B-Y)
Cuv
0.1 ~F
I~
'-----'
"
1 V (p_p)
£75
±(R-Y)
0(1)
"
SAA7165
I---
~SS02
g
5
.'50"(1~75 0(1)
~
30
en
g>
~.
~
500(1)
1 C-BUS
CONTROL
13
1 V (p-pt
44
~33
....
1
12,:>bus
Y
0(1)
<
m
o
-u
~
-6.
~
rL
~
CD
:J
_.-+
O.ll1~F
SWITCH
-..j
<
_.
0.
1)l~
::::~
34
35
38
V
V
V
~~ SSM ~ SSA2 ~ SSA3
MEH464
-U
~
(1) output amplitude determined by resistors (R L> 1250)
en
Fig.1 Block diagram and application circuit.
»
»
....
~
0')
01
3·
s·
III
-
(1)
PD1(7-0)
130 to 38 1 DEX~gER
(1)
SWITCHES
BUFFER
500
75n
(1)
BUFFER
22
16
129
I 39
I 40
17
VrefL
"'0
elK
(1) output amplitude determined by resistors (R L> 1200)
Fig.1 Block diagram and application circuit.
Cil
MEH331
en
»
»
--.J
......L
0)
CO
~
::J
I»
-
0
~
0
::J
Philips Semiconductors Video Products
Preliminary specification
35 MHz triple 9-bit DfA converter
for high-speed video
SAA7169
PINNING
SYMBOL
PIN
DESCRIPTION
Vo2
1
analog output voltage of channel 2
VSSA
2
analog ground (0 V)
Vo3
3
analog output voltage of channel 3
V DDA3
4
+5 V supply voltage for buffer amplifier of channel 3
CUR
5
current input for analog output buffers, decoupled to V SSA
V DDA4
6
+5 V supply voltage for analog reference part
PD3(8)
7
PD3(7)
8
PD3(6)
9
PD3(5)
10
PD3(4)
11
PD3(3)
12
PD3(2)
13
PD3(1)
14
PD3(0)
15
9-bit data input of channel 3
i.c.
16
connect to digital ground (input not used)
elK
17
clock frequency input
PD2(8)
18
PD2(7)
19
PD2(6)
20
9-bit data input of channel 2 (bits PD2(8-5))
PD2(5)
21
VSSD
22
digital ground (0 V)
VDDD
23
+5 V supply voltage for digital part
PD2(4)
24
PD2(3)
25
PD2(2)
26
PD2(1)
27
PD2(0)
28
i.c.
29
PD1(8)
30
PD1(7)
31
PD1(6)
32
PD1(5)
33
PD1(4)
34
April 1992
9-bit data input of channel 2 (bits PD2(4-0))
connect to digital ground (input not used)
9-bit data input of channel 1 (bits PD1 (8-4))
3-297
Philips Semiconductors Video Products
Preliminary specification
35 MHz triple 9-bit D/A converter
for high-speed video
SAA7169
DESCRIPTION
SYMBOL
PIN
PD1(3)
35
PD1(2)
36
PD1(1)
37
PD1(O)
38
i.c.
39
connect to digital ground (input not used)
Vref L
40
reference voltage LOW; analog ground (V SSA)
VrefH
41
internal generated reference voltage HIGH, decoupled to V SSA
VOOA1
42
+5 V supply voltage for buffer amplifier of channel 1
Vo 1
43
analog output voltage of channel 1
VOOA2
44
+5 V supply voltage for buffer amplifier of channel 2
9-bit data input of channel 1 (bits PD1 (3-0))
PIN CONFIGURATION
s
t.i
0a..
~
0a..
0a..
§:
0a..
~
0a..
§:
~
0a..
0a..
E §:
0a.. 0a..
.~
PD2(O)
v refH
PD2(1)
VDDA1
PD2(2)
va 1
PD2(3)
VDDA2
PD2(4)
V
a2
SAA7169
VSSA
Va3
PD2(6)
PD2(7)
PD2(8)
MEH337·1
Fig.2 Pin configuration.
April 1992
3-298
Philips Semiconductors Video Products
Preliminary specification
35 MHz triple 9-bit D/A converter
for high-speed video
FUNCTIONAL DESCRIPTION
The integrated monolithic CMOS
circuit SAA7169 is a triple 9-bit
digital-to-analog converter for
high-speed video applications. Its
three channels are equal. The
maximum conversion rate is 35 MHz.
The converters use a combination of
resistor chains with low-impedance
output buffers. The bottom output
SAA7169
voltage is 200 mV to reduce integral
non-linearity errors. The analog
signal, without load on output pin, is
between 0.2 and 2.2 V. Fig.1 shows
the application for 1 VI 75 n outputs,
using the serial 25 n + 50 n resistors.
Each digital-to-analog converter has
its own supply pin for purpose of
decoupling. V OOA4 is the supply
voltage for the resistor chains of the
three DACs. The accuracy of this
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER
MIN.
MAX.
UNIT
VOOO
digital supply voltage range (pin 23)
-0.3
7
V
V OOA1
analog supply voltage range (pin 42)
-0.3
7
V
VOOA2
analog supply voltage range (pin 44)
-0.3
7
V
VOOA3
analog supply voltage range (pin 4)
-0.3
7
V
V OOA4
analog supply voltage range (pin 6)
-0.3
VdiffGNO difference voltage VSSO -VSSA(1 to 4)
7
V
±100
mV
Vn
voltage on all input pins 7 to 15,
18 to 21 and 24 to 40
-0.3
VOOO
V
P tot
total power dissipation
0
tbf
mW
Tamb
operating ambient temperature range
0
70
°C
T stg
storage temperature range
-65
150
°C
V ESO
electrostatic handling* for all pins
±2000
V
* Equivalent to discharging a 100 pF capacitor through a 1.5 kn series resistor.
April 1992
3-299
supply voltage influences directly the
output amplitudes.
The current CUR into pin 5 is 0.3 mA
(VOOA4 = 5 V, RS -6 = 15 kil); a larger
current improves the bandwidth but
increases the integral non-linearity.
Philips Semiconductors Video Products
Preliminary specification
35 MHz triple 9-bit D/A converter
for high-speed video
SAA7169
CHARACTERISTICS
VOOD = 4.5 to 5.5 V; VOOA = 4.75 to 5.25 V; ClK = 35 MHz; fOATA = 17.5 MHz (squarewave, full scale);
Tamb = 0 to 70 °C; measurements taken in Fig.1 unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VOOO
supply voltage range (pin 23)
for digital part
4.5
5
5.5
V
V OOA1
supply voltage range (pin 42)
for buffer of DAC 1
4.75
5
5.25
V
V OOA2
supply voltage range (pin 44)
for buffer of DAC 2
4.75
5
5.25
V
VODA3
supply voltage range (pin 4)
for buffer of DAC 3
4.75
5
5.25
V
V ODA4
supply voltage range (pin 6)
DAC reference voltage
4.75
5
5.25
V
IOOD
supply current
for digital part; note 1
-
20
mA
supply current (IOOAl to IOOA4)
without load on outputs -
-
18
mA
-
0.8
V
IOOA
9-blt data inputs (pins 7 to 15; 18 to 21, 24 to 28 and 30 to 38)
input voltage lOW
-0.5
VIH
input voltage HIGH
2.0
CI
input capacitance
10
pF
10
flA
VI L
Ileak
input leakage current
tsu
data set-up time
tHO
data hold time
ClK input (pin 17)
Fig.3
11
frequency range
1
input voltage lOW
-0.5
VIH
input voltage HIGH
2.0
CI
input capacitance
-
Ileak
input leakage current
tCLK
cycle time
duty factor
rise time
tf
fall time
ns
ns
Fig.3
VI L
tpH
-
3
fCLK
tr
Vooo+0.5 V
-
35
MHz
0.8
V
VDDO+0.5 V
10
pF
10
flA
28.5
tCLK H / tCLK
40
ns
50
-
60
%
5
ns
6
ns
Digital-to-analog converters (pins 5, 6 and 40)
V OOA4
ICUR
reference input voltage for internal
resistor chains (pin 6)
input current (pin 5)
4.75
5
R6 -5 = 15 kQ
5.25
V
400
flA
-
V
0.24
V
2.3
V
Analog outputs Vol; Vo2 and Vo3 (pins 43, 1 and 3)
Vo
nominal output signal (peak-to-peak value)
without load
V43 ,1,3
minimum output voltage
without load; VOOA4 = 5 V 0.16
maximum output voltage
without load; VDDA4 = 5 V 2.1
DAC to DAC matching
between all channels
DTDM
April 1992
3-300
2
-
/30
I
mV
Preliminary specification
Philips Semiconductors Video Products
35 MHz triple 9-bit D/A converter
for high-speed video
SYMBOL
CONDITIONS
PARAMETER
B
output signal bandwidth
SAA7169
MIN.
-3 dB
20
48
(lCR
crosstalk attenuation
note 2
DNL
differential non-linearity
9-bit data; RL
INL
integral non-linearity
R43,1,3
internal serial output resistor
RL 43,1,3
load resistance on output
= 125 .n 9-bit data; RL = 125 .n 125
TYP.
-
MAX.
-
25
-
UNIT
MHz
dB
±0.5
LSB
±0.2
0/0
-
.n
.n
Notes to the characteristics
1. With fCLK = 35 MHz; fOATA = 17.5 MHz (squarewave, full scale)
2. Crosstalk from channel to channel. One DAC with digital 5 MHz (sinusoidal, full scale) in'put signal, the other input
data LOW. Measurements taken on outputs with 5.46 MHz filters (-3 dB at 5.87 MHz and -45 dB at 7.24 MHz).
MEH338
data valid
Fig.3 Input data timing.
April 1992
3-301
Philips Semiconductors Video Products
D·igital video encoder
(square pixel with Macrovision)
SAA7183
The SAA7183 Digital Video Encoder is functionally equivalent to the SAA7187. Both the electrical and physical
parameters are identical.
The only distinction is that the SAA7183 can be programmed to insert anti-taping encoding (Macrovision) onto the
video signal.
Use of Macrovision technology requires a license from Macrovision. Sample request and sales orders require the
following procedure:
Sample Requests
• Contact Bill Krepick, Macrovision
Phone: (415)691-2900
Fax:
(415)691-2999
• Macrovision will send an NDA to the customer
• Returned signed NDA will be senUo Macrovision and to Monica Howes, Tactical Marketing,
Philips Semiconductors'
Fax: (408)991-2133
• Samples will then be sent to the customer
Sales Orders
• If the customer has a Macrovision license:
- The customer provides Philips with written confirmation of the license
- Marketing will retain the written confirmation
- Customer can then purchase part
• If the customer does not have a Macrovision license:
- The customer must obtain a license or waiver from Macrovision
- Customer must provide Philips with written confirmation of the license or waiver from Macrovision
- Marketing retains written information
- Customer purchases part
Neither parts nor programming information will be sent to the customer until the above conditions are met.
May 18,1994
3-302
Preliminary specification
Philips Semiconductors Video Products
SAA7186
Digital video scaler
1. FEATURES
• Scaling of video picture windows
down to randomly sized windows
• Processes maximum 1023 pixels
per line and 1023 lines per field
• Two-dimensional data processing
for improved signal quality of
scaled video data and for
compression of video data
• 16-bit YUV input data buffer
• Interlace/non-interlace video data
processing and field control
• Line memories in Y path and UV
path to store two lines, each with
2 x 768 x 8 bit capacity
• Vertical sync processing by scale
control
• Non-scaled mode to get full picture
or to gate videotext lines
• UV input and output data
binary/two's complement
• Switchable RGB matrix and antigamma ROMs
• 16-word FIFO register for 32-bit
output data
• Output formats: 5-bit and
8-bit RGB, 8-bit YUV or 8-bit
monochrome
3. QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
Voo
supply voltage
100 tot
total supply current
(inputs LOW, without output load) -
4.5
TYP.
MAX.
UNIT
5
5.5
V
180
mA
VI
data input level
TTL-compatible
Vo
data output level
TTL-compatible
LLC
input clock frequency
-
32
MHz
Tamb
operating ambient temperature
range
0
70
°C
4. ORDERING INFORMATION
EXTENDED
TYPE NUMBER PINS
SAA7186
May 1993
100
PACKAGE
PIN POSITION
QFP
MATERIAL
CODE
plastic
SOT317
3-303
2. GENERAL DESCRIPTION
The CMOS circuit SAA7186 scales
and filters digital video data to
randomly sized picture windows.
YUV input data in 4:2:2 format are
required (SAA7191 B source).
~
~
~
<0
<0
OJ
r-
c..>
0
0
+5V
'"
»
c
VERTICAL FILTE~
..---
33
YIN
(7-0)
-~.
~
-,~
to 22
LUMINANCE
DECIMATIONJ--FILTER
~
INPUT
DATA
BUFFER
t-+- tu
I--+- ~
LINE
MEMORY
(2x8x768)
t-+-
UV
-~
~
CHROMA
DECIMATION
FILTER
HREF
37.....
W
~
RESN
43
SCL
45
44
FOL~~WED ~
ANTI-GAMMJI
ROMs
~r--
OUTPUT
FORMATIER
~
2
1
46
IICSA
~
CHROMA
KEYER'----'-'
I
f
~ controls
.
""
~
status
';::=
~I-+
49
r+
2
<
o·
0
-
Ci
CD
0
en
0
CD
3
::J
C.
c::
!l
0
iiJ
S
c.
Sl>
0
CD
"'tJ
CD
8.
~
VRO (31 to 0);
32-bitVRAM
port output
RGBorYUV
INCADR
HFL
LNQ
HREFD
SAA7186
9,15,21,27,29,39,34,41,52'_154, 60, 66, 72, 79, 84,90, 96
n.c.
3,16,28,42,
~,6~7~OO
j
35
en
. en
.c::
t---""
1
CLOCK
GENERATION
~
OUTPUT
FIFO
REGISTER
BTST
:D
~
"'tJ
~
-6'
;:::;:
Sl>
-,:
joutputPins (1):
56 to 64
68 to 75, 77
00 to 00
92 to 100 1 -""'
i
I
1C
CONTROL
~
SCALE CONTROL
•
-
~
.....,$,.
I ~
SDA
..
~ tii.
t-+- ~ t-J--- INTERPOLATOR V
t-+- ~
I--
LINE
MEMORY
(2x8x768)
f4
L -_ _ _---,
~
U
Y
I....--
c'w
I
~
~
-~
..
RGB
MATRIX
VERTICAL FILTER
to 10
c..>
Y
......::t.
~
UVIN
(7-0)
VLCK
[5C
~ r-- VOEN
1 55,67,76,91
Q
Y
Q
~t--
L 5, 14, 26,40,
0
cO·
36
7
8
SP
AP
1 4 ,6,
I
VSS1 to Vssa
.I.C.
CREF
~C
~_
~
~_
MEH422,l
(1) without pins 60, 72, 84 and 96,
these pins are not connected
"'tJ
~
3'
(f)
Fig.1 Block diagram.
~
.......
-.
ex>
0>
s'
1\)..
-= >= >=
Lt)
u..
(0
0
cO
u..
LU
C,)
LU
C,)
--1
--1
I
a:
a:
(J)
>
0
C
'"
o .
o to!
>
r::
ih
(fl
z
(J)
LU
> a:
«
0
(J)
Fig.2 Pin configuration.
May 1993
3-308
--1
C,)
(J)
«
(J)
g
I-
(J)
I-
co
a:
0
«
C,)
~
z
--1
LU
I
>
u..
0
MEH421
Preliminary specification
Philips Semiconductors Video Products
Digital video scaler
SAA7186
7. FUNCTIONAL DESCRIPTION
Sequential input data
Adaptive filterselection (AFS = 1):
The input port is output of Philips
digital video multistandard decoders
(SAA7151 B, SAA7191 B) or other
similar sources.
The SAA7186 input supports the
16-bit YUV 4:2:2 format.
The video data from the input port
are converted into a unique internal
two's complement data stream arid
are processed in horizontal direction
in two separate decimation
filters.Then they are processed in
vertical direction by the vertical
processing unit (VPU).
Chrominance data are interpolated
to a 4:4:4 format; a chroma keying
bit is generated.
The 4:4:4 YUV data are then
converted from the YUV to the RGB
domain in a digital matrix. ROM
tables in the RGB data path can be
used for anti-gamma correction of
gamma-corrected input signals.
Uncorrected RGB and YUV signals
can be bypassed.
A scale control unit generates
reference and gate signals for
scaling of the processed video data.
After data formatting to the various
VRAM port formats, the scaled video
data are buffered in the 16 word
x 32-bit output FIFO register. The
FIFO output is directly connected to
the VRAM output bus VRO(31-0).
Specific reference signals support an
easy memory interfacing.
All functions of the SAA7186 are
controlled via 12C-bus using 17
subaddresses. The external
microcontroller can get information
by reading the status register.
- are limited to maximum 768 active
pixels per line if the vertical filter is
active
scaling ratio
filter function
(refer to 12C section)
XD/XS
horizontal
:51
:514/15
:511/15
:57115
:53/15
bypassed
filter 1
filter 6
filter 3
filter 4
YDIYS
vertical
:51
bypassed
filter 1
filter 2
Video input port
The 16-bit YUV input data in 4:2:2
format (Table 1) consist of 8-bit
luminance data Y (pins YIN(7-0))
and 8-bit time-multiplexed
colour-difference data UV
(pins UVIN(7-0)).
The input data are clocked in by the
signals LLC and CREF (Fig.3).
HREF and VS inputs define the video
scan pattern (window).
- UV can be processed in straight
binary and two's complement
representation (controlled by TCC)
Decimation filters
The decimation filters perform
accurate horizontal filtering of the
input data stream.
Signal characteristics are matched in
front of the pixel decimation stage,
thus disturbing artifacts, caused by
the pixel dropping, are reduced.
The signal bandwidth can be
reduced in steps of:
Nap filter = -6 dB at 0.325 pixel rate
3-tap filter =-6 dB at 0.25 pixel rate
4-tap filter =-6 dB at 0.21 pixel rate
5-tap filter =-6 dB at 0.125 pixel rate
9-tap filter =-6 dB at 0.075 pixel rate
The different characteristics are
choosen dependent on the defined
scaling parameters in an adaptive
filter mode (AFS-bit = 1).
The filter characteristics can also be
selected independently by control
bits HF2 to HFO at AFS-bit =O.
Vertical filters
Yand UV data are handled in
separate filters (Fig.1). Each of the
two line memories has a capacity of
2 x 768 x 8-bit. Thus two complete
video lines of 4:2:2 YUV data can
be stored. The VPU is split into two
memory banks and one arithmetic
unit. The available processing
modes, respectively transfer
functions, are selectable by the bits
VP1 and VPO if AFS =O.
An adaptive mode is selected by
AFS = 1. Disturbing artifacts,
generated by line dropping, are
reduced.
:513/15
:54115
RGB matrix
Y data and UV data are converted
after interpolation into RGB data
according to CCIR601 recommendation.
Data are bypassed in YUV or
monochrome modes.
Table 1 4: 2 : 2 format (pixels per
line). The time frames are controlled by
the HREF signal.
INPUT
PIXEL BYTE SEQUENCE
YIN7
YIN6
YIN5
YIN4
YIN3
YIN2
YIN1
YINO
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
YeO
Y07
Y06
Y05
Y04
Y03
Y02
Y01
YoO
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
YeO
Y07
Y06
Y05
Y04
Y03
Y02
Y01
YoO
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
YeO
UVIN7
UVIN6
UVIN5
UVIN4
UVIN3
UVIN2
UVIN1
UVINO
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
UeO
Ve7
Ve6
Ve5
Ve4
Ve3
Ve2
Ve1
VeO
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
UeO
Ve7
Ve6
Ve5
Ve4
Ve3
Ve2
Ve1
YeO
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
UeO
Yframe
a
2
3
4
UVframe
0
e = even pixel; 0
May 1993
3-309
1
2
= odd pixel
4
Philips Semiconductors Video Products
Preliminary specification
Digital video scaler
SAA7186
The matrix equations are these
considering the digital quantization:
R = Y + 1.375 V
G = Y - 0.703125 V - 0.34375 U
B = Y + 1.734375 U.
Anti-gamma ROM tables:
ROM tables are implemented at the
matrix output to provide anti-gamma
correction of the RGB data. A curve
for a gamma of 1.4 is implemented
The tables can be used (RTB-bit = 0)
to compensate gamma correction for
linear data representation of RGB
output data.
Chrominance signal keyer
Scale control and vertical regions
The keyer generates an alpha signal
to achieve a 5-5-5 +ex -RGB alpha
output signal. Therefore, the
processed UV data amplitudes are
compared with thresholds set via
12 e-bus (subaddresses "oe to OF").
A logical "1" signal is generated if the
amplitude is inside the specified
amplitude range, otherwise a logical
"0" is generated.
Keying can be switched off by setting
the lower limit higher than the upper
limit ("oe or OE" and "OD or OF").
The scale control block se includes
vertical address/sequence counters
to define. the current position in the
input field and to address the internal
VPU memories.
To perform scaling, XD of XS pixel
selection in horizontal direction and
YD of YS line selection in vertical
direction are applied. The pixel and
line dropping are controlled at the
input of the FI Fa register.
To control the decimation filter
function and the vertical data
processing in the adaptive mode
LLC
CREF
HREF
---.1/:.'::
~
'startof
I
active line
,:
~:
Byte numbers for pixies:
Y signal
U and V signal
MEH411
LLC
CREF
:: end of ~,,~------------------------------------,
HREF
: active line :
,,
:
Byte number for pixels:
'
'
:
Y signal
U and V signal
MEH410
Fig.3 Horizontal and data multiplex timing.
May 1993
3-310
Preliminary specification
Philips Semiconductors Video Products
Digital video scaler
(AFS = 1), the scaling ratio in
horizontal and vertical direction is
estimated in the SC block.
The input field can be divided into
two vertical regions - the bypass
region and the scaling region, which
are defined via 12C-bus by the
parameters VS, VC, YO and YS.
Vertical bypass region:
Data are not scaled and independent
of 12C-bits FS1, FSO the output
format is always 8-bit grayscale
(monochrome). The SAA7186
outputs all active pixels of a line,
defined by the HREF input signal if
the vertical bypass region is active.
This can be used, for example, to
store videotext information in the
field memory.
The start line of the bypass region is
defined by VS; the number of lines to
be bypassed is defined by VC.
Vertical scaling region:
SAA7186
- the offsets XO and YO have to be
set according to the internal
processing delays to ensure the
complete number of destination
pixels and lines (Table 6).
The signal levels of the RGB formats
are limited in 8-bit to "0" or "255".
For the 5-bit RGB formats a
truncation from 8-bit to 5-bit is
implemented.
- the scaling parameters can be
used to perform a panning function
over the video frame/field.
Fill values are inserted dependent on
longword position and destination
size:
Output data representation and
levels
- "0"
Output data representation of the
YUV data can be modified by bit
MCT (subaddress 10).
The DC gain is 1 for YUV input data.
The corresponding RGB levels are
defined by the matrix equations.
The luminance levels are limited
according to CCIR 601
in RGB formats and for Y
two'2 complement U, V
- "128" for U, V (straight binary)
- "255" in 8-bit grayscale format
The unused output values of the
YUV and grayscale formats can be
used for other purposes.
16 (239) = black
235 (20) = white
( .. ) = grayscale luminance levels
if the YUV or monochrome
luminance output formats are
selected.
Data is scaled with start at line YO
and the output format is selected
when FS1, FSO are valid.
This is the "normal operation" area.
The input/output screen dimensions
in horizontal and vertical direction
are defined by the parameters
XO, XS and XD for horizontal
vertical sync ----..---v-ert-ic-al---.
blanking
::l~~:::::::~~I:'4-firstvalid line
YO, YS and YD for vertical.
The circuit processes XS samples of
a line. Remaining pixels are ignored
if a line is longer than XS. If a line is
shorter than XS, processing is
aborted when the falling edge of
HREF is detected.
vertical bypass start ~ __
t. ____________ -
, "CO ,,,,,,,~ _:b:~~:::.::: :1~~:,~pa~
scaling region
-----------------
Vertical regions in Fig.4:
1
scaling region count
equals YS Y-size source
MEH357.1
- the two regions can be programmed
via 12C-bus, whereby regions
should not overlap (active region
overrides the bypass region).
- the start of a normal active picture
depends on video standard and
has to be programmed to the
correct value.
May 1993
000",
Fig.4 Vertical regions.
3-311
Philips Semiconductors Video Products
Preliminary specification
Digital video scaler
SAA7186
Table 2 VRAM port output data formats at EEE-bit =a dependend on ES1 and ESO bits (set via 12C-bus)
FS1 = 1;FSO = 1
8-bit monochrome
32-BIT WORDS
PIXEL
OUTPUT
BITS
FS1 = 0; FSO = 0
RGB 5-5-5 + 1
32-BIT WORDS
FS1 = 0; FSO = 1
YUV 4:2:2
32-BIT WORDS
FS1 = 1; FSO = 0
YUV 4:2:2 TEST
16-BIT WORDS
PIXEL
ORDER
n
n+2
n+4
n
n+2
n+4
n
n+1
n+2
n
n+1
n+4
n+5
n+8
n+9
VR031
VR030
VR029
VR028
ex
R4
R3
R2
ex
R4
R3
R2
ex
R4
R3
R2
Ye7
YeG
YeS
Ye4
Ye7
YeG
Ye5
Ye4
Ye7
YeG
Ye5
Ye4
Ye7
YeG
Ye5
Ye4
Yo7
YoG
Yo5
Yo4
Ye7
YeG
Ye5
Ye4
Ya7
YaG
Ya5
Ya4
Ya7
YaG
YaS
Ya4
Ya7
YaG
Ya5
Ya4
VR027
VR02G
VR02S
VR024
R1
RO
G4
G3
R1
RO
G4
G3
R1
RO
G4
G3
Ye3
Ye2
Ye1
Yea
Ye3
Ye2
Ye1
Yea
Ye3
Ye2
Ye1
Yea
Ye3
Ye2
Ye1
Yea
Yo3
Yo2
Yo1
YoO
Ye3
Ye2
Ye1
Yea
Ya3
Ya2
Ya1
YaO
Ya3
Ya2
Ya1
YaO
Ya3
Ya2
Ya1
YaO
VR023
VR022
VR021
VR020
G2
G1
GO
84
G2
G1
GO
84
G2
G1
GO
84
Ue7
UeG
UeS
Ue4
Ue7
UeG
UeS
Ue4
Ue7
UeG
Ue5
Ue4
Ue7
Ue6
UeS
Ue4
Ve7
Ve6
VeS
Ve4
Ue7
Ue6
UeS
Ue4
Yb7
YbG
Yb5
Yb4
Yb7
Yb6
Yb5
Yb4
Yb7
Yb6
YbS
Yb4
VR019
VR018
VR017
VR01G
83
82
81
80
83
82
81
80
83
82
81
80
Ue3
Ue2
Ue1
UeO
Ue3
Ue2
Ue1
UeO
Ue3
Ue2
Ue1
UeO
Ue3
Ue2
Ue1
UeO
Ve3
Ve2
Ve1
YeO
Ue3
Ue2
Ue1
UeO
Yb3
Yb2
Yb1
YbO
Yb3
Yb2
Yb1
YbO
Yb3
Yb2
Yb1
YbO
PIXEL
ORDER
n+1
n+3
n+5
n+1
n+3
n+5
OUTPUTS NOT USED
n+2
n+3
n+6
n+7
n+10
n+11
VR015
VR014
VR013
VR012
ex
R4
R3
R2
ex
R4
R3
R2
ex
R4
R3
R2
Yo7
YoG
Yo5
Yo4
Yo7
Yo6
Yo5
Yo4
Yo7
YoG
Yo5
Yo4
X
X
X
X
X
X
X
X
X
X
X
X
Yc7
YcG
Yc5
Yc4
Yc7
YcG
Yc5
Yc4
Yc7
Yc6
Yc5
Yc4
VR011
VR010
VR09
VR08
R1
RO
G4
G3
R1
RO
G4
G3
R1
RO
G4
G3
Yo3
Yo2
Yo1
YoO
Yo3
Yo2
Yo1
YoO
Yo3
Yo2
Yo1
YoO
X
X
X
X
X
X
X
X
X
X
X
X
Yc3
Yc2
Yc1
YcO
Yc3
Yc2
Yc1
YcO
Yc3
Yc2
Yc1
YcO
VR07
VR06
VR05
VR04
G2
G1
GO
84
G2
G1
GO
84
G2
G1
GO
84
Ve7
Ve6
Ve5
Ve4
Ve7
VeG
Ve5
Ve4
Ve7
Ve6
Ve5
Ve4
X
X
X
X
X
X
X
X
X
X
X
X
Yd7
Yd6
Yd5
Yd4
Yd7
Yd6
Yd5
Yd4
Yd7
Yd6
Yd5
Yd4
VR03
VR02
VR01
VROO
83
82
81
80
83
82
81
80
83
82
81
80
Ve3
Ve2
Ve1
VeO
Ve3
Ve2
Ve1
VeO
Ve3
Ve2
Ve1
VeO
X
X
X
X
X
X
X
X
X
X
X
X
Yd3
Yd2
Yd1
YdO
Yd3
Yd2
Yd1
YdO
Yd3
Yd2
Yd1
YdO
ex = keying bit; R, G, 8, Y. U and V = digital signals; e =even pixel number;
abc d = consecutive pixels
May 1993
3-312
0
= odd pixel number;
Philips Semiconductors Video Products
Preliminary specification
Digital video scaler
SAA7186
Table 3 VRAM port output data formats at EFE-bit - 1 dependend on FS1 and FSO bits (set via 12C-bus)
PIXEL
OUTPUT
BITS
FS1 = 0; FSO = 0
RGB 5-5-5 + 1
16-BIT WORDS
FS1 =0; FSO = 1
VUV 4:2:2
16-BIT WORDS
FS1 = 1; FSO = 0
RGB 8-8-8
24-BIT WORDS
FS 1= 1; FSO = 1
8-bit monochrome
16-BIT WORDS
PIXEL
ORDER
n
n+1
n+2
n
n+1
n+2
n
n+1
n+2
n
n+1
n+2
n+3
n+4
n+5
VR031
VR030
VR029
VR028
a
a
a
R4
R3
R2
R4
R3
R2
R4
R3
R2
Ye?
YeS
Ye5
Ye4
Yo?
YoS
Yo5
Yo4
Ye?
YeS
Ye5
Ye4
R?
RS
R5
R4
R?
RS
R5
R4
R?
RS
R5
R4
Ya?
YaS
Ya5
Ya4
Ya?
YaS
Ya5
Ya4
Ya?
YaS
Ya5
Ya4
VR02?
VR02S
VR025
VR024
R1
RO
G4
G3
R1
RO
G4
G3
R1
RO
G4
G3
Ye3
Ye2
Ye1
YeO
Y03
Y02
Y01
YoO
Ye3
Ye2
Ye1
YeO
R3
R2
R1
RO
R3
R2
R1
RO
R3
R2
R1
RO
Ya3
Ya2
Ya1
YaO
Ya3
Ya2
Ya1
YaO
Ya3
Ya2
Ya1
YaO
VR023
VR022
VR021
VR020
G2
G1
GO
B4
G2
G1
GO
B4
G2
G1
GO
B4
Ue?
UeS
Ue5
Ue4
Vel
VeS
Ve5
Ve4
Ue?
UeS
Ue5
Ue4
G?
GS
G5
G4
G?
GS
G5
G4
G?
GS
G5
G4
Yb?
YbS
Yb5
Yb4
Yb?
YbS
Yb5
Yb4
Yb?
YbS
Yb5
Yb4
VR019
VR018
VR01?
VR01S
B3
B2
B1
BO
B3
B2
B1
BO
B3
B2
B1
BO
Ue3
Ue2
Ue1
UeO
Ve3
Ve2
Ve1
YeO
Ue3
Ue2
Ue1
UeO
G3
G2
G1
GO
G3
G2
G1
GO
G3
G2
G1
GO
Yb3
Yb2
Yb1
YbO
Yb3
Yb2
Yb1
YbO
Yb3
Yb2
Yb1
YbO
PIXEL
ORDER
n
n+1
n+2
n
n+1
n+2
n
n+1
n+2
n
n+1
n+2
n+3
n+4
n+5
VR015
VR014
VR013
VR012
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B?
BS
B5
B4
B?
BS
B5
B4
B?
BS
B5
B4
X
X
X
X
X
X
X
X
X
X
X
X
VR011
VR010
VR09
VR08
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B3
B2
B1
BO
B3
B2
B1
BO
B3
B2
B1
BO
X
X
X
X
X
X
X
X
X
X
X
X
VRO?(1)(2)
VROS (2)
VR05 (2)
VR04 (2)
a
a
a
a
a
a
a
a
a
a
OlE
VGT
HGT
OlE
VGT
HGT
OlE
VGT
HGT
X
OlE
VGT
HGT
a
OlE
VGT
HGT
OlE
VGT
HGT
OlE
VGT
HGT
OlE
VGT
HGT
OlE
VGT
HGT
OlE
VGT
HGT
OlE
VGT
HGT
OlE
VGT
HGT
VR03
VR02 (2)
VR01 (2)
VROO (2)
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
X
HRF
LNQ
PXQ
ex = keying bit; R, G, B, Y. U and V = digital signals; e = even pixel number; 0 = odd pixel number; abc d = consecutive pixels;
OlE = odd/even flag
(1) YUV 1S-bit format: the keying signal a is defined only for YU time steps. The corresponding YV sample has also to be
keyed. The a signal in monochrome mode can be used only in the transparent mode (TTR = 1), in this case Ya = Vb.
(2) Data valid only when transparent mode active (TTR-bit = 1) and VCLK pin connected to LLC/2 clock rate.
May 1993
3-313
Philips Semiconductors Video Products
Digita~' video
Preliminary specification
scaler
Output FIFO register and VRAM
output port
SAA7186
-
The output FIFO register is the buffer
between the video data stream and
the VRAM data input port. Resized
video data are buffered and
formatted. 32-, 24- and 16-bit video
data modes are supported. The
various formats are selected by the.
bits EFE, FS1 and FSO. VRAM port
formats are shown in Tables 2 and 3.
The FIFO register capacity is 16
word x 32 bit (for 32-, 24-, or 16-bit
video data). The bits LW1 and LWO
can be used to define the position of
the first pixel each line in the 32-bit
longword formats or to shift the UV
sequence to VU in the 16-bit YUV
formats (LW1 = 1).
VRAM port inputs are:
VCLK to clock the FIFO register
output data and VOEN to enable
output data.
-
VRAM port outputs are:
the HFL flag (half-full flag), the signal
INCADR (refer to section "data burst
transfer") and the reference signals
for pixel and line selection on outputs
VRO(7-0) (only for 24- and 16-bit
video data formats refer to
"transparent data transfer").
=
Data transfer on the VRAM port can
be done asynchroneously controlled
by outputs HFL, INCADR and input
VCLK (data burst transfer with bit
TTR= 0).
-
VCLK input signal to clock the
FIFO register output data VRO(n).
New data are placed on the VRO(n)
port with the rising edge of
VCLK (Fig.5).
-
VOEN input enables output data
VRO(n).The outputs are in 3-state
mode at VOEN = HIGH.
VOEN changes only when VCLK
Data burst transfer mode
Data transfer on the VRAM port is
asynchroneously (TTR = 0). This
mode can be used for all output
formats. Four signals for
communication with the external
memory are provided.
May 1993
INCADR output signal is used in
combination with HFL to control
horizontal and vertical address
generation for a memory
controller. The pulse sequence
depends on field formats
(interlace/ non-interlace or
odd/even fields, Figures 6 and 7)
and control bits OF (subaddress
00).
HFL 1 at the rising edge of
INCADR:
the end of line is reached,
request for line address increment
HFL = 0 atthe rising edge of
INCADR:
the end of field/frame is reached,
request for line and pixel
addresses reset
(The distance from the last halffull request HFL to the INCADR
pulse may be longer than 64 x
LLC. The HFL state is defined for
minimum 4 x LLC in front of the
rising edge of INCADR and
minimum 2 x LLC afterwards.)
VRAM port transfer procedures
Data transfer on the VRAM port can
be done synchroneously controlled
by output reference signals on
outputsVRO(7-0) and a clock rate of
LLC/2 on input VCLK (transparent
data transfer with bit
TTR = 1 and EFE = 1).
The scaling capability of the
SAA7186 can be used in various
applications.
H FL flag, the half-full flag of the
FIFO output register is raised
when the FI FO contains at least 8
data words (HFL = HIGH).
By setting HFL = 1, the SAA7186
requests a data burst transfer by
the external memory controller,
that has to start a transf~r cycle
within the next 32 LLC cycles for
32-bit longword modes (16 LLC
cycles for 16- and 24-bit modes).
If there are pixels in the FIFO at
the end of a line, which are not
transferred, the circuit fills up the
FIFO register with "fill pixels" until
it is half-full and sets the HFL flag
to request a data burst transfer.
After transfer is done, HFL is
used in combination with INCADR
to indicate the line increments
(Figures 6 and 7).
3-314
is LOW. If VCLK pulses are
applied during VOEN = HIGH, the
outputs remain inactive, but the
FIFO register accepts the pulses.
Transparent data transfer mode
Data transfer on the VRAM port can
be achieved synchroneously (TTR =1).
With a contineous clock rate of
LLC/2 on input VCLK, the SAA7186
delivers a contineously processed
data stream. Therefore, the extended
formats of the VRAM output port
have to be selected (bit EFE = 1 ;
Table 3). The reference and gate
signals on outputs VRO(6-1) and the
LNQ signal are delivered in each
field (means scaled and ignored
fields). The PXO signal (also VROO)
is only delivered in active fields.
The output signals VRO(7-0) can be
used to buffer qualified pre-processed
RGB or YUV video data (notice: the
YUV data are only valid in qualified
time slots). Control output signals in
Table 3 are:
a.
keying signal of the chroma
keyer
OlE odd/even field bit according
to the internal field processing
VGT vertical gate signal, "1"
marks the scaling window in
vertical direction from YO to
(YO + YS) lines, cut by VS.
HGT horizontal gate signal, "1"
marks horizontal direction
from XO to (XO + XS) lines,
cut by HREF.
HRF delay compensated
horizontal reference signal.
LNQ line qualifier signal, active
polarity is defined by QPL bit.
PXQ pixel qualifier signal, active
polarity is defined by QPP bit.
Power-on reset
- the FI FO register contents are
undefined
- outputs VRO are set to highimpedance state
- output INCADR = HIGH
- output HFL= LOW until the VPE
.bit is set to "1"
- subaddress "10" is set to OOh and
VPE-bit in subaddress "00" is set
to zero (Table 4).
Philips Semiconductors Video Products
Preliminary specification
Digital video scaler
SAA7186
PIXCLK
(LLC/2)
~il~~~~:ory
HFL
] ' - -_ _
6__
~~
7
---.----..:[I. I.
~-----,
min.8 samples
:
: . . - - available in FIFO
:..,
max. 32LLC
(16 PIXCLK
:
In
:::::
iii ' , , , ,
~:.
:,"
:
-----..
VCLK
1 transfer cycle
(8 VCLK cycles)
VOEN
----------------;~~L_~'_~'_~,_~,_~~
VRO(n)
MEH407
Fig.S Output port transfer to VRAM at 32-bit data format without scaling. If VCLK cycles occur at VOEN = HIGH,
the FIFO register is unchanged, but the outputs VRO(31-0) remain in 3-state position.
line n
line n+ 1
i-
internal
signal
active
video
•
:
14--------
vertical blanking
HFL
min. set-up time
INCADR
(1)
(1) pulse only at
interlace scan
L
line increment (VRAM) only in odd field
vertical reset
Fig.6 Vertical reset timing to the VRAM.
May 1993
3-315
MEH406
Philips Semiconductors Video Products
Preliminary specification
Digital video scaler
SAA7186
line n+1
internal
signal
active
video
horizontal blanking
first half-full request for line n+ 1
I
HFL
~I
min. set-up time
INCADR
(1) pulse only at
interlace scan
line increment (VRAM)
MEH405·1
Fig.7 Horizontal increment timing to the VRAM.
:..::.J
/
vs
line qualifier
LNQ
LNQ
.J
HGT = GTH x LNQ
L
....r-----l-
--n
\
"""""""""""""""""
VGT \ -----:-T:~ ~;~~~~,~~~~ -----.
HRF
GTH
PXQ
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.J
I..
line·
.
.1
Fig.S Reference signals for scaling window.
May 1993
3-316
MEH472·1
Preliminary specification
Philips Semiconductors Video Products
SAA7186
Digital video scaler
Field processing
The phase of the field sequence
(odd/even dependent on inputs
HREF and VS) is detected by means
of the falling edge of VS. The current
field phase is reported in the status
byte by the OEF bit (Table 5). OEF
bit can be stable 0 or 1 for noninterlaced input frames or non
standard input signals VS and/or
HREF (nominal condition for VS and
HREF - SAA7191 B with active
vertical noise limiter). A free-running
odd/even flag is generated for
internal field processing if the
detection reports a stable OEF bit.
8. OPERATION CYCLE
The operation is synchronized by the
input field. The cycle is specified in
the flow chart (Fig.9).
The circuit is inactive after power-on
reset, VPO is 0 and the FIFO control
is set "empty". The internal control
registers are updated with the falling
edge of VS signal. The circuit is
switched active and waits for a
transmission of VS and a vertical
reset sequence to the memory
controller. Afterwards, the circuit
waits for the beginning of a scaling or
bypass region. The processing of a
current line is finished when a
vertical sync pulse appears. The
May 1993
The POE bit (subaddress OB) can be
used to change the polarity of the
internal flag (in case of non-standard
VS and HREF signals) to control the
phase of the free-running flag, and to
compensate mis-detections. Thus,
the SAA7186 can be used under
various VS/HREF timing conditions.
The SAA7186 operates on fields. To
support progressive displays and to
avoid movement blurring and
artifacts, the circuit can process both
or single fields of interlaced or noninterlaced input data. Therefore the
OF bits can be used. The bits OF1
and OFO (Table 6) determine the
INCADR/HFL generation in "data
circuit performs a coefficient update
and generates a new vertical reset (if
it is still active).
Line processing starts when a line is
decided to be active, the circuit starts
to scale it. Active pixels are loaded
into the FIFO register. An HFL flag is
generated to initialize a data transfer
when eight words are completed.
The line end is reached when the
programmed pixel number is
processed or when a horizontal sync
pulse occurs. If there are pixels in
the FIFO register, it is filled up until it
is half-full to cause a data transfer.
Horizontal increment pulses are
transmitted after this data transfer.
3-317
burst transfer mode". One of the
fields (odd or even) is ignored when
OF1 = 1 ; then no line increment
sequence (INCADR/HFL) is
generated, the vertical reset pulse is
only generated.
With OF1 = OFO = 0 the circuit
supports correct interlaced data
storage. Two INCADR/HFL
sequences are generated in each
qualified line; additionally an
INCADR/HFL sequence after the
vertical reset sequence of an odd
field is generated. Thereby, the
scaled lines are automatically stored
in the right sequence.
Remarks:
The SAA7186 will always wait for the
HREFIVS pulse before the line
increment/vertical reset sequence is
performed.
After each line/field, the FIFO control
is set to empty when INCADR/HFL
sequence is transmitted.
No additional actions are necessary
if the memory controller has ignored
the HFL signal. There is no need to
handle overflow/underflow of the
FIFO register.
Philips Semiconductors Video Products
Preliminary specification
Digital video scaler
SAA7186
MEH473
Fig.9 Operation cycle
May 1993
3-318
Philips Semiconductors Video Products
Preliminary specification
Digital video scaler
~
ADC
SAA7186
DMSD
TDA8708A
~
CV.BS SAA7151B/91B
i
RGBlYUV
YUV
Tormat 4.2:2
DVS
HREF/VS
SAA7186
T
LLC/CREF
RAM
~
control
HFL/
INCADR
LFCO
display data
VIDEO
GRAPHICS
r-
address
'--
SCGC
VCLK
VOEN
SAA7157/97
MEMORY
------- CONTROLLER
~~~m
BUFFER
1
data bus
CPU
.
address I control bus
SYSTEM
RAM
MEH554
Fig.10 SAA7186 system configuration in Data Burst Transfer Mode
(TTR = , VCLK = continuous ).
,..----....... ;b~nYat 4.2:2
CVBS
ADC
digital
DMSD
TDA8708A
CV8S
SAA7151 8/91 8
RAM
VIDEO
GRAPHICS
HREF I VS
LLC/CREF
control
LFCO
address
VOEN = 1
SCGC
MEMORY
CONTROLLER
SAA7157/97
MEH555
Fig.11 SAA7186 system configuration in Transparent Data Transfer Mode
(TTR = 1, EFE = 1, VCLK =continuous (_LLC2)).
May 1993
3-319
Philips Semiconductors Video Products
Preliminary. specification
Digital video scaler
(a) 1st field
SAA7186
625
3
4
5
6
7
8
9
I
I
I
I
I
I
I
I
inputCVBS
HREF
VS
(b) 2nd field
inputCVBS
HREF
vs
~
____---..:...1-....1-,.--------------------11'
69x2lLLC
50 Hz
MEH412
(a) 1st field
inputCVBS
HREF
VS
I
--+--l.----2x 21LLC
(b) 2nd field
263
264
265
266
267
268
269
270
271
I
I
I
I
I
I
I
I
I
inputCVBS
HREF
~
vs
59x2lLLC
______~r~--I~----------------------~~I_______
60 Hz
- + 2 x 21LLC
MEH225·1
Fig.12 VS timing for video input source SAA7191 B.
May 1993
3-320
Philips Semiconductors Video Products
Preliminary specification
Digital video scaler
SAA71.86
9. 12C-BUS FORMAT
_S---I-I_S_LA_~_E_A_D_D_R_ES_S--,-I_A--L.I_S_UB_A_D_D_R_ES_S--,-I_A--L.._D_A_TA_O_.l--A---L..I------ ~_D_A_TA_n_..L-A---,I_p----,
1-1
S
start condition
1011100X (IICSA =LOW) or 1011110X (IICSA =HIGH)
acknowledge, generated by the slave
subaddress byte (Table 4)
data byte (Table 4)
stop condition
SLAVE ADDRESS
A
SUBADDRESS"
DATA
P
x
read/write control bit
X =0, order to write (the circuit is slave receiver)
X = 1, order to read (the circuit is slave transmitter)
* If more than 1 byte DATA are transmitted, then auto-increment of the subaddress is performed.
Table 4 12C-bus; subaddress and data bytes for writing (X in address byte = 0 ).
FUNCTION
DATA
ISUBAOORESS
07
06
05
04
03
02
Formats and sequence
Output data pixel/line
continued in
Input data pixel/line
continued in
Horizontal window start
Pixel decimation filter
00
01
04
02
04
03
04
RTB
XD7
OF1
XD6
OFO
XD5
VPE
XD4
LW1
XD3
LWO
XD2
XS7
XS6
XS5
XS4
X07
HF2
X06
HF1
X05
HFO
X04
X08
XS3
XS9
X03
XS9
XS2
XS8
X02
XS8
Output data lines/field
continued in
Input data lines/field
continued in
Vertical window start
AFSlvertical processing
05
09
06
09
07
08
YD7
YD6
YD5
YD4
YD3
YD2
YS7
YS6
YS5
YS4
Y07
AFS
Y06
VP1
Y05
VPO
Y04
Y08
YS3
YS9
Y03
YS9
YS2
YS8
Y02
YS8
Vertical bypass start
continued in
Vertical bypass count
continued in
09
OB
OA
OB
VS7
VS6
VS5
VS3
VC7
TCC
VC6
0
VC5
0
VS4
VS8
VC4
VS8
Chroma keying
lower limit for V
upper limit for V
lower limit for U
upper limit for U
OC
OD
OE
OF
VL7
VU7
UL7
UU7
VL6
VU6
UL6
UU6
VL5
VU5
UL5
UU5
10
0
0
0
Byte 10**
Unused
11 to 1F
*) Default register contents fill in by hand
**) Byte 10 is set to OOh after power-on reset.
May 1993
3-321
01
DO
FS1
XD1
XD9
XS1
FSO
XDO
XD8
XSO
X01
XD9
XOO
XD8
YD1
YD9
YS1
YDO
YD8
YSO
Y01
YD9
YOO
YD8
VS2
VS1
VSO
VC3
0
VC2
VC8
VC1
0
VCO
POE
VL4
VU4
UL4
UU4
VL3
VU3
UL3
UU3
VL2
VU2
UL2
UU2
VL1
VU1
UL 1
UU1
VLO
VUO
ULO
UUO
MCT
aPL
app
ITR
EFE
OF*
tbf
Preliminary specification
Philips Semiconductors Video Products
Digital video scaler
SAA7186
Table 5 12C-bus status byte (X in address byte = 1 )
FUNCTION
status byte
Function of status bits:
103
to
100
D7
D6
D5
DATA
D4
D3
D2
D1
DO
103
102
101
100
0
OEF
SVP
0
Software version of SM7186 compatible with
103
102
101
100
o
0
0
1
I ~ersion
Identification of field sequence dependent on inputs HREF and VS:
o = even field detected; 1 = odd field detected
State of VRAM port:
0 = inputs HFL and INCAOR inactive;
1 = inputs HFL and INCAOR active.
OEF
SVP
Table 6 Function of the register bits of Table 4
"00"
RTB
o = anti-gamma ROM active
ROM table bypass switch:
1
= table is bypassed
r'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'_._._._._._._._._._._.OF1
to
Set output field mode:
OFO
OF1
o
OFO
0
1
1
0
1
o
1
field mode OVS process
both fields for interlaced storage
both fields for non-interlaced storage
odd fields only (even fields ignored) for non-interlaced storage
even fields only(odd fields ignored) for non-interlaced storage
~.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-._._._._.-._._._._._._.-
VPE
VRAM port outputs enable: 0 = HFL and INCAOR inactive; VRO outputs in 3-state
position (HFL = LOW, INCAOR = HIGH)
1 = HFL and INCADR enabled; VRO outputs dependent
on VOEN
~.-.-.-.-.-.-.-.-.-
LW1
to
LWO
.•
_._ ....:.._._._._._._._._._._._._._._._._._._._._._._._._._.= 0; FSO =
First pixel position in VRO data for FS1
31 to 24 23 to 16
LW1 LWO
pixel 1
0
0
pixel 0
1
black
pixel 0
0
black
black
1
0
1
1
black
black
=1; FSO =1 (monochrome):
0
0
1
1
May 1993
a (RGB) and FS1 = 0; FSO =1(YUV):
7toO
pixel 1
)
pixel 1
)
pixel a
) EFE = 0, TRR =0
)
pixel 0
First pixel position in VRO data for FS1
LW1 LWO
31t024 23t016
0
0
pixel a
pixel 0
0
1
pixel 0
pixel 0
1
0
black
black
black
black
1
1
0
1
0
1
pixel 0
black
pixel 0
black
pixel
pixel
pixel
pixel
3·322
1
0
1
0
15't08
pixel 1
pixel 1
pixel 0
pixel 0
15 to 8
pixel 2
pixel 1
pixel 0
black
7to 0
pixel 3
pixel 2
pixel 1
pixel 0
X
X
X
X
X
X
X
X
)
)
) EFE
)
)
)
.)
)
= 0, TRR =0
EFE = 1, TRR = 0;
LW only effects the
greyscale formar
Philips Semiconductors Video Products
Preliminary specification
Digital video scaler
FS1
to
FSO
SAA7186
FIFO output register format select (EFE- bit see "10"):
EFE FS1 FSO
output format (Tables 2 and 3)
o
0
0
RGB 5-5-5 + alpa; 2x16-bitlpixel; 32-bit word length;
RGB matrix on, VRAM output format
o 0
1
YUV 4:2:2; 2x16-bitlpixel; 32-bit word length;
RGB matrix off, VRAM output format
o
1
0
YUV 4:2:2; video test mode; 1x16-bitlpixel;16-bit word length;
RGB matrix off, optional output format
o
1
1
monochrome mode; 4x8-bitlpixel; 32-bit word length;
RGB matrix off, VRAM output format
1
0
0
1
0
1
1
1
0
1
1
1
RGB 5-5-5 + alpa; 1x16-bitlpixel; 16-bit word length;
RGB matrix on, VRAM output + transparent format
YUV 4:2:2 + alpa; 1x16-bitlpixel; 16-bit word length;
RGB matrix off, VRAM output + transparent format
RGB 8-8-8 + alpa; 1x24-bitlpixel; 24-bit word length;
RGB matrix on, VRAM output + transparent format
monochrome mode; 2x8-bitlpixel; 16-bit word length;
RGB matrix off, VRAM output + transparent format
"01 and 04"
XD9
to
XDO
Pixel number per line (straight binary) on output (VRO):
0000000000 t01111111111 (numberofXS pixels as a maximum)
"02 and 04"
XS9
to
XSO
Pixel number per line (straight binary) on inputs (YIN and UVIN):
000000 0000 to 11 1111 1111 (number of input pixels per line as maximum)
"03 and 04"
X08
to
XOO
Horizontal start position (straight binary) ofscaling window (take care of active pixel
number per line).
startwith1stpixelafterHREFrise = 000010000 to 111111111 (010t01FF)
window start and window end may be cut by internal delay compensated HREF = 0
phase. XO has to be matched to the internal processing delay to get full scaling range
"04"
HF2
to
HFO
Horizontal decimation filter (Figures 13 and 14):
filter
HF2 HF1 HFO taps
o 0
0
2
filter 1 (1/2 (1 + z -1))
o 0
1
3
filter2 (1/4(1 +2z- 1 +z-2))
o
1
0
5
filter3 (1/8(1 +2z- 1 +2z-l!+2z-3 +z-4 ))
o
1
1
9
filter 4 (1/16 (1 + 2z -1 + 2z -2 + 2z -3 + 2z -4 + 2z -5
+ 2z -6 + 2z -7 + z -8))
o
o
1
1
"05 and 08"
YD9
to
May 1993
YDO
o
1
o
1
1
8
4
filter bypassed
filter bypassed + delay in Y channel of 1T
filter 5 (1/16 (1 + 3z -l + 3z -2 + Z -3 + z -4 + 3z -5
+ 3z -6 + z -7))
(1/8(1 +3z- 1 +3z- 2 +z-3 ))
Line number per output field (straight binary):
.
0000000000 to 11 1111 1111 (number of YS lines as a maximum)
3-323
Philips Semiconductors Video Products
Preliminary specification
Digital video scaler
SAA7186
"06 and 08"
to
YS9
YSO
Line number per input field (straight binary):
00 0000 0000
a line
11 1111 1111
1023 lines (maximum = number of lines/field - 3)
"07 and 08"
Y08
to
YOO
Vertical start of scaling window_ "a" equals 3rd line after rising slope of VS input signal.
Take care of active line number per field (straight binary)_
a 0000 0000 start with 3rd line after the rising slope of VS
00000 001.1 start with 1st line after the falling slope of nominal VS (SAA71518/918)
1 1111 1111 511 + 3 lines after the rising slope of VS (maximum value)
"08"
AFS
~-----------------
VP1
to
VPO
Adaptive filter switch: a = off; use VP1, VPO and HF2 to HFO bits
________________ ~_~~_n~f!~~ ~~~~~~~~i:.s_ ~~~~~~~~ ~~~_e-.:?~I~~ _____ _
Vertical data processing
VP1 VPO
processing
a
a
1
1
a
1
a
1
bypassed
delay of one line H(z) = z -H
vertical filter 1: (H(z) = 1/2 (1 + z -H))
vertical filter 2: (H(z) = 1/4 (1 + 2z -Ii + z -2H))
"09 and 08"
VS8
to
VSO
Vertical bypass start, sets begin of the bypass region (straight binary)_ Scaling region
overrides bypass region (YO bits):
a 0000 0000 start with 3rd line after the rising slope of VS
a 0000 0011 start with 1st line after the falling slope of nominal VS (SAA71518/918)
1 1111 1111 511 + 3 lines afterthe rising slope of VS (maximum value)
"OAand 08"
VC8
to
VCO
Vertical bypass count, sets length of bypass region (straight binary):
a 0000 0000
a line length
1 1111 1111
511 lines length (maximum = number of lines/field -3)
r------------------- ---------------------------------------------------------Tce
Two's complement input data select (U, V):
a = binary input data
1
POE
"OC"
VL7
Polarity, internally detected odd/even flag OlE:
a = flag unchanged;
1 = flag inverted
to
VLO
Set lower limit for V colour-difference signal (8 bit; two's complement):
1000 0000
0000 0000
0111 1111
"00"
VU7
to
VUO
as maximum negative value = -128 signal level
limit = a
as maximum positive value = +127 signal level
Set upper limit for V colour-difference signal (8 bit; two's complement):
1000 0000
0000 0000
0111 1111
May 1993
= two' complement input data
-----_._---_._-----------------------------_._---------7--
as maximum negative value = -128 signal level
limit = a
as maximum positive value = + 127 signal level
3-324
Preliminary specification
Philips Semiconductors Video Products
Digital video scaler
SAA7186
"OE"
UL7
to
ULO
Set lower limit for U colour-difference signal (8 bit; two's complement):
1000 0000
as maximum negative value = -128 signal level
0000 0000
limit = a
0111 1111
as maximum positive value = +127 signal level
"OF"
UU7
to
UUO
Set upper limit for U colour-difference signal (8 bit; two's complement):
1000 0000
as maximum negative value = -128 signal level
0000 0000
limit = a
0111 1111
as maximum positive value = + 127 signal level
"10"
MGT
Monochrome and two's complement output data select:
a = inverse grayscale luminance (if grayscale is selected by FS bits) or straight
binary U, V data output
1 = non-inverse monochrome luminance (if grayscale is selected by FS bits) or
two'complement U, V data output
------------------ ---------------------------------------------------------QPL
~-----------------
QPP
a=
Line qualifier polarity flag:
LNQ is active-LOW (pin 1 and on VR01, pin 99);
1 = LNQ is active-HIGH
---------------------------------------------------------a = PXQ is active-LOW (VROO, pin 100);
Pixel qualifier polarity flag:
1 = PXQ is active-HIGH
------------------ ---------------------------------------------------------TTR
Transparent data transfer:
a
1
= normal operation (V RAM protocol valid,)
= FI Fa register transparent
(output FIFO in shift register mode)
------------------ ---------------------------------------------------------EFE
May 1993
Extended formats enable, FS-bits in subaddress "00"
3-325
Philips Semiconductors Video Products
Preliminary specification
Digital video scaler
SAA7186
MEHS14
10
100,101
(dB)
-10
-20
-30
-40
Fig.13 Horizontal frequency
characteristic of luminance
signal (Y) dependent on HF2
to HFO bits (subaddress 04).
-50
f/fclook
MEH513
10
100,101
(dB)
-10
-20
-30
-40
-50
0.05
0.10
0.20
0.15
0.25
Fig.14 Horizontal frequency
characteristic of chrominance
signals (UV) without UV
interpolation dependent on
HF2 to HFO bits (subaddress 04).
f/fclook
Purchase of Philips' 12C components conveys a license under the
Philips' 12C patent to use the components in the 12C-system
provided the system conforms to the 12C specifications defined
by Philips.
May 1993
3-326
Philips Semiconductors Video Products
Preliminary specification
Digital video scaler
SAA7186
10. LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MAX.
MIN.
UNIT
VOO
supply voltage (pins 5, 14, 26, 40,
55, 67, 76 and 91)
-0.5
6.5
V
VI
DC input voltage on all pins
-0.5
Voo
V
100
supply current (pins 5, 14, 26, 40,
55, 67, 76 and 91)
Ptot
total power dissipation
0
T stg
storage temperature range
Tamb
operating ambient temperature range
V ESO
electrostatic handling* for all pins
70
mA
1
W
-65
150
°C
0
70
°C
-
±2000
V
* Equivalent to discharging a 100 pF
capacitor through a 1.5 kQ series
resistor.
11. DC CHARACTERISTICS
V 001 to Voos = 4.5 to 5.5 V; Tamb = 0 to 70°C unless otherwise specified.
SYMBOL
VOO
Ip
PARAMETER
CONDITIONS
supply voltage range (pins 5, 14, 26, 40,
55, 67, 76 and 91)
total supply current (1001 + 1002 + 1003
1004 + 1005 + 10DS + 1007 + loos)
inputs LOW and
outputs without load
MIN.
TYP.
MAX.
UNIT
4.5
5
5.5
V
-
80
-
mA
Data and control inputs
V IL
input voltage LOW
-0.5
-
V IH
input voltage HIGH
2.0
-
III
input leakage current
-
-
CI
input capacitance
V IL =0
data
clocks
-
0.8
Voo+0.5
V
V
10
IlA
8
pF
10
pF
Data and control outputs
VOL
output voltage LOW
note 1
-
-
0.6
V
V OH
outputt voltage HIGH
note 1
2.4
-
-
V
-
±5
IlA
8
pF
1.5
V
3-state outputs
high-impedance output current
-
high-impedance output capacitance
-
V IL
input voltage LOW
-0.5
VIH
input voltage HIGH
3
-
V DD +O.5 V
144 ,45
input current
-
-
HO
lACK
output current on pin 44
VOL
output voltage at acknowledge
100ft
Co
12C-bus, SDA and SCL (pins 44 and 45)
May 1993
acknowledge
144 = 3 rnA
3-327
3
IlA
-
mA
0.4
V
Philips Semiconductors Video Products
Prel!minaryspecification
Digital video scaler
12. AC CHARACTERISTICS
V DD1 to V DD8 = 4.5 to 5.5 V; T amb
SYMBOL
SAA7186
= 0 to 60°C unless otherwise specified.
PARAMETER
CONDITIONS
LLC timing (pin 36)
. MIN.
tLLC
cycle time
pulse width (duty factor)
tr
rise time
tf
fall time
31
tLLC HI tLLC
Input data and CREF timing
tsu
setup time
tHD
hold time
VCLK timing (pin 51)
45
ns
50
60
0/0
-
-
6
-
-
I
I
11
3
VRO outputs'
15
-
other outputs
7.5
CL::: 10 pF; note 4
0
50
note 3
17
tr
rise time
tf
fall time
Output data and reference signal timing
Figures 15 and 16
CL
load capacitance
tOH
VRO data hold time
0
to
output disable time to 3-state
tE
output enable time from 3-state
= 10 pF; note 5
CL =10 pF; note 5
CL =40 pF; note 4
CI,. =25 pF; note 5
CL =25 pF; note 5
C L =4{) pF; note 6
CL =40pF; note 6
tHFL VOE
HFL maximum response time
VRAM port enabled
tHFL VCLK
HFL maximum response time
HFL set at beginning
of VCLK burst
toDV
ns
ns
ns
ns
-
note 2
LOW and HIGH times
tOOL
,
Fig.16
VRAM port clock cycle time
toD
5
Fig.15
tp L, tpH
tOHv
UNIT
40
tVCLK
tOHL
MAX.
Fig.11
tp
r~lated
TYP.
to LLC (INCADR, HFL)
related to VCLK (HFL)
VRO data delay time
related to LLC (INCADR, HFL)
related to VCLK (HFL)
CL
-
200
ns
-
ns
5
ns
6
ns .
40
pF
25
pF
-
ns
-
ns
0
-
ns
-
25
ns
-
60
ns
-
-
-
-
60
ns
40
ns
40
ns
810
ns
840
ns
Notes to the caracteristics
1. Levels are measured with load circuit. VRO outputs with 1.2 kn in parallel to 25 pF at 3 V (TTL load)~
2. Maximum tVCLK =200 ns fortest mode only. The applicable maximum cycle time depends on data format,
horizontal scaling and input data rate.
3. Measured at 1,5 V level; tp L may be unlimited.
4. Timings of VRO refer to Hie rising edge of VLCK.
5. The timing of INCADR refers to LLC; the rising edge of HFL always refers to LLC. During a VRAM transfer is the
falling edge of HFL generated by VCLK. Both edges of HFL refer to LLC during horizontal increment and vertical
reset cyeles.
6. Asynchronous signals with timing refering to the 1.5 V switching point of VOEN input signal (pin 50).
May 1993
3-328
Philips Semiconductors Video Products
Preliminary specification
Digital video scaler
SAA7186
14-------14---- t
LLC H
t LLC -------~I
---+
2.4 V
clock input LLC
1.5V
0.6 V
2.0V
inputs CREF
input data
output HFL
and INCADR
/////////'l/
/@/
2.4 V
notvalidm
/'//////////
0.6 V
Fig.15 Data input timing (LLC).
MEH408-1
~_
VOEN
~---------------------~
2.0V
1.5 V
- - - - - 0.8V
2.0V
1.5 V
0.8 V
2.4 V
0.6 V
2.4 V
0.6V
Fig.16 Data output timing (VCLK).
May 1993
3-329
MEH409
Philips Semiconductors Video Products
Preliminary specification
Digital video scaler
SAA7186
13. PROCESSING DELAYS
PORTS
DELAY IN LLC
REMARKS'
YIN to VRO
UVIN to VRO
HREFto VRO
58
58
58
in transparent mode only
in transparent mode only
in transparent mode only
..
14. PROGRAMMING EXAMPLE
Slave address byte is B8h at pin IICSA =0 (or BCh at pin IICSA =+5 V).
This example shows the setting via 12C-bus for the processing of a picture segment at 1:1 horizontal and vertical scale.
Values in brackets [.. ]:
If no scaling or panning. is wanted
the parameters XD, X~l YD and' YS should be set to the maximum value 3FFh.
the parameters XO ana YO should be set to the minimum value OOOh.
(in this case, HREF and VS from external define the SAA7186 processing window).
SUBADDR
(hex)
BITS
FUNCTION
00
RTB, OF(1 :0), VPE,
LW(1 :0), FS(1 :0),
01
02
03
XD(7:0)
XS(7:0)
XO(7:0)
ROM table control and field
sequence processing; VRAM port
enable; output format select
LSB's output pixel/line
LSB's input pixell1ine
LSB's for horizontal window start
04
HF(2:0), XO(8),
XS(9, 8), XD(9, 8)
YD(7:0)
YS(7:0)
YO(7:0)
horizontal filter select and MS8's
of subaddresses 01, 02, 03
LSB's output lines/field
LSB's input lines/field
LSB's vertical window start
AFS, VP(1 :0), YO(8),
YS(9, 8), YD(9, 8)
VS(7:0)
VC(7:0)
VS(8), VC(8), TCC,
POE
adaptive and vertical filter select;
MSB's of subaddresses 05,06,07
LS8's vertical bypass start position
LSB's vertical bypass lines/field
MSB's of subaddresses 09, OA;
UV input data representation
and odd/even polarity switch
OC
OD
OE
OF
VL(7:0)
VU(7:0)
UL(7:0)
UU(7:0)
UV keyer:
UV keyer:
UV keyer:
UV keyer:
10
MCT, QPP, QPL,
TTR,EFE
Y or UV output data representation,
output data transfer mode,
pixel/ line qualifier polarity.
05
06
07
08
09
OA
OB
May 1993
lower limit V (R-Y)
upper limit V (R-Y)
.lower limit U (B-Y)
upper limit U (B-Y)
3-330
VALUE
(hex)
COMMENT
11
80 [FF]
80 [FF]
10 [00]
(1 )
384 pixels out
384 pixels in
1st pixel after HREF = 1
85
90
90
03
horizontal filter bypassed
144 lines out
144 lines in
1st line after VS = 0; (2)
[8F]
[FF]
[FF]
[00]
00 [FF]
00
00
no adaptive select
vertical filter bypassed
not bypassed
region
00
defined; (3) (4)
00
FF
00
00
) keying is switched off
) byVU < VL
00
(5)
-
Philips Semiconductors Video Products
Preliminary specification
Digital video scaler
SAA7186
Notes to the programming examples
(1)
(2)
RTB
OF
VPE
=
=
=
0
00
1
ROM table is active (only for RGB formats)
SM7186 processes the both fields for interlaced display
VRAM port is enabled
LW = 00
longword position of first pixel in each output line =0
FS = 01
16-bit 4:2:2 YUV output format is selected
for nominal VS length of 6 x H-period (input SM7191 B respectively SM7151 B with active VNL)
(3) DC = 0
straight binary UV input data expected
(4) odd/even polarity unchanged - can be used to change the field sequence if phase relations between HREF and
VSare not according to SM71 ~1 B respectively SM7151 B specification
(5) MCT = 0
when EFE, FS =001 h: UV output data are straight binary
OPP = 0
the pixel qualifier PXO is "O"-active (if DR, EFE = 1)
OPL = 0
line qualifier LNO is "O"-active (if DR, EFE = 1)
DR = 0
VRAM port is set to data burst transfer
EFE = 0
32-bit longword formats selected.
May 1993
3-331
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-SQ)
FEATURES
•
Monolithic CMOS 5V device
•
Digital PALINTSC encoder
•
SAA7187
Quick Reference Data
PARAMETER
MIN.
TYP.
MAX.
UNIT
digital supply voltage range
4.5
5.0
5.5
V
System Pixel Frequency selectable
for 12.27 MHz (60 Hz fields) or
14.75 MHz (50 Hz fields)
Vooo
VOOA
analog supply voltage range
4.75
5.0
5.25
V
1000
supply current digital
-
175
210
rnA
24-bit wide YUV Input port or
IOOA
supply current analog
-
50
55
rnA
16-bit wide YUV Input port or
Vi
input signal levels
TIL - compatible
V
•
Input data format Cb,Y,Cr,Y, ...
(CCIR 656 like)
Vo
analog output signals, Y, C
and CVBS without load
(peak to peak value)
-
2
V
•
IIC Bus control port
RL
load resistance
80
-
-
Q
•
MPU parallel control port
ILE
LF integral linearity error
-
-
±2
LSB
•
Encoder can be master or slave
DLE
LF differential linearity error
-
-
±l
LSB
•
Programmable horizontal and vertical input synchronization phase
Tamb
operating ambient temperature range
0
-
70
°c
•
Programmable horizontal sync out-
•
•
•
•
SYMBOL
put phase
General Description
OSD overlay with LUTs (8*3 bytes)
'Line 21' Closed Caption encoder
•
Cross colour reduction
The
Digital
Video
Encoder 2
(DENC2-SQ) encodes digital YUV
video data to an NTSC or PAL CVBS or
S-Video signal.
•
DACs running at two times oversampling with 10 bits resolution
Controlled rise-/fall times of output
syncs and blanking
The circuit accepts differently formatted
YUV data with 640 or 768 active pixels
per line. It includes a synclclock generator as well as on chip D/A converters.
•
•
Down mode of DACs
•
CVBS and S-Video output simultaneously.
•
PLCC68 package
EXTENDED
TYPE NUMBER
The circuit is compatible to the DIG.
TV2 chip family (Square Pixel).
PACKAGE
PINS
SAA7187
April 1994
-
68
3-332
IPIN POSITION1MATERIAL I
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PLCC
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plastic
I
CODE
SOT188
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-SQ)
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April 1994
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II:
3-333
Preliminary specification
Ph!lips Semiconductor Video Products
Digital video encoder (DENC2-SQ)
SAA7187
PINNING
SYMBOL
PIN
DESCRIPTION
Digital negative supply voltage (Ground)
VSS
1
VP3(4)
2
VP3(5)
3
VP3(6)
4
VP3(7)
5
RCVl
6
Raster Control 1 for Video port. Depending on the synchronization mode, this pin receives/
provides a VSIFSIFSEQ signal.
RCV2
7
Raster Control 2 for Video port. Depending on the synchronization mode, this pin receives/
provides a HSIHREF/CBL signal
Digital negative supply voltage (Ground)
VSS
8
VP2(0)
9
VP2(1)
10
VP2(2)
11
VP2(3)
12
VP2(4)
13
VP2(5)
14
Upper 4 bits bf the VP3 Port. If Pin 68 (SEL_MPU) is high, this is the data bus of the parallel MPU interface. If it is low, there can be multiplexed UV lines (422) or the U-signal
(444) of the Video input
Video Port VP2. In 444 input mode, this is input for the V-signal
VP2(6)
15
VP2(7)
16
VDD
17
res.
18
reserved, do not connect.
VSS
19
Digital negative supply voltage (Ground)
VP1(7)
20
VPl(6)
21
VP1(5)
22
VP1(4)
23
VPl(3)
24
Digital positive supply voltage.
Video Port VPl. This is an input for CCIR-656 compatible, multiplexed video data, or during other input modes, this is the Y-signal.
VPl(2)
25
VP1(1)
26
VP1(0)
27
VSS
28
Digital negative supply voltage (Ground)
RCMl
29
Raster Control Master 1. This pin provides a VSIFSIFSEQ signal
RCM2
30
Raster Control Master 2. This pin provides a programmable HS pulse
KEY
31
Key signal for OSD. It is high-active.
OSD(O)
32
OSD(1)
33
OSD(2)
34
On Screen Display data. This is the index for the internal OSD lookup table.
VSS
35
Digital negative supply voltage (Ground)
CDIR
36
Clock direction. If the CDIR input is high, the circuit receives a clock signal, otherwise
LLC and CREF are generated by the internal crystal oscillator.
VDD
37
Digital positive supply voltage.
April 1994
3-334
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
PINNING
SYMBOL
DESCRIPTION
38
Line Locked clock. This is the 24.54 MHz I 29.5 MHz master clock for the encoder. The
direction is set by the CDIR pin.
CREF
39
Clock Reference signal. This is the clock qualifier for DIG-TV2 compatible signals.
XTAL
40
Crystal oscillator output (to crystal).
XTALI
41
Crystal oscillator input (from crystal). If the oscillator is not used, this pin should be connected to ground.
LLC
April 1994
PIN
VDD
42
Digital positive supply voltage.
RTCI
43
Real Time Control Input. lithe clock is provided by a SAA7191B, RTCI should be connected to the RTCO pin of the decoder to improve the signal quality.
AP
44
Test pin. Connect to digital ground for normal operation.
SP
45
Test pin. Connect to digital ground for normal operation.
VREFL
46
Lower reference voltage for the D/A converters.
VREFH
47
Upper reference voltage for the D/A converters.
VDDA
48
Analog positive supply voltage for the D/A converters and output amplifiers.
C
49
Analog output of the chrominace signal.'
VDDA
50
Analog positive supply voltage for the D/A converters and output amplifiers.
y
51
Analog output of the luminance signal.
VSSA
52
Analog negative supply voltage for the D/A converters and output amplifiers (Ground).
CVBS
53
Analog output of the CVBS signal.
VDDA
54
Analog positive supply voltage for the D/A converters and output amplifiers.
CUR
55
Current input for the output amplifiers. connect 15 kOhm to VDDA
VDDA
56
Analog positive supply voltage for the D/A converters and output amplifiers.
RESN
57
Reset input, low active. After reset is applied, all outputs are in tristate/input mode. The
IIC receiver waits for the start condition.
DTACKN
58
Data acknowledge output of the parallel MPU interface; low-active, otherwise high-impedance.
RWN/SCL
59
If pin 68 (SEL_MPU) is high, this is the read/write signal of the parallel MPU interface,
otherwise it is the lIC serial clock line.
AOISDA
60
If pin 68 (SEL_MPU) is high, this is the address signal of the parallel MPU interface, otherwise it is the IIC serial data line.
CSN/SA
61
If pin 68 (SEL_MPU) is high, this is the chip select signal of the parallel MPU interface,
otherwise it is the lIC slave address select pin:
Low: Slave address =88h;
High: Slave address =8Ch
VSS
62
Digital negative supply voltage (Ground)
VP3(0)
63
VP3(1)
64
Lower 4 bits of the VP3 Port. If Pin 68 (SEL_MPU) is high, this is the data bus of the parallel MPU interface. If it is low, there can be multiplexed UV lines (422) or the U-signal
(444) of the Video input
VP3(2)
65
VP3(3)
66
VDD
67
Digital positive supply voltage.
SEL_MPU
68
Select MPU interface. If it is high, the parallel MPU interface is active, otherwise the lIe
bus interface will be used.
3-335
Philips Semiconductor Video Products
Preliminary.specification
Digital video encoder (DENC2-SQ)
SAA7187
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61
VDD
VSS
XTALI
XTAL
CREF
LLC
VDD
VDD
CDIR
SEL_MPU
VSS
SAA7187
VSS
OSD(2)
OSD(1)
OSD(O)
KEY
RCM2
RCV1
RCM1
RCV2
VSS
VSS
VP1(0)
VP2(0)
Fig. 2: Pinning Diagram
For ease of analog post filtering the signals The VP3 port accepts Cb-data (444
are two times oversampled w.r.t. pixel input mode) or multiplexed Cb/Cr-data
The
digital
Video
Encoder clock before digital-to-analog conversion. (422 input mode. If not used for video
(DENC2-SQ) encodes digital luminance
input data, it also can handle the data of
and. chrominance into analog CVBS- For total filter transfer characteristics see an 8 bit wide microprocessor interface,
and simultaneously S - Video (Y/C) sig- figs 3, 4, 5 and 6 for 60 Hz field rate, and alternatively.
.
nals. NTSC-M and PAL BIG standards figs 7,8,9 and 10 for 50 Hz field rate. The
DACs are realized with full 10 bit resolu- Minimum suppression of output chroma
as well as sub-standards are supported.
tion. The encoder provides three 8 bit wide alias components around 1 MHz due to
The basic encoder function consists of data ports,' that serve different applica- high frequency 444 input data is better
subcarriergeneration and colour modu- tions.
than 12 dB.
lation as well as insertion of synchroniThe
VPl
port
accepts
8
lines
multiplexed
The
8 bit multiplexed Cb-Y-Cr formats
and
zation
signals.
Luminance
chrominance signals are filtered accord- Cb-Y-Cr data (CCIR-656 mode), or Y-data are CCIR-656 (Dl format) compatible,
but the SAY, EAV e.t.c. codes are not
ing to the standard requirements only (444 mode).
decoded.
RS-170-A and CCIR-624.
The VP2 port accepts Cr-data in 444 input
mode.
A crystal-stable master clock (LLC) of
24.54 or 29.5 MHz, which is twice the
linelocked pixel clock, needs to be sup-
Functional Description
April 1994
3-336
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-SQ)
plied externally. Optionally, a crystal
oscillator input/output pair of pins and
an on-chip clock driver is provided.
Additionally, a DMSD2 compatible
clock interface, using CREF (input or
output) and RTC (see data sheet
SAA 719lB) is available.
The DENC2-SQ synthesizes all necessary internal signals, colour subcarrier
frequency, as well as synchronization
signals, from that clock. DENC2-SQ
can be timing master or slave.
SAA7187
The actual line number where data are to
be encoded in, can be modified in a certain range.
Encoder
Video Path:
Data clock frequency is acc. to definiThe encoder generates out of Y, U, V base
tion for NTSC-M standard 32 times horband signals output signals luminance and
izontalline frequency.
colour subcarrier, suitable for use as
Data LOW at the output of the DACs
CVBS or separate Y and C signals.
corresponds to 0 IRE, data HIGH at the
Luminance is modified in gain as well as
output of the DACs corresponds to
in offset (latter programmable in a certain
about 50 IRE.
range to enable different black level set-ups).After having been inserted a fixed It is also possible to encode Closed Capsync level, acc. to standard composite sync tion Data for 50 Hz field frequencies at
schemes, a variable blanking level, pro- 32 times horizontal line frequency.
grammable also in a certain range, is
inserted.
The IC contains Closed Caption and
Extended Data Services Encoding (Line
21); it also supports OSD via KEY and
three bit overlay techniques by a 24*8
Transients of both sync pulses and start!
LUT.
stop of blanking are reduced compared to
The IC can be programmed via I2C or overall luminance bandwidth.
8-bit MPU interface, but only one interface configuration can be active at a In order to enable easy analog post filtertime; if 422 or 444 input format is being ing, luminance is interpolated from square
used, only the I2C interface can be pixel data rate to twice that rate (24.54 or
29.5 MHz, respectively), providing lumiselected.
nance in 10 bit resolution. For transfer
A lot of possibilities is provided for set- characteristic of the luminance interpolating of different video parameters like tion filter see figs. 5 and 6 for 60 Hz field
Black- and Blanking level control, col- rate and figs. 9 and 10 for 50 Hz field rate.
our subcarrier frequency, variable burst
Chrominance is modified in gain (proamplitude etc.
grammable separately for U and V), standDuring Reset (RESN=low) and after ard dependent burst is inserted, before
Reset released, all digital I/O stages are base band colour signals are interpolated
set to input mode. A Reset forces the properly to 24.54/29.5 MHz data rate. One
control interfaces to abort any running of the interpolation stages can be
bus transfer and to set register 3Ah to by-passed, thus providing a higher colour
contents OOh, register 61h to contents bandwidth, which can be made use of for
ISh, and register 6Ch to contents OOh. Y/C output. For transfer characteristics of
All other control registers are not influ- the chrominance interpolation filter see
enced by a Reset.
figs. 3 and 4 for 60 Hz field rate and figs.7
and 8 for 50 Hz field rate.
Output Interface
In the output interface encoded Y and C
signals are converted from digital to
analog in 10 bit resolution both. Y and C
signals are combined to a 10 bit wide
CVBS-signal, as well; in front of the
summation point, the luminance signal
can optionally be fed through a further
filter stage, suppressing components in
the range of subcarrier frequency. Thus,
a kind of Cross Colour reduction is provided, useful in a standard TV set with
CVBS input.
Slopes of synchronization pulses are not
affected with any Cross Colour reduction active.
Three different filter characteristics or
bypass are available, see fig. 5 for 60 Hz
field rate and fig. 9 for 50 Hz field rate.
The CVBS output occurs with the same
processing delay as the Y,C outputs do.
Absolute amplitudes at the input of the
DAC for CVBS is reduced by 15116
Data Manager
The amplitude of inserted burst is pro- w.r.t. Y- and C- DACs to make optigrammable in a certain range, suitable for mized use of conversion ranges.
In the Data Manager, the de-multiplex- standard signals as well as for special
Outputs of all DACs can be set together
ing scheme is chosen acc. to the input
effects. Behind the succeeding quadrature via software control to minimum output
format.
modulator, colour in 10 bit resolution is voltage for either purpose.
Depending on hardware conditions (sig- provided on subcarrier.
nals on pins KEY and OSD(2-0), and The numeric ratio between Y and C output
Synchronization
software programming either data from is acc. to standards.
the VP ports or from the OSD port are
The synchronization of the DENC2-SQ
selected to be encoded to CVBS and YI Closed Caption Encoder:
is able to operate in two modes:
C signals.
By means of this circuit, data acc. to the In the slave mode, the circuit accepts
Optionally, the OSD colour look-up specification of Closed Caption or sync pulses at the bi-directional RCVl
tables located in this block, can be read Extended Data Service, delivered by the port. The timing and trigger behaviour
out in a pre-defined sequence (8 steps control interface, can be encoded related to the video signal on VP ports
per active video line), achieving e.g. a (LINE21). Two dedicated pairs of bytes can be influenced by programming the
colour bar test pattern generator without (two bytes per field), each pair preceded polarity and on-chip delay of RCVl.
need for an external data source. The by run-in clocks and framing code, are Active slope of RCVl defines the verticolour bar function is under software possible.
cal phase and optionally the oddlevencontrol, only.
and colour frame phase to be initialized,
it can be used also to set the horizontal
phase.
April 1994
3-337
Preliminary specification
Philips Semiconductor Video Products
Digital video encoder (DENC2-SQ)
SAA7187
If the horizontal phase shall not be influ- Control Interface
enced by RCV1, a horizontal. pulse
needs to be supplied at the RCV2 pin. DENC2-SQ contains two control interTiming and trigger behaviour can be faces: An IIC slave transceiver and 8 bit
parallel microprocessor interface. The
influenced for RCV2, as well.
interfaces cannot be used simultaneously.
If there are missing pulses at RCVl and/
or RCV2, the time base of DENC2-SQ The IIC bus interface is a standard slave
runs free, thus an arbitrary number of transceiver, supporti~. 7 bit slave
It/sec guaranteed
sync slopes may miss, but no additional addresses and .100
pulses (such with wrong phase) must transfer rate. It uses 8 bit subaddressing
with auto-increment function. All registers
occur.
are write-only, except one readable status
If the vertical arid horizontal phase is byte.
derived from RCV1, RCV2 can be used
for horizontal or composite blanking Two IIC slave addresses can be selected
(pin SEL_MPU must be low!):
input or output.
88h: Low at pin 61
In the master mode, the time base of the
circuit runs free continuously. On the
8Ch: High at pin 61
RCVl port, the IC can output:
• a Vertical Sync signal (VS) with 3 or The parallel interface is defined by
2.5 lines duration, or
D(7-0) data bus
•
•
an ODDIEVEN signal which is low
in odd fields, or
a field sequence signal (FSEQ)
which is high in the first of 4 resp. 8
fields.
CSN
low-active chip select signal
RWN read/write not signal, low for a
write cycle
DTACKN 680XX style dataacknowledge (hand-shake), active low
On the RCV2 port, the IC can provide a
AO
register select, low selects
horizontal pulse with programmable
address, high selects data
start and stop phase; this pulse can be
inhibited in the vertical 6lanking period The parallel interface uses two registers,
to build up e.g. a composite blanking one auto-incremental containing the current address of a control register (equals
signal.
subaddress with IIC control), one contain. The phase of the pulses output on RCVl
ing actual data. The currently addressed
or RCV2 are· related on the VP ports,
register is mapped to the corresponding
polarity of both signals is selectable.
control register.
On tbe RCMl port the same types of
Via a read access to the address register,
signals as on RCVl (as output) are
the status byte can be read optionally; no
available; on RCM2 the IC provides a
other read access is provided.
horiwntal pulse with programmable
start and stop phase.
The length of a field as well as start and
end of its active part can be programmed. The active part of a field
always starts at the beginning of a line.
April 1994
3-338
Input levels and formats
DENC2-SQ expects digital YUV data
with levels (digital codes) acc to
CCIR601:
Deviating amplitudes of the colour difference signals can be compensated by independent .gain control setting, while gain for
luminance is set to pre-defined values, distinguishable for 7.5 IRE setup or without
setup.
Reference levels are measured with a colour bar, 100% white, 100% amplitude,
100% saturation.
When the IC is operating with input data
acc. to CCIR656, programming. can be
done alternatively via the parallel interface using VP3 port for data transfer.
For other input modes, the IIC interface
has to be used for programming.
Preliminary specification
Philips Semiconductor Video Products
Digital video encoder (DENC2-SQ)
SAA7187
CCIR signal component levels
Signal
IRE
dig. level
0
16
126
235
16
128
240
50
100
Y
bottom peak
Cb
colourless
top peak
bottom peak
16
colourless
128
240
Cr
top peak
Code
straight binary
straight binary
straight binary
The 8 bit multiplexed format (CCIR656 like)
Time
Sample
Lum. pixel number
Cbo Yo
I
I3
Cro I Y I
0
1
011
Colour pixel number
2
4
I5
6
I7
Cb 2 1 Y2 Cr21 Y 3
2
3
2
0
The 16 bit multiplexed format (DTV2 format)
Time
011
2
I3
4
I5
6
I7
Sample Y - line
Yo
YI
Y2
Y3
Sample UV - line
Cbo
Cro
Cb 2
Cr2
0
1
2
Lum. pixel number
Colour pixel number
0
3
2
The 24 bit direct 444 format
Time
011
2
I3
4
I5
6
I7
Sample Y - line
Yo
YI
Y2
Y3
Sample U - line
Cbo
Cb l
Cb 2
Cb 3
Sample V - line
Cr3
Cro
Crl
Cr2
Lum. pixel number
0
1
2
3
Colour pixel number
0
1
2
3
April 1994
3-339
Preliminary specification
Philips Semiconductor Video Products
SAA7187
Digital video encoder (DENC2-SQ)
Bit allocation map
Slave Receiver [ Slave Address 88h or 8Ch]
REGISTER
FUNCTION
NULL
SUB- DATA BYTE
ADDR D7
D6
00
0
0
D5
D4
D3
D2
Dl
DO
0
0
0
0
0
0
.....
NULL
39
0
0
0
0
0
0
0
0
InpuCPorCControl
3A
CBENB
0
0
0
VY2C
VUV2C
FMTI
FMTO
OSD_LUT_YO
42
OSDY07
OSDY06
OSDY05
OSDY04 OSDY03
OSDY02
OSDYOI
OSDYOO
OSD_LUT_UO
43
OSDU07
OSDU06
OSDU05
OSDU04 OSDU03
OSDU02
OSDUOI
OSDUOO
OSD_LUT_VO
44
OSDV07
OSDV06
OSDV05
OSDV04 OSDV03
OSDV02
OSDVOI
OSDVOO
.....
OSD_LUT_Y7
57
OSDY77
OSDY76
OSDY75
OSDY74 OSDY73
OSDY72
OSDY71
OSDY70
OSD_LUT_U7
58
OSDU77
OSDU76
OSDU75
OSDU74 OSDU73
OSDU72
OSDU71
OSDU70
OSD_LUT_V7
59
OSDV77
OSDV76
OSDV75
OSDV74 OSDV73
OSDV72
OSDV71
OSDV70
Chroma_Phase
5A
CHPS7
CHPS6
CHPS5
CHPS4
CHPS2
CHPSI
CHPSO
Gain_U
5B
GAINU7
GAINU6
GAINU5
GAINU4 GAINU3
GAINU2
GAINUI
GAINUO
Gain_V
5C
GAINV7
GAINV6
GAINV5
GAINV4 GAINV3
GAINV2
GAINVI
GAINVO
Gain_U_MSB,
Black_Lev
5D
GAINU8
0
BLCKL5
BLCKL4 BLCKL3
BLCKL2
BLCKLI
BLCKLO
Gain_V_MSB,
Blank_Lev
5E
GAINV8
0
BLNNL5
BLNNL4 BLNNL3
BLNNL2
BLNNLl
BLNNLO
NULL
5F
0
0
0
0
0
0
0
0
X-Col_Select
60
CCRSI
CCRSO
0
0
0
0
0
0
Standard_Control
61
0
DOWN
INPIl
YGS
RTCE
SCBW
PAL
FISE
BurscAmplitude
62
SQP
BSTA6
BSTA5
BSTA4
BSTA3
BSTA2
BSTAI
BSTAO
SubcarriecO
63
FSC07
FSC06
FSC05
FSC04
FSC03
FSC02
FSCOI
FSCOO
Subcarriecl
64
FSC15
FSC14
FSC13
FSC12
FSCll
FSCIO
FSC09
FSC08
Subcarriec2
65
FSC23
FSC22
FSC21
FSC20
FSC19
FSC18
FSC17
FSC16
Subcarriec3
66
FSC31
FSC30
FSC29
FSC28
FSC27
FSC26
FSC25
FSC24
L21000
CHPS3
Line21_0dd_0
67
L21007
L21006
L21005
L21004
L21003
L21002
L21001
Line21_0dd_l
68
L21017
L21016
L21015
L21014
L21013
L21012
L21011
L21010
Line2 CEven_O
69
L2IE07
L2IE06
L2IE05
L2IE04
L2IE03
L2IE02
L21EOI
L2IEOO
Line2 CEven_1
6A
L2IEl7
L2IE16
L2IE15
L2IE14
L2IE13
L2IE12
L2IEll
L2IEIO
CC_Line
6B
0
0
0
SCCLN4 SCCLN3
SCCLN2
SCCLNI
SCCLNO
RCV_PorCControl
6C
SRCVll
SRCVlO
TRCV2
ORCVI
PRCVI
CBLF
ORCV2
PRCV2
RCM, CC-Mode
6D
0
0
0
0
SRCMll
SRCMlO
CCENI
CCENO
H-Trigger
6E
HTRIG7
HTRIG6
HTRIG5
HTRIG4
HTRIG3
HTRIG2
HTRIGI
HTRIGO
H-Trigger
6F
0
0
0
0
0
HTRIGIO HTRIG09 HTRIG08
April 1994
Preliminary specification
Philips Semiconductor Video Products
Digital video encoder (DENC2-SQ)
SAA7187
Slave Receiver [ Slave Address 88h or 8Ch]
SUB- OATABYTE
AOOR 07
06
REGISTER
FUNCTION
Fsc_Res_Mode,
V-Trigger
70
PHRESI
PHRESO
05
04
03 .
02
01
00
SBLBN
VTRIG4
VTRIG3
VTRIG2
VTRIGI
VTRIGO
,
Beg_MastecRequest
71
BMRQ7
BMRQ6
BMRQ5
BMRQ4
BMRQ3
BMRQ2
BMRQl
BMRQO
End_Master_Request
72
EMRQ7
EMRQ6
EMRQ5
EMRQ4
EMRQ3
EMRQ2
EMRQl
EMRQO
MSBs_MasCRequest
73
0
EMRQlO EMRQ9
EMRQ8
0
BMRQI0 BMRQ9
BMRQ8
NULL
74
0
0
0
0
0
0
0
0
NULL
75
0
0
0
0
0
0
0
0
NULL
76
0
0
0
0
0
0
0
0
Begin_RCV2_out
77
BRCV7
BRCV6
BRCV5
BRCV4
BRCV3
BRCV2
BRCVl
BRCVO
End_RCV2_out
78
ERCV7
ERCV6
ERCV5
ERCV4
ERCV3
ERCV2
ERCVl
ERCVO
MSBs_RCV2_out
79
0
ERCVlO
ERCV09
ERCV08 0
BRCVI0
BRCV09
BRCV08
Field_Length
7A
FLEN7
FLEN6
FLEN5
FLEN4
FLEN3
FLEN2
FLENI
FLENO
First_AcCLine
7B
FAL7
FAL6
FAL5
FAL4
FAL3
FAL2
FALl
FALO
Last_AcCLine
7C
LAL7
LAL6
LAL5
LAU
LAL3
LAL2
LALl
LALO
MSBs_Field_Ctrl
7D
0
0
LAL8
FAL8
0
0
FLEN9
FLEN8
12C-Bus Format
\ S \ Slave Addres~ A
Subaddiess
A \ DAIAq A \ --------\ DAIA@ A
Portion
Meaning
S
start condition
Slave Address
1000100X or lOOOllOX
A
acknowledge, generated by the slave
Subaddress(*)
subaddress byte
DATA
data byte
--------
continued data bytes and Pls
P
stop condition
p
X: read/write control bit; x=o is order to write; X=1 is order to read, no
subaddressing with read.
(*) if more than 1 byte DATA is transmitted, then auto-increment of the sub address is performed.
April 1994
3-341
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
Slave Receiver
Subaddress 3A'
Select input data format
FMT
VUV2C
VY2C
CBENB
f~~ction
FMTI
FMTO
0
0
input data YUV 444, 241ines, Y on VP1, Cr on VP2, Cb on VP3 (default after reset)
0
1
input data 'YUV 422, 16 lines, Y on VP1, multiplexed CbCr on VP3
1
0
inp~t dataYUV 422; 8 lines, multiplexed acc. to CCIR-656 on VPl
1
1
input data YUV 422, 8 lines, multiplexed acc. to CCIR-656 on VPl
0
Cb/Cr data input to VP ports are two's complement (defaultafteueset)
1
Cb/Cr data input to VP ports are straight. binary
0
Y data input to VPl port are two's complement (default after reset)
1
Y data input to VPl port are straight binary
0
Data from input ports are encoded (default after reset)
1
Colour Bar with programmable colours (entries of OSD-LUTs) is encoded
The LUTs are read in upward order from
~ndex
0 to index 7.
Subaddress 42 •• 59:
OSDY
OSDU
OSDV
Contents of OSD Look-up tables. All 8 entries are 8 bits. Data representation is acc. to CCIR 601 [Y,Cb,Cr], but
two's complement, e.g. for a 1001100 [upper number] or 100175 [lower number] Colour Bar:
Colour
OSDY
index (for normal colour bar with CBENB = 1)
OSDU
OSDV
107(6Bh)
107(6Bh)
O(OOh)
o (OOh)
O(OOh)
O(OOh)
0
Yellow
82(52h)
34(22h)
144(90h)
172 (ACh)
18(12h)
14(OEh)
1
Cyan
42 (2Ah)
03(03h)
38(26h)
29(lDh)
144(90h)
172 (ACh)
2
Green
17 (l1h)
240(FOh)
182 (B6h)
200(C8h)
162 (A2h)
185(B9h)
3
Magenta
234 (EAh)
212 (D4h)
74 (4Ah)
56(38h)
94(5Eh)
71 (47h)
4
Red
209(D1h)
193 (C1h)
218 (DAh)
227(E3h)
112 (70h)
84(54h)
5
Blue
169 (A9h)
163 (A3h)
112 (70h)
84(54h)
238(EEh)
242(F2h)
6
Black
144(90h)
144(90h)
o (OOh)
o (OOh)
o (OOh)
o (OOh)
7
White
Subaddress SA:
Phase of encoded colour subcarrier (including burst) relative to H - sync. Can be adjusted in steps of 360/256
degrees.
April 1994
3-342
Preliminary specification
Philips Semiconductor Video Products
Digital video encoder (DENC2-SQ)
SAA7187
Subaddress 5B, 5D:
GAINU
Variable gain for Cb signal (Input Representation acc. to CCIR 601) White - Black = 92.5 IRE
White - Black = 92.5 IRE
GAINU=O
Output subcarrier of U contribution = 0
GAINU=118 (76h)
Output subcarrier of U contribution = nominal
GAINU = -2.17
* nominal ... nominal ... 2.16 * nominal
White - Black = 100 IRE
GAINU= 0
Output subcarrier of U contribution = 0
GAINU=125 (7Dh)
GAINU = -2.05
Output subcarrier of U contribution = nominal
* nominal ... nominal ... 2.04 * nominal
Subaddress 5C, 5E:
GAINV
Variable gain for Cr signal (Input Representation acc. to CCIR 601)
White - Black = 92.5 IRE
GAINV= 0
Output subcarrier of V contribution = 0
GAINV=165 (ASh) Output subcarrier of V contribution = nominal
GAINV = -1.55
* nominal ... nominal ... 1.55 * nominal
White-Black = toO IRE
Output subcarrier of V contribution = 0
GAINV=O
GAINV=175 (AFh) Output subcarrier of V contribution = nominal
GAINV = -1.46
* nominal ... nominal ... 1.46 * nominal
Subaddress 5D:
BLCKL
Variable Black Level (Input Representation acc. to CCIR 601)
White - Sync = 140 IRE
BLCKL= 0
Output Black Level = 24 IRE
BLCKL= 63 (3Fb) Output Black Level = 49 IRE
Output Black LevellIRE = BLCKL * 25/63 + 24
Recommended Value:
BLCKL = 60 (3Ch) (normal)
White-Sync = 143 IRE
BLCKL= 0
Output Black Level = 24 IRE
BLCKL= 63 (3Fb) Output Black Level =50 IRE
Output Black LevellIRE =BLCKL * 26/63 + 24
Recommended Value:
April 1994
BLCKL =45 (2Dh) (normal)
3-343
I!
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
Subaddress 5E:
Variable BlankingLevel
BLNNL
White - 'Sync = 140 IRE
BLNNL= 0
Output Blanking Level = 17 IRE
BLNNL= 63 (3Fb) Output Blanking Level = 42 IRE
Output Blanking LevelJIRE = BLNNL
Recommended Value:
* 25/63 + 17
BLNNL = 58 (3Ah) (normal)
White - Sync = 143 IRE
BLNNL= 0
Output Blanking Level = 17 IRE
BLNNL= 63 (3Fb) Output Blanking Level = 43 IRE
Output Blanking LevelJIRE = BLNNL * 26/63 + 17
Recommended Value:
BLNNL = 63 (3Fb) (normal)
Subaddress 60'
Select cross colour reduction filter in luminance
CCRS
function
CCRSI
CCRSO
0
0
No Cross Colour Reduction (for transfer characteristic of luminance see figs. 5, 9)
0
1
Cross Colour Reduction #1 active (for transfer characteristic see figs. 5, 9)
1
0
Cross Colour Reduction #2 active (for transfer characteristjc see figs. 5, 9)
1
1
Cross Colour Reduction #3 active (for transfer characteristic see figs. 5, 9)
Subaddress 61:
FISE
0 944 total pixel clocks per line
PAL
SCBW
RTCE
1
780 total pixel clocks per line (default after reset)
0
NTSC Encoding (non-alternating V-compoQent) (default after reset)
1
PAL Encoding (alternating V-component)
0
Enlarged Bandwidth for Chrominance Encoding (for overall transfer characteristic of chrominance in base-band representation see figs. 3 and 4, 7 and 8).
1
Standard Bandwidth for Chrominance Encoding (for overall transfer characteristic of chrominance in base-band representation see figs. 3 and 4, 7 and 8). (default aft~r reset)
0
No Real Time Control of generated Subcarrier Frequency (default after reset)
1
Real Time Control of generated Subcarrier Frequency through SAA7191B (timing see fig. 13)
YGS
0
Luminance Gain for White-Black 100 IRE
1
Luminance Gain for White-Black 92.5 IRE incl. 7.5 IRE Set-up of Black (default after reset)
INPI
0
PAL Switch phase is nominal (default after reset)
1
PAL Switch phase is inverted compared to nominal
0
DACs in normal operational mode (default after reset)
1
DACs forced to lowest output voltage
DOWN
April 1994
3-344
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
Subaddress 62:
Amplitude of Colour Burst (Input Representation acc. to CCIR 601)
BSTA
White-Black =92.5 IRE, Burst =40 IRE, NTSC-Encoding
BSTA =0 .. 1.25
* nominal
BSTA = 102(66h)
Recommended Value:
White-Black =92.5 IRE, Burst =40 IRE, PAL-Encoding
BSTA =0 .. 1.76 * nominal
BSTA =72(48h)
Recommended Value:
White-Black = 100 IRE, Burst =43 IRE, NTSC-Encoding
BSTA =0 .. 1.20 * nominal
BSTA = 106(6Ah)
Recommended Value:
White-Black = 100 IRE, Burst =43 IRE, PAL-Encoding
BSTA =0 .. 1.67
* nominal
BSTA =75(4Bh)
Recommended Value:
SQP
0
not supported in current version, do not use
1
Subcarrier Real Time Control from 7191B Digital Colour Decoder
Note to subaddresses 5B,5C,5D,5E,62: All IRE values are rounded
Subaddress 63 .• 66 :
FSCO
Four bytes to program subcarrier frequency
...
FSC3
( F(jse)
FSC = round F (lie)
X
32)
2
F(fse)
Subcarrier frequency (in multiples of line frequency)
F(lIe)
Clock frequency (in multiples of line frequency)
FSC3
Most significant byte
FSCO
Least significant byte
Examples:
NTSC-M: F (fse) =227.5, F (lie)
FSC =626349397 (25555555h)
PAL-BIG: F (fse)
FSC
=1560 ==>
=283.7516, F (lIe) = 1888 ==>
=645499916 (26798COCh)
Subaddress 67 .. 6A:
L2100
First Byte of Captioning Data, Odd Field
L2101
Second Byte of Captioning Data, Odd Field
L21EO
First Byte of Extended Data, Even Field
L2IEI
Second Byte of Extended Data, Even Field
LSBs of the respective bytes are encoded immediately after run-in and framing
code, the MSBs of the respective bytes have to carry the parity bit, acc. to
the definition of line 21 encoding format.
Subaddress 6B
Selects the actual line, where Closed Caption or Extended Data are encoded.
SCCLN
Line = (SCCLN + 4) for M-systems
Line = (SCCLN + 1) for other systems
April 1994
3-345
Preliminary specification
Philips Semiconductor Video Products
SAA7187
Digital video encoder (DENC2-SQ)
Subaddress 6C:
PRCY2
0 Polarity of RCY2 as output is high-active, rising edge is taken when input, respectively (default after reset).
ORCV2
1
Polarity of RCV2 as output is low-active, falling edge is taken when input, respectively
0
Pin RCV2 is switched to input (default after reset).
1
Pin RCV2 is switched to output
0
If ORCV2=high, pin RCV2 provides a HREF signal (Horizontal Reference Pulse that is high during active
portion of line, also during Vertical Blanking Interval). (default after reset)
CBLF
If ORCV2=low, signal input to RCV2 is used for horizontal synchronization only (if TRCV2 = 1). (default
after reset)
1
PRCYI
ORCVl
TRCV2
SRCVl
If ORCV2=high, pin RCV2 provides a CBN signal (Reference Pulse that is high during active video, excluding Vertical Blanking Interval).
If ORCV2=low, signal input to RCV2 is used for horizontal synchronization (if TRCV2 = l)as well as an internal blanking signal
0
Polarity of RCVl as output is high-active, rising edge is taken when input, respectively. (default after reset)
1
Polarity of RCVl as output is low-active, falling edge is taken when input, respectively.
0
Pin RCVl is switched to input (default after reset).
1
Pin RCVl is switched to output.
0
Horizontal synchronization is taken from RCVl port. (default after reset)
1
Horizontal synchronization is taken from RCV2 pot;t.
Defines signal type on pin RCVl
SRCV11
SRCVlO as output as input
0
0
VS
VS
Vertical Sync each field (default after reset)
0
1
FS
FS
Frame Sync Codd/even)
1
0
FSEQ
FSEQ
Field SEQuence, Vertical sync every fourth (FISE=I) or
eighth field (FISE=O)
1
1
n.a.
n.a.
Subaddress 6D:
Enables individual Line 21 Encoding
CCEN
CCENI
SRCM
Line 21 Encoding OFF
0
0
1
Enables Encoding in field 1 (odd)
1
0
Enables Encoding in field 2 (even)
1
1
Enables Encoding in both fields
Defines signal type on pin RCMl
SRCMl
0
April 1994
CCENO
0
SRCMO
0
as output
VS
Vertical Sync each field
Frame Sync Codd/even)
0
1
FS
1
0
FESQ
1
1
n.a.
Field SEQuence, Vertical sync every fourth (FISE=I) or
eight field (FISE=O)
3-346
Preliminary specification
Philips Semiconductor Video Products
SAA7187
Digital video encoder (DENC2-SQ)
Subaddress 6E .. 6F:
HTRIG
Sets the Horizontal TRIGger phase related to signal onRCVl or RCV2 input.
Values above 1559 (FISE=l) or 1887 [FISE=O] are not allowed.
Increasing HTRIG decreases delays of all internally generated timing signals.
Reference mark:
Analog output horizontal sync (leading slope) coincides with active edge ofRCV used
for triggering at HTRIG = 031h [033h]
Subaddress 70:
VTRIG
Sets the Vertical TRIGger phase related to signal on RCVl input.
Increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines
Variation range of VTRIG = 0 .. 31 (1 Ph)
SBLBN
PHRES
0
Vertical Blanking is defined by programming of FAL and LAL.
1
Vertical Blanking is forced automatically at least during field synchronization and equalization pulses.
Note: If Cross-Colour Reduction is programmed, it is active between FAL and LAL in both cases.
Selects the phase reset mode of the colour subcarrier generator
PHRESI
PHRESO
0
0
no reset
0
1
reset every two lines
1
0
reset every eight fields
1
1
reset every four fields
Subaddress 71 .. 73:
BMRQ
Begin of Master ReQuest signal (RCM2).
Values above 1559 (FISE=I) or 1887 [FISE=O] are not allowed.
First active pixel at analog outputs (corresp. input pixel coinciding with RCM2) at BMRQ=OE1h [130h]
EMRQ
End of Master ReQuest signal (RCM2).
Values above 1559 (FISE=1) or 1887 [FISE=O] are not allowed.
Last active pixel at analog outputs (corresp. input pixel coinciding with RCM2) at EMRQ=5E9h [72Ah]
April 1994
3-347
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
Subaddress 77 -- 79BRCV.
Begin of output signal on RCV2 pin.
Values above 1559 (FISE=I) or 1887 [FISE=O] are not allowed.
First active pixel at analog outputs (corresp. input pixel coinciding with RCV2) at BRCV=OElh [130h]
ERCV
End of output signal on RCV2 pin.
Values above 1559 (FISE=l) or 1887 [FISE=O] are not allowed.
Last active pixel
at analog outputs (corresp. input pixel coinciding with RCV2) at ERCV=5E9h [nAh]
Subaddress 7 A __ 7D:
FLEN
LENgth ofa Field = FLEN + 1, measured in half lines
Valid range is limited to 524 ... 1022 (FISE=I) resp. 624 .. 1022 (FISE=O), FLEN should be even
FAL
First Active Line, measured in lines.
LAL
Last Active Line, measured in lines
FAL=O coincides with the first field synchronization pulse.
LAL=O coincides with the first field synchronization pulse.
Slave Transmitter
Slave Transmitter [Slave Address 89h or 8Dh]
SUB- DATA BYTE
ADDR D7
ID6
REGISTER
FUNCTION
-
Status Byte
VER2
I VERI
jD3
IDS
ID4
IVERO
ICCRDE I CCRDa
jD2
IDI
IDO
I FSQ2
I FSQl
IFSQO
no subaddress
VER
CCRDE
Version id of the device. It will be changed with all versions of the IC that have different programming models
Current Version is 000 bin.
Closed caption bytes of the even field have been encoded.
The bit is reset after information has been written to the subbaddresses 69, 6A. It is set immediately after
the data have been encoded.
CCRDa
Closed caption bytes of the odd field have been encoded.
The bit is reset after information has been written to the subbaddresses 67, 68. It is set immediately after
the data have been encoded.
FSQ
State of the internal field sequence counter.
Bit 0 (FSQO) gives the odd/even information. (Odd=Low, Even=High)
-
April 1994
3-348
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
6
0
-6
p
~4
~4
:npu t lnpu t -_. ,---
~
\\
-18
\
-24
\'.
\ \.
• .-1
cO
b1
4
4
\ :\'.
-12
;§
seE W=l
seE w=o
.~\",
-30
•
-36
\ \
-42
\
/--.
\
-48
o
1
2
3
4
5
6
7
8
"'\.
/
r
;\
/
(,\\
\
-54
,/
9
10 11 12 13 14
f(MHz)
Fig. 3: Chrominance transfer characteristic [60 Hz]
-lr··············· .. ··, .. ·.... ····· .. ···; .... ················ ...... i···············.'~<1~_,
-2~
.... ·· .... ·· .... ·,· ........ ·.. ·············, ..
-3~························~···
_6~
o
.. ·· .... !·· .... · .. ····· .. · , · · · ...............
.. ··········;··················;·················.;
____
~
0.2
____
~
0.4
....................;........................ i .....~
··················,··················,··················,'<·,~c,······· ...........
-4r··················,·· .... ········ .. ·,·················.,
-5~···
'-,~i
.................. ,
................... ;........................ ;
~
0.6
.................. ,
____L -_ _ _ _L -_ _ _ _L -_ _ _ _
0.8
1.2
Fig. 4: Chrominance transfer characteristic [60 Hz]
3-349
\ .•... ~., . •~
..................... ;........................
f(MHz)
April 1994
....~
! ....................•.................. !',y,,' ......... "' ... ~
.................. ,
____
,
~,,~
L-~
1.4
Preliminary specification
Philips Semiconductor Video Products
Digital video encoder (DENC2-SQ)
SAA7187
6
";':':.:~.;
-6
k~,~"",
',\, ''{
-12
r§
~
,0 ~..
./'---<
\ /\ I
-18
\
f
-24
OJ
.......
...... ;........
;l ~::!"b
cc RS1 =1,
~
i\
\
-30
\
-36
-42
/"'"
/,.....
\
. t/···I~\
!:,.,.\
-48
-54
-
--'---
1'1' R~1 :1
~"
o-
=0,
R~
.,-i
ro
1'1'j:: i~O=
1'1' R~1 :0
a
a
1
2
3
4
5
6
7
8
9
I'.
10 11 12 13 14
f(MHz)
Fig. 5: Luminance transfer characteristic [60 Hz]
0.5
i .1'1'1 tS1=1)
a
-0.5
-1
----------"
-1. 5
~
-2
.,-i
-2.5
~
ro
OJ
-
'\
i\
\
\
-3
\
·-3.5
-4
-4.5
-5
s·····
a
0.5
1
1.~
2
2.5
3
3.5
4
4.5
5
f(MHz)
Fig. 6: Luminance transfer characteristic [60 Hz]
April 1994
\
5.5
6
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
6
o
~"
-6
!~(,R W=1
4
~4
·~('R W=I
4
~4
[npu t
!npu t
- c--
--. ,---
!\""\
-12
\ i\\
\ \,
-18
-24
\
-30
•
\
\ \
-36
-42
,(\\
\
o
1
2
-----"'\
//
\
-48
-54
'\
3
4
i
5
6
7
8
/ !\
/
9
10 11 12 13 14
Fig. 7: Chrominance transfer characteristic [50 Hz]
..
..
~.~""
··'···~··=.~.=.7."".""
.......
>.:.7·::.~:.7.:.:.~:.~:
~ ~PUI
':':.:.::.:>--.
-1
SCBW=1
",-,,,,,,=u
444 Inpul f·
..•••..... "
-2
...
.....•....
.......
.=:.~=.=:.=:::~~:~~
~.
""':",..,:.~
-3
~,-"
~....
-4
-5
-6
o
0.2
0.4
0.6
0.8
1.2
f(MHz)
Fig. 8: Chrominance transfer characteristic [50 Hz]
April 1994
3-351
1.4
Preliminary specification
Philips Semiconductor Video Products
Digital video encoder (DENC2-SQ)
SAA7187
6
~r~c::
0
.,";.,.,
-6
:.<.~~~.- ""'"
'\
-12
;§
-18
s::
-24
,,/i:,::::s;
------
~ "'.
/)------
l
\ \ /
(
01
----
~CRS il=l
~~
_=.L
:L:K::;
\
\ !
\
'M
III
--
=n
L:L: K::;U:
\
-30
'\
-36
,---.
r,--..\
-48
II
o
1
2
3
4
5
6
7
8
9
'\
f, . . .
...
-42
-54
:.L
10
......
\ t11
:~~
'~
12
13
14
f(MHz)
Fig. 9: Luminance transfer characteristic [50 Hz]
0.5
'-'rl"Q1
0
-
='
--~
-0.5
~
-1
\
-1. 5
;§
s::
-.-I
III
01
-2
\
-2.5
-3
-3.5
-4
-4.5
-5
o 0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
f(MHz)
Fig. 10: Luminance transfer characteristic [50 Hz]
April 1994
3-352
5.5
6
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
Electrical Characteristics
Conditions: Tamb = 0 .. 70 °C; Vooo= 4.5 .. 5.5 V unless otherwise specified.
TEST
CONDITIONS
PARAMETER
SYMBOL
LIMITS
UNIT
MIN
MAX
Supply
Vooo
V OOA
supply voltage range digital
4.5
5.5
V
supply voltage range analog
4.75
5.25
V
1000
supply current
1)
-
210
rnA
IOOA
supply current
1)
-
55
rnA
V
Inputs
V IL
input voltage LOW (except SDA, SCL, AP, SP, XTALI)
-0.5
0.8
V IH
input voltage HIGH (except SDA, SCL, AP, SP, XTALI)
2.0
Vooo+O.5
V
V IH
input voltage HIGH (LLC)
2.4
Vooo+0.5
V
ILl
input leakage current
-
1
q
input capacitance
-
10
IlA
pF
CI
input capacitance
8
pF
8
pF
CI
pin 38, only
clocks
data
110 at high
input capacitance
impedance
Outputs
VOL
output voltage LOW (except XTAL, SDA)
2)
0
0.6
V
VOH
output voltage HIGH (except XTAL,DTACKN, SDA)
2)
2.4
Vooo+0.5
V
output voltage HIGH (LLC)
2) pin 38, only
2.6
Vooo+0.5
V
V OH
I 2 C Bus SDA and SCL
V IL
input voltage LOW
-0.5
1.5
V
V IH
input voltage HIGH
3.0
Vooo+O.5
V
II
input current
SDA output voltage
VI= low or high
10= 3 rnA
+1-10
VOL
IlA
V
10
output current
during acknowl.
0.4
3
rnA
Clock timing
tLLC
cycle time LLC
3)
31
44
0
duty factor tLLCh 1 tLLC
10)
40
60
ns
%
tr
rise time LLC
3)
-
5
ns
tf
fall time LLC
3)
-
6
ns
input data setup time (CREF)
6
-
ns
input data hold time (CREF)
3
-
ns
input data setup time (any other except SEL_MPU, CDIR,
RWN/SCL, AOISDA, CSN/SA, RESN, AP, SP)
6
-
ns
Input timing
tsuc
tHOC
tsu
April 1994
3-353
Preliminary specification
Philips Semiconductor Video Products
SAA7187
Digital video encoder (DENC2-SQ)
tHO
TEST·
CONDITIONS
PARAMETER
SYMBOL
input data hold time (any other except SEL_MPU, CDIR,
RWN/SCL, AO/SOA, CSN/SA, RESN, AP, SP)
LIMITS
UNIT
MIN
MAX
3
-
ns
Crystal Oscillator
24.~45454
-
30
MHz
-50
+50
10·t>
temperature range Tamb
0
70
C
load capacitance C L
8
-
pF
fn
nominal frequency (usually
Df/fn
permissible deviation fn
MHz or 29.5 MHz)
3rd harmonic
9)
crystal specification:
80
n
motional capacitance C 1
typically
1.5-20%
1.5+20%
fF
parallel capacitance Co
typically
3.5-20%
3.5+20%
pF
9
-
ns
0
-
ns
9
-
ns
0
-
ns
-
440
ns
series resonance resistance Rs
MPU interface timing
tAS
address setup time
tAH
address hold time
5)
tRWS
read/write setup time
tRWH
read/write hold time
too
data valid from CSN (read)
tOF
data bus floating from CSN (read)
6),7), n=5
-
275
ns
tos
data bus setup time (write)
5)
9
-
ns
tOH
data bus hold time (write)
5)
9
-
ns
tACS
acknowledge delay from CSN
6),7), n=11
-
520
ns
tcSD
CSN high from acknowledge
0
-
ns
tOAT
OTACKN floating from CSN high
-
360
ns
pF
5)
6), 7), 8), n=9
6),7), n=7
Data and reference signal output timing
CL
output load capacitance
7.5
40
toH
output hold time
4
-
ns
too
output delay time (CREF in output mode)
-
25
ns
1.9
2.1
V
18
35
80
C, Y, and CVBS outputs
Vo
output signal (peak to peak value)
RI
internal serial resistance
RL
output load resistance
B
output signal bandwidth (D/A-converters)
ILE
OLE
4)
-
n
n
10
-
MHz
LF integral linearity error (D/A-converters)
-
±2
LSB
LF differential linearity error (D/A-converters)
-
±1
LSB
-3dB
Notes:
1)
at maximum supply voltages and with high-activity input signals
2)
The levels have to be measured with load circuits of 1.2 kn to 3.0 V (standard TTL load), C L = 25pF.
April 1994
3-354
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
3)
The data is for both, input and output direction.
4)
for full digital range, without load, VOOA
put voltage (digital zero at DAC) is 0.2 V.
5)
The value is calculated via equation (1)
6)
7)
The value depends on the clock frequency. The numbers given are calculated with fLLC
The values are calculated via equation (2)
= 5.0 V. The typical voltage swing is 2.0 V, the typical minimum out=24.54 MHz
8)
The falling edge of DTACKN will always occur 1 * LLC after data is valid.
9)
If internal oscillator is used, crystal deviation of fn is directly proportional to the deviation of subcarrier frequency and
line/ field frequency.
10)
With LLC in input mode. In output mode, with a crystal connected to XTAL/ XTALI typically 50 %.
Equations:
(1 )
t =tsu + tHO
(2)
tdmax
=too + n*tLLC + tLLC + tsu
...
...
ClockLLC-out
LLC
tLLCh
-t
-I
~
~~~
Input Dat
~
~
~
lzL
/
I
I.5V
II
0.8V
- . tr.-
- . tf.-
~
~
valid
...
valid
not valid
toD
X_______
.-tOH-'
Output Da:::x_ _ _ _v_a_Ii_d_ _
n_ot_v_a_li_d_ _ _ _ _
Fig. 11: Clock Data Timing
April 1994
2.4V
1\
\:
.-tH~
tsu
- . tr.-
- . tf.-
tLLCh
0.6V
/
tLLC
....
~
2.6V
1.5V
--l-
/
\:
.-tH~
ClockLLC-in
~
~
3-355
~
~
-
2.0V
-
0.8V
=~: ~
_____v_al_id_ _ _ _
Philips Semiconductor Video Products
Preliminary specification
Digital Video encoder (DENC2-SQ)
SAA7187
CREF
VP1(n)
X
Y(O)
X
Y(1)
X
Y(2)
X
Y(3)
X
Y(4)
VP3(n)
X
Cb(O)
X
Cr(O)
X
Cb(2)
X
Cr(2)
X
Cb(4)
RCV2
/
Fig. 12: Dig. TV - Timing
Notes:
1)
The data demultiplex phase is coupled to the internal horizontal phase.
2)
The CREF signal applies only for the 16 lines DIG-TV format,because these signals are only valid in 12.27114.75MHz.
3)
The phase of the RCV2 signal is programmed to OE1h [ 130h for 50 Hz ] in this example in output mode (BRCV2)
HIL transition
count start
4 bits
reserved
HPLL
increment
FSCPLL increment
t t
not used in DENC2-SQ
valid invalid
sample sample
(1) sequence bit:
PAL:
0: (R-Y) line normal
1 : (R-Y) line inverted
NTSC: 0: (no change)
(2) reserved bits: 276 with 50Hz sysyems;188 with 60Hz systems
Fig. 13: RTCI timing
April 1994
3-356
Preliminary specification
Philips Semiconductor Video Products
SAA7187
Digital video encoder (DENC2-SQ)
AO
•
•
\
CSN
RWN
....
tAS
Y
.....
tRWS
tAH
....
/
....
•
tRWH
'....<
0
D(7 .. 0 )
\
I
.... tOF •
....-too.
\
DTAC KN
/
~ tACS---' .... tCSO •
. . - tOAT - .
Fig. 14: MPU Interface Timing (Read cycle)
AO
•
tAS
D(7 .. 0 )
DTAC KN
•
/
....
•
tRWH ....
....-
•
tOH
\
CSN
RWN
....
~
•
}
•
tRWS
tos
tAH
....
K
\
. . . . - - tACS---. .... tcSO •
/
. . - tOAT - .
Fig. 15: MPU Interface Timing (Write cycle)
April 1994
3-357
....
»
""\J
-0
0
==
cO'
~
co
;:::t:
.J>.
0)
Cfft5V digital
..=.Dgnd
+5Vanalog
<
O.IIlF
Dgnd
O·lJlF Agnd
~II
.111 Dgnd
~
lOpF lOpFI
IIHIII
O.IIlFDgnd
15K
O.IIlFDgnd
>
2
"0
17
37
c
~
:s:;
8.c
-m
~
CD
0
""\J
!l
UI
0
VrefH CUR VDDA
54
55
47
z
()
~
f\)
r;'
-=
~
35n 1
DAC3
0'
I
20n 0.62V(p_p)2
en
C
49
75n
t:r1
=
8
=
:3n>
=
....,
:::J
C.
0
CD
IIIH
VDDA
56
VDDD
67
en
CD
3
o·
0
c.
a.
Agnd O.IIlF
UI
CD
:::J
(")
HilI
IIIH
HilI
~
~
0
HilI
O.IIlF Agnd
Agnd O.IIlF
HilI
~
rRj'
a:
CD
~
"6.
0
~ ~,
VJ
(J1
(Xl
"'= Agnd:
-
Digital
n>
in- and
outputs
-=0
0
t:r1
Z
1.0V(p_p)2
DAC2
~y
SAA7187
75n
"'= Agnd
(i
N
1.23V(p_p)2
DACI
00
CVBS
,0
75n
46
Xl: 24.545454 MHz, Philips n.n.
29.5 MHz
, Philips n.n.
VrefL
Agnd
1,8, 19,28,35" 62
52
"'= Agnd
""\J
en
"'=
Dgnd
"'=
Agnd
(1) : typical value
(2) : for 100/100 color bar
»»
-.....J
....
(X)
-.....J
-i.
3·
:r
1\1
-<
UI
-0
0
1\1
0
:::J
d:
Preliminary specification
Philips Semiconductor Video Products
SAA7188A
Digital video encoder (DENC2-M)
FEATURES
Quick Reference Data
•
Monolithic CMOS 5V device
•
Digital PALINTSC encoder
•
System Pixel Frequency: 13.5 MHz
Vooo
digital supply voltage range
4.5
•
Accepts MPEG decoded data.
V OOA
analog supply voltage range
4.75
•
8-bit wide MPEG port.
1000
supply current digital
-
•
Input data format Cb,Y,Cr,Y, ...
(CCIR 656 like)
IOOA
supply current analog
-
Vi
input signal levels
TTL - compatible
V
•
16-bit wide YUV Input port
Vo
•
IIC Bus control port or alternatively
MPU parallel control port
analog output signals, Y , C
and CVBS without load
(peak to peak value)
-
V
•
Encoder can be master or slave
RL
load resistance
80
-
-
n
Programmable horizontal and vertical input synchronization phase
ILE
LF integral linearity error
-
-
±2
LSB
DLE
LF differential linearity error
-
-
±1
LSB
Tarnb
operating ambient temperature range
0
-
70
°C
•
•
Programmable horizontal sync output phase
•
OSD overlay with LUTs (8*3 bytes)
•
•
•
•
•
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
5.0
5.5
V
5.0
5.25
V
140
170
rnA
50
55
rnA
2
-
General Description
clock generator as well as on chip DfA
converters.
Macrovision Pay· -per-View copy The
Digital
Video
Encoder 2 The CIrCUIt
. . .IS compab'ble to the DIG.
(DENC2-M) encodes digital YUV video TV2 h' f '1
Protection system as option (Note 1) data
to an NTSC or PAL CVBS or
c Ip amI y.
Cross colour reduction
S-Video signal.
'Line 21' Closed Caption encoder
DACs running at 27 MHz with The circuit accepts CCIR compatible
10 bits resolution
YUV data with 720 active pixels per
line in 4:2:2 multiplexed formats, e.g.
Controlled rise-ffaIl times of output MPEG decoded data. It includes a syncf
syncs and blanking
•
Down mode of DACs
•
CVBS and S-Video output simultaneously.
•
PLCC68 package
Note I: This device is protected U.S. patent
numbers 4631603. 4577216 and 4819098 and
other intellectual property rights. The Macrovision
anticopy process is licensed for non-commercial
home use only. whiCh is its sole intended use in
this device. Please contact your nearest Philips
Semiconductors sales office for more information.
May 1994
PACKAGE
EXTENDED
TYPE NUMBER PINS PIN POSITION MATERIAL
SAA7188A
68
3-359
PLCC
plastic
CODE
SOT188
Preliminary specification
Philips Semiconductor Video Products
SAA7188A
Digital video encoder (DENC2-M)
u. >-. u.
48,50,
VDD A
54,5~
CU R
55
Vre fH
..
47
..
..
..
C')
Il)
10
I ~I
>
>
>
o
o
>
N
\C)
&;
\C)
It)
CJ)
CJ)
-:t
Xt t I-U
::>~
Q.cr:
I-w
::>1-
Oz
~~
~
n
--
W
r-:
~
......
~
I
t'"'-
(f'l
"
-
--
...
--
I
U~
Z...,J
-
----
>-u
en
.....
-.. 6
-.. 39
_ 36
-
__ 38
en
(ij
c
C)
i:7.i
C)
c
~~
7
l
AI
.... R
.... R
CV2
CV1
C DIR
-
.. C REF
... LLC
-
40 .. XTAL
41
XTALI
"E
F
RTC I
W
Cl
-
43 ...
---
0
U
Z
w
J~
--
-- -
cr:
..l<:
0
0
u
r------.
..
en
ec
u--E
OSD(2 :0\
KEY
31
D
cr:
-..
-..
cr:
W
I
(!J
~
«
Cl
..
«
z
«
~
18 ..
rJ
B
0
N
0'
t::.
--
E
I- cr:
w
I-
u
AI
.....
,
---
B
0'
r:..:
58
__ 60
-'-
0
0\
N
(f'l
r C\I'F
... 1
~
u
a:
~
u
a:
Fig. 1 : Block Diagram
3-360
-....0
TACKN
- -
....AO/SDA
RWN/SCL
.. 59
__ 61
z
-
t
C SN/SA
68
S
5 to 2, 66 to 61 .. DP(7:0)
..
_ 8,28,42,62
~
0\
~
U
«
U.
Z
0
$
N
May 1994
0
-
0
(ij
34,33,
32
RESN
.. 57
::J
(l)
~
-
...,J W
VSS
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-M)
SAA7188A
PINNING
SYMBOL
PIN
VSS
1
DP(4)
2
DESCRIPTION
Digital negative supply voltage (Ground)
DP(5)
3
DP(6)
4
DP(7)
5
RCVl
6
Raster Control 1 for Video port. Depending on the synchronization mode, this pin
receives/provides a VSIFSIFSEQ signal.
RCV2
7
Raster Control 2 for Video port. Depending on the synchronization mode, this pin
receives/provides a HSIHREF/CBL signal
VSS
8
Digital negative supply voltage (Ground)
VP(O)
9
VP(1)
10
VP(2)
11
VP(3)
12
VP(4)
13
VP(5)
14
Upper 4 bits of the Data Port. If Pin 68 (SEL_MPU) is high, this is the data bus of the parallel MPU interface. If it is low, they are the UV lines of the Video Port
Video Port. This is an input for CCIR-656 compatible, multiplexed video data. Ifthe 16-bit
DIG-TV2 format is used, this is the Y-data.
VP(6)
15
VP(7)
16
VDD
17
Digital positive supply voltage.
SEL_ED
18
Select Encoder Data. Selects data either from MPEG port or from video port as Encoder
input.
Digital negative supply voltage (Ground)
VSS
19
MP(7)
20
MP(6)
21
MP(5)
22
MP(4)
23
MP(3)
24
MP(2)
25
MP(1)
26
MP(O)
27
VSS
28
Digital negative supply voltage (Ground)
RCMl
29
Raster control 1 for MPEG port. This pin provides a VSIFSIFSEQ signal.
RCM2
30
Raster control 2 for MPEG port. The pin provides a HS pulse for the MPEG decoder.
KEY
31
Key signal for OSD. It is high-active.
OSD(O)
32
OSD(1)
33
OSD(2)
34
MPEG Port. It is an input for CCIR-656 style multiplexed YUV data.
On Screen Display data. This is the index for the internal OSD lookup table.
VSS
35
Digital negative supply voltage (Ground)
CDIR
36
Clock direction. If the CDIR input is high, the circuit receives a clock signal, otherwise
LLC and CREF are generated by the internal crystal oscillator.
VDD
37
Digital positive supply voltage.
May 1994
3-361
Preliminary specification
Philips Semiconductor Video Products
SAA7188A
Digital video encoder (DENC2-M)
PINNING
SYMBOL
PIN
DESCRIPTION
LLC
38
Line Locked clock. This is the 27 MHz master clock for the encoder. The direction is set
by the CDIR pin.
CREF
39
Clock Reference signal. This is the clock qualifier for DIG-TV2 compatible signals.
XTAL
40
Crystal oscillator output (to crystal).
XTALI
41
Crystal oscillator input (from crystal). If the oscillator is not used, this pin should be connected to ground.
VSS
42
Digital negative supply voltage (Ground)
RTCI
43
Real Time Control Input. If the clock is provided by a SAA715IB, RTCI should be connected to the RTCO pin of the decoder to improve the signal quality.
AP
44
Test pin. Connect to digital ground for normal operation.
SP
45
Test pin. Connect to digital ground for normal operation.
Lower reference voltage for the D/A converters.
VREFL
46
VREFH
47
Upper reference voltage for the D/A converters.
VDDA
48
Analog positive supply voltage for the D/A converters and output amplifiers.
C
49
Analog output of the chrominace signal.
VDDA
y
50
Analog positive supply voltage for the D/A converters and output amplifiers.
51
Analog output of the luminance signal.
VSSA
52
Analog negative supply voltage for the D/A converters and output amplifiers (Ground).
CVBS
53
Analog output of the CVBS signal.
VDDA
54
Analog positive supply voltage for the D/A converters and output amplifiers.
CUR
55
Current input for the output amplifiers, connect via 15k!} to VDDA.
VDDA
56
Analog positive supply voltage for the D/A converters and output amplifiers.
RESN
57
Reset input, low active. After reset is applied, all outputs are in tristate/input mode. The
IIC receiver waits for the start condition.
DTACKN
58
Data acknowledge output of the parallel MPU interface; low-active, otherwise high-impedance.
RWN/SCL
59
If pin 68 (SEL_MPU) is high, this is the read/write signal of the parallel MPU interface,
otherwise it is the IIC serial clock line.
AO/SDA
60
If pin 68 (SEL_MPU) is high, this is the address signal of the parallel MPU interface, otherwise it is the IIC serial data line.
CSN/SA
61
If pin 68 (SEL_MPU) is high, this is the chip select signal of the parallel MPU interface,
otherwise it is the IIC slave address select pin:
Low: Slave address = 88h;
High: Slave address = 8Ch
Digital negative supply voltage (Ground)
VSS
62
DP(O)
63
DP(l)
64
DP(2)
65
DP(3) .
66
VDD
67
Digital positive supply voltage.
SEL_MPU
68
Select MPU interface. If it is high, the parallel MPU interface is active, otherwise the IIC
bus interface will be used.
May 1994
Lower 4 bits of the Data Port. If Pin 68 (SEL_MPU) is high, this is the data bus of the parallel MPU interface. If it is low, they are the UV lines of the Video Port
3-362
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-M)
SAA7188A
z
5
~
o
:r:
U.
Z
W
~
a:
a:
>
CSN/SA
...J
U.
w
a: a..
> en
a..
«
RTCI
VSS
OP(O)
XTALI
XTAL
OP(2)
CREF
OP(3)
LLC
VOO
VOO
SEL_MPU
VSS
COIR
SAA7188A
VSS
OP(4)
OSO(2)
OP(5)
OSO(1)
OP(6)
OSO(O)
OP(7)
KEY
RCV1
RCM2
RCV2
RCM1
vss
vss
VP(O)
MP(O)
Fig. 2: Pinning Diagram
Functional Description
The digital MPEG-compatible Video
Encoder (DENC2-M) encodes digital
luminance and chrominance into analog
CVBS- and simultaneously S - Video
(Y/C) signals. NTSC-M and PAL BIG
standards as well as sub-standards are
supported.
The basic encoder function consists of
subcarrier generation and colour modulation as well as insertion of synchronization
signals.
Luminance
and
chrominance signals are filtered according to the standard requirements
RS-170-A and CCIR-624.
May 1994
For ease of analog post filtering the signals The Data port can handle the data of an
are two times oversampled w.r.t. pixel 8 .bit wide microprocessor interface,
clock before digital-to-analog conversion. alternatively.
For total filter transfer characteristics see
figs 3, 4, 5 and 6. The DACs are realized
with full 10 bit resolution. '!'he encoder
provides three 8 bit wide data ports, that
serve different applications.
The 8 bit multiplexed Cb-Y-Cr formats
are CCIR-656 (01 format) compatible,
but the SAY, EAV e;t.c. codes are not
decoded.
A crystal-stable master clock (LLC) of
The MPEG port (MP) as well as the Video 27 MHz, which is twice the CCIR lineport (VP) accept 8 lines multiplexed locked pixel clock of 13.5 MHz, needs
to be supplied externally. Optionally, a
Cb-Y-Cr data.
crystal oscillator input/output pair of
The Video port (VP) is also able to handle pins and an on-chip clock driver is proDIG-TV2 family compatible 16 bit YUV vided. Additionally, a DMSD2 compatisignals. In this case, the Data port (DP) is ble clock interface, using CREF (input
used for the UN components.
or output) and RTC (see data sheet
SAA 7151B) is available.
3-363
Philips Semiconductor Video Products
Preliminary specification
SAA7188A
Digital video encoder (DENC2-M)
The DENC2-M synthesizes all necessary internal signals, colour subcarrier
frequency, as well as synchronization
signals, from that clock. DENC2-M is
always timing master for the MPEG port
(MP), but it can additionally be configured as master or slave for the Video
port (VP):
The IC also contains Closed Caption
and Extended, Data Services Encoding
(Line 21), and supports Anti-Taping signal generation acc. to Macrovision; it
also supports OSD via KEY and three
bit overlay techniques by a 24*8 LUT.
The IC can be programmed via I2C or
8-bit MPU interface, but only one interface configuration can be active at a
time; if the 16 bit Video port mode (VP
and DP) is being used, only the I2C
interface can be selected.
A lot of possibilities is provided for setting of different video parameters like
Black- and Blanking level control, colour subcarrier frequency, variable burst
amplitude etc.
During Reset (RESN=low) and after
Reset released, all digital 110 stages are
set to input mode. A Reset forces the
control interfaces to abort any running
bus transfer and, to set register 3Ah to
contents 13h, register 61h to contents
15h, and register 6Ch to contents OOh.
All other control registers are not influenced by a Reset.
Data Manager
In the Data Manager, real time arbitration on the data stream to be encoded is
performed.
The actual line number where data are to
be encoded in, can be modified in a certain
range.
Encoder
Video Path:
Data clock frequency is acc. to definiThe encoder generates put of Y,U,V base tion for NTSC-M standard 32 times horband signals output signals luminance and izontalline frequency.
colour subcarrier, suitable for use as
Data LOW at the output of the DACs
CVBS or separate Y and C signals.
corresponds to 0 IRE, data HIGH at the
Luminance is modified in gain as well as output of the DACs corresponds to
in offset (latter programmable in a certain about 50 IRE.
range to enable different black level set-ups).After' having been inserted a fixed It is also possible to encode Closed Capsync level, acc. to standard composite sync tion Data for 50 Hz field frequencies at
schemes, and blanking level, programma- 32 times horizontal line frequency.
ble also in a certain range to allow for
manipulations with Macrovision Anti-Tap- Anti-Taping:
ing, additional insertion of AGe super For more information, please contact
white pulses, programmable in height, is your nearest Philips Semiconductors
suppqrted.
sales office.
In order to enable easy analog post filtering, luminance is interpolated from 13.5 Output Interface
MHz data rate to 27 MHz data rate, providing luminance in 10 bit resolution. This In the output interface encoded Y and C
filter is also used to define smoothed tran- signals are converted from digital to
sients for sync pulses and blanking period. analog in 10 bit resolution both .. Y and
For transfer characteristic of the lumi- C signals are combined to a 10 bit CVBnance interpolation filter see figs. 5 and 6. S-signal, as well; in front of the summation point, the luminance signal can
Chrominance is modified in gain (programmable separately for U and V), stand- optionally be fed through a further filter
stage, suppressing components in the
ard dependent burst is inserted, before
range of subcarrier frequency. Thus, a
base band colour signals are interpolated
kind of Cross Colour reduction is profrom 6.75 MHz data rate to 27 MHz data
vided, useful in a standard TV set with
rate. One of the, interpolation stages can be
CVBS input.
by-passed, thus providing a higher colour
bandwidth, which can be made use of for Slopes of synchronization pulses are not
Y/C output. For transfer characteristics of affected with any Cross Colour reducthe chrominance interpolation filter see tion active.
figs. 3 and 4.
Three different filter characteristics or
The amplitude of inserted burst is pro- bypass are available, see fig. 5.
grammable in a certain range, suitable for
The CVBS output occurs with the same
standard signals as well as for special processing delay as, the Y,C outputs do.
effects. Behind the succeeding quadrature Absolute amplitudes at the input of the
modulator, colour.in 10 bit resolution is DAC for CVBS is reduced by 15116
provided on subcarrier.
w.r.t., Y- and C- DACs to make opti-
Depending on hardware conditions (signals on pins SEL_ED, KEY, OSD(2-0),
MP(7-0), VP(7-0), DP(7-0)) and different software programming, either data
from the MP port, from the VP port, or The numeric ratib between Y and C output
from the OSD port are selected to be is acc. to standards.
encoded to CVBS and Y/C signals.
Closed Caption Encoder:
Optionally, the OSD colour look-:-up
By
means of this circuit, data acc. to the
tables located in this block, can be read
out in a pre-defined sequence (8 steps specification of Closed Caption or
per active video line), achieving e.g. a Extended Data Service, delivered by the
colour bar test pattern generator without control interface, can be encoded
need for an external data, source. The (LINE21), Two dedicated pairs of bytes
colour bar function is under software (two bytes per field), each pair preceded
by run-in clocks and framing code, are
control, only.
possible.
May 1994
3.-364
mized use of conversion ranges.
Outputs of all DACs can be set together
via software control to minimum output
voltage for either purpose.
Preliminary specification
Philips Semiconductor Video Products
Digital video encoder (DENC2-M)
SAA7188A
Synchronization
On the RCM1 port the same signals as
on RCV1 (as output) are available; on
The synchronization of the DENC2-M RCM2 the IC provides a horizontal
is able to operate in two modes:
pulse with programmable start and stop
In the slave mode, the circuit accepts phase.
sync pulses at the bi-directional RCV1 The length of a field as well as start and
port. The timing and trigger behavioijr end of its active part can be prorelated to the video signal on VP (and grammed. The active part of a field
DP, if used) can be influenced by pro- always starts at the beginning of a line.
gramming the polarity and on-chip
delay of RCVl. Active slope of RCV1
defines the vertical phase and optionally
the odd!even- and colour frame phase to Control Interface
be initialized, it can be used also to set DENC2-M contains two control interthe horizontal phase.
faces: An lIC slave transceiver and 8 bit
Input levels and formats
DENC2-M expects digital YUV data with
levels (digital codes) acc to CCIR601:
Deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for
luminance is set to pre-defined values, distinguishable for 7.5 IRE setup or without
setup.
The MPEG port accepts only 8 - bit multiplexed CCIR656 compatible data.
If the lIC bus interface is used, the VP port
can handle both formats, 8 bit multiplexed
Cb YCr data on the VP lines, or the 16 bit
If the horizontal phase shall not be influ- parallel microprocessor interface. The DTV2 format with the Y signal on the
enced by RCV1, a horizontal pulse interfaces cannot be used simultaneously. VP lines and the UV signal on the DP
needs to be supplied at the RCV2 pin. The IIC bus interface is a standard slave port.
Timing and trigger behaviour can be transceiver, supporti~. 7 bit slave
Reference levels are measured with a
influenced for RCV2, as well.
It/sec guaranteed
addresses and 100
colour bar, 100% white, 100% ampliIf there are missing pulses at RCVl and! transfer rate. It uses 8 bit subaddressing tude, 100% saturation.
or RCV2, the time base of DENC2-M with auto-increment function. All registers
runs free, thus an arbitrary number of are write-only, except one readable status
sync slopes may miss, but no additional byte.
pulses (such with wrong phase) must Two IIC slave addresses can be selected
occur.
(pin SEL_MPU must be low!):
If the vertical and horizontal phase is
derived from RCV1, RCV2 can be used
for horizontal or composite blanking
input or output.
In the master mode, the time base of the
circuit runs free continuously. On the
RCV 1 port, the IC can output:
88h:
Low at pin 61
8Ch:
High at pin 61
The parallel interface is defined by
D(7-0) data bus
CSN
low-active chip select signal
•
a Vertical Sync signal (VS) with 3 or
2.5 lines duration, or
RWN read!write not signal, low for a
write cycle
•
an ODDIEVEN signal which is low
in odd fields, or
DTACKN 680XX style data acknowledge (hand-shake), active low
•
a field sequence signal (FSEQ)
which is high in the first of 4 resp. 8
fields.
AO
On the RCV2 port, the IC can provide a
horizontal pulse with programmable
start and stop phase; this pulse can be
inhibited in the vertical blanking period
to build up e.g. a composite blanking
signal.
register select, low selects
address, high selects data
The parallel interface uses two registers,
one auto-incremental containing the current address of a control register (equals
subaddress with lIC control), one containing actual data. The currently addressed
register is mapped to the corresponding
control register.
The phase of the pulses output on RCV1 Via a read access to the address register,
or RCV2 are related on the VP port, the status byte can be read optionally; no
polarity of both signals is selectable.
other read access is provided.
The DENC2-M is always timing master
for the source at the MP input. The IC
provides two signals for synchronizing
this source:
May 1994
3-365
Philips Semiconductor· Video Products
Preliminary specification
Digital video encoder (DENC2-M)
SAA7188A
CCIR signal component levels
. Signal
IRE
Y
0
50
100
dig. level
bottom peak.
colourless
Cb
top peak
bottom peak.
Cr
Code
16
126
' 235
16
128
240
16
128
240
colourless
top peak
straight binary
straight binary
straight binary
The 8 bit multiplexed format (CCIR656 like)
Time
Sample
Lum. pixel number
0
1
2
Cbo Yo
3
4
0
0
Colour pixel number
6
I7
2
The 16 bit multiplexed format (DTV2 format)
Time
5
Cro Y 1 Cb2 Y 2 Cr2\ Y 3
1
3
2
011
2
I
3
4
I
5
6
I
Sample Y - line
Yo
Y1
Y2
Y3
Sample UV - line
Cbo
Cro
Cb2
Cr2
0
1
2
Lum. pixel number
Colour pixel number
May 1994
0
7
3
2
3-366
Preliminary specification
Philips Semiconductor Video Products
SAA7188A
Digital video encoder (DENC2-M)
Bit allocation map
Slave Receiver [Slave Address 88b or 8Cb]
REGISTER
FUNCTION
NULL
SUB- DATA BYTE
ADDR D7
D6
00
0
0
DS
D4
D3
D2
Dl
DO
0
0
0
0
0
0
0
0
0
0
0
.....
NULL
39
0
0
0
InpucPorCControl
3A
CBENB . 0
0
V656
VUV2C
MY2C
MUV2C
OSD_LUT_YO
42
OSDY07
OSDY06
OSDY05
OSDY04 OSDY03
OSDY02
OSDYOI
OSDYOO
OSD_LUT_UO
43
OSDU07
OSDU06
OSDU05
OSDU04 OSDU03
OSDU02
OSDUOI
OSDUOO
OSD_LUT_VO
44
OSDV07
OSDV06
OSDV05
OSDV04 OSDV03
OSDV02
OSDVOI
OSDVOO
OSDY70
VY2C
.....
OSD_LUT_Y7
57
OSDY77
OSDY76
OSDY75
OSDY74 OSDY73
OSDY72
OSDY71
OSD_LUT_U7
58
OSDU77
OSDU76
OSDU75
OSDU74 OSDU73
OSDU72
OSDU71
OSDU70
OSD_LUT_V7
59
OSDV77
OSDV76
OSDV75
OSDV74 OSDV73
OSDV72
OSDV71
OSDV70
Chroma_Phase
5A
CHPS7
CHPS6
CHPS5
CHPS4
CHPS2
CHPSI
CHPSO
Gain_U
5B
GAINU7
GAINU6
GAlNU5
GAINU4 GAINU3
GAINU2
GAINUI
GAINUO
Gain_V
5C
GAINV7
GAINV6
GAINV5
GAINV4 GAINV3
GAINV2
GAINVI
GAINVO
Gain_U_MSB,
Black_Lev
5D
GAINU8
0
BLCKL5
BLCKL4 BLCKL3
BLCKL2
BLCKLI
BLCKLO
Gain_V_MSB,
Blank_Lev
5E
GAINV8
0
BLNNL5
BLNNL4 BLNNL3
BLNNL2
BLNNLl
BLNNLO
NULL
5F
0
0
0
0
0
0
0
0
X-CoCSelect
60
CCRSI
CCRSO
0
0
0
0
0
0
Standard_Control
61
0
DOWN
INPIl
YGS
RTCE
SCBW
PAL
FISE
BurscAmplitude
62
SQP
BSTA6
BSTA5
BSTA4
BSTA3
BSTA2
BSTAI
BSTAO
SubcarriecO
63
FSC07
FSC06
FSC05
FSC04
FSC03 .
FSC02
FSCOI
FSCOO
CHPS3
Subcarriecl
64
FSC15
FSC14
FSC13
FSC12
FSCll
FSClO
FSC09
FSC08
Subcarriec2
65
FSC23
FSC22
FSC21
FSC20
FSC19
FSC18
FSC17
FSC16
FSC24
Subcarriec3
66
FSC31
FSC30
FSC29
FSC28
FSC27
FSC26
FSC25
Line21_0dd_0
67
L21007
L21006
L21005
L2 1004
L21003
L21002
L21001
L21000
Line2 C Odd_l
68
L21017
L21016
L21015
L21014
L21013
L21012
L21011
L21010
Line2CEven_0
69
L2IE07
L2IE06
L2IE05
L21E04
L2IE03
L2IE02
L2IEOI
L2IEOO
Line21_Even_l
6A
L21E17
L2IE16
L21E15
L2IE14
L21E13
L2IE12
L2IEll
L2IElO
Encod_Ctrl,CC_Line
6B
MODINI
MODINO 0
SCCLN4 SCCLN3
SCCLN2
SCCLNI
SCCLNO
:RCV_PorCControl
6C
SRCVll
SRCVIO
TRCV2
ORCVl
PRCVl
CBLF
ORCV2
PRCV2
RCM, CC-Mode
6D
0
0
0
0
SRCMll
SRCMlO
CCENI
H-Trigger
6E
HTRIG7
HTRIG6
HTRIG5
HTRIG4
HTRIG3
HTRIG2
HTRIGI
CCENO
HTRIGO·-
H-Trigger
6F
0
0
0
0
0
HTRIGlO HTRIG09 HTRIG08
May 1994
3·367
Preliminary specification
Philips Semiconductor Video Products
SAA7188A
Digital video encoder (DENC2-M)
Slave Receiver [ Slave Address 88b or 8Cb]
REGISTER
FUNCTION
SUB- DATA BYTE
ADDR D7
D6
D5
D4
D3
D2
Dl
DO
SBLBN
VTRIG4
VTRIG3
VTRIG2
VTRIGI
VTRIGO
BMRQ5
BMRQ4
BMRQ3
BMRQ2
BMRQI
BMRQO
EMRQ5
EMRQ4
EMRQ3
EMRQ2
EMRQI
EMRQO
Fsc_Res_Mode,
V-Trigger
70
Begin_MP_Request
71
BMRQ7
BMRQ6
End_MP_Request
72
EMRQ7
EMRQ6
MSBs_MP_Request
73
0
EMRQlO EMRQ09
EMRQ08 0
NULL
74
0
0
0
0
0
0
0
NULL
75
0
0
0
0
0
0
0
0
NULL
76
0
0
0
0
0
0
0
0
Begin_RCV2...:.out
77
BRCV7
BRCV6
BRCV5
BRCV4
BRCV3
BRCV2
BRCVI
BRCVO
End_RCV2_out
78
ERCV7
ERCV6
ERCV5
ERCV4
ERCV3
ERCV2
ERCVl
ERCVO
MSBs_RCV2_out
79
0
ERCVlO
ERCV09
ERCV08 0
BRCVlO
BRCV09
BRCV08
Field_Length
7A
FLEN7
FLEN6
FLEN5
FLEN4
FLEN3
FLEN2
FLENI
FLENO
Firs t_Act_Li ne
7B
FAL7
FAL6
FAL5
FAU
FAL3
FAL2
FALl
FALO
LasCAcCLine
7C
LAL7
LAL6
LAL5
LAL4
LAL3
LAL2
LALl
LALO
MSBs_Field_Ctrl
70
0
0
LAL8
FAL8
0
0
FLEN9
FLEN8
PHRESI
PHRESO
BMRQlO BMRQ09 BMRQ08
0
Note:
All bits labelled '0' are reserved. They must be programmed with O.
12 C-Bus Format
S 1Slave Address
1
A
Subaddress
AIDA I A 0
Portion
Meaning
S
start condition
Slave Address
1000100X or 1000 11 OX
A
acknowledge, generated by the slave
Subaddress(*)
subaddress byte
DATA
data byte
--------
continued data bytes and Ns
P
stop condition
A
1--------1 DAIA n
A
X: read/write control bit; X=O is order to write; X=l is order to read, no
subaddressing with read.
(*) if more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed.
May 1994
. 3-368
p
Preliminary specification
Philips Semiconductor Video Products
SAA7188A
Digital video encoder (DENC2-M)
Slave Receiver
Subaddress 3A:
MUV2C
0
Cb/Cr data at MP are two's complement
1
Cb/Cr data at MP are straight binary (default after reset)
MY2C
0
Y data at MP are two's complement
1
Y data at MP are straight binary (default after reset)
0
Cb/Cr data input to VP or DP are two's complement (default after reset)
1
Cb/Cr data input to VP or DP are straight binary
VUV2C
VY2C
V656
CBENB
0
Y data input to VP are two's complement (default after reset)
1
Y data input to VP are straight binary
0
Selects YUV 422 format on VP (8 lines Y) and DP (8 lines multiplexed Cb/Cr)
1
Selects CCIR 656 compatible format on VP (8 lines Cb,Y,Cr,Y) (default after reset)
0
Data from input ports are encoded (default afterreset)
1
Colour Bar with programmable colours (entries of OSD-LUTs) is encoded
The LUTs are read in upward order from index 0 to index 7,
Subaddress 42 ,. 59:
OSDY
OSDU
OSDV
Contents of OSD Look-up tables, All 8 entries are 8 bits. Data representation is acc,o, to CCIR 601 [Y,Cb,Cr], but
two's complement, e.g. for a 100/100 [upper number] or 100175 [lower number] Colour Bar:
OSDU
OSDV
107(6Bh)
107(6Bh)
O(OOh)
O(OOh)
O(OOh)
O(OOh)
0
Yellow
82(52h)
34 (22h)
144(90h)
172 (ACh)
18(12h)
14(OEh)
1
Cyan
42 (2Ah)
03(03h)
38(26h)
29 (lDh)
144(90h)
172 (ACh)
2
Green
17(11h)
240(FOh)
182(B6h)
200(C8h)
162 (A2h)
185(B9h)
3
Magenta
234 (EAh)
212(D4h)
74 (4Ah)
56(38h)
94(5Eh)
71(47h)
4
Red
209(D1h)
193(C1h)
218 (DAh)
227(E3h)
112(70h)
84(54h)
5
Blue
169(A9h)
163 (A3h)
112(70h)
84(54h)
238(EEh)
242 (F2h)
6
Black
144(90h)
144(90h)
O(OOh)
O(OOh)
O(OOh)
O(OOh)
7
Colour
White
OSDY
index (for normal colour bar with CBENB
=1)
Subaddress SA:
Phase of encoded colour subcarrier (including burst) realtive to H - sync. Can be adjusted in steps of 3601256
degrees.
May 1994
3-369
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-M)
SAA7188A
Subaddress 5B, 5D:
GAINU
Variable gain for Cb signal (Input Representation acc. to CCIR 601) White - Black = 92.5 IRE
White - Black = 92.5 IRE
GAINU=O
Output subcarrier of U contribution = 0
GAINU=118 (76h)
Output subcarrier of U contribution = nominal
GAINU = -2.17
* nominal ... nominal ... 2.16 * nominal
White - Black = 100 IRE
GAINU= 0
Output subcarrier of U contribution = 0
GAINU=125 (7Dh)
Output subcarrier ofU contribution = nominal
. GAINU = -2.05
* nominal ... nominal ... 2.04 * nominal
Subaddress 5C, 5E:
GAINV
Variable gain for Cr signal (Input Representation acc. to CCIR 601)
White - Black = 92.5 IRE
GAINV= 0
Output subcarrier of V contribution = 0
GAINV=165 (A5h) Output subcarrier of V contribution = nominal
GAINV = -1.55
* nominal ... nominal ... 1.55 * nominal
\\fhite-Black = 100 IRE
GAINV= 0
Output subcarrier of V contribution = 0
GAINV=175 (AFh) Output subcarrier of V contribution = nominal
GAINV = -1.46
* nominal ... nominal ... 1.46 * nominal
Subaddress 5D:
BLCKL
Variable Black Level (Input Representation acc. to CCIR 601)
White - Sync = 140 IRE
BLCKL= 0
Output Black Level
= 24 IRE
BLCKL= 63 (3Ph) Output Black Level = 49 IRE
Output Black LevellIRE = BLCKL * 25/63 + 24
Recommended Value:
BLCKL = 60 (3Ch) (normal)
White-Sync = 143 IRE
BLCKL= 0
Output Black Level = 24 IRE
BLCKL= 63 (3Ph) Output Black Level = 50 IRE
Output Black Level/lRE = BLCKL * 26/63 + 24
Recommended Value:
May 1994
BLCKL = 45 (2Dh) (normal)
3-370
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-M)
SAA7188A
Subaddress 5E:
Variable Blanking Level
BLNNL
White - Sync = 140 IRE
BLNNL= 0
Output Blanking Level = 17 IRE
BLNNL= 63 (3Fh) Output Blanking Level = 42 IRE
Output Blanking LevelJIRE = BLNNL * 25/63 + 17
Recommended Value:
BLNNL = 58 (3Ah) (normal)
White - Sync = 143 IRE
BLNNL= 0
Output Blanking Level = 17 IRE
BLNNL= 63 (3Fh) Output Blanking Level = 43 IRE
Output Blanking LevelJIRE = BLNNL * 26/63 + 17
Recommended Value:
BLNNL = 63 (3Fh) (normal)
Subaddress 60:
Select cross colour reduction filter in luminance
CCRS
CCRSI
CCRSO
function
0
No Cross Colour Reduction (for overall transfer characteristic of luminance see fig. 5)
0
1
Cross Colour Reduction #1 active (for overall transfer characteristic see fig. 5)
1
0
Cross Colour Reduction #2 active (for overall transfer characteristic see fig. 5)
1
1
Cross Colour Reduction #3 active (for overall transfer characteristic see fig. 5)
0
Subaddress 61:
FISE
0 864 total pixel clocks per line
PAL
SCBW
RTCE
1
858 total pixel clocks per line (default after reset)
0
NTSC Encoding (non-alternating V-component) (default after reset)
1
PAL Encoding (alternating V-component)
0
Enlarged Bandwidth for Chrominance Encoding (for overall transfer characteristic of chrominance in base-band representation see figs. 3 and 4).
1
Standard Bandwidth for Chrominance Encoding (for overall transfer characteristic of chrominance in base-band representation see figs. 3 and 4). (default after reset)
0
No Real Time Control of generated Subcarrier Frequency (default after reset)
1 Real Time Control of generated Subcarrier Frequency through SAA7151B (timing see fig. 9)
YGS
0
Luminance Gain for White-Black 100 IRE
1 Luminance Gain for White-Black 92.5 IRE incl. 7.5 IRE Set-up of Black (default after reset)
INPI
0
PAL Switch phase is nominal (default after reset)
1
PAL Switch phase is inverted compared to nominal
DOWN
0
DACs in normal operational mode (default after reset)
1
DACs forced to lowest output voltage
May 1994
3-371
Preliminary specification
Philips Semiconductor Video Products
Digital video encoder (DENC2-M)
SAA7188A
Subaddress 62:
Amplitude of Colour Burst (Input Representation acc. to CCIR 601)
BSTA
White-Black =92.5 IRE, Burst =40 IRE, NTSC-Encoding
BSTA =0 .. 1.25
* nominal
Recommended Value: BSTA = 102(66h)
White-Black =92.5 IRE, Burst =40 IRE, PAL-Encoding
BSTA =0 .. 1.76
* nominal
Recommended Value:
BSTA =72(48h)
White-Black = 100 IRE, Burst =43 IRE, NTSC-Encoding
BSTA =0 .. 1.20
* nominal
Recommended Value: BSTA = 106(6Ah)
White-Black = 100 IRE, Burst =43 IRE, PAL-Encoding
BSTA =0 .. 1.67
* nominal
Recommended Value: BSTA =75(4Bh)
SQP
0
Subcarrier Real Time Control from 7151B Digital Colour Decoder
I
not supported in current version, do not use.
Note to subaddresses 5B,5C,5D,5E,62: All IRE values are rounded
Subaddress 63 .. 66:
Four bytes to program subcarrier frequency
FSCO
...
FSC3
F(fsc)
32
FSC = round(F(llc) x2 )
F(Jsc)
Subcarrier frequency (in multiples of line frequency)
F(llc)
Clock frequency (in multiples of line frequency)
FSC3
Most significant byte
FSCO
Least significant byte
Examples:
NTSC-M: F(Jsc) =227.5, F(llc)
= 1716 ==>
PAL-BIG: F(Jsc) =283.7516 , F(llc) = 1728 ==>
. FSC =569408543 (21F07CIFh)
FSC =705268427 (2A098ACBh)
Subaddress 67 .. 6A:
L210D2
First Byte of Captioning Data, Odd Field
L210D3
Second Byte of Captioning Data, Odd Field
L2IEDO
First Byte of Extended Data, Even Field
L2IEDI
Second Byte of Extended Data, Even Field
LSBs of the respective bytes are encoded immediately after run"-in and framing
code; the MSBs of the respective bytes have to carry the parity bit, acc. to
the definition of line 21 encoding format.
May 1994
3-372
Preliminary specification
Philips Semiconductor Video Products
Digital video encoder (DENC2-M)
SAA7188A
Subaddress 6B
Selects the actual line, where Closed Caption or Extended Data are encoded.
SCCLN
Line = (SCCLN + 4) for M-systems
Line = (SCCLN + 1) for other systems
Defines video data of MP port or VP(DP) port to be encoded
MODIN
MODINI
MODINO
0
0
unconditionally from MP port
0
1
from MP port, if pin SEL_ED=high, else from VP port
1
0
unconditionally from VP port
1
1
from VP port, if pin SEL_ED=high, else from MP port
Sub address 6C:
PRCV2
0 Polarity of RCV2 as output is high-active, rising edge is taken when input, respectively (default after reset).
ORCV2
CBLF
1
Polarity of RCV2 as output is low-active, falling edge is taken when input, respectively
0
Pin RCV2 is switched to input (default after reset).
1
Pin RCV2 is switched to output
0 If ORCV2=high, pin RCV2 provides a HREF signal (Horizontal Reference Pulse that is high during active
portion of line, also during Vertical Blanking Interval). (default after reset)
If ORCV2=low, signal input to RCV2 is used for horizontal synchronization only (if TRCV2 = 1). (default
after reset)
1
PRCVl
ORCVl
TRCV2
SRCVl
If ORCV2=high, pin RCV2 provides a CBN signal (Reference Pulse that is high during active video, excluding Vertical Blanking Interval).
If ORCV2=low, signal input to RCV2 is used for horizontal synchronization (if TRCV2 = 1)as well as an internal blanking signal
0
Polarity of RCVl as output is high-active, rising edge is taken when input, respectively. (default after reset)
1
Polarity of RCVl as output is low-active, falling edge is taken when input, respectively.
0
Pin RCVl is switched to input (default after reset).
1
Pin RCVl is switched to output.
0
Horizontal synchronization is taken from RCVl port. (default after reset)
1
Horizontal synchronization is taken from RCV2 port.
Defines signal type on pin RCVl
SRCVll
May 1994
SRCVlO as output as input
0
0
VS
VS
Vertical Sync each field (default after reset)
0
1
FS
FS
Frame Sync Lodd/even)
1
0
FSEQ
FSEQ
Field SEQuence, Vertical sync every fourth (FISE=l) or
eighth field (FISE=O)
1
1
n.a.
n.a.
3-373
Preliminary specification
Philips Semiconductor Video Products
Digital video encoder (DENC2-M)
SAA7188A
Subaddress 6D:
Enables individual Line 21 Encoding
CCEN
CCENI
0
CCENO
0
Line 21 Encoding OFF
0
1
Enables Encoding in field 1 (odd)
1
0
Enables Encoding in field 2 (even)
1
1
Enables Encoding in both fields
Defines signal type on pin RCMl
SRCM
SRCMl
SRCMO
as output
0
0
VS
Vertical Sync each field
0
I
FS
Frame Sync Lodd/even)
1
0
FESQ
1
1
n.a.
Field SEQuence, Vertical sync every fourth (FISE=I) or
eight field (FISE=O)
Subaddress 6E .• 6F:
HTRIG
Sets the Horizontal TRIGger phase related to signal on RCVl or RCV2 input.
Values above 1715 (FISE=I) or 1727 [FISE=O] are not allowed.
Increasing HTRIG decreases delays of all internally generated timing signals.
Reference mark: Analog output horizontal sync (leading slope) coincides with active edge of RCV used
for triggering at HTRIG = 032h [032h]
Subaddress 70·
VTRIG
Sets the Vertical TRIGger phase related to signal on RCVl input.
Increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines
Variation range of VTRIG = 0 .. 31(1Fh)
SBLBN
0
Vertical Blanking is defined by programming of FAL and LAL .
1
Vertical Blanking is forced automatically at least during field synchronization and equalization pulses.
Note: If Cross-Colour Reduction is programmed, it is active between FAL and LAL in both cases.
PHRES
Selects the phase reset mode of the colour subcarrier generator
..
May 1994
PHRESl
PHRESO
0
0
0
1
reset every two lines
1
0
reset every eight fields
1
1
reset every four fields
. no reset
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-M)
SAA7188A
Subaddress 71 ;. 73:
BMRQ
Begin of MP ReQuest signal (RCM2).
Values above 1715 (FISE=I) or 1727 [FISE=O] are not allowed.
First active pixel at analog outputs (corresp. input pixel coinciding with RCM2) at BMRQ=OF9h [115h]
EMRQ
End of MP ReQuest signal (RCM2).
Values above 1715 (FISE=I) or 1727 [FISE=O] are not allowed.
Last active pixel at analog outputs (corresp. input pixel coinciding with RCM2) at EMRQ=686h [690h]
Subaddress 77 •. 79:
BRCV
Begin of output signal on RCV2 pin.
Values above 1715 (FISE=I) or 1727 [FISE=O] are not allowed.
First active pixel
ERCV
at analog outputs (corresp. input pixel coinciding with RCV2) at BRCV=OF9h [115h]
End of output signal on RCV2 pin.
Values above 1715 (FISE=l) or 1727 [FISE=O] are not allowed.
Last active pixel
at analog outputs (corresp. input pixel coinciding with RCV2) at ERCV=686h [690h]
Subaddress 7A .. 7D:
FLEN
LENgth of a Field = FLEN + 1, measured in ha1flines
FAL
First Active Line after vertical blanking interval = FAL + 1, measured in lines.
LAL
Last Active Line before vertical blanking interval = LAL + 1, measured in lines
Valid range is limited to 524 .. 1022 (FISE= 1) resp. 624 .. 1022 (FISE=O), FLEN should be even
FAL=O coincides with the first field synchronization pulse.
LAL=O coincides with the first field synchronization pulse.
May 1994
3-375
Preliminary specification
Philips Semiconductor Video Products
SAA7188A
Digital video encoder (DENC2-M)
Slave Transmitter
Slave Transmitter [Slave Address 89h or 8Dh]
REGISTER
FUNCTION
Status Byte
SUB- DATA BYTE
ADDR D7
D6
-
VER2
VERI
D5
D4
D3
D2
Dl
DO
VERO
CCRDE
CCRDO
FSQ2
FSQ1
FSQO
no subaddress
VER
CCRDE
Version id of the device. It will be changed with all versions of the IC that have different programming models
Current Version is 011 bin.
Closed caption bytes of the even field have heenencoded.
The bit is reset after information has been written to the subbaddresses 69,6A. It is set immediately after
the data have been encoded.
CCRDO
Closed caption bytes of the odd field have heen encoded.
The bit is reset after information has been written to the subbaddresses 67,68. It is set immediately after
the data have been encoded.
FSQ
State of the internal field sequence counter.
Bit 0 (FSQO) gives the odd/even information. (Odd=Low, Even=High)
May 1994
3-376
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-M)
SAA7188A
+--r---t
6~~~i~i----~I~!----~I~I~!----~~~-'----~
o
---r--r-r-1-1
.
I
!
,--i-
-6 -I--I--'1rl'",=--+
LJ
-12
I
---f
1
!
!
-18
-24
-30
-36
-42 -I----!--+--+-'
-48
-S4~-+~+-~~4-~~~~--~~--~~~-r~~
1
2
3
4
5
6
7
8
9
10 11 12 13
f(MHz)
Fig. 3 : Chrominance transfer characteristic
o
I
i
I
-1
-2
+-..SC8W-0 - : -
i i i
--r----..i 1
I
r---.J
I
I
Ii!
·----1·---I---i
!
+---'---r-' ~.~.::~t-I
-4
1
iii
·---t-----i-----i----t~~ ~r-----t--·
I
! "" I
I
I
!
I
I
I
~
·-----r--- 1----I-·--T---T-----r----I-----t-+--J---+----t------r--t--I
I
I
-3
i
.!-__ ........,.-..-....... ;, ···---!-----i···---scaW-l-.
.11
!
!
!
-5
I
I
!
I
,
I
i
I
!
I
I!
I ..
I
.1_
I
I
-6~--~----r_---+----;---~----~----+-~
0.2
0.4
0.6
0.8
1
1.2
f (MHz)
Fig. 4 : Chrominance transfer characteristic
May 1994
3-377
1.4
Philips Semiconductor Video Products
, Preliminary specification
Digital video encoder (DENC2-M)
6
I I
I~ "
0
-12
~
tJI
i
111~;q~~.~~-ll-
iI
...-.--ct-L~~;~.!-,
17R~ ICC :Sl- ,qCRSP-O:-
I'
~
.'
CCJ~~~..t~~B.$.b-11_....
'£ '/~~CT1-p, qCRSD-olI
I
1~ 1j
I
1\ I I
11 1
I I i
I
1
1 'H- '1
i
I
!
\
I
I
l,-.l
I I
i
-'
I !
I. I'\[ !
i
i
I
I d i .i\ i
!
·r I I I
I
I' ~:!!(I.I "\l!
1 2 3 4 5 6 7 8 9 10 11 12 13
-6
....IIIc
SAA7188A
I
,I
1
-18
·11
-24
I
-30
I
I
i
1
!
!
i
I
-36
I
I
I
I.
-42
I
!
I
I
I
-48
:
!
I
!
-54
i
\ i
.' -.
!
I
f(MHz)
'Fig. 5 : Luminance transfer characteristic
0.5
-0.5
I
~c
....III
;
tJI
I
I
-2
I
I
I
I
-1
-1.5
T
I'
0
I
I
I
I
-3
~,..l
_. 'C:1 -
I
I
I
I
I
I
!
I
!
!
I I i
i
I
-2.5
I
.
!
i
I
I
'.
cbR,lsd-o
I
~I
II I1,,1r\
I
I
i
!
I
-3.5
I
!
i
\1
'\
,
1\
I\
I1
-4.5
0.5
!
1 1.5 2
3
3.5
4
4.5
Fig.6 : Luminance transfer characteristic
3-378
I
I
1
2.5
f(MHz)
May 1994
I
I
-4
-5
i
-r--
!
5
5.5
6
Preliminary specification
Philips Semiconductor Video Products
SAA7188A
Digital video encoder (DENC2-M)
Electrical Characteristics
Conditions: Tamb =0 .. 70 °C; V DDD=4.5 .. 5.5 V unless otherwise specified.
SYMBOL
TEST
CONDITIONS
PARAMETER
LIMITS
UNIT
MIN
MAX
4.5
5.5
4.75
5.25
V
-
170
rnA
55
rnA
Supply
V DDD
supply voltage range digital
V DDA
supply voltage range analog
IDDD
supply current
1)
IDDA
supply current
1)
V
Inputs
V rL
input voltage LOW (except LLC, SDA, SCL, AP, SP,
XTALI)
-0.5
0.8
V
V lH
input voltage HIGH (except LLC, SDA, SCL, AP, SP,
XTALI)
2.0
V DDD+O.5
V
V lH
input voltage HIGH (LLC pin 38)
2.4
V DDD +0.5
,v
-
1
/J.A
-
10
pF
data
8
pF
input capacitance
110 at high
impedance
8
pF
VOL
output voltage LOW (except XTAL, SDA)
2)
0
0.6
V
V OH
output voltage HIGH (except LLC, XTAL,DTACKN,
SDA)
2)
2.4
V DDD+0.5
V
V OH
output voltage HIGH (LLC pin 38)
2)
2.6
V DDD +0.5
V
ILl
input leakage current
Cr
input capacitance
clocks
Cr
input capacitance
Cr
Outputs
I 2 C Bus SDA and SCL
V rL
input voltage LOW
-0.5
1.5
V
VlH
input voltage HIGH
3.0
V DDD+0.5
V
Ir
input current
V r= low or high
+/-10
IJ.A
VOL
SDA output voltage
10=3 rnA
10
output current
during acknowl.
0.4
3
V
rnA
Clock timing
tLLC
cycle time LLC
3)
34
41
0
duty factor tLLCh / tLLC
10)
40
60
%
tr
rise time LLC
3)
-
5
ns
tf
fall time LLC
3)
-
6
ns
ns
Input timing
tsuc
input data setup time (CREF)
6
-
ns
tHDC
input data hold time (CREF)
3
-
ns
May 1994
3-379
Preliminary specification
Philips Semiconductor Video Products
SAA7188A
Digital video encoder (DENC2-M)
TEST
CONDITIONS
PARAMETER
SYMBOL
LIMITS
UNIT
MIN
MAX
tsu
input data setup time (any other exceptSEL_MPU, CDIR,
RWN/SCL, AOISDA, CSN/SA, RESN, AP, SP)
6
-
ns
tHO
input data hold time (any other except SEL_MPU, CDIR,
RWN/SCL, AOISDA, CSN/SA, RESN, AP, SP)
3
-
ns
MHz
10-0
Crystal Oscillator
-
30
-50
+50
temperature range Tamb
0
70
C
load capacitance CL
8
-
pF
fn
nominal frequency (usually 27 MHz)
3rd harmonic
Df/fn
permissable deviation fn
9)
crystal specification:
80
n
motional capacitance C 1 .
typically
1.5-20%
1.5+20%
fF
parallel capacitance Co
typically
3.5-20%
3.5+20%
pF
9
-
ns
0
-
ns
9
-
ns
0
-
ns
-
400
ns
255
ns
series resonance resistance Rs
MPU interface timing
tAS
address setup time
tAH
address hold time
tRWS
read/write setup time
tRWH
read/write hold time
5)
5)
too
data valid from CSN (read)
6), 7), 8), n=9
tOF
data bus floating from CSN (read)
6),7), n=5
tos
data bus setup time (write)
5)
9
-
ns
tOH
data bus hold time (write)
5)
9
-
ns
tACS
acknowledge delay from CSN
6),7), n=11
-
475
ns
tcso
CSN high from acknowledge
0
-
ns
tOAT
DTACKN floating from CSN high
-
330
ns
pF
6),7), n=7
Data and reference signal output timing
CL
output load capacitance
7.5
40
tOH
output hold time
4
-
ns
too
output delay time (CREF in output mode)
-
25
ns
C, Y, and CVBS outputs
4)
Vo
output signal (peak to peak value)
1.9
2.1
V
RI
internal serial resistance
18
35
RL
output load resistance
80
-
n
n
B
output signal bandwidth (D/A-convertors)
10
-
MHz
ILE
LF integral linearity error (D/A-convertors)
-
±2
LSB
DLE
LF differential linearity error (DIA-convertors)
-
±1
LSB
May 1994
-3dB
3-380
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-M)
SAA7188A
Notes:
1)
At maximum supply voltage with highly active input signals.
2)
The levels have to be measured with load circuits of 1.2 ill to 3.0 V (standard TTL load), CL = 25pF.
3)
The data is for both, input and output direction.
4)
for full digital range, without load, V OOA = 5.0 V. The typical voltage swing is 2.0 V, the typical minimum output voltage (digital zero at DAC) is 0.2 V.
5)
The value is calculated via equation (1)
6)
The value depends on the clock frequency. The numbers given are calculated with fLLC = 27 MHz
7)
The values are calculated via equation (2)
8)
The falling edge of DTACKN will always occur 1 * LLC after data is valid.
9)
If internal oscillator is used, crystal deviation of fn is directly proportional to the deviation of subcarrier frequency and
linel field frequency.
10)
With LLC in input mode. In output mode, with a crystal connected to XTALI XTALI typically 50 %.
Equations:
(1)
t=tSU+tHO
(2)
tdmax =
too + n*tLLC + tLLC + tsu
......
Jt
-;
ClockLLC-out
~
--
...
tsu
)t
InputData
1\
.
...
IF
1\1\
... tr-4-
~
~
...
~ V_al_hl_~~
____
valid
not valid
valid
too
_ _ _ _ _n_o_t_w_l_hl_ _ _
....
3-381
- 2.0V
-
0.8V
~ ~_~_v_a_li_d =~~
__
Fig. 7 : Clock Data Timing
May 1994
2.4V
1.5V
0.8V
j
. . . . tr-4-
~to~
OU• •
2.6V
1.5V
0.6V
... tr-4-
tr~
~
~tHlr~
V
)
tLLC
tLLCh
-r£
7-
....
I)
1\"
~tHlr~
ClockLLC-in
..
.
LLC
tLLCh
____
Preliminary specification
Philips Semiconductor. Video Products
Digital video encoder (DENC2-M)
SAA7188A
VP(n)
X
Y(O)
X
Y(l)
X
Y(2)
X
Y(3)
X
Y(4)
DP(n)
X
Cb(O)
X
Cr(O)
X
Cb(2)
X
Cr(2)
X
Cb(4)
RCV2
/
Fig.8: Dig.TV - Timing
Notes:
1)
The data demultiplex phase is coupled to the internal horizontal phase.
2)
The CREF signal applies only for the 16 lines DIG-TV format, because these signals are only valid in 13.5 MHz.
3)
The phase of the RCV2 signal is programmed to OF9h [ 115h for 50 Hz ] in this example in output mode (BRCV2)
HIL transition
count start
1~128
4 bits
reserved
HPLL
increment
FSCPLL increment
RTCI~
t t
not used in DENC2-M
valid invalid
sample sample
(1) sequence bit:
PAL: 0: (R-Y) line normal
1 : (R-Y) line inverted
NTSC: 0: (no change)
(2) resrved bits: 236 with 50Hz sysyems; 233 with 60Hz systems
Fig.9 : RTCI timing
May 1994
3-382
Philips Semiconductor Video Products
Preliminary specification
Digital video encoder (DENC2-M)
AO
SAA7188A
---~-t-AS-~---------~--t-AAK------
CSN
RWN
0(7 ..0 ) - - - - - - - + - - - <
OTACKN
Fig.tO: MPU Interface Timing (Read cycle)
AO
~
~
)
K
tRws
~
~
tos
~
~
tRWH
~
}
~
OTACKN
tAH
f
~
0(7 .. 0 )
~
\
CSN
RWN
~
tAs
tOH
\
~
)
. . . . - tACS--.. ... tcso~ .....- tOAT ~
Fig.l1 : MPU Interface Timing (Write cycle)
May 1994
3-383
-0
~
~
co
co
.,..
=:=
=~
0.1J.LF Dgnd
H
riQ"
0.1J.1F Dgnd
HI--+
3rdOvert.
~
N
>
XTALI
XTAL V DDD V DDD V DDD
41
40
H>
-
'tS
"e.
;:;"
=
eo
e
17
37
67
~H~
15K!)
Agnd 0.1J.LF
0.1J.LF Agnd
Agnd 0.1J.LF
0.1J.LF Agnd
Hl
:H'
Xl
27.0MHz
~
=
tJ:j
=
<
::;"
8=
...=
==
VDD~~Vrem
48
/47
4
CUR VDDA V DDA
55
54
~
:::J
C.
c::
!l
Q
=s;
0
8.c::
CD
-
0
-0
!l
rn
""""
0
m
VDDA
48
z
0
I\)
I
-
s:
1Qg 0.62V(p-p)2
'---"
·C
-49
..-........
3
c')"
0
c.
(1)
a.
HH
~_~I
- I
DAC3
(]750
L-
~
:r
50
rn
CD
:J
(')
!H
Q
s,
0
0.1 J.LF Agnd
:H~
lOpF IOpF
InF
.,..
en
(1)
c:
CD
0.1J.LF Dgnd
W
;:::::t:
-Ol<
+5Vanalog
+5V digital
lO~H
c..>
~
-s.
cC'
.=!f=.Dgnd
CD
0
- I
rtf-
DAC2
Digital
SAA7188A
~
in . . and
outputs
lml
~ 1.0V(p-p)2
"'y
51
n
N
- I
~
DACI
a:
1,8, 19,28,
35,42,62
Vss
Xl : Philips 431206502341
--
-~-
-
~Dgnd
46
VretL
~Agnd
~
I
........Agnd
3501
53
1m
j
1.23V(p-p):
..-........
i
I
[]750
~~
t:='
tJ:j
Z
-~-
......F·Agnd
CVBSj
[]750
i
52
.....Agnd
I
~ Agnd (1) : typIC
. a1 I
va ue
(2) : for 1001100 color bar
-0
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I
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-
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SAA7191B
"0
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(Q
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i
test pins
c:
o
o
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en CJ
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_.
a
n
00
"0
8.
C
~
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............ c:
CV S7to
CV SSO
14to 17
20 to 23
--p
INPUT
INTERFACE
w
CH R7to
C -iRO
~
65
GP SjV1
24
GP SW2
25
PORTANO
STATUS
REGISTER
40
:
41
12 C-BUS
CONTROL
i43
RESN
...
LUMINANCE
PROCESSOR
Y output
(Y 7toYO)
U1 output
(U V7toUVO)
..........
I
3
37
...
~
I
~
~
SYNCHRONIZATION
\26
t
HCL
\29
t
HSY
30
t
VS
\31
t
HS
~L
\36
t
LFCO
\39
oto
...
j4
CJEF
CD
FEIN
+5V
VOOA
~
~
33
CLOCK
~
\32
35
o
a.
FEON
status
l'"
CD
n
HREF
64
clock
"""
a.
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63
i
GP SWO
IICSA
55 to 62
OUTPUT
INTERFACE
6 to 13
co
SOA
45 to 50, 53, 54
42
W
co
...
r-r--
CHROMINANCE PROCESSOR
VSSA
XTAL
XTAU
34
j27
L~C
MEH435
Fig.1 Block diagram.
"0
~
(f)
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~
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£cr.
g
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder,
square pixel (DMSD-SQP)
SAA7191B
6. PINNING
SYMBOL
PIN
DESCRIPTION
SP
1
connected to ground (shift pin for testing)
AP
2
connected to ground (action pin for testing)
RESN
3
reset, active LOW
CREF
4
clock reference, sync from external to ensure in-phase signals on the YUV-bus
VO O1
5
+5 V supply input 1
CHRO
6
CHR1
7
CHR2
8
CHR3
9
CHR4
10
CHR5
11
CHR6
12
CHR7
13
CVBSO
14
CVBS1
15
CVBS2
16
CVBS3
17
chrominance input data bits CHR7 to CHRO
from a Y/C (VHS, Hi8) source in two's complement format
luminance respectively CVBS lower input data bits CVBS3 to CVBSO
(CVBS with luminance, chrominance and all sync information in two's complement format)
V OO2
18
+5 V supply input 2
VS S1
19
ground 1 (0 V)
CVBS4
20
CVBS5
21
CVBS6
22
CVBS7
23
luminance respectively CVBS upper input data bits CVBS7 to CVBS4
(CVBS with luminance, chrominance and all sync information in two's complement format)
GPSW1
24
Port 1 output for general purpose (programmable)
GPSW2
25
Port 2 output for general purpose (programmable)
HCL
26
black level clamp pulse (programmable), e.g. for TDA8708 (ADC)
LLC
27
line-locked clock input signal (29.5 MHz for 50 Hz system; 24.5454 MHz for 60 Hz system)
VOO3
28
+5 V supply input 3
HSY
29
horizontal sync indicator output signal (programmable), e.g. for TDA8708 (ADC)
VS
30
vertical sync output signal
HS
31
horizontal sync output signal (programmable)
HL
32
horizontal lock flag, HIGH = PLL locked
XTAL
33
26.8 MHz clock output
XTALI
34
26.8 MHz connection for crystal or external oscillator (TTL compatible squarewave)
April 1993
3-389
Philips SemiconductorsVideo Products
Preliminary specification
Digital multistandard colour decoder,
square pixel (DMSD-SQP)
SAA7191B
SYMBOL
PIN
DESCRIPTION
VSSA
LFCO
35
analog ground
36
line frequency control output signal, multiple of horizontal frequency (7.375 MHzl6.136363 MHz)
VOOA
37
+5 V supply input for analog part
VSS2
38
ground 2 (0 V)
ODD
39
odd/even field identification output (odd = HIGH); active only at NFEN-bit = 1
SDA
40
12C-bus data line
SCL
41
12C-bus clock line
HREF
42
horizontal reference output for valid YUV data (for active line 768Y or 640Y samples long)
IICSA
43
set module address input (LOW = 1000 101 X; HIGH = 1000 111 X)
i.c.
44
internally connected
Y7
45
Y6
46
Y5
47
Y4
48
Y3
49
Y2
50
VSS3
51
ground 3 (0 V)
VOO4
Y1
52
+5 V supply input 4
YO
54
UV7
55
53
UV6
56
UV5
57
UV4
58
UV3
59
UV2
60
Y signal output bits Y7 to Y2 (luminance), part of the digital YUV-bus
Y signal output bits Y1 to YO (luminance), part of the digital YUV-bus
UV signal output bits UV7 to UVO
(colour~difference),
part of the digital YUV-bus
UV1
61
UVO
62
FEON
63
output active flag (active LOW when Yand UV data in high-impedance state)
fast 'enable input (active LOW to control fast switching due to YUV data)
FEIN
64
GPSWO
65
PUN
66
VSS4
RTCO
67
ground 4 (0 V)
68
real-time control output active at NFEN-bit = 1; Fig.7
April 1993
Port 0 output for general purpose (programmable); active only at NFEN-bit = 1
. PAL flag (active LOW at inverted line); SECAM flag (LOW equals DR, HIGH equals DB line)
3-390
Preliminary specification
Philips Semiconductors Video Products
Digital multistandard colour decoder,
square pixel (DMSD-SQP)
SAA7191B
PIN CONFIGURATION
UV1
IICSA
UVO
HAEF
FEON
SCl
FEIN
SDA
GPSWO
ODD
PUN
V SS2
V OOA
ATCO
lFCO
SAA71918
V SSA
XTAU
XTAl
Hl
HS
VS
HSY
V003
llC
Cf
:c
~
:c
£
:c
000
MEH436
Fig.2 Pin configuration.
7. FUNCTIONAL DESCRIPTION
Chrominance processor
The 8-bit chrominance input signal .
(CVBS or chrominance format).
passes a bandpass filter to eliminate
DC components and to decimate the
sample rate before it is fed to the two
multipliers (quadrature demodulator),
Fig.3(a).
Two subcarrier signals from a local
oscillator (0 and 90 degree) are fed
to the multiplicator inputs of the
multipliers. The multipliers operate
as a quadrature demodulator for all
April 1993
PAL and NTSC signals; it operates
as a frequency down-mixer for
SECAM signals.
The two multiplier output signals are
converted to a serial data stream and
applied to three low-pass filter
stages, then to a gain controlled
amplifier. A final multiplexed
low-pass filter achieves, together
with the preceding stages, the
required bandwidth performance.
The signals, originated from PAL and
NTSC, are applied to a comb-filter.
The signals, originated from SECAM,
are fed through a Cloche filter (0 Hz
3-391
centre frequency), a phase
demodulator and a differentiator to
obtain frequency-demodulated
colour-difference signals.
The SECAM signals are fed after
de-emphasis to a cross-over switch,
to provide the both serial-transmitted
colour-difference signals. These
signals are fed finally to the output
formatter stages and to the output
interface.
~
000
~
-"
c
<0
W
HRMV
SCEN
OEVS
OEHS
FISE
I
HSYS (7-0)
UDUIt7_n\
XTAL
HLCK
STTC
XTALI
SAA7191B
SYNC
SCL
FISE
COUNTER
SDA
FIDT
IICSA
65,24,25
26
29
30
31
32
39
Nt-eN
"'tl
136
(J)
GPSW(2-O)
HCL HSY
VS
HS
HL
ODD
LFCO
MEH438"l
Fig.3(b) Detailed block diagram; continued from Fig.3(a).
»
»-.....I
....
....
CO
OJ
!i
3"
:r
I»
---
bU----,rst
HCL
programming
range
+ 127
(ste~t~~)
r ___
~.-------------+!~.
::
(ste~t~~)
62 x 2JlLC
SAA71918
--~-~~~i+f------- 176x2Jl~------------~~~:f~-
------------~~--.;..l----------'X'----------t--
i~
38 x 21LLC i.---
100 x 2JlLC
---.1
~i:
HS(50 Hz)
-----------------~:
+117
64 x2JlLC
,if
,:
:0:
-118
~1----~lOJ(L-~i~---~:----------------~~
:38x2lLLC!
~I~--~--------~r---
HREF (60 Hz)
- - - - 640 x 2JlLC
---+'---~~:"4------,
140 x2JlLC
----------I~~:f~-
HS (60 Hz)
64 x 21LLC
+97
:0
-97
I~----;.»~"--+!~~-------------------~~
MEH226·2
Fig.12 Horizontal sync at HRMV = 0 and HRFS = 0 for 50/60 Hz
(signals HSY, Hel, HREF and PLlN).
April 1993
3"404
»
(/)0
"0
~
co
co
digital
eN
signal source selected by GPSW1-bit (lOW. source 1)
In+
IU
~
-
~
In+
IU
digital U
,n+
IU
~
In+
~
17
12
18
11 I CVBS2
~
O.~,jlF
\p,F
I
VOOA
"
TDA8708A
22
7
23
6
In+
IU
;--
HSY
,1Q.Q
o.......J
HCl
5
25
4~
26
3 I CVBS3
27
2 I CVBS2
28
CVBS7
n
1
V (analog supply)
+5
V (digital supply)
to
9
21
8
TDA8709A
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I
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2~
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~
180
120
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analog
[) 5 6
0
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7
23
6 Vooo
1
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25
4 I CHR4
26
3 I CHR5
r - 27
2 I CHR6
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n
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eng.
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5
0·1l1lF
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en
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24
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cr
o
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0.1
.~jlF
CHRO
CHRO
10 I CHR3
O.lj1F
Vooo
24
11
20
r---+-
~
28
Q
1 I CHR7
l}kO
.......
CV BS7
Ito
CV BSO
]5.60
llCA
+5
12
CHR7
I~ 0.11lF
VoOO
ClK
lit.
+UI
VooA
:u
10jlF
~~ analog
2.2kO
10 I CVBS3
19
21
+UI
O.~~IlF
5.60!
1
[
20
"
I CVBS1
IU
~
U1
17
19
13 I CVBSO
16
11l F
Y or CVBS VI. source 2
~
13
18
6~0
14
11l F
Y or CVBS VI. source 1
2.2 kO )
16
11l F
' - - 15
cp
14
11lF
chrominance Vj. source 1
chromillance VI, source 2
15
t~
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s:u;::::;:
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co-
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r
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en
M H4.3
»
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~
Fig.13· Application circuit for analog-to-digital conversions.
(0
~
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~
~f
5·
I»
---:::2 ::--.......
,~
"53h
b ~--- -.""'"
1'/ ........ ~
----
IfA
1/
"" 73h
63h
-12
-18
~
-50Hz
-24
-30
o
2
4
6
fy(MHz)
Fig.16 Luminance control in 50Hz / CVBS mode controllable by subaddress byte 06; pre-filter on and
coring off; maximum aperture bandpass filter characteristic.
MSH215
18
62h '\
61h"
12
Vy
(dB)
6
0
-
~
~~
x---:::
...-
-'"
1/42h
.... ~
-.... ~~
~
41h/
.........
40h
-6
f\..'
42h,
'"
~A' ~\
\,~
\~
\
-12
41h '\. ~- ~
62h" ~
.....
i-
/~ ~
/171
VI
I' 61h
40h
50 Hz
-18
-24
-30
o
2
6
4
fy(MHz)
Fig.17 Luminance control in 50 Hz / CVBS mode controllable by subaddress byte 06; pre-filter on and
coring off; other aperture bandpass filter characteristics.
April 1993
3-413
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder,
square pixel (DMSD-SQP)
SAA7191B
MSH216
18
23h,
12
~
Vy
(dB)
~ V"
6
~
33h
.,--
----- -
~-- V- A
~~
~
0
~
'7
-..... r--.....
13h /
-6
03h
. . . . 1">-..
........
DOh /
~
13h,
",
-12
1 VI
\
50 Hz
-24
-30
o
\
~h
f/Jj ~23h
\\
\
-18
iV
// / '
~
"\.
~~
03h,
/
/
\ I
I
~
~
/
' DOh
\
4
2
6
fy(MHz)
Fig.18 Luminance control in 50 Hz / eVBS mode controllable by subaddress byte 06; pre-filter off and
coring off; maximum aperture bandpass filter characteristic.
18
73h"
~
12
(dB)
Y
V::::r-
~
$.. ~ ~
63h
Vy
6
~
~
....
- ,
MSH217
I--
....
--.,
~
\.
\
43h
--
43h,
~
i'- 53h
c----..
, II
\
63h
r
-6
53h
~ ~ t-....
J~
~
///'
-~ ~
~
73h ....
-12
60 Hz
-18
-24
-30
o
4
2
6
5
fy(MHz)
Fig.19 Luminance control in 60 Hz / eVBS mode controllable by subaddress byte 06; pre-filter on and
coring off; maximum aperture bandpass filter characteristic.
April 1993
3-414
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder,
square pixel (DMSD-SQP)
SAA71918
MSH218
18
61h,.
12
62h,
Vy
(dB)
. / ~ 1-
~~
~ io-"""'"
6
41h'
...........
r-.... 42h
... ~
-...... t>..~1\.
"
50h/
0
-6
62h "-
i\.~
\',
fII,
"'"
~
v
~
......
-- ::--....
~
~
--.....
50h
f/
-12
-18
I' 42h
43h "-
~'-
61h
60 Hz
-24
-30
o
4
2
6
5
fy(MHz)
Fig.20 Luminance control in 60 Hz / CVBS mode controllable by subaddress byte 06; pre-filter on and
coring off; other aperture bandpass filter characteristics.
MSH219
18
I' 33h
12
23h",
Vy
(dB)
#
6
~
'13h'::.,
-
A ~~
0
r---
~
.---............
~
~
03h
r-.....
-6
"" .....
OOh/
-12
03h
\
"-
\
-24
-30
o
,
\
1
~
60 Hz
-18
/P--- ~
~
2
\
13h
/ / /33h- ~......
V/,
I. 1/
--- --
~
~
III " 23h ~
rv /' 'OOh
/
I
\
I
I
I
6
4
fy(MHz)
Fig.21 Luminance control in 60 Hz / CVBS mode controllable by subaddress byte 06; pre-filter off and
coring off; maximum and minimum aperture bandpass filter characteristics.
April 1993
3-415
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder,
square pixel (DMSD-SQP)
SAA7191B
MSH220
18
18 r-~-'__' - - '__'-~__TMS~H~221
C3h
12
Vy
(dB)
Vy
83h
-
6
82h
V
L
~
/
.
/
- - F=::
/--
/-
81h
-6 r--
80h
1-50 Hz
-6
I I
-12
COh
50 Hz --+--+--+---+----l
-12 I---I----l---+--+--+--l---+--l
-18
o
12 r--r~~""~~~~T--1
(dB)
2
6
4
-18 '----'----'__-'----'__--'----J._ _--'----'
o
2
4
6
8
8
fy(MHz)
fy(MHz)
Fig.23 Luminance control in 50 Hz / S-VHS mode
controllable by subaddress byte 06;
pre-filter on and coring off; different aperture
bandpass filter characteristics.
Fig.22 Luminance control in 50 Hz / S-VHS mode
controllable by subaddress byte 06;
pre-filter off and coring off; different aperture
bandpass filter characteristics.
MSH222
18
MSH223
18
C3h
Vy
(dB)
12
6
-~
o
-6
,...--
-
-
Vy
(dB)
82h
83h
v
-
6
r-.....
!-- ::z::: ~ ~
/
81h
f-60 Hz
--
12
~
COh
80h
-6
60 Hz
-12
-12
-18 '----'----'__-'----'__-'----J._ _-'----'
o
2
4
6
8
-18
o
2
4
6
8
fy(MHz)
fy(MHz)
Fig.24 Luminance control in 60 Hz / S-VHS mode
controllable by subaddress byte 06;
pre-filter off and coring off; different aperture
bandpass ffilter characteristics.
Fig.25 Luminance control in 60 Hz / S-VHS mode
controllable by subaddress byte 06;
pre-filter on and coring off; different aperture
bandpass filter characteristics.
Purchase of Philips' 12C components conveys a license under the
Philips' 12C patent to use the components in the 12C-system
provided the system conforms to the 12C specifications defined
by Philips.
April 1993
3-416
Philips Semiconductors Video Products
Preliminary specification
Digital multistandard colour decoder,
square pixel (DMSD-SQP)
SAA71918
PROGRAMMING EXAMPLE
Coefficients to set operation for application circuits Figures 13 and 14. (All numbers of the Table 6 are hex values).
Slave address byte is SA at pin 43 = 0 V (or SE at pin 43 = +5 V).
Table 7 Recommended default values
SUBADDRESS
BIT NAME
FUNCTION
VALUE (HEX)
00
01
02
IDEL(7-0)
HSY8(7-0)
HSYS(7-0)
increment delay
H sync beginning for 50 Hz
H sync stop for 50 Hz
50
30
00
03
04
05
HCL8(7-0)
HCLS(7-0)
HPHI(7-0)
H clamping beginning for 50 Hz
H clamping stop for 50 Hz
H sync position for 50 Hz
E8
86
F4
06
8YPS, PREF, 8PSS(1-0)
CORI(1-0), APER(1-0)
HUEC(7-0)
CKTQ(4-0)
CKTS(4-0)
luminance bandwidth control:
hue control (0 degree)
colour-killer threshold QUAM
colour-killer threshold SECAM
01(1)
00
F8
F8
PAL switch sensitivity
SECAM switch sensitivity
chroma gain control settings
90
90
00
standard/mode control
00(2)(4), 01 (3)(4)
_._._.-._.- -----------------_._-- ------------.--_._--------- ----------------07
OS
09
OA
08
OC
OD
OE
PLSE(7-0)
SESE(7-0)
COLO, LFIS(1-0)
VTRC, NFEN,HRMV,
GPSWO and SECS
HPLL,OEDC,OEHS,OEVS
OEDY, CHRS, GPSW(2-1)
I/O and clock control
79,7E(5)
AUFD, FSEL, SXCR, SCEN,
OFTS, YDEL(2-0)
miscellaneous control #1
91(6),99(7)
10
11
HRFS, VNOI(1-0)
CHCV(7-0)
miscellaneous control #2
chrominance gain nominal value
00
2C(8),59(9)
12
13
-
set to zero
set to zero
00
00
14
15
HS68(7-0)
HS6S(7-0)
H sync beginning for 60 Hz
H sync stop for 60 Hz
34
16
17
1S
HC68(7-0)
HC6S(7-0)
HP61(7-0)
Hclamping beginning for 60 Hz
F4
CE
F4
OF
----------- _._._---------------- ----------._--------------- ._-------------H clamping stop for 60 Hz
H sync position for 60 Hz
Notes to Table 7
(1)
dependent on application (Figures 16 to 25)
(2)
for QUAM standards
(3)
for SECAM
(4)
HPLL is in TV mode; value for VCR mode is SO (S1 for SECAM VCR mode)
(5)
for Y/C mode
(6)
4:1:1 format
(7)
4:2:2 format
(S)
nominal value for UV CCIR level with NTSC source
(9)
nominal value for UV CCIR level with PAL source
April 1993
3-417
OA
Philips Semiconductors Video Products
Product specification
Digital colour space converter
FEATURES
•
QUICK REFERENCE DATA
MIN
MAX
multiplexer
V DD
Supply voltage
-0.5
7
V
ycdalay line
VI
input voltage
-0.5
7
V
Cr and Cb interpolating
filters
VO
output voltage
-0.5
Plot
total power dissipation
Input formatter with:
• Conversion matrix (acc. to CCIR
601)
• Video look-up tables (provide
gamma correction)
•
SAA7192A
Pipeline delay line (horizontal
reference signal)
• 12C-bus interface
SYMBOL
PARAMETER
Tstg
storage temperature range
Tamb
operating ambient temperature
UNIT
7
V
1.5
W
-65
+150
C
0
+70
C
ORDERING INFORMATION
EXTENDED
TYPE NUMBER
PACKAGE
PINS
PIN POSITION
MATERIAL
CODE
SOT18-8AA,
SAA7192
68
GENERAL DESCRIPTION
plastic
AGA, CGS
The Digital Colour Space Converter
(DCSC) is a digital matrix which is
used to transform 16/24-bit digital
input signals, i.e. Y (luminance), Cr
(colour, R-Y) and Cb (colour, B-Y),
into an RGB 24-bit format in
accordance with the CCIR-601
recommendations.
Accepting inputs from the different
formats of the DMSD2 decoder
family, the device has a constant
propagation delay and a maximum
data rate of 16 MHz. A matched
pipeline delay line is available to
permit the HREF signal to be
synchronized with the video data at
the output.
June 1991
PLCC
3-418
Product specification
Philips Semiconductors
Digital colour space converter
SAA7192A
BLOCK DIAGRAM
FORMATIER
H
DATAIN1
Y
DELAY
MULTIPLEXER I - - -
DATAIN2
~
f---
I-f---
MATRIX
Cr and Cb
FILTER
DATAIN3
I---
1--1---
H
H
H
VIDEO
LOOK-UP
TABLES
VIDEO
LOOK-UP
TABLES
VIDEO
LOOK-UP
TABLES
Il
DATAOUT1
1I
DATAOUT2
Il
DATAOUT3
I
horizontol
reference
input
j
65
-
60
f-----
159
I
eLK_mode
I
I
I
SAA7192A
163
126
PIPELINE DELAY LINE
164
12C-BUS RECEIVER
128
I
I
I
I
clock
reset
clock
reference
serial
clock
27
12 C-bus
address
Fig.1 Block diagram.
June 1991
3-419
129
58
I
I
horizontal
reference
output
I
162
161
I
I
I
serial
data
VLUT
bypass
output
enable
MCB572-1
Philips Semiconductors
Product specification
Digital colour space converter
SAA7192A
PIN CONFIGURATION
M
Z
~
0
0
r--
Z
Z
C')
«
Ie(
0
C\I
~
0
CD
C\I
Z
LC')
C\I
«
l-
Z
0
0
e(
~
v
C')
Z
Z
C\I
C\I
C\I
C\I
Z
Z
«
«
«
«
IlIIe(
e(
e(
e(
0
0
0
0
C/)
C/)
e(
0
C\I
(\j
Z
C/)
C/)
>
0
0
>
«
Ie(
0
u..
W
a:
J:
u..
W
a:
()
~
()
0
....J
()
c..
>-
III
l-
::J
....J
>
I~
DATAIN32
TEST
DATAIN33
elK_MODE
DATAIN34
HREF_OUT
DATAIN35
DATAOUT37
DATAIN36
DATAOUT36
DATAIN37
DATAOUT35
DATAIN10
DATAOUT34
DATAIN11
DATAOUT33
SAA7192A
VDD
Vss
VSS
VDD
DATAIN12
DATAOUT32
DATAIN13
DATAOUT31
DATAIN14
DATAOUT30
DATAIN15
DATAOUT27
DATAIN16
DATAOUT26
DATAIN17
DATAOUT25
RESET
DATAOUT24
C/)
C/)
....J
()
e(
W
C/)
C/)
a:
0
0
e(
ci:
0
0
;::
::J
0
~
C\I
;:: ;::
::J
::J
~
I-
0
e(
e(
0
0
0e(
e(
0
C')
V
::J
::J
;:: ;::
~
0
0
0
~
0
0
>
C/)
>C/)
LC')
CD
r--
::J
::J
~
0
::J
0
I-
l-
0
0
0
0
;:: ;:: ;::
0
e(
l-
e(
e(
e(
e(
Fig.2 Pin configuration.
June 1991
3-420
e(
e(
0
C\I
(\j
C\I
C\I
C')
C\I
l-
I-
l-
0
0
0
0
I-
l-
I-
l-
0
0
0
::J
e(
e(
::J
e(
e(
::J
e(
e(
I-
::J
e(
e(
MLA089-1
Philips Semiconductors
Product specification
Digital colour space converter
SAA7192A
PINNING
SYMBOL
PIN
DATAIN (10-17)
16-17 and
20-25
DATAIN (20-27)
1-7 and 66 colour difference signal Cr (0-7)
DATAIN (30-37)
8-15
colour difference signal Cb (0-7) or
multiplexed Cb and Cr
DATAOUT
(10-17)
30-34 and
37-39
RED (0-7)
DATAOUT
(20-27)
40-47
GREEN (0-7)
DATAOUT
(30-37)
48-50 and
53-57
BLUE (0-7)
DESCRIPTION
luminance signal Y (0-7)
RESET
26
initially resets the functions
HREF_OUT
58
delayed horizontal reference signal
CLK_MODE
59
16 MHz or DMSD clock mode selection
TEST
60
test mode, usually not connected
OE
61
output enable (fast switch)
VLUTBYPASS
62
fast switch to operate the VLUTs in bypass
CLOCK
63
system clock
CREF
64
clock reference signal (DMSD mode)
HREF
65
horizontal reference signal
18,67
positive supply, voltage core (+ 5 V)
35, 51
positive supply voltage, output stages (+ 5 V)
V DD
19,68
negative supply, voltage core (ground)
36,52
negative supply, output stages
12C-bus
ADDRESS
27
J2C-bus SLAVE ADDRESS selection
SCL
28
12C-bus SERIAL CLOCK input
SDA
29
12C-bus SERIAL DATA input
Vss
Note
All DATAIN and DATAOUT busses count from 0 (LSB) to 7 (MSB).
June 1991
3-421
Philips Semiconductors
product specification
Digital colour space converter
SAA7192A
Functional modes
Table 1 Functional Modes
MODE
FUNCTION
1
4:1: 1 filter, no matrix, no VLUT; DATAOUT = upsampled DATAIN
2
4:1:1 filter, matrix, no VLUT; DATAOUT = RGB
3
4:1:1 filter, no matrix, VLUT; DATAOUT =upsampled DATAIN multiplied by the factor
loaded into the VLUT
4
4:1:1 filter, ~trix, VLUT;DATAOUT = RGB multiplied by the factor loaded into the VLUT
5
6
4:2:2 filter, no matrix, no VLUT; DATAOUT = upsampled DATAIN
4:2:2 filter, matrix, no VLUT; DATAOUT = RGB
7
4:2:2 filter, no matrix, VLUT; DATAOUT =upsampled DATAIN multiplied by the factor
loaded into the VLUT
8
4:2:2 filter, matrix, VLUT; DATAOUT = RGB multiplied by the factor loaded into the VLUT
9
no filter, no matrix, no VLUT; DATAOUT = DATAIN ·Process Bypass·
10
no filter, matrix, no VLUT; DATAOUT = RGB-
11
no filter, no matrix, VLUT; DATAOUT = DATAIN multiplied by the factor loaded into the
VLUT.
12
no filter, matrix, VLUT; DATAOUT = RGB multiplied by the factor loaded into the VLUT
Note
Figures 3 to 10 illustrate the various functional modes.
June 1991
3.. 422
Product specification
Philips Semiconductors
Digital colour space converter
SAA7192A
FORMATIER
DATAIN1
H
DATAIN2
MULTIPLEXER f - - - -
Y
DELAY
DATAOUT1
DATAOUT2
Cr and Cb
FILTER
DATAOUT3
I----
DATAIN3
I
horizontal
reference
input
I
65
I
I
1
I
PIPELINE DELAY LINE
58
horizontal
reference
output
60
t e s t - r-:--
163
159
1
1
ClK_mode
clock
126
164
~
reset
128
127
1
1
1
clock
reference
serial
clock
12C-bus
address
129
162
161
1 1 _I
serial
data
VlUT
bypass
MCB576
output
enable
Fig.3 Functional mode 1 and 5.
FORMATIER
H
DATAIN1
DATAIN2
Y
DELAY
~
I---
1-1---
MULTIPLEXER I - - - -
DATAOUT1
DATAOUT2
MATRIX
Cr and Cb
FilTER
I----
DATAIN3
horizontal
reference
input
I
I
65
-
DATAOUT3
1--1----
I
I
PIPELINE DELAY LINE
58
I
horizontal
reference
output
60
t---
159
1
ClK_ mode
163
I
clock
126
164
128
127
129
1
1
1
1
1
reset
clock
reference
serial
clock
12 C-bus
address
serial
data
Fig.4 Functional mode 2 and 6.
June 1991
1
3-423
162
I
VlUT
bypass
161
1
output
enable
MCB575
Philips Semiconductors
Product
Digital colour space converter
~pecification
SAA7192A
FORMATTER
DATAIN1
H
DATAIN2
MULTIPLEXER t - - - -
Y
DELAY
Cr and Cb
FILTER
DATAoun
VIDEO
1I LOOK-UP
Il
TABLES
DATAOUT2
I LOOK-UP
VIDEO
I
f---
DATAIN3
r LOOK-UP
VIDEO 1
I TABLES I
I
TABLES
DATAOUT3
I
1
horizontal
reference
input
I
65
I
I
PIPELINE DELAY LINE
58
1
r
horizontal
'reference
output
60
~
I---
159
163
I
I
128
164
126
I
reset
I
I
clock
reference
senar
clock
127
1
12 C'-bus
address
129
162
161
I
I
I
MCB574
serial
data
Fig.S Functional mode 3 and 7.
FORMATTER
H
DATAIN1
DATAIN2
Y
DELAY
~
f---
I--f---
MULTIPLEXER f - - -
MATRIX
Cr and Cb
FILTER
f---
DATAIN3
I--f---
H
H
H
VIDEO
LOOK-UP
TABLES
VIDEO
LOOK-UP
TABLES
lI
DATAOUT1
II
DATIIOI.:JT2
I
DATAOUT3
VIDEO-1
LOOK-UP
TABLES
1
horizontal
reference
input
I
65
-
I
I
r
horizontal
reference
output
60
I---
159
163
I
I
126
I
reset
164
I
clock
reference
128
I
serial
clock
129
162
161
T
r
I
I
12 C-bus
address
serial
data
127
Fig.6 Functional mode 4 and 8.
June 1991
58
1
PIPELINE "DELAY LINE
3-424
MCB573
Philips Semiconductors
Product specification
SAA7192A
Digital colour space converter
DATAIN1
I
PIPELINE DELAY LINE
J
PIPELINE DELAY LINE
I
I
DATAIN2
I
DATAIN3
I
horizontal
reference
input
I
I
-
I
I
DATAOUT1
I
DATAOUT2
PIPELINE DELAY LINE
I
I
DATAOUT3
PIPELINE DELAY LINE
I
I
horizontal
reference
output
J
60
-
159
1
163
1
164
126
128
1
1
1
reset
clock
reference
serial
clock
127
129
I
1
12 C-':bus
address
serial
data
162
161
~ _I
VLUT
bypass
MCB571
output
enable
Fig.? Functional mode 9.
DATAIN1
DATAOUT1
DATAIN2
DATAOUT2
MATRIX
DATAIN3
DATAOUT3
horizontal
reference
input
I
-
PIPELINE DELAY LINE
60
r--159
1
CLK_mode
163
126
164
128
127
129
162
161
1
1
1
1
1
1
1
1
clock
reset
clock
reference
serial
clock
12C-bus
address
serial
data
VLUT
bypass
Fig.S Functional mode 10.
June 1991
horizontal
reference
output
I
I
3-425
MCB570
Philips Semiconductors
Product specification
Digital colour space converter
SAA7192A
I LO~~:~P I
DA1AIN1
I
TABLES
DATAOUT1
I
I LOOK-UP
VIDEO
l
DATAIN2
I
TABLES
DATAOUT2
I
I VIDEO I
I LOOK-UP
TABLES I
DATAIN3
horizontal
reference
input
J
I
-
DATAOUT3
PIPELINE DELAY LINE
horizontal
reference
output
I
I
60
f--
159
I
t
I
63
126
164
128
/27
129
162
/61
I
I
I
I
I
I
I
reset
clock
reference
serial
clock
12 C-bus
address
serial
data
MCB568
Fig.9 Functional mode 11.
DATAIN1 - - + - - - - - - - - - - 1
DATAIN2 - - + - - - - - - - - - - - l
I-----~----+_-
t - - - - - - - - - - - t - - DATAOUT2
MATRIX
DAT~N3--+----------I
t---------~-t--
horizontal
reference - - + - - - - - - - - - - - /
input
DATAOUT1
DATAOUT3
horizontal
PIPELINE DELAY LINE
1 - - - - - - - - - - - - - + - - reference
output
60
61
MCB569
reset
clock
reference
serial
clock
12 C-bus
address
Fig.10 Functional mode 12.
June 1991
3·426
serial
data
Philips Semiconductors
Product specification
Digital colour space converter
Control facilities
After power-up all device internal
control signals are at undefined
values. The 12C-bus receiver must,
therefore, be reset by using the
external RESET signal.
SAA7192A
Table 2 12C-bus control signals (subadd OOH) after an external RESET is
received
SYMBOL
STATUS
BIT
IICOE
05
FMTCNTRL
00-02
MATBYPASS
03
INRESET
04
= 1 ; OE pin 61 enabled
=4 ; format 4:4:4
=0 ; matrix by-passed
=0 ; input data set to fixed values
Table 3 Input formats and functional modes
FMTCNTRL MATBYPASS VLUTBYPASS
000
0
0
000
1
0
mode 2, input format 0
(OMSD2 format)
001
0
0
mode 1, input format 1
001
1
0
mode 2, input format 1
010
0
0
mode 5, input format 2
(OMSD2 format)
010
1
0
mode 6, input format 2
(OMSD2 format)
011
0
0
mode 5, input format 3
(parallel IN)
011
1
0
mode 6, input format 3
(parallel IN)
100
0
0
mode 9, input format 4
(parallel IN)
100
1
0
mode 10, input format 4
(parallel IN)
1
each of the above
described modes will be
multiplied by the factor
loaded into the VLUT.
x
x
Note
The modes are given in Table 1.
June 1991
FUNCTIONS
mode 1, input format 0
(OMSD2 format)
3-427
Product specification
Philips Semiconductors
SAA7192A
Digital colour space converter
The other control signals are:
INRESET
logic 1
input latches at the formatter are
always transparent
logic 0
at the end of each active video line
the input latches have to be set to
fixed values (Y to 16; Cr and Cb to
128; if HREF =0)
logic 1
OMSO mode (LL27 clock of OMSO
feeds the OCSC)
logic 0
OCSC is fed by a maximum 16 MHz
clock without CREF signal.
Table 4 Output enable control
CONTROl LINE TO DRIVER STAGES
IICOE
OE
0
X
1 = DATAOUT i!1 high impedance mode
1
1
1 = OATAOUT in high impedance mode
1
0
0= OATAOUT working
Notes
IICOE : 05; output enable control of 12C-bus (enables OE)
OE: pin 61 ; output enable (fast switch)
June 1991
3-428
Product specification
Philips Semiconductors
SAA7192A
Digital colour space converter
SYSTEM 1/0 INTERFACES
Input signals
Table 5 Format 0 (4:1 :1, semi-parallel, DMSD2 decoder family format)
DATAIN1 - Y
luminance signal, 8-bit
Sampling frequency
12 to 16 MHz
Level
o IRE; black, quantization level 16 100 IRE; white, quantization level 235
DATAIN3 - U, V
multiplexed colour difference signals 4-bit; corresponds to UV7 to UV4 of DMSD2
Sampling frequency
1/4 of the Y signal
Level
bottom peak; quantization level 16 top peak; quantization level 240
colourless; quantization level 128
DATAIN2
not used
Table 6 Timing of Format 0; pin (DATAIN) and bit (U,V) numbers are indicated except clock
Y; 7 to 0
Y
Y
Y
Y
Y
Y
Y
DATAIN 37
U7
U5
U3
U1
U7
U5
U3
DATAIN 36
U6
U4
U2
UO
U6
U4
U2
DATAIN 35
V7
V5
V3
V1
V7
V5
V3
DATAIN 34
V6
V4
V2
VO
V6
V4
V2
1
2
3
4
5
6
7
Clock A
Note
Clock_A is the internal sampling clock of the system. The clock rate of the DMSD and the DCSC is twice that of
Clock_A in this mode.
Table 7 Format 1 (4:1: 1, semi-parallel, customized format)
DATAIN1 - Y
luminance signal; 8-bit
Sampling frequency
12 to 16 MHz
Level
o IRE; black; quantization level 16 100 IRE; white; quantization level 235
DATAIN3 - Cr, Cb
multiplexed colour difference signals, 8-bit
Sampling frequency
1/4 of the Y signal
Level
bottom peak; quantization level 16 top peak; quantization level 240
colourless; quantization level 128
DATAIN2
not used
June 1991
3-429
Product specification
Philips Semiconductors
SAA7192A
Digital colour space converter
Table 8 Timing of Format 1 ; the indices show the clock (sample) number
Y
YO
Cr, Cb
CbO
Clock A
0
Y1
Y2
Y3
crO
1
2
Y4
Y5
Cb4
3
Y6
Cr4
4
5
6
Note
Clock_A is the internal sampling clock of the system. The external CLOCK may differ from the CLK_MODE.
Table 9 Format 2 (4:2:2, semi-parallel, DMSD2 format)
DATAIN1 Y
luminance signal; 8-bit
Sampling frequency
12to 16 MHz
Level
o IRE; black; quantization level 16 100 IRE; white; quantization level 235
DATAIN3 - Cr, Cb
multiplexed colour difference signals; corresponds to UV7 to UVO of DMSD2
Sampling frequency
1/2 of the Y signal
Level
bottom peak; quantization level 16 top peak; quantization level 240
colourless; quantization level 128
DATAIN2
not used
Table 10 Timing of Format 2
Y
Cr, Cb
Clock A
YO
Y1
Y2
Y3
Y4
Y5
Y6
CbO
CrO
Cb2
Cr2
Cb4
Cr4
Cb6
0
1
2
3
4
5
6
Note
Clock_A is the internal sampling clock of the system. The clock of the DMSD (also the CLOCK of the DCSC) is twice
that of Clock_A in this mode.
June 1991
3-430
Philips Semiconductors
Produ9t specification
Digital colour space converter
SAA7192A
Table 11 Format 3 (4:2:2, Y-Cr-Cb, parallel)
DATAIN1 - Y
luminance signal; 8-bit
Sampling frequency
12 to 16 MHz
level
o IRE; black; quantization level 16 100 IRE; white; quantization level 235
DATAIN3 - Cb
colour difference signal 8- Y, 8-bit
Sampling frequency
112 of the Y signal
level
bottom peak; quantization level 16 top peak; quantization level 240
colourless; quantization level 128
DATAIN2 - Cr
colour difference signal R-Y, 8-bit
Sampling frequency
1/2 of the Y signal
level
bottom peak; quantization level 16 top peak; quantization level 240
colourless; quantization level 128
Table 12 Timing of Format 3
Y
YO
Cb
CbO
Cr
CrO
Clock A
0
Y1
Y2
Y3
Cb2
2
Y5
3
4
Y6
Cb6
Cr4
Cr2
1
Y4
Cb4
Cr6
5
6
Note
Clock_A is the internal sampling clock of the system. The external CLOCK may differ from the ClK_MODE.
Table 13 Format 4 (4:4:4, Y-Cr-Cb, parallel)
DATAIN2 - Cr
colour difference signal R-Y, 8-bit
Sampling frequency
as the Y signal
level
bottom peak; quantization level 16 top peak; quantization level 240 colourless, binary 128
DATAIN3- Cb
colour difference signal B-Y, 8-bit
Sampling frequency
as the Y signal
level
bottom peak; quantization level 16 top peak; quantization level 240
colourless; quantization level 128
DATAIN1 - Y
luminance signal; 8-bit
Sampling frequency
12 to 16 MHz
level
o IRE; black; quantization level 16 100 IRE; white; quantization level 235
June 1991
3-431
Philips Semiconductors
Product specification
Digital colour space converter
SAA7192A
VIDEO DATA (DATAIN)
Table 14 Timing of Format 4
YO
Y1
Y2
Y3
Y4
Y5
Y6
Cb
CbO
Cb1
Cb2
Cb3
Cb4
Cb5
Cb6
Cr
crO
Cr1
Cr2
Cr3
Cr4
Cr5
Cr6
0
1
2
3
4
5
6
Y
Clock A
Note
Clock_A is the internal sampling clock of the system. The external CLOCK may differ from CLK_MODE.
CONTROL DATA
Clock
The CLK-Mode signal is used to
select the frequency of the system
clock (denoted as CLOCK at the
DCSC input) and may be chosen
from two different Clock Modes.
16 MHz-Mode:
DCSC is used in any environment
except that of the DMSD2 decoder
family. The clock reference signal
(CREF) is internally set HIGH in
value.
The maximum CLOCK frequency is
16 MHz.
locked clock LL27 (denoted as
CLOCK at the DCSC input) is twice
the data rate of that specified for the
DMSD2 family of decoders. The
data rate is denoted as CLOCK_A in
Tables6,8, 10, 12and 14.
DCSC is used in a DMSD
environment.
The CLOCK signal (LL27) and the
CREF signal are fed by the clock
generator circuit
(SAA7157/SAA7197) and the line
June 1991
CREF
The clock reference signal
is a clock qualifier signal
distributed by the clock
generator of the DMSD
system. The frequency is
identical to the sample
rates denoted in the input
and the output formats
(see Video data and
Operating conditions).
HREF
Horizontal reference signal
is the line reference signal
of the YUV-bus. A positive
slope marks the beginning
of the active part of a line.
The length of the active
part corresponds to the
number of samples (see
Operating conditions).
The data rate on the input (DATAIN)
is as follows:
12.2727 MHz; 60 Hz signals
(from SAA7191)
13.5 MHz; CCIR signals (from
SAA7151)
14.75 MHz; 50 Hz signals (from
SAA7191)
16.0 MHz; maximum frequency
TIMING REFERENCE
DMSD-Mode:
The horizontal reference signal,
HREF, indicates the active part of a
line and also synchronizes the
multiplexer.
The timing reference signal from the
SAA715117191 is used to
synchronize the multiplexer and
refers to the LL27 clock. Each
alternative positive slope, marked by
a CREF signal, is used to obtain
data.
3-432
Philips Semiconductors
Product specification
Digital colour space converter
SAA7192A
Table 15 Real-time control signals
OE
VlUTBYPASS
RESET
ClK_MODE
pin 61
pin 62
pin 26
pin 59
=1:
switches the output to high-z mode
=0 :
output enable, output stage in use
=1:
VlUT's in use
= 0:
VlUT's bypassed
=1:
device in use
=0 :
general reset
=1:
DMSD mode (ll27 clock of DMSD feeds the DCSC)
=0 :
DCSC is fed by a clock signal with a maximum data rate of 16 MHz
(without CREF signal).
Table 16 12C-bus controls (sub-add. VlUTDATA)
SUB-ADD
VLUTDATA FED TO
RAM 1 (RED)
01H
RAM 2 (GREEN)
02H
RAM 3 (BLUE)
03H
RAM 1,2,3
04H
Note
See also example of VlUT programming Fig. 23.
June 1991
3-433
Product specifiCation
Philips Semiconductors
SAA7192A
Digital colour space converter
Table 17 12C-buS controls (sub-add. OOH)
FMTCNTRl
MATBYPASS
INRESET
DO-D2
D3
D4
IICOE
=000 :
4:1:1 format, DMSD2 format
= 001 :
4: 1:1 format, customiz,ed format
= 010:
4:2:2 format, from DMSD2
= 011 :
4:2:2 format, parallel
= 100:
4:4:4 format, parallel
= 101 :
not used
= 110:
not used
= 111 :
not used
= 1:
matrix in use
=0 :
matrix bypassed
tr~nsparent
=1:
input latches at the formatter are always
= 0:
at the end of each active video lioe the input latches have to be set to
fixed values (Y to 16; Cr, Cb to 128; if HREF = 0)
D5 = 1 :
OE enabled
=0 :
switches the. output to high impedance mode
OUTPUT SIGNALS
Video data
Table 19 Timing of DATAOUT (R-G-B if matrix in use)
Timing:
the indices show the clock sample number
DATAOUT1 :
RO
R1
R2
R3
R4
R5
R6
DATAOUT2 :
GO
G1
G2
G3
G4
G5
G6
DATAOUT3 :
BO
B1
B2
B3
B4
B5
B6
0
1
2
3
4
5
6
Clock_A:
Notes
Clock_A is the internal sampling clock of the system. The system clock may differ from ClK-MODE.
OE (output enable, fast switch, active lOW) and IICOE (l2C-bus output enable, active HIGH) will switch the
DATAOUT lines in high-z or normal mode.
See also Fig. 14.
June 1991
Philips Semiconductors
Product specification
Digital colour space converter
SAA7192A
Auxiliary data
Pipelined external reference signal
HREF_OUT (delayed HREF).
The delay line (word length 1-bit) has
the same duration as the signal
processing of the video data lines.
horizontal
reference
input
65
- + - - - - - 11
1
58
PIPELINE DELAY LINE
Llt----+--
horizontal
reference
output
159
OPERATING CONDITIONS
I
MCC024
Electrical Conditions
START-UP CONDITION
Fig.11 Delayed HREF.
No particular function except the
external power-on-reset e.g. for
12C-bus interface (RESET) is
intended.
OPERATING TIME
As this device will be used in
computers, it has been designed to
operate continuously.
HANDLING
Inputs and outputs are protected
against electrostatic discharge
during normal handling. It is
desirable, however, to observe
normal handling precautions
appropriate to MOS devices.
TEMPERATURE RANGE
Refer to the characteristics.
BACKUP
No internal backup capability
(standby) is provided.
POWER DOWN MODE
No internal power-down capability is
provided.
June 1991
3-435
Philips Semiconductors
Product specification
Digital colour space converter
SAA7192A
LIMITING VALUES
SYMBOL
PARAMETER
MIN
MAX
UNIT
V
-65
7
7
7
1.5
+150
0
+70
Voo
VI
input voltage
-0.5
-0.5
va
output voltage
-0.5
Ptot
total power dissipation
Supply voltage
Tstg
storage temperature range
Tamb
operating ambient temperature
-
V
V
W
C
C
CHARACTERISTICS
SYMBOL
PARAMETER
Voo
supply voltage
100
supply current
CONDITION
UNIT
MIN
MAX
4.5
5.5
V
-
150
mA
-0.5
-0.5
1.5
0.8
V
3
2
Voo +0.5
V
Voo +0.5
V
-
10
J.lA
10
pF
HIGH (any)
2.4
Voo
V
LOW (SDA)
0
0
0.4
0.4
V
-
4
3
4
40
10
note 1
Inputs
V1L
input voltage LOW
SDA, SCL
any other
V1H
V
input voltage HIGH
SDA,SCL
any other
IL
input leakage current
C1
input capacitance
note 2
Outputs
output voltage
VOH
VOL
LOW (any other)
V
output current
10H
HIGH (any)
10L
LOW (SDA)
LOW (any other
C Ld
output load capacitance
10
output leakage current
-
mA
mA
mA
pF
J.lA
Notes
The supply current may vary between 30 and 150 mA depending upon the input data. The minimum may be
achieved with OE disabled and no clock
2 All inputs except TEST (internal pull-up resistor).
June 1991
3-436
Philips Semiconductors
Product specification
Digital colour space converter
SAA7192A
TIMING CHARACTERISTICS
PARAMETER
SYMBOL
CONDITION
propagation delay
note 2
CLOCK (DMSD-mode, ll27) :
note 3
tc27
MIN
TYP
-
26
MAX
UNIT
tC16
cycle time
31
45
ns
duty cycle
40
-
60
0/0
-
83
ns
-
-
ns
-
ns
-
ns
CLOCK (16 MHz-mode):
note 4
tc16
cycle time
62
tcOL
duty time lOW
30
tcOH
duty time HIGH
16
tcs
set-up time
11
tcH
hold time
3
-
tHS
set-up time
11
-
tHH
hold time
3
ns
CREF
ns
HREF
tRH
ns
4 clock periods
RESEThold time
VlUTBYPASS
note 5
tvs
set-up time
8
tVH
hold time
0
-
-
ClK_MODE set-up time
must be set before RESET
12C-bus address set-up time
must be set before RESET
ns
ns
DATAIN
set-up time
11
hold time
3
-
los
set-up time
10
-
loH
hold time
10
tsu
fHo
-
ns
ns
DATAOUT
-
ns
-
ns
-
-
ns
10
15
ns
15
21
ns
HREF_OUT
loHS
set-up time
9
tOHH
hold time
10
fHz
output disable time (to tri-state)
tZH
output enable time (from tri-state)
-
ns
Notes
1 Typical ratings are measured at VDO
=5 V and 25°C room temperature
2 Denotes the delay in clock periods between DATAIN and DATAOUT
3 DMSD-mode designates that the DCSC will work in a DMSD environment. The CLOCK and the clock reference
signal CREF will be fed by the SCGC (SAA7157). This is further explained in the following diagrams.
4 16 MHz-mode indicates that the DCSC will work in any other environment. The CREF signal will be set internally to
HIGH, the CLOCK signal can be any clock up to 16 MHz {see also Fig. 15.
5 Must be set one clock period before DATAOUT.
June 1991
3-437
Philips Semiconductors
Product, specification
Digital colour space converter
SAA7192A
clock
LL27
CREF
HREF
input
data
MCB567-1
Fig.12 Timing diagram input.
tCDL- - - t C D H - - - t C 1 6 -
CLOCK
HREF
-
tsu
tHD--
DATA
INPUT
Fig.13 Timing diagram input (16 MHz mode).
June 1991
3-438
Product specification
Philips Semiconductors
SAA7192A
Digital colour space converter
MCB566-1
OE will also affect HREF_OUT
Fig.14 Timing diagram output.
Error condition
To inhibit unwanted operations, no
information signal is available to the
peripheral circuits. In the advent of
an error the system must be
re-started by application of the
RESET signal.
June 1991
3-439
Philips Semiconductors
Product specification
Digital colour space converter
SAA7192A
CLOCK
VLUTBYPASS
DATA
OUTPUT
VLUTBYPASS must be supplied one clock pulse in advance of the desired DATAOUT lines reaction.
Fig.1S Timing diagram VLUTBYPASS
SYSTEM BLOCK DESCRIPTION
Input formatter
The formatter consists of five
functional blocks:
• the multiplexer, which decodes
the luminance and chrominance
input signals
• the filter, which interpolates the
samples of the incoming signal
to get an upsampled data rate
as at DATAIN1
• the luminance delay line
• the timing control which creates
the internal reference Signals
from the various inputs
• the bypass output multiplexer
June 1991
3-440
The data applied at DATAIN1 to
DATAIN3 is converted as follows;
FIL1 : Y Luminance
FIL2 : Cr colour-difference Signal R-Y
FIL3 : Cb colour-difference signal
B-Y
Philips Semiconductors
Product specification
SAA7192A
Digital colour space converter
H
DATAIN1
DATAIN2
MULTIPLEXER
Y
DELAY
~
~
I----
FlL1
OUTPUT
MULTIPLEXER
FlL2
Cr and Cb
FILTER
DATAIN3
l----
FlL3
f---
horizontal
reference
input
I
I
TIMING CONTROL
Me 8564
format
control
in reset
CREF
clock
mode
clock
Fig.16 Input formatter.
Filter and delay line
CHROMINANCE FILTER
Format 3,4
In the various functional modes the
signal FMTCNTRL switches in the
required filters (FMTCNTRL is
described in 'Control data'). In all
modes the same propagation delay
will be realized, (the reference is
CbO, respective to U7 with format 0).
The filter for the Cr and Cb signal is
realized in one filter design.
An interpolating filter is inserted to
convert the original sampling
frequency to the sampling frequency
of the luminance signal i.e. twice the
colour signal. Figure 18 illustrates
the frequency response of the
chrominance section.
At all frequencies and in all formats,
there is a delay line to compensate
for the delay of the signal
processing time needed in the
chrominance section.
June 1991
4:1 :1
Format 1, 2
An interpolating filter is inserted to
convert the original sampling
frequency to the sampling frequency
of the luminance signal i.e. four
times that of the colour signal.
Figure 17 illustrates the frequency
response of the chrominance
section.
3-441
Format 5
4:2:2
4:4:4
A bypass with a specified delay is
inserted.
Philips Semiconductors
Product specification
Digital colour space converter
SAA7192A
" '\1\
A
(dB)
':"'10
MCB561
\\
-20
1
-30
\
r
-40
\
-50
\
0.1
(1
0.2
\
~
I
I
\
o
l"\
\
0.4
0.3
0.5
f
fclock_A
Fig.17 Frequencyresponseof4:1:1 filter.
MCB562
o
.....
A
(dB)
~
I\.
-10
"\
-20
\\
-30
~
I '\
\
-40
1\
-50
o
0.1
0.2
0.3
0.4
\
0.5
f
fclock_A
Fig.18 Frequency response of 4:2:2 filter
June 1991
3-442
Philips Semiconductors
Product specification
Digital colour space converter
SAA7192A
CONVERSION MATRIX
FIL1
FIL2
1
L
LIMITER
I -~
MUX
~ r------+
J
LIMITER
I H
MUX
t-
J
LIMITER
MUX
~-
I
MATRIX
FIL3
J
I
r-
I
J
r
I
H
MAn
r---- MAT2
MAT3
-
MCB563 1
Fig.19 MATRIX block diagram.
The properties of the conversion
matrix are as follows:
- the conversion equations are
(according to CCIR 601, with
respect to the different
quantisation on Y, Cb and Cr);
Red = Y + 1.371 (Cr - 0.5)
Green = Y - 0.698 (Cr - 0.5) 0.336 (Cb - 0.5)
Blue = Y + 1.732 (Cb - 0.5)
June 1991
- the accuracy of the signal
processing is within ± 0.5% of
the accuracy of a theoretical
conversion.
- the input and output data lines
are 8-bit.
- in the advent of non-standard
input levels, the limiter reduces
the possible output data values
to between 0 and 255 ..
3-443
- MATBYPASS switches the
matrix in bypass. The bypass
has the same propagation delay
as the matrix itself.
Product specification
Philips Semiconductors
Digital colour space converter
SAA7192A
VIDEO LOOK-UP TABLE AND OUTPUT STAGE
MAT1 ---f--4---------I
MAT2
~-+--VLUT1
-~I---+-_+--___i
~-+--VLUT2
MAT3---*--~~-r--~
~-+--VLUT3
MCB560-1
DATAVALID
VLUTSELECT
Fig.20 Block diagram video look up table.
June 1991
3-444
Philips Semiconductors
Product specification
Digital colour space converter
SAA7192A
Functional description
The VLUTLOAD will be set to the
WRITE operation if one of the four
addresses are received from the
RAMs. VLUTLOAD will be set to the
READ operation following reception
of the last databyte.
DATAVALID
serial data
input/output -
VLUTLOAD
serial clock _
input
VLUTSELECT provides selection of
one VLUT according to the
sub-address.
VLUTDATA
12C-bus_
address
12C -BUS
RECEIVER
RESET-
VLUTDATA contains the value for
the address counter
(VLUT_ADDRESS; the start
address of the first byte to be written
into the RAM) and the data for the
RAMs, validated with DATAVALID.
The databytes will be loaded by an
autoincrement function.
VLUTBYPASS will bypass the
VLUT's in clock period time (real
time switch).
In computer applications the VLUT
is also known as a Colour Look-Up
Table (CLUT).
In the DCSC this table might be
used to invert the Gamma-correction
of a camera. This correction is
applied to compensate for the
non-linear relationship between the
video voltage applied to the cathode
and the light output of the phosphor
of a CRT.
12C - bus OE
MATBYPASS
FMTCONTROL
clock_AINRESET
MBA959
Fig.21 Block diagram of 12C-bus receiver
12C-bus Receiver Functional
Description
Following power-up, all internal
control Signals are' at undefined
values. The 12C-bus receiver must
be reset by the external RESET
signal. Following RESET the control
signals are set to:
FMTCNTRL
100 format 4:4:4
o
o
MATBYPASS
INRESET
IICOE
matrix bypassed
input data set to fixed values
OE enabled
The Gamma-correction function
(also known as Gradation) is given
as;
Y = Xy
The VLUT's are realized by 256 x
a-bit RAMs.
FC-bus RECEIVER
The DCSC can be switched to
different functional modes via the
12C-bus receiver. The FC-bus
receiver is also used to feed the
VLUT RAMs with data.
June 1991
VLUTSELECT
3-445
Product specification
Philips Semiconductors
SAA7192A
Digital colour space converter
RECEIVER ORGANISATION
Ae AS A4 A3 A2 A1 AO R/W
1111111 0 1010lXlOI
IL
MBA961
write only
hardware programmable
address bit
(1 2 C - bus_address)
Fig.22 The address for the DC8C
THE CONTROL BYTE
DCSC ADDRESS
SUB - ADDRESS
CONTROL BYTE
S:= Start
A : = Acknowledge
P: = Stop
see Table
MBA962
Fig.23 The address of the control byte is OOHEX
In this example the control signals are set to:
FMTCNTR
L
2
MAT BY PA
88
·-
INRESET
·-
IICOE
·-
June 1991
4:2:2
DM8D
Format 3
matrix in use
0
input DATA at fixed values during
HREF =0
OE enabled
·3-446
Product specification
Philips Semiconductors
Digital colour space converter
SAA7192A
Table 20 Levels of the colour bar signal
CONDITION
White
E'R
E' G
E'
1.0
1.0
1.0
Y
CR
CB
R
G
B
235
128
128
235
235
235
B
0
0
0
16
128
128
16
16
16
1.0
0
0
82
240
90
236
17
16
Green
0
1.0
0
145
34
54
16
236
17
Blue
0
0
1.0
41
110
240
16
16
235
Black
Red
Yellow
1.0
1.0
0
210
146
16
235
235
16
Cyan
0
1.0
1.0
170
16
166
16
235
236
1.0
0
1.0
106
222
202
235
15
234
Magenta
Note
The colour bar signal is described in CCIR 601, Rep. 629-2, Table 1. It can be u.,ed to check the nominal levels (at
least for black and white) between the functional blocks of the OCSC.
Table 21 Control byte formats
07
06
05
04
03
02
01
x
x
x
x
x
0
0
x
x
x
x
x
0
0
00-02
FMTCONTROL
03
MATBYPASS
input formatter at format 0
04
INRESET
Filter switched to 4:1:1 filter
05
IICOE
06
not used
input formatter at format 1
07
not used
DO Functions
0
1
Filter switched to 4:1:1 filter
x
x
x
x
x
0
1
0
input formatter at format 2
Filter switched to 4:2:2 filter
x
x
x
x
x
0
1
1
input formatter at format 3
Filter switched to 4:2:2 filter
x
x
x
x
x
1
0
0
input formatter at format 4
Filter switched to bypass
x
x
0
x
x
x
matrix bypassed
x
x
x
x
x
x
1
x
x
x
matrix in use
x
x
x
0
x
x
x
x
input data at fixed values
x
x
x
1
x
x
x
x
input data to formatter
x
x
0
x
x
x
x
x
output stages tri-state
x
x
1
x
x
x
x
x
OE enabled
June 1991
3-447
Product specification
Philips Semiconductors
SAA7192A
Digital colour space converter
Table 22 Sub-addresses VLUTDATA:
VLUTDATA
Four sub-addresses are
implemented to convey data into the
different VLUT RAMs. RAM can be
addressed individually or together.
The memory of each VLUT RAM
can be addressed, e.g. if only parts
of the data has to be changed.
DATA BYTEs
SUB-ADDRESS
VLUT-ADDRESS
01
VLUTDATA RAM 1 (RED)
02
xx
xx
03
xx
VLUTDATA RAM 3 (BLUE)
04
xx
VLUTDATA RAM 1, 2, 3
VLUTDATA RAM 2 (GREEN)
Note
(") addresses in HEX representation
MBA963
S :=Start
A : = Acknowledge
P: = Stop
Fig.24 Sub-addresses VLUTDATA
12C-bus receiver timing examples
The exact timing of the signals are
described in the 12C-bus
specification. The addresses
indicated in the FIG. 25 are in HEX
representation.
June 1991
3-448
L
'"U
c:
:::J
m
0
cO·
-"
(0
==+
~
Po>
-
0
0
0
c:
....,
en
SDA
L..Jr------.........._----
___ F
~
'0'
(JI
(j)
m
3
o·
0
:::J
a.
c:
(')
0
en
'"C
Po>
0
CD
0
0
:J
<
CD
::+
SCL
t MSB
LSB
S
CD
....,
t t t MSB
LSB
A
slave address DCSC (EO)
t t t MSB
A
subaddress (00)
LSB
t t t
A
P
DATA for control register (4A)
UJ
t
MBA956
<0
S : = START condition
.A : = acknowledge from DCSC
P : = STOP condition
en
»
»
""
.....L
Fig.25 Example of control register loading.
CO
F\)
»
'"U
aa.
c:
n
(JI
~
(')
~
o·
:::J
c....
'1J
C
0
::J
(1)
<0
~
S"
CJ)
0
,5"
0
SDA
--"LJ
r-L.- - -
___
--I.--~
-
0
c
...,
L
g
0
I
I
~ ~rl38
. . GENERATOR
~--
~
5
(")
a.
(')
HS."C>
ft.""
SYNCHRONIZATION
~
-
<
0:
Q.
...,
clockA'
J.
Q)
(J)
en
CD
2,
::+
~
statue
,
::+
g
-0'
a.
z
REGISTER
4
~!J~
Q cg .....
J
LUMINANCE
PROCESSOR
H
clock
STATUS
GPSW2 32
4-
13
CD <»00
UV(7-Q}
~
.".
i
CGC
!I!~~g
L ________ 2
INTERFACE
.§Q!.
f~
HREF
INPUT
OPSW,
Q:~ ~ ~
~g,~g
ICTST
I
13108
r-+
g:
____
:
(J)
!.f'
,_! ~7
,
SAA7194 decoder part
CHR(7~) 1
~~~&
cg. ... 0'
RTCO
+5V
\J
0
«5'
I.
125
+
control and
l2e I2s
+ + +
HSY HCL LFCO
Bot
~
RTS1
+
RTSO
9;
It-sv +
VSSA VOOA
ltatuefrom
\J
8.c
XTAL XTALI CREF
LLC
!l
ecaIer part
(J)
"CD
(")
U>
Ag.1 (a) Block diagram of decoder part; (continued in Fig. 1(b) on page 6).
»»
""
......
co
~
~
(")
~
0
:::I
~::r
0
::I.
0-
3
Product specification-short form
Philips Semiconductors Video Products
SAA7194
Digital video decoder and scaler circuit (DESC)
SOA
sa.
IICSA
....
.:
..
+5V
10
11
12
13
I
...
17
II
II
20
21
22
23
24
, HSY
21
21
: HCL
:RTCX
: RTSI
:RTSO
44
34
35
37
BTST
43
33
32
f'oof1.
. ~ Ir:o-e.........r·~"I--V.,__
. 7.o.1u1
,AESN
,u.c
:u.ca
Fig.34 Application of SAA7194.
April 1994
3-456
4ft(
Philips Semiconductors Video Products
Product specification
Digital video decoder, scaler,
and clock generator (DESCPro)
SAA7196
1. FEATURES
2. GENERAL DESCRIPTION
• Digital 8-bit luminance input (video (V) or CVBS)
• Digital 8-bit chrominance input (CVBS or C from
CVBS, VIC, S-video (S-VHS or Hi8))
• Luminance and chrominance signal processing for
main standards PAL. NTSC and SECAM
• Horizontal and vertical sync detection for all standards
• User programmable luminance peaking for aperture correction
• Compatible with memory-based features (Iinelocked clock, square pixel)
• Cross colour reduction by chrominance comb filtering for NTSC or special cross-colour cancellation
for SECAM
• UV signal delay lines for PAL to correct chrominance phase errors
• Square-pixel format with 768/640 active samples
per line
• The bidirectional Expansion Port (VUV-bus) supports data rates of 780 x fH (NTSC) and 944 x fH
(PAL, SECAM) in 4:2:2 format
• Brightness, contrast, hue and saturation controls
for scaled outputs
• Down-scaling of video windows with 1023 active
samples per line and 1023 active lines per frame to
randomly sized windows
• 2D data processing for improved signal quality of
scaled luminance data, especially for compression
applications
• Chroma key (a.-generation)
• VUV to RGB conversation including Anti-gamma
ROM tables for RGB
• 16-word output FIFO (32-bit words)
• Output configurable for 32/24/16-bit video data bus
• Scaled 16-bit 4:2:2 VUV output
• Scaled 15-bit RGB (5-5-5+a.) and 24-bit (8-8-8+a)
output
• Scaled 8-bit monochrome output
• Line increment, field sequence (odd/even, interlace/non-interlace) and vertical reset control for
easy memory interfacing
• Output of discontinuous data bursts of scaled video
data or continuous data output with corresponding
qualifier signals
• Real-time status information
2
• 1 C-bus control
• Only one crystal of 26.8 MHz
• Clock generator on chip
The CMOS circuit SAA7196, digital video decoder,
scaler and clock generator (DESCPro), is a highly
integrated circuit for DeskTop Video applications. It
combines the functions of a digital multistandard
decoder (SAA7191 B), a digital video scaler
(SAA7186) and a clock generator (SAA7197).
The decoder is based on the principle of line-locked
clock decoding. It runs at square-pixel frequencies to
achieve correct aspect ratio.
Monitor controls are provided to ensure best display.
Four data ports are supported:
Ports CVBS(7-0) and CHR(7-0) of the input interface
are used in V/C mode (Fig.1 (a) on page 5) to decode
digitized luminace and chrominance signals (digitized in two external ADCs).
In normal mode, the CVBS(7-0) input is only used,
and only one ADC is neccessary (Fig.3 on page 12).
The 32-bit VRAM output port is interface to the video
memory; it outputs the down-scaled video data.
Different formats and operation modes are supported by this circuit.
The 16-bit wide Expansion Port is a bidirectional
port. In general, it establishes the digital VUV as
known from the SAA 71 x1 family of digital decoders.
In addition, the Expansion port is configurable to
send data from the decoder unit or to accept external
data for input into the scaler. In input mode the clock
rate and/or the sync signals may be delivered by the
external data source.
Decoder and scaler units can run at different clock
rates. The decoder processing always operates with
a line locked clock (LLC). This clock is derived from
the CVBS signal and is suited best for memory
based video processing; the LLC clock is always
present. The scaler clock may be driven by the LLC
clock or by an external clock depending on the configuration of the Expansion port.
The circuit is 12C-bus-controlled. The 12C-bus interface is clocked by LLC to ensure proper control.
The 12 C-bus control is identical to that of SAA7194. It
is divided into two sections:
- subaddress OOh to 1F for the decoder part (Tables
9 and 10)
- subaddress 20h to 3F for the scaler part (Tables 11
and 12)
The programming of the subaddresses for the scaler
part becomes effective at the first vertical sync pulse
VS after a transmission.
April 1994
3-457
Philips Semiconductors Video Products
Product specification
Digital video decoder, scaler,
and clock generator (DESCPro)
SAA7196
3. QUICK REFERENCE DATA
MAX.
TYP.
UNIT
PARAMETER
MIN.
Voo
supply voltage
4.5
5
5.5
V
100 tot
total supply current
-
180
280
rnA
VI
data input level
TTL-compatible
Vo
data output level
TTL~compatible
LLC
input clock frequency
-
32
MHz
Tamb
operating ambient temperature range
0
70
°c
SYMBOL
-
4. ORDERING INFORMATION
EXTENDED TYPE
NUMBER
SAA7196
April 1994
PACKAGE
PINS
PIN POSITION
MATERIAL
CODE
120
QFP
plastic
SOT349AA1
3-458
»
~
~
m
o
RTCO
+5V
co
r
<0
+5V
internally
~~
~
o
connt cted
V DD1 to V DD7
RESN
36
....
V SS1 to V SS7
14,31,45,61,
16,30,47,60,
77,91,106
75,104,120
176 ,105
44
"
~~
,
c
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CTST
37
15
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....
PORT AND
STATUS
G~PSW2 32
SCL 4
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V DD
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clock A
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LUMINANCE
PROCESSOR
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f"
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CV S(7-0) 24 to 17
o
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CHROMINANCE PROCESSOR
~
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CD
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r-
SYNCHRONIZATION
~
CLOCK A
GENERATOR
f-~
25
5
,
IICSA
control and
26
,
34
28
,
HSY HCL LFCO
,
RTSl
35
~
RTSO
29
27
P:,j~
1
....
...
1
1
~
1
2 40 138
, ,
f+-5V ....
V SSA V DDA XTAL XTALI CREF
status from
scaler part
Fig.1 (a) Block diagram of decoder part; (continued in Fig.1 (b) on page 6).
""U
a
LLC
(J)
»
»
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co
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VOEN
VCLK
BTST
CO
~
I
I
I
I
I
I
I
I
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VERTICAL FILTER '()"""
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VSS
:
I
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f--+
CI:>
J::::>
>-
~
f-+--
~
Y
~
I-
U
V
~
t
L
I
CHROMA
DECIMATION
FILTER
FOLLOWED
BY
ANTI-GAMMA
ROMs
J:
a:
r!L
INTERPOLATOR
V
CHROMA
KEYER
r-h
~
~
~
SCALE CONTROL
t- ~
Y(7-0)1
VS I
CRER
LLC· I
l
CREFINB
Jo.
.....
--'"
.~
.~
J
YUV
11!;-0)
puvoutp
96 to 103
107 to 114
,
41
95 /115 116 117 39
'ir
,.
,ir
,
LLCINB ..... GENERATOR r--tcIOCk B
to scaler and
brightness,
contrast
saturation
controls
42
::Jo.
(1)
(1)
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a.
c
~
en
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00.
~ r--+
rM r--+
46
48
49
50
51
INCADR
VMUX
~
go
_.Ol
r-+ -
_(1)
HFL
..... SODD
52
""""(1)
o~.CJ)
-""""
SVS
SHREF
POO
LNO
0""""
m
en
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--a
~ir
SAA7196 scaler part
118
119
AP
r.:~
HREF
(1)0
3
:J
CLOCKB
BUS INTERFAcE
r
32-bitVRAM
port output
RGBorYUV
~
~
--.
i
o <
~C:
co (1)
en
f{?
""""0
~
HREFI
UV(7-0~
OUTPUT
FIFO
REGISTER
1
>
"
~~ VRO (31 to 0);
r--
(J)
ROoutputs
57to59
6 2to74
7 8to90
9'2 to 94
OUTPUT
FORMATTER
r-4
~
w ....
~
~ ~
"
U.LO
Voo
LINE
MEMORY
(8x384)
BRIGHTNESS
CONTRAST
AND
SATURATION
CONTROLS
(BCS)
~
.;,..
LUMINANCE
DECIMATION
FILTER
RGB
MATRIX
.-
-0
~
-6.
SP
r,:,.
CREFB
-0
Expansion Port
Fig.1 (b) Block diagram of brightness, contrast, saturation controls and scaler
part; (continued from Fig.1 (a) on page 5).
en
»
»
-....J
....L
CO
(J)
aa.
c
s.en
"0
CD
2;
o·
III
e.
0
:J
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
6. PINNING
SYMBOL
PIN
STATUS
DESCRIPTION
XTAL
1
0
26.8 MHz crystal oscillator output, not used if TTL clock signal is used
XTALI
2
I
26.8 MHz crystal oscillator input or external clock input (TTL, squarewave)
SDA
3
1/0
12 C-bus data line
SCL
4
I
5
I
CHRO
6
I
CHR1
7
I
CHR2
8
I
CHR3
9
I
CHR4
10
I
CHR5
11
I
CHR6
12
I
IICSA
CHR7
13
I
V DD1
14
CTST
15
-
V SS1
16
CVBSO
17
I
CVBS1
18
I
CVBS2
19
I
CVBS3
20
I
CVBS4
21
I
12 C-bus clock line
2
1 C-bus set address
digital chrominance input Signal (bits 0 to 7)
+5V supply voltage 1
connected to ground (clock test pin)
GND1 (OV)
digital CVBS input signal (bits 0 to 7)
CVBS5
22
I
CVBS6
23
I
CVBS7
24
I
HSY
25
0
horizontal sync indicator output (programmable)
HCL
26
0
horizontal clamping pulse output (programmable)
V DDA
27
-
+5V analog supply voltage
LFCO
28
0
line frequency control output signal to CGC (multiple of present line frequency)
V SSA
29
analog ground (OV)
V SS2
30
GND2 (OV)
April 1994
3-461
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SYMBOL
PIN
SAA7196
STATUS
DESCRIPTION
general purpose output 2 (settable via 12 C-bus)
+5V supply voltage 2
V OO2
31
GPSW2
32
0
GPSW1
33
0
general purpose output 1 (settable via 12C-bus)
,
RTS1
34
0
real time status output 1; controlled by RTSE-bit
RTSO
35
0
real time status output 0; controlled by RTSE-bit
RESN
36
0
reset output, active low
CGCE
37
I
enable input for internal CGC (connected to +5V)
CREF
38
0
clock qualifier output (test only)
CREFB
39
1/0
clock reference qualifier input/output (HIGH indicates valid data on Expansion port)
LLC
40
0
line-locked video system clock output, for frontend (ADC's) only; frequency: 1888*fH for 50Hz/
625 lines per field systems and 1560*fH for 60 HZ/525 lines per field systems
LLCB
41
1/0
line-locked clock signal input/output, maximum 32 MHz (twice of pixel rate in 4:2:2);
frequency: 1888*fH for 50HZ/625 lines per field systems and 1560*fH for 60 HZ/525 lines per
field systems; or variable input clock up to 32 MHz in input mode
LLC2
42
0
line-locked clock signal output (pixel clock)
BTST
43
I
connected to ground; BTST
=HIGH sets all outputs (except pins 1,28, 38, 40 and 42) to
high-impedance state (testing)
RTCO
44
0
real time control output
V OD3
45
I
+5V supply voltage 3
VMUX
46
I
VRAM output multiplexing, control input for the 32- to 16-bit multiplexer (Table 4 on page 23)
VSS3
47
SODD
48
0
odd/even ,field sequence reference output related to the scaler output (test only)
GND3 (OV)
SVS
49
0
vertical sync signal related to the scaler output (test only)
SHREF
50
0
delayed HREF signal related to the scaler output (test only)
PXQ
51
0
pixel qualifier output signal to mark active pixels of a qualified line (polarity: OPP-bit;test only)
LNQ
52
0
line qualifier output signal to mark active video phase (polarity: OPP-bit; test only)
VOEN
53
I
enable input of VRAM output
HFL
54
0
FIFO half-full flag output signal
INCADR
55
0
line increment I vertical reset control output
VCLK
56
I
VR031
57
0
VR030
58
0
VR029
59
0
V SS4
60
-
April 1994
clock input ,signatQf FIFO output .
32-bit digital VRAM olltput port (bits 31 to 29)
GND4(OV)
3-462
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SYMBOL
PIN
VOD4
61
DESCRIPTION
STATUS
+5 V supply voltage 4
VR028
62
0
VR027
63
0
VR026
64
0
0
VR025
65
VR024
66
0
VR023
67
0
VR022
68
0
VR021
69
0
VR020
70
0
VR019
71
0
VR018
72
0
VR017
73
0
VR016
74
0
Vsss
75
i.c.
76
VODS
77
0
VR015
78
VR014
79
0
VR013
80
0
0
VR012
81
VR011
82
0
VR010
83
0
VR09
84
0
VR08
85
0
VR07
86
0
VR06
; 87
0
VR05
88
0
VR04
89
0
VR03
90
0
April 1994
SAA7196
32-bit VRAM output port (bits 28 to 16)
GND5 (OV)
internally connected
+5V supply voltage 5
32-bit VRAM output port (bits 15 to 3)
3-463
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
SYMBOL
PIN
STATUS.
DESCRIPTION
V DD6
91
-
+5V supply voltage 6
VR02
92
VR01
93
32-bit VRAM output port (bits 2 to 0)
VROO
94
a
a
a
DIR
95
I
direction control of Expansion Bus
YUV15
96
I/O
YUV14
97
I/O
YUV13
98
I/O
YUV12
99
I/O
YUV11
100
I/O
YUV10
101
I/O
YUV9
102
I/O
YUV8
103
I/O
VSS6
104
i.e.
105
digital 16-bit video input/output signal (bits 15 to 8): luminance (Y)
GND6 (OV)
-
internally connected
V OO7
106
YUV7
107
I/O
YUV6
108
I/O
YUV5
109
I/O
YUV4
110
I/O
YUV3
111
I/O
YUV2
112
I/O
YUV1
113
I/O
YUVO
114
I/O
HREF
115
I/O
horizontal reference signal
VS
116
I/O
vertical sync input/output signal with respect to the YUV input signal
HS
117
a
horizontal sync signal, programmable
AP
118
I
connected to ground (action pin for testing)
SP
119
I
connected to ground (shift pin for testing)
V SS7
120
April 1994
+5V supply voltage 7
digital 16-bit video input/output signal (bits 7 to 0): colour-difference signals (UV)
GND7 (OV)
3-464
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
PIN CONFIGURATION
VR03
XTAL
VR04
XTALI
VR05
SDA
VR06
SCL
VR07
IICSA
5
CHRO
VR09
CHR1
VR010
CHR2
VR011
CHR3
VR012
CHR4
VR013
CHR5
VR014
CHR6
VR015
CHR7
V005
V001
i.e.
CTST
VSS1
VR08
SAA7196
VSS5
CVBSO
VR016
CVBS1
VR017
CVBS2
VR018
CVBS3
VR019
CVBS4
VR020
CVBS5
VR021
CVBS6
VR022
CVBS7
VR023
HSY
VR024
HCL
VR025
VOOA
VR026
LFCO
VR027
VSSA
VR028
VSS2
V0 0 4
Fig.2 Pin configuration.
April 1994
3-465
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
The frequency is dependent on the present colour
standard. The signals are low-pass filtered and
amplified in a gain-controlled amplifier. A final
. low-pass stage provides a correct bandwidth performance.
7. FUNCTIONAL DESCRIPTION
7.1. FUNCTIONAL DESCRIPTION
DECODER PART
PAL, NTSC and SECAM standard colour signals
based on line-locked clock are decoded (Fig.25 on
page 41). In YIC mode (Fig.1 (a) on page 5), digitized
luminance CVBS(7-0) and chrominance CHR(7-0)
Signals - digitised in two external ADCs - are input. In
normal mode only CVBS(7 -0) is used.
The data rate is 29.5 MHz (50 MHz systems) or
24.54 MHz (60 MHz systems).
PAL signals are comb-filtered to eliminate crosstalk
between the chrominance channels according to
PAL standard requirements.
NTSC signals are comb-filtered to eliminate crosstalk from luminance to chrominance for vertical structures.
Chrominance processor
The input Signal passes the input interface, the
chrominance bandpass filter to eliminate DC components, and is finally fed to the multiplicator inputs of a
quadrature demodulator, where two subcarrier signals (0° and 90° phase-shifted) from a local digital
oscillator (DT01) are applied.
SECAM signals are fed through a cloche filter, a
phase demodulator and a differentiator to achieve
proportionality to the instantaneous frequency. The
Signals are de-multiplexed in the SECAM recombination stage after passing a de-emphasiS stage to
provide the two serially transmitted colour-difference
Signals.
+127 f - - - - - - - . . - - - - - - - - - - - +106
+95
o
white (60 Hz mode)
white (50 Hz mode)
luminance
60 Hz mode
chrominance
60 Hz mode
luminance
50 Hz mode
chrominance
50 Hz mode
o
-52
I----+----'"-----f--
-64
I---~-
blanking level
black (60 Hz mode)
=black (50 Hz mode)
______ r __
-91
-103 I- - - - - - - - - - - - - - - - - - - - - - - - - -
Notes: All levels are related to EBU colour bar.
Values in decimal at 100% luminance
and 75% chrominance amplitude.
-128
-132 I
Fig.3 CVBS(7 -0) input signal ranges.
April 1994
3-466
Product specificatien
Philips Semicenducters
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
The PLL fer quadrature demedulatien is clesed via
the cleche filter (to' impreve neise perfermance), a
phase demedulater, a burst gate accumulater, a leep
filter PI1 and a discrete time escillater DT01. The
gain centrelleep is clesed via the cleche filter, amplitude detecter, a burst gate accumulater and a leep
filter P12.
The Expansien pert is a bidirectienal interface fer
digital videO' signals YUV(15-0) in 4:2:2 fermat (Table
2 en page 15). External videO' signals can be
inserted to' the scaler er deceded videO' signals ef the
deceder part can be eutput.
The data directien is centrelled by pin 95
(DIR=HIGH: data frem external; Table 1 en page 14).
The sequence precesser switches signals accerding
to' standards.
YUV(15-0), HREF, VS, LLCB and CREFB pins are
input when bits OECL, OEHV, OEYC ef subaddress
OE are set to' "0". Different medes are previded (timing see Figures 5 and 6 en page 16 and page 17):
Luminance processor
The data rate ef the input signal is reduced to' LLC2
frequency by a sample rate cenverter in the input
interface. The high frequency cempenents are
emphasized in a prefilter to' cempensate fer lesses in
the succeeding chreminance trap. The chreminance
trap is adjusted to' a center frequency ef 3.58 MHz
(NTSC) er 4.4 MHz (PAL, SECAM) to' eliminate mest
ef the celeur carrier cempenents. The chreminance
trap is bypassed fer S-VHS signals.
The high frequency cempenents in the luminance
signal are "peaked" using a bandpass filter and a
cering stage.The "peaked" (high frequent) cempenent is added to' the "un peaked" signal part fer
sharpness imprevement and eutput via variable
delay to' the Expansien-Bus.
Synchronization
The sync input signal is reduced in bandwidth to'
1 MHz befere it is sliced and separated frem luminance signal. The sync pulses are cern pared in a
detecter with the divided cleck signal ef a ceunter.
The resulting eutput signal is fed to' a leep filter that
accumulates all the phase deviatiens. Thereby, a
discrete time escillater DT02 is driven generating
the line frequency centrel signal LFCO. An external
PLL generates the line-Iecked cleck LLC frem the
signal LFCO.
A neise-limited vertical deflectien pulse is generated
fer vertical processing that alsO' inserts artificial
pulses if vertical input pulses are missing.
50/60 Hz as well as edd/even field is autematically
detected by the identificatien stage.
Mede 0:
All bidirectienal terminals are eutputs. The signal ef
the deceder part (internal YUV(15-0)) is switched to'
be scaled.
Mede1:
External YUV(15-0) is input to' the scaler. LLCB/
CREFB cleck system and HREFNS frem the
SAA7196 are used to' centrel the external seurce. It
is pessible to' switch between Mede 0 and Mede 1 by
means ef DIR input (FigA en page 15).
Pixelwise switching ef the scaler seurce is pessible
because the internal cleck and sync seurces are
used.
Mede 2:
External YUV(15-0) is input to' the scaler. LLCB/
CREFB cleck system and HREFNS frem external
are used.
Mede 3:
YUV(15-0) and HREFNS terminals are inputs.
External YUV(15-0) is input to' the scaler with HREF/
VS reference frem external. LLCB/CREFB cleck system ef the SAA7196 is used.
7.2. FUNCTIONAL DESCRIPTION
EXPANSION PORT (Fig.1 (b) en page 6)
April 1994
3-467
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
7.3. MONITOR CONTROLS
(BCS; Fig.1 (b) on page 6)
BRIGHTNESS AND CONTRAST CONTROLS:
The luminance signal can be controlled via 12 C-bus
(Table 9 on page 32) by the bits BRIG(7-0) and
CONT(6-0).
Brightness control:
00 (hex)
80 (hex)
FF (hex)
value
minimum offset
CCIR level
maximum offset
Contrast control:
00 (hex)
40 (hex)
7F (hex)
value
luminance off
CCIR level
1.9999 amplitude
SATURATION CONTROL:
the chrominance signal can be controlled via 12 C-bus
(Table 9 on page 32) by the bits SAT(6-0) and
HUE(7-0).
Saturation control:
value
00 (hex)
colour off
40 (hex)
CCIR level
7F (hex)
1.9999 amplitude
Clipping:
All resulting output values are clipped to minimum
(equals 1) and maximum (equals 254).
Table 1 Operation modes
12 C BIT
OEYC OEHV OECL
MODE
0
1
2
3
1
X
X
X
X
April 1994
1
1
0
0
1
1
0
1
DlR
PINgS
YUV
0
LOW
HIGH
HIGH
HIGH
I
I
I
INPUT SOURCE
HREF VS
LLCB CREFB
0
0
0
0
I
I
I
I
0
0
I
0
= don't care; I = input to monitor control/scaler; 0 = output from decoder
3-468
0
0
I
0
Philips Semiconductors
Product specification
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
Table 2 YUV-bus format on Expansion Port
PIN
SIGNALS ON EXPANSION PORT (PIXEL BYTE SEQUENCE ON PINS)
YUV1S
YUV14
YUV13
YUV12
YUV11
YUV10
YUV9
YUV8
Ye7
Ye6
YeS
Ye4
Ye3
Ye2
Ye1
YeO
Yo7
Yo6
YoS
Yo4
Yo3
Yo2
Yo1
YoO
Ye7
Ye6
YeS
Ye4
Ye3
Ye2
Ye1
YeO
Yo7
Yo6
YoS
Yo4
Yo3
Yo2
Yo1
YoO'
Ye7
Ye6
YeS
Ye4
Ye3
Ye2
Ye1
YeO
YUV7
YUV6
YUVS
YUV4
YUV3
YUV2
YUV1
YUVO
Ue7
Ue6
UeS
Ue4
Ue3
Ue2
Ue1
UeO
Ve7
Ve6
VeS
Ve4
Ve3
Ve2
Ve1
VeO
Ue7
Ue6
UeS
Ue4
Ue3
Ue2
Ue1
UeO
Ve7
Ve6
VeS
Ve4
Ve3
Ve2
Ve1
VeO
Ue7
Ue6
UeS
Ue4
Ue3
Ue2
Ue1
UeO
Pixel order
n
n+1
n+2
n+3
n+4
e = even pixel number; 0 = odd pixel number
LLCB
--+!
HREF
I
I
I"/':
I
UVdec
(from decoder)
UVext
(from Ext. Port)
I
:
~
II
I
II
II
I
I:
:-tl
I
I
I
I
I
1-+1
I tHD
~
'&iiiJJA
tl rom 3-state min = 1.5 LLC
+ tpz min
tlrom 3-slate > tto 3-state
t lo 3-stale max
=1.5 LLC + tpz max
tpz W'",,'.w
""""""m¥n
....
: - - 4 - - - - - - - + - - - - - ' . . . . - - - - - - ' -_ _
I+-
-+:toH:~
~=-~==~1===+1~~~~1~=1~
ua dec
UV to scaler
I
I
••
DIR
to 3-state
I
CREFB
--~
va dec
U2 ext
V2 ext
U4 dec
V4 dec
FigA Real-time switching between Mode 0 and Mode 1 (internal/external YUV(1S-0))_
April 1994
3-469
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
(a) 1st field
SAA7196
625
2
3
4
5
6
7
8
9
I
I
I
I
I
I
I
I
I
inputCVBS
HREF
:-1
vs
-.1 :.- 1 x 21LLC
ODD (RTSO)
I
(b) 2nd field
313
314
315
316
317
318
320
319
321
I
I
input CVBS
HREF
+--:.-- 68 x 21LLC
I'
~I
VS
ODD (RTSO)
--.j
1
~
1 x 21LLC
50 Hz
(a) 1st field
525
2
3
4
5
6
7
8
9
I
I
I
I
I
I
I
I
I
input CVBS
HREF
~
VS
1l1li
1
I
448 x 21LLC
I
ODD (RTSO)
(b) 2nd field
263
264
265
266
267
268
269
-.j ~+-
1 x 21LLC
270
271
~
58x2lLLC
inputCVBS
HREF
vs
il
~
ODD (RTSO)
60 Hz
Fig.5 VS and ODD timing on Expansion Port.
April 1994
3-470
:..- 1 x 21LLC
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
,0
~~62X2/LLC_
~
CVBS
:
SAA7196
~~___b_ur_st__~)~---------------
,
4.
HSY
HSY
programming range
(step size: 21LLC)
,
,
+191
+127
programming range
(step size: 21LLC)
,0
-64
:
,
, $
,
'
~,h(:--------41----------~1
,
HCl
HCl
'
,
+4
-128
:0
~/,
,
7~~(--------------~
~,..L---- 216 LLC , - - - ' - - - - - - -••,
processing delay CVBS - YUV '
atYDEL=OOOb
'
~10x2lLLC
N:
V-output
,
"
,
~\ _____________
h'--!d
",""
- - - - - - - - 768 x 21LLC
_
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _L'_ _ _ _
:
,III
HS (50 Hz)
'
.:~
104x2JLLC
programming range
(step size: 8/LLC)
1
:0
1
'36 x 21LLC:
'~
,
HS (60 Hz)
.'
_
_
_
_
_
140 x 21LLC
64 x 21LLC
,
+97
~
, - - - I
.,~
_
.~
_- - - - - /
1
.~
-97
,
,0
;(~
~------~;~~(---r----------------------------------~
Fig.6 Horizontal sync timing at HRMV =0 and HRFS =0
(signals HSY, HCl, HREF, PUN and HS (50/60 Hz)).
April 1994
-118
~I--------~'/r(/--~,-----+,----------------------------~)/~
640 x 2JLLC
programming range
(step size: 8/LLC)
.',
64 x 21LLC
I ,
HREF (60 Hz)
HS (60 Hz)
i~-------~
_________________J;_13O x 21LLC ,
+117
.,~
176 x 21LLC
~:------------------~
!~
HS (50 Hz)
r-------~~
------II
HREF (50 Hz)
PUN (RTS1)
(50 Hz only)
J
/
3-471
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
LLCB
CREFB
I
I
I
HREF
/..
I
I
I
active line I
---' _ _- i
Byte numbers for pixels:
I
i"- start of
I
Y signal
50 Hz
U and V signal _ _ _J
Y signal
60 Hz
U and V signal _ _----'
LLCB
CREFB
I
HREF
I
I
Byte numbers for pixel~:
Y signal
50 Hz
U and V signal -
Y signal
60 Hz
U and V signal -
Fig.? Horizontal and data multiplex timing on Expansion Port.
April 1994
3-472
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
+254
+235
f------
- - - - - - - - white 100%
+ 128 r - - - - + - - -
+254!--+240
blue 100%
+254
+240
+212 - - - - - - - - - blue 75%
+212
+ 128 r - - - - + - - -
+ 128 r - - - - t - - -
1- ----_-_-- -
luminance
levels
+16
1
SAA7196
f------
- - - - - - - - red 100%
- - -
U-component
levels
+44 r- - -
--_1_ ---
black
+ 16
-~
-
-
red 75%
-
V-component
levels
- - - - yellow 75%
- - - - - - - - yellow 100%
1
(a) Y signal range.
II>- -
(b) U signal range (B-Y).
---~----
+44
cyan 75%
+ 16 - - - - - - - - - cyan 100%
1
(c) V signal range (R-Y).
Fig.B Input and output signal levels on Expansion Port.
RTCO output (pin 44; Fig.9)
dependent on RTSE bit (subaddress OD).
This real-time control and status output signal contains serial information about actual sytem clock,
subcarrier frequency and PAUSECAM sequence.
The signal can be used for various applications in
external circuits, e.g. in a digital encoder to achieve
"clean" encoding.
RTSE = 0: the output RTSO contains the odd/even
field identification bit (HIGH equals odd); output
RTS1 contains the inverted PAUSECAM sequence
bit (HIGH equals non-inverted (R-Y)-line/DB-line).
RTS1 and RTSO outputs (pins 34 and 35)
RTSE = 1: the output RTSO contains the horizontal
lock bit (HIGH equals PLL locked); output RTS1 contains the vertical detection bit (HIGH equals vertical
sync detected).
These outputs can be configured in two modes
H/L transition
(counter start)
4 bits
FSCPLL
increment
bits 22 to 0
I
~
128 clocks
--~·I
1 0
0
11-
_4_ _8_ _
14_ _1_9.. time slot
(LLC/4)
(1) Sequence bit:
SECAM:
0 equals DB-line
1 equals DR-line
PAL:
o equals (R-Y) line normal
1 equals (R-Y) line inverted
NTSC:
0 (no change)
(2) Reserve bits: 276 for 50 Hz systems; 188 for 60 Hz systems
Fig.9 RTCO timing.
April 1994
3 bits
reserve
I
sequence bit (1)
3-473
63
I
I
67
reserved (2)
/
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
7.4. FUNCTIONAL DESCRIPTION SCALER PART
Vertical processing (VPU-Y)
The scaler part receives YUV(15-0) input data in
4:2:2 format.
The video data from the BCS control are processed
in horizontal direction in two separate decimation filters. The luminance component is also processed in
vertical direction (VPU_V).
Chrominance data are interpolated to a 4:4:4 format;
a chroma keying bit is generated.
The 4:4:4 YUV data are then converted from the
YUV to the RGB domain in a digital matrix. ROM
tables in the RGB data path can be used for
anti-gamma correction of gamma-corrected input
signals. Uncorrected RGB and YUV signals can be
bypassed.
A scale control unit generates reference and gate
signals for scaling of the processed video data. After
data formating to the various VRAM port formats, the
scaled video data are buffered in the 16 word 32-bit
output FIFO register. The scaling is performed by
pixel and line dropping at the FIFO input. The FIFO
output is directly connected to the VRAM output bus
VRO(31-0).
Specific reference signals support an easy memory
interfacing.
Luminance data are fed to a vertical filter consisting
of a 384 x 8-bit RAM and an arithmetic block
(Fig.1 (b) on page 6). Sub-sampling and interpolation
operations are applied. The luminance data are
processed in vertical direction to preserve the video
information for small scaling factors and to reduce
artifacts caused by the dropping.
The available modes respectively transfer functions
are selectable by bits VP1 and VPO (subaddress 28).
Adaptive modes, controlled by AFS and AFG bits
(subaddresses 28 and 30) are also available (see
Table 3).
Table 3 Adaptive filter selection (AFS = 1)
scaling ratio
filter function
(refer to 12 C section)
XDIXS
horizontal
~1
~
14/15
~ 11/15
~ 7115
~ 3/15
Decimation filters
YDNS
The decimation filters perform accurate horizontal filtering of the input data stream.
The signal bandwith is matched in front of the pixel
decimation stage, thus disturbing artifacts, caused
by the pixel dropping, are reduced.
The signal bandwidth can be reduced in steps of
(Figures 27 and 28 on page 46):
2-tap filter = -6 dB at 0.325 pixel rate
3-tap filter = -6 dB at 0.25 pixel rate
4-tap filter = -6 dB at 0.21 pixel rate
5-tap filter = -6 dB at 0.125 pixel rate
9-tap filter = -6 dB at 0.075 pixel rate
The different characteristics are choosen independently by 12 C-bus control bits HF2 to HFO when
AFS = 0 (Subaddress 28). In the adaptive mode with
AFS = 1 , the filter characteristics are choosen
dependent on the defined sizing parameters (see
Table 3).
April 1994
~1
~
13/15
~4/15
bypassed
filter 1
filter 6
filter 3
filter 4
vertical
bypassed
filter 1
filter 2
RGB matrix
Y data and UV data are converted after interpolation
into RGB data according to CCIR601 recommendation. Data are bypassed in 16-bit YUV formats or
monochrome modes.
The matrix equations are these considering the digital quantization:
R = Y + 1.375 V
G = Y - 0.703125 V - 0.34375 U
B = Y + 1.734375 U
Anti-gamma ROM tables:
ROM tables are implemented at the matrix output to
3-474
Philips Semiconductors
Product specification
Digital video decoder, scaler
and clock generator circuit (DESCPro)
provide anti-gamma correction of the RGB data. A
curve for a gamma of 1.4 is implemented. The tables
can be used (RTB-bit = a, subaddress 20) to compensate gamma correction for linear data representation of RGB output data.
SAA7196
Vertical scaling region:
Data is scaled with start at line YO and the output
format is selected when FS1 and FSO are valid. This
is the "normal operation" area. The input/output
screen dimensions in horizontal and vertical direction are defined by the parameters
Chrominance signal keyer
The keyer generates an alpha signal to achieve a
5-5-5+<' ~
,,\
o
42h
"" "A\
41h"
40h/
-6
41h"
~
\ ~\
62h--../
\~\
50
.>:::
I} ~
\\\
-12
~I---
IlIA
'III
'61h
'40h
\\1 W
Hz
\1
-18
1/
\
-24
-30
o
2
3
4
6
S
fy(MHz)
Fig.18 Luminance control in 50 Hz / CVBS mode controllable by subaddress byte 06; pre-filter on
and coring off; other aperture bandpass filter characteristics.
April 1994
3-492
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
18
23~"
12
//
6
~~
---
--- ----~
(~e)
~=-- I - - -
0
13h
-6
/33h
.--
~~
1--7
rr
/
/
---
"-
~
13h,
~r"\..
~
'03h
~
'~
OOh
\
!tV
\
o
2
3
~
L33h
11// V"-23h ..---'1/ /
\
\
-24
~
1/ v
'" 1\ \\
\
50 Hz
-18
-30
~
,~
I~
-12
03h,
I
\ I
\\ I
/
V'
'OOh
4
6
fy (MHz)
Fig.19 Luminance control in 50 Hz / CVBS mode controllable by subaddress byte 06; pre-filter off
and coring off; maximum aperture bandpass filter characteristic.
'
18
73h
-f--
~V-
12
63~
(~e)
-
~/ ~
~ (:5<
i"S3h
~~
6
-......
~
~
~~
~
\
~3h
0
\,
60 Hz
J3h
t--
~ ~~
j/:= ~ ~
//; ~
I ~~
II
~ f
1\ I
-6
-12
-
43h
63h
7~h
~
-18
-24
-30
o
2
3
4
5
6
fy(MHz)
Fig.20 Luminance control in 60 Hz / CVBS mode controllable by subaddress byte 06; pre-filter on
and coring off; maximum aperture bandpass filter characteristic.
April 1994
3-493
Philips Semiconductors
Product specification
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
18
61h
12
.......,,,,
42h
/ K
~
/' ~
/
~
~
V-""" ~~[\
~~
41h
v"\ I~\
62~
(~e)
6
0
41~
1\\\
4011'
'/1/ \
\~
60 Hz
-12
=-=::
-..;
\~
\~
-6
42h
~
~
/~ ~ ~
-;;:::::, "~
Iii, ~
62~
W
"40h
61h
-18
-24
-30
o
3
5
4
6
fy(MHz)
Fig.21 Luminance control in 60 Hz / eVBS mode controllable by subaddress byte 06; pre-filter on
and coring off; other aperture bandpass filter characteristics.
18
/33h
12
23h"-."
(~e)
6
~
#' v 13~
~ r::--
- r--
0
--
~
--
-~
~
03h
--.... -..........
...........
-6
OOh/
60 Hz
-12
>..
""
03h,
\
/'"
/V~
\
//, ~
\
\ til 23h
:"-. \ Ii L
\ , II
\ 1\
-18
\\
-24
-30
//
o
2
3
'
r-
r-....)3h
}3h-
~
r-- r-...
~
~
~
~
"OOh
/
I
I
I
II I
4
5
6
fy(MHz)
Fig.22 Luminance control in 60 Hz / eVBS mode controllable by subaddress byte 06; pre-filter off
and coring off; maximum and minimum aperture bandpass filter characteristics.
April 1994
3-494
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
18
18
12
12
__ .1.C3h
(~e)
6
--=
0
--
~ah
lY2h
--.;::: t::::
-~
...-/'
-12
6
4
-18
8
o
2
4
6
fy(MHz)
Fig.24 Luminance control in 50 Hz / S-VHS mode
controllable by subaddress byte 06; pre-filter
on and coring .off; different aperture bandpass filter characteristics.
18
18
12
12
- ---
6
0
83h
(~e)
82h
v
--Z. ~ ~
/
r-- I-81h
60 Hz
-12
4
6
-18
8
fy(MHz)
~ t\ ~h
C1~
~~ ~
~
/"
c~
0
2
4
6
8
fy(MHz)
Fig.25 Luminance control in 60 Hz / S-VHS mode
controllable by subaddress byte 06; pre-filter
off and coring off; different aperture bandpass filter characteristics.
April 1994
3h
=-- 3
60 Hz
-12
2
~
~
0
io;; r---.:
-6
0
...-:
6..../
-6
-18
8
fy(MHz)
Fig.23 Luminance control in 50 Hz / S-VHS mode
controllable by subaddress byte 06; pre-filter
off and coring off; different aperture bandpass filter characteristics.
(~e)
~~
~~
doh
-12
2
C2h
50Hz
-6
o
C1h
0
86h
-6
-18
~
~
/
6
/
81h
50 Hz
(~e)
Fig.26 Luminance control in 60 Hz / S-VHS mode
controllable by subaddress byte 06; pre-filter
on and coring off; different aperture bandpass filter characteristics.
3-495
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
Table 11 12C-bus scaler control; subaddress and data bytes for writing
OATA
OF*
FUNCTION SUBADORESS
07
06
05
04
03
02
01
00
Formats and sequence
Output data pixellline (1)
Input data pixel/line (1)
Horiz. window start (1)
Horizontal filter
20
21
22
23
24
RTB
XD7
XS7
X07
HF2
OF1
XD6
XS6
X06
HF1
OFO
XD5
XS5
X05
HFO
VPE
XD4
XS4
X04
XOS
LW1
XD3
XS3
X03
XS9
LWO
XD2
XS2
X02
XSS
FS1
XD1
XS1
X01
XD9
FSO
XDO
XSO
XOO
XDS
Output data lines/field (2)
Input data lines/field (2)
Vertical window start (2)
AFS/vertical Y processing
25
26
27
2S
YD7
YS7
Y07
AFS
YD6
YS6
Y06
VP1
YD5
YS5
Y05
VPO
YD4
YS4
Y04
YOS
YD3
YS3
Y03
YS9
YD2
YS2
Y02
YSS
YD1
YS1
Y01
YD9
YDO
YSO
Vertical bypass start (3)
Ver1ical bypass count (3)
29
2A
2B
VS7
VC7
0
VS6
VC6
0
VS5
VC5
0
VS4
VC4
VSS
VS3
VC3
0
VS2
VC2
VCS
VS1
VC1
0
VSO
VCO
POE
2C
2D
2E
2F
VL7
VU7
UL7
UU7
VL6
VU6
UL6
UU6
VL5
VU5
UL5
UU5
VL4
VU4
UL4
UU4
VL3
VU3
UL3
UU3
VL2
VU2
UL2
UU2
VL1
VU1
UL1
UU1
VLO
VUO
ULO
UUO
30
VOF
AFG
LLV
MCT
OPL
OPP
TTR
EFE
Chroma keying
lower limit for V
upper limit for V
lower limit for U
upper limit for U
Data path setting
unused
..
Y~O
YDS
31 to3F
(1) continued in ''24'';
(2) continued in "2S";
*) Default register contents fill in by hand;
(3) continued in "2B";
**) Data representation, transfer mode and adaptivity
Table 12 Function of the register bits of Table 11 for subaddresses "20" to "30"
RTB
"20"
OF1
ROM table bypass switch:
= anti-gamma ROM active
1 = table is bypassed .
o
to OFO
Set outpuUield mode:
OF1
OFO
o
o
o
1
o
VPE
April 1994
field mode DVS process
both fields for interlaced storage
both fields for non-interlaced storage
odd fields only (even fields ignored) for non-interlaced storage
even fields only (odd fields ignored) for non-interlaced storage
VRAM port outputs enable:
0= HFL and INCADR inactive (HFL = LOW, INCADR = HIGH); VRO outputs in 3-state
1 = HFL and INCADR enabled; VRO outputs dependent on VOEN
3-496
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
LW1
"20"
to
LWO
First pixel position in VRO data for FS1
FS1
to
FSO
=0; FSO =0 (RGB) and FS1 =0; FSO =1 (YUV):
LW1
LWO
31 to 24
23 to 16
0
0
1
1
0
1
0
1
pixel 0
pixel 0
black
black
pixel 0
pixel 0
black
black
First pixel position in VRO data for FS1
SAA7196
15t08
7toO
pixel
pixel
pixel
pixel
pixel
pixel
pixel
pixel
1
1
0
0
1
1
0
0
)
)
)
)
EFE =0; TIR =0
= 1; FSO =1 (monochrome):
LW1
LWO
31 to 24
23 to 16
15t08
7toO
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
pixel 0
black
black
black
pixel 0
black
pixel 0
black
pixel 1
pixel 0
black
black
pixel 1
pixel 0
pixel 1
pixel 0
pixel 2
pixel 1
pixel 0
black
pixel
pixel
pixel
pixel
X
X
X
X
X
X
X
X
3
2
1
0
)
)
)
EFE = 0; TIR = 0
)
)
)
)
)
EFE = 1; TIR = 0;
LW only effects the
grayscale format
FIFO output register format select (EFE-bit see "30"):
EFE
FS1
FSO
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
output format (Tables 5 and 6)
RGB 5-5-5 + alpha; 2 x 16-bit/pixel; 32-bit word length;
RGB matrix on, VRAM output format
YUV 4:2:2; 2 x 16-biVpixel; 32-bit word length;
RGB matrix off; VRAM output format
YUV 4:2:2; 1 x 16-biVpixel; 16-bit word length;
RGB matrix off, optional output format
monochrome mode; 4 x 8-biVpixel; 32-bit word length;
RGB matrix off, VRAM output format
RGB 5-5-5 + alpha; 1 x 16-biVpixel; 16-bit word length;
RGB matrix on, VRAM output + transparent format
YUV 4:2:2 + alpha; 1 x 16-biVpixel; 16-bit word length;
RGB matrix off; VRAM output + transparent format
RGB 8-8-8 + alpha; 1 x 24-biVpixel; 24-bit word length;
RGB matrix on, VRAM output + transparent format
monochrome mode; 2 x 8-biVpixel; 16-bit word length;
RGB matrix off, VRAM output +transparent format
XD9
to
"21 and 24"
XDO
Pixel number per line (straight binary) on output (VRO):
0000000000 to 11 1111 1111 (number of XS pixels as a maximum; take care of vertical
processing)
XS9
to
"22 and 24"
XSO
Pixel number per line (straight binary) on inputs (YIN and UVIN):
0000000000 to 11 1111 1111 (number of input pixels per line as a maximum; take care of vertical processing)
XOS
to
"23 and 24"
XOO
Horizontal start position (straight binary) of scaling window (take care of active pixel number per
line):
start with 1st pixel after H REF rise = 0 0000 0011 to 1 1111 1111 (003 to 1FF)
Window start and window end may be cut by internal delay compensated HREF 0 phase.
=
April 1994
3-497
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
HF2
"24"
to
HFO
SAA7196
Horizontal deCimation filter:
filter (Figures 27 and 28 on page 4S)
HF2
HF1
HFO
taps
0
0
0
0
0
0
1
1
0
1
0
1
2
3
S
9
filter 1
filter 2
filter 3
filter 4
1
1
0
0
1
1
0
1
1
1
0
1
8
4
filter bypassed
filter bypassed + delay in Y channel of 1T
filterS
filterS
1
1
The filter coefficients are related to the luminance path. The filter coefficient may differ from
upper table when a combination with vertical Y processing and adaptive modes are provided.
YD9
to
"25 and 2S"
YDO
Line number per output field (straight binary):
0000000000 to 11 1111 1111 (number of YS lines as a maximum)
YS9
to
"26 and 2S"
YSO
Line number per input field (straight binary):
00 0000 0000 0 line
11 1111 1111.1023 lines (maximum
YOS
to
"27 and 2S"
YOO
Vertical start of scaling window. Take care of active line number per field (straight binary); window start and window end may be cut by the external VS signal:
a 0000 0000 start with 3rd line after the rising slope of VS
a 0000 0011 start with 1st line after the falling slope of nominal VS (71516, 71916
input)
1 1111 1111 511 + 3 lines after the rising slope of VS (maximum value)
AFS
"2S"
VP1
=number of lines/field - 3)
Adaptive filter switch:
o =off; use VP1, VPO and HF2 to HFO bits
1 =on; filter characteristics are selected by the scaler
to
VPO
Vertical luminance data processing:
VP1
VPO
0
0
1
1
0
1
0
1
processing (approximate equations)
bypassed
delay of one line H(z) =z-H
vertical filter 1: (H(z) =1/2 (1 + z-H»
vertical filter 2: (H(z) =1/4 (1 + 2z-H + z-2H»
VSS
to
"29 and 26"
VSO
Vertical bypass start, sets begin of the bypass region (straight binary). Scaling region overrides
bypass region (YO bits):
a 0000 0000 start with 3rd line after the rising slope of VS
o 0000 0011 start with 1st line after the falling slope of nominal VS (71516, 71916
.
input)
1 1111 1111 511 +, 3 lines after the rising slope of VS (maximum value)
VCS
to
"2Aand 26"
VCO
Vertical bypass count, sets length of bypass region (straight binary):
o 00900000 Oline length
1 1111 1111 511 lines length (maximum =number of lines/field - 3)
POE
April 1994
Polarity, internally detected odd/even flag OlE:
=flag unchanged
1 =flag inverted
o
3-498
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
VL7
"2C"
toVLO
Set lower limit V for colour-keying (8 bit; two's complement):
1000 0000
as maximum negative value = -128 signal level
0000 0000
limit = 0;
0111 1111
as maximum positive value = +127 signal level
VU7
"2D"
to VUO
Set upper limit V for colour-keying (8 bit; two's complement):
10 a a a a a a
as maximum negative value = -128 signal level
0000 0000
limit = 0
0111 1111
as maximum positive value = + 127 Signal level
UL7
"2E"
to ULO
Set lower limit U for colour-keying (8 bit; two's complement):
1000 0000
as maximum negative value = -128 signal level
0000 0000
limit = 0
0111 1111
as maximum positive value = +127 signal level
UU7
"2F"
to UUO
Set upper limit U for colour-keying (8 bit; two's complement):
10 a a a a a a
as maximum negative value = -128 signal level
0000 0000
limit = 0
0111 1111
as maximum positive value = + 127 signal level
SAA7196
VOF
"30"
VRAM bus output format:
= enabling of 32 to 16 bit multiplexing via VMUX (pin 46)
1 = disabling of 32 to 16 bit mUltiplexing via VMUX (pin 46)
AFG
Adaptive geometrical filter:
o = linear H· and V data processing
1 = approximated geometrical H and V interpolation (improved scaling accuracy of
,
luminance)
LLV
Luminance limiting value:
o = amplitude range between 1 and 254
1 = amplitude range between 16 and 235, suitable for monochrome and YUV modes
MCT
Monochrome and two's complement output data select:
0= inverse grayscale luminance (if grayscale is selected by FS bits) or straight binary
U, V data output
1 = non-inverse monochrome luminance (if grayscale is selected by FS bits) or two's
complement U, V data output
OPL
Line qualifier polarity flag:
o = LNO is active-LOW (pin 52)
1 = LNO is active-HIGH
OPP
Pixel qualifier polarity flag:
0= PXO is active-LOW (pin 51)
1 = PXO is active-HIGH
TIR
Transparent data transfer:
o = normal operation (VRAM data burst transfer)
1 = FIFO register transparent
EFE
Extended formats enable. bit (see FS-bits in subaddress "20"):
o = 32-bit longword output formats
1= extended output formats ("one pixel a time")
April 1994
o
3-499
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
10.------.----~_.------_,------._----__.
0
(dB)
-10
-20
/
/1
-30
I~
I' (
1'/
I'
,
-40
I'~
II
-50
0
0.1
0.2
0.3
0.4
0.5
f / fClock
Fig.27 Horizontal frequency characteristic of luminance signal (Y) dependent on HF2
to HFO bits (subaddress 24).
10
0
(dB)
-10
-20
-30
-40
-50
0
0.05
0.10
0.15
0.20
0.25
f I fClock
Fig.28 Horizontal frequency characteristic of chrominance signals (UV) without UV
interpolation dependent on HF2 to HFO bits (subaddresses 24).
Purchase of Philips' 12 C components conveys a license under
the Philips' 12C patent to use the components in the 12C-system
provided the system conforms to the 12C specifications defined
by Philips.
April 1994
3-500
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
9. LIMITING VALUES
In accordance with the Absolute Maximum Rating System (lEe 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
V DD
supply voltage (pins 14, 27, 31,45,
61, 77, 91 and 106)
-0.5
6.5
V
VI
voltage on all input/output pins
-0.5
Ptot
total power dissipation
-
1.5
W
Tstg
storage temperature range
-65
150
°e
Tamb
operating ambient temperature range
'0
70
°e
VES D
electrostatic handling* for all pins
±2000
V
10. CHARACTERISTICS
V DD = 4.5 to 5.5 V; Tamb =
V DD+0.5V
-
*)
Equivalent to discharging a
100 pF capacitor through a
1.5 kil series resistor.
a to 70 °e unless otherwise specified.
SYMBOL
PARAMETER
Vooo
digital supply voltage range (pins 14,31,45,
61,77,91 and 106)
CONDITIONS
VOOA
analog supply voltage range (pin 27)
1000
digital supply current
IOOA
analog supply current
inputs LOW;
outputs without load
MIN.
TYP.
MAX.
UNIT
4.5
5
5.5
V
4.5
5
5.5
V
-
170
260
mA
-
10
20
mA
Data, clock and control inputs
V 1L
V 1H
input voltage LOW
clocks
-0.5
0.6
V
input voltage HIGH
clocks
2.4
Voo+0.5
V
V1L
input voltage LOW
other inputs
-0.5
0.8
V
V 1H
input voltage HIGH
other inputs
2.0
Voo+0.5
V
III
input leakage current
V1L=0
input capacitance data
-
10
C1
8
IlA
pF
input capacitance clocks
input capacitance 3-state 1/0
Data and control outputs
VOL
high-impedance state
-
10
pF
-
8
pF
0.6
V
2.4
-
Voo
V
note 1
output voltage LOW
0
VOH
output voltage HIGH
LFCO output (pin 28)
Vo
LFCO output signal (peak-to-peak value)
1.4
2.1
2.6
V
V28
output voltage range
1
-
Voo
V
input voltage LOW
-0.5
V
3
-
1.5
input voltage HIGH
Voo+0.5
V
12 C-bus, SDA and SCL (pins 3 and 4)
V 1L
V1H
April 1994
3-501
Product specification
Philips Semiconductors
Digital video decoder, scaler
and 'clock generator circuit (DESCPro)
SYMBOL
PARAMETER
13,4
input current
lACK
output current on pin 3
VOL
output voltage at acknowledge
Clock input timing (LLCB)
SAA7196
CONDITIONS
MIN.
TYP.
MAX.
-
/!A
3
-
±10
acknowledge
-
rnA
0.4
V
ns
13
=3 rnA
-
UNIT
Fig.3D
tLLCB
cycle time
31
-
45
/)
duty factor
40
50
60
%
tr
rise time
5
ns
tf
fall time
6
ns
Data, control and CREFB input timing
tLLCBH/tLLCB
Fig.3D
and Fig.31
tsu
set-up time
11
tHD
hold-time
4
Data and control output timing
load capacitance
CL
tOH
output hold time
tpD
propagation delay from negative edge of
LLCB
tpz
propagation delay from negative edge of
LLCB {to 3-state}
Fig.3D
; note 2
-
ns
50
pF
25
pF
ns
; note 3
data, HREF and VS
15
control
7.5
=
CL 15 pF
data, HREF and VS;
CL 50 pF
control; CL 25 pF
=
=
Clock output timing (LLC, LLC2, LLCB)
-
note 4
-
-
ns
-
29
ns
-
29
ns
15
ns
40
pF
45
ns
90
ns
13
Fig.3D
CL
output load capacitance
15
tLLC, tLLCB
cycle time
31
tLLC2
cycle time
62
0
duty factor
tLLCH/tLLC
tLLC2H/tLLC2
tLLCBH/tLLCB
tr
rise time
0.6 to 2.6 V
tf
fall time
2.6 to 0.6 V
tdLLC2
delay between LLCBout and LLC20ut
at 1.5 V, 40 pF
Data qualifier output timing (CREFB)
Fig.3D
tOH
output hold time
tp 0
propagation delay from positive edge of
LLCB
CL
CL
=15 pF
=40 pF
-
40
50
60
%
-
-
5
ns
5
ns
8
ns
3
-
-
ns
18
ns
Horizontal PLL
fH n
nominal line frequency
50 Hz system
60 Hz system
dfH/fH n
permissible static deviation
50 Hz system
60 Hz system
April 1994
3-502
15625
-
Hz
15734
-
Hz
±5.6
%
±6.7
%
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SYMBOL
PARAMETER
CONDITIONS
SAA7196
MIN.
TYP.
MAX.
UNIT
4.433618
-
MHz
Subcarrier PLL
nominal subcarrier frequency
fsc n
lock-in range
Afsc
Crystal oscillator
PAL
NTSC
-
3.579545
PAUNTSC
±400
-
Fig.32
fn
nominal frequency
permissible deviation fn
-
temperature deviation from fn
26.8
-
MHz
±50
10-6
-
-
±20
10-6
temperature range Tamb
0
-
70
°C
load capacitance CL
8
-
pF
3rd harmonic
crystal specification:
-
. series resonance resistance Rs
50
motional capacitance C 1
-
parallel capacitance Co
VCLKtiming
Fig.29
-
pF
200
ns
'; note 12
tVCLK
note 5
50
tp L, tp H
LOW and HIGH times
note 6
17
tr
rise time
tf
fall time
output load capacitance
3.5±20%
n
fF
9922 520 30004
VRAM port clock cycle time
VRO and reference signal output timing
80
1.1±20%
Philips catalogue number
CL
Hz
; note 11
Af / fn
X1
MHz
ns
-
5
ns
6
ns
Fig.29
VRO outputs
15
40
pF
other outputs
7.5
25
pF
tOH
VRO data hold time
CL = 10 pF; note 7
0
tOHL
related to LCCS (INCADR, HFL)
C L = 10 pF; note 8
0
tOHV
related to VCLK (HFL)
CL = 10 pF; note 8
0
-
too
VRO data delay time
CL =40 pF; note 7
25
ns
tOOL
related to LCCS (INCADR,HFL)
CL =25 pF; note 8
-
60
ns
toov
related to VCLK (HFL)
CL =25 pF; note 8
-
to
VRO disable time to 3-state
CL =40 pF; note 9
-
CL =25 pF; note 10
tE
VRO enable time from 3-state
-
CL =40 pF; note 9
C L =25 pF; note 10
ns
ns
-
ns
60
ns
40
ns
24
ns
40
ns
25
ns
Response times to HFL flag
tHFL VOE
HFL rising edge to VRAM port enable
tHFL VCLK
HFL rising edge to VCLK burst
April 1994
-
3-503
810
ns
840
ns
Philips Semiconductors
Product specification
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
Notes to the characteristics
1.
Levels measured with load circuits dependent on output type. Control outputs (HREF, VS excluded): 1.2 kn at 3 V
(TIL load) and C L =25 pF. Data, HREF and VS outputs: 1.2 kn at 3 V (TIL load) andC L =50 pF.
2.
Data input signals are CVBS(7-0), CHR(7-0) (related to LLC) and YUV(15-0). Control input signals are HREF, VS and
DIR.
3.
Data outputs are YUV(15-0). Control outputs are HREF, VS, HS, HSY, HCL, SODD, SVS, SHREF, PXQ, LNQ, RTCO
and RTS(1-0).
4.
The minimum propagation delay from 3-state to data active is 0 related to the falling edge of LLCB.
5.
Maximum tVCLK =200 ns for test mode only. The applicable maximum cycle time depends on data format, horizontal
scaling and input data rate.
6.
Measured at 1.5 V level; tp L may be unfinite.
7.
Timings of VRO refer to the rising edge of VCLK.
8.
The timing of INCADR refers to LLCB; the rising edge of HFL always refers to LLCB. During a VRAM transfer, the failing edge of HFL is generated by VCLK. Both edges of HFL refer to LLCB during horizontal increment and vertical
reset cycles.
9.
Asynchronous signals. Its timing refers to the 1.5 V switching point of VOEN input Signal (pin 53).
10. The timing refers to the 1.5 V switching point of VMUX signal (pin 46) in 32- to 16-bit multiplexing mode. Corresponding pairs of VRO outputs are together connected.
11. If the internal oscillator is not being used, the applied clock signal must be TIL-compatible.
12. CREFB-timing also valid for VCLK in transparent mode (see Fig.30
).
2.0V
VOEN
1.5V
O.BV
2.4 V
VCLK
1.5V
~---+-----
output VRO(n)
output HFL
~
~~~'Q,---------------Fig.29 Data output timing (VCLK).
April 1994
3-504
O.6V
2.4V
O.6V
2.4 V
O.6V
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
2.4 V
clock input
LLCB
1.SV
a.6V
2.av
data input
YUV, HREF, VS
a.BV
2.av
input
CREFB
a.BV
2.av
control
input OIR
a.BV
data and
control output
data output
YUV-bus
(to 3-state)
clock output
LLCB
2.4 V
output
CREFB
a.6V
Fig.3D Data input/output timing by LLCB.
April 1994
3-505
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
2.6V
clock output
LLC
1.5V
O.6V
2.0V
data input
CVBS, CHR
O.8V
Fig.31 Data input timing by LLC.
26.8 MHz
(3rd harmonic)
~
_X1r
XTAL 1
10pF=(1)
J.,
SAA7196
SAA7196
JLns~2
XTALI 2
'-----
(1) value depends on
crystal parameters
(a)
(b)
Fig.32 Oscillator application (a) and optional clock from external source (b).
11. PROCESSING DELAYS
Table 13 Processing delays of signals
PORTS
DELAY IN LLC/LLCB CYCLES
REMARKS
CVBS/CHR to YUV
216
-
YUVto VRO
56 in YUV mode; 58 in RGB mode
only in transparent mode
CVBS/CHR to VRO
272 in YUV mode; 274 in RGB modes
only in transparent mode
April 1994
3-506
»
~
......
(0
(0
~
(J1
n
C
1
3
S-VHS
CONNECTOR
4
2
5
1
~75n
luminance ...
33 pF
c.u
33 pF
kQ
2~6
15
14
Vi
source 1
16
0+
F
13
~
12
~
4.71lF
11l
75Q ~t- 17
Vi
4.71lF
source 2
rn+
18
16
13
f--i?-
17
12
~~
18
~~
'23mH
11l1~+
0.11lF
I V'~OA
0.1,rF
'u
11lF
f~
02.2 ill
10 ICVBS3
19
20
21
TDA8708A
22
ClK..
25
4 ICVBS4
0.221lF
0.1
IlF
H=J---<
0.11lF
r+-
analog
~~
68
TpF
~
I-- 28
HCl
lLC
~
Oe..
-.: CD
o
:s:
,,0:
aO
Q.
-.:
~-.:
(J)
g_.0>0
0-':
(J)
3~
27
2~
2 ICVBS6
n
120
Q
L...o
(")
68
pF
'1J
a
--
1~
5.6Q 5.6Q
CV BS7
I:0
CV BSO
...
1 CVBS7
5.6Q
120Q
"1J
~
(3
22 Q
...
(J)
+5 V (analoQ supply'
+5 V (digital supply)
J:J
z
"T1
o <
(J)
CD
3
o·
o
::J
a.
c:
n.
o
en
m
...
26
n
Z
~
f/)
r-+ _CD
0.11l F
4~
28
G)
CO CD
CD 0
::Je..
CD CD
-.: 0
s:
r,;--:-
25
3kQ
(5
z
ClK
5
c
c
=i
»
6 Vooo
24
0-
(5
VOOO
O~
_0>
"1J
~
"6'
1 kQ
27
~
analog
7
e.. CO
3 ICVBS5,
, - - 26
10Q
TDA8709A
"'C
"'C
r-
mo
::J _.
o
J:J
0.11lF
4.71lF
HSY
8
0.11lF
6 Vooo
5
21
22
~f---
Vooo
24
9
23
:~
7
20
).
C')
»
~
10~
10.11lF
22Q
rn+
r
C7to CO
CO
11~
19
11 ~
23
5.6Q
14
11lF
~
CVBS (J2)
4.71lF
m+
'"
-+
digital
'-----
L GNO
jj
15
...
......
"I\)
C')
L
3PSW1 bit (LOW = source 1)
chrominance
cJ,
o
-...j
..:'I~
digital
......
""
:....
--
- - - - -
_._--
-
»
»
"-.I
....L
Fig.33 Application circuit analog-to-digital convertions.
<0
O)
a.
c:
n.
f/)
"C
CD
2:
o·
S-
o·
::J
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
SOA
SCl
IICSA
VRO(31-Q)
VOOO 1 to VOO07
+5V
~g~'~dn6
Vss
' - - - - i I-___..
=0-i
O.lI1F
each supply has Its
own decoupllng capacitor
digital ?-;
5
4
3 [t;:gm&l12~~l8
lDffim:e;::~~;:! 78 VR015
79
80
81
82
83
~~: fl04~ri;~20
15,118 and 119
(test pins)
84
85
86
87
88
89
90
92
93
94
53
54
55
CHRO
CHRl
CHR2
CHR3
CHR 7-0
CHR4
CHR5
10
11
~~~~ ~:
~~~----'~-~~~17
18
19
20
21
22
23
4r.H~S~Y_____________--1~~
117
96
97
98
99
100
101
102
103
107
108
109
110
111
112
113
:r:-=R=T~S~l==--=--=--=--=--=--=--=--=--=--=--=--=--=--=--=-~ ~
.....4rR~T~S~0________________-435
~B~T~ST~
37
______________~43
~~~G~PS~W~1~______________ J33
~~~G~PS~W~2~______________132
Xl: Philips 9922 520 30004
Xl
=
26.8 MHz
RESN
llC
CREF
t
VOEN
HFl
INCADR
SAA7196
~~=;~~~o~----------------i26
+5V CGCE
VR014
VR013
VR012
VROll
VR010
VR09
VR08
VR07
VR06
VR05
VR04
VR03
VR02
VROl
VROO
36
40
38 39 41
76,
42 28 48 49 50 51 52 105
27
29
95115 114
YUV15
YUV14
YUV13
YUV12
YUVll
YUV10
YUV9
YUV8
YUV7
YUV6
YUV5
YUV4
YUV3
YUV2
YUVl
YUVO
'---r~--~~~-T~-r-r--~--~----r-T-~
.,-; digital
~
mm
Il..U
W..J
II:..J
U
2.211H
O.lI1F
2
VOOA
4
analog
~ ~
i 19
11
13 c: 14
15 .2 16
~--r-----------~----------------r-----~17 ~ 18
L---~----------~----------------~-------419
~20
L-------------------------------4_------------------~--------4_----~21 ~ 22
23
"-----125
JPl
Fig.34 Application of SAA7196.
April 1994
3·508
241--1----'
26
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (DESCPro)
SAA7196
12.2. PROGRAMMING EXAMPLE
Coefficients to set operation for application circuits Figures 33 and 34 on page 53 and page 54. Slave address
byte is 40 h at pin 5 connected to Vsso (or 42 h at pin 5 connected to V ooo )
Table 14 Programming examples
SUBADDRESS
FUNCTION
BITS
VALUE (hex)
00
01
02
03
IDEL(7:0)
HSYB(7:0)
HSYS(7:0)
HCLB(7:0)
increment delay
H-sync beginning for 50 Hz
H-sync stop for 50 Hz
H-clamp beginning for 50 Hz
4C
30
00
E8
04
05
06
H-clamp stop for 50 Hz
HS pulse position for 50 Hz
B6
F4
07
HCLS(7:0)
HPHI(7:0)
BYPS, PREF, BPSS(1 :0),
CORI(1 :0), APER(1 :0)
HUEC(7:0)
luminance bandwidth control
hue control (0 degree)
01 (1)
00
08
09
OA
OB
CKTQ(4:0)
CKTS(4:0)
PLSE(7:0)
SESE(7:0)
colour-killer threshold QUAM
colour-killer threshold SECAM
PAL-switch sensivity
SECAM switch sensivity
F8
F8
40
40
OC
OD
COLO, LFIS(1 :0)
VTRC, RTSE, HRMV,
SSTB,SECS
HPLL, OECL, OEHV,
OEYC, CHRS, GPSW(2:1)
AUFD, FSEL, SXCR,
SCEN, YDEL(2:0)
chrominance gain control settings
00
standard/mode control
04 (2)(4); 05 (3)(4)
I/O and clock controls
38, 3B (5)
OE
OF
miscellaneous controls #1
90
10
11
12
13
HRFS, VNOI(1 :0)
CHCV(7:0)
SATN(6:0)
CONT(6:0)
miscellaneous controls #2
chrominance gain nominal value
chrominance saturation control value
luminance contrast control value
00
2C (6); 59 (7)
40
40
14
15
16
17
HS6B(7:0)
HS6S(7:0)
HC6B(7:0)
HC6S(7:0)
H-sync beginning for 60 Hz
H-sync stop for 60 Hz
H-clamp beginning for 60 Hz
H-clamp stop for 60 Hz
34
OA
F4
CE
18
19
1A to 1F
HP61(7:0)
BRIG(7:0)
reserved
HS pulse position for 60 Hz
luminance brightness control value
set to zero
F4
80
00
RTB, OF(1 :0), VPE,
LW(1 :0), FS(1 :0)
XD(7:0)
XS(7:0)
XO(7:0)
HF(2:0), XO(8), XS(9,8),
XD(9,8)
data formats and field sequence
processing
LSB's output pixel/line
LSB's input pixel/line
20
21
22
23
24
April 1994
LSB's for horizontal window start position
10
80
80
03
horizontal filter select and
MSB's of subaddresses 21, 22, 23
85 (9); 8F (13)
3-509
(8)
(9); FF (13)
(9); FF (13)
(9); 00 (13)
Product specification
Philips Semiconductors
Digital video decoder, scaler
and clock generator circuit (D~SCPro)
BITS
SUBADDRESS
FUNCTION
SAA7196
VALUE (hex)
25
26
27
28
YD(7:0)
YS(7:0)
YO(7:0)
AFS, VP(1 :0), YO(8),
YS(9,8), YD(9,8)
LSB's output lines/field
LSB's input lineslfield
LSB's vertical window start position
adaptive and vertical filter select and
MSB's of subaddresses 25, 26, 27
90 (9); FF (13)
90 (9); FF (13)
03 (9); 00 (13)
29
2A
2B
VS(7:0)
VC(7:0)
VS(8), VC(8), POE
00 (10)
00 (10)
00 (10)
2C
2D
2E
2F
30
VL(7:0)
VU(7:0)
UL(7:0)
UU(7:0)
VOF, AFG
LSB's vertical bypass start position
LSB's vertical bypass lines/field
MSB's of subaddresses 29, 2A
and odd/even polarity switch
chroma key: lower limit V (R-Y)
chroma key: upper limit V (R-Y)
chroma key: lower limit U (B-Y)
chroma key: upper limit U (B-Y)
VRAM port MUX enable, adaptivity
00 (9); OF (13)
00
FF (11)
00
00
80 (12)
Notes to Table 14
1. dependent on application (Figures 33 and 34 on page 53.and page 54)
2. for QUAM standards
3. for SECAM
4. HPLL is in TV-mode, value for VCR-mode is 84h (85h for SECAM VCR-mode)
5. for VIC-mode
6.
nominal value for UV-CCIR-Ievel with NTSC source.
7.
nominal value for UV-CCIR-Ievel with PAL source
8.
ROM-table is active, scaler processes both fields for interlaced display; VRAM port enabled; longword
position = 0; 16-bit 4:2:2 YUV output format selected
.9. scaler processes a segment of (384 pixels x 144 lines) with defaults XO and YO set to the first valid pixel!
line and line/field (for decoder as input source) with scaler factors of 1:1; horizontal and vertical filters are
bypassed, filter select adaptivity is disabled
10. no vertical bypass region is defined·
11. chrominance keyer is disabled (VL = 0, VU = -1)
12. 32-bit to 16 VRAM port MUX, adaptive scale and Y -limiter are disabled; pixel and .Iine qualifier polarity for
transparent mode are set to zero (active); data burst transfer for the 32-bit longword formats is set
13. if no scaling and panning is wanted, the parameters XD, XS, YD and YS should be set to maximum
(3FFh) and the parameters XO and YO should be set to minimum (OOOh). In this case, the HREF and VS
signals define the processing window of the scaler
April 1994
3-510
Philips Semiconductors Video Products
Preliminary specification
Clock signal generator circuit
for Desktop Video systems (SCGC)
FEATURES
• Suitable for Desktop Video systems
• Two different sync sources
selectable
• PLL frequency multiplier to
generate 4 times of input frequency
• Dividers to generate clocks LLCA,
LLCB, LLC2A and LLC2B (2nd and
4th multiples of input frequency)
• PLL mode or VCO mode selectable
• Reset control and power fail
detection
GENERAL DESCRIPTION
The SAA7197 generates all clock
signals required for a digital TV
system suitable for the SAA719x
family. The circuit operates in either
the phase-locked loop mode (PLL) or
voltage controlled oscillator mode
(VCO).
May 1992
SAA7197
QUICK REFERENCE DATA
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
4.5
5.0
5.5
V
5.0
VDDA
analog supply voltage (pin 5)
VDD D
digital supply voltage (pins 8, 17)
4.5
5.5
V
IDDA
analog supply current
5
9
mA
IDDD
digital supply current
10
60
mA
V LFca
LFCO input voltage
(peak-to-peak value)
1
VDDA
V
fj
input frequency range
6.0
7.2
MHz
V,
input voltage LOW
input voltage HIGH
0
2.4
0.8
VDD D
V
V
Va
output voltage LOW
output voltage HIGH
0
2.6
0.6
VDDD
V
V
Tamb
operating ambient temperature
range
0
70
°C
ORDERING INFORMATION
EXTENDED
TYPE NUMBER PINS
PACKAGE
PIN POSITION
MATERIAL
CODE
SAA7197
20
OIL
plastic
SOT146
SAA7197T
20
mini-pack (S020)
plastic
SOT163A
3-511
Preliminary spefification
Philips Semiconductors Video Products
Clock signal generator circuit
'for Destop Video systems (SCGC)
1
MS
SAA7197
I
I
I
/5
18
117
SAA7197
LOOP
FILTER
r----o'~
i
MS = LOW
PHASE
DETECTOR
i
11
LFCO
II
II,
~
PRE-FILTER
AND
PULSE
SHAPER
*
~
VCO
r-.....
+
L~~
FREQUENCY
DIVIDER
1 :2
j~
Lti?
Lti?
FREQUENCY
~---- --------~;
DIVIDER
1: 2
DELAY
~
POWER-ON
RESET
7
LLCA
10
14
LLCB
..
20
LLC2B
15
CREF
12
RESN
LFC02 19
2
CE
16
LFCOSEL
~
FUNCTION DESCRIPTION
The SAA7197 generates all clock
signals required for a digital TV
system suitable for the SAA719x
family consisting of an 8-bit
analog-to-digital converter (ADC8),
digital video multistandard decoder,
square pixel (DMSD-SQP), digital
video colour space converter (DCSC)
and optional extentions. The
SAA7197 completes a system for
Desktop Video applications in
conjunction with memory controllers.
The input signal LFCO is a digital-toanalog converted signal provided by
the DMDS-SQPs horizontal PLL. It is
the multiple of the line frequency:
7.38 MHz =472 x fH in 50 Hz systems
6.14 MHz = 360 x fH in 60 Hz systems
LFC02 (TTL-compatible signal from
an external reference source) can be
applied to pin 19 (LFCOSEL = HIGH).
The input signal LFCO or LFC02 is
May 1992
LLC2A
3
4
6,9,13,18
PORD
I
V SSA
:::!~
Vsso
:::::~
MEH46
Fig.1 Block diagram.
multiplied by factors 2 or 4 in the PLL
(including phase detector, loop filter,
VCO and frequency divider) and
output on LLCA (pin7), LLCB (pin 10),
LLC2A (pin 14) and LLC2B (pin 20).
The rectangular output signals have
50 % duty factor. Outputs with equal,
frequency may be connected
together externally. The clock
outputs go HIGH during power-on
reset (and chip enable) to ensure
that no output clock signals are
available the PLL has locked-on.
Mode select MS
The LFCO input signal is directly
connected to the VCO at MS = HIGH.
The circuit operates as an oscillator
and frequency divider. This function
is not tested.
Source select LFCOSEL
Line frequency control signal LFCO
(pin 11 ) is selected by LFCOSEL =
LOW. LFCOSEL = HIGH selects
LFC02 input signal (pin 19). This
function is not tested.
3-512
Chip enable CE
The buffer outputs are enabled and
RESN set HIGH by CE = HIGH (Fig.4),
CE = LOW sets the clock outputs
HIGH and RESN output LOW.
CREF output
2 fLFCO output to control the clock
dividers of the DMSD-SQP chip
family.
Power-on reset
Power-on reset is activated at
power-on, when the supply voltage
decreases below 3.5 V (Fig.4) or
when chip enable is done. The
indicator output RESN is LOW for a
time determined by capacitor on
pin 3. The RESN signal can be
applied to reset other circuits of this
digital TV system.
The LFCO or LFC02 input signals
have to be applied before RESN
becomes HIGH.
Preliminary specification
Philips Semiconductors Video Products
Clock signal generator circuit
for Destop Video systems (SCGC)
SAA7197
PIN CONFIGURATION
PINNING
SYMBOL
PIN
DESCRIPTION
CE
2
= PLL mode)*
chip .enable treset (HIGH = outputs enabled)
PORD
3
power-on reset delay, dependent on external capacitor
VS SD4
VSSA
4
analog ground (0 V)
vo oo2
VDDA
5
analog supply voltage (+5 V)
MS
1
mode select input (LOW
LLC2B
LFC02
LFCOSEL
CREF
V SSD1
6
digital ground 1 (0 V)
LLCA
7
line-locked clock output signal (4 times fLFCO)
VDDD1
8
digital supply voltage 1 (+5 V)
V SSD2
9
digital ground 2 (0 V)
LLCB
10
line-locked clock output signal (4 times fLFCO)
LFCO
11
line-locked frequency control input signal 1
RESN
12
reset output (active-LOW, Fig.4)
VSSD3
13
digital ground 3 (0 V)
LLC2A
14
line-locked clock output signal 2A (2 times f LFCO )
CREF
15
clock reference output, qualifier signal (2 times f LFCO )
LLC2A
VSS03
RESN
LLCB
Fig.2 Pin configuration.
= LFCO selected)*
LFCOSEL
16
LFCO source select (LOW
V DDD2
17
digital supply voltage 2 (+5 V)
V SSD4
18
digital ground 4 (0 V)
LFC02
19
line-locked frequency control input signal 2*
LLC2B
20
line-locked clock output signal 28 (2 times f LFCO )
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); ground
pins as well as supply pins together connected
SYMBOL
VDDA
VDDD
PARAMETER
analog supply voltage (pin 5)
digital supply voltage (pins 8 and 17)
MIN.
MAX.
UNIT
-D.5
7.0
V
-D.5
7;0
V
±100
mV
-D.5
Vdiff GND difference voltage VDDA - VDDD
=20 mAl
Vo
output voltage (10M
VDDD
V
Ptot
total power dissipation (DIL20)
0
1.1
W
T stg
storage temperature range
-65
150
°C
Tamb
operating ambient temperature range
0
70
°C
VESD
electrostatic handling** for all pins
tbf
V
May 1992
3-513
* MS and LFC02 functions are not
tested. LFC02 is a multiple of
horizontal frequency.
** Inputs and outputs are protected
against electrostatic discharge in
normal handling. However, to be
totally safe, it is recommended to
take normal handling precautions
appropriate to "Handling MOS
devices
fl.
Preliminary specification
Philips Semiconductors Video Products
Clock signal generator circuit
for Destop Video systems (SCGC)
SAA7197
CHARACTERISTICS
VDDA = 4.5 to 5.5 V; VD DD = 4.5 to 5.5 V; f LFCO = 5.5 to 8.0 MHz and T amb = 0 to 70°C unless otherwise specified.
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VOOA
analog supply voltage (pin 5)
4.5
5.0
. 5.5
V
Vooo
digital supply voltage (pins 8 and 17)
4.5
5.0
5.5
V
IOOA
analog supply current (pin 5)
5
9
mA
1000
digital supply current (Is + 117)
note 1
10
60
mA
Vreset
power-on reset threshold voltage
Fig.4
-
3.5
-
V
Input LFCO (pin 11)
V 11
DC input voltage
0
Vi
input signal (peak-to-peak value)
V OOA
V
1
V OOA
V
fLFCO
input frequency range
5.5
8.0
MHz
Cll
input capacitance
-
10
pF
0.8
V
-
Inputs MS, CE, LFCOSEL and LFC02 (pins 1, 2, 16 and 19)
V IL
input voltage LOW
VIH
input voltage HIGH
fLFC02
input frequency range for LFC02
III
input leakage current
CI
input capacitance
0
note 3
2.0
-
VOOO
V
5.5
-
8.0
MHz
-
-
10
~
5
pF
0.4
V
V OOD
V
200
ms
Output RESN (pin 12)
VOL
output voltage LOW
VOH
output voltage HIGH
td
RESN delay time
0
2.4
C 3 = 0.1 flF; FigA
20
Output CREF (pin 15)
VOL
output voltage LOW
0
-
0.6
V
VOH
output voltage HIGH
2.4
-
VOOO
V
fCREF
output frequency CREF
2 fLFCO 2)
MHz
CL
output load capacitance
15
-
pF
tsu
set-up time
Fig.3; note 1
12
-
tHO
hold time
Fig.3; note 1
4
Fig.3
40
ns
ns
Output signals LLCA, LLCB, LLC2A and LLC2B (pins 7,10,14, and 20); note 3
VOL
output voltage LOW
VOH
output voltage HIGH
tcomp
May 1992
composite rise time
10 L = 2 mA
0
0.6
V
10H =-0.5 mA
2.6
VOOO
V
CE = HIGH (pin 2)
2.6
VOOO
V
8
ns
Fig.3; notes 1 and 2
3-514
-
Preliminary specification
Philips Semiconductors Video Products
Clock signal generator circuit
for Destop Video systems (SCGC)
SYMBOL
fLL
PARAMETER
SAA7197
CONDITIONS
output frequency LLCA
MIN.
-
Fig.3
output frequency LLCB
output frequency LLC2A
output frequency LLC2B
tr, tr
rise and fall times
Fig.3;
tLL
duty factor LLCA, LLCB, LLC2A
and LLC2B (mean values)
note 1; Fig.3;
at 1.5 V level
40
TYP.
MAX.
UNIT
4 fLFCO(2)
MHz
4 fLFCO(2)
MHz
2 fLFCO(2)
MHz
2 f LFCO(2)
MHz
-
5
ns
50
SO
ns
Notes to the characteristics
1. f LFCO = 7.0 MHz and output load 40 pF (Fig.3)
2. tcomp is the rise time from LOW of all clocks to HIGH of all clocks (Fig.3) including rise time, skew and jitter
components. Measurements taken between O.S V and 2.S V. Skew between two LLx clocks will not deviate more
than ±2 ns if output loads are matched within 20 %.
3. LFC02 functions not tested.
CREF
0.6V
I"'~f-------
I LL1.5
2.6V
LL1.5A
LL1.58
1.5 v
1'L---~<-1-------- 0.6V
I LL3 H
- - -....~.14----
I LL3 L
LL3A
LL38
1.5 V
~-----~I---;f
-1--
0.6 V
MEH456
Fig.3 Output timing.
May 1992
3-515
Philips Semiconductors Video Products
Preliminary specification
Clock signal generator circuit
for Destop Video systems (SCGC)
~uuuuuu_mm_m
__
SAA7197
m_m~
__ m
__ m
___ m m : u _ m u __ m _ m m m
I
ov
power·on
LFCO
RESN
LL1.SA
LL1.SB
LL3A
LL3B
1111111
PLL lock·on
clockHIGH
~ in~~~?reset
~
reset
time
MEH457
Fig.4 Reset procedure.
May 1992
+3.S V
3·516
Philips Semiconductors Video Products
Preliminary specification
SAA7199B
Digital video encoder, GENLOCK-capable
1. FEATURES
• Monolithic integrated CMOS video
encoder circuit
• Standard MPU (12 lines) and
12C-bus interfaces for controls
• Three 8-bit signal inputs PD(7-0)
for RGB respectively YUV or
indexed colour signals
(Tables 10 to 17)
• Square pixel and CCIR input data
rates
• Band-limited composITe sync pulses
• Three 256X8 colour look-up tables
(CLUTs) e. g. for gammacorrection
• External subcarrier from a digital
decoder (SAA7151 B or SAA7191 B)
• Multi-purpose key for real-time
format switching
• Autonomous internal blanking
• Optional GENLOCK operation with
adjustable horizontal sync timing
and adjustable subcarrier phase
• Stable GENLOCK operation in
VCR standard playback mode
• Optional still video capture
extension
• Three suitable video 9-bit digitalto-analog converters
• Composite analog output signals
CVBS, Y and C for PAUNTSC
• "Line 21" data insertion possible
3. QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Vooo
digital supply voltage range
(pins 2, 21 and 41)
4.5
5.0
5.5
V
V OOA
analog supply voltage range
(pins 64, 66, 70 and 72)
4.75
5.0
5.25
V
200
mA
Ip
total supply current
VI
input signal levels
Vo
analog output signals Y, C and
CVBS without load
(peak-to-peak value)
TTL -compatible
RL
output load resistance
ILE
LF integral linearity error in
output signal (9-bit DAC)
DLE
Tamb
90
LF differential linearity error in
output signal (9-bit DAC)
2
V
-
n
-
operating ambient temperature
range
0
±1
LSB
±0.5
LSB
70
°C
4. ORDERING INFORMATION
EXTENDED
TYPE NUMBER PINS
SAA7199B
April 1993
84
PACKAGE
PIN POSITION
PLCC
MATERIAL
CODE
plastic
SOT189CG
3-517
2. GENERAL DESCRIPTION
The SAA71 99B encodes digital
base-band colour/video data into
analog Y, C and CVBS signals
(S-Video included). Pixel clock and
data are line-locked to the horizontal
scanning frequency of the video
Signal. The circuit can be used in a
square pixel or in a consumer TV
application. Flexibility is provided by
programming facilities via MPU-bus
(parallel) or 12C-bus (serial).
C)C
>
~
iO
mcC·
Z~·
r-O)
0-
~
+5V
~~
~~
KEY
MPK
VDDD1 to VDDD3
VSSD1 to VSSD3
I
2,21,41
PD1(7- }(1)
(digital I
1!l
<
M
67
69
i
~
(Xl
LD
"
J
tf
II
1
internal control bus
.:iDA
rJl
4]
.c
~
c:
C')
0)0
o..,
2:0
l>
Figo 1 Block diagram (application details Fig.4)o
3so
I»
-<
(fl
-..J
io
(0
(0
ac5"
...I,
m
~
::I
Philips Semiconductors
Preliminary specification
Digital video encoder,
GENLOCK-capable
SAA71998
PINNING
SYMBOL
V S S D1
PIN
1
DESCRIPTION
digital ground 1 (0 V)
V D DD1
2
+5 V digital supply 1
VSN
3
vertical sync output (3-state), conditionally composite sync output; active LOW or active HIGH
PD1(0)
4
PD1(1)
5
PD1(2)
6
PD1(3)
7
PD1(4)
8
PD1(5)
9
PD1(6)
10
PD1(7)
11
PD2(0)
12
PD2(1)
13
PD2(2)
14
PD2(3)
15
PD2(4)
16
PD2(5)
17
data 1 input: digital signal R (red) respectively V signal (formats in Table 6)
data 2 input: digital signal G (green) respectively Y signal or indexed colour data
(formats in Table 6)
PD2(6)
18
PD2(7)
19
LDV
20
load data clock input signal to input interface (samples PDn(7-0), CBN, MPK, KEY and RTCI)
V D DD2
21
+5 digital supply 2
V S SD2
22
digital ground 2 (0 V)
CBN
23
composite blanking input; active LOW
PD3(0)
24
PD3(1)
25
PD3(2)
26
PD3(3)
27
PD3(4)
28
PD3(5)
29
PD3(6)
30
PD3(7)
31
data 3 input: digital signal B (blue) respectively U signal (formats in Table 6)
MPK
32
mUlti-purpose key; active HIGH
AO
33
subaddress bit AO for microcomputer access (Table 3)
A1
34
subaddress bit A1 for microcomputer access (Table 3)
April 1993
3-519
Preliminary specification
Philips Semiconductors
Digital video encoder,
GENLOCK.. capable
SYMBOL
PIN
SAA71998
DESCRIPTION
RlWN
35
readl write not input signal from microcontroller
CSN
36
chip select input for parallel interface; active LOW
00
37
01
38
02
39
03
40
VOOO3
41
+5 V digital supply 3
VSS03
42
digital ground 3
04
43
05
44
06
45
bidirectional port from/to microcontroller (bits 03 to 00)
bidirectional port from/to microcontroller (bits 07 to 04)
07
46
SOA
47
12C-bus data line
SCL
48
12C-bus clock line
CLKIN
49
external clock signal input (maximum 60 MHz)
CLKSEL
50
clock source select input
PIXCLK
51
CLKO/2 or conditionally CLKO output signal
CLKO
52
selected clock output signal (LLC or CLKIN)
TP
53
connect to ground (test pin)
RESN
54
reset input; active LOW
LLC
55
line-locked clock input signal from external CGC
CREF
56
clock qualifier of external CGC
GPSWI
RTCI
57
general purpose switch output (set via 12C-bus or MPU-bus);
real-time control input, defined by 12C or MPU programming
SLT
58
GENLOCK flag (3-state): HIGH= sync lost in GENLOCK mode; LOW
XTALI
59
crystal oscillator input (26.8 or 24.576 MHz)
XTAL
60
crystal oscillator output
LFCO
61
line frequency control output signal for external CGC
V refL
62
reference LOW voltage of DACs (resistor chains)
VrefH
63
reference HIGH voltage of DACs (resistor chains)
V OOA4
64
+5 V analog supply 4 for resistor chains of the DACs
C
65
chrominance analog output signal C
VOOA1
66
+5 V analog supply 1 for output buffer amplifier of OAC1
y
67
luminance analog output signal Y
V SSA
68
analog ground (0 V)
April 1993
3-520
= otherwise
Philips Semiconductors
Preliminary specification
Digital video encoder,
GENLOCK-capable
SYMBOL
PIN
SAA7199B
DESCRIPTION
CVBS
69
CVBS analog output signal
VDDA2
70
+5 V analog supply 2 for output buffer amplifier of DAC2
current input for analog output buffers
CUR
71
V DDA3
72
+5 V analog supply 3 for output buffer amplifier of DAC3
KEY
73
key signal to insert CVBS input signal into encoded CVBS output signal; active HIGH
HSY
74
horizontal sync indicator output signal; active HIGH (3-state output to ADC)
HCL
75
horizontal clamping output; active HIGH (3-state output)
CVBSO
76
CVBS1
77
CVBS2
78
CVBS3
79
CVBS4
80
CVBS5
81
CVBS6
82
CVBS7
83
HSN
84
digital CVBS input signal
horizontal sync output; active LOW or active HIGH for 60/66/72 x PIXCLK
at 12.27/13.5/14.75 MHz (3-state output)
FUNCTIONAL DESCRIPTION
The SAA7199B is a digital video
encoder that translates digital RGB,
YUV or 8-bit indexed colour signals
into the analog PAUNTSC output
signals Y (luminance), C (4.43/3.58
MHz chrominance) and CVBS
(composite signal including sync).
Four different modes are selectable
(Table 9):
- stand-alone mode (horizontal and
vertical timings are generated)
- slaver mode (stand-alone unit
that accepts external horizontal
and vertical timing), and optional
real-time information for
subcarrier/clock from a digital
colour decoder
- GENLOCK mode (GENLOCK
capabilities are achieved in
conjunction with determined ICs).
- test mode (only clock signal is
required)
The input data rate (pixel sequence) has
April 1993
an integer relationship to the number
of horizontal clock cycles (Table 1).
A sufficient stable external clock
signal ensures correct encoding. The
generated clock frequency in the
GENLOCK mode may deviate by
±7 % depending on the reference
signal which is corresponding to its
input sync signal. The clock will be
nominal in the GENLOCK mode
when the reference signal is absent
(nominal with crystal oscillator
accuracy for TV time constants, and
nominal ±1.4 % for VCR time
constants).
The on-chip colour conversion matrix
provides CCIR 601 code-compatible
transcoding of RGB to YUV data.
RGB data out of bounds, with respect
to CCIR 601 specification, can be
clipped to prevent over-loading of the
colour modulator. RGB data input
can be either in linear colour space
or in gamma-corrected colour space.
YUV data must be gamma-corrected
according to CCIR 601. This circuit
operates primarily in a 24-bit colour
space (3 x 8-bit) but can also
accomodate different data formats
(4:1 :1, 4:2:2 and 4:4:4) as well as
8-bit indexed pseudo-colour space
operations (FMT-bits in Table 6).
RGB CLUTs on chip provide
gamma-correction and/or other CLUT
functions. They consist of
programmable tables to be loaded
Table 1 Pixel relationships
ACTIVE PIXELS FIELD
PER LINE
RATE
MULTIPLES OF LINE PIXCLK OUTPUT
FREQUENCY
SIGNAL (MHz)
XTAL
(MHz)
640 (square)
720
60 Hz
60 Hz
780
858
12.272727
13.5
26.8
24.576
768 (square)
720
50 Hz
50 Hz
944
864
14.75
13.5
26.8
24.576
3-521
Preliminary speCification
Philips Semiconductors
Digital video encoder,
GENLOCK-capable
>-
C/)
J:
>-
UJ
~
~
Cl
>
a:
(,)
::::>
SAA71998
~
Cl
Cl
>
C/)
CD
>
(,)
Cf)
>
v
:;:
«
(f)
>-
Cl
Cl
>
«
Cl
(,)
Cl
>
I
>'§
-'
>@.
0
~
...J
g
~
...J
z
fB
a:
TP
HCl
CVBSO
ClKO
CVBS1
PIXClK
CVBS2
ClKSEl
CVBS3
elKIN
CVBS4
SCl
CVBS5
SDA
CVBS6
07
CVBS7
06
HSN
05
0
SAA7199B
04
03
02
01
DO
CSN
R/WN
PD1(6)
A1
PD1(7)
AO
0
N
0
a..
N
0
a..
N
N
0
a..
~
0
a..
~
N
0
a..
~
0
a..
W
N
0
a..
~
0
a..
>
0
...J
N
Cl
Cl
Cl
>
N
Cl
(f)
(f)
>
Z
CD
(,)
0
(;)
0
a..
N
C')
0
a..
(;)
0
a..
M
(;)
0
a..
~
(;)
0
a..
l!)
(;)
0
a..
W
(;)
0
a..
~
0
a..
a..
~
::z
MEH417
Fig,2 Pin configuration.
independently, and they generate
24-bit gamma-corrected output
signals from 24-bit data of one of the
input formats. or from 8-bit indexed
pseudo-colour data.
Required modulation is performed.
The digital VUV data is encoded
according to standards RS-170A
(composite NTSC) and CCIR 624-4
(composite PAL-BIG). S-Video
April 1993
output signal is available (VIC) as
well as some sub-standard output
signals (STD-bits in Table 6).
A 7.5 IRE set-up level is
automatically selected in the 60 Hz
mode - there is none in 50 Hz mode.
The analog signal outputs can drive
directly into terminated 75 n coaxial
lines, a passive external filter is
recommended (Figures 3 and 13).
3-522
Analog post-filtering is required
(LP in Fig.3).
GENLOCK to an external reference
signal is achieved by addition of a
video ADC and a clock generator
combination. Thus, the system is
enabled to lock on a stable video
source or to a stable VCR source
(normal playback). The SAA7199B,
the ADC and the clock generator
i
G)C
~
1m
mcE'
co
RTCO (from SAA7151B or SAA7191 B)
~
CVBSl
(1)
CLK
I
(1) I
GPSW
CVBS2
•• _••••••••••••••••••••••••••••••••••••••••••
(
C/)
0
2:0
l>
(1) necessary in GENLOCK mode
(2) RTCI optional (GPSW not possible)
-..J
...A.
Fig.3 System configuration.
<0
<0
OJ
s·
Sll
-
"0
<0
+5 V
~
0.1 ~F
0.1 ~F
H
H
+5V --~----------------------------~~~-----0.1 ~F
20kn
,
I~
1
0.1 ~F
0.1 ~F
0.1
~
H
H
V0001
V0002
V0003
V,ef H ICUR
2
21
41
63
~F
VODA1
71
66
0.1 ~F
0.1 ~F
~
:r
VOOA3
70
72
Z~
"0
1m
O-
C/)
n
~.
3
I
.
CD
1.23 V (p-p)
y
DAC2
01
en
75n (3)
2.7 ~H
digital input
and output
signals
of Fig.1
01
-u
G)C
mcC'
~
:----. load
analog
output
..
r---------~
1.23 V (p-p)
75 n (3)
DAC1
SAA71998
22
VSS01
IVSS02
42
IVSS03
62
V,ef L
68
VSSA
"'U
I~
MEH420 -1
3'
(1) without compensation of the DAC hold characteristic (Fig.14).
(2) with compensation of the DAC hold characteristic (sin(x)f x correction, Fig.14).
(3) output amplitude determined by load resistors R L > 90 n.
en
~
»
»
-..J
~
(")
CO
CO
o·
~
o·
...I.
Fig.15 Application details due to Fig.1. Proposals of analog low-pass post-filtering of output signals.
5'
OJ
- 1 f.tF.
Vsso
14
Ground: ground connection 0 for video outputs.
VDD
15
Power Supply: +5 V (typ.).
V SS2
16
Ground: ground connection 2.
LL3D/LL1.5D
17
Line-Locked system clock: 13.5 MHz or 27 MHz system clock input for the display,
memory interface and control sections.
AO/A9to
A8/A17
18 to 26
Address: multiplexed address outputs for the external nibble-wide dynamic RAM
(DRAM). With a 256 kbit (64K x 4) DRAM the address pin A8 is not used.
RAS
27
Row Address Strobe: active LOW output for the external DRAM.
CAS
28
Column Address Strobe: active LOW output for the external DRAM.
29
Read/Write: active LOW write enable signal for the external DRAM.
RIW
D3/D7 to DO/D4
30 to 33
Data: data inputs/outputs from the external nibble-wide DRAM.
Vss 1
34
Ground: ground connection 1.
VSS3
35
Ground: ground connection 3.
May 1994
3-551
Preliminary specification
Philips Semiconductors
Multi-standard Teletext
features TV
SYMBOL
Ie for standard and
SAA9042
DESCRIPTION
PIN
INT
36
Interrupt: open-drain active LOW output which provides an interrupt signal for a
microcontroller indicating the arrival of a page or packet in anyone of the acquisition
channels, change in newsflash/subtitle status or power-on reset.
SAND
37
Sandcastle: 3-level output for the SAA5191 representing the PljCBB Signal, derived
from the acquisition timing chain.
TIC
38
Teletext Clock: input from the SAA5191 supplied via an external coupling capacitor.
TID
39
Teletext Data: input from the SAA5191 supplied via an external coupling capacitor,
internally clamped to Vss for 4 to 8 !As of each line to maintain the correct DC level.
FRAME
40
Frame: output for de-interlacing circuits. The signal is LOW for even fields and HIGH for
odd fields when text but no picture is displayed. It is forced LOW when a TV picture is
present.
May 1994
3-552
Preliminary specification
Philips Sem iconductors
Multi-standard Teletext
features TV
Ie for standard and
SAA9042
FRAME
TIO
TIC
SANO
INT
VSS3
VSS 1
00/04
01/05
02/06
03/07
Rm
C DAC
CAS
vsso
RAS
v DD
Aa/A17
VSS2
A7/A16
LL30/LL 1.50
A6/A15
AO/A9
AS/A14
A1/A10
A4/A13
A2/A11
A3/A12
MEA066
Fig.2 Pin configuration.
May 1994
3-553
Preliminary specification
Philips Semiconductors
Multi-standard Teletext
features TV
Ie for standard and
SAA9042
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). All voltages are with respect to VSS1/2/3.
VSSO is considered as an output.
SYMBOL
CONDITIONS
PARAMETER
MIN.
MAX.
UNIT
Voo
DC supply voltage
-0.5
+6.5
V
100
DC supply current
tbf
tbf
rnA
V
VI
DC input voltage
-0.5
Voo + 0.5
II
DC input current
-20
+20
mA
Vo
DC output voltage
-0.5
Voo + 0.5
V
10
DC output current
-20
+20
mA
T stg
storage temperature
-65
+150
°C
Tamb
operating ambient temperature
-20
+70
°C
Yes
electrostatic handling
-1000
+1000
V
note 1
Note
1.
Equivalent to discharging a 100 pF capaCitor via a 1.5 kQ series resistor with a rise time of 15 ns.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
CHARACTERISTICS
Voo
=4.5 to 5.5 V; VSS1/2/3 =0 V; Tamb =-20 to +70 °C; unless otherwise specified.
SYMBOL
CONDITIONS
PARAMETER
TYP.
MIN.
MAX.
UNIT
Supply
Voo
DC supply voltage
100
DC supply current
note 1
4.5
5.0
5.5
V
-
100
-
mA
V
Inputs; note 2
TID; NOTE 3
VI(p_p)
input voltage (peak-to-peak value)
2.0
-
5.0
Cext
external coupling capacitor
-
22
50
nF
t r , tf
input rise and fall times
notes 4 and 26
10
-
80
ns
tSU;OAT
input data set-up time
note 5
40
-
-
ns
tHO;OAT
input data hold up time
note 5
40
-
-
ns
III
input leakage current
VI
-10
-
+10
~
CI
input capacitance
note 26
-
7
-
pF
tClon
clamp start time
note 6
3.5
4.0
4.5
f.,tS
tCloff
clamp finish time
note 6
7.5
8.0
8.5
f.,ts
ICl
clamp output current
note 7
1.0
-
-
mA
May 1994
=0 to Voo
3-554
Philips Semiconductors
Preliminary specification
Multi-standard Teletext
features TV
SYMBOL
TTC;
NOTE
Ie for standard and
PARAMETER
SAA9042
CONDITIONS
MIN.
TYP.
MAX.
UNIT
8
VI(p_p)
input voltage (peak-to-peak value)
2.0
-
5.0
V
Cext
external coupling capacitor
-
10
10
nF
11M
peak input current
-10
+10
mA
VIM
input voltage (peak value) relative
to 50% duty factor
±0.2
-
±3.5
V
t r , tf
input rise and fall times
notes 4 and 26
10
-
80
ns
CI
input capacitance
note 26
-
7
-
pF
Vel
input clamp voltage
1.2
1.4
1.6
V
fclk
clock frequency
-
6.9375
-
MHz
MHz
625 line
525 line
HSA;
NOTE
5.7272
9
Vil
LOW level input voltage
0
V IH
HIGH level input voltage
2.0
-
t r , tf
input rise and fall times
notes 4 and 26
III
input leakage current
VI
CI
input capacitance
note 26
-
=0 to VDD
-10
-
0.8
V
V DD
V
500
ns
+10
ftA
7
pF
VSA
V il
LOW level input voltage
V IH
HIGH level input voltage
note 27
2.0
t r , tf
input rise and fall times
notes 4 and 26
-
III
input leakage current
VI
CI
input capacitance
note 26
LL3A; TTL
MODE;
0
=0 to VDD
-10
-
-
0.8
V
V DD
V
500
ns
+10
ftA
7
pF
FIG.4
V il
LOW level input voltage
0
V
HIGH level input voltage
2.0
-
0.8
VIH
V DD
V
tCA
LL3A cycle time
69
74
80
ns
teAH
LL3A HIGH time
28
-
tCAl
LL3A LOW time
28
-
-
ns
III
input leakage current
VI
-100
ftA
input capacitance
note 26
-
+100
CI
10
pF
May 1994
note 10
=0 to VDD
3-555
-
ns
Philips Semiconductors
Preliminary specification
Multi-standard Teletext
features TV
SYMBOL
Ie for standard and
PARAMETER
SAA9042
CONDITIONS
MIN.
TYP.
MAX.
UNIT
LL3A; AC MODE; F = 13.5 MHz; SEE FIG.4
VACM
mean voltage level
-12
-
+12
V
VAC(p-p)
AC voltage (peak-to-peak value)
1.0
-
3.0
V
VACH
voltage HIGH w.r.t. mean
0.3
-
2.0
V
VACl
voltage LOW w.r.t. mean
-2.0
-
-0.3
V
msr
input mark/space ratio w.r.t.
mean tAcHitACl or tAcLitACH
30: 70
-
70 :30
Cs
series capacitance
47
100
220
pF
Zj
input impedance
10
-
-
kQ
-
1.5
V
Voo
V
notes 25 and 26
note 28
notes 24 and 26
SCL; NOTE 31
V il
LOW level input voltage
0
VIH
HIGH level input voltage
3.0
tr
input rise time
notes 4 and 26
-
tf
input fall time
notes 11 and 26
-
III
input leakage current
note 12; VI
CI
input capacitance
note 26
=0 to Voo
-10
-
-
1
fJS
300
ns
+10
!AA
7
pF
HSD
V il
LOW level input voltage
0
V
HIGH level input voltage
2.0
-
0.8
VIH
Voo
V
t r, tf
input rise and fall times
notes 4 and 26
-
50
500
ns
III
input leakage current
VI
-10
-
+10
!AA
CI
input capacitance
note 26·
-
-
7
pF
=0 to Voo
VSD
Vil
LOW level input voltage
0
-
0.8
V
V IH
HIGH level input voltage
2.0
Voo
V
t r , tf
input rise and fall times
-
-
500
ns
-10
-
+10
!AA
-
-
7
pF
notes 4 and 26
=OtoVoo
III
input leakage current
VI
CI
input capacitance
note 26
May 1994
3-556
Preliminary specification
Philips Semiconductors
Multi-standard Teletext
features TV
SYMBOL
Ie for standard and
PARAMETER
SAA9042
CONDITIONS
MIN.
TYP.
MAX.
UNIT
LL3D/LL1.5D; TIL MODE
Vil
LOW level input voltage
0
VIH
HIGH level input voltage
2.0
-
0.8
V
Voo
V
t r, tf
input rise and fall times
notes 4 and 26
-
-
10
ns
tCA
LL3D/LL 1.5D cycle time
13.5 MHz
69
74
80
ns
27.0 MHz
35
37
40
ns
-
ns
-
ns
-
ns
-100
-
+100
ItA
-
-
10
pF
-12
-
tCAH
tCAl
LL3D/LL 1.5D HIGH time
LL3D/LL 1.5D LOW time
13.5 MHz
28
27.0 MHz
14
13.5 MHz
28
27.0 MHz
14
=0 to Voo
III
input leakage current
VI
CI
input capacitance
note 26
LL3D/LL1.5D; AC MODE; f
ns
=13.5 MHz OR 27 MHz; SEE FIG.4
VACM
mean voltage level
VAC(p-p)
AC voltage
notes 25 and 26
1.0
VACH
voltage HIGH w.r.t. mean
0.3
VACl
voltage LOW w.r.t. mean
-2.0
msr
input mark/space ratio w.r.t.
mean tACwtACl or tACutACH
Cs
series capacitance
Zj
input im pedance
note 28
notes 24 and 26
30: 70
+12
V
3.0
V
2.0
V
-0.3
V
70 :30
47
100
220
pF
10
-
-
kQ
Inputs/outputs; note 13
SDA; OPEN-DRAIN I/O; NOTE 31
V il
LOW level input voltage
0
VIH
HIGH level input voltage
3.0
tr
input rise time
notes 4 and 26
tf
input fall time
notes 11 and 26
III
input leakage current
VI =0 to Voo; note 12;
with output off
-10
-
-
-
7
pF
0
-
0.4
V
-
-
300
ns
400
pF
CI
input capacitance
note 26
VOL
LOW level output voltage
IOl
tf
output fall time
notes 11 and 26
Cl
load capacitance
May 1994
=3 rnA
3-557
-
1.5
V
Voo
V
1
lAs
300
ns
+10
ItA
Preliminary specification
Philips Semiconductors
Multi-standard Teletext
features TV
SYMBOL
Ie for standard and
PARAMETER
SAA9042
CONDITIONS
TYP.
MIN.
MAX.
UNIT
00/04 TO 03/07
VIL
LOW level input voltage
0
VIH
HIGH level input voltage
2.0
III
input leakage current
note 12; VI =0 to V DD ;
with output off
-10
-
0.8
V
VDD
V
+10
~
CI
input capacitance
note.26
-
pF
LOW level output voltage
10L = 1.6 mA
0
-
7
VOL
0.4
V
VOH
HIGH level output voltage
10H = -200 ""A
2.4
-
VDD
V
t r• tf
output rise and fall times between
0.6 V and 1.B V
note 26
-
-
10
ns
CL
load capacitance
note 21
-
-
100
pF
Outputs; note 13
SAN D; NOTE 22
VOL
LOW level output voltage
10L = 0.2 mA
0
-
0.3
V
VOl
intermediate level output voltage
101 = :!:30 ""A
1.3
-
2 ..7
V
VOH
HIGH level output voltage
10H = 0 to -1 0 ~
4.0
VDD
V
tr
output rise time VOL to VOl
between 0.4 V and 1.1 V
note 26
-
-
400
ns
tr
output rise time VOL to VOH
between 2.9 V and 4.0 V
note 26
-
-
200
ns
tf
output fall time VOH to VOL
between 4.0 V and 0.4 V
note 26
-
-
50
ns
CL
load capacitance
-
-
30
pF
I NT; OPEN-DRAIN· OUTPUT
VOL
LOW level output voltage
10L = 1.6 mA
0
-
0.4
V
ILO
output leakage current
V pu =OVtOV DD ;
with output off
-10
-
+10
~
tf
output fall time
notes 15 and 26
CL
load capacitance
-
-
50
ns
-
-
100
pF
AO/A9 TO AB/A17
VOL
LOW level output voltage
10L = 1.6 mA
0
V
HIGH level output voltage
10H = .-200 ""A
2.4
-
0.4
VOH
VDD
V
t r• tf
output rise and, fall times between
0.6 V and 1.B V
note 26
-
-
10
ns
CL
load capacitance
note 23
-
-
100
pF
May 1994
3-558
Preliminary specification
Philips Semiconductors
Multi-standard Teletext
features TV
SYMBOL
RAS, CAS AND
Ie for standard and
PARAMETER
SAA9042
CONDITIONS
MIN.
TYP.
MAX.
UNIT
R!W
VOH
HIGH level output voltage
IOH = -200 ftA
2.4
t r , tl
output rise and fall times between
0.6 V and 1.8 V
note 26
-
-
CL
load capacitance
note 23
-
-
100
pF
-
0.4
V
VDD
V
VOL
LOW level output voltage
IOL = 1.6 rnA
0
0.4
V
VDD
V
10
ns
DISP PL AND FRAME
VOL
LOW level output voltage
IOL = 1.6 rnA
0
V OH
HIGH level output voltage
10H = -200 ftA
2.4
t r , tl
output rise and fall times
notes 16 and 26
-
200
ns
CL
load capacitance
-
-
200
pF
R, G, 8; 3-STATE; NOTE 29
VOL
LOW level output voltage
IOL = 2.0 rnA; note 17
Vsso
-
Vsso + 0.2 V
VOH
HIGH level output voltage
IOH = -2 rnA; note 18
-
note 30
-
V
output rise and fall times between
0.6Vand 1.8V
notes 4, 17 and 26
-
-
10
ns
-
-
30
pF
-
10
pF
ftA
tn tl
CL
load capacitance
Coff
output capacitance
off state; note 26
Ioff
output leakage current
off state; VI = 0 to V DD -10
-
+10
-
0.2
V
2.8
V
-
10
ns
-
30
pF
+10
ftA
-
10
ns
VDS; 3-STATE; NOTE 29
VOL
LOW level output voltage
IOL = 1.0 rnA
0
VOH
HIGH level output voltage
IOH = -200 ftA
1.1
tn tl
output rise and fall times
note 26
CL
load capacitance
-
Ioff
output leakage current
off state; VI = 0 to V DD -10
tskew
skew delay between R, G, Band
VDS outputs
note 19
March 1994
3-559
-
Preliminary specification
Philips Semiconductors
Multi-standard Teletext
features TV
SYMBOL
Ie for standard and
PARAMETER
SAA9042
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Timing
12 C-BUS;
NOTE 20; FIG.3
fSCL
SCL clock frequency
0
-
100
tLow
clock LOW period
4
-
~
tHIGH
clock HIGH period
4
-
-
!!s
tSU;DAT
data set-up time
250
-
tHD;DAT
0
tSU;STO
set-up time from clock HIGH to
STOP
4
-
-
ns
data hold time
!!s
tBuF
START set-up time following a
STOP
4
-
-
!!s
tHD;STA
START hold time
4
-
!!s
tsu;STA
START set-up time following clock
LOW-to-HIGH transition
4
-
-
!!s
ns
note 31
kHz
ns
MEMORY INTERFACE; NOTE 14; FIGS 5 AND 6
tCY
cycle time
-
481
-
tT
transition time
-
10
ns
tW;RAS
RAS pulse width
120
RAS precharge time
90
tHD;CAS
CAS hold time
120
tCY;PM
page mode cycle time
120
-
ns
tpC;RAS
-
td
RAS to CAS delay time
25
-
-
ns
tW;CAS
CAS pulse width
60
ns
CAS precharge time
50
-
ns
tSU;ROW
row address set-up time
0
-
ns
tHD;ROW
row address hold time
15
-
ns
tSU;COL
column address set-up time
0
-
ns
tHD;COL
column address hold time
20
-
ns
tSU;RD
read command set-up time
0
-
-
tpC;CAS
ns
tHD;RDC
read command hold time
referenced to CAS
0
-
-
tHD;RDR
read command hold time
referenced to RAS
10
-
-
ns
tAcc;CAS
access time from CAS
-
-
60
ns
tW;WR
write command pulse width
50
-
-
ns
tHD;WR
write command hold time
40
-
tSU;DATI
data input set-up time
0
ns
tHO; DATI
data input hold time
40
-
-
-
ns
March 1994
3·560
ns
ns
ns
ns
ns
Philips Semiconductors
Preliminary specification
Multi-standard Teletext
features TV
SYMBOL
Ie for standard and
PARAMETER
SAA9042
CONDITIONS
TYP.
MIN.
tACC;RAS
access time from RAS
-
tHO;RC
RAS hold time after CAS
60
tpC;CR
CAS to RAS precharge time
20
tH~;COLR
column address hold time
referenced to RAS
tHO;OATIR
data input hold time referenced to
RAS
MAX.
UNIT
120
ns
-
ns
80
-
-
ns
100
-
-
ns
ns
Notes
1. The rise time of Voo from 0 to 4.5 V must be >150 ns to ensure that the internal power-on reset triggers. For this
circuit to reset the chip, Voo must be initially <1.0 V or fall to <1.0 V for at least 100 ns. Spikes on Voo are tolerable
provided that Voo is not reduced to <2.5 V.
2.
All inputs are protected against static charge under normal handling.
3.
The TID input incorporates an internal clamping diode in addition to the active clamping transistor.
4.
Rise and fall times are measured between 10% and 90% levels.
5. Teletext input data set-up and hold times are measured with respect to 50% duty factor level of the rising edge of the
teletext clock input (lTC). Data stable 1 ~ 2.0 V, data stable 0 s 0.8 V.
6.
Clamp times measured from the line sync reference pOint, assuming acquisition timing is set correctly.
7.
Clamping transistor on, Vno - Vss 1 S 0.1 V.
8.
The TIC input has an internal clamping diode.
9.
HSA is falling edge triggered.
10. Minimum and maximum cycle times are ±7.1 % of the typical value.
11. Fall time is measured between 3.0 V and 1.5 V.
12. Applies even when Voo
=0 V.
13. All input/outputs and outputs are protected against static charge under normal handling.
14. For details of memory interface timings to and from external DRAM see Figs 5 and 6.
15. Output fall time measured between 4.0 V and 1.0 V levels with a 3.3 kQ load to 5.0 V.
16. Output rise and fall times measured between 0.8 V and 2.0 V levels.
17. Measured with IOL
18. Measured with IOH
=2.0 mA, Vsso =VSS 1/2/3 and output voltage (CoAd = 1.5 V.
=-2 mA, Vsso =VSS1/2/3 and output voltage (CoAd =0.5 to 1.5 V.
19. Skew delay time measured at 0.7 V levels.
20. For details of 12C-bus timings see Fig.3; timings are referenced to VIH
=3.0 V and VIL =1.5 V.
21. Load capacitance measured with two DRAM data inputs; 50 pF maximum.
22. A current of 1 ~lA flows out of the SAA5191 while its SAND input is in the range of 1 V to 3.5 V.
23. Load capacitance measured with eight DRAM data inputs; 80 pF maximum.
24. Through a 200 pF capacitor with a 13.5 MHz sinewave.
25. To be applied via a series capacitor only.
26. This specification point is included because of its importance to the application environment; it is not however
guaranteed.
27. When connected to the SAA5191, it is acceptable for the clock frequency to initially attain s15 MHz in order to
achieve synchronization.
March 1994
3-561
Philips Semiconductors
Preliminary specificatibn
Multi-standard Teletext
features TV
Ie for standard and
SAA9042
28. When connected to the SAA5191, it is acceptable for the input voltage to attainVoo + 0.9 V. The input current must
be restricted as specified in the limiting values.
29. These outputs can be made 3-state via the 12C-bus.
30. Typical values adjustable over 0.5 to 1.5 V via the 12C-bus.
31. A standard (100 kHz) 12C interface is implemented. Fast mode (400 kHz) is not supported.
SOA
sel
SOA
Fig.3 12C-bus timing.
ll3A
ll30/lL1.S0 - - -
Fig.4 Line-locked system clock LL3A and LL3D/LL1.5D timing diagram.
March 1994
3-562
Philips Semiconductors
Preliminary specification
Multi-standard Teletext
features TV
Ie for standard and
SAA9042
~----------------tCY----------------
__
~-----------tW;AAS----------~~
tpC;AAS
tpC;CR
tHO;COL
AO/A9 to AB/A17
r
~-----~~--------------
RfiJ
rtHO;OATI
~-V-A-Ll-O~X~________________
00/04 to 03/07
ML8446
Fig.S Memory interface !iming for write cycle to external DRAM.
March 1994
3-563
PhilipsSem iconductors
Preliminary specification
Multi-standard Teletext
features TV
Ie for standard and
SAA9042
~--~-------------tCY------------------~
~------------
tw;RAS---------,
RAS
CAS
AO/A9 to AB/A17
RtW
00/04 to 03/07
tACC;CAS
Fig;6 Memory interface timing for read cycle from external DRAM.
CHARACTER SETTINGS
The different character settings are explained in Tables 1 to 6.
March 1994
3-564
~
Table 1 SAA9042A West European character set; for N.D. (national option character position) see Table 2.
.
b
~
T
7
_
0
0
0
ba -
~3 ~2 ~'
O
b.
o
0
1~lumn
w
0
0
alpha·
numerics
blad<
graphics
black
alpha·
numerics
red
graphics
red
alpha·
numerics
graphics
o
0
0
1
1
o
0
1
0
2
o
0
1
1
3
alphanumerics
yellow
graphics
yellOlN
o
1
0
0
4
alpha·
numerics
blue
graphics
blue
o
1
0
1
5
o
1
1
0
6
alphanumerics
cyan
o
1
1
1
7
alpha- (2)
numerics
white
1
0
0
0
e
'lash
1
0
0
,
9
steady
,
0
1
0
10
end box
separated
graphics
1
0
1
,
"
startbcx
ESC
1
1
0
0
12
green
--J
alphanumerics
magenta
green
graphics
magenta
graphics
cyan
graphics
white
concaal
display
(2)
(2)
oontiguous
graphics
(2)
(1)
(2)
normal
height
1
1
0
1
'3
double
1
1
1
0
14
~;:~e
1
1
1
1
15
d~:le
height
blad< (2)
bad.
~
b7 _
T
S
0
0
0
bs b sb- _
0
3
b
2
b
1
b
0
0
1
0
graphics
black
alpha numerics
red
graphics
red
0
0
1
1
o
0
1
0
2
o
0
1
1
3
alpha numerics
yellow
0
4
alpha numerics
blue
alpha numerics
green
1
0
o
1
0
1
5
o
1
1
0
6
o
1
1
1
7
1
0
0
0
8
alphanumerics
magenta
w
0.
OJ
c:o
alphanumerics
cyan
alpha _(2)
numerics
white
0
0
0
o
1
1
0
1
1
1
1
0
1
0
o
1
1
0
o
1
0
1
0
1
9
28
3
38
4
5
6
68
7
78
8
1
0
1
1
9
o
0
o
1
1
1
1
o
1
1
1
1
1
CD
Wi
1
1
10
11
12
13
1
o
14
1
15
m
rn
~ [j ~ ~ ~ [B] [§] ~ [a ~ 00 ~ ~ [5J ~ ~
[:J
a. U [3] ~ ~ ~ [9 ~ [§] C ~ ~ [Q] [3] [§ ~ ~ [!]
[:J
a. ~ ~ iJ [g [] [g] ~ ~ LJ ~ [g [!] ~ [g ~ ~ [!]
~ [] ~ IJ ~ [g] ~ ~ ~ ~ C!J [Q ~ ~ [g [!] ~ ~
~ ~ [§] ij [E] ~ ~ ~ M ~ [fJ [g ~ [§] EJ [g 00 ~
~ ~ [Z] Ij ~ ~ ~ ~ ~ ~ [I] ~ ~ [Z] D ~ [I] [g
KJ ~ ~ ~ BJ [g] [!] [j ~ ~ 8 [!J KJ ~ ~ ~ ~ [!]
~ [§J ~ ~ ~ ~ Li M ~ ~ ~ [§J ~ [g ~ ~
~ ~ [] ~ g [f] [J [] ~ ~ [I)J [Q] ~ [I] [Q] [i5J [g [IJ
a. ~ LI [:J
a. ~ ~ LQ L±J [i] [g ~ ~ ~
L±J ~ [j] ~ ~ [:J
[J ~ ~ ~ [!d [:J [!J ~ [:J iii ~ [g [J ~ ~ ~ LQ ~
EJ ~ §] ~ H [[]a. ~ [[]a. Ii [m EJ §] i] ~ ~ [g
[J ~ ~ ~ ~ [:J
a. [6] ~ [:J
a. iI (iJ !l [J ~ [§ ~ [g ~
~~~~~:(2) [Z] ~ [1J ~ [g [[] [g ~ ~ I ~ W[Z] [1J [-J ~ [Ig 00
graphics
yellow
graphics
blue
graphics
magenta
graphics
cyan
graphics
white
n>
(J)
a. [B [:J
a. ~ [Q ~ [I [g D [g [I [I 00 ~
D D [g ~ [:J
rn LJ [IJ (] ~ [Q] ~ ~ [g ~ ~ ern rn [IJ ~ LQ ~ ~
graphics
green
-g
T
(J)
--1:::J
<
~
3
8·
::J
O>
.,
g$l
0..
en
0..
0
CD'
CD
~
o
r-+
0'
.,
(J)
n>
:::J
0..
0>
a
0>
:::J
0..
conceal
display
flash
(2)
1
2
alpha·
numerics
black
o
o
0
1
o
1
0
1
0
1
~
~
o
w
0
0
1
0
tttt~IUmno
o
o
0
0
0
4
b
0
0
""U
s:
c
CD
o:::r
steady
(2)
(2)
contiguous
graphics
rn
rn
separated
graphics
1
0
1
0
10
end box
1
0
1
1
11
slartbox
1
1
0
0
12
normal
heigh1
(1)
(2)
13
~~~~~~
0
14
~i~~~e
1
15
d~~~e
1
1
0
1
1
1
1
1
1
1
ESC
black (2)
back·
ground
new
background
hold
graphics
1:1.
1:1.
m
m
""U
i
3·
(J)
»
»<.0
o~
I\)
~.
-<
~
CD
£:
o·
a
o·
::J
Preliminary specification
Philips Semiconductors .
Multi-standard Teletext Ie for standard and
features TV
SAA9042
Notes to Table 5
1. These control characters are reserved for compatibility with other data codes.
2. These control characters are presumed before each rows begins.
Table 6 SAA9042C Euro-Turkish national option sets.
PHCB(l)
CHARACTER POSITION (COLUMN I ROW)
LANGUAGE
C12 C13 C14 2/3
ENGLISH
GERMAN
(2)
ITALIAN
FRENCH
SPANISH
TURKISH
o~
2/4
4/0
5/11 5/12 5/13 5/14 5/15
6/0
7/11 7/12 7/13 7/14
m
I] ~ ~ ~ [f] [I] 8 ~ [II] ~ ~
1[1] I] [SJ [8J [g [g EJ D ~ ~ [§ [g ~
1~ I] ~ ~ [Q ~ [f] [I] ~ ~ [Q] ~ [!]
1 o~ 00 ~ ~ ~ ~ 00 [I] ~ ~ [Q] ~ [Q
1[Q I] OJ ~ ~ [!] [Q] ~ ~ [g L5J ~ ~
1 o[!] ~ ~ ~ [g lCJ [g ~ ~ ~ [§ [Q [g
0
0
0
0
0
1
0
1
0
1
MLB452
Notes
1. Other combinations of C12, C13 and C14 default to English.
2.
Basic character set is Italian. Selected when the force language bit (DS) in the display set-up register (R12) is set to
logic 1.
March 1994
3-570
Preliminary specification
Philips Semiconductors
Multi-standard Teletext
features TV
Ie for standard and
SAA9042
APPLICATION INFORMATION
I-
:::>
Z
a..
0
f::
l-
:::>
()
Oen
OW
w(!J
Q~
>en
~
u..
w
0
w
:E
00 «
en (!J
0
a:
> a: u..
i~
~
'E0
a..
en
Ci
()
I
I
E
..,.C\I
oo~
en....J
w«
a: Z
~Q
«Ii:
Wo
u..~
:E
0
«
a:
----~-
0
en
cil
>-
~
Ii:
a:
a:
W
Ow
()O
Z
00
a:
0
en
en
C/)
W
()()
zO
>-a:
en a..
I~
a:
W
(!J
....J()
I-
:::>
a..
:E
0
0
@~
0
()
>0..
:E
0
_a:
a:
()
-sB
E<=
0
I])
"C
os:
1])0
~O
March 1994
00
l"-
:::>
00
()
ro
:::>
(!J
>en
III
>
:::>0
*
°
------
a:~
~::J
OJ
....J
~
c
0
3-571
u::
-u
s:
CDS:
0> c
III
(1
~
to outpy: stages
(0
(0
B
+>-
G
B
VDS
100n1100n1100nFl
1T
~
1
r
FRAME'
~ FRAME
::1:'
l
n.C.- STTV
CVBS
-p
fromtuner
~ CV
2.2
W
750
.
10
13
SAA5191
7
~-
14
26
24
DO/04
A8/Ar
AO/A9
w
a,
-...I
N
2.7kO
19
INPUT
LEVEL
BLACK
LEVEL
TTD
TTC
CBB
PL
PULSE
TIMING
C
PULSE
TIMING
R
VCS
FILTER 2
F13
SCS
HF
FILTER
21
15
f.lH
20
5.6 pF 18
II
_
22nF
~
14
m
39
10 nF
38
lr
37
10
22
~2:6}
{
18
FILTER 1
~
17
3
STORE I 4
HF
15
STORE
AMPLITUDE
STORE I 6
OSCIN
ZERO
LEVEL
DATA 18
TIMING
OSCOUT
~'''O
II
••
" I nF
lr
nF
(1)
,,22 nF
r-+
0"
0>
--1:J
<0..
0>
--,;
0..
m
3
0
::::l
0-
c
S
@
~
CD
CD
><
TTD
+5V
V DD
TTC
SAND
100 pF
L - . , interrupt}
SCL
VS S2
1:
----+-}
SDA
I C
-+-+
VSSI
2
6 _ _ _-,
VSD 1-1_
HSO~7
JL
~
-U-
LL3D/LL 1.5D
VSS3
-
17
0
--,;
to/from
microcontroller
:J
},~_
.,,' """ok
cirCUits
line flyback
100 pF
en
r-+
0>
0..
0>
--,;
0..
0>
:J
0..
,L35
-U-
} from colour
decoder
burst gate
pulse
MLB454
(1)
,,270 pF
lr
(1)
O~
(1)
+12V
en
,"en
(j)
()
,,470 pF
-,r
--,;
CD
en
r-+
r-+
RAS
II
13.875 MHz
12
PJW
CAS
C
r-+
LL3A
" 15 pF
AO
SDA
VSA
28
100 nF
VSS
I
VSSO
DISP PL
1100PF1
L
DO
A8
33
I C OAC
HSA
23
{~D:3 ~DD-r
j 6~:~ .
3:0} _ _ _ __
- 1-=29=----_ _ _ _ _ _ _--1
SAA9042
R
t
~10W
n.c.-l EXD
SELECT
0311r
r-+
~
is·
t15"
(1) Values for 625/525 line applications.
MODE
SAA5191
PIN
-I
15W
Fig.B SAA9042 solution for 50/60 Hz analog TV (1 H/1 V) - scan sync mode.
UNIT
625
525
5
470
560
pF
8
270
330
pF
9
100
120
pF
11
13.875
11.4545
MH
12
27
39
pF
-u
i
(J)
»
»
CO
o
~
rv
3"
s·
~
-
''''
""'t
Q.
~
~
SDA
II
7
LL3A
P
116
""
HSD
17
LL3D/LL 1.5D ~
VSS3
I
0
c.
c
(")
8'
(jl
0
interrupt}
}
""'t
to/from
microcontn lIer
12C
en
.0>
:J
Q.
II
--l L-
0>
""'t
field flyback }
JL
line flyback
27 MHz clock
Q.
from
features
box
0>
:J
Q.
135
""
o·
:::J
CD
.CD
X
.0
+ 5V
22
C/)
CD
3
a;f
~
VSD 1 - - - - - - ,
VSA
V SS2
T
AO
_
RIW
CAS
-
256K4
DRAM
,"
6
HSA
::
100 F
-
~
54
8
I
~~ lC
VSS
OnF
-
.- . C
""'t
CD en
en .0>
~
-0'
en
ML8455
" 470 pF
~r
" 22 nF
Ir
8
(1)
" 270 pF
"(1)
9
" 100 pF
~~
(1) Values for 625/525 line apPlications._
II
XTAL - ' L
GND
(1)
]16 22nF
I
,<--__
+12 V
'
I
AO/A9 r------18
_
29
R/W
CAS 28
_
27
V
VDD '---
I
" ";l) Of<>1
~,i~~
VCC
~
25
17
HF
STORE
AMPLITUDE
TTD
TTC
SAND
37
1
n.c.- DISP PL
F13
28
SCS n.c.
HF
3
" 15 pF
FILTER"
STORE 4
" 1 nF
FILTER 2
,--_ _' _2_1, FILTER 1
D~
38
"
,k
VCS
l
l
15
14
~----I VSSO
22 nF'~
39
10
_ 22 r
PL ~
blMING
PULSE
TIMING
R
C DAC
+
~~ 10~
EXD
47 nF ~
F
SAA9042
-0---
{- ~3
{= ~:
I
I
13
SAA5191
~O}
A:~~~: :~:}
R
"'"
r-:..
~DS
10
CV
r-
I
l..-----------l G
STTV
.n+27
75Q
D3I~7
FRAME
11
1
C
+5V
FRAME'
VDS
CDS:
0> c
r
15pF
--4-_-I'nll-'-+----+
1~~ ~":
Fig.9 SAA9042 solution for features TV (2H/1 V or 2H/2V).
S. .5191
MODE
PIN
625
5
470
UN T
525
560
"U
~
pF
3'
-
8
270330
pF _
9
100
120
pF
(J)
11
13.875
5
11.4545
5
MH-
12
27
39
pF
»CO
»
o
~
f\)
5'
III
-
40
FRAME
I
I
n.c.
+12 V
~:}
D3ID7
DO/D4
VDS
D3
{
VDD
:
DO
100 nF
12
n.c.----t B
A8/A17 1--26}
::
11
n.c.--t G
STIV
CVBS
from tuner
10
T
u---l CV
750
.
22
. llf'
·n.c.~
l68nF
220pF
SAA5191
T
C
I
6.8 KH
2
233 I PULSE
~TIMING
R
cp
19
(]1
-...J
FILTER 2
15
II 22nF
TID 1
TIC, 14
_
10
CBB
2_?
PL
21
FILTER 1
47nF l
Jf"
+12V
.- I OSC OUT
(1)
27 pF
15J.lH
SM9042 RIW
Vce
DAC
SCS
~
n.C.
I
4700
15 pF
_
CAS
RAS
1
1
~
8
100 pF
-
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Philips Semiconductors
Product specification
Digital multistandard TV decoder
SAA9051
FEATURES
GENERAL DESCRIPTION
•
The SAA9051 digital multistandard
decoder (S-DMSD) performs
demodulation and decoding of all
quadrature modulated colour TV
standards, as well as performing
luminance processing for all TV
standards with CVBS or VIC input
signals.
All operations based on a
sampling frequency of
13.5 MHz, providing:
- full adaptability to all
transmission standards
- capability for memory-based
features
• Separate chrominance and
luminance input (VIC)
• CVBS input for standard
applications
• CVBS throughput capability for
SECAM application
•
Luminance signal processing for
all TV standards (PAL, NTSC,
SECAM, BIW)
•
Horizontal and vertical
synchronization detection for all
standards
• Chrominance signal processing
for all quadrature amplitude
modulated colour-carrier signals
•
Requires only one crystal
• Controlled via the FC-bus
•
User-programmable aperture
correction (horizontal peaking)
• Compatible with memory-based
features (line-locked clock)
• Cross-colour reduction by
chrominance comb-filter (NTSC)
• Wide range hue control
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
SAA9051
May 1991
PACKAGE
PINS
68
I
I
PIN POSITION
PLCC
3-575
I
I
MATERIAL
plastic
CODE
I
ISOT188AGA, Cel
-u
~
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0
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CD
~
~
GAIN
CONTROL
.CIRCUIT
14
CVBS1
15
16
CVBS2
CVBS3
CVBS4
CVBS5
17
20
21
22
CVBS6
CVBS7
23
100
I1111,"~'"~;=,":;'~",~,
101
102
00'
YC
lSI
OO"'''~''''
DQ1
,
SCB
CHROMINANCE
BANDPASS FILTER
T
--.J
O'l
106
,..
I SCT
(channel 1)
107
PF
V DD
V DD
VSS
~
52
19
51
VSS
TEST
RES
2
3
BY
YPN
~+ ~ H
I
t
t
BP1
BP2
PREFIL TER
LCU
I
a.
(channel 2)
V
COMBFILTER
LCV
t
~
CD
CD--+
I
DCA
n
0
0
a.
CD
-.,.
UVO
UV1
UV2
CO--+I
t
AP1--+
FIXED DELAY
COMPENSATION
a.
CI--+
UV3
YOLO - YDL2
~
COR1
COR2
AP2--+
I
<
LIMITER
CORNER
CORRECTION
(CORING)
f
(fl
a.
U
COMBFILTER
=)=t=6=IN ~
CHROMINANCE
TRAP
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ALT
VARIABLE
BANDPASS
FILTER
3
0
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QUADRATURE
DEMODULATOR
tn.f
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n.Q
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CCFRO
104
105
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103
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DISCRETE
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T'
su
I
CCFR1 --+1
GQ
3
~
DIVIDER
I
CCFRO--+
(PART)
CVBSO
ALT
HUE--+
SAA9051
W
or
-
INC1
~
if
CS'01
TIME02
VARIABLE
AND
ADDING
STAGE
03
TlON
OEC--+I
~
(channel 3)
04
05
OEY--+
06
AC1--+
07
VB
BL
FOE
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PREFIL rER
SYNCHRONllA nON
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HLOCK
XCL
CRYSTAL
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GENERATOR
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0
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12C
INTERFACE
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SP
YC
DETECTORS
~ (C6ARS~ & FINE)
YDLO - YDL2
40
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VTR
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XCL
DISCRETE
TIME
OSCILLATOR 2
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COUNT
VTR_
HORIZONTAL
&
VERTICAL
PROCESSING
IDEL
SYC_
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SS2
SS3
it]
HLOCK
HLOCK
25
PONRES
SSO
AFCC
30
RES
DIGITAL· TOANALOG
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68
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HS
VS
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Philips Semiconductors
Product specification
Digital multistandard TV decoder
SAA9051
PIN CONFIGURATION
C"l
2
2
C"l
0
N
2
...J
...J
2
I~
I-
u
l-
e{
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104
60
n.C.
105
59
n.C.
106
58
UVO
107
UV1
eV8S0
UV2
UV3
eV8S1
15
eV8S2
16
n.c.
eV8S3
17
01
SAA9051
VOO
VOO
18
VSS
19
51
VSS
eV8S4
20
50
02
eV8S5
21
49
03
eV8S6
22
48
04
eV8S7
23
47
05
SS2
24
46
06
SS3
25
45
07
He
26
44
n.c.
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7Z97944.1
Fig.3 Pinning configuration.
May 1991
3-578
Philips Semiconductors
Product specification
Digital multistandard TV decoder
SAA9051
PINNING
SYMBOL
PIN
DESCRIPTION
n.c.
1
not connected
TEST
2
test input (active HIGH); when HIGH enables scan-test mode, always
connected to ground
RES
3
reset input (active LOW); results in the 12C-bus control registers 1 to 3
and internal stages being reset during the reset phase. The minimum
LOW period of RES is 120 LL3 clock cycles
LL3
4
13.5 MHz line-locked system clock
n.c.
5
not connected
100 (LSB) - 107
(MSB)
6 - 13
bidirectional data path; chrominance input for separate luminance and
chrominance input (Y/C) or CVBS output for SECAM decoder SAA9056.
Two's complement format (100 is only used internally for CVBS
throughput)
CVBSO (LSB) CVBS7 (MSB)
14 - 17, 20 - 23
digitalized composite video blanking and synchronization signals;
containing luminance, chrominance and all synchronization information
or luminance, blanking and synchronization signals in the event of
separate luminance and chrominance (Y/C) input. Two's complement
format (CVBSO is only used internally for CVBS throughput)
positive supply voltage (+5 V)
V DD
18
Vss
19
ground (0 V)
SS2-SS3
24 - 25
source select output signals; 12C-bus controlled, TTL compatible switches
HC
26
programmable horizontal output pulse; when used in conjunction with
input circuits (e.g. ADC) indicates the black-level position before
analog-to-digital conversion. The start and stop times are programmable,
between -9.4 I.1s and +9.5 I.1s in steps of 74 ns, via the 12C-bus
n.c.
27 - 28
not connected
HSY
29
programmable horizontal output pulse; when used in conjunction with
input circuits (e.g. an ADC). It indicates the synchronization pulse
position before analog-to-digital conversion The start and stop times are
programmable, between -14.2I.1s and +4.7I.1s in steps of 74 ns, via the
FC-bus
VS
30
vertical synchronization output; indicates the vertical position of the
picture for 50/60 Hz field frequency
May 1991
3-579
Philips Semiconductors
Product specification
Digital multistandard TV decoder
SAA9051
PINNING (continued)
SYMBOL
PIN
DESCRIPTION
HS
31
horizontal synchronization pulse output (duration =64 LL3 clock cycles).
HS is programmable, between -32 Ils and +32 Ils in steps of 300 ns, via
the 12C-bus
XCL2
32
clock output; half of the crystal clock frequency (12.288 MHz). In phase
with crystal (pin 33)
XTAL
33
crystal oscillator inputlinverting amplifier output; input to the internal
clock generator from an external oscillator or output of the inverting
amplifier to an external crystal (24.576 MHz)
XTALI
34
input to the inverting amplifier from an externctl crystal (24.576 MHz);
connect to ground if an external oscillator is used
n.c.
35
not connected
LFCO
36
line frequency control; analog output representing a multiple of the line
frequency (6.75 MHz) with 4-bit resolution, the phase of which is
compared to the system clock by the CGC (SAA9057 A)
n.c.
37 - 39
not connected
SOA
40
FC-bus serial data input/output
SCL
41
12C-bus serial clock input
BL
42
blanking signal output (active LOW); indicates the active video and line
blanking periods. BL also synchronizes the data
multiplexers/demultiplexers
SA
43
12C-bus select address; input for selection of the appropriate 12C-bus
slave address
07 (MSB)01 (LSB)
45 - 50,53
luminance data output
Vss
51
ground (0 V)
V DD
52
positive supply voltage (+5 V)
n.c.
54
not connected
UV3. - UVO
55 - 58
multiplexed PAL or NTSC colour difference signal output or SECAM CS
input signal from the SECAM decoder. Output data format is two's
complement. The multiplexer is synchronized to the rising-edge of BL
n.c.
59 - 63
not connected
FOE
64
fast output enable signal (active LOW); sets 01 - 07 and UVO - UV3
outputs to the HIGH-impedance Z-state
SSO - SS1
65 - 66
source select output Signals, set via the 12C-bus; used to control the
input switch (e.g. TOA8708)
n.c.
67
not connected
AFCC
68
additional output for circuit control; activated via the 12C-bus
May 1991
3-580
Philips Semiconductors
Product specification
Digital multistandard TV decoder
FUNCTIONAL DESCRIPTION (see
Fig.1)
The S-DMSD performs the
demodulation and decoding for all
quadrature modulated colour TV
standards (PAL-B. G. H. I. M, N,
NTSC 4.43 MHz and NTSC-M), as
well as performing luminance, and
parts of the synchronization,
processing for TV standards (PAL,
NTSC and SECAM). All of the
controllable functions, user as well
as factory adjustments, are
accessed via 12C-bus thereby
enhancing the adaptability of the
digital TV concept.
Operation is based on a line-locked
sampling frequency of 13.5 MHz,
thus making the system fully
adaptable to all line frequencies.
Only one crystal is required for all
TV standards.
The S-DMSD is designed to operate
in conjunction with the SAA9057A
Clock Generating Circuit (CGC). If
the CGC is not utilized the designer
must ensure:
• a reset pulse is applied to the
S-DMSD after a power failure
Y/C processing
In the Y/C mode:
• The chrominance signal is input
at the 10 port (100 - 107) and
transmitted via the input
switch/SECAM delay
compensation circuit
(multiplexer) to the chrominance
bandpass filter, 'see section
Chrominance path'.
• The other components, Y signal
and synchronization pulse, are
input via inputs CVBSO - CVBS7
and transmitted via the input
switch/SECAM delay
compensation circuit to the
luminance prefilter.
May 1991
SAA9051
eVBS proceSSing
In the CVBS mode:
• The CVBS signal is separated
into its luminance (VBS) and
chrominance (CG) parts by the
chrominance trap and bandpass
circuits. These Circuits can be
switched by the standard
identification signals (CCFRO,
CCFR1IYPN) according to the
detected colour-carrier
frequency, 3.58 MHz or
4.43 MHz.
• On reception of a SECAM signal
the signal is transmitted to the
SECAM decoder (SAA9056) via
the 10 port (100 - 107). Bit CT
enables the 3-state buffer
between both parts.
Luminance path
After the chrominance trap stage
(see Fig.1), the luminance path is
separated into three Channels as
follows:
CHANNEL
1 SIGNAL
The Channel 1 signal is transmitted
to the programmable bandpass filter
where the high luminance
frequencies are removed (centre
frequency is programmable via bits
BP1 and BP2). The BC signal is
transmitted to the coring (corner
correction) stage where low
amplitlide noise is removed (amount
of low amplitude noise removal is
programmable via bits COR1 and
COR2). The HF signal is· transmitted
to the weighting and adding stage,
see section 'Combining Channel 1
and Channel 2 signals'.
CHANNEL
2
SIGNAL
The Channel 2 signal is transmitted
to the fixed delay compensation
stage where delay compensation
and black-level adjustment occurs.
The DCA signal is transmitted to the
3-581
weighting and adding stage, see
section 'Combining Channel 1 and
Channel 2 signals'.
COMBINING CHANNEL
1 AND
CHANNEL
2
SIGNALS
The Channel 1 HF Signal is
weighted and added to the
Channel 2 DCA signal. The
combined Signals are matched to
the specified amplitude and the
word size is reduced to 7 bits. The
AVO signal is transmitted to the
variable delay compensation stage
where compensation for IF group
delays occurs, the amount of delay
is programmable (from -4 to +3 LL3
clock cycles, see note) via bits YDLO
- YDL2. The Y signal is transmitted
to the time multiplexed interface
where the Signal is output via D1 D7.
CHANNEL
3
SIGNAL
The Channel 3 VB Signal is
transmitted to the prefilter
synchronization stage, see section
'Synchronization path'.
Note
Differences in the delay
compensation required for PAL and
NTSC are catered for by
identification signal YPN which
switches the chrominance trap to
the appropriate colour-carrier
frequency 3.58 MHz or 4.43 MHz.
Chrominance path (see Fig.1)
The chrominance CG signal is
transmitted from the chrominance
bandpass stage to the gain control
circuit (see note 1). The gain control
stage ensures that the chrominance
signal has constant burst amplitude.
The GO signal is transmitted to the
quadrature demodulator, where
demodulation of the quadrature
modulated chrominance GO Signal
to colour difference signals occurs.
Product specification
Philips Semiconductors
Digital multistandard TV decoder
The OLU and OLV signals are;
transmitted to a low-pass filter. The
LCU and LCV signals are
transmitted to the limiter and
comb-filter stage. The comb-filter
stage (see note 2) separates the
remaining vertically correlated
luminance components for NTSC
(for PAL, the signals are phase
corrected). The CCU and CCV
signals are transmitted to the
colour-killer and PAL switch stage
(see note 3). At this stage signals
which do not comply with the
selected standard are removed. In
the PAL mode this stage restores
the correct phase of the, V signal.
The signals are then transmitted to
the time multiplexed interface and
output via UVO - UV3.
Notes
1. The gain control stage is
controlled by the AG signal
which is derived from the
amplitude and colour-killer
detector stage (ACKD). A
non-standard burst-to-amplitude
ratio results in the automatic
colour-leveling stage functioning
as an amplitude detector to
ensure correct amplitude and
avoid overflow/limiter defects.
2. The c.omb-filter can be altered
from alternate to non-alternate
mode by the ALT signal.
3. The colour-killer and PAL
switching stages are controlled
by the amplitude and
colour-killer detection circuit
using the AC1 and CD signals.
May 1991
SAA9051
COLOUR-CARRIER FREQUENCY
REGENERATION
The regeneration of the
colour-carrier frequency is
performed by the phase-locked-loop
(PLL) which comprises a quadrature
demodulator, low-pass filter, burst
gate, loop filter 1 and
divider/discrete time oscillator
(DTOt). The DT01:iscontrolied by
the standard identification signals
CCFRO - CCFR1 and the Hue signal
which influences the demodulation
phase .of the chrominance signal.
Synchronization path
In the synchronization circuit,
prefilter synchronization is
implemented to normalize the
synchronization pulse slopes. A
synchronization-slicer provides the
detected synchronization pulses
(SP) to the horizontal and vertical
processing and phase detector
stages.
HORIZONTAL AND VERTICAL PROCESSING
The horizontal and vertical
processing comprises part of a PLL
circuit for regeneration of the
horizontal synchronization (HS) and
an adaptive filter for detection of the
vertical synchronization (VS). The
horizontal and vertical processing
also generates:
• coincidence signal (HLOCK)
which controls the mute function
• standard identification signal
(FD) which identifies-nominal
525 or 625 lines per picture.
3-582
PHASE DETECTORS
The phase detectors that receive the
SP signal, also part of the PLL,
control the generation of the
line-locked clock (PL). Lbopfilter 2,
which has a variable bandwidth
dependent on the time constant
signal (VTR), generates two
increment signals (INC1 and INC2)
with different delays. INC2 is
programmable via the increment
delay signal (IDEL). INC1 corrects
the regenerated subcarrier
frequency at Dr01 and INC2
performs phase incrementing of
DT02. The crystal clock generator
provides a stable 24.576 MHz clock
input to DT02 which in turn supplies
the 4-bit DAC with a digital control
signal of 432 or 429 times the line
frequency. The analog output LFCO,
from the DAC, is transmitted to the
SAA9057A (CGC).
Output interface
The signals OEY, OEC, CO, CI and
CD control the output interface (see
Fig.6). All but one of these signals
are received via the 12C-bus, except
the CD signal which is detected in
the S-DMSD. A power-ON reset
results in these signals being set to
zero.
Philips Semiconductors
Product specification
Digital multistandard TV decoder
SAA9051
Table 1 Vertical Noise limiter
(VNl) signal
VNL
OUTPUT
0
VNl bypassed
1
VNlactive
Table 2 CO, CI and CD signals
CO
CI
CO
0
X
X
UVO - UV3
OUTPUTS
colour OFF (zero)
OUTPUT STATUS
1
0
0
UVO - UV3
colour OFF (controlled by CD)
1
0
1
UVO - UV3
colour ON (controlled by CD)
1
1
X
UVO - UV3
colour forced ON
Where:
X = don't care.
Table 3 OEC, OEY, FOE, Bl, D1 - D7 and UVO - UV3 signals
BL,VS,HS
01· 07
UVO· UV3
OEC
OEY
FOE
0
0
X
HIZS
1
1
1
active
HIZS
HIZS
1
1
0
active
active
active
0
1
1
active
HIZS
HIZS
0
1
0
active
active
active
HIZS
HIZS
REMARKS
status after power-ON reset
Where:
X = don't care
HIZS = HIGH-impedance Z-state.
Note to Table 3
Combinations other than those shown in Table 3 are not allowed.
FOE signal
In PIPCO (picture-in-picture
controller, SAA9068) applications,
the PIPCO requires access to the
digital YUV-bus on a pixel
time-base. This requirement is
catered for by PIPCO generated
signal FOE, which forces all data
output of the S-DMSD and DSD
(SAA905G) into the
HIGH-impedance Z-state. The FOE
signal does not affect the
May 1991
synchronization data lines (HS and
VS) or the blanking data line (SL),
see Fig.7.
CSsignal
The CS signal is transmitted from
the digital SECAM decoder (DSD)
during the horizontal-blanking period
and is received via the UV2 input
(see Fig.G). The CS bit is read by
the S-DMSD once per line at ll3
clock cycle number 748 (see Fig.8).
3-583
12C bus interface
(see Tables 1 to 3)
The following control signals are
received via the 12C bus interface:
• standard identification signals
(CCFRO, CCFR1, All FS, YPN)
• video recorderlTV time constant
(VTR)
• hue control (HUE)
• delay programming of the
horizontal signals (HS, HC, HSY)
Product specification
Philips Semiconductors
Digital multistandard TV decoder
SAA9051
• chrominance output enable
(OEC)
• SECAM chrominance delay
compensation (SCDCO, SCDC1,
SCDC2, SCDC3, SCDC4,
SCDC5, SCDC6).
• luminance delay compensation
(YOLO, YDL 1, YDL2)
• switch signals (source select
signals SSO, SS1, SS2, SS3)
• horizontal sync (HSY) and clamp
(HC) pulse disable (SYC).
• fixed clock generation command
(HPLL)
• additional output for circuit
control (AFCC)
Signals transmitted from the
S-DMSD via the 12C bus are:
• internal colour ON/OFF (CO)
• chrominance source select
CVBS/chrominance inpuVoutput
(CTIYC).
• standard identification signals
(FD, CS)
• increment-delay (I DEL)
• luminance aperture-correction
control (BY, PF, BP1, BP2,
COR2, COR1, AP2, AP1)
• internal colour forced ON, test
purposes only (CI)
• luminance and sync output
enable (OEY)
• vertical noise limiter (VNL)
activelbypassed
May 1991
• colour-killer status signal (CD)
• coincidence information (HLOCK)
• power-on-reset of S-DMSD
(PONRES).
3-584
Philips Semiconductors
Product specification
Digital multistandard TV decoder
+63
: reserved
+47
r~J"=--
r--r
__1
+63
+38
chrominance
+DC
0
-31
SAA9051
-
input
+-blacklevel
-50
sync
t
0
-38
+
-64
+115
r--r
luminance
output
range
+64
+7
0
~
chrominance
input range
(red, cyan and
nominal)
____1______
-64
(a)
+127
r-----r------
__ L
(b)
+63
+50
0
+53
-51
r------
0
U-component
output range
I
(C)
+63
1------
V-component
output range
___1__
-54
-64
~ __ i __
-64
(d)
(e)
7Z28075
(a) CVBS1 to CVBS7 input range
(b) 101 to 107 input range
(c) Y output range
(d) U output range (B-Y)
(e) V output range (R-Y)
FigA Diagram showing input/output range of the S-DMSD; all levels in EBU colour bar, values in binary,
100% luminance and 75% chrominance amplitude.
May 1991
3-585
-u
~
0
til
'<
cO"
or
--
CD
~
~
"6'
(/)
CJ)
CD
3
n-
3
C
o::J
;::::t:'
c:
Cii"
Q)
Cl-
~
0
Cil
:::J
0-
..,
Q)
0~
<
INPUT SWITCH
0eD
()
0
CVBSI - CVBS7
CVBSO - CVBS7
~
"
"
~I
SCT to prefilter
and chrominance trap
I
}
0-
eD
..,
CT
YC
w
c:n
0)
0>
I
100 - 107
~
,
~
~
101 -107
I
L
I
CT
I
YC
I
r---r---r---r---,
I
I
I
I
I
L ___ L ___ L ___ L ___ J
slave receiver byte CONTROL 3
subaddress OA
SCB to chrominance
bandpass filter
r---.----,r----r----~--_,----_r----r_--_,
I
L___
~
__
~
____
~
__
~~
__
~
____L __ __ L_ _
slave receiver byte SECAM delay compensation
subaddress OB
~
7Z28076.1
-u
a
en
~
<0
Fig.5 Schematic diagram of the input switch.
o
01
-L
Cl-
c:
~
(/)
'0
~
g
0'
::J
~
o
Ql
'<
en
(l)
;:::::t.:
3
c
CO
;::::+
00'
1 - 1- - - - - - - - - - - - - - ,
5>
::l
r~J=J=I~~r~I=I~l~J
slave receiver byte CONTROL 1
subaddress 08
IOEYIOECI
3
(')'
o:J
a.
c
n-
o
en
a.
EJ
..,
0>
a.
--i
<
gated
LL3 ----.
pulse
"
[
"U
~
-6'
en
•
~ UVO - UV3
a.
CD
()
o
a.
~-T-T-l
CD
..,
..L.:...l_..L_.l.._...J
slave receiver byte CONTROL 2
subaddress 09
w
cJ,
CD
-..j
IpONI-T-T-T
RES
_..l.._...L_...L
slave transmitter byte
EEl
,
+-_ _ _-+___+-_ _ _ _
I
...J
FOE (internally synchronized
by the system clock LL3)
01 - 07
BL
HS
VS
"U
7Z81094.4
Fig.6 Schematic diagram of control signals at the output interface.
(j)
»»
<0
0
01
~
aa.
c
n-
en
'0
(l)
0
g
0'
:J
~
o
0>
'<
<0
~
-u
~
((5.
"'6m
~
3
(f)
c
;:::::;'
00·
0>
(1)
3
o
a.
(5'
:::l
C
~
o
en
::J
a.
,f"
n-2
n - 1
n
n + 1
/'
n-2
0>
a.
t
-I
n - 1
<
a.
.j"/,
.j"/,
BL
CD
,,:.
.j"
"
~,,:.
U)
&.
00
+lIGH-impedance Z-stat&
HIGH-impedance Z-state
HIGH-impedance Z-state
01 - 07
(output S-OMSO) ~
.j"":'
Y1
\
I
X X
Yn - 2
Yn - 1
o
o
a.
CD
~
.j"":'
Yn
"I"
Yn + 1
I"
I"
1",-
I
;,f"
00
.j"":'
UV (output OSO) ,,:.
.j"":'
U4
U3
V4
V3
U5
V6
V5
U2
U1
V2
V1
UV sample 0
FOE
f
I
I
I
I
X X
.j"#
LUO
x
VO
x
UV sample n - 4
I
u1
U6
U5
V6
V5
U4
U3
V4
V3
UV sample n
U2
U1
V2
V1
UO
x
VO
UV sample n - 4
U6 '
U5
V6
V5
U4
U3
V4
V3
UV sample n
U6
U5
V6
V5
U4
U3
V4
V3
U2
U1
V2
V1
UO
VO
UV sample 716
I I I If~ I I I 1/#1 I I I I I
f
7Z28077
-u
(3
en
~
CO
o
Fig.? Timing waveform of the output data and FOE signals.
01
.....L
a.
c
~
m
"0
(1)
o
£g
:::l
~
OJ
'<
\:J
0
If
LL3
3
~
-6en
(J)
CD
3
o·
0
C
;::+
:::J
0.
en"
......
S
en
Il>
c:
::l
1_
10
CVBS
I
II
II
t lNP
-I-
INPUT SWITCH
tb
CHROMINANCE
(etc.)
1-
BANDPASS"
GAO"
CONTROL
a.
a.
Il>
..,
L.
!
-i
<
a.
T
eD
0
DISCRETE
TIME
OSCILLATOR 1
SAA9051
0
a.
eD
..,
DTOl
(PART)
1SYN~~~~~;;~~ION 1
tADC
U)
tn
<0
0>
ANALOG-TODIGITAL
CONVFRTFR
II
ANALOG-TODIGITAL
r.nNVFRTFR
I II
tREF
I
"
DIVIDER
1+--11
IINCl
LOOP
FILTER 2
DIGITAL - TO ANALOG
CONVERTER
--1
~
- - - tCGC
•
I-
tlDEL
DT02
_ _ _ _ _...J
ta
7Z22076.2
-u
en
~
CO
o
Fig_9 Compensation of delay times by incrementing delay control IDEL.
01
---"
a
0.
c:
0en
-0
~
g
c)"
:::J
-u
~
III
'<
0
cO"
CVBS
<0
;::;:
~
preamplifier /
multiplexer
inputs
F-------1-
HC
HSY programming range
A
+127
+63
+127
HC programming range
1+
-
Y signal output
from S-DMSD
_
no
63
_
_
__ .._____
0
;:::;-
a.
00"
0
0>
(l)
3
0
::J
c
n
en
:::J
c..
0>
....,
64
c..
I -64
_~_
--I
___,1-128
<
.
T1
en
o·
-
--I
··--6
C/l
-0>
3
C
HSY
~
"6'
c..
CD
~1:1=\_ mm_ _ _ _ m_ m_ ,,~jm___ mmmmm-~ff
()
0
c..
CD
....,
BL (NTSC)
U)
0,
<0
-....J
I
BL (PAL)
~I
r-------------,
(3)
+ __
106 (*4)
L..L.L.J.......I I I I I I
HS (NTSC) programming range
I
.1..
- - - - - 720
..
~
I I I I ; I I I I
_ 4 __
144
I I I I
I
-107 (*4)
I'L...L..L....L.J
I
Ir-l
858 LL3
(4)
108 (*4)
HS (PAL) programming range
I,
I
I
I
+ --
f / ~141~
I
..
I
I
I
•
r---------------,
0 --- i
I
I
I
I
I
I
I
I
I
-107 (*4)
I
I :
864 LL3
f--1--J---i-1,
•
7Z22078.3
HSY and HC inputs are referenced to the analog input signal (1). BL and HS outputs are referenced to the
S-DMSD output (2). Waveform timing is indicated in numbers (n) of LL3 clock cycles (n x 1/fLL3), where n
for HSY, HC, BL and CVBS inputs to the S-DMSD and n = 4 for HS.
Data delay T1 input to output at subaddress SA06
SAOB
= 00 : 63 x 1/fLL3
SAOB
=3C : 123 x 1lfLL3
= CO
=
-u
en
»
»
CO
o
Fig.10 Signal correction.
(]l
~
aa.
c
U
C/l
"U
(l)
n
g
5::J
s::
-u
~
0
cO·
-"
<0
~
~
Il>
-
~
-6.
(J)
en
(l)
3
3
o·
-
a.
c:::
;::::;-
00·
Il>
:J
CL
Il>
CL
"""
0
:J
c::
S
en
--I
BP2
BP1
COR2
~
~
~
tn.!
(channel 1)
VARIABLE
BANDPASS
FILTER
eN
en<0
(Xl
SCT
~
PF
BY
YPN
~
~
~
L!
PREFILTER
PCT
~!
CHROMINANCE
TRAP
BC
COR1
~
=~~=~IN
<
r-------------l
CL
I
0
I
HFI
r
~
r'\
AP2
p1
WHF
I
I
I
I
CORNER
CORRECTION
(CORING)
I
I
I
1
I
I
I
I
I
VB
(channel 2)
DCA
(1)
I
0
CL
YOLO - YDL2
~
(1)
"""
VARIABLE
DELAY
COMPENSATION
IL _WEIGHTING
_ _ _ _ AND
_ _ADDING
_ _ _ STAGE
_ _ _ .-lI
7Z28079.1
(channel 3)
-u
en
»
»
CO
o
Fig.11 Luminance path of the S-DMSD.
(]1
~
aa.
c::
U
(J)
"0
~
~
o·
:J
Philips Semiconductors
Product specification
Digital multistandard TV decoder
SUBADDRESS
SAA9051
os
Table 13 Chrominance trap select (BY switches the chrominance trap to the bypass mode; YPN selects the
notch-frequency)
CONTROL BITS
CHROMINANCE TRAP
BY (SA06, 07)
YPN (SAOa, 02)
0
0
0
NTSC (3.58 MHz)
bypass
1
x
PAL (4.43 MHz)
1
Table 14 Disconnecting the luminance prefilter (user dependent)
PREFILTER
CONTROL BIT PF (SA06, 06)
ON
0
OFF
1
Table 15 Bandpass control (BP1 and BP2 control the centre frequency of the bandpass filter, see Figs 13 to 1S)
CONTROL BITS
BANDPASS TYPE (CENTRE FREQUENCy)
BP2 (SA06, 05)
BP1 (SA06, 04)
type 1 (4.1 MHz)
0
0
type 2 (3.8 MHz)
0
1
type 3 (2.S MHz)
1
0
type 4 (2.9 MHz)
1
1
Table 16 Coring threshold level (COR1 and COR2 control the suppression of low amplitude and high frequency
signal components, see Fig.12)
CONTROL BITS
THRESHOLD
Fig.12
COR2 (SA06, 03)
COR1 (SAOS, 02)
0
0
coring off
coring on (4 bits of 12 bits)
a
0
1
coring on (5 bits of 12 bits)
b
1
0
coring on (6 bits of 12 bits)
c
1
1
Note
The thresholds are related the word width of the bandpass filter (12 bits).
Table 17 Aperture correction factor (AP1 and AP2 select the weighting factor K of the high frequency (HF)
luminance components, see Fig.11)
CONTROL BITS
WEIGHTING FACTOR K
May 1991
AP2 (SA06, 01)
AP1 (SA06, ~O)
0
0
0
0.25
0
1
0.5
1
0
1
1
1
3-599
Product specification
Philips Semiconductors
Digital multistandard TV decoder
SAA9051
7Z2BOBO
35
I
bits
(ci
34
(b).,I
(a) (
33
~a)
(c)
32
/ib)
/
31
-64
-32
32
(a) for COR2
= 0 and COR1 = 1
(b) for COR2
= 1 and COR1 = 0
= 1 and COR1 = 1
(c) for COR2
.
bits
64
Fig.12 Coring stage response.
7Z2BOB1
12.-----.----=~~--,_----.-----._----._----_,----,
magnitude
(dB)
frequency response (MHz)
Fig.13 Magnitude of the frequency response of the unlimited summation signal (combining Channel 1 and
Channel 2); PAL mode; prefilter OFF; Responses 1 to 5 show various comb-filter combinations
programmable by bits BP2 and BP1, via the PC-bus.
May 1991
3-600
Philips Semiconductors
Product specification
Digital multistandard TV decoder
SAA9051
7Z28082
12,-----,------,-----,------,------,-----,------,-----,
magnitude
(dB)
_12L-----~----~----~------~ll-~~----~------L---~
o
frequency response (MHz)
Fig.14 Magnitude of the frequency response of the unlimited summation signal (combining Channel 1 and
Channel 2); PAL mode; prefilter ON; Responses 1 to 5 show various comb-filter combinations programmable
by bits BP2 and BP1 , via the FC-bus.
7Z28083
12,-----,------,-----,------~----~-----,------~--~
magnitude
(dB)
frequency response (M Hz)
Fig.15 Magnitude of the frequency response of the unlimited summation signal (combining Channel 1 and
Channel 2); NTSC mode; prefilter OFF; Responses 1 to 5 show various comb-filter combinations
programmable by bits BP2 and BP1, via the 12C-bus.
May 1991
3-601
Philips Semiconductors
Product specification
Digital multistandard TV decoder
SAA9051
7Z28084
12~----~----,-----,-----'-----'-----'-----'-----'
magnitude
(dB)
_12L-----L-----L-----~Ll~~--~J-----J-----~----~
o
frequency response (MHz)
Fig.16 Magnitude of the frequency response of the unlimited summation signal (combining Channel 1 and
Channel 2); NTSC mode; prefilter ON; Responses 1 to 5 show various comb-filter combinations
programmable by bits BP2 and BP1, via the 12C-bus.
SUBADDRESS
07
Table 18 Hue phase (user dependent, see notes 1 to 3)
CONTROL BITS
HUE PHASE (deg)
A77
A76
A75
A74
A73
A72
A71
+178.6 to 0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
o to -180
0
0
0
0
0
0
0
0
A70
Notes to Table 18
1. Step size per least significant bit (A70)
= 1.4 degree.
2. Reference point for positive colour difference signals
=0 degree.
3. The hue phase may be shifted ±180 degrees from the reference point using bit A77, the colour difference signals
are then switcheq from normally positive to negative polarity.
May 1991
3-602
Philips Semiconductors
Product specification
Digital multistandard TV decoder
SUBADDRESS
SAA9051
08
Table 19 Horizontal clock PLL (application dependent)
FUNCTION
HPLL CONTROL BIT (SA08, 07)
horizontal clock PLL open, horizontal frequency fixed
1
horizontal clock PLL closed
0
Table 20
Field frequency select (system mode dependent)
FUNCTION
CONTROL BIT FS (SA08, 06)
60 Hz; 525-line mode
1
50 Hz; 625-line mode
0
Table 21
VTRfrV mode select (system mode dependent)
CONTROL BIT VTR (SA08, 05)
FUNCTION
VTR mode
1
TV mode
0
Table 22 Colour on control (system mode dependent)
CONTROL BIT CO (SA08, 04)
FUNCTION
colour ON
1
colour OFF (all colour output samples zero)
0
Table 23 Alternate/non-alternate mode (system mode dependent)
CONTROL BIT ALT (SA08, 03)
FUNCTION
alternate mode (PAL)
1
non-alternate mode (NTSC)
0
Table 24 Chrominance trap select and amplitude matching (system mode dependent)
CONTROL BIT VPN (SA08, 02)
CHROMINANCE TRAP
3.58 MHz
1
4.43 MHz
0
Table 25 Colour carrier frequency control (system mode dependent)
CONTROL BITS
COLOUR CARRIER FREQUENCY
CCFR1 (SA08, 01)
CCFRO {SA08,
0
4 433 618.75 Hz (PAL-B, G, H, 1; NTSC 4.43)
0
3 575 611.49 Hz (PAL-M)
0
1
3 582 056.25 Hz (PAL-N)
1
0
3 579 545 Hz (NTSC-M)
1
1
May 1991
3-603
~O)
Philips Semicond.uctors
Product specification
Digital multistandard TV decoder
SUBADDRESS
SAA9051
09
Table 26 Vertical noise limiter.
FUNCTION
CONTROL BIT VNL (SA09, 07)
VNLactive
1
VNL bypassed
0
Table 27 V-output enable (system mode dependent)
FUNCTION
CONTROL BIT OEY (SA09, 06)
outputs 01 - 07 and BL active
1
outputs 01 - 07 and BL HIGH-impedance Z-state
0
Table 28 Chrominance output enable (system mode dependent)
FUNCTION
outputs UVO - UV3 active; if CO
CD =logic 0, zero signal
CONTROL BIT OEC (SA09, 05)
=logic 1, chrominance signal output; if
outputs UVO - UV3 HIGH-impedance Z-state
1
0
Table 29 Internal colour forced ON/OFF (test purposes only)
CONTROL BIT CI
(SA09,03)
FUNCT10N
=logic 1 (CD = X) or colour OFF, if CO = logic 0 (CD = X)
= logic 0 (CD = X) or colour controlled by CD, if CO = logic 1
colour forced ON, if CO
1
colour OFF, if CO
0
Where:
X = don't care.
Table 30 Additional output for circuit control
CONTROL BIT AFCC
FUNCTION
=HIGH
output AFCC = LOW
output AFCC
Table 31
1
0
Source-select (system mode dependent)
CONTROL BIT SSO - SS3
FUNCTION
output SSO - SS3 = HIGH
1
output SSO - SS3 = LOW
0
May 1991
3-604
Philips Semiconductors
Product specification
Digital multistandard TV decoder
SAA9051
Table 32 Source select (pin and subaddress)
CONTROL BIT
PIN
SUBAOORESS
AFCC
68
09, 02
SS3
25
OA,04
SS2
24
OA, 03
SS1
66
09, 01
SSO
65
09, DO
SUBADDRESS
OA
Disabling of HSY and HC pulses (system mode dependent)
Table 33
FUNCTION
CONTROL BIT SYC (SAOA, 07)
HSYand HC output pulses disabled
1
HSYand HC output pulses enabled
0
Table 34 Chrominance inpuVoutput 3-state control
FUNCTION
CONTROL BIT CT (SAOA, 06)
CVBS output active
1
output HIGH-impedance Z-state
0
Table 35 Chrominance source select
FUNCTION
CONTROL BIT YC (SAOA, 05)
Y/C separate inputs
1
CVBS input
0
Table 36 Variable delay compensation of the luminance path (YOLO - YDL2 control the luminance delay in order to
compensate different chrominance delays throughout the system)
CONTROL BITS (SAOA, 02 .. 00)
DELAY (N =)
YOL2
YOL1
YOLO
0
0
0
0
+1
0
0
1
+2
0
1
0
+3
0
1
1
-4
1
0
0
-3
1
0
1
-2
1
1
0
-1
1
1
1
Notes to Table 36
1.
The delay is given in terms of clock cycles:
2.
13.5 MHz
May 1991
= N x 74 ns.
3-605
Philips Semiconductors
Product specification
Digital multistandard TV decoder
SAA9051
SUBADDRESS OB
Table 37 SECAM chrominance delay compensation (system mode dependent)
PROGRAMMABLE
DELAY·
0
CONTROL BITS
SCDC6
SCDC5
SCDC3
SCDC2
SCDC1
SCDCO
0
0
0
0
0
0
0
0
0
SCDC4
1
0
0
0
2
0
0
0
0
0
1
0
4
0
0
0
0
1
0
0
8
0
0
0
1
0
0
0
0
1
.16
0
0
1
0
0
0
0
32
0
1
0
0
0
0
0
63
0
1
1
1
1
1
1
64
1
1
1
1
1
1
0
0
0
0
0
65
0
0
79
1
1
1
1
1
1
1
32
16
8
4
2
1
1
Maximum delay selected by single control bit
16
Notes to Table 37
1. * = Delay in number of LL3 clock cycles.
2. SAOB, D7 don't care.
May 1991
3-606
Philips Semiconductors
Product specification
Digital multistandard TV decoder
SAA9Q51
SLAVE TRANSMITTER ORGANIZATION
Slave transmitter format
start
I
acknowledge
from slave
no acknowledge
MBA949
Fig.17 Slave transmitter format (a general call address is not acknowledged).
The format of data byte 1 is:
Table 38
Data bits DO, D3 and D5 are fixed in slave transmitter byte.
Table 39 Description of data byte 1
BIT
DESCRIPTION
PONRES
Status bit for power-on-reset (RES) and after a power failure. logic 1 after the first power-on-reset
and after a power failure. Also set to logic 1 after a severe voltage dip that may have disturbed
slave receiver data in the PAUNTSC decoder (SAA9051). PONRES sets all data bits of control
registers 1 and 2 to zero. logic 0 after a successful read of the PAUNTSC decoder status byte
HLOCK
Status bit for horizontal frequency lock (transmitter identification, stop or mute bit): logic 1if
horizontal frequency is not locked (no transmitter available); logic 0 if horizontal frequency is locked
(transmitter received)
FD
Detected field frequency status bit: logic 1 when received signal has 60 Hz synchronization pulses;
logic 0 when received signal has 50 Hz synchronization pulses
CD
PAUNTSC colour-detected status bit: logic 1 when PAUNTSC colour signal is detected; logic 0
when no PAUNTSC colour signal is detected
CS
SECAM colour-detected status bit: logic 1 when SECAM colour signal is detected; logic 0 when no
SECAM colour signal is detected.
May 1991
3-607
Philips Semiconductors
Product specification
Digital multistandard TV decoder
Default coefficients set for the
S-DMSD and SAA9056
The default coefficients are set for
operation with the TOA8703 or
TOA8708, these devices are
SAA9051
analog-to-digital converters. The
3-state outputs of the chrominance
AOC are controlled by the SS3
switch in this example (all numbers
are hex values).
The slave addresses are as follows:
• S-OMSO; 8A or 8E
• SAA9056; 8A or 8E
Table 40 Slave address (SAA9051 part)
SUBADDRESS
FUNCTION
SHORT DELAY
LONG DELAY
00
inc. delay
5E
7E
01
HSY start
37
73
02
HSY stop
07
43
03
HC start
F6
32
04
HC stop
C7
03
05
HS start
FF
FF
06
H-peaking
02 (62 NTSC)
02 (62 NTSC)
07
HUE control
00
00
08
control 1
38 (77 NTSC)
38 (77 NTSC)
09
control 2
E3
E3 (03 SECAM)
OA
control 3
58 (28 Y/C mode)
58 (28 Y/C mode)
OB
SECAM delay
00
3C
Notes to Table 40
1. Subaddress 05; application dependent.
2. Subaddress 08; HPLL is in the VTR mode. Hex value for TV mode is 18 (57 for NTSC).
Table 41
Slave address (SAA9056 part)
SUBADDRESS
FUNCTION
VALUE
10
luminance delay
11
BLdelay
00
12
burst gate start
42
13
burst gate stop
56
14
sensitivity
20
15
filter
24
16
control
04 (02 active)
May 1991
CO - FF
3-608
Product specification
Philips Semiconductors
SAA9051
Digital multistandard TV decoder
Table 42 Operating modes of the S-DMSD
SCDC
IDEL
YPN
BY
FS
ALT
CCFR1
CCFRO
0
B(A)
B(A)
0
0
0
1
0
0
0
0
A
A
1
0
1
0
0
0
1 (0)
0
B (A)
B(A)
1
0
0
A
A
1 (0)
0
1 (0)
0
B(A)
B(A)
0
1
0
0
A
A
CVBS
1
0(1 )
1
1
B
B
Y/C
0
1 (0)
0
1
B
B
1 (0)
0
1 (0)
0
B(A)
B(A)
0
1
0
0
A
A
1 (0)
0
1 (0)
0
B (A)
B(A)
0
1
0
0
A
A
INPUT
CT
YC
SS3
CE
1 (0)
0
1 (0)
0
1
1 (0)
0
REMARKS
PAL B, G, H, I
CVBS
Y/C
0(1)
PALM
CVBS
Y/C
1
1 (0)
0
1
1
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
1
0
0
0
0(1 )
0(1 )
0(1)
1
0
0(1 )
0(1 )
0(1)
0
0
0
0
0
use FS = 1
for 60 Hz
vertical
frequency
1
1
0
0
0
use FS = 1
for 60 Hz
vertical
frequency
0
1
0
1
1
1
1
0
1
1
PALN
CVBS
Y/C
0
0(1 )
SECAM
0
0(1)
NTSC 4.43 MHz
CVBS
Y/C
0
0(1)
NTSCM
CVBS
Y/C
1
1 (0)
Notes to Table 42
1. SS3 is assumed to control the 3-state output of the chrominance ADC (active LOW).
2. To avoid data collision care must be taken with the programming of CT and SS3 (in this equal they are always
equal).
Where:
A = short time delay.
B = long time delay.
May 1991
3-609
~
~
~
-a-
;:::;:
(J)
CD
cO'
-""
<0
~
Il>
3
c
m
3
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a.
00'
~rn
Ol
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SAA9056
"'U
o
c:
a.
C1, CO
Il>
.----1--------~
I
a
5ECAM
DECODER
-I
<
a.
CD
o
SAA9051
U)
YC
OEC
chrominance
input
---.
I
~
o
o
a.
CD
.,
~
~
uv output
3-state control
(e.g. 553)
I---+--"~ Y output
OEY
DCVB5
.--~_ _..
CVB5 input ---.
synchronization
output
HSY, HC
"'U
(J)
»
»
CO
o
Fig_18 SAA9051 signal flow when used in conjunction with SAA9056_
01
~
aa.
c:
U
rn
"0
~
g
5:J
~
III
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.....
~
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;:::+
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<0
<0
0>
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w
3
0'
c
o
a.
en'
S
;:::::;
.-+
0>
SAA9056
-u
o
:::J
c:
en
:::l
Cl.
Ct, CO
0>
a.
~-.J--------+~
I
~
SECAM
DECODER
<
Cl.
CD
o
o
SAA9051
cp
Pl
.....
YC
Cl.
CD
-,
OEC
chrominance
input
--.
............... uv
output
3-state control
(e.g. SS3)
~-+
short or
long delay
DCVBS
CVBS input
__.I
Y output
OEY
t--t--+~ synchronization
~
output
HSY, HC
-u
U>
~
<0
0
Fig,19 Signal flow - PAL or NTSe with eVBS input signal.
01
--\,
aa.
c:
U
~
o
cO·
Dl
'<
<0
;:::::j.:
~
~
3
c
""0
~
~.
(J)
(J)
CD
3
o·
o
::J
;:::::;
C.
Cir
.....
~
S
::J
C
rn
c..
SAA9056
~
.---+--------.-1r
a.
-I
SECAM
DECODER
<
c..
C1>
()
o
c..
SAA9051
U)
YC
chrominance
input
~
I\)
C1>
..,
OEC
1-.........
UVoutput
1-"'__•
Y output
3-state control
(e.g. SS3)
short delay
DCVBS
1-----1-_ _._ synchronization
output
HSY. HC
""0
en
~
co
Fig.20 Signal flow - PAL or NTSC with Y/C input signal.
o
(Jl
......\,
a
Cl-
c
U
(J)
"0
~
£g
::J
~
OJ
'<
~
-6'
:::+:
III
(J)
CD
3
(')'
;::::;:-
c:
cO"
<0
<0
c
w"
SAA9056
or
::J
Ct, CO
"U
o
en
3
o
:::J
a.
nO
iii
a.
III
~
a.
~
<
a.
CD
()
SAA9051
o
a.
DEC
CD
~
chrominance
input
UVoutput
tv
~
tv
3-state control
(e.g. SS3)
~-+
__•
Y output
long delay
DCVBS
synchronization
output
HSY, HC
"U
(J)
»
»
CO
0
Fig.21 Signal flow - SECAM with CVBS input signal.
01
"""'"
a
a.
c:
nen
"0
CD
(")
£
go
:::J
~
o
~
<0"
-"
<0
;:::+
~
-u
~
-6'
en
(f)
Ol
m
3
c
o:::J
00"
S
;::::;Ol
::J
3
o·
a.
c
en
a.
SAA9056
Ol
a.
--I
<
a.
SAA9051
OEC
U)
~
.j::o.
eo
o
o
a.
eo
-.:
. . . . UVoutput
3-state control
(e.g. 553)
......_ _•
Youtput
long delay
OEY
DCVB5
synchronization
output
H5Y, HC
-u
<3
(J)
~
CO
0
Fig.22 Signal flow - SECAM with Y/C input signal.
01
......
a.
c
S
Philips Semiconductors
Product specification
Digital multistandard TV decoder
SAA9051
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
V DD
PARAMETER
CONDITIONS
supply voltage range
MIN.
MAX.
UNIT
-0.5
+7
V
-0.5
+7
V
-0.5
+7
V
2750
VI
input voltage range
Vo
output voltage range
Ptot
maximum power dissipation per package
Tamb
operating ambient temperature range
0
+70
mW
DC
Tstg
storage temperature range
-65
+150
DC
lomax
HANDLING
Inputs and outputs are protected
against electrostatic discharge in
normal handling. However, to be
totally safe, it is good practice to
take normal precautions appropriate
to handling MOS devices (see
'Handling MOS Devices').
May 1991
3-615
=20 mA
Philips Semiconductors
Product specification
Digital multistandard TV decoder
SAA9051
CHARACTERISTICS
VDD = 4.5 V to 5.5 V; Tarro = 0 to +70 °C; unless otherwise specified
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
supply voltage
IDD
supply current
4.5
note 1
5
5.5
V
370
500
mA
Inputs
INPUT VOLTAGE LOW
VIL
pins 2 - 4, 6 - 17,20 - 23,33,43,56 and 64
-0.5
+0.8
V
VIL
pins 40 and 41
-0.5
+1.5
V
VDD
VDD
V
10
Il A
INPUT VOLTAGE HIGH
VIH
pins 2 - 4, 6 - 17, 20 - 23, 43, 56 and 64
2
VIH
pins 33, 40 and 41
3
V
INPUT LEAKAGE CURRENT
II
pins 2 - 4, 6 - 17, 20 - 23,40 - 41,43 and 64
INPUT CAPACITANCE
CI
pin 4
2
10
pF
CI
CI
pins 2 - 3,14 - 17,20 - 23,43 and 64
2
7.5
pF
HIGH-impedance 2
Z-state
7.5
pF
pins 6 - 13
Outputs
OUTPUT VOLTAGE LOW
VOL
pins 6 - 13, 24 - 26, 29 - 32, 42, 45 -50, 53,
55 - 58, 65 - 66 and 68
IOL = 2.0 mA
0
0.6
V
VOL
pins 40 and 41
h=5.0 mA
0
0.45
V
IOH = -0.5 mA
2.2
VDD
V
7.5
pF
-
V
-
V
80
OUTPUT VOLTAGE HIGH
VOH
pins 6 - 13, 24 - 26, 29 - 32, 42, 45 - 50, 53,
55 - 58, 65 - 66 and 68
OUTPUT CAPACITANCE
CO
pins 45 - 50, 53 and 55 - 58
LFCO OUTPUT (NOTE 2)
Vo(P'P)
output voltage (peak-to-peak value)
Vo(P'P)
output voltage (peak-to-peak value)
RL
~
10 kQ; CL
< 15 pF
RL ~ 1 kQ; CL <
15 pF
1.0
-
0.5
Timing (see Fig.23)
tc3
LL3 cycle time
69
tc3H/tca
t, t,
LL3 duty factor
43
-
57
ns
0/0
6
ns
tsu: DAT
input data set-up time
12
-
-
ns
May 1991
LL3 rise and fall times
note 3
3-616
Philips Semiconductors
Product specification
Digital multistandard TV decoder
SYMBOL
PARAMETER
SAA9051
MIN.
CONDITION
MAX.
TYP.
UNIT
Timing (see Fig.23)
-
ns
except HSY and HC;
C L = 25 pF;
IOL = 2.0 mA;
V OH = 2.2 V
50
ns
C L = 25 pF;
IOL = 2.0 mA;
VOH=2.6V
80
ns
25,
pF
-
MHz
°C
410 OAT
input data hold time
5
tHO
output data hold time
5
to
output data delay time
to
HSY and HC output delay time
CL
output data load capacitance
ns
7.5
Crystal oscillator (see Fig.20)
fn
nominal frequency
M/f n
permissible deviation of fn
CiT/f n
temperature deviation from fn
-
TXTAL
temperature range
0
+70
C LXTAL
load capacitance
8
-
pF
Rr
maximum resonance resistance
80
Q
C,
motional capacitance
1.5 ±20%
Co
parallel capacitance
3.5 ±20%
third harmonic
24.576
±50 x
10~
±20 x
10~
40
fF
-
pF
Notes to the characteristics
1. Inputs LOW and outputs not connected, Voo = 5 V.
2. 4-bit triangular waveform clocked at 24.576 MHz, AC coupled at pin 36.
3. Rising and falling edges of the clock signal are assumed to be smooth e.g. due to roll-off low-pass filtering.
Purchase of Philips' 12C components conveys a license under the Philips' FC patent to use the
components in the 12C-system provided the system conforms to the 12C specifications defined by
Philips.
May 1991
3-617
Philips Semiconductors
Product specification
Digital multistandard TV decoder
SAA9051
clock LL3
2.0 V
input data
0.8 V
2.2 V
output data
0.6 V
7Z28090
Fig.23 Timing diagram.
6.8pF
~:
XTAL
SLJ
33
124.576 MHz
quartz (3rd harmonic)
10 pF
¥
SAA9051
XTALI
34
*
1Ol1H
±20%
....I... 1 nF
J;
33
SAA9051
XTALI
~~
XTAL
-
34
MBA950·1
(b)
(a)
Fig.24 Oscillator circuit requirements; (a) with quartz crystal; (b) with external clock.
May 1991
3-618
Philips Semiconductors Video Products
Preliminary specification
Clock signal generator circuit
for Digital TV systems (CGC)
FEATURES
• Clock generation suitable for digital
TV systems (line-locked)
• PLL frequency multiplier to generate
4 times of input frequency
• Dividers to generate clocks LL 1.5,
LL3 and LL3T (4th and 2nd multiples
of input frequency)
• Reset control and power fail
detection
GENERAL DESCRIPTION
The 5AA9057B generates all clock
signals required for a digital TV
system suitable for the 5AA90xx
family. Optional extras (feature box
etc.) can be driven via external
buffers, adventageous for a digital
TV system based on display
standard conversion concepts.
May 1992
SAA90578
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
V OOA
analog supply voltage (pin 5)
4.5
5.0
5.5
V
VOOO
digital supply voltage (pins 8, 17)
4.5
5.0
5.5
V
IOOA
analog supply current
3
9
mA
1000
digital supply current
10
40
mA
V LFca
LFCO input voltage
(peak-to-peak value)
1
V OOA
V
fi
input frequency range
6.25
7.25
MHz
VI
input voltage LOW
input voltage HIGH
0
2.4
0.8
VOOO
V
V
Va
output voltage LOW
output voltage HIGH
0
2.6
0.6
VOOO
V
V
Tamb
operating ambient temperature
range
0
70
°C
ORDERING INFORMATION
EXTENDED
TYPE NUMBER PINS
PACKAGE
PIN POSITION
MATERIAL
CODE
5AA9057B
20
OIL
plastic
50T146
5AA9057BT
20
mini-pack (5020)
plastic
50T163A
3-619
Philips Semiconductors
Preliminary specification
Clock signal generator circuit
for digital
+5V
+5V
0.11JF
15kO
~i-~
0.1 IJF
0.11JF
H~
H~
V OOO1
V
12
31
0.1 IJF
0.1 IJF
0.11JF
H~ H~ H~
OOO2
"
+5V
c
0.11JF
:tI
H~
i:
);
G')
VOOA1
VOOA2
VOOA3
CUR
V OOA4
32
37
40
41
42
»
iF
2
~
21 to 14
-+
YUV-bus
Y
FORMATTER
~
PEAKING
AND
CORING
Yo.
DAC3
UV7 to UVO
11 to4
~
6>
I\)
UV
FORMATTER
~
~ '----<
INTERPOLATION
~
-4
i
-..j
CREF
MC
LL27 ..
LLC
24
I
RESN
27
SCL
..
2
~
r---
DAC 2
1 V (g-p)
Y
750n(1~
~
75 0(1)
~36
1 V (p-p)...
'---'
44
REFLuv
T
II -.- 1
~
0)
:::J
(1)(1)
~ 3
o (1)
_< ...
C
l>
DAC1
43
~33
'---'
±(B-Y)
~50n(1Q
~
75 0(1)
C uv
0.11J F
I~
I'
£
1 V (p-p)
500(1)
±(R-Y)
75 0(1)
I'
I---
1 C-BUS
CONTROL
29
...
o
00
I'
~
28
12 :::-bus
SDA
REFLy
4
TIMING
CONTROL
p
26
Ir-~
1
i
-"
25
HREF
n-
f-
l>:::J
"'C:::J"
m
0.\ IJF
'---'
DATA
SWITCH
c.v
~39
~
data clock
--(1)
... :::J
Cy
Y7to YO
(1)
CO
-.
TEST
CONTROL
SAA9065
f-+
"U
13
V
i'-~SSOl
30
22
23
(MS1)
(MS2)
3
l'.~
:::J~
35
~
38
~r
s·
V
l'.~SS02
34
::::~
(1) output amplitude determined by resistors (R L> 1250)
Fig.1 Block diagram and application circuit.
V
V
V
~~ SSAl :::: ~ SSA2 ~~ SSA3
MEH267
en
ll>
-<
C/)
l>
l>
co
-0
U1
:::l
o0')
CD
o
~
o·
ao·
Preliminary specification
Video enhancement
and 01A processor (VEDA)
SAA9065
5. PINNING
SYMBOL
PIN
DESCRIPTION
REFLy
1
low reference of luminance DAC (connected to V SSA1 )
Cy
2
capacitor for luminance DAC (high reference)
SUB
3
substrate (connected to VSSA1)
UVO
4
UV1
5
UV2
6
UV3
7
UV4
8
UV5
9
UV6
10
UV7
11
UV signal input bits UV7 to UVO (digital colour-difference signal)
V OOO1
12
+5 V digital supply voltage 1
V SS01
13
digital ground 1 (0 V)
YO
14
Y1
15
Y2
16
Y3
17
Y4
18
Y5
19
Y signal input bits Y7 to YO (digital luminance signal)
Y6
20
Y7
21
MS2
22
mode select 2 input for testing chip
MS1
23
mode select 1 input for testing chip
MC
24
data clock CREF (13.5 MHz e. g.); at MC
LLC
25
line-locked clock signal (LL27
HREF
26
data clock for YUV data inputs (for active line 768Y or 640Y long)
RESN
27
reset input (active LOW)
SCL
28
12C-bus clock line
'SDA
29
12C-bus data line
VSS 02
30
digital ground 2 (0 V)
V OOO2
31
+5 V digital supply vOltage 2
= HIGH the LLC divider-by-two is inactive
=27 MHz)
VOO A1
32
+5 V anaiog supply voltage for buffer of DAC 1
(R-Y)
33
±(R-Y) output signal (analog signal)
VSSA1
34
analog ground 1 (0 V)
April 1993
3-628
Preliminary specification
Video enhancement
and 01 A processor (VEDA)
SAA9065
SYMBOL
PIN
V SSA2
35
analog ground 2 (0 V)
(B-Y)
36
±(B-Y) output signal (analog colour-difference signal)
VOO A2
37
+5 V analog supply voltage for buffer of DAC 2
V SSA3
38
analog ground 3 (0 V)
Y
39
Y output signal (analog luminance signal)
V OOA3
40
+5 V analog supply voltage for buffer of DAC 3
CUR
41
current input for analog output buffers
VOO A4
42
supply and reference voltage for the three DACs
Cuv
43
capacitor for chrominance DACs (high reference)
REFLuv
44
low reference of chrominance DACs (connected to VSSA1)
DESCRIPTION
PIN CONFIGURATION
~
CJ)
CJ)
>-
>
SCL
RESN
HREF
LLC
MC
REFLy
MS1
SAA9065
MS2
Y7
Y6
Y5
Y4
\0
>
:::>
r--
>
:::>
8a
>
~ ~
>=
Fig.2 Pin configuration.
April 1993
~
CJ)
>
3-629
MEH276
Preliminary specification
Video enhancement
and DIA processor (VEDA)
6. FUNCTIONAL DESCRIPTION
The CMOS circuit SAA9065
processes digital YUV-bus data up to
a data rate of 30 MHz. The data
inputs Y7 to YO and UV7 to UVO
(Fig.1) are provided with 8-bit data.
The data of digital colour-difference
signals U and V are in a multiplexed
state (serial in 4:2:2 or 4:1:1 format;
Tables 2 and 3).
Data is read with the rising edge of
LLC (line-locked clock) to achieve a
data rate of LLC at MC = HIGH only.
If MC is supplied with the frequency
CREF (LLC/2 for example), data is
read only at every second rising
edge (Fig.3).The 7-bit YUV input
data are also supported by means of
the R78-bit (R78 = 0). Additionally,
the luminance data format is
converted for internal use into a
two's complement format by
inverting MSB. The Y input byte (bits
Y7 to YO) represent luminance
information; the UV input byte (bits
UV7 to UVO) one of the two digital
colour-difference signals in 4:2:2
format (Table 2).
SAA9065
The HREF input signal (HREF = HIGH)
determines the start and the end of
an active line·(Fig.3) the number of
pixels respectively. The analog
output Y is blanked at HREF = LOW,
the (B-Y) and ,(R-Y) outputs are in a
colourless state. The blanking level
can be set by the BLV-bit.
The SAA9065 is controllable via the
12C-bus.
Y and UV formatters
The input data formats are formatted
into the internally used processing
formats (separate for 4:2:2 and 4:1:1
formats). The IFF, IFC and IFL bits
control the input data format and
determine the right interpolation filter
(Figures 10 to 13).
Peaking is applied to the V signal to
compensate several bandwidth
reductions of the external
pre-processing. Y signals can be
improved to obtain a better
sharpness.
There are the two switchable
bandpass filters BF1 and BF 2
PIN
INPUT SIGNAL
COMMENT
LLC
MC
LLC (LL27)
CREF
The data rate on YUV-bus is half the clock rate
on pin LLC, e. g. in SAA7151B, SAA7191 and
SAA7191 B single scan operation.
LLC
MC
LLC (LL27)
MC= HIGH
The data rate on YUV-bus must be identical to
the clock rate on pin LLC, e. g. in double scan
applications.
LLC2ILL3
MC= HIGH
The data rate on YUV-bus must be identical to
the clock rate on pin LLC, e. g. SAA9051 single
scan operation.
Note: YUV data are only latched with the rising edge of LLC at MC = HIGH.
April 1993
The coring stage with controllable
threshold (4 states controlled by C01
and COO bits) reduces noise
disturbances (generated by the
bandpass gain) by suppressing the
amplitude of small high-frequent
signal components. The remaining
high-frequent peaking component is
available for a weighted addition
after coring.
Peaking and coring
Table 1 LLC and MC configuration modes in DMSD applications
LLC
MC
controlled via the 12C-bus by the bits
BP1 , BPO and BFB. Thus, a
frequency response is achieved in
combination with the peaking factor K
(Figures 5 to 9; K is determined by
the bits BFB, WG1 and WGO).
3-630
Table 2 Data format 4 : 2 : 2. (Fig.3)
INPUT
PIXEL BYTE SEQUENCE
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
V6
Y7
UO
U1
U2
U3
U4
U5
U6
V7 U7
va
V1
V2
V3
V4
V5
V6
3
5
YO (LSB) YO
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7 (MSB) Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
UVO (LSB)
UV1
UV2
UV3
UV4
UV5
UV6
UV7(MSB)
UO
U1
U2
U3
U4
U5
U6
U7
VO
V1
V2
V3
V4
V5
V6
VO
V1
V2
V3
V4
V5
V6
V7
UO
U1
U2
U3
U4
U5
U6
U7
Yframe
0
1
2
UV frame
a
2
4
4
V7
Preliminary specification
Video enhancement
and OfA processor (VEDA)
SAA9065
Interpolation
Data switch
The chrominance interpolation filter
consists of various filter stages,
multiplexers and de-multiplexers to
increase the data rate of the
colour-difference signals by a factor
of 2 or 4. The switching of the filters
by the bits I FF, I FC and I FL is
described previously. Additional
signal samples with significant
amplitudes between two consecutive
signal samples of the low data rate
are generated. The time-multiplexed
U and V samples are stored in
parallel for converting.
The digital signals are adapted to the
conversation range. U and V data
have a-bit formats again; Y can have
9 bits dependent on peaking.
Blanking and switching to colourless
level is applied here. Bits can be
inverted by INV-bit to change the
polarity of colour-difference output
signals.
Digital-to-analog converters
Conversion is separate for Y, U
and V. The converters use resistor
chains with low-impedance output
buffers. The minimum output voltage
is 200 mV to reduce integral
Table 3 Data format 4 : 1 : 1
INPUT
PIXEL BYTE SEQUENCE
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
UVO
UV1
UV2
UV3
UV4
UV5
UV6
UV7
0
0
0
0
V6
V7
U6
U7
0
0
0
0
V4
V5
U4
U5
0
0
0
0
V2
V3
U2
U3
0
0
0
0
VO
V1
UO
U1
0
0
0
0
V6
V7
U6
U7
0
0
0
0
V4
V5
U4
U5
0
0
0
0
V2
V3
U2
U3
0
0
0
0
VO
V1
UO
U1
Yframe
0
1
2
3
4
5
6
7
UV frame
0
April 1993
4
3-631
non-linearity errors. The analog
signal, without load on output pin, is
between 0.2 and 2.2 V floating. An
application for 1 VI 75 n on outputs
is shown in Fig.1.
Each digital-to-analog converter has
its own supply and ground pins
suitable for decoupling. The
reference voltage, supplying the
resistor chain of all three DACs, is
the supply voltage V DDA4. The
current into pin 41 is 0.3 rnA ; a
larger current improves the
bandwidth but increases the integral
non-Ii nearity.
Preliminary specification
Video enhancement
and D/A processor (VEDA)
SAA9065
LL27
(LLC)
CREF
internal
bus clock
,
(LLC2)
,
HREF
,
,
---.LJ~startoI
1,
active line
:
1,
Byte numbers tor pixels:
Y signal
50Hz
U and V sig:....na_I_ _J
'-----"---'---J '------'---'---J '-----"-=--J '------'-=--J '-----"-_J '------'---'-----J
'-----"-'---J
'-----"-'---J
Y signal
60 Hz
U and V sig;,..na_I_ _-,
'----":;;-,---J
MEH268
LL27
(LLC)
CREF
internal
bus clock
(LLC2)
HREF
: end 01.
--:-'1-1__"'--__--'-___'--___
: active line
,,,
Byte number tor pixels:
,
:
,,,
,
Y signal
50 Hz
U and V signa}~
Y signal
60Hz
U and V signaJ~
MEH269
Fig.3 Line control by HREF for 4: 2: 2 format, CREF
50 Hz and 60 Hz field.
April 1993
3-632
= 13.5 MHz; HREF = 720 pixel;
Preliminary specification
Video enhancement
and 01 A processor (VEDA)
SAA9065
7. LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER
MIN.
MAX.
UNIT
VDDD1
supply voltage range (pin 12)
-0.3
7
V
V DDD2
supply voltage range (pin 31 )
-0.3
7
V
VDDA1
supply voltage range (pin 32)
-0.3
7
V
V DDA2
supply voltage range (pin 37)
-0.3
7
V
VDDA3
supply voltage range (pin 40)
-0.3
7
V
V DDA4
supply voltage range (pin 42)
-0.3
7
V
-
±100
mV
V DDD
V
VdiffGND difference voltage VSSD - V SSA
Vn
voltage on all input pins 4 to 11 ,
14 to 27 and 41
-0.3
Vn
voltage on analog outplit pins 33,
36 and 39
-0.3
VDDD
V
Ptot
total power dissipation
0
tbf
mW
T stg
storage temperature range
-55
150
°C
Tamb
operating ambient temperature range
0
70
°C
VESD
electrostatic handling* for all pins
±2000
-
V
* Equivalent to discharging a 100 pF capacitor through a 1.5 kn series resistor.
8. THERMAL RESISTANCE
SYMBOL
Rthj-a
April 1993
PARAMETER
from junction-to-ambient in free air
THERMAL RESISTANCE
46 KNJ
3-633
Preliminary specification
Video enhancement
and 01 A processor (VEDA)
SAA9065
9. CHARACTERISTICS
VOOO = 4.5 to 5.5 V; VOOA = 4.75 to 5.25 V; LLC = LL27; MC
taken in Fig.1 unless otherwise specified.
SYMBOL
PARAMETER
=CREF = 13.5 MHz; Tamb = 0 to 70°C; measurements
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V OO01
supply voltage range (pin 12)
for digital part
4.5
5
5.5
V
V OO02
supply voltage range (pin 31 )
for digital part
4.5
5
5.5
V
V OOA1
supply voltage range (pin 32)
for buffer of DAC 1
4.75
5
5.25
V
VOOA2
supply voltage range (pin 37)
for buffer of DAC 2
4.75
5
5.25
V
VOOA3
supply voltage range (pin 40)
for buffer of DAC 3
4.75
5
5.25
V
V OOA4
supply voltage range (pin 42)
DAC reference voltage
4.75
5
5.25
V
1000
supply current (10001 + 10002 )
for digital part
-
tbf
tbf
mA
100A
supply current (l00A1 to 100A4)
for DACs and buffers
-
tbf
tbf
mA
0.8
V
YUV-bus inputs (pins 4 to 11 and 14 to 21)
Figures 3 and 4
V IL
input voltage LOW
-0.5
V IH
input voltage HIGH
2.0
-
CI
input capacitance
III
-
-
input leakage current
VI
= HIGH
Vooo+0.5 V
10
pF
4.5
~A
0.8
V
Inputs MS1, MS2, MC, LLC, HREF and .RESN (pins 22 to 27)
V IL
input voltage LOW
-0.5
-
V IH
input voltage HIGH
2.0
-
CI
input capacitance
-
-
10
pF
4.5
~A
III
input leakage current
V24
MC input voltage for LL27
CREF signal on MC input
VI
= HIGH
27 MHz data rate
. CREF data rate; note 1
V ooo +0.5 V
-
-
2.0
-
Vooo+0.5 V
-
-
I-
V
12C-bus SCL and SDA (pins 28 and 29)
II
input current
VOL
SDA output voltage LOW (pin 29)
= LOW or HIGH
129 =3 mA
-
129
output current
during acknowledge
3
-
4.75
R41 -42 = 15 kn
pin connected to VSSA 1
VI L
input voltage LOW
-0.5
V IH
input voltage HIGH
3.0
VI
1.5
V
Vooo+0.5 V
±10
~A
0.4
V
-
mA
5
5.25
V
-
300
-
~A
-
0
-
V
-
0.1
-
~F
.
Digital-to-analog converters (pins 1, 2, 41, 42, 43 and 44)
V OAC
input reference voltage for internal
resistor chains (pin 42)
ICUR
input current (pin 41)
V 1,44
reference voltage LOW
CL
external blocki ng capacitor to V SSA 1
for reference voltage HIGH (pins 2 and 43)
April 1993
3-634
Preliminary specification
Video enhancement
and DfA processor (VEDA)
SYMBOL
SAA9065
PARAMETER
CONDITIONS
TYP.
MIN.
MAX.
UNIT
f LLC
data conversation rate (clock)
Fig.3
-
-
30
MHz
Res
resolution
luminance DAC
-
9
-
bit
chrominance DACs
-
bit
DC integral linearity error
8-bit data
LSB
DC differential error
8-bit data
-
1.0
DLE
-
8
ILE
0.5
LSB
Y, ±(R-Y) and ±(B-Y) analog outputs (pins 39,33 and 36)
Vo
output signal voltage (peak-to-peak value) without load
-
2
-
V
V33,36,39
output voltage range
without load; note 2
0.2
-
2.2
V
V39
output blanking level
Y output; note 3
-
16
LSB
V33 ,36
output no-colour level
±(R-Y), ±(B-Y); note 4
-
128
R33,36,39
internal serial output resistance
n
n
-
25
RL 33,36,39 output load resistance
external load
125
B
output signal bandwidth
-3 dB
20
-
td
signal delay from input to Y output
-
tbf
-
tLLC
cycle time
33
37
41
ns
tp H
pulse width
40
50
60
%
tr
rise time
-
-
5
ns
tf
fall time
-
-
6
ns
11
-
-
ns
3
-
-
ns
-
-
ns
4 xtLLC -
-
ns
LLC timing (pins 25)
YUV-bus timing (pins 4 to 11 and 14 to 21)
tsu
input data set-up time
tHO
input data hold time
MC timing (pin24)
;:
LSB
MHz
ns
LLC; Fig.3
Fig.5
Fig.5
tsu
input data set-up time
11
tHO
input data hold time
3
ns
RESN timing (pin 27)
tsu
set-up time after power-on or failure
active LOW; note 5
Notes to the characteristics
1. YUV-bus data is read at MC = HIGH (pin 24) clocked with LLC (Fig.5) . Data is read only with every second
rising edge of LLC when CREF ::::; LLC/2 on MC-pin 24.
2. 0.2 to 2.2 V ouput voltage range at 8-bit DAC input data. The data word can increase to 9-bit dependent on
peaking factor.
3. The luminance signal is set to the digital black level: 16 LSB for BLV-bit
= 0; 0 LSB for BLV-bit = 1.
4. The chrominance amplitudes are set to the digital colourless level of 128 LSB.
5. The circuit is prepared for a new data initialization.
April 1993
3-635
Preliminary specification
Video enhancement
and 01 A processor (VEDA)
SAA9065
input clock
LLC (LL27)
O.6V
MEH270
data valid
Fig.4 YUV-bus data and CREF timing.
PROCESSING DELAY
LLC CYCLES
REMARKS
YUV digital input
to
YUV analog output
44
atMC
= "1"
88
at MC
= LLC/2
April 1993
3-636
Preliminary specification
Video enhancement
and· OfA processor (VEDA)
SAA9065
10. 12C-BUS FORMAT
I I
S
SLAVE ADDRESS
I A I SUBADDRESS I A
DATAO
S
start condition
SLAVE ADDRESS
1011111X
A
acknowledge, generated by the slave
subadress byte (Table 4)
databyte (Table 4)
stop condition
SUBADDRESS*
DATA
P
x
A
DATAn
A
P
readlwrite control bit
X = 0, order to write (the circuit is slave receiver)
X = 1, order to read (the circuit is slave transmitter)
* If more than 1 byte DATA are transmitted, then auto-increment of the subaddress is performed.
Table 4 12C-bus transmission
FUNCTION
I
SUBAOORESS
DATA
03
02
01
DO
Peaking and coring
01
0
C01
COO
BP1
BPO
BFB
WG1
WGO
Input formats; interpolation
02
IFF
IFC
IFL
0
0
0
0
0
Input/output setting
03
0
0
0
0
DRP
BLV
R?8
INV
07
06
05
04
Bit functions in data bytes:
C01
to
COO
BP1, BPO and BFB
April 1993
Control of coring threshold:
Bandpass filter selection:
C01
0
0
1
1
COO
0
1
0
1
BP1
0
0
1
1
BPO
0
1
0
1
0
0
X
X
3-637
coring off
small noise reduction
medium noise reduction
high noise reduction
BFB
0
0
0
0
characteristic
characteristic
characteristic
characteristic
1
1
BF1 filter bypassed Fig.9
not recommended
Fig.5
Fig.6
Fig.?
Fig.8
Preliminary specification
Video enhancement
and 01 A processor (VEDA)
BFB, WG1 and WGO
IFF, IFC, IFL
Peaking factor K:
Input format and filter control
at 13.5 MHz data rate:
SAA9065
BFB
WG1 WGO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
K
K
K
K
K
K
K
K
IFF
IFC
IFL
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
X
=
=
=
=
=
=
=
=
1/8;
1/4
1/2
1·,
0;
1/4;
1/2
1;
minimum peaking
maximum peaking
peaking off
minimum peaking
maximum peaking
4 : 1 : 1 format; -3 dB attenuation
at 1.6 MHz video frequency; Fig.1 0
4 : 1 : 1 format; -3 dB attenuation
at 600 kHz video frequency; Fig.11
4 : 1 : 1 format; -3 dB attenuation
at 1.2 MHz video frequency; Fig.12
4 : 2 : 2 format; -3 dB attenuation
at 1.6 MHz video frequency; Fig.1 0
4 : 2 : 2 format; -3 dB attenuation
at 600 kHz video frequency; Fig.11
4 : 2 : 2 format; -3 dB attenuation
at 2.5 MHz video frequency; Fig.13
DRP
UV input data code:
o = two's complement;
BLV
Blanking level on Y output:
o = 16 LSB;
R78
YUV input data solution:
o = 7-bit data;
INV
Polarity of colour-difference
output signals:
o = normal polarity equal to input signal
1
1
1
= offset binary
= 0 LSB
1
= 8-bit data
= inverted polarity
Purchase of Philips' 12C components conveys a license under the
Philips' 12C patent to use the components in the 12C-system
provided the system conforms to the 12C specifications defined
by Philips.
April 1993
3-638
Preliminary specification
Video enhancement
and Of A processor (VEDA)
SAA9065
MEH271
16
i.---
(dB)
(1)
12
/~
V
8
I
6
/
I
V
"\
/
I
/
10
(2)
/
-
-"'"
2
~
'''-
r\
""
r---
~I--'"
(4)
\
\
1/
/ V/
V/ V V
~ ~V
.'"\
~
V
II J (3) V
) / /'
4
o
~
V
14
Vy
--
[,........-1""'
\
\
f\\
r": ~~
',,- '\ \
t--...... "- \.\
~ ~ '\.\
~K~ ~
~~
o
"'~
2
4
5
6
fy(MHz)
7
Fig.S Peaking frequency response with 12C-bus control bits BP1 = 0; BPO = 0 and BFB = 0:
(1) K = 1; (2) K = 1/2; (3) K = 1/4 and (4)K = 1/8.
MEH273
6
I.-
V
(1)
4
Vy
(dB)
V
2
0
/
8
II
6
/ I
/
(2)
V
I
I
I '1/
Ij V
4
'\
I
/
I
'" "-
/
~
/'
I.-
t-...
.......
1\
\
""
\
"
'\.,
\
r--.. . .
1\
8J...- .....
V
-
(4)
~
r\\
"'-
I--...
1/// 1/
JW'/
2
'\
"-',,-\.\
..
..... ~
'\: ~
i'-... . .
1'....'
...... t--.,........... ~
n~""
o
~
2
4
3
5
6
fy(MHz)
Fig.6 Peaking frequency response with 12C-bus control bits BP1 = 0; BPO = 1 and BFB = 0:
(1) K = 1; (2) K = 1/2; (3) K= 1/4 and (4) K= 1/8.
April 1993
3-639
7
Preliminary specification
Video enhancement
and D/A processor (VEDA)
SAA9065
MEH273
6
(dB)
V
2
0
I
8
/
~
'\
J
;,..-
(2)
1/
I
"-
r--
/'
.......
IJ V
j
'"
"1\
\:
\:
'\.
\. \
'
"
r---. . . .
"' "-
~ .....
I
I I "v
I 11/ (4)
4
"
I
II
6
2
I
~
V
(1)
4
Vy
~\
-- ,
r--....'
~
II/I 1/
lP"/
'\\
~~ ~
r--......
~
~ ~
....
~~
..P~
o
2
4
3
6
5
fy(MHz)
7
Fig.? Peaking frequency response with 12C-bus control bits BP1 = 1; BPO = 0 and BFB = 0:
(1) K = 1; (2) K = 1/2; (3) K = 1/4 and (4) K = 1IS.
MEH274
16
.'
14
(1)
Vy
(dB)
/
8
/
/
I
V J
6
I /
4
/ V
IJ /
V/.1
L I i j....V
V
o ~
o
(2)
V
/
"'"
~
V
~
..........
(4)
V
'
"
"
"-
~
..
r--.
4
3
Fig.S Peaking frequency response with 12C-bus contrQI bits BP1
(1) K = 1; (2) K= 1/2; (3) K = 1/4 and (4) K = 1is.
April 1993
I\.
'\:
.... ~ "\
.'"
r-....
~
-...... """'" ............ ""'- ~,
~
2
I\.
~
(3)
~ V,
./
t'....
~
/
V
2
.........
/
12
10
V
3-640
""'"""t-... . ........ . . . "'"'~
r--.....
5
~
1""'-00.:::--" [""0".
-~
6
7
fy(MHz)
= 1 ; BPO = 1· and BFB == 0:
Preliminary specification
Video enhancement
and 01A processor (VEDA)
SAA9065
MEH275
10
Vy
(dB)
8
6
(1)
4
~
2
L..---::
o
--'
V
10---'
~
-
(2)
L--' ~(3)
~
.....
~
.-'
---
..-
.-- ~I---
- ---
-2
-4
o
2
4
5
6
fy(MHz)
Fig.9 Peaking frequency response with 12C-bus control bits BP1 = 0; BPO = 0 and BFB = 1;
bandpass filter BF1 bypassed and peaking off; (1) K = 1; (2) K = 1/2; (3) K = 1/4.
April 1993
3-641
7
Preliminary specification
Video enhancement
and 01 A processor (VEDA)
SAA9065
MEH277
o
r--.k
11 "'"
-8
-3 dB
Vu
(dB)
-16
"-\
1\
\
-24
\
/
7
\
1\
-32
I./'"r--....."
"-
"1\
\
J
-40
I
I
~
1\
-48
\
\
\
-56
\
-64
7
o
\
\
\
1\
\
\
I
4
2
6
5
7
fy(MHz)
Fig.10 Interpolation filter with 12C-bus control bits IFF = 0; IFC =0 and IFL = 0 in 4:1:1 format,
and control bits IFF = 1; IFC = 0 and IFL = 0 in 4:2:2 format; 13.5 MHz data rate.
o
MEH278
---I-l
-3 dB
-8
Vu
(dB)
-16
-24
"
f\
\
,
\
v--~
I
'\
\
-32
-40
,
r7
1\
-48
\
\
\
-56
\
-64
o
,
/ ~
2
v---.~
I
I
."\.
'\
~
-}
\
\
I
I
I
\
\
4
5
6
fy(MHz)
7
Fig.11 Interpolation filter with 12C-bus control bits IFF = 0; IFC = 0 and IFL = 1 in 4:1:1 format,
and control bits IFF = 1; IFC = 0 and IFL = 1 in 4:2:2 format; 13.5 MHz data rate.
April 1993
3-642
Preliminary specification
Video enhancement
and OfA processor (VEDA)
---
o
-8
Vu
(dB)
w. ......
-3 dB
SAA9065
MEH279
"
........
,
"\
-16
1\
-24
-32
\
./
,
'\
\
I
I
I
I
I
\
\
\
\
I
I
-56
-64
~
If
\
\
-48
-"""'-
/
\
-40
~
\
\
I
o
2
3
\
4
5
6
7
fy(MHz)
Fig.12 Interpolation filter with 12C-bus control bits IFF = 0; IFC = 1 and IFL
13.5 MHz data rate.
o
--
1/
-3
dB
Vu
(dB)
= 0 in 4:1:1
MEH280
.............
~
-16
-24
"" ""'-
-32
'".'"
r\
\
-40
-48
\
\,
\
-56
-64
format;
o
2
3
4
5
\
\\
6
fy(MHz)
Fig.13 Interpolation filter with 12C-bus control bits IFF = 1; IFC
13.5 MHz data rate.
April 1993
3-643
= 1 and IFL = X in 4:2:2 format;
7
Product specification
Philips Semiconductors Video Products
TDA2595
Horizontal combination
GENERAL DESCRIPTION
The TDA2595 is a monolithic integrated
circuit intended for use in colour television
receivers.
FEATURES
• Positive video input; capacitively coupled
(source impedance < 200Q)
• Adaptive sync separator; slicing level at
50% of sync amplitude
• Internal vertical pulse separator with
double slope integrator
• Output stage for vertical sync pulse or
composite sync depending on the load;
both are switched off at muting
• Burst keying and horizontal blanking pulse
generation, in combination with clamping of
the vertical blanking pulse (three-level
sandcastle)
• <1>1 phase control between horizontal sync
and oscillator
• Coincidence detector <1>3 for automatic
time-constant switching; overruled by the
VCR switch
• Horizontal drive output with constant duty
cycle inhibited by the protection circuit or
the supply voltage sensor
• Time-constant switch between two external
time-constants or loop-gain; both controlled
by the coincidence detector <1>3
• Detector for too low supply voltage
• Protection circuit for switching off the
horizontal drive output continuously if the
input voltage is below 4V or higher than 8V
• O.sv
7
-r, }{
.utpul
- -29".
pha .....dulat.d
T
6
5
"T1
c::
~
.....
w
0,
.j>.
(}l
...
lOAQ
SENSOR
iii'
~
DI
3
HOR./VEAT.
BlANMING
t
r-- U.
~
~
,
K.keying
pulse
VERT SYNC
SEPARATOR
I
VERT SYNC
PULSE
INTEGRATION
NORI20NTAL
SYNC
SEPARATOR
,
t
SYNC SLICING
LEVEL
150% of sync)
l+-
kEYINO
PUl.SE
OENERATION
BLACk LEVEl
DETERMINATION
I
VIDEO
AMPLIFIER
GATE
MODE
l
I7,S~.1
,-
l
I
GENERATION
OF COMPOSITE
1
~
TV
m_',,"
IDENTIFICATION
:-+-
DRIVE
fopen.collectorl
.'
n
SWITCH
OUTPUT
PULSE
SUPPRESSION
lOW"fli"
,
2
.
CONTROl
GENERATION
"'2
1220nF
"
T~
composite video
o
3
g:
OUTPUT STAGE
FOR SPOT
SUPPRESSION
lope:n.cotle.
Z
--I
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I
0
BLUE
a.
brightness
CD
0
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(J)
en
CD
3
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0
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Q.
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0
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I
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I
irt~~~~ion
(M)
w
m
U1
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""tJ
--I
a
t;;
Sl
o
01
For explanation of pulse mnemonics see Fig. 7.
Fig.1 Block diagram.
0'>
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o·
el.
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Product specification
Philips Semiconductors
TDA3566A
PALINTSC decoder
FEATURES
APPLICATIONS
• A black-current stabilizer which
controls the black-currents of the
three electron-guns to a level low
enough to om it the black-level
adjustment
• Teletext/broadcast antiope
Furthermore it contains a luminance
amplifier, an RGB-matrix and
amplifier. These amplifiers supply
output signals up to 4 V peak-to-peak
(picture information) enabling direct
drive of the discrete output stages.
The circuit also contains separate
inputs for data insertion, analog and
digital, which can be used for text
display systems.
• Channel number display.
GENERAL DESCRIPTION
• Contrast control of inserted RGB
signals
• No black-level disturbance when
non-synchronized external RGB
signals are available on the inputs
The TDA3566A is a decoder for the
PAL and/or NTSC colour television
standards. It combines all functions
required for the identification and
demodulation of PAUNTSC Signals.
• NTSC capability with hue control.
QUICK REFERENCE DATA
All voltages referenced to ground.
SYMBOL
I
I
PARAMETER
MIN.
I
TYP.
1 MAX. 1 UNIT
Supply
Vp
I supply voltage (pin 1)
1-
112
1-
Iv
Ip
I supply current (pin 1)
1-
190
l-
ImA
I input voltage (peak-to-peak value)
1-
ImV
1-
1450
116.5
1-
I contrast control
I-
I dB
140
1-
1150
11100
ImV
I output voltage at nominal luminance and contrast
(peak-to-peak value)
1-
I input signals (peak-to-peak value)
Luminance amplifier (pin 8)
V8 (p-p)
CON
Chrominance amplifier (pin 4)
I input voltage (peak-to-peak value)
V4 (p-p)
SAT
I saturation control
1-
IdB
1 .
1-
Iv
1-
11
1-
Iv
10.9
I-
I-
Iv
RGB matrix and amplifiers
V 13 ,
15, 17(p-p)
38
Data insertion
V 12, 14, 16(p-p)
Data blanking (pin 9)
I input voltage for data insertion
Vg
Sandcastle input (pin 7)
V7
I blanking input voltage
1-
11.5
J-
JV
V7
I burst gating and clamping input voltage
1-
17
1-
Iv
ORDERING INFORMATION
PACKAGE
EXTENDED TYPE
NUMBER
PINS
TDA3566A
28
February 1994
I
I
PIN POSITION
DIL
3-651
I
I
MATERIAL
plastic
I
I
CODE
SOT117
Product specification
Philips Semiconductors Video Products
Horizontal combination
TDA2595
CHARACTERISTICS (Continued)
vp = 12V; Tamb = +25°C; measured in Figure 1; unless otherwise specified
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Mute output (pin 7)
= 3mA; no TV transmitter
= 3mA; no TV transmitter
V7- 5
Output voltage at 17
-
-
0.5
V
R7- 5
Output resistance at 17
-
-
100
Q
17
Output leakage current at V12- 5 > 3V; TV transmitter identified
-
-
5
I1A
-
6
-
V
V
Protection circuit (beam-currentlEHT voltage protection) (pin 8)
= 0 (operative condition)
VS- 5
No-load voltage for Is
VS-5
Threshold at positive-going voltage
-
8±0.8
-
VS- 5
Threshold at negative-going voltage
-
4±0.4
-
V
±Is
Current limiting for VS-5
= 1 to 8.5V
-
60
-
I1A
RS- 5
Input resistance for VS- 5 > 8.5V
-
3
-
kQ
td
Internal response delay of threshold switch
-
10
-
I1s
-
-
0.5
V
-
-
5
I1A
Control output of line flyback pulse control (pin 1)
= 3mA
V1-5sat
Saturation voltage at standard operation; 11
11
Output leakage current in case of disturbance of line flyback pulse
NOTES TO THE CHARACTERISTICS:
1. Phase comparison between horizontal oscillator and the line flyback pulse. Generation of a phase modulated ( 2.15V
-
2.3
-
mA
16max
Maximum output current at V 6- 5 < 3V
-
3.3
-
mA
2.15
V
TV-transmitter identification (pin 12) (NOTE 4)
Output voltage
V 12- 5
no TV transmitter
-
-
V 12- 5
TV transmitter identified
7
-
March 1987
3-649
1
-
V
V
Product specification
Philips Semiconductors Video Products
Horizontal combination
TDA2595
CHARACTERISTICS (Continued)
V p = 12V; Tamb = +25°C; measured in Figure 1; unless otherwise specified
SYMBOL
PARAMETER
TYP.
MAX.
UNIT
-
-
0.5
V
its
MIN.
Horizontal output pulse (pin 4)
V4- 5
Output voltage LOW at 14 = SOmA
tp
Pulse duration (HIGH)
-
29± 15
-
Vp
Supply voltage for switching off the output pulse (pin 15)
-
4
-
V
t-.Vp
Hysteresis for switching on the output pulse
-
250
-
mV
Phase comparison 9.5V
-
8
-
mA
±117
Control current at V 18- 5 = V 15- 5 and V 13- 5 = 2 to 9.5V
1.8
2
2.2
mA
-
Horizontal oscillator control
-
kHz/its
680
-
Hz
-
10
-
%
-
7.5
-
its
-
2
V
9.5
V
-
-
3
mV
-
10
n
S 0.9 V
46
-
-
dB
suppression of external RGB signals
when V g < 0.3 V
46
-
-
dB
note 12
Data blanking
..
Sandcastle input (note 13)
V7
level at which the RGB blanking is
activated
1.0
1.5
2.0
V
Vi
level at which the horizontal pulses are
separated
3.0
3.5
4.0
V
February 1994
3-660
Product specification
Philips Semiconductors
TDA3566A
PAUNTSC decoder
PARAMETER
SYMBOL
CONDITIONS
TYP.
MIN.
MAX.
UNIT
V7
level at which the burst gate and
clamping pulse are separated
6.5
7.0
7.5
V
td
delay between black level clamping and
burst gating pulse
-
0.6
-
its
Ii
input current
-
-
-1
mA
50
itA
-
2
mA
Vi = 0 to 1 V
Vi = 1 to 8 V
Vi=8t012V
Black current stabilization
V 18
DC bias voltage
3.5
5.0
7.0
V
f"..V
difference between input voltage for
black current and leakage current
0.35
0.5
0.65
V
118
input current during black current
input current during scan
-
-
1
118
10
itA
mA
V18
internal lim iting at pin 18
8.5
9.0
9.5
V
V 18
switching threshold for black current
control on
7.6
8.0
8.4
V
R 18
input resistance during scan
1.0
1.5
2.0
kQ
DC input current during scan at pins 10,
20 and 21
-
-
30
nA
maximum charge or discharge current
during measuring time
(pins 10, 20 and 21)
-
1
-
mA
a
20
mV
-
8.8
9.2
V
itA
110,20,21
difference in drift of the blank level
note 11;
f"..T=40°C
NTSC
V24 -25
124+25 (AV)
HUE
level at which the PAUNTSC switch is
activated (pins 24 and 25)
average output current
(pin 24 plus pin 25)
note 14
62
82.5
103
hue control
see Fig.6
-
-
-
Notes to the characteristics
1.
Signal with the negative-going sync; amplitude includes sync pulse amplitude.
2.
Indicated is a signal with 75% colour bar, so the chrominance-to-burst ratio is 2.2: 1.
3.
Nominal contrast is specified as the maximum contrast -5 dB and nominal saturation as maximum -6 dB. This figure
is valid in the PAL-condition. In the NTSC-condition no output signal is available at pin 28.
4.
Cross coupling is measured under the following condition: input signal nominal, contrast and saturation such that
nominal output signals are obtained. The signals at the output at which no signal should be available must be
compared with the nominal output signal at that output.
5.
The signal-to-noise ratio is defined as peak-to-peak signal with respect to RMS noise.
6.
All frequency variations are referenced to the 4.4 MHz carrier frequency. All oscillator specifications have been
measured with the Philips crystaI4322143 ... or 4322144 ... series.
7.
The change in burst with Vp is proportional.
February 1994
3-661
Philips Semiconductors
Product specification
PAljNTSC decoder
TDA3566A
8.
These signal amplitudes are determined by the ACC circuit of the reference part.
9.
This value depends on the gain setting of the RGB output amplifiers and the drift of the picture tube guns. Higher
black level values are possible (up to 5 V) however, in that condition the amplitude of the available output signal is
reduced.
10. The variation of the black-level during brightness control in the three different channels is directly dependent on the
gain of each channel. Discolouration during adjustments of contrast and brightness does not occur because
amplitude and the black-level change with brightness control are directly related.
11. With respect to the measuring pulse.
12. This difference occurs when the source impedance of the data signals is 150 Q and the black level clam p pulse width
is 4 f-A,s (sandcastle pulse). For a lower impedance the difference will be lower.
13. For correct operating of the black level stabilization loop, the leading and trailing edges of the sandcastle pulse
(measured between 1.5 V and 3.5 V) must be within 200 ns and 600 ns respectively.
14. The voltage at pins 24 and 25 can be changed by connecting the load resistors (20 kQ, 1%, in this condition) to the
slider bar of the hue control potentiometer (see Fig.6). When the translstor is switched on, the voltage at pins 24 and
25 is reduced below 9 V, and the circuit is switched to NTSC mode. The width of the burst gate is assumed to be
4 f-A,S typical.
.
February 1994
3-662
Product specification
Philips Semiconductors
TDA3566A
PAUNTSC decoder
MBA967
MLA408
--
100
/1 / .'
/ /
G
(%)
80
100
-
40
/
/
20
/
VI
I' /
/
/
II
/1//
60
"I,
IVI
20
/ tfl
r-
o
o
4
V6-27
/'k'
o
4
V5 -27
M
Fig.3 Contrast control voltage range.
/
/11/
40
/
/
/11
-
//,
80
, / I'
60
///
G
(%)
I
/
o
,.....
Fig.4 Saturation control voltage range.
-
MLA409
MLA410
60
/~
.v
M
/'
/
-1
.............
//
,,'1',",
,,,\ '-.
V/
o
~.'
"
"
/' /. v'
-20
-- / / ~/
-2 --
-- r-_
........
-r..........
i'-..
"
20
40
/'/ v/
/'
M
"
~\....
,~
t'-, "
'-
-40
,..,/
-60
3
4
7.5
V11 -27 (1)
Fig.5
Difference between black level and
measuring level at the RGB outputs (~V) as
a function of the brightness control input
voltage (V11)'
February 1994
8
V25 -27 (1)
Fig.6 Hue control voltage range.
3-663
Product specification
Philips Semiconductors
TDA3566A
PALJNTSC decoder
21
2
22
23
24
JJLJL __ _
, lines
------',-
vertical blanking
01)
--
blanking pulse
(BL1)
~---
blanking pulse
(BL2)
~---
blanking pulse
(BL3)
~---
ULJLJL
insertion pulse (4L)
(control via pin 11)
black current
information pulse (M)
(pin 18)
---------------------------4--41--~~~--------
I
in
clamp pulse (LO)
__________________________-+__
clamp pulse (L1)
__________________________~~:--~rl~-------------------
clamp pulse (L2)
_____________________~~---~n~---------
clamp pulse (L3)
____________________________~I~~I--------~rl~--------
~I
L -_________________
I
l
retrace must
be completed
l
tt
end of vertical sync
Fig.7 Timing diagram for black-current stabilization.
February 1994
3-664
MLA411
"J;1
C"
APPLICATION INFORMATION
""'0
2
~
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-<
CD
CD
C
(f)
CD
(j)
::l
Z
--i
-I>-
120 kQ
()
+12V
390QII
1 DL700
AI
I
.---1
11 470 Q
10kQ
brightness
black
current
information
I I
+12V
0
0
en
..,
CD
1kQ
Y
1
3-level
sandcastle
pulse
I 1+'-'
CD
o·
a.
c
U
Q.
130
kQ
+12V
. __ .1- 331
Q.
()
3
0
10 nF
1.2 kQ
~
m
-6'
"'·U I I ...
I
BAW62
I
average
beam
current
!
+12V
10 kQ
contrast
"pF
c:J
T
I
RB
8.8
MHz
RED
GREEN
BLUE
18
13
15
17
11
8
9
12
14
16
c..>
cr,
C])
(J1
28
3
25
24
23
22
26
7
TDA3566A
4
27
+12V
19
10
di11lF
J:
1kQ
20
470 nF
;;s;jU
J:
21
470 nF
J:
J:
470 nF
10 nF
J:
100 nF
J:
100 nF
J:
68 kQ
100 nF
+12V
10kQ
• • saturation
ns
~
10.7 f.tH
composite
video
(1 Vp-p)
T
~
/1'I
27pF
R
blanking
G
B
~
data inputs
~normal
J;" killed
MGA821
--i
o
a.
c
U
CJ1
"0
CD
l;
0')
0')
Fig.8 Application diagram showing the TDA3566A for a PAL decoder.
""'0
(3
»
m
o
~
o·
~
o·
::l
~
~
~
~
2
~
0>
0>
TDA3566A
+12V
+12V
+12 V
-c::::J---T--I t--+
B~
loF
I
I
composite
video
(1Vp-p)
T
Q
10 kQ
saturation
t
y
y
Y
Y
I '''"
T
1 kQ
•
B
'v "..
+122~ ~
+12V
~ ""
~
pF
_
\..R .......
~~
blanking
G~
~
data inputs
L.-o- normal
M~8ro
?- killed
~
I I --I
g
CJ1
-g
g
»
W
0')
0')
Fig.9 Application diagram showing the TDA3566A for a PAUNTSC decoder.
~
0
CJ
»
$l
(J)
o·
~
o
::J
Philips Semiconductors
Product specification
PAUNTSC decoder
TDA3566A
MLA412
28
26
290 Q
3mA
31<0
TDA3566A
23
2.9V
1.75 mA
22
Fig.10 Internal pin circuitry (first part).
February 1994
3-667
Product specification
Philips Semiconductors
TDA3566A
PAUNTSC decoder
see pin 10
see pin 10
21
20
19
TDA3566A
1.5V
2.5V
1 kQ
see pin 19
see pin 12
see pin 19
see pin 12
17
16
15
14
1.5
2.2V
kQ
13
..n..
12
Fig.11 Internal pin circuitry (second part).
February 1994
3-668
3mA
Philips Semiconductors
Preliminary specification
Baseband delay line
FEATURES
• Two comb filters, using the
switched-capacitor technique, for
one line delay time (64I1-s)
• Adjustment-free application
• No crosstalk between SECAM
colour carriers (diaphoty)
• Handles negative or positive
colour-difference input signals
• Clamping of AC-coupled input
signals (±(R-Y) and ±(B-Y))
• VCO without external components
.3 MHz internal clock signal derived
from a 6 MHz CCO, line-locked by
the sandcastle pulse (64 IlS line)
• Sample-and-hold circuits and
low-pass filters to suppress the
3 MHz clock signal
• Addition of delayed and
non-delayed output signals
• Output buffer amplifiers
• Comb filtering functions for NTSC
colour-difference signals to
suppress cross-colour.
GENERAL DESCRIPTION
The TDA4665 is an integrated
baseband delay line circuit with one
line delay. It is suitable for decoders
with colour-difference signal outputs
±(R-Y) and ±(B-Y).
August 1993
TDA4665
QUICK REFERENCE DATA
SYMBOL
VP1
PARAMETER
analog supply voltage (pin 9)
MIN.
TYP.
MAX.
UNIT
4.5
5
6
V
V
VP2
digital supply voltage (pin 1)
4.5
5
6
IPtat
total supply current
5.9
7.0
mA
Vi
±(R-Y) input signal PAUNTSC
(peak-to-peak value, pin 16)
-
525
-
mV
±(B-Y) input signal PAUNTSC
(peak-to-peak value, pin 14)
-
665
-
mV
±(R-Y) input signal SECAM
(peak-to-peak value, pin 16)
-
1.05
-
V
±(B-Y) input signal SECAM
(peak-to-peak value, pin 14)
-
1.33
-
V
Gv
gain Va / Vi of colour-difference output signals
V11 / V16 for PAL and NTSC
5.3
5.8
6.3
dB
V12 / V14 for PAL and NTSC
5.3
5.8
6.3
dB
V11 / V16 for SECAM
-0.6
-0.1
+0.4
dB
V12 / V14 for SECAM
-0.6
-0.1
+0.4
dB
ORDERING INFORMATION
PACKAGE
EXTENDED
TYPE NUMBER
PINS
PIN
POSITION
MATERIAL
CODE
TDA4665
16
OIL
plastic
SOT38-4
TDA4665T
16
mini-pack
plastic
SOT109A
3-669
»
c
i)
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to
C
Il)
~
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(0
CD
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c.v
~
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co
:J
0..
0..
c..
Il)
Cil
CD
c
n-
o
'<
±(R-Y)
--I
SIGNAL
CLAMPING
±(R-Y)
colour-difference
input signals
pre-amplifiers
addition
stages
w
0,
0
V P1
output
buffers
colour- difference
output signals
SIGNAL
CLAMPING
±(B-Y) - - \
......
::J
CD
--f.
±(B-Y)
LINE
MEMORY
aoalog ,"pply
TDA4665
5
2]-
n.c .
6 - n.c.
13 - n.c.
15 - - n.c.
sandcastle
pulse input
IGND1
di:~
14 -
If t,J-;'
V p2
i)
MED848
...,
o
»
~
Q)
Q)
Fig.1 Block diagram.
01
~
~r
s·
~
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Preliminary specification
Philips Semiconductors
Baseband delay line
TDA4665
PINNING
SYMBOL
GND2
i.c.
PIN
1
2
3
4
SAND
n.c.
5
6
sandcastle pulse input
not connected
i.c.
i.c.
7
8
9
internally connected
internally connected
+5 V supply voltage for analog part
ground for analog part (0 V)
VP2
n.c.
VP1
GND1
Vo(R-Y)
VO (B-Y)
n.c.
Vi (B-Y)
n.c.
Vi (R-Y)
DESCRIPTION
+5 V supply voltage for digital part
not connected
ground for digital part (0 V)
internally connected
10
11
±(R-Y) output signal
12
13
±(8-Y) output signal
not connected
14
15
16
±(8-Y) input signal
not connected
±(R-Y) input signal
MED849
TDA4665
Fig.2 Pin configuration.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Ground pins 3 and 10 connected together.
SYMBOL
VP1
VP2
Vs
Vn
T 5 tg
Tamb
VESD
PARAMETER
supply voltage (pin 9)
supply voltage (pin 1)
voltage on pin 5
voltage on pins 11, 12, 14 and 1 6
storage temperature
MAX.
UNIT
MIN.
V
-0.5
+7
V
-0.5
+7
Vp + 1.0 V
-0.5
Vp
V
-0.5
-25
+150
°c
operating ambient temperature
0
electrostatic handling for all pins (note 1) -
+70
±500
°c
V
Note to the Limiting Values
1. Equivalent to discharging a 200 pF capacitor through a 0 n series resistor.
THERMAL RESISTANCE
SYMBOL
Rthj-a
August 1993
PARAMETER
THERMAL RESISTANCE
from junction to ambient in free air
SOT38-4
SOT109A
75 KJW
220 KJW
3-671
Philips Semiconductors
Preliminary specification
TDA4665
Baseband delay line
CHARACTERISTICS
Vp = 5.0 V; input signals as specified in characteristics with 75% colour bars; super-sandcastle frequency of
15.625 kHz; Tamb = +25 °c, measurements taken in Fig.3 unless otherwise specified.
SYMBOL
VP1
VP2
Ip1
Ip2
PARAMETER
supply voltage (analog part, pin 9)
supply voltage (digital part, pin 1)
supply current
supply current
CONDITIONS
MIN.
4.5
4.5
TYP.
5
5
5.2
0.7
6
UNIT
V
V
6.0
1.0
mA
mA
-
525
-
665
1.05
1.33
-
mV
mV
V
V
1
2
-
-
V
V
-
MAX.
6
Colour-difference input signals
Vi
input signal (peak-to-peak value; note 1)
±(R-Y) PAL and NTSC (pin 16)
±(B-Y) PAL and NTSC (pin 14)
Vi max
R14.16
C14,16
V14,16
±(R-Y) SECAM (pin 16)
±(B-Y) SECAM (pin 14)
maximum symmetrical input signal (peak-to-peak value)
±(R-Y) or ±(B-Y) for PAL and NTSC
before clipping
±(R-Y) or ±(B-Y) for SECAM
before clipping
input resistance
input capacitance
input clamping voltage
Colour-difference output signals
Vo
output signal (peak-to-peak value)
±(R-Y) on pin 11
proportional to Vp
-
1.05
-
V
-
Vi 14, 16 = 1.33 V (p-p)
-0.4
1.33
0
+0.4
V
dB
3.10
330
3.30
400
Q
5.8
-0.1
0
+0.4
+0.1
DC output voltage
proportional to Vp
output resistance
Gv
gain for PAL and NTSC
gain for SECAM
ratio of output signals on pins 11 and 12
for adjacent time samples at constant
input signals
td
ttr
August 1993
1.7
-
R11,12
Vn
S/N(W)
1.5
kQ
pF
V
all standards
V11,12
VnNn+1
1.3
40
10
all standards
±(B-Y) on pin 12
ratio of output amplitudes at equal input
signals
V11N12
-
-
-
2.90
5.3
ratio Vo!Vi
-0.6
ratio Vo!Vi
Vi 14,16 = 1.33 V (p-p); -0.1
SECAM signals
noise voltage (RMS value, pins 11 and 12) Vi 14, 16 = 0 V; note 2
weighted signal-to-noise ratio
Vo = 1 V (p-p); f = tbn
delay of delayed signals
delay of non-delayed signals
6.3
V
dB
dB
dB
-
-
1.2
-
54
-
63.94
40
64.0
60
64.06
80
~s
mV
dB
ns
transient time of delayed signal on
pins 11 respectively 12
300 ns transient of
SECAM signal
-
350
-
ns
transient time of non-delayed signal on
pins 11 respectively 12
300 ns transient of
SECAM signal
-
320
-
ns
3-672
Preliminary specification
Philips Semiconductors
TDA4665
Baseband delay line
SYMBOL
PARAMETER
Sandcastle pulse input (pin 5)
burst-key frequency / sandcastle frequency
fSK
top pulse voltage
Vs
internal slicing level
Vslice
Is
input current
Cs
input capacitance
CONDITIONS
note 3
MIN.
TYP.
15.625
14.2
4.0
Vs-1.0 -
-
-
UNIT
MAX.
17.0
kHz
Vp + 1.0 V
V5 - 0.5 V
10
10
J.l.A
pF
Notes to the characteristics
1. For SECAM the signal must be blanked line-sequentially. The blanking level must be equal to the non-colour signal.
For SECAM, PAL and NTSC the input signal must be equal to the non-colour signal during the internal clamping of
TDA4665 (3 J.l.s to 1 J.l.s before the leading edge of the top pulse of Vs.
2. Noise voltage at f = 10kHz to 1 MHz; Vi 14, 16 = 0 (Rs < 300 il).
3. The leading edge of the burst-key pulse or top pulse is used for timing.
August 1993
3-673
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TDA4665
0.33 iJF
colourdifference
signals
~1-I16
±(R-V) comb filtering
~t--I14
Vo-(R-V)
10 nF
3 l---jJ
Vo-{B-V)
., . " I
~
TDA4650
cp
~
8
i.c.
PAL
2E~
-+-NTSC-4.43 •
colour standard
switching signals
~
n.c.
n.c.
n.c.
n.c.
28
27
~~
23
22
17
21
Vp
nF
~
20
XlX~
nF
~
HUE
off
HUE
~ontrol
'If
18
l--
n..L 0 33 iJF
10 kn c:::J c:::J
22]22
]
19
88 7 2
1
1 .
f7 nF
.LMHz.lMHz
30
pF
30
pF
:.r
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33kn
=r
-u
i
0.1 iJF
~r
3'
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MED850
Fig.3 Application circuit with TDA4650.
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Preliminary specification
Philips Semiconductors Video Products
TDA4670
Picture signal improvement (PSI) circuit
.1I
f
•
"I.!,I.C,,·.".·
.•·.:
. .
.",I.i.l.•.,.·.•.
B'mB'
...........................
FEATURES
• Luminance signal delay from 20 ns
up to 1100 ns (minimum step 45 ns)
• Luminance signal peaking with
symmetrical overshoots selectable
.2.6 or 5 MHz peaking centre
frequency and degree of peaking
selectable (-3, 0, +3 and +6 dB)
QUICK REFERENCE DATA
SYMBOL
MIN.
PARAMETER
TYP.
MAX.
UNIT
supply voltage (pins 1 and 5)
4.5
5
8.8
V
Ip
total supply current
31
41
52
mA
tdY
Y signal delay time
20
1130
ns
ViVBS
composite Y input signal
(peak-to-peak value, pin 16)
450
640
mV
ViCD
colour-difference input signal
(peak-to-peak value)
±(R-Y) on pin 3
1.05
1.48
V
±(B-Y) on pin 7
1.33
1.88
V
-1
-
dB
70
°C
Vp
• Noise reduction by coring selectable
• Handles negative as well as
positive colour-difference signals
• Colour transient improvement (CTI)
selectable to decrease the
colour-difference signal transient
times to those of the high frequency
luminance signals
• 5 or 12 V sandcastle input voltage
selectable
• All controls selected via the 12C-bus
• Timing pulse generation for
clamping and delay time control
synchronized by sandcastle pulse
-
Gy
gain of Y channel
G CD
gain of colour-difference channel
Tamb
operating ambient temperature
range
0
0
dB
• Automatic luminance signal delay
correction using a control loop
• Luminance and colour-difference
input signal clamping with
coupling-capacitor
• +4.5 to 8.8 V supply voltage range
• Minimum of external components
GENERAL DESCRIPTION
The TOA4670 delays the luminance
signal and improves colour-difference
signal transients. Additional, the
luminance signal can be improved by
peaking and noise reduction (coring).
May 1991
ORDERING INFORMATION
EXTENDED
TYPE NUMBER PINS
TOA4670
18
3-675
PACKAGE
PIN POSITION
OIL
MATERIAL
CODE
plastic
SOT102
(")-0
~
co
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~
~100nF
SDA
~100nF
SCL
In
cC°
-1 2 C-Bus
12C-BUS RECEIVER
V_ncl:::H/ r - i
:J
1--,
at
I
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(") ...
c:: C -0'
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degree of
peaking
3
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CD
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CD
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I
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t
I~B~sl
I
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100nF
HI 113
H100nF
TDA4670
1
-(R-Yl
f'--..
~
BK
-1
II
DlFFEREN-
FULL-WAVE
,..........
f'--..
~.
;..a
17.
Y
4 1-(R-YI
1.. capacitors
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Il.
I I
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s·
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7Z30096
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i
en
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-.
,FSkT
all input
a!'ld out~ut
pins wit out
pins 9 and 10
GNDI
+-f
vt
-...
"0
en
..:;
TDA4670
=~
10L
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~
3'
s·
III
2
3
COL
CD input
-I
C
9
CD output
Vp I
CD output
Fig.4 Internal circuit.
CD input
GND
SDA
MEH238
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Philips Semiconductors Video Products
Preliminary specification
Video processor with automatic cut-off
and white level control
TDA4680
PINNING
SYMBOL PIN
DESCRIPTION
FSW2
1 fast switch 2 input
2
red input 2
R2
DESCRIPTION
SYMBOL PIN
BCl
15 average beam current limiting input
16 storage capacitor for peak drive limiting
CPDl
G2
B2
Vp
-(B-Y)
-(R-Y)
Y
GND
R,
G1
B1
FSW1
SC
17
3
4
5
6
green input 2
blue input 2
supply voltage
colour difference input -(B-Y)
Cl
WI
CI
7
8
9
10
11
colour difference input -(R-Y)
luminance input
ground
red input 1
green input 1
Ca
12
13
blue input 1
fast switch 1 input
HUE
SOA
26
27
14
sandcastle pulse input
SCl
28
18
19
20
So
21
22
23
24
25
Go
CG
Ro
CR
a:
MED694
u
0
a:
C)
u
storage capacitor for leakage current
white level measurement input
cut-off measurement input
blue output
blue cut-off storage capacitor
green output
green cut-off storage capacitor
red outP!Jt
red cut-off storage capacitor
hue control output
I4!C-bus serial data input/output
I<::C-bus serial clock input
0
(!')
al
u
0
CD
C3
SCL
SDA
HUE
C
R
HUE
18 WI
SDA
17 C L
RO
CG
SCl
Go
FSW 2
ce
16 C pDL
28
TDA4680WP
15
BCl
R2
2
14 SC
CI
G2
3
13
FSW 1
WI
82
4
12
B1
BO
R1
B1
cL
FSW,
C pDL
SC
Bel ,
Fig.2 Pin configuration for Oil
package.
April 1993
CL
>
s:- s:$. ~
>-
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z
a:
(!')
(!')
Fig.3 Pin configuration for PlCC paclcage.
3-687
MED695
Philips Semiconductors Video Products
Preliminary specification
Video processor with automatic cut-off
and white level control
12C-BUS CONTROL
The 12C-bus transmitter/receiver
provides the data bytes to select
and adjust the following functions
and parameters:
- brightness adjust
- saturation adjust
- contrast adjust
- hue control voltage
- RGB gain adjust
- RGB reference voltage levels
- peak drive limiting
- selection of the vertical blanking
interval and measurement lines for
cut-off and white level control
according to transmission standard
- selects either 3-level or 2-level
(5 V) sandcastle pulse
- enables/disables input clamping
pulse delay
- enables/disables white level control
- enables cut-off control/ enables
output clamping
- enables/disables full screen white
level
- enables/disables full screen black
level
-selects either PAUSECAM or
NTSC matrix
- enables saturation adjust / enables
nominal saturation
- enables/disables synchronization
of the execution of ,2C-bus
commands with the vertical
blanking interval
- reads the result of the comparison
of the nominal and actual RGB
signal levels for automatic white
level control.
TDA4680
12 C-BUS TRANSMITTER I
RECEIVER AND DATA TRANSFER.
12 C-bus specification
The 12C-bus is a bi-directional,
two-wire, serial data bus for
intercommunication between ICs in
an equipment. The microcontroller
transmits/receives data from the
12C-bus transceiver in the TDA4680
over the serial data line SDA
(pin 27) synchronized by the serial
clock line SCL (pin 28). Both lines
are normally connected to a positive
voltage supply through pull-up
resistors. Data is transferred when
theSCL line is LOW. When SCL is
HIGH the serial data line SDA must
be stable. A HIGH-to-LOW transition
of the SDA line when SCL is HIGH
is defined as a start bit. A
LOW-to-HIGH transition of the SDA
line when SCL is HIGH is defined as
a stop bit. Each transmission must
start with a start bit and end with a
stop bit. The bus is busy after a start
bit and is only free again after a stop
bit has been transmitted.
12C-bus receiver
(microcontroller write mode)
Each transmission tolfrom the
12C-bus transceiver consists of at
least three bytes following the start
bit. Each byte is acknowledged by
an acknowledge bit immediately
following each byte. The first byte is
the Module ADdress (MAD) byte,
also called slave address byte. This
consists of the module address,
10001002 for the TDA4680, plus the
Rm bit (see Fig.4). When the
TDA4680 is a slave receiver
(Rm =0) the module address byte
is 100010002 (88 Hex). When the
TDA4680 is a slave transmitter
(Rm =1) the module address byte
is 10001 0012 (89 Hex).
The length of a data transmission is
unrestricted, but the module address
and the correct sub-address must
be transmitted before the data
byte(s). The order of data
transmission is shown in Fig.5 and
Fig.S. Without auto-increment
(BREN =0 or 1) the module address
(MAD) byte is followed by a
Sub-ADdress (SAD) byte and one
data byte only (Fig.5).
MSB
LSB
o
- - - module address -
I I
0
X
ACK
R/W
MED696
Fig.4 The module address byte.
l 1 1 1/ I I
ST A
MAD
SAD
STO
(
start
condition
data byte
stop
MED697
condition
Fig.5 Data transmission without auto-increment (BREN
I srAI
stort
condition
MAD
I ~L I
SAD
dota byte
~L ~L ~L ~/ ~I I I
dato byte
5TO
3-688
stop
condition
... E0698
Fig.6 Data transmission with auto-increment (BREN
April 1993
=0 or 1).
=0).
Philips Semiconductors Video Products
Preliminary specification
Video processor with automatic cut-off
and white level control
Auto-Increment
The auto-increment format enables
quick slave receiver initialization by
one transmission, when the 12C-bus
control bit BREN = 0 (see control
register bits of Table 1). If BREN = 1
auto-increment is not possible.
If the auto-increment format is
selected, the MAD byte is followed
by an SAD byte and by the data
bytes of consecutive sub-addresses
(Fig.6).
All sub-addresses from 00 to OF are
automatically incremented, the
sub-address counter wraps round
from OF to 00. Reserved
sub-addresses OB, OE and OF are
treated as legal but have no effect.
Sub-addresses outside the range 00
and OF are not acknowledged by the
device and neither auto-increment
nor any other internal operation
takes place (For versions V1 to V5
sub-addresses outside the range 00
and OF are acknowledged but
neither auto-increment nor any other
internal operation takes place).
Sub-addresses are stored in the
TDA4680 to address the following
parameters and functions, see
Table 1:
- brightness adjust
- saturation adjust
- contrast adjust
- hue control voltage
- RGB gain adjust
- RGB reference voltage levels
- peak drive limiting adjust
- control register functions.
The data bytes (07-00 of Table 1)
provide the data of the parameters
and functions for video processing.
Control register 1
VBWx (Vertical Blanking Window):
x = 0, 1 or 2. VBWx selects the
vertical blanking interval and
positions the measurement lines
for cut-off and white level control.
The actual lines in the vertical
blanking interval after the start of the
V pulses selected as measurement
April 1993
TDA4680
lines for cut-off and white level
control are shown in Table 2.
The standards marked with (*) are
for progressive line scan at double
line frequency (2FL), i.e.
approximately 31 kHz.
NMEN (NTSC - Matrix ENable):
0= PAUSECAM matrix
1 = NTSC matrix.
WPEN (White Pulse ENable):
o = white measuring pulse
disabled
1 = white measuring pulse
enabled.
BREN (Buffer Register ENable):
o = new data is executed as soon
as it is received
1 == data is stored in buffer
registers and is transferred to the
data registers during the next
vertical blanking interval.
The 12C-bus transceiver does not
accept any new data until this
data is transferred into the data
registers.
DELOF (DELay OFf) delays the
leading edge of clamping pulses:
o = delay enabled
1 = delay disabled.
SC5 (SandCastle 5 V):
o= 3-level sandcastle pulse
1 = 2-level (5 V) sandcastle pulse.
Control register 2
FSON2 - Fast Switch 2 ON
FSDIS2 - Fast Switch 2 DISable
FSON1 - Fast Switch 1 ON
FSDIS1 - Fast Switch 1 DISable
The RGB input signals are selected
by FSON2 and FSON1 or FSW2 and
FSW1:
- FSON2 has priority over FSON1 ;
- FSW2 has priority over FSW1 ;
- FSDIS1 and FSDIS2 disable
FSW1 and FSW2 (see Table 3).
BCOF - Black level Control OFf:
o = automatic cut-off control
enabled
1 = automatic cut-off control
disabled; RGB outputs are
clamped to fixed DC levels.
3-689
FSBL - Full Screen Black Level:
o= normal mode
1 = full screen black level (cut-off
measurement level during full
field).
FSWL - Full Screen White Level:
o = normal mode
1 = full screen white level (white
measurement level during full
field).
SATOF - SATuration control OFf:
o= saturation control enabled
1 = saturation control disabled,
nominal saturation enabled.
12 C-bus transmitter
(microcontroller read mode)
As an 12C-bus transmitter, RiW = 1,
the TDA4680 sends a data byte
from the status register to the
microcontroller. The data byte
consists of following bits:
PONRES, CB1, CBO, CG1 , CGO,
CR1, CRO and 0, where PONRES is
the most significant bit.
PONRES (Power ON RESet)
monitors the state of TDA4680's
supply voltage:
o = normal operation
1 = supply voltage has dropped
below approximately 6.0 V
(usually occurs when the TV
receiver is switched on or the
supply voltage was interrupted).
When PONRES changes state from
a logic LOW to a logic HIGH all data
and function bits are set to logic
LOW.
2-blt white level error signal
(see Table 4).
CB1, CBO =2-bit white level of the
blue channel.
CG1 • CGO = 2-bit white level of the
green channel.
CR1. CRO = 2-bit white level of the
red channel.
Philips Semiconductors Video Products
Preliminary specification
Video processor with automatic cut-off
and white level control
TDA4680
Table 1 Sub-address (SAD) and data bytes.
FUNCTION
BrightneSs
Saturation
Contrast
Hue control voltage
Red gain
Green gain
Blue gain
Red level reference
Green level reference
Blue level reference
Peak drive limit
Reserved
Control register 1
Control register 2
Reserved
Reserved
SAD
(HEX)
00
01
02
03
04
05
06
07
08
09
OA
OS
OC
00
OE
OF
MSB
7
0
0
0
0
0
0
0
0
0
0
0
x
SC5
SATOF
x
x
6
0
0
0
0
0
0
0
0
0
0
0
x
OELOF
FSWL
x
x
5
A05
A15
A25
A35
A45
ASS
ASS
A75
A85
A95
AA5
x
BREN
FSBL
x
x
DATA BYTE
3
4
A04
A03
A13
A14
A24
A23
A33
A34
A43
A44
A54
A53
A64
A63
A73
A74
A83
A84
A93
A94
AA4
AA3
x
x
NMEN
WPEN
BCOF FSDIS2
x
x
x
x
Table 2 Cut-off and white level measurement lines.
VBW2 VBW1 VBWO
R
G
WHITE
B
0
0
0
20
19
21
22
0
0
1
16
17
18
19
0
1
0
22
23
24
25
1
0
0
38,39 40,41 42,43 44,45
1
0
1
32,33 34,35 36,37 38,39
1
1
0
44,45 46,47 48,49 50,51
STANDARD
PAUSECAM
NTSCIPALM
PAUSECAM (EB)
PAL */SECAM*
NTSC*IPAL M*
PAL*/SECAM* (EB)
Notes to Table 2
1. The line numbers given are those of the horizontal pulse counts after the
start of the vertical component of the sandcastle pulse.
2. * line frequency of approximately 31 kHz.
3. (EB) is extended blanking.
April 1993
3-690
2
A02
A12
A22
A32
A42
A52
A62
A72
A82
A92
AA2
x
VBW2
FSON2
x
x
1
A01
A11
A21
A31
A41
A51
A61
A71
A81
A91
AA1
x
VBW1
FSDIS1
x
x
LSB
0
AOO
A10
A20
A30
A40
A50
A60
A70
A80
A90
AAO
x
VBWO
FSON1
x
x
Philips Semiconductors Video Products
Preliminary specification
Video processor with automatic cut-off
and white level control
TDA4680
Table 3 Signal input selection by the fast source switches.
ANALOG SWITCH SIGNALS
12C-BUS CONTROL BITS
FSON2
FSDIS2
FSON1
FSDIS1
l
l
l
l
l
L
l
L
l
H
L
H
H
X
l
H
l
H
l
L
H
X
INPUT SELECTED
FSW2
(pin 1)
FSW1
(pin 13)
l
l
H
H
X
l
X
H
ON
l
X
X
H
X
ON
H
X
H
X
X
RGB1
l
H
X
X
X
X
X
X
YICD
ON
ON
ON
ON
ON
l
X
X
l
RGB2
ON
ON
ON
ON
ON
Note to Table 3
Where l is a logic LOW « 0.4 V), H is a logic HIGH (> 0.9 V), X is 'don't care', and ON is the selected input signal.
Table 4 2-bit white level error signals, CX1 and CXO.
CX1
0
CXO
0
1
0
1
1
0
1
INTERPRETATION
RAR (Reset-Atter-Read):
no new measurements since last read
actual (measured) white level less than
the tolerance range
actual (measured) white level within
the tolerance range
actual (measured) white level greater than
the tolerance range
UMI11NG VALUES
tn accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL
Vp
VI
'AV
1M
1,8
126
Tstg
Tamb
Plot
April 1993
PARAMETER
supply voltage (pin 5)
-
MAX.
8.8
input voltage (pins 1 to 8, 10 to 13, 16,
21, 23 and 25)
-0.1
Vp
input voltage (pins 14, 15, 18 and 19)
input voltage (pins 27 and 28)
average current (pins 20,22 and 24)
-0.7
-0.1
4
Vp + 0.7 V
8.8
V
-10
rnA
peak current (pins 20, 22 and 24)
input current
output current
storage temperature
4
0
0.5
-20
-20
2
-8
rnA
rnA
rnA
+150
operating ambient temperature
total power diSSipation
SOT117
SOT261CG
0
+70
°c
°c
-
1.2
1.0
VI
MIN.
-
3-691
UNIT
V
V
W
»
m
::J
~
<
_.
Q..Q..
CD
-<
(J)
'0
~
(j)
CD
ex>
~
o
o
(")
:::;;
0"
::J
Philips Semiconductors Video Products
Preliminary specification
Video processor with automatic cut-off
and white level control
TDA4680
CHARACTERISTICS
All voltages are measured in test circuit of Fig.8 with respect to GND (pin 9); Vp
- at nominal signal amplitudes (black-to-white) at output pins 24, 22 and 20,
- at nominal settings of brightness, contrast, saturation and white level control,
- without beam current or peak drive limiting; unless otherwise specified.
SYMBOL
Vp
Ip
PARAMETER
supply voltage (pin 5)
supply current (pin 5)
Colour difference Inputs
V6(p-p)
-(B-Y) input (peak-to-peak value)
V7(p-p)
-(R-Y) input (peak-to-peak value)
V6,7
internal DC bias voltage
input current
16,7
input resistance
R6,7
Luminance/sync (VBS)
Vi (p-p)
luminance input at pin 8
(peak-to-peak value)
Va
internal DC bias voltage
input current
18
TYP.
8.0
85
UNIT
MAX.
V
8.8
mA
110
1.33
1.05
3.1
-
±100
10
-
-
note 2
-
0.45
-
V
at black level clamping
during line scan
at black level clamping
-
CONDITIONS
MIN.
7.2
notes 1 and 2
notes 1 and 2
at black level clamping
during line scan
at black level clamping
input resistance
Ra
R1, G1 and B1 Inputs
Vi(p-p)
black-to-white input signals at pins 10, 11 note 2
and 12 (peak-to-peak value)
internal DC bias voltage
V10/11/12
at black level clamping
input current
during line scan
/'0111112
at black level clamping
input resistance
R10/11/12
R2, G2 and B21nputs
Vi(p-p)
black-to-white input signals at pins 2, 3
note 2
and 4 (peak-to-peak value)
internal DC bias voltage
V21314
at black level clamping
input current
during line scan
121314
at black level clamping
input resistance
R21314
PAUSECAM and NTSC matrix (notes 3 and 4)
PAUSECAM matrix
control bit NMEN = 0
NTSCmatrix
control bit NMEN = 1
Fast Signal switch FSW1 to select Y, CD or R1. G1. B1 Inputs
(control bits: see Table 3)
voltage to select Y and CD
V13
voltage range to select R1, G1, 81
internal resistance to ground
R13
At
difference between transit times for
signal switching and signal insertion
April 1993
=8.0 V; Tamb = +25 °C:
3-693
-
±100
10
-
-
±O.1
V
V
V
~
~
Mil
3.1
-
V
-
±0.1
-
~
~
-
-
Mil
0.7
-
V
5.3
-
V
±0.1
±100
10
-
-
~
~
Mil
-
0.7
-
V
-
5.3
-
V
-
±O.1
~
-
-
-
~
Mil
-
0.4
5.0
V
V
kil
ns
±100
10
0.9
-
4.0
-
-
10
Philips Semiconductors Video Products
Preliminary specification
Video processor with automatic cut-off
and white level control
TDA4680
SYMBOL
PARAMETER
CONDITIONS
Fast signal switch FSW2 to select Y, CD I R1, G1, B1 or R2, G2, B21nputs
(control bits: see Table 3)
V1
voltage to select Y, CO/R1, G1, B1
voltage range to select R2, G2, ~
R1
internal resistance to ground
at
difference between transit times for
signal switching and signal insertion
Saturation adjust
acts on internal RGB signals under 12C-bus control,
sub-address 01 Hex (bit resolution 1.5% of maximum saturation);
data byte 3FHex for maximum saturation
data byte 23Hex for nominal saturation
data byte OOHex for minimum saturation
ds
saturation below maximum
at 23Hex
at OOHex; f = 100 kHz
Contrast adjust
acts on internal RGB signals under 12C-bus control,
sub-address 02Hex (bit resolution 1.5% of maximum contrast);
data byte 3FHex for maximum contrast
data byte 2CHex for nominal contrast
data byte OOHex for minimum contrast
contrast below maximum
de
at 2CHex
at OOHex
Brightness adjust
acts on internal RGB signals under 12C-bus control,
sub-address OOHex (bit resolution 1.5% of brightness range);
data byte 3FHex for maximum brightness
data byte 27Hex for nominal brightness
data byte OOHex for minimum brightness
dbr
black level shift of nominal signal
at 3FHex
amplitude referred to cut-off
at OOHex
measurement level
White potentiometers, under fC-bus control,
sub-addresses 04tiex (red), OSHex (green) and 06Hex (blue); see note 5.
data byte 3FHex for maximum gain
data byte 22Hex for nominal gain
data byte OOHex for minimum gain
aG v
relative to nominal gain:
increase of gain
at 3FHex
decrease of gain
at OOHex
April 1993
3-694
MIN.
-
TYP.
-
UNIT
MAX.
10
V
V
kn
ns
5
50
-
dB
dB
-
3
22
-
dB
dB
-
30
-50
-
0/0
%
-
60
60
-
0/0
-
%
0.9
-
-
-
-
4.0
0.4
5.0
-
Philips Semiconductors Video Products
Preliminary specification
Video processor with automatic cut-off
and white level control
TDA4680
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
RGB outputs pins 24, 22 and 20
(positive going output signals and no peak drive limitation; sub-address OAHex = 3FHex); see note 6.
nominal output signals
2
Vo(b-w)
(black-to-white value)
maximum output signals
3.2
(black-ta-white value)
10
spread between RGB output signals
!No
0.8
minimum output voltages
Vo
maximum output voltages
6.8
2.7
voltage of cut-off measurement line
2.3
2.5
V24,22,20
output clamping
(BCOF =1)
internal current sources
5.0
lint
output resistance
110
65
Ro
Frequency response
d
3
frequency response of Y path
f = 10 MHz
(from pin 8 to pins 24, 22, 20)
frequency response of CD path
3
f= 8 MHz
(from pins 7 to 24 and 6 to 20)
3
frequency response of RGBI path (from f = 10 MHz
pins 10 to 24,11 to 22 and 12 to 20)
3
frequency response of RGB2 path
f = 10 MHz
(from pins 2 to 24, 3 to 22 and 4 to 20)
Sandcastle pulse detector (control bit SC5 = O)
three level; notes 7 and 8
required voltage range.
V14
for H and V blanking pulses
3.0
2.0
2.5
for H pulses (line count)
5.0
4.0
4.5
for burst key pulses
Vp + 0.7
6.3
SandcastJe pulse detector (control bit SC5 = 1)
two level; note 7
required voltage range
V14
for H and V blanking pulses
3.0
2.0
2.5
for burst key pulses
Vp + 0.7
4.0
4.5
Sandcastle ~ ulse detector
input current
100
114
V14= OV
leading edge delay of the clamping pulse control bit DElOF = 0 td
1.5
control bit DElOF = 1 0
required burst key pulse time
t8K
control bit DELOF = 0; 3
normally used with fL
control bit DElOF = 1; 1.5
normally used with 2ft.
npulse
required horizontal or burst key pulses
29
e.g. at interlace scan
4
during vertical blanking interval
(VBW2=0)
57
e.g. at progressive line 8
scan (VBW2 = 1)
April 1993
3-695
UNIT
V
V
%
V
V
V
mA
n
dB
dB
dB
dB
V
V
V
V
V
~
~
~
~
~
Preliminary specification
· Philips Semiconductors Video Products
Video processor with automatic cut-off
and white level control
SYMBOL
PARAMETER
Averaae beam current IImltlna (note 9)
contrast reduction starting voltage
Vc(15)
~VC(15)
voltage difference for full contrast
reduction
Vbr(15)
brightness reduction starting voltage
~Vbr(15)
voltage difference for full brightness
reduction
TDA4680
CONDITIONS
MIN.
3-696
MAX.
UNIT
-
4.0
-2.0
-
V
V
-
2.5
-1.6
-
V
V
-
3.0
-
V
V
4.0
-2.0
-
2.5
-1.6
-
-
Vp -1.4 V
Peak drive limiting voltage (note 10)
internal peak drive limiting level (Vpdl) acts on RGB outputs under 12C-bus control,
sub-address OAHex
level for minimum RGB outputs
V20/22124
at byte OOHex
level for maximum RGB outputs
at byte 3FHex
6.5
charge current
I1s
discharge current
durtng peak white
internal voltage limitation
V1S
4.5
Vc(1S)
contrast reduction starting voltage
~VC(1S)
voltage difference for full contrast
reduction
Vbr(1S)
brightness reduction starting voltage
~Vbr(1S)
voltage difference for full brightness
reduction
Automatic cut-off and white level control (notes 11, 12 and 13)
see Fig.10
permissible voltage
Vl9
(also during scanning period)
(,9
output current
input current
150
additional input current
during monitor pulse
monitor pulse amplitude (under
switch-on delay 1
V24,22,20
12C-bus control, sub-address OAHex)
voltage threshold for picture tube
switch-on delay 1
V19
cathode warm-up
internally controlled voltage (VREF)
during leakage
measurement period
data byte 07Hex for red reference level
data byte 08Hex for green reference level
data byte 09Hex for blue reference level
~V19
difference between VMEAS (cut-off or 3FHex (maximum VMEAS) 1.5
white level measurement voltage)
20Hex (nominal VMEAS)
andVREF
OOHex (minimum VMEAS) input current
l1a
white level measurement internal resistance
Rla
to VREF; (,a S 800 j.l.A
~V19
white level register (measured value white level measurement within tolerance range)
April 1993
TYP.
-1
5
-
-
~
mA
V
V
V
V
V
0.5
Vpdl- 0.7
-
~
~
mA
V
5.0
-
V
3.0
-
V
-
-
V
V
V
1.0
100
250
-140
0.5
800
-
-
~
Q
mV
Preliminary specification
Philips Semiconductors Video Products
Video processor with automatic cut-off
and white level control
SYMBOL
PARAMETER
Cut-off storage
charge and discharge currents
121/23/25
current
Leakage storage
117
charge and discharge currents
current
voltage for reset to switch-on below
V17
Hue control (note 14)
under 12C-bus control, sub-address 03Hex
data byte 3FHex for maximum voltage
data byte 20Hex for nominal voltage
data byte OOHex for minimum voltage
output voltage
V26
TDA4680
TYP.
MAX.
UNIT
during cut-off
measurement lines
outside measurement
-
to.3
-
mA
-
-
to.1
~
during leakage
measurement period
outside measurement
-
to.4
-
rnA
-
<3.0
-
V
4.8
-
-
at byte 3FHex
at byte 20Hex
at byte OOHex
current of the internal current source at
pin 26
12C-bus transceiver clock SCL
m
~
-
Fig.2 Pin configuration for Oil
package.
May 1993
s:- s:-
$- $-
>-
CI
z
a:
C.!)
(!J
Fig.3 Pin configuration for PLCC package.
3-703
MED717
Philips Semiconductors
Preliminary specification
Video processor with automatic cut-off control
GENERAL DESCRIPTION
(continued)
Its primary function is to process the
luminance and colour difference
signals from a colour decoderwhich
is equipped e. g. with the
multistandard decoder TDA4655 or
TDA9160 plus delayline tda4661
and the Picture Signal Improvement
(PSI) IC TDA467X or from a Feature
Module. The required input signals
are:
-luminance and negative colour
difference signals
- 2- or 3-level sandcastle pulse for
internal timing pulse generation
2
- 1 C-bus data and clock signals for
microprocessor control.
Two sets of analog RGB colour
signals can also be inserted, e.g.
one from a peritelevision connector
and the other from an on-screen
display generator. The TDA4686
has 12 C-bus control of all parameters
and functions with automatic cut-off
control of the picture tube cathode
currents. It provides RGB output
signals for the video output stages.
The TDA4686 is a simplified, pin
compatible (except pin 18) version
of the TDA4680. The module
address via the 12C-bus can be used
for both ICs; where a function is not
included in the TDA4686 then the
2
1 C-bus command is not executed.
The differences with the TDA4680
are:
- no automatic white level control;
the white levels are determined
directly by the 12 C-bus data
- RGB reference levels for
automatic cut-off control are not
adjustable via 12 C-bus
- no clamping delay
- only contrast and brightness adjust
for the RGB input signals
- the measurement lines are
triggered either by the trailing edge
of the vertical component of the
sandcastle pulse or by the trailing
edge of an optional external
TDA4686
vertical fly back pulse (on pin 18),
according to which occurs first.
The TDA4685 is like TDA4686 but
intended for normal line frequency
application.
2
1 C-BUS CONTROL
2
The 1 C-bus transmitter provides
the data bytes to select and adjust
the following functions and
parameters:
- brightness adjust
- saturation adjust
- contrast adjust
- DC output e. g. for hue control
- RGB gain adjust
- peak drive limiting level adjust
- selects either 3-level or 2-level
(5 V) sand castle pulse
- enables cut-off control/enables
output clamping
- selects either PAUSECAM or
NTSC matrix
- enables/disables synchronization
of the execution of 12C-bus
commands with the vertical
blanking interval
-enables Y-CD, RGB1 or RGB2
input.
12 C-BUS TRANSMITTER AND DATA
TRANSFER
12C-bus specification
The 12C-bus is a bi-directional,
two-wire, serial data bus for
intercommunication between ICs in
an eqUipment. The microcontroller
transmits data to the 12C-bus
receiver in the TDA4686 over the
serial data line SDA (pin 27)
synchronized by the serial clock line
SCL (pin 28). Both lines are
normally connected to a positive
voltage supply through pull-up
resistors. Data is transferred when
the SCL line is LOW. When SCL is
HIGH the serial data line SDA must
be st~ble. A HIGH-to-LOW transition
of the SDA line when SCL is HIGH
is defined as a start bit.
A LOW-to-HIGH transition of the
SDA line when SCL is HIGH is
defined as a stop bit. Each
transmission must start with a start
bit and end with a stop bit. The bus
is busy after a start bit and is only
free again after a stop bit has been
transmitted.
MSB
LSB
o
o
0
o
0
ACK
- - - - - module address - - _ . R/W
MED710
Fig.4 The module address byte.
MED697
condition
data byte
.condition
Fig.5 Data transmission without auto-increment (BREN = 0 or 1).
I I I
STA
start
condition
.AD
SAD
}!
data byte
I 5TO
data byte
~ED698
Fig.6 Data transmission with auto-increment (BREN
May 1993
3-704
stop
condition
=0).
Preliminary specification
Philips Semiconductors
Video processor with automatic cut-off control
12 C-bus receiver
(microcontroller write mode)
Each transmission to the 12C-bus
receiver consists of at least three
bytes following the start bit. Each
byte is acknowledged by an
acknowledge bit immediately
following each byte. The first byte is
the Module ADdress (MAD) byte,
also called slave address byte. This
includes the module address,
10001002 for the TDA4686. The
TDA4686 is a slave receiver
(RiiJ = 0), therefore the module
address byte is 100010002 (88 Hex),
see Fig.4.
The length of a data transmission is
unrestricted, but the module address
and the correct sub-address must
be transmitted before the data
byte(s). The order of data
transmission is shown in Fig.5 and
Fig.6. Without auto-increment
(BREN =0 or 1 ) the Module
ADdress (MAD) byte is followed by
a Sub-ADdress (SAD) byte and one
data byte only (Fig.5).
Auto-increment
The auto-increment format enables
quick slave receiver initialization by
one transmission, when the 12C-bus
control bit BREN= 0 (see control
register bits of Table 1). If BREN =1
auto-increment is not possible.
If the auto-increment format is
selected, the MAD byte is followed
by an SAD byte and by the data
bytes of consecutive sub-addresses
(Fig.6).
All sub-addresses from 00 to OF are
automatically incremented, the
sub-address counter wraps round
from OF to 00. Reserved
sub-addresses 07, 08, 09, OB, OE
and OF are treated as legal but have
no effect. Sub-addresses outside
the range 00 and OF are not
acknowledged by the device.
The sub-addresses are stored in the
TDA4686 to address the following
parameters and functions, see
Table 1:
- brightness adjust
- saturation adjust
- contrast adjust
- hue control voltage
- RGB gain adjust
- peak drive limiting adjust
- control register functions.
The data bytes (D7 ~DO of Table 1)
provide the data of the parameters
and functions for video processing.
TDA4686
Control register 1
NMEN (NTSC-Matrix ENable):
0= PAUSECAM matrix
1 = NTSC matrix.
BREN (Buffer Register ENable):
o =new data is executed as soon
as it is received
1 = data is stored in buffer
registers and is transferred to the
data registers during the next
vertical blanking interval.
The fC-bus receiver does not
accept any new data until this
data is transferred into the data
registers.
SC5 (SandCastle 5 V):
o = 3-level sandcastle pulse
1 =2-level (5 V) sandcastle pulse.
Control register 2
FSON2 - Fast Switch 2 ON
FSDIS2 - Fast Switch 2 DISable
FSON1 - Fast Switch 1 ON
FSDIS1 - Fast Switch 1 DISable
The RGB input signals are selected
by FSON2 and FSON1 or FSW2 and
FSW1:
- FSON2 has priority over FSON 1;
- FSW2 has priority over FSW1;
- FSDIS1 and FSDIS2 disable
FSW1 and FSW2(see Table 2).
BCOF - Black level Control OFf:
o=automatic cut-off control
enabled
1 = automatic cut-off control
disabled; RGB outputs are
clamped to fixed DC levels.
When the supply voltage has
dropped below approximately 6.0 V
(usually occurs when the TV
receiver is switched on or the supply
voltage is interrupted) all data and
function bits are set to 01 Hex.
May 1993
3-705
Preliminary specification
Philips Semiconductors
TDA4686
Video processor with automatic:cut-off control
Table 1 Sub-address (SAD) and data bytes.
FUNCTION
Brightness
Saturation
Contrast
SAD
(HEX)
00
01
02
7
LSB
DATA BYTE
MSB
5
6
0
0
0
3
A03
A13
A23
A33
A43
2
A02
A12
A22
A32
A42
1
A01
A11
A21
A31
A41
AOO
Afo
A20
A30
A40
A25
A35
A45
0
0
0
0
0
0
0
0
0
0
0
0
0
4
A04
A14
A24
A34
A44
A55
A65
A54
A64
A53
A63
A52
A62
A51
A61
A50
A60
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
OA
OB
0
0
AA5
AA4
AA3
AA2
AA1
AAO
x
x
SC5
x
x
x
OC
00
x
x
x
x
x
x
x
x
BCOF
NMEN
FSDIS2
x
x
FSON2
FSDIS1
FSON1
x
x
x
x
x
x
x
x
x
x
0
0
Hue control voltage
Red gain
03
04
0
0
0
Green gain
Blue gain
Reserved
Reserved
Reserved
05
06
07
08
09
Peak drive limit
Reserved
Control register 1
Control register 2
Reserved
Reserved
OE
OF
x
x
x
A05
A15
BREN
x
x
x
x
Note to Table 1
X is 'don't care', but for software compatibility with other or future video ICs it is recommended to set all 'X' to '0'.
Table 2 Signal input selection by the fast source switches.
12C-BUS CONTROL BITS
ANALOG SWITCH SIGNALS
FSON2
FSDIS2
FSON1
FSDlS1
L
L
L
L
FSW2
(pin 1)
FSW1
(pin 13)
L
L
H
H
L
L
L
H
L
H
L
L
H
X
L
H
L
L
L
H
H
L
L
H
H
L
H
H
X
X
X
X
X
X
X
X
X
INPUT SELECTED
RGB2
RGB1
ON
L
X
X
X
X
X
V/CD
ON
ON
ON
ON
ON
ON
ON
L
H
ON
X
X
X
ON
ON
ON
Note to Table 2
Where L is a logic LOW « 0.4 V), H is a logic HIGH (> 0.9 V), X is 'don't care', and ON is the selected input signal.
May 1993
3-706
Preliminary specification
Philips Semiconductors
TDA4686
Video processor with automatic cut-off control
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL
Vp
VI
PARAMETER
supply voltage (pin 5)
input voltage (pins 1 to 8, 10 to 13, 16,
21, 23 and 25)
input voltage (pins 15, 18 and 19)
input voltage (pins 27 and 28)
-
MAX.
8.8
-0.1
Vp
-0.7
-0.1
MIN.
UNIT
V
V
V14
IAv
1M
peak current (pins 20,22 and 24)
-20
126
output current
-8
Vp + 0.7 V
V
Vp +5.8 V
rnA
4
rnA
4
rnA
0.6
Tstg
Tamb
Ptot
storage temperature
operating ambient temperature
total power dissipation
SOT117
SOT261CG
-20
0
+150
+70
°c
-
1.2
1.0
W
W
May 1993
sand castle pulse voltage
average current (pins 20,22 and 24)
-0.7
-10
-
8.8
3-707
°C
Preliminary specification
Philips Semiconductors
Video processor with automatic cut-off control
TDA4686
$
"5
~
N
"u
cti
c
2
~
oS
l"-
e,
u:
May 1993
3-708
Philips Semiconductors
Preliminary specification
TDA4686
Video processor with automatic cut-off control
CHARACTERISTICS
All voltages are measured in test circuit of Figo8 with respect to GND (pin 9); Vp = 8.0 V; Tamb = +25 °C:
- at nominal signal amplitudes (black-to-white) at output pins 24, 22 and 20,
- at nominal settings of brightness, contrast, saturation and white level control,
- without beam current or peak drive limiting; unless otherwise specified.
SYMBOL
Vp
Ip
PARAMETER
supply voltage (pin 5)
supply current (pin 5)
Colour difference inputs
V6(p-p)
-(B-Y) input (peak-to-peak value)
V7(pop)
-(R-Y) input (peak-to-peak value)
V6,7
16,7
R6,7
internal DC bias voltage
input current
input current
R21314
input resistance
PAUSECAM and NTSC matrix (note 3)
PAUSECAM matrix
NTSC matrix
R13
May 1993
-
1.33
-
1.05
4.1
-
-
±0.1
UNIT
V
mA
at black level clamping
-
at black level clamping
±100
10
-
-
-
note 2
-
0.45
-
V
at black level clamping
during line scan
at black level clamping
-
4.1
-
V
-
-
±0.1
+100
-
10
-
-
~
~
MQ
-
0.7
-
V
V
V
V
~
~
MQ
5.7
-
V
±0.1
10
-
-
~
~
MQ
note 2
-
0.7
-
V
at black level clamping
during line scan
-
5.7
-
V
-
-
±0.1
~
at black level clamping
±100
-
-
!JA
10
-
-
0.4
V
0.9
-
5.0
V
-
4.0
-
kQ
-
10
ns
control bit NMEN
control bit NMEN
Fast signal switch FSW1 to select Y, CD or R1, Gl, B1 inputs
control bits FSDIS1, FSON1 (see Table 2)
voltage to select Y and CD
V13
~t
MAX.
8.8
during line scan
input resistance
121314
TYP.
8.0
60
-
notes 1 and 2
notes 1 and 2
R1, G1 and B1 inputs
Vi (pop)
black-to-white input signals at pins 10, 11 note 2
and 12 (peak-to-peak value)
internal DC bias voltage
V10/11/12
at black level clamping
input current
(,0111112
during line scan
at black level clamping
input resistance
R10/11/12
R2, G2 and B2 inputs
Vi(pop)
black-to-white input signals at pins 2, 3
and 4 (peak-to-peak value)
internal DC bias voltage
V2/314
MIN.
7.2
-
input resistance
Luminance/sync (VBS)
Vi (p-p)
luminance input at pin 8
(peak-to-peak value)
internal DC bias voltage
Vs
input current
Is
Rs
CONDITIONS
voltage range to select R1, G1, B1
internal resistance to ground
difference between transit times for
signal switching and signal insertion
3-709
±100
MQ
=0
=1
Philips Semiconductors
Preliminary specification
Video processor with automatic cut-off control
SYMBOL
PARAMETER
TDA4686
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Fast signal switch FSW2 to select Y, CD I R1, G1, B1 or R2, G2, B2 inputs
control bits FSDIS2, FSON2 (see Table 2)
V1
Rl
.lt
0.9
-
0.4
5.0
V
V
-
4.0
-
kn
-
10
ns
-
5
50
-
dB
dB
-
5
22
-
dB
dB
-
30
-50
-
0/0
-
-
0/0
-
50
50
-
voltage to select Y, CD/R1, Gl, B1
voltage range to select R2, G2, B2
internal resistance to ground
difference between transit times for
signal switching and signal insertion
Saturation adjust
acts on -(R-Y) and -(B-Y) signals under 12C-bus control,
sub-address 01 Hex (bit resolution 1.5% of maximum saturation);
data byte 3FHex for maximum saturation
data byte 23Hex for nominal saturation
data byte OOHex for minimum saturation
ds
saturation below maximum
at 23Hex
at OOHex; f
Contrast adjust
acts on internal RGB signals under 12C-bus control,
sub-address 02Hex (bit resolution 1.5% of maximum contrast);
data byte 3FHex for maximum contrast
data byte 22Hex for nominal contrast
data byte OOHex for minimum contrast
contrast below maximum
de
at 22Hex
at OOHex
=100 kHz
Brightness adjust
acts on internal RGB signals under 12C-bus control,
sub-address OOHex (bit resolution 1.5% of maximum brightness);
data byte 3FHex for maximum brightness
data byte 26Hex for nominal brightness
data byte OOHex for minimum brightness
black leve~ shift of nominal signal
amplitude referred to cut-off
measurement level
White potentiometers, under 12C-bus control,
dbr
at 3FHex
at OOHex
sub-addresses 04Hex (red), 05Hex (green) and 06Hex (blue); note 4.
data byte 3FHex for maximum gain
data byte 19Hex for nominal gain
data byte OOHex for minimum gain·
.lG v
relative to nominal gain:
increase of gain .
at 3FHex
decrease of gain
at OOHex
May 1993
3-710
-
0/0
-
%
Philips Semiconductors
Preliminary specification
Video processor with automatic cut-off control
SYMBOL
PARAMETER
CONDITIONS
RGB outputs pins 24, 22 and 20
(positive going output signals; peak drive limiter set = 3FHex); note 5.
VO(b.W)
nominal output signal amplitudes
(black-to-white value)
maximum output signal amplitudes
(black-to-white value)
6.Vo
spread between RGB output signals
Vo
V24.22.20
minimum output voltages
maximum output voltages
voltage of cut-off measurement line
lint
Ro
internal current sources
output resistance
BCOF = 1
(output clamping)
FreQuency response (measured with 10 Mil, 30 pF external load)
d
frequency response of Y path
f = 14 MHz
(from pin 8 to pins 24, 22, 20)
TDA4686
MIN.
UNIT
MAX.
TYP.
-
2
-
V
3.0
-
-
V
-
-
10
0.8
0/0
6.8
-
-
2.3
2.5
2.7
V
V
V
-
-
5.0
20
-
n
-
-
3
dB
rnA
frequency response of CD path
(from pins 7 to 24 and 6 to 20)
f=12MHz
-
-
3
dB
frequency response of RGB1 path (from
pins 10 to 24,11 to 22 and 12 to 20)
frequency response of RGB2 path
(from pins 2 to 24, 3 to 22 and 4 to 20)
f=22 MHz
-
-
3
dB
f = 22 MHz
-
-
3
dB
2.0
4.0
2.5
4.5
7.6
-
3.0
V
V
5.0
Vp + 5.8 V
2.0
2.5
3.0
4.0
4.5
Vp + 5.8 V
Sandcastle pulse detector (control bit SC5 = 0)
three level; notes 6 and 7
V14
required voltage range
for H and V blanking pulses
for H pulses (line count)
for burst key pulses (clamping)
Sandcastle pulse detector (control bit SC5 = 1)
two level; notes 6 and 7
required voltage range
V14
for H and V blanking pulses
for burst key pulses
V
Sandcastle pulse detector
output current
114
V14 = 0 V
td
leading edge delay of the clamping pulse
-
-
-100
-
0
-
~
IlS
VFB (note 7)
vertical flyback pulse
V18
for LOW
-
-
2.5
V
for HIGH
pin 18 open-circuit;
note 8
4.5
-
-
-
5.0
-
V
V
-
-
5
~
internal voltage
1,8
May 1993
input current
3-711
Preliminary specification
Philips Semiconductors
Video processor with automatic cut-off control
SYMBOL
PARAMETER
Average beam current limiting (note 9)
Vc(15)
llVC(15)
TDA4686
CONDITIONS
:
contrast reduction starting voltage
voltage difference for full contrast
reduction
-
MAX.
TYP.
MIN.
UNIT
-
V
-2.0
V
V
4.0
V
Vbr(15)
brightness reduction starting voltage
-
2.5
-
llVbr(15)
voltage difference for full brightness
reduction
-
-1.6
-
-
3.0
V
-
V
-
~
mA
V
V
V
2.5
-1.6
-
V
V
-
~O
Peak drive limiting voltage (note 10)
internal peak drive limiting level (Vpdl) acts on RGB outputs
12C-bus control, sub-address OAHex
V20122J24
level for minimum RGB outputs
at byte OOHex
-
level for maximum RGB outputs
at byte 3FHex
7.0
-
-1
during peak white
4.5
-
-
-
4.0
-
-2.0
h6
charge current
V16
discharge current
internal voltage limitation
Vc(16)
contrast reduction starting voltage
llVC(16)
voltage difference for full contrast
reduction
Vbr(16)
llVbr(16)
brightness reduction starting voltage
voltage difference for full brightness
reduction
-
-
5
,
Automatic cut-off control (notes 7, 11, 12 and 13)
see Fig.10
V19
external voltage
119
output current
input current
V24.22.20
V'9
llV19
May 1993
-
Vp -1.4 V
additional input current
monitor pulse amplitude (under
12C-bus control, sub-address OAHex)
voltage threshold for picture tube
cathode warm-up
switch-on delay 1
switch-on de lay 1 ;
note 12
switch-on delay 1
-
0.5
Vpdl-1.0
-
~
~
mA
V
-
4.5
-
V
internally controlled voltage (VREF)
during leakage
measurement period
-
2.7
-
V
-
1.0
-
V
150
voltage difference between VMEAS
(cut-off measurement voltage) and
VREF
3-712
-
Philips Semiconductors
Preliminary specification
Video processor with automatic cut-off control
SYMBOL
PARAMETER
TDA4686
CONDITIONS
MIN.
MAX.
TYP.
UNIT
Cut-off storage
121/23/25
charge and discharge currents
during cut-off
measurement lines
-
±0.3
-
rnA
current
outside measurement
-
-
±0.1
~
-
rnA
Leakage storage
117
charge and discharge currents
during leakage
measurement period
-
±O.4
current
outside measurement
±0.1
threshold voltage for reset to switch-on
state
-
-
V17
2.5
-
V
at byte 3FHex
4.8
-
at byte 20Hex
-
3.0
-
V
-
1.2
V
500
-
-
~
~
Hue control (note 14)
2
under 1 C-bus control, sub-address 03Hex
data byte 3FHex for maximum voltage
data byte 20Hex for nominal voltage
data byte OOHex for minimum voltage
V26
output voltage
at byte OOHex
lint
current of the internal current source at
pin 26
V
12C-bus receiver clock SCL (pin 28)
fSCL
input frequency range
0
-
100
kHz
V,L
LOW level input voltage
-
1.5
V
V,H
HIGH level input voltage
3.0
-
6.0
V
hL
LOW level input current
-10
IIH
HIGH level input current
-
~
~
pulse delay time LOW
4.7
pulse delay time HIGH
4.0
tr
rise time
tf
fall time
-
td
-
10
-
~
1.0
~
-
0.3
~
-
1.5
V
6.0
V
-10
-
~
~
rnA
1.0
~
0.3
~
-
~
~
2
1 C-bus receiver data input/output SDA (pin 27)
V,L
LOW level input voltage
-
V,H
HIGH level input voltage
3.0
IlL
' LOW level input current
hH
HIGH level input current
-
IOL
LOW level output current
3.0
tr
rise time
tf
fall time
-
tSU;OAT
data set-up time
0.25
May 1993
3-713
-
10
Preliminary specification
Philips Semiconductors
Video processor with automatic cut"-off control
TDA4686
Notes to the characteristics
1, The values of the -(B-Y) and -(R-Y) colour difference input signals are for a 75% colour-bar signal.
2. The pins are capacitively coupled to a low otimicsource, with a recommended maximum output impedance of 600 Q.
3. PAUSECAM signals are matrixed by the equation: VG--V =-0.51 VR-V - 0.19Vs-y
NTSC signals are matrixed by the equations (hue phase shift of -5 degrees):
VR-Y* = 1.57VR-V - 0.41 VB-V; VG-v* =-0.43VR-Y - 0.11 VB-V; VB-Y* = VB-V
In the matrix equations: VR-Y and VB-yare conventional PAL demodulation axes and amplitudes at the output of the
NTSC demodulator. VG-v*, VR-V* and VB-v* are the NTSC"modified colour difference signals; this is equivalent to
the following demodulator axes and amplification factors:
NTSC
(B-Y)* demodulator axis
0°
PAL
0°
(R-Y)* demodulator axis
115°
90°
(R-Y)* amplification factor
(B-Y)* amplification factor
1.97
2.03
1.14
2.03
VG-Y* =-O.27VR-V* - 0.22Vs-v*.
4. The white potentiometers affect the amplitudes of the 'AGB output signals.
5. The RGB outputs at pins 24, 22 and 20 are emitter followers with current sources.
6. Sandcastle pulses are compared with internalthreshold voltages independent of VP. The threshold voltages
separate the components of the sandcastle pulse. The particular component is generated when the voltage on
pin 14 exceeds the defined internal threshold voltage. The internal threshold voltages (control bit SC5 = 0) are:
1.5 V for horizontal and vertical blanking pulses (H and V blanking pulses),
3.5 V for horizontal pulses,
6.5 V for the burst key pulse.
The internal threshold voltages, control bit SC5 = 1, are:
1.5 V for horizontal and vertical blanking pulses,
3.5 V for the burst key pulse.
7. Vertical signal blanking is determined by the vertical component of the sandcastle pulse. The leakage and the RGB
cut-off measurement lines are positioned in the first four complete lines after the end of the vertical component. In
this case, the RGB output signals are blanked until the end.of the last measurement line; see Fig.1 O(a). If an extra
vertical flyback pulse VFB is applied to pin 18, the four measurement lines start in the first complete line after the
end of the VFB pulse; see Fig.1 O(b). In this case, the output signals are blanked either until the end of the last
measurement line or until the end of the vertical component of the sandcastle pulse, according to which occurs last.
8. If no VFB pulse is applied, pin 18 should be connected to VP. If pin 18 is always LOW neither automatic cut-off
control nor output clamping can happen.
9. Average beam current limiting reduces the contrast, at minimum contrast it reduces the brightness.
10. Peak drive limiting reduces the RGB outputs by reducing the contrast, at minimum contrast it reduces the
brightness. The maximum RGB outputs are determined via the 12C-bus under,sub-address OAHex. When an RGB .
output exceeds the maximum voltage, peak drive limiting is delayed by one horizontal line.
11. During leakage current measurement, theRGB channels are blanked to ultra-black level. During cut-off
measurement one channel is setto the, measurement pulse level, the other channels are blanked to ultra-black.
Since the brightness adjust shifts thecQI()ur signal relative to the black level, the brightness adjust is disabled during
the vertical blanking interval (see Fig.9 and Fig.10).
12. During picture cathode warm~up (first switch-on delay) the RGB outputs (pins 24, 22 and 20) are blanked to the
ultra-black level during line scan. During the vertical blanking interval a white-level monitor pulse is fed out on the
RGB outputs and the cathode currents are measured. When the voltage threshold on pin 19 is greater than 4.5 V,
the monitor pulse is switched off and cut-off control is activated (second switch-on delay). As soon as cut-off control
stabilizes, RGB output blanking is removed.
13. The cut-off measurement level range at the RGB outputs is 1 to 5 V. The recommended value is 3 V.
14. The hue control output at pin 26 is an emitter follower with current source.
May 1993
3-714
Philips Semiconductors
Preliminary specification
Video processor with automatic cut-off control
TDA4686
SCl
FSW2
FSW 2 ~---------.-------~
R2
100
~------~~--t-:----:';:";';'4.--~
G2
~-------'---Ir--+----4 .--~
B2
B2 ~--_--+----1I---i-----:'':''':':'4.--~
26
CR
24
-(S-Y)
-(R-Y)
Y
Y ~------------~~~I-+-~
23
7
22
TDA4686
8
21
GND
R,
G,
G,
B,
B1
FSW,
FSW 1
200 V
HUE
25
Vp
-.~----------""':"='.:..::....jIHf--..!:~
n
27
G2
-(R-Y)
hue
28
R2
-(B-Y)
SOA
20
10
19
11
18
12
17
13
16
SC
SC ~---r--+----Ir--+---------r-~ 14
15
+ 12V
1220 nF~
Ro
CG
GNO
,220 nF~
Go
CB
Ro
,220 nF ~
Go
80
Bo
CI
CI
VF8
CL
10
,330 nF~
CON2
CPDL+ ~
BCl
VFB
(optional)
lN4148
MED719
Vp=
8V
220
~F
beam
current
information
+
r
(1) Insert link SRl if average beam
current limiting is not applied.
Fig.8 Test and application circuit.
maximum brightness
nominal brightness
MED713
cut-off measurement line
for red signal
ultra-black
Fig.9 Cut-off measurement pulse.
May 1993
3-715
Preliminary specification
Philips Semiconductors
Video processor with automatic cut-off control
_R_c_h_~_n_el
TDA4686
LM~~
________________________________________
_____
B channel
~
/1 /1
~V~
LM
G channel
~
_ _ _ _ _ _ _ _ _~/1V /1~
LM
(a) Timing controlled by sandcas~e pulse
R ch~nel
.
I
~
venical
flyback
pulse (VFB)
LM = leakage current measurement time
MR, MG. MB = R,G.B cut-off measurement pulses
__________________________________________________________________
LM
MR
G channel
LM
B channel
LM
MG
(b) Timing controlled by additional venical flyback pulse (VFB)
Fig.10 Leakage and cut-off current measurement timing diagram.
May 1993
3-716
MED714
Philips Semiconductors Video Products
Preliminary specification
Sync separation circuit for video applications
FEATURES
• Fully integrated, few external
components
• Positive video input signal,
capacitively coupled
• Operates with non-standard video
input signals
• Black level clamping
• Generation of composite sync
slicing level at 50% of peak sync
voltage
• Vertical sync separator with
double slope integrator
• Delay time of the vertical output
pulse is determined by an external
resistor
• Vertical sync generation with a
slicing level at 40% of peak sync
voltage
• Output stage for composite sync
• Output stage for vertical sync
QUICK REFERENCE DATA
CONDITIONS MIN_ TYP. MAX. UNIT
SYMBOL PARAMETER
Vp
supply voltage
range (pin 1)
10.8
12
13.2
V
Ip
supply current
(pin 1)
-
8
12
mA
V 2(p-p)
input voltage
amplitude
(peak-to-peak value)
0.2
1
3
V
50
300
500
mV
Vsync(p-p sync pulse input
voltage amplitude
(pin 2)
(peak-to-peak value)
Vo
maximum vertical
sync output voltage
(pin 6)
16=-1 rnA
10.0
-
-
V
Vo
maximum composite 17=-3 mA
sync output voltage
(pin 7)
10.0
-
-
V
Vo
minimum output
voltage
(pins 6 and 7)
-
-
0.6
V
Tamb
operating ambient
temperature range
0
-
+ 70
°c
GENERAL DESCRIPTION
The TDA4820T is a monolithic
integrated circuit including a
horizontal and a vertical sync
separator, offering composite sync
and vertical sync extracted from the
video signal.
TDA4820T
16,7 = 1 mA
ORDERING AND PACKAGE INFORMATION
June 1990
PACKAGE
EXTENDED
TYPE NUMBER
PINS
PIN POSITION
MATERIAL
CODE
TDA4820T
8
mfnj-pack
plastic
S08;SOT96A
3-717
Preliminary specification
Philips Semiconductors Video Products
Sync separation circuit for video applications
'-
"
L1
TDA4820T
positive
eves
signal
Fig. 1 Block diagram and application circuit.
PINNING
SYMBOL
Vp
VCVBS
SLEV
VDEL
PIN CONRGURAll0N
PIN
DESCRIPTION
1
supply voltage
2
video input signal
3
slicing level
4
vertical integration delay time
n.c.
S
not connected
VSYN
CSYN
GND
6
vertical sync output signal
7
composite sync output signal
8
ground
June 1990
Fig. 2 Pin configuration.
3-718
Philips Semiconductors Video Products
Preliminary specification
TDA4820T
Sync separation circuit for video applications
FUNCTIONAL DESCRIPTION
The complete circuit consists of the
following functional blocks as shown
in Fig. 1:
- Video amplifier and black level
clamping
- 50% peak sync voltage
- Composite sync slicing
- Vertical slicing and double slope
integrator
- Vertical sync output
- Composite sync output
voltage, similar to the composite
sync slicing.
With signal interference (reflections
or noise) the reduced vertical slicing
level ensures more energy for the
vertical pulse integration. The slope
is double-integrated to eliminate the
influence of signal interference.
The vertical integration delay time fctv
can be set from typically 45 ~ (pin 4
open) to typically 18 J.1s (pin 4
grounded). Between these maximum
and minimum values,
fctv can be set
by a resistor R1 from pin 4 to ground.
For optimum sync behaviour with
input line sync pulses only, R1 has to
be ~ 3.3 kn. In this case fctv is
typically~ 23 J.1S.
Vertical sync output
Composite sync output
Both output stages are emitter
followers with bias currents of 2 mA.
Video amplifier and black level
clamping (pin 2)
The sync separation circuit
TDA4820T is designed for positive
video input signals.
The video signal (supplied via
capacitor C2 at pin 2) is amplified by
approximately 15 in the input
amplifier. The black level clamping
voltage (approximately 2 V) is stored
by capacitor C2.
6
5
n.c.
TDA4820T
50% peak sync voltage (pin 3)
From the black level and the peak
sync voltage, the 500.4 value of the
peak sync voltage is generated and
stored by capacitor C3 at pin 3.
A slicing level control circuit ensures
a constant 50% value, as long as the
sync pulse amplitude at pin 2 is
between 50 mV and 500 mV,
independent of the amplitude of the
picture content
Composite sync slicing
A comparator in the composite sync
slicing stage compares the amplified
video signal with the DC voltage
derived from 50% peak sync voltage.
This generates the composite sync
output signal.
Vertical slicing and double slope
Integrator
Vertical slicing compares the
composite sync signal with a DC
level equal to 40 % of the peak sync
June 1990
Fig.3 Internal circuits.
UMmNG VALUES
In accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
Vp
supply voltage "(pin 1)
0
13.2
V
Vi
input voltage (pin 2)
-0.5
6
V
'0
output current (pin 6 and pin 7)
3
-10
mA
Tstg
storage temperature range
-25
+ 150
°C
Tamb .
operating ambient temperature range
0
+ 70
°C
Tj
maximum junction temperature
150
°C
Ptot
total power dissipation
-
500
mW
3-719
Preliminary specification
Philips Semiconductors Video Products
TDA4820T
Sync separation circuit for video applications
CHARACTERISTICS
All voltages measured to GND (pin 8); Vp = 12 V; Tamb = 25 DC; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Vp
supply voltage range (pin 1)
10.8
12.0
13.2
V
Ip
supply current (pin 1)
4
8
12
mA
Video amplifier
V2(p_p)
input amplitude
(peak-to-peak value)
positive video signal
AC coupled
0.2
1
3
V
Vsync (p-p)
sync pulse amplitude (pin 2)
(peak-to-peak value)
composite sync slicing
level 50% for
0.2 V S V2(p-p) S 1.5 V
50
300
500
mV
Zs
source impedance
-
-
200
n
5
-25
-
~
during black level
-
-
~
-40
-20
-
~
during video content
-
16
-345
-
~
-
Black level clamping
12
discharge current of C2
during video content
charge currents of C2
sync below slicing level
sync above slicing level
-
~A
50% peak sync voltage
13
discharge current of C3
maximum charge current of C3
~
reduced charge current of C3
during vertical sync
-
-255
~
charge current of C3
during sync pulse
-
-
-160
-
~
50
-
0/0
250
500
ns
Composite sync slicing (see Fig.4)
tclH
composite sync slicing level
0.2 V S V2(p-p) S 1.5 V
horizontal delay time (pin 7)
maximum load at pin 7:
CL S 5 pF; RU~ 100 kn
-
Vertical sync separation· (see Fig.5)
tclv
slicing level for vertical sync
0.2 V S V2(p_p) S 1.5 V
-
40
-
0/0
vertical leading edge delay times
(pin 6)
pin 4 open
30
45
60
J.Ls
pin 4 grounded
11
18
25
~s
Vertical and composite sync outputs
Vo
maximum vertical sync
output voltage (pin 6)
Is =-1 mA
10.0
10.5
11.5
V
Vo
maximum composite sync
output voltage (pin 7)
17 =-3 mA
10.0
10.5
11.5
V
Vo
minimum output voltages
(pins 6 and 7)
Is,7 =1 mA
0.1
0.3
0.6
V
tw
vertical sync pulse width
pin 4 open; standard
signal of 625 lines
-
180
-
~s
June 1990
3-720
Philips Semiconductors Video Products
Preliminary specification
Sync separation circuit for video applications
TDA4820T
----------------------------1
V2"1
i
!
teli
--1 j'4-
V. I"· 7)
f,
. . ; j'4- tdH
---~1-~J
r--''--50-'' '---- ,..---..'1----------::
::
:.L
1
tllll-64~. - - - _ .
....' .... tpu... ...:
..
Fig.4 Typical horizontal sync signal.
,,
,
,,
i
f~-;:----Ve"*
'--tw-"!
t
~t~~
...,;vo;..c_Pl_·n_6_>-
___
_+_~_-II
(1) due to 625 line standard
Fig.5 Typical vertical sync signal.
June 1990
3-721
Preliminary specification
Philips Semiconductors Video Products
'Octuple 6-bit DAC with 12C-bus
GENERAL DESCRIPTION
The TDA8444/ATff comprises eight
digital-to-analog converters (DSCs), each
controlled via the two-wire 12C-bus. The
DACs are individually programmed using a
6-bit word to select an output from one of 64
voltage steps. The maximum output voltage
TDA8444/ATIT
of all DACs is set by the input Vmax and the
resolution is approximately Vma xl64. At
power-on all DAC outputs are set to their
lowest value. The 12C-bus slave receiver has
a 7-bit address of which 3 bits are
programmable via pins AO, A 1 and A2.
FEATURES
• Eight discrete DACs
• 12C-bus slave receiver
• 16-pin DIL package
16-pin SO package
20-pin SO package
QUICK REFERENCE DATA
SYMBOL
Vp
PARAMETER
MIN.
CONDITIONS
Supply voltage
TYP.
4.5
12.0
MAX.
13.2
UNIT
V
Icc
Supply current
no loads; Vmax = Vp; all data = 00
0
12
15
mA
Ptot
Total power dissipation
no loads; Vmax = Vp; all data = 00
-
150
-
mW
Vp= 12V
Vmax
Effective range of Vmax input
Vo
DAC output voltage range
VLS B
Step value of 1 LSB
V max = vp; 10 = -2mA
PACKAGE OUTLINES
TDA8444
16-lead DIL; plastic (SOT38)
TDA8444T 16-lead SO; plastic (SOT-162)
TDA8444AT 20-lead SO; (SOT-163)
June 1994
3-722
1
-
10.5
V
0.1
-
Vp-0.5
V
70
160
250
mV
Philips Semiconductors Video Products
Preliminary specification
Oetuple 6-bit DAC with 12C-bus
TDA8444/AT/T
AD
Al
Vp
A2
GND
SDA __~3~~____________________--'1
12C BUS
SCL
SLAVE RECEIVER
Vmax--+-2~------~
DACD
REFERENCE
VOLTAGE
GENERATOR
DACl
TDA8444
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
7Z94743
Fig.1 Block diagram.
PINNING
DAC7
2
Vp
positive supply voltage
V max
control input for DAC maximum
output voltage
12 C-bus serial data input/output
12 C-bus serial data clock
Vmax
2
15 DAC6
3
SDA
SDA
3
14 DAC5
4
SCL
DAC4
5
AO
DAC3
6
A1
7
A2
8
GND
ground
9-16
DACO-7
analogue voltage outputs
TDA8444
DAC2
Al
A2
7
GND
8
DACl
7Z94741
Fig.2 Pinning diagram.
June 1994
3-723
programmable address bits for
12 C- bus slave receiver
Philips Semiconductors Video Products
Preliminary specification
Octuple 6-bit DAC with 12C-bus
TDA8444/ATIT
BLOCK DIAGRAM - TDA8444AT (SO-20)
AD
SDA
-11--01----------------.1
SCL
-I~---------------.I
VMAX - - I I - - - - - - i . . t
DACO
A1
Vp
A2
12c.BUS
SLAVE RECEIVER
GND
TDA8444AT
REFERENCE
VOLTAGE
GENERATOR
DAC1
DAC2
DAC3
DAC4
DACS
DAC6
DAC7
PIN CONFIGURATION AND DESCRIPTION - TDA8444AT (SO-20, SOT-163)
DAC7
1
Vp
NC
2
VMAX
Control input tor DAC maximum output voltage
3
SDA
12C bus serial data input/output
4
SCL
7
AO
Programmable address bits for 12C bus slave receiver
8
A1
Programmable address bits tor 12C bus slave receiver
DAC1
9
A2
NC
10
GND
11,13·18,20
DACO·7
DAC6
DACS
Positive supply voltage
12C bus serial data clock
DAC4
DAC3
DAC2
GND
June 1994
3·724
Programmable address bits tor 12C bus slave receiver
Ground
Analog voltage outputs
Philips Semiconductors Video Products
Preliminary specification
Oetuple 6-bit DAC with 12C-bus
TDA8444/AT/T
BLOCK DIAGRAM - TDA8444T (SO-16)
AD
Vp
Al
GND
1----------------.1
SDA ---1..........
SCl
~f-----------------I
12c-BUS
SLAVE RECEIVER
TDA8444T
REFERENCE
VOLTAGE
GENERATOR
DACO
DACl
DAC2
DAC3
DAC4
DACS
DAC6
DAC7
PIN CONFIGURATION AND DESCRIPTION - TDA8444T (SO-16, SOT-162)
June 1994
1
Vp
2
V MAX
Control input for DAC maximum output voltage
3
SDA
12C bus serial data inpuVoutput
4
SCL
12C bus serial data clock
6
AO
Programmable address bits for 12C bus slave receiver
7
A1
Programmable address bits for 12C bus slave receiver
8
GND
9-16
DACO-7
3-725
Positive supply voltage
Ground
Analog voltage outputs
Philips Semiconductors Video Products
Preliminary specification
Octuple 6-bit DAC with 12C-bus
TDA8444/ATIT
FUNCTIONAL DESCRIPTION
12 C-bus
The TDA8444 12 C-bus interface isa receive-only slave. Data is accepted from the 12 C-bus in the
following format:
S 0 1 0 0 A2 A 1 AO 0 A 13 12 11 10 SD SC SB SA A X X D5 04 03 02 01 00 A P
1.- address byte
--..
I I +-
instruction byte --.
I I
4 - first data byte
--.
1
Where:
S
start condition
A2,.A 1, AO
P
stop condition
13,12,11,10
A
acknowledge
SO, SC, SB, SA
X
don't care
05, 04, D3, D2, D 1, DO
= programmable address
= instruction bits
= subaddress bits
= data bits
bits
Fig.3 Data form~3t.
Address byte
Valid addresses are 40, 42,44,46,48, 4A, 4C, 4E (hexadec), depending on the programming of bits
A2, A 1 and AO. With these addresses, up to eight TDA8444 ICs can be operated independently from
one 12C-bus. No other addresses are acknowledged by the TOA8444.
Instruction and data bytes
Valid instructions are 00 to OF and FO to F F (hexadec); the TDA8444 will not respond to other
instruction values.
Instructions 00 to OF cause auto-incrementing of the subaddress (bits SD to SA) when more than one
data byte is sent within one transmission. With auto-incrementing, the first data byte is written into the
DAC addressed by bits SO to SA and then the subaddress is automatically incremented by one position
for the next data byte inthe series.
Auto-incrementation does not occur with instructions FO to F F. Other than auto-incrementation
there is no difference between instructions 00 to OF and FO to FF. When only one data byte per
transmission is present, the DAO addressed by the subaddress will always receive the data.
Valid subaddresses (bits SO to SA) are 0 to 7 (hexadec) relating numerically to O.ACO to DAC7. When
the auto-incrementing function is used, the subaddress will sequence through all possible values
(0 to F, 0 to F, etc.).
12 C-bus
Input SCL (pin 3) and input/output SOA (pin 4) conform to 12 C-bus specifications. * Pins 3 and 4
are protected against positive voltage pulses by internal zener diodes .connected to the ground plane
and therefore the normal bus line voltage should not exceed 5.5 V.
The address inputs AO, A 1, A2 are programmed by a connection to GN D for An = 0 or to Vp for
An = 1. If the inputs are left floating, An = 1 will result.
June 1994
3-726
Philips Semiconductors Video Products
Preliminary specification
Octuple 6-bit DAC with 12C-bus
TDA84441ATIT
FUNCTIONAL DESCRIPTION (continued)
Input V max
I nput V max (pin 2) provides a means of compressing the output voltage swing of the DACs. The
maximum DAC output voltage is restricted to approximately V max while the 6-bit resolution is
maintained, so giving a finer voltage resolution of smaller output swings.
Digital-to-analogue converters
Each DAC comprises a 6-bit data latch, current switches and an output driver. Current sources with
values weighted by 2° up to 2 5 are switched according to the data input so that the sum of the
selected currents gives the required analogue voltage from the output driver. The range of the output
voltage is approximately 0.5 to 10.5 V when V max = Vp.
The DAC outputs are protected against short-circuits to Vp and GN D.
To avoid the possibility of oscillations, capacitive loading at the DAC outputs should not exceed 2 nF.
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
parameter
conditions
symbol
= V1
I
min.
I max.
I
unit
-0.5
18
V
-
-10
40
mA
mA
-0.5
5.9
V
VI
-0.5
Vp + 0.5
V
Vo
-0.5
Vp + 0.5
V
±I max
Ptot
-
10
mA
Total power dissipation
-
500
mW
Operating ambient
temperature range
Tamb
-20
+ 70
°C
-65
+ 150
°C
Supply voltage
Vp
Supply current (source)
I p = 11
Ip = II
-
V3,4
12C-bus line voltage
I I nput voltage
Output voltage
Maximum current on any pin
(except pins 1 and 8)
Storage temperatu re range
T stg
THERMAL RESISTANCE
From junction to ambient
Rth j-a
75 K/W
Purchase of Philips' 12 C components conveys a license under the
Philips' 12 C patent to use the components in the 12 C-system provided
the system conforms to the 12 C specifications defined by Philips.
June 1994
3-727
Philips Semiconductors Video Products
Preliminary specification
Octuple 6:-bit DAC with 12C-bus
TDA8444/AT/T
CHARACTERISTICS
All voltages are with respect to GND; T amb
= 25 oC;
Vp
= 12 V
unless otherwise specified
symbol
min.
typo
I max.
Supply voltage
Vp
4.5
12.0
13.2
V
Voltage level for
power-on reset
Vl
1
-
4.8
V
8
12
15
mA
-
150
-
mW
1.0
10.5
V
parameter
Supply current
Total power dissipation
Effective range of
V max input (pin 2)
I conditions
no loads; V max
all data = 00
= Vp;
no loads; V max
all data = 00
= Vp;
Ip
= 11
Ptet
unit
12
12
-
-
-
-
-10
10
flA
flA
I nput voltage range
VI
0
-
5.5
V
I nput voltage LOW
VIL
-
-
1.5
V
VIH
3.0
-
-
V
IlL
-
flA
-
-
-10
IIH
±10
flA
VOL
-
-
0.4
V
10
3
8
-
mA
Pin 2 current
= 12 V
V2 = 1 V
V2 = Vp
Vp
V max
= V2
SDA, SCL inputs
(pins 3 and 4)
Input voltage HIGH
Input current LOW
V3;4
Input current HIGH
V3;4
= 0.3 V
=6 V
SDA output
(pin 3)
Output voltage LOW
13
= 3 mA
Sink current
Address inputs
(pins 5 to 7)
I nput voltage range
VI
0
V
VIL
-
-
Vp
I nput voltage LOW
1
V
Input voltage HIGH
VIH
2.1
-
-
V
IIIL
-
-7
-12
flA
IIIH
-
-
1
flA
Input cu rrent LOW
Input current HIGH
June 1994
3-728
Philips Semiconductors Video Products
Preliminary specification
Octuple 6-bit DAC with 12C-bus
TDA8444/ATIT
CHARACTERISTICS (continued)
parameter
conditions
symbol
min.
typo
max.
Vo
0.1
-
Vp-0.5
V
VOmin
0.1
0.4
0.8
V
VO max
10
10.5
11.5
V
I unit
DAC outputs
(pins 9 to 16)
Output voltage range
Minimum output voltage
data = 00;
10 = .-2 mA
Maximum output voltage
data = 3F;
10 = -2 mA
at V max = Vp
at 1 50IlA
Rext
7000
~t--0 ~=
1 nF
,.k V (P-P)
_ _ _ _ _ _ _--' IIIILBr,.
Fig.11 Tuning circuit for extemal signal source.
April 1993
Pulses are used for:
• clamping
• video blanking
• HI2
• chrominance blanking
• burst pulse generation for adding to U, V
• pulses for the modulator offset control.
The value of the sawtooth generator output (current) is
determined by the value of a fixed resistor to ground
which is connected extemally at pin 21 (BURST AOJ).
When finer tolerance of the burst position is required, the
fixed resistor is connected in series with a variable
potentiometer to ground. By use of the potentiometer the
burst position at the outputs can be finely adjusted, after
which the pulse width of the burst and the position and
pulse width of all other intemal pulses are then
determined. When using a fixed resistor with a tolerance
of 2%, a tolerance of 10% of the burst position can be
expeCted. Timing diagrams of the pulses are provided by
Figs 12 and 13.
Hl2 at pin 4 is only necessary in the PAL mode when the
intemal Hl2 pulse requires locking with an extemal HI2
phase (two or more encoders locked in same phase).
The forcing of the internal Hl2 to a desired phase is
possible by means of an extemal pulse. ForCing is active
at HIGH level.
For the functioning of Pin 4 in the NTSC mode see also
section Black and Blanking levels in PAL and NTSC
modes.
3-747
~
2:
FIELD 2
I
623
622
~
FIELD 1
624
625
3
2
5
4
6
~
7
-t
I
i
I
&
en
o
sync input
[
no'"
1
31.
311
312
313
31.
315
31&
317
318
31.
32.
field 2 --...., ..--....----.---,..---.---..-..
CD
:::J
....
CD
field 1
field 2
H/2
field 3
field 4
Co)
~
co
blanking rield 1
R, G, B. Y. U. V
chrominonce
~ield 2
r1eld 1
blanking Gield 2
claRlJ Y
tuat
cloRlJ
rield 1
I .
~ield 2
. I
1___ I
~
CD
pield 1
-I
R, G, B, U, V Gield 2
o
MKA438
Fig.12 Sync separator and pulse shaper pulses.
~
~
~
-8
o....
i
01
~
g:
:l
~
....CD2.:
!:
.
-l
CD
W
sync Input
(pin 24)
~
C
z
·r
I
Pw
~td -
crlo
(1)
:l
290 no ±70 no
sync output
o
~
.a(I)
~lS'
~
~
OJ
8.
(pin 22)
.,
(1)
H/2
____--:-1_--'[
T
i
blanking
R. G. B. U. V and Y
w
td -
1100 no "00 no
td - 90 ns t10 ns
Pw - 9400 no >300 no
-----t'l.
~
~
co
11
chrominance
blanking
clamp Y
burst
___
--t'!I~--P-W---55-1-0-ns---~~-----------------+
:--
: td - 5600 ns t100 ns
adjust by resistor pin 21
-ll- Pw-
2380 ns
_-----In
ltd - 200 ns
clamp
R. G. B. U and V
!
1 . - . - - - - _
MKA439
~
as
~
01
I
o
Pw- 1480 ns
Fig.13 Sync separator and pulse shaper pulse timing levels,
i
-I
o
~
3i
2
g:::I
. Objective specification
PhiUps Semiconductors
PAUNTSC encoder
T.DA8501
PAUNTSC and YIY + SYNC
Pin 17 is used as a four level control pin to condition the YIY + SYNC input signal (via pin 5). Pin 17 is normally
connected to ground for PAL mode, or to Vet; for the NTSC mode. By use of external resistors (potential divider
connected to pin 17), the input blanking at pin 5 can be switched on and off. (see Table 1 and Fig 14).
Table 1 PALINTSC YIY + SYNC pin 5 options (pin 17 connection configurations).
PAL
NTSe
PAL
PIN 5 STATUS
Y without sync and input blanking on
Y without sync and input blanking on
Y with sync and input blanking off
NTSC
Y with sync and input blanking off
MODE
PIN 17 CONNECTION REQUIREMENT
pin 17 LOW, connected to Vsa
pin 17 HIGH, connected to Vet;
pin 17 with 39 kO connected to Vcc and 22 kQ
connected to Vsa
pin 17 with 22 kQ connected to Vet; and 39 kQ
connected to Vss
UMITING VALUES
In accordance with the Absolute Maximum System (IEC134): all voltages referenced to Vss (pin 10).
SYMBOL
PARAMETER
positive supply voltage
storage temperature
operating ambient temperature
Vet;
T.
TIIIIb
MIN.
MAX.
5.5
+150
+70
0
-65
-25
UNIT
V
°C
°C
THERMAL RESISTANCE
~
..
SYMBOL
THERMAL RESISTANCE
PARAMETER
from junction to ambient in free air
SOT234
SOT137
66KJW
75KJW
DC CHARACTERISTICS
Vet; 5 V: TIIIIb = 25 °C: all voltages referenced to ground (pin 10): unless otherwise specified.
=
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply (pin 8)
Vet;
let;
Pili!
V,.
April 1993
supply wllage
supply current
total power dissipation
reference voltage output (pin 13)
4.5
-
2.425
3-750
5.0
40
200
2.5
5.5
-
2.575
V
mA
mW
V
Philips Semiconductors
Objective specification
PALJNTSC encoder
TDA8501
AC CHARACTERlsncs
vcc = 5 v; T1mb = 25 °C; composite sync signal connected to pin 24; unless otherwise specified.
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
UNIT
MAX.
Encoder circuit
Input stage (pins 1. 3. 5. 7. 9 and 11); black level = clamping level
maximum signal
from black level positive
Vn(1IIIX)
from black level negative
only pins 1. 3 and 5
Vn(rrIIn)
Input bias current
Ibial
VI=V"
input voltage clamped
input capacitor
VI
connected to ground
input clamping impedance
IZtI
'1=1 mA
10= 1 mA
G
matrix and gain tolerance of R. G
and B Signals
gain tolerance of Y....(R-Yl and
-(8-Y)
.
;..
-
1.2
0.9
-
V
V
-
V
~
tbf
V"
<1
tbf
-
80
80
-
n
n
<5
%
-
-
-
-
-
<5
%
0
-
0.4
V
1
-
5
V
MCONTROL (pin 2; note 1)
VL
Vtt
'I
t.w
LOW level input voltage
V. -(R-Y) and -(8-Y)
HIGH level input voltage
R.GandB
input current
switching time
.
-
-
-3
~
50
-
ns
2.5
-
V
nA
V
V
U modulator offset control (pin 6)
Va
lu
VLL
V...
DC voltage control level
input leakage current
limited level voltage LOW
limited level voltage HIGH
-
-
-
1.8
3.2
-
2.5
-
-
100 .
-
Y modulator offset control (pin 12)
V'2
lu
VLL
Y...
DC voltage control level
input leakage current
limited level voltage LOW
limited level voltage HIGH
-
1.8
3.2
-
V
nA
V
V
-
-
<25
n
-
~
-
~
V
100
Y + SYNC (pin 22 out to delay circuit)
Ro
I....
IIOIRe
Va.
April 1993
output resistance
maxit:num sink current
maximum source current
black level. output voltage
350
1000
3-751
-
2.5
-
Philips Semiconductors
Objective speCification
PAUNTSC encoder
SYMBOL
TDA8501
PARAMETER
CONDITIONS
PAL mode; pin 17 =OV
sync voltage amplitude
VSVNC
Y voltage amplitude
Vy
VDF
difference between black and
blanking level
NTSC mode; pin 17 = 5 V and pin 4 open-circuit or ground
VS'{NC
sync voltage amplitude
Vy
Y voltage amplitude
VDF
difference between black and
blanking level
BW
frequency response
pin 22 with extemal
load of R = 10 kO and
C= 10pF
group delay tolerance
sync delay from pin 24 to pin 22
\,
Y delay from pin 5 to pin 22
\,
a
Chrominance cross talk
OdB = 1330 mV
(peak-to-peak)
= 75% RED
MIN.
285
665
MAX.
TYP.
-
300
700
0
270
628
286
661
-
.53
10
-
-
-
220
290
10
315
735
300
694
-
mV
mV
mV
mV
mV
mV
MHz
~O
ns
ns
ns
dB
-
1
1
V
120
-
-
-
input bias current
I~
maximum voltage amplitude
VI
Y + SYNC OUT (pin 19 output Y (SVHS); note 2)
-
BW
output resistance
maximum sink current
maximum source current
black level output voltage
Y + SYNC gain;
from pin 20 to pin 19
frequency response
a
group delay tolerance
Chrominance crosstalk
20
360
UNIT
-
Y + SYNC IN (pin 20 from delay circuit; note 2)
Ro
llink
IIIOWQI
Va.
G
I·
pin 19 withextemal
load of R = 10 kO and
C= 10pF
OdB=133OmV
(peak-to-peak)
=75% RED
650
1000
-
-
-
1.65
12
10
-
-
J1A
CI)
-
-
J1A
J1A
-
V
dB
-
-
MHz
-
20
-54
ns
dB
-
-
Notes
1. The threshold level of this pin is 700 mV ±20 mY. The specification of the HIGH and LOW levels is according to
the SCART fast blanking.
2. Pin 20 condition: black level of input signal must be 2.5 V; amplitude 0.5 V (peak-to-peak) nominal.
April 1993
3-752
Philips .Semiconductors
Objective specification
PAUNTSC encoder
TDA8501
AC CHARACTERlsncs (continued)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTCH (pIn 18)
Ro
Voo
I_
output resistance
DC voltage level
maximum sink current
1750
-
2000
2.5
2500
350
-
-
700
1000
-
-
n
V
JlA
Chromlnance output (pin 14)
maximum sink current
maximum source current
1output
resistance
Ro
variation
of DC voltage level
INoc
when chrominance signal is
blanked and chrominance signal is
not blanked
PAL mode; pin 17 = 0 V
chrominance output voltage
Vo
(peak-to-peak) amplitude burst
ratio: chrominance
(75% RED)lburst
NTSC mode; pin 17 = 5 V
chrominance output voltage
Vo
(peak-to-peak) amplitude burst
ratio: chrominance
(75% RED)lburst
carrier suppression when
OdB=1330mV
(peak-to-peak)
input-signals are 0 V
phase accuracy (difference
between 0 and 90 degree carriers)
.Low-pass filters
LPF
see Figs 3 and 4
see Figs 5 .and 6
Band-pass filters
BPF
noise
level
(RMS
value)
Vn
burst pt)ase; 0 degrees = phase U carrier
BP
PAl mode
NTSCmode
Y + SYNC cross talk
OdB = 1400 mV
ex
(0 to 6 MHz)
.
(peak-to-peak)
'link
.'
April 1993
3-753
-
-
480
-
~
~
-
n
5
mV
600
720
mV
2.1
2.2
2.3
460
570
680
2.1
2.2
2.3
-
37
-
dB
-
2
degrees
-
-
4
mV
-
±135
180
-
-
-60
degrees
degrees
dB
-
120
-
mV
Philips SemiconductOrs
Objective specification
PAUNTSC encoder
PARAMETER
SYMBOL
TDA8501
CONDITIONS
MAX. '
TYP.
MIN.
UNIT
CVBS output (pin 16)
I....
IIOII'CI
Vo
G
G
G.
Gv
Ro
maximum sink current
maximum source current
DC voltage level
Y + SYNC gain;
from pin 20 to pin 16
chrominance difference;
from pin 14 to pin 16
differential phase
differential gain
output resistance
Y+SYNC=O
note 1
note 2
650
1000
-
-
-
1.6
12
-
~
V
dB
-
0
-
dB
-
-
3
3
degrees
dB
-
n
-
120
-
~
Oscillator output (pin 23)
OSC
series-resonance
the resonance resistanc.e of th.e crystal should be < 60 n and the
parallel capacitance of the crystal should be < 10 pF.
Filter tuning loop (pin 15)
Voc
Voc
VDCl
VDCH
H2 (pin 4)
DC control voltage level NTSC
DC control voltage level PAL
limited DC-level LOW
limited DC-level HIGH
VL
LOW level input voltage
HIGH level input voltage
current for forcing HIGH
current for forcing LOW
voltage out LOW
V..
II
'10
Vo
Vo
II/nk
IIOWCe
-
10=200~
11=2oo~
inactive
active
-
0
4
220
260
-
voltage out HIGH
maximum sink current
maximum source current
4
50
'50
0.83
0.88
0.27
1.8
-
-
-
-
V
V
V
V
1
5
V
V
-
~
<0.5
~
V
V
-
-
-
~
~
Composite sync Input (pin 24)
Vsvw;
II
10
SYNC pulse amplitude
slicing Iavet
input current
maximum output current during
SYNC
75
300
600
-
50
-
~
~
-
V
4
100
mV(p-p)
%
BURST ADJ (pin 21; note 3)
BP
April 1993
-
DC voltage level
3-754
VREF
(V13)
Philips Semiconductors
Objective specification
PAUNTSC encoder
PARAMETER
SYMBOL
TDA8501
MIN.
CONDITIONS
TYP.
MAX.
UNIT
Control pin PAUNTSC and YIY + SYNC (pin 17; note 4)
VI
VI
VI
VI
lbill
PAL mode and blanking pin 5
active
internal sync added to Y
PAL mode and blanking pin 5
inactive
internal sync not added to Y
NTSC mode and blanking pin 5
active
internal sync added to Y
NTSC mode and blanking pin 5
inactive
internal sync not added to Y
input bias current
0
-
1
V
1.6
-
2.0
V
4
-
5
V
3
-
3.4
V
-
-
-10
J&A
Note.
1. Definition:
maximum phase - minimum phase = difference phase
maximum gain - minimum gain x 100= difference gain %
maximum gain
3. The output impedance of this pin is low « 100 Q). The nominal value of the external resistor is 196 kn (see also
section Sync separator and Pulse shaper).
4. The threshold levels are: 0.25 times Vee. 0.5 times Vee and 0.75 times Vee'
2. Definition:
April 1993
3-755
Philips Semiconductors
Objective specification
PAUNTSC encoder
TDA8501
Table 2 Internal circuitry. .
PIN
NAME
DESCRIPnQN
CIRCUIT
1
-(R-V)
-(R-Y) input; connected via
47 nF capacitor
1.05 V (p-p) for EBU bar of 75%
see also pins 3,5,7,9 and 11
2
MCONTROL
multiplexer switch control input
< 0.4 V Y, U and V
> 1 VR, GandB
i
25 IJA
2
MKA441
3
-(B-Y)
4
HI2
IN/OUT
see pin 1
4
April 1993
-(B-Y) input; connected via
47 nF capacitor
1.33 V (p-p) for EBU bar of 75%
HI2 input
PAL MODE:
pin open, output of internal Hl2
Forcing possibility
NTSCmode:
OV set-up
5V no set-up
275 0
3-756
Philips Semiconductors
Objective specification
PAUNTSC encoder
PIN
TDA8501
NAME
5
Y
6
UOFFSET
DESCRIPTION
CIRCUIT
Y input; connected via 47 nF
capacitor '
1 V (p-p) for EBU bar of 75%
see pin 1
220 nF (low-leakage)
connected to ground
see also pin 12
I
I
2.5 V
7
R
--
8 IJA
--
MKA443
RED input; connected via 47 nF
capacitor
0.7 V (p-p) for EBU bar of 75%
see pin 1
supply voltage
5Vnominal
8
-r~supply
8'""l~
MKA444
9
G
10
Vss
see pin 1
GREEN input; connected via
47 nF capacitor
0.7 V (p-p) for EBU bar of 75%
ground
substrate
10~
11
April 1993
B
--
ground
MKA445
see pin 1
3-757
BLUE input; connected via
47 nF capacitor
0.7 V (p-p) for EBU bar of 75%
Philips Semiconductors
Objective specification
PAUNTSC encoder
PIN
TDA8501
NAME
12
VOFFSET
13
V,.
CIRCUIT
DESCRIPTION
see pin 6
220 nF (low-leakage) connected
to ground
2.5 V reference voltage
decoupling with 47 JlF and 22 nF
capacitors
2.5 V
13
14
CHROMA
chrominance output; together
with pin 19 the Y + C (SVHS)
output
14
15
filter control pin
220 nF capacitor to ground
FLT
15
April 1993
3-758
Philips Semiconductors
Objective specification
PAUNTSC encoder
PIN
16
TDA8501
NAME
DESCRIPTION
CIRCUIT
cves
cves output
16
3 kO
MKA449
17
4-level control pin
Pin 5:
PAUNTSC
YN+SYNC
OV PAL, Y
1.8 V PAL Y + SYNC
3.2 V NTSC Y + SYNC
5VNTSCY
18
April 1993
pin for external notch filter
NOTCH
3-759
Philips Semiconductors
Objective specific;:ation
PAUNTSC encoder
PIN
19
TDA8501
NAME
DESCRIPTION
CIRCUIT
output of the Y + SYNC signal;
together with pin 14 the Y + C
(SVHS) output
Y + SYNCOUT
19
9 kO
2.5 V
20
MKA452
input of the delayed Y + SYNC
signal of the delay line
black level must be 2.5 V
Y + SYNC IN
20
21
external resistor to ground for
adjusting the position of the burst
BURSTADJ
21
MKA454
April 1993
3-760
Philips Semiconductors
Objective specification
PAUNTSC encoder
PIN
NAME
22
Y + SYNC OUT
TDA8501
CIRCUIT
OESCRIPnON
output of the Y + SYNC signal.
connected to the delay line via a
resistor
22
23
subcarrier-crystal in series with a
trimmer. or an extemal
subcarriersignal. via 1 nF in
series with a resistor
OSC
23
24
composite SYNC signal input
amplitude < 600 mV (p-p)
CS
24
April 1993
3-761
~
-
~
2:
ccoo
C
Z
CAl
-I
en
0
+5V ••
SYNC
Input
C11~
Input
75 0
•
22nF
C11S
C100
I
C101
t
I
I
47nF
Cf
-..J
REO
Input
GREEN
Input
C105
t~
IIR108 ',. 47nF
750
I I ...
47pF
22
21
C102
luminance
Input
0
Co
CD
~
23
47nF
0)
I\)
C1!;4
~
47nF
-(8-V)
:::J
0
~ 3.58 MHz (NTSC mode)
.~
I
R100
• 47nF
-(R-V)
Input
CD
U100 signallOUICI
~ 4.43 MHz (Pal mode)
C1r;1H~~
220nF
H 22nF
20
TOA8501
19~
,no
18
17
R105
C106
t~1
R110' . 47nF
16
,
BlUE
input
750
C110
'~I
R113
• 47nF
R~11
1 kSl
1.2 kSl
750
R115
1.2 kSl
R104
CV8S
+------c::J-+-0UIpUt ,
680
9.
CD
IIS4.s
-I
C
»
CD
FIQ.14 Application diagram.
0'1
o
...a.
t
.lJ
"~
S
g:J
Philips Semiconductors Video Products
4
X
Product specification
TDA8540
4 video switch matrix
FEATURES
APPLICATIONS
• 12C-bus or the non-I2C-bus mode (controlled by DC
voltages)
• Peritelevision sets
• Slave receiver in the 12C mode
• Satellite receivers.
• CTV receivers
• S-VHS or CVBS processing
• 3-state switches for all channels
GENERAL DESCRIPTION
• Selectable gain for the video channels
The. TDA8540 has been deSigned primarily for switching
between composite video signals. Consequently, a
minimum of four input lines has been provided as
required for switching between two S-VHS sources.
Each of the four outputs can be set to a high impedance
state, permitting parallel connection to several devices.
• sub-address facility
• Auxiliary logic outputs for audio switching
• System expansion possible up to 7 devices
(28 sources)
• Static short-circuit proof outputs
• ESD protection.
QUICK REFERENCE DATA
SYMBOL
Vee
PARAMETER
TYP.
MIN.
-
7.2
MAX.
8.8
UNIT
V
-
20
30
mA
60
80
dB
3 dB bandwidth
12
-
-
crosstalk attenuation
between channels
60
70
-
dB
Icc
supply cun:ent
Iso
B
isolation "OFF" state
(l
CONDITIONS
supply voltage
at f = 5 MHz
MHz
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
PACKAGE
PINS
PIN POSITION
TDA8540
20
TDA8540T
20
April 1993
MATERIAL
CODE
DIL
plastic
SOT146E
SO
plastic
SOT163A
3-763
Product specification
Philips Semiconductors
4
X
4 video switch matrix
TDA8540
15
4
IN3
OUT3
IN2
OUT2
IN1
OUT1
INO
OUTO
Vee
DGND
AGND
r-~----~----~----~--~-----------'----~~D1
t----+-t-- DO
SO
S1
S2
SCl
SDA
Fig.1 Block diagram.
April 1993
3-764
Product specification
Philips Semiconductors
4
X
TDA8540
4 video switch matrix
PINNING
DESCRIPTION
SYMBOL
PIN
OUT2
1
video output 2
control output
DO
2
OUT3
3
video output 3
V023
4
driver supply
S2
5
sub-address input 2
INO
6
video input (CVBS or chrominance
signal)
SOA
SCL
Sl
7
sub-address input 1
INl
8
video input (CVBS or chrominance
signal)
AGND
9
analog ground
V001
IN2
10
video input (CVBS or luminance
signal)
OUT1
SO
11
sub-address input 0
IN3
12
video input (CVBS or luminance
signal)
Vee
OUTl
13
positive supply voltage
14
video output 1
driver supply
VOO1
15
OUTO
16
video output 0
01
17
control output
SCL
18
serial clock input
SDA
19
serial data input/output
DGND
20
digital ground
April 1993
01
OUTO
vee
IN2
ULA2T7-1
Fig.2 Pinning configuration.
3-765
Philips Semiconductors
Product specification
4 X 4 video switch matrix
TDA8540
FUNCTIONAL DESCRIPTION
The TDA8540 is controlled via a bi-directionaI1 2C-bus.
3-bits of the 12C address can be selected via sub-address
input pins, thus providing a facility for parallel operation
of 7 devices.
Control options via the 12C-bus:
• the input signals can be clamped at their negative
peak (top sync).
• the gain factor of the outputs can be selected
between 1x or 2x.
• each of the four outputs can be individually connected
to one of the four inputs.
• each output can be individually set in a high
impedance state.
• two binary output data lines can be controlled for
switching accompanying sound signals.
The SDAand SCL pins (pins 19 and 18) can be
connected to the 12C-bus or to DC switching voltage
sources. Address inputs SO to S2 (pins 11, 7 and 5) are
used to select sub-addresses for switching to the non-12C
mode. Inputs SO, Sl and S2 can be connected to the
supply voltage (HIGH) or the ground (LOW). In this way
no peripheral components are required for selection.
Table 1 12C-bus sub-addressing.
52
51
sub-address
50
A1
AO
L
L
L
0
0
0
L
L
H
0
0
1
L
H
L
0
1
0
L
H
H
0
1
1
H
L
L
1
0
0
H
H
H
L
H
1
0
1
H
L
1
1
0
H
H
non 12C addressable
April 1993
A2
3-766
Product specification
Philips Semiconductors
4
X
TDA8540
4 video switch matrix
12C-bus control
After power-up the outputs are initialized in the high impedance state, and DO, 01 are at a low level.
Detailed information on 12C-bus is available on request.
The TDA8540 is a SLAVE RECEIVER with the following protocol:
I
I
S
I
SLV
A
I
SUB
I
A
I
DATA
A
DATA
A
P
Where:
S
start condition
A
acknowledge bit (generated by TDA8540)
P
stop condition.
Data transmission to the TDA8540 begins with the following slave address (SLV):
I
MSB
AO
Where:
A6 = 1, AS = 0, A4 = 0, A3
=1
A2, A 1, AO : pin programmable address bits
RIW
=0 (write only)
Where:
if SUB
= OOH
if SUB
= 01 H
: access to gain/clamp/data control (GCO)
if SUB
= 02H
: access to output enable control (OEN)
: access to switch control (SW1)
After the slave address, a second byte, SUB, is required for selecting the functions:
I
MSB
RS1
Note
If more than one data byte is sent, the SUB byte will be automatically incremented
If more than 3 data bytes are sent, the internal counter will roll over and the device will then rewrite the first register.
April 1993
3-767
. Product specification
Philips Semiconductors
4
X
TDA8540
4 video switch matrix
DATA BYTES
-
SWI (SUB = OOH)
SWI (SUB = OOH) determines which input is connected to the different outputs:
MSB
IsWI:
831
For J
lSB
830
S21
S20
810
S01
SOO
CL1
CLO
D1
DO
II
=0 to 3:
Example: if S21 = 0 and S20 = 1, then OUT2 is connected to
IN~.
-
GCO (SUB = 01 H)
-
selects the gain of each output
-
selects the clamp action or mean value on inputs 0 and 1
-
determines the value of the auxiliary outputs D1 and DO
IGCO:
-
S11
I MS~
lSB
G2
G1
GO
II
for j = 0 to 3 : if Gj = 0 (resp 1), then output j has a gain of 2 (resp 1)
-
if CLO (resp CL1) = 0, then input signal on INO (resp IN 1) is clamped
-
for j = 0.1 : if Dj = 0 (resp 1), then logical output j is LOW (resp HIGH).
OEN (SUB = 02H) determines which output is active or high impedance:
IOEN:
I MS~
lSB
X
X
X
EN3
EN2
EN1
ENO
II
- for j = 0 to 3 : if ENj = 0 (resp 1), then OUT J is HIGHZ (resp ACTIVE).
After a power-on reset: the outputs are set to a high impedance state; the outputs are connected to INO; the gains are
set at two and inputs INO and IN1 are clamped.
After a power-on reset, the programming of the device is required by the outputs being in a high impedance state.
April 1993
3-768
Product specification
Philips Semiconductors
4
X
TDA8540
4 video switch matrix
Non-I2C-bus Control
If the SO, Sl and S2 pins are all tied to Vee the device will then enter the non-l2C mode.
-
After a power-on reset:
-
gain is set at two for all outputs
-
all inputs are clamped
-
all outputs are active
-
the matrix position is given by SOA and SCl voltage level..
Table 2 Non FC-bus Control.
sel-SOA
0.0
0.1
1.0
1.1
aUT3
IN3
IN2
IN1
INO
aUT2
IN2
IN3
INO
IN1
aUTl
INl
INO
IN3
IN2
aUTO
INO
IN1
IN2
IN3
~
SCl and SOA act as normal input pins:
-
SCl interchanges (aUT3 and aUT2) with (aUTl and aUTO).
-
SOA interchanges aUT3 with aUT2; aUTl with aUTO.
Note:
For use with chrominance signals, the clamp action must be overruled by external
bias.
:~~ or_+-_+-----_ _--t
TOA8540
ULA282
Fig.3 INO and IN1 inputs.
April 1993
3-769
Product specification
Philips Semiconductors
4
X
TDA8540
4 video switch matrix
TDA8540
-~-.......- - t - - 6 V
IN20r
IN3 --t--~--I
..---+--'---Ir--
OUTO (OUT2)
~--f--
OUT1 (OUT3)
AfLA280
AfLAZSI
Fig.4 IN2 and IN3 inputs.
April 1993
Fig.S Driver output stage.
3-770
Product specification
Philips Semiconductors
4
X
TDA8540
4 video switch matrix
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134).
-0.3
supply voltage
total power dissipation
PlOt
Tstg
Tj
MIN.
PARAMETER
SYMBOL
Vee
MAX.
UNIT
9.1
V
-
750
mW
storage temperature
maximum junction temperature
-55
+125
°C
-
V001 ' V023
INO to IN3
OUTOtoOUT3
driver supply input voltage
-0.3
+150
13.8
°C
V
video input voltage
-0.3
-0.3
7.2
V
video output voltage
7.2
V
00,01
control output voltage
-0.3
7.2
V
SOA, SOL
FC input/output voltage
-0.3
8.8
V
SO to S2
sub-address input voltage
-0.3
8.8
V
Handling
HUMAN BODY MoDEL
The IC withstands 1500 V in accordance with UZW-BQ..FQ..A303.
MACHINE MODEL
The IC withstands 200 V in accordance with UZW-BO-FQ-B303 (stress reference pins: AGNO - GNOO short-circuit
and Vee>.
THERMAL RESISTANCE
SYMBOL
R1hj-a
April 1993
PARAMETER
THERMAL RESISTANCE
from junction to ambient in free air
SOT146
60KlW
SOT163A
85K1W
3-771
Product specification
Philips SemiconduCtors
4 x 4 video switch matrix
TDA8540
OPERATING CHARACTERISTICS
CONDITIONS
PARAMETER
SYMBOL
"
Vee
supply voltage
Tanb
operating ambient temperature
TYP.
MIN.
MAX.
UNIT
7.2
0
-
8.8
V
70
DC
-
100
-
nF
-
1
V
1.5
V
-
25
22
-
a
4
0
-
Vee
V
1
V
Video Inputs (pins 6, 8, 10 and 12)
CI
VI
external capacitor
C signal amplitude (peak-to-peak value)
note 1
VI
CVBS or V-signal amplitude
(peak-to-peak value)
note 2
Video drivers (pins 4 and 15)
Ro
external collector resistor
note 3
Co
external decoupling capacitor
note 4
J.LF
sub-address SO, S1 and S2 (pins 5, 7 and 11)
VIH
VIL
HIGH level input voltage
LOW level input voltage
Notes to the Operating Characteristics:
1. Only for pins 6 and 8 when clamp action is not selected for these pins.
2. On all the video input pins when non-J2C:-bus control mode is selected or when clamp action is selected on pins 6
and 8 (by 12C-bus control).
3. Connected between Vee and pin 4 or pin 15.
4. Connected between AGRND and pin 4 or pin 15.
April 1993
3-772
Product specification
Philips Semiconductors
4
X
TDA8540
4 video switch matrix
CHARACTERISTICS
Vcc = 8 V; TMlb = 25°C; gain condition, clamp condition and OFF state are controlled by the FC bus unless otherwise
specified.
CONDITIONS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply
Icc
supply current
without load
OFF state
-
20
30
12
-
rnA
rnA
0.4
1
rnA
2.2
-
V
Video inputs: INO to IN3 when the clamp is active (see Figs 3 and 4)
lu
input leakage current
V,=3V
Vdall1()
IdMlp
input clamping voltage
1,=5~
-
nput clamping current
V,=OV
1.2
-
-
rnA
-
2.9
-
k.Q
Video inputs: INO and IN2 when the clamp is not active (see Fig.3)
V~as
DC input bias level
R,
input resistance
I, =0
10
V
Video outputs: OUTO to OUT3 (see Fig.S)
100
-
-
5
-
n
60
-
-
dB
0.4
0.7
1
V
G = 2, load = 150 Q
1.5
1.9
2.2
V
G = 1, without load
1
1.3
1.6
V
0
+1
dB
+6
+7
dB
0.5
3
%
20
output impedance
Ro
output resistance
ISO
isolation
Vo
output top sync level
(Yor CVBS)
V~as
output mean value for chrominance
signals
voltage gain
G = 1; f = 1 MHz
-1
G = 2 f = 1 MHz
+5
note 1
-
~
OFF state
OFF state
f = 5 MHz
k.Q
Gdiff
differential gain
Cj)diff
differential phase
note 1
-
0.6
-
deg
NL
non linearity
note 2
-
0.5
2
%
a
crosstalk attenuation between channels
note 3
60
70
-
dB
SVRR
supply voltage rejection
note 4
36
55
-
dB
~G
maximum gain variation
100 kHz < f < 5 MHz
-
0.5
100 kHz < f < 8.5 MHz
-
1
-
dB
100 kHz < f < 12 MHz
-
3
-
dB
60
-
-
dB
-
-
10
rnA
-
-
0.4
V
al 2C
crosstalk attenuation of bus signals
dB
Auxiliary outputs DO, 01 (open collector)
10H
HIGH level output current
VOL
LOW level output voltage
April 1993
VoH =5.5V
10L =4 rnA
3~773
Product specification
Philips Semiconductors
4
X
4 video switch matrix
SYMBOL
TDA8540
PARAMETER
MIN.
CONDITIONS
TYP.
MAX.
UNIT
l2C-bus inputs SCL, SDA
I'H
IlL
H.IGH level input current
C,
input capacitance
"
LOW level input current
V'H = 3.0 V
-
V'L = 1.5 V
-10
-
J1A
J1A
-
-
10
·pF
IOL=3mA,
-
-
OA
V
V'H = Vee
VIL = 0 V
-
-
10
l1A
-
10
J1A
10
l2C-bus output SDA
VOL
LOW level output voltage
sub-address SO, S1 and S2
I'H
IlL
HIGH level input current
LOW level input current
Notes to the Characteristics:
1. Gain set at two, RL
= 150 n, test signal D2 from CCIR 330.
2. Gain set at two, RL = 150 n, test signal D1 from CCIR 17.
3. Measured from any selected input to output; f = 5 MHz, RL
= 150 n, gain set at 2, VI = 1.5 V (p-p).
This measurement requires an optimized board.
4. Supply voltage ripple rejection: 20 log
~I(SUpply) measured at f = 1 kHz with V r(supply max) = 100 mV (p-p).
I(OUIpIII)
The supply voltage rejection r~tio is higher than 36 dB at fmax = 100kHz.
April 1993
3·774
Philips Semiconductors
4
X
Product specification
4 video switch matrix
TDA8540
250
250
Vee
Vee
+
100
Cj
100 nF
-+-I
+
JIF ~
F
;J;.• 22!1
Co
V023
IN3
AO
4
V001
15
12
3
OUT3
Cj
100 nF
-+-I
video
sources
IN2
outputs
10
14
C,
100 nF
-+-I
Ci
100 nF
-+-I
IN1
INO
8
16
TDA8540
10
6
k.Q
17
VCC
13
2
20
VCC - analog
supply
(+8 V)
9
11
5
18
01
}
00
19
ULA278·2
address
inputs
serial data
and
clock signals
Fig.6 Application diagram.
April 1993
digital
supply
(+5 V)
3-775
audio
source
control
Philips Semiconductors Video Products
Product specification
8-bit video digital-to-analog converter
TDA8702
FEATURES
APPLICATIONS
• 8-bit resolution
• High-speed digital-to-analog conversion
• Conversion rate up to 30 MHz
• Digital TV including:
• TTL input levels
- field progressive scan
• Internal reference voltage generator
-line progressive scan
o
Two complementary analog voltage outputs
• Subscriber TV decoders
• No deglitching circuit required
• Satellite TV decoders
• Internal input register
• Digital VCRs.
• low power dissipation
• Internal 75 n output load (connected to the analog
supply)
DESCRIPTION
The TDA8702 is an 8-bit digital-to-analog converter
(DAC) for video and other applications. It converts the
digital input signal into an analog voltage output at a
maximum conversion rate of 30 MHz. No external
reference voltage is required and all digital inputs are
TTL compatible.
• Very few external components required.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
5.5
V
32
mA
-
23
30
mA
ZL=10kn
-1.45
-1.60
-1.75
V
ZL = 75 kn
-0.72
-0.80
-0.88
V
note 1
ICCD
VOUT
digital supply current
note 1
full-scale analog output voltage
(peak-to-peak value)
note 2
digital supply voltage
5.0
4.5
-
UNIT
26
analog supply current
4.5
MAX.
5.0
ICCA
VOUT
TYP.
V
analog supply voltage
-
MIN.
5.5
VCCA
VCCD
IlE
DC integral linearity error
-
-
±1/2
lSB
-
-
±1/2
lSB
-
-
30
MHz
-
150
-
MHz
-
250
340
mW
OLE
DC differential linearity error
fCLK
B
maximum conversion rate
-3 dB analog bandwidth
PlOt
total power dissipation
fCLK = 30 MHz;
note 3
Notes
1. DO to 07 connected to VCCD and ClK connected to DGND.
2. The analog output voltages (VOUT and ~) are negative with respect to VCCA (see Table 1). The output resistance
between VCCA and each of these outputs is typically 75 n.
3. The -3 dB analog output bandwidth is determined by real time analysis of the output transient at a maximum input
code transition (code 0 to 255).
April 1993
3-776
Product specification
Philips Semiconductors
TDA8702
8-bit video digital-to-analog converter
ORDERING INFORMATION
PACKAGE
EXTENDED TYPE
NUMBER
PINS
PIN POSITION
MATERIAL
CODE
TDA8702
16
DIL
plastic
SOT38
TDA8702T
16
S016
plastic
SOT162A
REF
100nF
I
16
OGND
AGNO
75
n
75
n
15
CLK
VCCA
14
VOUT
VOUT
TDA8702/
TDA8702T
(LSB) 00
01
02
03
04
05
06
(MSB) 07
12
11
3
4
10
9
8
13
OATA
INPUT
INTERFACE
7
MSA659
Fig.1 Block diagram.
April 1993
3-777
VCCD
Philips Semiconductors
Product specification
8-bit video digital-to-analog converter
TDA8702
PINNING
DESCRIPTION
SYMBOL PIN
REF
1
voltage reference (decoupling)
AGND
2
analog ground
02
3
data input; bit 2
03
4
data input; bit 3
elK
5
clock input
vOUT
OGND
6
digital ground
VCCD
DO
07
7
data input; bit 7
06
8
data input; bit 6
05
9
data input; bit 5
04
10
data input; bit 4
01
11
data input; bit 1
00
12
data input; bit 0
VCCD
13
positive supply voltage for digital
circuits (+5 V)
VOUT
14
analog voltage output
'lOUT
15
complementary analog voltage output
VCCA
16
positive supply voltage for analog
circuits (+5 V)
April 1993
VCCA
V OUT
D4
MSA658
Fig.2 Pin configuration.
3-778
Product specification
Philips Semiconductors
8-bit video digital-to-analog converter
TDA8702
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
-0.3
analog supply voltage
MAX.
+7.0
UNIT
V
V
V
V
V
VCCA
VCCD
VCCA - VCCD
digital supply voltage
-0.3
+7.0
supply voltage differential
-0.5
+0.5
AGND-DGND
ground voltage differential
-0.1
+0.1
VI
input voltage (pins 3 to 5 and 7 to 12)
-0.3
VCCD
Iou/loUT
Tstg
total output current (pins 14 and 15)
-5
+26
rnA
storage temperature
-55
+150
°C
Tamb
Tj
operating ambienttemperature
0
+70
°C
junction temperature
-
+125
°C
THERMAL RESISTANCE
PARAMETER
SYMBOL
Rth j-a
THERMAL RESISTANCE
from junction to ambient in free air
SOT38
70 Kffl
SOT162A
90 Kffl
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
April 1993
3-779
Philips Semiconductors
Product specification
8-bit video digital-to-analog converter
TDA8702
CHARACTERISTICS
VCCA = V 16 - V2 = 4.5 V to 5.5 V; V CCD = V 13 - V6 = 4.5 V to 5.5 V; VCCA - V CCD = -0.5 V to +0.5 V; V REF decoupled to
AGND by a 100 nF capacitor; T amb = 0 °C to +70 °C; AGND and DGND shorted together; unless otherwise specified
(typical values measured at VCCA = VCCD = 5 V and Tamb = 25 °C).
SYMBOL
PARAMETER
MIN.
CONDITIONS
TYP.
MAX.
UNIT
Supply
VCCA
V CCD
analog supply voltage
4.5
5.0
5.5
V
digital supply voltage
4.5
5.0
5.5
V
ICCA
analog supply current
note 1
-
26
32
rnA
note 1
-
23
30
rnA
-0.1
-
+0.1
V
digital supply current
ICCD
AGND-DGND ground voltage differential
Inputs
DIGITAL INPUTS (07 TO DO) AND CLOCK INPUT (ClK)
V IL
lOW level input voltage
0
-
0.8
V
V IH
HIGH level input voltage
2.0
-
VCCD
V
IlL
lOW level input current
VI = 0.4 V
-
-0.3
-0.4
rnA
IIH
HIGH level input current
VI =2.7 V
-
0.01
20
JlA
fCLK
maximum clock frequency
-
-
30
MHz
ZL=10kQ
-1.45
-1.60
-1.75.
V
ZL = 75 Q
-0.72
-0.80
-0.88
V
code =0
-
-3
-25
mV
Outputs (note 2; referenced to V CCA)
V OUT - V OUT
full-scale analog output voltages
(peak-to-peak value)
Vos
analog offset output voltage
Vou/TC
full-scale analog output voltage
temperature coefficient
-
-
200
JlV/K
VodTC
analog offset output voltage
temperature coefficient
-
-
20
JlV/K
B
-3 dB analog bandwidth
-
150
-
MHz
G diff
differential gain
-
0.6
-
%
difl
differential phase
-
1
Zo
output impedance
-
75
-
Q
note 3; fCLK = 30 MHz
deg
Transfer function (fcLK = 30 MHz)
IlE
DC integral linearity error
-
-
OLE
DC differential linearity error
-
-
April 1993
3-780
±1/2
±1/2
lSB
lSB
Product specification
Philips Semiconductors
TDA8702
8-bit video digital-to-analog converter
SYMBOL
PARAMETER
Switching characteristics (fCLK
CONDITIONS
MIN.
TYP.
MAX.
UNIT
= 30 MHz; notes 4 and 5; see Figs 3, 4 and 5)
tSU;DAT
data set-up time
-0.3
-
-
ns
tHD;DAT
data hold time
2.0
-
-
ns
tpD
propagation delay time
-
-
1.0
ns
tS1
settling time
10% to 90% full-scale
change to ±1 lSB
-
1.1
1.5
ns
tS2
settling time
10% to 90% full-scale
change to ±1 lSB
-
6.5
8.0
ns
td
input to 50% output delay time
-
3.0
5.0
ns
-
-
30
lSB.ns
Output transients (glitches; (fCLK
=30 MHz; note 6; see Fig.6)
glitch energy from code
Eg
transition 127 to 128
Notes
1. DO to D7 are connected to VCCD ' ClK is connected to DGND.
2. The analog output voltages (VOUT and VOuT are negative with respect to VCCA (see Table 1). The output resistance
between VCCA and each of these outputs is 75 n (typ.).
3. The -3 dB analog output bandwidth is determined by real time analysis of the output transient at a maximum input
code transition (code 0 to 255).
4. The worst case characteristics are obtained at the transition from input code 0 to 255 and if an external load
impedance greater than 75 n is connected between VOUT or VOuT and VCCA. The specified values have been
measured with an active probe between V OUT and AGND. No further load impedance between V OUT and AGND
has been applied. All input data is latched at the rising edge of the clock. The output voltage remains stable
(independent of input data variations) during the HIGH level of the clock (ClK = HIGH). During a lOW-to-HIGH
transition of the clock (ClK = lOW), the DAC operates in the transparent mode (input data will be directly
transferred to their corresponding analog output voltages (see Fig.5).
5. The data set-up (tSU;DAT) is the minimum period preceding the rising edge of the clock that the input data must be
stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the
rising edge of the clock and still be recognized. The data hold time (tHD;DAT) is the minimum period following the
rising edge of the clock that the input data must be stable in order to be correctly registered. A negative hold time
indicates that the data may be released prior to the rising edge of the clock and still be recognized.
6. The definition of glitch energy and the measurement set-up are shown in Fig.6. The glitch energy is measured at
the input transition between code 127 to 128 and on the falling edge of the clock.
April 1993
3-781
Philips Semiconductors
Product specification
8-bit video digital-to-analog converter
TDA8702
Table 1 Input coding and output voltages (typical values; referenced to VCCA' regardless of the offset voltage).
DACOUTPUT VOLTAGES
CODE
INPUT DATA
(07 to DO)
ZL=10kQ
0
0000000
1
00000001
ZL= 75 Q
VOuT
VOUT
-1.6
0
V OUT
0
VOuT
-0.8
-0.006
-1.594
-0.003
-0.797
-0.8
-0.8
-0.4
-0.4
-0.006
-0.797
-0.003
........
128
10000000
........
254
111 111 10
-1.594
255
111 111 11
-1.6
0
1 4 - - - tsu; OAT ----JI>.t
input data
-0.8
0
tHO; OAT
stable
, . . . - - - - - - - " - - - - - - 3.0V
elK
-----1.3V
'-----OV
MBC912
The shaded areas indicate when the input data may change and be correctly registered. Data input update must
be completed within 0.3 ns after the first rising edge of the clock (tSU;DAT is negative; -0.3 ns). Data must be held
at least 2 ns after the rising edge (tHD;DAT +2 ns).
=
Fig.3 Data set-up and hold times.
April 1993
3-782
Product specification
Philips Semiconductors
a-bit video digital-to-analog converter
TDA8702
-
CLK
-
-
-
-
-
-
-
-
1.3 V
code 255
input data
(example of a
full-scale input
transition)
1.3V
codeD
1LSS
VCCA
(code 0)
VOUT
VCCA -1.6V
(code 255)
FigA Switching characteristics.
tra~b~~ent
CLK
' - -_ _ _ _ _..J
_I~~~~d _
1.3 V
:
I
input
codes
---+------,w
VOUT
I
I
I
I
LflL...-.l---
I
analog
output
voltage
MBC914·1
i
I
I
I
transparent
mode
latched mode
(stable output)
beginning of
transparent
mode
During the transparent mode (ClK = lOW), any change of input data will be seen at the output. During the
latched mode (ClK = HIGH), the analog output remains stable regardless of any change at the input A change
of input data during the latched mode will be seen on the falling edge of the clock (beginning of the transparent
mode)_
Fig_5 latched and transparent mode_
April 1993
3-783
Product s~ecification
Philips Semiconductors
8-bit video digital-to-analog converter
fClKll0
(2)
HP8082A
07 MSB
06
05
fClKll0
04
(1)
03
02
TDA8702
TEK P6201
TEK7104 and TEK7A26
R= 100 kn
C=3pF
bandwidth = 20 MHz
VOUT
VOUT
TDA87021
TDA8702T
01
clock
DO (lSB)
+
3
fClK
JlJ1JUlJUlJUl
,JrLJL
(3)
MOOElEH107
I
lLSB
2ll-JLJ
timing diagram
code 128
MSA660
The value of the glitch energy is the sum of the shaded area measured in LSB.ns.
Fig.6 Glitch energy measurement.
April 1993
3-784
Philips Semiconductors
Product specification
8-bit video digital-to-analog converter
TDA8702
INTERNAL PIN CONFIGURATIONS
V CCA --11--__- - - - - - - - - - - - - - - - _ -
output current
generators
REF~--+-----------~--~~
AGNO
~---+---------------------------'
Fig.7 Reference voltage generator decoupling.
VCCA
I]
~:-
OGNO
AGNO
---+-_----..---
Do to 07,
ClK
---+--+-----+.--
.~
substrate
~
...
..L
MBC90B
AGNO
,.
~
J
MBC910
Fig.9 D7 to DO and elK.
Fig.8 AGND and DGND.
April 1993
3-785
Product specification
Philips Semiconductors
8-bit video digital-to-analog converter
TDA8702
V CCA -lr----..,.-~--___.-___.-
VCCDtr
VOUT --..j~-+--+---~
VOUT --..j~+--+----~~
DGNDt
AGND
~I---+--+---l
MSC907
MSC909 • 1
Fig.10 Digital supply.
Fig.11 Analog outputs.
VCCAtr
AGNDt
MSC906
'Fig.12 Analog supply.
April 1993
switches and
current generators
3-786
Philips Semiconductors
Product specification
8-bit video digital-to-analog converter
TDA8702
APPLICATION INFORMATION
Additional application information will be supplied upon request (please quote number FTV/8901).
100 nF(1)
REF VCCA I------!Vo
AGND
VOUT
VOUT~---------o
TDA87021
TDA8702T
----
MSA661
(1) This is a recommended value for decoupling pin 1.
Fig.13 Analog output voltage without external load (Vo
=-\lOuT; see Table 1, ZL =10 kO).
100 nF(1)
AGND
TDA87021
TDA8702T
---
MSA662
(1) This is a recommended value for decoupling pin 1.
Fig.14 Analog output voltage with external load (external load ZL = 75 n to oo).
April 1993
3-787
Philips Semiconductors
8~bit
Product specification
video digital-to-analog converter
r
TDA8702
100nF(1)
REF
100 Ilf
VOUT t----t 111-+'--1--'0
AGND
750
TDA87021
TDA8702
MSA663
---
AGND
(1) This is a recommended value for decoupling pin 1.
Fig.15 Analog output with AGND as reference.
10 I!H
TDA8702
121!H
V OUT
(pin 15)
or
r--ilr-~C=~~-ilr-~~.r-~~--~-.-+
V OUT
Vo [390/(780+75)]
(pin 14)
Fig.16 Example of anti-aliasing filter (analog output referenced to AGND).
April 1993
3-788
Philips Semiconductors
Product specification
8-bit video digital-to-analog converter
TDA8702
MSA657
o
Characteristics
-h
a
\
\
\
(dB)
20
40
• Order 5; adapted CHEBYSHEV
• Ripple at ~ 0.1 dB
• f(-3 dB) = 6.7 MHz
• f(NOTCH) = 9.7 MHz and 13.3 MHz
L
,
I
60
80
100
o
10
30
20
40
fi (MHz)
Fig.17 Frequency response for filter shown in Fig.16.
100nF(1)
R2
REF
AGND
VOUT~~II~~--~4-~~
o
vOUT~~II~~==~~;/
TDA87021
TDA8702T
2 X Vo (R2IR1)
--~
AGND
(1) This is a recommended value for decoupling pin 1.
Fig.18 Differential mode (improved supply voltage ripple rejection).
April 1993
3-789
MSA664
Philips Semiconductors Video Products
Product specification
8-bit high-speed analog-to-digital
converter
FEATURES
• 8-bit resolution
• Sampling rate up to 40 MHz
• High signal-to-noise ratio over a
large analog input frequency
range (7.1 effective bits at
4.43 MHz full-scale input)
• Binary or two's complement
3-state TTL outputs
TDA8703
APPLICATIONS
GENERAL DESCRIPTION
• General purpose high-speed
analog-to-digital conversion
The TDA8703 is an 8-bit high-speed
analog-to-digital converter (AD C) for
video and other applications. It
converts the analog input signal into
8-bit binary-coded digital words at a
maximum sampling rate of 40 MHz.
All digital inputs and outputs are TTL
compatible, although a low-level AC
clock input signal is allowed.
• Digital TV, IDTV
• Subscriber TV decoder
• Satellite TV decoders
• Digital VCR.
• Overflow/underflow 3-state TTL
output
• TTL compatible digital inputs
• Low-level AC clock input signal
allowed
• Internal reference voltage
generator
• Power dissipation only 290 mW
(typical)
• Low analog input capacitance, no
buffer amplifier required
• No sample-and-hold circuit
required.
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
PACKAGE
PINS
PIN POSITION
MATERIAL
CODE
TDA8703
24
OIL
plastic
SOT101
TDA8703T
24
S024
plastic
SOT137A
April 1993
3-790
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital
converter
TDA8703
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
VCCA
analog supply voltage
VCCD
digital supply voltage
Vcco
output stages supply voltage
4.5
4.5
4.2
ICCA
analog supply current
-
ICCD
digital supply current
Icco
IlE
output stages supply current
DC integral linearity error
OLE
DC differential linearity error
AilE
AC integral linearity error
B
-3 dB bandwidth
note 2; fCLK
fCLK/fCiJ(
maximum conversion rate
note 3
PlOt
total power dissipation
note 1
=40 MHz
TYP.
MAX.
UNIT
5.0
5.0
5.5
5.5
-
5.0
28
19
5.5
36
25
-
11
14
rnA
-
lSB
-
-
±1
±1/2
-
±2
lSB
-
MHz
40
19.5
-
-
MHz
-
290
415
mW
-
V
V
V
rnA
rnA
lSB
Notes
1. Full-scale sinewave (fj = 4.4 MHz; fcLK ; fCiJ( = 27 MHz).
2. The -3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at input).
3. The circuit has two clock inputs ClK and ClK. There are four modes of operation:
e TTL (mode 1); ClK decoupled to DGND by a capacitor. ClK input is TTL threshold voltage of 1.5 Vand
sampling on the lOW-to-HIGH transition of the input clock signal.
• TTL (mode 2); ClK decoupled to DGND by a capacitor. ClK input is TTL threshold voltage of 1.5 V and
sampling on the HIGH-to-lOW transition of the input clock signal.
• AC dr.ive modes (modes 3 and 4); When driving the ClK input directly and with any AC signal of 0.5 V
(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the lOW-to-HIGH transition of the
clock signal. When driving the ClK input with such a signal, sampling takes place on the HIGH-to-lOW transition.
• If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF
capacitor.
April 1993
3-791
Product specification
Philips Semiconductors
a-bit high-speed analog-to-digital
converter
TDA8703
clock inputs
IVcCA
ICLK
ICLK
f
~16
~17
I
STABIUZER
DEC 5
VRT 9
~
II
CLOCK DRIVER
jVCCD
\18
TC
CE
21
22
I
TDA8703
TDA8703T
12 07
13 06
[J
analog
voltage input
VI 8
--.
I
I
:
14 05
15 04
ANALOG - TO - DIGITAL
CONVERTER
f+ r---
LATCHES
~
TTL OUTPUTS
~
23 03
data outputs
24 02
1 01
2 DO
VRB 4
LSB
19
Y
I)
VCCO
OVERFLOW I UNDERFLOW
3
AGND
,,!o?
analog ground
LATCH
TTL OUTPUT
11
20
DGND
MGAOt5
,!07.
digital ground
Fig.1 Block diagram.
April 1993
MSB
3-792
--.
overflow I underflow
output
Product specification
Philips Semiconductors
a-bit high-speed analog-to-digital
converter
TDA8703
PINNING
SYMBOL
DESCRIPTION
PIN
01
1
data output; bit 1
data output; bit 0 (lSB)
00
2
AGNO
3
analog ground
VAB
4
reference voltage bottom (decoupling)
02
OEC
5
decoupling input (internal stabilization loop decoupling)
03
n.c.
6
not connected
VCCA
VI
7
positive supply voltage for analog circuits (+5 V)
8
analog voltage input
VAT
9
reference voltage top (decoupling)
CE
TC
VAB
OGNO
vcca
n.c.
10
not connected
O/UF
11
overflow/underflow data output
VCCO
07
12
data output; bit 7 (MSB)
ClK
06
13
data output; bit 6
ClK
05
14
data output; bit 5
04
15
data output; bit 4
ClK
16
clock input
ClK
17
complementary clock input
n.c.
04
05
06
07
MLB034
positive supply voltage for digital circuits (+5 V)
VCCD
Vcco
18
19
positive supply voltage for output stages (+5 V)
OGNO
20
digital ground
TC
21
input for two's complement output (TTL level input,
active lOW)
CE
22
chip enable input (TTL level input, active lOW)
03
23
data output; bit 3
02
24
data output; bit 2
April 1993
Fig.2 Pin configuration.
3-793
Product specification
Philips Semiconductors
8-bit high-speed analog-to-digital
converter
TDA8703
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL
CONDITIONS
PARAMETER
MIN.
UNIT
MAX.
VCCA
analog supply voltage
-0.3
7.0
V
V CCD
digital supply voltage
-0.3
7.0
Vcco
output stages supply voltage
-0.3
7.0
V
V
V CCA - V CCD
supply voltage differences
-1.0
1.0
V
Vcco - VCCD
VCCA - Vcco
supply voltage differences
-1.0
1.0
V
-1.0
1.0
V
VVI
input voltage range
referenced to AGND
-0.3
7.0
VcLKIVCCK
AC input voltage for switching
(peak-to-peak value)
note 1; referenced to
DGND
-
2.0
V
V
supply voltage differences
10
output current
-
+10
mA
T s1g
storage temperature
-55
+150
°C
Tamb
operating ambient temperature
0
+70
°C
Tj
junction temperature
-
+125
°C
Note
1. The circuit has two clock inputs ClK and ClK. There are four modes of operation:
• TTL (mode 1); ClK decoupled to DGND by a capacitor. ClK input is TTL threshold voltage of 1.5 V and
sampling on the lOW-to-HIGH transition of the input clock signal.
• TTL (mode 2); ClK decoupled to DGND by a capacitor. ClK input is TTL threshold voltage of 1.5 V and
sampling on the HIGH-to-lOW transition of the input clock signal.
• AC drive modes (modes 3 and 4); When driving the ClK input directly and with any AC signal of 0.5 V
(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the lOW-to-HIGH transition of the
clock Signal. When driving the ClK input with such a signal, sampling takes place on the HIGH-to-lOW transition.
If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF
capacitor.
THERMAL RESISTANCE
SYMBOL
Rthj-a
PARAMETER
THERMAL RESISTANCE
from junction to ambient in free air
SOT101
55K/W
SOT137A
75K/W
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
April 1993
3-794
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital
converter
TDA8703
CHARACTERISTICS (see Tables 1 and 2)
VecA = V7 - V3 = 4.5 V to 5.5 V; Vcco = V18 - V20 =4.5 V to 5.5 V; Vcco = V19 - V20 = 4.5 V to 5.5 V; AGND and DGND
shorted together; VCCA - Vcco =-0.5 Vto +0.5 V; Vcco - Vcco =-0.5 V to +0.5 V; VCCA - Vcco = -0.5 V to +0.5 V;
Tamb = 0 °C to +70 °C; unless otherwise specified (typical values measured at VCCA = Vcco = Vcco = 5 V and
Tamb = 25°C).
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VCCA
analog supply voltage
4.5
5.0
5.5
V
Vcco
digital supply voltage
5.0
5.0
28
5.5
5,5
V
36
25
rnA
14
rnA
Vcco
output stages supply voltage
4.5
4.2
IccA
analog supply current
-
Icco
digital supply current
Icco
output stage supply current
-
all outputs lOW
V
rnA
-
19
11
0
2.0
-
0.8
V
-
Vcco
-
V
J.1A
100
300
-
J.1A
kn
Inputs
Clock input ClK and ClK (note 1; referenced to DGND)
Vil
VIH
lOW level input voltage
HIGH level input voltage
III
lOW level input current
Vcu!'IW. = 0.4 V
-400
I'H
HIGH level input current
Vcu/'IW. = 0.4 V
-
-
-
-
Zj
input impedance
Vcu/'IW. = Vcco
fClK/tCLK = 10 MHz
Cj
input capacitance
-
4
4.5
-
pF
0.5
-
2.0
V
0
2.0
-
0.8
V
-
Vil = 0.4 V
VIH =2.7 V
-400
-
-
Vcco
-
J.1A
-
20
J.1A
1.33
10455
VCLK -
VCi:K
AC input voltage for switching
(peak-to-peak value)
fClK/tCLK = 10 MHz
note 1;
DC level = 1.5 V
J.1A
TC and CE (referenced to DGND)
Vil
VIH
HIGH level input voltage
III
lOW level input current
lOW level input voltage
HIGH level input current
IIH
VI (analog input voltage referenced to AGND)
VVI(B)
input voltage (bottom)
VVI(O)
input voltage
output code = 0
VeS(B)
offset voltage (bottom)
VVI(O) - VVI(B)
VVI(T)
input voltage {top)
1.41
1.48
V
1.55
1.635
0.155
3.5
3.385
V
0.125
3.2
3.115
-
0.085
1.66
-
VVI
-
-
J.1A
60
-
0
120
180
10
14
-
J.1A
kn
-
pF
VVI(255)
input voltage
output code = 255
VOS(T)
offset voltage (top)
VVI(T) - VVI(255)
VVI(P-P)
input voltage amplitude
(peak-to-peak value)
III
lOW level input current
IIH
Zj
HIGH level input current
input impedance
fj = 1 MHz
Cj
input capacitance
fj
April 1993
V
=1.4 V
VVI =3.6 V
= 1 MHz
3-795
-
3.36
3.26
1.71
0.115
1.75
V
V
V
V
V
Product specifiGation
Philips Semiconductors
8-bit high-speed analog-to-digital
converter
TDA8703
CHARACTERISTICS
PARAMETER
SYMBOL
MIN.
CONDITIONS
TYP.
MAX.
UNIT
Reference resistance
Rrel
reference resistance
V RT to VRB
-
220
-
n
0.4
V
Vcco
+20
V
-20
-
40
-
-
MHz
Outputs
Digital outputs (07 - DO) (referenced to DGND)
VOL
VOH
LOW level output voltage
10= 1 mA
0
HIGH level output voltage
2.7
loz
output current in 3-state mode
10 =-0.4 mA
0.4 V< Vo < Vcco
J.lA
Switching characteristics (note 2; see Fig.3)
fCL~/fCu<
maximum clock frequency
Analog signal processing (fCLK
= 40 MHz)
B
-3 dB bandwidth
note 3
-
19.5
-
MHz
Gd
differential gain
note 4
0.6
-
%
note 4
-
C\)d
differential phase
0.8
-
deg
f1
fundamental harmonics (full-scale) fj = 4.43 MHz
-
-
0
dB
fau
harmonics (full-scare). all
components
f j = 4.43 MHz
-
-55
-
dB
SVRR1
supply voltage ripple rejection
note 5
-28
-25
dB
SVRR2
supply voltage ripple rejection
note 5
-
1
2.5
%IV
Transfer function
ILE
DC integral linearity error
-
-
±1
LSB
DLE
DC differential linearity error
-
-
±1/2
LSB
AILE
AC integral linearity error
note 6
±2
LSB
effective bits
fj = 4.43 MHz
-
-
EB
7.1
-
bits
Timing (note 7; see Figs 3 to 6; fCLK = 40 MHz)
~
sampling delay
-
-
2
ns
tHO
output hold time
6
-
-
ns
~H
output delay time
LOW-to-HIGH transition
8
10
ns
~HL
output del~y time
HIGH-to-LOW transition
-
16
20
ns
~H
. 3-state output delay times
enable-to-HIGH
-
19
25
ns
~L
3-state output delay times
enable-te-LOW
-
16
20
ns
~HZ
3-stateoutput delay times
disable-to-HIGH
-
14
20
ns
~LZ
3-state output delay times
disable-to-LOW
-
9
12
ns
April 1993
3-796
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital
converter
TDA8703
Notes
1. The circuit has two clock inputs ClK and ClK. There are four modes of operation:
• TTL (mode 1); ClK decoupled to DGND by a capacitor. ClK input is TTL threshold voltage of 1.5 V and
sampling on the lOW-to-HIGH transition of the input clock signal.
• TTL (mode 2); ClK decoupled to DGND by a capacitor. ClK input is TTL threshold voltage of 1.5 V and
sampling on the HIGH-to-lOW transition of the input clock signal.
• AC drive modes (modes 3 and 4); When driving the ClK input directly and with any AC signal of 0.5 V
(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the lOW-to-HIGH transition of the
clock signal. When driving the ClK input with such a signal, sampling takes place on the HIGH-to-lOW transition.
If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF
capacitor.
2. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the
clock must not be less than 2 ns.
3. The -3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at the
input).
=
4. low frequency ramp signal (VVI(P-P) 1.8 V and fj
(VVI(P-P) 0.5 V, fj 4.43 MHz) at the input.
=
=
=15 kHz) combined with a sinewave input voltage
5. Supply voltage ripple rejection:
8 SVRR1; variation of the input voltage producing output code 127 for supply voltage variation of 1 V:
SVRR1
20 log (~VVI(127) / ~VeeA)
• SVRR2; relative variation of the full-scale range of analog input for a supply voltage variation of 1 V:
SVR2 = {~(V VI(O) - V VI(255») / (V VI(O) - V VI(255»)} + ~ VecA,
=
6. Full-scale sinewave (fj = 4.4 MHz; feLK ; fCU( = 27 MHz).
7. Output data acquisition:
• Output data is available after the maximum delay of ~HL and t dLH .
April 1993
3-797
Product specification
Philips Semiconductors
8-bit high-speed analog-to-digital
converter
TDA8703
Table 1 Output coding and input voltage (referenced to AGNO; typical values).
BINARY OUTPUT BllS
STEP
VVl(P-P)
underflow < 1.55
TWO's COMPLEMENT OUTPUT BITS
OiUF
07
06
05
04
03
02
01
00
07
06
05
04
03
02
01
00
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1.55
0
0
0
0
0
0
0
0
0
1.
0
0
0
0
0
0
1
-
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
•
•
•
•
•
•
•
•
•
•
~
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
254
•
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
255
3.26
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
overflow
> 3.26
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
Table 2 Mode selection.
TC
CE
X
1
high impedance
0
0
active; two's complement
active
1
0
active; binary
active
Where: X = don't care
elK
VI
00-07
Fig.3 Timing diagram.
April 1993
O/UF
07·00
high impedance
3-798
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital
converter
CE
input
TDA8703
reference
-f---------'l.---------Ievel
(1.4V)
data
outputs
""""'........""""'........"" - - 0.4 V
MLB035· ,
FigA 3-state delay timing diagram.
Vcco
DO - 07 t-----<,.---t-i.-t---+
DO - 07
t----t--1~-+-I~~-+
IN916
or
IN3064
IN916
or
IN3064
MBB955
OGNO
Fig.6 Load circuit for timing measurement;
3-state outputs (CE: fj = 1 MHz; VVI =3 V); see
Table 3.
Fig.S Load circuit for timing measurement; data
outputs (CE = LOW).
April 1993
3-799
Philips- Semiconductors
Product specification
8-bit high-speed analog-to-digital
converter
TDA8703
Table 3 Timing measurement for load circuit.
TIMING MEASUREMENT
SWITCH S1
SWITCH S2
~H
open
closed
15pF
tdZL
closed
open
15pF
~HZ
closed
closed
5 pF
tdLZ
closed
closed
5 pF
CAPACITOR
INTERNAL PIN CONFIGURATIONS
Vcco
-1-.---.----..---
V CCA
-t---,.----t------,.-
(x 90)
DGND
-+---------
AGND
-t-'----+--+----~-
MLB036
MLB037
Fig.S Analog inputs.
Fig.7 TTL data and overflow/underflow outputs.
VCCD
vcco
TC
CE
lr.
DGND
MLB039
DGND
-1--4------4-MLB038
Fig.9 CE (3-state) input.
April 1993
Fig.10 TC (two's complement) input.
3-S00
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital
converter
TDA8703
VCCA--4-~--------------~--~------~--~-
DEC -+--+-~--I-----------,
AGND-~---4--------------~------~--~----MCDI88
Fig.11 VRe • VRT and DEC.
VCCD---~----------~----~--------
CLK
----~----.----.__--t
30kn
DGND-----~----~------~----~~~
Fig.12 ClK and ClK inputs.,
April 1993
3-801
. Product specification
Philips Semiconductors
8-bit high-speed analog-to-digital
converter
TDA8703
APPLICATION INFORMATION
Additional application information will be supplied upon request (please quote number FTV/8901).
01
1
00
2
AGNO
3
v RS
4
OEC
5
24
23
22
21
20
19
TOA8703
TOA8703T
18
02
03
CE
Tc
OGNO
VCCO
+5V
VCCO
r
22nF
17
16
Y
10
O/UF
11
07
12
15
14
CLK
CLK
04
1100PF
OGNO
05
AGNO
13
06
MGAOl4- I
Fig.13 Application diagram.
Notes to Fig.13
1. It is recommended to decouple Veeo through a 22
interfaces with a capacitive CMOS load device.
n
resistor especially when the output data of the TDA8703
2. ClK should be decoupled to the DGND with a 100 nF capacitor, if a TIL signal is used on ClK (see 'Notes to the
characteristics', note 1).
3. ClK and ClK can be used in a differential mode (see 'Notes to the characteristics', note 1).
4. VRB and VAT are decoupling pins for the internal reference ladder; do not draw current from these pins in order to
achieve good linearity.
5. If it is required to use the TDA8703 in a parallel system configuration, the references (VAB and VAT) of each
TDA87803 can be connected together. Code 0 will be identical and code 255 will remain in the 1lSB variation for
each TDA8703.
6. Analog and digital supplies should be separated and decoupled.
7. Pins 6 and 10 should be connected to AGND in order to prevent noise influence.
April 1993
3-802
Philips Semiconductors Video Products
Preliminary specification
6-bit analog-to-digital converter
with multiplexer and clamp
FEATURES
• 6-bit resolution
TDA8706
QUICK REFERENCE DATA
Measured over full voltage and temperature ranges
MIN.
TYP.
MAX.
UNIT
analog supply
voltage (pin 2)
4.5
5.0
5.5
V
VCCD
digital supply
voltage (pin 10)
4.5
5.0
5.5
V
ICCA
analog supply
current (pin 20)
-
32
39
rnA
ICCD
digital supply
current (pin 10)
-
28
37
rnA
ILE
integral
linearity error
-
-
±D.75 LSB
OLE
DC differential
linearity error
-
-
±D.5
LSB
• Y, U and V signals
fcu<
maximum
clock frequency
20
-
-
MHz
• Colour Picture-in-Picture
(PIPCO) for TV
Plot
total power
disSipation
-
300
418
rnW
Tamb
operating
ambient
temperature
range
0
-
+70
°C
• Binary 3-state TIL outputs
SYMBOL
• TIL compatible digital inputs
VCCA
• 3 multiplexed video inputs
• Luminance and colour difference
clamps
• Internal reference
• 300 mW power dissipation
• 20-pin plastic package
APPLICATIONS
• General purpose video
applications
• Videophone
• Frame grabber
GENERAL DESCRIPTION
The TOA8706 is a monolithic bipolar
6-bit analog-to-digital converter
(AOC) with a 3 analog input
multiplexer and a clamp. All digital
inputs and outputs are TIL
compatible. Regulator with good
temperature compensation.
PARAMETER
ORDERING INFORMATION
EXTENDED
TYPE NUMBER
PACKAGE
PINS
PIN POSITION
MATERIAL
CODE
TOA8706
20
OIL
plastic
SOT146EF4
TOA8706T
20
S020L
plastic
SOT163AG7
FUNCTIONAL DESCRIPTION
The TOA8706 is a "like-flash"
converter which produces an output
code in one clock period. The device
can withstand a duty clock cycle of
50 to 66.6% (clock HIGH).
Luminance clamping level is fitted
with 00 hex. code (output 000000).
Chrominance clamping level is fitted
with 20 Hex. code (output 100000).
February 1992
CONDITIONS
3-803
~
2
:EO)
0-
_.
I
-:::T::;:
0-
~
3
-"
0)
c:
<0
<0
::J
;::::;-0)
I\)
clock
input
-0.
chip
enable
13
0
-<0
CD I
X
CD 0
....,
I
14
-u
~
-6°
en
(J)
CD
3
o~
0°
a.
c
&
en
0)9:
::J CQ.
chrominance ----tl
input
1-
Q .0)-
.,
~
0-0
0) 0
~
-0<
3
::J
CD
;l.
chrominance
input
----t I
,-
~
••
TIL
OUTPUTS
------I MULTIPLEXER
~
CD
....,
digital
voltage
outputs
u.:>
cD
~
o.j:>..
luminance ----tl
input
I"
.,
20
1. 00
clamp
input
TDA8706
11
VCCA
VCCD
18
19
110
C
B
A
~
select
inputs
:t
~
reference
voltage
TOP
~
reference
voltage
BOTIOM
ground
-u
~
MCD267
3°
so
o
-<'C/l"
.......
g
--I
»
00
Figo1 Block diagramo
o
0)
"0
~
0°
~
Philips Semiconductors
Preliminary specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706
PINNING
SYMBOL
Fig.2 Pin configuration.
HANDLING
Inputs and outputs are protected
against electrostatic discharges in
normal handling. However, to be
totally safe, it is desirable to take
normal precautions appropriate to
handling integrated circuits.
February 1992
PIN
DESCRIPTION
GNO
1
ground
VCCA
VAT
VRB
2
analog positive supply (+5 V)
3
reference voltage TOP decoupling
4
reference voltage BOnOM decoupling
INC
5
chrominance input
INB
6
chrominance input
INA
7
luminance input
C
8
select input
select input
B
9
A
10
select input
VCCD
11
digital positive supply voltage (+5 V)
CLAMP
12
clamp pulse input (positive pulse)
ClK
13
clock input
CE
14
chip enable (active lOW)
05
15
digital voltage output: most significant bit (MSB)
04
16
digital voltage output
03
17
digital voltage output
02
18
digital voltage output
01
19
digital voltage output
00
20
digital voltage input: least significant bit (lSB)
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134)
MAX.
UNIT
7.0
V
-0.3
7.0
1.0
-
V
V
input voltage range
-0.3
7.0
V
output current
-
10
mA
storage temperature range
-55
+150
°C
operating ambient temperature
range
0
+70
°C
PARAMETER
SYMBOL
MIN.
VCCA
VCCD
analog supply voltage range (pin 2)
-0.3
digital supply voltage range (pin.1 0)
VCCA-VCCD
supply voltage difference
VI
10
Tstg
Tamb
3-805
Philips Semiconductors
Preliminary specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706
CHARACTERISTICS (see Tables 1 and 2)
VCCA =4.5 V to 5.5 V; VCCD =4.5 V to 5.5 V =VCCD ; Tal'rb =0 °C to +70°C; CYRB =CVA1
measured at VCCA =VCCD =5 V and Tamb =25°C; unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
= 100 nF;Typical values
MIN.
TYP.
MAX.
UNIT
Supply
VCCA
VCCD
analog supply voltage (pin 2)
4.5
5.0
5.5
V
digital supply voltage (pin 10)
4.5
5.0
5.5
V
ICCA
analog supply current (pin 2)
-
32
39
mA
ICCD
digital supply current (pin 10)
-
28
37
mA
-
0.8
V
V
all outputs at
LOW level
Inputs
CLOCK INPUT (PIN 13)
VIL
LOW level input voltage
0
VIH
IlL
HIGH level input voltage
2.0
IIH
HIGH level input current
ZI
Cj
input impedance
VCLK = 0.4 V
VCLK = 2.7 V
fCLK = 20 MHz
input capacitance
fCLK = 20 MHz ,
LOW level input current
-400
-
VCCD
-
-
-
100
-
4
-
J.1A
kQ
-
2
-
pF
0
0.8
V
2
-
VCCD
V
-400
-
-
J.1A
-
-
20
J.1A
V
J.1A
A, B, C, CLAMP AND CEN INPUTS (PINS 8,9,10,12 AND 14)
LOW level input voltage
VIL
VIH
HIGH level input voltage
IlL
LOW level input current
IIH
HIGH level input current
VCLK
VCLK
= 0.4 V
=2.7 V
Reference voltage (pins 3 and 4)
VAT
VAB
VAT - VAB
reference voltage TOP decoupling
3.22
"3.35
3.44
reference voltage BOTTOM decoupling
1.84
1.9
1.96
V
reference voltage TOP - BOTTOM decoupling
1.36
1.435
1.48
V
mV
Analog inputs INA, INB, INC (pins 7, 6and 5)
VI(P1ll
input voltage amplitude (peak-ta-peak value)
Zt
input impedance
Cclarrp
coupling clamp capacitance
Analog signal processing (pins 5, 6, and 7) (fCLK
f;
=4.43 MHz
840
900
940
100
-
-
kQ
1
10
1000
nF
-
-
0
dB
-45
-
dB
=20 MHz)
=4.43 MHz
=4.43 MHz
f1
fundamental harmonics (full scale)
fj
fall
Gdilf
harmonics (full scale); all components
fj
differential gain
note 1
-
0.4
-
differential phase
note 1
1.0
-
supply voltage ripple rejection
note 2
-
-30
-
%
deg
dB
10= 1 mA
0
-
0.4
V
sampling time offset
Notes to the characteristics
1. Low frequency ramp Signal (Vy1(P-P)
and f, = 4.43 MHz) at the input.
= 1.8 V and fi = 15 kHz) combined with a sinewave input voltage (VY1(P'P) = 0.5 V
2. Supply voltage ripple rejection (SVRR): variation of the input voltage produces output code 31 for a supply voltage
variation of 1 V.
~V
SVRR = 20 log ~
~VCCA
3. Full-scale sinewave; fi
February 1992
=4.43 MHz, fClK =20 MHz.
3-807
Philips Semiconductors
Preliminary specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706
Table 1 Output coding
VI (note 1)
BINARY OUTPUTS
(TYP. value)
05 to DO
Underflow
<2.2V
000000
0
2.2V
1
2.215 V
STEP
000000
. 000001
......
......
......
62
3.072 V
111110
63
3.086 V
111111
Overflow
>3.1 V
111111
Note
1. With clamping capacitance.
Table 2 Mode selection
CEN
DO to 05
1
high impedance
0
active. Binary
Table3 Clamp input A
A
CLAMP
DIGITAL OUTPUTS
V.",A
0
1
X
2.2
1
1
0
2.2
Note
X = don't care.
Table 4 Clamp input Band C
BIC
CLAMP
DIGITAL
OUTPUTS
VlnBN.",C
0
1
X
2.65
1
1
32
2.65
Note
X = don't care.
February 1992
3-808
Philips Semiconductors
Preliminary specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706
.,...--- - - - V
1H
---50%
_IClH--ICll-
MCD268
1 - - - - - - - - - - - - I ClP - - - - - - - - - - - - ,
Fig.3 AC clock characteristics.
ClK
A
r-l~"'"\
I
B
\
r-C
~~~
--
--IDH
I ClPS --
______________
I
~
\- 4 -
--
/
CLAMP
1 - - - - - - I ClPP
OUTPUT
DATA
MCD269· 1
Fig.4 AC characteristics select signals; Clamp, Data.
February 1992
3-809
Preliminary specification
Philips Semiconductors
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706
-(8-Y)
(C input)
......- - - + - t -..... - - - - - " c : - - - -
digital outputs
= 100000
-(R-Y)
._---+--+--J'---\----
digital outputs
.---+--+---'-----
digital outputs
= 100000
(8 input)
Y
(A input)
= 000000
__---'n'--__
CLAMP
input
Fig.S AC characteristics select signals; Clamp, Data.
Table 5 Clamp characteristic related to TV signals
PARAMETER
MIN.
TYP.
MAX.
UNIT
Il s
lines
clamping time per line (signal active)
2.2
3.0
3.3
input signals clamped to correct level after
-
3
10
February 1992
3-810
MCD270
Philips Semiconductors
Preliminary specification
6-bit analog-to-digital converter
with multiplexer and clamp
CE
input
TDA8706
-¥--------'t--------
reference
level
(1.3 V)
""""'77".r-r7"'777-r - - 2.4 V
data
outputs
L
'-L..4..1...L..1.~'-i....i.."'- - -
7Z24765.1
Fig.6 Timing diagram of 3-state delay.
February 1992
0.4 V
3-811
Philips Semiconductors
Preliminary specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706
Application information
Additional application information will be supplied on request (please quote reference number FTV/9112).
20
2
19
3
18
4
17
22 nF
22 nF
INC
1---+ 5
16
TDA8706
INB
1--+ 6
15
INA
1--+ 7
14
~8
13 •
C
c ~9
12
J--L
11
C
10
clock signal
c
I
I
MGA230
Fig.? Application diagram.
Notes to figure?
1.
'e' capacitors must be determined on the output capacitance of the circuits driving A, Band e or elK pins
2. V RS and VRT are decoupling pins for the internal reference ladder. Do not draw current from these pins in order to
achieve good linearity
3. Analog and digital supplies should be separated and decoupled.
February 1992
3-812
Preliminary specification
Philips Semiconductors
Triple RGB 6-bit video analog-to-digital
interface
TDA8707
FEATURES
Analog-to-digital converter
• Triple analog-to-digital converter (ADC)
The TDA8707 implements 3 independent 6-bit
analog-to-digital converters in CMOS 1 "",m process.
These converters use a full-flash approach.
• 6-bit resolution
• Sampling rate up to 35 MHz
• Power dissipation of 300 mW (typical)
Clamping feature
• Internal clamping function.
An internal clamping circuit is provided in each of the 3
analog channels. The analog pins INR, ING and INB are
switched, through series capacitors, to on-chip clamping
levels during an active pulse on the clamp input CLP.
Clamping level in the R, G and B channels is Code O.
APPLICATIONS
• High-speed analog-to-digital conversion for video
signals
• VGA signal treatment.
Input buffers
DESCRIPTION
Internal buffers are provided to drive the analog-to-digital
converter inputs. Their ratio can be adjusted externally at
1.5 or 2.0 with select input SLT.
The TDA8707 is a CMOS triple 6-bit video low-power
analog-to-digital converter (ADC) for RGB signals. It
converts the analog inputs into 6-bit binary coded digital
words at a sampling rate of 35 MHz. All analog signal
inputs are clamped.
QUICK REFERENCE DATA
SYMBOL
V DDA
PARAMETER
CONDITIONS
MIN.
TYP.
analog supply voltage
4.5
5.0
V DDD
digital supply voltage
4.5
IDDA
analog supply current
IDDD
ILE
digital supply current
35
-
DC integral linearity error
OLE
DC differential linearity error
EB
effective bits
fclk
Ptot
maximum clock conversion rate
note 1
total power dissipation
note 2
MAX.
UNIT
5.5
V
5.0
5.5
V
50
-
mA
10
-
mA
-
±0.5
LSB
±0.5
LSB
5.3
bits
-
-
300
tbf
mW
MHz
Notes
1. The number of effective bits is measured with a clock frequency of 35 MHz. This value is given for a 4.43 MHz
frequency on the R, G and B channels.
2.
The external resistor (between VDDA and CLREF), fixing internal static currents, influences Ptot ' Its ~alue should be
15 kQ.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
PINS
TDA8707H
May 1994
44
I
I
PIN POSITION
I
I
QFP
3-813
MATERIAL
plastic
1
I
CODE
SOT307B
Philips Semiconductors
Preliminary specification
Triple RGB 6-bit video analog-to-digital
interface
TDA8707
BLOCK DIAGRAM
current reference
input (ClREF)
clamping input
(ClP)
clock input
(ClK)
VDDA1
V
SSA1
RED analog
input (INR)
RED data outputs
(RO to R5)
VDDA2
V
SSA2
GREEN analog
input (ING)
GREEN data outputs
(GO to G5)
VDDA3
V SSA3
BLUE analog
input (INB)
converter reference
HIGH input (CREFH)
converter reference
lOW input (CREFl)
BLUE data outputs
(80 to 85)
22
26
25
V
36
V DDD1
select input
buffer ratio (Sl1)
Fig.1 Block diagram.
May 1994
V DDD2
3-814
V
SSD1
SSD2
Preliminary specification
Philips Semiconductors
Triple RGB 6-bit video analog-to-digital
interface
TDA8707
PINNING
SYMBOL
n.c.
PIN
1
DESCRIPTION
not connected
n.c.
2
not connected
GO
3
GREEN data output; bit 0 (LSB)
GREEN data output; bit 1
G1
4
G2
5
GREEN data output; bit 2
G3
6
GREEN data output; bit 3
G4
7
GREEN data output; bit 4
G5
8
GREEN data output; bit 5 (MSS)
9
digital supply ground 1
10
clock input
V DD D1
11
digital supply voltage 1
n.c.
12
not connected
n.c.
13
not connected
BO
14
BLUE data output; bit 0 (LSB)
V SSD1
CLK
B1
15
BLUE data output; bit 1
B2
16
BLUE data output; bit 2
n.c.
17
not connected
B3
18
BLUE data output; bit 3
BLUE data output; bit 4
B4
19
B5
20
BLUE data output; bit 5 (MSB)
V SSD2
21
digital supply ground 2
V DD02
22
digital supply voltage 2
CLP
23
clamping input
CLREF
24
current reference level input for ADCs
CREFL
25
converter reference LOW level input
CREFH
26
converter reference HIGH level input
V OOA3
27
analog supply voltage 3
INB
28
BLUE analog input
V SSA3
29
analog supply ground 3
V OOA2
30
analog supply voltage 2
ING
31
GREEN analog input.
VSSA2
32
analog supply ground 2
V OOA1
33
analog supply voltage 1
INR
34
RED analog input
V SSA1
35
analog supply ground 1
select input buffer ratio
SLT
36
n.c.
37
not connected
RO
38
RED data output; bit 0 (LSB)
n.c.
39
not connected
R1
40
RED data output; bit 1
May 1994
3-815
Philips Semiconductors
Preliminary specification
Triple RGB 6-bit video analog-to-digital
interface
SYMBOL
PIN
TDA8707
DESCRIPTION
R2
41
RED data output; bit 2
R3
42
RED data output; bit 3
R4
43
RED data output; bit 4
R5
44
RED data output; bit 5 (MSB)
~
II)
~
a: a:
C?
a:
(\j
a:
t.i
0: r:
0
a:
t.i
r:
~
(f)
(f)
(f)
>
a:
~
index
corner
TDA8707
ClK
V DDD1
MGA920
0
r:
0
r:
0
co
co
(\j
co
0
r:
C?
co
~
co
II)
co
(\j
(\j
0
0
0
0
(f)
>(f)
>
Fig.2 Pin configuration.
May 1994
3-816
Preliminary specification
Philips Semiconductors
Triple RGB 6-bit video analog-to-digital
interface
TDA8707
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL
CONDITIONS
PARAMETER
MIN.
MAX.
UNIT
V OOA
analog supply voltage (pins 27, 30 and 33)
-0.3
+6.5
V
Vooo
digital supply voltage (pins 11 and 22)
-0.3
+6.5
V
~Voo
supply voltage difference between VOOA and Vooo
-0.5
+0.5
V
V,
input voltage (pins 28, 31 and 34)
referenced to V SSA
-
VO OA
V
Vi(p.p)
AC input voltage for switching
(pins 10 and 23; peak-to-peak value)
referenced to V sso
-
Vooo
V
T stg
storage temperature
-55
+150
°C
Tamb
operating ambient temperature
0
+70
°C
THERMAL CHARACTERISTICS
PARAMETER
thermal resistance from junction to ambient in free air
THERMAL RESISTANCE
75K/W
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
May 1994
3-817
Preliminary specification
Philips Semiconductors
Triple HGB 6-bit video analog-to-digital'
interface
TOA8707
CHARACTERISTICS (see Tables 1 and 2)
VDDA =VDDD =4.5 V to 5.5 V; VSSA and VSSD shorted together; VDDA - V DDD =-0.5 V to +0.5 V; T~mb =Oto +70 °C;
SLT :;: 0 V; CREFH =2.0 V, CREFL = 0.5 V; typical values measured at V qDA =VDDD = 5 V; VssA =V SSD =0 V and
T amb
=25°C; unless otherwise specified.
CONDITIONS
PARAMETER
SYMBOL
TYP.
MIN.
MAX.
Unit
Supply
V DDA
analog supply voltage
note 1
4.5
5.0
5.5
V
V DDD
digital supply voltage
note 1
4.5
5.0
5.5
V
IDDA
analog supply current
note 2
-
50
tbf
mA
IDDD
digital supply current
fclk
-
10
tbf
mA
=35 MHz
Inputs
DIGITAL INPUTS (ClK: PIN 10 AND ClP: PIN 23)
V il
LOW level input voltage
0
-
0.8,
V
V 1H
HIGH level input vo~age
2.0
VDDD
V
III
input leakage current
-10
-
+10
CI
input capacitance
-
7
-
~
pF
CLAMP AND REFERENCES (CLREF: PIN 24, CREFL: PIN 25 AND CREFH: PIN 26)
ACl
clamping accuracy
-
±0.5
-
LSB
ICl
input clamping current
-200
-
+400
CCl
external series clamping capacitor
10
22
~
nF
RClREF
external resistor on CLREF pin for
current reference of converter
note 2
12
15
-
VREFH
converter reference voltage HIGH
level applied to CREFH pin
referenced to VSSA
1.5
2.0
2.5
V
VREFl
converter reference voltage LOW
level applied to CREFL pin
referenced to V SSA
0.25
0.5
0.75
V
ilREF
reference voltage difference
between V REFH and V REFl
note 3
-
1.5
-
V
ZCREF
internal ladder impedance between
pins CREFH and CREFL
300
-
Q
-
1.0
-
V
-
0.75
-
V
-
5
100
nA
7
15
pF
-
-40
dB
-
1(3 00 )
kQ
ANALOG INPUTS (INR: PIN 34, ING: PIN 31 AND INB: PIN 28)
VI(p.p)
full-range input voltage
(peak-to-peak value)
II
input current
CI
input capacitance
UCT
crosstalk between INR, ING and INB
SLT =logic 0;
gain 1.5; note 4
=
SLT =logic 1;
gain =2.0; note 4
clamp off
INPUT ISOLATION
Outputs (RO to R5: pins 38 and 40 to 44; GO to G5: pins 3 to 8; 80 to 85: pins 14 to 16 and 18 to 20)
VOL
LOW level output voltage
0
VOH
HIGH level output voltage
tbf
May 1994
3-818
-
tbf
V
VDDD
V
Preliminary specification
Philips Semiconductors
Triple RGB 6-bit video analog-to-digital
interface
SYMBOL
PARAMETER
TDA8707
CONDITIONS
MIN.
TYP.
MAX.
Unit
Analog signal processing (see Fig.S)
Gdiff
differential gain
note 5
-
tbf
qJdiff
differential phase
note 5
-
tbf
-
deg
f1
fundamental harmonic
note 6
-
fall
harmonics, all components
note 6
-
-
0
dB
-32
-
dB
-
±0.5
LSB
±O.5
LSB
±1.0
LSB
5.3
-
bits
MHz
-
-
-
16
ns
-
ns
%
Transfer function (50% duty factor)
ILE
DC integral linearity error
DLE
DC differential linearity error
AILE
AC integral linearity error
note 7
-
EB
effective bits
note 8
-
Timing (see Fig.3, 4 and 6)
fclk(max)
maximum clock frequency
35
-
tcPH
clock pulse width HIGH
11
-
tCPL
clock pulse width LOW
11
tdS
sampling delay time
-
th
output hold time
6
td
output delay time
tr
clock rise time
3
5
tl
clock fall time
3
5
tCLP
active clam ping duration
3
4
note 9
-
-=0..
'~~fJ
I
J.r7
ns
ns
ns
ns
ns
fls
Notes
1.
2.
V OOA and Vooo should be supplied from the same power supply and decoupled separately.
The analog supply current is directly proportional to the series resistance between V OOA and CLREF.
3.
CREFH and CREFL are connected respectively to the top and bottom reference ladders of the 3 analog-to-digital
converters.
4.
V1(p_p) = (VREFL - VREFH)/buffer gain factor. See Table 2 for gain factor selection. When clamping at code 0 is used,
active video signal am plitude V ACT should be:
=
V
ACT
(VREFH-VREFL)
buffer gain factor
5.
Low frequency ramp signal (V1(p-p) = full scale and 64 fls period) combined with a sine wave input voltage.
V1(p_p) = 0.3 V, fi = maximum allowed input frequency; see Fig.5
=~REF with fi =4.43 MHz.
6.
V1(p_p)
7.
Fu" scale input sine wave; fi = 4.43 MHz, fCLK = 35 MHz.
8.
The number of effective bits is measured with a clock frequency of 35 MHz. This value is given for a 4.43 MHz input
frequency.
9.
Output data acquisition: output data is available after the maximum delay time of td.
May 1994
3-819
Preliminary specificatiori
Philips Semiconductors
Triple RGB 6-bit video analog-to-digital
interface
Table 1 Output coding (VREFH
TDA8707
=2.0 V; VREFL =0.5 V referenced to V SSA • SLT =~O V; buffer ratio =1.5).
BINARY OUTPU.T BITS
STEP
VI (p-p)
-
<0.333
=VREFL/1.5
05
04
03
02
01
00
0
0
0
0
0
0
0
0.349
0
0
0
0
0
0
1
0.364
0
0
0
0
0
1
62
1.317
1
1
1
1
1
0
63
1.333
1
1
1
1
1
1
1
1
1
1
1
1
-
>1.333
=VREFW1.5
Table 2 Mode selection.
May 1994
SLT
BUFFER RATIO
VI(p_p) FULL SCALE
0
1.5
(VREFH- V REF d/1.5
1
2.0
(VREFH - VREFL)/2.0
. 3-820
Preliminary specification
Philips 8em iconductors
Triple RGB 6-bit video analog-to-digital
interface
TDA8707
TIMING DIAGRAMS
ClK
",j.0
INY, U, V
2.4 V
DATA
1.4V
DO to D5
0.4 V
MLB759
Fig.3 Input timing.
digital
output
level
63
black-level
clamping
..
_time
rl~--------------
ClP_________________
-11tClP
Fig.4 Clamp timing.
May 1994
3-821
MGA922
Preliminary specification
Philips Semiconductors
Triple, RGB 6-bit video analog-to-digital'
interface
TDA8707
RGB"channels: 4.43 MHz sine wave -
2V
1.0---___
...
"--___ 64I-!S-------~..,.. 1
MGA923
Fig.5 Differential gain and phase measurements.
test probe TEK
P6201
DO to D5
-
1---_--+
151
PFI
MGA924
Fig.6 Load circuit for timing measurements.
May 1994
3-822
Philips Semiconductors
Preliminary specification
Triple RGB 6-bit video analog-to-digital
interface
TDA8707
INTERNAL CIRCUITRY
V DDD
VSSD
V SSA V SSA
(a)
(b)
VDDD
I
I
I
VSSA
)--
~
VSSA
VSSD
MGA925
(c)
(d)
(a) Digital inputs; pins 10, 23 and 36.
(b) Analog inputs; pins 28, 31 and 34.
(c) Current reference; pin 24.
(d) Digital outputs; pins 3 to 8,14 to 16, 18 to 20 and 40 to 44.
Fig.7 Internal circuitry.
May 1994
3-823
Preliminary specification
Philips Semiconductors
Triple RGB 6-bit video analog-to-digital
interface
TDA8707
APPLICATION INFORMATION
R5
R4
R3
R2
R1
n.c.
RO
SlT
100 nF
V DDA1
n.c.
33
n.c.
32
GO
31
G1
30
G2
29
ING
TDA8707
28
I-- GREEN
100 nF
VD DA2
INB
22 nF
I-- BLUE
VDDA3
G4
27
G5
26
25
ClK
VDDD1
CREFH
2V
2.2 nF
VSSD1
CREFl
ClREF
10
24
11
23
12
13
14
15
16
17
18
19
20
21
22
V SSD2 VDDD2
n.c,
BO
B1
B2
B3
B4
B5
100
nF
MGA926
5V
Analog and digital supplies should be separated and decoupled.
Supplies are not connected internally; also applicable to grounds.
The intemal reference currents are set by the series resistor between pin
The resistor value should be in the range of 12 kQ and 15 kQ.
VDDA
and ClREF.
It is recommended. if possible. to connect pins 1. 2.12.13.17.37 and 39 to V SSD '
Fig.8 Application diagram.
May 1994
22 nF
VSSA3
G3
100
nF
VSSA2
3-824
0.5V
15kn
ClP
5V
Product specification
Philips Semiconductors
TDA8708A
Video analog input interface
FEATURES
APPLICATIONS
• 8-bit resolution
• Video signal decoding
• Sampling rate up to 32 MHz
• Scrambled TV (encoding and decoding)
• Binary or two's complement 3-state TTL outputs
• Digital picture processing
• TTL-compatible digital inputs and outputs
• Frame grabbing.
• Internal reference voltage regulator
• Power dissipation of 365 mW (typical)
GENERAL DESCRIPTION
• Input selector circuit (one out of three video inputs)
The TDA8708A is an analog input interface for video signal
processing. It includes a video amplifier with clamp and
gain control, an 8-bit analog-to-digital converter (ADC)
with a sampling rate of 32 MHz and an input selector.
• Clamp and Automatic Gain Control (AGC) functions for
CVBS and Y signals
• No sample-and-hold circuit required.
• The TDA8708A has white peak control in modes 1 and
2 whereas the TDA8708B has control in mode 1 only.
QUICK REFERENCE DATA
SYMBOL
VCCA
MIN.
PARAMETER
analog supply voltage
TYP.
UNIT
MAX.
4.5
5.0
5.5
V
VCCD
digital supply voltage
4.5
5.0
5.5
V
Vcco
TTL output supply voltage
4.2
5.0
5.5
V
ICCA
analog supply current
37
45
rnA
Iceo
digital supply current
-
24
30
rnA
Icco
TTL output supply current
-
12
16
rnA
±1
LSB
ILE
DC integral linearity error
-
DLE
DC differential linearity error
-
-
±0.5
LSB
fclk(max)
B
maximum clock frequency
30
32
-
MHz
maximum -3 dB bandwidth (AGC amplifier)
12
18
-
MHz
Ptot
total power dissipation
-
365
500
mW
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
PINS
PIN POSITION
MATERIAL
CODE
TDA8708A
28
DIP
plastic
SOT117-1
TDA8708AT
28
S028L
plastic
SOT136-1
June 1994
3-825
Product specification
Philips Semiconductors
Video analog input interface
TDA8708A
BLOCK DIAGRAM
video input
selection bit 0
video input
selection bit 1
analog
voltage
output
VIDEO
19
clock
input
ADC
input
decoupling
input
TTL outputs V CCO (+ 5 V)
20
output forma!/
chip enable
(3-state input)
video input 0
video input 1
D7
video input 2
D6
clamp capacitor - 1 - - - - - - - - - 1
connection
AG:C:::~ii~~ -I...::..=_-----l---.-J
TTL
OUTPUTS
TDA8708A
D5
D4
D3
D2
D1
AGC &
CLAMP
LOGIC
&
MODE
SELECTION
peak level current
resistor input
PEAK LEVEL
DIGITAL COMPARATOR
DO
BLACK LEVEL
DIGITAL COMPARATOR
28
L-_ _-!_ _ _ _~:....----I-----~---_+::::....---~:....----..J MBB965
sync level
sync pulse
black level
sync pulse
digital V CCD
(+5V)
digital
ground
analogVCCA
(+ 5 V)
Fig.1 Block diagram.
June 1994
3-826
analog
ground
Product specification
Philips Semiconductors
TDA8708A
Video analog input interface
PINNING
SYMBOL
D7
PIN
1
DESCRIPTION
data output; bit 7 (MSB)
D6
2
data output; bit 6
D5
3
data output; bit 5
D4
4
data output; bit 4
ClK
5
clock input
V CCD
6
digital supply voltage (+5 V)
RPEAK
Vcco
DGND
7
TIL outputs supply voltage (+5 V)
GATE A
8
digital ground
GATEB
OF
9
output format/chip enable
(3-state input)
AGC
CLAMP
D3
10
D2
11
data output; bit 3
data output; bit 2
AGND
D1
12
data output; bit 1
VCCA
DEC
DO
13
data output; bit 0 (lSB)
10
14
video input selection bit 0
11
15
video input selection bit 1
VINO
16
video input 0
VIN1
17
video input 1
VIN2
18
video input 2
ANOUT
19
analog voltage output
ADCIN
20
analog-to-digital converter input
DEC
21
decoupling-input
VCCA
22
analog supply voltage (+5 V)
AGND
23
analog ground
CLAMP
24
clamp capacitor connection
AGC
25
AGC capacitor connection
GATEB
26
black level synchronization pulse
GATE A
27
sync level synchronization pulse
RPEAK
28
peak level current resistor input
June 1994
ADCIN
D3
ANOUT
D2
VIN2
D1
VIN1
DO
VINO
M88964
Fig.2 Pin configuration.
3-827
Product specification
Philips Semiconductors
TDA8708A
Video analog input interface
FUNCTIONAL DESCRIPTION
The TDA8708A provides a simple interface for decoding
video signals.
The TDA8708A operates in configuration mode 1 (see
Fig.4) when the video signals are weak (Le. when the gain
of the AGC amplifier has not yet reached its optimum
value). This enables a fast recovery of the synchronization
pulses in the decoder circuit. When the pulses at the
GATE A and GATE B inputs become distinct (GATE Aand
GATE B pulses are synchronization pulses occurring
during the sync period and rear porch respectively) the
TDA8708A automatically switchesto configuration mode 2
(see Fig.5).
When the TDA8708A is in configuration mode 1, the gain
oftheAGC amplifier will be roughly adjusted (sync level to
a digital output level of 0 and the peak level to a digital
output level of 255).
In configuration mode 2 the digital output of the ADC is
compared to internal digital reference levels. The resultant
outputs control the charge or discharge current of a
capacitor connected to the AGC pin. The voltage across
this capacitor controls the gain of the video amplifier. This
is the gain control loop.
The sync level comparator is active during a positive-going
pulse at the GATE A input. This means that the sync pulse
of the composite video signal is used as an amplitude
reference. The bottom of the sync pulse is adjusted to
obtain a digital output of logic 0 at the converter output. As
the black level is at digital level 64, the sync pulse will have
a digital amplitude of 64 LSBs.
The peak-white control loop is always active. If the video
signal tends to exceed the digital code of 248, the gain will
be limited to avoid any over-range of the converter.
The use of nominal signals will prevent the output from
exceeding a digital code of 213 and the peak-white control
loop will be non-active.
The clamp level control is accomplished by using the same
techniques as used for the gain control. The black-level
digital comparator is active during a positive-going pulse at
the GATE B input. The clamp capacitor will be charged or
discharged to adjust the digital output to code 64.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VCCA
V CCD
analog supply voltage
-0.3
+7.0
V
digital supply voltage
-0.3
+7.0
V
Vcca
output supply voltage
-0.3
+7.0
V
""Vce
supply voltage difference between V CCA and V cco
-1.0
+1.0
V
supply voltage difference between Vcco a:nd Vcco
-1.0
+1.0
V
supply voltage difference between V CCA and V cco
-1.0
+1.0
V
VI
input voltage
-0.3
VCCA
V
mA
10
output current
0
+10
T stg
storage temperature
-55
+150
°C
Tamb
Tj
operating am bient tem perature
0
+70
°C
junction temperature
0
+125
°C
THERMAL CHARACTERISTICS
SYMBOL
Rthj-a
June 1994
PARAMETER
VALUE
UNIT
SOT117-1
55
SOT136-1
70
K!W
K!W
thermal resistance from junction to ambient in free air
3-828
Product specification
Philips Semiconductors
TDA8708A
Video analog input interface
CHARACTE RISTICS
VCCA = V 22 to V 23 =4.5 to 5.5 V; VCCD = V6 to V8 = 4.5 to 5.5 V; Vcco =V 7 to V8 = 4.2 to 5.5 V; AGND and DGND
shorted together; VCCA to V CCD = -0.5 to +0.5 V; Vcco to V CCD = -0.5 to +0.5 V; V CCA to Vcco =-0.5 to +0.5V;
Tamb
= 0 to +70 °C; typical readings taken at VCCA =V CCD =Vcco =5 V and Tamb =25°C; unless otherwise specified.
CONDITIONS
PARAMETER
SYMBOL
TYP.
MIN.
MAX.
UNIT
Supplies
VCCA
analog supply voltage
4.5
5.0 .
5.5
V
V CCD
digital supply voltage
4.5
5.0
5.5
V
Vcco
TTL output supply voltage
4.2
5.0
5.5
V
ICCA
analog supply current
-
37
45
rnA
Iceo
digital supply current
24
30
rnA
Icco
TTL output supply current
-
12
16
rnA
0.6
-
1.5
V
TTL load (see Fig.8)
Video amplifier inputs
VIN(O TO 2) INPUTS
VI(p_p)
input voltage (peak-to-peak value)
AGC load with external
capacitor; note 1
IZil
input im pedance
fi
CI
input capacitance
fi
= 6 MHz
= 6 MHz
10
20
-
kQ
-
1
-
pF
10 AND 11 TTL INPUTS (SEE TABLE 1)
V IL
LOW level input voltage
0
-
0.8
V
V IH
HIGH level input voltage
2.0
-
V CCD
V
IlL
LOW level input current
-400
-
-
IIH
HIGH level input current
-
-
20
iJ.A
iJ.A
= 0.4 V
VI = 2.7V
VI
GATE A AND GATE B TTL INPUTS (SEE FIGS 4 AND 5)
V IL
LOW level input voltage
0
-
0.8
V
V IH
HIGH level input voltage
2.0
-
V CCD
V
IlL
LOW level input current
-400
-
iJ.A
IIH
tw
HIGH level input current
= 0.4 V
VI = 2.7V
-
pulse width
see Fig.5
2
-
=0 Q
-
80
-
VI
20
iJ.A
-
iJ.s
150
iJ.A
2.8
-
V
4.0
-
V
-
V
RPEAK INPUT (PIN 28)
128 (min)
minim urn peak level current
R28
AGC INPUT (PIN 25)
V25 (min)
AGC voltage for minimum gain
V25 (maX)
AGC voltage for maximum gain
AGC output current
see Table 2
CLAMP INPUT (PIN 24)
V 24
clamp voltage for code 128 output
124
clamp output current
June 1994
-
3.5
see Table 3
3-829
Product specification
Philips Semiconductors
TDA8708A
Video analog input interface
PARAMETER
SYMBOL
TYP.
MIN.
CONDITIONS
MAX.
UNIT
Video amplifier outputs
ANOUT OUTPUT (PIN 19)
V 19 (P-P)
AC output voltage
(peak-to-peak value)
VVIN = 1.33 V (p-p);
V 25 = 3.6 V
-
1.33
-
V
119
internal current source
RL =
2.0
2.5
-
mA
lo(p_p)
output current driven by the load
V ANOUT = 1.33 V (p-p);
note 2
-
-
1.0
mA
V 19
DC output voltage for black level
note 3
-
VCCA -2.24
-
V
Z19
output impedance
-
20
-
Q
00
~
Video amplifier dynamic characteristics
act
crosstalk between VIN inputs
VCCA = 4.75 to 5.25 V
-
-50
-45
dB
Gdiff
differential gain
VVIN = 1.33 V (p-p);
V25 = 3.6 V
-
2
-
%
(jJdiff
differential phase
VVIN = 1.33 V (p-p);
V 25 = 3.6 V
-
0.8
-
deg
12
note 4
60
-
dB
SIN
signal-to-noise ratio
SVRR1
supply voltage ripple rejection
note 5
-
45
-
LlG
gain range
see Fig.10
-4.5
-
+6.0
dB
G Stab
gain stability as a function of supply
voltage and temperature
see Fig.1 0
-
-
5
%
B
-3 dB bandwidth
MHz
dB
Analog-to-digital converter inputs
ClK INPUT (PIN 5)
V IL
lOW level input voltage ,
0
-
0.8
V
V IH
HIGH level input voltage
2.0
-
V CCD
V
IlL
lOW level input current
V clk = 0.4 V
-400
-
-
I-tA
IIH
HIGH level input current
Vclk
-
100
!Zi!
CI
input impedance
fclk= 10 Mrlz
4
fclk = 10 MHz
-
I-tA
kQ
input capacitance
-
=2.7V
4.5
pF
OF INPUT (3-STATE; SEE TABLE 4)
VIL
lOW level input voltage
0
-
0.2
V
V IH
HIGH level input voltage
2.6
-
V CCD
V
V9
input voltage in high impedance state
-
1.15
-
V
IlL
lOW level input current
-370
-300
-
I-tA
IIH
HIGH level input current
-
300
450
I-tA
June 1994
3-830
Product specification
Philips Sem iconductors
TDA8708A
Video analog input interface
SYMBOL
PARAMETER
CONDITIONS
TYP.
MIN.
MAX.
UNIT
ADCIN INPUT (PIN 20; SEE TABLE 5)
V20
input voHage
digital output
V20
input voHage
digital output
V20 (p-P)
input voHage amplitude
(peak-to-peak value)
120
input current
IZil
input im pedance
CI
input capacitance
=00
=255
=6 MHz
fj =6 MHz
fi
-
VC CA - 2.42
-
LO
-
LO
10
ftA
50
-
MQ
V CCA -1.41
1
-
V
V
V
pF
Analog-to-digital converter outputs
DIGITAL OUTPUTS DO TO D7
VOL
LOW level output voltage
IOL
VOH
HIGH level output voltage
10L
=2 rnA
=-0.4 rnA
2.4
loz
output current in 3-state mode
O.4V2.7 kQ.
b) The load impedance should be coupled directly to the output of the amplifier so that the DC voltage supplied by
the clamp is not disturbed.
3.
Control mode 2 is selected.
4.
Signal-to-noise ratio measured with 5 MHz bandwidth:
§ = 20 log
N
5.
V ANOUTC(p- p) at B
V ANOUTY (RMS noise)
= 5 MHz.
The voltage ratio is expressed as:
SVR R 1 =20 log Il.VVCCA x
CCA
Il.~
for VI = 1 V (p-p), gain at 100 kHz = 1 and 1 V supply variation.
~2
6.
It is recommended that the rise and fall times of the clock are
analog grounds is recommended.
7.
These measurements are realized on analog signals after a digital-to-analog conversion (TDA8702 is used).
8.
The supply voltage rejection is the relative variation of the analog signal (full-scale signal at input) for 1 V of supply
variation:
SVRR2 =
9.
Il.(VI(OO) -VI(FF») + (VI(OO) -VI(FF»)
Il.V
CCA
Full-scale sine wave (fi = 4.4 MHz; fclk = 27 MHz).
June 1994
3-832
ns. In addition, a 'good layout' for the digital and
Product specification
Philips Semiconductors
TDA8708A
Video analog input interface
Table 1 Video input selection (CVBS).
Table 3 CLAMP output current.
11
10
SELECTED INPUT
0
0
VINO
0
1
VIN1
1
0
VIN2
1
1
VIN2
MODE
output < 0
ICLAMPM
1
-2.5 ""A
1
0
output> 0
X(1)
O~
2
1
output < 64
+ 5O rtA
-50 rtA
2
GATEB
1
1
X(1)
0
Table 2 AGC output current.
GATE A GATEB
1
1
0
X(1)
64 < output
DIGITAL
OUTPUT
IAGC
MODE(2)
output < 255
-2.5~
1
output> 255
IAGCM
OrtA
1
output < 248
Table 4 OF input coding.
0< output <
248
-2.5rtA
2
output> 248
IAGCM
2
DO TO 07
OF
2
2
output < 0
0
=don't care.
2
IAGCM
+2.5 rtA
2
Note
1. X
output> 248
1
DIGITAL
OUTPUT
ICLAMP
GATE A
0
active, two's complement
1
high impedance
open circuit(1)
active, binary
Note
1.
Note
UseC~10pFtoDGND.
= don't care.
1.
X
2.
Mode 2 can only be initialized with successive pulses
on GATE A and GATE B (see Fig.5).
Table 5 Output coding and input voltage (typical values).
BINARY OUTPUTS
STEP
VADCIN
07
06
05
04
03
TWO'S COMPLEMENT
02
01
DO
07
06
05
04
03
02
01
DO
Underflow
-
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
VCCA - 2.41 V
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
-
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
254
-
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
255
VCCA - 1.41 V
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
Overflow
-
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
June 1994
3-833
Product specification'
Philips Semiconductors
TDA8708A
Video analog input interface
1.0V
1.>--_______
...
64 11 ---------..,1'.,
5
MBB959
Fig.3 Test signal on the ADCIN pin for differential gain and phase measurements.
digital
output
level
MBB969
t
PE1ak-level gain control
~5
----------------------
black-level
clamping
sync-level gain control ,
O~----------~~I----------------------GATEA
---+ time
~
GATEB
MODE 1
Fig.4 Control mode 1.
June 1994
3-834
Product specification
Philips Semiconductors
Video analog input interface
TDA8708A
digital
output
level
MBB970
t
248
213
64
- - - - - - - - - - - - - - - - - - - - - -r----I- - - - - peak-level gain control
----------------------
~~~~~
black-level
clamping
sync-level control
O~---------------------~--------------------------------------_time
GATE A
GATEB
MODE2
Fig.5 Control mode 2.
ClK
input
analog
input
(ADCIN)
...
~---+-
J------,
~--- 2.4 V
data
O.4V
Fig.6 Timing diagram for data output.
June 1994
3-835
Product specification
Philips Semiconductors
Video analog input interface
TDA8708A
open
OF
input
2.4 V
data
outputs
(DO to D7)
0.4 V
Fig.7 Output format timing diagram.
Veeo
DOtoD71--_--H~1--4
IN916
or
IN3064
DGND
Fig.8 Load circuit for timing measurement; data outputs(GP
June 1994
3-836
= LOW or open-circuit).
Product specification
Philips Semiconductors
TDA8708A
Video analog input interface
00 to 07 t-----t"-.---t-M-t-----.
IN916
or
IN3064
I
MBB955
S2
OGNO
Fig.9 Load circuit for timing measurement; 3-state outputs (OF: fi
MSA676
12
G
(dB)
...
5%
/} 'i"
- 1--=
~;~/
~I
~
-4
=-=
vi?
~
M
//
(1)
(2)
~ :"
-8
2.6
3.4
3.8
4.2
4.6
V 25 (V)
(1) Typical value 01ccA = VCCD = 5 V; Tamb = 25°C).
(2) Minimum and maximum values (temperature and supply).
Fig.10 Gain control CUNeo
June 1994
3-837
=1 MHz; VOF =3 V).
Z
--~.------
<-
c
~
m
CD
:lJ
Z
-I
cr;
.j>.
pins 26 or 27
GATE A or GATE B
pin 26
RPEAK
pins 1 to 4
and10t013
data outputs
II
I ....
~
~
'ReEAK
f
l>
r-
pin 25
AGC
"0
Z
I "T ., ., ~
J
VCCD
0
VCCA
jj
0
GYtW-+"",
...
CCD
V
pin 7
VCCO
1"
pin 22
VCCA
pin 24
CLAMP
c
=i
~
""0
<
~
-5'
CD
0
0>
(J)
0.:
:::J
0>
0
(Q
5
(f)
CD
3
(';0
~
0.
c
5l
0
0
CD
pin 5
clock input
~
VJ
c»
VJ
(Xl
TDA8708A
•
v~~~
pin 9
OF
,lIt
r">- ~~n..~~! ___,____"
10,11
' I 1l1li T ~I ~I ,
I.IA
1'1,'1
All?
+
pin 8
DGND
pin 23
AGND
VCCA
I
pins 14 and 15
('
VCCA
c::J--f
""0
MBB971
pins 16to 18
VINO, VIN1 and VIN2
pin 19
AN OUT
pin 20
ADCIN
pin 21
DEC
--I
o
~
-.....J
o
Fig.11 Internal pin configuration.
~
a
0.
C
5l
(f)
'0
CD
(")
~
O·
~
O·
~
Product specification
Philips Semiconductors
Video analog input interface
TDA8708A
APPLICATION INFORMATION
Additional information can be found in the laboratory report "FBUAN9308".
330Q
28
horizontal sync
27
data outputs
horizontal clamp
26
220nF
100 Q
!
H
25
18 nF
33 pF
clock
H
24
6
23
+5V
22
22 nF
1 ",H
+5V
TDA8708A
8
21
1 !-IF
20
J; 10 pF
LOW PASS
FILTER
10
19
11
18
12
17
13
16
(2)
tQ
to
4.7 !-IF
data outputs
4.7 !-IF
W
15Q'
MBB967·1
(1)
It is recommended to decouple Veeo through a 22 Q resistor especially when
the output data of TDA8708A interfaces with a capacitive CMOS load device.
(2) See Figs 13 and 15 for exam pies of the low-pass filters.
Fig.12 Application diagram.
June 1994
3-839
Product specification
Philips Semiconductors
TDA8708A
Video analog input interface
ANOUT
I - _ ' - - - H -.......-
(pin 19)
ADCIN
...ft...~r-+--_--,-....... (pin 20)
VCCA
(pin 22)
This filter can be adapted to various applications with respect to performance requirements. An input and output impedance of at least 680 Q and 2.2 kQ
must in any event be applied.
Fig.13 Example of a low . . pass filter for CVBS and Y signals.
Characteristics of Fig. 13
• Order 5; adapted CHEBYSHEV
MSA6B2
"\
(dB)
• Ripple p s 0.4 dB
• f
\
-40
1\
/
r
\I
-80
-120
-160
o
10
20
f (MHz)
30
Fig.14 Frequency response for filter shown in
Fig.13.
June 1994
= 6.5 MHz at -3 dB
= 9.75 MHz.
• fnotch
3... 840
Product specification
Philips Semiconductors
TDA8708A
Video analog input interface
680
ADOUT
(pin 19)
Q
82
JlH
ADCIN
(pin 20)
r
Vi
Vo
VCCA
(pin 22)
This filter can be adapted to various applications with respect to performance requirements. An input and output impedance of at least 680 Q and 2.2 kQ
must in any event be applied.
Fig.15 Example of an economical low-pass filter for CVBS and Y signals.
Characteristics of Fig. 15
• Order 5; adapted CHEBYSHEV
(dB)
- --...
MSA681
1\
\
-10
\
\
-20
'"
-30
-40
• Ripple p :5 0.4 dB
• f
"~
"" "o
10
20
.........
f (MHz)
"
30
Fig.16 Frequency response for filter shown in Fig.15.
June 1994
3-841
= 6.5 MHz at
-3 dB.
Product specification
Philips Se,miconductors
TDA87088
Video analog input interface
FEATURES
APPLICATIONS
• 8-bit resolution
• Video signal decoding
• Sampling rate up to 32 MHz
• Scrambled TV (encoding and decoding)
• Binary or two's complement 3-state TTL outputs
• Digital picture processing
• TTL-compatible digital inputs and outputs
• Frame grabbing.
• Internal reference voltage regulator
• Power dissipation of 365 mW (typical)
GENERAL DESCRIPTION
• Input selector circuit (one out of three video inputs)
The TDA8708B is an analog input interface for video signal
processing. It includes a video amplifier with clamp and
gain control, an 8-bit analog-to-digital converter (ADC)
with a sampling rate of 32 MHz and an input selector.
• Clamp and Automatic Gain Control (AGC) functions for
CVBS and Y signals
• No sample-and-hold circuit required
• The TDA8708B has no white peak control in mode 2
whereas the TDA8708A has control in modes 1 and 2.
• In-range output (not TTL levels).
QUICK REFERENCE DATA
SYMBOL
PARAMETER
TYP.
MIN.
UNIT
MAX.
analog supply voltage
4.5
5.0
5.5
V
VCCD
digital supply voltage
4.5
5.0
5.5
V
Vcco
TTL output supply voltage
4.2
5.0
5.5
V
ICCA
analog supply current
37
45
rnA
ICCD
digital supply current
24
30
rnA
Icco
ILE
TTL output supply current
12
16
rnA
-
±1
LSB
±0.5
LSB
32
-
MHz
V CCA
DLE
DC differential linearity error
-
fclk(max)
B
maximum clock frequency
30
maximum -3 dB bandwidth (AGC amplifier)
12
18
-
MHz
Ptot
total power dissipation
-
365
500
mW
DC integral linearity error
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
PINS
PIN POSITION
MATERIAL
CODE
TDA8708B
28
DIP
plastic
80T117-1
TDA8708BT
28
S028L
plastic
SOT136-1
June 1994
3-842
Product specification
Philips Semiconductors
TDA8708B
Video analog input interface
BLOCK DIAGRAM
video input
selection bit 0
analog
voltage
output
video input
selection bit 1
ADC
input
19
clock
input
decoupling
input
TTL outputs VCCO (+ 5 V)
20
output format!
chip enable
(3-state input)
D7
video input 0
video input 1
video input 2
D6
clamp capacitor
connection
D5
AGC capacitor
connection
TTL
OUTPUTS
TDA8708B
D4
D3
D2
D1
PEAK LEVEL
DIGITAL COMPARATOR
AGC&
CLAMP
LOGIC
&
MODE
SELECTION
in-range
output
BLACK LEVEL
DIGITAL COMPARATOR
28
~
____-+________
sync level
sync pulse
~
______
black level
sync pulse
~
________
digital V CCD
(+ 5V)
~
______
digital
ground
Fig.1 Block diagram.
June 1994
DO
3-843
~
________
analog VCCA
(+ 5V)
~
______
analog
ground
~MSA6~
Product specification
Philips Semiconductors
Video analog input interface
TDA8708B
PINNING
SYMBOL
PIN
DESCRIPTION
1
data output; bit 7 (MSS)
D6
2
data output; bit 6
D5
3
data output; bit 5
D4
4
data output; bit 4
ClK
5
clock input
V CCD
6
digital supply voltage (+5 V)
Vcco
DGND
7
TTL outputs supply voltage (+5 V)
8
digital ground
OF
9
output formaVchip enable
(3-state input)
D7
D3
10
data output; bit 3
D2
11
data output; bit 2
D1
12
data output; bit 1
DO
13
data output; bit 0 (lSS)
10
14
video input selection bit 0
IR
GATE A
GATEB
AGC
CLAMP
AGND
VCCA
DEC
ADCIN
11
15
video input selection bit 1
D3
VIN2
ANOUT
VINO
16
video input 0
D2
VIN1
17
video input 1
D1
VIN1
VIN2
18
video input 2
DO
VINO
ANOUT
19
analog voltage output
ADCIN
20
analog-to-digital converter input
DEC
21
decoupling input
VCCA
AGND
22
analog supply voltage (+5 V)
23
analog ground
CLAMP
24
clamp capacitor connection
AGC
25
AGC capacitor connection
GATES
26
black level synchronization pulse
GATE A
27
sync level synchronization pulse
IR
28
in-range output
June 1994
MSA671
Fig.2 Pin configuration.
3c844
Philips Semiconductors
Product specification
TDA8708B
Video analog input interface
across the capacitor connected to the AGC pin controls the
gain of the video amplifier. This is the gain control loop.
FUNCTIONAL DESCRIPTION
The TDA8708B provides a simple interface for decoding
video signals.
The TDA8708B operates in configuration mode 1
(see Fig.4) when the video signals are weak (Le. when the
gain of the AGC am plifier has not yet reached its optim urn
value). This enables a fast recovery of the synchronization
pulses in the decoder circuit. When the pulses at the
GATE Aand GATE B inputs become distinct (GATE Aand
GATE B pulses are synchronization pulses occurring
during the sync period and rear porch respectively) the
TDA8708B automatically switches to configuration mode 2
(see Fig.5).
When the TDA8708B is in configuration mode 1, the gain
of the AGC amplifier will be roughly adjusted (sync level to
a digital output level of 0 and the peak level to a digital
output level of 255).
The sync level comparator is active during a positive-going
pulse at the GATE A input. This means that the sync pulse
of the composite video signal is used as an amplitude
reference. The bottom of the sync pulse is adjusted to
obtain a digital output of logic 0 at the converter output. As
the black level is at digital level 64, the sync pulse will have
a digital amplitude of 64 LSBs.
The use of nominal signals will prevent the output from
exceeding a digital code of 213.
The clamp level control is accomplished by using the same
techniques as used for the gain control. The black-level
digital comparator is active during a positive-going pulse at
the GATE B input. The clamp capacitor will be charged or
discharged to adjust the digital output to code 64.
In configuration mode 2 the digital output of the ADC is
compared to internal digital reference levels. The voltage
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MAX.
MIN.
UNIT
analog supply voltage
-0.3
+7.0
V
Vcco
digital supply voltage
-0.3
+7.0
V
Veea
TTL output supply voltage
-0.3
+7.0
V
t:Nce
supply voltage difference between V CCA and V cco
-1.0
+1.0
V
supply voltage difference between Vcca and Vcco
-1.0
+1.0
V
supply voltage difference between V CCA and V cca
-1.0
+1.0
V
input voltage
-0.3
VceA
V
rnA
VCCA
VI
la
output current
0
+10
T stg
storage temperature
-55
+150
°C
Tamb
operating ambient temperature
0
+70
°C
Tj
junction temperature
0
+125
°C
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
June 1994
PARAMETER
VALUE
UNIT
SOT117-1
55
SOT136-1
70
K!W
K!W
thermal resistance from junction to ambient in free air
3-845
Product specification
Philips Semiconductors
TDA87088
Video .analog input interface
CHARACTERISTICS
VCCA = V 22 to V23'~ 4.5 to 5.5 V; VCCD = V6 to Va = 4.5 to 5.5 V; Vcco = V7 to Va = 4.2 t<;> 5.5 V; AGND andDGND
shorted together; VCCA to V CCD = -0.5 to +0.5 V; Vcco to VCCD -0.5 to +0.5 V; VCCA to Vcco = -0.5 to +0.5 V;
Tamb = 0 to +70 °C; typical readings taken at VCCA
=
=VCCD = Vcco = 5 V and Tamb = 25 °C; unless otherwise specified.
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VCCA
analog supply voltage
4.5
5.0
5.5
V
VCCD
digital supply voltage
4.5
5.0
5.5
V
Vcco
TTL output supply voltage
4.2
5.0
5.5
V
ICCA
analog supply current
-
37
45
rnA
ICCD
digital supply current
24
30
rnA
Icco
TTL output supply current
-
12
16
rnA
0.6
-
1.5
V
10
20
1
-
kQ
-
TTL load (see Fig.8)
Video amplifier inputs
VINO TO VIN2 INPUTS
VI(p.p)
input voltage (peak-to-peak value)
AGC load with external
capacitor; note 1
IZil
CI
input impedance
fj
input capacitance
fj = 6 MHz
=6 MHz
pF
10 AND 11 TTL INPUTS (SEE TABLE 1)
V IL
LOW lever input vortage
0
-
0.8
V
VIH
HIGH level input voltage
2.0
VCCD
V
IlL
LOW level input current
VI = 0.4 V
-400
-
-
fAA
IIH
HIGH level input current
VI=2.7V
-
-
20
fAA
-
0.8
V
GATE A AND GATE B TTL INPUTS (SEE FIGS 4 AND 5)
V IL
LOW revel input voltage
0
V IH
HIGH level input voltage
2.0
, IlL
LOW
lev~1 input current
VI
=0.4 V
-400
IIH
HIGH level input current
VI=2.7V
-
tw
pulse width
see Fig.5
2,
VCCD
V
-
-
fAA
20
fAA
-
fAs
2.8
-
V
-
V
AGC INPUT (PIN 25)
V 25 (min)
AGC voltage for minimum gain
V 25 (maX)
AGC voltage for maximum gain
-
AGC output current
4.0
V
see Table 2
CLAMP INPUT (PIN 24)
V 24
clamp voltage for code 128 output
124
clamp output current
June 1994
-
3.5
see Table 3
3-846
Product specification
Philips Semiconductors
TDA8708B
Video analog input interface
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Video amplifier outputs
ANOUT OUTPUT (PIN 19)
V19(p-P)
AC output voltage
(peak-to-peak value)
VVIN = 1.33 V (p-p);
V25 = 3.6V
-
1.33
-
V
119
internal current source
RL = 00
2.0
2.5
-
rnA
lo(p_p)
output current driven by the load
VANOUT = 1.33 V (p-p);
note 2
-
-
1.0
rnA
V 19
DC output voltage for black level
note 3
Z19
output impedance
-
VCCA -2.24
20
-
V
-
-
-50
-45
dB
2
-
%
deg
Q
Video amplifier dynamic characteristics
act
crosstalk between VI N inputs
VCCA = 4.75 to 5.25 V
Gdiff
differential gain
VVIN = 1.33 V (p-p);
V25 = 3.6V
(jJdiff
differential phase
VVIN = 1.33 V (p-p);
V25 = 3.6V
-
0.8
-
12
MHz
60
-
-
note 4
-
dB
B
-3 dB bandwidth
SIN
signal-to-noise ratio
SVRR1
supply voltage ripple rejection
note 5
-
45
~G
gain range
see Fig.10
-4.5
GStab
gain stability as a function of supply
voltage and temperature
see Fig.10
-
-
dB
+6.0
dB
5
%
Analog-to-digital converter Inputs
ClK INPUT (PIN 5)
V IL
lOW level input voltage
0
VIH
HIGH level input voltage
2.0
IlL
lOW level input current
Vclk = 0.4 V
-400
IIH
HIGH level input current
Vclk = 2.7V
!Zi!
CI
input impedance
fclk = 10 MHz
input capacitance
fclk = 10 MHz
-
-
0.8
V
VCCD
V
-
itA
100
4
-
itA
kQ
4.5
-
pF
-
0.2
V
V CCD
V
OF INPUT (3-STATE; SEE TABLE 4)
VIL
V IH
lOW level input voltage
0
HIGH level input voltage
2.6
V9
input voltage in high impedance state
-
1.15
lOW level input current
-370
-300
-
V
IlL
IIH
HIGH level input current
-
300
450
ItA
June 1994
3-847
itA
Product specification
Philips Semiconductors
TDA8708B
Video analog input interface
SYMBOL
CONDITIONS
PARAMETER
TYP.
MIN.
MAX.
UNIT
ADCIN INPUT (PIN 20; SEE TABLE 5)
V 20
input voltage
digital output
V 20
input voltage
digital output
V 20 (p-p)
input voltage am plitude
(peak-to-peak value)
120
input current
IZil
C1
input im pedance
=00
=255
=6 MHz
fi =6 MHz
fi
input capacitance
-
VeCA - 1.41
-
V
1.0
-
V
-
1.0
10
ftA
50
-
MQ
1
-
pF
-
1.7
V
-
V
VCCA - 2.42
V
Analog-to-digital converter outputs
IR OUTPUT (PIN 28)
VOL
LOW level output voltage
-
V OH
HIGH level output voltage
1.9
10
output current
-500
ftA
DIGITAL OUTPUTS DO TO D7
VOL
LOW level output voltage
10L =2 mA
V OH
HIGH level output voltage
10L
=-0.4 mA
2.4
loz
output current in 3-state mode
0.4 V < Vo< Vcco
see Fig.6; note 6
0.6
V
Vcco
V
-20
-
+20
ftA
30
32
-
MHz
V 20 =1,0 V (p-p);
see Fig.3; note 7
-
2
-
%
-
2
-
deg
=4.43 MHz; note 7
fi =4.43 MHz; note 7
-
0
dB
-55
-
dB
note 8
-
1
5
%N
-
±1
LSB
±0_5
LSB
note 9
-
±2
LSB
tds
sampling delay time
-
2
output hold time
6
8
-
ns
th
td
output delay time
16
20
ns
tdEZ
3-state delay time; output enable
19
25
ns
tdOZ
3-state delay time; output disable
-
14
20
ns
0
Switching characteristics
fclk(max)
maximum clock input frequency
Analog signal processing (fclk
Gdiff
=32 MHz; see Fig.8)
differential gain
qJdiff
differential phase
see Fig.3; note 7
f1
fundamental harmonics (full-scale)
fi
fall
harmonics (full-scale);
all components
SVRR2
supply voltage ripple rejection
Transfer function (see Fig.8)
ILE
DC integral linearity error
DLE
DC differential linearity error
ILE
AC integral linearity error
Timing (fclk =32 MHz; see Figs 6, 7 and 8)
DIGITAL OUTPUTS (C L =15 pF; 10L =2 mA; RL
June 1994
=2 kQ)
3-848
ns
Product specification
Philips Semiconductors
Video analog input interface
TDA87088
Notes to the "Characteristics"
=1.33 V.
1.
0 dB is obtained at the AGC amplifier when applying Vi(p-p)
2.
The output current at pin 19 should not exceed 1 rnA. The load impedance RL should be referenced to VCCA and
defined as:
a) AC impedance ~1 kQ and the DC impedance >2.7 kQ.
b) The load impedance should be coupled directly to the output of the amplifier so that the DC voltage supplied by
the clamp is not disturbed.
3.
Control mode 2 is selected.
4.
Signal-to-noise ratio measured with 5 MHz bandwidth:
§ = 20 log
N
5.
V ANOUTC(p- p) at B
V ANOUlY (RMS noise)
The voltage ratio is expressed as:
SVRR1
= 20 log f1VV CCA x f1~
CCA
6.
=5 MHz.
for VI
=1 V (p-p), gain at 100 kHz =1 and 1 V supply variation.
It is recommended that the rise and fall times of the clock are
analog grounds is recommended.
~2
ns. In addition, a 'good layout' for the digital and
7. These measurements are realized on analog signals after a digital-to-analog conversion (TDA8702 is used).
8.
The supply voltage rejection is the relative variation of the analog signal (full-scale signal at input) for 1 V of supply
variation:
SVRR2
9.
= f1(V I(OO) -VI(FF»)
Full-scale sine wave (fi
June 1994
+ (VI(OO) -VI(FF»)
f1 V CCA
=4.4 MHz; fclk =27 MHz).
3-849
Product specification
Philips Sem iconductors
TDA8708B
Video analog input interface
Table 3 CLAMP output current.
Table 1 Video input selection (CVBS).
11
10
SELECTED INPUT
0
0
VINO
0
1
VIN1
1
0
VIN2
1
1
VIN2
GATE A
GATE B
1
1
X(1)
0
0
1
Table 2 AGC output current.
DIGITAL
OUTPUT
IAGC
MODE(2)
output < 255
-2.5 flA
1
GATE A GATE B
1
1
0
X(1)
1
0
output> 255
130 ftA
1
o itA
2
output < 0
+2.5 itA
2
output> 0
-2.5 ftA
2
ICLAMP
MODE
output < 0
130 ftA
output> 0
-2.5 ftA
1
1
X
a ftA
2
output < 64
+50 ftA
2
64 < output
-50 ftA
2
Note
1.
-
DIGITAL
OUTPUT
X
= don't care.
Table 4 OF input coding.
DO TO D7
OF
0
active, two's complement
1
high impedance
open circuit(1)
Notes
1. X = don't care.
Note
2.
1.
Mode 2 can only be initialized with successive pulses
on GATE A and GATE B (see Fig.5).
Use C
0
pi~_28
:JJ
---
pin 25
__ £~S_26~:"L_
Z
l>
r-
"g
z
cr
pins 1 to 4
and 10to 13
data outputs
I II ~~
t~
n
J
I
f
V
I
1 ~ tKJ +
pin 6
VCCD
- .
pin 7
Vcca
pin 22
VCCA
pin 24
CLAMP
pin 5
clock input
:u0'
c
=i
~
<
a:
CD
0
m
::J
m
0
OJ
Q.
C
"0
CD
(")
=+;
o·
~
o·
::J
Product specification
Philips Semiconductors
Video analog input interface
TDA8708B
APPLICATION INFORMATION
Additional information can be found in the laboratory report of TDAB70BA "FBUAN9308".
28
(2)
2
27
horizontal sync
3
26
data outputs
horizontal clamp
220 nF
100
Q
!
4
25
H
18 nF
33 pF
clock
24
H
23
+5V
22
22 nF
+5 V
1f1H
TDA8708B
21
1 flF
20
J; 10 pF
LOW PASS
FILTER
10
19
11
18
12
17
(3)
to
to
4.7 flF
data outputs
4.7 flF
4.71'.F
13
16
MSA673
t"
(1) It is recommended to decouple VCGO through a 22 Q resistor especially when
the output data of TDA8708B interfaces with a capacitive CMOS load device.
(2) When IR is not used, it must be connected to ground via a 47 pF capacitor.
(3) See Figs 13 and 15 for exam pies of the low-pass filters.
Fig.12 Application diagram.
June 1994
3-856
Product specification
Philips Semiconductors
Video analog input interface
TDA8708B
22ltH
ANOUT
ADCIN
(pin 19) -'-r-~~_---1I--........~-I
(pin 20)
VCCA
(pin 22)
This filter can be adapted to various applications with respect to performance requirements. An input and output impedance of at least 680 Q and 2.2 kQ
must in any event be applied.
Fig.13 Example of a low-pass filter for CVBS and Y signals.
Characteristics of Fig.14
• Order 5; adapted CHEBYSHEV
MSA682
1\
0.
(dB)
-40
• Ripple p
•
\
I
r
\ II
-80
-120
-160
o
10
20
f (MHz)
30
Fig.14 Frequency response for filter shown in
Fig.13.
June 1994
3-857
:s;
0.4 dB
= 6.5 MHz at -3 dB
fnotch = 9.75 MHz.
• f
Philips Semiconductors
Product specification
Video analog input interface
TDAB70BB
VCCA
(pin 22)
This filter can be adapted to various applicatiqns with respect to performance requirements. An input and output impedance of at least 680 Q and 2.2 kQ
must in any event be applied.
Fig.15 Example of an economical low-pass filter for CVBS and Y signals.
Characteristics of Fig.16
• Order 5; adapted CHEBYSHEV
o
MSA681
1- ---..
(dB)
\
-10
\
\
-20
1\
'~
-30
-40
• Ripple p s 0.4 dB
• f
1\
o
10
"'"
20
.........
f (MHz)
"
30
Fig.16 Frequency response for filter shown in Fig.15.
June 1994
3-858
=6.5 MHz at
-3 dB.
Product specification
Philips Semiconductors
TDA8709A
Video analog input interface
FEATURES
GENERAL DESCRIPTION
• 8-bit resolution
The TDA8709A is an analog input interface tor video signal
processing. It includes a an input selector
(one out-at-three video signals), video amplifierwith clamp
and external gain control, an 8-bit analog-to-digital
converter (ADC) with a sampling rate of 32 MHz and an
input selector.
• Sampling rate up to 32 MHz
• TIL-compatible digital inputs and outputs
• Internal reference voltage regulator
• LOW-level AC clock inputs and outputs
• Clamp function with selection for '16' or '128'
• No sample-and-hold circuit required
• Three selectable video inputs.
APPLICATIONS
• Video signal processing
• Digital picture processing
• Frame grabbing.
• Colour difference Signals (U, V)
• R, G, B signals
• Chrominance signal (C).
QUICK REFERENCE DATA
SYMBOL
VCCA
PARAMETER
MIN.
analog supply voltage
TYP.
MAX.
4.5
5.0
5.5
UNIT
V
VCCD
digital supply voltage
4.5
5.0
5.5
V
Vcco
TIL output supply voltage
4.2
5.0
5.5
V
ICCA
analog supply current
-
40
47
rnA
ICCD
digital supply current
-
24
30
rnA
Icco
ILE
TIL output supply current
12
16
rnA
-
±1
LSB
DLE
DC differential linearity error
-
-
±0.5
LSB
fclk(max)
B
maximum clock frequency
30
32
-
MHz
maximum -3 dB bandwidth (preamplifier)
12
18
-
MHz
Ptot
total power dissipation
-
380
512
mW
DC integral linearity error
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
PINS
PIN POSITION
MATERIAL
CODE
TDA8709A
28
DIP
plastic
SOT117-1
TDA8709AT
28
S028L
plastic
SOT136-1
June 1994
3-859
Philips Semiconductors
Product specification
Video analog input interface
TDA8709A
BLOCK DIAGRAM
video input
selection bit 0
analog
voltage
output
video input
selection bit 1
clock
input
ADC
input
decoupling
input
TIL outputs V CCO (+ 5 V)
fast output
chip enable
video input 0
video input 1
D7
video input 2
D6
clamp capacitor --t...:;;;...;.-----~
connection
D5
gain control
input --t-------~-~
TIL
OUTPUTS
TDA8709A
D4
D3
D2
D1
CLAMP LEVEL "16"
DIGITAL COMPARATOR
DO
28
CLAMP
LOGIC
~
____
~
______
clamp
level
selection
~~
clamp
pulse
_____
~
________
~
digital V CCD
(+ 5 V)
______
digital
ground
~~
Fig.1 Block diagram.
June 1994
3-860
______
analog V CCA
(+ 5 V)
~
______
analog
ground
output
format
selection
~MB~51
Philips Semiconductors
Product specification
Video analog input interface
TDA8709A
PINNING
SYMBOL
07
PIN
1
DESCRIPTION
data output; bit 7 (MSB)
06
2
data output; bit 6
05
3
data output; bit 5
04
4
data output; bit 4
ClK
5
clock input
VCCD
6
digital supply voltage (+5 V)
CLS
Vcco
OGNO
7
TTL outputs supply voltage (+5 V)
CLP
8
digital ground
FOEN
9
fast output chip enable
03
10
data output; bit 3
02
11
data output; bit 2
GAIN
CLAMP
AGND
01
12
data output; bit 1
VCCA
00
13
data output; bit 0 (LSB)
DEC
10
14
video input selection bit 0
11
15
video input selection bit 1
VINO
16
video input 0
VIN1
17
video input 1
VIN2
18
video input 2
ANOUT
19
AOCIN
20
analog-to-digital converter input
OEC
21
decoupling input
VCCA
AGNO
22
analog supply voltage (+5 V)
23
analog ground
CLAMP
24
clamp capacitor connection
GAIN
25
gain control input
ClP
26
clamping pulse
ClS
27
clamping level selection input
OFS
28
output format selection
June 1994
ADCIN
analog voltage output
D3
ANOUT
D2
VIN2
D1
VIN1
DO
VINO
MBB950
Fig.2 Pin configuration.
3-861
Product specification
Philips Semiconductors
TDA8709A
Video analog input interface
chrominance or colour difference signals). While clamping
pulse at pin 27 is logic 1, the device will adjust the
clamping level to the chosen value. The output format can
be selected between binary and two's complement at
pin 28.
FUNCTIONAL DESCRIPTION
TDA8709A is an 8-bit ADC with internal clamping and a
preamplifier with adjustable gain.
The clamping value is switched via pin 27 between
digital 16 (for R, G, B signals) and digital 128 (for
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VCCA
V CCD
analog supply voltage
-0.3
+7.0
V
digital supply voltage
-0.3
+7.0
V
Vcco
TTL output supply voltage
-0.3
+7.0
V
t.V cc
supply voltage difference between VCCA and V CCD
supply voltage difference between V cco and V CCD
-0.5
+0.5
V
-0.5
+0.5
V
supply voltage difference between VCCA and Vcco
-1.0
+1.0
V
VI
input voltage
-0.3
+7.0
V
10
output current
-
+10
mA
T stg
storage temperature
-55
+150
°C
Tamb
Tj
operating ambient temperature
0
+70
°C
junction temperature
0
+125
°C
THERMAL CHARACTERISTICS
SYMBOL
Rth
j-a
June 1994
VALUE
UNIT
SOT117-1
55
SOT136-1
70
KJW
KJW
PARAMETER
thermal resistance from junction to ambient in free air
3-862
Product specification
Philips Semiconductors
TDA8709A
Video analog input interface
CHARACTERISTICS
VCCA = V 22 to V23 = 4.5 to 5.5 V; VCCD = V6 to Va = 4.5 to 5.5 V; Vcca = V 7 to Va = 4.2 to 5.5 V; AGND and DGND
shorted together; VCCA to VCCD = -0.5 to +0.5 V; Vcca to V CCD = -0.5 to +0.5 V; VCCA to Vcca = -0.5 to +0.5 V;
T amb = 0 to +70 °C; typical readings taken at V CCA = V CCD = V cca = 5 V and T amb
SYMBOL
PARAMETER
=25°C; unless otherwise specified.
MIN.
CONDITIONS
MAX.
TYP.
UNIT
Supplies
VCCA
analog supply voltage
4.5
5.0
5.5
V
V CCD
digital supply voltage
4.5
5.0
5.5
V
Vcca
TTL output supply voltage
4.2
5.0
5.5
V
ICCA
analog supply current
-
40
47
rnA
Iceo
digital supply current
24
30
mA
Icca
TTL output supply current
TTL load (see Fig.7)
-
12
16
mA
Preamplifier inputs
VINO TO VIN2 INPUTS
VI(p_p)
input voltage (peak-to-peak value)
note 1
0.6
-
1.5
V
Iljl
input impedance
fj= 6 MHz
10
20
-
kQ
CI
input capacitance
fj = 6 MHz
-
1
-
pF
10 AND 11 TTL INPUTS (SEE TABLE 1)
VIL
LOW level input voltage
0
V IH
HIGH level input voltage
2.0
IlL
LOW level input current
VI = 0.4 V
-400
IIH
HIGH level input current
VI = 2.7V
-
-
0.8
V
VCCD
V
-
f.tA
20
f.tA
CLS, OFS AND CLP TTL INPUTS (SEE FIG.5)
VIL
LOW level input voltage
0
-
0.8
V
V IH
HIGH level input voltage
2.0
-
V CCD
V
IlL
LOW level input current
VI = 0.4 V
-400
-
-
f.tA
IIH
HIGH level input current
VI=2.7V
-
-
20
f.tA
tCLP
clam p pulse width
2
-
-
f.ts
-
1.8
-
V
3.8
V
1.0
-
-
3.5
-
V
GAIN INPUT (PIN 25)
V 25 (mjn)
input voltage for minimum gain
see Fig.9
V25 (max)
input voltage for maximum gain
see Fig.9
II
input current
f.tA
CLAMP INPUT (PIN 24)
V24
clamp voltage for code 128 output
124
clamp output current
June 1994
see Table 2
3-863
Product specification
Philips Sem iconductors
Video analog input interface
SYMBOL
TDA8709A
PARAMETER
CONDITIONS
TYP.
MIN.
MAX.
UNIT
Video amplifier outputs
ANOUT OUTPUT (PIN 19)
V 19 (p-p)
AC output voltage
(peak-to-peak value)
119
internal current source
lo(p_p)
output current driven by the load
=1.33 V (p-p);
=3.0 V
RL =
VANOUT =1.33 V (p-p);
V OF
V 25
00
-
1 ..33
-
V
2.0
2.5
-
rnA
-
-
1.0
rnA
-
VCCA -2.02
-
V
VCCA -2.6
-
V
20
-
Q
note 2
=logic 1
V 19
DC output voltage for black level
ClS
V 19
DC output voltage for black level
ClS = logic 0
Z19
output impedance
Preamplifier dynamic characteristics
act
crosstalk between VIN inputs
V CCA = 4.75 to 5.25 V;
note 3
-
-50
-45
dB
G diff
differential gain
VVIN = 1.33 V (p-p);
V 25 =3.0V
-
2
-
%
<]Jdiff
differential phase
VVIN = 1 .33 V (p-p);
V 25 = 3.0 V
-
0.8
-
deg
12
note 4
60
-
dB
B
-3 dB bandwidth
SIN
signal-to-noise ratio
SVRR1
supply voltage ripple rejection
note 5
-
45
-
~G
gain range
see Fig.9
-4.5
-
+6.0
dB
Gstab
gain stability as a function of supply
voltage and temperature
see Fig.9
-
-
5
%
-
0.8
V
VCCD
V
-
f!A
MHz
dB
Analog-to-digital converter inputs
ClK INPUT (PIN 5)
V IL
lOW level input voltage
0
VIH
HIGH level input voltage
2.0
IlL
lOW level input current
V clk = 0.4 V
-400
IIH
HIGH level input current
V clk = 2.7 V
!Zi!
input impedance
fclk = 10 MHz
CI
input capacitance
fclk = 10 MHz
-
100
f!A
4
-
kQ
4.5
-
pF
0.8
V
V CCD
V
-
f!A
20
f!A
FOEN INPUT (SEE TABLE 3)
VIL
lOW level input voltage
0
V IH
HIGH level input voltage
2.0
IlL
lOW level input -current
V9 = 0.4 V
-400
-
IIH
HIGH level input current
V9 = 2.7 V
-
-
June 1994
3-864
Philips Semiconductors
Product specification
Video analog input interface
SYMBOL
TDA8709A
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ADCIN INPUT (PIN 20; SEE TABLE 4)
V 20
input voltage
digital output = 00
V 20
input voltage
digital output
V 20 (p-p)
input voltage amplitude
(peak-to-peak value)
120
input current
IZil
C1
input impedance
fi= 6 MHz
input capacitance
fj = 6 MHz
=255
-
VCCA - 2.52
-
V
-
V CCA -1.52
V
-
1.0
-
-
1.0
10
itA
50
1
-
pF
-
0.6
V
2.4
V CCD
V
V
MQ
Analog-to-digital converter outputs
DIGITAL OUTPUTS DO TO 07
=2 rnA
=-0.4 rnA
VOL
LOW level output voltage
IOL
V OH
HIGH level output voltage
IOL
loz
output current in 3-state mode
0.4 V < Vo< V CCD
-20
-
+20
ftA
see Fig.5; note 6
30
32
-
MHz
V 20 =1.0 V (p-p);
see Fig.6; note 7
-
2
-
%
2
-
deg
-
0
dB
-55
-
dB
%N
0
Switching characteristics
fc1k(max)
maximum clock input frequency
Analog signal processing (fclk = 32 MHz; see Fig.7)
Gdiff
differential gain
CPdiff
differential phase
see Fig.6; note 7
f1
fundamental harmonics (full-scale)
fj
fall
harmonics (full-scale);
all components
fj = 4.43 MHz; note 7
-
SVRR2
supply voltage ripple rejection
note 8
-
1
5
-
±1
LSB
±0.5
LSB
±2
LSB
=4.43 MHz; note 7
Transfer function
ILE
DC integral linearity error
-
OLE
DC differential linearity error
ILE
AC integral linearity error
-
note 9
Timing (fclk =32 MHz; see Figs 5, 6 and 7)
DIGITAL OUTPUTS (CL = 15 pF; IOL = 2 rnA; RL = 2 kQ)
-
2
-
ns
8
16
20
ns
3-state delay time; output enable
-
16
25
ns
3-state delay time; output disable
-
12
25
ns
tds
sampling delay time
th
output hold time
td
output delay time
tdEZ
tdDZ
June 1994
3-865
ns
Product specification
Philips Semiconductors
TDA8709A
Video analog input interface
Notes to the "CharacteristiCs"
=1.33 V.
1.
0 dB is obtained at the AGC amplifier when applying Vi(p-p)
2.
The output current at pin 19 should not exceed 1 rnA. The load impedance RL should be referenced to V CCA and
defined as:
a) AC impedance
~1
kQ and the DC impedance >2.7 kQ_
b) The load impedance should be coupled directly to the output of the amplifier so that the DC voltage supplied by
the clamp is not disturbed.
3.
Input signals with the same amplitude. Gain is adjusted to obtain ANOUT = 1.33 V (p-p).
4.
Signal-to-noise ratio measured with 5 MHz bandwidth:
~
= 20 log
N
5.
VANOUT(p-p) atB=5MHz.
V ANOUT (RMS noise)
The voltage ratio is expressed as:
eN
G·
SVRR1= 20 log V CCA x LlG for VI = 1 V (p-p), gain at 100 kHz = 1 and 1 V supply variation.
CCA
are~2
6.
It is recommended that the rise and fall times of the clock
analog grounds is recommended.
7.
These measurements are realized on analog signals after a digital-to-analog conversion (TDA8702 is used)_
8.
The supply voltage rejection is the relative variation of the analog signal (full-scale signal at input) for 1 V of supply
variation:
SVRR2 = Ll(VI(OO)-VI(FF)~ + (VI(OO)-VI(FF»)
Ll CCA
9.
Full-scale sine wave (fj = 4.4 MHz; fclk = 27 MHz).
June 1994
3-866
ns. In addition, a 'good layout' for the digital and
Product specification
Philips Semiconductors
TDA8709A
Video analog input interface
Table 1 Video input selection (CVBS).
Table 3 FOEN input coding.
00 TO 07
11
10
SELECTEOINPUT
FOEN
0
0
VINO
0
active, two's complement
0
1
VIN1
1
high impedance
1
0
VIN2
1
1
VIN1
Table 2 CLAMP output current.
CLS
CLP
1
1
OIGITAL
OUTPUT
ICLAMP
output < 128
+50f.,tA
output> 128
-50 f.,tA
X(1)
0
X
o f.,tA
0
1
output < 16
+50f.,tA
16 < output
-50 f.,tA
Note
1.
X
=don't care.
Table 4 Output coding and input vOltage (typical values).
BINARY OUTPUTS
STEP
VADCIN
TWO'S COMPLEMENT
05
04
03
02
01
00
Underflow
-
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
V CCA - 2.52 V
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
-
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
07
06
05
04
03
02
01
00
07
06
-
254
-
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
255
VCCA -1.52 V
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
Overflow
-
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
June 1994
3-867
Product specification
Philips Semiconductors
Video analog input interface
TDA8709A
1.0V
1025V
I.. .1 - - - - - - - - -
64
115---------'.1
M88959
Fig.3 Test signal on the ADCIN pin for differential gain and phase measurements.
digital
output
level
~5
M88960
----------------------
"128"
CLS = 1
"16"
CLS = 2
O~-------------I~--~-----------------------CLP
________________::flr-~ tCLP
Fig.4 Control mode ·selection.
June 1994
3-868
Philips Semiconductors
Product specification
Video analog input interface
TDA8709A
ClK
-
input
clock input
reference level
analog
input
(ADCIN)
r-----
2.4V
data
' - - - - - - - f '-_ _ _-+---J
~----...J
'----
0.4 V
M88958
Fig.5 Timing diagram.
FOEN
input
;"""7"7">"7"7">"""""""""""""""""""""'" 2.4 V
data
outputs
(DO to D7)
Fig.6 Output format timing diagram.
June 1994
3-869
Product specification
Philips Semiconductors
TDA8709A
Video analog input interface
DO to 07 1---....---<__-f-M-J---4
IN916
or
IN3064
M88955
OGNO
Fig.7 Load circuit for timing measurement; data outputs (FOEN
=LOW).
Vcco
DO to 07 1----<__-~II--\----4
IN916
or
IN3064
Fig.S Load circuit for timing measurement; 3-state outputs (FOEN: fj = 1 MHz; VFOEN = 3 V).
June 1994
3-870
Product specification
Philips Semiconductors
TDA8709A
Video analog input interface
MBB961· I
12
G
(dS)
1-'-
8
./~ ~
/~
5%
/J
~J
~/~
~ ~I/
-4
~V
" p:...
-::,. ~ ~
(1)
(2)
_I-'
-8
1.6
2.4
3.2
V
25
M
4.0
(1) Typical value (lJCCA = VCCD = 5 V; Tamb = 25°C).
(2) Minimum and maximum values (temperature and supply).
Fig.9
June 1994
Typical gain control curve as a function of
gain voltage.
3-871
<-
Z
m
C
::l
CD
-t
Z
:J
0
0>
jj
0
0
c:
=i
~
CO
~
~.
fI)
(J)
CD
3
C'S"
0
::J
a.
c
~
0
Cil
:J
""0
C
.-+
:5
.-+
CD
4.
0>
CD
0
V
TDA8709A
""-oj
I\)
n
iJ
<
a:
1100?t 1"lt~ i~e
.~
DGND
pin 23
CLAMP
Ping
FOEN
VCCA
I
pins140r15~~ I ~I
ID,11
VCCA
~I, c::::::J-I
pins 16 to 18
VIND, VIN1 and VIN2
pin 19
ANOUT
pin 20
ADCIN
pin 21
DEC
iJ
-I
o
~
-...J
o
Fig.10 Internal pin configuration.
~
(3
a.
c
~
en
"0
CD
o
:::;;
o·
~
o·
::J
Product specification
Philips Semiconductors
Video analog input interface
TDA8709A
APPLICATION INFORMATION
Additional information can be found in the laboratory report of TDA8708A "FBUAN9308".
V CCA
28
2
27
3
26
data outputs
horizontal clamp
220 nF
100 Q
!
4
25
H
18 nF
33 pF
clock
24
H
23
+5V
22
22 nF
1J.1H
TDA8709A
8
21
9
20
+5V
1J.1F
LOW PASS
FILTER
10
19
11
18
12
17
13
16
4.7
data outputs
4.7 J.lF
(1) It is recommended to decouple Veeo through a 22 Q resistor especially when
the output data 01 TDA8709A interfaces with a capacitive CMOS load device.
(2) See Figs 12,14,16 and 18 lor examples 01 the low-pass filters.
Fig.11 Application diagram.
June 1994
3-873
J.IF
1:"
fo
to
4.7 J.lF
1.188954-1
(2)
Product specification
Philips Semiconductors
Video analog input interface
TDA8709A
ANOUT
ADCIN
(pin 19) -"--r--C:::J--.-~-II-----3.30
1
1
1
1
1
1
1
1
1
254
Table 2
Mode selection.
07 TO 00
CE
O/UF
1
high impedance
high impedance
0
active; binary
active
ClK
--~~--T---~--~---.r.---~---+--~~1.4V
2.4 V
DATA
1.4 V
001007
0.4 V
Fig.3 Timing diagram.
June 1994
3·901
Product specification
Philips Semiconductors
TDA8714
8-bit high-speed analog-to-digital converter
VCCD------~----~
CE
output
data
output
data
TEST
V CCD
S1
1
tdLZ
V CCD
tdZL
VCCD
tdHZ
GND
tdZH
GND
MBD876
teE = 100 kHz.
Fig.4 Timing diagram and test conditions of 3-state output delay time.
DO to D7
1-------....
f
15pF
MB8956·'
Fig.5 Load circuit for timing measurement.
June 1994
3-902
S1
Product specification
Philips Semiconductors
8-bit high-speed analog-to-digital converter
TDA8714
tSTlH
code 255
VI
code 0
elK
MBD875
0.5 ns
Fig.6 Analog input settling-time diagram.
June 1994
3-903
Product specification
Philips Semiconductors
TDA8714
8-bit high-speed analog-to-digital converter
MBD877
amplitude I - - - - - - - - _ i _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - l
(dB)
-20~-------~-----------------------------~
-401--------~---------------~-------------~
-601--------~--------~-------~_i_-----------~
-80
2.50
5.00
Effective bits: 7.80; THD = -57.82 dB;
Harmonic levels (dB): 2nd =-68.00; 3rd
7.50
10.0
12.5
15.0
17.5
f (MHz)
20.0
=-61.54; 4th =-72.46; 5th =-65.80; 6th =-68.88.
Fig.7 Fast Fourier Transform (fclk =40 MHz; fi
=4.43 MHz).
MBD878
am~~de I - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - l
-20r----------r----------------------------~
-40r-------------r-----------------------------~
-60r----------r-----------+----~----~------~
-80
-100
9.39
4.69
Effective bits: 7.27; THD = -49.23 dB;
Harmonic levels (dB): 2nd =-56.16; 3rd
14.1
18.8
28.2
=-51.01; 4th =-69.84; 5th =-59.10; 6th =-65.34.
Fig.S Fast Fourier Transform (fC\k
June 1994
23.5
3-904
=75 MHz; fi =10 MHz).
32.9
37.5
f (MHz)
Product specification
Philips Semiconductors
8-bit high-speed analog-to-digital converter
TDA8714
INTERNAL PIN CONFIGURATIONS
vee02 --+-----,
D7 to DO
O/UF
vecA ---l1--1----.---_
(x 90)
-----if---4~-
_
___[-
DGND - - - l - - + - - - + - - - - -
AGND
-----if--_--4---~
MLB036
MLB037
Fig.9 TIL data and overflow/underflow outputs.
Fig.10 Analog inputs.
vee01
VeeA
VRT
RLAD
CE
VRB
AGND
DGND
MLB038
Fig.11 CE (3-state) input.
June 1994
Fig.12 VRB and VRT.
3-905
MEA050
Product specification
Philips Semiconductors
TDA8714
8-bit high-speed analog-to-digital converter
VCCD---~-----~~-~------
ClK
----+--....--__--1
30 kQ
DGND----4--~---~-----MCD189·1
Fig.13 •elK input.
June 1994
3-906
Product specification
Philips Semiconductors
TDA8714
8-bit high-speed analog-to-digital converter
APPLICATION INFORMATION
01
24
DO
23
(2)
n.c.
22
02
03
CE
(1)
VRB
100 nF~
21
Vee02
(2)
n.c.
20
OGNO
AGNO
AGNO
19
VeC01
TDA8714
VCCA
18
VI
17
VCCO
OGNO
(1)
VRT
100 nF ~
16
elK
(2)
10
15
11
14
12
13
04
AGNO
O/UF
07
05
06
MSA688
The analog and digital supplies should be separated and decoupled.
The external voltage generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value.
(1) VRB and VAT are decoupled to AGNO.
(2) Pin.5 should be connected to AGNO; pins 3 and 10 to OGNO in order to prevent noise influence.
Fig.14 Application diagram.
June 1994
3·907
Philips Semiconductors Video Products
, Product specification
8-bit high-speed analog-to-digital
converter
TDA8716
FEATURES
GENERAL DESCRIPTION
• 8-bit resolution
o Sampling rate up to 120 MHz
The TOA8716 is an 8-bit high-speed analog-to-digital
converter (AOC) designed for HOTV and professional
applications. The device converts the analog input signal
into 8-bit binary coded digital words at a sampling rate of
120 MHz. All digital outputs are ECl compatible.
o
ECl (10 Kfamily) compatible digital inputs and
outputs
• Overflow/Underflow output
• low power dissipation
o low input capacitance (13 pF typ.).
APPLICATIONS
• High speed analog-to-digital convertion
• Video signal digitizing
• Radar pulse analysis
• Transient signal analysis
o High energy physics research
• Medical systems
• Industrial instrumentation.
QUICK REFERENCE DATA
Measured over full voltage and temperature ranges, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
UNIT
MAX.
VEEA
VEED
analog supply voltage
digital supply voltage
-5.45
-5.45
-5.2
-5.2
-4.95
-4.95
V
V
IEEA
IEED
IEEo
VRS
analog supply current
digital supply current
-
50
100
55
110
mA
mA
25
-
20
-3.130
-1.870
-
rnA
V
V
±O.5
±O.25
±1
±O.45
lSB
lSB
output supply current
reference voltage BOTTOM
reference voltage TOP
Rl = 2.2kn
DC integral linearity error
DC differential linearity error
see Fig.8
see Fig.9
EB
effective bit
fj =20 MHz;
fcu< = 100 MHz
-
7
-
bits
fcu<
Pm!
maximum clock frequency
total power dissipation
120
-
-
excluding load
-
780
900
MHz
mW
Vrrr
IlE
OLE
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
TOA8716
TOA8716T
April 1993
PACKAGE
PINS
PIN POSITION
MATERIAL
CODE
24
32
Oil
S032l
plastic
plastic
SOT101
SOT287
3-908
Product specification
Philips Semiconductors
8-bit high-speed analog-to-digital
converter
TDA8716
analog input
CLKinput
13
24
LATCHES
CLKinput
3
12
4
digital ground
digital negative
supply voltage
(-S2V)
two's complement
output select
OUTPUT LATCHES
TDA8716
19
output ground
supply voltage.
(0 V)
digital outputs
DO to 07
Fig.1 Block diagram; TDA8716.
April 1993
3-909
IN range
Product specification
Philips Semiconductors
8-bit high-speed analog-to-digital
converter
TDA8716
PINNING
SYMBOL
PIN
DESCRIPTION
CLK
1
complementary clock input
CLK
2
clock input
V~eDl
3
digital negative supply voltage
(-5.2 V)
C PLT2
4
two's complement output select
(active HIGH)
OGN02
IR
VeEA
5
analog negative supply voltage
(-5.2 V)
VRB
6
reference voltage BOTTOM
AGN01
7
analog ground 1
VI
VRM
8
analog input
9
reference voltage MIDDLE
decoupling
VRT
10
reference voltage TOP
AGN02
11
analog ground 2
VEED2
12
digital negative supply voltage
(-5.2 V)
DO
digital ground 1
OGN01
OGN01
13
DO
14
digital output (LSB)
01
15
digital output
02
16
digital output
03
17
digital output
07
D6
05
OGNO
04
03
02
VRT
04
18
digital output
OGNO
19
output ground supply voltage (0 V)
05
20
digital output
06
21
digital output
digital output (MSB)
07
22
IR
23
IN range
OGN02
24
digital ground 2
April 1993
01
Fig.2 Pin configuration; TOA8716.
3-910
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital
converter
TDA8716
PINNING
SYMBOL
ClK
PIN
DESCRIPTION
1
complementary clock input
ClK
2
clock input
VEED1
3
digital negative supply voltage
(-5.2 V)
n.c.
4
not connected
n.c.
5
not connected
C PLT2
6
two's complement output select
(active HIGH)
OGN02
IR
07
n.c.
n.c.
VEEA
7
analog negative supply voltage
(-5.2 V)
VRB
8
reference voltage BOnOM
AGND1
9
analog ground 1
05
OGNO
V,
10
analog input
V RM
11
reference voltage MIDDLE
decoupling
n.c.
12
not connected
n.c.
13
not connected
Vr:rr
AGND2
14
reference voltage TOP
15
analog ground 2
VEED2
16
digital negative supply voltage
(-5.2 V)
DGND1
17
digital ground 1
DO
18
digital output (lSB)
n.c.
D6
04
VI
03
n.c.
n.c.
02
n.c.
n.c.
VRT
01
AGN02
DO
VEE02
OGN01
MBC742·2
01
19
digital output
n.c.
20
not connected
n.c.
21
not connected
02
22
digital output
03
23
digital output
04
24
digital output
OGND
25
output ground supply voltage
(0 V)
05
26
digital output
06
27
digital output
n.c.
28
not connected
n.c.
29
not connected
digital output (MSB)
07
30
IR
31
IN range
DGND2
32
digital ground 2
April 1993
Fig.3 Pin configuration; TDA8716T.
3-911
Philips Semiconductors
Product specification
a-bit high-speed analog-to-digital
converter
TDA8716
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
analog supply voltage
-7.0
+0.3
V EED1' V EED2
digital supply voltage
-7.0
+0.3
V
VEEA-VEED1;
supply voltage differences
-1
+1
V
V EEA
V
VEEA-VEED2
VI
V CLK ;
ClK(p-p)
input voltage
referenced to
AGND
V EEA
0
V
input voltage for differential clock drive
(peak-to-peak value)
note 1
-
2.0
V
10
output current (each output stage)
-
10
rnA
T stg
storage temperature
-55
+150
°C
Tamb
Tj
operating ambient temperature
0
+70
°C
junction temperature
-
+150
°C
Note
1. The circuit has two clock inputs: ClK and ClK. Sampling takes place on the rising edge of the clock input Signal:
ClK and ClK are two's complementary ECl signals.
THERMAL RESISTANCE
SYMBOL
Rlhj-a
PARAMETER
THERMAL RESISTANCE
from junction to ambient in free air
SOT101
35K/W
SOT287 (see Fig.4)
65K/W
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
April 1993
3-912
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital
converter
TDA8716
CHARACTERISTICS
VEEA = -4.95 V to -5.45 V; VEED1 • VEED2 = -4.95 V to -5.45 V; AGND. DGND and OGND shorted together;
Tamb = 0 °C to +70°C; unless otherwise specified. (Typical values taken at VEEA = -5.2 V; VEED1 • VEED2 = -5.2 V;
Tamb = 25°C).
PARAMETER
SYMBOL
CONDITIONS
TYP.
MIN.
MAX.
UNIT
Supply
VEEA
VEED1' VEED2
IEEA
analog supply voltage
digital supply voltage
analog supply current
IEED1.IEED2
lEE
Vdfl
digital supply current
output supply current
supply voltage differential
-5.45
-5.45
-4.95
-4.95
55
V
V
rnA
100
110
rnA
-
20
25
rnA
-0.5
0
+0.5
V
-3.5
-3.13
-1.87
-
V
-1.5
V
1.26
-
130
-
V
rnV
RL =2.2 kO
VEEA - VEED1 ; VEEA - VEED2
-5.2
-5.2
50
Reference voltages for the resistor ladder
VAS
VRT
reference voltage BOTTOM
reference voltage TOP
Vref
reference voltage differential
Vos
VOT
voltage offset BOnOM
VAT - VAS
note 1
-
voltage offset TOP
note 1
-
130
-
mV
V,(p"P)
input voltage amplitude
(peak-to-peak value)
0.95
1.0
1.5
V
Iref
reference current
resistor ladder
-
n
-1650
-810
rnV
mV
J.lA
J.lA
RLAD
TC AL
temperature coefficient of the
resistor ladder
-
15
-
85
0.18
-1850
-960
-880
-
1
-
10
-
20
2
-
900
-
mV
-
J.lA
J.lA
rnA
n/K
Inputs
ClK and ClK input
VIL
VIH
lOW level input voltage
HIGH level input voltage
I'L
lOW level input current
I'H
R,
HIGH level input current
C,
input capacitance
VCLK(P-P)
differential clock input VCLK VCLK (peak-to-peak value)
VCLK = -1.77 V
VCLK = -0.88 V
input resistance
-1nO
kn
pF
Analog input; note 2
lis
input current BOnOM
VAB = -3.13 V
-
0
liT
R,
C,
input current TOP
input resistance
VRT =-1.87V
-
170
7
-
kn
13
20
pF
April 1993
input capacitance
3-913
Philips Semiconductors
Product specification
a-bit high-speed analog-to-digital
converter
SYMBOL
Outputs (Rl
PARAMETER
TDA8716
CONDITIONS
MIN.
TYP.
MAX.
UNIT
=2.2 kO)
Digital 10K ECl outputs (DO to 07; IR)
VOL
lOW level output voltage
-1850
-1770
-1600
mV
VOH
HIGH level output voltage
-960
-880
-810
rnV
IOl
lOW level output current
4.0
rnA
HIGH level output current
-
1.8
IOH
2.0
4.0
mA
Timing ('ClK
=100 MHz; Rl =2.2 kQ; see Flg.5)
~
sampling delay
-
1
·3
ns
~D
output hold time
4
-
-
ns
~
output delay time
-
-
7.E)
ns
-
9
ns
-
15
-
ps
120
_.
-
MHz
-
%
note 3
Cl =3.3 pF
C l = 7.5 pF
laJ
aperture jitter
Switching characteristics
fCLK; fCU(.
maximum clock frequency
Analog signal processing ('CLK
=100 MHz)
Gdiff
differential gain
note 4
-
0.3
«1>dill
differential phase
note 4
-
0.4
-
-60
°C
Harmonics (full scale); fl = 10 MHz; fClK = 100 MHz
f1
fundamental
f2
even harmonics
f3
odd harmonics
-
0
-50
dB
dB
dB
Transfer function
IlE
DC integral, linearity error
OLE
DC differential linearity error
AilE
AC integral linearity error
note 4
EB
effective bits
BER
fl = 4.43 MHz
fl = 10 MHz
fj =20 MHz
fl =3O MHz
bit error rate
Figs 13 and 14; note 5;
fClK = 100 MHz
Fig.10
Fig.11
Fig.12
April 1993
fClK = 100 MHz;
fj = 10 MHz; VI = ±8 lSB at
code 128;50% clock duty
cycle
3-914
-
-
7.7
7.5
7.0
6.5
-
10-11
±O.5
±1
lSB
±O.25
±O.45
lSB
±1
±1.5
lSB
-
bits
bits
bits
bits
.
-
times!
samples
,
Philips Semiconductors
Product specification
a-bit high-speed analog-to-digital
converter
TDA8716
Notes
1. Voltage offset BonOM (VOB) is the difference between the analog input which produces data outputs equal to 00
and the reference voltage BOnOM (VAB). at Tamb = 25°C. Voltage offset TOP (VOT) is the difference between
reference voltage TOP (VAT) and the analog input which produces data outputs equal to FF. at Tamb = 25°C.
2. The analog input is not internally biased. It should be externally biased between V AB and VAT levels.
3. The TDA8716 can only withstand one or two 10K or 100K ECL loads in order to work-out timings at the maximum
sampling frequency. It is therefore recommended to minimize the printed-circuit board load by implementing the
load device as close as possible to the TDA8716.
=
=
4. Full-scale sinewave; fj 4.43 MHz; f CLK • fCLK 100 MHz.
5. Effective bits are obtained via a Fast Fourier Transformer (FFT) treatment taking 4 K acquisition pOints per period.
The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency).
Conversion to SNR: SNR = EB (dB) x 6.02 + 1.76.
percent
change
o
MEA540
I,
"'
(Rthj-a)
-10
-20
.....
~
...............
-30
---....
--- ----
~
-40
--
SOL
-50
-60
o
200
400
600
FigA Average effect of air flow on thermal resistance.
April 1993
3-915
800
air flow (LFPM)
1000
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital
converter
TDA8716
Table 1 Output coding (CPLT2 HIGH).
Table 2 Two's complement coding.
BINARY
STEP
Underflow
0
1
VI (TVP.)
IR
<-3V
-3V
00000000
0
00000000
1
00000001
1
1 (V1H)
o(Vll)
......
......
......
254
255
Overflow
11111110
1
-2V
11111111
1
>-2V
11111111
0
elK
ANALOG
INPUT
vI
DATA
OUTPUT
00·07
Fig.5 Timing diagram.
April 1993
07 (MSB)
CPLT2
OUTPUTS
07 to 00
3·916
non inverted
inverted
Product specification
Philips Semiconductors
8-bit high-speed analog-to-digital
converter
TDA8716
APPLICATION INFORMATION
Additional application information will be supplied upon request. please quote reference number FTV/AN 9109.
OGN02
24
eLK
IR
CLK
2
23
VEE01 (- 5.2 V)
3
22
C pLT2
4
21
V EEA (- 5.2 V)
5
20
VRB (-3.13V)
;t; 100 nF
07
06
05
OGNO(OV)
19
6
TOA8716
7
18
8
17
9
16
10
15
11
14
12
13
04
AGN01
analog input
V RM
03
02
GnF
VRT (-1.87V)
;;t; 100 nF
01
DO
VEED
AGN02
VEE02 (- 5.2 V)
OGN01
MCD260·2
Fig.6 Application diagram; TDA8716.
Notes to Flg.S
1. Typical value for resistors = 2.2 kO.
2. lower resistor values can be used down to 500 0 to obtain higher sampling frequencies in the 150 MSPS range
(limited by td and ~D timings). In this configuration a DC shift of the ECl output levels
VOL
and V OH will occur.
3. VRB • VRT and VM are decoupled to AGND.
4. Analog. digital and output supplies should be separated and decoupled.
5. The external voltage regulator must be constructed in such a way that a good supply voltage ripple rejection is
achieved with respect to the lSB value.
April 1993
3-917
Produ~
Philips Semiconductors
8-bit high-speed analog-to-digital
converter
OGNO
CLK; CLK
VCC01
TDA8716
13,24
AGNO
1 2
VI
3
VCCA
7,11
8
5
MCD262·1
MeD2S1
AGNO
OGNO
C pLT2
VCC02
7,11
~~
13,24
4
VRT
10
VRM
9
VRB
6
:~
:~
J resistor
ladder
IJ
12
~~
VCCA
...
~
.
5
Me
AGNO
7,11
~~
.~
:~
10
OGNO
I
I
9
6
resistor
ladder
07-00
IR
18,19
22-24
26,27
31
3,12
:~
:~
VEEO
:~
5
MeD264
Fig.7 Internal pin configuration diagram.
April 1993
specification
3-918
AlSA6S5
Product .specification
Philips Semiconductors
8-bit high-speed analog-to-digital
converter
TDA8716
MEA537
1.01--- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
LSB
0.5 1'""--------------------------------------------------------
r
.JI
'\....
• ~vt,r L . n . k
...1
I...
Jill
no
~
tl'l ....
JL
I 1.11
J
, Oil
~
• I.... II, 1
LI'VU JllulU'
o I-----_-m.
...........
.----M---=-~~If--i:'\.c.n.--,.lft:'),,'-IL--,,----....--nn::-:lln.....I....'IId-tIr-.P'tI~rR"rl--fI"rllt--ll't:-vt'I-t-1
nt--'tll't---''"---'"--'-I
II'
- - ... \ J~' V. JIf' .I 'U ,.
V' ~_,.....
-u
II
U''''-
"If
-
-0.5 ---'-'--:----- ---,-.-- -'------ ----- - -,. -'-'------------- --...,.--: - --- . . . ----1.01---------------------------------------------------------
o
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
256
CODE
Fig.8 DC Integral linearity error (ILE).
MEA536
1.0 I- - - - -
- - - - --- -
- - -- -- -- -- -- -- -- - - ---- -- - - -
- - - -- - - ---- - - - ---
LSB
0.5 I- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
n
n
n
..
-0.5---------------------------------------------------------1.0 - -- -- - - - - - - -- - - - - - - - - --- - -- - - -- ---- - - -- - - - - -- - - ---- -- - ---
o
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
CODE
Fig.9 DC differential linearity error (OLE).
April 1993
3-919
256
Product specification
Philips Semiconductors
a-bit· high-speed analog-to-digital
converter
TDA8716
MEA535
Or----r------------------------------------------------------,
amplitude
(dB)
-20
-40
-60
-100
-120~~~~--~--~--~--~--~--~--~~--~--~--~--~--~~
o
6.25
12.5
18.7
25.0
31.2
43.7
37.5
50.0
frequency (MHz)
Effective bits: 7.74; Harmonic levels (in dB): 2nd
6th = -63.01
=-69.34; 3rd =-58.85; 4th =-82.55; 5th =-68.16 and
Fig.10 Fast fourier transformer (fClK = 100 MHz; fl = 4.43 MHz).
April 1993
3-920
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital
converter
TDA8716
O.-----------r-------------------------------------------~M=~~
amplitude
(dB)
-20
-40
-100
-120 L - - - - - - '_ _----L_ _----'-_ _- - ' -_ _- - ' -_ _- ' - -_ _- ' -_ _- ' - - -_ _L - - - - - '_ _----'-_ _----'-_ _- - ' -_ _- - ' -_ _- ' - - - - - - - '
o
6.25
12.5
18.7
25.0
37.5
31.2
43.7
50.0
frequency
(MHz)
Effective bits: 7.57; Harmonic levels (in dB): 2nd = -82.07; 3rd = -61.90; 4th = -75.70; 5th = -65.61 and
6th = -72.50
Fig.11 Fast fourier transformer (fcLK = 100 MHz; fi = 10 MHz).
April 1993
3-921
Product specification
Philips Semiconductors
8-bit high-speed analog-to-digital
converter
TDA8716
Or-______________________. -________________________________
~ME=A=~~3
amplitude
(dB)
-20
-40
-60
-100
-120~--~~~~--~--~--~--~--~--~--~--~--~--~--~--~~
o
12.9
6.43
25.7
19.3
45.0
38.6
32.2
51.5
frequency (MHz)
Effective bits: 7.04; Harmonic levels (in dB): 2nd
6th = -61.52
=-61.36; 3rd =-56.66; 4th =-61.97; 5th =-62.79 and
Fig.12 Fast fourier transformer (fcLK = 100 MHz; fi = 20 MHz).
MEA~9
8
effective
bits
7
6
5
4
0
5
4.43 MHz
10
15
20
25
30
40
fi (MHz)
Fig.13 Typical effective bit as a function of input signal at fCLK
April 1993
35
3-922
=100 MHz.
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital
converter
TDA8716
8~--------------------------------------------------------~-~~
effectifs
bits
7---------------------------------------------------------
6.51--- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10
20
30
40
50
60
70
80
90
100
Fig.14 Typical effective bits as a function of clock frequency at fi = 10 MHz.
April 1993
3-923
110
120
f clock (MHz)
Product specification
Philips Semiconductors
TDA8718
8-bit high-speed analog-to-digital converter
FEATURES
GENERAL DESCRIPTION
• 8-bit resolution
The TDA8718 is an 8-bit analog-to-digital converter (ADC)
designed for professional applications. The device
converts the analog input signal into 8-bit binary coded
digital words at a sampling rate of 600 MHz. It has an
effective bandwidth capability up to 150 MHz full-scale
sine wave. All digital outputs are ECl compatible.
• Sampling rate up to 600 MHz
• ECl (1 OOK family) compatible for digital inputs and
outputs
• Overflow/Underflow output
• 50
Q
load drive capability
• low input capacitance (5 pF typ.).
APPLICATIONS
• High speed analog-to-digital conversion
• Industrial instrumentation
• Data communication
• RF communication.
QUICK REFERENCE DATA
Measured over full voltage and temperature ranges, unless otherwise specified.
SYMBOL
V EEA
PARAMETER
MIN.
CONDITIONS
analog supply voltage
-4.2
TYP.
-4.5
MAX.
UNIT
-4.8
V
-4.2
-4.5
-4.8
V
30
45
60
mA
analog supply current
30
42
54
mA
IEED
digital supply current
100
120
150
mA
IEEo(L)
lOW level output supply current
RL = 50 Q
40
70
90
rnA
IEEo(H)
IlE
HIGH level output supply current
RL = 50 Q
155
170
185
mA
DC integral linearity error
-
±0.7
±1.0
lSB
DlE
DC differential linearity error
±0.3
±0.5
lSB
EB
effective bits
-
7.5
-
bits
-
6.5
-
bits
maximum clock frequency
600
-
-
MHz
total power dissipation
-
990
1250
mW
V EED
digital supply voltage
Iref
resistive ladder current
IEEA
R =48 Q
fj = 4.43 MHz; Iref = 45 mA;
fclk = 100 MHz
fj = 4.43 MHz; Iref = 45 rnA;
fclk = 100 MHz
fc1k(max)
P tot
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
PINS
TDA8718K
June 1994
28
I
I
PIN POSITION
PlCC28
3-924
1
1
MATERIAL
plastic
1
I
CODE
SOT261-2
Product specification
Philips Semiconductors
8-bit high-speed analog-to-digital converter
TDA8718
BLOCK DIAGRAM
clock inputs
analog negative
supply voltage
28
TDA8718
18 OGND2 , output
ground
reference VRM
voltage middle -'--'-''-+-------,
reference
VRT
TOP
5
...--_-I_O_F_-+ overflow
output
07
MSB
vo~age
D6
INPUT
AND
OUTPUT
LATCHES
RESISTOR
LADDER
analog
voltage input
05
04
&
32Q
ANALOG SIGNAL
PROCESSING
03
&
DIGITAL
DECODING
01
00
vOlt~~~e~~~~OM-:-V-'-R;;:B:-_'-_-_-_-_-'
VB B
digital ground
OGND1
Fig.1 Block diagram.
June 1994
LSB
~::::...-t---.u~~~;~~w
--+...:;;.__+-____________+1_2_+_ _ _
__
analog ground
data outputs
02
3-925
MBB854-2
Product specification
Philips Semiconductors
TDA8718
8-bit high-speed analog-to-digital converter
PINNING
SYMB
Ol
PIN
DESCRIPTION
VRB
1
reference voltage BOTTOM
VRM
2
reference voltage MIDDLE decoupling
VI
3
analog input voltage
not connected
n.c.
4
VRT
5
reference voltage TOP
OF
6
overflow digital output
n.c.
7
not connected
elK
8
clock input
elK
9
complementary clock input
o·
digital output; bit 7 (MSB)
D7
10
VBB
1'1
Eel reference voltage
OGND1
12
output ground 1 (0 V)
D6
13
digital output; bit 6
D5
14
digital output; bit 5
D4
15
digital output; bit 4
D3
16
digital output; bit 3
D2
17
digital output; bit 2
OGND2
18
output ground 2 (0 V)
D1
19
digital output; bit 1
DO
20
digital output; bit 0 (lSB)
UF
21
underflow digital output
n.c.
22
not connected
VEED
23
digital supply voltage (-4.5 V)
DGND
24
digital ground
n.c.
25
not connected
n.c.
26
not connected
AGND
27
analog ground
VEEA
28
analog supply voltage (-4.5 V)
June 1994
LiS
d>_~~UJi5d
> > > -8 0 x IAT
1
1
1
1
1
1
1
255
Overflow
O/UF
elK
~---;.---+---~--~~--~--~----~----50%
DATA
50%
OF/UF
MSA666
Fig.4 Timing diagram.
June 1994
3-930
Product specification
Philips Semiconductors
TDA8718
8-bit high-speed analog-to-digital converter
M8D879
am~I~)de f - - - - - I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I
-20~--~-------------------------------------I
-40f------I----------------------------------------I
-60f-----I-------~------~------------------------I
-80
6.27
12.S
18.8
31.3
2S.1
37.6
43.9
f (MHz)
SO.2
Effective bits: 7.S3; THD = -S4.S6 dB.
Harmonic levels (dB): 2nd = -77.28; 3rd = -S4.76; 4th = -71.43; Sth = -71.8S; 6th = -10S.S0.
Fig.5 Fast Fourier Transform (fclk
=100 MHz; fi =4.43 MHz).
M8D880
am~I~)de
1-_ _ _ _ _ _ _ _ _ _ _ _ _ _+-_______________________---1
-20~----------------+_----------------------___I
-401----------------+-----------------------~
-60 __-------------34~._------------~~r_-----~
-80
31.2
62.4
Effective bits: 6.60; THD = -48.60 dB.
Harmonic levels (dB): 2nd = -64.81; 3rd = -SUO; 4th
93.S
12S.0
187.0
=-6S.0S; Sth = -S8.33; 6th =-S4.07.
Fig.6 Fast Fourier Transform (fclk
June 1994
lS6.0
3-931
=500 MHz; fj =100 MHz).
218.0
f (MHz)
249.0
Product specification
Philips Semiconductors
TDA8718
8-bit high-speed analog-to-digital converter
APPLICATION INFORMATION
VRM
V RB
22
nF
VI
2
·VRT
V EEA
22
nF
AGND
22
nF
22
nF
****
28
27
n.c.
26
25
n.c.
~
22 nF
24
OF
n.c.
TDA8718
ClK
VBB
V EED
23
ClK
D7
DGND
10
22
n.c.
21
UF
20
11
19
12
13
14
15
16
17
DO
D1
18
-2V
MBB852-2
Fig.7 Application diagram.
June 1994
3-932
Product specification
Philips Semiconductors
YUV 8-bit video low-power
analog;.to-digital interface
TDA8755
FEATURES
APPLICATIONS
• 8-bit resolution
• Sampling rate up to 20 MHz
• High speed analog-to-digital convertion for video signal
digitizing
• TTL compatible digital inputs
• 100 Hz improved definition TV (I DTV).
• 3-state TTL outputs
• U, V two's complement outputs
GENERAL DESCRIPTION
• Y binary output
The TDA8755 is a bipolar 8-bit video low-power
analog-to-digital conversion (ADC) interface for YUV
signals. The device converts the YUV analog input signal
into 8-bit coded digital words in a 4 : 1 : 1 format at a
sampling rate of 20 MHz. The UN signals are converted in
a multiplexed manner. All analog signal inputs are digitally
clamped and a fast precharge is provided for start-up.
All digital inputs and outputs are TTL compatible. Frame
synchronization is supported in a multiplexed manner.
• Power dissipation of 550 mW (typical)
• Low analog input capacitance, no buffer amplifier
required
• High signal-to-noise ratio over a large analog input
frequency range
• Track-and-hold included
• Clamp functions included
• UV multiplexed ADC
• 4: 1 : 1 output data encoder
• Stable voltage regulator included.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN;
CONDITIONS
TYP.
UNIT
MAX.
VecA
V CCD
analog supply voltage
4.75
5.0
5.25
V
digital supply voltage
4.75
5.0
5.25
V
Vcco
output stages supply voltage
4.75
5.0
5.25
V
ICCA
analog supply current
-
46
51
mA
ICCD
digital supply current
55
61
mA
Icco
ILE
output stages supply current
9
12
mA
DC integral linear error
fclk =2 MHz
±0.4
±1
LSB
DLE
DC differential linearity error
f clk =2 MHz
±0.3
±O.5
LSB
EB
effective, bit
-
7.1
-
MHz
fclk(max)
maximum clock frequency
20
-
-
MHz
Ptot
total power dissipation
-
550
650
mW
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
PINS
TDA8755T
32
I
I
PIN POSITION
S032L
I
I
MATERIAL
plastic
"
June 1994
3-933
I
I
CODE
SOT287-1
Cl
c....
c:
5
::J
c
+>-
G')
lJ
VCCA
VCCD
VCCO
AGND
DGND
I
I
I
I
I
132
1 23
1
16
I
INY -...
118
10
CLPU
"?"
-+-
INV
-+-
REG3
I
I
11
12
14
1 13
rIG
11
CLAMP
12
9
CLAMP
V
~
I--I---
co
o~ 6.-+
_0
I
a. <
tOO
So
~
g>
3
g'
::J
a.
t:
c: S
CD
:::+
Sl> 0
(i)
0
.-+~
CLAMP
~
TRACK
AND
HOLD
r-
8-BIT
ADC
8
f-+-r-t
8-BIT
8
PIPELINE ~
Y
TTL
1/0
CD
I
Sl>
0
4"'0
r--24
8
DO} Y
3;- f-+- 07
o
~
CD CD
....,
"'---r0-
t
~
~
DIGITAL
MULTIPLEXER
TRACK
AND
HOLD
16
14
17
TIMING GENERATOR
+
~
s::
o
-0
~
-,
COMPARATOR
16
AND
TMeK
HOLD
U
CLPV
"'
CLAMP
LOGIC
w
cO
w
INU
REG2
I
8
i
15
+>-
REG1
I
3
I
CLP
n.c.
.~
SUPPLY AND REFERENCE
VOLTAGE REGULATOR
5
CLPY
SON
l>
-<
C
<
ex>
Sl>
:::J
Sl>
f-
-'--
4
I<-lJ
t
~
HREF
CE
ClK
ANALOG
MULTIPLEXER r
....
TRACK
AND
HOLD
I
I
r-
8-BIT
ADC
COMPARATOR
128
8
f-+-r--
UANDV
DATA
ENCODER
TTL
1/0
I---t
----
19
2
D'O} V
~ f-+- 0'1
21
~
rJ
D'2} U
0'3
TDA8755
MLA734-1
-u
-I
0
S
ex>
"0
CD
0
::::a;
»
-..J
Fig.1 Block diagram.
a
a.
01
01
t:
CIi
0'
~
O·
::J
Product specification
Philips Semiconductors
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
PINNING
SYMBOL
PIN
DESCRIPTION
n.c.
1
not connected
REG1
2
decoupling input (internal
stabilization loop decoupling)
INY
3
Y analog voltage input
REG2
4'
decoupling input (internal
stabilization loop decoupling)
ClPY
5
Y clamp capacitor connection
VCCA
6
analog positive supply vokage
(+5 V)
INU
7
U analog voltage input
VCCO
SDN
8
stabilizer decoupling node and
analog reference voltage (+3.35 V)
07
INV
9
V analog voltage input
AGND
10
analog ground
05
06
ClPU
11
U clamp capacitor connection
04
ClPV
12
V clamp capacitor connection
03
REG3
13
decoupling input (internal
stabilization loop decoupling)
02
CE
14
chip enable input (TTl level input
active lOW)
ClP
15
clamp control input
AGNO
vcca
HREF
16
horizontal reference signal
ClPU
0'3
ClK
17
clock input
ClPV
0'2
OGND
18
digital ground
D'O
19
V data output; bit 0 (n-1)
REG3
0'1
0'1
20
V data output; bit 1 (n)
0'2
21
U data output; bit 0 (n-1)
0'3
22
U data output; bit 1 (n)
Vcca
23
positive supply voltage for output
stages (+5 V)
00
24
Y data output; bit 0 (lSB)
01
25
Y data output; bit 1
02
26
Y data output; bit 2
D3
27
Y data output; bit 3
04
28
Y data output; bit 4
D5
29
Y data output; bit 5
06
30
Y data output; bit 6
07
31
Y data output; bit 7 (MSB)
Vcco
32
digital positive supply voltage (+5 V)
June 1994
01
00
0'0
BE
ClP
OGNO
HREF
ClK
MLA728·1
Fig.2 Pin configuration.
3-935
Product specification
Philips Semiconductors
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL
PARAMETER
MIN.
CONDITIONS
MAX.
UNIT
VCCA
analog supply voltage
-0.3
+7.0
VecD
digital supply voltage
-0.3
+7.0
V
Vcco
output stages supply voltage
-0.3
+7.0
V
!:Nec
supply voltage difference between VecA and V CCD
-1.0
+1.0
V
supply voltage difference between V cco and V CCD
-1.0
+1.0
V
supply voltage difference between V CCA and V cco
-1.0
+1.0
V
V
VI
input voltage
referenced to AGND
-
+5.0
V
Vclk(p-p)
AC input voltage for switching (peak-to-peak value)
referenced to DGN D
VCCD
V
10
output current
-
+6
mA
T8t9
storage temperature
-55
+150
°C
Tamb
operating am bient tem perature
0
+70
°C
Tj
junction temperature
-
+150
°C
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
PARAMETER
thermal resistance from junction to ambient in free air
June 1994
3-936
Product specification
Philips 8em iconductors
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
CHARACTERISTICS
VCCA =V6 to VlO = 4.75 to 5.25 V; VCCD =V 32 to V 18 = 4.75 to 5.25 V; Vcco = V 23 to V 18 = 4.75 to 5.25 V;
AGND and DGND shorted together; VCCA to VCCD = -0.25 to +0.25 V; Vcco to VCCD = -0.25 to +0.25 V;
VCCA to Vcco = -0.25 to +0.25 V; Tamb = 0 to +70 °C; typical values measured at VCCA = VCCD =Vcco = 5 V and
Tamb =25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VCCA
analog supply voltage
4.75
5.0
5.25
V
V CCD
digital supply voltage
4.75
5.0
5.25
V
Vcco
output stages supply voltage
4.75
5.0
5.25
V
ICCA
analog supply current
46
51
rnA
ICCD
digital supply current
-
55
61
rnA
Icco
output stages supply current
-
9
12
rnA
V IL
lOW level input voltage
0
-
0.8
V
V IH
HIGH level input voltage
2.0
VCCD
V
IlL
lOW level input current
-
flA
IIH
HIGH level input current
100
flA
ZI
input impedance
4
input capacitance
-
kQ
CI
-
-
Inputs
ClK (PIN 17)
= 0.4 V
V clk = 2.7 V
fclk = 20 MHz
fclk = 20 MHz
V clk
-400
4.5
pF
CE, ClP AND HREF (PINS 14 TO 16)
VIL
lOW level input voltage
0
-
0.8
V
V IH
HIGH level input voltage
2.0
-
V CCD
V
IlL
lOW level input current
-400
-
flA
IIH
HIGH level input current
-
100
flA
-
3.725
-
V
±50
-
flA
-
3.30
-
V
±50
-
flA
= 0.4 V
Vclk =2.7 V
V clk
-
ClPY (PIN 5)
Vs
clamp voltage for 16 output code
15
clamp output current
ClPU AND ClPV (PINS 11 AND 12)
V 11 . 12
clamp voltage for 128 output code
111 ,12
clamp output current
INY (PIN 3)
VI(p_p)
input voltage, full range
(peak-to-peak value)
fi
=4.43 MHz
0.93
1.0
1.07
V
ZI
input impedance
fj
fj
-
-
kQ
input capacitance
= 6 MHz
= 6 MHz
30
CI
June 1994
3-937
1
pF
Product specification
Philips Semiconductors
YUV 8-bit video low-power
analog-to-digital interface
SYMBOL
PARAMETER
TDA8755
TYP.
MIN.
CONDITIONS
UNIT
MAX.
INU AND INV (PINS 7 AND 9)
VI(p_p)
input voltage, full range
(peak-to-peak value)
fi = 1.5 MHz
0.9
1.0
1.1
V
ZI
input impedance
fi = 2 MHz
fi = 2 MHz
1
-
kQ
input capacitance
-
30
CI
-
-55
-50
dB
pF
I NPUTS ISOLATION
act
crosstalk between Y, U and V
Outputs
SDN (PIN 8)
Vref
reference voltage
VREG
line regulation
IL
load current
4.75 V s VCCA s 5.25 V
-
3.35
-
V
-
4.0
mV
-2
-
-
mA
DIGITAL OUTPUTS DO TO D7 AND D'O TO D'3 (PINS 24 TO 31 AND 19 TO 22)
VOL
LOW level output voltage
10 = 0.4 mA
0
-
0.4
V
10 = 1.5 mA
0
-
0.5
V
V CCD
V
+20
I-tA
-
-
MHz
2.0
MHz
-
-
ns
VOH
HIGH level output voltage
10 = -0.4 mA
2.4
loz
output current in 3-state mode
0.4 V < Vo < VCCD
-20
Switching characteristics
felk(max)
maximum clock frequency
20
felk(min)
minimum clock frequency
-
tCPH
clock pulse width HIGH
20
tCPL
clock pulse width LOW
20
ns
Analog signal processing (felk = 20 MHz; 50% clock duty factor)
Gdiff
differential gain
note 1; see Fig.8
-
2
-
3
-
%
note 1; see Fig.8
-
0
dB
-
-54
-
dB
IPdiff
differential phase
f1
fundamental harmonics (full-scale) note 2
fall
harmonics (full-scale),
all components
note 2; see Fig.1 0
deg
SVRR1
supply vOltage ripple rejection 1
note 3
-
-40
SVRR2
supply voltage ripple rejection 2
note 3
-
1.0
-
%N
dB
Transfer function (50% clock duty factor)
ILE
DC integral linearity error
felk= 2 MHz
-
±0.4
±1.0
LSB
DLE
DC differential linearity error
felk= 2 MHz
±0.3
±0.5
LSB
AILE
AC integral linearity error
note 4
-
±1.0
±2.0
LSB
EB
effective bit
note 5; Fig.10
-
7.1
-
bits
June 1994
3-938
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-d ig ital interface
SYMBOL
TDA8755
PARAMETER
Timing (note 6; see Figs 3 to 7; fclk
CONDITIONS
MIN.
TYP.
MAX.
UNIT
=20 MHz)
tds
sampling delay time
-
1
-
ns
th
output hold time
7
-
-
ns
td
output delay time
-
33
42
ns
tdZH
3-state output delay time
enable-to-H IGH
-
10
14
ns
tdZ L
3-state output delay time
enable-to-LOW
-
10
14
ns
tdHZ
3-state output delay time
disable-to-HIGH
8
11
ns
tdLZ
3-state output delay time
disable-to-LOW
-
4
6
ns
tr
clock rise time
3
5
tf
clock fall time
3
5
tsu
HREF set-up time
7
th
HREF hold time
3
-
-
tr
data output rise time
10
tf
data output fall time
-
tCLP
minimum time for active clamp
3
note 7; see Fig.9
ns
ns
ns
ns
10
-
ns
-
-
f.ls
ns
Notes
1.
Low frequency ramp signal (V1(p-p) =full-scale and 64 f.ls period) combined with a sine wave input voltage
(VI(p_p) = 0.25 full-scale, fj = maximum permitted frequency) at the input.
2.
The input conditions are related as follows:
a) Y channel: VI(p_p)
=1.0 V; fj =4.43 MHz
b) UN channel: VI(p_p)
3.
= 1.0 V; fj = 1.5 MHz.
Supply voltage ripple rejection:
a) SVRR1 is the variation of the input voltage producing output code 127 (code 15) for supply voltage variation
of 0.5 V:
SVRR1
= 20
/:;.V
log~
/:;,V CCA
b) SVRR2 is the relative variation of the full-scale range of analog input for a supply voltage variation of 0.5 V:
SVVR2
= /:;.(VI(O) -V I (255))
VI (0)
-
VI (255)
x _1_
/:;. V CCA
=4.43 MHz for Y and fj = 1.5 MHz for U and V; fclk =20 MHz).
4.
Full-scale sine wave (fj
5.
The number of effective bits is measured using a 20 MHz clock frequency. This value is given for a 4.43 MHz input
frequency on the Y channel (1.5 MHz on the U and V channels). This value is obtained via a Fast Fourier Transform
(FFT) treatment taking 4 x Tclk (clock periods) acquisition points per period. The calculation takes into account all
harmonics and noise up to half of the clock frequency (NYQUIST frequency).
Conversion to signal-to-noise ratio: SIN
= EB x 6.02 + 1.76 dB.
6.
Output data acquisition is available after the maximum delay time of td.
7.
U and V output data is not valid during tCLP.
June 1994
3-939
Product specification
Philips Semiconductors
YUV 8-bit video low-power
analog-to-digital interface
Table 1
TDA8755
Mode selection.
CE
07 TO DO; 0'3 TO 0'0
1
high impedance
0
active; binary
Table 2 Output data coding.
OUTPUT PORT
BIT
Y
07
Y07
Y 17
Y 27
Y37
06
Y o6
Y 16
Y26
Y36
Y3 5
U
V
tCPH
OUTPUT DATA
05
Yo5
Y 15
Y 25
04
Y04
Y 14
Y 24
Y3 4
03
Y03
Y 13
Y 23
Y 33
02
Y02
Y1 2
Y 22
Y3 2
01
Y01
Y 11
Y 21
Y 31
00
YoO
Y 10
Y 20
Y3 0
0'3
Uo7
U05
U03
Uo1
0'2
U06
U04
Uo2
UoO
0'1
V07
Vo5
V 03
V o1
0'0
V 06
Vo4
V 02
VoO
tCPl
1.4 V
ClK
sample N+3
#'
VI
tds
2.4V
DO to D7
DATA
N-4
1AV
0.4 V
Fig.3 Timing diagram (INY signal).
June 1994
3-940
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
CE
output
data
output
data
TEST
VCCD
S1
1
ICE =
tdZL
tdHZ
GND
tdZH
GND
MBD874
100 kHz.
Fig.4 Timing diagram and test conditions of 3-state output delay time.
TDA8755
MLA733- 1
Fig.5
June 1994
Load circuit for the 3-state output timing
measurement.
3-941
S1
VCCD
VCCD
tdLZ
Product specification
Philips Semiconductors
YUV 8-bit video low-power
analog-to-digital interface
sample N
TDA8755
sample N+4
eLK
HREF
MLA73R· ,
output
data
The output data is valid 4 clock periods after HREF goes HIGH.
Fig.6 Timing definition for set-up and hold times (HREF signal).
4 clock periods (Tclk)
sample N
sample N+4 xT elk
elK
HREF
output
data
MLA731-1
When the HREF period is a multiple of 4 clock periods, the output data is valid without any clock delay.
The internal circuit always gives an internal delay of 4 clock periods as illustrated in Fig.S.
Fig.? Timing diagram (HREF signal)_
June 1994
3-942
Product specification
Philips Semiconductors
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
Y, U and V
channel
1.0V
025V
1
I~.1---------- 64 Jl.S _ _ _ _ _ _ _ _ _....1
MSA644
Y channel = 4.43 MHz sine wave.
U, V channel = 1.5 MHz sine wave.
Fig.8 Input test signal for differential gain and phase measurements.
digital
output
level
MSA645
t
255
black-level
clamping
Y: 16
U,V: 128
_time
D--I t CLP
CLP _ _ _ _ _ _ _ _
Fig.9 Clamping control timing.
June 1994
3-943
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
MBD873
amplitude 1 - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - 1
(dB)
-20r-----------------r-------------------~
-401--------------------+---------------------------1
-601----------~----------+-------~-------~--~
-80
1.25
2.50
3.75
5.00
6.25
7.50
8.75
10.00
f (MHz)
Effective bits: 7.30; THD = -53.35 dB.
Harmonic levels (dB): 2nd
= -58.38; 3rd = -60.03; 4th = -57.30; 5th = -69.38; 6th = -67.09.
Fig.10 Fast Fourier Transform (fclk
June 1994
3-944
=20 MHz; fi =4.43 MHz).
Product specification
Philips Semiconductors
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
APPLICATION INFORMATION
VCCD
n.C.
10 nF
AGND~
32
5V
10nF
REG1
D7
31
1
DGNO
-H
(3)
+
INY
D6
3
30
4.71'F
REG2
AGND~
29
05
220 nF
AGND~
ClPY
VCCA
5V
6
27
D4
D3
10 nF
I
D2
INU
(3;-H
26
+
4.71'F
D1
SON
+ 3.35 V
(2)
28
(1)
;;J; 10 nF
.
TDA8755
-H
(3)
25
+
INV
DO
24
4.71'F
AGND
Vcca
10
23
5V
10nF
AGND~
ClPU
(1)
11
22
D'3
1
DGND
AGND~
ClPV
12
21
13
20
14
19
15
18
16
17
D'2
(1)
REG3
AGND~
D'1
220 nF
CE
ClP
HREF
0'0
OGND
ClK
MLA735- f
The analog and digital supplies should be separated and decoupled.
(1) Clamp capacitors must be determined in accordance with the application; recommended values are ClPY = 18 nF, ClPU and ClPV = 33 nF.
(2) It is possible to use the reference output vo~age pin SON to drive other analog circuits under the limits indicated in Chapter "Characteristics".
(3) Input signal pins have a high bandwidth. It is necessary to take special care on PCB layout to avoid any interaction from other signals (digital clocks
for example).
Fig.11 Application diagram.
June 1994
3-945
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
SAA7158
SAA4940
NOISE
REDUCTION
INCLUDING
CROSS-COLOUR
REDUCTION
TDA8755
12
:
VIDEO
ENHANCEMENT,
LFR
V
PROCESSING
AND DACs
)
Vi~oeo
processor
12
12/13.5/16/18 MHz
control
32/36 MHz
H2, V2
(32 kHz/1 00 Hz)
VSYNC
SC1
1
27 MHz
2C
MSA642
Fig.12 Block diagram of a full-options Improved Picture Quality (IPQ) module.
June 1994
3-946
} deflection
to
processor
Product specification
Philips Semiconductors
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
VIDEO
ENHANCEMENT
AND
DACs
12
TDA8755
Y
U
)
video
ill
processor
V
SAA7165
12 C-bus
12/13.5/16/18 MHz
control
32/36 MHz
H2, V2
(32 kHz/100 Hz)
VSYNC
SC1
27 MHz
~----- 1ST FIELD
2ND FIELD
625
50 Hz
1
!
ASCillD
I
VA
~L__________________________~___________________
J
!
...L 2ND
1ST FIELD
FIELD
I
ASC
....i-. 1ST
2ND FIELD
525
1ST FIELD
262!
!
FIELD
60 Hz
1
12ND FIELD
:
I
ASC
Fig.7 Acquisition sandcastle signal and VA pulse timing diagram.
December 1992
3-1019
Philips Semiconductors Video Products
Objective specification
PAUNTSC/SECAM
decoder/sync processor
TDA9141
. Table 1 Slave address (SA).
__
'1~ A_6__-+I____:5____~1___A_:___+----:-3--~---A2----~---:-1--~---A-O---+---RNY-X---~
Table 2 Inputs.
SUBADDRESS
MSB
LSB
00
INA
INB
TB
ECMB
FOA
FOB
XA
01
FORF
FORS
OPA
OPB
pac
FM
SAF
FROF
02
EFS
STM
HU5
HU4
HU3
HU2
HU1
HUO
03
LCA
-
-
-
-
-
-
-
I paR
I FSI
Iyc
ISL
XB
Table 3 Outputs.
I ADDRESS
ISAK
ISBK
I FRO
12C-bus protocol
If the address input is connected to the positive supply the address will change from SA to SE.
Valid subaddresses = 00 to OF
Auto-increment mode available for subaddresses.
= 0; send subaddress 00 with the crystal indicator bits (XA and
XB) indicating that only one crystal is connected to the IC; wait for 250 ms; send subaddress 01; wait for at least
100 ms; set XA, XB to the actual crystal configuration.
Each time before the data in the IC is refreshed, the staus byte must be read. If POR = 1, then the above procedure
must be carried out to restart the IC.
Failure to stick to the above procedure may result in an incorrect line frequency after power-up or a power-dip.
Start-up procedure: read the status byte until paR
December 1992
3-1020
Objective specification
Philips Semiconductors Video Products
PAUNTSC/SECAM
decoder/sync processor
TDA9141
INPUT SIGNALS
Table 4 Source select.
INA
INB
0
0
1
a
Table 9 Forced field frequency.
SOURCE
FORF
FORS
0
FIELD FREQUENCY
1
YC
a
a
1
60 Hz
-
auto CVBSIYC
1
a
50 Hz
1
1
auto; 50 Hz if no lock
CVBS
auto; 60 Hz if no lock
Table 5 Trap bypass.
TB
CONDITION
a
trap not bypassed
1
trap bypassed
Table 10 Output value 1/0 port.
OPA
CONDITION
0
LOW
1
HIGH
Table 6 Comb filter enable.
ECMB
0
1
CONDITION
Table 11 Output value 0 port.
CONDITION
comb filter disabled
OPB
comb filter enabled
0
LOW
1
HIGH
Table 7 Phase 1 time constant.
MODE
Table 12 Phase 1 loop control.
FOA
FOB
0
0
1
auto
POC
a
slow
a
phase one loop closed
1
-
fast
1
phase one loop open
Table 8 Crystal indication.
CONDITION
Table 13 Forced standard.
XA
XB
FM
SAF
FRQF
0
a
2 x 3.6 MHz
-
-
auto search
a
0
1
1 x 3.6 MHz
1
a
PAUNTSC second crystal
a
a
1
1 x 4.4 MHz
1
0
1
PAUNTSC reference crystal
1
1
3.6 and 4.4 MHz
1
1
a
illegal
1
1
1
SECAM reference crystal
CRYSTAL
STANDARD
Note to Table 13
If XA and XB indicate that only one crystal is connected
to the IC and FM and FRQF force it to use the second
crystal the colour will be switched off.
December 1992
3-1021
Philips Semiconductors Video Products
Objective specification
PAUNTSC/SECAM
decoder/sync processor
TDA91-41
Table 14 Fast switch enable.
EFS
0
1
Table 20 Input switch mode.
CONDITION
YC
fast switch disabled
fast switch enabled
0
1
0
1
SL
CONomON
0
search tuning mode off
search tuning mode on
1
FUNCTION
ADDRESS
HU5to HUO
LCA
1
",
Table 23 Standard read-out.
CONDitiON
OPB/CLP mode
LLC/HAmode
OUTPUT SIGNALS
Table 18 Power-on reset.
POR
0
1
CONDITION
normal mode
power-down mode
Table 19 Field frequency indication.
FSI
CONDITION
0
50 Hz
1
60Hz
December 1992
not locked
lOCked
DIGITAL NUMBER
000000 =-45 0
111111 =+45 0
Table 17 Line-locked clock active.
0
CONDITION"
Table 22 Input value 1/0 port.
Table 16 Hue.
hue
CVBSmode
YC mode
Table 21 Phase 1 lock indication; "
Table 15 Search tuning mode.
STM
CONDITION
3-1022
SAK
SBK
FRQ
STANDARD
0
0
0
0
1
1
1
0
0,
PAL ~condcrystal
PAL reference crystal
NTSC second crystal
NTSC reference crystal
illegal forced mode
SECAM reference crystal
colour off
0
1
1
1
0
0
1
0
1
0
1
-
Philips Semiconductors Video Products
Objective specification
PAUNTSC/SECAM
decoder/sync processor
TDA9141
LIMITING VALUES
In accordance with the Absolute Maximum Rating System. (IEC134)
SYMBOL
PARAMETER
CONOmONS
MIN.
-
Vee
positive supply voltage
Icc
supply current
Plot
total power dissipation
Tslg
storage temperature
Tamb
operating ambient temperature
ESO
electrostatic discharge (on all pins)
MAX.
UNIT
8.8
V
-
60
rnA
-
530
mW
-55
+150
°C
-10
+65
°C
V
V
Human body model
note 1
-2000
+2000
Machine model
note 2
-200
+200
Notes to the limiting values
1. Equivalent to discharging a 100 pF capacitor via a 1.5 kn series resistor.
2. Equivalent to discharging a 200 pF capacitor via a 0 n series resistor.
THERMAL RESISTANCE
SYMBOL
RIh j-a
December 1992
PARAMETER
from junction to ambient in free air
3-1023
THERMAL, RESISTANCE
48KIW
Objective specification
Philips Semiconductors Video Products
PAL/NTSC/SECAM
decoder/sync processor
TDA9141
CHARACTERISTICS
Vce
=B V; Tamb =25°C; unless otherwise specified.
CONOmONS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply
Vee
positive supply voltage
7.2
B.O
B.B
V
Icc
supply current
-
45
Plot
total power dissipation
-
360
-
rnA
mW
Input switch
Y/CVBS
INPUT (PIN
26)
V26(p.p)
input voltage (peak-to-peak value)
ZI
input impedance
C
INPUT (PIN
top sync - white
-
1.0
1.43
V
60
-
-
kQ
25)
V25(p·P)
input burst voltage (peak-to-peak value)
-
0.3
0.43
V
ZI
input impedance
60
-
--
kQ
V
CVBS OUTPUT
(PIN
22)
ONLY ADDRESS
BA
V 22(P'P)
output voltage (peak-to-peak value)
-
1.0
-
Zo
output impedance
-
-
500
Q
VIsI
top sync voltage level
-
2.B
-
V
-
5.0
-
V
reference crystal 4.4 MHz
±400
Hz
tbf
-
Hz
second crystal 3.6 MHz
±300
-
-
reference crystal 3.6 MHz
-
Hz
-
-
5
deg
-
5
deg
-
tbf
-
HzlK
-
1.0
-
kQ
1.5
-
kQ
-
tbf
-
V
150
200
300
mV
top sync - white
Bias generator (pin 8)
Va
digital supply voltage
Subcarrier regeneration
GENERAL
CR
q>
catching range
note 1
phase shift
for 400 Hz deviation
4.4 MHz
for 300 Hz deviation
3.6 MHz
TC
temperature coefficient of oscillator
ZI
input impedance
reference crystal input
second crystal input
Vdep
supply voltage dependency
FSCOMB OUTPUT (PIN
23)
C L = 15
VU(P'P)
subcarrier output amplitude
(peak-to-peak value)
Vcen
comb enable voltage level
4.0
4.2
-
V
Veas
comb disable voltage level
-
O.B
1.4
V
December 1992
3-1024
pF
Philips Semiconductors Video Products
Objective specification
PAUNTSC/SECAM
decoder/sync processor
SYMBOL
TDA9141
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Isink
minimum sink current to force output
to comb disable level
0.4
-
2.0
rnA
RaND
value of grounded resistor to force output
to comb disable level
0.4
-
2.0
kn
ACC control range
-20
dB
-
-
+5
change of -(R-Y) and -(B-Y) signals over
ACCrange
1
dB
PAUNTSC
-
-25
-
dB
SECAM
-
-23
dB
-
3
-
ACC
colour killer threshold
kill - unkill hysteresis
dB
Demodulators -(R-Y) and -(B-Y) outputs (pins 1 and 2)
1.20
1.27
1.34
temperature coefficient of -(R-Y) and
-(B-Y) amplitude
-
tbf·
-
HzIK
spread of -(R-Y) and -(B-Y) ratio
between standards
-1
-
+1
dB
-
V
ratio of -(R-Y) and -(B-Y) signals
TC
standard colour bar
V1
output level of -(R-Y) during blanking
-
2.0
V2
output level of -(B-Y) during blanking
-
2.0
V
B
-3 dB bandwidth
-
1
-
MHz
Zo
output impedance
-
-
,500
n
Vdep
supply voltage dependency
-
tbf
-
V
525
585
mV
PAUNTSC DEMODULATOR
-(R-Y) output voltage (peak-to-peak value)
standard colour bar
470
V2(P'P)
-(B-Y) output voltage (peak-to-peak value)
standard colour bar
595
665
740
mV
ex
crosstalk between -(R-Y) and -(B-Y)
-
tbt
-
dB
V1(P'P)
V1.2(P-P)
8.8 MHz residue (peak-to-peak value)
both outputs
-
-
15
mV
V 1.2(P-P)
7.2 MHz residue (peak-to-peak value)
both outputs
-
-
20
mV
-
50
mV
46
-
-
dB
-
±45
-
deg
PAL DEMODULATOR
VR(p_P)
H/2 ripple (peak-to-peak value)
SIN
signal-to-noise ratio
NTSC DEMODULATOR
3.46
1
1
1
1
1
1
1
1
1
Table 2
Mode selection.
07 TO 00
CE
O/UF
1
high impedance
high impedance
0
active; binary
active
ClK
--i--\;---/---\;------ci----\,----/----'\__ 1.4 V
,..---..........,.,.,... 2.4 V
DATA
DO to 07
1.4V
'--_.J,..I.J.~
Fig.5 Timing diagram for data output.
June 1994
3-1041
0.4V
Product specification
Philips Sem iconductors
8-bit high-speed analog-to-digitalconverter
TDF8704
VCCD
CE
output
data
output
data
TEST
tdLZ
VCCD
~ZL
VCCD
tdHZ
GND
tdZH
GND
MLB880
ICE = 100 kHz.
Fig.6 Timing diagram and test conditions of 3-state output delay time.
00 to, 07
M88956·!
Fig.7 Load circuit for timing measurement.
June 1994
3-1042
$1
Product specification
Philips Semiconductors
TDF8704
8-bit high-speed analog-to-digital converter
code 255
code 0
ClK
MB0869
0.5 ns
Fig.8 Analog input settling-time diagram.
am~~de r - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _ 1
-20r--------+---------------------------------------------------------------40r--------+---------------------------------------------------------------
-60r--------+----------------~--------------------------------------------_1
-80
1.25
2.49
Effective bits: 7.89; THO = -61.05 dB.
Harmonic levels (dB): 2nd =-84.07; 3rd
3.74
4.98
7.47
=-62.50; 4th =-92.01; 5th =-66.56; 6th =-101.15.
Fig.9 Fast Fourier Transform (fclk
June 1994
6.23
3-1043
= 20 MHz; fi = 1.25 MHz).
8.72
f (MHz)
9.96
Product specification
Philips Semiconductors
8-bit high-speed
an~log-to-digitalconverter
TDF8704
MBD871
amplitude I - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - l
(dB)
-201--------+------------------------------l
-40r--------~-----------------------------l
-60r--------~~----------------~-------------l
-80
2.48
4.96
Effective bits: 7.61; THD = -57.11 dB.
Harmonic levels (dB): 2nd =-68.53; 3rd
7.44
9.93
12.4
14.9
17.4
f (MHz)
19.9
=-58.36; 4th =-74.89; 5th =-65.37; 6th =-76.08.
Fig.10 Fast Fourier Transform (fclk
=40 MHz; fi =4.43 MHz).
MBD872
am~~de
r---------------;-----------------------1
-20~-------------_+---------------------~
-40r---------------+-----------------------l
-60~-------------_+-------------"h_------~
-80
3.12
6.24
Effective bits: 6.91; THD = -46.13 dB.
Harmonic levels (dB): 2nd =-59.66; 3rd
9.35
12.5
113.7
=-46.67; 4th =-70.80; 5th =-57.96; 6th =-72.16.
Fig.l1 Fast Fourier Transform (fdk
June 1994
15.6
3-1044
=50 MHz;fi =10 MHz).
21.8
f (MHz)
24.9
Product specification
Philips Sem iconductors
8-bit high-speed analog-to-digital converter
TDF8704
INTERNAL PIN CONFIGURATIONS
vee01
veeA -~~-------
07 to DO
(x 90)
O/UF
---1f-4_--+-+--L~-:J--'
OGNO
-11---~-,-+-----
AGNO ---ll---~---+---~
ML8037
MLB036
Fig.12 TIL data and overflow/underflow outputs.
Fig.13 Analog inputs.
OGNO---1~-+-----~
MLB038
Fig.14 CE (3-state) input.
June 1994
3-1045
Product specification
Philips Semiconductors
TDF8704
8-bit high-speed analog-to-digital converter
VCCA-4-~-------~-~---~---~
VFjB
DEC --I--+----1'--I----.....J
AGND--I---4~--------~------~-~---~
MSA687
Fig.15
and DEC.
VRB, VAT
VCCD---~-----~~-~-----
ClK ----+..--....--+----I
I--~I--- Vref
30kn
--+-------
DGND-----4--~__
Fig.16 ClK input.
June 1994
3-1046
~CDI89.1
Product specification
Philips Semiconductors
8-bit high-speed analog-to-digital converter
TDF8704
APPLICATION INFORMATION
01
24
2
00
23
(2)
n.c.
V
(1)
RB
4
OEC
5
10 nF
AGNO
6
l47 PF
AGNO
22
l
AGNO
21
20
19
02
03
CE
V CC02
OGNO
VCC01
TDF8704
V CCA
7
VI
8
18
17
VCCO
OGNO
(1)
VRT
I
100 nF
9
16
ClK
(2)
n.c.
10
15
04
AGNO
O/UF
11
07
12
14
13
05
06
MSA684
The analog and digital supplies should be separated and decoupled.
(1) VRS and VAT are decoupling pins for the internal reference ladder; do not draw current from these pins in order to achieve good linearity.
(2) Pins 3 and 10 should be connected to OGNO in order to prevent noise influence.
Fig.17 Application diagram.
June 1994
3-1047
Desktop Video Products
Section 4
Package Outlines
CONTENTS
SOT38-1
SOT96A
SOT101
SOT102
SOT109A
SOT117-1
SOT129
SOT136-1
SOT137-1
SOT146EF4
SOT158A
SOT162-1
SOT163AG7
SOT187
SOT188AA
SOT189CG
SOT225
SOT232
SOT234AG
SOT247-1
SOT261-2
SOT287-1
SOT307-2
SOT313-2
SOT317
SOT318
SOT34Q-1
SOT349
Plastic dual in-line package; 16 leads (300 mil) .............................................................
8-Pin Plastic SOL (Small Outline Large) Dual In-Line (DfT) Package .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24-Pin Plastic Dual In-Line (NIP) Package with Internal Heatspreader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18-Pin Plastic Dual In-Line (NIP) Package with Internal Heatspreader .. .... .. .. .. . . . .. . ... ... .. .. . . .. . . .. . .. ...
16-Pin Plastic SO (Small Outline) Dual In-Line (DfT) Package ................................................
Plastic dual in-line package; 28 leads (600 mil) with internal heat spreader .....................................
40-Pin Plastic Dual In-Line (NIP) Package .................................................................
Plastic small outline package; 28 leads; large body .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Plastic small outline package; 24 leads; large body ......... " ........ , ..... , . . . . . .. . . . . . .. ... . . . . . . . . . . . . . . .
20-Lead Dual In-Line; Plastic ........................... , ..... , ............................ , . . .. . . . . . . . . ..
40-Pin Plastic VSO (Very Small Outline) Dual In-Line (DfT) Package .......... , ..... , .. : . . . . . .. . . . . . . .. . . . . . . ..
Plastic small outline package; 16 leads; large body ........................................... , .......... , ...
20-Lead Mini-pack; Plastic ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
44-Pin Plastic Leaded Chip Carrier; Pocket Version (A) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
68-Pin Plastic Leaded Chip Carrier; Pocket Version (A) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
84-Pin Plastic Leaded Chip Carrier (A) Package ............................................................
160-Pin Plastic Quad Flat Pack (H) Package ...............................................................
32-Pin Plastic Shrink Dual In-Line (NIP) Package ...........................................................
24-Lead Plastic Shrink Dual In-Line Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
52-Pin Shrink Dual In-Line Package; Plastic .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Plastic leaded chip carrier, 28 leads ..................................................... .. . . . . . . . . . . . . . . ..
Plastic small outline package; 32 leads; large body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
44-Pin Plastic Quad Flat Pack (8) Package ................................................................
Plastic thin quad flat package; 48 leads; 7 x 7 x 1.4 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
100-Pin Plastic Quad Flat Pack (8) Package ...............................................................
80-Pin Plastic Quad Flat Pack (8) Package ................................................................
Plastic shrink small outline package; 24 leads; medium body .................................................
120-Pin Plastic Quad Flat Pack (8) Package...............................................................
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
Philips Semiconductors Video Products
Package outlines
SOT38-1
PLASTIC DUAL IN-LINE PACKAGE; 16 LEADS (300 MIL)
r - - - - - - - - ~~:~~ - - - - - - - - - ,
max
+
max
16
9
-t
6.48
Dimensions in mm.
June 1994
4-3
Philips Semiconductors Video Products
Package outlines
SOT96A
a-PIN PLASTIC SOL (SMALL OUTLINE LARGE) DUAL IN-LINE (OfT) PACKAGE
~_ _ 5.0~
14---U--4.0
4.8
3.8
top view
SOT96A
June 1994
7Z68240.8
4-4
Philips Semiconductors Video Products
Package outlines
S0T101
24-PIN PLASTIC DUAL IN-LINE (NIP) PACKAGE WITH INTERNAL HEATSPREADER
1.------------------------c
32 max
-------------------------.1
_ _ _ ...J
Ij
5,1
max
~
+•
+0.511
mm •
+
3,9
-
076 121
3,4
+
2,2
max
i....
top view
131
4
11
Eft
Maximum Material Condition.
(1)
Centre-lines of all leads are
within ±0,127 mm of the
nominal position shown; in
the worst case, the spacing
between any two leads may
deviate from nominal by
:!:O,254 mm.
(2)
Lead spacing tolerances apply
from seating plane to the line
indicated.
(3)
Index may be horizontal as
shown, or vertical.
side view
I
I
II
II
:1
1,1
------ M
Dimensions in mm
---___.1
17,15 _ _ _ _ _ _--+
15,90
SOT101A. B. F. G. l
June 1994
Positional accuracy.
@
7Z73670.5
4-5
Philips Semiconductors Video Products
Package outlines
SOT102
18~PIN PLASTIC DUAL IN-LINE (N/P)PACKAGE WITH INTERNAL HEATSPREADER
22 max
side view
I
•
1
3,9
3,4
.11
+
0,85...
max
I
II
0,32
I.
...1..
...1.
...1...
...1...
max
~
''''
...1 ......1
~'
_. [IT]
,
.
'
... 1
9,5
8,3
top view
(1) Centre-lines of all leads are within
+0.127 mm of the nominal
position shown; in the worst
case, the spacing between any
two leads may deviate from
nominal by to.254 mm.
(2) Lead spacing tolerances apply
from seating plane to the line
indicated.
(3) Dimensions in mm.
7Z83532.1
SOT 102
June 1994
4-6
Philips Semiconductors Video Products
Package outlines
16-PIN PLASTIC SO (SMALL OUTLINE) DUAL IN-LINE (OIT) PACKAGE
S0T109A
_ - - - - - - - 1 0 , 0 _ __
4
80
9,8
.- r
~',~ - - - . ,
14
',°
1,25 _ _ 4 38
0,85
1
6°
0,7~rr--------------------------------~~·~t
0,6
1,45 175
1,;5 1:35
t
0,7 max
.0,49/1
036 '
~
-==----1
I 4+1
I
--[Q2]--
0,25
®I
8°
2°
., ~
~I
+
'--'-::0:-::,2:-::-5-----1
0:;--+ 0,10
0,19
62
-----5:8
"171)9785
top view
Dimensions in mm
SOT 109A
June 1994
$-
Positional accu racy.
@
Maximum Material Condition.
7Z739785
4-7
Philips Semiconductors Video Products
Package outlines
SOT117-1
PLASTIC DUAL IN-LINE PACKAGE; 28 LEADS (600 MIL) WITH INTERNAL HEAT SPREADER
2!
'"
C.
36.0
35.0
Ol
<:
~
5l
l
14.1
Dimensions in mm.
SOT117-1
June 1994
4-8
Philips Semiconductors Video Products
Package outlines
SOT129
40-PIN PLASTIC DUAL IN-LINE (NIP) PACKAGE
!
rj-.
~
),'50
---1
_.
.
-
.
,
~
L__ ___
Jb
ma,
.
.
. _.'
-
-.
-.~ . . .
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l",
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'--=±~~~'
t 0,76 111
'ma'_J,,:~)_
.
top vi!'w
I~
-~
11,11)
15,90
(1) Centre-lines of all leads are within
±O.127 mm of the nominal
position shown; in the worst
case, the spacing between any
two leads may deviate from
nominal by ±O.254 mm.
-_I I
.1 " .... ,
(2) Lead spacing tolerances apply
from seating plane to the line
indicated.
(3) Index may be horizontal as
shown, or vertical
(4) Dimensions in mm.
SOT 129
June 1994
7Z70128.5
4-9
Philips Semiconductors Video Products
Package outlines
S0T136-1.
PLASTIC SMALL OUTLINE PACKAGE; 28 LEADS; LARGE BODY
f
.~
FnD DO 0 00100 0 ~o;
•
17.7
18.1
,
0
0.1 S
S
~.
.j: t
I.
74
7.6
10.65
10.00
,----~1\
2.45
2.25
0.3
0; 1
I
I
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1.0
;-----} 0.32
~
T 0.23
2.65
2.35
---l + ~
1.11~
0.51-
OtoSO
MBC236-1
Dimensions in mm.
SOT136-1
June 1994
4-10
Philips Semiconductors Video Products
Package outlines
S0T137-1
PLASTIC SMALL OUTLINE PACKAGE; 24 LEADS; LARGE BODY
1 4 - - - - 7.6 _ _ _~
7.4
I
I
/
'-~/1
2.45
2.25
t
1.0
0.3
~
2.65
2.35
~
~
0.32
'0.23
,,[9=7
0.5
•
0 to 8°
MBC235-1
Dimensions in mm.
June 1994
4-11
Philips Semiconductors Video Products
Package outlines
S0T146EF4
20-LEAD DUAL IN-LINE; PLASTIC
•__- - - - - - - - 26.92 _________ •
26.54
3.60
3.2
4.2
max
max
I
0.51
3.05
min
~~J 1~~lo.254@1
..../ -I~ 0.38
II
~"
max
II
-[g]-
_10.0_
8.3
MSA25B
11
-j
6.40
6.22
~=9FF=9~=T'-=TT==rT==Fr=9FF=~==~:1=0~_--l
Dimensions in mm
June 1994
4-12
Philips Semiconductors Video Products
Package outlines
SOT158A
40-PIN PLASTIC VSO (VERY SMALL OUTLINE) DUAL IN-LINE (orr) PACKAGE
I.
00ii
15,5max·"1
~.
i -~
1:zf
+
+
2,45 2,7
~x
- 0,42 '1'1
max
t
+
O,3:1"1:j$10,1 ®l
7Z96425
10,7621
top view
$
Positional accuracy.
@
Maximum Material Condition.
'---- 16,0 max - - - -...'
Dimensions in mm
7Z96425
SOT 15BA
June 1994
4-13
Philips Semiconductors Video Products
Package outlines
SOT162-1
PLASTIC SMALL OUTLINE PACKAGE; 16 LEADS; LARGE BODY
t4-_ _ _ _
10.5 _ _ _ _~
10.1
r-~1\
2.45
2.25
0.3
I
0; 1 I
~
1.0
~ 0.32
~, 0.23
2.65
2.35
~.
111~
... 0.5'-
•
Ot08°
MBC233-1
Dimensions in mm.
June 1994
4-14
Philips Semiconductors Video Products
Package outlines
SOT163AG7
20-LEAD MINI-PACK; PLASTIC
1-----
7.6 _ _----.;.1
7.4
I
/
2.45
2.25
1.1
1.0
0.3
O.t
):::===+=~--.
+
---1
-
Dimensions in mm
June 1994
4-15
2.65
2.35
0.32
0.23
•
1·'1--=r"i
0.5 --
0 to 8 0
+
Philips Semiconductors Video Products
Package outlines
SOT187
44-PIN PLASTIC LEADED CHIP CARRIER; POCKET VERSION (A) PACKAGE
16.00 max.
----..-j
R = 0.64
to 1.14
2.15
l
x _.
max.
c
1
Dimensions in mm
MEH282
1.07
to 1.22
max.
$
Positional accuracy.
@
Maximum Material Condition.
(1) Centre-lines of all leads
are within ±O.127 mm of the
nominal position shown;
in the worst case, the spacing
between any two leads may
may deviate from nominal
by ±O.18 mm.
June 1994
4-16
Philips Semiconductors Video Products
Package outlines
S0T188AA 68-PIN PLASTIC LEADED CHIP CARRIER; POCKET VERSION (A) PACKAGE
f
1-------- 25.27
25.02
- - - - - -.. ,
24.33
~-----24.13 - - - - - -...
[I] ~olo.'oisl
--~ ~;;--'I..H110.,8®1
(64 x)
60
)-----+-----
23.6
22.6
24.33 25.27
24.13 25.02
2.15
max
+
I
26 __ ___ 0.51 (3x)
max
1.22
1.07
0.27
max
5.08
max
j
+
3.3
max
~
t
0.51 max
Idetail A!
Dimensions in mm
June 1994
4-17
MBC652
Philips Semiconductors Video Products
Package outlines
SOT189CG 84-PIN PLASTIC LEADED CHIP CARRIER (A) PACKAGE
0.51 max
0-1
(3x)
75_l-flrt,O,8@1-"081F::;
i'T-_ _ _ _ _ _ _--"fI,;I_B4_'---,-_ _ _ _ _
t-'
g:~~ ..J----'1-t----'-~ 0.81
t max
---
I
'
I
.
--~I---'·-·
28.70
27.69
._-.
54
---03.35~ ~I
----029.41 max-====J
seating plane
-1L
0.51 min
7Z25140.1
S0T189CG. AGA
June 1994
4-18
Philips Semiconductors Video Products
Package outlines
SOT225
160-PIN PLASTIC QUAD FLAT PACK (H) PACKAGE
101
c
01
c
=.
<
a:
CD
en
lJ
&
c
~
(;
"c:
DETAIL -8"
l>
C
."
;:-r
NOTES:
I. ALL DIMENSIONS AND TOLERANCES CONFDRU TO ANSI YI4.SM-1982.
&
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N
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0>
(Q
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I
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en
en
CD
m
o
-b
Z
""'TUM
PLANE
lJ
"'U
3-i--~~/.2'&
-==r:1.B.D-'1
DATUM PLANE -H- IS LOCATED AT THE UOLD PARTING LINE AND IS
COINCIDENT WITH THE Bonou OF THE LEADS WHERE THE LEAD EXITS
THE PLASTIC BODV.
•
.&. DATUMS A-B AND -0- TO BE DETERMINED AT DATUM PLANE -H-.
& TO 8E DETERMINED AT SEATING PLANE -C-.
.&. DIMENSIONS 01 AND £1 00 NOTINCLUD£ MOLD PROTRUSION.
ALLOWABLE PROTRUSION IS .2Smm/.0IO· PER SIDE. DIMENSIONS
01 AND EI DO.NOT·INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT OATUM PLANE -H-.
&
DETAILS OF PIN I IDENTiFIER ARE' OPTIONAL BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED.
r
~
~
o
o"o
~
5'
c:
-9:
7. CONTROLLING DIMENSION: MILLIMETER.
B OOES NOT INCL~DE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE :08inm/.OOY TOTAL IN EXCESS
OF THE B DIMENSION AT IAAXIMUM MATERIAL CONDITION.DAMBAR
CAlmOT BE LOCAlE!} ON THE LOWER RADIUS OR THE FOOT. UINIMUM
SPACING BETWEEN IIDJ"CENT LEADS TO BE O.IOmm.
& DIMENSION
f)/EN LEAD SIDES
a p=il~""~",
--=-j
000 LEAD SIDES
DETAIL -,,-
&-. MARKING
AREA MUST. BE FREE tROM PACKAGE SURFACE PROTRUSION.
OR INTRUSION.
10 PLATING THICKNESS ·INCLUDED. PLATING THICKNESS TO BE O.OOSmm
MINIMUM. O.020mn, .IAAXIMUM.
~,
Philips Semiconductors Video Products
Package outlines
SOT232
32-PIN PLASTIC SHRINK DUAL IN-LINE (NIP) PACKAGE
,.....- - - - - - - 29.4 max. - - - - - - - - ,
t
3.8
4.7.
max. max.
,J---'-f- ++
0.51 min.
0.53 max.
I
16
Dimensions in mm
OT232
June 1994
4-21
1$1 0.18 @I (I)
$
Positional accuracy.
@
Maximum Material Condition.
(1) Centre-lines of all leads are within
±O.09 mm of the nominal position
shown; in the worst case, the spacing
between any two leads may deviate
from nominal by ±O.18 mm.
Philips Semiconductors Video Products
Package outlines
SOT234AG 24-LEAD PLASTIC SHRINK DUAL IN-LINE PACKAGE
t--_ _ _ _ _ _ _ 22 .3 _ _ _ _ _ _ _.,
21.4
t
I "----1".....,----1
I
II
II
II
..l
max
~
11.7781
(11x)
max
j~-ELm.. ~.i,
LI10.161---.J
12.2
10.5
Dimensions in mm.
SOT234AG
June 1994
4-22
Philips Semiconductors Video Products
Package outlines
SOT247-1
52-PIN SHRINK DUAL IN-LINE PACKAGEjPLASTIC
I
III
47.02-47.92
0
~
0III
III
I
1
JIIIIIIIIIIIIII 1111111111111 1111111111 11111111111 11111111111 I
:
~WWW~~WH~nn
,~~~n
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\
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I
I
!
t-f-J
1.73 max.
~
(25xl
0.53 max.
e
1.10.18 u
-
0.32max.
~
15,90-17.15
...
_ _ _ _ _ _ _ _ _ _ _. _ _ _ _ _ _ _ _ _ _ _ _
'i
I
I"-
~
26
June 1994
1524 -1580
U'i
.:
NCO
rrif'i
X
a X
.~ e ea
0
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0
...;
i
c
a
0
4-23
,
I
Philips Semiconductors Video Products
Package outlines
SOT261-2
PLASTIC LEADED CHIP CARRIER, 28 LEADS
R. 1. 14
0.64
26
/
/28
I
\
1
0'-/"-4
45o~
t
I
18
I
-+-I
I
r
10.92
9.91
12
•
L
1.22
1.07
MBC654
Dimensions in mm.
June 1994
4-24
Philips Semiconductors Video Products
Package outlines
PLASTIC SMALL OUTLINE PACKAGE; 32 LEADS; LARGE BODY
SOT287-1
I~
~
. "I
~:
UIu] uuUuDiu ~ uuul
00.1 S
I
I
I
pin 1
index
---------L----------
MSA235-2
Dimensions in mm.
June 1994
4-25
Philips Semiconductors Video Products
Package outlines
SOT307-2
44-PIN PLASTIC QUAD FLAT PACK (8) PACKAGE
1 - - - - - - - :~:~-------I
,I
-----+-----
Dimensions in mm.
SOT307·2
June 1994
4-26
Philips Semiconductors Video Products
Package outlines
SOT313-2
PLASTIC THIN QUAD FLAT PACKAGE; 48 LEADS; 7
x 7 x 1.4 mm
::~
~I
48
~~~~~~~--~----~
1
I
I
-----:-r---7.1
6.9
I
12
~
_ _ _ _ 7.1 _ _ _ _ _+--1
6.9
f
1.45
1.35
l
MSA395
Dimensions in mm.
June 1994
4-27
9.3
8.7
Philips Semiconductors Video Products
Package outlines
SOT317
100-PIN PLASTIC QUAD FLAT PACK (8) PACKAGE
I
i
i
t ......
N
~
l-
I
I-
N
~
I
0(0 - SO'O:
!
7ii
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d
- ,-
lJ1
f-
N
~
I
.....
-i
.....
~
I
Dimensions in mm.
50T317
June 1994
4-28
I
Philips Semiconductors Video Products
Package outlines
SOT318
80-PIN PLASTIC QUAD FLAT PACK (8) PACKAGE
13.9 - 14.1
IJ)
C>
.-=
i
i
i
---------+--------Ph 1 Index i
4
I
!
01
0.3 - 0.45 (48x)
June 1994
4-29
Philips Semiconductors Video Products
Package outlines
SOT340-1
PLASTIC SHRINK SMALL OUTLINE PACKAGe; 24 LEADS; MEDIUM BODY
1 4 - - - 5.4 - - - * 1
5.2
24
2.0
1.7
~---------r~~=:~4
L
pin 1
index
OtoSO
MSA321-1
Dimensions in mm.
June 1994
4-30
j
Philips Semiconductors Video Products
Package outlines
120-PIN PLASTIC QUAD FLAT PACK (8) PACKAGE
SOT349
flO-o'o
-~
r--
·0
Sg'£ - s,'£
sn - sn
'--
,.....
1
~
11"1
0\
0
.---
I
11"1
-0
~
0
---
L"'0 - SO·O
lS £ - lL £
<~--------------------------------~
sro
I
I
I
I
I
to
N
I
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I
------~------I
I
I~-==~~
I
d
I
I
I
I
June 1994
4-31
Desktop Video Products
Section 5
Sales Offices, Rep\resentatives
& Distributors
Philips Semiconductors
North American Sales Offices, Representatives
and Distributors
PHILIPS
SEMICONDUCTORS
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, CA 94088-3409
ALABAMA
Huntsville
Philips Semiconductors
Phone: (205) 464-0111
(205) 464-9101
Elcom, Inc.
Phone: (205) 830-4001
ARIZONA
Scottsdale
Thom Luke Sales, Inc.
Phone: (602) 451-5400
Tempe
Philips Semiconductors
Phone: (602) 820-2225
CALIFORNIA
Calabasas
Philips Semiconductors
Phone: (818) 880-6304
Irvine
Philips Semiconductors
Phone: (714) 453-0770
Loomis
B.A.E. Sales, Inc.
Phone: (916) 652-6777
San Diego
Philips Semiconductors
Phone: (619) 560-0242
San Jose
B.A.E. Sales, Inc.
Phone: (408) 452-8133
Sunnyvale
Philips Semiconductors
Phone: (408) 991-3737
COLORADO
En~lewood
hilips Semiconductors
Phone: (303) 792-9011
Thom Luke Sales, Inc.
Phone: (303) 649-9717
CONNECTICUT
Wallingford
JEBCO
Phone: (203) 265-1318
FLORIDA
Oviedo
Conley and Assoc., Inc.
Phone: (407) 365-3283
Kokomo
Philips Semiconductors
Phone: (317) 459-5355
Columbus
S-J Associates, Inc.
Phone: (614) 885-6700
KENTUCKY
Lexington
Mohrfield Marketing, Inc.
Phone: (606) 223-5243
Kettering
S-J Associates, Inc.
Phone: (513) 298-7322
MARYLAND
Columbia
Third Wave Solutions, Inc.
Phone: (410) 290-5990
MASSACHUSETTS
Chelmsford
JEBCO
Phone: (508) 256-5800
Westford
Philips Semiconductors
Phone: (508) 692-6211
MICHIGAN
Monroe
S-J Associates
Phone: (313) 242-0450
Novi
Philips Semiconductors
Phone: (313) 347-1700
MINNESOTA
Bloomington
High Technology Sales
Phone: (612) 844-9933
MISSOURI
Bridgeton
Centech, Inc.
Phone: (314) 291-4230
Raytown
Centech, Inc.
Phone: (816) 358-8100
NEW JERSEY
Toms River
Philips Semiconductors
Phone: (908) 505-1200
NEW YORK
Ithaca
Bob Dean, Inc.
Phone: (607) 257-1111
Rockville Centre
S-J Associates
Phone: (516) 536-4242
Wappingers Falls
Philips Semiconductors
Phone: (914) 297-4074
Parma
S-J Associates, Inc.
Phone: (216) 888-7004
Toledo
S-J Associates, Inc.
Phone: (313) 242-0450
West Carrollton
S-J Associates, Inc.
Phone: (513) 438-1700
OREGON
Beaverton
Philips Semiconductors
Phone: (503) 627-0110
Western Technical Sales
Phone: (503) 644-8860
PENNSYLVANIA
Erie
S-J Associates, Inc.
Phone: (216) 888-7004
Hatboro
Delta Technical Sales, Inc.
Phone: (215) 957-0600
Pittsburgh
S-J Associates, Inc.
Phone: (216) 888-7004
Plymouth Meeting
Philips Semiconductors
Phone: (215) 825-4404
SOUTH CAROLINA
Greenville
Elcom, Inc.
Phone: (803) 370-9119
TENNESSEE
Dandridge
Philips Semiconductors
Phone: (615) 397-5053
TEXAS
Austin
Philips Semiconductors
Phone: (512) 339-9945
Bob Dean, Inc.
Phone: (914) 297-6406
Austin
Synergistic Sales, Inc.
Phone: (512) 346-2122
Houston
SynergistiC Sales, Inc.
Phone: (713) 937-1990
ILLINOIS
Hoffman Estates
Micro-Tex, Inc.
Phone: (708) 765-3000
NORTH CAROLINA
Charlotte
Elcom, Inc.
Phone: (704) 543-1229
Greensboro
Elcom, Inc.
Phone: (919) 273-8887
Richardson
Philips Semiconductors
Phone: (214) 644-1610
Itasca
Philips Semiconductors
Phone: (708) 250-0050
Matthews
Elcom, Inc.
Phone: (704) 847-4323
Richardson
Shnergistic Sales, Inc.
Pone: (214) 644-3500
INDIANA
Indianapolis
Mohrfield Marketing, Inc.
Phone: (317) 546-6969
OHIO
Chardon
S-J Associates, Inc.
Phone: (216) 285-7771
UTAH
Salt Lake City
Electrodyne
Phone: (801) 264-8050
GEORGIA
Norcross
Elcom, Inc.
Phone: (404) 447-8200
June 1994
5-3
WASHINGTON
Bellevue
Western Technical Sales
Phone: (206) 641-3900
Spokane
Western Technical Sales
Phone: (509) 922-7600
WISCONSIN
Waukesha
Micro-Tex, Inc.
Phone: (414) 542-5352
CANADA
PHILIPS
SEMICONDUCTORS
CANADA, LTD.
Calgary, Alberta
Tech-Trek, Ltd.
Phone: (403) 241-1719
Kanata, Ontario
Philips Semiconductors
Phone: (613) 599-8720
Tech-Trek, Ltd.
Phone: (613) 599-8787
Mississauga, Ontario
Tech-Trek, Ltd.
Phone: (416) 238-0366
Richmond, B.C.
Tech-Trek, Ltd.
Phone: (604) 276-8735
Scarborough, Ontario
Philips Semiconductors!
Components, Ltd.
(416) 292-5161
Ville St. Laurent, Quebec
Tech-Trek, Ltd.
Phone: (514) 337-7540
MEXICO
Anzures Section
Philips Components
Phone: (800) 234-7381
EIPaso,TX
Philips Components
Phone: (915) 775-4020
PUERTO RICO
Caguas
Mectron Group
Phone: (809) 746-3522
DISTRIBUTORS
Contact one of our
local distributors:
Anthem Electronics
Arrow/Schweber Electronics
Future Electronics (Canada only)
Gerber Electronics
Hamilton Hallmark!
Allied Electronics
Marshall Industries
Newark Electronics
Richardson Electronics
Wyle Laboratories, EMG
07/20194
Philips Semiconductors
Appendix A
Data handbook system
DATA HANDBOOK SYSTEM
Discrete Semiconductors
Philips Semiconductors data handbooks contain all pertinent
data available at the time of publication and each is revised
and reissued regularly.
Loose data sheets are sent to subscribers to keep them
up-to-date on additions or alterations made during the
lifetime of a data handbook.
Catalogs are available for selected product ranges (some
catalogs are also on floppy discs).
Book
Title
SC01
Diodes
SC02
Power Diodes
SC03
Thyristors and Triacs
SC04
Small-signal Transistors
SC05
Low-frequency Power Transistors and Hybrid IC
Power Modules
SC06
High-voltage and Switching NPN Power
Transistors
Small-signal Field-effect Transistors
Our data handbook titles are listed here.
Integrated Circuits
Book
Title
SCO?
IC01
Semiconductors for Radio and Audio Systems
SC08a
RF Power Bipolar Transistors
IC02
Semiconductors for Television and Video Systems
SC08b
RF Power MOS Transistors
IC03
Semiconductors for Telecom Systems
SC09
RF Power Modules
IC04
CMOS HE4000B Logic Family
SC10
Surface Mounted Semiconductors
IC05
Advanced Low-power Schottky (ALS) Logic
Series
SC13
Power MOS Transistors
including TOPFETs and IGBTs
IC06
High-speed CMOS Logic Family
SC14
ICOB
100K ECL Logic Families
RF Wideband Transistors, Video Transistors
and Modules
IC10
Memories
SC15
Microwave Transistors
IC11
General-purpose/Linear ICs
SC16
Wideband Hybrid IC Modules
IC12
Display Drivers and Microcontroller Peripherals
(planned)
SC1?
Semiconductor Sensors
IC13
Programmable Logic Devices (PLD)
PC01
High-power Klystrons and Accessories
IC14
B04S-based S-bit Microcontrollers
PC06
Circulators and Isolators
IC15
FAST TTL Logic Series
IC16
ICs for Clocks and Watches
IC18
Semiconductors for In-car Electronics and
General Industrial Applications (planned)
IC17
RFlWireless Communications
IC19
Semiconductors for Datacom: LANs, UARTs,
Multi-protocol Controllers and Fibre Optics
IC20
SOC51-based 8-bit Microcontrollers
IC21
6S000-based 16-bit Microcontrollers (planned)
IC22
ICs for Multi-media Systems (planned)
IC23
QUBiC Advanced BiCMOS Bus Interface Logic
ABT, MULTIBYTE™
IC24
Low Voltage CMOS & BiCMOS Logic
February 1994
Professional Components
MORE INFORMATION FROM PHILIPS
SEMICONDUCTORS?
For more information about Philips Semiconductors data
handbooks, catalogs and subscriptions contact your nearest
Philips Semiconductors national organization, select from
the address list on the back cover of this handbook.
Product specialists are at your service and inquiries are
answered promptly.
A-1
Philips Semiconductors
Appendix A
Data handbook system
OVERVIEW OF PHILIPS COMPONENTS
DATA HANDBOOKS
MORE INFORMATION FROM PHILIPS
COMPONENTS?
Our sister product division, Philips Components, also has a
comprehensive data handbook system to support their
products. Their data handbook titles are listed here.
For more information contact your nearest Philips
Components national organizaiton shown in the following
list.
Display Components
Argentina: BUENOS AIRES, Tel. (541) 786 7633, Fax. (541) 786 9367.
Australia: NORTH RYDE, Tel. (02) 805 4455, Fax. (02) 8054466.
Book
Title
DC01
Colour Display Components
Colour TV Picture Tubes and Assemblies
Colour Monitor Tube Assemblies
DC02
Monochrome Monitor Tubes and Deflection Units
DC03
Television Tuners, Coaxial Aerial Input
Assemblies
Canada: INTEGRATED CIRCUITS: Tel. (800) 234-7381, Fax. (708) 296-8556
DISCRETE SEMICONDUCTORS: SCARBOROUGH
Tel. (0416) 292-5161 ext. 2336, Fax. (0416) 292-4477
Chile: SANTIAGO, Tel. (02) 773 816, Fax. (02) 777 6730.
DC05
Flyback Transformers, Mains Transformers and
General-purpose FXC Assemblies
Columbia: BOGOTA, Tel. (571)2174609, Fax (01) 2174549.
Denmark: COPENHAGEN, Tel. (032) 88 2636, Fax. (031) 571949.
Austria: WIEN, Tel. (01) 60 101·1236, Fax. (01) 60 101-1211.
Belgium: EINDHOVEN, The Netherlands,
Tel. (31)40783749, Fax. (31)40788399.
Brazil: SAO PAULO, Tel. (011) 829-1166, Fax (011) 829-1849.
Finland: ESPOO, Tel. (9)050261, Fax. (9)0520971.
France: SURESNES, Tel. (01 )40996161, Fax, (01)40996427.
Germany: HAMBURG, Tel. (040) 3296-0, Fax. (040) 3296 213.
Magnetic Products
MA01
Soft Ferrites
MA03
Piezoelectric Ceramics
Specialty Ferrites
MA04
Dry-reed Switches
Greece: TAVROS, Tel. (01) 4894 339/4894 911, Fax. (01) 4814 240.
Hong Kong: KWAI CHUNG, Tel. (0)4245121, Fax. (0) 4806 960.
India: BOMBAY, Tel. (022) 4938 541, Fax. (022) 4938 722.
Indonesia: JAKARTA, Tel. (021) 5201122, Fax. (021) 5205189.
Ireland: DUBLIN, Tel. (01) 640000, Fax. (01) 640 200.
Passive Components
PA01
Electrolytic Capacitors
PA02
Varistors, Thermistors and Sensors
PA03
Potentiometers and Switches
PA04
Variable Capacitors
PA05
Film Capacitors
PA06
Ceramic Capacitors
PAO?
Quartz Crystals for Special and Industrial
Applications
PA08
Fixed Resistors
PA10
Quartz Crystals for Automotive and Standard
Applications
PA11
Italy: MILANO, Tel. (02) 6752.1, Fax. (02) 6752.3350.
Japan: TOKYO, Tel. (03) 3740 5101, Fax. (03) 3740 0570.
Korea (Republic o~: SEOUL, SEOUL, Tel. (02) 794-5011, Fax. (02) 798-8022.
Malaysia: SELANGOR, Tel. (03) 757 5511, Fax. (03) 7574880.
Mexico: EL PASO, TX 79905, Tel. 9-5(800) 234-7381, Fax. (708) 296-8556
Netherlands: EINDHOVEN, Tel. (040) 78 37 49, Fax. (040)78 83 99.
New Zealand: AUKLAND, Tel. (09) 849-4160, Fax. (09) 849-7811.
Norway: OSLO, Tel. (22) 748000, Fax (22)748341.
Pakistan: KARACHI, Tel. (021) 577039, Fax. (021) 569 1832.
Philippines: MANILA, Tel. (02) 8100161, Fax. (02) 8173474.
Portugal: LlSBOA, Tel. (01) 683 121, Fax. (01) 658 013.
Singapore: SINGAPORE, Tel. (65) 350 2000, Fax. (65) 251 6500.
South Africa: JOHANNESBURG, Tel. (011) 470-5433, Fax. (011) 470-5494.
Spain: BARCELONA, Tel. (03) 301 6312, Fax. (03) 301 4243.
Sweden: STOCKHOLM, Tel. (0)8-6322000, Fax. (0)8-632 2745.
Switzerland: ZORICH, Tel. (01) 488 2211, Fax. (01) 4817730.
Taiwan: TAIPEI, Tel. (2) 388 7666, Fax. (2)3824382.
Quartz Oscillators
Professional Components
PC04
Photo Multipliers
PC05
Plumbicon Camera Tubes and Accessories
PCO?
Vidicon and Newvicon Camera Tubes and
Deflection Units
Thailand: BANGKOK, Tel. (2)399-3280 to 9, (2)398-2083, Fax. (2)398-2080.
Turkey: ISTANBUL, Tel. (0212) 2792770, Fax. (0212) 2693094.
United Kingdom: LONDON, Tel. (071) 436 4144, Fax. (071) 323 0342.
PC08
Image Intensifiers
United States: INTEGRATED CIRCUITS: SUNNYVALE, CA
Tel. (800) 234-7381, Fax. (708) 296-8556
DISCRETE SEMICONDUCTORS: RIVIERA BEACH, FL
Tel. (800) 447-3762 and (407)881-3200, Fax. (407) 881·3300
PC12
Electron Multipliers
Uruguay: MONTEVIDEO, Tel. (02) 70-4044, Fax (02) 920601.
For all other countries apply to: Philips Components.
Marketing Communications, Building BAF-l,
P.O. Box 218,5600 MD, EINDHOVEN, The Netherlands
Telex 35000 phtcnl, Fax. +31-40-724825.
February 1994
A-2
II
','II
Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 -14.b (1428) BUENOS AIRES,
Tel. (541) 7867633, Fax. (541) 786 9367
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. (02) 8054455, Fax. (02) 805 4466
Austria: Triester Str. 64, A-l101 WIEN, P.O. Box 213,
•
Tel. (01) 60101-1236, Fax. (01) 60101-1211
Pakistan: Philips Electrical Industries of Pakistan Ltd.,
Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. (021 )5874641-49, Fax. (021 )577035/5874546
Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474
Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,
Tel. (31)40783749, Fax. (31)40 788 399
Brazil: Rua do Rocio 220 - 5th Floor, Suite 51
,
CEP: 04552-903 sAo PAULO-SP, Brazil
P.O. Box 7383-(01064-970),
Tel. (011) 821-2333, Fax (011) 829-1849
, Chile: Av. Santa Maria 0760, SANTIAGO,
Tel. (02) 773 816, Fax. (02) 777 6730
Portugal: PHILIPS PORTUGUESA, SA,
Rua dr. AntOnio Loureiro Borges 5, Arquiparque - Miraflores,
Apartado 300, 2795 LlNDA-A-VELHA,
Tel. (01)14163160/4163333, Fax. (01)14163174/4163366
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. (65)350 2000, Fax. (65)251 6500
South Africa: SA PHILIPS Pty Ltd., Components Division,
195-215 Main Road, Martindale, 2092 JOHANNESBURG,
P.O. Box 7430, Johannesburg 2000,
Tel. (011 )470-5911, Fax. (011 )470-5494
, Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA,
Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549
Spain: Balmes 22, 08007 BARCELONA,
Tel. (03)301 6312, Fax. (03)301 4243
I
'I
1"
'I Canada: PHILIPS SEMICONDUCTORS/COMPONENTS:
Tel. (800) 234-7381, Fax. (708) 296-8556
I
,
I
II
I
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. (032) 88 2636, Fax. (031) 571949
Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,
Tel. (0)8-6322000, Fax. (0)8-6322745
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. (9)0 50261, Fax. (9)0 520971
Switzerland: Allmendstrasse 140, CH-8027 ZURICH,
Tel. (01)4882211, Fax. (01)481 7730
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. (01 )40996161, Fax. (01 )40996427
Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road,
Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100,
Tel. (02)3887666, Fax. (02)3824382
Germany: PHILIPS COMPONENTS UB der Philips G.m.b.H.,
P.O. Box 10 63 23, 20043 HAMBURG,
Tel. (040) 3296-0, Fax. (040) 3296 213
Greece: No. 15, 25th March Street, GR 17778 TAVROS,
Tel. (01) 4894 339/4894 911, Fax. (On 4814 240
Hong Kong: PHILIPS HONG KONG Ltd., Components Div.,
6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T.,
Tel. (852)424 5121, Fax. (852)428 6729
India: Philips INDIA Ltd., Components Dept., Shivsagar Estate, A Block,
Dr. Annie Besant Rd., Worli, BOMBAY 400 018,
Tel. (022)4938 541, Fax. (022)4938 722
Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,
P.O. Box 4252, JAKARTA 12950
Tel. (021)5201122, Fax. (021)5205189
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. (01)640000, Fax. (01 )640200
Italy: PHILIPS COMPONENTS S.r.l., Viale F. Testi, 327, 20162 MILANO,
Tel. (02)6752.3302, Fax. (02)6752.3300
Japan: Philips Bldg. 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. (03)37405028, Fax. (03) 3740 0580
I,
I
I
I
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong,
BANGKOK 10260, Thailand
Tel. (662)398-0141, Fax. (662)398-3319
Turkey: Talatpasa Cad. No.5, 80640 GULTEPE/ISTANBUL,
Tel. (0212)2792770, Fax. (0212)2693094
United Kingdom: Philips Semiconductors Limited, P.O. Box 65,
Philips House, Torrington Place, LONDON WCl E 7HD,
Tel. (071)4364144, Fax. (071)3230342
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. (800)234-7381, Fax. (708)296-8556
Uruguay: Coronel Mora 433, MONTEVIDEO,
Tel. (02)70-4044, Fax (02)920601
For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BE-p,
P.O. Box 218,5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax +31-40-724825
SCD32
©Philips Electronics NV 1994
Korea (Republic of): Philips House, 260-199Itaewon-dong,
Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022
All rights are reserved. Reproduction in whole or in part is prohibited
without the prior written consent of the copyright owner.
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,
SELANGOR, Tel. (03)7505214, Fax. (03)7574880
Mexico: Philips Components, 5900 Gateway East, Suite 200,
EL PASO, TX 79905, Tel. 9-5 (800)234-7381, Fax. (708)296-8556
Netherlands: POStbllS 90050, 5600 PB EINDHOVEN, Bldg. VB
Tel. (040)783749, Fax. (040)788399
The information presented in this document does not form part of any
quotation or contract, is believed to be accurate and reliable and may be
changed without notice. No liability will be accepted by the publisher for
any consequence of its use. Publication thereof does not convey nor imply
any license under patent- or industrial or intellectual property rights.
New Zealand 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tol. (09)849-4160, Fax. (09)849-7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. (022)748000, Fax (022)74 8341
Printed in the USA
I)
41400/32.5M/CR4/pp1400
Document order number USA:
This book was printed on recycled paper.
Date of release: June 1994
98-1900-000-04
: .. 11
1
PliilipB Semiellildaetllia
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